2016-10-06 13:21:30 +02:00
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/* ESP32 Linker Script Memory Layout
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This file describes the memory layout (memory blocks) as virtual
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memory addresses.
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esp32.common.ld contains output sections to link compiler output
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into these memory blocks.
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***
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This linker script is passed through the C preprocessor to include
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configuration options.
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Please use preprocessor features sparingly! Restrict
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to simple macros with numeric values, and/or #if/#endif blocks.
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*/
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#include "sdkconfig.h"
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2017-09-12 08:40:52 +02:00
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/* If BT is not built at all */
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#ifndef CONFIG_BT_RESERVE_DRAM
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#define CONFIG_BT_RESERVE_DRAM 0
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#endif
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2016-10-06 13:21:30 +02:00
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MEMORY
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{
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/* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
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of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
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are connected to the data port of the CPU and eg allow bytewise access. */
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/* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
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iram0_0_seg (RX) : org = 0x40080000, len = 0x20000
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2017-08-01 07:51:04 +02:00
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/* Even though the segment name is iram, it is actually mapped to flash
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*/
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iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000-0x18
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/*
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(0x18 offset above is a convenience for the app binary image generation. Flash cache has 64KB pages. The .bin file
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which is flashed to the chip has a 0x18 byte file header. Setting this offset makes it simple to meet the flash
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cache MMU's constraint that (paddr % 64KB == vaddr % 64KB).)
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*/
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2016-10-06 13:21:30 +02:00
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/* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
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Enabling Bluetooth & Trace Memory features in menuconfig will decrease
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the amount of RAM available.
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2018-01-17 23:56:58 +01:00
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Note: Length of this section *should* be 0x50000, and this extra DRAM is available
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in heap at runtime. However due to static ROM memory usage at this 176KB mark, the
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additional static memory temporarily cannot be used.
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2016-10-06 13:21:30 +02:00
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*/
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dram0_0_seg (RW) : org = 0x3FFB0000 + CONFIG_BT_RESERVE_DRAM,
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2018-01-17 23:56:58 +01:00
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len = 0x2c200 - CONFIG_BT_RESERVE_DRAM
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2016-10-06 13:21:30 +02:00
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/* Flash mapped constant data */
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2017-08-01 07:51:04 +02:00
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drom0_0_seg (R) : org = 0x3F400018, len = 0x400000-0x18
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/* (See iram0_2_seg for meaning of 0x18 offset in the above.) */
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2016-10-06 13:21:30 +02:00
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/* RTC fast memory (executable). Persists over deep sleep.
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*/
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rtc_iram_seg(RWX) : org = 0x400C0000, len = 0x2000
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/* RTC slow memory (data accessible). Persists over deep sleep.
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Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.
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*/
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rtc_slow_seg(RW) : org = 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM,
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len = 0x1000 - CONFIG_ULP_COPROC_RESERVE_MEM
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}
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/* Heap ends at top of dram0_0_seg */
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_heap_end = 0x40000000 - CONFIG_TRACEMEM_RESERVE_DRAM;
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