437 lines
13 KiB
C
437 lines
13 KiB
C
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/*
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* xtensa/cacheattrasm.h -- assembler-specific CACHEATTR register related definitions
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* that depend on CORE configuration
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*
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* This file is logically part of xtensa/coreasm.h (or perhaps xtensa/cacheasm.h),
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* but is kept separate for modularity / compilation-performance.
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*/
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/*
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* Copyright (c) 2001-2009 Tensilica Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef XTENSA_CACHEATTRASM_H
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#define XTENSA_CACHEATTRASM_H
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#include <xtensa/coreasm.h>
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/* Determine whether cache attributes are controlled using eight 512MB entries: */
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#define XCHAL_CA_8X512 (XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR \
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|| (XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY))
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/*
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* This header file defines assembler macros of the form:
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* <x>cacheattr_<func>
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* where:
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* <x> is 'i', 'd' or absent for instruction, data
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* or both caches; and
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* <func> indicates the function of the macro.
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*
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* The following functions are defined:
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*
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* icacheattr_get
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* Reads I-cache CACHEATTR into a2 (clobbers a3-a5).
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*
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* dcacheattr_get
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* Reads D-cache CACHEATTR into a2 (clobbers a3-a5).
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* (Note: for configs with a real CACHEATTR register, the
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* above two macros are identical.)
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*
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* cacheattr_set
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* Writes both I-cache and D-cache CACHEATTRs from a2 (a3-a8 clobbered).
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* Works even when changing one's own code's attributes.
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*
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* icacheattr_is_enabled label
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* Branches to \label if I-cache appears to have been enabled
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* (eg. if CACHEATTR contains a cache-enabled attribute).
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* (clobbers a2-a5,SAR)
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*
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* dcacheattr_is_enabled label
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* Branches to \label if D-cache appears to have been enabled
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* (eg. if CACHEATTR contains a cache-enabled attribute).
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* (clobbers a2-a5,SAR)
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*
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* cacheattr_is_enabled label
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* Branches to \label if either I-cache or D-cache appears to have been enabled
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* (eg. if CACHEATTR contains a cache-enabled attribute).
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* (clobbers a2-a5,SAR)
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*
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* The following macros are only defined under certain conditions:
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*
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* icacheattr_set (if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR)
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* Writes I-cache CACHEATTR from a2 (a3-a8 clobbered).
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*
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* dcacheattr_set (if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR)
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* Writes D-cache CACHEATTR from a2 (a3-a8 clobbered).
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*/
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/*************************** GENERIC -- ALL CACHES ***************************/
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/*
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* _cacheattr_get
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*
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* (Internal macro.)
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* Returns value of CACHEATTR register (or closest equivalent) in a2.
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*
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* Entry:
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* (none)
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* Exit:
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* a2 value read from CACHEATTR
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* a3-a5 clobbered (temporaries)
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*/
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.macro _cacheattr_get tlb
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#if XCHAL_HAVE_CACHEATTR
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rsr a2, CACHEATTR
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#elif XCHAL_CA_8X512
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// We have a config that "mimics" CACHEATTR using a simplified
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// "MMU" composed of a single statically-mapped way.
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// DTLB and ITLB are independent, so there's no single
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// cache attribute that can describe both. So for now
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// just return the DTLB state.
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movi a5, 0xE0000000
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movi a2, 0
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movi a3, XCHAL_SPANNING_WAY
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1: add a3, a3, a5 // next segment
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r&tlb&1 a4, a3 // get PPN+CA of segment at 0xE0000000, 0xC0000000, ..., 0
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dsync // interlock???
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slli a2, a2, 4
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extui a4, a4, 0, 4 // extract CA
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or a2, a2, a4
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bgeui a3, 16, 1b
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#else
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// This macro isn't applicable to arbitrary MMU configurations.
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// Just return zero.
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movi a2, 0
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#endif
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.endm
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.macro icacheattr_get
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_cacheattr_get itlb
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.endm
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.macro dcacheattr_get
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_cacheattr_get dtlb
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.endm
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/* Default (powerup/reset) value of CACHEATTR,
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all BYPASS mode (ie. disabled/bypassed caches): */
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#if XCHAL_HAVE_PTP_MMU
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# define XCHAL_CACHEATTR_ALL_BYPASS 0x33333333
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#else
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# define XCHAL_CACHEATTR_ALL_BYPASS 0x22222222
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#endif
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#if XCHAL_CA_8X512
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#if XCHAL_HAVE_PTP_MMU
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# define XCHAL_FCA_ENAMASK 0x0AA0 /* bitmap of fetch attributes that require enabled icache */
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# define XCHAL_LCA_ENAMASK 0x0FF0 /* bitmap of load attributes that require enabled dcache */
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# define XCHAL_SCA_ENAMASK 0x0CC0 /* bitmap of store attributes that require enabled dcache */
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#else
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# define XCHAL_FCA_ENAMASK 0x003A /* bitmap of fetch attributes that require enabled icache */
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# define XCHAL_LCA_ENAMASK 0x0033 /* bitmap of load attributes that require enabled dcache */
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# define XCHAL_SCA_ENAMASK 0x0033 /* bitmap of store attributes that require enabled dcache */
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#endif
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#define XCHAL_LSCA_ENAMASK (XCHAL_LCA_ENAMASK|XCHAL_SCA_ENAMASK) /* l/s attrs requiring enabled dcache */
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#define XCHAL_ALLCA_ENAMASK (XCHAL_FCA_ENAMASK|XCHAL_LSCA_ENAMASK) /* all attrs requiring enabled caches */
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/*
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* _cacheattr_is_enabled
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*
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* (Internal macro.)
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* Branches to \label if CACHEATTR in a2 indicates an enabled
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* cache, using mask in a3.
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*
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* Parameters:
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* label where to branch to if cache is enabled
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* Entry:
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* a2 contains CACHEATTR value used to determine whether
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* caches are enabled
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* a3 16-bit constant where each bit correspond to
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* one of the 16 possible CA values (in a CACHEATTR mask);
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* CA values that indicate the cache is enabled
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* have their corresponding bit set in this mask
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* (eg. use XCHAL_xCA_ENAMASK , above)
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* Exit:
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* a2,a4,a5 clobbered
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* SAR clobbered
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*/
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.macro _cacheattr_is_enabled label
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movi a4, 8 // loop 8 times
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.Lcaife\@:
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extui a5, a2, 0, 4 // get CA nibble
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ssr a5 // index into mask according to CA...
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srl a5, a3 // ...and get CA's mask bit in a5 bit 0
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bbsi.l a5, 0, \label // if CA indicates cache enabled, jump to label
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srli a2, a2, 4 // next nibble
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addi a4, a4, -1
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bnez a4, .Lcaife\@ // loop for each nibble
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.endm
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#else /* XCHAL_CA_8X512 */
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.macro _cacheattr_is_enabled label
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j \label // macro not applicable, assume caches always enabled
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.endm
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#endif /* XCHAL_CA_8X512 */
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/*
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* icacheattr_is_enabled
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*
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* Branches to \label if I-cache is enabled.
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*
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* Parameters:
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* label where to branch to if icache is enabled
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* Entry:
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* (none)
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* Exit:
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* a2-a5, SAR clobbered (temporaries)
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*/
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.macro icacheattr_is_enabled label
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#if XCHAL_CA_8X512
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icacheattr_get
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movi a3, XCHAL_FCA_ENAMASK
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#endif
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_cacheattr_is_enabled \label
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.endm
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/*
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* dcacheattr_is_enabled
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*
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* Branches to \label if D-cache is enabled.
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*
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* Parameters:
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* label where to branch to if dcache is enabled
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* Entry:
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* (none)
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* Exit:
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* a2-a5, SAR clobbered (temporaries)
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*/
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.macro dcacheattr_is_enabled label
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#if XCHAL_CA_8X512
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dcacheattr_get
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movi a3, XCHAL_LSCA_ENAMASK
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#endif
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_cacheattr_is_enabled \label
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.endm
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/*
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* cacheattr_is_enabled
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*
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* Branches to \label if either I-cache or D-cache is enabled.
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*
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* Parameters:
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* label where to branch to if a cache is enabled
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* Entry:
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* (none)
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* Exit:
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* a2-a5, SAR clobbered (temporaries)
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*/
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.macro cacheattr_is_enabled label
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#if XCHAL_HAVE_CACHEATTR
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rsr a2, CACHEATTR
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movi a3, XCHAL_ALLCA_ENAMASK
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#elif XCHAL_CA_8X512
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icacheattr_get
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movi a3, XCHAL_FCA_ENAMASK
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_cacheattr_is_enabled \label
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dcacheattr_get
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movi a3, XCHAL_LSCA_ENAMASK
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#endif
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_cacheattr_is_enabled \label
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.endm
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/*
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* The ISA does not have a defined way to change the
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* instruction cache attributes of the running code,
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* ie. of the memory area that encloses the current PC.
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* However, each micro-architecture (or class of
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* configurations within a micro-architecture)
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* provides a way to deal with this issue.
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*
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* Here are a few macros used to implement the relevant
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* approach taken.
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*/
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#if XCHAL_CA_8X512 && !XCHAL_HAVE_CACHEATTR
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// We have a config that "mimics" CACHEATTR using a simplified
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// "MMU" composed of a single statically-mapped way.
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/*
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* icacheattr_set
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*
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* Entry:
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* a2 cacheattr value to set
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* Exit:
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* a2 unchanged
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* a3-a8 clobbered (temporaries)
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*/
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.macro icacheattr_set
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movi a5, 0xE0000000 // mask of upper 3 bits
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movi a6, 3f // PC where ITLB is set
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movi a3, XCHAL_SPANNING_WAY // start at region 0 (0 .. 7)
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mov a7, a2 // copy a2 so it doesn't get clobbered
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and a6, a6, a5 // upper 3 bits of local PC area
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j 3f
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// Use micro-architecture specific method.
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// The following 4-instruction sequence is aligned such that
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// it all fits within a single I-cache line. Sixteen byte
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// alignment is sufficient for this (using XCHAL_ICACHE_LINESIZE
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// actually causes problems because that can be greater than
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// the alignment of the reset vector, where this macro is often
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// invoked, which would cause the linker to align the reset
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// vector code away from the reset vector!!).
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.begin no-transform
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.align 16 /*XCHAL_ICACHE_LINESIZE*/
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1: witlb a4, a3 // write wired PTE (CA, no PPN) of 512MB segment to ITLB
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isync
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.end no-transform
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nop
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nop
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sub a3, a3, a5 // next segment (add 0x20000000)
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bltui a3, 16, 4f // done?
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// Note that in the WITLB loop, we don't do any load/stores
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// (may not be an issue here, but it is important in the DTLB case).
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2: srli a7, a7, 4 // next CA
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3:
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# if XCHAL_HAVE_MIMIC_CACHEATTR
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extui a4, a7, 0, 4 // extract CA to set
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# else /* have translation, preserve it: */
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ritlb1 a8, a3 // get current PPN+CA of segment
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//dsync // interlock???
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extui a4, a7, 0, 4 // extract CA to set
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srli a8, a8, 4 // clear CA but keep PPN ...
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slli a8, a8, 4 // ...
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add a4, a4, a8 // combine new CA with PPN to preserve
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# endif
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beq a3, a6, 1b // current PC's region? if so, do it in a safe way
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witlb a4, a3 // write wired PTE (CA [+PPN]) of 512MB segment to ITLB
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sub a3, a3, a5 // next segment (add 0x20000000)
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bgeui a3, 16, 2b
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isync // make sure all ifetch changes take effect
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4:
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.endm // icacheattr_set
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/*
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* dcacheattr_set
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*
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* Entry:
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* a2 cacheattr value to set
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* Exit:
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* a2 unchanged
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* a3-a8 clobbered (temporaries)
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*/
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.macro dcacheattr_set
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movi a5, 0xE0000000 // mask of upper 3 bits
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movi a3, XCHAL_SPANNING_WAY // start at region 0 (0 .. 7)
|
||
|
|
mov a7, a2 // copy a2 so it doesn't get clobbered
|
||
|
|
// Note that in the WDTLB loop, we don't do any load/stores
|
||
|
|
2: // (including implicit l32r via movi) because it isn't safe.
|
||
|
|
# if XCHAL_HAVE_MIMIC_CACHEATTR
|
||
|
|
extui a4, a7, 0, 4 // extract CA to set
|
||
|
|
# else /* have translation, preserve it: */
|
||
|
|
rdtlb1 a8, a3 // get current PPN+CA of segment
|
||
|
|
//dsync // interlock???
|
||
|
|
extui a4, a7, 0, 4 // extract CA to set
|
||
|
|
srli a8, a8, 4 // clear CA but keep PPN ...
|
||
|
|
slli a8, a8, 4 // ...
|
||
|
|
add a4, a4, a8 // combine new CA with PPN to preserve
|
||
|
|
# endif
|
||
|
|
wdtlb a4, a3 // write wired PTE (CA [+PPN]) of 512MB segment to DTLB
|
||
|
|
sub a3, a3, a5 // next segment (add 0x20000000)
|
||
|
|
srli a7, a7, 4 // next CA
|
||
|
|
bgeui a3, 16, 2b
|
||
|
|
dsync // make sure all data path changes take effect
|
||
|
|
.endm // dcacheattr_set
|
||
|
|
|
||
|
|
#endif /* XCHAL_CA_8X512 && !XCHAL_HAVE_CACHEATTR */
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* cacheattr_set
|
||
|
|
*
|
||
|
|
* Macro that sets the current CACHEATTR safely
|
||
|
|
* (both i and d) according to the current contents of a2.
|
||
|
|
* It works even when changing the cache attributes of
|
||
|
|
* the currently running code.
|
||
|
|
*
|
||
|
|
* Entry:
|
||
|
|
* a2 cacheattr value to set
|
||
|
|
* Exit:
|
||
|
|
* a2 unchanged
|
||
|
|
* a3-a8 clobbered (temporaries)
|
||
|
|
*/
|
||
|
|
.macro cacheattr_set
|
||
|
|
|
||
|
|
#if XCHAL_HAVE_CACHEATTR
|
||
|
|
# if XCHAL_ICACHE_LINESIZE < 4
|
||
|
|
// No i-cache, so can always safely write to CACHEATTR:
|
||
|
|
wsr a2, CACHEATTR
|
||
|
|
# else
|
||
|
|
// The Athens micro-architecture, when using the old
|
||
|
|
// exception architecture option (ie. with the CACHEATTR register)
|
||
|
|
// allows changing the cache attributes of the running code
|
||
|
|
// using the following exact sequence aligned to be within
|
||
|
|
// an instruction cache line. (NOTE: using XCHAL_ICACHE_LINESIZE
|
||
|
|
// alignment actually causes problems because that can be greater
|
||
|
|
// than the alignment of the reset vector, where this macro is often
|
||
|
|
// invoked, which would cause the linker to align the reset
|
||
|
|
// vector code away from the reset vector!!).
|
||
|
|
j 1f
|
||
|
|
.begin no-transform
|
||
|
|
.align 16 /*XCHAL_ICACHE_LINESIZE*/ // align to within an I-cache line
|
||
|
|
1: wsr a2, CACHEATTR
|
||
|
|
isync
|
||
|
|
.end no-transform
|
||
|
|
nop
|
||
|
|
nop
|
||
|
|
# endif
|
||
|
|
#elif XCHAL_CA_8X512
|
||
|
|
// DTLB and ITLB are independent, but to keep semantics
|
||
|
|
// of this macro we simply write to both.
|
||
|
|
icacheattr_set
|
||
|
|
dcacheattr_set
|
||
|
|
#else
|
||
|
|
// This macro isn't applicable to arbitrary MMU configurations.
|
||
|
|
// Do nothing in this case.
|
||
|
|
#endif
|
||
|
|
.endm
|
||
|
|
|
||
|
|
|
||
|
|
#endif /*XTENSA_CACHEATTRASM_H*/
|
||
|
|
|