100 lines
2.2 KiB
C
100 lines
2.2 KiB
C
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#include "esp32-hal.h"
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#include "sdkconfig.h"
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#if CONFIG_SPIRAM_SUPPORT
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#include "esp_spiram.h"
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#include "soc/efuse_reg.h"
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#include "esp_heap_caps.h"
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static volatile bool spiramDetected = false;
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static volatile bool spiramFailed = false;
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bool psramInit(){
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if (spiramDetected) {
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return true;
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}
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#ifndef CONFIG_SPIRAM_BOOT_INIT
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if (spiramFailed) {
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return false;
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}
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uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG);
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uint32_t pkg_ver = chip_ver & 0x7;
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if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 || pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 || pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4) {
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spiramFailed = true;
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log_w("PSRAM not supported!");
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return false;
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}
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esp_spiram_init_cache();
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if (esp_spiram_init() != ESP_OK) {
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spiramFailed = true;
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log_w("PSRAM init failed!");
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pinMatrixOutDetach(16, false, false);
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pinMatrixOutDetach(17, false, false);
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return false;
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}
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if (!esp_spiram_test()) {
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spiramFailed = true;
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log_e("PSRAM test failed!");
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return false;
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}
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if (esp_spiram_add_to_heapalloc() != ESP_OK) {
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spiramFailed = true;
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log_e("PSRAM could not be added to the heap!");
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return false;
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}
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#endif
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spiramDetected = true;
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log_d("PSRAM enabled");
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return true;
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}
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bool IRAM_ATTR psramFound(){
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return spiramDetected;
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}
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void IRAM_ATTR *ps_malloc(size_t size){
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if(!spiramDetected){
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return NULL;
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}
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return heap_caps_malloc(size, MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT);
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}
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void IRAM_ATTR *ps_calloc(size_t n, size_t size){
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if(!spiramDetected){
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return NULL;
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}
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return heap_caps_calloc(n, size, MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT);
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}
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void IRAM_ATTR *ps_realloc(void *ptr, size_t size){
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if(!spiramDetected){
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return NULL;
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}
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return heap_caps_realloc(ptr, size, MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT);
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}
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#else
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bool psramInit(){
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return false;
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}
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bool IRAM_ATTR psramFound(){
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return false;
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}
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void IRAM_ATTR *ps_malloc(size_t size){
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return NULL;
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}
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void IRAM_ATTR *ps_calloc(size_t n, size_t size){
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return NULL;
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}
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void IRAM_ATTR *ps_realloc(void *ptr, size_t size){
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return NULL;
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}
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#endif
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