2021-03-11 11:11:53 +01:00
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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2016-10-06 13:21:30 +02:00
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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2021-03-11 11:11:53 +01:00
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// modified Nov 2017 by Chuck Todd <StickBreaker> to support Interrupt Driven I/O
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2016-10-06 13:21:30 +02:00
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#ifndef _ESP32_HAL_I2C_H_
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#define _ESP32_HAL_I2C_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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2016-10-11 14:11:51 +02:00
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#include <stdint.h>
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#include <stdbool.h>
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2018-06-27 09:01:06 +02:00
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#include "freertos/FreeRTOS.h"
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#include "freertos/event_groups.h"
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2016-10-11 14:11:51 +02:00
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2018-06-27 09:01:06 +02:00
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// External Wire.h equivalent error Codes
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2016-10-11 14:11:51 +02:00
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typedef enum {
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2018-06-27 09:01:06 +02:00
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I2C_ERROR_OK=0,
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2016-10-11 14:11:51 +02:00
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I2C_ERROR_DEV,
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I2C_ERROR_ACK,
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I2C_ERROR_TIMEOUT,
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2017-09-29 15:17:13 +02:00
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I2C_ERROR_BUS,
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2018-06-27 09:01:06 +02:00
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I2C_ERROR_BUSY,
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I2C_ERROR_MEMORY,
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I2C_ERROR_CONTINUE,
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I2C_ERROR_NO_BEGIN
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2016-10-11 14:11:51 +02:00
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} i2c_err_t;
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2016-10-06 13:21:30 +02:00
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2016-10-11 13:20:02 +02:00
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struct i2c_struct_t;
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typedef struct i2c_struct_t i2c_t;
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2016-10-06 13:21:30 +02:00
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2018-06-27 09:01:06 +02:00
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i2c_t * i2cInit(uint8_t i2c_num, int8_t sda, int8_t scl, uint32_t clk_speed);
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void i2cRelease(i2c_t *i2c); // free ISR, Free DQ, Power off peripheral clock. Must call i2cInit() to recover
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i2c_err_t i2cWrite(i2c_t * i2c, uint16_t address, uint8_t* buff, uint16_t size, bool sendStop, uint16_t timeOutMillis);
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i2c_err_t i2cRead(i2c_t * i2c, uint16_t address, uint8_t* buff, uint16_t size, bool sendStop, uint16_t timeOutMillis, uint32_t *readCount);
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i2c_err_t i2cFlush(i2c_t *i2c);
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2016-10-11 14:11:51 +02:00
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i2c_err_t i2cSetFrequency(i2c_t * i2c, uint32_t clk_speed);
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2016-10-06 13:21:30 +02:00
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uint32_t i2cGetFrequency(i2c_t * i2c);
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Wire ReSTART fix, with others (#1717)
* ReSTART fix, Sequencing fix
pr #1665 introduce a problem with ReSTART, when solving this problem I found an interaction between the TxFifo refill, RxFifo empty and CMD[] fill. during certain sequences a dataqueue command would be skipped, this skipping resulted in a mismatch between the contents of the TxFifo and the i2c command sequence. The problem manifested as an ACK error.
In addition to this required bug fix I propose:
* `Wire.begin()` be changed from a `void` to a `bool` this will allow the reset functionality of `Wire.begin()` to be reported. Currently `Wire.begin()` attempts to reset the i2c Peripheral, but cannot report success/failure.
* `Wire.busy()` be added. this `bool` function returns the hardware status of the bus. This status can be use in multi-master environments for application level interleaving of commands, also in single master environment, it can be used to detect a 'hung' bus. With the functional change to `Wire.begin()` this allows app level recover of a hung bus.
* `Wire.lastError()` value updated for all errors, previously when interleaving `Wire.endTransmission(false)` and `Wire.readTransmission(false)`, the 128 byte `Wire.write()` buffer was exhausted without generating and error(very exotic). I discovered this error when I created a sequence of directed reads to a EEPROM. Each directed read used 2 bytes of the 128 byte `write()` buffer, so after 64 consecutive ReSTART writes with ReSTART reads, `Wire()` had no room to record the directed address bytes. It generated just a NAK check without setting the EEPROMs internal register address. The succeeding ReSTART read succeeded at incorrect address.
* Changes to the HAL layer:
** added `i2cGetStatus()` which returns the i2c peripheral status word, used to detect bus_busy currently
** added `i2cDebug()` programmatic control of debug buffer output
** changed `i2cAddQueue()` to allow data_only queue element this will allow a i2c transaction to use multiple data pointers.
** removed direct access to DumpInts(), DumpI2c() from app, use i2cDebug() to set trigger points
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* Update esp32-hal-i2c.c
* Update Wire.cpp
* ReSTART, Sequencing
pr #1665 introduce a problem with ReSTART, when solving this problem I found an interaction between the TxFifo refill, RxFifo empty and CMD[] fill. during certain sequences a dataqueue command would be skipped, this skipping resulted in a mismatch between the contents of the TxFifo and the i2c command sequence. The problem manifested as an ACK error.
In addition to this required bug fix I propose:
* `Wire.begin()` be changed from a `void` to a `bool` this will allow the reset functionality of `Wire.begin()` to be reported. Currently `Wire.begin()` attempts to reset the i2c Peripheral, but cannot report success/failure.
* `Wire.busy()` be added. this `bool` function returns the hardware status of the bus. This status can be use in multi-master environments for application level interleaving of commands, also in single master environment, it can be used to detect a 'hung' bus. With the functional change to `Wire.begin()` this allows app level recover of a hung bus.
* `Wire.lastError()` value updated for all errors, previously when interleaving `Wire.endTransmission(false)` and `Wire.readTransmission(false)`, the 128 byte `Wire.write()` buffer was exhausted without generating and error(very exotic). I discovered this error when I created a sequence of directed reads to a EEPROM. Each directed read used 2 bytes of the 128 byte `write()` buffer, so after 64 consecutive ReSTART writes with ReSTART reads, `Wire()` had no room to record the directed address bytes. It generated just a NAK check without setting the EEPROMs internal register address. The succeeding ReSTART read succeeded at incorrect address.
* Changes to the HAL layer:
** added `i2cGetStatus()` which returns the i2c peripheral status word, used to detect bus_busy currently
** added `i2cDebug()` programmatic control of debug buffer output
** changed `i2cAddQueue()` to allow data_only queue element this will allow a i2c transaction to use multiple data pointers.
** removed direct access to DumpInts(), DumpI2c() from app, use i2cDebug() to set trigger points
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* Forgot DebugFlags Return
@andriyadi found this, total brain fade on my part.
2018-08-14 11:51:15 +02:00
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uint32_t i2cGetStatus(i2c_t * i2c); // Status register of peripheral
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2016-10-06 13:21:30 +02:00
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2018-06-27 09:01:06 +02:00
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//Functions below should be used only if well understood
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//Might be deprecated and removed in future
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2016-10-11 14:11:51 +02:00
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i2c_err_t i2cAttachSCL(i2c_t * i2c, int8_t scl);
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i2c_err_t i2cDetachSCL(i2c_t * i2c, int8_t scl);
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i2c_err_t i2cAttachSDA(i2c_t * i2c, int8_t sda);
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i2c_err_t i2cDetachSDA(i2c_t * i2c, int8_t sda);
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2016-10-06 13:21:30 +02:00
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2018-06-27 09:01:06 +02:00
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//Stickbreakers ISR Support
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i2c_err_t i2cProcQueue(i2c_t *i2c, uint32_t *readCount, uint16_t timeOutMillis);
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i2c_err_t i2cAddQueueWrite(i2c_t *i2c, uint16_t i2cDeviceAddr, uint8_t *dataPtr, uint16_t dataLen, bool SendStop, EventGroupHandle_t event);
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i2c_err_t i2cAddQueueRead(i2c_t *i2c, uint16_t i2cDeviceAddr, uint8_t *dataPtr, uint16_t dataLen, bool SendStop, EventGroupHandle_t event);
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2016-10-06 13:21:30 +02:00
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2018-06-27 09:01:06 +02:00
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//stickbreaker debug support
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Wire ReSTART fix, with others (#1717)
* ReSTART fix, Sequencing fix
pr #1665 introduce a problem with ReSTART, when solving this problem I found an interaction between the TxFifo refill, RxFifo empty and CMD[] fill. during certain sequences a dataqueue command would be skipped, this skipping resulted in a mismatch between the contents of the TxFifo and the i2c command sequence. The problem manifested as an ACK error.
In addition to this required bug fix I propose:
* `Wire.begin()` be changed from a `void` to a `bool` this will allow the reset functionality of `Wire.begin()` to be reported. Currently `Wire.begin()` attempts to reset the i2c Peripheral, but cannot report success/failure.
* `Wire.busy()` be added. this `bool` function returns the hardware status of the bus. This status can be use in multi-master environments for application level interleaving of commands, also in single master environment, it can be used to detect a 'hung' bus. With the functional change to `Wire.begin()` this allows app level recover of a hung bus.
* `Wire.lastError()` value updated for all errors, previously when interleaving `Wire.endTransmission(false)` and `Wire.readTransmission(false)`, the 128 byte `Wire.write()` buffer was exhausted without generating and error(very exotic). I discovered this error when I created a sequence of directed reads to a EEPROM. Each directed read used 2 bytes of the 128 byte `write()` buffer, so after 64 consecutive ReSTART writes with ReSTART reads, `Wire()` had no room to record the directed address bytes. It generated just a NAK check without setting the EEPROMs internal register address. The succeeding ReSTART read succeeded at incorrect address.
* Changes to the HAL layer:
** added `i2cGetStatus()` which returns the i2c peripheral status word, used to detect bus_busy currently
** added `i2cDebug()` programmatic control of debug buffer output
** changed `i2cAddQueue()` to allow data_only queue element this will allow a i2c transaction to use multiple data pointers.
** removed direct access to DumpInts(), DumpI2c() from app, use i2cDebug() to set trigger points
*
* Update esp32-hal-i2c.c
* Update Wire.cpp
* ReSTART, Sequencing
pr #1665 introduce a problem with ReSTART, when solving this problem I found an interaction between the TxFifo refill, RxFifo empty and CMD[] fill. during certain sequences a dataqueue command would be skipped, this skipping resulted in a mismatch between the contents of the TxFifo and the i2c command sequence. The problem manifested as an ACK error.
In addition to this required bug fix I propose:
* `Wire.begin()` be changed from a `void` to a `bool` this will allow the reset functionality of `Wire.begin()` to be reported. Currently `Wire.begin()` attempts to reset the i2c Peripheral, but cannot report success/failure.
* `Wire.busy()` be added. this `bool` function returns the hardware status of the bus. This status can be use in multi-master environments for application level interleaving of commands, also in single master environment, it can be used to detect a 'hung' bus. With the functional change to `Wire.begin()` this allows app level recover of a hung bus.
* `Wire.lastError()` value updated for all errors, previously when interleaving `Wire.endTransmission(false)` and `Wire.readTransmission(false)`, the 128 byte `Wire.write()` buffer was exhausted without generating and error(very exotic). I discovered this error when I created a sequence of directed reads to a EEPROM. Each directed read used 2 bytes of the 128 byte `write()` buffer, so after 64 consecutive ReSTART writes with ReSTART reads, `Wire()` had no room to record the directed address bytes. It generated just a NAK check without setting the EEPROMs internal register address. The succeeding ReSTART read succeeded at incorrect address.
* Changes to the HAL layer:
** added `i2cGetStatus()` which returns the i2c peripheral status word, used to detect bus_busy currently
** added `i2cDebug()` programmatic control of debug buffer output
** changed `i2cAddQueue()` to allow data_only queue element this will allow a i2c transaction to use multiple data pointers.
** removed direct access to DumpInts(), DumpI2c() from app, use i2cDebug() to set trigger points
*
* Forgot DebugFlags Return
@andriyadi found this, total brain fade on my part.
2018-08-14 11:51:15 +02:00
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uint32_t i2cDebug(i2c_t *, uint32_t setBits, uint32_t resetBits);
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// Debug actions have 3 currently defined locus
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// 0xXX------ : at entry of ProcQueue
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// 0x--XX---- : at exit of ProcQueue
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// 0x------XX : at entry of Flush
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//
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// bit 0 causes DumpI2c to execute
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// bit 1 causes DumpInts to execute
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// bit 2 causes DumpCmdqueue to execute
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// bit 3 causes DumpStatus to execute
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// bit 4 causes DumpFifo to execute
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2016-10-06 13:21:30 +02:00
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ESP32_HAL_I2C_H_ */
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