// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_LEDC_STRUCT_H_
#define _SOC_LEDC_STRUCT_H_
typedefvolatilestruct{
struct{
struct{
union{
struct{
uint32_ttimer_sel:2;/*There are four high speed timers the two bits are used to select one of them for high speed channel. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/
uint32_tsig_out_en:1;/*This is the output enable control bit for high speed channel*/
uint32_tidle_lv:1;/*This bit is used to control the output value when high speed channel is off.*/
uint32_tclk_en:1;/*This bit is clock gating control signal. when software configure LED_PWM internal registers it controls the register clock.*/
};
uint32_tval;
}conf0;
union{
struct{
uint32_thpoint:20;/*The output value changes to high when htimerx(x=[0 3]) selected by high speed channel has reached reg_hpoint_hsch0[19:0]*/
uint32_treserved20:12;
};
uint32_tval;
}hpoint;
union{
struct{
uint32_tduty:25;/*The register is used to control output duty. When hstimerx(x=[0 3]) chosen by high speed channel has reached reg_lpoint_hsch0 the output signal changes to low. reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4]) (1) reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
uint32_treserved25:7;
};
uint32_tval;
}duty;
union{
struct{
uint32_tduty_scale:10;/*This register controls the increase or decrease step scale for high speed channel.*/
uint32_tduty_cycle:10;/*This register is used to increase or decrease the duty every reg_duty_cycle_hsch0 cycles for high speed channel.*/
uint32_tduty_num:10;/*This register is used to control the number of increased or decreased times for high speed channel.*/
uint32_tduty_inc:1;/*This register is used to increase the duty of output signal or decrease the duty of output signal for high speed channel.*/
uint32_tduty_start:1;/*When reg_duty_num_hsch0 reg_duty_cycle_hsch0 and reg_duty_scale_hsch0 has been configured. these register won't take effect until set reg_duty_start_hsch0. this bit is automatically cleared by hardware.*/
};
uint32_tval;
}conf1;
union{
struct{
uint32_tduty_read:25;/*This register represents the current duty of the output signal for high speed channel.*/
uint32_treserved25:7;
};
uint32_tval;
}duty_rd;
}channel[8];
}channel_group[2];/*two channel groups : 0: high-speed channels; 1: low-speed channels*/
struct{
struct{
union{
struct{
uint32_tbit_num:5;/*This register controls the range of the counter in high speed timer. the counter range is [0 2**reg_hstimer0_lim] the max bit width for counter is 20.*/
uint32_tdiv_num:18;/*This register is used to configure parameter for divider in high speed timer the least significant eight bits represent the decimal part.*/
uint32_tpause:1;/*This bit is used to pause the counter in high speed timer*/
uint32_trst:1;/*This bit is used to reset high speed timer the counter will be 0 after reset.*/
uint32_ttick_sel:1;/*This bit is used to choose apb_clk or ref_tick for high speed timer. 1'b1:apb_clk 0:ref_tick*/
uint32_tlow_speed_update:1;/*This bit is only useful for low speed timer channels, reserved for high speed timers*/
uint32_treserved26:5;
};
uint32_tval;
}conf;
union{
struct{
uint32_ttimer_cnt:20;/*software can read this register to get the current counter value in high speed timer*/
uint32_treserved20:12;
};
uint32_tval;
}value;
}timer[4];
}timer_group[2];/*two channel groups : 0: high-speed channels; 1: low-speed channels*/
union{
struct{
uint32_thstimer0_ovf:1;/*The interrupt raw bit for high speed channel0 counter overflow.*/
uint32_thstimer1_ovf:1;/*The interrupt raw bit for high speed channel1 counter overflow.*/
uint32_thstimer2_ovf:1;/*The interrupt raw bit for high speed channel2 counter overflow.*/
uint32_thstimer3_ovf:1;/*The interrupt raw bit for high speed channel3 counter overflow.*/
uint32_tlstimer0_ovf:1;/*The interrupt raw bit for low speed channel0 counter overflow.*/
uint32_tlstimer1_ovf:1;/*The interrupt raw bit for low speed channel1 counter overflow.*/
uint32_tlstimer2_ovf:1;/*The interrupt raw bit for low speed channel2 counter overflow.*/
uint32_tlstimer3_ovf:1;/*The interrupt raw bit for low speed channel3 counter overflow.*/
uint32_tduty_chng_end_hsch0:1;/*The interrupt raw bit for high speed channel 0 duty change done.*/
uint32_tduty_chng_end_hsch1:1;/*The interrupt raw bit for high speed channel 1 duty change done.*/
uint32_tduty_chng_end_hsch2:1;/*The interrupt raw bit for high speed channel 2 duty change done.*/
uint32_tduty_chng_end_hsch3:1;/*The interrupt raw bit for high speed channel 3 duty change done.*/
uint32_tduty_chng_end_hsch4:1;/*The interrupt raw bit for high speed channel 4 duty change done.*/
uint32_tduty_chng_end_hsch5:1;/*The interrupt raw bit for high speed channel 5 duty change done.*/
uint32_tduty_chng_end_hsch6:1;/*The interrupt raw bit for high speed channel 6 duty change done.*/
uint32_tduty_chng_end_hsch7:1;/*The interrupt raw bit for high speed channel 7 duty change done.*/
uint32_tduty_chng_end_lsch0:1;/*The interrupt raw bit for low speed channel 0 duty change done.*/
uint32_tduty_chng_end_lsch1:1;/*The interrupt raw bit for low speed channel 1 duty change done.*/
uint32_tduty_chng_end_lsch2:1;/*The interrupt raw bit for low speed channel 2 duty change done.*/
uint32_tduty_chng_end_lsch3:1;/*The interrupt raw bit for low speed channel 3 duty change done.*/
uint32_tduty_chng_end_lsch4:1;/*The interrupt raw bit for low speed channel 4 duty change done.*/
uint32_tduty_chng_end_lsch5:1;/*The interrupt raw bit for low speed channel 5 duty change done.*/
uint32_tduty_chng_end_lsch6:1;/*The interrupt raw bit for low speed channel 6 duty change done.*/
uint32_tduty_chng_end_lsch7:1;/*The interrupt raw bit for low speed channel 7 duty change done.*/
uint32_treserved24:8;
};
uint32_tval;
}int_raw;
union{
struct{
uint32_thstimer0_ovf:1;/*The interrupt status bit for high speed channel0 counter overflow event.*/
uint32_thstimer1_ovf:1;/*The interrupt status bit for high speed channel1 counter overflow event.*/
uint32_thstimer2_ovf:1;/*The interrupt status bit for high speed channel2 counter overflow event.*/
uint32_thstimer3_ovf:1;/*The interrupt status bit for high speed channel3 counter overflow event.*/
uint32_tlstimer0_ovf:1;/*The interrupt status bit for low speed channel0 counter overflow event.*/
uint32_tlstimer1_ovf:1;/*The interrupt status bit for low speed channel1 counter overflow event.*/
uint32_tlstimer2_ovf:1;/*The interrupt status bit for low speed channel2 counter overflow event.*/
uint32_tlstimer3_ovf:1;/*The interrupt status bit for low speed channel3 counter overflow event.*/
