// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_SPI_STRUCT_H_
#define _SOC_SPI_STRUCT_H_
typedefvolatilestruct{
union{
struct{
uint32_treserved0:16;/*reserved*/
uint32_tflash_per:1;/*program erase resume bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_tflash_pes:1;/*program erase suspend bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_tusr:1;/*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_tflash_hpm:1;/*Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_tflash_res:1;/*This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_tflash_dp:1;/*Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_tflash_ce:1;/*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_tflash_be:1;/*Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_tflash_se:1;/*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_tflash_pp:1;/*Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/
uint32_tflash_wrsr:1;/*Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_tflash_rdsr:1;/*Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_tflash_rdid:1;/*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
uint32_tflash_wrdi:1;/*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
uint32_tflash_wren:1;/*Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
uint32_tflash_read:1;/*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
uint32_tcs_hold_delay_res:12;/*Delay cycles of resume Flash when resume Flash is enable by spi clock.*/
uint32_tcs_hold_delay:4;/*SPI cs signal is delayed by spi clock cycles*/
};
uint32_tval;
}ctrl1;
union{
struct{
uint32_tstatus:16;/*In the slave mode, it is the status for master to read out.*/
uint32_twb_mode:8;/*Mode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit.*/
uint32_tstatus_ext:8;/*In the slave mode,it is the status for master to read out.*/
};
uint32_tval;
}rd_status;
union{
struct{
uint32_tsetup_time:4;/*(cycles-1) of ,prepare, phase by spi clock, this bits combined with spi_cs_setup bit.*/
uint32_thold_time:4;/*delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit.*/
uint32_tck_out_low_mode:4;/*modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits.*/
uint32_tck_out_high_mode:4;/*modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits.*/
uint32_tmiso_delay_mode:2;/*MISO signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/
uint32_tmiso_delay_num:3;/*MISO signals are delayed by system clock cycles*/
uint32_tmosi_delay_mode:2;/*MOSI signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/
uint32_tmosi_delay_num:3;/*MOSI signals are delayed by system clock cycles*/
uint32_tcs_delay_mode:2;/*spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/
uint32_tcs_delay_num:4;/*spi_cs signal is delayed by system clock cycles*/
};
uint32_tval;
}ctrl2;
union{
struct{
uint32_tclkcnt_l:6;/*In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0.*/
uint32_tclkcnt_h:6;/*In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0.*/
uint32_tclkcnt_n:6;/*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)*/
uint32_tclkdiv_pre:13;/*In the master mode it is pre-divider of spi_clk.*/
uint32_tclk_equ_sysclk:1;/*In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock.*/
};
uint32_tval;
}clock;
union{
struct{
uint32_tdoutdin:1;/*Set the bit to enable full duplex communication. 1: enable 0: disable.*/
uint32_treserved1:3;/*reserved*/
uint32_tcs_hold:1;/*spi cs keep low when spi is in ,done, phase. 1: enable 0: disable.*/
uint32_tcs_setup:1;/*spi cs is enable when spi is in ,prepare, phase. 1: enable 0: disable.*/
uint32_tck_i_edge:1;/*In the slave mode the bit is same as spi_ck_out_edge in master mode. It is combined with spi_miso_delay_mode bits.*/
uint32_tck_out_edge:1;/*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode.*/
uint32_tfwrite_dual:1;/*In the write operations read-data phase apply 2 signals*/
uint32_tfwrite_quad:1;/*In the write operations read-data phase apply 4 signals*/
uint32_tfwrite_dio:1;/*In the write operations address phase and read-data phase apply 2 signals.*/
uint32_tfwrite_qio:1;/*In the write operations address phase and read-data phase apply 4 signals.*/
uint32_tsio:1;/*Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable.*/
uint32_tusr_hold_pol:1;/*It is combined with hold bits to set the polarity of spi hold line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low*/
uint32_tusr_dout_hold:1;/*spi is hold at data out state the bit combined with spi_usr_hold_pol bit.*/
uint32_tusr_din_hold:1;/*spi is hold at data in state the bit combined with spi_usr_hold_pol bit.*/
uint32_tusr_dummy_hold:1;/*spi is hold at dummy state the bit combined with spi_usr_hold_pol bit.*/
uint32_tusr_addr_hold:1;/*spi is hold at address state the bit combined with spi_usr_hold_pol bit.*/
uint32_tusr_cmd_hold:1;/*spi is hold at command state the bit combined with spi_usr_hold_pol bit.*/
uint32_tusr_prep_hold:1;/*spi is hold at prepare state the bit combined with spi_usr_hold_pol bit.*/
uint32_tusr_miso_highpart:1;/*read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.*/
uint32_tusr_mosi_highpart:1;/*write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.*/
uint32_tusr_dummy_idle:1;/*spi clock is disable in dummy phase when the bit is enable.*/
uint32_tusr_mosi:1;/*This bit enable the write-data phase of an operation.*/
uint32_tusr_miso:1;/*This bit enable the read-data phase of an operation.*/
uint32_tusr_dummy:1;/*This bit enable the dummy phase of an operation.*/
uint32_tusr_addr:1;/*This bit enable the address phase of an operation.*/
uint32_tusr_command:1;/*This bit enable the command phase of an operation.*/
};
uint32_tval;
}user;
union{
struct{
uint32_tusr_dummy_cyclelen:8;/*The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/
uint32_treserved8:18;/*reserved*/
uint32_tusr_addr_bitlen:6;/*The length in bits of address phase. The register value shall be (bit_num-1).*/
};
uint32_tval;
}user1;
union{
struct{
uint32_tusr_command_value:16;/*The value of command.*/
uint32_treserved16:12;/*reserved*/
uint32_tusr_command_bitlen:4;/*The length in bits of command phase. The register value shall be (bit_num-1)*/
};
uint32_tval;
}user2;
union{
struct{
uint32_tusr_mosi_dbitlen:24;/*The length in bits of write-data. The register value shall be (bit_num-1).*/
uint32_treserved24:8;/*reserved*/
};
uint32_tval;
}mosi_dlen;
union{
struct{
uint32_tusr_miso_dbitlen:24;/*The length in bits of read-data. The register value shall be (bit_num-1).*/
uint32_treserved24:8;/*reserved*/
};
uint32_tval;
}miso_dlen;
uint32_tslv_wr_status;/*In the slave mode this register are the status register for the master to write into. In the master mode this register are the higher 32bits in the 64 bits address condition.*/
union{
struct{
uint32_tcs0_dis:1;/*SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin*/
uint32_tcs1_dis:1;/*SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin*/
uint32_tcs2_dis:1;/*SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin*/
uint32_treserved3:2;/*reserved*/
uint32_tck_dis:1;/*1: spi clk out disable 0: spi clk out enable*/
uint32_tcs_i_mode:2;/*In the slave mode this bits used to synchronize the input spi cs signal and eliminate spi cs jitter.*/
uint32_treserved12:5;/*reserved*/
uint32_tlast_command:3;/*In the slave mode it is the value of command.*/
uint32_tlast_state:3;/*In the slave mode it is the state of spi state machine.*/
uint32_ttrans_cnt:4;/*The operations counter in both the master mode and the slave mode. 4: read-status*/
uint32_tcmd_define:1;/*1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as: 1: write-status 2: write-buffer and 3: read-buffer.*/
uint32_twr_rd_sta_en:1;/*write and read status enable in the slave mode*/
uint32_twr_rd_buf_en:1;/*write and read buffer enable in the slave mode*/
uint32_tsync_reset:1;/*Software reset enable, reset the spi clock line cs line and data lines.*/
};
uint32_tval;
}slave;
union{
struct{
uint32_trdbuf_dummy_en:1;/*In the slave mode it is the enable bit of dummy phase for read-buffer operations.*/
uint32_twrbuf_dummy_en:1;/*In the slave mode it is the enable bit of dummy phase for write-buffer operations.*/
uint32_trdsta_dummy_en:1;/*In the slave mode it is the enable bit of dummy phase for read-status operations.*/
uint32_twrsta_dummy_en:1;/*In the slave mode it is the enable bit of dummy phase for write-status operations.*/
uint32_twr_addr_bitlen:6;/*In the slave mode it is the address length in bits for write-buffer operation. The register value shall be (bit_num-1).*/
uint32_trd_addr_bitlen:6;/*In the slave mode it is the address length in bits for read-buffer operation. The register value shall be (bit_num-1).*/
uint32_treserved16:9;/*reserved*/
uint32_tstatus_readback:1;/*In the slave mode 1:read register of SPI_SLV_WR_STATUS 0: read register of SPI_RD_STATUS.*/
uint32_tstatus_fast_en:1;/*In the slave mode enable fast read status.*/
uint32_tstatus_bitlen:5;/*In the slave mode it is the length of status bit.*/
};
uint32_tval;
}slave1;
union{
struct{
uint32_trdsta_dummy_cyclelen:8;/*In the slave mode it is the length in spi_clk cycles of dummy phase for read-status operations. The register value shall be (cycle_num-1).*/
uint32_twrsta_dummy_cyclelen:8;/*In the slave mode it is the length in spi_clk cycles of dummy phase for write-status operations. The register value shall be (cycle_num-1).*/
uint32_trdbuf_dummy_cyclelen:8;/*In the slave mode it is the length in spi_clk cycles of dummy phase for read-buffer operations. The register value shall be (cycle_num-1).*/
uint32_twrbuf_dummy_cyclelen:8;/*In the slave mode it is the length in spi_clk cycles of dummy phase for write-buffer operations. The register value shall be (cycle_num-1).*/
};
uint32_tval;
}slave2;
union{
struct{
uint32_trdbuf_cmd_value:8;/*In the slave mode it is the value of read-buffer command.*/
uint32_twrbuf_cmd_value:8;/*In the slave mode it is the value of write-buffer command.*/
uint32_trdsta_cmd_value:8;/*In the slave mode it is the value of read-status command.*/
uint32_twrsta_cmd_value:8;/*In the slave mode it is the value of write-status command.*/
};
uint32_tval;
}slave3;
union{
struct{
uint32_tbit_len:24;/*In the slave mode it is the length in bits for write-buffer operations. The register value shall be (bit_num-1).*/
uint32_treserved24:8;/*reserved*/
};
uint32_tval;
}slv_wrbuf_dlen;
union{
struct{
uint32_tbit_len:24;/*In the slave mode it is the length in bits for read-buffer operations. The register value shall be (bit_num-1).*/
uint32_tusr_sram_dio:1;/*For SPI0 In the spi sram mode spi dual I/O mode enable 1: enable 0:disable*/
uint32_tusr_sram_qio:1;/*For SPI0 In the spi sram mode spi quad I/O mode enable 1: enable 0:disable*/
uint32_tusr_wr_sram_dummy:1;/*For SPI0 In the spi sram mode it is the enable bit of dummy phase for write operations.*/
uint32_tusr_rd_sram_dummy:1;/*For SPI0 In the spi sram mode it is the enable bit of dummy phase for read operations.*/
uint32_tcache_sram_usr_rcmd:1;/*For SPI0 In the spi sram mode cache read sram for user define command.*/
uint32_tsram_bytes_len:8;/*For SPI0 In the sram mode it is the byte length of spi read sram data.*/
uint32_tsram_dummy_cyclelen:8;/*For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).*/
uint32_tsram_addr_bitlen:6;/*For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).*/
uint32_tcache_sram_usr_wcmd:1;/*For SPI0 In the spi sram mode cache write sram for user define command*/
uint32_treserved29:3;/*reserved*/
};
uint32_tval;
}cache_sctrl;
union{
struct{
uint32_tdio:1;/*For SPI0 SRAM DIO mode enable . SRAM DIO enable command will be send when the bit is set. The bit will be cleared once the operation done.*/
uint32_tqio:1;/*For SPI0 SRAM QIO mode enable . SRAM QIO enable command will be send when the bit is set. The bit will be cleared once the operation done.*/
uint32_treserved2:2;/*For SPI0 SRAM write enable . SRAM write operation will be triggered when the bit is set. The bit will be cleared once the operation done.*/
uint32_trst_io:1;/*For SPI0 SRAM IO mode reset enable. SRAM IO mode reset operation will be triggered when the bit is set. The bit will be cleared once the operation done*/
uint32_treserved5:27;/*reserved*/
};
uint32_tval;
}sram_cmd;
union{
struct{
uint32_tusr_rd_cmd_value:16;/*For SPI0 When cache mode is enable it is the read command value of command phase for SRAM.*/
uint32_treserved16:12;/*reserved*/
uint32_tusr_rd_cmd_bitlen:4;/*For SPI0 When cache mode is enable it is the length in bits of command phase for SRAM. The register value shall be (bit_num-1).*/
};
uint32_tval;
}sram_drd_cmd;
union{
struct{
uint32_tusr_wr_cmd_value:16;/*For SPI0 When cache mode is enable it is the write command value of command phase for SRAM.*/
uint32_treserved16:12;/*reserved*/
uint32_tusr_wr_cmd_bitlen:4;/*For SPI0 When cache mode is enable it is the in bits of command phase for SRAM. The register value shall be (bit_num-1).*/
};
uint32_tval;
}sram_dwr_cmd;
union{
struct{
uint32_tslv_rdata_bit:24;/*In the slave mode it is the bit length of read data. The value is the length - 1.*/
uint32_treserved24:8;/*reserved*/
};
uint32_tval;
}slv_rd_bit;
uint32_treserved_68;
uint32_treserved_6c;
uint32_treserved_70;
uint32_treserved_74;
uint32_treserved_78;
uint32_treserved_7c;
uint32_tdata_buf[16];/*data buffer*/
uint32_ttx_crc;/*For SPI1 the value of crc32 for 256 bits data.*/
uint32_treserved_c4;
uint32_treserved_c8;
uint32_treserved_cc;
uint32_treserved_d0;
uint32_treserved_d4;
uint32_treserved_d8;
uint32_treserved_dc;
uint32_treserved_e0;
uint32_treserved_e4;
uint32_treserved_e8;
uint32_treserved_ec;
union{
struct{
uint32_tt_pp_time:12;/*page program delay time by system clock.*/
uint32_treserved12:4;/*reserved*/
uint32_tt_pp_shift:4;/*page program delay time shift .*/
uint32_treserved20:11;/*reserved*/
uint32_tt_pp_ena:1;/*page program delay enable.*/
};
uint32_tval;
}ext0;
union{
struct{
uint32_tt_erase_time:12;/*erase flash delay time by system clock.*/
uint32_treserved12:4;/*reserved*/
uint32_tt_erase_shift:4;/*erase flash delay time shift.*/
uint32_tst:3;/*The status of spi state machine .*/
uint32_treserved3:29;/*reserved*/
};
uint32_tval;
}ext2;
union{
struct{
uint32_tint_hold_ena:2;/*This register is for two SPI masters to share the same cs clock and data signals. The bits of one SPI are set if the other SPI is busy the SPI will be hold. 1(3): hold at ,idle, phase 2: hold at ,prepare, phase.*/
uint32_treserved2:30;/*reserved*/
};
uint32_tval;
}ext3;
union{
struct{
uint32_treserved0:2;/*reserved*/
uint32_tin_rst:1;/*The bit is used to reset in dma fsm and in data fifo pointer.*/
uint32_tout_rst:1;/*The bit is used to reset out dma fsm and out data fifo pointer.*/
