Fix io16 io17 and PSRAM support (#1564)

* Add PSRAM init and malloc funtions

* Rebuild IDF libs

CMakeLists.txt

@@ -9,6 +9,7 @@ set(CORE_SRCS
   cores/esp32/esp32-hal-ledc.c
   cores/esp32/esp32-hal-matrix.c
   cores/esp32/esp32-hal-misc.c
+  cores/esp32/esp32-hal-psram.c
   cores/esp32/esp32-hal-sigmadelta.c
   cores/esp32/esp32-hal-spi.c
   cores/esp32/esp32-hal-time.c

cores/esp32/esp32-hal-misc.c

@@ -84,6 +84,9 @@ bool btInUse(){ return false; }
 
 void initArduino()
 {
+#if CONFIG_SPIRAM_SUPPORT
+    psramInit();
+#endif
     esp_log_level_set("*", CONFIG_LOG_DEFAULT_LEVEL);
     esp_err_t err = nvs_flash_init();
     if(err == ESP_ERR_NVS_NO_FREE_PAGES){

cores/esp32/esp32-hal-psram.c

@@ -0,0 +1,99 @@
+
+#include "esp32-hal.h"
+#include "sdkconfig.h"
+
+#if CONFIG_SPIRAM_SUPPORT
+#include "esp_spiram.h"
+#include "soc/efuse_reg.h"
+#include "esp_heap_caps.h"
+
+static volatile bool spiramDetected = false;
+static volatile bool spiramFailed = false;
+
+bool psramInit(){
+    if (spiramDetected) {
+        return true;
+    }
+#ifndef CONFIG_SPIRAM_BOOT_INIT
+    if (spiramFailed) {
+        return false;
+    }
+    uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG);
+    uint32_t pkg_ver = chip_ver & 0x7;
+    if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 || pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 || pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4) {
+        spiramFailed = true;
+        log_w("PSRAM not supported!");
+        return false;
+    }
+    esp_spiram_init_cache();
+    if (esp_spiram_init() != ESP_OK) {
+        spiramFailed = true;
+        log_w("PSRAM init failed!");
+        pinMatrixOutDetach(16, false, false);
+        pinMatrixOutDetach(17, false, false);
+        return false;
+    }
+    if (!esp_spiram_test()) {
+        spiramFailed = true;
+        log_e("PSRAM test failed!");
+        return false;
+    }
+    if (esp_spiram_add_to_heapalloc() != ESP_OK) {
+        spiramFailed = true;
+        log_e("PSRAM could not be added to the heap!");
+        return false;
+    }
+#endif
+    spiramDetected = true;
+    log_d("PSRAM enabled");
+    return true;
+}
+
+bool IRAM_ATTR psramFound(){
+    return spiramDetected;
+}
+
+void IRAM_ATTR *ps_malloc(size_t size){
+    if(!spiramDetected){
+        return NULL;
+    }
+    return heap_caps_malloc(size, MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT);
+}
+
+void IRAM_ATTR *ps_calloc(size_t n, size_t size){
+    if(!spiramDetected){
+        return NULL;
+    }
+    return heap_caps_calloc(n, size, MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT);
+}
+
+void IRAM_ATTR *ps_realloc(void *ptr, size_t size){
+    if(!spiramDetected){
+        return NULL;
+    }
+    return heap_caps_realloc(ptr, size, MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT);
+}
+
+#else
+
+bool psramInit(){
+    return false;
+}
+
+bool IRAM_ATTR psramFound(){
+    return false;
+}
+
+void IRAM_ATTR *ps_malloc(size_t size){
+    return NULL;
+}
+
+void IRAM_ATTR *ps_calloc(size_t n, size_t size){
+    return NULL;
+}
+
+void IRAM_ATTR *ps_realloc(void *ptr, size_t size){
+    return NULL;
+}
+
+#endif

cores/esp32/esp32-hal-psram.h

@@ -0,0 +1,25 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _ESP32_HAL_PSRAM_H_
+#define _ESP32_HAL_PSRAM_H_
+
+bool psramInit();
+bool psramFound();
+
+void *ps_malloc(size_t size);
+void *ps_calloc(size_t n, size_t size);
+void *ps_realloc(void *ptr, size_t size);
+
+#endif /* _ESP32_HAL_PSRAM_H_ */

cores/esp32/esp32-hal.h

@@ -59,6 +59,7 @@ void yield(void);
 #include "esp32-hal-sigmadelta.h"
 #include "esp32-hal-timer.h"
 #include "esp32-hal-bt.h"
+#include "esp32-hal-psram.h"
 #include "esp_system.h"
 
 //returns chip temperature in Celsius

tools/sdk/include/config/sdkconfig.h

@@ -190,7 +190,6 @@
 #define CONFIG_LOG_BOOTLOADER_LEVEL 0
 #define CONFIG_MBEDTLS_TLS_ENABLED 1
 #define CONFIG_LWIP_MAX_RAW_PCBS 16
-#define CONFIG_SPIRAM_IGNORE_NOTFOUND 1
 #define CONFIG_SMP_ENABLE 1
 #define CONFIG_SPIRAM_SIZE 4194304
 #define CONFIG_MBEDTLS_SSL_SESSION_TICKETS 1
@@ -228,6 +227,7 @@
 #define CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED 1
 #define CONFIG_MONITOR_BAUD 115200
 #define CONFIG_ESP32_DEBUG_STUBS_ENABLE 1
+#define CONFIG_WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST 1
 #define CONFIG_FREERTOS_CORETIMER_0 1
 #define CONFIG_PARTITION_TABLE_CUSTOM_FILENAME "partitions.csv"
 #define CONFIG_MBEDTLS_HAVE_TIME 1
@@ -238,12 +238,10 @@
 #define CONFIG_ADC_CAL_EFUSE_VREF_ENABLE 1
 #define CONFIG_MBEDTLS_TLS_SERVER 1
 #define CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT 1
-#define CONFIG_SPIRAM_BOOT_INIT 1
 #define CONFIG_FREERTOS_ISR_STACKSIZE 1536
 #define CONFIG_CLASSIC_BT_ENABLED 1
 #define CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK 1
 #define CONFIG_OPENSSL_ASSERT_DO_NOTHING 1
-#define CONFIG_SPIRAM_MEMTEST 1
 #define CONFIG_WL_SECTOR_SIZE_4096 1
 #define CONFIG_OPTIMIZATION_LEVEL_DEBUG 1
 #define CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED 1

tools/sdk/sdkconfig

@@ -217,17 +217,15 @@ CONFIG_SPIRAM_SUPPORT=y
 #
 # SPI RAM config
 #
-CONFIG_SPIRAM_BOOT_INIT=y
-CONFIG_SPIRAM_IGNORE_NOTFOUND=y
+CONFIG_SPIRAM_BOOT_INIT=
 CONFIG_SPIRAM_USE_MEMMAP=
 CONFIG_SPIRAM_USE_CAPS_ALLOC=y
 CONFIG_SPIRAM_USE_MALLOC=
 CONFIG_SPIRAM_TYPE_ESPPSRAM32=y
 CONFIG_SPIRAM_SIZE=4194304
 CONFIG_SPIRAM_SPEED_40M=y
-CONFIG_SPIRAM_MEMTEST=y
 CONFIG_SPIRAM_CACHE_WORKAROUND=y
-CONFIG_WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST=
+CONFIG_WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST=y
 CONFIG_MEMMAP_TRACEMEM=
 CONFIG_MEMMAP_TRACEMEM_TWOBANKS=
 CONFIG_ESP32_TRAX=