diff --git a/tools/sdk/bin/bootloader.bin b/tools/sdk/bin/bootloader.bin
index 39de6fce..e5275599 100644
Binary files a/tools/sdk/bin/bootloader.bin and b/tools/sdk/bin/bootloader.bin differ
diff --git a/tools/sdk/include/config/sdkconfig.h b/tools/sdk/include/config/sdkconfig.h
index 32da0608..aba1f522 100644
--- a/tools/sdk/include/config/sdkconfig.h
+++ b/tools/sdk/include/config/sdkconfig.h
@@ -9,7 +9,6 @@
 #define CONFIG_PHY_ENABLED 1
 #define CONFIG_TRACEMEM_RESERVE_DRAM 0x0
 #define CONFIG_FREERTOS_MAX_TASK_NAME_LEN 16
-#define CONFIG_FOUR_MAC_ADDRESS_FROM_EFUSE 1
 #define CONFIG_SW_COEXIST_ENABLE 1
 #define CONFIG_ESPTOOLPY_FLASHSIZE_4MB 1
 #define CONFIG_ESPTOOLPY_FLASHFREQ "80m"
@@ -24,7 +23,6 @@
 #define CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS 1
 #define CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM 10
 #define CONFIG_BT_RESERVE_DRAM 0x10000
-#define CONFIG_LOG_BOOTLOADER_LEVEL_ERROR 1
 #define CONFIG_CONSOLE_UART_BAUDRATE 115200
 #define CONFIG_LWIP_MAX_SOCKETS 10
 #define CONFIG_EMAC_TASK_PRIORITY 20
@@ -40,8 +38,10 @@
 #define CONFIG_CONSOLE_UART_NUM 0
 #define CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC 1
 #define CONFIG_LWIP_THREAD_LOCAL_STORAGE_INDEX 0
+#define CONFIG_FOUR_UNIVERSAL_MAC_ADDRESS 1
 #define CONFIG_CONSOLE_UART_DEFAULT 1
 #define CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN 16384
+#define CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS 4
 #define CONFIG_ESPTOOLPY_FLASHSIZE_DETECT 1
 #define CONFIG_AUTOSTART_ARDUINO 1
 #define CONFIG_LOG_DEFAULT_LEVEL_ERROR 1
@@ -73,10 +73,8 @@
 #define CONFIG_PARTITION_TABLE_FILENAME "partitions_singleapp.csv"
 #define CONFIG_LWIP_DHCP_MAX_NTP_SERVERS 1
 #define CONFIG_PARTITION_TABLE_SINGLE_APP 1
-#define CONFIG_NUMBER_OF_MAC_ADDRESS_GENERATED_FROM_EFUSE 4
 #define CONFIG_WIFI_ENABLED 1
 #define CONFIG_FLASHMODE_QIO 1
-#define CONFIG_BASE_MAC_STORED_DEFAULT_EFUSE 1
 #define CONFIG_ESPTOOLPY_FLASHFREQ_80M 1
 #define CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE 2048
 #define CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY 2000
@@ -90,11 +88,12 @@
 #define CONFIG_FREERTOS_ASSERT_FAIL_ABORT 1
 #define CONFIG_ESP32_XTAL_FREQ 0
 #define CONFIG_MONITOR_BAUD_115200B 1
-#define CONFIG_LOG_BOOTLOADER_LEVEL 1
+#define CONFIG_LOG_BOOTLOADER_LEVEL 0
 #define CONFIG_SMP_ENABLE 1
 #define CONFIG_ESPTOOLPY_BEFORE_RESET 1
 #define CONFIG_ESPTOOLPY_BAUD_OTHER_VAL 115200
 #define CONFIG_ENABLE_ARDUINO_DEPENDS 1
+#define CONFIG_LOG_BOOTLOADER_LEVEL_NONE 1
 #define CONFIG_ESP32_DEFAULT_CPU_FREQ_240 1
 #define CONFIG_ESP32_XTAL_FREQ_AUTO 1
 #define CONFIG_TCP_MAXRTX 12
diff --git a/tools/sdk/include/driver/driver/dac.h b/tools/sdk/include/driver/driver/dac.h
index ce5a90b3..07e1ff80 100644
--- a/tools/sdk/include/driver/driver/dac.h
+++ b/tools/sdk/include/driver/driver/dac.h
@@ -28,13 +28,31 @@ typedef enum {
     DAC_CHANNEL_MAX,
 } dac_channel_t;
 
+
+/**
+  * @brief  Set DAC output voltage.
+  *
+  * @note Function has been deprecated, please use dac_output_voltage instead.
+  *       This name will be removed in a future release.
+  *       The difference is that before calling dac_output_voltage, we need to initialize the dac pad by dac_output_enable
+  *
+  *
+  * @param channel DAC channel
+  * @param dac_value DAC output value
+  *
+  * @return
+  *     - ESP_OK success
+  *     - ESP_ERR_INVALID_ARG Parameter error
+  */
+esp_err_t dac_out_voltage(dac_channel_t channel, uint8_t dac_value) __attribute__ ((deprecated));
+
 /**
  * @brief Set DAC output voltage.
  *
  * DAC output is 8-bit. Maximum (255) corresponds to VDD.
  *
- * @note When this function is called, function for the DAC
- * channel's GPIO pin is reconfigured for RTC DAC function.
+ * @note Need to configure DAC pad before calling this function.
+ *       DAC channel 1 is attached to GPIO25, DAC channel 2 is attached to GPIO26
  *
  * @param channel DAC channel
  * @param dac_value DAC output value
@@ -43,8 +61,35 @@ typedef enum {
  *     - ESP_OK success
  *     - ESP_ERR_INVALID_ARG Parameter error
  */
-esp_err_t dac_out_voltage(dac_channel_t channel, uint8_t dac_value);
+esp_err_t dac_output_voltage(dac_channel_t channel, uint8_t dac_value);
 
+/**
+ * @brief DAC pad output enable
+ *
+ * @param channel DAC channel
+ * @note DAC channel 1 is attached to GPIO25, DAC channel 2 is attached to GPIO26
+ *       I2S left channel will be mapped to DAC channel 2
+ *       I2S right channel will be mapped to DAC channel 1
+ */
+esp_err_t dac_output_enable(dac_channel_t channel);
+
+/**
+ * @brief DAC pad output disable
+ *
+ * @param channel DAC channel
+ * @note DAC channel 1 is attached to GPIO25, DAC channel 2 is attached to GPIO26
+ */
+esp_err_t dac_output_disable(dac_channel_t channel);
+
+/**
+ * @brief Enable DAC output data from I2S
+ */
+esp_err_t dac_i2s_enable();
+
+/**
+ * @brief Disable DAC output data from I2S
+ */
+esp_err_t dac_i2s_disable();
 #ifdef __cplusplus
 }
 #endif
diff --git a/tools/sdk/include/driver/driver/i2s.h b/tools/sdk/include/driver/driver/i2s.h
index 562f0985..5777e34b 100644
--- a/tools/sdk/include/driver/driver/i2s.h
+++ b/tools/sdk/include/driver/driver/i2s.h
@@ -109,13 +109,17 @@ typedef enum {
 /**
  * @brief I2S Mode, defaut is I2S_MODE_MASTER | I2S_MODE_TX
  *
+ * @note PDM and built-in DAC functions are only supported on I2S0 for current ESP32 chip.
+ *
  */
 typedef enum {
     I2S_MODE_MASTER = 1,
     I2S_MODE_SLAVE = 2,
     I2S_MODE_TX = 4,
     I2S_MODE_RX = 8,
-    I2S_MODE_DAC_BUILT_IN = 16
+    I2S_MODE_DAC_BUILT_IN = 16,       /*!< Output I2S data to built-in DAC, no matter the data format is 16bit or 32 bit, the DAC module will only take the 8bits from MSB*/
+    //I2S_MODE_ADC_BUILT_IN = 32,     /*!< Currently not supported yet, will be added for the next version*/
+    I2S_MODE_PDM = 64,
 } i2s_mode_t;
 
 /**
@@ -144,6 +148,19 @@ typedef enum {
     I2S_EVENT_MAX,         /*!< I2S event max index*/
 } i2s_event_type_t;
 
+/**
+ * @brief I2S DAC mode for i2s_set_dac_mode.
+ *
+ * @note PDM and built-in DAC functions are only supported on I2S0 for current ESP32 chip.
+ */
+typedef enum {
+    I2S_DAC_CHANNEL_DISABLE  = 0,    /*!< Disable I2S built-in DAC signals*/
+    I2S_DAC_CHANNEL_RIGHT_EN = 1,    /*!< Enable I2S built-in DAC right channel, maps to DAC channel 1 on GPIO25*/
+    I2S_DAC_CHANNEL_LEFT_EN  = 2,    /*!< Enable I2S built-in DAC left  channel, maps to DAC channel 2 on GPIO26*/
+    I2S_DAC_CHANNEL_BOTH_EN  = 0x3,  /*!< Enable both of the I2S built-in DAC channels.*/
+    I2S_DAC_CHANNEL_MAX      = 0x4,  /*!< I2S built-in DAC mode max index*/
+} i2s_dac_mode_t;
+
 /**
  * @brief Event structure used in I2S event queue
  *
@@ -166,6 +183,7 @@ typedef struct {
     int data_in_num;    /*!< DATA in pin*/
 } i2s_pin_config_t;
 
+
 typedef intr_handle_t i2s_isr_handle_t;
 /**
  * @brief Set I2S pin number
@@ -181,12 +199,30 @@ typedef intr_handle_t i2s_isr_handle_t;
  * Inside the pin configuration structure, set I2S_PIN_NO_CHANGE for any pin where
  * the current configuration should not be changed.
  *
+ * @note if *pin is set as NULL, this function will initialize both of the built-in DAC channels by default.
+ *       if you don't want this to happen and you want to initialize only one of the DAC channels, you can call i2s_set_dac_mode instead.
+ *
  * @return
  *     - ESP_OK   Success
  *     - ESP_FAIL Parameter error
  */
 esp_err_t i2s_set_pin(i2s_port_t i2s_num, const i2s_pin_config_t *pin);
 
+/**
+ * @brief Set I2S dac mode, I2S built-in DAC is disabled by default
+ *
+ * @param dac_mode DAC mode configurations - see i2s_dac_mode_t
+ *
+ * @note Built-in DAC functions are only supported on I2S0 for current ESP32 chip.
+ *       If either of the built-in DAC channel are enabled, the other one can not
+ *       be used as RTC DAC function at the same time.
+ *
+ * @return
+ *     - ESP_OK  Success
+ *     - ESP_ERR_INVALID_ARG  Parameter error
+ */
+esp_err_t i2s_set_dac_mode(i2s_dac_mode_t dac_mode);
+
 /**
  * @brief Install and start I2S driver.
  *
diff --git a/tools/sdk/include/driver/driver/mcpwm.h b/tools/sdk/include/driver/driver/mcpwm.h
new file mode 100644
index 00000000..2a4433fc
--- /dev/null
+++ b/tools/sdk/include/driver/driver/mcpwm.h
@@ -0,0 +1,709 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _DRIVER_MCPWM_H_
+#define _DRIVER_MCPWM_H_
+
+#include "esp_err.h"
+#include "soc/soc.h"
+#include "driver/gpio.h"
+#include "driver/periph_ctrl.h"
+#include "esp_intr.h"
+#include "esp_intr_alloc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief IO signals for MCPWM
+ *        6 MCPWM output pins that generate PWM signals
+ *        3 MCPWM fault input pins to detect faults like overcurrent, overvoltage, etc
+ *        3 MCPWM sync input pins to synchronize MCPWM outputs signals
+ *        3 MCPWM capture input pin to capture hall sell signal to measure time
+ */
+typedef enum {
+    MCPWM0A = 0,        /*!<PWM0A output pin*/
+    MCPWM0B,            /*!<PWM0B output pin*/
+    MCPWM1A,            /*!<PWM1A output pin*/
+    MCPWM1B,            /*!<PWM1B output pin*/
+    MCPWM2A,            /*!<PWM2A output pin*/
+    MCPWM2B,            /*!<PWM2B output pin*/
+    MCPWM_SYNC_0,       /*!<SYNC0  input pin*/
+    MCPWM_SYNC_1,       /*!<SYNC1  input pin*/
+    MCPWM_SYNC_2,       /*!<SYNC2  input pin*/
+    MCPWM_FAULT_0,      /*!<FAULT0 input pin*/
+    MCPWM_FAULT_1,      /*!<FAULT1 input pin*/
+    MCPWM_FAULT_2,      /*!<FAULT2 input pin*/
+    MCPWM_CAP_0 = 84,   /*!<CAP0   input pin*/
+    MCPWM_CAP_1,        /*!<CAP1   input pin*/
+    MCPWM_CAP_2,        /*!<CAP2   input pin*/
+} mcpwm_io_signals_t;
+
+/**
+ * @brief MCPWM pin number for
+ *
+ */
+typedef struct {
+    int mcpwm0a_out_num;       /*!<MCPWM0A out pin*/
+    int mcpwm0b_out_num;       /*!<MCPWM0A out pin*/
+    int mcpwm1a_out_num;       /*!<MCPWM0A out pin*/
+    int mcpwm1b_out_num;       /*!<MCPWM0A out pin*/
+    int mcpwm2a_out_num;       /*!<MCPWM0A out pin*/
+    int mcpwm2b_out_num;       /*!<MCPWM0A out pin*/
+    int mcpwm_sync0_in_num;    /*!<SYNC0  in pin*/
+    int mcpwm_sync1_in_num;    /*!<SYNC1  in pin*/
+    int mcpwm_sync2_in_num;    /*!<SYNC2  in pin*/
+    int mcpwm_fault0_in_num;   /*!<FAULT0 in pin*/
+    int mcpwm_fault1_in_num;   /*!<FAULT1 in pin*/
+    int mcpwm_fault2_in_num;   /*!<FAULT2 in pin*/
+    int mcpwm_cap0_in_num;     /*!<CAP0   in pin*/
+    int mcpwm_cap1_in_num;     /*!<CAP1   in pin*/
+    int mcpwm_cap2_in_num;     /*!<CAP2   in pin*/
+} mcpwm_pin_config_t;
+
+/**
+ * @brief Select MCPWM unit
+ */
+typedef enum {
+    MCPWM_UNIT_0 = 0,  /*!<MCPWM unit0 selected*/
+    MCPWM_UNIT_1,      /*!<MCPWM unit1 selected*/
+    MCPWM_UNIT_MAX,    /*!<Num of MCPWM units on ESP32*/
+} mcpwm_unit_t;
+
+/**
+ * @brief Select MCPWM timer
+ */
+typedef enum {
+    MCPWM_TIMER_0 = 0,  /*!<Select MCPWM timer0*/
+    MCPWM_TIMER_1,      /*!<Select MCPWM timer1*/
+    MCPWM_TIMER_2,      /*!<Select MCPWM timer2*/
+    MCPWM_TIMER_MAX,    /*!<Num of MCPWM timers on ESP32*/
+} mcpwm_timer_t;
+
+/**
+ * @brief Select MCPWM operator
+ */
+typedef enum {
+    MCPWM_OPR_A = 0,  /*!<Select MCPWMXA, where 'X' is timer number*/
+    MCPWM_OPR_B,      /*!<Select MCPWMXB, where 'X' is timer number*/
+    MCPWM_OPR_MAX,    /*!<Num of operators to each timer of MCPWM*/
+} mcpwm_operator_t;
+
+/**
+ * @brief Select type of MCPWM counter
+ */
+typedef enum {
+    MCPWM_UP_COUNTER = 1,   /*!<For asymmetric MCPWM*/
+    MCPWM_DOWN_COUNTER,     /*!<For asymmetric MCPWM*/
+    MCPWM_UP_DOWN_COUNTER,  /*!<For symmetric MCPWM, frequency is half of MCPWM frequency set*/
+    MCPWM_COUNTER_MAX,      /*!<Maximum counter mode*/
+} mcpwm_counter_type_t;
+
+/**
+ * @brief Select type of MCPWM duty cycle mode
+ */
+typedef enum {
+    MCPWM_DUTY_MODE_0 = 0, /*!<Active high duty, i.e. duty cycle proportional to high time for asymmetric MCPWM*/
+    MCPWM_DUTY_MODE_1,     /*!<Active low duty,  i.e. duty cycle proportional to low  time for asymmetric MCPWM, out of phase(inverted) MCPWM*/
+    MCPWM_DUTY_MODE_MAX,   /*!<Num of duty cycle modes*/
+} mcpwm_duty_type_t;
+
+/**
+ * @brief MCPWM carrier oneshot mode, in this mode the width of the first pulse of carrier can be programmed
+ */
+typedef enum {
+    MCPWM_ONESHOT_MODE_DIS = 0,  /*!<Enable oneshot mode*/
+    MCPWM_ONESHOT_MODE_EN,       /*!<Disable oneshot mode*/
+} mcpwm_carrier_os_t;
+
+/**
+ * @brief MCPWM carrier output inversion, high frequency carrier signal active with MCPWM signal is high
+ */
+typedef enum {
+    MCPWM_CARRIER_OUT_IVT_DIS = 0,  /*!<Enable  carrier output inversion*/
+    MCPWM_CARRIER_OUT_IVT_EN,       /*!<Disable carrier output inversion*/
+} mcpwm_carrier_out_ivt_t;
+
+/**
+ * @brief MCPWM select sync signal input
+ */
+typedef enum {
+    MCPWM_SELECT_SYNC0 = 4,  /*!<Select SYNC0 as input*/
+    MCPWM_SELECT_SYNC1,      /*!<Select SYNC1 as input*/
+    MCPWM_SELECT_SYNC2,      /*!<Select SYNC2 as input*/
+} mcpwm_sync_signal_t;
+
+/**
+ * @brief MCPWM select fault signal input
+ */
+typedef enum {
+    MCPWM_SELECT_F0 = 0,  /*!<Select F0 as input*/
+    MCPWM_SELECT_F1,      /*!<Select F1 as input*/
+    MCPWM_SELECT_F2,      /*!<Select F2 as input*/
+} mcpwm_fault_signal_t;
+
+/**
+ * @brief MCPWM select triggering level of fault signal
+ */
+typedef enum {
+    MCPWM_LOW_LEVEL_TGR = 0,  /*!<Fault condition occurs when fault input signal goes from high to low, currently not supported*/
+    MCPWM_HIGH_LEVEL_TGR,     /*!<Fault condition occurs when fault input signal goes low to high*/
+} mcpwm_fault_input_level_t;
+
+/**
+ * @brief MCPWM select action to be taken on MCPWMXA when fault occurs
+ */
+typedef enum {
+    MCPWM_NO_CHANGE_IN_MCPWMXA = 0,  /*!<No change in MCPWMXA output*/
+    MCPWM_FORCE_MCPWMXA_LOW,         /*!<Make MCPWMXA output low*/
+    MCPWM_FORCE_MCPWMXA_HIGH,        /*!<Make MCPWMXA output high*/
+    MCPWM_TOG_MCPWMXA,               /*!<Make MCPWMXA output toggle*/
+} mcpwm_action_on_pwmxa_t;
+
+/**
+ * @brief MCPWM select action to be taken on MCPWMxB when fault occurs
+ */
+typedef enum {
+    MCPWM_NO_CHANGE_IN_MCPWMXB = 0,  /*!<No change in MCPWMXB output*/
+    MCPWM_FORCE_MCPWMXB_LOW,         /*!<Make MCPWMXB output low*/
+    MCPWM_FORCE_MCPWMXB_HIGH,        /*!<Make MCPWMXB output high*/
+    MCPWM_TOG_MCPWMXB,               /*!<Make MCPWMXB output toggle*/
+} mcpwm_action_on_pwmxb_t;
+
+/**
+ * @brief MCPWM select capture signal input
+ */
+typedef enum {
+    MCPWM_SELECT_CAP0 = 0, /*!<Select CAP0 as input*/
+    MCPWM_SELECT_CAP1,     /*!<Select CAP1 as input*/
+    MCPWM_SELECT_CAP2,     /*!<Select CAP2 as input*/
+} mcpwm_capture_signal_t;
+
+/**
+ * @brief MCPWM select capture starts from which edge
+ */
+typedef enum {
+    MCPWM_NEG_EDGE = 0,  /*!<Capture starts from negative edge*/
+    MCPWM_POS_EDGE,      /*!<Capture starts from positive edge*/
+} mcpwm_capture_on_edge_t;
+
+/**
+ * @brief MCPWM deadtime types, used to generate deadtime, RED refers to rising edge delay and FED refers to falling edge delay
+ */
+typedef enum {
+    MCPWM_BYPASS_RED = 0,               /*!<MCPWMXA = no change, MCPWMXB = falling edge delay*/
+    MCPWM_BYPASS_FED,                   /*!<MCPWMXA = rising edge delay, MCPWMXB = no change*/
+    MCPWM_ACTIVE_HIGH_MODE,             /*!<MCPWMXA = rising edge delay,  MCPWMXB = falling edge delay*/
+    MCPWM_ACTIVE_LOW_MODE,              /*!<MCPWMXA = compliment of rising edge delay,  MCPWMXB = compliment of falling edge delay*/
+    MCPWM_ACTIVE_HIGH_COMPLIMENT_MODE,  /*!<MCPWMXA = rising edge delay,  MCPWMXB = compliment of falling edge delay*/
+    MCPWM_ACTIVE_LOW_COMPLIMENT_MODE,   /*!<MCPWMXA = compliment of rising edge delay,  MCPWMXB = falling edge delay*/
+    MCPWM_ACTIVE_RED_FED_FROM_PWMXA,    /*!<MCPWMXA = MCPWMXB = rising edge delay as well as falling edge delay, generated from MCPWMXA*/
+    MCPWM_ACTIVE_RED_FED_FROM_PWMXB,    /*!<MCPWMXA = MCPWMXB = rising edge delay as well as falling edge delay, generated from MCPWMXB*/
+    MCPWM_DEADTIME_TYPE_MAX,
+} mcpwm_deadtime_type_t;
+
+/**
+ * @brief MCPWM config structure
+ */
+typedef struct {
+    uint32_t frequency;              /*!<Set frequency of MCPWM in Hz*/
+    float cmpr_a;                    /*!<Set % duty cycle for operator a(MCPWMXA), i.e for 62.3% duty cycle, duty_a = 62.3*/
+    float cmpr_b;                    /*!<Set % duty cycle for operator b(MCPWMXB), i.e for 48% duty cycle, duty_b = 48.0*/
+    mcpwm_duty_type_t duty_mode;     /*!<Set type of duty cycle*/
+    mcpwm_counter_type_t counter_mode;  /*!<Set  type of MCPWM counter*/
+} mcpwm_config_t;
+
+/**
+ * @brief MCPWM config carrier structure
+ */
+typedef struct {
+    uint8_t carrier_period;                 /*!<Set carrier period = (carrier_period + 1)*800ns, carrier_period should be < 16*/
+    uint8_t carrier_duty;                   /*!<Set carrier duty cycle, carrier_duty should be less then 8(increment every 12.5%)*/
+    uint8_t pulse_width_in_os;              /*!<Set pulse width of first pulse in one shot mode = (carrier period)*(pulse_width_in_os + 1), should be less then 16*/
+    mcpwm_carrier_os_t carrier_os_mode;        /*!<Enable or disable carrier oneshot mode*/
+    mcpwm_carrier_out_ivt_t carrier_ivt_mode;  /*!<Invert output of carrier*/
+} mcpwm_carrier_config_t;
+
+
+/**
+ * @brief This function initializes each gpio signal for MCPWM
+ *        @note
+ *        This function initializes one gpio at a time.
+ *
+ * @param mcpwm_num set MCPWM Channel(0-1)
+ * @param io_signal set MCPWM signals, each MCPWM unit has 6 output(MCPWMXA, MCPWMXB) and 9 input(SYNC_X, FAULT_X, CAP_X)
+ *                  'X' is timer_num(0-2)
+ * @param gpio_num set this to configure gpio for MCPWM, if you want to use gpio16, gpio_num = 16
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_gpio_init(mcpwm_unit_t mcpwm_num, mcpwm_io_signals_t io_signal, int gpio_num);
+
+/**
+ * @brief Initialize MCPWM gpio structure
+ *        @note
+ *        This function can be used to initialize more then one gpio at a time.
+ *
+ * @param mcpwm_num set MCPWM Channel(0-1)
+ * @param mcpwm_pin MCPWM pin structure
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_set_pin(mcpwm_unit_t mcpwm_num, const mcpwm_pin_config_t *mcpwm_pin);
+
+/**
+ * @brief Initialize MCPWM parameters
+ *
+ * @param mcpwm_num set MCPWM Channel(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param mcpwm_conf configure structure mcpwm_config_t
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_init( mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, const mcpwm_config_t  *mcpwm_conf);
+
+/**
+ * @brief Set frequency(in Hz) of MCPWM timer
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param frequency set the frequency in Hz of each timer
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_set_frequency(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, uint32_t frequency);
+
+/**
+ * @brief Set duty cycle of each operator(MCPWMXA/MCPWMXB)
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param op_num set the operator(MCPWMXA/MCPWMXB), 'X' is timer number selected
+ * @param duty set duty cycle in %(i.e for 62.3% duty cycle, duty = 62.3) of each operator
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_set_duty(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_operator_t op_num, float duty);
+
+/**
+ * @brief Set duty cycle of each operator(MCPWMXA/MCPWMXB) in us
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param op_num set the operator(MCPWMXA/MCPWMXB), 'x' is timer number selected
+ * @param duty set duty value in microseconds of each operator
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_set_duty_in_us(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_operator_t op_num, uint32_t duty);
+
+/**
+ * @brief Set duty either active high or active low(out of phase/inverted)
+ *        @note
+ *        Call this function every time after mcpwm_set_signal_high or mcpwm_set_signal_low to resume with previously set duty cycle
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param op_num set the operator(MCPWMXA/MCPWMXB), 'x' is timer number selected
+ * @param duty_num set active low or active high duty type
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_set_duty_type(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_operator_t op_num, mcpwm_duty_type_t duty_num);
+
+/**
+* @brief Get frequency of timer
+*
+* @param mcpwm_num set MCPWM unit(0-1)
+* @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+*
+* @return
+*     - frequency of timer
+*/
+uint32_t mcpwm_get_frequency(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num);
+
+/**
+ * @brief Get duty cycle of each operator
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param op_num set the operator(MCPWMXA/MCPWMXB), 'x' is timer number selected
+ *
+ * @return
+ *     - duty cycle in % of each operator(56.7 means duty is 56.7%)
+ */
+float mcpwm_get_duty(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_operator_t op_num);
+
+/**
+ * @brief Use this function to set MCPWM signal high
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param op_num set the operator(MCPWMXA/MCPWMXB), 'x' is timer number selected
+
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_set_signal_high(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_operator_t op_num);
+
+/**
+ * @brief Use this function to set MCPWM signal low
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param op_num set the operator(MCPWMXA/MCPWMXB), 'x' is timer number selected
+
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_set_signal_low(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_operator_t op_num);
+/**
+ * @brief Start MCPWM signal on timer 'x'
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_start(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num);
+
+/**
+ * @brief Start MCPWM signal on timer 'x'
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_stop(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num);
+
+/**
+ * @brief  Initialize carrier configuration
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param carrier_conf configure structure mcpwm_carrier_config_t
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_carrier_init(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, const mcpwm_carrier_config_t *carrier_conf);
+
+/**
+* @brief Enable MCPWM carrier submodule, for respective timer
+*
+* @param mcpwm_num set MCPWM unit(0-1)
+* @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+*
+* @return
+*     - ESP_OK Success
+*     - ESP_ERR_INVALID_ARG Parameter error
+*/
+esp_err_t mcpwm_carrier_enable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num);
+
+/**
+ * @brief Disable MCPWM carrier submodule, for respective timer
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_carrier_disable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num);
+
+/**
+ * @brief Set period of carrier
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param carrier_period set the carrier period of each timer, carrier period = (carrier_period + 1)*800ns
+ *                    (carrier_period <= 15)
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_carrier_set_period(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, uint8_t carrier_period);
+
+/**
+ * @brief Set duty_cycle of carrier
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param carrier_duty set duty_cycle of carrier , carrier duty cycle = carrier_duty*12.5%
+ *                  (chop_duty <= 7)
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_carrier_set_duty_cycle(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, uint8_t carrier_duty);
+
+/**
+ * @brief Enable and set width of first pulse in carrier oneshot mode
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param pulse_width set pulse width of first pulse in oneshot mode, width = (carrier period)*(pulse_width +1)
+ *                    (pulse_width <= 15)
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_carrier_oneshot_mode_enable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, uint8_t pulse_width);
+
+/**
+ * @brief Disable oneshot mode, width of first pulse = carrier period
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_carrier_oneshot_mode_disable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num);
+
+/**
+ * @brief Enable or disable carrier output inversion
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param carrier_ivt_mode enable or disable carrier output inversion
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_carrier_output_invert(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num,
+                                      mcpwm_carrier_out_ivt_t carrier_ivt_mode);
+
+/**
+ * @brief Enable and initialize deadtime for each MCPWM timer
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param dt_mode set deadtime mode
+ * @param red set rising edge delay = red*100ns
+ * @param fed set rising edge delay = fed*100ns
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_deadtime_enable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_deadtime_type_t dt_mode,
+                                uint32_t red, uint32_t fed);
+
+/**
+ * @brief Disable deadtime on MCPWM timer
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_deadtime_disable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num);
+
+/**
+ * @brief Initialize fault submodule, currently low level triggering not supported
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param intput_level set fault signal level, which will cause fault to occur
+ * @param fault_sig set the fault Pin, which needs to be enabled
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_fault_init(mcpwm_unit_t mcpwm_num, mcpwm_fault_input_level_t intput_level, mcpwm_fault_signal_t fault_sig);
+
+/**
+ * @brief Set oneshot mode on fault detection, once fault occur in oneshot mode reset is required to resume MCPWM signals
+ *        @note
+ *        currently low level triggering not supported
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param fault_sig set the fault Pin, which needs to be enabled for oneshot mode
+ * @param action_on_pwmxa action to be taken on MCPWMXA when fault occurs, either no change or high or low or toggle
+ * @param action_on_pwmxb action to be taken on MCPWMXB when fault occurs, either no change or high or low or toggle
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_fault_set_oneshot_mode(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_fault_signal_t fault_sig,
+                                       mcpwm_action_on_pwmxa_t action_on_pwmxa, mcpwm_action_on_pwmxb_t action_on_pwmxb);
+
+/**
+ * @brief Set cycle-by-cycle mode on fault detection, once fault occur in cyc mode MCPWM signal resumes as soon as fault signal becomes inactive
+ *        @note
+ *        currently low level triggering not supported
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param fault_sig set the fault Pin, which needs to be enabled for cyc mode
+ * @param action_on_pwmxa action to be taken on MCPWMXA when fault occurs, either no change or high or low or toggle
+ * @param action_on_pwmxb action to be taken on MCPWMXB when fault occurs, either no change or high or low or toggle
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_fault_set_cyc_mode(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_fault_signal_t fault_sig,
+                                   mcpwm_action_on_pwmxa_t action_on_pwmxa, mcpwm_action_on_pwmxb_t action_on_pwmxb);
+
+/**
+ * @brief Disable fault signal
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param fault_sig fault pin, which needs to be disabled
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_fault_deinit(mcpwm_unit_t mcpwm_num, mcpwm_fault_signal_t fault_sig);
+
+/**
+ * @brief Initialize capture submodule
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param cap_edge set capture edge, BIT(0) - negative edge, BIT(1) - positive edge
+ * @param cap_sig capture Pin, which needs to be enabled
+ * @param num_of_pulse count time between rising/falling edge between 2 *(pulses mentioned), counter uses APB_CLK
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+
+esp_err_t mcpwm_capture_enable(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t cap_sig, mcpwm_capture_on_edge_t cap_edge,
+                               uint32_t num_of_pulse);
+
+/**
+ * @brief Disable capture signal
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param cap_sig capture Pin, which needs to be disabled
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_capture_disable(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t cap_sig);
+
+/**
+ * @brief Get capture value
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param cap_sig capture pin on which value is to be measured
+ *
+ * @return
+ *     Captured value
+ */
+uint32_t mcpwm_capture_signal_get_value(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t cap_sig);
+
+/**
+ * @brief Get edge of capture signal
+ *
+ * @param mcpwm_num set MCPWM Channel(0-1)
+ * @param cap_sig capture pin of whose edge is to be determined
+ *
+ * @return
+ *     Capture signal edge: 1 - positive edge, 2 - negtive edge
+ */
+uint32_t mcpwm_capture_signal_get_edge(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t cap_sig);
+
+/**
+ * @brief Initialize sync submodule
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param sync_sig set the fault Pin, which needs to be enabled
+ * @param phase_val phase value in 1/1000(for 86.7%, phase_val = 867) which timer moves to on sync signal
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_sync_enable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_sync_signal_t sync_sig,
+                            uint32_t phase_val);
+
+/**
+ * @brief Disable sync submodule on given timer
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_sync_disable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num);
+
+/**
+ * @brief Register MCPWM interrupt handler, the handler is an ISR.
+ *        the handler will be attached to the same CPU core that this function is running on.
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param fn interrupt handler function.
+ * @param arg user-supplied argument passed to the handler function.
+ * @param intr_alloc_flags flags used to allocate the interrupt. One or multiple (ORred)
+ *        ESP_INTR_FLAG_* values. see esp_intr_alloc.h for more info.
+ * @param arg parameter for handler function
+ * @param handle pointer to return handle. If non-NULL, a handle for the interrupt will
+ *        be returned here.
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Function pointer error.
+ */
+esp_err_t mcpwm_isr_register(mcpwm_unit_t mcpwm_num, void (*fn)(void *), void *arg, int intr_alloc_flags, intr_handle_t *handle);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /*_DRIVER_MCPWM_H_*/
diff --git a/tools/sdk/include/driver/driver/spi_master.h b/tools/sdk/include/driver/driver/spi_master.h
index ba8bc5d9..29b408af 100644
--- a/tools/sdk/include/driver/driver/spi_master.h
+++ b/tools/sdk/include/driver/driver/spi_master.h
@@ -100,6 +100,10 @@ typedef struct spi_device_t* spi_device_handle_t;  ///< Handle for a device on a
  *                 for a SPI bus allows transfers on the bus to have sizes only limited by the amount of 
  *                 internal memory. Selecting no DMA channel (by passing the value 0) limits the amount of
  *                 bytes transfered to a maximum of 32.
+ *
+ * @warning If a DMA channel is selected, any transmit and receive buffer used should be allocated in 
+ *          DMA-capable memory.
+ *
  * @return 
  *         - ESP_ERR_INVALID_ARG   if configuration is invalid
  *         - ESP_ERR_INVALID_STATE if host already is in use
diff --git a/tools/sdk/include/driver/driver/spi_slave.h b/tools/sdk/include/driver/driver/spi_slave.h
index a3706bb6..047ab413 100644
--- a/tools/sdk/include/driver/driver/spi_slave.h
+++ b/tools/sdk/include/driver/driver/spi_slave.h
@@ -69,6 +69,10 @@ struct spi_slave_transaction_t {
  * @param dma_chan Either 1 or 2. A SPI bus used by this driver must have a DMA channel associated with
  *                 it. The SPI hardware has two DMA channels to share. This parameter indicates which
  *                 one to use.
+ *
+ * @warning If a DMA channel is selected, any transmit and receive buffer used should be allocated in 
+ *          DMA-capable memory.
+ *
  * @return 
  *         - ESP_ERR_INVALID_ARG   if configuration is invalid
  *         - ESP_ERR_INVALID_STATE if host already is in use
diff --git a/tools/sdk/include/esp32/esp_assert.h b/tools/sdk/include/esp32/esp_assert.h
new file mode 100644
index 00000000..39d6a328
--- /dev/null
+++ b/tools/sdk/include/esp32/esp_assert.h
@@ -0,0 +1,37 @@
+// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef __ESP_ASSERT_H__
+#define __ESP_ASSERT_H__
+
+#include "assert.h"
+
+/* Assert at compile time if possible, runtime otherwise */
+#ifndef __cplusplus
+/* __builtin_choose_expr() is only in C, makes this a lot cleaner */
+#define TRY_STATIC_ASSERT(CONDITION, MSG) do {                                                              \
+            _Static_assert(__builtin_choose_expr(__builtin_constant_p(CONDITION), (CONDITION), 1), #MSG);   \
+            assert(#MSG && (CONDITION));                                                                    \
+        } while(0)
+#else
+/* for C++, use __attribute__((error)) - works almost as well as _Static_assert */
+#define TRY_STATIC_ASSERT(CONDITION, MSG) do {                                                              \
+            if (__builtin_constant_p(CONDITION) && !(CONDITION)) {          \
+                extern __attribute__((error(#MSG))) void failed_compile_time_assert(void);      \
+                failed_compile_time_assert();                                                   \
+            }                                                                                   \
+            assert(#MSG && (CONDITION));                                                                    \
+        } while(0)
+#endif /* __cplusplus */
+
+#endif /* __ESP_ASSERT_H__ */
diff --git a/tools/sdk/include/esp32/esp_dport_access.h b/tools/sdk/include/esp32/esp_dport_access.h
new file mode 100644
index 00000000..14b589aa
--- /dev/null
+++ b/tools/sdk/include/esp32/esp_dport_access.h
@@ -0,0 +1,22 @@
+// Copyright 2010-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _ESP_DPORT_ACCESS_H_
+#define _ESP_DPORT_ACCESS_H_
+
+void esp_dport_access_stall_other_cpu_start(void);
+void esp_dport_access_stall_other_cpu_end(void);
+void esp_dport_access_int_init(void);
+
+#endif /* _ESP_DPORT_ACCESS_H_ */
diff --git a/tools/sdk/include/esp32/esp_err.h b/tools/sdk/include/esp32/esp_err.h
index 2990c893..cf0973c5 100644
--- a/tools/sdk/include/esp32/esp_err.h
+++ b/tools/sdk/include/esp32/esp_err.h
@@ -37,6 +37,8 @@ typedef int32_t esp_err_t;
 #define ESP_ERR_TIMEOUT         0x107
 #define ESP_ERR_INVALID_RESPONSE    0x108
 #define ESP_ERR_INVALID_CRC     0x109
+#define ESP_ERR_INVALID_VERSION     0x10A
+#define ESP_ERR_INVALID_MAC     0x10B
 
 #define ESP_ERR_WIFI_BASE       0x3000 /*!< Starting number of WiFi error codes */
 
diff --git a/tools/sdk/include/esp32/esp_heap_alloc_caps.h b/tools/sdk/include/esp32/esp_heap_alloc_caps.h
index e1021c30..a0e40a7c 100644
--- a/tools/sdk/include/esp32/esp_heap_alloc_caps.h
+++ b/tools/sdk/include/esp32/esp_heap_alloc_caps.h
@@ -87,4 +87,17 @@ size_t xPortGetMinimumEverFreeHeapSizeCaps( uint32_t caps );
 
 
 
+/**
+ * @brief Convenience function to check if a pointer is DMA-capable.
+ *
+ * @param ptr         Pointer to check
+ *
+ * @return True if DMA-capable, false if not.
+ */
+static inline bool  esp_ptr_dma_capable( const void *ptr ) 
+{
+    return ( (int)ptr >= 0x3FFAE000 && (int)ptr < 0x40000000 );
+}
+
+
 #endif
\ No newline at end of file
diff --git a/tools/sdk/include/esp32/esp_system.h b/tools/sdk/include/esp32/esp_system.h
index 24eebb8b..63592081 100644
--- a/tools/sdk/include/esp32/esp_system.h
+++ b/tools/sdk/include/esp32/esp_system.h
@@ -31,9 +31,9 @@ typedef enum {
     ESP_MAC_ETH,
 } esp_mac_type_t;
 
-#define TWO_MAC_ADDRESS_FROM_EFUSE 2
-#define FOUR_MAC_ADDRESS_FROM_EFUSE 4
-#define NUM_MAC_ADDRESS_FROM_EFUSE CONFIG_NUMBER_OF_MAC_ADDRESS_GENERATED_FROM_EFUSE
+#define TWO_UNIVERSAL_MAC_ADDR 2
+#define FOUR_UNIVERSAL_MAC_ADDR 4
+#define UNIVERSAL_MAC_ADDR_NUM CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS
 
 /**
   * @attention  application don't need to call this function anymore. It do nothing and will
@@ -103,60 +103,84 @@ uint32_t system_get_free_heap_size(void)  __attribute__ ((deprecated));
 uint32_t esp_random(void);
 
 /**
-  * @brief  Set base MAC address from external storage e.g. flash and EEPROM.
+  * @brief  Set base MAC address with the MAC address which is stored in BLK3 of EFUSE or
+  *         external storage e.g. flash and EEPROM.
   *
   * Base MAC address is used to generate the MAC addresses used by the networking interfaces.
-  * If using base MAC address stored in external storage, call this API to set base MAC
-  * address from external storage before initializing WiFi/BT/Ethernet.
+  * If using base MAC address stored in BLK3 of EFUSE or external storage, call this API to set base MAC
+  * address with the MAC address which is stored in BLK3 of EFUSE or external storage before initializing
+  * WiFi/BT/Ethernet.
   *
   * @param  mac  base MAC address, length: 6 bytes.
   *
   * @return ESP_OK on success
   */
-esp_err_t esp_base_mac_addr_set_external(uint8_t *mac);
+esp_err_t esp_base_mac_addr_set(uint8_t *mac);
 
 /**
-  * @brief  Return base MAC address set using esp_mac_addr_set_external.
+  * @brief  Return base MAC address which is set using esp_base_mac_addr_set.
   *
   * @param  mac  base MAC address, length: 6 bytes.
   *
+  * @return ESP_OK on success
+  *         ESP_ERR_INVALID_MAC base MAC address has not been set
+  */
+esp_err_t esp_base_mac_addr_get(uint8_t *mac);
+
+/**
+  * @brief  Return base MAC address which was previously written to BLK3 of EFUSE.
+  *
   * Base MAC address is used to generate the MAC addresses used by the networking interfaces.
-  * If using base MAC address stored in external storage, call this API to set base MAC
-  * address from external storage before initializing WiFi/BT/Ethernet.
+  * This API returns the custom base MAC address which was previously written to BLK3 of EFUSE.
+  * Writing this EFUSE allows setting of a different (non-Espressif) base MAC address. It is also
+  * possible to store a custom base MAC address elsewhere, see esp_base_mac_addr_set() for details.
+  *
+  * @param  mac  base MAC address, length: 6 bytes.
+  *
+  * @return ESP_OK on success
+  *         ESP_ERR_INVALID_VERSION An invalid MAC version field was read from BLK3 of EFUSE
+  *         ESP_ERR_INVALID_CRC An invalid MAC CRC was read from BLK3 of EFUSE
+  */
+esp_err_t esp_efuse_mac_get_custom(uint8_t *mac);
+
+/**
+  * @brief  Return base MAC address which is factory-programmed by Espressif in BLK0 of EFUSE.
+  *
+  * @param  mac  base MAC address, length: 6 bytes.
   *
   * @return ESP_OK on success
   */
-esp_err_t esp_base_mac_addr_get_external(uint8_t *mac);
+esp_err_t esp_efuse_mac_get_default(uint8_t *mac);
 
 /**
   * @brief  Read hardware MAC address from efuse.
   *
-  * In WiFi MAC, only ESP32 station MAC is the hardware MAC, ESP32 softAP MAC is a software MAC 
-  * calculated from ESP32 station MAC. 
-  * So users need to call esp_wifi_get_macaddr to query the ESP32 softAP MAC if ESP32 station MAC changed.
+  * Function has been renamed to esp_efuse_mac_get_default.
+  * This name will be removed in a future release.
   *
   * @param  mac  hardware MAC address, length: 6 bytes.
   *
   * @return ESP_OK on success
   */
-esp_err_t esp_efuse_read_mac(uint8_t* mac);
+esp_err_t esp_efuse_read_mac(uint8_t *mac) __attribute__ ((deprecated));
 
 /**
   * @brief  Read hardware MAC address.
   *
-  * Function has been renamed to esp_efuse_read_mac.
+  * Function has been renamed to esp_efuse_mac_get_default.
   * This name will be removed in a future release.
   *
   * @param  mac  hardware MAC address, length: 6 bytes.
   * @return ESP_OK on success
   */
-esp_err_t system_efuse_read_mac(uint8_t mac[6]) __attribute__ ((deprecated));
+esp_err_t system_efuse_read_mac(uint8_t *mac) __attribute__ ((deprecated));
 
 /**
-  * @brief  Read hardware MAC address and set MAC address of the interface.
+  * @brief  Read base MAC address and set MAC address of the interface.
   *
-  * This function first reads hardware MAC address from efuse. Then set the MAC address of the interface
-  * including wifi station, wifi softap, bluetooth and ethernet.
+  * This function first get base MAC address using esp_base_mac_addr_get or reads base MAC address
+  * from BLK0 of EFUSE. Then set the MAC address of the interface including wifi station, wifi softap,
+  * bluetooth and ethernet.
   *
   * @param  mac  MAC address of the interface, length: 6 bytes.
   * @param  type  type of MAC address, 0:wifi station, 1:wifi softap, 2:bluetooth, 3:ethernet.
@@ -166,32 +190,20 @@ esp_err_t system_efuse_read_mac(uint8_t mac[6]) __attribute__ ((deprecated));
 esp_err_t esp_read_mac(uint8_t* mac, esp_mac_type_t type);
 
 /**
-  * @brief  Derive MAC address.
+  * @brief  Derive local MAC address from universal MAC address.
   *
   * This function derives a local MAC address from an universal MAC address.
-  * Addresses can either be universally administered addresses or locally administered addresses.
-  * A universally administered address is uniquely assigned to a device by its manufacturer.
-  * The first three octets (in transmission order) identify the organization that issued the identifier
-  * and are known as the Organizationally Unique Identifier (OUI).[4] The remainder of the address
-  * (three octets for MAC-48 and EUI-48 or five for EUI-64) are assigned by that organization in nearly
-  * any manner they please, subject to the constraint of uniqueness. A locally administered address is
-  * assigned to a device by a network administrator, overriding the burned-in address.
-  * Universally administered and locally administered addresses are distinguished by setting
-  * the second-least-significant bit of the first octet of the address. This bit is also referred to
-  * as the U/L bit, short for Universal/Local, which identifies how the address is administered.
-  * If the bit is 0, the address is universally administered. If it is 1, the address is locally administered.
-  * In the example address 06-00-00-00-00-00 the first octet is 06 (hex), the binary form of which is 00000110,
-  * where the second-least-significant bit is 1. Therefore, it is a locally administered address.[7] Consequently,
-  * this bit is 0 in all OUIs.
-  * In ESP32, universal MAC address is generated from the hardware MAC address in efuse.
+  * A `definition of local vs universal MAC address can be found on Wikipedia
+  * <https://en.wikipedia.org/wiki/MAC_address#Universal_vs._local>`.
+  * In ESP32, universal MAC address is generated from base MAC address in EFUSE or other external storage.
   * Local MAC address is derived from the universal MAC address.
   *
-  * @param  dst_mac  Derived local MAC address, length: 6 bytes.
-  * @param  src_mac  Source universal MAC address, length: 6 bytes.
+  * @param  local_mac  Derived local MAC address, length: 6 bytes.
+  * @param  universal_mac  Source universal MAC address, length: 6 bytes.
   *
   * @return ESP_OK on success
   */
-esp_err_t esp_derive_mac(uint8_t* dst_mac, const uint8_t* src_mac);
+esp_err_t esp_derive_local_mac(uint8_t* local_mac, const uint8_t* universal_mac);
 
 /**
  * Get SDK version
@@ -209,6 +221,38 @@ const char* system_get_sdk_version(void)  __attribute__ ((deprecated));
  */
 const char* esp_get_idf_version(void);
 
+
+/**
+ * @brief Chip models
+ */
+typedef enum {
+    CHIP_ESP32 = 1, //!< ESP32
+} esp_chip_model_t;
+
+/**
+ * Chip feature flags, used in esp_chip_info_t
+ */
+#define CHIP_FEATURE_EMB_FLASH      BIT(0)
+#define CHIP_FEATURE_WIFI_BGN       BIT(1)
+#define CHIP_FEATURE_BLE            BIT(4)
+#define CHIP_FEATURE_BT             BIT(5)
+
+/**
+ * @brief The structure represents information about the chip
+ */
+typedef struct {
+    esp_chip_model_t model;  //!< chip model, one of esp_chip_model_t
+    uint32_t features;       //!< bit mask of CHIP_FEATURE_x feature flags
+    uint8_t cores;           //!< number of CPU cores
+    uint8_t revision;        //!< chip revision number
+} esp_chip_info_t;
+
+/**
+ * @brief Fill an esp_chip_info_t structure with information about the chip
+ * @param[out] out_info structure to be filled
+ */
+void esp_chip_info(esp_chip_info_t* out_info);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/tools/sdk/include/esp32/rom/cache.h b/tools/sdk/include/esp32/rom/cache.h
index fb84bca0..72aa33aa 100644
--- a/tools/sdk/include/esp32/rom/cache.h
+++ b/tools/sdk/include/esp32/rom/cache.h
@@ -15,6 +15,8 @@
 #ifndef _ROM_CACHE_H_
 #define _ROM_CACHE_H_
 
+#include "soc/dport_access.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -64,7 +66,18 @@ void mmu_init(int cpu_no);
   *                   4 : mmu table to be written is out of range
   *                   5 : vaddr is out of range
   */
-unsigned int cache_flash_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr,  int psize, int num);
+static inline unsigned int IRAM_ATTR cache_flash_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr,  int psize, int num)
+{
+    extern unsigned int cache_flash_mmu_set_rom(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr,  int psize, int num);
+
+    unsigned int ret;
+
+    DPORT_STALL_OTHER_CPU_START();
+    ret = cache_flash_mmu_set_rom(cpu_no, pid, vaddr, paddr, psize, num);
+    DPORT_STALL_OTHER_CPU_END();
+
+    return ret;
+}
 
 /**
   * @brief Set Ext-SRAM-Cache mmu mapping.
@@ -93,7 +106,18 @@ unsigned int cache_flash_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsign
   *                   4 : mmu table to be written is out of range
   *                   5 : vaddr is out of range
   */
-unsigned int cache_sram_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num);
+static inline unsigned int IRAM_ATTR cache_sram_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num)
+{
+    extern unsigned int cache_sram_mmu_set_rom(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num);
+
+    unsigned int ret;
+
+    DPORT_STALL_OTHER_CPU_START();
+    ret = cache_sram_mmu_set_rom(cpu_no, pid, vaddr, paddr, psize, num);
+    DPORT_STALL_OTHER_CPU_END();
+
+    return ret;
+}
 
 /**
   * @brief Initialise cache access for the cpu.
@@ -103,7 +127,13 @@ unsigned int cache_sram_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigne
   *
   * @return None
   */
-void Cache_Read_Init(int cpu_no);
+static inline void IRAM_ATTR Cache_Read_Init(int cpu_no)
+{
+    extern void Cache_Read_Init_rom(int cpu_no);
+    DPORT_STALL_OTHER_CPU_START();
+    Cache_Read_Init_rom(cpu_no);
+    DPORT_STALL_OTHER_CPU_END();
+}
 
 /**
   * @brief Flush the cache value for the cpu.
@@ -113,7 +143,13 @@ void Cache_Read_Init(int cpu_no);
   *
   * @return None
   */
-void Cache_Flush(int cpu_no);
+static inline void IRAM_ATTR Cache_Flush(int cpu_no)
+{
+    extern void Cache_Flush_rom(int cpu_no);
+    DPORT_STALL_OTHER_CPU_START();
+    Cache_Flush_rom(cpu_no);
+    DPORT_STALL_OTHER_CPU_END();
+}
 
 /**
   * @brief Disable Cache access for the cpu.
@@ -123,7 +159,13 @@ void Cache_Flush(int cpu_no);
   *
   * @return None
   */
-void Cache_Read_Disable(int cpu_no);
+static inline void IRAM_ATTR Cache_Read_Disable(int cpu_no)
+{
+    extern void Cache_Read_Disable_rom(int cpu_no);
+    DPORT_STALL_OTHER_CPU_START();
+    Cache_Read_Disable_rom(cpu_no);
+    DPORT_STALL_OTHER_CPU_END();
+}
 
 /**
   * @brief Enable Cache access for the cpu.
@@ -133,7 +175,13 @@ void Cache_Read_Disable(int cpu_no);
   *
   * @return None
   */
-void Cache_Read_Enable(int cpu_no);
+static inline void IRAM_ATTR Cache_Read_Enable(int cpu_no)
+{
+    extern void Cache_Read_Enable_rom(int cpu_no);
+    DPORT_STALL_OTHER_CPU_START();
+    Cache_Read_Enable_rom(cpu_no);
+    DPORT_STALL_OTHER_CPU_END();
+}
 
 /**
   * @}
diff --git a/tools/sdk/include/soc/soc/dport_access.h b/tools/sdk/include/soc/soc/dport_access.h
new file mode 100644
index 00000000..3371b71e
--- /dev/null
+++ b/tools/sdk/include/soc/soc/dport_access.h
@@ -0,0 +1,126 @@
+// Copyright 2010-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _DPORT_ACCESS_H_
+#define _DPORT_ACCESS_H_
+
+#include <stdint.h>
+#include "esp_attr.h"
+
+void esp_dport_access_stall_other_cpu_start(void);
+void esp_dport_access_stall_other_cpu_end(void);
+
+#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !defined(ESP_PLATFORM)
+#define DPORT_STALL_OTHER_CPU_START()
+#define DPORT_STALL_OTHER_CPU_END()
+#else
+#define DPORT_STALL_OTHER_CPU_START()   esp_dport_access_stall_other_cpu_start()
+#define DPORT_STALL_OTHER_CPU_END()     esp_dport_access_stall_other_cpu_end()
+#endif
+
+//Registers Operation {{
+//Origin access operation for the base and some special scene
+#define _DPORT_REG_READ(_r)        (*(volatile uint32_t *)(_r))
+#define _DPORT_REG_WRITE(_r, _v)   (*(volatile uint32_t *)(_r)) = (_v)
+
+//write value to register
+#define DPORT_REG_WRITE(_r, _v)   _DPORT_REG_WRITE(_r, _v)
+
+//read value from register
+static inline uint32_t IRAM_ATTR DPORT_REG_READ(uint32_t reg)
+{
+    uint32_t val;
+
+    DPORT_STALL_OTHER_CPU_START();
+    val = _DPORT_REG_READ(reg);
+    DPORT_STALL_OTHER_CPU_END();
+    
+    return val;
+}
+
+//get bit or get bits from register
+#define DPORT_REG_GET_BIT(_r, _b)  (DPORT_REG_READ(_r) & (_b))
+
+//set bit or set bits to register
+#define DPORT_REG_SET_BIT(_r, _b)  DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r)|(_b)))
+
+//clear bit or clear bits of register
+#define DPORT_REG_CLR_BIT(_r, _b)  DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r) & (~(_b))))
+
+//set bits of register controlled by mask
+#define DPORT_REG_SET_BITS(_r, _b, _m) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~(_m))) | ((_b) & (_m))))
+
+//get field from register, uses field _S & _V to determine mask
+#define DPORT_REG_GET_FIELD(_r, _f) ((DPORT_REG_READ(_r) >> (_f##_S)) & (_f##_V))
+
+//set field to register, used when _f is not left shifted by _f##_S
+#define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f) << (_f##_S))))|(((_v) & (_f))<<(_f##_S))))
+
+//get field value from a variable, used when _f is not left shifted by _f##_S
+#define DPORT_VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
+
+//get field value from a variable, used when _f is left shifted by _f##_S
+#define DPORT_VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
+
+//set field value to a variable, used when _f is not left shifted by _f##_S
+#define DPORT_VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
+
+//set field value to a variable, used when _f is left shifted by _f##_S
+#define DPORT_VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
+
+//generate a value from a field value, used when _f is not left shifted by _f##_S
+#define DPORT_FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
+
+//generate a value from a field value, used when _f is left shifted by _f##_S
+#define DPORT_FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
+
+#define _READ_PERI_REG(addr) (*((volatile uint32_t *)(addr))) 
+#define _WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)(addr))) = (uint32_t)(val) 
+
+//read value from register
+static inline uint32_t IRAM_ATTR DPORT_READ_PERI_REG(uint32_t addr) 
+{
+    uint32_t val;
+
+    DPORT_STALL_OTHER_CPU_START();
+    val = _READ_PERI_REG(addr);
+    DPORT_STALL_OTHER_CPU_END();
+    
+    return val;
+}
+
+//write value to register
+#define DPORT_WRITE_PERI_REG(addr, val) _WRITE_PERI_REG(addr, val)  
+
+//clear bits of register controlled by mask
+#define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&(~(mask))))
+
+//set bits of register controlled by mask
+#define DPORT_SET_PERI_REG_MASK(reg, mask)   DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|(mask)))
+
+//get bits of register controlled by mask
+#define DPORT_GET_PERI_REG_MASK(reg, mask)   (DPORT_READ_PERI_REG(reg) & (mask))
+
+//get bits of register controlled by highest bit and lowest bit
+#define DPORT_GET_PERI_REG_BITS(reg, hipos,lowpos)     ((DPORT_READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
+
+//set bits of register controlled by mask and shift
+#define DPORT_SET_PERI_REG_BITS(reg,bit_map,value,shift) DPORT_WRITE_PERI_REG((reg),(DPORT_READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)))
+
+//get field of register
+#define DPORT_GET_PERI_REG_BITS2(reg, mask,shift)      ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask))
+//}}
+
+
+#endif /* _DPORT_ACCESS_H_ */
diff --git a/tools/sdk/include/soc/soc/dport_reg.h b/tools/sdk/include/soc/soc/dport_reg.h
index b2e14376..4e17363b 100644
--- a/tools/sdk/include/soc/soc/dport_reg.h
+++ b/tools/sdk/include/soc/soc/dport_reg.h
@@ -16,6 +16,14 @@
 
 #include "soc.h"
 
+#ifndef __ASSEMBLER__
+#include "dport_access.h"
+#endif
+   
+/* Registers defined in this header file must be accessed using special macros,
+ * prefixed with DPORT_. See soc/dport_access.h file for details.
+ */
+
 #define DPORT_PRO_BOOT_REMAP_CTRL_REG          (DR_REG_DPORT_BASE + 0x000)
 /* DPORT_PRO_BOOT_REMAP : R/W ;bitpos:[0] ;default: 1'b0 ; */
 /*description: */
diff --git a/tools/sdk/include/soc/soc/efuse_reg.h b/tools/sdk/include/soc/soc/efuse_reg.h
index 291e3984..b9ad20ee 100644
--- a/tools/sdk/include/soc/soc/efuse_reg.h
+++ b/tools/sdk/include/soc/soc/efuse_reg.h
@@ -79,12 +79,27 @@
 #define EFUSE_RD_WIFI_MAC_CRC_HIGH_S  0
 
 #define EFUSE_BLK0_RDATA3_REG          (DR_REG_EFUSE_BASE + 0x00c)
-/* EFUSE_RD_CHIP_VER_RESERVE : RO ;bitpos:[16:9] ;default: 8'b0 ; */
+/* EFUSE_RD_CHIP_VER_REV1 : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: bit is set to 1 for rev1 silicon*/
+#define EFUSE_RD_CHIP_VER_REV1  (BIT(15))
+#define EFUSE_RD_CHIP_VER_REV1_M  ((EFUSE_RD_CHIP_VER_REV1_V)<<(EFUSE_RD_CHIP_VER_REV1_S))
+#define EFUSE_RD_CHIP_VER_REV1_V  0x1
+#define EFUSE_RD_CHIP_VER_REV1_S  15
+/* EFUSE_RD_CHIP_VER_RESERVE : R/W ;bitpos:[15:12] ;default: 3'b0 ; */
 /*description: */
-#define EFUSE_RD_CHIP_VER_RESERVE  0x000000FF
+#define EFUSE_RD_CHIP_VER_RESERVE  0x00000007
 #define EFUSE_RD_CHIP_VER_RESERVE_M  ((EFUSE_RD_CHIP_VER_RESERVE_V)<<(EFUSE_RD_CHIP_VER_RESERVE_S))
-#define EFUSE_RD_CHIP_VER_RESERVE_V  0xFF
-#define EFUSE_RD_CHIP_VER_RESERVE_S  9
+#define EFUSE_RD_CHIP_VER_RESERVE_V  0x7
+#define EFUSE_RD_CHIP_VER_RESERVE_S  12
+/* EFUSE_RD_CHIP_VER : R/W ;bitpos:[11:9] ;default: 3'b0 ; */
+/*description: chip package */
+#define EFUSE_RD_CHIP_VER  0x00000007
+#define EFUSE_RD_CHIP_VER_PKG_M  ((EFUSE_RD_CHIP_VER_PKG_V)<<(EFUSE_RD_CHIP_VER_PKG_S))
+#define EFUSE_RD_CHIP_VER_PKG_V  0x7
+#define EFUSE_RD_CHIP_VER_PKG_S  9
+#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ6  0
+#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ5  1
+#define EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5  2
 /* EFUSE_RD_SPI_PAD_CONFIG_HD : RO ;bitpos:[8:4] ;default: 5'b0 ; */
 /*description: read for SPI_pad_config_hd*/
 #define EFUSE_RD_SPI_PAD_CONFIG_HD  0x0000001F
@@ -297,12 +312,24 @@
 #define EFUSE_WIFI_MAC_CRC_HIGH_S  0
 
 #define EFUSE_BLK0_WDATA3_REG          (DR_REG_EFUSE_BASE + 0x028)
-/* EFUSE_CHIP_VER_RESERVE : R/W ;bitpos:[16:9] ;default: 8'b0 ; */
+/* EFUSE_CHIP_VER_REV1 : R/W ;bitpos:[16] ;default: 1'b0 ; */
 /*description: */
-#define EFUSE_CHIP_VER_RESERVE  0x000000FF
+#define EFUSE_CHIP_VER_REV1  (BIT(15))
+#define EFUSE_CHIP_VER_REV1_M  ((EFUSE_CHIP_VER_REV1_V)<<(EFUSE_CHIP_VER_REV1_S))
+#define EFUSE_CHIP_VER_REV1_V  0x1
+#define EFUSE_CHIP_VER_REV1_S  15
+/* EFUSE_CHIP_VER_RESERVE : R/W ;bitpos:[15:12] ;default: 3'b0 ; */
+/*description: */
+#define EFUSE_CHIP_VER_RESERVE  0x00000007
 #define EFUSE_CHIP_VER_RESERVE_M  ((EFUSE_CHIP_VER_RESERVE_V)<<(EFUSE_CHIP_VER_RESERVE_S))
-#define EFUSE_CHIP_VER_RESERVE_V  0xFF
-#define EFUSE_CHIP_VER_RESERVE_S  9
+#define EFUSE_CHIP_VER_RESERVE_V  0x7
+#define EFUSE_CHIP_VER_RESERVE_S  12
+/* EFUSE_CHIP_VER : R/W ;bitpos:[11:9] ;default: 3'b0 ; */
+/*description: */
+#define EFUSE_CHIP_VER_PKG  0x00000007
+#define EFUSE_CHIP_VER_PKG_M  ((EFUSE_CHIP_VER_PKG_V)<<(EFUSE_CHIP_VER_PKG_S))
+#define EFUSE_CHIP_VER_PKG_V  0x7
+#define EFUSE_CHIP_VER_PKG_S  9
 /* EFUSE_SPI_PAD_CONFIG_HD : R/W ;bitpos:[8:4] ;default: 5'b0 ; */
 /*description: program for SPI_pad_config_hd*/
 #define EFUSE_SPI_PAD_CONFIG_HD  0x0000001F
diff --git a/tools/sdk/include/soc/soc/mcpwm_reg.h b/tools/sdk/include/soc/soc/mcpwm_reg.h
new file mode 100644
index 00000000..1dce94d4
--- /dev/null
+++ b/tools/sdk/include/soc/soc/mcpwm_reg.h
@@ -0,0 +1,3028 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_MCPWM_REG_H_
+#define _SOC_MCPWM_REG_H_
+#include "soc.h"
+
+#define REG_MCPWM_BASE(i)               (DR_REG_PWM_BASE + i * (0xE000))
+#define MCPWM_CLK_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x0000)
+/* MCPWM_CLK_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)*/
+#define MCPWM_CLK_PRESCALE  0x000000FF
+#define MCPWM_CLK_PRESCALE_M  ((MCPWM_CLK_PRESCALE_V)<<(MCPWM_CLK_PRESCALE_S))
+#define MCPWM_CLK_PRESCALE_V  0xFF
+#define MCPWM_CLK_PRESCALE_S  0
+
+#define MCPWM_TIMER0_CFG0_REG(i)          (REG_MCPWM_BASE(i) + 0x0004)
+/* MCPWM_TIMER0_PERIOD_UPMETHOD : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
+/*description: Update method for active reg of PWM timer0 period  0: immediate
+  1: TEZ  2: sync  3: TEZ or sync. TEZ here and below means timer equal zero event*/
+#define MCPWM_TIMER0_PERIOD_UPMETHOD  0x00000003
+#define MCPWM_TIMER0_PERIOD_UPMETHOD_M  ((MCPWM_TIMER0_PERIOD_UPMETHOD_V)<<(MCPWM_TIMER0_PERIOD_UPMETHOD_S))
+#define MCPWM_TIMER0_PERIOD_UPMETHOD_V  0x3
+#define MCPWM_TIMER0_PERIOD_UPMETHOD_S  24
+/* MCPWM_TIMER0_PERIOD : R/W ;bitpos:[23:8] ;default: 16'h00ff ; */
+/*description: Period shadow reg of PWM timer0*/
+#define MCPWM_TIMER0_PERIOD  0x0000FFFF
+#define MCPWM_TIMER0_PERIOD_M  ((MCPWM_TIMER0_PERIOD_V)<<(MCPWM_TIMER0_PERIOD_S))
+#define MCPWM_TIMER0_PERIOD_V  0xFFFF
+#define MCPWM_TIMER0_PERIOD_S  8
+/* MCPWM_TIMER0_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: Period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1)*/
+#define MCPWM_TIMER0_PRESCALE  0x000000FF
+#define MCPWM_TIMER0_PRESCALE_M  ((MCPWM_TIMER0_PRESCALE_V)<<(MCPWM_TIMER0_PRESCALE_S))
+#define MCPWM_TIMER0_PRESCALE_V  0xFF
+#define MCPWM_TIMER0_PRESCALE_S  0
+
+#define MCPWM_TIMER0_CFG1_REG(i)          (REG_MCPWM_BASE(i) + 0x0008)
+/* MCPWM_TIMER0_MOD : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: PWM timer0 working mode  0: freeze  1: increase mod  2: decrease
+ mod  3: up-down mod*/
+#define MCPWM_TIMER0_MOD  0x00000003
+#define MCPWM_TIMER0_MOD_M  ((MCPWM_TIMER0_MOD_V)<<(MCPWM_TIMER0_MOD_S))
+#define MCPWM_TIMER0_MOD_V  0x3
+#define MCPWM_TIMER0_MOD_S  3
+/* MCPWM_TIMER0_START : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: PWM timer0 start and stop control. 0: stop @ TEZ  1: stop @ TEP
+  2: free run  3: start and stop @ next TEZ  4: start and stop @ next TEP. TEP here and below means timer equal period event*/
+#define MCPWM_TIMER0_START  0x00000007
+#define MCPWM_TIMER0_START_M  ((MCPWM_TIMER0_START_V)<<(MCPWM_TIMER0_START_S))
+#define MCPWM_TIMER0_START_V  0x7
+#define MCPWM_TIMER0_START_S  0
+
+#define MCPWM_TIMER0_SYNC_REG(i)          (REG_MCPWM_BASE(i) + 0x000c)
+/* MCPWM_TIMER0_PHASE : R/W ;bitpos:[20:4] ;default: 17'd0 ; */
+/*description: Phase for timer reload on sync event*/
+#define MCPWM_TIMER0_PHASE  0x0001FFFF
+#define MCPWM_TIMER0_PHASE_M  ((MCPWM_TIMER0_PHASE_V)<<(MCPWM_TIMER0_PHASE_S))
+#define MCPWM_TIMER0_PHASE_V  0x1FFFF
+#define MCPWM_TIMER0_PHASE_S  4
+/* MCPWM_TIMER0_SYNCO_SEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
+/*description: PWM timer0 synco selection  0: synci  1: TEZ  2: TEP  else 0*/
+#define MCPWM_TIMER0_SYNCO_SEL  0x00000003
+#define MCPWM_TIMER0_SYNCO_SEL_M  ((MCPWM_TIMER0_SYNCO_SEL_V)<<(MCPWM_TIMER0_SYNCO_SEL_S))
+#define MCPWM_TIMER0_SYNCO_SEL_V  0x3
+#define MCPWM_TIMER0_SYNCO_SEL_S  2
+/* MCPWM_TIMER0_SYNC_SW : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: Toggling this bit will trigger a software sync*/
+#define MCPWM_TIMER0_SYNC_SW  (BIT(1))
+#define MCPWM_TIMER0_SYNC_SW_M  (BIT(1))
+#define MCPWM_TIMER0_SYNC_SW_V  0x1
+#define MCPWM_TIMER0_SYNC_SW_S  1
+/* MCPWM_TIMER0_SYNCI_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: When set   timer reload with phase on sync input event is enabled*/
+#define MCPWM_TIMER0_SYNCI_EN  (BIT(0))
+#define MCPWM_TIMER0_SYNCI_EN_M  (BIT(0))
+#define MCPWM_TIMER0_SYNCI_EN_V  0x1
+#define MCPWM_TIMER0_SYNCI_EN_S  0
+
+#define MCPWM_TIMER0_STATUS_REG(i)          (REG_MCPWM_BASE(i) + 0x0010)
+/* MCPWM_TIMER0_DIRECTION : RO ;bitpos:[16] ;default: 1'd0 ; */
+/*description: Current PWM timer0 counter direction  0: increment 1: decrement*/
+#define MCPWM_TIMER0_DIRECTION  (BIT(16))
+#define MCPWM_TIMER0_DIRECTION_M  (BIT(16))
+#define MCPWM_TIMER0_DIRECTION_V  0x1
+#define MCPWM_TIMER0_DIRECTION_S  16
+/* MCPWM_TIMER0_VALUE : RO ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: Current PWM timer0 counter value*/
+#define MCPWM_TIMER0_VALUE  0x0000FFFF
+#define MCPWM_TIMER0_VALUE_M  ((MCPWM_TIMER0_VALUE_V)<<(MCPWM_TIMER0_VALUE_S))
+#define MCPWM_TIMER0_VALUE_V  0xFFFF
+#define MCPWM_TIMER0_VALUE_S  0
+
+#define MCPWM_TIMER1_CFG0_REG(i)          (REG_MCPWM_BASE(i) + 0x0014)
+/* MCPWM_TIMER1_PERIOD_UPMETHOD : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
+/*description: Update method for active reg of PWM timer1 period  0: immediate
+  1: TEZ  2: sync  3: TEZ or sync*/
+#define MCPWM_TIMER1_PERIOD_UPMETHOD  0x00000003
+#define MCPWM_TIMER1_PERIOD_UPMETHOD_M  ((MCPWM_TIMER1_PERIOD_UPMETHOD_V)<<(MCPWM_TIMER1_PERIOD_UPMETHOD_S))
+#define MCPWM_TIMER1_PERIOD_UPMETHOD_V  0x3
+#define MCPWM_TIMER1_PERIOD_UPMETHOD_S  24
+/* MCPWM_TIMER1_PERIOD : R/W ;bitpos:[23:8] ;default: 16'h00ff ; */
+/*description: Period shadow reg of PWM timer1*/
+#define MCPWM_TIMER1_PERIOD  0x0000FFFF
+#define MCPWM_TIMER1_PERIOD_M  ((MCPWM_TIMER1_PERIOD_V)<<(MCPWM_TIMER1_PERIOD_S))
+#define MCPWM_TIMER1_PERIOD_V  0xFFFF
+#define MCPWM_TIMER1_PERIOD_S  8
+/* MCPWM_TIMER1_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: Period of PT1_clk = Period of PWM_clk * (PWM_TIMER1_PRESCALE + 1)*/
+#define MCPWM_TIMER1_PRESCALE  0x000000FF
+#define MCPWM_TIMER1_PRESCALE_M  ((MCPWM_TIMER1_PRESCALE_V)<<(MCPWM_TIMER1_PRESCALE_S))
+#define MCPWM_TIMER1_PRESCALE_V  0xFF
+#define MCPWM_TIMER1_PRESCALE_S  0
+
+#define MCPWM_TIMER1_CFG1_REG(i)          (REG_MCPWM_BASE(i) + 0x0018)
+/* MCPWM_TIMER1_MOD : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: PWM timer1 working mode  0: freeze  1: increase mod  2: decrease
+ mod  3: up-down mod*/
+#define MCPWM_TIMER1_MOD  0x00000003
+#define MCPWM_TIMER1_MOD_M  ((MCPWM_TIMER1_MOD_V)<<(MCPWM_TIMER1_MOD_S))
+#define MCPWM_TIMER1_MOD_V  0x3
+#define MCPWM_TIMER1_MOD_S  3
+/* MCPWM_TIMER1_START : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: PWM timer1 start and stop control. 0: stop @ TEZ  1: stop @ TEP
+  2: free run  3: start and stop @ next TEZ  4: start and stop @ next TEP.*/
+#define MCPWM_TIMER1_START  0x00000007
+#define MCPWM_TIMER1_START_M  ((MCPWM_TIMER1_START_V)<<(MCPWM_TIMER1_START_S))
+#define MCPWM_TIMER1_START_V  0x7
+#define MCPWM_TIMER1_START_S  0
+
+#define MCPWM_TIMER1_SYNC_REG(i)          (REG_MCPWM_BASE(i) + 0x001c)
+/* MCPWM_TIMER1_PHASE : R/W ;bitpos:[20:4] ;default: 17'd0 ; */
+/*description: Phase for timer reload on sync event*/
+#define MCPWM_TIMER1_PHASE  0x0001FFFF
+#define MCPWM_TIMER1_PHASE_M  ((MCPWM_TIMER1_PHASE_V)<<(MCPWM_TIMER1_PHASE_S))
+#define MCPWM_TIMER1_PHASE_V  0x1FFFF
+#define MCPWM_TIMER1_PHASE_S  4
+/* MCPWM_TIMER1_SYNCO_SEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
+/*description: PWM timer1 synco selection  0: synci  1: TEZ  2: TEP  else 0*/
+#define MCPWM_TIMER1_SYNCO_SEL  0x00000003
+#define MCPWM_TIMER1_SYNCO_SEL_M  ((MCPWM_TIMER1_SYNCO_SEL_V)<<(MCPWM_TIMER1_SYNCO_SEL_S))
+#define MCPWM_TIMER1_SYNCO_SEL_V  0x3
+#define MCPWM_TIMER1_SYNCO_SEL_S  2
+/* MCPWM_TIMER1_SYNC_SW : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: Toggling this bit will trigger a software sync*/
+#define MCPWM_TIMER1_SYNC_SW  (BIT(1))
+#define MCPWM_TIMER1_SYNC_SW_M  (BIT(1))
+#define MCPWM_TIMER1_SYNC_SW_V  0x1
+#define MCPWM_TIMER1_SYNC_SW_S  1
+/* MCPWM_TIMER1_SYNCI_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: When set   timer reload with phase on sync input event is enabled*/
+#define MCPWM_TIMER1_SYNCI_EN  (BIT(0))
+#define MCPWM_TIMER1_SYNCI_EN_M  (BIT(0))
+#define MCPWM_TIMER1_SYNCI_EN_V  0x1
+#define MCPWM_TIMER1_SYNCI_EN_S  0
+
+#define MCPWM_TIMER1_STATUS_REG(i)          (REG_MCPWM_BASE(i) + 0x0020)
+/* MCPWM_TIMER1_DIRECTION : RO ;bitpos:[16] ;default: 1'd0 ; */
+/*description: Current PWM timer1 counter direction  0: increment 1: decrement*/
+#define MCPWM_TIMER1_DIRECTION  (BIT(16))
+#define MCPWM_TIMER1_DIRECTION_M  (BIT(16))
+#define MCPWM_TIMER1_DIRECTION_V  0x1
+#define MCPWM_TIMER1_DIRECTION_S  16
+/* MCPWM_TIMER1_VALUE : RO ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: Current PWM timer1 counter value*/
+#define MCPWM_TIMER1_VALUE  0x0000FFFF
+#define MCPWM_TIMER1_VALUE_M  ((MCPWM_TIMER1_VALUE_V)<<(MCPWM_TIMER1_VALUE_S))
+#define MCPWM_TIMER1_VALUE_V  0xFFFF
+#define MCPWM_TIMER1_VALUE_S  0
+
+#define MCPWM_TIMER2_CFG0_REG(i)          (REG_MCPWM_BASE(i) + 0x0024)
+/* MCPWM_TIMER2_PERIOD_UPMETHOD : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
+/*description: Update method for active reg of PWM timer2 period  0: immediate
+  1: TEZ  2: sync  3: TEZ or sync*/
+#define MCPWM_TIMER2_PERIOD_UPMETHOD  0x00000003
+#define MCPWM_TIMER2_PERIOD_UPMETHOD_M  ((MCPWM_TIMER2_PERIOD_UPMETHOD_V)<<(MCPWM_TIMER2_PERIOD_UPMETHOD_S))
+#define MCPWM_TIMER2_PERIOD_UPMETHOD_V  0x3
+#define MCPWM_TIMER2_PERIOD_UPMETHOD_S  24
+/* MCPWM_TIMER2_PERIOD : R/W ;bitpos:[23:8] ;default: 16'h00ff ; */
+/*description: Period shadow reg of PWM timer2*/
+#define MCPWM_TIMER2_PERIOD  0x0000FFFF
+#define MCPWM_TIMER2_PERIOD_M  ((MCPWM_TIMER2_PERIOD_V)<<(MCPWM_TIMER2_PERIOD_S))
+#define MCPWM_TIMER2_PERIOD_V  0xFFFF
+#define MCPWM_TIMER2_PERIOD_S  8
+/* MCPWM_TIMER2_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: Period of PT2_clk = Period of PWM_clk * (PWM_TIMER2_PRESCALE + 1)*/
+#define MCPWM_TIMER2_PRESCALE  0x000000FF
+#define MCPWM_TIMER2_PRESCALE_M  ((MCPWM_TIMER2_PRESCALE_V)<<(MCPWM_TIMER2_PRESCALE_S))
+#define MCPWM_TIMER2_PRESCALE_V  0xFF
+#define MCPWM_TIMER2_PRESCALE_S  0
+
+#define MCPWM_TIMER2_CFG1_REG(i)          (REG_MCPWM_BASE(i) + 0x0028)
+/* MCPWM_TIMER2_MOD : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: PWM timer2 working mode  0: freeze  1: increase mod  2: decrease
+ mod  3: up-down mod*/
+#define MCPWM_TIMER2_MOD  0x00000003
+#define MCPWM_TIMER2_MOD_M  ((MCPWM_TIMER2_MOD_V)<<(MCPWM_TIMER2_MOD_S))
+#define MCPWM_TIMER2_MOD_V  0x3
+#define MCPWM_TIMER2_MOD_S  3
+/* MCPWM_TIMER2_START : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: PWM timer2 start and stop control. 0: stop @ TEZ  1: stop @ TEP
+  2: free run  3: start and stop @ next TEZ  4: start and stop @ next TEP.*/
+#define MCPWM_TIMER2_START  0x00000007
+#define MCPWM_TIMER2_START_M  ((MCPWM_TIMER2_START_V)<<(MCPWM_TIMER2_START_S))
+#define MCPWM_TIMER2_START_V  0x7
+#define MCPWM_TIMER2_START_S  0
+
+#define MCPWM_TIMER2_SYNC_REG(i)          (REG_MCPWM_BASE(i) + 0x002c)
+/* MCPWM_TIMER2_PHASE : R/W ;bitpos:[20:4] ;default: 17'd0 ; */
+/*description: Phase for timer reload on sync event*/
+#define MCPWM_TIMER2_PHASE  0x0001FFFF
+#define MCPWM_TIMER2_PHASE_M  ((MCPWM_TIMER2_PHASE_V)<<(MCPWM_TIMER2_PHASE_S))
+#define MCPWM_TIMER2_PHASE_V  0x1FFFF
+#define MCPWM_TIMER2_PHASE_S  4
+/* MCPWM_TIMER2_SYNCO_SEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
+/*description: PWM timer2 synco selection  0: synci  1: TEZ  2: TEP  else 0*/
+#define MCPWM_TIMER2_SYNCO_SEL  0x00000003
+#define MCPWM_TIMER2_SYNCO_SEL_M  ((MCPWM_TIMER2_SYNCO_SEL_V)<<(MCPWM_TIMER2_SYNCO_SEL_S))
+#define MCPWM_TIMER2_SYNCO_SEL_V  0x3
+#define MCPWM_TIMER2_SYNCO_SEL_S  2
+/* MCPWM_TIMER2_SYNC_SW : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: Toggling this bit will trigger a software sync*/
+#define MCPWM_TIMER2_SYNC_SW  (BIT(1))
+#define MCPWM_TIMER2_SYNC_SW_M  (BIT(1))
+#define MCPWM_TIMER2_SYNC_SW_V  0x1
+#define MCPWM_TIMER2_SYNC_SW_S  1
+/* MCPWM_TIMER2_SYNCI_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: When set   timer reload with phase on sync input event is enabled*/
+#define MCPWM_TIMER2_SYNCI_EN  (BIT(0))
+#define MCPWM_TIMER2_SYNCI_EN_M  (BIT(0))
+#define MCPWM_TIMER2_SYNCI_EN_V  0x1
+#define MCPWM_TIMER2_SYNCI_EN_S  0
+
+#define MCPWM_TIMER2_STATUS_REG(i)          (REG_MCPWM_BASE(i) + 0x0030)
+/* MCPWM_TIMER2_DIRECTION : RO ;bitpos:[16] ;default: 1'd0 ; */
+/*description: Current PWM timer2 counter direction  0: increment 1: decrement*/
+#define MCPWM_TIMER2_DIRECTION  (BIT(16))
+#define MCPWM_TIMER2_DIRECTION_M  (BIT(16))
+#define MCPWM_TIMER2_DIRECTION_V  0x1
+#define MCPWM_TIMER2_DIRECTION_S  16
+/* MCPWM_TIMER2_VALUE : RO ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: Current PWM timer2 counter value*/
+#define MCPWM_TIMER2_VALUE  0x0000FFFF
+#define MCPWM_TIMER2_VALUE_M  ((MCPWM_TIMER2_VALUE_V)<<(MCPWM_TIMER2_VALUE_S))
+#define MCPWM_TIMER2_VALUE_V  0xFFFF
+#define MCPWM_TIMER2_VALUE_S  0
+
+#define MCPWM_TIMER_SYNCI_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x0034)
+/* MCPWM_EXTERNAL_SYNCI2_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: Onvert SYNC2 from GPIO matrix*/
+#define MCPWM_EXTERNAL_SYNCI2_INVERT  (BIT(11))
+#define MCPWM_EXTERNAL_SYNCI2_INVERT_M  (BIT(11))
+#define MCPWM_EXTERNAL_SYNCI2_INVERT_V  0x1
+#define MCPWM_EXTERNAL_SYNCI2_INVERT_S  11
+/* MCPWM_EXTERNAL_SYNCI1_INVERT : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: Invert SYNC1 from GPIO matrix*/
+#define MCPWM_EXTERNAL_SYNCI1_INVERT  (BIT(10))
+#define MCPWM_EXTERNAL_SYNCI1_INVERT_M  (BIT(10))
+#define MCPWM_EXTERNAL_SYNCI1_INVERT_V  0x1
+#define MCPWM_EXTERNAL_SYNCI1_INVERT_S  10
+/* MCPWM_EXTERNAL_SYNCI0_INVERT : R/W ;bitpos:[9] ;default: 1'd0 ; */
+/*description: Invert SYNC0 from GPIO matrix*/
+#define MCPWM_EXTERNAL_SYNCI0_INVERT  (BIT(9))
+#define MCPWM_EXTERNAL_SYNCI0_INVERT_M  (BIT(9))
+#define MCPWM_EXTERNAL_SYNCI0_INVERT_V  0x1
+#define MCPWM_EXTERNAL_SYNCI0_INVERT_S  9
+/* MCPWM_TIMER2_SYNCISEL : R/W ;bitpos:[8:6] ;default: 3'd0 ; */
+/*description: Select sync input for PWM timer2  1: PWM timer0 synco  2: PWM
+ timer1 synco  3: PWM timer2 synco  4: SYNC0 from GPIO matrix  5: SYNC1 from GPIO matrix  6: SYNC2 from GPIO matrix  other values: no sync input selected*/
+#define MCPWM_TIMER2_SYNCISEL  0x00000007
+#define MCPWM_TIMER2_SYNCISEL_M  ((MCPWM_TIMER2_SYNCISEL_V)<<(MCPWM_TIMER2_SYNCISEL_S))
+#define MCPWM_TIMER2_SYNCISEL_V  0x7
+#define MCPWM_TIMER2_SYNCISEL_S  6
+/* MCPWM_TIMER1_SYNCISEL : R/W ;bitpos:[5:3] ;default: 3'd0 ; */
+/*description: Select sync input for PWM timer1  1: PWM timer0 synco  2: PWM
+ timer1 synco  3: PWM timer2 synco  4: SYNC0 from GPIO matrix  5: SYNC1 from GPIO matrix  6: SYNC2 from GPIO matrix  other values: no sync input selected*/
+#define MCPWM_TIMER1_SYNCISEL  0x00000007
+#define MCPWM_TIMER1_SYNCISEL_M  ((MCPWM_TIMER1_SYNCISEL_V)<<(MCPWM_TIMER1_SYNCISEL_S))
+#define MCPWM_TIMER1_SYNCISEL_V  0x7
+#define MCPWM_TIMER1_SYNCISEL_S  3
+/* MCPWM_TIMER0_SYNCISEL : R/W ;bitpos:[2:0] ;default: 3'd0 ; */
+/*description: Select sync input for PWM timer0  1: PWM timer0 synco  2: PWM
+ timer1 synco  3: PWM timer2 synco  4: SYNC0 from GPIO matrix  5: SYNC1 from GPIO matrix  6: SYNC2 from GPIO matrix  other values: no sync input selected*/
+#define MCPWM_TIMER0_SYNCISEL  0x00000007
+#define MCPWM_TIMER0_SYNCISEL_M  ((MCPWM_TIMER0_SYNCISEL_V)<<(MCPWM_TIMER0_SYNCISEL_S))
+#define MCPWM_TIMER0_SYNCISEL_V  0x7
+#define MCPWM_TIMER0_SYNCISEL_S  0
+
+#define MCPWM_OPERATOR_TIMERSEL_REG(i)          (REG_MCPWM_BASE(i) + 0x0038)
+/* MCPWM_OPERATOR2_TIMERSEL : R/W ;bitpos:[5:4] ;default: 2'd0 ; */
+/*description: Select which PWM timer's is the timing reference for PWM operator2
+  0: timer0  1: timer1  2: timer2*/
+#define MCPWM_OPERATOR2_TIMERSEL  0x00000003
+#define MCPWM_OPERATOR2_TIMERSEL_M  ((MCPWM_OPERATOR2_TIMERSEL_V)<<(MCPWM_OPERATOR2_TIMERSEL_S))
+#define MCPWM_OPERATOR2_TIMERSEL_V  0x3
+#define MCPWM_OPERATOR2_TIMERSEL_S  4
+/* MCPWM_OPERATOR1_TIMERSEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
+/*description: Select which PWM timer's is the timing reference for PWM operator1
+  0: timer0  1: timer1  2: timer2*/
+#define MCPWM_OPERATOR1_TIMERSEL  0x00000003
+#define MCPWM_OPERATOR1_TIMERSEL_M  ((MCPWM_OPERATOR1_TIMERSEL_V)<<(MCPWM_OPERATOR1_TIMERSEL_S))
+#define MCPWM_OPERATOR1_TIMERSEL_V  0x3
+#define MCPWM_OPERATOR1_TIMERSEL_S  2
+/* MCPWM_OPERATOR0_TIMERSEL : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: Select which PWM timer's is the timing reference for PWM operator0
+  0: timer0  1: timer1  2: timer2*/
+#define MCPWM_OPERATOR0_TIMERSEL  0x00000003
+#define MCPWM_OPERATOR0_TIMERSEL_M  ((MCPWM_OPERATOR0_TIMERSEL_V)<<(MCPWM_OPERATOR0_TIMERSEL_S))
+#define MCPWM_OPERATOR0_TIMERSEL_V  0x3
+#define MCPWM_OPERATOR0_TIMERSEL_S  0
+
+#define MCPWM_GEN0_STMP_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x003c)
+/* MCPWM_GEN0_B_SHDW_FULL : RO ;bitpos:[9] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  PWM generator 0 time stamp
+ B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared  B's active reg has been updated with shadow reg latest value*/
+#define MCPWM_GEN0_B_SHDW_FULL  (BIT(9))
+#define MCPWM_GEN0_B_SHDW_FULL_M  (BIT(9))
+#define MCPWM_GEN0_B_SHDW_FULL_V  0x1
+#define MCPWM_GEN0_B_SHDW_FULL_S  9
+/* MCPWM_GEN0_A_SHDW_FULL : RO ;bitpos:[8] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  PWM generator 0 time stamp
+ A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared  A's active reg has been updated with shadow reg latest value*/
+#define MCPWM_GEN0_A_SHDW_FULL  (BIT(8))
+#define MCPWM_GEN0_A_SHDW_FULL_M  (BIT(8))
+#define MCPWM_GEN0_A_SHDW_FULL_V  0x1
+#define MCPWM_GEN0_A_SHDW_FULL_S  8
+/* MCPWM_GEN0_B_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */
+/*description: Update method for PWM generator 0 time stamp B's active reg.
+ 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
+#define MCPWM_GEN0_B_UPMETHOD  0x0000000F
+#define MCPWM_GEN0_B_UPMETHOD_M  ((MCPWM_GEN0_B_UPMETHOD_V)<<(MCPWM_GEN0_B_UPMETHOD_S))
+#define MCPWM_GEN0_B_UPMETHOD_V  0xF
+#define MCPWM_GEN0_B_UPMETHOD_S  4
+/* MCPWM_GEN0_A_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: Update method for PWM generator 0 time stamp A's active reg.
+ 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
+#define MCPWM_GEN0_A_UPMETHOD  0x0000000F
+#define MCPWM_GEN0_A_UPMETHOD_M  ((MCPWM_GEN0_A_UPMETHOD_V)<<(MCPWM_GEN0_A_UPMETHOD_S))
+#define MCPWM_GEN0_A_UPMETHOD_V  0xF
+#define MCPWM_GEN0_A_UPMETHOD_S  0
+
+#define MCPWM_GEN0_TSTMP_A_REG(i)          (REG_MCPWM_BASE(i) + 0x0040)
+/* MCPWM_GEN0_A : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: PWM generator 0 time stamp A's shadow reg*/
+#define MCPWM_GEN0_A  0x0000FFFF
+#define MCPWM_GEN0_A_M  ((MCPWM_GEN0_A_V)<<(MCPWM_GEN0_A_S))
+#define MCPWM_GEN0_A_V  0xFFFF
+#define MCPWM_GEN0_A_S  0
+
+#define MCPWM_GEN0_TSTMP_B_REG(i)          (REG_MCPWM_BASE(i) + 0x0044)
+/* MCPWM_GEN0_B : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: PWM generator 0 time stamp B's shadow reg*/
+#define MCPWM_GEN0_B  0x0000FFFF
+#define MCPWM_GEN0_B_M  ((MCPWM_GEN0_B_V)<<(MCPWM_GEN0_B_S))
+#define MCPWM_GEN0_B_V  0xFFFF
+#define MCPWM_GEN0_B_S  0
+
+#define MCPWM_GEN0_CFG0_REG(i)          (REG_MCPWM_BASE(i) + 0x0048)
+/* MCPWM_GEN0_T1_SEL : R/W ;bitpos:[9:7] ;default: 3'd0 ; */
+/*description: Source selection for PWM generator 0 event_t1  take effect immediately
+  0: fault_event0  1: fault_event1  2: fault_event2  3: sync_taken  4: none*/
+#define MCPWM_GEN0_T1_SEL  0x00000007
+#define MCPWM_GEN0_T1_SEL_M  ((MCPWM_GEN0_T1_SEL_V)<<(MCPWM_GEN0_T1_SEL_S))
+#define MCPWM_GEN0_T1_SEL_V  0x7
+#define MCPWM_GEN0_T1_SEL_S  7
+/* MCPWM_GEN0_T0_SEL : R/W ;bitpos:[6:4] ;default: 3'd0 ; */
+/*description: Source selection for PWM generator 0 event_t0  take effect immediately
+  0: fault_event0  1: fault_event1  2: fault_event2  3: sync_taken  4: none*/
+#define MCPWM_GEN0_T0_SEL  0x00000007
+#define MCPWM_GEN0_T0_SEL_M  ((MCPWM_GEN0_T0_SEL_V)<<(MCPWM_GEN0_T0_SEL_S))
+#define MCPWM_GEN0_T0_SEL_V  0x7
+#define MCPWM_GEN0_T0_SEL_S  4
+/* MCPWM_GEN0_CFG_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: Update method for PWM generator 0's active reg of configuration.
+ 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync. bit3: disable update*/
+#define MCPWM_GEN0_CFG_UPMETHOD  0x0000000F
+#define MCPWM_GEN0_CFG_UPMETHOD_M  ((MCPWM_GEN0_CFG_UPMETHOD_V)<<(MCPWM_GEN0_CFG_UPMETHOD_S))
+#define MCPWM_GEN0_CFG_UPMETHOD_V  0xF
+#define MCPWM_GEN0_CFG_UPMETHOD_S  0
+
+#define MCPWM_GEN0_FORCE_REG(i)          (REG_MCPWM_BASE(i) + 0x004c)
+/* MCPWM_GEN0_B_NCIFORCE_MODE : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
+/*description: Non-continuous immediate software force mode for PWM0B  0: disabled
+  1: low  2: high  3: disabled*/
+#define MCPWM_GEN0_B_NCIFORCE_MODE  0x00000003
+#define MCPWM_GEN0_B_NCIFORCE_MODE_M  ((MCPWM_GEN0_B_NCIFORCE_MODE_V)<<(MCPWM_GEN0_B_NCIFORCE_MODE_S))
+#define MCPWM_GEN0_B_NCIFORCE_MODE_V  0x3
+#define MCPWM_GEN0_B_NCIFORCE_MODE_S  14
+/* MCPWM_GEN0_B_NCIFORCE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: Non-continuous immediate software force trigger for PWM0B  a
+ toggle will trigger a force event*/
+#define MCPWM_GEN0_B_NCIFORCE  (BIT(13))
+#define MCPWM_GEN0_B_NCIFORCE_M  (BIT(13))
+#define MCPWM_GEN0_B_NCIFORCE_V  0x1
+#define MCPWM_GEN0_B_NCIFORCE_S  13
+/* MCPWM_GEN0_A_NCIFORCE_MODE : R/W ;bitpos:[12:11] ;default: 2'd0 ; */
+/*description: Non-continuous immediate software force mode for PWM0A  0: disabled
+  1: low  2: high  3: disabled*/
+#define MCPWM_GEN0_A_NCIFORCE_MODE  0x00000003
+#define MCPWM_GEN0_A_NCIFORCE_MODE_M  ((MCPWM_GEN0_A_NCIFORCE_MODE_V)<<(MCPWM_GEN0_A_NCIFORCE_MODE_S))
+#define MCPWM_GEN0_A_NCIFORCE_MODE_V  0x3
+#define MCPWM_GEN0_A_NCIFORCE_MODE_S  11
+/* MCPWM_GEN0_A_NCIFORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: Non-continuous immediate software force trigger for PWM0A  a
+ toggle will trigger a force event*/
+#define MCPWM_GEN0_A_NCIFORCE  (BIT(10))
+#define MCPWM_GEN0_A_NCIFORCE_M  (BIT(10))
+#define MCPWM_GEN0_A_NCIFORCE_V  0x1
+#define MCPWM_GEN0_A_NCIFORCE_S  10
+/* MCPWM_GEN0_B_CNTUFORCE_MODE : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
+/*description: Continuous software force mode for PWM0B. 0: disabled  1: low
+  2: high  3: disabled*/
+#define MCPWM_GEN0_B_CNTUFORCE_MODE  0x00000003
+#define MCPWM_GEN0_B_CNTUFORCE_MODE_M  ((MCPWM_GEN0_B_CNTUFORCE_MODE_V)<<(MCPWM_GEN0_B_CNTUFORCE_MODE_S))
+#define MCPWM_GEN0_B_CNTUFORCE_MODE_V  0x3
+#define MCPWM_GEN0_B_CNTUFORCE_MODE_S  8
+/* MCPWM_GEN0_A_CNTUFORCE_MODE : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
+/*description: Continuous software force mode for PWM0A. 0: disabled  1: low
+  2: high  3: disabled*/
+#define MCPWM_GEN0_A_CNTUFORCE_MODE  0x00000003
+#define MCPWM_GEN0_A_CNTUFORCE_MODE_M  ((MCPWM_GEN0_A_CNTUFORCE_MODE_V)<<(MCPWM_GEN0_A_CNTUFORCE_MODE_S))
+#define MCPWM_GEN0_A_CNTUFORCE_MODE_V  0x3
+#define MCPWM_GEN0_A_CNTUFORCE_MODE_S  6
+/* MCPWM_GEN0_CNTUFORCE_UPMETHOD : R/W ;bitpos:[5:0] ;default: 6'h20 ; */
+/*description: Update method for continuous software force of PWM generator0.
+ 0: immediate  bit0: TEZ  bit1: TEP  bit2: TEA  bit3: TEB  bit4: sync  bit5: disable update. (TEA/B here and below means an event generated when timer value equals A/B register)*/
+#define MCPWM_GEN0_CNTUFORCE_UPMETHOD  0x0000003F
+#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_M  ((MCPWM_GEN0_CNTUFORCE_UPMETHOD_V)<<(MCPWM_GEN0_CNTUFORCE_UPMETHOD_S))
+#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_V  0x3F
+#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_S  0
+
+#define MCPWM_GEN0_A_REG(i)          (REG_MCPWM_BASE(i) + 0x0050)
+/* MCPWM_GEN0_A_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: Action on PWM0A triggered by event_t1 when timer decreasing.
+ 0: no change  1: low  2: high  3: toggle*/
+#define MCPWM_GEN0_A_DT1  0x00000003
+#define MCPWM_GEN0_A_DT1_M  ((MCPWM_GEN0_A_DT1_V)<<(MCPWM_GEN0_A_DT1_S))
+#define MCPWM_GEN0_A_DT1_V  0x3
+#define MCPWM_GEN0_A_DT1_S  22
+/* MCPWM_GEN0_A_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: Action on PWM0A triggered by event_t0 when timer decreasing*/
+#define MCPWM_GEN0_A_DT0  0x00000003
+#define MCPWM_GEN0_A_DT0_M  ((MCPWM_GEN0_A_DT0_V)<<(MCPWM_GEN0_A_DT0_S))
+#define MCPWM_GEN0_A_DT0_V  0x3
+#define MCPWM_GEN0_A_DT0_S  20
+/* MCPWM_GEN0_A_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: Action on PWM0A triggered by event TEB when timer decreasing*/
+#define MCPWM_GEN0_A_DTEB  0x00000003
+#define MCPWM_GEN0_A_DTEB_M  ((MCPWM_GEN0_A_DTEB_V)<<(MCPWM_GEN0_A_DTEB_S))
+#define MCPWM_GEN0_A_DTEB_V  0x3
+#define MCPWM_GEN0_A_DTEB_S  18
+/* MCPWM_GEN0_A_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: Action on PWM0A triggered by event TEA when timer decreasing*/
+#define MCPWM_GEN0_A_DTEA  0x00000003
+#define MCPWM_GEN0_A_DTEA_M  ((MCPWM_GEN0_A_DTEA_V)<<(MCPWM_GEN0_A_DTEA_S))
+#define MCPWM_GEN0_A_DTEA_V  0x3
+#define MCPWM_GEN0_A_DTEA_S  16
+/* MCPWM_GEN0_A_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
+/*description: Action on PWM0A triggered by event TEP when timer decreasing*/
+#define MCPWM_GEN0_A_DTEP  0x00000003
+#define MCPWM_GEN0_A_DTEP_M  ((MCPWM_GEN0_A_DTEP_V)<<(MCPWM_GEN0_A_DTEP_S))
+#define MCPWM_GEN0_A_DTEP_V  0x3
+#define MCPWM_GEN0_A_DTEP_S  14
+/* MCPWM_GEN0_A_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */
+/*description: Action on PWM0A triggered by event TEZ when timer decreasing*/
+#define MCPWM_GEN0_A_DTEZ  0x00000003
+#define MCPWM_GEN0_A_DTEZ_M  ((MCPWM_GEN0_A_DTEZ_V)<<(MCPWM_GEN0_A_DTEZ_S))
+#define MCPWM_GEN0_A_DTEZ_V  0x3
+#define MCPWM_GEN0_A_DTEZ_S  12
+/* MCPWM_GEN0_A_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
+/*description: Action on PWM0A triggered by event_t1 when timer increasing*/
+#define MCPWM_GEN0_A_UT1  0x00000003
+#define MCPWM_GEN0_A_UT1_M  ((MCPWM_GEN0_A_UT1_V)<<(MCPWM_GEN0_A_UT1_S))
+#define MCPWM_GEN0_A_UT1_V  0x3
+#define MCPWM_GEN0_A_UT1_S  10
+/* MCPWM_GEN0_A_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
+/*description: Action on PWM0A triggered by event_t0 when timer increasing*/
+#define MCPWM_GEN0_A_UT0  0x00000003
+#define MCPWM_GEN0_A_UT0_M  ((MCPWM_GEN0_A_UT0_V)<<(MCPWM_GEN0_A_UT0_S))
+#define MCPWM_GEN0_A_UT0_V  0x3
+#define MCPWM_GEN0_A_UT0_S  8
+/* MCPWM_GEN0_A_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
+/*description: Action on PWM0A triggered by event TEB when timer increasing*/
+#define MCPWM_GEN0_A_UTEB  0x00000003
+#define MCPWM_GEN0_A_UTEB_M  ((MCPWM_GEN0_A_UTEB_V)<<(MCPWM_GEN0_A_UTEB_S))
+#define MCPWM_GEN0_A_UTEB_V  0x3
+#define MCPWM_GEN0_A_UTEB_S  6
+/* MCPWM_GEN0_A_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */
+/*description: Action on PWM0A triggered by event TEA when timer increasing*/
+#define MCPWM_GEN0_A_UTEA  0x00000003
+#define MCPWM_GEN0_A_UTEA_M  ((MCPWM_GEN0_A_UTEA_V)<<(MCPWM_GEN0_A_UTEA_S))
+#define MCPWM_GEN0_A_UTEA_V  0x3
+#define MCPWM_GEN0_A_UTEA_S  4
+/* MCPWM_GEN0_A_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
+/*description: Action on PWM0A triggered by event TEP when timer increasing*/
+#define MCPWM_GEN0_A_UTEP  0x00000003
+#define MCPWM_GEN0_A_UTEP_M  ((MCPWM_GEN0_A_UTEP_V)<<(MCPWM_GEN0_A_UTEP_S))
+#define MCPWM_GEN0_A_UTEP_V  0x3
+#define MCPWM_GEN0_A_UTEP_S  2
+/* MCPWM_GEN0_A_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: Action on PWM0A triggered by event TEZ when timer increasing*/
+#define MCPWM_GEN0_A_UTEZ  0x00000003
+#define MCPWM_GEN0_A_UTEZ_M  ((MCPWM_GEN0_A_UTEZ_V)<<(MCPWM_GEN0_A_UTEZ_S))
+#define MCPWM_GEN0_A_UTEZ_V  0x3
+#define MCPWM_GEN0_A_UTEZ_S  0
+
+#define MCPWM_GEN0_B_REG(i)          (REG_MCPWM_BASE(i) + 0x0054)
+/* MCPWM_GEN0_B_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: Action on PWM0B triggered by event_t1 when timer decreasing.
+ 0: no change  1: low  2: high  3: toggle*/
+#define MCPWM_GEN0_B_DT1  0x00000003
+#define MCPWM_GEN0_B_DT1_M  ((MCPWM_GEN0_B_DT1_V)<<(MCPWM_GEN0_B_DT1_S))
+#define MCPWM_GEN0_B_DT1_V  0x3
+#define MCPWM_GEN0_B_DT1_S  22
+/* MCPWM_GEN0_B_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: Action on PWM0B triggered by event_t0 when timer decreasing*/
+#define MCPWM_GEN0_B_DT0  0x00000003
+#define MCPWM_GEN0_B_DT0_M  ((MCPWM_GEN0_B_DT0_V)<<(MCPWM_GEN0_B_DT0_S))
+#define MCPWM_GEN0_B_DT0_V  0x3
+#define MCPWM_GEN0_B_DT0_S  20
+/* MCPWM_GEN0_B_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: Action on PWM0B triggered by event TEB when timer decreasing*/
+#define MCPWM_GEN0_B_DTEB  0x00000003
+#define MCPWM_GEN0_B_DTEB_M  ((MCPWM_GEN0_B_DTEB_V)<<(MCPWM_GEN0_B_DTEB_S))
+#define MCPWM_GEN0_B_DTEB_V  0x3
+#define MCPWM_GEN0_B_DTEB_S  18
+/* MCPWM_GEN0_B_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: Action on PWM0B triggered by event TEA when timer decreasing*/
+#define MCPWM_GEN0_B_DTEA  0x00000003
+#define MCPWM_GEN0_B_DTEA_M  ((MCPWM_GEN0_B_DTEA_V)<<(MCPWM_GEN0_B_DTEA_S))
+#define MCPWM_GEN0_B_DTEA_V  0x3
+#define MCPWM_GEN0_B_DTEA_S  16
+/* MCPWM_GEN0_B_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
+/*description: Action on PWM0B triggered by event TEP when timer decreasing*/
+#define MCPWM_GEN0_B_DTEP  0x00000003
+#define MCPWM_GEN0_B_DTEP_M  ((MCPWM_GEN0_B_DTEP_V)<<(MCPWM_GEN0_B_DTEP_S))
+#define MCPWM_GEN0_B_DTEP_V  0x3
+#define MCPWM_GEN0_B_DTEP_S  14
+/* MCPWM_GEN0_B_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */
+/*description: Action on PWM0B triggered by event TEZ when timer decreasing*/
+#define MCPWM_GEN0_B_DTEZ  0x00000003
+#define MCPWM_GEN0_B_DTEZ_M  ((MCPWM_GEN0_B_DTEZ_V)<<(MCPWM_GEN0_B_DTEZ_S))
+#define MCPWM_GEN0_B_DTEZ_V  0x3
+#define MCPWM_GEN0_B_DTEZ_S  12
+/* MCPWM_GEN0_B_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
+/*description: Action on PWM0B triggered by event_t1 when timer increasing*/
+#define MCPWM_GEN0_B_UT1  0x00000003
+#define MCPWM_GEN0_B_UT1_M  ((MCPWM_GEN0_B_UT1_V)<<(MCPWM_GEN0_B_UT1_S))
+#define MCPWM_GEN0_B_UT1_V  0x3
+#define MCPWM_GEN0_B_UT1_S  10
+/* MCPWM_GEN0_B_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
+/*description: Action on PWM0B triggered by event_t0 when timer increasing*/
+#define MCPWM_GEN0_B_UT0  0x00000003
+#define MCPWM_GEN0_B_UT0_M  ((MCPWM_GEN0_B_UT0_V)<<(MCPWM_GEN0_B_UT0_S))
+#define MCPWM_GEN0_B_UT0_V  0x3
+#define MCPWM_GEN0_B_UT0_S  8
+/* MCPWM_GEN0_B_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
+/*description: Action on PWM0B triggered by event TEB when timer increasing*/
+#define MCPWM_GEN0_B_UTEB  0x00000003
+#define MCPWM_GEN0_B_UTEB_M  ((MCPWM_GEN0_B_UTEB_V)<<(MCPWM_GEN0_B_UTEB_S))
+#define MCPWM_GEN0_B_UTEB_V  0x3
+#define MCPWM_GEN0_B_UTEB_S  6
+/* MCPWM_GEN0_B_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */
+/*description: Action on PWM0B triggered by event TEA when timer increasing*/
+#define MCPWM_GEN0_B_UTEA  0x00000003
+#define MCPWM_GEN0_B_UTEA_M  ((MCPWM_GEN0_B_UTEA_V)<<(MCPWM_GEN0_B_UTEA_S))
+#define MCPWM_GEN0_B_UTEA_V  0x3
+#define MCPWM_GEN0_B_UTEA_S  4
+/* MCPWM_GEN0_B_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
+/*description: Action on PWM0B triggered by event TEP when timer increasing*/
+#define MCPWM_GEN0_B_UTEP  0x00000003
+#define MCPWM_GEN0_B_UTEP_M  ((MCPWM_GEN0_B_UTEP_V)<<(MCPWM_GEN0_B_UTEP_S))
+#define MCPWM_GEN0_B_UTEP_V  0x3
+#define MCPWM_GEN0_B_UTEP_S  2
+/* MCPWM_GEN0_B_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: Action on PWM0B triggered by event TEZ when timer increasing*/
+#define MCPWM_GEN0_B_UTEZ  0x00000003
+#define MCPWM_GEN0_B_UTEZ_M  ((MCPWM_GEN0_B_UTEZ_V)<<(MCPWM_GEN0_B_UTEZ_S))
+#define MCPWM_GEN0_B_UTEZ_V  0x3
+#define MCPWM_GEN0_B_UTEZ_S  0
+
+#define MCPWM_DT0_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x0058)
+/* MCPWM_DT0_CLK_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */
+/*description: Dead time generator 0 clock selection. 0: PWM_clk  1: PT_clk*/
+#define MCPWM_DT0_CLK_SEL  (BIT(17))
+#define MCPWM_DT0_CLK_SEL_M  (BIT(17))
+#define MCPWM_DT0_CLK_SEL_V  0x1
+#define MCPWM_DT0_CLK_SEL_S  17
+/* MCPWM_DT0_B_OUTBYPASS : R/W ;bitpos:[16] ;default: 1'd1 ; */
+/*description: S0 in documentation*/
+#define MCPWM_DT0_B_OUTBYPASS  (BIT(16))
+#define MCPWM_DT0_B_OUTBYPASS_M  (BIT(16))
+#define MCPWM_DT0_B_OUTBYPASS_V  0x1
+#define MCPWM_DT0_B_OUTBYPASS_S  16
+/* MCPWM_DT0_A_OUTBYPASS : R/W ;bitpos:[15] ;default: 1'd1 ; */
+/*description: S1 in documentation*/
+#define MCPWM_DT0_A_OUTBYPASS  (BIT(15))
+#define MCPWM_DT0_A_OUTBYPASS_M  (BIT(15))
+#define MCPWM_DT0_A_OUTBYPASS_V  0x1
+#define MCPWM_DT0_A_OUTBYPASS_S  15
+/* MCPWM_DT0_FED_OUTINVERT : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: S3 in documentation*/
+#define MCPWM_DT0_FED_OUTINVERT  (BIT(14))
+#define MCPWM_DT0_FED_OUTINVERT_M  (BIT(14))
+#define MCPWM_DT0_FED_OUTINVERT_V  0x1
+#define MCPWM_DT0_FED_OUTINVERT_S  14
+/* MCPWM_DT0_RED_OUTINVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: S2 in documentation*/
+#define MCPWM_DT0_RED_OUTINVERT  (BIT(13))
+#define MCPWM_DT0_RED_OUTINVERT_M  (BIT(13))
+#define MCPWM_DT0_RED_OUTINVERT_V  0x1
+#define MCPWM_DT0_RED_OUTINVERT_S  13
+/* MCPWM_DT0_FED_INSEL : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: S5 in documentation*/
+#define MCPWM_DT0_FED_INSEL  (BIT(12))
+#define MCPWM_DT0_FED_INSEL_M  (BIT(12))
+#define MCPWM_DT0_FED_INSEL_V  0x1
+#define MCPWM_DT0_FED_INSEL_S  12
+/* MCPWM_DT0_RED_INSEL : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: S4 in documentation*/
+#define MCPWM_DT0_RED_INSEL  (BIT(11))
+#define MCPWM_DT0_RED_INSEL_M  (BIT(11))
+#define MCPWM_DT0_RED_INSEL_V  0x1
+#define MCPWM_DT0_RED_INSEL_S  11
+/* MCPWM_DT0_B_OUTSWAP : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: S7 in documentation*/
+#define MCPWM_DT0_B_OUTSWAP  (BIT(10))
+#define MCPWM_DT0_B_OUTSWAP_M  (BIT(10))
+#define MCPWM_DT0_B_OUTSWAP_V  0x1
+#define MCPWM_DT0_B_OUTSWAP_S  10
+/* MCPWM_DT0_A_OUTSWAP : R/W ;bitpos:[9] ;default: 1'd0 ; */
+/*description: S6 in documentation*/
+#define MCPWM_DT0_A_OUTSWAP  (BIT(9))
+#define MCPWM_DT0_A_OUTSWAP_M  (BIT(9))
+#define MCPWM_DT0_A_OUTSWAP_V  0x1
+#define MCPWM_DT0_A_OUTSWAP_S  9
+/* MCPWM_DT0_DEB_MODE : R/W ;bitpos:[8] ;default: 1'd0 ; */
+/*description: S8 in documentation  dual-edge B mode  0: FED/RED take effect
+ on different path separately  1: FED/RED take effect on B path  A out is in bypass or normal operation mode*/
+#define MCPWM_DT0_DEB_MODE  (BIT(8))
+#define MCPWM_DT0_DEB_MODE_M  (BIT(8))
+#define MCPWM_DT0_DEB_MODE_V  0x1
+#define MCPWM_DT0_DEB_MODE_S  8
+/* MCPWM_DT0_RED_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */
+/*description: Update method for RED (rising edge delay) active reg. 0: immediate
+  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
+#define MCPWM_DT0_RED_UPMETHOD  0x0000000F
+#define MCPWM_DT0_RED_UPMETHOD_M  ((MCPWM_DT0_RED_UPMETHOD_V)<<(MCPWM_DT0_RED_UPMETHOD_S))
+#define MCPWM_DT0_RED_UPMETHOD_V  0xF
+#define MCPWM_DT0_RED_UPMETHOD_S  4
+/* MCPWM_DT0_FED_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: Update method for FED (falling edge delay) active reg. 0: immediate
+  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
+#define MCPWM_DT0_FED_UPMETHOD  0x0000000F
+#define MCPWM_DT0_FED_UPMETHOD_M  ((MCPWM_DT0_FED_UPMETHOD_V)<<(MCPWM_DT0_FED_UPMETHOD_S))
+#define MCPWM_DT0_FED_UPMETHOD_V  0xF
+#define MCPWM_DT0_FED_UPMETHOD_S  0
+
+#define MCPWM_DT0_FED_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x005c)
+/* MCPWM_DT0_FED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: Shadow reg for FED*/
+#define MCPWM_DT0_FED  0x0000FFFF
+#define MCPWM_DT0_FED_M  ((MCPWM_DT0_FED_V)<<(MCPWM_DT0_FED_S))
+#define MCPWM_DT0_FED_V  0xFFFF
+#define MCPWM_DT0_FED_S  0
+
+#define MCPWM_DT0_RED_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x0060)
+/* MCPWM_DT0_RED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: Shadow reg for RED*/
+#define MCPWM_DT0_RED  0x0000FFFF
+#define MCPWM_DT0_RED_M  ((MCPWM_DT0_RED_V)<<(MCPWM_DT0_RED_S))
+#define MCPWM_DT0_RED_V  0xFFFF
+#define MCPWM_DT0_RED_S  0
+
+#define MCPWM_CARRIER0_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x0064)
+/* MCPWM_CARRIER0_IN_INVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: When set  invert the input of PWM0A and PWM0B for this submodule*/
+#define MCPWM_CARRIER0_IN_INVERT  (BIT(13))
+#define MCPWM_CARRIER0_IN_INVERT_M  (BIT(13))
+#define MCPWM_CARRIER0_IN_INVERT_V  0x1
+#define MCPWM_CARRIER0_IN_INVERT_S  13
+/* MCPWM_CARRIER0_OUT_INVERT : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: When set  invert the output of PWM0A and PWM0B for this submodule*/
+#define MCPWM_CARRIER0_OUT_INVERT  (BIT(12))
+#define MCPWM_CARRIER0_OUT_INVERT_M  (BIT(12))
+#define MCPWM_CARRIER0_OUT_INVERT_V  0x1
+#define MCPWM_CARRIER0_OUT_INVERT_S  12
+/* MCPWM_CARRIER0_OSHWTH : R/W ;bitpos:[11:8] ;default: 4'd0 ; */
+/*description: Width of the fist pulse in number of periods of the carrier*/
+#define MCPWM_CARRIER0_OSHWTH  0x0000000F
+#define MCPWM_CARRIER0_OSHWTH_M  ((MCPWM_CARRIER0_OSHWTH_V)<<(MCPWM_CARRIER0_OSHWTH_S))
+#define MCPWM_CARRIER0_OSHWTH_V  0xF
+#define MCPWM_CARRIER0_OSHWTH_S  8
+/* MCPWM_CARRIER0_DUTY : R/W ;bitpos:[7:5] ;default: 3'd0 ; */
+/*description: Carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8*/
+#define MCPWM_CARRIER0_DUTY  0x00000007
+#define MCPWM_CARRIER0_DUTY_M  ((MCPWM_CARRIER0_DUTY_V)<<(MCPWM_CARRIER0_DUTY_S))
+#define MCPWM_CARRIER0_DUTY_V  0x7
+#define MCPWM_CARRIER0_DUTY_S  5
+/* MCPWM_CARRIER0_PRESCALE : R/W ;bitpos:[4:1] ;default: 4'd0 ; */
+/*description: PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk
+ = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)*/
+#define MCPWM_CARRIER0_PRESCALE  0x0000000F
+#define MCPWM_CARRIER0_PRESCALE_M  ((MCPWM_CARRIER0_PRESCALE_V)<<(MCPWM_CARRIER0_PRESCALE_S))
+#define MCPWM_CARRIER0_PRESCALE_V  0xF
+#define MCPWM_CARRIER0_PRESCALE_S  1
+/* MCPWM_CARRIER0_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: When set  carrier0 function is enabled. When cleared  carrier0 is bypassed*/
+#define MCPWM_CARRIER0_EN  (BIT(0))
+#define MCPWM_CARRIER0_EN_M  (BIT(0))
+#define MCPWM_CARRIER0_EN_V  0x1
+#define MCPWM_CARRIER0_EN_S  0
+
+#define MCPWM_FH0_CFG0_REG(i)          (REG_MCPWM_BASE(i) + 0x0068)
+/* MCPWM_FH0_B_OST_U : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: One-shot mode action on PWM0B when fault event occurs and timer
+ is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH0_B_OST_U  0x00000003
+#define MCPWM_FH0_B_OST_U_M  ((MCPWM_FH0_B_OST_U_V)<<(MCPWM_FH0_B_OST_U_S))
+#define MCPWM_FH0_B_OST_U_V  0x3
+#define MCPWM_FH0_B_OST_U_S  22
+/* MCPWM_FH0_B_OST_D : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: One-shot mode action on PWM0B when fault event occurs and timer
+ is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH0_B_OST_D  0x00000003
+#define MCPWM_FH0_B_OST_D_M  ((MCPWM_FH0_B_OST_D_V)<<(MCPWM_FH0_B_OST_D_S))
+#define MCPWM_FH0_B_OST_D_V  0x3
+#define MCPWM_FH0_B_OST_D_S  20
+/* MCPWM_FH0_B_CBC_U : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: Cycle-by-cycle mode action on PWM0B when fault event occurs and
+ timer is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH0_B_CBC_U  0x00000003
+#define MCPWM_FH0_B_CBC_U_M  ((MCPWM_FH0_B_CBC_U_V)<<(MCPWM_FH0_B_CBC_U_S))
+#define MCPWM_FH0_B_CBC_U_V  0x3
+#define MCPWM_FH0_B_CBC_U_S  18
+/* MCPWM_FH0_B_CBC_D : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: Cycle-by-cycle mode action on PWM0B when fault event occurs and
+ timer is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH0_B_CBC_D  0x00000003
+#define MCPWM_FH0_B_CBC_D_M  ((MCPWM_FH0_B_CBC_D_V)<<(MCPWM_FH0_B_CBC_D_S))
+#define MCPWM_FH0_B_CBC_D_V  0x3
+#define MCPWM_FH0_B_CBC_D_S  16
+/* MCPWM_FH0_A_OST_U : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
+/*description: One-shot mode action on PWM0A when fault event occurs and timer
+ is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH0_A_OST_U  0x00000003
+#define MCPWM_FH0_A_OST_U_M  ((MCPWM_FH0_A_OST_U_V)<<(MCPWM_FH0_A_OST_U_S))
+#define MCPWM_FH0_A_OST_U_V  0x3
+#define MCPWM_FH0_A_OST_U_S  14
+/* MCPWM_FH0_A_OST_D : R/W ;bitpos:[13:12] ;default: 2'd0 ; */
+/*description: One-shot mode action on PWM0A when fault event occurs and timer
+ is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH0_A_OST_D  0x00000003
+#define MCPWM_FH0_A_OST_D_M  ((MCPWM_FH0_A_OST_D_V)<<(MCPWM_FH0_A_OST_D_S))
+#define MCPWM_FH0_A_OST_D_V  0x3
+#define MCPWM_FH0_A_OST_D_S  12
+/* MCPWM_FH0_A_CBC_U : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
+/*description: Cycle-by-cycle mode action on PWM0A when fault event occurs and
+ timer is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH0_A_CBC_U  0x00000003
+#define MCPWM_FH0_A_CBC_U_M  ((MCPWM_FH0_A_CBC_U_V)<<(MCPWM_FH0_A_CBC_U_S))
+#define MCPWM_FH0_A_CBC_U_V  0x3
+#define MCPWM_FH0_A_CBC_U_S  10
+/* MCPWM_FH0_A_CBC_D : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
+/*description: Cycle-by-cycle mode action on PWM0A when fault event occurs and
+ timer is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH0_A_CBC_D  0x00000003
+#define MCPWM_FH0_A_CBC_D_M  ((MCPWM_FH0_A_CBC_D_V)<<(MCPWM_FH0_A_CBC_D_S))
+#define MCPWM_FH0_A_CBC_D_V  0x3
+#define MCPWM_FH0_A_CBC_D_S  8
+/* MCPWM_FH0_F0_OST : R/W ;bitpos:[7] ;default: 1'd0 ; */
+/*description: event_f0 will trigger one-shot mode action. 0: disable  1: enable*/
+#define MCPWM_FH0_F0_OST  (BIT(7))
+#define MCPWM_FH0_F0_OST_M  (BIT(7))
+#define MCPWM_FH0_F0_OST_V  0x1
+#define MCPWM_FH0_F0_OST_S  7
+/* MCPWM_FH0_F1_OST : R/W ;bitpos:[6] ;default: 1'd0 ; */
+/*description: event_f1 will trigger one-shot mode action. 0: disable  1: enable*/
+#define MCPWM_FH0_F1_OST  (BIT(6))
+#define MCPWM_FH0_F1_OST_M  (BIT(6))
+#define MCPWM_FH0_F1_OST_V  0x1
+#define MCPWM_FH0_F1_OST_S  6
+/* MCPWM_FH0_F2_OST : R/W ;bitpos:[5] ;default: 1'd0 ; */
+/*description: event_f2 will trigger one-shot mode action. 0: disable  1: enable*/
+#define MCPWM_FH0_F2_OST  (BIT(5))
+#define MCPWM_FH0_F2_OST_M  (BIT(5))
+#define MCPWM_FH0_F2_OST_V  0x1
+#define MCPWM_FH0_F2_OST_S  5
+/* MCPWM_FH0_SW_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */
+/*description: Enable register for software force one-shot mode action. 0: disable  1: enable*/
+#define MCPWM_FH0_SW_OST  (BIT(4))
+#define MCPWM_FH0_SW_OST_M  (BIT(4))
+#define MCPWM_FH0_SW_OST_V  0x1
+#define MCPWM_FH0_SW_OST_S  4
+/* MCPWM_FH0_F0_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */
+/*description: event_f0 will trigger cycle-by-cycle mode action. 0: disable  1: enable*/
+#define MCPWM_FH0_F0_CBC  (BIT(3))
+#define MCPWM_FH0_F0_CBC_M  (BIT(3))
+#define MCPWM_FH0_F0_CBC_V  0x1
+#define MCPWM_FH0_F0_CBC_S  3
+/* MCPWM_FH0_F1_CBC : R/W ;bitpos:[2] ;default: 1'd0 ; */
+/*description: event_f1 will trigger cycle-by-cycle mode action. 0: disable  1: enable*/
+#define MCPWM_FH0_F1_CBC  (BIT(2))
+#define MCPWM_FH0_F1_CBC_M  (BIT(2))
+#define MCPWM_FH0_F1_CBC_V  0x1
+#define MCPWM_FH0_F1_CBC_S  2
+/* MCPWM_FH0_F2_CBC : R/W ;bitpos:[1] ;default: 1'd0 ; */
+/*description: event_f2 will trigger cycle-by-cycle mode action. 0: disable  1: enable*/
+#define MCPWM_FH0_F2_CBC  (BIT(1))
+#define MCPWM_FH0_F2_CBC_M  (BIT(1))
+#define MCPWM_FH0_F2_CBC_V  0x1
+#define MCPWM_FH0_F2_CBC_S  1
+/* MCPWM_FH0_SW_CBC : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: Enable register for software force cycle-by-cycle mode action.
+ 0: disable  1: enable*/
+#define MCPWM_FH0_SW_CBC  (BIT(0))
+#define MCPWM_FH0_SW_CBC_M  (BIT(0))
+#define MCPWM_FH0_SW_CBC_V  0x1
+#define MCPWM_FH0_SW_CBC_S  0
+
+#define MCPWM_FH0_CFG1_REG(i)          (REG_MCPWM_BASE(i) + 0x006c)
+/* MCPWM_FH0_FORCE_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */
+/*description: A toggle (software negation of value of this bit) triggers a
+ one-shot mode action*/
+#define MCPWM_FH0_FORCE_OST  (BIT(4))
+#define MCPWM_FH0_FORCE_OST_M  (BIT(4))
+#define MCPWM_FH0_FORCE_OST_V  0x1
+#define MCPWM_FH0_FORCE_OST_S  4
+/* MCPWM_FH0_FORCE_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */
+/*description: A toggle triggers a cycle-by-cycle mode action*/
+#define MCPWM_FH0_FORCE_CBC  (BIT(3))
+#define MCPWM_FH0_FORCE_CBC_M  (BIT(3))
+#define MCPWM_FH0_FORCE_CBC_V  0x1
+#define MCPWM_FH0_FORCE_CBC_S  3
+/* MCPWM_FH0_CBCPULSE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */
+/*description: The cycle-by-cycle mode action refresh moment selection. Bit0: TEZ  bit1:TEP*/
+#define MCPWM_FH0_CBCPULSE  0x00000003
+#define MCPWM_FH0_CBCPULSE_M  ((MCPWM_FH0_CBCPULSE_V)<<(MCPWM_FH0_CBCPULSE_S))
+#define MCPWM_FH0_CBCPULSE_V  0x3
+#define MCPWM_FH0_CBCPULSE_S  1
+/* MCPWM_FH0_CLR_OST : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: A toggle will clear on going one-shot mode action*/
+#define MCPWM_FH0_CLR_OST  (BIT(0))
+#define MCPWM_FH0_CLR_OST_M  (BIT(0))
+#define MCPWM_FH0_CLR_OST_V  0x1
+#define MCPWM_FH0_CLR_OST_S  0
+
+#define MCPWM_FH0_STATUS_REG(i)          (REG_MCPWM_BASE(i) + 0x0070)
+/* MCPWM_FH0_OST_ON : RO ;bitpos:[1] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  an one-shot mode action is on going*/
+#define MCPWM_FH0_OST_ON  (BIT(1))
+#define MCPWM_FH0_OST_ON_M  (BIT(1))
+#define MCPWM_FH0_OST_ON_V  0x1
+#define MCPWM_FH0_OST_ON_S  1
+/* MCPWM_FH0_CBC_ON : RO ;bitpos:[0] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  an cycle-by-cycle mode action is on going*/
+#define MCPWM_FH0_CBC_ON  (BIT(0))
+#define MCPWM_FH0_CBC_ON_M  (BIT(0))
+#define MCPWM_FH0_CBC_ON_V  0x1
+#define MCPWM_FH0_CBC_ON_S  0
+
+#define MCPWM_GEN1_STMP_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x0074)
+/* MCPWM_GEN1_B_SHDW_FULL : RO ;bitpos:[9] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  PWM generator 1 time stamp
+ B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared  B's active reg has been updated with shadow reg latest value*/
+#define MCPWM_GEN1_B_SHDW_FULL  (BIT(9))
+#define MCPWM_GEN1_B_SHDW_FULL_M  (BIT(9))
+#define MCPWM_GEN1_B_SHDW_FULL_V  0x1
+#define MCPWM_GEN1_B_SHDW_FULL_S  9
+/* MCPWM_GEN1_A_SHDW_FULL : RO ;bitpos:[8] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  PWM generator 1 time stamp
+ A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared  A's active reg has been updated with shadow reg latest value*/
+#define MCPWM_GEN1_A_SHDW_FULL  (BIT(8))
+#define MCPWM_GEN1_A_SHDW_FULL_M  (BIT(8))
+#define MCPWM_GEN1_A_SHDW_FULL_V  0x1
+#define MCPWM_GEN1_A_SHDW_FULL_S  8
+/* MCPWM_GEN1_B_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */
+/*description: Update method for PWM generator 1 time stamp B's active reg.
+ 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
+#define MCPWM_GEN1_B_UPMETHOD  0x0000000F
+#define MCPWM_GEN1_B_UPMETHOD_M  ((MCPWM_GEN1_B_UPMETHOD_V)<<(MCPWM_GEN1_B_UPMETHOD_S))
+#define MCPWM_GEN1_B_UPMETHOD_V  0xF
+#define MCPWM_GEN1_B_UPMETHOD_S  4
+/* MCPWM_GEN1_A_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: Update method for PWM generator 1 time stamp A's active reg.
+ 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
+#define MCPWM_GEN1_A_UPMETHOD  0x0000000F
+#define MCPWM_GEN1_A_UPMETHOD_M  ((MCPWM_GEN1_A_UPMETHOD_V)<<(MCPWM_GEN1_A_UPMETHOD_S))
+#define MCPWM_GEN1_A_UPMETHOD_V  0xF
+#define MCPWM_GEN1_A_UPMETHOD_S  0
+
+#define MCPWM_GEN1_TSTMP_A_REG(i)          (REG_MCPWM_BASE(i) + 0x0078)
+/* MCPWM_GEN1_A : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: PWM generator 1 time stamp A's shadow reg*/
+#define MCPWM_GEN1_A  0x0000FFFF
+#define MCPWM_GEN1_A_M  ((MCPWM_GEN1_A_V)<<(MCPWM_GEN1_A_S))
+#define MCPWM_GEN1_A_V  0xFFFF
+#define MCPWM_GEN1_A_S  0
+
+#define MCPWM_GEN1_TSTMP_B_REG(i)          (REG_MCPWM_BASE(i) + 0x007c)
+/* MCPWM_GEN1_B : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: PWM generator 1 time stamp B's shadow reg*/
+#define MCPWM_GEN1_B  0x0000FFFF
+#define MCPWM_GEN1_B_M  ((MCPWM_GEN1_B_V)<<(MCPWM_GEN1_B_S))
+#define MCPWM_GEN1_B_V  0xFFFF
+#define MCPWM_GEN1_B_S  0
+
+#define MCPWM_GEN1_CFG0_REG(i)          (REG_MCPWM_BASE(i) + 0x0080)
+/* MCPWM_GEN1_T1_SEL : R/W ;bitpos:[9:7] ;default: 3'd0 ; */
+/*description: Source selection for PWM generate1 event_t1  take effect immediately
+  0: fault_event0  1: fault_event1  2: fault_event2  3: sync_taken  4: none*/
+#define MCPWM_GEN1_T1_SEL  0x00000007
+#define MCPWM_GEN1_T1_SEL_M  ((MCPWM_GEN1_T1_SEL_V)<<(MCPWM_GEN1_T1_SEL_S))
+#define MCPWM_GEN1_T1_SEL_V  0x7
+#define MCPWM_GEN1_T1_SEL_S  7
+/* MCPWM_GEN1_T0_SEL : R/W ;bitpos:[6:4] ;default: 3'd0 ; */
+/*description: Source selection for PWM generate1 event_t0  take effect immediately
+  0: fault_event0  1: fault_event1  2: fault_event2  3: sync_taken  4: none*/
+#define MCPWM_GEN1_T0_SEL  0x00000007
+#define MCPWM_GEN1_T0_SEL_M  ((MCPWM_GEN1_T0_SEL_V)<<(MCPWM_GEN1_T0_SEL_S))
+#define MCPWM_GEN1_T0_SEL_V  0x7
+#define MCPWM_GEN1_T0_SEL_S  4
+/* MCPWM_GEN1_CFG_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: Update method for PWM generate1's active reg of configuration.
+ 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync. bit3: disable update*/
+#define MCPWM_GEN1_CFG_UPMETHOD  0x0000000F
+#define MCPWM_GEN1_CFG_UPMETHOD_M  ((MCPWM_GEN1_CFG_UPMETHOD_V)<<(MCPWM_GEN1_CFG_UPMETHOD_S))
+#define MCPWM_GEN1_CFG_UPMETHOD_V  0xF
+#define MCPWM_GEN1_CFG_UPMETHOD_S  0
+
+#define MCPWM_GEN1_FORCE_REG(i)          (REG_MCPWM_BASE(i) + 0x0084)
+/* MCPWM_GEN1_B_NCIFORCE_MODE : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
+/*description: Non-continuous immediate software force mode for PWM1B  0: disabled
+  1: low  2: high  3: disabled*/
+#define MCPWM_GEN1_B_NCIFORCE_MODE  0x00000003
+#define MCPWM_GEN1_B_NCIFORCE_MODE_M  ((MCPWM_GEN1_B_NCIFORCE_MODE_V)<<(MCPWM_GEN1_B_NCIFORCE_MODE_S))
+#define MCPWM_GEN1_B_NCIFORCE_MODE_V  0x3
+#define MCPWM_GEN1_B_NCIFORCE_MODE_S  14
+/* MCPWM_GEN1_B_NCIFORCE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: Non-continuous immediate software force trigger for PWM1B  a
+ toggle will trigger a force event*/
+#define MCPWM_GEN1_B_NCIFORCE  (BIT(13))
+#define MCPWM_GEN1_B_NCIFORCE_M  (BIT(13))
+#define MCPWM_GEN1_B_NCIFORCE_V  0x1
+#define MCPWM_GEN1_B_NCIFORCE_S  13
+/* MCPWM_GEN1_A_NCIFORCE_MODE : R/W ;bitpos:[12:11] ;default: 2'd0 ; */
+/*description: Non-continuous immediate software force mode for PWM1A  0: disabled
+  1: low  2: high  3: disabled*/
+#define MCPWM_GEN1_A_NCIFORCE_MODE  0x00000003
+#define MCPWM_GEN1_A_NCIFORCE_MODE_M  ((MCPWM_GEN1_A_NCIFORCE_MODE_V)<<(MCPWM_GEN1_A_NCIFORCE_MODE_S))
+#define MCPWM_GEN1_A_NCIFORCE_MODE_V  0x3
+#define MCPWM_GEN1_A_NCIFORCE_MODE_S  11
+/* MCPWM_GEN1_A_NCIFORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: Non-continuous immediate software force trigger for PWM1A  a
+ toggle will trigger a force event*/
+#define MCPWM_GEN1_A_NCIFORCE  (BIT(10))
+#define MCPWM_GEN1_A_NCIFORCE_M  (BIT(10))
+#define MCPWM_GEN1_A_NCIFORCE_V  0x1
+#define MCPWM_GEN1_A_NCIFORCE_S  10
+/* MCPWM_GEN1_B_CNTUFORCE_MODE : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
+/*description: Continuous software force mode for PWM1B. 0: disabled  1: low
+  2: high  3: disabled*/
+#define MCPWM_GEN1_B_CNTUFORCE_MODE  0x00000003
+#define MCPWM_GEN1_B_CNTUFORCE_MODE_M  ((MCPWM_GEN1_B_CNTUFORCE_MODE_V)<<(MCPWM_GEN1_B_CNTUFORCE_MODE_S))
+#define MCPWM_GEN1_B_CNTUFORCE_MODE_V  0x3
+#define MCPWM_GEN1_B_CNTUFORCE_MODE_S  8
+/* MCPWM_GEN1_A_CNTUFORCE_MODE : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
+/*description: Continuous software force mode for PWM1A. 0: disabled  1: low
+  2: high  3: disabled*/
+#define MCPWM_GEN1_A_CNTUFORCE_MODE  0x00000003
+#define MCPWM_GEN1_A_CNTUFORCE_MODE_M  ((MCPWM_GEN1_A_CNTUFORCE_MODE_V)<<(MCPWM_GEN1_A_CNTUFORCE_MODE_S))
+#define MCPWM_GEN1_A_CNTUFORCE_MODE_V  0x3
+#define MCPWM_GEN1_A_CNTUFORCE_MODE_S  6
+/* MCPWM_GEN1_CNTUFORCE_UPMETHOD : R/W ;bitpos:[5:0] ;default: 6'h20 ; */
+/*description: Update method for continuous software force of PWM generator1.
+ 0: immediate  bit0: TEZ  bit1: TEP  bit2: TEA  bit3: TEB  bit4: sync  bit5: disable update. (TEA/B here and below means an event generated when timer value equals A/B register)*/
+#define MCPWM_GEN1_CNTUFORCE_UPMETHOD  0x0000003F
+#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_M  ((MCPWM_GEN1_CNTUFORCE_UPMETHOD_V)<<(MCPWM_GEN1_CNTUFORCE_UPMETHOD_S))
+#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_V  0x3F
+#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_S  0
+
+#define MCPWM_GEN1_A_REG(i)          (REG_MCPWM_BASE(i) + 0x0088)
+/* MCPWM_GEN1_A_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: Action on PWM1A triggered by event_t1 when timer decreasing.
+ 0: no change  1: low  2: high  3: toggle*/
+#define MCPWM_GEN1_A_DT1  0x00000003
+#define MCPWM_GEN1_A_DT1_M  ((MCPWM_GEN1_A_DT1_V)<<(MCPWM_GEN1_A_DT1_S))
+#define MCPWM_GEN1_A_DT1_V  0x3
+#define MCPWM_GEN1_A_DT1_S  22
+/* MCPWM_GEN1_A_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: Action on PWM1A triggered by event_t0 when timer decreasing*/
+#define MCPWM_GEN1_A_DT0  0x00000003
+#define MCPWM_GEN1_A_DT0_M  ((MCPWM_GEN1_A_DT0_V)<<(MCPWM_GEN1_A_DT0_S))
+#define MCPWM_GEN1_A_DT0_V  0x3
+#define MCPWM_GEN1_A_DT0_S  20
+/* MCPWM_GEN1_A_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: Action on PWM1A triggered by event TEB when timer decreasing*/
+#define MCPWM_GEN1_A_DTEB  0x00000003
+#define MCPWM_GEN1_A_DTEB_M  ((MCPWM_GEN1_A_DTEB_V)<<(MCPWM_GEN1_A_DTEB_S))
+#define MCPWM_GEN1_A_DTEB_V  0x3
+#define MCPWM_GEN1_A_DTEB_S  18
+/* MCPWM_GEN1_A_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: Action on PWM1A triggered by event TEA when timer decreasing*/
+#define MCPWM_GEN1_A_DTEA  0x00000003
+#define MCPWM_GEN1_A_DTEA_M  ((MCPWM_GEN1_A_DTEA_V)<<(MCPWM_GEN1_A_DTEA_S))
+#define MCPWM_GEN1_A_DTEA_V  0x3
+#define MCPWM_GEN1_A_DTEA_S  16
+/* MCPWM_GEN1_A_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
+/*description: Action on PWM1A triggered by event TEP when timer decreasing*/
+#define MCPWM_GEN1_A_DTEP  0x00000003
+#define MCPWM_GEN1_A_DTEP_M  ((MCPWM_GEN1_A_DTEP_V)<<(MCPWM_GEN1_A_DTEP_S))
+#define MCPWM_GEN1_A_DTEP_V  0x3
+#define MCPWM_GEN1_A_DTEP_S  14
+/* MCPWM_GEN1_A_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */
+/*description: Action on PWM1A triggered by event TEZ when timer decreasing*/
+#define MCPWM_GEN1_A_DTEZ  0x00000003
+#define MCPWM_GEN1_A_DTEZ_M  ((MCPWM_GEN1_A_DTEZ_V)<<(MCPWM_GEN1_A_DTEZ_S))
+#define MCPWM_GEN1_A_DTEZ_V  0x3
+#define MCPWM_GEN1_A_DTEZ_S  12
+/* MCPWM_GEN1_A_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
+/*description: Action on PWM1A triggered by event_t1 when timer increasing*/
+#define MCPWM_GEN1_A_UT1  0x00000003
+#define MCPWM_GEN1_A_UT1_M  ((MCPWM_GEN1_A_UT1_V)<<(MCPWM_GEN1_A_UT1_S))
+#define MCPWM_GEN1_A_UT1_V  0x3
+#define MCPWM_GEN1_A_UT1_S  10
+/* MCPWM_GEN1_A_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
+/*description: Action on PWM1A triggered by event_t0 when timer increasing*/
+#define MCPWM_GEN1_A_UT0  0x00000003
+#define MCPWM_GEN1_A_UT0_M  ((MCPWM_GEN1_A_UT0_V)<<(MCPWM_GEN1_A_UT0_S))
+#define MCPWM_GEN1_A_UT0_V  0x3
+#define MCPWM_GEN1_A_UT0_S  8
+/* MCPWM_GEN1_A_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
+/*description: Action on PWM1A triggered by event TEB when timer increasing*/
+#define MCPWM_GEN1_A_UTEB  0x00000003
+#define MCPWM_GEN1_A_UTEB_M  ((MCPWM_GEN1_A_UTEB_V)<<(MCPWM_GEN1_A_UTEB_S))
+#define MCPWM_GEN1_A_UTEB_V  0x3
+#define MCPWM_GEN1_A_UTEB_S  6
+/* MCPWM_GEN1_A_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */
+/*description: Action on PWM1A triggered by event TEA when timer increasing*/
+#define MCPWM_GEN1_A_UTEA  0x00000003
+#define MCPWM_GEN1_A_UTEA_M  ((MCPWM_GEN1_A_UTEA_V)<<(MCPWM_GEN1_A_UTEA_S))
+#define MCPWM_GEN1_A_UTEA_V  0x3
+#define MCPWM_GEN1_A_UTEA_S  4
+/* MCPWM_GEN1_A_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
+/*description: Action on PWM1A triggered by event TEP when timer increasing*/
+#define MCPWM_GEN1_A_UTEP  0x00000003
+#define MCPWM_GEN1_A_UTEP_M  ((MCPWM_GEN1_A_UTEP_V)<<(MCPWM_GEN1_A_UTEP_S))
+#define MCPWM_GEN1_A_UTEP_V  0x3
+#define MCPWM_GEN1_A_UTEP_S  2
+/* MCPWM_GEN1_A_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: Action on PWM1A triggered by event TEZ when timer increasing*/
+#define MCPWM_GEN1_A_UTEZ  0x00000003
+#define MCPWM_GEN1_A_UTEZ_M  ((MCPWM_GEN1_A_UTEZ_V)<<(MCPWM_GEN1_A_UTEZ_S))
+#define MCPWM_GEN1_A_UTEZ_V  0x3
+#define MCPWM_GEN1_A_UTEZ_S  0
+
+#define MCPWM_GEN1_B_REG(i)          (REG_MCPWM_BASE(i) + 0x008c)
+/* MCPWM_GEN1_B_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: Action on PWM1B triggered by event_t1 when timer decreasing.
+ 0: no change  1: low  2: high  3: toggle*/
+#define MCPWM_GEN1_B_DT1  0x00000003
+#define MCPWM_GEN1_B_DT1_M  ((MCPWM_GEN1_B_DT1_V)<<(MCPWM_GEN1_B_DT1_S))
+#define MCPWM_GEN1_B_DT1_V  0x3
+#define MCPWM_GEN1_B_DT1_S  22
+/* MCPWM_GEN1_B_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: Action on PWM1B triggered by event_t0 when timer decreasing*/
+#define MCPWM_GEN1_B_DT0  0x00000003
+#define MCPWM_GEN1_B_DT0_M  ((MCPWM_GEN1_B_DT0_V)<<(MCPWM_GEN1_B_DT0_S))
+#define MCPWM_GEN1_B_DT0_V  0x3
+#define MCPWM_GEN1_B_DT0_S  20
+/* MCPWM_GEN1_B_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: Action on PWM1B triggered by event TEB when timer decreasing*/
+#define MCPWM_GEN1_B_DTEB  0x00000003
+#define MCPWM_GEN1_B_DTEB_M  ((MCPWM_GEN1_B_DTEB_V)<<(MCPWM_GEN1_B_DTEB_S))
+#define MCPWM_GEN1_B_DTEB_V  0x3
+#define MCPWM_GEN1_B_DTEB_S  18
+/* MCPWM_GEN1_B_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: Action on PWM1B triggered by event TEA when timer decreasing*/
+#define MCPWM_GEN1_B_DTEA  0x00000003
+#define MCPWM_GEN1_B_DTEA_M  ((MCPWM_GEN1_B_DTEA_V)<<(MCPWM_GEN1_B_DTEA_S))
+#define MCPWM_GEN1_B_DTEA_V  0x3
+#define MCPWM_GEN1_B_DTEA_S  16
+/* MCPWM_GEN1_B_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
+/*description: Action on PWM1B triggered by event TEP when timer decreasing*/
+#define MCPWM_GEN1_B_DTEP  0x00000003
+#define MCPWM_GEN1_B_DTEP_M  ((MCPWM_GEN1_B_DTEP_V)<<(MCPWM_GEN1_B_DTEP_S))
+#define MCPWM_GEN1_B_DTEP_V  0x3
+#define MCPWM_GEN1_B_DTEP_S  14
+/* MCPWM_GEN1_B_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */
+/*description: Action on PWM1B triggered by event TEZ when timer decreasing*/
+#define MCPWM_GEN1_B_DTEZ  0x00000003
+#define MCPWM_GEN1_B_DTEZ_M  ((MCPWM_GEN1_B_DTEZ_V)<<(MCPWM_GEN1_B_DTEZ_S))
+#define MCPWM_GEN1_B_DTEZ_V  0x3
+#define MCPWM_GEN1_B_DTEZ_S  12
+/* MCPWM_GEN1_B_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
+/*description: Action on PWM1B triggered by event_t1 when timer increasing*/
+#define MCPWM_GEN1_B_UT1  0x00000003
+#define MCPWM_GEN1_B_UT1_M  ((MCPWM_GEN1_B_UT1_V)<<(MCPWM_GEN1_B_UT1_S))
+#define MCPWM_GEN1_B_UT1_V  0x3
+#define MCPWM_GEN1_B_UT1_S  10
+/* MCPWM_GEN1_B_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
+/*description: Action on PWM1B triggered by event_t0 when timer increasing*/
+#define MCPWM_GEN1_B_UT0  0x00000003
+#define MCPWM_GEN1_B_UT0_M  ((MCPWM_GEN1_B_UT0_V)<<(MCPWM_GEN1_B_UT0_S))
+#define MCPWM_GEN1_B_UT0_V  0x3
+#define MCPWM_GEN1_B_UT0_S  8
+/* MCPWM_GEN1_B_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
+/*description: Action on PWM1B triggered by event TEB when timer increasing*/
+#define MCPWM_GEN1_B_UTEB  0x00000003
+#define MCPWM_GEN1_B_UTEB_M  ((MCPWM_GEN1_B_UTEB_V)<<(MCPWM_GEN1_B_UTEB_S))
+#define MCPWM_GEN1_B_UTEB_V  0x3
+#define MCPWM_GEN1_B_UTEB_S  6
+/* MCPWM_GEN1_B_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */
+/*description: Action on PWM1B triggered by event TEA when timer increasing*/
+#define MCPWM_GEN1_B_UTEA  0x00000003
+#define MCPWM_GEN1_B_UTEA_M  ((MCPWM_GEN1_B_UTEA_V)<<(MCPWM_GEN1_B_UTEA_S))
+#define MCPWM_GEN1_B_UTEA_V  0x3
+#define MCPWM_GEN1_B_UTEA_S  4
+/* MCPWM_GEN1_B_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
+/*description: Action on PWM1B triggered by event TEP when timer increasing*/
+#define MCPWM_GEN1_B_UTEP  0x00000003
+#define MCPWM_GEN1_B_UTEP_M  ((MCPWM_GEN1_B_UTEP_V)<<(MCPWM_GEN1_B_UTEP_S))
+#define MCPWM_GEN1_B_UTEP_V  0x3
+#define MCPWM_GEN1_B_UTEP_S  2
+/* MCPWM_GEN1_B_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: Action on PWM1B triggered by event TEZ when timer increasing*/
+#define MCPWM_GEN1_B_UTEZ  0x00000003
+#define MCPWM_GEN1_B_UTEZ_M  ((MCPWM_GEN1_B_UTEZ_V)<<(MCPWM_GEN1_B_UTEZ_S))
+#define MCPWM_GEN1_B_UTEZ_V  0x3
+#define MCPWM_GEN1_B_UTEZ_S  0
+
+#define MCPWM_DT1_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x0090)
+/* MCPWM_DT1_CLK_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */
+/*description: Dead time generator 1 clock selection. 0: PWM_clk  1: PT_clk*/
+#define MCPWM_DT1_CLK_SEL  (BIT(17))
+#define MCPWM_DT1_CLK_SEL_M  (BIT(17))
+#define MCPWM_DT1_CLK_SEL_V  0x1
+#define MCPWM_DT1_CLK_SEL_S  17
+/* MCPWM_DT1_B_OUTBYPASS : R/W ;bitpos:[16] ;default: 1'd1 ; */
+/*description: S0 in documentation*/
+#define MCPWM_DT1_B_OUTBYPASS  (BIT(16))
+#define MCPWM_DT1_B_OUTBYPASS_M  (BIT(16))
+#define MCPWM_DT1_B_OUTBYPASS_V  0x1
+#define MCPWM_DT1_B_OUTBYPASS_S  16
+/* MCPWM_DT1_A_OUTBYPASS : R/W ;bitpos:[15] ;default: 1'd1 ; */
+/*description: S1 in documentation*/
+#define MCPWM_DT1_A_OUTBYPASS  (BIT(15))
+#define MCPWM_DT1_A_OUTBYPASS_M  (BIT(15))
+#define MCPWM_DT1_A_OUTBYPASS_V  0x1
+#define MCPWM_DT1_A_OUTBYPASS_S  15
+/* MCPWM_DT1_FED_OUTINVERT : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: S3 in documentation*/
+#define MCPWM_DT1_FED_OUTINVERT  (BIT(14))
+#define MCPWM_DT1_FED_OUTINVERT_M  (BIT(14))
+#define MCPWM_DT1_FED_OUTINVERT_V  0x1
+#define MCPWM_DT1_FED_OUTINVERT_S  14
+/* MCPWM_DT1_RED_OUTINVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: S2 in documentation*/
+#define MCPWM_DT1_RED_OUTINVERT  (BIT(13))
+#define MCPWM_DT1_RED_OUTINVERT_M  (BIT(13))
+#define MCPWM_DT1_RED_OUTINVERT_V  0x1
+#define MCPWM_DT1_RED_OUTINVERT_S  13
+/* MCPWM_DT1_FED_INSEL : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: S5 in documentation*/
+#define MCPWM_DT1_FED_INSEL  (BIT(12))
+#define MCPWM_DT1_FED_INSEL_M  (BIT(12))
+#define MCPWM_DT1_FED_INSEL_V  0x1
+#define MCPWM_DT1_FED_INSEL_S  12
+/* MCPWM_DT1_RED_INSEL : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: S4 in documentation*/
+#define MCPWM_DT1_RED_INSEL  (BIT(11))
+#define MCPWM_DT1_RED_INSEL_M  (BIT(11))
+#define MCPWM_DT1_RED_INSEL_V  0x1
+#define MCPWM_DT1_RED_INSEL_S  11
+/* MCPWM_DT1_B_OUTSWAP : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: S7 in documentation*/
+#define MCPWM_DT1_B_OUTSWAP  (BIT(10))
+#define MCPWM_DT1_B_OUTSWAP_M  (BIT(10))
+#define MCPWM_DT1_B_OUTSWAP_V  0x1
+#define MCPWM_DT1_B_OUTSWAP_S  10
+/* MCPWM_DT1_A_OUTSWAP : R/W ;bitpos:[9] ;default: 1'd0 ; */
+/*description: S6 in documentation*/
+#define MCPWM_DT1_A_OUTSWAP  (BIT(9))
+#define MCPWM_DT1_A_OUTSWAP_M  (BIT(9))
+#define MCPWM_DT1_A_OUTSWAP_V  0x1
+#define MCPWM_DT1_A_OUTSWAP_S  9
+/* MCPWM_DT1_DEB_MODE : R/W ;bitpos:[8] ;default: 1'd0 ; */
+/*description: S8 in documentation  dual-edge B mode  0: FED/RED take effect
+ on different path separately  1: FED/RED take effect on B path  A out is in bypass or normal operation mode*/
+#define MCPWM_DT1_DEB_MODE  (BIT(8))
+#define MCPWM_DT1_DEB_MODE_M  (BIT(8))
+#define MCPWM_DT1_DEB_MODE_V  0x1
+#define MCPWM_DT1_DEB_MODE_S  8
+/* MCPWM_DT1_RED_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */
+/*description: Update method for RED (rising edge delay) active reg. 0: immediate
+  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
+#define MCPWM_DT1_RED_UPMETHOD  0x0000000F
+#define MCPWM_DT1_RED_UPMETHOD_M  ((MCPWM_DT1_RED_UPMETHOD_V)<<(MCPWM_DT1_RED_UPMETHOD_S))
+#define MCPWM_DT1_RED_UPMETHOD_V  0xF
+#define MCPWM_DT1_RED_UPMETHOD_S  4
+/* MCPWM_DT1_FED_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: Update method for FED (falling edge delay) active reg. 0: immediate
+  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
+#define MCPWM_DT1_FED_UPMETHOD  0x0000000F
+#define MCPWM_DT1_FED_UPMETHOD_M  ((MCPWM_DT1_FED_UPMETHOD_V)<<(MCPWM_DT1_FED_UPMETHOD_S))
+#define MCPWM_DT1_FED_UPMETHOD_V  0xF
+#define MCPWM_DT1_FED_UPMETHOD_S  0
+
+#define MCPWM_DT1_FED_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x0094)
+/* MCPWM_DT1_FED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: Shadow reg for FED*/
+#define MCPWM_DT1_FED  0x0000FFFF
+#define MCPWM_DT1_FED_M  ((MCPWM_DT1_FED_V)<<(MCPWM_DT1_FED_S))
+#define MCPWM_DT1_FED_V  0xFFFF
+#define MCPWM_DT1_FED_S  0
+
+#define MCPWM_DT1_RED_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x0098)
+/* MCPWM_DT1_RED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: Shadow reg for RED*/
+#define MCPWM_DT1_RED  0x0000FFFF
+#define MCPWM_DT1_RED_M  ((MCPWM_DT1_RED_V)<<(MCPWM_DT1_RED_S))
+#define MCPWM_DT1_RED_V  0xFFFF
+#define MCPWM_DT1_RED_S  0
+
+#define MCPWM_CARRIER1_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x009c)
+/* MCPWM_CARRIER1_IN_INVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: When set  invert the input of PWM1A and PWM1B for this submodule*/
+#define MCPWM_CARRIER1_IN_INVERT  (BIT(13))
+#define MCPWM_CARRIER1_IN_INVERT_M  (BIT(13))
+#define MCPWM_CARRIER1_IN_INVERT_V  0x1
+#define MCPWM_CARRIER1_IN_INVERT_S  13
+/* MCPWM_CARRIER1_OUT_INVERT : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: When set  invert the output of PWM1A and PWM1B for this submodule*/
+#define MCPWM_CARRIER1_OUT_INVERT  (BIT(12))
+#define MCPWM_CARRIER1_OUT_INVERT_M  (BIT(12))
+#define MCPWM_CARRIER1_OUT_INVERT_V  0x1
+#define MCPWM_CARRIER1_OUT_INVERT_S  12
+/* MCPWM_CARRIER1_OSHWTH : R/W ;bitpos:[11:8] ;default: 4'd0 ; */
+/*description: Width of the fist pulse in number of periods of the carrier*/
+#define MCPWM_CARRIER1_OSHWTH  0x0000000F
+#define MCPWM_CARRIER1_OSHWTH_M  ((MCPWM_CARRIER1_OSHWTH_V)<<(MCPWM_CARRIER1_OSHWTH_S))
+#define MCPWM_CARRIER1_OSHWTH_V  0xF
+#define MCPWM_CARRIER1_OSHWTH_S  8
+/* MCPWM_CARRIER1_DUTY : R/W ;bitpos:[7:5] ;default: 3'd0 ; */
+/*description: Carrier duty selection. Duty = PWM_CARRIER1_DUTY / 8*/
+#define MCPWM_CARRIER1_DUTY  0x00000007
+#define MCPWM_CARRIER1_DUTY_M  ((MCPWM_CARRIER1_DUTY_V)<<(MCPWM_CARRIER1_DUTY_S))
+#define MCPWM_CARRIER1_DUTY_V  0x7
+#define MCPWM_CARRIER1_DUTY_S  5
+/* MCPWM_CARRIER1_PRESCALE : R/W ;bitpos:[4:1] ;default: 4'd0 ; */
+/*description: PWM carrier1 clock (PC_clk) prescale value. Period of PC_clk
+ = period of PWM_clk * (PWM_CARRIER1_PRESCALE + 1)*/
+#define MCPWM_CARRIER1_PRESCALE  0x0000000F
+#define MCPWM_CARRIER1_PRESCALE_M  ((MCPWM_CARRIER1_PRESCALE_V)<<(MCPWM_CARRIER1_PRESCALE_S))
+#define MCPWM_CARRIER1_PRESCALE_V  0xF
+#define MCPWM_CARRIER1_PRESCALE_S  1
+/* MCPWM_CARRIER1_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: When set  carrier1 function is enabled. When cleared  carrier1 is bypassed*/
+#define MCPWM_CARRIER1_EN  (BIT(0))
+#define MCPWM_CARRIER1_EN_M  (BIT(0))
+#define MCPWM_CARRIER1_EN_V  0x1
+#define MCPWM_CARRIER1_EN_S  0
+
+#define MCPWM_FH1_CFG0_REG(i)          (REG_MCPWM_BASE(i) + 0x00a0)
+/* MCPWM_FH1_B_OST_U : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: One-shot mode action on PWM1B when fault event occurs and timer
+ is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH1_B_OST_U  0x00000003
+#define MCPWM_FH1_B_OST_U_M  ((MCPWM_FH1_B_OST_U_V)<<(MCPWM_FH1_B_OST_U_S))
+#define MCPWM_FH1_B_OST_U_V  0x3
+#define MCPWM_FH1_B_OST_U_S  22
+/* MCPWM_FH1_B_OST_D : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: One-shot mode action on PWM1B when fault event occurs and timer
+ is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH1_B_OST_D  0x00000003
+#define MCPWM_FH1_B_OST_D_M  ((MCPWM_FH1_B_OST_D_V)<<(MCPWM_FH1_B_OST_D_S))
+#define MCPWM_FH1_B_OST_D_V  0x3
+#define MCPWM_FH1_B_OST_D_S  20
+/* MCPWM_FH1_B_CBC_U : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: Cycle-by-cycle mode action on PWM1B when fault event occurs and
+ timer is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH1_B_CBC_U  0x00000003
+#define MCPWM_FH1_B_CBC_U_M  ((MCPWM_FH1_B_CBC_U_V)<<(MCPWM_FH1_B_CBC_U_S))
+#define MCPWM_FH1_B_CBC_U_V  0x3
+#define MCPWM_FH1_B_CBC_U_S  18
+/* MCPWM_FH1_B_CBC_D : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: Cycle-by-cycle mode action on PWM1B when fault event occurs and
+ timer is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH1_B_CBC_D  0x00000003
+#define MCPWM_FH1_B_CBC_D_M  ((MCPWM_FH1_B_CBC_D_V)<<(MCPWM_FH1_B_CBC_D_S))
+#define MCPWM_FH1_B_CBC_D_V  0x3
+#define MCPWM_FH1_B_CBC_D_S  16
+/* MCPWM_FH1_A_OST_U : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
+/*description: One-shot mode action on PWM1A when fault event occurs and timer
+ is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH1_A_OST_U  0x00000003
+#define MCPWM_FH1_A_OST_U_M  ((MCPWM_FH1_A_OST_U_V)<<(MCPWM_FH1_A_OST_U_S))
+#define MCPWM_FH1_A_OST_U_V  0x3
+#define MCPWM_FH1_A_OST_U_S  14
+/* MCPWM_FH1_A_OST_D : R/W ;bitpos:[13:12] ;default: 2'd0 ; */
+/*description: One-shot mode action on PWM1A when fault event occurs and timer
+ is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH1_A_OST_D  0x00000003
+#define MCPWM_FH1_A_OST_D_M  ((MCPWM_FH1_A_OST_D_V)<<(MCPWM_FH1_A_OST_D_S))
+#define MCPWM_FH1_A_OST_D_V  0x3
+#define MCPWM_FH1_A_OST_D_S  12
+/* MCPWM_FH1_A_CBC_U : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
+/*description: Cycle-by-cycle mode action on PWM1A when fault event occurs and
+ timer is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH1_A_CBC_U  0x00000003
+#define MCPWM_FH1_A_CBC_U_M  ((MCPWM_FH1_A_CBC_U_V)<<(MCPWM_FH1_A_CBC_U_S))
+#define MCPWM_FH1_A_CBC_U_V  0x3
+#define MCPWM_FH1_A_CBC_U_S  10
+/* MCPWM_FH1_A_CBC_D : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
+/*description: Cycle-by-cycle mode action on PWM1A when fault event occurs and
+ timer is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH1_A_CBC_D  0x00000003
+#define MCPWM_FH1_A_CBC_D_M  ((MCPWM_FH1_A_CBC_D_V)<<(MCPWM_FH1_A_CBC_D_S))
+#define MCPWM_FH1_A_CBC_D_V  0x3
+#define MCPWM_FH1_A_CBC_D_S  8
+/* MCPWM_FH1_F0_OST : R/W ;bitpos:[7] ;default: 1'd0 ; */
+/*description: event_f0 will trigger one-shot mode action. 0: disable  1: enable*/
+#define MCPWM_FH1_F0_OST  (BIT(7))
+#define MCPWM_FH1_F0_OST_M  (BIT(7))
+#define MCPWM_FH1_F0_OST_V  0x1
+#define MCPWM_FH1_F0_OST_S  7
+/* MCPWM_FH1_F1_OST : R/W ;bitpos:[6] ;default: 1'd0 ; */
+/*description: event_f1 will trigger one-shot mode action. 0: disable  1: enable*/
+#define MCPWM_FH1_F1_OST  (BIT(6))
+#define MCPWM_FH1_F1_OST_M  (BIT(6))
+#define MCPWM_FH1_F1_OST_V  0x1
+#define MCPWM_FH1_F1_OST_S  6
+/* MCPWM_FH1_F2_OST : R/W ;bitpos:[5] ;default: 1'd0 ; */
+/*description: event_f2 will trigger one-shot mode action. 0: disable  1: enable*/
+#define MCPWM_FH1_F2_OST  (BIT(5))
+#define MCPWM_FH1_F2_OST_M  (BIT(5))
+#define MCPWM_FH1_F2_OST_V  0x1
+#define MCPWM_FH1_F2_OST_S  5
+/* MCPWM_FH1_SW_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */
+/*description: Enable register for software force one-shot mode action. 0: disable  1: enable*/
+#define MCPWM_FH1_SW_OST  (BIT(4))
+#define MCPWM_FH1_SW_OST_M  (BIT(4))
+#define MCPWM_FH1_SW_OST_V  0x1
+#define MCPWM_FH1_SW_OST_S  4
+/* MCPWM_FH1_F0_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */
+/*description: event_f0 will trigger cycle-by-cycle mode action. 0: disable  1: enable*/
+#define MCPWM_FH1_F0_CBC  (BIT(3))
+#define MCPWM_FH1_F0_CBC_M  (BIT(3))
+#define MCPWM_FH1_F0_CBC_V  0x1
+#define MCPWM_FH1_F0_CBC_S  3
+/* MCPWM_FH1_F1_CBC : R/W ;bitpos:[2] ;default: 1'd0 ; */
+/*description: event_f1 will trigger cycle-by-cycle mode action. 0: disable  1: enable*/
+#define MCPWM_FH1_F1_CBC  (BIT(2))
+#define MCPWM_FH1_F1_CBC_M  (BIT(2))
+#define MCPWM_FH1_F1_CBC_V  0x1
+#define MCPWM_FH1_F1_CBC_S  2
+/* MCPWM_FH1_F2_CBC : R/W ;bitpos:[1] ;default: 1'd0 ; */
+/*description: event_f2 will trigger cycle-by-cycle mode action. 0: disable  1: enable*/
+#define MCPWM_FH1_F2_CBC  (BIT(1))
+#define MCPWM_FH1_F2_CBC_M  (BIT(1))
+#define MCPWM_FH1_F2_CBC_V  0x1
+#define MCPWM_FH1_F2_CBC_S  1
+/* MCPWM_FH1_SW_CBC : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: Enable register for software force cycle-by-cycle mode action.
+ 0: disable  1: enable*/
+#define MCPWM_FH1_SW_CBC  (BIT(0))
+#define MCPWM_FH1_SW_CBC_M  (BIT(0))
+#define MCPWM_FH1_SW_CBC_V  0x1
+#define MCPWM_FH1_SW_CBC_S  0
+
+#define MCPWM_FH1_CFG1_REG(i)          (REG_MCPWM_BASE(i) + 0x00a4)
+/* MCPWM_FH1_FORCE_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */
+/*description: A toggle (software negation of value of this bit) triggers a
+ one-shot mode action*/
+#define MCPWM_FH1_FORCE_OST  (BIT(4))
+#define MCPWM_FH1_FORCE_OST_M  (BIT(4))
+#define MCPWM_FH1_FORCE_OST_V  0x1
+#define MCPWM_FH1_FORCE_OST_S  4
+/* MCPWM_FH1_FORCE_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */
+/*description: A toggle triggers a cycle-by-cycle mode action*/
+#define MCPWM_FH1_FORCE_CBC  (BIT(3))
+#define MCPWM_FH1_FORCE_CBC_M  (BIT(3))
+#define MCPWM_FH1_FORCE_CBC_V  0x1
+#define MCPWM_FH1_FORCE_CBC_S  3
+/* MCPWM_FH1_CBCPULSE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */
+/*description: The cycle-by-cycle mode action refresh moment selection. Bit0: TEZ  bit1:TEP*/
+#define MCPWM_FH1_CBCPULSE  0x00000003
+#define MCPWM_FH1_CBCPULSE_M  ((MCPWM_FH1_CBCPULSE_V)<<(MCPWM_FH1_CBCPULSE_S))
+#define MCPWM_FH1_CBCPULSE_V  0x3
+#define MCPWM_FH1_CBCPULSE_S  1
+/* MCPWM_FH1_CLR_OST : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: A toggle will clear on going one-shot mode action*/
+#define MCPWM_FH1_CLR_OST  (BIT(0))
+#define MCPWM_FH1_CLR_OST_M  (BIT(0))
+#define MCPWM_FH1_CLR_OST_V  0x1
+#define MCPWM_FH1_CLR_OST_S  0
+
+#define MCPWM_FH1_STATUS_REG(i)          (REG_MCPWM_BASE(i) + 0x00a8)
+/* MCPWM_FH1_OST_ON : RO ;bitpos:[1] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  an one-shot mode action is on going*/
+#define MCPWM_FH1_OST_ON  (BIT(1))
+#define MCPWM_FH1_OST_ON_M  (BIT(1))
+#define MCPWM_FH1_OST_ON_V  0x1
+#define MCPWM_FH1_OST_ON_S  1
+/* MCPWM_FH1_CBC_ON : RO ;bitpos:[0] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  an cycle-by-cycle mode action is on going*/
+#define MCPWM_FH1_CBC_ON  (BIT(0))
+#define MCPWM_FH1_CBC_ON_M  (BIT(0))
+#define MCPWM_FH1_CBC_ON_V  0x1
+#define MCPWM_FH1_CBC_ON_S  0
+
+#define MCPWM_GEN2_STMP_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x00ac)
+/* MCPWM_GEN2_B_SHDW_FULL : RO ;bitpos:[9] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  PWM generator 2 time stamp
+ B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared  B's active reg has been updated with shadow reg latest value*/
+#define MCPWM_GEN2_B_SHDW_FULL  (BIT(9))
+#define MCPWM_GEN2_B_SHDW_FULL_M  (BIT(9))
+#define MCPWM_GEN2_B_SHDW_FULL_V  0x1
+#define MCPWM_GEN2_B_SHDW_FULL_S  9
+/* MCPWM_GEN2_A_SHDW_FULL : RO ;bitpos:[8] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  PWM generator 2 time stamp
+ A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared  A's active reg has been updated with shadow reg latest value*/
+#define MCPWM_GEN2_A_SHDW_FULL  (BIT(8))
+#define MCPWM_GEN2_A_SHDW_FULL_M  (BIT(8))
+#define MCPWM_GEN2_A_SHDW_FULL_V  0x1
+#define MCPWM_GEN2_A_SHDW_FULL_S  8
+/* MCPWM_GEN2_B_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */
+/*description: Update method for PWM generator 2 time stamp B's active reg.
+ 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
+#define MCPWM_GEN2_B_UPMETHOD  0x0000000F
+#define MCPWM_GEN2_B_UPMETHOD_M  ((MCPWM_GEN2_B_UPMETHOD_V)<<(MCPWM_GEN2_B_UPMETHOD_S))
+#define MCPWM_GEN2_B_UPMETHOD_V  0xF
+#define MCPWM_GEN2_B_UPMETHOD_S  4
+/* MCPWM_GEN2_A_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: Update method for PWM generator 2 time stamp A's active reg.
+ 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
+#define MCPWM_GEN2_A_UPMETHOD  0x0000000F
+#define MCPWM_GEN2_A_UPMETHOD_M  ((MCPWM_GEN2_A_UPMETHOD_V)<<(MCPWM_GEN2_A_UPMETHOD_S))
+#define MCPWM_GEN2_A_UPMETHOD_V  0xF
+#define MCPWM_GEN2_A_UPMETHOD_S  0
+
+#define MCPWM_GEN2_TSTMP_A_REG(i)          (REG_MCPWM_BASE(i) + 0x00b0)
+/* MCPWM_GEN2_A : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: PWM generator 2 time stamp A's shadow reg*/
+#define MCPWM_GEN2_A  0x0000FFFF
+#define MCPWM_GEN2_A_M  ((MCPWM_GEN2_A_V)<<(MCPWM_GEN2_A_S))
+#define MCPWM_GEN2_A_V  0xFFFF
+#define MCPWM_GEN2_A_S  0
+
+#define MCPWM_GEN2_TSTMP_B_REG(i)          (REG_MCPWM_BASE(i) + 0x00b4)
+/* MCPWM_GEN2_B : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: PWM generator 2 time stamp B's shadow reg*/
+#define MCPWM_GEN2_B  0x0000FFFF
+#define MCPWM_GEN2_B_M  ((MCPWM_GEN2_B_V)<<(MCPWM_GEN2_B_S))
+#define MCPWM_GEN2_B_V  0xFFFF
+#define MCPWM_GEN2_B_S  0
+
+#define MCPWM_GEN2_CFG0_REG(i)          (REG_MCPWM_BASE(i) + 0x00b8)
+/* MCPWM_GEN2_T1_SEL : R/W ;bitpos:[9:7] ;default: 3'd0 ; */
+/*description: Source selection for PWM generate2 event_t1  take effect immediately
+  0: fault_event0  1: fault_event1  2: fault_event2  3: sync_taken  4: none*/
+#define MCPWM_GEN2_T1_SEL  0x00000007
+#define MCPWM_GEN2_T1_SEL_M  ((MCPWM_GEN2_T1_SEL_V)<<(MCPWM_GEN2_T1_SEL_S))
+#define MCPWM_GEN2_T1_SEL_V  0x7
+#define MCPWM_GEN2_T1_SEL_S  7
+/* MCPWM_GEN2_T0_SEL : R/W ;bitpos:[6:4] ;default: 3'd0 ; */
+/*description: Source selection for PWM generate2 event_t0  take effect immediately
+  0: fault_event0  1: fault_event1  2: fault_event2  3: sync_taken  4: none*/
+#define MCPWM_GEN2_T0_SEL  0x00000007
+#define MCPWM_GEN2_T0_SEL_M  ((MCPWM_GEN2_T0_SEL_V)<<(MCPWM_GEN2_T0_SEL_S))
+#define MCPWM_GEN2_T0_SEL_V  0x7
+#define MCPWM_GEN2_T0_SEL_S  4
+/* MCPWM_GEN2_CFG_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: Update method for PWM generate2's active reg of configuration.
+ 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync. bit3: disable update*/
+#define MCPWM_GEN2_CFG_UPMETHOD  0x0000000F
+#define MCPWM_GEN2_CFG_UPMETHOD_M  ((MCPWM_GEN2_CFG_UPMETHOD_V)<<(MCPWM_GEN2_CFG_UPMETHOD_S))
+#define MCPWM_GEN2_CFG_UPMETHOD_V  0xF
+#define MCPWM_GEN2_CFG_UPMETHOD_S  0
+
+#define MCPWM_GEN2_FORCE_REG(i)          (REG_MCPWM_BASE(i) + 0x00bc)
+/* MCPWM_GEN2_B_NCIFORCE_MODE : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
+/*description: Non-continuous immediate software force mode for PWM2B  0: disabled
+  1: low  2: high  3: disabled*/
+#define MCPWM_GEN2_B_NCIFORCE_MODE  0x00000003
+#define MCPWM_GEN2_B_NCIFORCE_MODE_M  ((MCPWM_GEN2_B_NCIFORCE_MODE_V)<<(MCPWM_GEN2_B_NCIFORCE_MODE_S))
+#define MCPWM_GEN2_B_NCIFORCE_MODE_V  0x3
+#define MCPWM_GEN2_B_NCIFORCE_MODE_S  14
+/* MCPWM_GEN2_B_NCIFORCE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: Non-continuous immediate software force trigger for PWM2B  a
+ toggle will trigger a force event*/
+#define MCPWM_GEN2_B_NCIFORCE  (BIT(13))
+#define MCPWM_GEN2_B_NCIFORCE_M  (BIT(13))
+#define MCPWM_GEN2_B_NCIFORCE_V  0x1
+#define MCPWM_GEN2_B_NCIFORCE_S  13
+/* MCPWM_GEN2_A_NCIFORCE_MODE : R/W ;bitpos:[12:11] ;default: 2'd0 ; */
+/*description: Non-continuous immediate software force mode for PWM2A  0: disabled
+  1: low  2: high  3: disabled*/
+#define MCPWM_GEN2_A_NCIFORCE_MODE  0x00000003
+#define MCPWM_GEN2_A_NCIFORCE_MODE_M  ((MCPWM_GEN2_A_NCIFORCE_MODE_V)<<(MCPWM_GEN2_A_NCIFORCE_MODE_S))
+#define MCPWM_GEN2_A_NCIFORCE_MODE_V  0x3
+#define MCPWM_GEN2_A_NCIFORCE_MODE_S  11
+/* MCPWM_GEN2_A_NCIFORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: Non-continuous immediate software force trigger for PWM2A  a
+ toggle will trigger a force event*/
+#define MCPWM_GEN2_A_NCIFORCE  (BIT(10))
+#define MCPWM_GEN2_A_NCIFORCE_M  (BIT(10))
+#define MCPWM_GEN2_A_NCIFORCE_V  0x1
+#define MCPWM_GEN2_A_NCIFORCE_S  10
+/* MCPWM_GEN2_B_CNTUFORCE_MODE : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
+/*description: Continuous software force mode for PWM2B. 0: disabled  1: low
+  2: high  3: disabled*/
+#define MCPWM_GEN2_B_CNTUFORCE_MODE  0x00000003
+#define MCPWM_GEN2_B_CNTUFORCE_MODE_M  ((MCPWM_GEN2_B_CNTUFORCE_MODE_V)<<(MCPWM_GEN2_B_CNTUFORCE_MODE_S))
+#define MCPWM_GEN2_B_CNTUFORCE_MODE_V  0x3
+#define MCPWM_GEN2_B_CNTUFORCE_MODE_S  8
+/* MCPWM_GEN2_A_CNTUFORCE_MODE : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
+/*description: Continuous software force mode for PWM2A. 0: disabled  1: low
+  2: high  3: disabled*/
+#define MCPWM_GEN2_A_CNTUFORCE_MODE  0x00000003
+#define MCPWM_GEN2_A_CNTUFORCE_MODE_M  ((MCPWM_GEN2_A_CNTUFORCE_MODE_V)<<(MCPWM_GEN2_A_CNTUFORCE_MODE_S))
+#define MCPWM_GEN2_A_CNTUFORCE_MODE_V  0x3
+#define MCPWM_GEN2_A_CNTUFORCE_MODE_S  6
+/* MCPWM_GEN2_CNTUFORCE_UPMETHOD : R/W ;bitpos:[5:0] ;default: 6'h20 ; */
+/*description: Update method for continuous software force of PWM generator2.
+ 0: immediate  bit0: TEZ  bit1: TEP  bit2: TEA  bit3: TEB  bit4: sync  bit5: disable update. (TEA/B here and below means an event generated when timer value equals A/B register)*/
+#define MCPWM_GEN2_CNTUFORCE_UPMETHOD  0x0000003F
+#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_M  ((MCPWM_GEN2_CNTUFORCE_UPMETHOD_V)<<(MCPWM_GEN2_CNTUFORCE_UPMETHOD_S))
+#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_V  0x3F
+#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_S  0
+
+#define MCPWM_GEN2_A_REG(i)          (REG_MCPWM_BASE(i) + 0x00c0)
+/* MCPWM_GEN2_A_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: Action on PWM2A triggered by event_t1 when timer decreasing.
+ 0: no change  1: low  2: high  3: toggle*/
+#define MCPWM_GEN2_A_DT1  0x00000003
+#define MCPWM_GEN2_A_DT1_M  ((MCPWM_GEN2_A_DT1_V)<<(MCPWM_GEN2_A_DT1_S))
+#define MCPWM_GEN2_A_DT1_V  0x3
+#define MCPWM_GEN2_A_DT1_S  22
+/* MCPWM_GEN2_A_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: Action on PWM2A triggered by event_t0 when timer decreasing*/
+#define MCPWM_GEN2_A_DT0  0x00000003
+#define MCPWM_GEN2_A_DT0_M  ((MCPWM_GEN2_A_DT0_V)<<(MCPWM_GEN2_A_DT0_S))
+#define MCPWM_GEN2_A_DT0_V  0x3
+#define MCPWM_GEN2_A_DT0_S  20
+/* MCPWM_GEN2_A_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: Action on PWM2A triggered by event TEB when timer decreasing*/
+#define MCPWM_GEN2_A_DTEB  0x00000003
+#define MCPWM_GEN2_A_DTEB_M  ((MCPWM_GEN2_A_DTEB_V)<<(MCPWM_GEN2_A_DTEB_S))
+#define MCPWM_GEN2_A_DTEB_V  0x3
+#define MCPWM_GEN2_A_DTEB_S  18
+/* MCPWM_GEN2_A_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: Action on PWM2A triggered by event TEA when timer decreasing*/
+#define MCPWM_GEN2_A_DTEA  0x00000003
+#define MCPWM_GEN2_A_DTEA_M  ((MCPWM_GEN2_A_DTEA_V)<<(MCPWM_GEN2_A_DTEA_S))
+#define MCPWM_GEN2_A_DTEA_V  0x3
+#define MCPWM_GEN2_A_DTEA_S  16
+/* MCPWM_GEN2_A_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
+/*description: Action on PWM2A triggered by event TEP when timer decreasing*/
+#define MCPWM_GEN2_A_DTEP  0x00000003
+#define MCPWM_GEN2_A_DTEP_M  ((MCPWM_GEN2_A_DTEP_V)<<(MCPWM_GEN2_A_DTEP_S))
+#define MCPWM_GEN2_A_DTEP_V  0x3
+#define MCPWM_GEN2_A_DTEP_S  14
+/* MCPWM_GEN2_A_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */
+/*description: Action on PWM2A triggered by event TEZ when timer decreasing*/
+#define MCPWM_GEN2_A_DTEZ  0x00000003
+#define MCPWM_GEN2_A_DTEZ_M  ((MCPWM_GEN2_A_DTEZ_V)<<(MCPWM_GEN2_A_DTEZ_S))
+#define MCPWM_GEN2_A_DTEZ_V  0x3
+#define MCPWM_GEN2_A_DTEZ_S  12
+/* MCPWM_GEN2_A_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
+/*description: Action on PWM2A triggered by event_t1 when timer increasing*/
+#define MCPWM_GEN2_A_UT1  0x00000003
+#define MCPWM_GEN2_A_UT1_M  ((MCPWM_GEN2_A_UT1_V)<<(MCPWM_GEN2_A_UT1_S))
+#define MCPWM_GEN2_A_UT1_V  0x3
+#define MCPWM_GEN2_A_UT1_S  10
+/* MCPWM_GEN2_A_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
+/*description: Action on PWM2A triggered by event_t0 when timer increasing*/
+#define MCPWM_GEN2_A_UT0  0x00000003
+#define MCPWM_GEN2_A_UT0_M  ((MCPWM_GEN2_A_UT0_V)<<(MCPWM_GEN2_A_UT0_S))
+#define MCPWM_GEN2_A_UT0_V  0x3
+#define MCPWM_GEN2_A_UT0_S  8
+/* MCPWM_GEN2_A_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
+/*description: Action on PWM2A triggered by event TEB when timer increasing*/
+#define MCPWM_GEN2_A_UTEB  0x00000003
+#define MCPWM_GEN2_A_UTEB_M  ((MCPWM_GEN2_A_UTEB_V)<<(MCPWM_GEN2_A_UTEB_S))
+#define MCPWM_GEN2_A_UTEB_V  0x3
+#define MCPWM_GEN2_A_UTEB_S  6
+/* MCPWM_GEN2_A_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */
+/*description: Action on PWM2A triggered by event TEA when timer increasing*/
+#define MCPWM_GEN2_A_UTEA  0x00000003
+#define MCPWM_GEN2_A_UTEA_M  ((MCPWM_GEN2_A_UTEA_V)<<(MCPWM_GEN2_A_UTEA_S))
+#define MCPWM_GEN2_A_UTEA_V  0x3
+#define MCPWM_GEN2_A_UTEA_S  4
+/* MCPWM_GEN2_A_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
+/*description: Action on PWM2A triggered by event TEP when timer increasing*/
+#define MCPWM_GEN2_A_UTEP  0x00000003
+#define MCPWM_GEN2_A_UTEP_M  ((MCPWM_GEN2_A_UTEP_V)<<(MCPWM_GEN2_A_UTEP_S))
+#define MCPWM_GEN2_A_UTEP_V  0x3
+#define MCPWM_GEN2_A_UTEP_S  2
+/* MCPWM_GEN2_A_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: Action on PWM2A triggered by event TEZ when timer increasing*/
+#define MCPWM_GEN2_A_UTEZ  0x00000003
+#define MCPWM_GEN2_A_UTEZ_M  ((MCPWM_GEN2_A_UTEZ_V)<<(MCPWM_GEN2_A_UTEZ_S))
+#define MCPWM_GEN2_A_UTEZ_V  0x3
+#define MCPWM_GEN2_A_UTEZ_S  0
+
+#define MCPWM_GEN2_B_REG(i)          (REG_MCPWM_BASE(i) + 0x00c4)
+/* MCPWM_GEN2_B_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: Action on PWM2B triggered by event_t1 when timer decreasing.
+ 0: no change  1: low  2: high  3: toggle*/
+#define MCPWM_GEN2_B_DT1  0x00000003
+#define MCPWM_GEN2_B_DT1_M  ((MCPWM_GEN2_B_DT1_V)<<(MCPWM_GEN2_B_DT1_S))
+#define MCPWM_GEN2_B_DT1_V  0x3
+#define MCPWM_GEN2_B_DT1_S  22
+/* MCPWM_GEN2_B_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: Action on PWM2B triggered by event_t0 when timer decreasing*/
+#define MCPWM_GEN2_B_DT0  0x00000003
+#define MCPWM_GEN2_B_DT0_M  ((MCPWM_GEN2_B_DT0_V)<<(MCPWM_GEN2_B_DT0_S))
+#define MCPWM_GEN2_B_DT0_V  0x3
+#define MCPWM_GEN2_B_DT0_S  20
+/* MCPWM_GEN2_B_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: Action on PWM2B triggered by event TEB when timer decreasing*/
+#define MCPWM_GEN2_B_DTEB  0x00000003
+#define MCPWM_GEN2_B_DTEB_M  ((MCPWM_GEN2_B_DTEB_V)<<(MCPWM_GEN2_B_DTEB_S))
+#define MCPWM_GEN2_B_DTEB_V  0x3
+#define MCPWM_GEN2_B_DTEB_S  18
+/* MCPWM_GEN2_B_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: Action on PWM2B triggered by event TEA when timer decreasing*/
+#define MCPWM_GEN2_B_DTEA  0x00000003
+#define MCPWM_GEN2_B_DTEA_M  ((MCPWM_GEN2_B_DTEA_V)<<(MCPWM_GEN2_B_DTEA_S))
+#define MCPWM_GEN2_B_DTEA_V  0x3
+#define MCPWM_GEN2_B_DTEA_S  16
+/* MCPWM_GEN2_B_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
+/*description: Action on PWM2B triggered by event TEP when timer decreasing*/
+#define MCPWM_GEN2_B_DTEP  0x00000003
+#define MCPWM_GEN2_B_DTEP_M  ((MCPWM_GEN2_B_DTEP_V)<<(MCPWM_GEN2_B_DTEP_S))
+#define MCPWM_GEN2_B_DTEP_V  0x3
+#define MCPWM_GEN2_B_DTEP_S  14
+/* MCPWM_GEN2_B_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */
+/*description: Action on PWM2B triggered by event TEZ when timer decreasing*/
+#define MCPWM_GEN2_B_DTEZ  0x00000003
+#define MCPWM_GEN2_B_DTEZ_M  ((MCPWM_GEN2_B_DTEZ_V)<<(MCPWM_GEN2_B_DTEZ_S))
+#define MCPWM_GEN2_B_DTEZ_V  0x3
+#define MCPWM_GEN2_B_DTEZ_S  12
+/* MCPWM_GEN2_B_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
+/*description: Action on PWM2B triggered by event_t1 when timer increasing*/
+#define MCPWM_GEN2_B_UT1  0x00000003
+#define MCPWM_GEN2_B_UT1_M  ((MCPWM_GEN2_B_UT1_V)<<(MCPWM_GEN2_B_UT1_S))
+#define MCPWM_GEN2_B_UT1_V  0x3
+#define MCPWM_GEN2_B_UT1_S  10
+/* MCPWM_GEN2_B_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
+/*description: Action on PWM2B triggered by event_t0 when timer increasing*/
+#define MCPWM_GEN2_B_UT0  0x00000003
+#define MCPWM_GEN2_B_UT0_M  ((MCPWM_GEN2_B_UT0_V)<<(MCPWM_GEN2_B_UT0_S))
+#define MCPWM_GEN2_B_UT0_V  0x3
+#define MCPWM_GEN2_B_UT0_S  8
+/* MCPWM_GEN2_B_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
+/*description: Action on PWM2B triggered by event TEB when timer increasing*/
+#define MCPWM_GEN2_B_UTEB  0x00000003
+#define MCPWM_GEN2_B_UTEB_M  ((MCPWM_GEN2_B_UTEB_V)<<(MCPWM_GEN2_B_UTEB_S))
+#define MCPWM_GEN2_B_UTEB_V  0x3
+#define MCPWM_GEN2_B_UTEB_S  6
+/* MCPWM_GEN2_B_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */
+/*description: Action on PWM2B triggered by event TEA when timer increasing*/
+#define MCPWM_GEN2_B_UTEA  0x00000003
+#define MCPWM_GEN2_B_UTEA_M  ((MCPWM_GEN2_B_UTEA_V)<<(MCPWM_GEN2_B_UTEA_S))
+#define MCPWM_GEN2_B_UTEA_V  0x3
+#define MCPWM_GEN2_B_UTEA_S  4
+/* MCPWM_GEN2_B_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
+/*description: Action on PWM2B triggered by event TEP when timer increasing*/
+#define MCPWM_GEN2_B_UTEP  0x00000003
+#define MCPWM_GEN2_B_UTEP_M  ((MCPWM_GEN2_B_UTEP_V)<<(MCPWM_GEN2_B_UTEP_S))
+#define MCPWM_GEN2_B_UTEP_V  0x3
+#define MCPWM_GEN2_B_UTEP_S  2
+/* MCPWM_GEN2_B_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: Action on PWM2B triggered by event TEZ when timer increasing*/
+#define MCPWM_GEN2_B_UTEZ  0x00000003
+#define MCPWM_GEN2_B_UTEZ_M  ((MCPWM_GEN2_B_UTEZ_V)<<(MCPWM_GEN2_B_UTEZ_S))
+#define MCPWM_GEN2_B_UTEZ_V  0x3
+#define MCPWM_GEN2_B_UTEZ_S  0
+
+#define MCPWM_DT2_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x00c8)
+/* MCPWM_DT2_CLK_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */
+/*description: Dead time generator 1 clock selection. 0: PWM_clk  1: PT_clk*/
+#define MCPWM_DT2_CLK_SEL  (BIT(17))
+#define MCPWM_DT2_CLK_SEL_M  (BIT(17))
+#define MCPWM_DT2_CLK_SEL_V  0x1
+#define MCPWM_DT2_CLK_SEL_S  17
+/* MCPWM_DT2_B_OUTBYPASS : R/W ;bitpos:[16] ;default: 1'd1 ; */
+/*description: S0 in documentation*/
+#define MCPWM_DT2_B_OUTBYPASS  (BIT(16))
+#define MCPWM_DT2_B_OUTBYPASS_M  (BIT(16))
+#define MCPWM_DT2_B_OUTBYPASS_V  0x1
+#define MCPWM_DT2_B_OUTBYPASS_S  16
+/* MCPWM_DT2_A_OUTBYPASS : R/W ;bitpos:[15] ;default: 1'd1 ; */
+/*description: S1 in documentation*/
+#define MCPWM_DT2_A_OUTBYPASS  (BIT(15))
+#define MCPWM_DT2_A_OUTBYPASS_M  (BIT(15))
+#define MCPWM_DT2_A_OUTBYPASS_V  0x1
+#define MCPWM_DT2_A_OUTBYPASS_S  15
+/* MCPWM_DT2_FED_OUTINVERT : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: S3 in documentation*/
+#define MCPWM_DT2_FED_OUTINVERT  (BIT(14))
+#define MCPWM_DT2_FED_OUTINVERT_M  (BIT(14))
+#define MCPWM_DT2_FED_OUTINVERT_V  0x1
+#define MCPWM_DT2_FED_OUTINVERT_S  14
+/* MCPWM_DT2_RED_OUTINVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: S2 in documentation*/
+#define MCPWM_DT2_RED_OUTINVERT  (BIT(13))
+#define MCPWM_DT2_RED_OUTINVERT_M  (BIT(13))
+#define MCPWM_DT2_RED_OUTINVERT_V  0x1
+#define MCPWM_DT2_RED_OUTINVERT_S  13
+/* MCPWM_DT2_FED_INSEL : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: S5 in documentation*/
+#define MCPWM_DT2_FED_INSEL  (BIT(12))
+#define MCPWM_DT2_FED_INSEL_M  (BIT(12))
+#define MCPWM_DT2_FED_INSEL_V  0x1
+#define MCPWM_DT2_FED_INSEL_S  12
+/* MCPWM_DT2_RED_INSEL : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: S4 in documentation*/
+#define MCPWM_DT2_RED_INSEL  (BIT(11))
+#define MCPWM_DT2_RED_INSEL_M  (BIT(11))
+#define MCPWM_DT2_RED_INSEL_V  0x1
+#define MCPWM_DT2_RED_INSEL_S  11
+/* MCPWM_DT2_B_OUTSWAP : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: S7 in documentation*/
+#define MCPWM_DT2_B_OUTSWAP  (BIT(10))
+#define MCPWM_DT2_B_OUTSWAP_M  (BIT(10))
+#define MCPWM_DT2_B_OUTSWAP_V  0x1
+#define MCPWM_DT2_B_OUTSWAP_S  10
+/* MCPWM_DT2_A_OUTSWAP : R/W ;bitpos:[9] ;default: 1'd0 ; */
+/*description: S6 in documentation*/
+#define MCPWM_DT2_A_OUTSWAP  (BIT(9))
+#define MCPWM_DT2_A_OUTSWAP_M  (BIT(9))
+#define MCPWM_DT2_A_OUTSWAP_V  0x1
+#define MCPWM_DT2_A_OUTSWAP_S  9
+/* MCPWM_DT2_DEB_MODE : R/W ;bitpos:[8] ;default: 1'd0 ; */
+/*description: S8 in documentation  dual-edge B mode  0: FED/RED take effect
+ on different path separately  1: FED/RED take effect on B path  A out is in bypass or normal operation mode*/
+#define MCPWM_DT2_DEB_MODE  (BIT(8))
+#define MCPWM_DT2_DEB_MODE_M  (BIT(8))
+#define MCPWM_DT2_DEB_MODE_V  0x1
+#define MCPWM_DT2_DEB_MODE_S  8
+/* MCPWM_DT2_RED_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */
+/*description: Update method for RED (rising edge delay) active reg. 0: immediate
+  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
+#define MCPWM_DT2_RED_UPMETHOD  0x0000000F
+#define MCPWM_DT2_RED_UPMETHOD_M  ((MCPWM_DT2_RED_UPMETHOD_V)<<(MCPWM_DT2_RED_UPMETHOD_S))
+#define MCPWM_DT2_RED_UPMETHOD_V  0xF
+#define MCPWM_DT2_RED_UPMETHOD_S  4
+/* MCPWM_DT2_FED_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: Update method for FED (falling edge delay) active reg. 0: immediate
+  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
+#define MCPWM_DT2_FED_UPMETHOD  0x0000000F
+#define MCPWM_DT2_FED_UPMETHOD_M  ((MCPWM_DT2_FED_UPMETHOD_V)<<(MCPWM_DT2_FED_UPMETHOD_S))
+#define MCPWM_DT2_FED_UPMETHOD_V  0xF
+#define MCPWM_DT2_FED_UPMETHOD_S  0
+
+#define MCPWM_DT2_FED_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x00cc)
+/* MCPWM_DT2_FED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: Shadow reg for FED*/
+#define MCPWM_DT2_FED  0x0000FFFF
+#define MCPWM_DT2_FED_M  ((MCPWM_DT2_FED_V)<<(MCPWM_DT2_FED_S))
+#define MCPWM_DT2_FED_V  0xFFFF
+#define MCPWM_DT2_FED_S  0
+
+#define MCPWM_DT2_RED_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x00d0)
+/* MCPWM_DT2_RED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: Shadow reg for RED*/
+#define MCPWM_DT2_RED  0x0000FFFF
+#define MCPWM_DT2_RED_M  ((MCPWM_DT2_RED_V)<<(MCPWM_DT2_RED_S))
+#define MCPWM_DT2_RED_V  0xFFFF
+#define MCPWM_DT2_RED_S  0
+
+#define MCPWM_CARRIER2_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x00d4)
+/* MCPWM_CARRIER2_IN_INVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: When set  invert the input of PWM2A and PWM2B for this submodule*/
+#define MCPWM_CARRIER2_IN_INVERT  (BIT(13))
+#define MCPWM_CARRIER2_IN_INVERT_M  (BIT(13))
+#define MCPWM_CARRIER2_IN_INVERT_V  0x1
+#define MCPWM_CARRIER2_IN_INVERT_S  13
+/* MCPWM_CARRIER2_OUT_INVERT : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: When set  invert the output of PWM2A and PWM2B for this submodule*/
+#define MCPWM_CARRIER2_OUT_INVERT  (BIT(12))
+#define MCPWM_CARRIER2_OUT_INVERT_M  (BIT(12))
+#define MCPWM_CARRIER2_OUT_INVERT_V  0x1
+#define MCPWM_CARRIER2_OUT_INVERT_S  12
+/* MCPWM_CARRIER2_OSHWTH : R/W ;bitpos:[11:8] ;default: 4'd0 ; */
+/*description: Width of the fist pulse in number of periods of the carrier*/
+#define MCPWM_CARRIER2_OSHWTH  0x0000000F
+#define MCPWM_CARRIER2_OSHWTH_M  ((MCPWM_CARRIER2_OSHWTH_V)<<(MCPWM_CARRIER2_OSHWTH_S))
+#define MCPWM_CARRIER2_OSHWTH_V  0xF
+#define MCPWM_CARRIER2_OSHWTH_S  8
+/* MCPWM_CARRIER2_DUTY : R/W ;bitpos:[7:5] ;default: 3'd0 ; */
+/*description: Carrier duty selection. Duty = PWM_CARRIER2_DUTY / 8*/
+#define MCPWM_CARRIER2_DUTY  0x00000007
+#define MCPWM_CARRIER2_DUTY_M  ((MCPWM_CARRIER2_DUTY_V)<<(MCPWM_CARRIER2_DUTY_S))
+#define MCPWM_CARRIER2_DUTY_V  0x7
+#define MCPWM_CARRIER2_DUTY_S  5
+/* MCPWM_CARRIER2_PRESCALE : R/W ;bitpos:[4:1] ;default: 4'd0 ; */
+/*description: PWM carrier2 clock (PC_clk) prescale value. Period of PC_clk
+ = period of PWM_clk * (PWM_CARRIER2_PRESCALE + 1)*/
+#define MCPWM_CARRIER2_PRESCALE  0x0000000F
+#define MCPWM_CARRIER2_PRESCALE_M  ((MCPWM_CARRIER2_PRESCALE_V)<<(MCPWM_CARRIER2_PRESCALE_S))
+#define MCPWM_CARRIER2_PRESCALE_V  0xF
+#define MCPWM_CARRIER2_PRESCALE_S  1
+/* MCPWM_CARRIER2_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: When set  carrier2 function is enabled. When cleared  carrier2 is bypassed*/
+#define MCPWM_CARRIER2_EN  (BIT(0))
+#define MCPWM_CARRIER2_EN_M  (BIT(0))
+#define MCPWM_CARRIER2_EN_V  0x1
+#define MCPWM_CARRIER2_EN_S  0
+
+#define MCPWM_FH2_CFG0_REG(i)          (REG_MCPWM_BASE(i) + 0x00d8)
+/* MCPWM_FH2_B_OST_U : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: One-shot mode action on PWM2B when fault event occurs and timer
+ is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH2_B_OST_U  0x00000003
+#define MCPWM_FH2_B_OST_U_M  ((MCPWM_FH2_B_OST_U_V)<<(MCPWM_FH2_B_OST_U_S))
+#define MCPWM_FH2_B_OST_U_V  0x3
+#define MCPWM_FH2_B_OST_U_S  22
+/* MCPWM_FH2_B_OST_D : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: One-shot mode action on PWM2B when fault event occurs and timer
+ is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH2_B_OST_D  0x00000003
+#define MCPWM_FH2_B_OST_D_M  ((MCPWM_FH2_B_OST_D_V)<<(MCPWM_FH2_B_OST_D_S))
+#define MCPWM_FH2_B_OST_D_V  0x3
+#define MCPWM_FH2_B_OST_D_S  20
+/* MCPWM_FH2_B_CBC_U : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: Cycle-by-cycle mode action on PWM2B when fault event occurs and
+ timer is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH2_B_CBC_U  0x00000003
+#define MCPWM_FH2_B_CBC_U_M  ((MCPWM_FH2_B_CBC_U_V)<<(MCPWM_FH2_B_CBC_U_S))
+#define MCPWM_FH2_B_CBC_U_V  0x3
+#define MCPWM_FH2_B_CBC_U_S  18
+/* MCPWM_FH2_B_CBC_D : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: Cycle-by-cycle mode action on PWM2B when fault event occurs and
+ timer is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH2_B_CBC_D  0x00000003
+#define MCPWM_FH2_B_CBC_D_M  ((MCPWM_FH2_B_CBC_D_V)<<(MCPWM_FH2_B_CBC_D_S))
+#define MCPWM_FH2_B_CBC_D_V  0x3
+#define MCPWM_FH2_B_CBC_D_S  16
+/* MCPWM_FH2_A_OST_U : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
+/*description: One-shot mode action on PWM2A when fault event occurs and timer
+ is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH2_A_OST_U  0x00000003
+#define MCPWM_FH2_A_OST_U_M  ((MCPWM_FH2_A_OST_U_V)<<(MCPWM_FH2_A_OST_U_S))
+#define MCPWM_FH2_A_OST_U_V  0x3
+#define MCPWM_FH2_A_OST_U_S  14
+/* MCPWM_FH2_A_OST_D : R/W ;bitpos:[13:12] ;default: 2'd0 ; */
+/*description: One-shot mode action on PWM2A when fault event occurs and timer
+ is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH2_A_OST_D  0x00000003
+#define MCPWM_FH2_A_OST_D_M  ((MCPWM_FH2_A_OST_D_V)<<(MCPWM_FH2_A_OST_D_S))
+#define MCPWM_FH2_A_OST_D_V  0x3
+#define MCPWM_FH2_A_OST_D_S  12
+/* MCPWM_FH2_A_CBC_U : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
+/*description: Cycle-by-cycle mode action on PWM2A when fault event occurs and
+ timer is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH2_A_CBC_U  0x00000003
+#define MCPWM_FH2_A_CBC_U_M  ((MCPWM_FH2_A_CBC_U_V)<<(MCPWM_FH2_A_CBC_U_S))
+#define MCPWM_FH2_A_CBC_U_V  0x3
+#define MCPWM_FH2_A_CBC_U_S  10
+/* MCPWM_FH2_A_CBC_D : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
+/*description: Cycle-by-cycle mode action on PWM2A when fault event occurs and
+ timer is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH2_A_CBC_D  0x00000003
+#define MCPWM_FH2_A_CBC_D_M  ((MCPWM_FH2_A_CBC_D_V)<<(MCPWM_FH2_A_CBC_D_S))
+#define MCPWM_FH2_A_CBC_D_V  0x3
+#define MCPWM_FH2_A_CBC_D_S  8
+/* MCPWM_FH2_F0_OST : R/W ;bitpos:[7] ;default: 1'd0 ; */
+/*description: event_f0 will trigger one-shot mode action. 0: disable  1: enable*/
+#define MCPWM_FH2_F0_OST  (BIT(7))
+#define MCPWM_FH2_F0_OST_M  (BIT(7))
+#define MCPWM_FH2_F0_OST_V  0x1
+#define MCPWM_FH2_F0_OST_S  7
+/* MCPWM_FH2_F1_OST : R/W ;bitpos:[6] ;default: 1'd0 ; */
+/*description: event_f1 will trigger one-shot mode action. 0: disable  1: enable*/
+#define MCPWM_FH2_F1_OST  (BIT(6))
+#define MCPWM_FH2_F1_OST_M  (BIT(6))
+#define MCPWM_FH2_F1_OST_V  0x1
+#define MCPWM_FH2_F1_OST_S  6
+/* MCPWM_FH2_F2_OST : R/W ;bitpos:[5] ;default: 1'd0 ; */
+/*description: event_f2 will trigger one-shot mode action. 0: disable  1: enable*/
+#define MCPWM_FH2_F2_OST  (BIT(5))
+#define MCPWM_FH2_F2_OST_M  (BIT(5))
+#define MCPWM_FH2_F2_OST_V  0x1
+#define MCPWM_FH2_F2_OST_S  5
+/* MCPWM_FH2_SW_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */
+/*description: Enable register for software force one-shot mode action. 0: disable  1: enable*/
+#define MCPWM_FH2_SW_OST  (BIT(4))
+#define MCPWM_FH2_SW_OST_M  (BIT(4))
+#define MCPWM_FH2_SW_OST_V  0x1
+#define MCPWM_FH2_SW_OST_S  4
+/* MCPWM_FH2_F0_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */
+/*description: event_f0 will trigger cycle-by-cycle mode action. 0: disable  1: enable*/
+#define MCPWM_FH2_F0_CBC  (BIT(3))
+#define MCPWM_FH2_F0_CBC_M  (BIT(3))
+#define MCPWM_FH2_F0_CBC_V  0x1
+#define MCPWM_FH2_F0_CBC_S  3
+/* MCPWM_FH2_F1_CBC : R/W ;bitpos:[2] ;default: 1'd0 ; */
+/*description: event_f1 will trigger cycle-by-cycle mode action. 0: disable  1: enable*/
+#define MCPWM_FH2_F1_CBC  (BIT(2))
+#define MCPWM_FH2_F1_CBC_M  (BIT(2))
+#define MCPWM_FH2_F1_CBC_V  0x1
+#define MCPWM_FH2_F1_CBC_S  2
+/* MCPWM_FH2_F2_CBC : R/W ;bitpos:[1] ;default: 1'd0 ; */
+/*description: event_f2 will trigger cycle-by-cycle mode action. 0: disable  1: enable*/
+#define MCPWM_FH2_F2_CBC  (BIT(1))
+#define MCPWM_FH2_F2_CBC_M  (BIT(1))
+#define MCPWM_FH2_F2_CBC_V  0x1
+#define MCPWM_FH2_F2_CBC_S  1
+/* MCPWM_FH2_SW_CBC : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: Enable register for software force cycle-by-cycle mode action.
+ 0: disable  1: enable*/
+#define MCPWM_FH2_SW_CBC  (BIT(0))
+#define MCPWM_FH2_SW_CBC_M  (BIT(0))
+#define MCPWM_FH2_SW_CBC_V  0x1
+#define MCPWM_FH2_SW_CBC_S  0
+
+#define MCPWM_FH2_CFG1_REG(i)          (REG_MCPWM_BASE(i) + 0x00dc)
+/* MCPWM_FH2_FORCE_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */
+/*description: A toggle (software negation of value of this bit) triggers a
+ one-shot mode action*/
+#define MCPWM_FH2_FORCE_OST  (BIT(4))
+#define MCPWM_FH2_FORCE_OST_M  (BIT(4))
+#define MCPWM_FH2_FORCE_OST_V  0x1
+#define MCPWM_FH2_FORCE_OST_S  4
+/* MCPWM_FH2_FORCE_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */
+/*description: A toggle triggers a cycle-by-cycle mode action*/
+#define MCPWM_FH2_FORCE_CBC  (BIT(3))
+#define MCPWM_FH2_FORCE_CBC_M  (BIT(3))
+#define MCPWM_FH2_FORCE_CBC_V  0x1
+#define MCPWM_FH2_FORCE_CBC_S  3
+/* MCPWM_FH2_CBCPULSE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */
+/*description: The cycle-by-cycle mode action refresh moment selection. Bit0: TEZ  bit1:TEP*/
+#define MCPWM_FH2_CBCPULSE  0x00000003
+#define MCPWM_FH2_CBCPULSE_M  ((MCPWM_FH2_CBCPULSE_V)<<(MCPWM_FH2_CBCPULSE_S))
+#define MCPWM_FH2_CBCPULSE_V  0x3
+#define MCPWM_FH2_CBCPULSE_S  1
+/* MCPWM_FH2_CLR_OST : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: A toggle will clear on going one-shot mode action*/
+#define MCPWM_FH2_CLR_OST  (BIT(0))
+#define MCPWM_FH2_CLR_OST_M  (BIT(0))
+#define MCPWM_FH2_CLR_OST_V  0x1
+#define MCPWM_FH2_CLR_OST_S  0
+
+#define MCPWM_FH2_STATUS_REG(i)          (REG_MCPWM_BASE(i) + 0x00e0)
+/* MCPWM_FH2_OST_ON : RO ;bitpos:[1] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  an one-shot mode action is on going*/
+#define MCPWM_FH2_OST_ON  (BIT(1))
+#define MCPWM_FH2_OST_ON_M  (BIT(1))
+#define MCPWM_FH2_OST_ON_V  0x1
+#define MCPWM_FH2_OST_ON_S  1
+/* MCPWM_FH2_CBC_ON : RO ;bitpos:[0] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  an cycle-by-cycle mode action is on going*/
+#define MCPWM_FH2_CBC_ON  (BIT(0))
+#define MCPWM_FH2_CBC_ON_M  (BIT(0))
+#define MCPWM_FH2_CBC_ON_V  0x1
+#define MCPWM_FH2_CBC_ON_S  0
+
+#define MCPWM_FAULT_DETECT_REG(i)          (REG_MCPWM_BASE(i) + 0x00e4)
+/* MCPWM_EVENT_F2 : RO ;bitpos:[8] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  event_f2 is on going*/
+#define MCPWM_EVENT_F2  (BIT(8))
+#define MCPWM_EVENT_F2_M  (BIT(8))
+#define MCPWM_EVENT_F2_V  0x1
+#define MCPWM_EVENT_F2_S  8
+/* MCPWM_EVENT_F1 : RO ;bitpos:[7] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  event_f1 is on going*/
+#define MCPWM_EVENT_F1  (BIT(7))
+#define MCPWM_EVENT_F1_M  (BIT(7))
+#define MCPWM_EVENT_F1_V  0x1
+#define MCPWM_EVENT_F1_S  7
+/* MCPWM_EVENT_F0 : RO ;bitpos:[6] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  event_f0 is on going*/
+#define MCPWM_EVENT_F0  (BIT(6))
+#define MCPWM_EVENT_F0_M  (BIT(6))
+#define MCPWM_EVENT_F0_V  0x1
+#define MCPWM_EVENT_F0_S  6
+/* MCPWM_F2_POLE : R/W ;bitpos:[5] ;default: 1'd0 ; */
+/*description: Set event_f2 trigger polarity on FAULT2 source from GPIO matrix.
+ 0: level low  1: level high*/
+#define MCPWM_F2_POLE  (BIT(5))
+#define MCPWM_F2_POLE_M  (BIT(5))
+#define MCPWM_F2_POLE_V  0x1
+#define MCPWM_F2_POLE_S  5
+/* MCPWM_F1_POLE : R/W ;bitpos:[4] ;default: 1'd0 ; */
+/*description: Set event_f1 trigger polarity on FAULT2 source from GPIO matrix.
+ 0: level low  1: level high*/
+#define MCPWM_F1_POLE  (BIT(4))
+#define MCPWM_F1_POLE_M  (BIT(4))
+#define MCPWM_F1_POLE_V  0x1
+#define MCPWM_F1_POLE_S  4
+/* MCPWM_F0_POLE : R/W ;bitpos:[3] ;default: 1'd0 ; */
+/*description: Set event_f0 trigger polarity on FAULT2 source from GPIO matrix.
+ 0: level low  1: level high*/
+#define MCPWM_F0_POLE  (BIT(3))
+#define MCPWM_F0_POLE_M  (BIT(3))
+#define MCPWM_F0_POLE_V  0x1
+#define MCPWM_F0_POLE_S  3
+/* MCPWM_F2_EN : R/W ;bitpos:[2] ;default: 1'd0 ; */
+/*description: Set to enable generation of event_f2*/
+#define MCPWM_F2_EN  (BIT(2))
+#define MCPWM_F2_EN_M  (BIT(2))
+#define MCPWM_F2_EN_V  0x1
+#define MCPWM_F2_EN_S  2
+/* MCPWM_F1_EN : R/W ;bitpos:[1] ;default: 1'd0 ; */
+/*description: Set to enable generation of event_f1*/
+#define MCPWM_F1_EN  (BIT(1))
+#define MCPWM_F1_EN_M  (BIT(1))
+#define MCPWM_F1_EN_V  0x1
+#define MCPWM_F1_EN_S  1
+/* MCPWM_F0_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: Set to enable generation of event_f0*/
+#define MCPWM_F0_EN  (BIT(0))
+#define MCPWM_F0_EN_M  (BIT(0))
+#define MCPWM_F0_EN_V  0x1
+#define MCPWM_F0_EN_S  0
+
+#define MCPWM_CAP_TIMER_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x00e8)
+/* MCPWM_CAP_SYNC_SW : WO ;bitpos:[5] ;default: 1'd0 ; */
+/*description: Set this bit to force a capture timer sync  capture timer is
+ loaded with value in phase register.*/
+#define MCPWM_CAP_SYNC_SW  (BIT(5))
+#define MCPWM_CAP_SYNC_SW_M  (BIT(5))
+#define MCPWM_CAP_SYNC_SW_V  0x1
+#define MCPWM_CAP_SYNC_SW_S  5
+/* MCPWM_CAP_SYNCI_SEL : R/W ;bitpos:[4:2] ;default: 3'd0 ; */
+/*description: Capture module sync input selection. 0: none  1: timer0 synco
+  2: timer1 synco  3: timer2 synco  4: SYNC0 from GPIO matrix  5: SYNC1 from GPIO matrix  6: SYNC2 from GPIO matrix*/
+#define MCPWM_CAP_SYNCI_SEL  0x00000007
+#define MCPWM_CAP_SYNCI_SEL_M  ((MCPWM_CAP_SYNCI_SEL_V)<<(MCPWM_CAP_SYNCI_SEL_S))
+#define MCPWM_CAP_SYNCI_SEL_V  0x7
+#define MCPWM_CAP_SYNCI_SEL_S  2
+/* MCPWM_CAP_SYNCI_EN : R/W ;bitpos:[1] ;default: 1'd0 ; */
+/*description: When set  capture timer sync is enabled.*/
+#define MCPWM_CAP_SYNCI_EN  (BIT(1))
+#define MCPWM_CAP_SYNCI_EN_M  (BIT(1))
+#define MCPWM_CAP_SYNCI_EN_V  0x1
+#define MCPWM_CAP_SYNCI_EN_S  1
+/* MCPWM_CAP_TIMER_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: When set  capture timer incrementing under APB_clk is enabled.*/
+#define MCPWM_CAP_TIMER_EN  (BIT(0))
+#define MCPWM_CAP_TIMER_EN_M  (BIT(0))
+#define MCPWM_CAP_TIMER_EN_V  0x1
+#define MCPWM_CAP_TIMER_EN_S  0
+
+#define MCPWM_CAP_TIMER_PHASE_REG(i)          (REG_MCPWM_BASE(i) + 0x00ec)
+/* MCPWM_CAP_PHASE : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: Phase value for capture timer sync operation.*/
+#define MCPWM_CAP_PHASE  0xFFFFFFFF
+#define MCPWM_CAP_PHASE_M  ((MCPWM_CAP_PHASE_V)<<(MCPWM_CAP_PHASE_S))
+#define MCPWM_CAP_PHASE_V  0xFFFFFFFF
+#define MCPWM_CAP_PHASE_S  0
+
+#define MCPWM_CAP_CH0_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x00f0)
+/* MCPWM_CAP0_SW : WO ;bitpos:[12] ;default: 1'd0 ; */
+/*description: Write 1 will trigger a software forced capture on channel 0*/
+#define MCPWM_CAP0_SW  (BIT(12))
+#define MCPWM_CAP0_SW_M  (BIT(12))
+#define MCPWM_CAP0_SW_V  0x1
+#define MCPWM_CAP0_SW_S  12
+/* MCPWM_CAP0_IN_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: When set  CAP0 form GPIO matrix is inverted before prescale*/
+#define MCPWM_CAP0_IN_INVERT  (BIT(11))
+#define MCPWM_CAP0_IN_INVERT_M  (BIT(11))
+#define MCPWM_CAP0_IN_INVERT_V  0x1
+#define MCPWM_CAP0_IN_INVERT_S  11
+/* MCPWM_CAP0_PRESCALE : R/W ;bitpos:[10:3] ;default: 8'd0 ; */
+/*description: Value of prescale on possitive edge of CAP0. Prescale value =
+ PWM_CAP0_PRESCALE + 1*/
+#define MCPWM_CAP0_PRESCALE  0x000000FF
+#define MCPWM_CAP0_PRESCALE_M  ((MCPWM_CAP0_PRESCALE_V)<<(MCPWM_CAP0_PRESCALE_S))
+#define MCPWM_CAP0_PRESCALE_V  0xFF
+#define MCPWM_CAP0_PRESCALE_S  3
+/* MCPWM_CAP0_MODE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */
+/*description: Edge of capture on channel 0 after prescale.  bit0: negedge cap
+ en  bit1: posedge cap en*/
+#define MCPWM_CAP0_MODE  0x00000003
+#define MCPWM_CAP0_MODE_M  ((MCPWM_CAP0_MODE_V)<<(MCPWM_CAP0_MODE_S))
+#define MCPWM_CAP0_MODE_V  0x3
+#define MCPWM_CAP0_MODE_S  1
+/* MCPWM_CAP0_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: When set  capture on channel 0 is enabled*/
+#define MCPWM_CAP0_EN  (BIT(0))
+#define MCPWM_CAP0_EN_M  (BIT(0))
+#define MCPWM_CAP0_EN_V  0x1
+#define MCPWM_CAP0_EN_S  0
+
+#define MCPWM_CAP_CH1_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x00f4)
+/* MCPWM_CAP1_SW : WO ;bitpos:[12] ;default: 1'd0 ; */
+/*description: Write 1 will trigger a software forced capture on channel 1*/
+#define MCPWM_CAP1_SW  (BIT(12))
+#define MCPWM_CAP1_SW_M  (BIT(12))
+#define MCPWM_CAP1_SW_V  0x1
+#define MCPWM_CAP1_SW_S  12
+/* MCPWM_CAP1_IN_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: When set  CAP1 form GPIO matrix is inverted before prescale*/
+#define MCPWM_CAP1_IN_INVERT  (BIT(11))
+#define MCPWM_CAP1_IN_INVERT_M  (BIT(11))
+#define MCPWM_CAP1_IN_INVERT_V  0x1
+#define MCPWM_CAP1_IN_INVERT_S  11
+/* MCPWM_CAP1_PRESCALE : R/W ;bitpos:[10:3] ;default: 8'd0 ; */
+/*description: Value of prescale on possitive edge of CAP1. Prescale value =
+ PWM_CAP1_PRESCALE + 1*/
+#define MCPWM_CAP1_PRESCALE  0x000000FF
+#define MCPWM_CAP1_PRESCALE_M  ((MCPWM_CAP1_PRESCALE_V)<<(MCPWM_CAP1_PRESCALE_S))
+#define MCPWM_CAP1_PRESCALE_V  0xFF
+#define MCPWM_CAP1_PRESCALE_S  3
+/* MCPWM_CAP1_MODE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */
+/*description: Edge of capture on channel 1 after prescale.  bit0: negedge cap
+ en  bit1: posedge cap en*/
+#define MCPWM_CAP1_MODE  0x00000003
+#define MCPWM_CAP1_MODE_M  ((MCPWM_CAP1_MODE_V)<<(MCPWM_CAP1_MODE_S))
+#define MCPWM_CAP1_MODE_V  0x3
+#define MCPWM_CAP1_MODE_S  1
+/* MCPWM_CAP1_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: When set  capture on channel 1 is enabled*/
+#define MCPWM_CAP1_EN  (BIT(0))
+#define MCPWM_CAP1_EN_M  (BIT(0))
+#define MCPWM_CAP1_EN_V  0x1
+#define MCPWM_CAP1_EN_S  0
+
+#define MCPWM_CAP_CH2_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x00f8)
+/* MCPWM_CAP2_SW : WO ;bitpos:[12] ;default: 1'd0 ; */
+/*description: Write 1 will trigger a software forced capture on channel 2*/
+#define MCPWM_CAP2_SW  (BIT(12))
+#define MCPWM_CAP2_SW_M  (BIT(12))
+#define MCPWM_CAP2_SW_V  0x1
+#define MCPWM_CAP2_SW_S  12
+/* MCPWM_CAP2_IN_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: When set  CAP2 form GPIO matrix is inverted before prescale*/
+#define MCPWM_CAP2_IN_INVERT  (BIT(11))
+#define MCPWM_CAP2_IN_INVERT_M  (BIT(11))
+#define MCPWM_CAP2_IN_INVERT_V  0x1
+#define MCPWM_CAP2_IN_INVERT_S  11
+/* MCPWM_CAP2_PRESCALE : R/W ;bitpos:[10:3] ;default: 8'd0 ; */
+/*description: Value of prescale on possitive edge of CAP2. Prescale value =
+ PWM_CAP2_PRESCALE + 1*/
+#define MCPWM_CAP2_PRESCALE  0x000000FF
+#define MCPWM_CAP2_PRESCALE_M  ((MCPWM_CAP2_PRESCALE_V)<<(MCPWM_CAP2_PRESCALE_S))
+#define MCPWM_CAP2_PRESCALE_V  0xFF
+#define MCPWM_CAP2_PRESCALE_S  3
+/* MCPWM_CAP2_MODE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */
+/*description: Edge of capture on channel 2 after prescale.  bit0: negedge cap
+ en  bit1: posedge cap en*/
+#define MCPWM_CAP2_MODE  0x00000003
+#define MCPWM_CAP2_MODE_M  ((MCPWM_CAP2_MODE_V)<<(MCPWM_CAP2_MODE_S))
+#define MCPWM_CAP2_MODE_V  0x3
+#define MCPWM_CAP2_MODE_S  1
+/* MCPWM_CAP2_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: When set  capture on channel 2 is enabled*/
+#define MCPWM_CAP2_EN  (BIT(0))
+#define MCPWM_CAP2_EN_M  (BIT(0))
+#define MCPWM_CAP2_EN_V  0x1
+#define MCPWM_CAP2_EN_S  0
+
+#define MCPWM_CAP_CH0_REG(i)          (REG_MCPWM_BASE(i) + 0x00fc)
+/* MCPWM_CAP0_VALUE : RO ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: Value of last capture on channel 0*/
+#define MCPWM_CAP0_VALUE  0xFFFFFFFF
+#define MCPWM_CAP0_VALUE_M  ((MCPWM_CAP0_VALUE_V)<<(MCPWM_CAP0_VALUE_S))
+#define MCPWM_CAP0_VALUE_V  0xFFFFFFFF
+#define MCPWM_CAP0_VALUE_S  0
+
+#define MCPWM_CAP_CH1_REG(i)          (REG_MCPWM_BASE(i) + 0x0100)
+/* MCPWM_CAP1_VALUE : RO ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: Value of last capture on channel 1*/
+#define MCPWM_CAP1_VALUE  0xFFFFFFFF
+#define MCPWM_CAP1_VALUE_M  ((MCPWM_CAP1_VALUE_V)<<(MCPWM_CAP1_VALUE_S))
+#define MCPWM_CAP1_VALUE_V  0xFFFFFFFF
+#define MCPWM_CAP1_VALUE_S  0
+
+#define MCPWM_CAP_CH2_REG(i)          (REG_MCPWM_BASE(i) + 0x0104)
+/* MCPWM_CAP2_VALUE : RO ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: Value of last capture on channel 2*/
+#define MCPWM_CAP2_VALUE  0xFFFFFFFF
+#define MCPWM_CAP2_VALUE_M  ((MCPWM_CAP2_VALUE_V)<<(MCPWM_CAP2_VALUE_S))
+#define MCPWM_CAP2_VALUE_V  0xFFFFFFFF
+#define MCPWM_CAP2_VALUE_S  0
+
+#define MCPWM_CAP_STATUS_REG(i)          (REG_MCPWM_BASE(i) + 0x0108)
+/* MCPWM_CAP2_EDGE : RO ;bitpos:[2] ;default: 1'd0 ; */
+/*description: Edge of last capture trigger on channel 2  0: posedge  1: negedge*/
+#define MCPWM_CAP2_EDGE  (BIT(2))
+#define MCPWM_CAP2_EDGE_M  (BIT(2))
+#define MCPWM_CAP2_EDGE_V  0x1
+#define MCPWM_CAP2_EDGE_S  2
+/* MCPWM_CAP1_EDGE : RO ;bitpos:[1] ;default: 1'd0 ; */
+/*description: Edge of last capture trigger on channel 1  0: posedge  1: negedge*/
+#define MCPWM_CAP1_EDGE  (BIT(1))
+#define MCPWM_CAP1_EDGE_M  (BIT(1))
+#define MCPWM_CAP1_EDGE_V  0x1
+#define MCPWM_CAP1_EDGE_S  1
+/* MCPWM_CAP0_EDGE : RO ;bitpos:[0] ;default: 1'd0 ; */
+/*description: Edge of last capture trigger on channel 0  0: posedge  1: negedge*/
+#define MCPWM_CAP0_EDGE  (BIT(0))
+#define MCPWM_CAP0_EDGE_M  (BIT(0))
+#define MCPWM_CAP0_EDGE_V  0x1
+#define MCPWM_CAP0_EDGE_S  0
+
+#define MCPWM_UPDATE_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x010c)
+/* MCPWM_OP2_FORCE_UP : R/W ;bitpos:[7] ;default: 1'd0 ; */
+/*description: A toggle (software negation of value of this bit) will trigger
+ a forced update of active registers in PWM operator 2*/
+#define MCPWM_OP2_FORCE_UP  (BIT(7))
+#define MCPWM_OP2_FORCE_UP_M  (BIT(7))
+#define MCPWM_OP2_FORCE_UP_V  0x1
+#define MCPWM_OP2_FORCE_UP_S  7
+/* MCPWM_OP2_UP_EN : R/W ;bitpos:[6] ;default: 1'd1 ; */
+/*description: When set and PWM_GLOBAL_UP_EN is set  update of active registers
+ in PWM operator 2 are enabled*/
+#define MCPWM_OP2_UP_EN  (BIT(6))
+#define MCPWM_OP2_UP_EN_M  (BIT(6))
+#define MCPWM_OP2_UP_EN_V  0x1
+#define MCPWM_OP2_UP_EN_S  6
+/* MCPWM_OP1_FORCE_UP : R/W ;bitpos:[5] ;default: 1'd0 ; */
+/*description: A toggle (software negation of value of this bit) will trigger
+ a forced update of active registers in PWM operator 1*/
+#define MCPWM_OP1_FORCE_UP  (BIT(5))
+#define MCPWM_OP1_FORCE_UP_M  (BIT(5))
+#define MCPWM_OP1_FORCE_UP_V  0x1
+#define MCPWM_OP1_FORCE_UP_S  5
+/* MCPWM_OP1_UP_EN : R/W ;bitpos:[4] ;default: 1'd1 ; */
+/*description: When set and PWM_GLOBAL_UP_EN is set  update of active registers
+ in PWM operator 1 are enabled*/
+#define MCPWM_OP1_UP_EN  (BIT(4))
+#define MCPWM_OP1_UP_EN_M  (BIT(4))
+#define MCPWM_OP1_UP_EN_V  0x1
+#define MCPWM_OP1_UP_EN_S  4
+/* MCPWM_OP0_FORCE_UP : R/W ;bitpos:[3] ;default: 1'd0 ; */
+/*description: A toggle (software negation of value of this bit) will trigger
+ a forced update of active registers in PWM operator 0*/
+#define MCPWM_OP0_FORCE_UP  (BIT(3))
+#define MCPWM_OP0_FORCE_UP_M  (BIT(3))
+#define MCPWM_OP0_FORCE_UP_V  0x1
+#define MCPWM_OP0_FORCE_UP_S  3
+/* MCPWM_OP0_UP_EN : R/W ;bitpos:[2] ;default: 1'd1 ; */
+/*description: When set and PWM_GLOBAL_UP_EN is set  update of active registers
+ in PWM operator 0 are enabled*/
+#define MCPWM_OP0_UP_EN  (BIT(2))
+#define MCPWM_OP0_UP_EN_M  (BIT(2))
+#define MCPWM_OP0_UP_EN_V  0x1
+#define MCPWM_OP0_UP_EN_S  2
+/* MCPWM_GLOBAL_FORCE_UP : R/W ;bitpos:[1] ;default: 1'd0 ; */
+/*description: A toggle (software negation of value of this bit) will trigger
+ a forced update of all active registers in MCPWM module*/
+#define MCPWM_GLOBAL_FORCE_UP  (BIT(1))
+#define MCPWM_GLOBAL_FORCE_UP_M  (BIT(1))
+#define MCPWM_GLOBAL_FORCE_UP_V  0x1
+#define MCPWM_GLOBAL_FORCE_UP_S  1
+/* MCPWM_GLOBAL_UP_EN : R/W ;bitpos:[0] ;default: 1'd1 ; */
+/*description: The global enable of update of all active registers in MCPWM module*/
+#define MCPWM_GLOBAL_UP_EN  (BIT(0))
+#define MCPWM_GLOBAL_UP_EN_M  (BIT(0))
+#define MCPWM_GLOBAL_UP_EN_V  0x1
+#define MCPWM_GLOBAL_UP_EN_S  0
+
+#define MCMCPWM_INT_ENA_MCPWM_REG(i)          (REG_MCPWM_BASE(i) + 0x0110)
+/* MCPWM_CAP2_INT_ENA : R/W ;bitpos:[29] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by captureon channel 2*/
+#define MCPWM_CAP2_INT_ENA  (BIT(29))
+#define MCPWM_CAP2_INT_ENA_M  (BIT(29))
+#define MCPWM_CAP2_INT_ENA_V  0x1
+#define MCPWM_CAP2_INT_ENA_S  29
+/* MCPWM_CAP1_INT_ENA : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by captureon channel 1*/
+#define MCPWM_CAP1_INT_ENA  (BIT(28))
+#define MCPWM_CAP1_INT_ENA_M  (BIT(28))
+#define MCPWM_CAP1_INT_ENA_V  0x1
+#define MCPWM_CAP1_INT_ENA_S  28
+/* MCPWM_CAP0_INT_ENA : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by captureon channel 0*/
+#define MCPWM_CAP0_INT_ENA  (BIT(27))
+#define MCPWM_CAP0_INT_ENA_M  (BIT(27))
+#define MCPWM_CAP0_INT_ENA_V  0x1
+#define MCPWM_CAP0_INT_ENA_S  27
+/* MCPWM_FH2_OST_INT_ENA : R/W ;bitpos:[26] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by an one-shot mode action on PWM2*/
+#define MCPWM_FH2_OST_INT_ENA  (BIT(26))
+#define MCPWM_FH2_OST_INT_ENA_M  (BIT(26))
+#define MCPWM_FH2_OST_INT_ENA_V  0x1
+#define MCPWM_FH2_OST_INT_ENA_S  26
+/* MCPWM_FH1_OST_INT_ENA : R/W ;bitpos:[25] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by an one-shot mode action on PWM0*/
+#define MCPWM_FH1_OST_INT_ENA  (BIT(25))
+#define MCPWM_FH1_OST_INT_ENA_M  (BIT(25))
+#define MCPWM_FH1_OST_INT_ENA_V  0x1
+#define MCPWM_FH1_OST_INT_ENA_S  25
+/* MCPWM_FH0_OST_INT_ENA : R/W ;bitpos:[24] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by an one-shot mode action on PWM0*/
+#define MCPWM_FH0_OST_INT_ENA  (BIT(24))
+#define MCPWM_FH0_OST_INT_ENA_M  (BIT(24))
+#define MCPWM_FH0_OST_INT_ENA_V  0x1
+#define MCPWM_FH0_OST_INT_ENA_S  24
+/* MCPWM_FH2_CBC_INT_ENA : R/W ;bitpos:[23] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by an cycle-by-cycle mode action on PWM2*/
+#define MCPWM_FH2_CBC_INT_ENA  (BIT(23))
+#define MCPWM_FH2_CBC_INT_ENA_M  (BIT(23))
+#define MCPWM_FH2_CBC_INT_ENA_V  0x1
+#define MCPWM_FH2_CBC_INT_ENA_S  23
+/* MCPWM_FH1_CBC_INT_ENA : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by an cycle-by-cycle mode action on PWM1*/
+#define MCPWM_FH1_CBC_INT_ENA  (BIT(22))
+#define MCPWM_FH1_CBC_INT_ENA_M  (BIT(22))
+#define MCPWM_FH1_CBC_INT_ENA_V  0x1
+#define MCPWM_FH1_CBC_INT_ENA_S  22
+/* MCPWM_FH0_CBC_INT_ENA : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by an cycle-by-cycle mode action on PWM0*/
+#define MCPWM_FH0_CBC_INT_ENA  (BIT(21))
+#define MCPWM_FH0_CBC_INT_ENA_M  (BIT(21))
+#define MCPWM_FH0_CBC_INT_ENA_V  0x1
+#define MCPWM_FH0_CBC_INT_ENA_S  21
+/* MCPWM_OP2_TEB_INT_ENA : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by a PWM operator 2 TEB event*/
+#define MCPWM_OP2_TEB_INT_ENA  (BIT(20))
+#define MCPWM_OP2_TEB_INT_ENA_M  (BIT(20))
+#define MCPWM_OP2_TEB_INT_ENA_V  0x1
+#define MCPWM_OP2_TEB_INT_ENA_S  20
+/* MCPWM_OP1_TEB_INT_ENA : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by a PWM operator 1 TEB event*/
+#define MCPWM_OP1_TEB_INT_ENA  (BIT(19))
+#define MCPWM_OP1_TEB_INT_ENA_M  (BIT(19))
+#define MCPWM_OP1_TEB_INT_ENA_V  0x1
+#define MCPWM_OP1_TEB_INT_ENA_S  19
+/* MCPWM_OP0_TEB_INT_ENA : R/W ;bitpos:[18] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by a PWM operator 0 TEB event*/
+#define MCPWM_OP0_TEB_INT_ENA  (BIT(18))
+#define MCPWM_OP0_TEB_INT_ENA_M  (BIT(18))
+#define MCPWM_OP0_TEB_INT_ENA_V  0x1
+#define MCPWM_OP0_TEB_INT_ENA_S  18
+/* MCPWM_OP2_TEA_INT_ENA : R/W ;bitpos:[17] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by a PWM operator 2 TEA event*/
+#define MCPWM_OP2_TEA_INT_ENA  (BIT(17))
+#define MCPWM_OP2_TEA_INT_ENA_M  (BIT(17))
+#define MCPWM_OP2_TEA_INT_ENA_V  0x1
+#define MCPWM_OP2_TEA_INT_ENA_S  17
+/* MCPWM_OP1_TEA_INT_ENA : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by a PWM operator 1 TEA event*/
+#define MCPWM_OP1_TEA_INT_ENA  (BIT(16))
+#define MCPWM_OP1_TEA_INT_ENA_M  (BIT(16))
+#define MCPWM_OP1_TEA_INT_ENA_V  0x1
+#define MCPWM_OP1_TEA_INT_ENA_S  16
+/* MCPWM_OP0_TEA_INT_ENA : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by a PWM operator 0 TEA event*/
+#define MCPWM_OP0_TEA_INT_ENA  (BIT(15))
+#define MCPWM_OP0_TEA_INT_ENA_M  (BIT(15))
+#define MCPWM_OP0_TEA_INT_ENA_V  0x1
+#define MCPWM_OP0_TEA_INT_ENA_S  15
+/* MCPWM_FAULT2_CLR_INT_ENA : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered when event_f2 ends*/
+#define MCPWM_FAULT2_CLR_INT_ENA  (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_ENA_M  (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_ENA_V  0x1
+#define MCPWM_FAULT2_CLR_INT_ENA_S  14
+/* MCPWM_FAULT1_CLR_INT_ENA : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered when event_f1 ends*/
+#define MCPWM_FAULT1_CLR_INT_ENA  (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_ENA_M  (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_ENA_V  0x1
+#define MCPWM_FAULT1_CLR_INT_ENA_S  13
+/* MCPWM_FAULT0_CLR_INT_ENA : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered when event_f0 ends*/
+#define MCPWM_FAULT0_CLR_INT_ENA  (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_ENA_M  (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_ENA_V  0x1
+#define MCPWM_FAULT0_CLR_INT_ENA_S  12
+/* MCPWM_FAULT2_INT_ENA : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered when event_f2 starts*/
+#define MCPWM_FAULT2_INT_ENA  (BIT(11))
+#define MCPWM_FAULT2_INT_ENA_M  (BIT(11))
+#define MCPWM_FAULT2_INT_ENA_V  0x1
+#define MCPWM_FAULT2_INT_ENA_S  11
+/* MCPWM_FAULT1_INT_ENA : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered when event_f1 starts*/
+#define MCPWM_FAULT1_INT_ENA  (BIT(10))
+#define MCPWM_FAULT1_INT_ENA_M  (BIT(10))
+#define MCPWM_FAULT1_INT_ENA_V  0x1
+#define MCPWM_FAULT1_INT_ENA_S  10
+/* MCPWM_FAULT0_INT_ENA : R/W ;bitpos:[9] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered when event_f0 starts*/
+#define MCPWM_FAULT0_INT_ENA  (BIT(9))
+#define MCPWM_FAULT0_INT_ENA_M  (BIT(9))
+#define MCPWM_FAULT0_INT_ENA_V  0x1
+#define MCPWM_FAULT0_INT_ENA_S  9
+/* MCPWM_TIMER2_TEP_INT_ENA : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: The enable bit for interrupt triggered by a PWM timer 2 TEP event*/
+#define MCPWM_TIMER2_TEP_INT_ENA  (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_ENA_M  (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_ENA_V  0x1
+#define MCPWM_TIMER2_TEP_INT_ENA_S  8
+/* MCPWM_TIMER1_TEP_INT_ENA : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: The enable bit for interrupt triggered by a PWM timer 1 TEP event*/
+#define MCPWM_TIMER1_TEP_INT_ENA  (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_ENA_M  (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_ENA_V  0x1
+#define MCPWM_TIMER1_TEP_INT_ENA_S  7
+/* MCPWM_TIMER0_TEP_INT_ENA : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: The enable bit for interrupt triggered by a PWM timer 0 TEP event*/
+#define MCPWM_TIMER0_TEP_INT_ENA  (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_ENA_M  (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_ENA_V  0x1
+#define MCPWM_TIMER0_TEP_INT_ENA_S  6
+/* MCPWM_TIMER2_TEZ_INT_ENA : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: The enable bit for interrupt triggered by a PWM timer 2 TEZ event*/
+#define MCPWM_TIMER2_TEZ_INT_ENA  (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_ENA_M  (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_ENA_V  0x1
+#define MCPWM_TIMER2_TEZ_INT_ENA_S  5
+/* MCPWM_TIMER1_TEZ_INT_ENA : R/W ;bitpos:[4] ;default: 1'h0 ; */
+/*description: The enable bit for interrupt triggered by a PWM timer 1 TEZ event*/
+#define MCPWM_TIMER1_TEZ_INT_ENA  (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_ENA_M  (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_ENA_V  0x1
+#define MCPWM_TIMER1_TEZ_INT_ENA_S  4
+/* MCPWM_TIMER0_TEZ_INT_ENA : R/W ;bitpos:[3] ;default: 1'h0 ; */
+/*description: The enable bit for interrupt triggered by a PWM timer 0 TEZ event*/
+#define MCPWM_TIMER0_TEZ_INT_ENA  (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_ENA_M  (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_ENA_V  0x1
+#define MCPWM_TIMER0_TEZ_INT_ENA_S  3
+/* MCPWM_TIMER2_STOP_INT_ENA : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: The enable bit for interrupt triggered when timer 2 stops*/
+#define MCPWM_TIMER2_STOP_INT_ENA  (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_ENA_M  (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_ENA_V  0x1
+#define MCPWM_TIMER2_STOP_INT_ENA_S  2
+/* MCPWM_TIMER1_STOP_INT_ENA : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: The enable bit for interrupt triggered when timer 1 stops*/
+#define MCPWM_TIMER1_STOP_INT_ENA  (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_ENA_M  (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_ENA_V  0x1
+#define MCPWM_TIMER1_STOP_INT_ENA_S  1
+/* MCPWM_TIMER0_STOP_INT_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: The enable bit for interrupt triggered when timer 0 stops*/
+#define MCPWM_TIMER0_STOP_INT_ENA  (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_ENA_M  (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_ENA_V  0x1
+#define MCPWM_TIMER0_STOP_INT_ENA_S  0
+
+#define MCMCPWM_INT_RAW_MCPWM_REG(i)          (REG_MCPWM_BASE(i) + 0x0114)
+/* MCPWM_CAP2_INT_RAW : RO ;bitpos:[29] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by captureon channel 2*/
+#define MCPWM_CAP2_INT_RAW  (BIT(29))
+#define MCPWM_CAP2_INT_RAW_M  (BIT(29))
+#define MCPWM_CAP2_INT_RAW_V  0x1
+#define MCPWM_CAP2_INT_RAW_S  29
+/* MCPWM_CAP1_INT_RAW : RO ;bitpos:[28] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by captureon channel 1*/
+#define MCPWM_CAP1_INT_RAW  (BIT(28))
+#define MCPWM_CAP1_INT_RAW_M  (BIT(28))
+#define MCPWM_CAP1_INT_RAW_V  0x1
+#define MCPWM_CAP1_INT_RAW_S  28
+/* MCPWM_CAP0_INT_RAW : RO ;bitpos:[27] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by captureon channel 0*/
+#define MCPWM_CAP0_INT_RAW  (BIT(27))
+#define MCPWM_CAP0_INT_RAW_M  (BIT(27))
+#define MCPWM_CAP0_INT_RAW_V  0x1
+#define MCPWM_CAP0_INT_RAW_S  27
+/* MCPWM_FH2_OST_INT_RAW : RO ;bitpos:[26] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by an one-shot mode action on PWM2*/
+#define MCPWM_FH2_OST_INT_RAW  (BIT(26))
+#define MCPWM_FH2_OST_INT_RAW_M  (BIT(26))
+#define MCPWM_FH2_OST_INT_RAW_V  0x1
+#define MCPWM_FH2_OST_INT_RAW_S  26
+/* MCPWM_FH1_OST_INT_RAW : RO ;bitpos:[25] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by an one-shot mode action on PWM0*/
+#define MCPWM_FH1_OST_INT_RAW  (BIT(25))
+#define MCPWM_FH1_OST_INT_RAW_M  (BIT(25))
+#define MCPWM_FH1_OST_INT_RAW_V  0x1
+#define MCPWM_FH1_OST_INT_RAW_S  25
+/* MCPWM_FH0_OST_INT_RAW : RO ;bitpos:[24] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by an one-shot mode action on PWM0*/
+#define MCPWM_FH0_OST_INT_RAW  (BIT(24))
+#define MCPWM_FH0_OST_INT_RAW_M  (BIT(24))
+#define MCPWM_FH0_OST_INT_RAW_V  0x1
+#define MCPWM_FH0_OST_INT_RAW_S  24
+/* MCPWM_FH2_CBC_INT_RAW : RO ;bitpos:[23] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by an cycle-by-cycle
+ mode action on PWM2*/
+#define MCPWM_FH2_CBC_INT_RAW  (BIT(23))
+#define MCPWM_FH2_CBC_INT_RAW_M  (BIT(23))
+#define MCPWM_FH2_CBC_INT_RAW_V  0x1
+#define MCPWM_FH2_CBC_INT_RAW_S  23
+/* MCPWM_FH1_CBC_INT_RAW : RO ;bitpos:[22] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by an cycle-by-cycle
+ mode action on PWM1*/
+#define MCPWM_FH1_CBC_INT_RAW  (BIT(22))
+#define MCPWM_FH1_CBC_INT_RAW_M  (BIT(22))
+#define MCPWM_FH1_CBC_INT_RAW_V  0x1
+#define MCPWM_FH1_CBC_INT_RAW_S  22
+/* MCPWM_FH0_CBC_INT_RAW : RO ;bitpos:[21] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by an cycle-by-cycle
+ mode action on PWM0*/
+#define MCPWM_FH0_CBC_INT_RAW  (BIT(21))
+#define MCPWM_FH0_CBC_INT_RAW_M  (BIT(21))
+#define MCPWM_FH0_CBC_INT_RAW_V  0x1
+#define MCPWM_FH0_CBC_INT_RAW_S  21
+/* MCPWM_OP2_TEB_INT_RAW : RO ;bitpos:[20] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by a PWM operator 2 TEB event*/
+#define MCPWM_OP2_TEB_INT_RAW  (BIT(20))
+#define MCPWM_OP2_TEB_INT_RAW_M  (BIT(20))
+#define MCPWM_OP2_TEB_INT_RAW_V  0x1
+#define MCPWM_OP2_TEB_INT_RAW_S  20
+/* MCPWM_OP1_TEB_INT_RAW : RO ;bitpos:[19] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by a PWM operator 1 TEB event*/
+#define MCPWM_OP1_TEB_INT_RAW  (BIT(19))
+#define MCPWM_OP1_TEB_INT_RAW_M  (BIT(19))
+#define MCPWM_OP1_TEB_INT_RAW_V  0x1
+#define MCPWM_OP1_TEB_INT_RAW_S  19
+/* MCPWM_OP0_TEB_INT_RAW : RO ;bitpos:[18] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by a PWM operator 0 TEB event*/
+#define MCPWM_OP0_TEB_INT_RAW  (BIT(18))
+#define MCPWM_OP0_TEB_INT_RAW_M  (BIT(18))
+#define MCPWM_OP0_TEB_INT_RAW_V  0x1
+#define MCPWM_OP0_TEB_INT_RAW_S  18
+/* MCPWM_OP2_TEA_INT_RAW : RO ;bitpos:[17] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by a PWM operator 2 TEA event*/
+#define MCPWM_OP2_TEA_INT_RAW  (BIT(17))
+#define MCPWM_OP2_TEA_INT_RAW_M  (BIT(17))
+#define MCPWM_OP2_TEA_INT_RAW_V  0x1
+#define MCPWM_OP2_TEA_INT_RAW_S  17
+/* MCPWM_OP1_TEA_INT_RAW : RO ;bitpos:[16] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by a PWM operator 1 TEA event*/
+#define MCPWM_OP1_TEA_INT_RAW  (BIT(16))
+#define MCPWM_OP1_TEA_INT_RAW_M  (BIT(16))
+#define MCPWM_OP1_TEA_INT_RAW_V  0x1
+#define MCPWM_OP1_TEA_INT_RAW_S  16
+/* MCPWM_OP0_TEA_INT_RAW : RO ;bitpos:[15] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by a PWM operator 0 TEA event*/
+#define MCPWM_OP0_TEA_INT_RAW  (BIT(15))
+#define MCPWM_OP0_TEA_INT_RAW_M  (BIT(15))
+#define MCPWM_OP0_TEA_INT_RAW_V  0x1
+#define MCPWM_OP0_TEA_INT_RAW_S  15
+/* MCPWM_FAULT2_CLR_INT_RAW : RO ;bitpos:[14] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered when event_f2 ends*/
+#define MCPWM_FAULT2_CLR_INT_RAW  (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_RAW_M  (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_RAW_V  0x1
+#define MCPWM_FAULT2_CLR_INT_RAW_S  14
+/* MCPWM_FAULT1_CLR_INT_RAW : RO ;bitpos:[13] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered when event_f1 ends*/
+#define MCPWM_FAULT1_CLR_INT_RAW  (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_RAW_M  (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_RAW_V  0x1
+#define MCPWM_FAULT1_CLR_INT_RAW_S  13
+/* MCPWM_FAULT0_CLR_INT_RAW : RO ;bitpos:[12] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered when event_f0 ends*/
+#define MCPWM_FAULT0_CLR_INT_RAW  (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_RAW_M  (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_RAW_V  0x1
+#define MCPWM_FAULT0_CLR_INT_RAW_S  12
+/* MCPWM_FAULT2_INT_RAW : RO ;bitpos:[11] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered when event_f2 starts*/
+#define MCPWM_FAULT2_INT_RAW  (BIT(11))
+#define MCPWM_FAULT2_INT_RAW_M  (BIT(11))
+#define MCPWM_FAULT2_INT_RAW_V  0x1
+#define MCPWM_FAULT2_INT_RAW_S  11
+/* MCPWM_FAULT1_INT_RAW : RO ;bitpos:[10] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered when event_f1 starts*/
+#define MCPWM_FAULT1_INT_RAW  (BIT(10))
+#define MCPWM_FAULT1_INT_RAW_M  (BIT(10))
+#define MCPWM_FAULT1_INT_RAW_V  0x1
+#define MCPWM_FAULT1_INT_RAW_S  10
+/* MCPWM_FAULT0_INT_RAW : RO ;bitpos:[9] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered when event_f0 starts*/
+#define MCPWM_FAULT0_INT_RAW  (BIT(9))
+#define MCPWM_FAULT0_INT_RAW_M  (BIT(9))
+#define MCPWM_FAULT0_INT_RAW_V  0x1
+#define MCPWM_FAULT0_INT_RAW_S  9
+/* MCPWM_TIMER2_TEP_INT_RAW : RO ;bitpos:[8] ;default: 1'h0 ; */
+/*description: The raw status bit for interrupt triggered by a PWM timer 2 TEP event*/
+#define MCPWM_TIMER2_TEP_INT_RAW  (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_RAW_M  (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_RAW_V  0x1
+#define MCPWM_TIMER2_TEP_INT_RAW_S  8
+/* MCPWM_TIMER1_TEP_INT_RAW : RO ;bitpos:[7] ;default: 1'h0 ; */
+/*description: The raw status bit for interrupt triggered by a PWM timer 1 TEP event*/
+#define MCPWM_TIMER1_TEP_INT_RAW  (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_RAW_M  (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_RAW_V  0x1
+#define MCPWM_TIMER1_TEP_INT_RAW_S  7
+/* MCPWM_TIMER0_TEP_INT_RAW : RO ;bitpos:[6] ;default: 1'h0 ; */
+/*description: The raw status bit for interrupt triggered by a PWM timer 0 TEP event*/
+#define MCPWM_TIMER0_TEP_INT_RAW  (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_RAW_M  (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_RAW_V  0x1
+#define MCPWM_TIMER0_TEP_INT_RAW_S  6
+/* MCPWM_TIMER2_TEZ_INT_RAW : RO ;bitpos:[5] ;default: 1'h0 ; */
+/*description: The raw status bit for interrupt triggered by a PWM timer 2 TEZ event*/
+#define MCPWM_TIMER2_TEZ_INT_RAW  (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_RAW_M  (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_RAW_V  0x1
+#define MCPWM_TIMER2_TEZ_INT_RAW_S  5
+/* MCPWM_TIMER1_TEZ_INT_RAW : RO ;bitpos:[4] ;default: 1'h0 ; */
+/*description: The raw status bit for interrupt triggered by a PWM timer 1 TEZ event*/
+#define MCPWM_TIMER1_TEZ_INT_RAW  (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_RAW_M  (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_RAW_V  0x1
+#define MCPWM_TIMER1_TEZ_INT_RAW_S  4
+/* MCPWM_TIMER0_TEZ_INT_RAW : RO ;bitpos:[3] ;default: 1'h0 ; */
+/*description: The raw status bit for interrupt triggered by a PWM timer 0 TEZ event*/
+#define MCPWM_TIMER0_TEZ_INT_RAW  (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_RAW_M  (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_RAW_V  0x1
+#define MCPWM_TIMER0_TEZ_INT_RAW_S  3
+/* MCPWM_TIMER2_STOP_INT_RAW : RO ;bitpos:[2] ;default: 1'h0 ; */
+/*description: The raw status bit for interrupt triggered when timer 2 stops*/
+#define MCPWM_TIMER2_STOP_INT_RAW  (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_RAW_M  (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_RAW_V  0x1
+#define MCPWM_TIMER2_STOP_INT_RAW_S  2
+/* MCPWM_TIMER1_STOP_INT_RAW : RO ;bitpos:[1] ;default: 1'h0 ; */
+/*description: The raw status bit for interrupt triggered when timer 1 stops*/
+#define MCPWM_TIMER1_STOP_INT_RAW  (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_RAW_M  (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_RAW_V  0x1
+#define MCPWM_TIMER1_STOP_INT_RAW_S  1
+/* MCPWM_TIMER0_STOP_INT_RAW : RO ;bitpos:[0] ;default: 1'h0 ; */
+/*description: The raw status bit for interrupt triggered when timer 0 stops*/
+#define MCPWM_TIMER0_STOP_INT_RAW  (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_RAW_M  (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_RAW_V  0x1
+#define MCPWM_TIMER0_STOP_INT_RAW_S  0
+
+#define MCMCPWM_INT_ST_MCPWM_REG(i)          (REG_MCPWM_BASE(i) + 0x0118)
+/* MCPWM_CAP2_INT_ST : RO ;bitpos:[29] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by captureon channel 2*/
+#define MCPWM_CAP2_INT_ST  (BIT(29))
+#define MCPWM_CAP2_INT_ST_M  (BIT(29))
+#define MCPWM_CAP2_INT_ST_V  0x1
+#define MCPWM_CAP2_INT_ST_S  29
+/* MCPWM_CAP1_INT_ST : RO ;bitpos:[28] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by captureon channel 1*/
+#define MCPWM_CAP1_INT_ST  (BIT(28))
+#define MCPWM_CAP1_INT_ST_M  (BIT(28))
+#define MCPWM_CAP1_INT_ST_V  0x1
+#define MCPWM_CAP1_INT_ST_S  28
+/* MCPWM_CAP0_INT_ST : RO ;bitpos:[27] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by captureon channel 0*/
+#define MCPWM_CAP0_INT_ST  (BIT(27))
+#define MCPWM_CAP0_INT_ST_M  (BIT(27))
+#define MCPWM_CAP0_INT_ST_V  0x1
+#define MCPWM_CAP0_INT_ST_S  27
+/* MCPWM_FH2_OST_INT_ST : RO ;bitpos:[26] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by an one-shot mode action on PWM2*/
+#define MCPWM_FH2_OST_INT_ST  (BIT(26))
+#define MCPWM_FH2_OST_INT_ST_M  (BIT(26))
+#define MCPWM_FH2_OST_INT_ST_V  0x1
+#define MCPWM_FH2_OST_INT_ST_S  26
+/* MCPWM_FH1_OST_INT_ST : RO ;bitpos:[25] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by an one-shot mode action on PWM0*/
+#define MCPWM_FH1_OST_INT_ST  (BIT(25))
+#define MCPWM_FH1_OST_INT_ST_M  (BIT(25))
+#define MCPWM_FH1_OST_INT_ST_V  0x1
+#define MCPWM_FH1_OST_INT_ST_S  25
+/* MCPWM_FH0_OST_INT_ST : RO ;bitpos:[24] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by an one-shot mode action on PWM0*/
+#define MCPWM_FH0_OST_INT_ST  (BIT(24))
+#define MCPWM_FH0_OST_INT_ST_M  (BIT(24))
+#define MCPWM_FH0_OST_INT_ST_V  0x1
+#define MCPWM_FH0_OST_INT_ST_S  24
+/* MCPWM_FH2_CBC_INT_ST : RO ;bitpos:[23] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by an cycle-by-cycle
+ mode action on PWM2*/
+#define MCPWM_FH2_CBC_INT_ST  (BIT(23))
+#define MCPWM_FH2_CBC_INT_ST_M  (BIT(23))
+#define MCPWM_FH2_CBC_INT_ST_V  0x1
+#define MCPWM_FH2_CBC_INT_ST_S  23
+/* MCPWM_FH1_CBC_INT_ST : RO ;bitpos:[22] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by an cycle-by-cycle
+ mode action on PWM1*/
+#define MCPWM_FH1_CBC_INT_ST  (BIT(22))
+#define MCPWM_FH1_CBC_INT_ST_M  (BIT(22))
+#define MCPWM_FH1_CBC_INT_ST_V  0x1
+#define MCPWM_FH1_CBC_INT_ST_S  22
+/* MCPWM_FH0_CBC_INT_ST : RO ;bitpos:[21] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by an cycle-by-cycle
+ mode action on PWM0*/
+#define MCPWM_FH0_CBC_INT_ST  (BIT(21))
+#define MCPWM_FH0_CBC_INT_ST_M  (BIT(21))
+#define MCPWM_FH0_CBC_INT_ST_V  0x1
+#define MCPWM_FH0_CBC_INT_ST_S  21
+/* MCPWM_OP2_TEB_INT_ST : RO ;bitpos:[20] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by a PWM operator 2 TEB event*/
+#define MCPWM_OP2_TEB_INT_ST  (BIT(20))
+#define MCPWM_OP2_TEB_INT_ST_M  (BIT(20))
+#define MCPWM_OP2_TEB_INT_ST_V  0x1
+#define MCPWM_OP2_TEB_INT_ST_S  20
+/* MCPWM_OP1_TEB_INT_ST : RO ;bitpos:[19] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by a PWM operator 1 TEB event*/
+#define MCPWM_OP1_TEB_INT_ST  (BIT(19))
+#define MCPWM_OP1_TEB_INT_ST_M  (BIT(19))
+#define MCPWM_OP1_TEB_INT_ST_V  0x1
+#define MCPWM_OP1_TEB_INT_ST_S  19
+/* MCPWM_OP0_TEB_INT_ST : RO ;bitpos:[18] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by a PWM operator 0 TEB event*/
+#define MCPWM_OP0_TEB_INT_ST  (BIT(18))
+#define MCPWM_OP0_TEB_INT_ST_M  (BIT(18))
+#define MCPWM_OP0_TEB_INT_ST_V  0x1
+#define MCPWM_OP0_TEB_INT_ST_S  18
+/* MCPWM_OP2_TEA_INT_ST : RO ;bitpos:[17] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by a PWM operator 2 TEA event*/
+#define MCPWM_OP2_TEA_INT_ST  (BIT(17))
+#define MCPWM_OP2_TEA_INT_ST_M  (BIT(17))
+#define MCPWM_OP2_TEA_INT_ST_V  0x1
+#define MCPWM_OP2_TEA_INT_ST_S  17
+/* MCPWM_OP1_TEA_INT_ST : RO ;bitpos:[16] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by a PWM operator 1 TEA event*/
+#define MCPWM_OP1_TEA_INT_ST  (BIT(16))
+#define MCPWM_OP1_TEA_INT_ST_M  (BIT(16))
+#define MCPWM_OP1_TEA_INT_ST_V  0x1
+#define MCPWM_OP1_TEA_INT_ST_S  16
+/* MCPWM_OP0_TEA_INT_ST : RO ;bitpos:[15] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by a PWM operator 0 TEA event*/
+#define MCPWM_OP0_TEA_INT_ST  (BIT(15))
+#define MCPWM_OP0_TEA_INT_ST_M  (BIT(15))
+#define MCPWM_OP0_TEA_INT_ST_V  0x1
+#define MCPWM_OP0_TEA_INT_ST_S  15
+/* MCPWM_FAULT2_CLR_INT_ST : RO ;bitpos:[14] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered when event_f2 ends*/
+#define MCPWM_FAULT2_CLR_INT_ST  (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_ST_M  (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_ST_V  0x1
+#define MCPWM_FAULT2_CLR_INT_ST_S  14
+/* MCPWM_FAULT1_CLR_INT_ST : RO ;bitpos:[13] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered when event_f1 ends*/
+#define MCPWM_FAULT1_CLR_INT_ST  (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_ST_M  (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_ST_V  0x1
+#define MCPWM_FAULT1_CLR_INT_ST_S  13
+/* MCPWM_FAULT0_CLR_INT_ST : RO ;bitpos:[12] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered when event_f0 ends*/
+#define MCPWM_FAULT0_CLR_INT_ST  (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_ST_M  (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_ST_V  0x1
+#define MCPWM_FAULT0_CLR_INT_ST_S  12
+/* MCPWM_FAULT2_INT_ST : RO ;bitpos:[11] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered when event_f2 starts*/
+#define MCPWM_FAULT2_INT_ST  (BIT(11))
+#define MCPWM_FAULT2_INT_ST_M  (BIT(11))
+#define MCPWM_FAULT2_INT_ST_V  0x1
+#define MCPWM_FAULT2_INT_ST_S  11
+/* MCPWM_FAULT1_INT_ST : RO ;bitpos:[10] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered when event_f1 starts*/
+#define MCPWM_FAULT1_INT_ST  (BIT(10))
+#define MCPWM_FAULT1_INT_ST_M  (BIT(10))
+#define MCPWM_FAULT1_INT_ST_V  0x1
+#define MCPWM_FAULT1_INT_ST_S  10
+/* MCPWM_FAULT0_INT_ST : RO ;bitpos:[9] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered when event_f0 starts*/
+#define MCPWM_FAULT0_INT_ST  (BIT(9))
+#define MCPWM_FAULT0_INT_ST_M  (BIT(9))
+#define MCPWM_FAULT0_INT_ST_V  0x1
+#define MCPWM_FAULT0_INT_ST_S  9
+/* MCPWM_TIMER2_TEP_INT_ST : RO ;bitpos:[8] ;default: 1'h0 ; */
+/*description: The masked status bit for interrupt triggered by a PWM timer 2 TEP event*/
+#define MCPWM_TIMER2_TEP_INT_ST  (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_ST_M  (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_ST_V  0x1
+#define MCPWM_TIMER2_TEP_INT_ST_S  8
+/* MCPWM_TIMER1_TEP_INT_ST : RO ;bitpos:[7] ;default: 1'h0 ; */
+/*description: The masked status bit for interrupt triggered by a PWM timer 1 TEP event*/
+#define MCPWM_TIMER1_TEP_INT_ST  (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_ST_M  (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_ST_V  0x1
+#define MCPWM_TIMER1_TEP_INT_ST_S  7
+/* MCPWM_TIMER0_TEP_INT_ST : RO ;bitpos:[6] ;default: 1'h0 ; */
+/*description: The masked status bit for interrupt triggered by a PWM timer 0 TEP event*/
+#define MCPWM_TIMER0_TEP_INT_ST  (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_ST_M  (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_ST_V  0x1
+#define MCPWM_TIMER0_TEP_INT_ST_S  6
+/* MCPWM_TIMER2_TEZ_INT_ST : RO ;bitpos:[5] ;default: 1'h0 ; */
+/*description: The masked status bit for interrupt triggered by a PWM timer 2 TEZ event*/
+#define MCPWM_TIMER2_TEZ_INT_ST  (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_ST_M  (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_ST_V  0x1
+#define MCPWM_TIMER2_TEZ_INT_ST_S  5
+/* MCPWM_TIMER1_TEZ_INT_ST : RO ;bitpos:[4] ;default: 1'h0 ; */
+/*description: The masked status bit for interrupt triggered by a PWM timer 1 TEZ event*/
+#define MCPWM_TIMER1_TEZ_INT_ST  (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_ST_M  (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_ST_V  0x1
+#define MCPWM_TIMER1_TEZ_INT_ST_S  4
+/* MCPWM_TIMER0_TEZ_INT_ST : RO ;bitpos:[3] ;default: 1'h0 ; */
+/*description: The masked status bit for interrupt triggered by a PWM timer 0 TEZ event*/
+#define MCPWM_TIMER0_TEZ_INT_ST  (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_ST_M  (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_ST_V  0x1
+#define MCPWM_TIMER0_TEZ_INT_ST_S  3
+/* MCPWM_TIMER2_STOP_INT_ST : RO ;bitpos:[2] ;default: 1'h0 ; */
+/*description: The masked status bit for interrupt triggered when timer 2 stops*/
+#define MCPWM_TIMER2_STOP_INT_ST  (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_ST_M  (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_ST_V  0x1
+#define MCPWM_TIMER2_STOP_INT_ST_S  2
+/* MCPWM_TIMER1_STOP_INT_ST : RO ;bitpos:[1] ;default: 1'h0 ; */
+/*description: The masked status bit for interrupt triggered when timer 1 stops*/
+#define MCPWM_TIMER1_STOP_INT_ST  (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_ST_M  (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_ST_V  0x1
+#define MCPWM_TIMER1_STOP_INT_ST_S  1
+/* MCPWM_TIMER0_STOP_INT_ST : RO ;bitpos:[0] ;default: 1'h0 ; */
+/*description: The masked status bit for interrupt triggered when timer 0 stops*/
+#define MCPWM_TIMER0_STOP_INT_ST  (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_ST_M  (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_ST_V  0x1
+#define MCPWM_TIMER0_STOP_INT_ST_S  0
+
+#define MCMCPWM_INT_CLR_MCPWM_REG(i)          (REG_MCPWM_BASE(i) + 0x011c)
+/* MCPWM_CAP2_INT_CLR : WO ;bitpos:[29] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by captureon channel 2*/
+#define MCPWM_CAP2_INT_CLR  (BIT(29))
+#define MCPWM_CAP2_INT_CLR_M  (BIT(29))
+#define MCPWM_CAP2_INT_CLR_V  0x1
+#define MCPWM_CAP2_INT_CLR_S  29
+/* MCPWM_CAP1_INT_CLR : WO ;bitpos:[28] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by captureon channel 1*/
+#define MCPWM_CAP1_INT_CLR  (BIT(28))
+#define MCPWM_CAP1_INT_CLR_M  (BIT(28))
+#define MCPWM_CAP1_INT_CLR_V  0x1
+#define MCPWM_CAP1_INT_CLR_S  28
+/* MCPWM_CAP0_INT_CLR : WO ;bitpos:[27] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by captureon channel 0*/
+#define MCPWM_CAP0_INT_CLR  (BIT(27))
+#define MCPWM_CAP0_INT_CLR_M  (BIT(27))
+#define MCPWM_CAP0_INT_CLR_V  0x1
+#define MCPWM_CAP0_INT_CLR_S  27
+/* MCPWM_FH2_OST_INT_CLR : WO ;bitpos:[26] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by an one-shot mode action on PWM2*/
+#define MCPWM_FH2_OST_INT_CLR  (BIT(26))
+#define MCPWM_FH2_OST_INT_CLR_M  (BIT(26))
+#define MCPWM_FH2_OST_INT_CLR_V  0x1
+#define MCPWM_FH2_OST_INT_CLR_S  26
+/* MCPWM_FH1_OST_INT_CLR : WO ;bitpos:[25] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by an one-shot mode action on PWM0*/
+#define MCPWM_FH1_OST_INT_CLR  (BIT(25))
+#define MCPWM_FH1_OST_INT_CLR_M  (BIT(25))
+#define MCPWM_FH1_OST_INT_CLR_V  0x1
+#define MCPWM_FH1_OST_INT_CLR_S  25
+/* MCPWM_FH0_OST_INT_CLR : WO ;bitpos:[24] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by an one-shot mode action on PWM0*/
+#define MCPWM_FH0_OST_INT_CLR  (BIT(24))
+#define MCPWM_FH0_OST_INT_CLR_M  (BIT(24))
+#define MCPWM_FH0_OST_INT_CLR_V  0x1
+#define MCPWM_FH0_OST_INT_CLR_S  24
+/* MCPWM_FH2_CBC_INT_CLR : WO ;bitpos:[23] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by an cycle-by-cycle
+ mode action on PWM2*/
+#define MCPWM_FH2_CBC_INT_CLR  (BIT(23))
+#define MCPWM_FH2_CBC_INT_CLR_M  (BIT(23))
+#define MCPWM_FH2_CBC_INT_CLR_V  0x1
+#define MCPWM_FH2_CBC_INT_CLR_S  23
+/* MCPWM_FH1_CBC_INT_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by an cycle-by-cycle
+ mode action on PWM1*/
+#define MCPWM_FH1_CBC_INT_CLR  (BIT(22))
+#define MCPWM_FH1_CBC_INT_CLR_M  (BIT(22))
+#define MCPWM_FH1_CBC_INT_CLR_V  0x1
+#define MCPWM_FH1_CBC_INT_CLR_S  22
+/* MCPWM_FH0_CBC_INT_CLR : WO ;bitpos:[21] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by an cycle-by-cycle
+ mode action on PWM0*/
+#define MCPWM_FH0_CBC_INT_CLR  (BIT(21))
+#define MCPWM_FH0_CBC_INT_CLR_M  (BIT(21))
+#define MCPWM_FH0_CBC_INT_CLR_V  0x1
+#define MCPWM_FH0_CBC_INT_CLR_S  21
+/* MCPWM_OP2_TEB_INT_CLR : WO ;bitpos:[20] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by a PWM operator 2 TEB event*/
+#define MCPWM_OP2_TEB_INT_CLR  (BIT(20))
+#define MCPWM_OP2_TEB_INT_CLR_M  (BIT(20))
+#define MCPWM_OP2_TEB_INT_CLR_V  0x1
+#define MCPWM_OP2_TEB_INT_CLR_S  20
+/* MCPWM_OP1_TEB_INT_CLR : WO ;bitpos:[19] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by a PWM operator 1 TEB event*/
+#define MCPWM_OP1_TEB_INT_CLR  (BIT(19))
+#define MCPWM_OP1_TEB_INT_CLR_M  (BIT(19))
+#define MCPWM_OP1_TEB_INT_CLR_V  0x1
+#define MCPWM_OP1_TEB_INT_CLR_S  19
+/* MCPWM_OP0_TEB_INT_CLR : WO ;bitpos:[18] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by a PWM operator 0 TEB event*/
+#define MCPWM_OP0_TEB_INT_CLR  (BIT(18))
+#define MCPWM_OP0_TEB_INT_CLR_M  (BIT(18))
+#define MCPWM_OP0_TEB_INT_CLR_V  0x1
+#define MCPWM_OP0_TEB_INT_CLR_S  18
+/* MCPWM_OP2_TEA_INT_CLR : WO ;bitpos:[17] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by a PWM operator 2 TEA event*/
+#define MCPWM_OP2_TEA_INT_CLR  (BIT(17))
+#define MCPWM_OP2_TEA_INT_CLR_M  (BIT(17))
+#define MCPWM_OP2_TEA_INT_CLR_V  0x1
+#define MCPWM_OP2_TEA_INT_CLR_S  17
+/* MCPWM_OP1_TEA_INT_CLR : WO ;bitpos:[16] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by a PWM operator 1 TEA event*/
+#define MCPWM_OP1_TEA_INT_CLR  (BIT(16))
+#define MCPWM_OP1_TEA_INT_CLR_M  (BIT(16))
+#define MCPWM_OP1_TEA_INT_CLR_V  0x1
+#define MCPWM_OP1_TEA_INT_CLR_S  16
+/* MCPWM_OP0_TEA_INT_CLR : WO ;bitpos:[15] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by a PWM operator 0 TEA event*/
+#define MCPWM_OP0_TEA_INT_CLR  (BIT(15))
+#define MCPWM_OP0_TEA_INT_CLR_M  (BIT(15))
+#define MCPWM_OP0_TEA_INT_CLR_V  0x1
+#define MCPWM_OP0_TEA_INT_CLR_S  15
+/* MCPWM_FAULT2_CLR_INT_CLR : WO ;bitpos:[14] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered when event_f2 ends*/
+#define MCPWM_FAULT2_CLR_INT_CLR  (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_CLR_M  (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_CLR_V  0x1
+#define MCPWM_FAULT2_CLR_INT_CLR_S  14
+/* MCPWM_FAULT1_CLR_INT_CLR : WO ;bitpos:[13] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered when event_f1 ends*/
+#define MCPWM_FAULT1_CLR_INT_CLR  (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_CLR_M  (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_CLR_V  0x1
+#define MCPWM_FAULT1_CLR_INT_CLR_S  13
+/* MCPWM_FAULT0_CLR_INT_CLR : WO ;bitpos:[12] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered when event_f0 ends*/
+#define MCPWM_FAULT0_CLR_INT_CLR  (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_CLR_M  (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_CLR_V  0x1
+#define MCPWM_FAULT0_CLR_INT_CLR_S  12
+/* MCPWM_FAULT2_INT_CLR : WO ;bitpos:[11] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered when event_f2 starts*/
+#define MCPWM_FAULT2_INT_CLR  (BIT(11))
+#define MCPWM_FAULT2_INT_CLR_M  (BIT(11))
+#define MCPWM_FAULT2_INT_CLR_V  0x1
+#define MCPWM_FAULT2_INT_CLR_S  11
+/* MCPWM_FAULT1_INT_CLR : WO ;bitpos:[10] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered when event_f1 starts*/
+#define MCPWM_FAULT1_INT_CLR  (BIT(10))
+#define MCPWM_FAULT1_INT_CLR_M  (BIT(10))
+#define MCPWM_FAULT1_INT_CLR_V  0x1
+#define MCPWM_FAULT1_INT_CLR_S  10
+/* MCPWM_FAULT0_INT_CLR : WO ;bitpos:[9] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered when event_f0 starts*/
+#define MCPWM_FAULT0_INT_CLR  (BIT(9))
+#define MCPWM_FAULT0_INT_CLR_M  (BIT(9))
+#define MCPWM_FAULT0_INT_CLR_V  0x1
+#define MCPWM_FAULT0_INT_CLR_S  9
+/* MCPWM_TIMER2_TEP_INT_CLR : WO ;bitpos:[8] ;default: 1'h0 ; */
+/*description: Set this bit to clear interrupt triggered by a PWM timer 2 TEP event*/
+#define MCPWM_TIMER2_TEP_INT_CLR  (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_CLR_M  (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_CLR_V  0x1
+#define MCPWM_TIMER2_TEP_INT_CLR_S  8
+/* MCPWM_TIMER1_TEP_INT_CLR : WO ;bitpos:[7] ;default: 1'h0 ; */
+/*description: Set this bit to clear interrupt triggered by a PWM timer 1 TEP event*/
+#define MCPWM_TIMER1_TEP_INT_CLR  (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_CLR_M  (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_CLR_V  0x1
+#define MCPWM_TIMER1_TEP_INT_CLR_S  7
+/* MCPWM_TIMER0_TEP_INT_CLR : WO ;bitpos:[6] ;default: 1'h0 ; */
+/*description: Set this bit to clear interrupt triggered by a PWM timer 0 TEP event*/
+#define MCPWM_TIMER0_TEP_INT_CLR  (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_CLR_M  (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_CLR_V  0x1
+#define MCPWM_TIMER0_TEP_INT_CLR_S  6
+/* MCPWM_TIMER2_TEZ_INT_CLR : WO ;bitpos:[5] ;default: 1'h0 ; */
+/*description: Set this bit to clear interrupt triggered by a PWM timer 2 TEZ event*/
+#define MCPWM_TIMER2_TEZ_INT_CLR  (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_CLR_M  (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_CLR_V  0x1
+#define MCPWM_TIMER2_TEZ_INT_CLR_S  5
+/* MCPWM_TIMER1_TEZ_INT_CLR : WO ;bitpos:[4] ;default: 1'h0 ; */
+/*description: Set this bit to clear interrupt triggered by a PWM timer 1 TEZ event*/
+#define MCPWM_TIMER1_TEZ_INT_CLR  (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_CLR_M  (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_CLR_V  0x1
+#define MCPWM_TIMER1_TEZ_INT_CLR_S  4
+/* MCPWM_TIMER0_TEZ_INT_CLR : WO ;bitpos:[3] ;default: 1'h0 ; */
+/*description: Set this bit to clear interrupt triggered by a PWM timer 0 TEZ event*/
+#define MCPWM_TIMER0_TEZ_INT_CLR  (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_CLR_M  (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_CLR_V  0x1
+#define MCPWM_TIMER0_TEZ_INT_CLR_S  3
+/* MCPWM_TIMER2_STOP_INT_CLR : WO ;bitpos:[2] ;default: 1'h0 ; */
+/*description: Set this bit to clear interrupt triggered when timer 2 stops*/
+#define MCPWM_TIMER2_STOP_INT_CLR  (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_CLR_M  (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_CLR_V  0x1
+#define MCPWM_TIMER2_STOP_INT_CLR_S  2
+/* MCPWM_TIMER1_STOP_INT_CLR : WO ;bitpos:[1] ;default: 1'h0 ; */
+/*description: Set this bit to clear interrupt triggered when timer 1 stops*/
+#define MCPWM_TIMER1_STOP_INT_CLR  (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_CLR_M  (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_CLR_V  0x1
+#define MCPWM_TIMER1_STOP_INT_CLR_S  1
+/* MCPWM_TIMER0_STOP_INT_CLR : WO ;bitpos:[0] ;default: 1'h0 ; */
+/*description: Set this bit to clear interrupt triggered when timer 0 stops*/
+#define MCPWM_TIMER0_STOP_INT_CLR  (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_CLR_M  (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_CLR_V  0x1
+#define MCPWM_TIMER0_STOP_INT_CLR_S  0
+
+#define MCPWM_CLK_REG(i)          (REG_MCPWM_BASE(i) + 0x0120)
+/* MCPWM_CLK_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: Force clock on for this reg file*/
+#define MCPWM_CLK_EN  (BIT(0))
+#define MCPWM_CLK_EN_M  (BIT(0))
+#define MCPWM_CLK_EN_V  0x1
+#define MCPWM_CLK_EN_S  0
+
+#define MCPWM_VERSION_REG(i)          (REG_MCPWM_BASE(i) + 0x0124)
+/* MCPWM_DATE : R/W ;bitpos:[27:0] ;default: 28'h1509110 ; */
+/*description: Version of this reg file*/
+#define MCPWM_DATE  0x0FFFFFFF
+#define MCPWM_DATE_M  ((MCPWM_DATE_V)<<(MCPWM_DATE_S))
+#define MCPWM_DATE_V  0xFFFFFFF
+#define MCPWM_DATE_S  0
+
+
+
+
+#endif /*_SOC_MCPWM_REG_H_ */
+
+
diff --git a/tools/sdk/include/soc/soc/mcpwm_struct.h b/tools/sdk/include/soc/soc/mcpwm_struct.h
new file mode 100644
index 00000000..4d49e504
--- /dev/null
+++ b/tools/sdk/include/soc/soc/mcpwm_struct.h
@@ -0,0 +1,452 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_MCPWM_STRUCT_H__
+#define _SOC_MCPWM_STRUCT_H__
+typedef volatile struct {
+    union {
+        struct {
+            uint32_t prescale: 8;                  /*Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)*/
+            uint32_t reserved8:   24;
+        };
+        uint32_t val;
+    }clk_cfg;
+    struct {
+        union {
+            struct {
+                uint32_t prescale:        8;        /*period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1)*/
+                uint32_t period:         16;        /*period shadow reg of PWM timer0*/
+                uint32_t upmethod: 2;        /*Update method for active reg of PWM timer0 period  0: immediate  1: TEZ  2: sync  3: TEZ | sync. TEZ here and below means timer equal zero event*/
+                uint32_t reserved26:      6;
+            };
+            uint32_t val;
+        }period;
+        union {
+            struct {
+                uint32_t start: 3;                  /*PWM timer0 start and stop control. 0: stop @ TEZ  1: stop @ TEP  2: free run  3: start and stop @ next TEZ  4: start and stop @ next TEP. TEP here and below means timer equal period event*/
+                uint32_t mode:   2;                  /*PWM timer0 working mode  0: freeze  1: increase mod  2: decrease mod  3: up-down mod*/
+                uint32_t reserved5:   27;
+            };
+            uint32_t val;
+        }mode;
+        union {
+            struct {
+                uint32_t in_en:     1;              /*when set   timer reload with phase on sync input event is enabled*/
+                uint32_t sync_sw:   1;              /*write the negate value will trigger a software sync*/
+                uint32_t out_sel: 2;              /*PWM timer0 synco selection  0: synci  1: TEZ  2: TEP  else 0*/
+                uint32_t timer_phase:    17;              /*phase for timer reload on sync event*/
+                uint32_t reserved21:      11;
+            };
+            uint32_t val;
+        }sync;
+        union {
+            struct {
+                uint32_t value:    16;              /*current PWM timer0 counter value*/
+                uint32_t direction: 1;              /*current PWM timer0 counter direction  0: increment 1: decrement*/
+                uint32_t reserved17:      15;
+            };
+            uint32_t val;
+        }status;
+    }timer[3];
+
+
+    union {
+        struct {
+            uint32_t t0_in_sel:   3;        /*select sync input for PWM timer0  1: PWM timer0 synco  2: PWM timer1 synco  3: PWM timer2 synco  4: SYNC0 from GPIO matrix  5: SYNC1 from GPIO matrix  6: SYNC2 from GPIO matrix  else: none*/
+            uint32_t t1_in_sel:   3;        /*select sync input for PWM timer1  1: PWM timer0 synco  2: PWM timer1 synco  3: PWM timer2 synco  4: SYNC0 from GPIO matrix  5: SYNC1 from GPIO matrix  6: SYNC2 from GPIO matrix  else: none*/
+            uint32_t t2_in_sel:   3;        /*select sync input for PWM timer2  1: PWM timer0 synco  2: PWM timer1 synco  3: PWM timer2 synco  4: SYNC0 from GPIO matrix  5: SYNC1 from GPIO matrix  6: SYNC2 from GPIO matrix  else: none*/
+            uint32_t ext_in0_inv: 1;        /*invert SYNC0 from GPIO matrix*/
+            uint32_t ext_in1_inv: 1;        /*invert SYNC1 from GPIO matrix*/
+            uint32_t ext_in2_inv: 1;        /*invert SYNC2 from GPIO matrix*/
+            uint32_t reserved12:            20;
+        };
+        uint32_t val;
+    }timer_synci_cfg;
+    union {
+        struct {
+            uint32_t operator0_sel: 2;            /*Select which PWM timer's is the timing reference for PWM operator0  0: timer0  1: timer1  2: timer2*/
+            uint32_t operator1_sel: 2;            /*Select which PWM timer's is the timing reference for PWM operator1  0: timer0  1: timer1  2: timer2*/
+            uint32_t operator2_sel: 2;            /*Select which PWM timer's is the timing reference for PWM operator2  0: timer0  1: timer1  2: timer2*/
+            uint32_t reserved6:         26;
+        };
+        uint32_t val;
+    }timer_sel;
+
+
+    struct {
+        union {
+            struct {
+                uint32_t a_upmethod:  4;             /*Update method for PWM compare0 A's active reg. 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync  bit3: freeze*/
+                uint32_t b_upmethod:  4;             /*Update method for PWM compare0 B's active reg. 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync  bit3: freeze*/
+                uint32_t a_shdw_full: 1;             /*Set and reset by hardware. If set  PWM compare0 A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared  A's active reg has been updated with shadow reg latest value*/
+                uint32_t b_shdw_full: 1;             /*Set and reset by hardware. If set  PWM compare0 B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared  B's active reg has been updated with shadow reg latest value*/
+                uint32_t reserved10:       22;
+            };
+            uint32_t val;
+        }cmpr_cfg;
+        union {
+            struct {
+                uint32_t cmpr_val:       16;                    /*PWM compare0 A's shadow reg*/
+                uint32_t reserved16:16;
+            };
+            uint32_t val;
+        }cmpr_value[2];
+        union {
+            struct {
+                uint32_t upmethod: 4;             /*Update method for PWM generate0's active reg of configuration. 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync. bit3: freeze*/
+                uint32_t t0_sel:       3;             /*Source selection for PWM generate0 event_t0  take effect immediately  0: fault_event0  1: fault_event1  2: fault_event2  3: sync_taken  4: none*/
+                uint32_t t1_sel:       3;             /*Source selection for PWM generate0 event_t1  take effect immediately  0: fault_event0  1: fault_event1  2: fault_event2  3: sync_taken  4: none*/
+                uint32_t reserved10:       22;
+            };
+            uint32_t val;
+        }gen_cfg0;
+        union {
+            struct {
+                uint32_t cntu_force_upmethod: 6;       /*Update method for continuous software force of PWM generate0. 0: immediate  bit0: TEZ  bit1: TEP  bit2: TEA  bit3: TEB  bit4: sync  bit5: freeze. (TEA/B here and below means timer equals A/B event)*/
+                uint32_t a_cntuforce_mode:   2;       /*Continuous software force mode for PWM0A. 0: disabled  1: low  2: high  3: disabled*/
+                uint32_t b_cntuforce_mode:   2;       /*Continuous software force mode for PWM0B. 0: disabled  1: low  2: high  3: disabled*/
+                uint32_t a_nciforce:         1;       /*non-continuous immediate software force trigger for PWM0A  a toggle will trigger a force event*/
+                uint32_t a_nciforce_mode:    2;       /*non-continuous immediate software force mode for PWM0A  0: disabled  1: low  2: high  3: disabled*/
+                uint32_t b_nciforce:         1;       /*non-continuous immediate software force trigger for PWM0B  a toggle will trigger a force event*/
+                uint32_t b_nciforce_mode:    2;       /*non-continuous immediate software force mode for PWM0B  0: disabled  1: low  2: high  3: disabled*/
+                uint32_t reserved16:             16;
+            };
+            uint32_t val;
+        }gen_force;
+        union {
+            struct {
+                uint32_t utez: 2;                   /*Action on PWM0A triggered by event TEZ when timer increasing*/
+                uint32_t utep: 2;                   /*Action on PWM0A triggered by event TEP when timer increasing*/
+                uint32_t utea: 2;                   /*Action on PWM0A triggered by event TEA when timer increasing*/
+                uint32_t uteb: 2;                   /*Action on PWM0A triggered by event TEB when timer increasing*/
+                uint32_t ut0:  2;                   /*Action on PWM0A triggered by event_t0 when timer increasing*/
+                uint32_t ut1:  2;                   /*Action on PWM0A triggered by event_t1 when timer increasing*/
+                uint32_t dtez: 2;                   /*Action on PWM0A triggered by event TEZ when timer decreasing*/
+                uint32_t dtep: 2;                   /*Action on PWM0A triggered by event TEP when timer decreasing*/
+                uint32_t dtea: 2;                   /*Action on PWM0A triggered by event TEA when timer decreasing*/
+                uint32_t dteb: 2;                   /*Action on PWM0A triggered by event TEB when timer decreasing*/
+                uint32_t dt0:  2;                   /*Action on PWM0A triggered by event_t0 when timer decreasing*/
+                uint32_t dt1:  2;                   /*Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change  1: low  2: high  3: toggle*/
+                uint32_t reserved24:  8;
+            };
+            uint32_t val;
+        }generator[2];
+        union {
+            struct {
+                uint32_t fed_upmethod:  4;             /*Update method for FED (falling edge delay) active reg. 0: immediate  bit0: tez  bit1: tep  bit2: sync  bit3: freeze*/
+                uint32_t red_upmethod:  4;             /*Update method for RED (rising edge delay) active reg. 0: immediate  bit0: tez  bit1: tep  bit2: sync  bit3: freeze*/
+                uint32_t deb_mode:      1;             /*S8 in documentation  dual-edge B mode  0: fed/red take effect on different path separately  1: fed/red take effect on B path  A out is in bypass or dulpB mode*/
+                uint32_t a_outswap:     1;             /*S6 in documentation*/
+                uint32_t b_outswap:     1;             /*S7 in documentation*/
+                uint32_t red_insel:     1;             /*S4 in documentation*/
+                uint32_t fed_insel:     1;             /*S5 in documentation*/
+                uint32_t red_outinvert: 1;             /*S2 in documentation*/
+                uint32_t fed_outinvert: 1;             /*S3 in documentation*/
+                uint32_t a_outbypass:   1;             /*S1 in documentation*/
+                uint32_t b_outbypass:   1;             /*S0 in documentation*/
+                uint32_t clk_sel:       1;             /*Dead band0 clock selection. 0: PWM_clk  1: PT_clk*/
+                uint32_t reserved18:   14;
+            };
+            uint32_t val;
+        }db_cfg;
+        union {
+            struct {
+                uint32_t fed:   16;                    /*Shadow reg for FED*/
+                uint32_t reserved16:16;
+            };
+            uint32_t val;
+        }db_fed_cfg;
+        union {
+            struct {
+                uint32_t red:   16;                    /*Shadow reg for RED*/
+                uint32_t reserved16:16;
+            };
+            uint32_t val;
+        }db_red_cfg;
+        union {
+            struct {
+                uint32_t en:         1;           /*When set  carrier0 function is enabled. When reset  carrier0 is bypassed*/
+                uint32_t prescale:   4;           /*carrier0 clk (CP_clk) prescale value. Period of CP_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)*/
+                uint32_t duty:       3;           /*carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8*/
+                uint32_t oshtwth:    4;           /*width of the fist pulse in number of periods of the carrier*/
+                uint32_t out_invert: 1;           /*when set  invert the output of PWM0A and PWM0B for this submodule*/
+                uint32_t in_invert:  1;           /*when set  invert the input of PWM0A and PWM0B for this submodule*/
+                uint32_t reserved14:         18;
+            };
+            uint32_t val;
+        }carrier_cfg;
+        union {
+            struct {
+                uint32_t sw_cbc:  1;                   /*Cycle-by-cycle tripping software force event will trigger cycle-by-cycle trip event. 0: disable  1: enable*/
+                uint32_t f2_cbc:  1;                   /*event_f2 will trigger cycle-by-cycle trip event. 0: disable  1: enable*/
+                uint32_t f1_cbc:  1;                   /*event_f1 will trigger cycle-by-cycle trip event. 0: disable  1: enable*/
+                uint32_t f0_cbc:  1;                   /*event_f0 will trigger cycle-by-cycle trip event. 0: disable  1: enable*/
+                uint32_t sw_ost:  1;                   /*one-shot tripping software force event will trigger one-shot trip event. 0: disable  1: enable*/
+                uint32_t f2_ost:  1;                   /*event_f2 will trigger one-shot trip event. 0: disable  1: enable*/
+                uint32_t f1_ost:  1;                   /*event_f1 will trigger one-shot trip event. 0: disable  1: enable*/
+                uint32_t f0_ost:  1;                   /*event_f0 will trigger one-shot trip event. 0: disable  1: enable*/
+                uint32_t a_cbc_d: 2;                   /*Action on PWM0A when cycle-by-cycle trip event occurs and timer is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+                uint32_t a_cbc_u: 2;                   /*Action on PWM0A when cycle-by-cycle trip event occurs and timer is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+                uint32_t a_ost_d: 2;                   /*Action on PWM0A when one-shot trip event occurs and timer is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+                uint32_t a_ost_u: 2;                   /*Action on PWM0A when one-shot trip event occurs and timer is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+                uint32_t b_cbc_d: 2;                   /*Action on PWM0B when cycle-by-cycle trip event occurs and timer is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+                uint32_t b_cbc_u: 2;                   /*Action on PWM0B when cycle-by-cycle trip event occurs and timer is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+                uint32_t b_ost_d: 2;                   /*Action on PWM0B when one-shot trip event occurs and timer is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+                uint32_t b_ost_u: 2;                   /*Action on PWM0B when one-shot trip event occurs and timer is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+                uint32_t reserved24:  8;
+            };
+            uint32_t val;
+        }tz_cfg0;
+        union {
+            struct {
+                uint32_t clr_ost:   1;                 /*a toggle will clear on going one-shot tripping*/
+                uint32_t cbcpulse:  2;                 /*cycle-by-cycle tripping refresh moment selection. Bit0: TEZ  bit1:TEP*/
+                uint32_t force_cbc: 1;                 /*a toggle trigger a cycle-by-cycle tripping software force event*/
+                uint32_t force_ost: 1;                 /*a toggle (software negate its value) trigger a one-shot tripping software force event*/
+                uint32_t reserved5:    27;
+            };
+            uint32_t val;
+        }tz_cfg1;
+        union {
+            struct {
+                uint32_t cbc_on: 1;                    /*Set and reset by hardware. If set  an cycle-by-cycle trip event is on going*/
+                uint32_t ost_on: 1;                    /*Set and reset by hardware. If set  an one-shot trip event is on going*/
+                uint32_t reserved2: 30;
+            };
+            uint32_t val;
+        }tz_status;
+    }channel[3];
+
+    union {
+        struct {
+            uint32_t f0_en:      1;                    /*When set  event_f0 generation is enabled*/
+            uint32_t f1_en:      1;                    /*When set  event_f1 generation is enabled*/
+            uint32_t f2_en:      1;                    /*When set  event_f2 generation is enabled*/
+            uint32_t f0_pole:    1;                    /*Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low  1: level high*/
+            uint32_t f1_pole:    1;                    /*Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low  1: level high*/
+            uint32_t f2_pole:    1;                    /*Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low  1: level high*/
+            uint32_t event_f0:   1;                    /*Set and reset by hardware. If set  event_f0 is on going*/
+            uint32_t event_f1:   1;                    /*Set and reset by hardware. If set  event_f1 is on going*/
+            uint32_t event_f2:   1;                    /*Set and reset by hardware. If set  event_f2 is on going*/
+            uint32_t reserved9: 23;
+        };
+        uint32_t val;
+    }fault_detect;
+    union {
+        struct {
+            uint32_t timer_en:  1;                 /*When set  capture timer incrementing under APB_clk is enabled.*/
+            uint32_t synci_en:  1;                 /*When set  capture timer sync is enabled.*/
+            uint32_t synci_sel: 3;                 /*capture module sync input selection. 0: none  1: timer0 synco  2: timer1 synco  3: timer2 synco  4: SYNC0 from GPIO matrix  5: SYNC1 from GPIO matrix  6: SYNC2 from GPIO matrix*/
+            uint32_t sync_sw:   1;                 /*Write 1 will force a capture timer sync  capture timer is loaded with value in phase register.*/
+            uint32_t reserved6:    26;
+        };
+        uint32_t val;
+    }cap_timer_cfg;
+    uint32_t cap_timer_phase;                      /*Phase value for capture timer sync operation.*/
+    union {
+        struct {
+            uint32_t en:        1;                /*When set  capture on channel 0 is enabled*/
+            uint32_t mode:      2;                /*Edge of capture on channel 0 after prescale.  bit0: negedge cap en  bit1: posedge cap en*/
+            uint32_t prescale:  8;                /*Value of prescale on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + 1*/
+            uint32_t in_invert: 1;                /*when set  CAP0 form GPIO matrix is inverted before prescale*/
+            uint32_t sw:        1;                /*Write 1 will trigger a software forced capture on channel 0*/
+            uint32_t reserved13:    19;
+        };
+        uint32_t val;
+    }cap_cfg_ch[3];
+    uint32_t cap_val_ch[3];                              /*Value of last capture on channel 0*/
+    union {
+        struct {
+            uint32_t cap0_edge:  1;                    /*Edge of last capture trigger on channel 0  0: posedge  1: negedge*/
+            uint32_t cap1_edge:  1;                    /*Edge of last capture trigger on channel 1  0: posedge  1: negedge*/
+            uint32_t cap2_edge:  1;                    /*Edge of last capture trigger on channel 2  0: posedge  1: negedge*/
+            uint32_t reserved3: 29;
+        };
+        uint32_t val;
+    }cap_status;
+    union {
+        struct {
+            uint32_t global_up_en:    1;               /*The global enable of update of all active registers in MCPWM module*/
+            uint32_t global_force_up: 1;               /*a toggle (software invert its value) will trigger a forced update of all active registers in MCPWM module*/
+            uint32_t op0_up_en:       1;               /*When set and PWM_GLOBAL_UP_EN is set  update of active registers in PWM operator 0 are enabled*/
+            uint32_t op0_force_up:    1;               /*a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 0*/
+            uint32_t op1_up_en:       1;               /*When set and PWM_GLOBAL_UP_EN is set  update of active registers in PWM operator 1 are enabled*/
+            uint32_t op1_force_up:    1;               /*a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 1*/
+            uint32_t op2_up_en:       1;               /*When set and PWM_GLOBAL_UP_EN is set  update of active registers in PWM operator 2 are enabled*/
+            uint32_t op2_force_up:    1;               /*a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 2*/
+            uint32_t reserved8:      24;
+        };
+        uint32_t val;
+    }update_cfg;
+    union {
+        struct {
+            uint32_t timer0_stop_int_ena: 1;           /*Interrupt when timer 0 stops*/
+            uint32_t timer1_stop_int_ena: 1;           /*Interrupt when timer 1 stops*/
+            uint32_t timer2_stop_int_ena: 1;           /*Interrupt when timer 2 stops*/
+            uint32_t timer0_tez_int_ena:  1;           /*A PWM timer 0 TEZ event will trigger this interrupt*/
+            uint32_t timer1_tez_int_ena:  1;           /*A PWM timer 1 TEZ event will trigger this interrupt*/
+            uint32_t timer2_tez_int_ena:  1;           /*A PWM timer 2 TEZ event will trigger this interrupt*/
+            uint32_t timer0_tep_int_ena:  1;           /*A PWM timer 0 TEP event will trigger this interrupt*/
+            uint32_t timer1_tep_int_ena:  1;           /*A PWM timer 1 TEP event will trigger this interrupt*/
+            uint32_t timer2_tep_int_ena:  1;           /*A PWM timer 2 TEP event will trigger this interrupt*/
+            uint32_t fault0_int_ena:      1;           /*Interrupt when event_f0 starts*/
+            uint32_t fault1_int_ena:      1;           /*Interrupt when event_f1 starts*/
+            uint32_t fault2_int_ena:      1;           /*Interrupt when event_f2 starts*/
+            uint32_t fault0_clr_int_ena:  1;           /*Interrupt when event_f0 ends*/
+            uint32_t fault1_clr_int_ena:  1;           /*Interrupt when event_f1 ends*/
+            uint32_t fault2_clr_int_ena:  1;           /*Interrupt when event_f2 ends*/
+            uint32_t cmpr0_tea_int_ena:   1;           /*A PWM operator 0 TEA event will trigger this interrupt*/
+            uint32_t cmpr1_tea_int_ena:   1;           /*A PWM operator 1 TEA event will trigger this interrupt*/
+            uint32_t cmpr2_tea_int_ena:   1;           /*A PWM operator 2 TEA event will trigger this interrupt*/
+            uint32_t cmpr0_teb_int_ena:   1;           /*A PWM operator 0 TEB event will trigger this interrupt*/
+            uint32_t cmpr1_teb_int_ena:   1;           /*A PWM operator 1 TEB event will trigger this interrupt*/
+            uint32_t cmpr2_teb_int_ena:   1;           /*A PWM operator 2 TEB event will trigger this interrupt*/
+            uint32_t tz0_cbc_int_ena:     1;           /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/
+            uint32_t tz1_cbc_int_ena:     1;           /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/
+            uint32_t tz2_cbc_int_ena:     1;           /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/
+            uint32_t tz0_ost_int_ena:     1;           /*An one-shot trip event on PWM0 will trigger this interrupt*/
+            uint32_t tz1_ost_int_ena:     1;           /*An one-shot trip event on PWM1 will trigger this interrupt*/
+            uint32_t tz2_ost_int_ena:     1;           /*An one-shot trip event on PWM2 will trigger this interrupt*/
+            uint32_t cap0_int_ena:        1;           /*A capture on channel 0 will trigger this interrupt*/
+            uint32_t cap1_int_ena:        1;           /*A capture on channel 1 will trigger this interrupt*/
+            uint32_t cap2_int_ena:        1;           /*A capture on channel 2 will trigger this interrupt*/
+            uint32_t reserved30:          2;
+        };
+        uint32_t val;
+    }int_ena;
+    union {
+        struct {
+            uint32_t timer0_stop_int_raw: 1;           /*Interrupt when timer 0 stops*/
+            uint32_t timer1_stop_int_raw: 1;           /*Interrupt when timer 1 stops*/
+            uint32_t timer2_stop_int_raw: 1;           /*Interrupt when timer 2 stops*/
+            uint32_t timer0_tez_int_raw:  1;           /*A PWM timer 0 TEZ event will trigger this interrupt*/
+            uint32_t timer1_tez_int_raw:  1;           /*A PWM timer 1 TEZ event will trigger this interrupt*/
+            uint32_t timer2_tez_int_raw:  1;           /*A PWM timer 2 TEZ event will trigger this interrupt*/
+            uint32_t timer0_tep_int_raw:  1;           /*A PWM timer 0 TEP event will trigger this interrupt*/
+            uint32_t timer1_tep_int_raw:  1;           /*A PWM timer 1 TEP event will trigger this interrupt*/
+            uint32_t timer2_tep_int_raw:  1;           /*A PWM timer 2 TEP event will trigger this interrupt*/
+            uint32_t fault0_int_raw:      1;           /*Interrupt when event_f0 starts*/
+            uint32_t fault1_int_raw:      1;           /*Interrupt when event_f1 starts*/
+            uint32_t fault2_int_raw:      1;           /*Interrupt when event_f2 starts*/
+            uint32_t fault0_clr_int_raw:  1;           /*Interrupt when event_f0 ends*/
+            uint32_t fault1_clr_int_raw:  1;           /*Interrupt when event_f1 ends*/
+            uint32_t fault2_clr_int_raw:  1;           /*Interrupt when event_f2 ends*/
+            uint32_t cmpr0_tea_int_raw:   1;           /*A PWM operator 0 TEA event will trigger this interrupt*/
+            uint32_t cmpr1_tea_int_raw:   1;           /*A PWM operator 1 TEA event will trigger this interrupt*/
+            uint32_t cmpr2_tea_int_raw:   1;           /*A PWM operator 2 TEA event will trigger this interrupt*/
+            uint32_t cmpr0_teb_int_raw:   1;           /*A PWM operator 0 TEB event will trigger this interrupt*/
+            uint32_t cmpr1_teb_int_raw:   1;           /*A PWM operator 1 TEB event will trigger this interrupt*/
+            uint32_t cmpr2_teb_int_raw:   1;           /*A PWM operator 2 TEB event will trigger this interrupt*/
+            uint32_t tz0_cbc_int_raw:     1;           /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/
+            uint32_t tz1_cbc_int_raw:     1;           /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/
+            uint32_t tz2_cbc_int_raw:     1;           /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/
+            uint32_t tz0_ost_int_raw:     1;           /*An one-shot trip event on PWM0 will trigger this interrupt*/
+            uint32_t tz1_ost_int_raw:     1;           /*An one-shot trip event on PWM1 will trigger this interrupt*/
+            uint32_t tz2_ost_int_raw:     1;           /*An one-shot trip event on PWM2 will trigger this interrupt*/
+            uint32_t cap0_int_raw:        1;           /*A capture on channel 0 will trigger this interrupt*/
+            uint32_t cap1_int_raw:        1;           /*A capture on channel 1 will trigger this interrupt*/
+            uint32_t cap2_int_raw:        1;           /*A capture on channel 2 will trigger this interrupt*/
+            uint32_t reserved30:          2;
+        };
+        uint32_t val;
+    }int_raw;
+    union {
+        struct {
+            uint32_t timer0_stop_int_st: 1;            /*Interrupt when timer 0 stops*/
+            uint32_t timer1_stop_int_st: 1;            /*Interrupt when timer 1 stops*/
+            uint32_t timer2_stop_int_st: 1;            /*Interrupt when timer 2 stops*/
+            uint32_t timer0_tez_int_st:  1;            /*A PWM timer 0 TEZ event will trigger this interrupt*/
+            uint32_t timer1_tez_int_st:  1;            /*A PWM timer 1 TEZ event will trigger this interrupt*/
+            uint32_t timer2_tez_int_st:  1;            /*A PWM timer 2 TEZ event will trigger this interrupt*/
+            uint32_t timer0_tep_int_st:  1;            /*A PWM timer 0 TEP event will trigger this interrupt*/
+            uint32_t timer1_tep_int_st:  1;            /*A PWM timer 1 TEP event will trigger this interrupt*/
+            uint32_t timer2_tep_int_st:  1;            /*A PWM timer 2 TEP event will trigger this interrupt*/
+            uint32_t fault0_int_st:      1;            /*Interrupt when event_f0 starts*/
+            uint32_t fault1_int_st:      1;            /*Interrupt when event_f1 starts*/
+            uint32_t fault2_int_st:      1;            /*Interrupt when event_f2 starts*/
+            uint32_t fault0_clr_int_st:  1;            /*Interrupt when event_f0 ends*/
+            uint32_t fault1_clr_int_st:  1;            /*Interrupt when event_f1 ends*/
+            uint32_t fault2_clr_int_st:  1;            /*Interrupt when event_f2 ends*/
+            uint32_t cmpr0_tea_int_st:   1;            /*A PWM operator 0 TEA event will trigger this interrupt*/
+            uint32_t cmpr1_tea_int_st:   1;            /*A PWM operator 1 TEA event will trigger this interrupt*/
+            uint32_t cmpr2_tea_int_st:   1;            /*A PWM operator 2 TEA event will trigger this interrupt*/
+            uint32_t cmpr0_teb_int_st:   1;            /*A PWM operator 0 TEB event will trigger this interrupt*/
+            uint32_t cmpr1_teb_int_st:   1;            /*A PWM operator 1 TEB event will trigger this interrupt*/
+            uint32_t cmpr2_teb_int_st:   1;            /*A PWM operator 2 TEB event will trigger this interrupt*/
+            uint32_t tz0_cbc_int_st:     1;            /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/
+            uint32_t tz1_cbc_int_st:     1;            /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/
+            uint32_t tz2_cbc_int_st:     1;            /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/
+            uint32_t tz0_ost_int_st:     1;            /*An one-shot trip event on PWM0 will trigger this interrupt*/
+            uint32_t tz1_ost_int_st:     1;            /*An one-shot trip event on PWM1 will trigger this interrupt*/
+            uint32_t tz2_ost_int_st:     1;            /*An one-shot trip event on PWM2 will trigger this interrupt*/
+            uint32_t cap0_int_st:        1;            /*A capture on channel 0 will trigger this interrupt*/
+            uint32_t cap1_int_st:        1;            /*A capture on channel 1 will trigger this interrupt*/
+            uint32_t cap2_int_st:        1;            /*A capture on channel 2 will trigger this interrupt*/
+            uint32_t reserved30:         2;
+        };
+        uint32_t val;
+    }int_st;
+    union {
+        struct {
+            uint32_t timer0_stop_int_clr: 1;           /*Interrupt when timer 0 stops*/
+            uint32_t timer1_stop_int_clr: 1;           /*Interrupt when timer 1 stops*/
+            uint32_t timer2_stop_int_clr: 1;           /*Interrupt when timer 2 stops*/
+            uint32_t timer0_tez_int_clr:  1;           /*A PWM timer 0 TEZ event will trigger this interrupt*/
+            uint32_t timer1_tez_int_clr:  1;           /*A PWM timer 1 TEZ event will trigger this interrupt*/
+            uint32_t timer2_tez_int_clr:  1;           /*A PWM timer 2 TEZ event will trigger this interrupt*/
+            uint32_t timer0_tep_int_clr:  1;           /*A PWM timer 0 TEP event will trigger this interrupt*/
+            uint32_t timer1_tep_int_clr:  1;           /*A PWM timer 1 TEP event will trigger this interrupt*/
+            uint32_t timer2_tep_int_clr:  1;           /*A PWM timer 2 TEP event will trigger this interrupt*/
+            uint32_t fault0_int_clr:      1;           /*Interrupt when event_f0 starts*/
+            uint32_t fault1_int_clr:      1;           /*Interrupt when event_f1 starts*/
+            uint32_t fault2_int_clr:      1;           /*Interrupt when event_f2 starts*/
+            uint32_t fault0_clr_int_clr:  1;           /*Interrupt when event_f0 ends*/
+            uint32_t fault1_clr_int_clr:  1;           /*Interrupt when event_f1 ends*/
+            uint32_t fault2_clr_int_clr:  1;           /*Interrupt when event_f2 ends*/
+            uint32_t cmpr0_tea_int_clr:   1;           /*A PWM operator 0 TEA event will trigger this interrupt*/
+            uint32_t cmpr1_tea_int_clr:   1;           /*A PWM operator 1 TEA event will trigger this interrupt*/
+            uint32_t cmpr2_tea_int_clr:   1;           /*A PWM operator 2 TEA event will trigger this interrupt*/
+            uint32_t cmpr0_teb_int_clr:   1;           /*A PWM operator 0 TEB event will trigger this interrupt*/
+            uint32_t cmpr1_teb_int_clr:   1;           /*A PWM operator 1 TEB event will trigger this interrupt*/
+            uint32_t cmpr2_teb_int_clr:   1;           /*A PWM operator 2 TEB event will trigger this interrupt*/
+            uint32_t tz0_cbc_int_clr:     1;           /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/
+            uint32_t tz1_cbc_int_clr:     1;           /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/
+            uint32_t tz2_cbc_int_clr:     1;           /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/
+            uint32_t tz0_ost_int_clr:     1;           /*An one-shot trip event on PWM0 will trigger this interrupt*/
+            uint32_t tz1_ost_int_clr:     1;           /*An one-shot trip event on PWM1 will trigger this interrupt*/
+            uint32_t tz2_ost_int_clr:     1;           /*An one-shot trip event on PWM2 will trigger this interrupt*/
+            uint32_t cap0_int_clr:        1;           /*A capture on channel 0 will trigger this interrupt*/
+            uint32_t cap1_int_clr:        1;           /*A capture on channel 1 will trigger this interrupt*/
+            uint32_t cap2_int_clr:        1;           /*A capture on channel 2 will trigger this interrupt*/
+            uint32_t reserved30:          2;
+        };
+        uint32_t val;
+    }int_clr;
+    union {
+        struct {
+            uint32_t clk_en:     1;                    /*Force clock on for this reg file*/
+            uint32_t reserved1: 31;
+        };
+        uint32_t val;
+    }reg_clk;
+    union {
+        struct {
+            uint32_t date:      28;                    /*Version of this reg file*/
+            uint32_t reserved28: 4;
+        };
+        uint32_t val;
+    }version;
+} mcpwm_dev_t;
+extern mcpwm_dev_t MCPWM0;
+extern mcpwm_dev_t MCPWM1;
+#endif  /* _SOC_MCPWM_STRUCT_H__ */
diff --git a/tools/sdk/include/soc/soc/soc.h b/tools/sdk/include/soc/soc/soc.h
index 1df888ce..218cdf96 100644
--- a/tools/sdk/include/soc/soc/soc.h
+++ b/tools/sdk/include/soc/soc/soc.h
@@ -17,6 +17,7 @@
 
 #ifndef __ASSEMBLER__
 #include <stdint.h>
+#include "esp_assert.h"
 #endif
 
 //Register Bits{{
@@ -57,98 +58,6 @@
 #define PRO_CPU_NUM (0)
 #define APP_CPU_NUM (1)
 
-//Registers Operation {{
-#define ETS_UNCACHED_ADDR(addr) (addr)
-#define ETS_CACHED_ADDR(addr) (addr) 
-
-#ifndef __ASSEMBLER__
-#define BIT(nr)                 (1UL << (nr))
-#else
-#define BIT(nr)                 (1 << (nr))
-#endif
-
-#ifndef __ASSEMBLER__
-//write value to register
-#define REG_WRITE(_r, _v)    (*(volatile uint32_t *)(_r)) = (_v)
-
-//read value from register
-#define REG_READ(_r) (*(volatile uint32_t *)(_r))
-
-//get bit or get bits from register
-#define REG_GET_BIT(_r, _b)  (*(volatile uint32_t*)(_r) & (_b))
-
-//set bit or set bits to register
-#define REG_SET_BIT(_r, _b)  (*(volatile uint32_t*)(_r) |= (_b))
-
-//clear bit or clear bits of register
-#define REG_CLR_BIT(_r, _b)  (*(volatile uint32_t*)(_r) &= ~(_b))
-
-//set bits of register controlled by mask
-#define REG_SET_BITS(_r, _b, _m) (*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m)))
-
-//get field from register, uses field _S & _V to determine mask
-#define REG_GET_FIELD(_r, _f) ((REG_READ(_r) >> (_f##_S)) & (_f##_V))
-
-//set field of a register from variable, uses field _S & _V to determine mask
-#define REG_SET_FIELD(_r, _f, _v) (REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S)))))
-
-//get field value from a variable, used when _f is not left shifted by _f##_S
-#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
-
-//get field value from a variable, used when _f is left shifted by _f##_S
-#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
-
-//set field value to a variable, used when _f is not left shifted by _f##_S
-#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
-
-//set field value to a variable, used when _f is left shifted by _f##_S
-#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
-
-//generate a value from a field value, used when _f is not left shifted by _f##_S
-#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
-
-//generate a value from a field value, used when _f is left shifted by _f##_S
-#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
-
-//read value from register
-#define READ_PERI_REG(addr) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) 
-
-//write value to register
-#define WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val)   
-
-//clear bits of register controlled by mask
-#define CLEAR_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask))))
-
-//set bits of register controlled by mask
-#define SET_PERI_REG_MASK(reg, mask)   WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask)))
-
-//get bits of register controlled by mask
-#define GET_PERI_REG_MASK(reg, mask)   (READ_PERI_REG(reg) & (mask))
-
-//get bits of register controlled by highest bit and lowest bit
-#define GET_PERI_REG_BITS(reg, hipos,lowpos)      ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
-
-//set bits of register controlled by mask and shift
-#define SET_PERI_REG_BITS(reg,bit_map,value,shift) (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) ))
-
-//get field of register
-#define GET_PERI_REG_BITS2(reg, mask,shift)      ((READ_PERI_REG(reg)>>(shift))&(mask))
-//}}
-
-#endif /* !__ASSEMBLER__ */
-
-//Periheral Clock {{
-#define  APB_CLK_FREQ_ROM                            ( 26*1000000 )
-#define  CPU_CLK_FREQ_ROM                            APB_CLK_FREQ_ROM
-#define  CPU_CLK_FREQ                                APB_CLK_FREQ
-#define  APB_CLK_FREQ                                ( 80*1000000 )       //unit: Hz
-#define  UART_CLK_FREQ                               APB_CLK_FREQ
-#define  WDT_CLK_FREQ                                APB_CLK_FREQ
-#define  TIMER_CLK_FREQ                              (80000000>>4) //80MHz divided by 16
-#define  SPI_CLK_DIV                                 4
-#define  TICKS_PER_US_ROM                            26              // CPU is 80MHz
-//}}
-
 /* Overall memory map */
 #define SOC_IROM_LOW    0x400D0000
 #define SOC_IROM_HIGH   0x40400000
@@ -160,6 +69,7 @@
 #define SOC_RTC_DATA_HIGH 0x50002000
 
 #define DR_REG_DPORT_BASE                       0x3ff00000
+#define DR_REG_DPORT_END                        0x3ff00FFC
 #define DR_REG_RSA_BASE                         0x3ff02000
 #define DR_REG_SHA_BASE                         0x3ff03000
 #define DR_REG_UART_BASE                        0x3ff40000
@@ -210,6 +120,155 @@
 #define DR_REG_PWM3_BASE                        0x3ff70000
 #define PERIPHS_SPI_ENCRYPT_BASEADDR		DR_REG_SPI_ENCRYPT_BASE
 
+//Registers Operation {{
+#define ETS_UNCACHED_ADDR(addr) (addr)
+#define ETS_CACHED_ADDR(addr) (addr) 
+
+#ifndef __ASSEMBLER__
+#define BIT(nr)                 (1UL << (nr))
+#else
+#define BIT(nr)                 (1 << (nr))
+#endif
+
+#ifndef __ASSEMBLER__
+
+#define IS_DPORT_REG(_r) (((_r) >= DR_REG_DPORT_BASE) && (_r) <= DR_REG_DPORT_END)
+
+#if !defined( BOOTLOADER_BUILD ) && !defined( CONFIG_FREERTOS_UNICORE ) && defined( ESP_PLATFORM )
+#define ASSERT_IF_DPORT_REG(_r, OP)  TRY_STATIC_ASSERT(!IS_DPORT_REG(_r), (Cannot use OP for DPORT registers use DPORT_##OP));
+#else
+#define ASSERT_IF_DPORT_REG(_r, OP)
+#endif
+
+//write value to register
+#define REG_WRITE(_r, _v) ({                                                                                           \
+            ASSERT_IF_DPORT_REG(_r, REG_WRITE);                                                                        \
+            (*(volatile uint32_t *)(_r)) = (_v);                                                                       \
+        })
+
+//read value from register
+#define REG_READ(_r) ({                                                                                                \
+            ASSERT_IF_DPORT_REG((_r), REG_READ);                                                                       \
+            (*(volatile uint32_t *)_r);                                                                                \
+        })
+
+//get bit or get bits from register
+#define REG_GET_BIT(_r, _b)  ({                                                                                        \
+            ASSERT_IF_DPORT_REG((_r), REG_GET_BIT);                                                                    \
+            (*(volatile uint32_t*)(_r) & (_b));                                                                        \
+        })
+
+//set bit or set bits to register
+#define REG_SET_BIT(_r, _b)  ({                                                                                        \
+            ASSERT_IF_DPORT_REG((_r), REG_SET_BIT);                                                                    \
+            (*(volatile uint32_t*)(_r) |= (_b));                                                                       \
+        })
+
+//clear bit or clear bits of register
+#define REG_CLR_BIT(_r, _b)  ({                                                                                        \
+            ASSERT_IF_DPORT_REG((_r), REG_CLR_BIT);                                                                    \
+            (*(volatile uint32_t*)(_r) &= ~(_b));                                                                      \
+        })
+
+//set bits of register controlled by mask
+#define REG_SET_BITS(_r, _b, _m) ({                                                                                    \
+            ASSERT_IF_DPORT_REG((_r), REG_SET_BITS);                                                                   \
+            (*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m)));                         \
+        })
+
+//get field from register, uses field _S & _V to determine mask
+#define REG_GET_FIELD(_r, _f) ({                                                                                       \
+            ASSERT_IF_DPORT_REG((_r), REG_GET_FIELD);                                                                  \
+            ((REG_READ(_r) >> (_f##_S)) & (_f##_V));                                                                   \
+        })
+
+//set field of a register from variable, uses field _S & _V to determine mask
+#define REG_SET_FIELD(_r, _f, _v) ({                                                                                   \
+            ASSERT_IF_DPORT_REG((_r), REG_SET_FIELD);                                                                  \
+            (REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S)))));                \
+        })
+
+//get field value from a variable, used when _f is not left shifted by _f##_S
+#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
+
+//get field value from a variable, used when _f is left shifted by _f##_S
+#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
+
+//set field value to a variable, used when _f is not left shifted by _f##_S
+#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
+
+//set field value to a variable, used when _f is left shifted by _f##_S
+#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
+
+//generate a value from a field value, used when _f is not left shifted by _f##_S
+#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
+
+//generate a value from a field value, used when _f is left shifted by _f##_S
+#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
+
+//read value from register
+#define READ_PERI_REG(addr) ({                                                                                         \
+            ASSERT_IF_DPORT_REG((addr), READ_PERI_REG);                                                                \
+            (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr)));                                                         \
+        })
+
+//write value to register
+#define WRITE_PERI_REG(addr, val) ({                                                                                   \
+            ASSERT_IF_DPORT_REG((addr), WRITE_PERI_REG);                                                               \
+            (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val);                                       \
+        })
+
+//clear bits of register controlled by mask
+#define CLEAR_PERI_REG_MASK(reg, mask) ({                                                                              \
+            ASSERT_IF_DPORT_REG((reg), CLEAR_PERI_REG_MASK);                                                           \
+            WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask))));                                                     \
+        })
+
+//set bits of register controlled by mask
+#define SET_PERI_REG_MASK(reg, mask) ({                                                                                \
+            ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_MASK);                                                             \
+            WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask)));                                                        \
+        })
+
+//get bits of register controlled by mask
+#define GET_PERI_REG_MASK(reg, mask) ({                                                                                \
+            ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_MASK);                                                             \
+            (READ_PERI_REG(reg) & (mask));                                                                             \
+        })
+
+//get bits of register controlled by highest bit and lowest bit
+#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({                                                                        \
+            ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS);                                                             \
+            ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1));                                            \
+        })
+
+//set bits of register controlled by mask and shift
+#define SET_PERI_REG_BITS(reg,bit_map,value,shift) ({                                                                  \
+            ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_BITS);                                                             \
+            (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) ));      \
+        })
+
+//get field of register
+#define GET_PERI_REG_BITS2(reg, mask,shift) ({                                                                         \
+            ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS2);                                                            \
+            ((READ_PERI_REG(reg)>>(shift))&(mask));                                                                    \
+        })
+
+#endif /* !__ASSEMBLER__ */
+//}}
+
+//Periheral Clock {{
+#define  APB_CLK_FREQ_ROM                            ( 26*1000000 )
+#define  CPU_CLK_FREQ_ROM                            APB_CLK_FREQ_ROM
+#define  CPU_CLK_FREQ                                APB_CLK_FREQ
+#define  APB_CLK_FREQ                                ( 80*1000000 )       //unit: Hz
+#define  UART_CLK_FREQ                               APB_CLK_FREQ
+#define  WDT_CLK_FREQ                                APB_CLK_FREQ
+#define  TIMER_CLK_FREQ                              (80000000>>4) //80MHz divided by 16
+#define  SPI_CLK_DIV                                 4
+#define  TICKS_PER_US_ROM                            26              // CPU is 80MHz
+//}}
+
 //Interrupt hardware source table
 //This table is decided by hardware, don't touch this.
 #define ETS_WIFI_MAC_INTR_SOURCE                0/**< interrupt of WiFi MAC, level*/
@@ -238,8 +297,8 @@
 #define ETS_GPIO_NMI_SOURCE                     23/**< interrupt of GPIO, NMI*/
 #define ETS_FROM_CPU_INTR0_SOURCE               24/**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */
 #define ETS_FROM_CPU_INTR1_SOURCE               25/**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */
-#define ETS_FROM_CPU_INTR2_SOURCE               26/**< interrupt2 generated from a CPU, level*/ /* Used for VHCI */
-#define ETS_FROM_CPU_INTR3_SOURCE               27/**< interrupt3 generated from a CPU, level*/ /* Reserved */
+#define ETS_FROM_CPU_INTR2_SOURCE               26/**< interrupt2 generated from a CPU, level*/ /* Used for DPORT Access */
+#define ETS_FROM_CPU_INTR3_SOURCE               27/**< interrupt3 generated from a CPU, level*/ /* Used for DPORT Access */
 #define ETS_SPI0_INTR_SOURCE                    28/**< interrupt of SPI0, level, SPI0 is for Cache Access, do not use this*/
 #define ETS_SPI1_INTR_SOURCE                    29/**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/
 #define ETS_SPI2_INTR_SOURCE                    30/**< interrupt of SPI2, level*/
@@ -316,7 +375,7 @@
  *      28                      4               extern edge             
  *      29                      3               software                Reserved                Reserved
  *      30                      4               extern edge             Reserved                Reserved
- *      31                      5               extern level            Reserved                Reserved
+ *      31                      5               extern level            DPORT ACCESS            DPORT ACCESS
  *************************************************************************************************************
  */
 
@@ -328,6 +387,7 @@
 #define ETS_FRC1_INUM                           22
 #define ETS_T1_WDT_INUM                         24
 #define ETS_CACHEERR_INUM                       25
+#define ETS_DPORT_INUM                          31
 
 //CPU0 Interrupt number used in ROM, should be cancelled in SDK
 #define ETS_SLC_INUM                            1
diff --git a/tools/sdk/ld/esp32.peripherals.ld b/tools/sdk/ld/esp32.peripherals.ld
index 8d8d4e8b..79becfc9 100644
--- a/tools/sdk/ld/esp32.peripherals.ld
+++ b/tools/sdk/ld/esp32.peripherals.ld
@@ -12,11 +12,13 @@ PROVIDE ( RMT = 0x3ff56000 );
 PROVIDE ( RMTMEM = 0x3ff56800 );
 PROVIDE ( PCNT = 0x3ff57000 );
 PROVIDE ( LEDC = 0x3ff59000 );
+PROVIDE ( MCPWM0 = 0x3ff5E000 );
 PROVIDE ( TIMERG0 = 0x3ff5F000 );
 PROVIDE ( TIMERG1 = 0x3ff60000 );
 PROVIDE ( SPI2 = 0x3ff64000 );
 PROVIDE ( SPI3 = 0x3ff65000 );
 PROVIDE ( I2C1 = 0x3ff67000 );
+PROVIDE ( MCPWM1 = 0x3ff6C000 );
 PROVIDE ( I2S1 = 0x3ff6D000 );
 PROVIDE ( UART2 = 0x3ff6E000 );
 PROVIDE ( SDMMC = 0x3ff68000 );
diff --git a/tools/sdk/ld/esp32.rom.ld b/tools/sdk/ld/esp32.rom.ld
index 97588fb6..9981e59f 100644
--- a/tools/sdk/ld/esp32.rom.ld
+++ b/tools/sdk/ld/esp32.rom.ld
@@ -50,12 +50,12 @@ PROVIDE ( btdm_r_modules_func_p_set = 0x40054270 );
 PROVIDE ( btdm_r_plf_func_p_set = 0x40054288 );
 PROVIDE ( bt_util_buf_env = 0x3ffb8bd4 );
 PROVIDE ( bzero = 0x4000c1f4 );
-PROVIDE ( cache_flash_mmu_set = 0x400095e0 );
-PROVIDE ( Cache_Flush = 0x40009a14 );
-PROVIDE ( Cache_Read_Disable = 0x40009ab8 );
-PROVIDE ( Cache_Read_Enable = 0x40009a84 );
-PROVIDE ( Cache_Read_Init = 0x40009950 );
-PROVIDE ( cache_sram_mmu_set = 0x400097f4 );
+PROVIDE ( cache_flash_mmu_set_rom = 0x400095e0 );
+PROVIDE ( Cache_Flush_rom = 0x40009a14 );
+PROVIDE ( Cache_Read_Disable_rom = 0x40009ab8 );
+PROVIDE ( Cache_Read_Enable_rom = 0x40009a84 );
+PROVIDE ( Cache_Read_Init_rom = 0x40009950 );
+PROVIDE ( cache_sram_mmu_set_rom = 0x400097f4 );
 /* This is static function, but can be used, not generated by script*/
 PROVIDE ( calc_rtc_memory_crc = 0x40008170 );
 PROVIDE ( calloc = 0x4000bee4 );
@@ -827,6 +827,9 @@ PROVIDE ( lmp_dhkey_chk_handler = 0x4002ab48 );
 PROVIDE ( lmp_pause_enc_aes_req_handler = 0x400279a4 );
 PROVIDE ( lmp_io_cap_res_handler = 0x4002c670 );
 PROVIDE ( lmp_io_cap_req_handler = 0x4002c7a4 );
+PROVIDE ( ld_acl_tx_packet_type_select = 0x4002fb40 );
+PROVIDE ( ld_acl_sched = 0x40033268 );
+PROVIDE ( ld_acl_sniff_sched = 0x4003340c );
 PROVIDE ( r_ld_acl_active_hop_types_get = 0x40036e10 );
 PROVIDE ( r_ld_acl_afh_confirm = 0x40036d40 );
 PROVIDE ( r_ld_acl_afh_prepare = 0x40036c84 );
@@ -1858,5 +1861,6 @@ PROVIDE ( ld_sscan_env = 0x3ffb832c );
 PROVIDE ( ld_strain_env = 0x3ffb8330 );
 PROVIDE ( LM_Sniff = 0x3ffb8230 );
 PROVIDE ( LM_SniffSubRate = 0x3ffb8214 );
+PROVIDE ( prbs_64bytes = 0x3ff98992 );
 /* Above are static data, but can be used, not generated by script >>>>> btdm data */
 
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