diff --git a/.gitignore b/.gitignore new file mode 100644 index 00000000..21d2fdcd --- /dev/null +++ b/.gitignore @@ -0,0 +1,2 @@ + +tools/xtensa-esp32-elf diff --git a/boards.txt b/boards.txt new file mode 100644 index 00000000..3835d5c3 --- /dev/null +++ b/boards.txt @@ -0,0 +1,42 @@ +menu.UploadSpeed=Upload Speed +menu.FlashFreq=Flash Frequency + +############################################################## +esp32.name=ESP32 Dev Module + +esp32.upload.tool=esptool +esp32.upload.maximum_size=1044464 +esp32.upload.maximum_data_size=114688 +esp32.upload.wait_for_upload_port=true + +esp32.serial.disableDTR=true +esp32.serial.disableRTS=true + +esp32.build.mcu=esp32 +esp32.build.core=esp32 +esp32.build.variant=esp32 +esp32.build.board=ESP32_DEV + +esp32.build.f_cpu=160000000L +esp32.build.flash_mode=dio +esp32.build.flash_size=4MB + +esp32.menu.FlashFreq.80=80MHz +esp32.menu.FlashFreq.80.build.flash_freq=80m +esp32.menu.FlashFreq.40=40MHz +esp32.menu.FlashFreq.40.build.flash_freq=40m + +esp32.menu.UploadSpeed.921600=921600 +esp32.menu.UploadSpeed.921600.upload.speed=921600 +esp32.menu.UploadSpeed.115200=115200 +esp32.menu.UploadSpeed.115200.upload.speed=115200 +esp32.menu.UploadSpeed.256000.windows=256000 +esp32.menu.UploadSpeed.256000.upload.speed=256000 +esp32.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp32.menu.UploadSpeed.230400=230400 +esp32.menu.UploadSpeed.230400.upload.speed=230400 +esp32.menu.UploadSpeed.460800.linux=460800 +esp32.menu.UploadSpeed.460800.macosx=460800 +esp32.menu.UploadSpeed.460800.upload.speed=460800 +esp32.menu.UploadSpeed.512000.windows=512000 +esp32.menu.UploadSpeed.512000.upload.speed=512000 diff --git a/cores/esp32/Arduino.h b/cores/esp32/Arduino.h new file mode 100644 index 00000000..372e70ec --- /dev/null +++ b/cores/esp32/Arduino.h @@ -0,0 +1,63 @@ +/* + Arduino.h - Main include file for the Arduino SDK + Copyright (c) 2005-2013 Arduino Team. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef Arduino_h +#define Arduino_h + +#ifdef __cplusplus +extern "C" { +#endif + +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "freertos/semphr.h" +#include "esp32-hal.h" +#include "pins_arduino.h" + +#include +#include +#include +#include +#include +#include +#include +#include + +typedef bool boolean; +typedef uint8_t byte; + +#include "binary.h" + +#ifdef __cplusplus +} +#endif + +#include "WCharacter.h" +#include "WString.h" +#include "Stream.h" +#include "Printable.h" +#include "Print.h" +#include "IPAddress.h" +#include "Client.h" +#include "Server.h" +#include "Udp.h" +#include "HardwareSerial.h" +#include "Esp.h" + +#endif /* _ESP32_CORE_ARDUINO_H_ */ diff --git a/cores/esp32/Client.h b/cores/esp32/Client.h new file mode 100644 index 00000000..962cacc5 --- /dev/null +++ b/cores/esp32/Client.h @@ -0,0 +1,48 @@ +/* + Client.h - Base class that provides Client + Copyright (c) 2011 Adrian McEwen. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef client_h +#define client_h +#include "Print.h" +#include "Stream.h" +#include "IPAddress.h" + +class Client: public Stream +{ +public: + virtual int connect(IPAddress ip, uint16_t port) =0; + virtual int connect(const char *host, uint16_t port) =0; + virtual size_t write(uint8_t) =0; + virtual size_t write(const uint8_t *buf, size_t size) =0; + virtual int available() = 0; + virtual int read() = 0; + virtual int read(uint8_t *buf, size_t size) = 0; + virtual int peek() = 0; + virtual void flush() = 0; + virtual void stop() = 0; + virtual uint8_t connected() = 0; + virtual operator bool() = 0; +protected: + uint8_t* rawIPAddress(IPAddress& addr) + { + return addr.raw_address(); + } +}; + +#endif diff --git a/cores/esp32/Esp.cpp b/cores/esp32/Esp.cpp new file mode 100644 index 00000000..82713624 --- /dev/null +++ b/cores/esp32/Esp.cpp @@ -0,0 +1,223 @@ +/* + Esp.cpp - ESP31B-specific APIs + Copyright (c) 2015 Ivan Grokhotkov. All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "Arduino.h" +#include "Esp.h" +#include "rom/spi_flash.h" +#include + +//#define DEBUG_SERIAL Serial + + +/** + * User-defined Literals + * usage: + * + * uint32_t = test = 10_MHz; // --> 10000000 + */ + +unsigned long long operator"" _kHz(unsigned long long x) +{ + return x * 1000; +} + +unsigned long long operator"" _MHz(unsigned long long x) +{ + return x * 1000 * 1000; +} + +unsigned long long operator"" _GHz(unsigned long long x) +{ + return x * 1000 * 1000 * 1000; +} + +unsigned long long operator"" _kBit(unsigned long long x) +{ + return x * 1024; +} + +unsigned long long operator"" _MBit(unsigned long long x) +{ + return x * 1024 * 1024; +} + +unsigned long long operator"" _GBit(unsigned long long x) +{ + return x * 1024 * 1024 * 1024; +} + +unsigned long long operator"" _kB(unsigned long long x) +{ + return x * 1024; +} + +unsigned long long operator"" _MB(unsigned long long x) +{ + return x * 1024 * 1024; +} + +unsigned long long operator"" _GB(unsigned long long x) +{ + return x * 1024 * 1024 * 1024; +} + + +EspClass ESP; + +uint32_t EspClass::getCycleCount() +{ + uint32_t ccount; + __asm__ __volatile__("esync; rsr %0,ccount":"=a" (ccount)); + return ccount; +} + +void EspClass::restart(void) +{ + system_restart(); +} + +uint32_t EspClass::getFreeHeap(void) +{ + return system_get_free_heap_size(); +} + +const char * EspClass::getSdkVersion(void) +{ + return system_get_sdk_version(); +} + +uint32_t EspClass::getFlashChipSize(void) +{ + uint32_t data; + uint8_t * bytes = (uint8_t *) &data; + // read first 4 byte (magic byte + flash config) + if(SPIRead(0x0000, &data, 4) == SPI_FLASH_RESULT_OK) { + return magicFlashChipSize((bytes[3] & 0xf0) >> 4); + } + return 0; +} + +uint32_t EspClass::getFlashChipSpeed(void) +{ + uint32_t data; + uint8_t * bytes = (uint8_t *) &data; + // read first 4 byte (magic byte + flash config) + if(SPIRead(0x0000, &data, 4) == SPI_FLASH_RESULT_OK) { + return magicFlashChipSpeed(bytes[3] & 0x0F); + } + return 0; +} + +FlashMode_t EspClass::getFlashChipMode(void) +{ + FlashMode_t mode = FM_UNKNOWN; + uint32_t data; + uint8_t * bytes = (uint8_t *) &data; + // read first 4 byte (magic byte + flash config) + if(SPIRead(0x0000, &data, 4) == SPI_FLASH_RESULT_OK) { + mode = magicFlashChipMode(bytes[2]); + } + return mode; +} + +uint32_t EspClass::magicFlashChipSize(uint8_t byte) +{ + switch(byte & 0x0F) { + case 0x0: // 4 Mbit (512KB) + return (512_kB); + case 0x1: // 2 MBit (256KB) + return (256_kB); + case 0x2: // 8 MBit (1MB) + return (1_MB); + case 0x3: // 16 MBit (2MB) + return (2_MB); + case 0x4: // 32 MBit (4MB) + return (4_MB); + case 0x5: // 64 MBit (8MB) + return (8_MB); + case 0x6: // 128 MBit (16MB) + return (16_MB); + case 0x7: // 256 MBit (32MB) + return (32_MB); + default: // fail? + return 0; + } +} + +uint32_t EspClass::magicFlashChipSpeed(uint8_t byte) +{ + switch(byte & 0x0F) { + case 0x0: // 40 MHz + return (40_MHz); + case 0x1: // 26 MHz + return (26_MHz); + case 0x2: // 20 MHz + return (20_MHz); + case 0xf: // 80 MHz + return (80_MHz); + default: // fail? + return 0; + } +} + +FlashMode_t EspClass::magicFlashChipMode(uint8_t byte) +{ + FlashMode_t mode = (FlashMode_t) byte; + if(mode > FM_DOUT) { + mode = FM_UNKNOWN; + } + return mode; +} + +bool EspClass::eraseConfig(void) +{ + bool ret = true; + size_t cfgAddr = (getFlashChipSize() - 0x4000); + size_t cfgSize = (8*1024); + + while(cfgSize) { + + if(SPIEraseSector((cfgAddr / 4096)) != SPI_FLASH_RESULT_OK) { + ret = false; + } + + cfgSize -= 4096; + cfgAddr += 4096; + } + + return ret; +} + +bool EspClass::flashEraseSector(uint32_t sector) +{ + int rc = SPIEraseSector(sector); + return rc == 0; +} + +bool EspClass::flashWrite(uint32_t offset, uint32_t *data, size_t size) +{ + int rc = SPIWrite(offset, (uint32_t*) data, size); + return rc == 0; +} + +bool EspClass::flashRead(uint32_t offset, uint32_t *data, size_t size) +{ + int rc = SPIRead(offset, (uint32_t*) data, size); + return rc == 0; +} diff --git a/cores/esp32/Esp.h b/cores/esp32/Esp.h new file mode 100644 index 00000000..db90709a --- /dev/null +++ b/cores/esp32/Esp.h @@ -0,0 +1,85 @@ +/* + Esp.h - ESP31B-specific APIs + Copyright (c) 2015 Ivan Grokhotkov. All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef ESP_H +#define ESP_H + +#include + +/** + * AVR macros for WDT managment + */ +typedef enum { + WDTO_0MS = 0, //!< WDTO_0MS + WDTO_15MS = 15, //!< WDTO_15MS + WDTO_30MS = 30, //!< WDTO_30MS + WDTO_60MS = 60, //!< WDTO_60MS + WDTO_120MS = 120, //!< WDTO_120MS + WDTO_250MS = 250, //!< WDTO_250MS + WDTO_500MS = 500, //!< WDTO_500MS + WDTO_1S = 1000,//!< WDTO_1S + WDTO_2S = 2000,//!< WDTO_2S + WDTO_4S = 4000,//!< WDTO_4S + WDTO_8S = 8000 //!< WDTO_8S +} WDTO_t; + + +typedef enum { + FM_QIO = 0x00, + FM_QOUT = 0x01, + FM_DIO = 0x02, + FM_DOUT = 0x03, + FM_UNKNOWN = 0xff +} FlashMode_t; + +class EspClass +{ +public: + EspClass() {} + ~EspClass() {} + void restart(); + uint32_t getFreeHeap(); + + uint32_t getChipId(); + + const char * getSdkVersion(); + + + uint8_t getCpuFreqMHz(); + + uint32_t getFlashChipSize(); + uint32_t getFlashChipSpeed(); + FlashMode_t getFlashChipMode(); + + uint32_t magicFlashChipSize(uint8_t byte); + uint32_t magicFlashChipSpeed(uint8_t byte); + FlashMode_t magicFlashChipMode(uint8_t byte); + + bool flashEraseSector(uint32_t sector); + bool flashWrite(uint32_t offset, uint32_t *data, size_t size); + bool flashRead(uint32_t offset, uint32_t *data, size_t size); + + bool eraseConfig(); + + uint32_t getCycleCount(); +}; + +extern EspClass ESP; + +#endif //ESP_H diff --git a/cores/esp32/HardwareSerial.cpp b/cores/esp32/HardwareSerial.cpp new file mode 100644 index 00000000..423c512a --- /dev/null +++ b/cores/esp32/HardwareSerial.cpp @@ -0,0 +1,117 @@ +#include +#include +#include +#include + +#include "HardwareSerial.h" + +HardwareSerial Serial(0); + +HardwareSerial::HardwareSerial(int uart_nr) : _uart_nr(uart_nr), _uart(NULL) {} + +void HardwareSerial::begin(unsigned long baud, uint32_t config, int8_t rxPin, int8_t txPin) +{ + if(_uart_nr == 0 && rxPin < 0 && txPin < 0) { + rxPin = 3; + txPin = 1; + } + _uart = uartBegin(_uart_nr, baud, config, rxPin, txPin, 256, false); +} + +void HardwareSerial::end() +{ + if(uartGetDebug() == _uart_nr) { + uartSetDebug(0); + } + uartEnd(_uart); + _uart = 0; +} + +void HardwareSerial::setDebugOutput(bool en) +{ + if(_uart == 0) { + return; + } + if(en) { + if(_uart->txEnabled) { + uartSetDebug(_uart); + } else { + uartSetDebug(0); + } + } else { + if(uartGetDebug() == _uart_nr) { + uartSetDebug(0); + } + } +} + +bool HardwareSerial::isTxEnabled(void) +{ + if(_uart == 0) { + return false; + } + return _uart->txEnabled; +} + +bool HardwareSerial::isRxEnabled(void) +{ + if(_uart == 0) { + return false; + } + return _uart->rxEnabled; +} + +int HardwareSerial::available(void) +{ + if (_uart && _uart->rxEnabled) { + return uartAvailable(_uart); + } + return 0; +} + +int HardwareSerial::peek(void) +{ + if (_uart && _uart->rxEnabled) { + return uartPeek(_uart); + } + return -1; +} + +int HardwareSerial::read(void) +{ + if(_uart && _uart->rxEnabled) { + return uartRead(_uart); + } + return -1; +} + +void HardwareSerial::flush() +{ + if(_uart == 0 || !_uart->txEnabled) { + return; + } + uartFlush(_uart); +} + +size_t HardwareSerial::write(uint8_t c) +{ + if(_uart == 0 || !_uart->txEnabled) { + return 0; + } + uartWrite(_uart, c); + return 1; +} + +size_t HardwareSerial::write(const uint8_t *buffer, size_t size) +{ + if(_uart == 0 || !_uart->txEnabled) { + return 0; + } + uartWriteBuf(_uart, buffer, size); + return size; +} + +HardwareSerial::operator bool() const +{ + return _uart != 0; +} diff --git a/cores/esp32/HardwareSerial.h b/cores/esp32/HardwareSerial.h new file mode 100644 index 00000000..924b1408 --- /dev/null +++ b/cores/esp32/HardwareSerial.h @@ -0,0 +1,78 @@ +/* + HardwareSerial.h - Hardware serial library for Wiring + Copyright (c) 2006 Nicholas Zambetti. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Modified 28 September 2010 by Mark Sproul + Modified 14 August 2012 by Alarus + Modified 3 December 2013 by Matthijs Kooijman + Modified 18 December 2014 by Ivan Grokhotkov (esp8266 platform support) + Modified 31 March 2015 by Markus Sattler (rewrite the code for UART0 + UART1 support in ESP8266) + Modified 25 April 2015 by Thomas Flayols (add configuration different from 8N1 in ESP8266) + */ + +#ifndef HardwareSerial_h +#define HardwareSerial_h + +#include + +#include "Stream.h" +#include "esp32-hal.h" + +class HardwareSerial: public Stream +{ +public: + HardwareSerial(int uart_nr); + + void begin(unsigned long baud, uint32_t config=SERIAL_8N1, int8_t rxPin=-1, int8_t txPin=-1); + void end(); + int available(void); + int peek(void); + int read(void); + void flush(void); + size_t write(uint8_t); + size_t write(const uint8_t *buffer, size_t size); + + inline size_t write(unsigned long n) + { + return write((uint8_t) n); + } + inline size_t write(long n) + { + return write((uint8_t) n); + } + inline size_t write(unsigned int n) + { + return write((uint8_t) n); + } + inline size_t write(int n) + { + return write((uint8_t) n); + } + operator bool() const; + + void setDebugOutput(bool); + bool isTxEnabled(void); + bool isRxEnabled(void); + +protected: + int _uart_nr; + uart_t* _uart; +}; + +extern HardwareSerial Serial; + +#endif diff --git a/cores/esp32/IPAddress.cpp b/cores/esp32/IPAddress.cpp new file mode 100644 index 00000000..c2c0811b --- /dev/null +++ b/cores/esp32/IPAddress.cpp @@ -0,0 +1,81 @@ +/* + IPAddress.cpp - Base class that provides IPAddress + Copyright (c) 2011 Adrian McEwen. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include + +IPAddress::IPAddress() +{ + _address.dword = 0; +} + +IPAddress::IPAddress(uint8_t first_octet, uint8_t second_octet, uint8_t third_octet, uint8_t fourth_octet) +{ + _address.bytes[0] = first_octet; + _address.bytes[1] = second_octet; + _address.bytes[2] = third_octet; + _address.bytes[3] = fourth_octet; +} + +IPAddress::IPAddress(uint32_t address) +{ + _address.dword = address; +} + +IPAddress::IPAddress(const uint8_t *address) +{ + memcpy(_address.bytes, address, sizeof(_address.bytes)); +} + +IPAddress& IPAddress::operator=(const uint8_t *address) +{ + memcpy(_address.bytes, address, sizeof(_address.bytes)); + return *this; +} + +IPAddress& IPAddress::operator=(uint32_t address) +{ + _address.dword = address; + return *this; +} + +bool IPAddress::operator==(const uint8_t* addr) const +{ + return memcmp(addr, _address.bytes, sizeof(_address.bytes)) == 0; +} + +size_t IPAddress::printTo(Print& p) const +{ + size_t n = 0; + for(int i = 0; i < 3; i++) { + n += p.print(_address.bytes[i], DEC); + n += p.print('.'); + } + n += p.print(_address.bytes[3], DEC); + return n; +} + +String IPAddress::toString() +{ + char szRet[16]; + sprintf(szRet,"%u.%u.%u.%u", _address.bytes[0], _address.bytes[1], _address.bytes[2], _address.bytes[3]); + return String(szRet); +} + diff --git a/cores/esp32/IPAddress.h b/cores/esp32/IPAddress.h new file mode 100644 index 00000000..980be00f --- /dev/null +++ b/cores/esp32/IPAddress.h @@ -0,0 +1,93 @@ +/* + IPAddress.h - Base class that provides IPAddress + Copyright (c) 2011 Adrian McEwen. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef IPAddress_h +#define IPAddress_h + +#include +#include +#include + +// A class to make it easier to handle and pass around IP addresses + +class IPAddress: public Printable +{ +private: + union { + uint8_t bytes[4]; // IPv4 address + uint32_t dword; + } _address; + + // Access the raw byte array containing the address. Because this returns a pointer + // to the internal structure rather than a copy of the address this function should only + // be used when you know that the usage of the returned uint8_t* will be transient and not + // stored. + uint8_t* raw_address() + { + return _address.bytes; + } + +public: + // Constructors + IPAddress(); + IPAddress(uint8_t first_octet, uint8_t second_octet, uint8_t third_octet, uint8_t fourth_octet); + IPAddress(uint32_t address); + IPAddress(const uint8_t *address); + virtual ~IPAddress() {} + + // Overloaded cast operator to allow IPAddress objects to be used where a pointer + // to a four-byte uint8_t array is expected + operator uint32_t() const + { + return _address.dword; + } + bool operator==(const IPAddress& addr) const + { + return _address.dword == addr._address.dword; + } + bool operator==(const uint8_t* addr) const; + + // Overloaded index operator to allow getting and setting individual octets of the address + uint8_t operator[](int index) const + { + return _address.bytes[index]; + } + uint8_t& operator[](int index) + { + return _address.bytes[index]; + } + + // Overloaded copy operators to allow initialisation of IPAddress objects from other types + IPAddress& operator=(const uint8_t *address); + IPAddress& operator=(uint32_t address); + + virtual size_t printTo(Print& p) const; + String toString(); + + friend class EthernetClass; + friend class UDP; + friend class Client; + friend class Server; + friend class DhcpClass; + friend class DNSClient; +}; + +const IPAddress INADDR_NONE(0, 0, 0, 0); + +#endif diff --git a/cores/esp32/MD5Builder.cpp b/cores/esp32/MD5Builder.cpp new file mode 100644 index 00000000..f2168f4e --- /dev/null +++ b/cores/esp32/MD5Builder.cpp @@ -0,0 +1,117 @@ +/* + Copyright (c) 2015 Hristo Gochkov. All rights reserved. + This file is part of the esp8266 core for Arduino environment. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ +#include +#include + +uint8_t hex_char_to_byte(uint8_t c) +{ + return (c >= 'a' && c <= 'f') ? (c - ((uint8_t)'a' - 0xa)) : + (c >= 'A' && c <= 'F') ? (c - ((uint8_t)'A' - 0xA)) : + (c >= '0' && c<= '9') ? (c - (uint8_t)'0') : 0; +} + +void MD5Builder::begin(void) +{ + memset(_buf, 0x00, 16); + MD5Init(&_ctx); +} + +void MD5Builder::add(uint8_t * data, uint16_t len) +{ + MD5Update(&_ctx, data, len); +} + +void MD5Builder::addHexString(const char * data) +{ + uint16_t i, len = strlen(data); + uint8_t * tmp = (uint8_t*)malloc(len/2); + if(tmp == NULL) { + return; + } + for(i=0; i 0) && (maxLengthLeft > 0)) { + + // determine number of bytes to read + int readBytes = bytesAvailable; + if(readBytes > maxLengthLeft) { + readBytes = maxLengthLeft ; // read only until max_len + } + if(readBytes > buf_size) { + readBytes = buf_size; // not read more the buffer can handle + } + + // read data and check if we got something + int numBytesRead = stream.readBytes(buf, readBytes); + if(numBytesRead< 1) { + return false; + } + + // Update MD5 with buffer payload + MD5Update(&_ctx, buf, numBytesRead); + + // update available number of bytes + maxLengthLeft -= numBytesRead; + bytesAvailable = stream.available(); + } + free(buf); + return true; +} + +void MD5Builder::calculate(void) +{ + MD5Final(_buf, &_ctx); +} + +void MD5Builder::getBytes(uint8_t * output) +{ + memcpy(output, _buf, 16); +} + +void MD5Builder::getChars(char * output) +{ + for(uint8_t i = 0; i < 16; i++) { + sprintf(output + (i * 2), "%02x", _buf[i]); + } +} + +String MD5Builder::toString(void) +{ + char out[33]; + getChars(out); + return String(out); +} diff --git a/cores/esp32/MD5Builder.h b/cores/esp32/MD5Builder.h new file mode 100644 index 00000000..5429d9ae --- /dev/null +++ b/cores/esp32/MD5Builder.h @@ -0,0 +1,63 @@ +/* + Copyright (c) 2015 Hristo Gochkov. All rights reserved. + This file is part of the esp8266 core for Arduino environment. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ +#ifndef __ESP8266_MD5_BUILDER__ +#define __ESP8266_MD5_BUILDER__ + +#include +#include +#include "rom/md5_hash.h" + +class MD5Builder +{ +private: + struct MD5Context _ctx; + uint8_t _buf[16]; +public: + void begin(void); + void add(uint8_t * data, uint16_t len); + void add(const char * data) + { + add((uint8_t*)data, strlen(data)); + } + void add(char * data) + { + add((const char*)data); + } + void add(String data) + { + add(data.c_str()); + } + void addHexString(const char * data); + void addHexString(char * data) + { + addHexString((const char*)data); + } + void addHexString(String data) + { + addHexString(data.c_str()); + } + bool addStream(Stream & stream, const size_t maxLen); + void calculate(void); + void getBytes(uint8_t * output); + void getChars(char * output); + String toString(void); +}; + + +#endif diff --git a/cores/esp32/Print.cpp b/cores/esp32/Print.cpp new file mode 100644 index 00000000..e01304ff --- /dev/null +++ b/cores/esp32/Print.cpp @@ -0,0 +1,293 @@ +/* + Print.cpp - Base class that provides print() and println() + Copyright (c) 2008 David A. Mellis. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Modified 23 November 2006 by David A. Mellis + Modified December 2014 by Ivan Grokhotkov + Modified May 2015 by Michael C. Miller - ESP31B progmem support + */ + +#include +#include +#include +#include +#include "Wiring.h" + +#include "Print.h" +extern "C" { +//#include "esp_common.h" +} + +// Public Methods ////////////////////////////////////////////////////////////// + +/* default implementation: may be overridden */ +size_t Print::write(const uint8_t *buffer, size_t size) +{ + size_t n = 0; + while(size--) { + n += write(*buffer++); + } + return n; +} + +size_t Print::printf(const char *format, ...) +{ + va_list arg; + va_start(arg, format); + size_t len = vsnprintf(NULL, 0, format, arg); + char temp[len+1]; + uint8_t * stemp = (uint8_t*)temp; + len = vsnprintf(temp, len+1, format, arg); + write(stemp, len); + va_end(arg); + return len; +} +/* +size_t Print::print(const __FlashStringHelper *ifsh) { + PGM_P p = reinterpret_cast(ifsh); + + size_t n = 0; + while (1) { + uint8_t c = pgm_read_byte(p++); + if (c == 0) break; + n += write(c); + } + return n; +} +*/ +size_t Print::print(const String &s) +{ + return write(s.c_str(), s.length()); +} + +size_t Print::print(const char str[]) +{ + return write(str); +} + +size_t Print::print(char c) +{ + return write(c); +} + +size_t Print::print(unsigned char b, int base) +{ + return print((unsigned long) b, base); +} + +size_t Print::print(int n, int base) +{ + return print((long) n, base); +} + +size_t Print::print(unsigned int n, int base) +{ + return print((unsigned long) n, base); +} + +size_t Print::print(long n, int base) +{ + if(base == 0) { + return write(n); + } else if(base == 10) { + if(n < 0) { + int t = print('-'); + n = -n; + return printNumber(n, 10) + t; + } + return printNumber(n, 10); + } else { + return printNumber(n, base); + } +} + +size_t Print::print(unsigned long n, int base) +{ + if(base == 0) { + return write(n); + } else { + return printNumber(n, base); + } +} + +size_t Print::print(double n, int digits) +{ + return printFloat(n, digits); +} + +size_t Print::println(const __FlashStringHelper *ifsh) +{ + size_t n = print(ifsh); + n += println(); + return n; +} + +size_t Print::print(const Printable& x) +{ + return x.printTo(*this); +} + +size_t Print::println(void) +{ + return print("\r\n"); +} + +size_t Print::println(const String &s) +{ + size_t n = print(s); + n += println(); + return n; +} + +size_t Print::println(const char c[]) +{ + size_t n = print(c); + n += println(); + return n; +} + +size_t Print::println(char c) +{ + size_t n = print(c); + n += println(); + return n; +} + +size_t Print::println(unsigned char b, int base) +{ + size_t n = print(b, base); + n += println(); + return n; +} + +size_t Print::println(int num, int base) +{ + size_t n = print(num, base); + n += println(); + return n; +} + +size_t Print::println(unsigned int num, int base) +{ + size_t n = print(num, base); + n += println(); + return n; +} + +size_t Print::println(long num, int base) +{ + size_t n = print(num, base); + n += println(); + return n; +} + +size_t Print::println(unsigned long num, int base) +{ + size_t n = print(num, base); + n += println(); + return n; +} + +size_t Print::println(double num, int digits) +{ + size_t n = print(num, digits); + n += println(); + return n; +} + +size_t Print::println(const Printable& x) +{ + size_t n = print(x); + n += println(); + return n; +} + +// Private Methods ///////////////////////////////////////////////////////////// + +size_t Print::printNumber(unsigned long n, uint8_t base) +{ + char buf[8 * sizeof(long) + 1]; // Assumes 8-bit chars plus zero byte. + char *str = &buf[sizeof(buf) - 1]; + + *str = '\0'; + + // prevent crash if called with base == 1 + if(base < 2) { + base = 10; + } + + do { + unsigned long m = n; + n /= base; + char c = m - base * n; + *--str = c < 10 ? c + '0' : c + 'A' - 10; + } while(n); + + return write(str); +} + +size_t Print::printFloat(double number, uint8_t digits) +{ + size_t n = 0; + + if(isnan(number)) { + return print("nan"); + } + if(isinf(number)) { + return print("inf"); + } + if(number > 4294967040.0) { + return print("ovf"); // constant determined empirically + } + if(number < -4294967040.0) { + return print("ovf"); // constant determined empirically + } + + // Handle negative numbers + if(number < 0.0) { + n += print('-'); + number = -number; + } + + // Round correctly so that print(1.999, 2) prints as "2.00" + double rounding = 0.5; + for(uint8_t i = 0; i < digits; ++i) { + rounding /= 10.0; + } + + number += rounding; + + // Extract the integer part of the number and print it + unsigned long int_part = (unsigned long) number; + double remainder = number - (double) int_part; + n += print(int_part); + + // Print the decimal point, but only if there are digits beyond + if(digits > 0) { + n += print("."); + } + + // Extract digits from the remainder one at a time + while(digits-- > 0) { + remainder *= 10.0; + int toPrint = int(remainder); + n += print(toPrint); + remainder -= toPrint; + } + + return n; +} diff --git a/cores/esp32/Print.h b/cores/esp32/Print.h new file mode 100644 index 00000000..49867289 --- /dev/null +++ b/cores/esp32/Print.h @@ -0,0 +1,101 @@ +/* + Print.h - Base class that provides print() and println() + Copyright (c) 2008 David A. Mellis. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef Print_h +#define Print_h + +#include +#include + +#include "WString.h" +#include "Printable.h" + +#define DEC 10 +#define HEX 16 +#define OCT 8 +#define BIN 2 + +class Print +{ +private: + int write_error; + size_t printNumber(unsigned long, uint8_t); + size_t printFloat(double, uint8_t); +protected: + void setWriteError(int err = 1) + { + write_error = err; + } +public: + Print() : + write_error(0) + { + } + virtual ~Print() {} + int getWriteError() + { + return write_error; + } + void clearWriteError() + { + setWriteError(0); + } + + virtual size_t write(uint8_t) = 0; + size_t write(const char *str) + { + if(str == NULL) { + return 0; + } + return write((const uint8_t *) str, strlen(str)); + } + virtual size_t write(const uint8_t *buffer, size_t size); + size_t write(const char *buffer, size_t size) + { + return write((const uint8_t *) buffer, size); + } + + size_t printf(const char * format, ...) __attribute__ ((format (printf, 2, 3))); + size_t print(const __FlashStringHelper *); + size_t print(const String &); + size_t print(const char[]); + size_t print(char); + size_t print(unsigned char, int = DEC); + size_t print(int, int = DEC); + size_t print(unsigned int, int = DEC); + size_t print(long, int = DEC); + size_t print(unsigned long, int = DEC); + size_t print(double, int = 2); + size_t print(const Printable&); + + size_t println(const __FlashStringHelper *); + size_t println(const String &s); + size_t println(const char[]); + size_t println(char); + size_t println(unsigned char, int = DEC); + size_t println(int, int = DEC); + size_t println(unsigned int, int = DEC); + size_t println(long, int = DEC); + size_t println(unsigned long, int = DEC); + size_t println(double, int = 2); + size_t println(const Printable&); + size_t println(void); +}; + +#endif diff --git a/cores/esp32/Printable.h b/cores/esp32/Printable.h new file mode 100644 index 00000000..aa4e62f8 --- /dev/null +++ b/cores/esp32/Printable.h @@ -0,0 +1,41 @@ +/* + Printable.h - Interface class that allows printing of complex types + Copyright (c) 2011 Adrian McEwen. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef Printable_h +#define Printable_h + +#include + +class Print; + +/** The Printable class provides a way for new classes to allow themselves to be printed. + By deriving from Printable and implementing the printTo method, it will then be possible + for users to print out instances of this class by passing them into the usual + Print::print and Print::println methods. + */ + +class Printable +{ +public: + virtual ~Printable() {} + virtual size_t printTo(Print& p) const = 0; +}; + +#endif + diff --git a/cores/esp32/Server.h b/cores/esp32/Server.h new file mode 100644 index 00000000..1be91873 --- /dev/null +++ b/cores/esp32/Server.h @@ -0,0 +1,31 @@ +/* + Server.h - Base class that provides Server + Copyright (c) 2011 Adrian McEwen. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef server_h +#define server_h + +#include "Print.h" + +class Server: public Print +{ +public: + virtual void begin() =0; +}; + +#endif diff --git a/cores/esp32/Stream.cpp b/cores/esp32/Stream.cpp new file mode 100644 index 00000000..6d1b1fc8 --- /dev/null +++ b/cores/esp32/Stream.cpp @@ -0,0 +1,291 @@ +/* + Stream.cpp - adds parsing methods to Stream class + Copyright (c) 2008 David A. Mellis. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Created July 2011 + parsing functions based on TextFinder library by Michael Margolis + */ + +#include "Wiring.h" +#include "Stream.h" +#include "esp32-hal.h" + +#define PARSE_TIMEOUT 1000 // default number of milli-seconds to wait +#define NO_SKIP_CHAR 1 // a magic char not found in a valid ASCII numeric field + +// private method to read stream with timeout +int Stream::timedRead() +{ + int c; + _startMillis = millis(); + do { + c = read(); + if(c >= 0) { + return c; + } + } while(millis() - _startMillis < _timeout); + return -1; // -1 indicates timeout +} + +// private method to peek stream with timeout +int Stream::timedPeek() +{ + int c; + _startMillis = millis(); + do { + c = peek(); + if(c >= 0) { + return c; + } + } while(millis() - _startMillis < _timeout); + return -1; // -1 indicates timeout +} + +// returns peek of the next digit in the stream or -1 if timeout +// discards non-numeric characters +int Stream::peekNextDigit() +{ + int c; + while(1) { + c = timedPeek(); + if(c < 0) { + return c; // timeout + } + if(c == '-') { + return c; + } + if(c >= '0' && c <= '9') { + return c; + } + read(); // discard non-numeric + } +} + +// Public Methods +////////////////////////////////////////////////////////////// + +void Stream::setTimeout(unsigned long timeout) // sets the maximum number of milliseconds to wait +{ + _timeout = timeout; +} + +// find returns true if the target string is found +bool Stream::find(const char *target) +{ + return findUntil(target, (char*) ""); +} + +// reads data from the stream until the target string of given length is found +// returns true if target string is found, false if timed out +bool Stream::find(const char *target, size_t length) +{ + return findUntil(target, length, NULL, 0); +} + +// as find but search ends if the terminator string is found +bool Stream::findUntil(const char *target, const char *terminator) +{ + return findUntil(target, strlen(target), terminator, strlen(terminator)); +} + +// reads data from the stream until the target string of the given length is found +// search terminated if the terminator string is found +// returns true if target string is found, false if terminated or timed out +bool Stream::findUntil(const char *target, size_t targetLen, const char *terminator, size_t termLen) +{ + size_t index = 0; // maximum target string length is 64k bytes! + size_t termIndex = 0; + int c; + + if(*target == 0) { + return true; // return true if target is a null string + } + while((c = timedRead()) > 0) { + + if(c != target[index]) { + index = 0; // reset index if any char does not match + } + + if(c == target[index]) { + //////Serial.print("found "); Serial.write(c); Serial.print("index now"); Serial.println(index+1); + if(++index >= targetLen) { // return true if all chars in the target match + return true; + } + } + + if(termLen > 0 && c == terminator[termIndex]) { + if(++termIndex >= termLen) { + return false; // return false if terminate string found before target string + } + } else { + termIndex = 0; + } + } + return false; +} + +// returns the first valid (long) integer value from the current position. +// initial characters that are not digits (or the minus sign) are skipped +// function is terminated by the first character that is not a digit. +long Stream::parseInt() +{ + return parseInt(NO_SKIP_CHAR); // terminate on first non-digit character (or timeout) +} + +// as above but a given skipChar is ignored +// this allows format characters (typically commas) in values to be ignored +long Stream::parseInt(char skipChar) +{ + boolean isNegative = false; + long value = 0; + int c; + + c = peekNextDigit(); + // ignore non numeric leading characters + if(c < 0) { + return 0; // zero returned if timeout + } + + do { + if(c == skipChar) { + } // ignore this charactor + else if(c == '-') { + isNegative = true; + } else if(c >= '0' && c <= '9') { // is c a digit? + value = value * 10 + c - '0'; + } + read(); // consume the character we got with peek + c = timedPeek(); + } while((c >= '0' && c <= '9') || c == skipChar); + + if(isNegative) { + value = -value; + } + return value; +} + +// as parseInt but returns a floating point value +float Stream::parseFloat() +{ + return parseFloat(NO_SKIP_CHAR); +} + +// as above but the given skipChar is ignored +// this allows format characters (typically commas) in values to be ignored +float Stream::parseFloat(char skipChar) +{ + boolean isNegative = false; + boolean isFraction = false; + long value = 0; + int c; + float fraction = 1.0; + + c = peekNextDigit(); + // ignore non numeric leading characters + if(c < 0) { + return 0; // zero returned if timeout + } + + do { + if(c == skipChar) { + } // ignore + else if(c == '-') { + isNegative = true; + } else if(c == '.') { + isFraction = true; + } else if(c >= '0' && c <= '9') { // is c a digit? + value = value * 10 + c - '0'; + if(isFraction) { + fraction *= 0.1; + } + } + read(); // consume the character we got with peek + c = timedPeek(); + } while((c >= '0' && c <= '9') || c == '.' || c == skipChar); + + if(isNegative) { + value = -value; + } + if(isFraction) { + return value * fraction; + } else { + return value; + } +} + +// read characters from stream into buffer +// terminates if length characters have been read, or timeout (see setTimeout) +// returns the number of characters placed in the buffer +// the buffer is NOT null terminated. +// +size_t Stream::readBytes(char *buffer, size_t length) +{ + size_t count = 0; + while(count < length) { + int c = timedRead(); + if(c < 0) { + break; + } + *buffer++ = (char) c; + count++; + } + return count; +} + +// as readBytes with terminator character +// terminates if length characters have been read, timeout, or if the terminator character detected +// returns the number of characters placed in the buffer (0 means no valid data found) + +size_t Stream::readBytesUntil(char terminator, char *buffer, size_t length) +{ + if(length < 1) { + return 0; + } + size_t index = 0; + while(index < length) { + int c = timedRead(); + if(c < 0 || c == terminator) { + break; + } + *buffer++ = (char) c; + index++; + } + return index; // return number of characters, not including null terminator +} + +String Stream::readString() +{ + String ret; + int c = timedRead(); + while(c >= 0) { + ret += (char) c; + c = timedRead(); + } + return ret; +} + +String Stream::readStringUntil(char terminator) +{ + String ret; + int c = timedRead(); + while(c >= 0 && c != terminator) { + ret += (char) c; + c = timedRead(); + } + return ret; +} + diff --git a/cores/esp32/Stream.h b/cores/esp32/Stream.h new file mode 100644 index 00000000..e5f4f6cc --- /dev/null +++ b/cores/esp32/Stream.h @@ -0,0 +1,128 @@ +/* + Stream.h - base class for character-based streams. + Copyright (c) 2010 David A. Mellis. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + parsing functions based on TextFinder library by Michael Margolis + */ + +#ifndef Stream_h +#define Stream_h + +#include +#include "Print.h" + +// compatability macros for testing +/* + #define getInt() parseInt() + #define getInt(skipChar) parseInt(skipchar) + #define getFloat() parseFloat() + #define getFloat(skipChar) parseFloat(skipChar) + #define getString( pre_string, post_string, buffer, length) + readBytesBetween( pre_string, terminator, buffer, length) + */ + +class Stream: public Print +{ +protected: + unsigned long _timeout; // number of milliseconds to wait for the next char before aborting timed read + unsigned long _startMillis; // used for timeout measurement + int timedRead(); // private method to read stream with timeout + int timedPeek(); // private method to peek stream with timeout + int peekNextDigit(); // returns the next numeric digit in the stream or -1 if timeout + +public: + virtual int available() = 0; + virtual int read() = 0; + virtual int peek() = 0; + virtual void flush() = 0; + + Stream():_startMillis(0) + { + _timeout = 1000; + } + virtual ~Stream() {} + +// parsing methods + + void setTimeout(unsigned long timeout); // sets maximum milliseconds to wait for stream data, default is 1 second + + bool find(const char *target); // reads data from the stream until the target string is found + bool find(uint8_t *target) + { + return find((char *) target); + } + // returns true if target string is found, false if timed out (see setTimeout) + + bool find(const char *target, size_t length); // reads data from the stream until the target string of given length is found + bool find(const uint8_t *target, size_t length) + { + return find((char *) target, length); + } + // returns true if target string is found, false if timed out + + bool find(char target) + { + return find (&target, 1); + } + + bool findUntil(const char *target, const char *terminator); // as find but search ends if the terminator string is found + bool findUntil(const uint8_t *target, const char *terminator) + { + return findUntil((char *) target, terminator); + } + + bool findUntil(const char *target, size_t targetLen, const char *terminate, size_t termLen); // as above but search ends if the terminate string is found + bool findUntil(const uint8_t *target, size_t targetLen, const char *terminate, size_t termLen) + { + return findUntil((char *) target, targetLen, terminate, termLen); + } + + long parseInt(); // returns the first valid (long) integer value from the current position. + // initial characters that are not digits (or the minus sign) are skipped + // integer is terminated by the first character that is not a digit. + + float parseFloat(); // float version of parseInt + + size_t readBytes(char *buffer, size_t length); // read chars from stream into buffer + size_t readBytes(uint8_t *buffer, size_t length) + { + return readBytes((char *) buffer, length); + } + // terminates if length characters have been read or timeout (see setTimeout) + // returns the number of characters placed in the buffer (0 means no valid data found) + + size_t readBytesUntil(char terminator, char *buffer, size_t length); // as readBytes with terminator character + size_t readBytesUntil(char terminator, uint8_t *buffer, size_t length) + { + return readBytesUntil(terminator, (char *) buffer, length); + } + // terminates if length characters have been read, timeout, or if the terminator character detected + // returns the number of characters placed in the buffer (0 means no valid data found) + + // Arduino String functions to be added here + String readString(); + String readStringUntil(char terminator); + +protected: + long parseInt(char skipChar); // as above but the given skipChar is ignored + // as above but the given skipChar is ignored + // this allows format characters (typically commas) in values to be ignored + + float parseFloat(char skipChar); // as above but the given skipChar is ignored +}; + +#endif diff --git a/cores/esp32/StreamString.cpp b/cores/esp32/StreamString.cpp new file mode 100644 index 00000000..80b2aff0 --- /dev/null +++ b/cores/esp32/StreamString.cpp @@ -0,0 +1,71 @@ +/** + StreamString.cpp + + Copyright (c) 2015 Markus Sattler. All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + */ + +#include +#include "StreamString.h" + +size_t StreamString::write(const uint8_t *data, size_t size) +{ + if(size && data) { + if(reserve(length() + size + 1)) { + memcpy((void *) (buffer + len), (const void *) data, size); + len += size; + *(buffer + len) = 0x00; // add null for string end + return size; + } + } + return 0; +} + +size_t StreamString::write(uint8_t data) +{ + return concat((char) data); +} + +int StreamString::available() +{ + return length(); +} + +int StreamString::read() +{ + if(length()) { + char c = charAt(0); + remove(0, 1); + return c; + + } + return -1; +} + +int StreamString::peek() +{ + if(length()) { + char c = charAt(0); + return c; + } + return -1; +} + +void StreamString::flush() +{ +} + diff --git a/cores/esp32/StreamString.h b/cores/esp32/StreamString.h new file mode 100644 index 00000000..a1983d88 --- /dev/null +++ b/cores/esp32/StreamString.h @@ -0,0 +1,39 @@ +/** + StreamString.h + + Copyright (c) 2015 Markus Sattler. All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + +*/ + +#ifndef STREAMSTRING_H_ +#define STREAMSTRING_H_ + + +class StreamString: public Stream, public String +{ +public: + size_t write(const uint8_t *buffer, size_t size) override; + size_t write(uint8_t data) override; + + int available() override; + int read() override; + int peek() override; + void flush() override; +}; + + +#endif /* STREAMSTRING_H_ */ diff --git a/cores/esp32/Udp.h b/cores/esp32/Udp.h new file mode 100644 index 00000000..f47f83cc --- /dev/null +++ b/cores/esp32/Udp.h @@ -0,0 +1,92 @@ +/* + * Udp.cpp: Library to send/receive UDP packets. + * + * NOTE: UDP is fast, but has some important limitations (thanks to Warren Gray for mentioning these) + * 1) UDP does not guarantee the order in which assembled UDP packets are received. This + * might not happen often in practice, but in larger network topologies, a UDP + * packet can be received out of sequence. + * 2) UDP does not guard against lost packets - so packets *can* disappear without the sender being + * aware of it. Again, this may not be a concern in practice on small local networks. + * For more information, see http://www.cafeaulait.org/course/week12/35.html + * + * MIT License: + * Copyright (c) 2008 Bjoern Hartmann + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * bjoern@cs.stanford.edu 12/30/2008 + */ + +#ifndef udp_h +#define udp_h + +#include +#include + +class UDP: public Stream +{ + +public: + virtual uint8_t begin(uint16_t) =0; // initialize, start listening on specified port. Returns 1 if successful, 0 if there are no sockets available to use + virtual void stop() =0; // Finish with the UDP socket + + // Sending UDP packets + + // Start building up a packet to send to the remote host specific in ip and port + // Returns 1 if successful, 0 if there was a problem with the supplied IP address or port + virtual int beginPacket(IPAddress ip, uint16_t port) =0; + // Start building up a packet to send to the remote host specific in host and port + // Returns 1 if successful, 0 if there was a problem resolving the hostname or port + virtual int beginPacket(const char *host, uint16_t port) =0; + // Finish off this packet and send it + // Returns 1 if the packet was sent successfully, 0 if there was an error + virtual int endPacket() =0; + // Write a single byte into the packet + virtual size_t write(uint8_t) =0; + // Write size bytes from buffer into the packet + virtual size_t write(const uint8_t *buffer, size_t size) =0; + + // Start processing the next available incoming packet + // Returns the size of the packet in bytes, or 0 if no packets are available + virtual int parsePacket() =0; + // Number of bytes remaining in the current packet + virtual int available() =0; + // Read a single byte from the current packet + virtual int read() =0; + // Read up to len bytes from the current packet and place them into buffer + // Returns the number of bytes read, or 0 if none are available + virtual int read(unsigned char* buffer, size_t len) =0; + // Read up to len characters from the current packet and place them into buffer + // Returns the number of characters read, or 0 if none are available + virtual int read(char* buffer, size_t len) =0; + // Return the next byte from the current packet without moving on to the next byte + virtual int peek() =0; + virtual void flush() =0; // Finish reading the current packet + + // Return the IP address of the host who sent the current incoming packet + virtual IPAddress remoteIP() =0; + // Return the port of the host who sent the current incoming packet + virtual uint16_t remotePort() =0; +protected: + uint8_t* rawIPAddress(IPAddress& addr) + { + return addr.raw_address(); + } +}; + +#endif diff --git a/cores/esp32/WCharacter.h b/cores/esp32/WCharacter.h new file mode 100644 index 00000000..93e5dda4 --- /dev/null +++ b/cores/esp32/WCharacter.h @@ -0,0 +1,155 @@ +/* + WCharacter.h - Character utility functions for Wiring & Arduino + Copyright (c) 2010 Hernando Barragan. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef Character_h +#define Character_h + +#include +#include "WTypes.h" +#define isascii(__c) ((unsigned)(__c)<=0177) +#define toascii(__c) ((__c)&0177) + +// WCharacter.h prototypes +inline boolean isAlphaNumeric(int c) __attribute__((always_inline)); +inline boolean isAlpha(int c) __attribute__((always_inline)); +inline boolean isAscii(int c) __attribute__((always_inline)); +inline boolean isWhitespace(int c) __attribute__((always_inline)); +inline boolean isControl(int c) __attribute__((always_inline)); +inline boolean isDigit(int c) __attribute__((always_inline)); +inline boolean isGraph(int c) __attribute__((always_inline)); +inline boolean isLowerCase(int c) __attribute__((always_inline)); +inline boolean isPrintable(int c) __attribute__((always_inline)); +inline boolean isPunct(int c) __attribute__((always_inline)); +inline boolean isSpace(int c) __attribute__((always_inline)); +inline boolean isUpperCase(int c) __attribute__((always_inline)); +inline boolean isHexadecimalDigit(int c) __attribute__((always_inline)); +inline int toAscii(int c) __attribute__((always_inline)); +inline int toLowerCase(int c) __attribute__((always_inline)); +inline int toUpperCase(int c) __attribute__((always_inline)); + +// Checks for an alphanumeric character. +// It is equivalent to (isalpha(c) || isdigit(c)). +inline boolean isAlphaNumeric(int c) +{ + return (isalnum(c) == 0 ? false : true); +} + +// Checks for an alphabetic character. +// It is equivalent to (isupper(c) || islower(c)). +inline boolean isAlpha(int c) +{ + return (isalpha(c) == 0 ? false : true); +} + +// Checks whether c is a 7-bit unsigned char value +// that fits into the ASCII character set. +inline boolean isAscii(int c) +{ + return ( isascii (c) == 0 ? false : true); +} + +// Checks for a blank character, that is, a space or a tab. +inline boolean isWhitespace(int c) +{ + return (isblank(c) == 0 ? false : true); +} + +// Checks for a control character. +inline boolean isControl(int c) +{ + return (iscntrl(c) == 0 ? false : true); +} + +// Checks for a digit (0 through 9). +inline boolean isDigit(int c) +{ + return (isdigit(c) == 0 ? false : true); +} + +// Checks for any printable character except space. +inline boolean isGraph(int c) +{ + return (isgraph(c) == 0 ? false : true); +} + +// Checks for a lower-case character. +inline boolean isLowerCase(int c) +{ + return (islower(c) == 0 ? false : true); +} + +// Checks for any printable character including space. +inline boolean isPrintable(int c) +{ + return (isprint(c) == 0 ? false : true); +} + +// Checks for any printable character which is not a space +// or an alphanumeric character. +inline boolean isPunct(int c) +{ + return (ispunct(c) == 0 ? false : true); +} + +// Checks for white-space characters. For the avr-libc library, +// these are: space, formfeed ('\f'), newline ('\n'), carriage +// return ('\r'), horizontal tab ('\t'), and vertical tab ('\v'). +inline boolean isSpace(int c) +{ + return (isspace(c) == 0 ? false : true); +} + +// Checks for an uppercase letter. +inline boolean isUpperCase(int c) +{ + return (isupper(c) == 0 ? false : true); +} + +// Checks for a hexadecimal digits, i.e. one of 0 1 2 3 4 5 6 7 +// 8 9 a b c d e f A B C D E F. +inline boolean isHexadecimalDigit(int c) +{ + return (isxdigit(c) == 0 ? false : true); +} + +// Converts c to a 7-bit unsigned char value that fits into the +// ASCII character set, by clearing the high-order bits. +inline int toAscii(int c) +{ + return toascii(c); +} + +// Warning: +// Many people will be unhappy if you use this function. +// This function will convert accented letters into random +// characters. + +// Converts the letter c to lower case, if possible. +inline int toLowerCase(int c) +{ + return tolower(c); +} + +// Converts the letter c to upper case, if possible. +inline int toUpperCase(int c) +{ + return toupper(c); +} + +#endif diff --git a/cores/esp32/WMath.cpp b/cores/esp32/WMath.cpp new file mode 100644 index 00000000..fef0e94b --- /dev/null +++ b/cores/esp32/WMath.cpp @@ -0,0 +1,67 @@ +/* -*- mode: jde; c-basic-offset: 2; indent-tabs-mode: nil -*- */ + +/* + Part of the Wiring project - http://wiring.org.co + Copyright (c) 2004-06 Hernando Barragan + Modified 13 August 2006, David A. Mellis for Arduino - http://www.arduino.cc/ + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General + Public License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place, Suite 330, + Boston, MA 02111-1307 USA + + $Id$ + */ + +extern "C" { +#include +} + +void randomSeed(unsigned long seed) +{ + if(seed != 0) { + srand(seed); + } +} + +long random(long howbig) +{ + if(howbig == 0) { + return 0; + } + return rand() % howbig; +} + +long random(long howsmall, long howbig) +{ + if(howsmall >= howbig) { + return howsmall; + } + long diff = howbig - howsmall; + return random(diff) + howsmall; +} + +long map(long x, long in_min, long in_max, long out_min, long out_max) +{ + return (x - in_min) * (out_max - out_min) / (in_max - in_min) + out_min; +} + +unsigned int makeWord(unsigned int w) +{ + return w; +} + +unsigned int makeWord(unsigned char h, unsigned char l) +{ + return (h << 8) | l; +} diff --git a/cores/esp32/WString.cpp b/cores/esp32/WString.cpp new file mode 100644 index 00000000..e67eb7f9 --- /dev/null +++ b/cores/esp32/WString.cpp @@ -0,0 +1,894 @@ +/* + WString.cpp - String library for Wiring & Arduino + ...mostly rewritten by Paul Stoffregen... + Copyright (c) 2009-10 Hernando Barragan. All rights reserved. + Copyright 2011, Paul Stoffregen, paul@pjrc.com + Modified by Ivan Grokhotkov, 2014 - ESP31B support + Modified by Michael C. Miller, 2015 - ESP31B progmem support + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "WString.h" +#include "stdlib_noniso.h" +//extern "C" { +//#include "esp_common.h" +//} + +/*********************************************/ +/* Constructors */ +/*********************************************/ + +String::String(const char *cstr) +{ + init(); + if(cstr) { + copy(cstr, strlen(cstr)); + } +} + +String::String(const String &value) +{ + init(); + *this = value; +} +/* +String::String(const __FlashStringHelper *pstr) { + init(); + *this = pstr; // see operator = +} +*/ +#ifdef __GXX_EXPERIMENTAL_CXX0X__ +String::String(String &&rval) +{ + init(); + move(rval); +} + +String::String(StringSumHelper &&rval) +{ + init(); + move(rval); +} +#endif + +String::String(char c) +{ + init(); + char buf[2]; + buf[0] = c; + buf[1] = 0; + *this = buf; +} + +String::String(unsigned char value, unsigned char base) +{ + init(); + char buf[1 + 8 * sizeof(unsigned char)]; + utoa(value, buf, base); + *this = buf; +} + +String::String(int value, unsigned char base) +{ + init(); + char buf[2 + 8 * sizeof(int)]; + itoa(value, buf, base); + *this = buf; +} + +String::String(unsigned int value, unsigned char base) +{ + init(); + char buf[1 + 8 * sizeof(unsigned int)]; + utoa(value, buf, base); + *this = buf; +} + +String::String(long value, unsigned char base) +{ + init(); + char buf[2 + 8 * sizeof(long)]; + ltoa(value, buf, base); + *this = buf; +} + +String::String(unsigned long value, unsigned char base) +{ + init(); + char buf[1 + 8 * sizeof(unsigned long)]; + ultoa(value, buf, base); + *this = buf; +} + +String::String(float value, unsigned char decimalPlaces) +{ + init(); + char buf[33]; + *this = dtostrf(value, (decimalPlaces + 2), decimalPlaces, buf); +} + +String::String(double value, unsigned char decimalPlaces) +{ + init(); + char buf[33]; + *this = dtostrf(value, (decimalPlaces + 2), decimalPlaces, buf); +} + +String::~String() +{ + if(buffer) { + free(buffer); + } + init(); +} + +// /*********************************************/ +// /* Memory Management */ +// /*********************************************/ + +inline void String::init(void) +{ + buffer = NULL; + capacity = 0; + len = 0; +} + +void String::invalidate(void) +{ + if(buffer) { + free(buffer); + } + init(); +} + +unsigned char String::reserve(unsigned int size) +{ + if(buffer && capacity >= size) { + return 1; + } + if(changeBuffer(size)) { + if(len == 0) { + buffer[0] = 0; + } + return 1; + } + return 0; +} + +unsigned char String::changeBuffer(unsigned int maxStrLen) +{ + size_t newSize = (maxStrLen + 16) & (~0xf); + char *newbuffer = (char *) malloc(newSize); + if(newbuffer) { + memset(newbuffer, 0, newSize); + memcpy(newbuffer, buffer, len); + if (buffer) { + free(buffer); + } + capacity = newSize - 1; + buffer = newbuffer; + return 1; + } + buffer = newbuffer; + return 0; +} + +// /*********************************************/ +// /* Copy and Move */ +// /*********************************************/ + +String & String::copy(const char *cstr, unsigned int length) +{ + if(!reserve(length)) { + invalidate(); + return *this; + } + len = length; + strcpy(buffer, cstr); + return *this; +} +/* +String & String::copy(const __FlashStringHelper *pstr, unsigned int length) { + if (!reserve(length)) { + invalidate(); + return *this; + } + len = length; + strcpy_P(buffer, (PGM_P)pstr); + return *this; +} +*/ +#ifdef __GXX_EXPERIMENTAL_CXX0X__ +void String::move(String &rhs) +{ + if(buffer) { + if(capacity >= rhs.len) { + strcpy(buffer, rhs.buffer); + len = rhs.len; + rhs.len = 0; + return; + } else { + free(buffer); + } + } + buffer = rhs.buffer; + capacity = rhs.capacity; + len = rhs.len; + rhs.buffer = NULL; + rhs.capacity = 0; + rhs.len = 0; +} +#endif + +String & String::operator =(const String &rhs) +{ + if(this == &rhs) { + return *this; + } + + if(rhs.buffer) { + copy(rhs.buffer, rhs.len); + } else { + invalidate(); + } + + return *this; +} + +#ifdef __GXX_EXPERIMENTAL_CXX0X__ +String & String::operator =(String &&rval) +{ + if(this != &rval) { + move(rval); + } + return *this; +} + +String & String::operator =(StringSumHelper &&rval) +{ + if(this != &rval) { + move(rval); + } + return *this; +} +#endif + +String & String::operator =(const char *cstr) +{ + if(cstr) { + copy(cstr, strlen(cstr)); + } else { + invalidate(); + } + + return *this; +} +/* +String & String::operator = (const __FlashStringHelper *pstr) +{ + if (pstr) copy(pstr, strlen_P((PGM_P)pstr)); + else invalidate(); + + return *this; +} +*/ +// /*********************************************/ +// /* concat */ +// /*********************************************/ + +unsigned char String::concat(const String &s) +{ + return concat(s.buffer, s.len); +} + +unsigned char String::concat(const char *cstr, unsigned int length) +{ + unsigned int newlen = len + length; + if(!cstr) { + return 0; + } + if(length == 0) { + return 1; + } + if(!reserve(newlen)) { + return 0; + } + strcpy(buffer + len, cstr); + len = newlen; + return 1; +} + +unsigned char String::concat(const char *cstr) +{ + if(!cstr) { + return 0; + } + return concat(cstr, strlen(cstr)); +} + +unsigned char String::concat(char c) +{ + char buf[2]; + buf[0] = c; + buf[1] = 0; + return concat(buf, 1); +} + +unsigned char String::concat(unsigned char num) +{ + char buf[1 + 3 * sizeof(unsigned char)]; + itoa(num, buf, 10); + return concat(buf, strlen(buf)); +} + +unsigned char String::concat(int num) +{ + char buf[2 + 3 * sizeof(int)]; + itoa(num, buf, 10); + return concat(buf, strlen(buf)); +} + +unsigned char String::concat(unsigned int num) +{ + char buf[1 + 3 * sizeof(unsigned int)]; + utoa(num, buf, 10); + return concat(buf, strlen(buf)); +} + +unsigned char String::concat(long num) +{ + char buf[2 + 3 * sizeof(long)]; + ltoa(num, buf, 10); + return concat(buf, strlen(buf)); +} + +unsigned char String::concat(unsigned long num) +{ + char buf[1 + 3 * sizeof(unsigned long)]; + ultoa(num, buf, 10); + return concat(buf, strlen(buf)); +} + +unsigned char String::concat(float num) +{ + char buf[20]; + char* string = dtostrf(num, 4, 2, buf); + return concat(string, strlen(string)); +} + +unsigned char String::concat(double num) +{ + char buf[20]; + char* string = dtostrf(num, 4, 2, buf); + return concat(string, strlen(string)); +} +/* +unsigned char String::concat(const __FlashStringHelper * str) { + if (!str) return 0; + int length = strlen_P((PGM_P)str); + if (length == 0) return 1; + unsigned int newlen = len + length; + if (!reserve(newlen)) return 0; + strcpy_P(buffer + len, (PGM_P)str); + len = newlen; + return 1; +} +*/ +/*********************************************/ +/* Concatenate */ +/*********************************************/ + +StringSumHelper & operator +(const StringSumHelper &lhs, const String &rhs) +{ + StringSumHelper &a = const_cast(lhs); + if(!a.concat(rhs.buffer, rhs.len)) { + a.invalidate(); + } + return a; +} + +StringSumHelper & operator +(const StringSumHelper &lhs, const char *cstr) +{ + StringSumHelper &a = const_cast(lhs); + if(!cstr || !a.concat(cstr, strlen(cstr))) { + a.invalidate(); + } + return a; +} + +StringSumHelper & operator +(const StringSumHelper &lhs, char c) +{ + StringSumHelper &a = const_cast(lhs); + if(!a.concat(c)) { + a.invalidate(); + } + return a; +} + +StringSumHelper & operator +(const StringSumHelper &lhs, unsigned char num) +{ + StringSumHelper &a = const_cast(lhs); + if(!a.concat(num)) { + a.invalidate(); + } + return a; +} + +StringSumHelper & operator +(const StringSumHelper &lhs, int num) +{ + StringSumHelper &a = const_cast(lhs); + if(!a.concat(num)) { + a.invalidate(); + } + return a; +} + +StringSumHelper & operator +(const StringSumHelper &lhs, unsigned int num) +{ + StringSumHelper &a = const_cast(lhs); + if(!a.concat(num)) { + a.invalidate(); + } + return a; +} + +StringSumHelper & operator +(const StringSumHelper &lhs, long num) +{ + StringSumHelper &a = const_cast(lhs); + if(!a.concat(num)) { + a.invalidate(); + } + return a; +} + +StringSumHelper & operator +(const StringSumHelper &lhs, unsigned long num) +{ + StringSumHelper &a = const_cast(lhs); + if(!a.concat(num)) { + a.invalidate(); + } + return a; +} + +StringSumHelper & operator +(const StringSumHelper &lhs, float num) +{ + StringSumHelper &a = const_cast(lhs); + if(!a.concat(num)) { + a.invalidate(); + } + return a; +} + +StringSumHelper & operator +(const StringSumHelper &lhs, double num) +{ + StringSumHelper &a = const_cast(lhs); + if(!a.concat(num)) { + a.invalidate(); + } + return a; +} +/* +StringSumHelper & operator + (const StringSumHelper &lhs, const __FlashStringHelper *rhs) +{ + StringSumHelper &a = const_cast(lhs); + if (!a.concat(rhs)) a.invalidate(); + return a; +} +*/ +// /*********************************************/ +// /* Comparison */ +// /*********************************************/ + +int String::compareTo(const String &s) const +{ + if(!buffer || !s.buffer) { + if(s.buffer && s.len > 0) { + return 0 - *(unsigned char *) s.buffer; + } + if(buffer && len > 0) { + return *(unsigned char *) buffer; + } + return 0; + } + return strcmp(buffer, s.buffer); +} + +unsigned char String::equals(const String &s2) const +{ + return (len == s2.len && compareTo(s2) == 0); +} + +unsigned char String::equals(const char *cstr) const +{ + if(len == 0) { + return (cstr == NULL || *cstr == 0); + } + if(cstr == NULL) { + return buffer[0] == 0; + } + return strcmp(buffer, cstr) == 0; +} + +unsigned char String::operator<(const String &rhs) const +{ + return compareTo(rhs) < 0; +} + +unsigned char String::operator>(const String &rhs) const +{ + return compareTo(rhs) > 0; +} + +unsigned char String::operator<=(const String &rhs) const +{ + return compareTo(rhs) <= 0; +} + +unsigned char String::operator>=(const String &rhs) const +{ + return compareTo(rhs) >= 0; +} + +unsigned char String::equalsIgnoreCase(const String &s2) const +{ + if(this == &s2) { + return 1; + } + if(len != s2.len) { + return 0; + } + if(len == 0) { + return 1; + } + const char *p1 = buffer; + const char *p2 = s2.buffer; + while(*p1) { + if(tolower(*p1++) != tolower(*p2++)) { + return 0; + } + } + return 1; +} + +unsigned char String::startsWith(const String &s2) const +{ + if(len < s2.len) { + return 0; + } + return startsWith(s2, 0); +} + +unsigned char String::startsWith(const String &s2, unsigned int offset) const +{ + if(offset > len - s2.len || !buffer || !s2.buffer) { + return 0; + } + return strncmp(&buffer[offset], s2.buffer, s2.len) == 0; +} + +unsigned char String::endsWith(const String &s2) const +{ + if(len < s2.len || !buffer || !s2.buffer) { + return 0; + } + return strcmp(&buffer[len - s2.len], s2.buffer) == 0; +} + +// /*********************************************/ +// /* Character Access */ +// /*********************************************/ + +char String::charAt(unsigned int loc) const +{ + return operator[](loc); +} + +void String::setCharAt(unsigned int loc, char c) +{ + if(loc < len) { + buffer[loc] = c; + } +} + +char & String::operator[](unsigned int index) +{ + static char dummy_writable_char; + if(index >= len || !buffer) { + dummy_writable_char = 0; + return dummy_writable_char; + } + return buffer[index]; +} + +char String::operator[](unsigned int index) const +{ + if(index >= len || !buffer) { + return 0; + } + return buffer[index]; +} + +void String::getBytes(unsigned char *buf, unsigned int bufsize, unsigned int index) const +{ + if(!bufsize || !buf) { + return; + } + if(index >= len) { + buf[0] = 0; + return; + } + unsigned int n = bufsize - 1; + if(n > len - index) { + n = len - index; + } + strncpy((char *) buf, buffer + index, n); + buf[n] = 0; +} + +// /*********************************************/ +// /* Search */ +// /*********************************************/ + +int String::indexOf(char c) const +{ + return indexOf(c, 0); +} + +int String::indexOf(char ch, unsigned int fromIndex) const +{ + if(fromIndex >= len) { + return -1; + } + const char* temp = strchr(buffer + fromIndex, ch); + if(temp == NULL) { + return -1; + } + return temp - buffer; +} + +int String::indexOf(const String &s2) const +{ + return indexOf(s2, 0); +} + +int String::indexOf(const String &s2, unsigned int fromIndex) const +{ + if(fromIndex >= len) { + return -1; + } + const char *found = strstr(buffer + fromIndex, s2.buffer); + if(found == NULL) { + return -1; + } + return found - buffer; +} + +int String::lastIndexOf(char theChar) const +{ + return lastIndexOf(theChar, len - 1); +} + +int String::lastIndexOf(char ch, unsigned int fromIndex) const +{ + if(fromIndex >= len) { + return -1; + } + char tempchar = buffer[fromIndex + 1]; + buffer[fromIndex + 1] = '\0'; + char* temp = strrchr(buffer, ch); + buffer[fromIndex + 1] = tempchar; + if(temp == NULL) { + return -1; + } + return temp - buffer; +} + +int String::lastIndexOf(const String &s2) const +{ + return lastIndexOf(s2, len - s2.len); +} + +int String::lastIndexOf(const String &s2, unsigned int fromIndex) const +{ + if(s2.len == 0 || len == 0 || s2.len > len) { + return -1; + } + if(fromIndex >= len) { + fromIndex = len - 1; + } + int found = -1; + for(char *p = buffer; p <= buffer + fromIndex; p++) { + p = strstr(p, s2.buffer); + if(!p) { + break; + } + if((unsigned int) (p - buffer) <= fromIndex) { + found = p - buffer; + } + } + return found; +} + +String String::substring(unsigned int left, unsigned int right) const +{ + if(left > right) { + unsigned int temp = right; + right = left; + left = temp; + } + String out; + if(left >= len) { + return out; + } + if(right > len) { + right = len; + } + char temp = buffer[right]; // save the replaced character + buffer[right] = '\0'; + out = buffer + left; // pointer arithmetic + buffer[right] = temp; //restore character + return out; +} + +// /*********************************************/ +// /* Modification */ +// /*********************************************/ + +void String::replace(char find, char replace) +{ + if(!buffer) { + return; + } + for(char *p = buffer; *p; p++) { + if(*p == find) { + *p = replace; + } + } +} + +void String::replace(const String& find, const String& replace) +{ + if(len == 0 || find.len == 0) { + return; + } + int diff = replace.len - find.len; + char *readFrom = buffer; + char *foundAt; + if(diff == 0) { + while((foundAt = strstr(readFrom, find.buffer)) != NULL) { + memcpy(foundAt, replace.buffer, replace.len); + readFrom = foundAt + replace.len; + } + } else if(diff < 0) { + char *writeTo = buffer; + while((foundAt = strstr(readFrom, find.buffer)) != NULL) { + unsigned int n = foundAt - readFrom; + memcpy(writeTo, readFrom, n); + writeTo += n; + memcpy(writeTo, replace.buffer, replace.len); + writeTo += replace.len; + readFrom = foundAt + find.len; + len += diff; + } + strcpy(writeTo, readFrom); + } else { + unsigned int size = len; // compute size needed for result + while((foundAt = strstr(readFrom, find.buffer)) != NULL) { + readFrom = foundAt + find.len; + size += diff; + } + if(size == len) { + return; + } + if(size > capacity && !changeBuffer(size)) { + return; // XXX: tell user! + } + int index = len - 1; + while(index >= 0 && (index = lastIndexOf(find, index)) >= 0) { + readFrom = buffer + index + find.len; + memmove(readFrom + diff, readFrom, len - (readFrom - buffer)); + len += diff; + buffer[len] = 0; + memcpy(buffer + index, replace.buffer, replace.len); + index--; + } + } +} + +void String::remove(unsigned int index) +{ + // Pass the biggest integer as the count. The remove method + // below will take care of truncating it at the end of the + // string. + remove(index, (unsigned int) -1); +} + +void String::remove(unsigned int index, unsigned int count) +{ + if(index >= len) { + return; + } + if(count <= 0) { + return; + } + if(count > len - index) { + count = len - index; + } + char *writeTo = buffer + index; + len = len - count; + strncpy(writeTo, buffer + index + count, len - index); + buffer[len] = 0; +} + +void String::toLowerCase(void) +{ + if(!buffer) { + return; + } + for(char *p = buffer; *p; p++) { + *p = tolower(*p); + } +} + +void String::toUpperCase(void) +{ + if(!buffer) { + return; + } + for(char *p = buffer; *p; p++) { + *p = toupper(*p); + } +} + +void String::trim(void) +{ + if(!buffer || len == 0) { + return; + } + char *begin = buffer; + while(isspace(*begin)) { + begin++; + } + char *end = buffer + len - 1; + while(isspace(*end) && end >= begin) { + end--; + } + len = end + 1 - begin; + if(begin > buffer) { + memcpy(buffer, begin, len); + } + buffer[len] = 0; +} + +// /*********************************************/ +// /* Parsing / Conversion */ +// /*********************************************/ + +long String::toInt(void) const +{ + if(buffer) { + return atol(buffer); + } + return 0; +} + +float String::toFloat(void) const +{ + if(buffer) { + return atof(buffer); + } + return 0; +} diff --git a/cores/esp32/WString.h b/cores/esp32/WString.h new file mode 100644 index 00000000..604763aa --- /dev/null +++ b/cores/esp32/WString.h @@ -0,0 +1,327 @@ +/* + WString.h - String library for Wiring & Arduino + ...mostly rewritten by Paul Stoffregen... + Copyright (c) 2009-10 Hernando Barragan. All right reserved. + Copyright 2011, Paul Stoffregen, paul@pjrc.com + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef String_class_h +#define String_class_h +#ifdef __cplusplus + +#include +#include +#include +//#include + +// An inherited class for holding the result of a concatenation. These +// result objects are assumed to be writable by subsequent concatenations. +class StringSumHelper; + +// an abstract class used as a means to proide a unique pointer type +// but really has no body +class __FlashStringHelper; +#define FPSTR(pstr_pointer) (reinterpret_cast(pstr_pointer)) +#define F(string_literal) (FPSTR(PSTR(string_literal))) + +// The string class +class String +{ + // use a function pointer to allow for "if (s)" without the + // complications of an operator bool(). for more information, see: + // http://www.artima.com/cppsource/safebool.html + typedef void (String::*StringIfHelperType)() const; + void StringIfHelper() const + { + } + +public: + // constructors + // creates a copy of the initial value. + // if the initial value is null or invalid, or if memory allocation + // fails, the string will be marked as invalid (i.e. "if (s)" will + // be false). + String(const char *cstr = ""); + String(const String &str); + //String(const __FlashStringHelper *str); +#ifdef __GXX_EXPERIMENTAL_CXX0X__ + String(String &&rval); + String(StringSumHelper &&rval); +#endif + explicit String(char c); + explicit String(unsigned char, unsigned char base = 10); + explicit String(int, unsigned char base = 10); + explicit String(unsigned int, unsigned char base = 10); + explicit String(long, unsigned char base = 10); + explicit String(unsigned long, unsigned char base = 10); + explicit String(float, unsigned char decimalPlaces = 2); + explicit String(double, unsigned char decimalPlaces = 2); + ~String(void); + + // memory management + // return true on success, false on failure (in which case, the string + // is left unchanged). reserve(0), if successful, will validate an + // invalid string (i.e., "if (s)" will be true afterwards) + unsigned char reserve(unsigned int size); + inline unsigned int length(void) const + { + if(buffer) { + return len; + } else { + return 0; + } + } + + // creates a copy of the assigned value. if the value is null or + // invalid, or if the memory allocation fails, the string will be + // marked as invalid ("if (s)" will be false). + String & operator =(const String &rhs); + String & operator =(const char *cstr); + //String & operator = (const __FlashStringHelper *str); +#ifdef __GXX_EXPERIMENTAL_CXX0X__ + String & operator =(String &&rval); + String & operator =(StringSumHelper &&rval); +#endif + + // concatenate (works w/ built-in types) + + // returns true on success, false on failure (in which case, the string + // is left unchanged). if the argument is null or invalid, the + // concatenation is considered unsucessful. + unsigned char concat(const String &str); + unsigned char concat(const char *cstr); + unsigned char concat(char c); + unsigned char concat(unsigned char c); + unsigned char concat(int num); + unsigned char concat(unsigned int num); + unsigned char concat(long num); + unsigned char concat(unsigned long num); + unsigned char concat(float num); + unsigned char concat(double num); + //unsigned char concat(const __FlashStringHelper * str); + + // if there's not enough memory for the concatenated value, the string + // will be left unchanged (but this isn't signalled in any way) + String & operator +=(const String &rhs) + { + concat(rhs); + return (*this); + } + String & operator +=(const char *cstr) + { + concat(cstr); + return (*this); + } + String & operator +=(char c) + { + concat(c); + return (*this); + } + String & operator +=(unsigned char num) + { + concat(num); + return (*this); + } + String & operator +=(int num) + { + concat(num); + return (*this); + } + String & operator +=(unsigned int num) + { + concat(num); + return (*this); + } + String & operator +=(long num) + { + concat(num); + return (*this); + } + String & operator +=(unsigned long num) + { + concat(num); + return (*this); + } + String & operator +=(float num) + { + concat(num); + return (*this); + } + String & operator +=(double num) + { + concat(num); + return (*this); + } + //String & operator += (const __FlashStringHelper *str){ + // concat(str); + // return (*this); + //} + + friend StringSumHelper & operator +(const StringSumHelper &lhs, const String &rhs); + friend StringSumHelper & operator +(const StringSumHelper &lhs, const char *cstr); + friend StringSumHelper & operator +(const StringSumHelper &lhs, char c); + friend StringSumHelper & operator +(const StringSumHelper &lhs, unsigned char num); + friend StringSumHelper & operator +(const StringSumHelper &lhs, int num); + friend StringSumHelper & operator +(const StringSumHelper &lhs, unsigned int num); + friend StringSumHelper & operator +(const StringSumHelper &lhs, long num); + friend StringSumHelper & operator +(const StringSumHelper &lhs, unsigned long num); + friend StringSumHelper & operator +(const StringSumHelper &lhs, float num); + friend StringSumHelper & operator +(const StringSumHelper &lhs, double num); + //friend StringSumHelper & operator +(const StringSumHelper &lhs, const __FlashStringHelper *rhs); + + // comparison (only works w/ Strings and "strings") + operator StringIfHelperType() const + { + return buffer ? &String::StringIfHelper : 0; + } + int compareTo(const String &s) const; + unsigned char equals(const String &s) const; + unsigned char equals(const char *cstr) const; + unsigned char operator ==(const String &rhs) const + { + return equals(rhs); + } + unsigned char operator ==(const char *cstr) const + { + return equals(cstr); + } + unsigned char operator !=(const String &rhs) const + { + return !equals(rhs); + } + unsigned char operator !=(const char *cstr) const + { + return !equals(cstr); + } + unsigned char operator <(const String &rhs) const; + unsigned char operator >(const String &rhs) const; + unsigned char operator <=(const String &rhs) const; + unsigned char operator >=(const String &rhs) const; + unsigned char equalsIgnoreCase(const String &s) const; + unsigned char startsWith(const String &prefix) const; + unsigned char startsWith(const String &prefix, unsigned int offset) const; + unsigned char endsWith(const String &suffix) const; + + // character acccess + char charAt(unsigned int index) const; + void setCharAt(unsigned int index, char c); + char operator [](unsigned int index) const; + char& operator [](unsigned int index); + void getBytes(unsigned char *buf, unsigned int bufsize, unsigned int index = 0) const; + void toCharArray(char *buf, unsigned int bufsize, unsigned int index = 0) const + { + getBytes((unsigned char *) buf, bufsize, index); + } + const char * c_str() const + { + return buffer; + } + + // search + int indexOf(char ch) const; + int indexOf(char ch, unsigned int fromIndex) const; + int indexOf(const String &str) const; + int indexOf(const String &str, unsigned int fromIndex) const; + int lastIndexOf(char ch) const; + int lastIndexOf(char ch, unsigned int fromIndex) const; + int lastIndexOf(const String &str) const; + int lastIndexOf(const String &str, unsigned int fromIndex) const; + String substring(unsigned int beginIndex) const + { + return substring(beginIndex, len); + } + ; + String substring(unsigned int beginIndex, unsigned int endIndex) const; + + // modification + void replace(char find, char replace); + void replace(const String& find, const String& replace); + void remove(unsigned int index); + void remove(unsigned int index, unsigned int count); + void toLowerCase(void); + void toUpperCase(void); + void trim(void); + + // parsing/conversion + long toInt(void) const; + float toFloat(void) const; + +protected: + char *buffer; // the actual char array + unsigned int capacity; // the array length minus one (for the '\0') + unsigned int len; // the String length (not counting the '\0') +protected: + void init(void); + void invalidate(void); + unsigned char changeBuffer(unsigned int maxStrLen); + unsigned char concat(const char *cstr, unsigned int length); + + // copy and move + String & copy(const char *cstr, unsigned int length); + //String & copy(const __FlashStringHelper *pstr, unsigned int length); +#ifdef __GXX_EXPERIMENTAL_CXX0X__ + void move(String &rhs); +#endif +}; + +class StringSumHelper: public String +{ +public: + StringSumHelper(const String &s) : + String(s) + { + } + StringSumHelper(const char *p) : + String(p) + { + } + StringSumHelper(char c) : + String(c) + { + } + StringSumHelper(unsigned char num) : + String(num) + { + } + StringSumHelper(int num) : + String(num) + { + } + StringSumHelper(unsigned int num) : + String(num) + { + } + StringSumHelper(long num) : + String(num) + { + } + StringSumHelper(unsigned long num) : + String(num) + { + } + StringSumHelper(float num) : + String(num) + { + } + StringSumHelper(double num) : + String(num) + { + } +}; + +#endif // __cplusplus +#endif // String_class_h diff --git a/cores/esp32/base64.cpp b/cores/esp32/base64.cpp new file mode 100644 index 00000000..b95064ae --- /dev/null +++ b/cores/esp32/base64.cpp @@ -0,0 +1,65 @@ +/** + * base64.cpp + * + * Created on: 09.12.2015 + * + * Copyright (c) 2015 Markus Sattler. All rights reserved. + * This file is part of the ESP31B core for Arduino. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +#include "Arduino.h" +extern "C" { +#include "libb64/cdecode.h" +#include "libb64/cencode.h" +} +#include "base64.h" + +/** + * convert input data to base64 + * @param data uint8_t * + * @param length size_t + * @return String + */ +String base64::encode(uint8_t * data, size_t length) +{ + // base64 needs more size then the source data + size_t size = ((length * 1.6f) + 1); + char * buffer = (char *) malloc(size); + if(buffer) { + base64_encodestate _state; + base64_init_encodestate(&_state); + int len = base64_encode_block((const char *) &data[0], length, &buffer[0], &_state); + len = base64_encode_blockend((buffer + len), &_state); + + String base64 = String(buffer); + free(buffer); + return base64; + } + return String("-FAIL-"); +} + +/** + * convert input data to base64 + * @param text String + * @return String + */ +String base64::encode(String text) +{ + return base64::encode((uint8_t *) text.c_str(), text.length()); +} + diff --git a/cores/esp32/base64.h b/cores/esp32/base64.h new file mode 100644 index 00000000..f2466521 --- /dev/null +++ b/cores/esp32/base64.h @@ -0,0 +1,13 @@ +#ifndef CORE_BASE64_H_ +#define CORE_BASE64_H_ + +class base64 +{ +public: + static String encode(uint8_t * data, size_t length); + static String encode(String text); +private: +}; + + +#endif /* CORE_BASE64_H_ */ diff --git a/cores/esp32/binary.h b/cores/esp32/binary.h new file mode 100644 index 00000000..c2f189da --- /dev/null +++ b/cores/esp32/binary.h @@ -0,0 +1,534 @@ +/* + binary.h - Definitions for binary constants + Copyright (c) 2006 David A. Mellis. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef Binary_h +#define Binary_h + +#define B0 0 +#define B00 0 +#define B000 0 +#define B0000 0 +#define B00000 0 +#define B000000 0 +#define B0000000 0 +#define B00000000 0 +#define B1 1 +#define B01 1 +#define B001 1 +#define B0001 1 +#define B00001 1 +#define B000001 1 +#define B0000001 1 +#define B00000001 1 +#define B10 2 +#define B010 2 +#define B0010 2 +#define B00010 2 +#define B000010 2 +#define B0000010 2 +#define B00000010 2 +#define B11 3 +#define B011 3 +#define B0011 3 +#define B00011 3 +#define B000011 3 +#define B0000011 3 +#define B00000011 3 +#define B100 4 +#define B0100 4 +#define B00100 4 +#define B000100 4 +#define B0000100 4 +#define B00000100 4 +#define B101 5 +#define B0101 5 +#define B00101 5 +#define B000101 5 +#define B0000101 5 +#define B00000101 5 +#define B110 6 +#define B0110 6 +#define B00110 6 +#define B000110 6 +#define B0000110 6 +#define B00000110 6 +#define B111 7 +#define B0111 7 +#define B00111 7 +#define B000111 7 +#define B0000111 7 +#define B00000111 7 +#define B1000 8 +#define B01000 8 +#define B001000 8 +#define B0001000 8 +#define B00001000 8 +#define B1001 9 +#define B01001 9 +#define B001001 9 +#define B0001001 9 +#define B00001001 9 +#define B1010 10 +#define B01010 10 +#define B001010 10 +#define B0001010 10 +#define B00001010 10 +#define B1011 11 +#define B01011 11 +#define B001011 11 +#define B0001011 11 +#define B00001011 11 +#define B1100 12 +#define B01100 12 +#define B001100 12 +#define B0001100 12 +#define B00001100 12 +#define B1101 13 +#define B01101 13 +#define B001101 13 +#define B0001101 13 +#define B00001101 13 +#define B1110 14 +#define B01110 14 +#define B001110 14 +#define B0001110 14 +#define B00001110 14 +#define B1111 15 +#define B01111 15 +#define B001111 15 +#define B0001111 15 +#define B00001111 15 +#define B10000 16 +#define B010000 16 +#define B0010000 16 +#define B00010000 16 +#define B10001 17 +#define B010001 17 +#define B0010001 17 +#define B00010001 17 +#define B10010 18 +#define B010010 18 +#define B0010010 18 +#define B00010010 18 +#define B10011 19 +#define B010011 19 +#define B0010011 19 +#define B00010011 19 +#define B10100 20 +#define B010100 20 +#define B0010100 20 +#define B00010100 20 +#define B10101 21 +#define B010101 21 +#define B0010101 21 +#define B00010101 21 +#define B10110 22 +#define B010110 22 +#define B0010110 22 +#define B00010110 22 +#define B10111 23 +#define B010111 23 +#define B0010111 23 +#define B00010111 23 +#define B11000 24 +#define B011000 24 +#define B0011000 24 +#define B00011000 24 +#define B11001 25 +#define B011001 25 +#define B0011001 25 +#define B00011001 25 +#define B11010 26 +#define B011010 26 +#define B0011010 26 +#define B00011010 26 +#define B11011 27 +#define B011011 27 +#define B0011011 27 +#define B00011011 27 +#define B11100 28 +#define B011100 28 +#define B0011100 28 +#define B00011100 28 +#define B11101 29 +#define B011101 29 +#define B0011101 29 +#define B00011101 29 +#define B11110 30 +#define B011110 30 +#define B0011110 30 +#define B00011110 30 +#define B11111 31 +#define B011111 31 +#define B0011111 31 +#define B00011111 31 +#define B100000 32 +#define B0100000 32 +#define B00100000 32 +#define B100001 33 +#define B0100001 33 +#define B00100001 33 +#define B100010 34 +#define B0100010 34 +#define B00100010 34 +#define B100011 35 +#define B0100011 35 +#define B00100011 35 +#define B100100 36 +#define B0100100 36 +#define B00100100 36 +#define B100101 37 +#define B0100101 37 +#define B00100101 37 +#define B100110 38 +#define B0100110 38 +#define B00100110 38 +#define B100111 39 +#define B0100111 39 +#define B00100111 39 +#define B101000 40 +#define B0101000 40 +#define B00101000 40 +#define B101001 41 +#define B0101001 41 +#define B00101001 41 +#define B101010 42 +#define B0101010 42 +#define B00101010 42 +#define B101011 43 +#define B0101011 43 +#define B00101011 43 +#define B101100 44 +#define B0101100 44 +#define B00101100 44 +#define B101101 45 +#define B0101101 45 +#define B00101101 45 +#define B101110 46 +#define B0101110 46 +#define B00101110 46 +#define B101111 47 +#define B0101111 47 +#define B00101111 47 +#define B110000 48 +#define B0110000 48 +#define B00110000 48 +#define B110001 49 +#define B0110001 49 +#define B00110001 49 +#define B110010 50 +#define B0110010 50 +#define B00110010 50 +#define B110011 51 +#define B0110011 51 +#define B00110011 51 +#define B110100 52 +#define B0110100 52 +#define B00110100 52 +#define B110101 53 +#define B0110101 53 +#define B00110101 53 +#define B110110 54 +#define B0110110 54 +#define B00110110 54 +#define B110111 55 +#define B0110111 55 +#define B00110111 55 +#define B111000 56 +#define B0111000 56 +#define B00111000 56 +#define B111001 57 +#define B0111001 57 +#define B00111001 57 +#define B111010 58 +#define B0111010 58 +#define B00111010 58 +#define B111011 59 +#define B0111011 59 +#define B00111011 59 +#define B111100 60 +#define B0111100 60 +#define B00111100 60 +#define B111101 61 +#define B0111101 61 +#define B00111101 61 +#define B111110 62 +#define B0111110 62 +#define B00111110 62 +#define B111111 63 +#define B0111111 63 +#define B00111111 63 +#define B1000000 64 +#define B01000000 64 +#define B1000001 65 +#define B01000001 65 +#define B1000010 66 +#define B01000010 66 +#define B1000011 67 +#define B01000011 67 +#define B1000100 68 +#define B01000100 68 +#define B1000101 69 +#define B01000101 69 +#define B1000110 70 +#define B01000110 70 +#define B1000111 71 +#define B01000111 71 +#define B1001000 72 +#define B01001000 72 +#define B1001001 73 +#define B01001001 73 +#define B1001010 74 +#define B01001010 74 +#define B1001011 75 +#define B01001011 75 +#define B1001100 76 +#define B01001100 76 +#define B1001101 77 +#define B01001101 77 +#define B1001110 78 +#define B01001110 78 +#define B1001111 79 +#define B01001111 79 +#define B1010000 80 +#define B01010000 80 +#define B1010001 81 +#define B01010001 81 +#define B1010010 82 +#define B01010010 82 +#define B1010011 83 +#define B01010011 83 +#define B1010100 84 +#define B01010100 84 +#define B1010101 85 +#define B01010101 85 +#define B1010110 86 +#define B01010110 86 +#define B1010111 87 +#define B01010111 87 +#define B1011000 88 +#define B01011000 88 +#define B1011001 89 +#define B01011001 89 +#define B1011010 90 +#define B01011010 90 +#define B1011011 91 +#define B01011011 91 +#define B1011100 92 +#define B01011100 92 +#define B1011101 93 +#define B01011101 93 +#define B1011110 94 +#define B01011110 94 +#define B1011111 95 +#define B01011111 95 +#define B1100000 96 +#define B01100000 96 +#define B1100001 97 +#define B01100001 97 +#define B1100010 98 +#define B01100010 98 +#define B1100011 99 +#define B01100011 99 +#define B1100100 100 +#define B01100100 100 +#define B1100101 101 +#define B01100101 101 +#define B1100110 102 +#define B01100110 102 +#define B1100111 103 +#define B01100111 103 +#define B1101000 104 +#define B01101000 104 +#define B1101001 105 +#define B01101001 105 +#define B1101010 106 +#define B01101010 106 +#define B1101011 107 +#define B01101011 107 +#define B1101100 108 +#define B01101100 108 +#define B1101101 109 +#define B01101101 109 +#define B1101110 110 +#define B01101110 110 +#define B1101111 111 +#define B01101111 111 +#define B1110000 112 +#define B01110000 112 +#define B1110001 113 +#define B01110001 113 +#define B1110010 114 +#define B01110010 114 +#define B1110011 115 +#define B01110011 115 +#define B1110100 116 +#define B01110100 116 +#define B1110101 117 +#define B01110101 117 +#define B1110110 118 +#define B01110110 118 +#define B1110111 119 +#define B01110111 119 +#define B1111000 120 +#define B01111000 120 +#define B1111001 121 +#define B01111001 121 +#define B1111010 122 +#define B01111010 122 +#define B1111011 123 +#define B01111011 123 +#define B1111100 124 +#define B01111100 124 +#define B1111101 125 +#define B01111101 125 +#define B1111110 126 +#define B01111110 126 +#define B1111111 127 +#define B01111111 127 +#define B10000000 128 +#define B10000001 129 +#define B10000010 130 +#define B10000011 131 +#define B10000100 132 +#define B10000101 133 +#define B10000110 134 +#define B10000111 135 +#define B10001000 136 +#define B10001001 137 +#define B10001010 138 +#define B10001011 139 +#define B10001100 140 +#define B10001101 141 +#define B10001110 142 +#define B10001111 143 +#define B10010000 144 +#define B10010001 145 +#define B10010010 146 +#define B10010011 147 +#define B10010100 148 +#define B10010101 149 +#define B10010110 150 +#define B10010111 151 +#define B10011000 152 +#define B10011001 153 +#define B10011010 154 +#define B10011011 155 +#define B10011100 156 +#define B10011101 157 +#define B10011110 158 +#define B10011111 159 +#define B10100000 160 +#define B10100001 161 +#define B10100010 162 +#define B10100011 163 +#define B10100100 164 +#define B10100101 165 +#define B10100110 166 +#define B10100111 167 +#define B10101000 168 +#define B10101001 169 +#define B10101010 170 +#define B10101011 171 +#define B10101100 172 +#define B10101101 173 +#define B10101110 174 +#define B10101111 175 +#define B10110000 176 +#define B10110001 177 +#define B10110010 178 +#define B10110011 179 +#define B10110100 180 +#define B10110101 181 +#define B10110110 182 +#define B10110111 183 +#define B10111000 184 +#define B10111001 185 +#define B10111010 186 +#define B10111011 187 +#define B10111100 188 +#define B10111101 189 +#define B10111110 190 +#define B10111111 191 +#define B11000000 192 +#define B11000001 193 +#define B11000010 194 +#define B11000011 195 +#define B11000100 196 +#define B11000101 197 +#define B11000110 198 +#define B11000111 199 +#define B11001000 200 +#define B11001001 201 +#define B11001010 202 +#define B11001011 203 +#define B11001100 204 +#define B11001101 205 +#define B11001110 206 +#define B11001111 207 +#define B11010000 208 +#define B11010001 209 +#define B11010010 210 +#define B11010011 211 +#define B11010100 212 +#define B11010101 213 +#define B11010110 214 +#define B11010111 215 +#define B11011000 216 +#define B11011001 217 +#define B11011010 218 +#define B11011011 219 +#define B11011100 220 +#define B11011101 221 +#define B11011110 222 +#define B11011111 223 +#define B11100000 224 +#define B11100001 225 +#define B11100010 226 +#define B11100011 227 +#define B11100100 228 +#define B11100101 229 +#define B11100110 230 +#define B11100111 231 +#define B11101000 232 +#define B11101001 233 +#define B11101010 234 +#define B11101011 235 +#define B11101100 236 +#define B11101101 237 +#define B11101110 238 +#define B11101111 239 +#define B11110000 240 +#define B11110001 241 +#define B11110010 242 +#define B11110011 243 +#define B11110100 244 +#define B11110101 245 +#define B11110110 246 +#define B11110111 247 +#define B11111000 248 +#define B11111001 249 +#define B11111010 250 +#define B11111011 251 +#define B11111100 252 +#define B11111101 253 +#define B11111110 254 +#define B11111111 255 + +#endif diff --git a/cores/esp32/cbuf.cpp b/cores/esp32/cbuf.cpp new file mode 100644 index 00000000..7175a5f5 --- /dev/null +++ b/cores/esp32/cbuf.cpp @@ -0,0 +1,196 @@ +/* + cbuf.cpp - Circular buffer implementation + Copyright (c) 2014 Ivan Grokhotkov. All rights reserved. + This file is part of the esp8266 core for Arduino environment. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "cbuf.h" + +cbuf::cbuf(size_t size) : + next(NULL), _size(size), _buf(new char[size]), _bufend(_buf + size), _begin(_buf), _end(_begin) +{ +} + +cbuf::~cbuf() +{ + delete[] _buf; +} + +size_t cbuf::resizeAdd(size_t addSize) +{ + return resize(_size + addSize); +} + +size_t cbuf::resize(size_t newSize) +{ + + size_t bytes_available = available(); + + // not lose any data + // if data can be lost use remove or flush before resize + if((newSize < bytes_available) || (newSize == _size)) { + return _size; + } + + char *newbuf = new char[newSize]; + char *oldbuf = _buf; + + if(!newbuf) { + return _size; + } + + if(_buf) { + read(newbuf, bytes_available); + memset((newbuf + bytes_available), 0x00, (newSize - bytes_available)); + } + + _begin = newbuf; + _end = newbuf + bytes_available; + _bufend = newbuf + newSize; + _size = newSize; + + _buf = newbuf; + delete[] oldbuf; + + return _size; +} + +size_t cbuf::available() const +{ + if(_end >= _begin) { + return _end - _begin; + } + return _size - (_begin - _end); +} + +size_t cbuf::size() +{ + return _size; +} + +size_t cbuf::room() const +{ + if(_end >= _begin) { + return _size - (_end - _begin) - 1; + } + return _begin - _end - 1; +} + +int cbuf::peek() +{ + if(empty()) { + return -1; + } + + return static_cast(*_begin); +} + +size_t cbuf::peek(char *dst, size_t size) +{ + size_t bytes_available = available(); + size_t size_to_read = (size < bytes_available) ? size : bytes_available; + size_t size_read = size_to_read; + char * begin = _begin; + if(_end < _begin && size_to_read > (size_t) (_bufend - _begin)) { + size_t top_size = _bufend - _begin; + memcpy(dst, _begin, top_size); + begin = _buf; + size_to_read -= top_size; + dst += top_size; + } + memcpy(dst, begin, size_to_read); + return size_read; +} + +int cbuf::read() +{ + if(empty()) { + return -1; + } + + char result = *_begin; + _begin = wrap_if_bufend(_begin + 1); + return static_cast(result); +} + +size_t cbuf::read(char* dst, size_t size) +{ + size_t bytes_available = available(); + size_t size_to_read = (size < bytes_available) ? size : bytes_available; + size_t size_read = size_to_read; + if(_end < _begin && size_to_read > (size_t) (_bufend - _begin)) { + size_t top_size = _bufend - _begin; + memcpy(dst, _begin, top_size); + _begin = _buf; + size_to_read -= top_size; + dst += top_size; + } + memcpy(dst, _begin, size_to_read); + _begin = wrap_if_bufend(_begin + size_to_read); + return size_read; +} + +size_t cbuf::write(char c) +{ + if(full()) { + return 0; + } + + *_end = c; + _end = wrap_if_bufend(_end + 1); + return 1; +} + +size_t cbuf::write(const char* src, size_t size) +{ + size_t bytes_available = room(); + size_t size_to_write = (size < bytes_available) ? size : bytes_available; + size_t size_written = size_to_write; + if(_end >= _begin && size_to_write > (size_t) (_bufend - _end)) { + size_t top_size = _bufend - _end; + memcpy(_end, src, top_size); + _end = _buf; + size_to_write -= top_size; + src += top_size; + } + memcpy(_end, src, size_to_write); + _end = wrap_if_bufend(_end + size_to_write); + return size_written; +} + +void cbuf::flush() +{ + _begin = _buf; + _end = _buf; +} + +size_t cbuf::remove(size_t size) +{ + size_t bytes_available = available(); + if(size >= bytes_available) { + flush(); + return 0; + } + size_t size_to_remove = (size < bytes_available) ? size : bytes_available; + if(_end < _begin && size_to_remove > (size_t) (_bufend - _begin)) { + size_t top_size = _bufend - _begin; + _begin = _buf; + size_to_remove -= top_size; + } + _begin = wrap_if_bufend(_begin + size_to_remove); + return available(); +} diff --git a/cores/esp32/cbuf.h b/cores/esp32/cbuf.h new file mode 100644 index 00000000..ca65affc --- /dev/null +++ b/cores/esp32/cbuf.h @@ -0,0 +1,79 @@ +/* + cbuf.h - Circular buffer implementation + Copyright (c) 2014 Ivan Grokhotkov. All rights reserved. + This file is part of the esp8266 core for Arduino environment. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __cbuf_h +#define __cbuf_h + +#include +#include +#include + +class cbuf +{ +public: + cbuf(size_t size); + ~cbuf(); + + size_t resizeAdd(size_t addSize); + size_t resize(size_t newSize); + size_t available() const; + size_t size(); + + size_t room() const; + + inline bool empty() const + { + return _begin == _end; + } + + inline bool full() const + { + return wrap_if_bufend(_end + 1) == _begin; + } + + int peek(); + size_t peek(char *dst, size_t size); + + int read(); + size_t read(char* dst, size_t size); + + size_t write(char c); + size_t write(const char* src, size_t size); + + void flush(); + size_t remove(size_t size); + + cbuf *next; + +private: + inline char* wrap_if_bufend(char* ptr) const + { + return (ptr == _bufend) ? _buf : ptr; + } + + size_t _size; + char* _buf; + const char* _bufend; + char* _begin; + char* _end; + +}; + +#endif//__cbuf_h diff --git a/cores/esp32/esp32-hal-gpio.c b/cores/esp32/esp32-hal-gpio.c new file mode 100644 index 00000000..729b56f3 --- /dev/null +++ b/cores/esp32/esp32-hal-gpio.c @@ -0,0 +1,217 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "esp32-hal-gpio.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "rom/ets_sys.h" +#include "esp_attr.h" +#include "esp_intr.h" +#include "rom/gpio.h" +#include "soc/gpio_reg.h" +#include "soc/io_mux_reg.h" +#include "soc/gpio_struct.h" + +#define ETS_GPIO_INUM 4 + +const uint8_t esp32_gpioToFn[40] = { + 0x44,//0 + 0x88,//1 + 0x40,//2 + 0x84,//3 + 0x48,//4 + 0x6c,//5 + 0x60,//6 + 0x64,//7 + 0x68,//8 + 0x54,//9 + 0x58,//10 + 0x5c,//11 + 0x34,//12 + 0x38,//13 + 0x30,//14 + 0x3c,//15 + 0x4c,//16 + 0x50,//17 + 0x70,//18 + 0x74,//19 + 0x78,//20 + 0x7c,//21 + 0x80,//22 + 0x8c,//23 + 0xFF,//N/A + 0x24,//25 + 0x28,//26 + 0x2c,//27 + 0xFF,//N/A + 0xFF,//N/A + 0xFF,//N/A + 0xFF,//N/A + 0x1c,//32 + 0x20,//33 + 0x14,//34 + 0x18,//35 + 0x04,//36 + 0x08,//37 + 0x0c,//38 + 0x10 //39 +}; + +typedef void (*voidFuncPtr)(void); +static voidFuncPtr __pinInterruptHandlers[GPIO_PIN_COUNT] = {0,}; + +extern void IRAM_ATTR __pinMode(uint8_t pin, uint8_t mode) +{ + uint32_t pinFunction = 0, pinControl = 0; + + if(pin > 39 || esp32_gpioToFn[pin] == 0xFF) { + return; + } + + if(mode & INPUT) { + if(pin < 32) { + GPIO.enable_w1tc = ((uint32_t)1 << pin); + } else { + GPIO.enable1_w1tc.val = ((uint32_t)1 << (pin - 32)); + } + + if(mode & PULLUP) { + pinFunction |= FUN_PU; + } else if(mode & PULLDOWN) { + pinFunction |= FUN_PD; + } + + } else if(mode & OUTPUT) { + if(pin < 32) { + GPIO.enable_w1ts = ((uint32_t)1 << pin); + } else { + GPIO.enable1_w1ts.val = ((uint32_t)1 << (pin - 32)); + } + } + + pinFunction |= ((uint32_t)2 << FUN_DRV_S);//what are the drivers? + pinFunction |= FUN_IE;//input enable but required for output as well? + + if(mode & (INPUT | OUTPUT)) { + pinFunction |= ((uint32_t)2 << MCU_SEL_S); + } else if(mode == SPECIAL) { + pinFunction |= ((uint32_t)(((pin)==1||(pin)==3)?0:1) << MCU_SEL_S); + } else { + pinFunction |= ((uint32_t)(mode >> 5) << MCU_SEL_S); + } + + if(mode & OPEN_DRAIN) { + pinControl = (1 << GPIO_PIN0_PAD_DRIVER_S); + } + + ESP_REG(DR_REG_IO_MUX_BASE + esp32_gpioToFn[pin]) = pinFunction; + GPIO.pin[pin].val = pinControl; +} + +extern void IRAM_ATTR __digitalWrite(uint8_t pin, uint8_t val) +{ + if(pin > 39) { + return; + } + if(val) { + if(pin < 32) { + GPIO.out_w1ts = ((uint32_t)1 << pin); + } else { + GPIO.out1_w1ts.val = ((uint32_t)1 << (pin - 32)); + } + } else { + if(pin < 32) { + GPIO.out_w1tc = ((uint32_t)1 << pin); + } else { + GPIO.out1_w1tc.val = ((uint32_t)1 << (pin - 32)); + } + } +} + +extern int IRAM_ATTR __digitalRead(uint8_t pin) +{ + if(pin > 39) { + return 0; + } + if(pin < 32) { + return (GPIO.in >> pin) & 0x1; + } else { + return (GPIO.in1.val >> (pin - 32)) & 0x1; + } +} + + +static void IRAM_ATTR __onPinInterrupt(void *arg) +{ + uint32_t gpio_intr_status_l=0; + uint32_t gpio_intr_status_h=0; + + gpio_intr_status_l = GPIO.status; + gpio_intr_status_h = GPIO.status1.val; + GPIO.status_w1tc = gpio_intr_status_l;//Clear intr for gpio0-gpio31 + GPIO.status1_w1tc.val = gpio_intr_status_h;//Clear intr for gpio32-39 + + uint8_t pin=0; + if(gpio_intr_status_l) { + do { + if(gpio_intr_status_l & ((uint32_t)1 << pin)) { + if(__pinInterruptHandlers[pin]) { + __pinInterruptHandlers[pin](); + } + } + } while(++pin<32); + } + if(gpio_intr_status_h) { + pin=32; + do { + if(gpio_intr_status_h & ((uint32_t)1 << (pin - 32))) { + if(__pinInterruptHandlers[pin]) { + __pinInterruptHandlers[pin](); + } + } + } while(++pinnum), false, false); + pinMatrixInAttach(scl, I2C_SCL_IDX(i2c->num), false); +} + +void i2cDetachSCL(i2c_t * i2c, int8_t scl) +{ + pinMatrixOutDetach(scl, false, false); + pinMatrixInDetach(I2C_SCL_IDX(i2c->num), false, false); + pinMode(scl, INPUT); +} + +void i2cAttachSDA(i2c_t * i2c, int8_t sda) +{ + pinMode(sda, INPUT); + pinMatrixOutAttach(sda, I2C_SDA_IDX(i2c->num), false, false); + pinMatrixInAttach(sda, I2C_SDA_IDX(i2c->num), false); +} + +void i2cDetachSDA(i2c_t * i2c, int8_t sda) +{ + pinMatrixOutDetach(sda, false, false); + pinMatrixInDetach(I2C_SDA_IDX(i2c->num), false, false); + pinMode(sda, INPUT); +} + +enum { + I2C_CMD_RSTART, + I2C_CMD_WRITE, + I2C_CMD_READ, + I2C_CMD_STOP, + I2C_CMD_END +}; + +/* + * index - command index (0 to 15) + * op_code - is the command + * ack_val - Each data byte is terminated by an ACK bit used to set the bit level. + * ack_exp - This bit is to set an expected ACK value for the transmitter. + * ack_check - This bit is to decide whether the transmitter checks ACK bit. 1 means yes and 0 means no. + * byte_num - This register is to store the amounts of data that is read and written. byte_num in RSTART, STOP, END is null. + * */ +void i2cSetCmd(i2c_t * i2c, uint8_t index, uint8_t op_code, uint8_t byte_num, bool ack_val, bool ack_exp, bool ack_check) +{ + i2c->dev->command[index].val = 0; + i2c->dev->command[index].ack_en = ack_check; + i2c->dev->command[index].ack_exp = ack_exp; + i2c->dev->command[index].ack_val = ack_val; + i2c->dev->command[index].byte_num = byte_num; + i2c->dev->command[index].op_code = op_code; +} + +int i2cWrite(i2c_t * i2c, uint16_t address, bool addr_10bit, uint8_t * data, uint8_t len, bool sendStop) +{ + uint8_t index = 0; + uint8_t dataLen = len + (addr_10bit?2:1); + address = (address << 1); + + while(dataLen) { + uint8_t willSend = (dataLen > 32)?32:dataLen; + uint8_t dataSend = willSend; + i2cSetCmd(i2c, 0, I2C_CMD_RSTART, 0, false, false, false);//START + i2cSetCmd(i2c, 1, I2C_CMD_WRITE, willSend, false, false, true); + if(!index) { + i2c->dev->fifo_data.data = address & 0xFF; + dataSend--; + if(addr_10bit) { + i2c->dev->fifo_data.data = (address >> 8) & 0xFF; + dataSend--; + } + } + int i = 0; + while(idev->fifo_data.data = data[index++]; + } + dataLen -= willSend; + if(dataLen) { + i2cSetCmd(i2c, 2, I2C_CMD_END, 0, false, false, false); + } else if(sendStop) { + i2cSetCmd(i2c, 2, I2C_CMD_STOP, 0, false, false, true); + } + i2c->dev->ctr.trans_start = 1; + while(i2c->dev->ctr.trans_start || i2c->dev->status_reg.bus_busy || (!i2c->dev->int_raw.ack_err && !i2c->dev->command[2].done)); + if(!i2c->dev->command[2].done) { + log_e("Ack Error"); + return -1; + } + if(i2c->dev->status_reg.arb_lost || i2c->dev->status_reg.time_out) { + log_e("Bus Fail"); + return -1; + } + } + return 0; +} + +int i2cRead(i2c_t * i2c, uint16_t address, bool addr_10bit, uint8_t * data, uint8_t len, bool sendStop) +{ + address = (address << 1) | 1; + uint8_t addrLen = (addr_10bit?2:1); + uint8_t index = 0; + uint8_t cmdIdx; + uint8_t willRead; + + i2cSetCmd(i2c, 0, I2C_CMD_RSTART, 0, false, false, false);//START + i2cSetCmd(i2c, 1, I2C_CMD_WRITE, addrLen, false, false, true); + i2c->dev->fifo_data.data = address & 0xFF; + if(addr_10bit) { + i2c->dev->fifo_data.data = (address >> 8) & 0xFF; + } + while(len) { + cmdIdx = (index)?0:2; + willRead = (len > 32)?32:(len-1); + i2cSetCmd(i2c, cmdIdx++, I2C_CMD_READ, willRead, false, false, false); + if((len - willRead) > 1) { + i2cSetCmd(i2c, cmdIdx++, I2C_CMD_END, 0, false, false, false); + } else { + willRead++; + i2cSetCmd(i2c, cmdIdx++, I2C_CMD_READ, 1, true, false, false); + if(sendStop) { + i2cSetCmd(i2c, cmdIdx++, I2C_CMD_STOP, 0, false, false, false); + } + } + + i2c->dev->ctr.trans_start = 1; + while(i2c->dev->ctr.trans_start || i2c->dev->status_reg.bus_busy || (!i2c->dev->int_raw.ack_err && !i2c->dev->command[cmdIdx-1].done)); + if(!i2c->dev->command[cmdIdx-1].done) { + log_e("Ack Error"); + return -1; + } + if(i2c->dev->status_reg.arb_lost || i2c->dev->status_reg.time_out) { + log_e("Bus Fail"); + return -1; + } + int i = 0; + while(idev->fifo_data.data; + } + len -= willRead; + } + return 0; +} + +void i2cResetFiFo(i2c_t * i2c) +{ + //TX FIFO + i2c->dev->fifo_conf.tx_fifo_rst = 1; + i2c->dev->fifo_conf.tx_fifo_rst = 0; + //RX FIFO + i2c->dev->fifo_conf.rx_fifo_rst = 1; + i2c->dev->fifo_conf.rx_fifo_rst = 0; +} + +void i2cSetFrequency(i2c_t * i2c, uint32_t clk_speed) +{ + uint32_t period = (APB_CLK_FREQ/clk_speed) / 2; + i2c->dev->scl_low_period.scl_low_period = period; + i2c->dev->scl_high_period.period = period; + + i2c->dev->scl_start_hold.time = 50; + i2c->dev->scl_rstart_setup.time = 50; + + i2c->dev->scl_stop_hold.time = 50; + i2c->dev->scl_stop_setup.time = 50; + + i2c->dev->sda_hold.time = 40; + i2c->dev->sda_sample.time = 40; +} + +uint32_t i2cGetFrequency(i2c_t * i2c) +{ + return APB_CLK_FREQ/(i2c->dev->scl_low_period.scl_low_period+i2c->dev->scl_high_period.period); +} + +/* + * mode - 0 = Slave, 1 = Master + * slave_addr - I2C Address + * addr_10bit_en - enable slave 10bit address mode. + * clk_speed - SCL Frequency + * */ + +i2c_t * i2cInit(uint8_t i2c_num, uint16_t slave_addr, bool addr_10bit_en) +{ + i2c_t* i2c = (i2c_t*) malloc(sizeof(i2c_t)); + if(i2c == 0) { + return NULL; + } + + i2c->num = i2c_num; + i2c->dev = I2C_DEV(i2c_num); + + if(i2c->num == 0) { + SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG,DPORT_I2C_EXT0_CLK_EN); + CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,DPORT_I2C_EXT0_RST); + } else if(i2c->num == 1) { + SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG,DPORT_I2C_EXT1_CLK_EN); + CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,DPORT_I2C_EXT1_RST); + } + + i2c->dev->ctr.rx_lsb_first = 0 ; + i2c->dev->ctr.tx_lsb_first = 0 ; + i2c->dev->ctr.ms_mode = (slave_addr == 0); + i2c->dev->ctr.sda_force_out = 1 ; + i2c->dev->ctr.scl_force_out = 1 ; + i2c->dev->ctr.sample_scl_level = 0 ; + + i2c->dev->timeout.tout = 2000; + i2c->dev->fifo_conf.nonfifo_en = 0; + + if (slave_addr) { + i2c->dev->slave_addr.addr = slave_addr; + i2c->dev->slave_addr.en_10bit = addr_10bit_en; + } + + return i2c; +} + + diff --git a/cores/esp32/esp32-hal-i2c.h b/cores/esp32/esp32-hal-i2c.h new file mode 100644 index 00000000..d543ee95 --- /dev/null +++ b/cores/esp32/esp32-hal-i2c.h @@ -0,0 +1,50 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _ESP32_HAL_I2C_H_ +#define _ESP32_HAL_I2C_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "esp32-hal.h" +#include "soc/i2c_struct.h" + +typedef struct { + i2c_dev_t * dev; + uint8_t num; +} i2c_t; + +i2c_t * i2cInit(uint8_t i2c_num, uint16_t slave_addr, bool addr_10bit_en); + +void i2cSetFrequency(i2c_t * i2c, uint32_t clk_speed); +uint32_t i2cGetFrequency(i2c_t * i2c); + +void i2cResetFiFo(i2c_t * i2c); + +void i2cAttachSCL(i2c_t * i2c, int8_t scl); +void i2cDetachSCL(i2c_t * i2c, int8_t scl); +void i2cAttachSDA(i2c_t * i2c, int8_t sda); +void i2cDetachSDA(i2c_t * i2c, int8_t sda); + +int i2cWrite(i2c_t * i2c, uint16_t address, bool addr_10bit, uint8_t * data, uint8_t len, bool sendStop); +int i2cRead(i2c_t * i2c, uint16_t address, bool addr_10bit, uint8_t * data, uint8_t len, bool sendStop); + + +#ifdef __cplusplus +} +#endif + +#endif /* _ESP32_HAL_I2C_H_ */ diff --git a/cores/esp32/esp32-hal-log.h b/cores/esp32/esp32-hal-log.h new file mode 100644 index 00000000..cedf1625 --- /dev/null +++ b/cores/esp32/esp32-hal-log.h @@ -0,0 +1,105 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef __ARDUHAL_LOG_H__ +#define __ARDUHAL_LOG_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "sdkconfig.h" + +#define ARDUHAL_LOG_LEVEL_NONE (0) +#define ARDUHAL_LOG_LEVEL_ERROR (1) +#define ARDUHAL_LOG_LEVEL_WARN (2) +#define ARDUHAL_LOG_LEVEL_INFO (3) +#define ARDUHAL_LOG_LEVEL_DEBUG (4) +#define ARDUHAL_LOG_LEVEL_VERBOSE (5) + +#ifndef CONFIG_ARDUHAL_LOG_DEFAULT_LEVEL +#define CONFIG_ARDUHAL_LOG_DEFAULT_LEVEL ARDUHAL_LOG_LEVEL_NONE +#endif + +#ifndef CONFIG_ARDUHAL_LOG_COLORS +#define CONFIG_ARDUHAL_LOG_COLORS 0 +#endif + +#if CONFIG_ARDUHAL_LOG_COLORS +#define ARDUHAL_LOG_COLOR_BLACK "30" +#define ARDUHAL_LOG_COLOR_RED "31" //ERROR +#define ARDUHAL_LOG_COLOR_GREEN "32" //INFO +#define ARDUHAL_LOG_COLOR_YELLOW "33" //WARNING +#define ARDUHAL_LOG_COLOR_BLUE "34" +#define ARDUHAL_LOG_COLOR_MAGENTA "35" +#define ARDUHAL_LOG_COLOR_CYAN "36" //DEBUG +#define ARDUHAL_LOG_COLOR_GRAY "37" //VERBOSE +#define ARDUHAL_LOG_COLOR_WHITE "38" + +#define ARDUHAL_LOG_COLOR(COLOR) "\033[0;" COLOR "m" +#define ARDUHAL_LOG_BOLD(COLOR) "\033[1;" COLOR "m" +#define ARDUHAL_LOG_RESET_COLOR "\033[0m" + +#define ARDUHAL_LOG_COLOR_E ARDUHAL_LOG_COLOR(ARDUHAL_LOG_COLOR_RED) +#define ARDUHAL_LOG_COLOR_W ARDUHAL_LOG_COLOR(ARDUHAL_LOG_COLOR_YELLOW) +#define ARDUHAL_LOG_COLOR_I ARDUHAL_LOG_COLOR(ARDUHAL_LOG_COLOR_GREEN) +#define ARDUHAL_LOG_COLOR_D ARDUHAL_LOG_COLOR(ARDUHAL_LOG_COLOR_CYAN) +#define ARDUHAL_LOG_COLOR_V ARDUHAL_LOG_COLOR(ARDUHAL_LOG_COLOR_GRAY) +#else +#define ARDUHAL_LOG_COLOR_E +#define ARDUHAL_LOG_COLOR_W +#define ARDUHAL_LOG_COLOR_I +#define ARDUHAL_LOG_COLOR_D +#define ARDUHAL_LOG_COLOR_V +#define ARDUHAL_LOG_RESET_COLOR +#endif + +#define ARDUHAL_SHORT_LOG_FORMAT(letter, format) ARDUHAL_LOG_COLOR_ ## letter format ARDUHAL_LOG_RESET_COLOR "\r\n" +#define ARDUHAL_LOG_FORMAT(letter, format) ARDUHAL_LOG_COLOR_ ## letter "[" #letter "][%s():%d] " format ARDUHAL_LOG_RESET_COLOR "\r\n", __FUNCTION__, __LINE__ + +#if CONFIG_ARDUHAL_LOG_DEFAULT_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE +#define log_v(format, ...) ets_printf(ARDUHAL_SHORT_LOG_FORMAT(V, format), ##__VA_ARGS__) +#else +#define log_v(format, ...) +#endif + +#if CONFIG_ARDUHAL_LOG_DEFAULT_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG +#define log_d(format, ...) ets_printf(ARDUHAL_SHORT_LOG_FORMAT(D, format), ##__VA_ARGS__) +#else +#define log_d(format, ...) +#endif + +#if CONFIG_ARDUHAL_LOG_DEFAULT_LEVEL >= ARDUHAL_LOG_LEVEL_INFO +#define log_i(format, ...) ets_printf(ARDUHAL_SHORT_LOG_FORMAT(I, format), ##__VA_ARGS__) +#else +#define log_i(format, ...) +#endif + +#if CONFIG_ARDUHAL_LOG_DEFAULT_LEVEL >= ARDUHAL_LOG_LEVEL_WARN +#define log_w(format, ...) ets_printf(ARDUHAL_LOG_FORMAT(W, format), ##__VA_ARGS__) +#else +#define log_w(format, ...) +#endif + +#if CONFIG_ARDUHAL_LOG_DEFAULT_LEVEL >= ARDUHAL_LOG_LEVEL_ERROR +#define log_e(format, ...) ets_printf(ARDUHAL_LOG_FORMAT(E, format), ##__VA_ARGS__) +#else +#define log_e(format, ...) +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __ESP_LOGGING_H__ */ diff --git a/cores/esp32/esp32-hal-matrix.c b/cores/esp32/esp32-hal-matrix.c new file mode 100644 index 00000000..fb1b498c --- /dev/null +++ b/cores/esp32/esp32-hal-matrix.c @@ -0,0 +1,47 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "esp32-hal-matrix.h" +#include "esp_attr.h" +#include "rom/gpio.h" + +#define MATRIX_DETACH_OUT_SIG 0x100 +#define MATRIX_DETACH_IN_LOW_PIN 0x30 +#define MATRIX_DETACH_IN_LOW_HIGH 0x38 + +void IRAM_ATTR pinMatrixOutAttach(uint8_t pin, uint8_t function, bool invertOut, bool invertEnable) +{ + gpio_matrix_out(pin, function, invertOut, invertEnable); +} + +void IRAM_ATTR pinMatrixOutDetach(uint8_t pin, bool invertOut, bool invertEnable) +{ + gpio_matrix_out(pin, MATRIX_DETACH_OUT_SIG, invertOut, invertEnable); +} + +void IRAM_ATTR pinMatrixInAttach(uint8_t pin, uint8_t signal, bool inverted) +{ + gpio_matrix_in(pin, signal, inverted); +} + +void IRAM_ATTR pinMatrixInDetach(uint8_t signal, bool high, bool inverted) +{ + gpio_matrix_in(high?MATRIX_DETACH_IN_LOW_HIGH:MATRIX_DETACH_IN_LOW_PIN, signal, inverted); +} +/* +void IRAM_ATTR intrMatrixAttach(uint32_t source, uint32_t inum){ + intr_matrix_set(PRO_CPU_NUM, source, inum); +} +*/ + diff --git a/cores/esp32/esp32-hal-matrix.h b/cores/esp32/esp32-hal-matrix.h new file mode 100644 index 00000000..3bc90498 --- /dev/null +++ b/cores/esp32/esp32-hal-matrix.h @@ -0,0 +1,35 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _ESP32_HAL_MATRIX_H_ +#define _ESP32_HAL_MATRIX_H_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#include "esp32-hal.h" +#include "soc/gpio_sig_map.h" + +void pinMatrixOutAttach(uint8_t pin, uint8_t function, bool invertOut, bool invertEnable); +void pinMatrixOutDetach(uint8_t pin, bool invertOut, bool invertEnable); +void pinMatrixInAttach(uint8_t pin, uint8_t signal, bool inverted); +void pinMatrixInDetach(uint8_t signal, bool high, bool inverted); + +#ifdef __cplusplus +} +#endif + +#endif /* COMPONENTS_ARDUHAL_INCLUDE_ESP32_HAL_MATRIX_H_ */ diff --git a/cores/esp32/esp32-hal-misc.c b/cores/esp32/esp32-hal-misc.c new file mode 100644 index 00000000..092a36a5 --- /dev/null +++ b/cores/esp32/esp32-hal-misc.c @@ -0,0 +1,50 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "esp32-hal.h" +#include "sdkconfig.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "esp_attr.h" + +uint32_t IRAM_ATTR micros() +{ + uint32_t ccount; + __asm__ __volatile__ ( "rsr %0, ccount" : "=a" (ccount) ); + return ccount / CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ; + //return system_get_time(); +} + +uint32_t IRAM_ATTR millis() +{ + return xTaskGetTickCount() * portTICK_PERIOD_MS; +} + +void delay(uint32_t ms) +{ + vTaskDelay(ms / portTICK_PERIOD_MS); +} + +void delayMicroseconds(uint32_t us) +{ + if(us) { + unsigned long endat = micros(); + endat += us; + while(micros() < endat) { + NOP(); + } + } +} + + diff --git a/cores/esp32/esp32-hal-spi.c b/cores/esp32/esp32-hal-spi.c new file mode 100644 index 00000000..9e0f0c59 --- /dev/null +++ b/cores/esp32/esp32-hal-spi.c @@ -0,0 +1,700 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "esp32-hal-spi.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "rom/ets_sys.h" +#include "esp_attr.h" +#include "esp_intr.h" +#include "rom/gpio.h" +#include "soc/spi_reg.h" +#include "soc/io_mux_reg.h" +#include "soc/gpio_sig_map.h" +#include "soc/dport_reg.h" + +#define SPI_REG_BASE(p) ((p==0)?DR_REG_SPI0_BASE:((p==1)?DR_REG_SPI1_BASE:((p==2)?DR_REG_SPI2_BASE:((p==3)?DR_REG_SPI3_BASE:0)))) +#define SPI_DEV(i) ((spi_dev_t *)(SPI_REG_BASE(i))) + +#define SPI_CLK_IDX(p) ((p==0)?SPICLK_OUT_IDX:((p==1)?SPICLK_OUT_IDX:((p==2)?HSPICLK_OUT_IDX:((p==3)?VSPICLK_OUT_MUX_IDX:0)))) +#define SPI_MISO_IDX(p) ((p==0)?SPIQ_OUT_IDX:((p==1)?SPIQ_OUT_IDX:((p==2)?HSPIQ_OUT_IDX:((p==3)?VSPIQ_OUT_IDX:0)))) +#define SPI_MOSI_IDX(p) ((p==0)?SPID_IN_IDX:((p==1)?SPID_IN_IDX:((p==2)?HSPID_IN_IDX:((p==3)?VSPID_IN_IDX:0)))) + +#define SPI_SPI_SS_IDX(n) ((n==0)?SPICS0_OUT_IDX:((n==1)?SPICS1_OUT_IDX:((n==2)?SPICS2_OUT_IDX:SPICS0_OUT_IDX))) +#define SPI_HSPI_SS_IDX(n) ((n==0)?HSPICS0_OUT_IDX:((n==1)?HSPICS1_OUT_IDX:((n==2)?HSPICS2_OUT_IDX:HSPICS0_OUT_IDX))) +#define SPI_VSPI_SS_IDX(n) ((n==0)?VSPICS0_OUT_IDX:((n==1)?VSPICS1_OUT_IDX:((n==2)?VSPICS2_OUT_IDX:VSPICS0_OUT_IDX))) +#define SPI_SS_IDX(p, n) ((p==0)?SPI_SPI_SS_IDX(n):((p==1)?SPI_SPI_SS_IDX(n):((p==2)?SPI_HSPI_SS_IDX(n):((p==3)?SPI_VSPI_SS_IDX(n):0)))) + +#define SPI_INUM(u) (2) +#define SPI_INTR_SOURCE(u) ((u==0)?ETS_SPI0_INTR_SOURCE:((u==1)?ETS_SPI1_INTR_SOURCE:((u==2)?ETS_SPI2_INTR_SOURCE:((p==3)?ETS_SPI3_INTR_SOURCE:0)))) + +void spiAttachSCK(spi_t * spi, int8_t sck) +{ + if(!spi) { + return; + } + if(sck < 0) { + if(spi->num == HSPI) { + sck = 14; + } else if(spi->num == VSPI) { + sck = 18; + } else { + sck = 6; + } + } + pinMode(sck, OUTPUT); + pinMatrixOutAttach(sck, SPI_CLK_IDX(spi->num), false, false); +} + +void spiAttachMISO(spi_t * spi, int8_t miso) +{ + if(!spi) { + return; + } + if(miso < 0) { + if(spi->num == HSPI) { + miso = 12; + } else if(spi->num == VSPI) { + miso = 19; + } else { + miso = 7; + } + } + pinMode(miso, INPUT); + pinMatrixInAttach(miso, SPI_MISO_IDX(spi->num), false); +} + +void spiAttachMOSI(spi_t * spi, int8_t mosi) +{ + if(!spi) { + return; + } + if(mosi < 0) { + if(spi->num == HSPI) { + mosi = 13; + } else if(spi->num == VSPI) { + mosi = 23; + } else { + mosi = 8; + } + } + pinMode(mosi, OUTPUT); + pinMatrixOutAttach(mosi, SPI_MOSI_IDX(spi->num), false, false); +} + +void spiDetachSCK(spi_t * spi, int8_t sck) +{ + if(!spi) { + return; + } + if(sck < 0) { + if(spi->num == HSPI) { + sck = 14; + } else if(spi->num == VSPI) { + sck = 18; + } else { + sck = 6; + } + } + pinMatrixOutDetach(sck, false, false); + pinMode(sck, INPUT); +} + +void spiDetachMISO(spi_t * spi, int8_t miso) +{ + if(!spi) { + return; + } + if(miso < 0) { + if(spi->num == HSPI) { + miso = 12; + } else if(spi->num == VSPI) { + miso = 19; + } else { + miso = 7; + } + } + pinMatrixInDetach(SPI_MISO_IDX(spi->num), false, false); + pinMode(miso, INPUT); +} + +void spiDetachMOSI(spi_t * spi, int8_t mosi) +{ + if(!spi) { + return; + } + if(mosi < 0) { + if(spi->num == HSPI) { + mosi = 13; + } else if(spi->num == VSPI) { + mosi = 23; + } else { + mosi = 8; + } + } + pinMatrixOutDetach(mosi, false, false); + pinMode(mosi, INPUT); +} + +void spiAttachSS(spi_t * spi, uint8_t cs_num, int8_t ss) +{ + if(!spi) { + return; + } + if(cs_num > 2) { + return; + } + if(ss < 0) { + cs_num = 0; + if(spi->num == HSPI) { + ss = 15; + } else if(spi->num == VSPI) { + ss = 5; + } else { + ss = 11; + } + } + pinMode(ss, OUTPUT); + pinMatrixOutAttach(ss, SPI_SS_IDX(spi->num, cs_num), false, false); + spiEnableSSPins(spi, (1 << cs_num)); +} + +void spiDetachSS(spi_t * spi, int8_t ss) +{ + if(!spi) { + return; + } + if(ss < 0) { + if(spi->num == HSPI) { + ss = 15; + } else if(spi->num == VSPI) { + ss = 5; + } else { + ss = 11; + } + } + pinMatrixOutDetach(ss, false, false); + pinMode(ss, INPUT); +} + +void spiEnableSSPins(spi_t * spi, uint8_t cs_mask) +{ + if(!spi) { + return; + } + spi->dev->pin.val &= ~(cs_mask & SPI_CS_MASK_ALL); +} + +void spiDisableSSPins(spi_t * spi, uint8_t cs_mask) +{ + if(!spi) { + return; + } + spi->dev->pin.val |= (cs_mask & SPI_CS_MASK_ALL); +} + +void spiSSEnable(spi_t * spi) +{ + if(!spi) { + return; + } + spi->dev->user.cs_setup = 1; + spi->dev->user.cs_hold = 1; +} + +void spiSSDisable(spi_t * spi) +{ + if(!spi) { + return; + } + spi->dev->user.cs_setup = 0; + spi->dev->user.cs_hold = 0; +} + +void spiSSSet(spi_t * spi) +{ + if(!spi) { + return; + } + spi->dev->pin.cs_keep_active = 1; +} + +void spiSSClear(spi_t * spi) +{ + if(!spi) { + return; + } + spi->dev->pin.cs_keep_active = 0; +} + +uint32_t spiGetClockDiv(spi_t * spi) +{ + if(!spi) { + return 0; + } + return spi->dev->clock.val; +} + +void spiSetClockDiv(spi_t * spi, uint32_t clockDiv) +{ + if(!spi) { + return; + } + spi->dev->clock.val = clockDiv; +} + +uint8_t spiGetDataMode(spi_t * spi) +{ + if(!spi) { + return 0; + } + bool idleEdge = spi->dev->pin.ck_idle_edge; + bool outEdge = spi->dev->user.ck_out_edge; + if(idleEdge) { + if(outEdge) { + return SPI_MODE3; + } + return SPI_MODE2; + } + if(outEdge) { + return SPI_MODE1; + } + return SPI_MODE0; +} + +void spiSetDataMode(spi_t * spi, uint8_t dataMode) +{ + if(!spi) { + return; + } + switch (dataMode) { + case SPI_MODE1: + spi->dev->pin.ck_idle_edge = 0; + spi->dev->user.ck_out_edge = 1; + break; + case SPI_MODE2: + spi->dev->pin.ck_idle_edge = 1; + spi->dev->user.ck_out_edge = 0; + break; + case SPI_MODE3: + spi->dev->pin.ck_idle_edge = 1; + spi->dev->user.ck_out_edge = 1; + break; + case SPI_MODE0: + default: + spi->dev->pin.ck_idle_edge = 0; + spi->dev->user.ck_out_edge = 0; + break; + } +} + +uint8_t spiGetBitOrder(spi_t * spi) +{ + if(!spi) { + return 0; + } + return (spi->dev->ctrl.wr_bit_order | spi->dev->ctrl.rd_bit_order) == 0; +} + +void spiSetBitOrder(spi_t * spi, uint8_t bitOrder) +{ + if(!spi) { + return; + } + if (SPI_MSBFIRST == bitOrder) { + spi->dev->ctrl.wr_bit_order = 0; + spi->dev->ctrl.rd_bit_order = 0; + } else if (SPI_LSBFIRST == bitOrder) { + spi->dev->ctrl.wr_bit_order = 1; + spi->dev->ctrl.rd_bit_order = 1; + } +} + +void spiStopBus(spi_t * spi) +{ + if(!spi) { + return; + } + spi->dev->slave.trans_done = 0; + spi->dev->slave.slave_mode = 0; + spi->dev->pin.val = 0; + spi->dev->user.val = 0; + spi->dev->user1.val = 0; + spi->dev->ctrl.val = 0; + spi->dev->ctrl1.val = 0; + spi->dev->ctrl2.val = 0; + spi->dev->clock.val = 0; +} + +spi_t * spiStartBus(uint8_t spi_num, uint32_t clockDiv, uint8_t dataMode, uint8_t bitOrder) +{ + + spi_t* spi = (spi_t*) malloc(sizeof(spi_t)); + if(spi == 0) { + return NULL; + } + + spi->num = spi_num; + spi->dev = (spi_dev_t *)SPI_DEV(spi_num); + + if(spi_num == HSPI) { + SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI_CLK_EN_1); + CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_RST_1); + } else if(spi_num == VSPI) { + SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI_CLK_EN_2); + CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_RST_2); + } else { + SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI_CLK_EN); + CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_RST); + } + + spiStopBus(spi); + spiSetDataMode(spi, dataMode); + spiSetBitOrder(spi, bitOrder); + spiSetClockDiv(spi, clockDiv); + + spi->dev->user.usr_mosi = 1; + spi->dev->user.usr_miso = 1; + spi->dev->user.doutdin = 1; + + int i; + for(i=0; i<16; i++) { + spi->dev->data_buf[i] = 0x00000000; + } + + return spi; +} + +void spiWaitReady(spi_t * spi) +{ + if(!spi) { + return; + } + while(spi->dev->cmd.usr); +} + +void spiWrite(spi_t * spi, uint32_t *data, uint8_t len) +{ + if(!spi) { + return; + } + int i; + if(len > 16) { + len = 16; + } + while(spi->dev->cmd.usr); + spi->dev->mosi_dlen.usr_mosi_dbitlen = (len * 32) - 1; + spi->dev->miso_dlen.usr_miso_dbitlen = (len * 32) - 1; + for(i=0; idev->data_buf[i] = data[i]; + } + spi->dev->cmd.usr = 1; +} + +void spiRead(spi_t * spi, uint32_t *data, uint8_t len) +{ + if(!spi) { + return; + } + int i; + if(len > 16) { + len = 16; + } + while(spi->dev->cmd.usr); + for(i=0; idev->data_buf[i]; + } +} + +void spiWriteByte(spi_t * spi, uint8_t data) +{ + if(!spi) { + return; + } + while(spi->dev->cmd.usr); + spi->dev->mosi_dlen.usr_mosi_dbitlen = 7; + spi->dev->miso_dlen.usr_miso_dbitlen = 7; + spi->dev->data_buf[0] = data; + spi->dev->cmd.usr = 1; +} + +uint8_t spiReadByte(spi_t * spi) +{ + if(!spi) { + return 0; + } + while(spi->dev->cmd.usr); + return spi->dev->data_buf[0] & 0xFF; +} + +uint32_t __spiTranslate16(uint16_t data, bool msb) +{ + if(msb) { + return (data >> 8) | (data << 8); + } else { + return data; + } +} + +uint32_t __spiTranslate24(uint32_t data, bool msb) +{ + if(msb) { + union { + uint32_t l; + uint8_t b[4]; + } out; + out.l = data; + return out.b[2] | (out.b[1] << 8) | (out.b[0] << 16); + } else { + return data; + } +} + +uint32_t __spiTranslate32(uint32_t data, bool msb) +{ + if(msb) { + union { + uint32_t l; + uint8_t b[4]; + } out; + out.l = data; + return out.b[3] | (out.b[2] << 8) | (out.b[1] << 16) | (out.b[0] << 24); + } else { + return data; + } +} + +void spiWriteWord(spi_t * spi, uint16_t data) +{ + if(!spi) { + return; + } + while(spi->dev->cmd.usr); + spi->dev->mosi_dlen.usr_mosi_dbitlen = 15; + spi->dev->miso_dlen.usr_miso_dbitlen = 15; + spi->dev->data_buf[0] = __spiTranslate16(data, !spi->dev->ctrl.wr_bit_order); + spi->dev->cmd.usr = 1; +} + +uint16_t spiReadWord(spi_t * spi) +{ + if(!spi) { + return 0; + } + while(spi->dev->cmd.usr); + return __spiTranslate16(spi->dev->data_buf[0] & 0xFFFF, !spi->dev->ctrl.rd_bit_order); +} + +void spiWriteLong(spi_t * spi, uint32_t data) +{ + if(!spi) { + return; + } + while(spi->dev->cmd.usr); + spi->dev->mosi_dlen.usr_mosi_dbitlen = 31; + spi->dev->miso_dlen.usr_miso_dbitlen = 31; + spi->dev->data_buf[0] = __spiTranslate32(data, !spi->dev->ctrl.wr_bit_order); + spi->dev->cmd.usr = 1; +} + +uint32_t spiReadLong(spi_t * spi) +{ + if(!spi) { + return 0; + } + while(spi->dev->cmd.usr); + return __spiTranslate32(spi->dev->data_buf[0], !spi->dev->ctrl.rd_bit_order); +} + +void spiTransferBits(spi_t * spi, uint32_t data, uint32_t * out, uint8_t bits) +{ + if(!spi) { + return; + } + + if(bits > 32) { + bits = 32; + } + uint32_t bytes = (bits + 7) / 8;//64 max + uint32_t mask = (((uint64_t)1 << bits) - 1) & 0xFFFFFFFF; + + while(spi->dev->cmd.usr); + spi->dev->mosi_dlen.usr_mosi_dbitlen = (bits - 1); + spi->dev->miso_dlen.usr_miso_dbitlen = (bits - 1); + if(bytes == 1) { + spi->dev->data_buf[0] = data & mask; + } else if(bytes == 2) { + spi->dev->data_buf[0] = __spiTranslate16(data & mask, !spi->dev->ctrl.wr_bit_order); + } else if(bytes == 3) { + spi->dev->data_buf[0] = __spiTranslate24(data & mask, !spi->dev->ctrl.wr_bit_order); + } else { + spi->dev->data_buf[0] = __spiTranslate32(data & mask, !spi->dev->ctrl.wr_bit_order); + } + spi->dev->cmd.usr = 1; + + if(out) { + while(spi->dev->cmd.usr); + if(bytes == 1) { + *out = spi->dev->data_buf[0] & mask; + } else if(bytes == 2) { + *out = __spiTranslate16(spi->dev->data_buf[0] & mask, !spi->dev->ctrl.wr_bit_order); + } else if(bytes == 3) { + *out = __spiTranslate24(spi->dev->data_buf[0] & mask, !spi->dev->ctrl.wr_bit_order); + } else { + *out = __spiTranslate32(spi->dev->data_buf[0] & mask, !spi->dev->ctrl.wr_bit_order); + } + } +} + +void __spiTransferBytes(spi_t * spi, uint8_t * data, uint8_t * out, uint32_t bytes) +{ + if(!spi) { + return; + } + int i; + + if(bytes > 64) { + bytes = 64; + } + + uint32_t words = (bytes + 3) / 4;//16 max + + uint32_t wordsBuf[16] = {0,}; + uint8_t * bytesBuf = (uint8_t *) wordsBuf; + + if(data) { + for(i=0; idev->cmd.usr); + spi->dev->mosi_dlen.usr_mosi_dbitlen = ((bytes * 8) - 1); + spi->dev->miso_dlen.usr_miso_dbitlen = ((bytes * 8) - 1); + + for(i=0; idev->data_buf[i] = wordsBuf[i]; //copy buffer to spi fifo + } + + spi->dev->cmd.usr = 1; + + if(out) { + while(spi->dev->cmd.usr); + for(i=0; idev->data_buf[i];//copy spi fifo to buffer + } + for(i=0; i 64) { + __spiTransferBytes(spi, data, out, 64); + size -= 64; + if(data) { + data += 64; + } + if(out) { + out += 64; + } + } else { + __spiTransferBytes(spi, data, out, size); + size = 0; + } + } +} + + +typedef union { + uint32_t regValue; + struct { + unsigned regL :6; + unsigned regH :6; + unsigned regN :6; + unsigned regPre :13; + unsigned regEQU :1; + }; +} spiClk_t; + +#define ClkRegToFreq(reg) (CPU_CLK_FREQ / (((reg)->regPre + 1) * ((reg)->regN + 1))) + +uint32_t spiClockDivToFrequency(uint32_t clockDiv) +{ + spiClk_t reg = { clockDiv }; + return ClkRegToFreq(®); +} + +uint32_t spiFrequencyToClockDiv(uint32_t freq) +{ + + if(freq >= CPU_CLK_FREQ) { + return SPI_CLK_EQU_SYSCLK; + } + + const spiClk_t minFreqReg = { 0x7FFFF000 }; + uint32_t minFreq = ClkRegToFreq((spiClk_t*) &minFreqReg); + if(freq < minFreq) { + return minFreqReg.regValue; + } + + uint8_t calN = 1; + spiClk_t bestReg = { 0 }; + int32_t bestFreq = 0; + + while(calN <= 0x3F) { + spiClk_t reg = { 0 }; + int32_t calFreq; + int32_t calPre; + int8_t calPreVari = -2; + + reg.regN = calN; + + while(calPreVari++ <= 1) { + calPre = (((CPU_CLK_FREQ / (reg.regN + 1)) / freq) - 1) + calPreVari; + if(calPre > 0x1FFF) { + reg.regPre = 0x1FFF; + } else if(calPre <= 0) { + reg.regPre = 0; + } else { + reg.regPre = calPre; + } + reg.regL = ((reg.regN + 1) / 2); + calFreq = ClkRegToFreq(®); + if(calFreq == (int32_t) freq) { + memcpy(&bestReg, ®, sizeof(bestReg)); + break; + } else if(calFreq < (int32_t) freq) { + if(abs(freq - calFreq) < abs(freq - bestFreq)) { + bestFreq = calFreq; + memcpy(&bestReg, ®, sizeof(bestReg)); + } + } + } + if(calFreq == (int32_t) freq) { + break; + } + calN++; + } + return bestReg.regValue; +} + + + diff --git a/cores/esp32/esp32-hal-spi.h b/cores/esp32/esp32-hal-spi.h new file mode 100644 index 00000000..1ff5e822 --- /dev/null +++ b/cores/esp32/esp32-hal-spi.h @@ -0,0 +1,118 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef MAIN_ESP32_HAL_SPI_H_ +#define MAIN_ESP32_HAL_SPI_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "esp32-hal.h" +#include "soc/spi_struct.h" + +#define SPI_HAS_TRANSACTION + +#define FSPI 1 //SPI bus attached to the flash (can use the same data lines but different SS) +#define HSPI 2 //SPI bus normally mapped to pins 12 - 15, but can be matrixed to any pins +#define VSPI 3 //SPI bus normally attached to pins 5, 18, 19 and 23, but can be matrixed to any pins + +// This defines are not representing the real Divider of the ESP32 +// the Defines match to an AVR Arduino on 16MHz for better compatibility +#define SPI_CLOCK_DIV2 0x00101001 //8 MHz +#define SPI_CLOCK_DIV4 0x00241001 //4 MHz +#define SPI_CLOCK_DIV8 0x004c1001 //2 MHz +#define SPI_CLOCK_DIV16 0x009c1001 //1 MHz +#define SPI_CLOCK_DIV32 0x013c1001 //500 KHz +#define SPI_CLOCK_DIV64 0x027c1001 //250 KHz +#define SPI_CLOCK_DIV128 0x04fc1001 //125 KHz + +#define SPI_MODE0 0 +#define SPI_MODE1 1 +#define SPI_MODE2 2 +#define SPI_MODE3 3 + +#define SPI_CS0 0 +#define SPI_CS1 1 +#define SPI_CS2 2 +#define SPI_CS_MASK_ALL 0x7 + +#define SPI_LSBFIRST 0 +#define SPI_MSBFIRST 1 + +typedef struct { + spi_dev_t * dev; + uint8_t num; +} spi_t; + +spi_t * spiStartBus(uint8_t spi_num, uint32_t freq, uint8_t dataMode, uint8_t bitOrder); +void spiStopBus(spi_t * spi); + +//Attach/Detach Signal Pins +void spiAttachSCK(spi_t * spi, int8_t sck); +void spiAttachMISO(spi_t * spi, int8_t miso); +void spiAttachMOSI(spi_t * spi, int8_t mosi); +void spiDetachSCK(spi_t * spi, int8_t sck); +void spiDetachMISO(spi_t * spi, int8_t miso); +void spiDetachMOSI(spi_t * spi, int8_t mosi); + +//Attach/Detach SS pin to SPI_CSx signal +void spiAttachSS(spi_t * spi, uint8_t cs_num, int8_t ss); +void spiDetachSS(spi_t * spi, int8_t ss); + +//Enable/Disable SPI_CSx pins +void spiEnableSSPins(spi_t * spi, uint8_t cs_mask); +void spiDisableSSPins(spi_t * spi, uint8_t cs_mask); + +//Enable/Disable hardware control of SPI_CSx pins +void spiSSEnable(spi_t * spi); +void spiSSDisable(spi_t * spi); + +//Activate enabled SPI_CSx pins +void spiSSSet(spi_t * spi); +//Deactivate enabled SPI_CSx pins +void spiSSClear(spi_t * spi); + +void spiWaitReady(spi_t * spi); + +uint32_t spiGetClockDiv(spi_t * spi); +void spiSetClockDiv(spi_t * spi, uint32_t clockDiv); + +uint8_t spiGetDataMode(spi_t * spi); +void spiSetDataMode(spi_t * spi, uint8_t dataMode); + +uint8_t spiGetBitOrder(spi_t * spi); +void spiSetBitOrder(spi_t * spi, uint8_t bitOrder); + +void spiWrite(spi_t * spi, uint32_t *data, uint8_t len); +void spiWriteByte(spi_t * spi, uint8_t data); +void spiWriteWord(spi_t * spi, uint16_t data); +void spiWriteLong(spi_t * spi, uint32_t data); + +void spiRead(spi_t * spi, uint32_t *out, uint8_t len); +uint8_t spiReadByte(spi_t * spi); +uint16_t spiReadWord(spi_t * spi); +uint32_t spiReadLong(spi_t * spi); + +void spiTransferBits(spi_t * spi, uint32_t data, uint32_t * out, uint8_t bits); +void spiTransferBytes(spi_t * spi, uint8_t * data, uint8_t * out, uint32_t size); + +uint32_t spiFrequencyToClockDiv(uint32_t freq); +uint32_t spiClockDivToFrequency(uint32_t freq); + +#ifdef __cplusplus +} +#endif + +#endif /* MAIN_ESP32_HAL_SPI_H_ */ diff --git a/cores/esp32/esp32-hal-uart.c b/cores/esp32/esp32-hal-uart.c new file mode 100644 index 00000000..6739dd2a --- /dev/null +++ b/cores/esp32/esp32-hal-uart.c @@ -0,0 +1,270 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "esp32-hal-uart.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "freertos/semphr.h" +#include "rom/ets_sys.h" +#include "esp_attr.h" +#include "esp_intr.h" +#include "rom/uart.h" +#include "soc/uart_reg.h" +#include "soc/io_mux_reg.h" +#include "soc/gpio_sig_map.h" + +#define ETS_UART2_INUM 5 + +#define UART_REG_BASE(u) ((u==0)?DR_REG_UART_BASE:( (u==1)?DR_REG_UART1_BASE:( (u==2)?DR_REG_UART2_BASE:0))) +#define UART_RXD_IDX(u) ((u==0)?U0RXD_IN_IDX:( (u==1)?U1RXD_IN_IDX:( (u==2)?U2RXD_IN_IDX:0))) +#define UART_TXD_IDX(u) ((u==0)?U0TXD_OUT_IDX:( (u==1)?U1TXD_OUT_IDX:( (u==2)?U2TXD_OUT_IDX:0))) +#define UART_INUM(u) ((u==0)?ETS_UART0_INUM:( (u==1)?ETS_UART1_INUM:( (u==2)?ETS_UART2_INUM:0))) +#define UART_INTR_SOURCE(u) ((u==0)?ETS_UART0_INTR_SOURCE:( (u==1)?ETS_UART1_INTR_SOURCE:((u==2)?ETS_UART2_INTR_SOURCE:0))) + +static int s_uart_debug_nr = 0; + +static void IRAM_ATTR _uart_isr(void *arg) +{ + uint8_t c; + BaseType_t xHigherPriorityTaskWoken; + uart_t* uart = (uart_t*)arg; + + uart->dev->int_clr.val = UART_RXFIFO_FULL_INT_ENA | UART_FRM_ERR_INT_ENA | UART_RXFIFO_TOUT_INT_ENA; //Acknowledge the interrupt + while(uart->dev->status.rxfifo_cnt) { + c = uart->dev->fifo.rw_byte; + if(!xQueueIsQueueFullFromISR(uart->queue)) { + xQueueSendFromISR(uart->queue, &c, &xHigherPriorityTaskWoken); + } + } + + if (xHigherPriorityTaskWoken) { + portYIELD_FROM_ISR(); + } +} + +uart_t* uartBegin(uint8_t uart_nr, uint32_t baudrate, uint32_t config, int8_t rxPin, int8_t txPin, uint16_t queueLen, bool inverted) +{ + uint32_t conf1 = 0; + + if(uart_nr > 2) { + return NULL; + } + + if(rxPin == -1 && txPin == -1) { + return NULL; + } + + uart_t* uart = (uart_t*) malloc(sizeof(uart_t)); + if(uart == 0) { + return NULL; + } + + uart->dev = (uart_dev_t *)UART_REG_BASE(uart_nr); + uart->num = uart_nr; + uart->inverted = inverted; + + uart->rxPin = rxPin; + uart->txPin = txPin; + uart->rxEnabled = (uart->rxPin != -1); + uart->txEnabled = (uart->txPin != -1); + + uartFlush(uart); + + if(uart->rxEnabled) { + uart->queue = xQueueCreate(queueLen, sizeof(uint8_t)); //initialize the queue + if(uart->queue == NULL) { + free(uart); + return NULL; + } + + pinMode(uart->rxPin, INPUT); + pinMatrixInAttach(uart->rxPin, UART_RXD_IDX(uart->num), uart->inverted); + intr_matrix_set(PRO_CPU_NUM, UART_INTR_SOURCE(uart->num), UART_INUM(uart->num)); + xt_set_interrupt_handler(UART_INUM(uart->num), _uart_isr, uart); + ESP_INTR_ENABLE(UART_INUM(uart->num)); + conf1 = (112 << UART_RXFIFO_FULL_THRHD_S) | (0x02 << UART_RX_TOUT_THRHD_S) | UART_RX_TOUT_EN; + uart->dev->int_ena.val = UART_RXFIFO_FULL_INT_ENA | UART_FRM_ERR_INT_ENA | UART_RXFIFO_TOUT_INT_ENA; + uart->dev->int_clr.val = 0xffff; + } + if(uart->txEnabled) { + pinMode(uart->txPin, OUTPUT); + pinMatrixOutAttach(uart->txPin, UART_TXD_IDX(uart->num), uart->inverted, false); + } + + uartSetBaudRate(uart, baudrate); + uart->dev->conf0.val = config; + uart->dev->conf1.val = conf1; + return uart; +} + +void uartEnd(uart_t* uart) +{ + if(uart == 0) { + return; + } + + if(uart->rxEnabled) { + pinMode(uart->rxPin, INPUT); + if(uart->num || uart->rxPin != 3) { + pinMatrixInDetach(UART_RXD_IDX(uart->num), uart->inverted, false); + } + + ESP_INTR_DISABLE(UART_INUM(uart->num)); + xt_set_interrupt_handler(UART_INUM(uart->num), NULL, NULL); + vQueueDelete(uart->queue); + } + if(uart->txEnabled) { + pinMode(uart->txPin, INPUT); + if(uart->num || uart->txPin != 1) { + pinMatrixInDetach(UART_TXD_IDX(uart->num), !uart->inverted, uart->inverted); + } + } + + uart->dev->conf0.val = 0; + uart->dev->conf1.val = 0; + uart->dev->int_ena.val = 0; + uart->dev->int_clr.val = 0xffff; + + free(uart); +} + +uint32_t uartAvailable(uart_t* uart) +{ + return uxQueueMessagesWaiting(uart->queue); +} + +uint8_t uartRead(uart_t* uart) +{ + uint8_t c; + if(xQueueReceive(uart->queue, &c, 0)) { + return c; + } + return 0; +} + +uint8_t uartPeek(uart_t* uart) +{ + uint8_t c; + if(xQueuePeek(uart->queue, &c, 0)) { + return c; + } + return 0; +} + +void uartWrite(uart_t* uart, uint8_t c) +{ + while(uart->dev->status.rxfifo_cnt == 0x7F); + uart->dev->fifo.rw_byte = c; +} + +void uartWriteBuf(uart_t* uart, const uint8_t * data, size_t len) +{ + while(len && uart->dev->status.rxfifo_cnt < 0x7F) { + uart->dev->fifo.rw_byte = *data++; + len--; + } +} + +void uartFlush(uart_t* uart) +{ + uint32_t tmp = 0x00000000; + + if(uart == 0) { + return; + } + + if(uart->rxEnabled) { + tmp |= UART_RXFIFO_RST; + } + + if(uart->txEnabled) { + tmp |= UART_TXFIFO_RST; + while(uart->dev->status.txfifo_cnt); + } + + uart->dev->conf0.val |= (tmp); + uart->dev->conf0.val &= ~(tmp); +} + +void uartSetBaudRate(uart_t* uart, uint32_t baud_rate) +{ + if(uart == 0) { + return; + } + uart->baud_rate = baud_rate; + uint32_t clk_div = ((UART_CLK_FREQ<<4)/baud_rate); + uart->dev->clk_div.div_int = clk_div>>4 ; + uart->dev->clk_div.div_frag = clk_div & 0xf; +} + +uint32_t uartGetBaudRate(uart_t* uart) +{ + if(uart == 0) { + return 0; + } + return uart->baud_rate; +} + +static void IRAM_ATTR uart0_write_char(char c) +{ + while(((ESP_REG(0x01C+DR_REG_UART_BASE) >> UART_TXFIFO_CNT_S) & 0x7F) == 0x7F); + ESP_REG(DR_REG_UART_BASE) = c; +} + +static void IRAM_ATTR uart1_write_char(char c) +{ + while(((ESP_REG(0x01C+DR_REG_UART1_BASE) >> UART_TXFIFO_CNT_S) & 0x7F) == 0x7F); + ESP_REG(DR_REG_UART1_BASE) = c; +} + +static void IRAM_ATTR uart2_write_char(char c) +{ + while(((ESP_REG(0x01C+DR_REG_UART2_BASE) >> UART_TXFIFO_CNT_S) & 0x7F) == 0x7F); + ESP_REG(DR_REG_UART2_BASE) = c; +} + +void uartSetDebug(uart_t* uart) +{ + if(uart == NULL || uart->num > 2) { + s_uart_debug_nr = -1; + ets_install_putc1(NULL); + return; + } + if(s_uart_debug_nr == uart->num) { + return; + } + s_uart_debug_nr = uart->num; + switch(s_uart_debug_nr) { + case 0: + ets_install_putc1((void (*)(char)) &uart0_write_char); + break; + case 1: + ets_install_putc1((void (*)(char)) &uart1_write_char); + break; + case 2: + ets_install_putc1((void (*)(char)) &uart2_write_char); + break; + default: + ets_install_putc1(NULL); + break; + } +} + +int uartGetDebug() +{ + return s_uart_debug_nr; +} + + + diff --git a/cores/esp32/esp32-hal-uart.h b/cores/esp32/esp32-hal-uart.h new file mode 100644 index 00000000..d3669f83 --- /dev/null +++ b/cores/esp32/esp32-hal-uart.h @@ -0,0 +1,84 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef MAIN_ESP32_HAL_UART_H_ +#define MAIN_ESP32_HAL_UART_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "esp32-hal.h" +#include "soc/uart_struct.h" +#include "freertos/FreeRTOS.h" +#include "freertos/queue.h" + +#define SERIAL_5N1 0x8000010 +#define SERIAL_6N1 0x8000014 +#define SERIAL_7N1 0x8000018 +#define SERIAL_8N1 0x800001c +#define SERIAL_5N2 0x8000030 +#define SERIAL_6N2 0x8000034 +#define SERIAL_7N2 0x8000038 +#define SERIAL_8N2 0x800003c +#define SERIAL_5E1 0x8000012 +#define SERIAL_6E1 0x8000016 +#define SERIAL_7E1 0x800001a +#define SERIAL_8E1 0x800001e +#define SERIAL_5E2 0x8000032 +#define SERIAL_6E2 0x8000036 +#define SERIAL_7E2 0x800003a +#define SERIAL_8E2 0x800003e +#define SERIAL_5O1 0x8000013 +#define SERIAL_6O1 0x8000017 +#define SERIAL_7O1 0x800001b +#define SERIAL_8O1 0x800001f +#define SERIAL_5O2 0x8000033 +#define SERIAL_6O2 0x8000037 +#define SERIAL_7O2 0x800003b +#define SERIAL_8O2 0x800003f + +typedef struct { + uart_dev_t * dev; + xQueueHandle queue; + uint32_t baud_rate; + uint8_t num; + int8_t rxPin; + int8_t txPin; + bool rxEnabled; + bool txEnabled; + bool inverted; +} uart_t; + +uart_t* uartBegin(uint8_t uart_nr, uint32_t baudrate, uint32_t config, int8_t rxPin, int8_t txPin, uint16_t queueLen, bool inverted); +void uartEnd(uart_t* uart); + +uint32_t uartAvailable(uart_t* uart); +uint8_t uartRead(uart_t* uart); +uint8_t uartPeek(uart_t* uart); +void uartWrite(uart_t* uart, uint8_t c); +void uartWriteBuf(uart_t* uart, const uint8_t * data, size_t len); +void uartFlush(uart_t* uart); + +void uartSetBaudRate(uart_t* uart, uint32_t baud_rate); +uint32_t uartGetBaudRate(uart_t* uart); + +void uartSetDebug(uart_t* uart); +int uartGetDebug(); + +#ifdef __cplusplus +} +#endif + +#endif /* MAIN_ESP32_HAL_UART_H_ */ diff --git a/cores/esp32/esp32-hal.h b/cores/esp32/esp32-hal.h new file mode 100644 index 00000000..826fa62b --- /dev/null +++ b/cores/esp32/esp32-hal.h @@ -0,0 +1,54 @@ +/* + Arduino.h - Main include file for the Arduino SDK + Copyright (c) 2005-2013 Arduino Team. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef HAL_ESP32_HAL_H_ +#define HAL_ESP32_HAL_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include +#include + +#define ESP_REG(addr) *((volatile uint32_t *)(addr)) +#define NOP() asm volatile ("nop") + +#include "esp32-hal-log.h" +#include "esp32-hal-matrix.h" +#include "esp32-hal-uart.h" +#include "esp32-hal-gpio.h" +#include "esp32-hal-spi.h" +#include "esp32-hal-i2c.h" +#include "esp_system.h" + +uint32_t micros(); +uint32_t millis(); +void delay(uint32_t); +void delayMicroseconds(uint32_t us); + +#ifdef __cplusplus +} +#endif + +#endif /* HAL_ESP32_HAL_H_ */ diff --git a/cores/esp32/libb64/AUTHORS b/cores/esp32/libb64/AUTHORS new file mode 100755 index 00000000..af687375 --- /dev/null +++ b/cores/esp32/libb64/AUTHORS @@ -0,0 +1,7 @@ +libb64: Base64 Encoding/Decoding Routines +====================================== + +Authors: +------- + +Chris Venter chris.venter@gmail.com http://rocketpod.blogspot.com diff --git a/cores/esp32/libb64/LICENSE b/cores/esp32/libb64/LICENSE new file mode 100755 index 00000000..a6b56069 --- /dev/null +++ b/cores/esp32/libb64/LICENSE @@ -0,0 +1,29 @@ +Copyright-Only Dedication (based on United States law) +or Public Domain Certification + +The person or persons who have associated work with this document (the +"Dedicator" or "Certifier") hereby either (a) certifies that, to the best of +his knowledge, the work of authorship identified is in the public domain of the +country from which the work is published, or (b) hereby dedicates whatever +copyright the dedicators holds in the work of authorship identified below (the +"Work") to the public domain. A certifier, moreover, dedicates any copyright +interest he may have in the associated work, and for these purposes, is +described as a "dedicator" below. + +A certifier has taken reasonable steps to verify the copyright status of this +work. Certifier recognizes that his good faith efforts may not shield him from +liability if in fact the work certified is not in the public domain. + +Dedicator makes this dedication for the benefit of the public at large and to +the detriment of the Dedicator's heirs and successors. Dedicator intends this +dedication to be an overt act of relinquishment in perpetuity of all present +and future rights under copyright law, whether vested or contingent, in the +Work. Dedicator understands that such relinquishment of all rights includes +the relinquishment of all rights to enforce (by lawsuit or otherwise) those +copyrights in the Work. + +Dedicator recognizes that, once placed in the public domain, the Work may be +freely reproduced, distributed, transmitted, used, modified, built upon, or +otherwise exploited by anyone for any purpose, commercial or non-commercial, +and in any way, including by methods that have not yet been invented or +conceived. \ No newline at end of file diff --git a/cores/esp32/libb64/cdecode.c b/cores/esp32/libb64/cdecode.c new file mode 100755 index 00000000..2963d5f7 --- /dev/null +++ b/cores/esp32/libb64/cdecode.c @@ -0,0 +1,94 @@ +/* +cdecoder.c - c source to a base64 decoding algorithm implementation + +This is part of the libb64 project, and has been placed in the public domain. +For details, see http://sourceforge.net/projects/libb64 +*/ + +#include "cdecode.h" + +int base64_decode_value(char value_in) +{ + static const char decoding[] = {62,-1,-1,-1,63,52,53,54,55,56,57,58,59,60,61,-1,-1,-1,-2,-1,-1,-1,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,-1,-1,-1,-1,-1,-1,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51}; + static const char decoding_size = sizeof(decoding); + value_in -= 43; + if (value_in < 0 || value_in > decoding_size) { + return -1; + } + return decoding[(int)value_in]; +} + +void base64_init_decodestate(base64_decodestate* state_in) +{ + state_in->step = step_a; + state_in->plainchar = 0; +} + +int base64_decode_block(const char* code_in, const int length_in, char* plaintext_out, base64_decodestate* state_in) +{ + const char* codechar = code_in; + char* plainchar = plaintext_out; + char fragment; + + *plainchar = state_in->plainchar; + + switch (state_in->step) { + while (1) { + case step_a: + do { + if (codechar == code_in+length_in) { + state_in->step = step_a; + state_in->plainchar = *plainchar; + return plainchar - plaintext_out; + } + fragment = (char)base64_decode_value(*codechar++); + } while (fragment < 0); + *plainchar = (fragment & 0x03f) << 2; + case step_b: + do { + if (codechar == code_in+length_in) { + state_in->step = step_b; + state_in->plainchar = *plainchar; + return plainchar - plaintext_out; + } + fragment = (char)base64_decode_value(*codechar++); + } while (fragment < 0); + *plainchar++ |= (fragment & 0x030) >> 4; + *plainchar = (fragment & 0x00f) << 4; + case step_c: + do { + if (codechar == code_in+length_in) { + state_in->step = step_c; + state_in->plainchar = *plainchar; + return plainchar - plaintext_out; + } + fragment = (char)base64_decode_value(*codechar++); + } while (fragment < 0); + *plainchar++ |= (fragment & 0x03c) >> 2; + *plainchar = (fragment & 0x003) << 6; + case step_d: + do { + if (codechar == code_in+length_in) { + state_in->step = step_d; + state_in->plainchar = *plainchar; + return plainchar - plaintext_out; + } + fragment = (char)base64_decode_value(*codechar++); + } while (fragment < 0); + *plainchar++ |= (fragment & 0x03f); + } + } + /* control should not reach here */ + return plainchar - plaintext_out; +} + +int base64_decode_chars(const char* code_in, const int length_in, char* plaintext_out) +{ + base64_decodestate _state; + base64_init_decodestate(&_state); + int len = base64_decode_block(code_in, length_in, plaintext_out, &_state); + if(len > 0) { + plaintext_out[len] = 0; + } + return len; +} diff --git a/cores/esp32/libb64/cdecode.h b/cores/esp32/libb64/cdecode.h new file mode 100755 index 00000000..44f114f6 --- /dev/null +++ b/cores/esp32/libb64/cdecode.h @@ -0,0 +1,38 @@ +/* +cdecode.h - c header for a base64 decoding algorithm + +This is part of the libb64 project, and has been placed in the public domain. +For details, see http://sourceforge.net/projects/libb64 +*/ + +#ifndef BASE64_CDECODE_H +#define BASE64_CDECODE_H + +#define base64_decode_expected_len(n) ((n * 3) / 4) + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + step_a, step_b, step_c, step_d +} base64_decodestep; + +typedef struct { + base64_decodestep step; + char plainchar; +} base64_decodestate; + +void base64_init_decodestate(base64_decodestate* state_in); + +int base64_decode_value(char value_in); + +int base64_decode_block(const char* code_in, const int length_in, char* plaintext_out, base64_decodestate* state_in); + +int base64_decode_chars(const char* code_in, const int length_in, char* plaintext_out); + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif /* BASE64_CDECODE_H */ diff --git a/cores/esp32/libb64/cencode.c b/cores/esp32/libb64/cencode.c new file mode 100755 index 00000000..ee9a18f0 --- /dev/null +++ b/cores/esp32/libb64/cencode.c @@ -0,0 +1,111 @@ +/* +cencoder.c - c source to a base64 encoding algorithm implementation + +This is part of the libb64 project, and has been placed in the public domain. +For details, see http://sourceforge.net/projects/libb64 +*/ + +#include "cencode.h" + +const int CHARS_PER_LINE = 72; + +void base64_init_encodestate(base64_encodestate* state_in) +{ + state_in->step = step_A; + state_in->result = 0; + state_in->stepcount = 0; +} + +char base64_encode_value(char value_in) +{ + static const char* encoding = "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789+/"; + if (value_in > 63) { + return '='; + } + return encoding[(int)value_in]; +} + +int base64_encode_block(const char* plaintext_in, int length_in, char* code_out, base64_encodestate* state_in) +{ + const char* plainchar = plaintext_in; + const char* const plaintextend = plaintext_in + length_in; + char* codechar = code_out; + char result; + char fragment; + + result = state_in->result; + + switch (state_in->step) { + while (1) { + case step_A: + if (plainchar == plaintextend) { + state_in->result = result; + state_in->step = step_A; + return codechar - code_out; + } + fragment = *plainchar++; + result = (fragment & 0x0fc) >> 2; + *codechar++ = base64_encode_value(result); + result = (fragment & 0x003) << 4; + case step_B: + if (plainchar == plaintextend) { + state_in->result = result; + state_in->step = step_B; + return codechar - code_out; + } + fragment = *plainchar++; + result |= (fragment & 0x0f0) >> 4; + *codechar++ = base64_encode_value(result); + result = (fragment & 0x00f) << 2; + case step_C: + if (plainchar == plaintextend) { + state_in->result = result; + state_in->step = step_C; + return codechar - code_out; + } + fragment = *plainchar++; + result |= (fragment & 0x0c0) >> 6; + *codechar++ = base64_encode_value(result); + result = (fragment & 0x03f) >> 0; + *codechar++ = base64_encode_value(result); + + ++(state_in->stepcount); + if (state_in->stepcount == CHARS_PER_LINE/4) { + *codechar++ = '\n'; + state_in->stepcount = 0; + } + } + } + /* control should not reach here */ + return codechar - code_out; +} + +int base64_encode_blockend(char* code_out, base64_encodestate* state_in) +{ + char* codechar = code_out; + + switch (state_in->step) { + case step_B: + *codechar++ = base64_encode_value(state_in->result); + *codechar++ = '='; + *codechar++ = '='; + break; + case step_C: + *codechar++ = base64_encode_value(state_in->result); + *codechar++ = '='; + break; + case step_A: + break; + } + *codechar = 0x00; + + return codechar - code_out; +} + +int base64_encode_chars(const char* plaintext_in, int length_in, char* code_out) +{ + base64_encodestate _state; + base64_init_encodestate(&_state); + int len = base64_encode_block(plaintext_in, length_in, code_out, &_state); + return len + base64_encode_blockend((code_out + len), &_state); +} diff --git a/cores/esp32/libb64/cencode.h b/cores/esp32/libb64/cencode.h new file mode 100755 index 00000000..51bb3f3d --- /dev/null +++ b/cores/esp32/libb64/cencode.h @@ -0,0 +1,41 @@ +/* +cencode.h - c header for a base64 encoding algorithm + +This is part of the libb64 project, and has been placed in the public domain. +For details, see http://sourceforge.net/projects/libb64 +*/ + +#ifndef BASE64_CENCODE_H +#define BASE64_CENCODE_H + +#define base64_encode_expected_len(n) ((((4 * n) / 3) + 3) & ~3) + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + step_A, step_B, step_C +} base64_encodestep; + +typedef struct { + base64_encodestep step; + char result; + int stepcount; +} base64_encodestate; + +void base64_init_encodestate(base64_encodestate* state_in); + +char base64_encode_value(char value_in); + +int base64_encode_block(const char* plaintext_in, int length_in, char* code_out, base64_encodestate* state_in); + +int base64_encode_blockend(char* code_out, base64_encodestate* state_in); + +int base64_encode_chars(const char* plaintext_in, int length_in, char* code_out); + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif /* BASE64_CENCODE_H */ diff --git a/cores/esp32/main.cpp b/cores/esp32/main.cpp new file mode 100644 index 00000000..48a3ef76 --- /dev/null +++ b/cores/esp32/main.cpp @@ -0,0 +1,35 @@ +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" + +void initVariant() __attribute__((weak)); +void initVariant() {} + +void init() __attribute__((weak)); +void init() {} + +void bootWiFi() __attribute__((weak)); +void bootWiFi() {} + +extern void loop(); +extern void setup(); + +void loopTask(void *pvParameters) +{ + bool setup_done = false; + for(;;) { + if(!setup_done) { + bootWiFi(); + setup(); + setup_done = true; + } + loop(); + } +} + +extern "C" void app_main() +{ + init(); + initVariant(); + xTaskCreatePinnedToCore(loopTask, "loopTask", 4096, NULL, 1, NULL, 0); +} + diff --git a/cores/esp32/pgmspace.h b/cores/esp32/pgmspace.h new file mode 100644 index 00000000..ce155391 --- /dev/null +++ b/cores/esp32/pgmspace.h @@ -0,0 +1,42 @@ +/* + Copyright (c) 2015 Hristo Gochkov. All rights reserved. + This file is part of the RaspberryPi core for Arduino environment. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ +#ifndef PGMSPACE_INCLUDE +#define PGMSPACE_INCLUDE + +typedef char __FlashStringHelper; +#define PROGMEM +#define PSTR(s) (s) +#define F(string_literal) (reinterpret_cast(PSTR(string_literal))) + +#define pgm_read_byte(addr) (*(const unsigned char *)(addr)) +#define pgm_read_word(addr) (*(const unsigned short *)(addr)) +#define pgm_read_dword(addr) (*(const unsigned long *)(addr)) +#define pgm_read_float(addr) (*(const float *)(addr)) + +#define pgm_read_byte_near(addr) pgm_read_byte(addr) +#define pgm_read_word_near(addr) pgm_read_word(addr) +#define pgm_read_dword_near(addr) pgm_read_dword(addr) +#define pgm_read_float_near(addr) pgm_read_float(addr) +#define pgm_read_byte_far(addr) pgm_read_byte(addr) +#define pgm_read_word_far(addr) pgm_read_word(addr) +#define pgm_read_dword_far(addr) pgm_read_dword(addr) +#define pgm_read_float_far(addr) pgm_read_float(addr) + +#define memcpy_P(to,from,len) memcpy(to,from,len) +#endif diff --git a/cores/esp32/stdlib_noniso.h b/cores/esp32/stdlib_noniso.h new file mode 100644 index 00000000..3df2cc2a --- /dev/null +++ b/cores/esp32/stdlib_noniso.h @@ -0,0 +1,49 @@ +/* + stdlib_noniso.h - nonstandard (but usefull) conversion functions + + Copyright (c) 2014 Ivan Grokhotkov. All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef STDLIB_NONISO_H +#define STDLIB_NONISO_H + +#ifdef __cplusplus +extern "C" { +#endif + +int atoi(const char *s); + +long atol(const char* s); + +double atof(const char* s); + +char* itoa (int val, char *s, int radix); + +char* ltoa (long val, char *s, int radix); + +char* utoa (unsigned int val, char *s, int radix); + +char* ultoa (unsigned long val, char *s, int radix); + +char* dtostrf (double val, signed char width, unsigned char prec, char *s); + +#ifdef __cplusplus +} // extern "C" +#endif + + +#endif diff --git a/cores/esp32/wiring_private.h b/cores/esp32/wiring_private.h new file mode 100644 index 00000000..f58089ed --- /dev/null +++ b/cores/esp32/wiring_private.h @@ -0,0 +1,45 @@ +/* + wiring_private.h - Internal header file. + Part of Arduino - http://www.arduino.cc/ + + Copyright (c) 2005-2006 David A. Mellis + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General + Public License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place, Suite 330, + Boston, MA 02111-1307 USA + + $Id: wiring.h 239 2007-01-12 17:58:39Z mellis $ + */ + +#ifndef WiringPrivate_h +#define WiringPrivate_h + +#include +#include + +#include "arducore.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef void (*voidFuncPtr)(void); + +void initPins(); + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif diff --git a/libraries/SPI/keywords.txt b/libraries/SPI/keywords.txt new file mode 100644 index 00000000..fa761658 --- /dev/null +++ b/libraries/SPI/keywords.txt @@ -0,0 +1,36 @@ +####################################### +# Syntax Coloring Map SPI +####################################### + +####################################### +# Datatypes (KEYWORD1) +####################################### + +SPI KEYWORD1 + +####################################### +# Methods and Functions (KEYWORD2) +####################################### +begin KEYWORD2 +end KEYWORD2 +transfer KEYWORD2 +setBitOrder KEYWORD2 +setDataMode KEYWORD2 +setClockDivider KEYWORD2 + + +####################################### +# Constants (LITERAL1) +####################################### +SPI_CLOCK_DIV4 LITERAL1 +SPI_CLOCK_DIV16 LITERAL1 +SPI_CLOCK_DIV64 LITERAL1 +SPI_CLOCK_DIV128 LITERAL1 +SPI_CLOCK_DIV2 LITERAL1 +SPI_CLOCK_DIV8 LITERAL1 +SPI_CLOCK_DIV32 LITERAL1 +SPI_CLOCK_DIV64 LITERAL1 +SPI_MODE0 LITERAL1 +SPI_MODE1 LITERAL1 +SPI_MODE2 LITERAL1 +SPI_MODE3 LITERAL1 \ No newline at end of file diff --git a/libraries/SPI/library.properties b/libraries/SPI/library.properties new file mode 100644 index 00000000..9e8f805d --- /dev/null +++ b/libraries/SPI/library.properties @@ -0,0 +1,9 @@ +name=SPI +version=1.0 +author=Hristo Gochkov +maintainer=Hristo Gochkov +sentence=Enables the communication with devices that use the Serial Peripheral Interface (SPI) Bus. For all Arduino boards, BUT Arduino DUE. +paragraph= +category=Signal Input/Output +url=http://arduino.cc/en/Reference/SPI +architectures=esp32 diff --git a/libraries/SPI/src/SPI.cpp b/libraries/SPI/src/SPI.cpp new file mode 100644 index 00000000..4dee46fb --- /dev/null +++ b/libraries/SPI/src/SPI.cpp @@ -0,0 +1,232 @@ +/* + SPI.cpp - SPI library for esp8266 + + Copyright (c) 2015 Hristo Gochkov. All rights reserved. + This file is part of the esp8266 core for Arduino environment. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "SPI.h" + +SPIClass::SPIClass(uint8_t spi_bus) + :_spi_num(spi_bus) + ,_spi(NULL) + ,_use_hw_ss(false) + ,_sck(-1) + ,_miso(-1) + ,_mosi(-1) + ,_ss(-1) + ,_div(0) + ,_freq(1000000) +{} + +void SPIClass::begin(int8_t sck, int8_t miso, int8_t mosi, int8_t ss) +{ + if(_spi) { + return; + } + + if(!_div) { + _div = spiFrequencyToClockDiv(_freq); + } + + _spi = spiStartBus(_spi_num, _div, SPI_MODE0, SPI_MSBFIRST); + if(!_spi) { + return; + } + + _sck = sck; + _miso = miso; + _mosi = mosi; + _ss = ss; + + spiAttachSCK(_spi, _sck); + spiAttachMISO(_spi, _miso); + spiAttachMOSI(_spi, _mosi); + +} + +void SPIClass::end() +{ + if(!_spi) { + return; + } + spiDetachSCK(_spi, _sck); + spiDetachMISO(_spi, _miso); + spiDetachMOSI(_spi, _mosi); + setHwCs(false); + spiStopBus(_spi); + _spi = NULL; +} + +void SPIClass::setHwCs(bool use) +{ + if(use && !_use_hw_ss) { + spiAttachSS(_spi, 0, _ss); + spiSSEnable(_spi); + } else if(_use_hw_ss) { + spiSSDisable(_spi); + spiDetachSS(_spi, _ss); + } + _use_hw_ss = use; +} + +void SPIClass::beginTransaction(SPISettings settings) +{ + spiWaitReady(_spi); + setFrequency(settings._clock); + setBitOrder(settings._bitOrder); + setDataMode(settings._dataMode); +} + +void SPIClass::endTransaction() {} + +void SPIClass::setFrequency(uint32_t freq) +{ + //check if last freq changed + uint32_t cdiv = spiGetClockDiv(_spi); + if(_freq != freq || _div != cdiv) { + _freq = freq; + _div = spiFrequencyToClockDiv(_freq); + spiSetClockDiv(_spi, _div); + } +} + +void SPIClass::setClockDivider(uint32_t clockDiv) +{ + _div = clockDiv; + spiSetClockDiv(_spi, _div); +} + +void SPIClass::setDataMode(uint8_t dataMode) +{ + spiSetDataMode(_spi, dataMode); +} + +void SPIClass::setBitOrder(uint8_t bitOrder) +{ + spiSetBitOrder(_spi, bitOrder); +} + +void SPIClass::write(uint8_t data) +{ + spiWriteByte(_spi, data); +} + +uint8_t SPIClass::transfer(uint8_t data) +{ + spiWriteByte(_spi, data); + return spiReadByte(_spi); +} + +void SPIClass::write16(uint16_t data) +{ + spiWriteWord(_spi, data); +} + +uint16_t SPIClass::transfer16(uint16_t data) +{ + spiWriteWord(_spi, data); + return spiReadWord(_spi); +} + +void SPIClass::write32(uint32_t data) +{ + spiWriteLong(_spi, data); +} + +uint32_t SPIClass::transfer32(uint32_t data) +{ + spiWriteLong(_spi, data); + return spiReadLong(_spi); +} + +void SPIClass::transferBits(uint32_t data, uint32_t * out, uint8_t bits) +{ + spiTransferBits(_spi, data, out, bits); +} + +/** + * Note: + * data need to be aligned to 32Bit + * or you get an Fatal exception (9) + * @param data uint8_t * + * @param size uint32_t + */ +void SPIClass::writeBytes(uint8_t * data, uint32_t size) +{ + spiTransferBytes(_spi, data, 0, size); +} + +/** + * @param data uint8_t * data buffer. can be NULL for Read Only operation + * @param out uint8_t * output buffer. can be NULL for Write Only operation + * @param size uint32_t + */ +void SPIClass::transferBytes(uint8_t * data, uint8_t * out, uint32_t size) +{ + spiTransferBytes(_spi, data, out, size); +} + +/** + * Note: + * data need to be aligned to 32Bit + * or you get an Fatal exception (9) + * @param data uint8_t * + * @param size uint8_t max for size is 64Byte + * @param repeat uint32_t + */ +void SPIClass::writePattern(uint8_t * data, uint8_t size, uint32_t repeat) +{ + if(size > 64) { + return; //max Hardware FIFO + } + + uint32_t byte = (size * repeat); + uint8_t r = (64 / size); + + while(byte) { + if(byte > 64) { + writePattern_(data, size, r); + byte -= 64; + } else { + writePattern_(data, size, (byte / size)); + byte = 0; + } + } +} + +void SPIClass::writePattern_(uint8_t * data, uint8_t size, uint8_t repeat) +{ + uint8_t bytes = (size * repeat); + uint8_t buffer[64]; + uint8_t * bufferPtr = &buffer[0]; + uint8_t * dataPtr; + uint8_t dataSize = bytes; + for(uint8_t i = 0; i < repeat; i++) { + dataSize = size; + dataPtr = data; + while(dataSize--) { + *bufferPtr = *dataPtr; + dataPtr++; + bufferPtr++; + } + } + + writeBytes(&buffer[0], bytes); +} + +SPIClass SPI(VSPI); diff --git a/libraries/SPI/src/SPI.h b/libraries/SPI/src/SPI.h new file mode 100644 index 00000000..fbb56935 --- /dev/null +++ b/libraries/SPI/src/SPI.h @@ -0,0 +1,81 @@ +/* + SPI.h - SPI library for esp8266 + + Copyright (c) 2015 Hristo Gochkov. All rights reserved. + This file is part of the esp8266 core for Arduino environment. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ +#ifndef _SPI_H_INCLUDED +#define _SPI_H_INCLUDED + +#include +#include "esp32-hal-spi.h" + +class SPISettings +{ +public: + SPISettings() :_clock(1000000), _bitOrder(SPI_MSBFIRST), _dataMode(SPI_MODE0) {} + SPISettings(uint32_t clock, uint8_t bitOrder, uint8_t dataMode) :_clock(clock), _bitOrder(bitOrder), _dataMode(dataMode) {} + uint32_t _clock; + uint8_t _bitOrder; + uint8_t _dataMode; +}; + +class SPIClass +{ +public: + SPIClass(uint8_t spi_bus=HSPI); + void begin(int8_t sck=-1, int8_t miso=-1, int8_t mosi=-1, int8_t ss=-1); + void end(); + + void setHwCs(bool use); + void setBitOrder(uint8_t bitOrder); + void setDataMode(uint8_t dataMode); + void setFrequency(uint32_t freq); + void setClockDivider(uint32_t clockDiv); + + void beginTransaction(SPISettings settings); + void endTransaction(void); + + uint8_t transfer(uint8_t data); + uint16_t transfer16(uint16_t data); + uint32_t transfer32(uint32_t data); + void transferBytes(uint8_t * data, uint8_t * out, uint32_t size); + void transferBits(uint32_t data, uint32_t * out, uint8_t bits); + + void write(uint8_t data); + void write16(uint16_t data); + void write16(uint16_t data, bool msb); + void write32(uint32_t data); + void write32(uint32_t data, bool msb); + void writeBytes(uint8_t * data, uint32_t size); + void writePattern(uint8_t * data, uint8_t size, uint32_t repeat); +private: + int8_t _spi_num; + spi_t * _spi; + bool _use_hw_ss; + int8_t _sck; + int8_t _miso; + int8_t _mosi; + int8_t _ss; + uint32_t _div; + uint32_t _freq; + void writePattern_(uint8_t * data, uint8_t size, uint8_t repeat); +}; + +extern SPIClass SPI; + +#endif diff --git a/libraries/WiFi/examples/HTTPSRequest/HTTPSRequest.ino b/libraries/WiFi/examples/HTTPSRequest/HTTPSRequest.ino new file mode 100644 index 00000000..56294d08 --- /dev/null +++ b/libraries/WiFi/examples/HTTPSRequest/HTTPSRequest.ino @@ -0,0 +1,90 @@ +/* + * HTTP over TLS (HTTPS) example sketch + * + * This example demonstrates how to use + * WiFiClientSecure class to access HTTPS API. + * We fetch and display the status of + * esp8266/Arduino project continuous integration + * build. + * + * Created by Ivan Grokhotkov, 2015. + * This example is in public domain. + */ + +#include +#include + +const char* ssid = "........"; +const char* password = "........"; + +const char* host = "api.github.com"; +const int httpsPort = 443; + +// Use web browser to view and copy +// SHA1 fingerprint of the certificate +const char* fingerprint = "CF 05 98 89 CA FF 8E D8 5E 5C E0 C2 E4 F7 E6 C3 C7 50 DD 5C"; + +void setup() +{ + Serial.begin(115200); + Serial.println(); + Serial.print("connecting to "); + Serial.println(ssid); + WiFi.begin(ssid, password); + while (WiFi.status() != WL_CONNECTED) { + delay(500); + Serial.print("."); + } + Serial.println(""); + Serial.println("WiFi connected"); + Serial.println("IP address: "); + Serial.println(WiFi.localIP()); + + // Use WiFiClientSecure class to create TLS connection + WiFiClientSecure client; + Serial.print("connecting to "); + Serial.println(host); + if (!client.connect(host, httpsPort)) { + Serial.println("connection failed"); + return; + } + + if (client.verify(fingerprint, host)) { + Serial.println("certificate matches"); + } else { + Serial.println("certificate doesn't match"); + } + + String url = "/repos/esp8266/Arduino/commits/master/status"; + Serial.print("requesting URL: "); + Serial.println(url); + + client.print(String("GET ") + url + " HTTP/1.1\r\n" + + "Host: " + host + "\r\n" + + "User-Agent: BuildFailureDetectorESP8266\r\n" + + "Connection: close\r\n\r\n"); + + Serial.println("request sent"); + while (client.connected()) { + String line = client.readStringUntil('\n'); + if (line == "\r") { + Serial.println("headers received"); + break; + } + } + String line = client.readStringUntil('\n'); + if (line.startsWith("{\"state\":\"success\"")) { + Serial.println("esp8266/Arduino CI successfull!"); + } else { + Serial.println("esp8266/Arduino CI has failed"); + } + Serial.println("reply was:"); + Serial.println("=========="); + Serial.println(line); + Serial.println("=========="); + Serial.println("closing connection"); +} + +void loop() +{ +} diff --git a/libraries/WiFi/examples/NTPClient/NTPClient.ino b/libraries/WiFi/examples/NTPClient/NTPClient.ino new file mode 100644 index 00000000..004d4566 --- /dev/null +++ b/libraries/WiFi/examples/NTPClient/NTPClient.ino @@ -0,0 +1,152 @@ +/* + + Udp NTP Client + + Get the time from a Network Time Protocol (NTP) time server + Demonstrates use of UDP sendPacket and ReceivePacket + For more on NTP time servers and the messages needed to communicate with them, + see http://en.wikipedia.org/wiki/Network_Time_Protocol + + created 4 Sep 2010 + by Michael Margolis + modified 9 Apr 2012 + by Tom Igoe + updated for the ESP8266 12 Apr 2015 + by Ivan Grokhotkov + + This code is in the public domain. + + */ + +#include +#include + +char ssid[] = "*************"; // your network SSID (name) +char pass[] = "********"; // your network password + + +unsigned int localPort = 2390; // local port to listen for UDP packets + +/* Don't hardwire the IP address or we won't get the benefits of the pool. + * Lookup the IP address for the host name instead */ +//IPAddress timeServer(129, 6, 15, 28); // time.nist.gov NTP server +IPAddress timeServerIP; // time.nist.gov NTP server address +const char* ntpServerName = "time.nist.gov"; + +const int NTP_PACKET_SIZE = 48; // NTP time stamp is in the first 48 bytes of the message + +byte packetBuffer[ NTP_PACKET_SIZE]; //buffer to hold incoming and outgoing packets + +// A UDP instance to let us send and receive packets over UDP +WiFiUDP udp; + +void setup() +{ + Serial.begin(115200); + Serial.println(); + Serial.println(); + + // We start by connecting to a WiFi network + Serial.print("Connecting to "); + Serial.println(ssid); + WiFi.begin(ssid, pass); + + while (WiFi.status() != WL_CONNECTED) { + delay(500); + Serial.print("."); + } + Serial.println(""); + + Serial.println("WiFi connected"); + Serial.println("IP address: "); + Serial.println(WiFi.localIP()); + + Serial.println("Starting UDP"); + udp.begin(localPort); + Serial.print("Local port: "); + Serial.println(udp.localPort()); +} + +void loop() +{ + //get a random server from the pool + WiFi.hostByName(ntpServerName, timeServerIP); + + sendNTPpacket(timeServerIP); // send an NTP packet to a time server + // wait to see if a reply is available + delay(1000); + + int cb = udp.parsePacket(); + if (!cb) { + Serial.println("no packet yet"); + } else { + Serial.print("packet received, length="); + Serial.println(cb); + // We've received a packet, read the data from it + udp.read(packetBuffer, NTP_PACKET_SIZE); // read the packet into the buffer + + //the timestamp starts at byte 40 of the received packet and is four bytes, + // or two words, long. First, esxtract the two words: + + unsigned long highWord = word(packetBuffer[40], packetBuffer[41]); + unsigned long lowWord = word(packetBuffer[42], packetBuffer[43]); + // combine the four bytes (two words) into a long integer + // this is NTP time (seconds since Jan 1 1900): + unsigned long secsSince1900 = highWord << 16 | lowWord; + Serial.print("Seconds since Jan 1 1900 = " ); + Serial.println(secsSince1900); + + // now convert NTP time into everyday time: + Serial.print("Unix time = "); + // Unix time starts on Jan 1 1970. In seconds, that's 2208988800: + const unsigned long seventyYears = 2208988800UL; + // subtract seventy years: + unsigned long epoch = secsSince1900 - seventyYears; + // print Unix time: + Serial.println(epoch); + + + // print the hour, minute and second: + Serial.print("The UTC time is "); // UTC is the time at Greenwich Meridian (GMT) + Serial.print((epoch % 86400L) / 3600); // print the hour (86400 equals secs per day) + Serial.print(':'); + if ( ((epoch % 3600) / 60) < 10 ) { + // In the first 10 minutes of each hour, we'll want a leading '0' + Serial.print('0'); + } + Serial.print((epoch % 3600) / 60); // print the minute (3600 equals secs per minute) + Serial.print(':'); + if ( (epoch % 60) < 10 ) { + // In the first 10 seconds of each minute, we'll want a leading '0' + Serial.print('0'); + } + Serial.println(epoch % 60); // print the second + } + // wait ten seconds before asking for the time again + delay(10000); +} + +// send an NTP request to the time server at the given address +unsigned long sendNTPpacket(IPAddress& address) +{ + Serial.println("sending NTP packet..."); + // set all bytes in the buffer to 0 + memset(packetBuffer, 0, NTP_PACKET_SIZE); + // Initialize values needed to form NTP request + // (see URL above for details on the packets) + packetBuffer[0] = 0b11100011; // LI, Version, Mode + packetBuffer[1] = 0; // Stratum, or type of clock + packetBuffer[2] = 6; // Polling Interval + packetBuffer[3] = 0xEC; // Peer Clock Precision + // 8 bytes of zero for Root Delay & Root Dispersion + packetBuffer[12] = 49; + packetBuffer[13] = 0x4E; + packetBuffer[14] = 49; + packetBuffer[15] = 52; + + // all NTP fields have been given values, now + // you can send a packet requesting a timestamp: + udp.beginPacket(address, 123); //NTP requests are to port 123 + udp.write(packetBuffer, NTP_PACKET_SIZE); + udp.endPacket(); +} diff --git a/libraries/WiFi/examples/WiFiAccessPoint/WiFiAccessPoint.ino b/libraries/WiFi/examples/WiFiAccessPoint/WiFiAccessPoint.ino new file mode 100644 index 00000000..9fa6c91f --- /dev/null +++ b/libraries/WiFi/examples/WiFiAccessPoint/WiFiAccessPoint.ino @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2015, Majenko Technologies + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * * Neither the name of Majenko Technologies nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* Create a WiFi access point and provide a web server on it. */ + +#include +#include +#include + +/* Set these to your desired credentials. */ +const char *ssid = "ESPap"; +const char *password = "thereisnospoon"; + +ESP8266WebServer server(80); + +/* Just a little test message. Go to http://192.168.4.1 in a web browser + * connected to this access point to see it. + */ +void handleRoot() +{ + server.send(200, "text/html", "

You are connected

"); +} + +void setup() +{ + delay(1000); + Serial.begin(115200); + Serial.println(); + Serial.print("Configuring access point..."); + /* You can remove the password parameter if you want the AP to be open. */ + WiFi.softAP(ssid, password); + + IPAddress myIP = WiFi.softAPIP(); + Serial.print("AP IP address: "); + Serial.println(myIP); + server.on("/", handleRoot); + server.begin(); + Serial.println("HTTP server started"); +} + +void loop() +{ + server.handleClient(); +} diff --git a/libraries/WiFi/examples/WiFiClient/WiFiClient.ino b/libraries/WiFi/examples/WiFiClient/WiFiClient.ino new file mode 100644 index 00000000..7dd9c8d0 --- /dev/null +++ b/libraries/WiFi/examples/WiFiClient/WiFiClient.ino @@ -0,0 +1,94 @@ +/* + * This sketch sends data via HTTP GET requests to data.sparkfun.com service. + * + * You need to get streamId and privateKey at data.sparkfun.com and paste them + * below. Or just customize this script to talk to other HTTP servers. + * + */ + +#include + +const char* ssid = "your-ssid"; +const char* password = "your-password"; + +const char* host = "data.sparkfun.com"; +const char* streamId = "...................."; +const char* privateKey = "...................."; + +void setup() +{ + Serial.begin(115200); + delay(10); + + // We start by connecting to a WiFi network + + Serial.println(); + Serial.println(); + Serial.print("Connecting to "); + Serial.println(ssid); + + WiFi.begin(ssid, password); + + while (WiFi.status() != WL_CONNECTED) { + delay(500); + Serial.print("."); + } + + Serial.println(""); + Serial.println("WiFi connected"); + Serial.println("IP address: "); + Serial.println(WiFi.localIP()); +} + +int value = 0; + +void loop() +{ + delay(5000); + ++value; + + Serial.print("connecting to "); + Serial.println(host); + + // Use WiFiClient class to create TCP connections + WiFiClient client; + const int httpPort = 80; + if (!client.connect(host, httpPort)) { + Serial.println("connection failed"); + return; + } + + // We now create a URI for the request + String url = "/input/"; + url += streamId; + url += "?private_key="; + url += privateKey; + url += "&value="; + url += value; + + Serial.print("Requesting URL: "); + Serial.println(url); + + // This will send the request to the server + client.print(String("GET ") + url + " HTTP/1.1\r\n" + + "Host: " + host + "\r\n" + + "Connection: close\r\n\r\n"); + unsigned long timeout = millis(); + while (client.available() == 0) { + if (millis() - timeout > 5000) { + Serial.println(">>> Client Timeout !"); + client.stop(); + return; + } + } + + // Read all the lines of the reply from server and print them to Serial + while(client.available()) { + String line = client.readStringUntil('\r'); + Serial.print(line); + } + + Serial.println(); + Serial.println("closing connection"); +} + diff --git a/libraries/WiFi/examples/WiFiClientBasic/WiFiClientBasic.ino b/libraries/WiFi/examples/WiFiClientBasic/WiFiClientBasic.ino new file mode 100644 index 00000000..27901521 --- /dev/null +++ b/libraries/WiFi/examples/WiFiClientBasic/WiFiClientBasic.ino @@ -0,0 +1,70 @@ +/* + * This sketch sends a message to a TCP server + * + */ + +#include +#include + +WiFiMulti WiFiMulti; + +void setup() +{ + Serial.begin(115200); + delay(10); + + // We start by connecting to a WiFi network + WiFiMulti.addAP("SSID", "passpasspass"); + + Serial.println(); + Serial.println(); + Serial.print("Wait for WiFi... "); + + while(WiFiMulti.run() != WL_CONNECTED) { + Serial.print("."); + delay(500); + } + + Serial.println(""); + Serial.println("WiFi connected"); + Serial.println("IP address: "); + Serial.println(WiFi.localIP()); + + delay(500); +} + + +void loop() +{ + const uint16_t port = 80; + const char * host = "192.168.1.1"; // ip or dns + + + + Serial.print("connecting to "); + Serial.println(host); + + // Use WiFiClient class to create TCP connections + WiFiClient client; + + if (!client.connect(host, port)) { + Serial.println("connection failed"); + Serial.println("wait 5 sec..."); + delay(5000); + return; + } + + // This will send the request to the server + client.print("Send this data to server"); + + //read back one line from server + String line = client.readStringUntil('\r'); + client.println(line); + + Serial.println("closing connection"); + client.stop(); + + Serial.println("wait 5 sec..."); + delay(5000); +} + diff --git a/libraries/WiFi/examples/WiFiClientEvents/WiFiClientEvents.ino b/libraries/WiFi/examples/WiFiClientEvents/WiFiClientEvents.ino new file mode 100644 index 00000000..b6842cd4 --- /dev/null +++ b/libraries/WiFi/examples/WiFiClientEvents/WiFiClientEvents.ino @@ -0,0 +1,51 @@ +/* + * This sketch shows the WiFi event usage + * + */ + +#include + +const char* ssid = "your-ssid"; +const char* password = "your-password"; + + +void WiFiEvent(WiFiEvent_t event) +{ + Serial.printf("[WiFi-event] event: %d\n", event); + + switch(event) { + case WIFI_EVENT_STAMODE_GOT_IP: + Serial.println("WiFi connected"); + Serial.println("IP address: "); + Serial.println(WiFi.localIP()); + break; + case WIFI_EVENT_STAMODE_DISCONNECTED: + Serial.println("WiFi lost connection"); + break; + } +} + +void setup() +{ + Serial.begin(115200); + + // delete old config + WiFi.disconnect(true); + + delay(1000); + + WiFi.onEvent(WiFiEvent); + + WiFi.begin(ssid, password); + + Serial.println(); + Serial.println(); + Serial.println("Wait for WiFi... "); +} + + +void loop() +{ + delay(1000); +} + diff --git a/libraries/WiFi/examples/WiFiMulti/WiFiMulti.ino b/libraries/WiFi/examples/WiFiMulti/WiFiMulti.ino new file mode 100644 index 00000000..2e490d06 --- /dev/null +++ b/libraries/WiFi/examples/WiFiMulti/WiFiMulti.ino @@ -0,0 +1,35 @@ +/* + * This sketch trys to Connect to the best AP based on a given list + * + */ + +#include +#include + +WiFiMulti wifiMulti; + +void setup() +{ + Serial.begin(115200); + delay(10); + + wifiMulti.addAP("ssid_from_AP_1", "your_password_for_AP_1"); + wifiMulti.addAP("ssid_from_AP_2", "your_password_for_AP_2"); + wifiMulti.addAP("ssid_from_AP_3", "your_password_for_AP_3"); + + Serial.println("Connecting Wifi..."); + if(wifiMulti.run() == WL_CONNECTED) { + Serial.println(""); + Serial.println("WiFi connected"); + Serial.println("IP address: "); + Serial.println(WiFi.localIP()); + } +} + +void loop() +{ + if(wifiMulti.run() != WL_CONNECTED) { + Serial.println("WiFi not connected!"); + delay(1000); + } +} \ No newline at end of file diff --git a/libraries/WiFi/examples/WiFiScan/WiFiScan.ino b/libraries/WiFi/examples/WiFiScan/WiFiScan.ino new file mode 100644 index 00000000..975a1fe6 --- /dev/null +++ b/libraries/WiFi/examples/WiFiScan/WiFiScan.ino @@ -0,0 +1,48 @@ +/* + * This sketch demonstrates how to scan WiFi networks. + * The API is almost the same as with the WiFi Shield library, + * the most obvious difference being the different file you need to include: + */ +#include "WiFi.h" + +void setup() +{ + Serial.begin(115200); + + // Set WiFi to station mode and disconnect from an AP if it was previously connected + WiFi.mode(WIFI_STA); + WiFi.disconnect(); + delay(100); + + Serial.println("Setup done"); +} + +void loop() +{ + Serial.println("scan start"); + + // WiFi.scanNetworks will return the number of networks found + int n = WiFi.scanNetworks(); + Serial.println("scan done"); + if (n == 0) { + Serial.println("no networks found"); + } else { + Serial.print(n); + Serial.println(" networks found"); + for (int i = 0; i < n; ++i) { + // Print SSID and RSSI for each network found + Serial.print(i + 1); + Serial.print(": "); + Serial.print(WiFi.SSID(i)); + Serial.print(" ("); + Serial.print(WiFi.RSSI(i)); + Serial.print(")"); + Serial.println((WiFi.encryptionType(i) == ENC_TYPE_NONE)?" ":"*"); + delay(10); + } + } + Serial.println(""); + + // Wait a bit before scanning again + delay(5000); +} diff --git a/libraries/WiFi/examples/WiFiTelnetToSerial/WiFiTelnetToSerial.ino b/libraries/WiFi/examples/WiFiTelnetToSerial/WiFiTelnetToSerial.ino new file mode 100644 index 00000000..4099928e --- /dev/null +++ b/libraries/WiFi/examples/WiFiTelnetToSerial/WiFiTelnetToSerial.ino @@ -0,0 +1,103 @@ +/* + WiFiTelnetToSerial - Example Transparent UART to Telnet Server for esp8266 + + Copyright (c) 2015 Hristo Gochkov. All rights reserved. + This file is part of the WiFi library for Arduino environment. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ +#include + +//how many clients should be able to telnet to this ESP8266 +#define MAX_SRV_CLIENTS 1 +const char* ssid = "**********"; +const char* password = "**********"; + +WiFiServer server(23); +WiFiClient serverClients[MAX_SRV_CLIENTS]; + +void setup() +{ + Serial1.begin(115200); + WiFi.begin(ssid, password); + Serial1.print("\nConnecting to "); + Serial1.println(ssid); + uint8_t i = 0; + while (WiFi.status() != WL_CONNECTED && i++ < 20) { + delay(500); + } + if(i == 21) { + Serial1.print("Could not connect to"); + Serial1.println(ssid); + while(1) { + delay(500); + } + } + //start UART and the server + Serial.begin(115200); + server.begin(); + server.setNoDelay(true); + + Serial1.print("Ready! Use 'telnet "); + Serial1.print(WiFi.localIP()); + Serial1.println(" 23' to connect"); +} + +void loop() +{ + uint8_t i; + //check if there are any new clients + if (server.hasClient()) { + for(i = 0; i < MAX_SRV_CLIENTS; i++) { + //find free/disconnected spot + if (!serverClients[i] || !serverClients[i].connected()) { + if(serverClients[i]) { + serverClients[i].stop(); + } + serverClients[i] = server.available(); + Serial1.print("New client: "); + Serial1.print(i); + continue; + } + } + //no free/disconnected spot so reject + WiFiClient serverClient = server.available(); + serverClient.stop(); + } + //check clients for data + for(i = 0; i < MAX_SRV_CLIENTS; i++) { + if (serverClients[i] && serverClients[i].connected()) { + if(serverClients[i].available()) { + //get data from the telnet client and push it to the UART + while(serverClients[i].available()) { + Serial.write(serverClients[i].read()); + } + } + } + } + //check UART for data + if(Serial.available()) { + size_t len = Serial.available(); + uint8_t sbuf[len]; + Serial.readBytes(sbuf, len); + //push UART data to all connected telnet clients + for(i = 0; i < MAX_SRV_CLIENTS; i++) { + if (serverClients[i] && serverClients[i].connected()) { + serverClients[i].write(sbuf, len); + delay(1); + } + } + } +} diff --git a/libraries/WiFi/examples/WiFiWebServer/WiFiWebServer.ino b/libraries/WiFi/examples/WiFiWebServer/WiFiWebServer.ino new file mode 100644 index 00000000..91e85b3d --- /dev/null +++ b/libraries/WiFi/examples/WiFiWebServer/WiFiWebServer.ino @@ -0,0 +1,100 @@ +/* + * This sketch demonstrates how to set up a simple HTTP-like server. + * The server will set a GPIO pin depending on the request + * http://server_ip/gpio/0 will set the GPIO2 low, + * http://server_ip/gpio/1 will set the GPIO2 high + * server_ip is the IP address of the ESP8266 module, will be + * printed to Serial when the module is connected. + */ + +#include + +const char* ssid = "your-ssid"; +const char* password = "your-password"; + +// Create an instance of the server +// specify the port to listen on as an argument +WiFiServer server(80); + +void setup() +{ + Serial.begin(115200); + delay(10); + + // prepare GPIO2 + pinMode(2, OUTPUT); + digitalWrite(2, 0); + + // Connect to WiFi network + Serial.println(); + Serial.println(); + Serial.print("Connecting to "); + Serial.println(ssid); + + WiFi.begin(ssid, password); + + while (WiFi.status() != WL_CONNECTED) { + delay(500); + Serial.print("."); + } + Serial.println(""); + Serial.println("WiFi connected"); + + // Start the server + server.begin(); + Serial.println("Server started"); + + // Print the IP address + Serial.println(WiFi.localIP()); +} + +void loop() +{ + // Check if a client has connected + WiFiClient client = server.available(); + if (!client) { + return; + } + + // Wait until the client sends some data + Serial.println("new client"); + while(!client.available()) { + delay(1); + } + + // Read the first line of the request + String req = client.readStringUntil('\r'); + Serial.println(req); + client.flush(); + + // Match the request + int val; + if (req.indexOf("/gpio/0") != -1) { + val = 0; + } else if (req.indexOf("/gpio/1") != -1) { + val = 1; + } else { + Serial.println("invalid request"); + client.stop(); + return; + } + + // Set GPIO2 according to the request + digitalWrite(2, val); + + client.flush(); + + // Prepare the response + String s = "HTTP/1.1 200 OK\r\nContent-Type: text/html\r\n\r\n\r\n\r\nGPIO is now "; + s += (val)?"high":"low"; + s += "\n"; + + // Send the response to the client + client.print(s); + delay(1); + Serial.println("Client disonnected"); + + // The client will actually be disconnected + // when the function returns and 'client' object is detroyed +} + diff --git a/libraries/WiFi/keywords.txt b/libraries/WiFi/keywords.txt new file mode 100644 index 00000000..5720aaac --- /dev/null +++ b/libraries/WiFi/keywords.txt @@ -0,0 +1,68 @@ +####################################### +# Syntax Coloring Map For WiFi +####################################### + +####################################### +# Library (KEYWORD3) +####################################### + +WiFi KEYWORD3 + +####################################### +# Datatypes (KEYWORD1) +####################################### + +WiFi KEYWORD1 +WiFiClient KEYWORD1 +WiFiServer KEYWORD1 +WiFiUDP KEYWORD1 +WiFiClientSecure KEYWORD1 + +####################################### +# Methods and Functions (KEYWORD2) +####################################### + +status KEYWORD2 +mode KEYWORD2 +connect KEYWORD2 +write KEYWORD2 +available KEYWORD2 +config KEYWORD2 +setDNS KEYWORD2 +read KEYWORD2 +flush KEYWORD2 +stop KEYWORD2 +connected KEYWORD2 +begin KEYWORD2 +beginMulticast KEYWORD2 +disconnect KEYWORD2 +macAddress KEYWORD2 +localIP KEYWORD2 +subnetMask KEYWORD2 +gatewayIP KEYWORD2 +SSID KEYWORD2 +psk KEYWORD2 +BSSID KEYWORD2 +RSSI KEYWORD2 +encryptionType KEYWORD2 +beginPacket KEYWORD2 +beginPacketMulticast KEYWORD2 +endPacket KEYWORD2 +parsePacket KEYWORD2 +destinationIP KEYWORD2 +remoteIP KEYWORD2 +remotePort KEYWORD2 +softAP KEYWORD2 +softAPIP KEYWORD2 +softAPmacAddress KEYWORD2 +softAPConfig KEYWORD2 +printDiag KEYWORD2 +hostByName KEYWORD2 +scanNetworks KEYWORD2 + +####################################### +# Constants (LITERAL1) +####################################### +WIFI_AP LITERAL1 +WIFI_STA LITERAL1 +WIFI_AP_STA LITERAL1 diff --git a/libraries/WiFi/library.properties b/libraries/WiFi/library.properties new file mode 100644 index 00000000..c98691df --- /dev/null +++ b/libraries/WiFi/library.properties @@ -0,0 +1,9 @@ +name=WiFi +version=1.0 +author=Hristo Gochkov +maintainer=Hristo Gochkov +sentence=Enables network connection (local and Internet) using the ESP32 built-in WiFi. +paragraph=With this library you can instantiate Servers, Clients and send/receive UDP packets through WiFi. The shield can connect either to open or encrypted networks (WEP, WPA). The IP address can be assigned statically or through a DHCP. The library can also manage DNS. +category=Communication +url= +architectures=esp32 diff --git a/libraries/WiFi/src/WiFi.cpp b/libraries/WiFi/src/WiFi.cpp new file mode 100644 index 00000000..87dc2a2f --- /dev/null +++ b/libraries/WiFi/src/WiFi.cpp @@ -0,0 +1,96 @@ +/* + ESP8266WiFi.cpp - WiFi library for esp8266 + + Copyright (c) 2014 Ivan Grokhotkov. All rights reserved. + This file is part of the esp8266 core for Arduino environment. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Reworked on 28 Dec 2015 by Markus Sattler + + */ +#include "WiFi.h" + +extern "C" { +#include +#include +#include +#include +#include +#include +#include +#include +#include +} + + +// ----------------------------------------------------------------------------------------------------------------------- +// ---------------------------------------------------------- Debug ------------------------------------------------------ +// ----------------------------------------------------------------------------------------------------------------------- + + +/** + * Output WiFi settings to an object derived from Print interface (like Serial). + * @param p Print interface + */ +void WiFiClass::printDiag(Print& p) +{ + const char* modes[] = { "NULL", "STA", "AP", "STA+AP" }; + + wifi_mode_t mode; + esp_wifi_get_mode(&mode); + + uint8_t primaryChan; + wifi_second_chan_t secondChan; + esp_wifi_get_channel(&primaryChan, &secondChan); + + bool autoConnect; + esp_wifi_get_auto_connect(&autoConnect); + + p.print("Mode: "); + p.println(modes[mode]); + + p.print("Channel: "); + p.println(primaryChan); + /* + p.print("AP id: "); + p.println(wifi_station_get_current_ap_id()); + + p.print("Status: "); + p.println(wifi_station_get_connect_status()); + */ + p.print("Auto connect: "); + p.println(autoConnect); + + wifi_config_t conf; + esp_wifi_get_config(WIFI_IF_STA, &conf); + + const char* ssid = reinterpret_cast(conf.sta.ssid); + p.print("SSID ("); + p.print(strlen(ssid)); + p.print("): "); + p.println(ssid); + + const char* passphrase = reinterpret_cast(conf.sta.password); + p.print("Passphrase ("); + p.print(strlen(passphrase)); + p.print("): "); + p.println(passphrase); + + p.print("BSSID set: "); + p.println(conf.sta.bssid_set); +} + +WiFiClass WiFi; diff --git a/libraries/WiFi/src/WiFi.h b/libraries/WiFi/src/WiFi.h new file mode 100644 index 00000000..d56d2b7e --- /dev/null +++ b/libraries/WiFi/src/WiFi.h @@ -0,0 +1,62 @@ +/* + ESP8266WiFi.h - esp8266 Wifi support. + Based on WiFi.h from Arduino WiFi shield library. + Copyright (c) 2011-2014 Arduino. All right reserved. + Modified by Ivan Grokhotkov, December 2014 + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef WiFi_h +#define WiFi_h + +#include + +#include "Print.h" +#include "IPAddress.h" + +#include "WiFiType.h" +#include "WiFiSTA.h" +#include "WiFiAP.h" +#include "WiFiScan.h" +#include "WiFiGeneric.h" + +#include "WiFiClient.h" + +class WiFiClass : public WiFiGenericClass, public WiFiSTAClass, public WiFiScanClass, public WiFiAPClass +{ +public: + using WiFiGenericClass::channel; + + using WiFiSTAClass::SSID; + using WiFiSTAClass::RSSI; + using WiFiSTAClass::BSSID; + using WiFiSTAClass::BSSIDstr; + + using WiFiScanClass::SSID; + using WiFiScanClass::encryptionType; + using WiFiScanClass::RSSI; + using WiFiScanClass::BSSID; + using WiFiScanClass::BSSIDstr; + using WiFiScanClass::channel; + +public: + void printDiag(Print& dest); + friend class WiFiClient; +}; + +extern WiFiClass WiFi; + +#endif diff --git a/libraries/WiFi/src/WiFiAP.cpp b/libraries/WiFi/src/WiFiAP.cpp new file mode 100644 index 00000000..d824c104 --- /dev/null +++ b/libraries/WiFi/src/WiFiAP.cpp @@ -0,0 +1,234 @@ +/* + ESP8266WiFiSTA.cpp - WiFi library for esp8266 + + Copyright (c) 2014 Ivan Grokhotkov. All rights reserved. + This file is part of the esp8266 core for Arduino environment. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Reworked on 28 Dec 2015 by Markus Sattler + + */ + +#include "WiFi.h" +#include "WiFiGeneric.h" +#include "WiFiAP.h" + +extern "C" { +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +} + + + +// ----------------------------------------------------------------------------------------------------------------------- +// ---------------------------------------------------- Private functions ------------------------------------------------ +// ----------------------------------------------------------------------------------------------------------------------- + +static bool softap_config_equal(const wifi_config_t& lhs, const wifi_config_t& rhs); + + + +/** + * compare two AP configurations + * @param lhs softap_config + * @param rhs softap_config + * @return equal + */ +static bool softap_config_equal(const wifi_config_t& lhs, const wifi_config_t& rhs) +{ + if(strcmp(reinterpret_cast(lhs.ap.ssid), reinterpret_cast(rhs.ap.ssid)) != 0) { + return false; + } + if(strcmp(reinterpret_cast(lhs.ap.password), reinterpret_cast(rhs.ap.password)) != 0) { + return false; + } + if(lhs.ap.channel != rhs.ap.channel) { + return false; + } + if(lhs.ap.ssid_hidden != rhs.ap.ssid_hidden) { + return false; + } + return true; +} + +// ----------------------------------------------------------------------------------------------------------------------- +// ----------------------------------------------------- AP function ----------------------------------------------------- +// ----------------------------------------------------------------------------------------------------------------------- + + +/** + * Set up an access point + * @param ssid Pointer to the SSID (max 63 char). + * @param passphrase (for WPA2 min 8 char, for open use NULL) + * @param channel WiFi channel number, 1 - 13. + * @param ssid_hidden Network cloaking (0 = broadcast SSID, 1 = hide SSID) + */ +bool WiFiAPClass::softAP(const char* ssid, const char* passphrase, int channel, int ssid_hidden) +{ + + if(!WiFi.enableAP(true)) { + // enable AP failed + return false; + } + + if(!ssid || *ssid == 0 || strlen(ssid) > 31) { + // fail SSID too long or missing! + return false; + } + + if(passphrase && (strlen(passphrase) > 63 || strlen(passphrase) < 8)) { + // fail passphrase to long or short! + return false; + } + + esp_wifi_start(); + + wifi_config_t conf; + strcpy(reinterpret_cast(conf.ap.ssid), ssid); + conf.ap.channel = channel; + conf.ap.ssid_len = strlen(ssid); + conf.ap.ssid_hidden = ssid_hidden; + conf.ap.max_connection = 4; + conf.ap.beacon_interval = 100; + + if(!passphrase || strlen(passphrase) == 0) { + conf.ap.authmode = WIFI_AUTH_OPEN; + *conf.ap.password = 0; + } else { + conf.ap.authmode = WIFI_AUTH_WPA2_PSK; + strcpy(reinterpret_cast(conf.ap.password), passphrase); + } + + wifi_config_t conf_current; + esp_wifi_get_config(WIFI_IF_AP, &conf_current); + if(softap_config_equal(conf, conf_current)) { + //DEBUGV("softap config unchanged"); + return true; + } + + bool ret; + + ret = esp_wifi_set_config(WIFI_IF_AP, &conf) == ESP_OK; + + return ret; +} + + +/** + * Configure access point + * @param local_ip access point IP + * @param gateway gateway IP + * @param subnet subnet mask + */ +bool WiFiAPClass::softAPConfig(IPAddress local_ip, IPAddress gateway, IPAddress subnet) +{ + + if(!WiFi.enableAP(true)) { + // enable AP failed + return false; + } + + tcpip_adapter_ip_info_t info; + info.ip.addr = static_cast(local_ip); + info.gw.addr = static_cast(gateway); + info.netmask.addr = static_cast(subnet); + tcpip_adapter_dhcps_stop(TCPIP_ADAPTER_IF_AP); + if(tcpip_adapter_set_ip_info(TCPIP_ADAPTER_IF_AP, &info)) { + return tcpip_adapter_dhcps_start(TCPIP_ADAPTER_IF_AP); + } + return false; +} + + + +/** + * Disconnect from the network (close AP) + * @param wifioff disable mode? + * @return one value of wl_status_t enum + */ +bool WiFiAPClass::softAPdisconnect(bool wifioff) +{ + bool ret; + wifi_config_t conf; + *conf.ap.ssid = 0; + *conf.ap.password = 0; + ret = esp_wifi_set_config(WIFI_IF_AP, &conf) == ESP_OK; + + if(wifioff) { + ret = WiFi.enableAP(false) == ESP_OK; + } + + return ret; +} + + +/** + * Get the count of the Station / client that are connected to the softAP interface + * @return Stations count + */ +uint8_t WiFiAPClass::softAPgetStationNum() +{ + uint16_t number; + if(esp_wifi_get_ap_num(&number) == ESP_OK) { + return number; + } + return 0; +} + +/** + * Get the softAP interface IP address. + * @return IPAddress softAP IP + */ +IPAddress WiFiAPClass::softAPIP() +{ + tcpip_adapter_ip_info_t ip; + tcpip_adapter_get_ip_info(TCPIP_ADAPTER_IF_AP, &ip); + return IPAddress(ip.ip.addr); +} + + +/** + * Get the softAP interface MAC address. + * @param mac pointer to uint8_t array with length WL_MAC_ADDR_LENGTH + * @return pointer to uint8_t* + */ +uint8_t* WiFiAPClass::softAPmacAddress(uint8_t* mac) +{ + esp_wifi_get_mac(WIFI_IF_AP, mac); + return mac; +} + +/** + * Get the softAP interface MAC address. + * @return String mac + */ +String WiFiAPClass::softAPmacAddress(void) +{ + uint8_t mac[6]; + char macStr[18] = { 0 }; + esp_wifi_get_mac(WIFI_IF_AP, mac); + + sprintf(macStr, "%02X:%02X:%02X:%02X:%02X:%02X", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + return String(macStr); +} diff --git a/libraries/WiFi/src/WiFiAP.h b/libraries/WiFi/src/WiFiAP.h new file mode 100644 index 00000000..c7124a0b --- /dev/null +++ b/libraries/WiFi/src/WiFiAP.h @@ -0,0 +1,55 @@ +/* + ESP8266WiFiAP.h - esp8266 Wifi support. + Based on WiFi.h from Arduino WiFi shield library. + Copyright (c) 2011-2014 Arduino. All right reserved. + Modified by Ivan Grokhotkov, December 2014 + Reworked by Markus Sattler, December 2015 + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef ESP32WIFIAP_H_ +#define ESP32WIFIAP_H_ + + +#include "WiFiType.h" +#include "WiFiGeneric.h" + + +class WiFiAPClass +{ + + // ---------------------------------------------------------------------------------------------- + // ----------------------------------------- AP function ---------------------------------------- + // ---------------------------------------------------------------------------------------------- + +public: + + bool softAP(const char* ssid, const char* passphrase = NULL, int channel = 1, int ssid_hidden = 0); + bool softAPConfig(IPAddress local_ip, IPAddress gateway, IPAddress subnet); + bool softAPdisconnect(bool wifioff = false); + + uint8_t softAPgetStationNum(); + + IPAddress softAPIP(); + + uint8_t* softAPmacAddress(uint8_t* mac); + String softAPmacAddress(void); + +protected: + +}; + +#endif /* ESP32WIFIAP_H_*/ diff --git a/libraries/WiFi/src/WiFiClient.cpp b/libraries/WiFi/src/WiFiClient.cpp new file mode 100644 index 00000000..e59a3ddc --- /dev/null +++ b/libraries/WiFi/src/WiFiClient.cpp @@ -0,0 +1,250 @@ +/* + Client.h - Client class for Raspberry Pi + Copyright (c) 2016 Hristo Gochkov All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include "WiFiClient.h" +#include +#include +#include + +#undef connect +#undef write +#undef read + +WiFiClient::WiFiClient():sockfd(-1),_connected(false),next(NULL) +{ + //ets_printf("WiFiClient(%d)\n", sockfd); +} + +WiFiClient::WiFiClient(int fd):sockfd(fd),_connected(true),next(NULL) +{ + ets_printf("WiFiClient(%d)\n", sockfd); +} + +WiFiClient::~WiFiClient() +{ + if(sockfd >= 0) { + ets_printf("~WiFiClient(%d)\n", sockfd); + } + //stop(); +} + +WiFiClient & WiFiClient::operator=(const WiFiClient &other) +{ + ets_printf("WiFiClient(%d) = (%d)\n", sockfd, other.sockfd); + stop(); + sockfd = other.sockfd; + _connected = other._connected; + return *this; +} + +void WiFiClient::stop() +{ + if(_connected && sockfd >= 0) { + close(sockfd); + sockfd = -1; + _connected = false; + } +} + +int WiFiClient::connect(IPAddress ip, uint16_t port) +{ + sockfd = socket(AF_INET, SOCK_STREAM, 0); + if (sockfd < 0) { + log_e("error: %d", errno); + return 0; + } + uint32_t ip_addr = ip; + struct sockaddr_in serveraddr; + bzero((char *) &serveraddr, sizeof(serveraddr)); + serveraddr.sin_family = AF_INET; + bcopy((const void *)(&ip_addr), (void *)&serveraddr.sin_addr.s_addr, 4); + serveraddr.sin_port = htons(port); + int res = lwip_connect_r(sockfd, (struct sockaddr*)&serveraddr, sizeof(serveraddr)); + if (res < 0) { + log_e("error: %d", errno); + close(sockfd); + sockfd = -1; + return 0; + } + _connected = true; + return 1; +} + +int WiFiClient::connect(const char *host, uint16_t port) +{ + struct hostent *server; + server = gethostbyname(host); + if (server == NULL) { + return 0; + } + IPAddress srv((const uint8_t *)(server->h_addr)); + return connect(srv, port); +} + +int WiFiClient::setSocketOption(int option, char* value, size_t len) +{ + int res = setsockopt(sockfd, SOL_SOCKET, option, value, len); + if(res < 0) { + log_e("error: %d", errno); + } + return res; +} + +int WiFiClient::setTimeout(uint32_t seconds) +{ + struct timeval tv; + tv.tv_sec = seconds; + tv.tv_usec = 0; + if(setSocketOption(SO_RCVTIMEO, (char *)&tv, sizeof(struct timeval)) < 0) { + return -1; + } + return setSocketOption(SO_SNDTIMEO, (char *)&tv, sizeof(struct timeval)); +} + +int WiFiClient::setOption(int option, int *value) +{ + int res = setsockopt(sockfd, IPPROTO_TCP, option, (char *)value, sizeof(int)); + if(res < 0) { + log_e("error: %d", errno); + } + return res; +} + +int WiFiClient::getOption(int option, int *value) +{ + size_t size = sizeof(int); + int res = getsockopt(sockfd, IPPROTO_TCP, option, (char *)value, &size); + if(res < 0) { + log_e("error: %d", errno); + } + return res; +} + +int WiFiClient::setNoDelay(bool nodelay) +{ + int flag = nodelay; + return setOption(TCP_NODELAY, &flag); +} + +bool WiFiClient::getNoDelay() +{ + int flag = 0; + getOption(TCP_NODELAY, &flag); + return flag; +} + +size_t WiFiClient::write(uint8_t data) +{ + return write(&data, 1); +} + +int WiFiClient::read() +{ + uint8_t data = 0; + int res = read(&data, 1); + if(res < 0) { + return res; + } + return data; +} + +size_t WiFiClient::write(const uint8_t *buf, size_t size) +{ + if(!_connected) { + return 0; + } + int res = send(sockfd, (void*)buf, size, MSG_DONTWAIT); + if(res < 0) { + log_e("error: %d", errno); + _connected = false; + sockfd = -1; + res = 0; + } + return res; +} + +int WiFiClient::read(uint8_t *buf, size_t size) +{ + if(!available()) { + return -1; + } + int res = recv(sockfd, buf, size, MSG_DONTWAIT); + if(res < 0 && errno != EWOULDBLOCK) { + log_e("error: %d", errno); + _connected = false; + sockfd = -1; + } + return res; +} + +int WiFiClient::available() +{ + if(!_connected) { + return 0; + } + int count; + int res = ioctl(sockfd, FIONREAD, &count); + if(res < 0) { + log_e("error: %d", errno); + _connected = false; + sockfd = -1; + return 0; + } + return count; +} + +uint8_t WiFiClient::connected() +{ + uint8_t dummy = 0; + read(&dummy, 0); + return _connected; +} + +IPAddress WiFiClient::remoteIP(int fd) +{ + struct sockaddr_storage addr; + socklen_t len = sizeof addr; + getpeername(fd, (struct sockaddr*)&addr, &len); + struct sockaddr_in *s = (struct sockaddr_in *)&addr; + return IPAddress((uint32_t)(s->sin_addr.s_addr)); +} + +uint16_t WiFiClient::remotePort(int fd) +{ + struct sockaddr_storage addr; + socklen_t len = sizeof addr; + getpeername(fd, (struct sockaddr*)&addr, &len); + struct sockaddr_in *s = (struct sockaddr_in *)&addr; + return ntohs(s->sin_port); +} + +IPAddress WiFiClient::remoteIP() +{ + return remoteIP(sockfd); +} + +uint16_t WiFiClient::remotePort() +{ + return remotePort(sockfd); +} + +bool WiFiClient::operator==(const WiFiClient& rhs) +{ + return sockfd == rhs.sockfd && remotePort(sockfd) == remotePort(rhs.sockfd) && remoteIP(sockfd) == remoteIP(rhs.sockfd); +} diff --git a/libraries/WiFi/src/WiFiClient.h b/libraries/WiFi/src/WiFiClient.h new file mode 100644 index 00000000..b2e3e450 --- /dev/null +++ b/libraries/WiFi/src/WiFiClient.h @@ -0,0 +1,92 @@ +/* + Client.h - Base class that provides Client + Copyright (c) 2011 Adrian McEwen. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef _WIFICLIENT_H_ +#define _WIFICLIENT_H_ + + +#include "Arduino.h" +#include "Client.h" + +class WiFiClient : public Client +{ +protected: + int sockfd; + bool _connected; + +public: + WiFiClient *next; + WiFiClient(); + WiFiClient(int fd); + ~WiFiClient(); + int connect(IPAddress ip, uint16_t port); + int connect(const char *host, uint16_t port); + size_t write(uint8_t data); + size_t write(const uint8_t *buf, size_t size); + int available(); + int read(); + int read(uint8_t *buf, size_t size); + int peek() + { + return 0; + } + void flush() {} + void stop(); + uint8_t connected(); + + operator bool() + { + return connected(); + } + WiFiClient & operator=(const WiFiClient &other); + bool operator==(const bool value) + { + return bool() == value; + } + bool operator!=(const bool value) + { + return bool() != value; + } + bool operator==(const WiFiClient&); + bool operator!=(const WiFiClient& rhs) + { + return !this->operator==(rhs); + }; + + int fd() + { + return sockfd; + } + IPAddress remoteIP(); + uint16_t remotePort(); + int setSocketOption(int option, char* value, size_t len); + int setOption(int option, int *value); + int getOption(int option, int *value); + int setTimeout(uint32_t seconds); + int setNoDelay(bool nodelay); + bool getNoDelay(); + + IPAddress remoteIP(int fd); + uint16_t remotePort(int fd); + + //friend class WiFiServer; + using Print::write; +}; + +#endif /* _WIFICLIENT_H_ */ diff --git a/libraries/WiFi/src/WiFiGeneric.cpp b/libraries/WiFi/src/WiFiGeneric.cpp new file mode 100644 index 00000000..5b5b426f --- /dev/null +++ b/libraries/WiFi/src/WiFiGeneric.cpp @@ -0,0 +1,333 @@ +/* + ESP8266WiFiGeneric.cpp - WiFi library for esp8266 + + Copyright (c) 2014 Ivan Grokhotkov. All rights reserved. + This file is part of the esp8266 core for Arduino environment. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Reworked on 28 Dec 2015 by Markus Sattler + + */ + +#include "WiFi.h" +#include "WiFiGeneric.h" + +extern "C" { +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "lwip/opt.h" +#include "lwip/err.h" +#include "lwip/dns.h" + +#include "esp32-hal-log.h" +} + +//#include "WiFiClient.h" +//#include "WiFiUdp.h" + +#undef min +#undef max +#include + +// ----------------------------------------------------------------------------------------------------------------------- +// ------------------------------------------------- Generic WiFi function ----------------------------------------------- +// ----------------------------------------------------------------------------------------------------------------------- + +// arduino dont like std::vectors move static here +static std::vector cbEventList; + +bool WiFiGenericClass::_persistent = true; +wifi_mode_t WiFiGenericClass::_forceSleepLastMode = WIFI_MODE_NULL; + +WiFiGenericClass::WiFiGenericClass() +{ + +} + +/** + * set callback function + * @param cbEvent WiFiEventCb + * @param event optional filter (WIFI_EVENT_MAX is all events) + */ +void WiFiGenericClass::onEvent(WiFiEventCb cbEvent, system_event_id_t event) +{ + if(!cbEvent) { + return; + } + WiFiEventCbList_t newEventHandler; + newEventHandler.cb = cbEvent; + newEventHandler.event = event; + cbEventList.push_back(newEventHandler); +} + +/** + * removes a callback form event handler + * @param cbEvent WiFiEventCb + * @param event optional filter (WIFI_EVENT_MAX is all events) + */ +void WiFiGenericClass::removeEvent(WiFiEventCb cbEvent, system_event_id_t event) +{ + if(!cbEvent) { + return; + } + + for(uint32_t i = 0; i < cbEventList.size(); i++) { + WiFiEventCbList_t entry = cbEventList[i]; + if(entry.cb == cbEvent && entry.event == event) { + cbEventList.erase(cbEventList.begin() + i); + } + } +} + +/** + * callback for WiFi events + * @param arg + */ +esp_err_t WiFiGenericClass::_eventCallback(void *arg, system_event_t *event) +{ + log_d("wifi evt: %d", event->event_id); + + if(event->event_id == SYSTEM_EVENT_SCAN_DONE) { + WiFiScanClass::_scanDone(); + } else if(event->event_id == SYSTEM_EVENT_STA_DISCONNECTED) { + uint8_t reason = event->event_info.disconnected.reason; + if(reason == WIFI_REASON_NO_AP_FOUND) { + WiFiSTAClass::_setStatus(WL_NO_SSID_AVAIL); + } else if(reason == WIFI_REASON_AUTH_FAIL || reason == WIFI_REASON_ASSOC_FAIL) { + WiFiSTAClass::_setStatus(WL_CONNECT_FAILED); + } else if(reason == WIFI_REASON_BEACON_TIMEOUT || reason == WIFI_REASON_HANDSHAKE_TIMEOUT) { + WiFiSTAClass::_setStatus(WL_CONNECTION_LOST); + } else { + WiFiSTAClass::_setStatus(WL_DISCONNECTED); + } + log_d("wifi reason: %d", reason); + } else if(event->event_id == SYSTEM_EVENT_STA_START) { + WiFiSTAClass::_setStatus(WL_DISCONNECTED); + } else if(event->event_id == SYSTEM_EVENT_STA_STOP) { + WiFiSTAClass::_setStatus(WL_NO_SHIELD); + } else if(event->event_id == SYSTEM_EVENT_STA_GOT_IP) { + WiFiSTAClass::_setStatus(WL_CONNECTED); + } + + for(uint32_t i = 0; i < cbEventList.size(); i++) { + WiFiEventCbList_t entry = cbEventList[i]; + if(entry.cb) { + if(entry.event == (system_event_id_t) event->event_id || entry.event == SYSTEM_EVENT_MAX) { + entry.cb((system_event_id_t) event->event_id); + } + } + } + return ESP_OK; +} + +/** + * Return the current channel associated with the network + * @return channel (1-13) + */ +int32_t WiFiGenericClass::channel(void) +{ + uint8_t primaryChan; + wifi_second_chan_t secondChan; + esp_wifi_get_channel(&primaryChan, &secondChan); + return primaryChan; +} + + +/** + * store WiFi config in SDK flash area + * @param persistent + */ +void WiFiGenericClass::persistent(bool persistent) +{ + _persistent = persistent; +} + + +/** + * set new mode + * @param m WiFiMode_t + */ +bool WiFiGenericClass::mode(wifi_mode_t m) +{ + if(getMode() == m) { + return true; + } + return esp_wifi_set_mode(m) == ESP_OK; +} + +/** + * get WiFi mode + * @return WiFiMode + */ +wifi_mode_t WiFiGenericClass::getMode() +{ + uint8_t mode; + esp_wifi_get_mode((wifi_mode_t*)&mode); + return (wifi_mode_t)mode; +} + +/** + * control STA mode + * @param enable bool + * @return ok + */ +bool WiFiGenericClass::enableSTA(bool enable) +{ + + wifi_mode_t currentMode = getMode(); + bool isEnabled = ((currentMode & WIFI_MODE_STA) != 0); + + if(isEnabled != enable) { + if(enable) { + return mode((wifi_mode_t)(currentMode | WIFI_MODE_STA)); + } else { + return mode((wifi_mode_t)(currentMode & (~WIFI_MODE_STA))); + } + } else { + return true; + } +} + +/** + * control AP mode + * @param enable bool + * @return ok + */ +bool WiFiGenericClass::enableAP(bool enable) +{ + + wifi_mode_t currentMode = getMode(); + bool isEnabled = ((currentMode & WIFI_MODE_AP) != 0); + + if(isEnabled != enable) { + if(enable) { + return mode((wifi_mode_t)(currentMode | WIFI_MODE_AP)); + } else { + return mode((wifi_mode_t)(currentMode & (~WIFI_MODE_AP))); + } + } else { + return true; + } +} + + +// ----------------------------------------------------------------------------------------------------------------------- +// ------------------------------------------------ Generic Network function --------------------------------------------- +// ----------------------------------------------------------------------------------------------------------------------- + +void wifi_dns_found_callback(const char *name, const ip_addr_t *ipaddr, void *callback_arg); + +/** + * Resolve the given hostname to an IP address. + * @param aHostname Name to be resolved + * @param aResult IPAddress structure to store the returned IP address + * @return 1 if aIPAddrString was successfully converted to an IP address, + * else error code + */ +static bool _dns_busy = false; + +int WiFiGenericClass::hostByName(const char* aHostname, IPAddress& aResult) +{ + ip_addr_t addr; + aResult = static_cast(0); + err_t err = dns_gethostbyname(aHostname, &addr, &wifi_dns_found_callback, &aResult); + _dns_busy = err == ERR_INPROGRESS; + while(_dns_busy); + if(err == ERR_INPROGRESS && aResult) { + //found by search + } else if(err == ERR_OK && addr.u_addr.ip4.addr) { + aResult = addr.u_addr.ip4.addr; + } else { + return 0; + } + return 1; +} + +/** + * DNS callback + * @param name + * @param ipaddr + * @param callback_arg + */ +void wifi_dns_found_callback(const char *name, const ip_addr_t *ipaddr, void *callback_arg) +{ + if(ipaddr) { + (*reinterpret_cast(callback_arg)) = ipaddr->u_addr.ip4.addr; + } + _dns_busy = false; +} + +/** + * Boot and start WiFi + * This method get's called on boot if you use any of the WiFi methods. + * If you do not link to this library, WiFi will not be started. + * */ +#include "nvs_flash.h" + +void bootWiFi() +{ + esp_err_t err; + wifi_init_config_t cfg; + wifi_mode_t mode = WIFI_MODE_NULL; + bool auto_connect = false; + + err = nvs_flash_init(); + if (err != ESP_OK) { + log_e("nvs_flash_init fail %d", err); + return; + } + + system_init(); + tcpip_adapter_init(); + esp_event_loop_init(WiFiGenericClass::_eventCallback, NULL); + + cfg.event_handler = &esp_event_send; + err = esp_wifi_init(&cfg); + if (err != ESP_OK) { + log_e("esp_wifi_init fail %d\n", err); + return; + } + + err = esp_wifi_start(); + if (err != ESP_OK) { + log_e("esp_wifi_start fail %d\n", err); + return; + } + + err = esp_wifi_get_mode(&mode); + if (err != ESP_OK) { + log_e("esp_wifi_get_mode fail %d\n", err); + return; + } + + err = esp_wifi_get_auto_connect(&auto_connect); + if ((mode == WIFI_MODE_STA || mode == WIFI_MODE_APSTA) && auto_connect) { + err = esp_wifi_connect(); + if (err != ESP_OK) { + log_e("esp_wifi_connect fail %d\n", err); + } + } +} + diff --git a/libraries/WiFi/src/WiFiGeneric.h b/libraries/WiFi/src/WiFiGeneric.h new file mode 100644 index 00000000..95b85b16 --- /dev/null +++ b/libraries/WiFi/src/WiFiGeneric.h @@ -0,0 +1,73 @@ +/* + ESP8266WiFiGeneric.h - esp8266 Wifi support. + Based on WiFi.h from Ardiono WiFi shield library. + Copyright (c) 2011-2014 Arduino. All right reserved. + Modified by Ivan Grokhotkov, December 2014 + Reworked by Markus Sattler, December 2015 + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef ESP32WIFIGENERIC_H_ +#define ESP32WIFIGENERIC_H_ + +#include "WiFiType.h" +#include +#include + +typedef void (*WiFiEventCb)(system_event_id_t event); + +typedef struct { + WiFiEventCb cb; + system_event_id_t event; +} WiFiEventCbList_t; + +class WiFiGenericClass +{ +public: + + WiFiGenericClass(); + + void onEvent(WiFiEventCb cbEvent, system_event_id_t event = SYSTEM_EVENT_MAX); + void removeEvent(WiFiEventCb cbEvent, system_event_id_t event = SYSTEM_EVENT_MAX); + + int32_t channel(void); + + void persistent(bool persistent); + + static bool mode(wifi_mode_t); + static wifi_mode_t getMode(); + + bool enableSTA(bool enable); + bool enableAP(bool enable); + + static esp_err_t _eventCallback(void *arg, system_event_t *event); + +protected: + static bool _persistent; + static wifi_mode_t _forceSleepLastMode; + +public: + + int hostByName(const char* aHostname, IPAddress& aResult); + +protected: + + friend class WiFiSTAClass; + friend class WiFiScanClass; + friend class WiFiAPClass; +}; + +#endif /* ESP32WIFIGENERIC_H_ */ diff --git a/libraries/WiFi/src/WiFiMulti.cpp b/libraries/WiFi/src/WiFiMulti.cpp new file mode 100644 index 00000000..ef7fdd4e --- /dev/null +++ b/libraries/WiFi/src/WiFiMulti.cpp @@ -0,0 +1,218 @@ +/** + * + * @file ESP8266WiFiMulti.cpp + * @date 16.05.2015 + * @author Markus Sattler + * + * Copyright (c) 2015 Markus Sattler. All rights reserved. + * This file is part of the esp8266 core for Arduino environment. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +#include "WiFiMulti.h" +#include +#include +#include + +WiFiMulti::WiFiMulti() +{ +} + +WiFiMulti::~WiFiMulti() +{ + APlistClean(); +} + +bool WiFiMulti::addAP(const char* ssid, const char *passphrase) +{ + return APlistAdd(ssid, passphrase); +} + +uint8_t WiFiMulti::run(void) +{ + + int8_t scanResult; + uint8_t status = WiFi.status(); + if(status == WL_DISCONNECTED || status == WL_NO_SSID_AVAIL || status == WL_IDLE_STATUS || status == WL_CONNECT_FAILED) { + + scanResult = WiFi.scanComplete(); + if(scanResult == WIFI_SCAN_RUNNING) { + // scan is running + return WL_NO_SSID_AVAIL; + } else if(scanResult > 0) { + // scan done analyze + WifiAPlist_t bestNetwork { NULL, NULL }; + int bestNetworkDb = INT_MIN; + uint8_t bestBSSID[6]; + int32_t bestChannel = 0; + + DEBUG_WIFI_MULTI("[WIFI] scan done\n"); + delay(0); + + if(scanResult <= 0) { + DEBUG_WIFI_MULTI("[WIFI] no networks found\n"); + } else { + DEBUG_WIFI_MULTI("[WIFI] %d networks found\n", scanResult); + for(int8_t i = 0; i < scanResult; ++i) { + + String ssid_scan; + int32_t rssi_scan; + uint8_t sec_scan; + uint8_t* BSSID_scan; + int32_t chan_scan; + + WiFi.getNetworkInfo(i, ssid_scan, sec_scan, rssi_scan, BSSID_scan, chan_scan); + + bool known = false; + for(uint32_t x = 0; x < APlist.size(); x++) { + WifiAPlist_t entry = APlist[x]; + + if(ssid_scan == entry.ssid) { // SSID match + known = true; + if(rssi_scan > bestNetworkDb) { // best network + if(sec_scan == WIFI_AUTH_OPEN || entry.passphrase) { // check for passphrase if not open wlan + bestNetworkDb = rssi_scan; + bestChannel = chan_scan; + memcpy((void*) &bestNetwork, (void*) &entry, sizeof(bestNetwork)); + memcpy((void*) &bestBSSID, (void*) BSSID_scan, sizeof(bestBSSID)); + } + } + break; + } + } + + if(known) { + DEBUG_WIFI_MULTI(" ---> "); + } else { + DEBUG_WIFI_MULTI(" "); + } + + DEBUG_WIFI_MULTI(" %d: [%d][%02X:%02X:%02X:%02X:%02X:%02X] %s (%d) %c\n", i, chan_scan, BSSID_scan[0], BSSID_scan[1], BSSID_scan[2], BSSID_scan[3], BSSID_scan[4], BSSID_scan[5], ssid_scan.c_str(), rssi_scan, (sec_scan == WIFI_AUTH_OPEN) ? ' ' : '*'); + delay(0); + } + } + + // clean up ram + WiFi.scanDelete(); + + DEBUG_WIFI_MULTI("\n\n"); + delay(0); + + if(bestNetwork.ssid) { + DEBUG_WIFI_MULTI("[WIFI] Connecting BSSID: %02X:%02X:%02X:%02X:%02X:%02X SSID: %s Channal: %d (%d)\n", bestBSSID[0], bestBSSID[1], bestBSSID[2], bestBSSID[3], bestBSSID[4], bestBSSID[5], bestNetwork.ssid, bestChannel, bestNetworkDb); + + WiFi.begin(bestNetwork.ssid, bestNetwork.passphrase, bestChannel, bestBSSID); + status = WiFi.status(); + + // wait for connection or fail + while(status != WL_CONNECTED && status != WL_NO_SSID_AVAIL && status != WL_CONNECT_FAILED) { + delay(10); + status = WiFi.status(); + } + + IPAddress ip; + uint8_t * mac; + switch(status) { + case 3: + ip = WiFi.localIP(); + mac = WiFi.BSSID(); + DEBUG_WIFI_MULTI("[WIFI] Connecting done.\n"); + DEBUG_WIFI_MULTI("[WIFI] SSID: %s\n", WiFi.SSID()); + DEBUG_WIFI_MULTI("[WIFI] IP: %d.%d.%d.%d\n", ip[0], ip[1], ip[2], ip[3]); + DEBUG_WIFI_MULTI("[WIFI] MAC: %02X:%02X:%02X:%02X:%02X:%02X\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + DEBUG_WIFI_MULTI("[WIFI] Channel: %d\n", WiFi.channel()); + break; + case 1: + DEBUG_WIFI_MULTI("[WIFI] Connecting Failed AP not found.\n"); + break; + case 4: + DEBUG_WIFI_MULTI("[WIFI] Connecting Failed.\n"); + break; + default: + DEBUG_WIFI_MULTI("[WIFI] Connecting Failed (%d).\n", status); + break; + } + } else { + DEBUG_WIFI_MULTI("[WIFI] no matching wifi found!\n"); + } + } else { + // start scan + DEBUG_WIFI_MULTI("[WIFI] delete old wifi config...\n"); + WiFi.disconnect(); + + DEBUG_WIFI_MULTI("[WIFI] start scan\n"); + // scan wifi async mode + WiFi.scanNetworks(true); + } + } + return status; +} + +// ################################################################################## + +bool WiFiMulti::APlistAdd(const char* ssid, const char *passphrase) +{ + + WifiAPlist_t newAP; + + if(!ssid || *ssid == 0x00 || strlen(ssid) > 31) { + // fail SSID to long or missing! + DEBUG_WIFI_MULTI("[WIFI][APlistAdd] no ssid or ssid to long\n"); + return false; + } + + if(passphrase && strlen(passphrase) > 63) { + // fail passphrase to long! + DEBUG_WIFI_MULTI("[WIFI][APlistAdd] passphrase to long\n"); + return false; + } + + newAP.ssid = strdup(ssid); + + if(!newAP.ssid) { + DEBUG_WIFI_MULTI("[WIFI][APlistAdd] fail newAP.ssid == 0\n"); + return false; + } + + if(passphrase && *passphrase != 0x00) { + newAP.passphrase = strdup(passphrase); + if(!newAP.passphrase) { + DEBUG_WIFI_MULTI("[WIFI][APlistAdd] fail newAP.passphrase == 0\n"); + free(newAP.ssid); + return false; + } + } + + APlist.push_back(newAP); + DEBUG_WIFI_MULTI("[WIFI][APlistAdd] add SSID: %s\n", newAP.ssid); + return true; +} + +void WiFiMulti::APlistClean(void) +{ + for(uint32_t i = 0; i < APlist.size(); i++) { + WifiAPlist_t entry = APlist[i]; + if(entry.ssid) { + free(entry.ssid); + } + if(entry.passphrase) { + free(entry.passphrase); + } + } + APlist.clear(); +} + diff --git a/libraries/WiFi/src/WiFiMulti.h b/libraries/WiFi/src/WiFiMulti.h new file mode 100644 index 00000000..500aada1 --- /dev/null +++ b/libraries/WiFi/src/WiFiMulti.h @@ -0,0 +1,66 @@ +/** + * + * @file ESP8266WiFiMulti.h + * @date 16.05.2015 + * @author Markus Sattler + * + * Copyright (c) 2015 Markus Sattler. All rights reserved. + * This file is part of the esp8266 core for Arduino environment. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +#ifndef WIFICLIENTMULTI_H_ +#define WIFICLIENTMULTI_H_ + +#include "WiFi.h" +#undef min +#undef max +#include + +#ifdef DEBUG_ESP_WIFI +#ifdef DEBUG_ESP_PORT +#define DEBUG_WIFI_MULTI(...) DEBUG_ESP_PORT.printf( __VA_ARGS__ ) +#endif +#endif + +#ifndef DEBUG_WIFI_MULTI +#define DEBUG_WIFI_MULTI(...) +#endif + +typedef struct { + char * ssid; + char * passphrase; +} WifiAPlist_t; + +class WiFiMulti +{ +public: + WiFiMulti(); + ~WiFiMulti(); + + bool addAP(const char* ssid, const char *passphrase = NULL); + + uint8_t run(void); + +private: + std::vector APlist; + bool APlistAdd(const char* ssid, const char *passphrase = NULL); + void APlistClean(void); + +}; + +#endif /* WIFICLIENTMULTI_H_ */ diff --git a/libraries/WiFi/src/WiFiSTA.cpp b/libraries/WiFi/src/WiFiSTA.cpp new file mode 100644 index 00000000..fd4c90d0 --- /dev/null +++ b/libraries/WiFi/src/WiFiSTA.cpp @@ -0,0 +1,455 @@ +/* + ESP8266WiFiSTA.cpp - WiFi library for esp8266 + + Copyright (c) 2014 Ivan Grokhotkov. All rights reserved. + This file is part of the esp8266 core for Arduino environment. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Reworked on 28 Dec 2015 by Markus Sattler + + */ + +#include "WiFi.h" +#include "WiFiGeneric.h" +#include "WiFiSTA.h" + +extern "C" { +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "lwip/err.h" +#include "lwip/dns.h" +} + +extern "C" void esp_schedule(); +extern "C" void esp_yield(); + +// ----------------------------------------------------------------------------------------------------------------------- +// ---------------------------------------------------- Private functions ------------------------------------------------ +// ----------------------------------------------------------------------------------------------------------------------- + +static bool sta_config_equal(const wifi_config_t& lhs, const wifi_config_t& rhs); + + +/** + * compare two STA configurations + * @param lhs station_config + * @param rhs station_config + * @return equal + */ +static bool sta_config_equal(const wifi_config_t& lhs, const wifi_config_t& rhs) +{ + if(strcmp(reinterpret_cast(lhs.sta.ssid), reinterpret_cast(rhs.sta.ssid)) != 0) { + return false; + } + + if(strcmp(reinterpret_cast(lhs.sta.password), reinterpret_cast(rhs.sta.password)) != 0) { + return false; + } + + if(lhs.sta.bssid_set != rhs.sta.bssid_set) { + return false; + } + + if(lhs.sta.bssid_set) { + if(memcmp(lhs.sta.bssid, rhs.sta.bssid, 6) != 0) { + return false; + } + } + + return true; +} + +// ----------------------------------------------------------------------------------------------------------------------- +// ---------------------------------------------------- STA function ----------------------------------------------------- +// ----------------------------------------------------------------------------------------------------------------------- + +bool WiFiSTAClass::_useStaticIp = false; +wl_status_t WiFiSTAClass::_status = WL_NO_SHIELD; +/** + * Start Wifi connection + * if passphrase is set the most secure supported mode will be automatically selected + * @param ssid const char* Pointer to the SSID string. + * @param passphrase const char * Optional. Passphrase. Valid characters in a passphrase must be between ASCII 32-126 (decimal). + * @param bssid uint8_t[6] Optional. BSSID / MAC of AP + * @param channel Optional. Channel of AP + * @param connect Optional. call connect + * @return + */ +wl_status_t WiFiSTAClass::begin(const char* ssid, const char *passphrase, int32_t channel, const uint8_t* bssid, bool connect) +{ + + if(!WiFi.enableSTA(true)) { + // enable STA failed + return WL_CONNECT_FAILED; + } + + if(!ssid || *ssid == 0x00 || strlen(ssid) > 31) { + // fail SSID too long or missing! + return WL_CONNECT_FAILED; + } + + if(passphrase && strlen(passphrase) > 63) { + // fail passphrase too long! + return WL_CONNECT_FAILED; + } + + wifi_config_t conf; + strcpy(reinterpret_cast(conf.sta.ssid), ssid); + + if(passphrase) { + strcpy(reinterpret_cast(conf.sta.password), passphrase); + } else { + *conf.sta.password = 0; + } + + if(bssid) { + conf.sta.bssid_set = 1; + memcpy((void *) &conf.sta.bssid[0], (void *) bssid, 6); + } else { + conf.sta.bssid_set = 0; + } + + wifi_config_t current_conf; + esp_wifi_get_config(WIFI_IF_STA, ¤t_conf); + if(!sta_config_equal(current_conf, conf)) { + esp_wifi_set_config(WIFI_IF_STA, &conf); + } + + + + if(channel > 0 && channel <= 13) { + esp_wifi_set_channel(channel, WIFI_SECOND_CHAN_NONE); + } + + if(!_useStaticIp) { + tcpip_adapter_dhcpc_start(TCPIP_ADAPTER_IF_STA); + } + + if(connect) { + esp_wifi_connect(); + } + + return status(); +} + +wl_status_t WiFiSTAClass::begin(char* ssid, char *passphrase, int32_t channel, const uint8_t* bssid, bool connect) +{ + return begin((const char*) ssid, (const char*) passphrase, channel, bssid, connect); +} + +/** + * Use to connect to SDK config. + * @return wl_status_t + */ +wl_status_t WiFiSTAClass::begin() +{ + + if(!WiFi.enableSTA(true)) { + // enable STA failed + return WL_CONNECT_FAILED; + } + esp_wifi_start(); + esp_wifi_connect(); + + if(!_useStaticIp) { + tcpip_adapter_dhcpc_start(TCPIP_ADAPTER_IF_STA); + } + return status(); +} + +void WiFiSTAClass::_setStatus(wl_status_t status) +{ + _status = status; + //log_i("wifi status: %d", status); +} + +/** + * Change IP configuration settings disabling the dhcp client + * @param local_ip Static ip configuration + * @param gateway Static gateway configuration + * @param subnet Static Subnet mask + * @param dns1 Static DNS server 1 + * @param dns2 Static DNS server 2 + */ +bool WiFiSTAClass::config(IPAddress local_ip, IPAddress gateway, IPAddress subnet, IPAddress dns1, IPAddress dns2) +{ + + if(!WiFi.enableSTA(true)) { + return false; + } + + tcpip_adapter_ip_info_t info; + info.ip.addr = static_cast(local_ip); + info.gw.addr = static_cast(gateway); + info.netmask.addr = static_cast(subnet); + + tcpip_adapter_dhcpc_stop(TCPIP_ADAPTER_IF_STA); + if(tcpip_adapter_set_ip_info(TCPIP_ADAPTER_IF_STA, &info)) { + _useStaticIp = true; + } else { + return false; + } + ip_addr_t d; + + if(dns1 != (uint32_t)0x00000000) { + // Set DNS1-Server + d.u_addr.ip4.addr = static_cast(dns1); + dns_setserver(0, &d); + } + + if(dns2 != (uint32_t)0x00000000) { + // Set DNS2-Server + d.u_addr.ip4.addr = static_cast(dns2); + dns_setserver(1, &d); + } + + return true; +} + +/** + * will force a disconnect an then start reconnecting to AP + * @return ok + */ +bool WiFiSTAClass::reconnect() +{ + if((WiFi.getMode() & WIFI_MODE_STA) != 0) { + if(esp_wifi_disconnect() == ESP_OK) { + return esp_wifi_connect() == ESP_OK; + } + } + return false; +} + +/** + * Disconnect from the network + * @param wifioff + * @return one value of wl_status_t enum + */ +bool WiFiSTAClass::disconnect(bool wifioff) +{ + bool ret; + wifi_config_t conf; + *conf.sta.ssid = 0; + *conf.sta.password = 0; + + esp_wifi_set_config(WIFI_IF_STA, &conf); + ret = esp_wifi_set_config(WIFI_IF_STA, &conf) == ESP_OK; + + if(wifioff) { + WiFi.enableSTA(false); + } + + return ret; +} + +/** + * is STA interface connected? + * @return true if STA is connected to an AD + */ +bool WiFiSTAClass::isConnected() +{ + return (status() == WL_CONNECTED); +} + + +/** + * Setting the ESP32 station to connect to the AP (which is recorded) + * automatically or not when powered on. Enable auto-connect by default. + * @param autoConnect bool + * @return if saved + */ +bool WiFiSTAClass::setAutoConnect(bool autoConnect) +{ + bool ret; + ret = esp_wifi_set_auto_connect(autoConnect); + return ret; +} + +/** + * Checks if ESP32 station mode will connect to AP + * automatically or not when it is powered on. + * @return auto connect + */ +bool WiFiSTAClass::getAutoConnect() +{ + bool autoConnect; + esp_wifi_get_auto_connect(&autoConnect); + return autoConnect; +} + +/** + * Wait for WiFi connection to reach a result + * returns the status reached or disconnect if STA is off + * @return wl_status_t + */ +uint8_t WiFiSTAClass::waitForConnectResult() +{ + //1 and 3 have STA enabled + if((WiFiGenericClass::getMode() & WIFI_MODE_STA) == 0) { + return WL_DISCONNECTED; + } + int i = 0; + while(status() >= WL_DISCONNECTED && i++ < 100) { + delay(100); + } + return status(); +} + +/** + * Get the station interface IP address. + * @return IPAddress station IP + */ +IPAddress WiFiSTAClass::localIP() +{ + tcpip_adapter_ip_info_t ip; + tcpip_adapter_get_ip_info(TCPIP_ADAPTER_IF_STA, &ip); + return IPAddress(ip.ip.addr); +} + + +/** + * Get the station interface MAC address. + * @param mac pointer to uint8_t array with length WL_MAC_ADDR_LENGTH + * @return pointer to uint8_t * + */ +uint8_t* WiFiSTAClass::macAddress(uint8_t* mac) +{ + esp_wifi_get_mac(WIFI_IF_STA, mac); + return mac; +} + +/** + * Get the station interface MAC address. + * @return String mac + */ +String WiFiSTAClass::macAddress(void) +{ + uint8_t mac[6]; + char macStr[18] = { 0 }; + esp_wifi_get_mac(WIFI_IF_STA, mac); + + sprintf(macStr, "%02X:%02X:%02X:%02X:%02X:%02X", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + return String(macStr); +} + +/** + * Get the interface subnet mask address. + * @return IPAddress subnetMask + */ +IPAddress WiFiSTAClass::subnetMask() +{ + tcpip_adapter_ip_info_t ip; + tcpip_adapter_get_ip_info(TCPIP_ADAPTER_IF_STA, &ip); + return IPAddress(ip.netmask.addr); +} + +/** + * Get the gateway ip address. + * @return IPAddress gatewayIP + */ +IPAddress WiFiSTAClass::gatewayIP() +{ + tcpip_adapter_ip_info_t ip; + tcpip_adapter_get_ip_info(TCPIP_ADAPTER_IF_STA, &ip); + return IPAddress(ip.gw.addr); +} + +/** + * Get the DNS ip address. + * @param dns_no + * @return IPAddress DNS Server IP + */ +IPAddress WiFiSTAClass::dnsIP(uint8_t dns_no) +{ + ip_addr_t dns_ip = dns_getserver(dns_no); + return IPAddress(dns_ip.u_addr.ip4.addr); +} + +/** + * Return Connection status. + * @return one of the value defined in wl_status_t + * + */ +wl_status_t WiFiSTAClass::status() +{ + return WiFiSTAClass::_status; +} + +/** + * Return the current SSID associated with the network + * @return SSID + */ +String WiFiSTAClass::SSID() const +{ + wifi_config_t conf; + esp_wifi_get_config(WIFI_IF_STA, &conf); + return String(reinterpret_cast(conf.sta.ssid)); +} + +/** + * Return the current pre shared key associated with the network + * @return psk string + */ +String WiFiSTAClass::psk() const +{ + wifi_config_t conf; + esp_wifi_get_config(WIFI_IF_STA, &conf); + return String(reinterpret_cast(conf.sta.password)); +} + +/** + * Return the current bssid / mac associated with the network if configured + * @return bssid uint8_t * + */ +uint8_t* WiFiSTAClass::BSSID(void) +{ + static uint8_t bssid[6]; + wifi_config_t conf; + esp_wifi_get_config(WIFI_IF_STA, &conf); + memcpy(bssid, conf.sta.bssid, 6); + return reinterpret_cast(bssid); +} + +/** + * Return the current bssid / mac associated with the network if configured + * @return String bssid mac + */ +String WiFiSTAClass::BSSIDstr(void) +{ + char mac[18] = { 0 }; + wifi_config_t conf; + esp_wifi_get_config(WIFI_IF_STA, &conf); + sprintf(mac, "%02X:%02X:%02X:%02X:%02X:%02X", conf.sta.bssid[0], conf.sta.bssid[1], conf.sta.bssid[2], conf.sta.bssid[3], conf.sta.bssid[4], conf.sta.bssid[5]); + return String(mac); +} + +/** + * Return the current network RSSI. + * @return RSSI value + */ +int32_t WiFiSTAClass::RSSI(void) +{ + return 0;//wifi_station_get_rssi(); +} diff --git a/libraries/WiFi/src/WiFiSTA.h b/libraries/WiFi/src/WiFiSTA.h new file mode 100644 index 00000000..587eaefb --- /dev/null +++ b/libraries/WiFi/src/WiFiSTA.h @@ -0,0 +1,85 @@ +/* + ESP8266WiFiSTA.h - esp8266 Wifi support. + Based on WiFi.h from Ardiono WiFi shield library. + Copyright (c) 2011-2014 Arduino. All right reserved. + Modified by Ivan Grokhotkov, December 2014 + Reworked by Markus Sattler, December 2015 + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef ESP32WIFISTA_H_ +#define ESP32WIFISTA_H_ + + +#include "WiFiType.h" +#include "WiFiGeneric.h" + + +class WiFiSTAClass +{ + // ---------------------------------------------------------------------------------------------- + // ---------------------------------------- STA function ---------------------------------------- + // ---------------------------------------------------------------------------------------------- + +public: + + wl_status_t begin(const char* ssid, const char *passphrase = NULL, int32_t channel = 0, const uint8_t* bssid = NULL, bool connect = true); + wl_status_t begin(char* ssid, char *passphrase = NULL, int32_t channel = 0, const uint8_t* bssid = NULL, bool connect = true); + wl_status_t begin(); + + bool config(IPAddress local_ip, IPAddress gateway, IPAddress subnet, IPAddress dns1 = (uint32_t)0x00000000, IPAddress dns2 = (uint32_t)0x00000000); + + bool reconnect(); + bool disconnect(bool wifioff = false); + + bool isConnected(); + + bool setAutoConnect(bool autoConnect); + bool getAutoConnect(); + + bool setAutoReconnect(bool autoReconnect); + + uint8_t waitForConnectResult(); + + // STA network info + IPAddress localIP(); + + uint8_t * macAddress(uint8_t* mac); + String macAddress(); + + IPAddress subnetMask(); + IPAddress gatewayIP(); + IPAddress dnsIP(uint8_t dns_no = 0); + + // STA WiFi info + wl_status_t status(); + String SSID() const; + String psk() const; + + uint8_t * BSSID(); + String BSSIDstr(); + + int32_t RSSI(); + + static void _setStatus(wl_status_t status); +protected: + static wl_status_t _status; + static bool _useStaticIp; + +}; + + +#endif /* ESP32WIFISTA_H_ */ diff --git a/libraries/WiFi/src/WiFiScan.cpp b/libraries/WiFi/src/WiFiScan.cpp new file mode 100644 index 00000000..2e96bf91 --- /dev/null +++ b/libraries/WiFi/src/WiFiScan.cpp @@ -0,0 +1,268 @@ +/* + ESP8266WiFiScan.cpp - WiFi library for esp8266 + + Copyright (c) 2014 Ivan Grokhotkov. All rights reserved. + This file is part of the esp8266 core for Arduino environment. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Reworked on 28 Dec 2015 by Markus Sattler + + */ + +#include "WiFi.h" +#include "WiFiGeneric.h" +#include "WiFiScan.h" + +extern "C" { +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "lwip/err.h" +} + +bool WiFiScanClass::_scanAsync = false; +bool WiFiScanClass::_scanStarted = false; +bool WiFiScanClass::_scanComplete = false; + +uint16_t WiFiScanClass::_scanCount = 0; +void* WiFiScanClass::_scanResult = 0; + +/** + * Start scan WiFi networks available + * @param async run in async mode + * @param show_hidden show hidden networks + * @return Number of discovered networks + */ +int8_t WiFiScanClass::scanNetworks(bool async, bool show_hidden) +{ + if(WiFiScanClass::_scanStarted) { + return WIFI_SCAN_RUNNING; + } + + WiFiScanClass::_scanAsync = async; + + WiFi.enableSTA(true); + + scanDelete(); + + wifi_scan_config_t config; + config.ssid = 0; + config.bssid = 0; + config.channel = 0; + config.show_hidden = show_hidden; + if(esp_wifi_scan_start(&config, WiFiScanClass::_scanAsync) == ESP_OK) { + WiFiScanClass::_scanComplete = false; + WiFiScanClass::_scanStarted = true; + + if(WiFiScanClass::_scanAsync) { + return WIFI_SCAN_RUNNING; + } + while(!(WiFiScanClass::_scanComplete)) { + delay(10); + } + return WiFiScanClass::_scanCount; + } else { + return WIFI_SCAN_FAILED; + } + +} + + +/** + * private + * scan callback + * @param result void *arg + * @param status STATUS + */ +void WiFiScanClass::_scanDone() +{ + WiFiScanClass::_scanComplete = true; + WiFiScanClass::_scanStarted = false; + esp_wifi_get_ap_num(&(WiFiScanClass::_scanCount)); + if(WiFiScanClass::_scanCount) { + WiFiScanClass::_scanResult = new wifi_ap_list_t[WiFiScanClass::_scanCount]; + if(WiFiScanClass::_scanResult) { + esp_wifi_get_ap_list(&(WiFiScanClass::_scanCount), (wifi_ap_list_t*)_scanResult); + } else { + //no memory + WiFiScanClass::_scanCount = 0; + } + } +} + +/** + * + * @param i specify from which network item want to get the information + * @return bss_info * + */ +void * WiFiScanClass::_getScanInfoByIndex(int i) +{ + if(!WiFiScanClass::_scanResult || (size_t) i > WiFiScanClass::_scanCount) { + return 0; + } + return reinterpret_cast(WiFiScanClass::_scanResult) + i; +} + +/** + * called to get the scan state in Async mode + * @return scan result or status + * -1 if scan not fin + * -2 if scan not triggered + */ +int8_t WiFiScanClass::scanComplete() +{ + + if(_scanStarted) { + return WIFI_SCAN_RUNNING; + } + + if(_scanComplete) { + return WiFiScanClass::_scanCount; + } + + return WIFI_SCAN_FAILED; +} + +/** + * delete last scan result from RAM + */ +void WiFiScanClass::scanDelete() +{ + if(WiFiScanClass::_scanResult) { + delete[] reinterpret_cast(WiFiScanClass::_scanResult); + WiFiScanClass::_scanResult = 0; + WiFiScanClass::_scanCount = 0; + } + _scanComplete = false; +} + + +/** + * loads all infos from a scanned wifi in to the ptr parameters + * @param networkItem uint8_t + * @param ssid const char** + * @param encryptionType uint8_t * + * @param RSSI int32_t * + * @param BSSID uint8_t ** + * @param channel int32_t * + * @return (true if ok) + */ +bool WiFiScanClass::getNetworkInfo(uint8_t i, String &ssid, uint8_t &encType, int32_t &rssi, uint8_t* &bssid, int32_t &channel) +{ + wifi_ap_list_t* it = reinterpret_cast(_getScanInfoByIndex(i)); + if(!it) { + return 0; + } + ssid = (const char*) it->ssid; + encType = it->authmode; + rssi = it->rssi; + bssid = it->bssid; + channel = it->primary; + return true; +} + + +/** + * Return the SSID discovered during the network scan. + * @param i specify from which network item want to get the information + * @return ssid string of the specified item on the networks scanned list + */ +String WiFiScanClass::SSID(uint8_t i) +{ + wifi_ap_list_t* it = reinterpret_cast(_getScanInfoByIndex(i)); + if(!it) { + return 0; + } + return String(reinterpret_cast(it->ssid)); +} + + +/** + * Return the encryption type of the networks discovered during the scanNetworks + * @param i specify from which network item want to get the information + * @return encryption type (enum wl_enc_type) of the specified item on the networks scanned list + */ +wifi_auth_mode_t WiFiScanClass::encryptionType(uint8_t i) +{ + wifi_ap_list_t* it = reinterpret_cast(_getScanInfoByIndex(i)); + if(!it) { + return WIFI_AUTH_OPEN; + } + return it->authmode; +} + +/** + * Return the RSSI of the networks discovered during the scanNetworks + * @param i specify from which network item want to get the information + * @return signed value of RSSI of the specified item on the networks scanned list + */ +int32_t WiFiScanClass::RSSI(uint8_t i) +{ + wifi_ap_list_t* it = reinterpret_cast(_getScanInfoByIndex(i)); + if(!it) { + return 0; + } + return it->rssi; +} + + +/** + * return MAC / BSSID of scanned wifi + * @param i specify from which network item want to get the information + * @return uint8_t * MAC / BSSID of scanned wifi + */ +uint8_t * WiFiScanClass::BSSID(uint8_t i) +{ + wifi_ap_list_t* it = reinterpret_cast(_getScanInfoByIndex(i)); + if(!it) { + return 0; + } + return it->bssid; +} + +/** + * return MAC / BSSID of scanned wifi + * @param i specify from which network item want to get the information + * @return String MAC / BSSID of scanned wifi + */ +String WiFiScanClass::BSSIDstr(uint8_t i) +{ + char mac[18] = { 0 }; + wifi_ap_list_t* it = reinterpret_cast(_getScanInfoByIndex(i)); + if(!it) { + return String(""); + } + sprintf(mac, "%02X:%02X:%02X:%02X:%02X:%02X", it->bssid[0], it->bssid[1], it->bssid[2], it->bssid[3], it->bssid[4], it->bssid[5]); + return String(mac); +} + +int32_t WiFiScanClass::channel(uint8_t i) +{ + wifi_ap_list_t* it = reinterpret_cast(_getScanInfoByIndex(i)); + if(!it) { + return 0; + } + return it->primary; +} + diff --git a/libraries/WiFi/src/WiFiScan.h b/libraries/WiFi/src/WiFiScan.h new file mode 100644 index 00000000..ec89f0c9 --- /dev/null +++ b/libraries/WiFi/src/WiFiScan.h @@ -0,0 +1,64 @@ +/* + ESP8266WiFiScan.h - esp8266 Wifi support. + Based on WiFi.h from Ardiono WiFi shield library. + Copyright (c) 2011-2014 Arduino. All right reserved. + Modified by Ivan Grokhotkov, December 2014 + Reworked by Markus Sattler, December 2015 + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef ESP32WIFISCAN_H_ +#define ESP32WIFISCAN_H_ + +#include "WiFiType.h" +#include "WiFiGeneric.h" + +class WiFiScanClass +{ + +public: + + int8_t scanNetworks(bool async = false, bool show_hidden = false); + + int8_t scanComplete(); + void scanDelete(); + + // scan result + bool getNetworkInfo(uint8_t networkItem, String &ssid, uint8_t &encryptionType, int32_t &RSSI, uint8_t* &BSSID, int32_t &channel); + + String SSID(uint8_t networkItem); + wifi_auth_mode_t encryptionType(uint8_t networkItem); + int32_t RSSI(uint8_t networkItem); + uint8_t * BSSID(uint8_t networkItem); + String BSSIDstr(uint8_t networkItem); + int32_t channel(uint8_t networkItem); + + static void _scanDone(); +protected: + + static bool _scanAsync; + static bool _scanStarted; + static bool _scanComplete; + + static uint16_t _scanCount; + static void* _scanResult; + + static void * _getScanInfoByIndex(int i); + +}; + + +#endif /* ESP32WIFISCAN_H_ */ diff --git a/libraries/WiFi/src/WiFiType.h b/libraries/WiFi/src/WiFiType.h new file mode 100644 index 00000000..c4b09106 --- /dev/null +++ b/libraries/WiFi/src/WiFiType.h @@ -0,0 +1,48 @@ +/* + ESP8266WiFiType.h - esp8266 Wifi support. + Copyright (c) 2011-2014 Arduino. All right reserved. + Modified by Ivan Grokhotkov, December 2014 + Reworked by Markus Sattler, December 2015 + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#ifndef ESP32WIFITYPE_H_ +#define ESP32WIFITYPE_H_ + +#define WIFI_SCAN_RUNNING (-1) +#define WIFI_SCAN_FAILED (-2) + +#define WiFiMode_t wifi_mode_t +#define WIFI_OFF WIFI_MODE_NULL +#define WIFI_STA WIFI_MODE_STA +#define WIFI_AP WIFI_MODE_AP +#define WIFI_AP_STA WIFI_MODE_APSTA + +#define WiFiEvent_t system_event_id_t + +typedef enum { + WL_NO_SHIELD = 255, // for compatibility with WiFi Shield library + WL_IDLE_STATUS = 0, + WL_NO_SSID_AVAIL = 1, + WL_SCAN_COMPLETED = 2, + WL_CONNECTED = 3, + WL_CONNECT_FAILED = 4, + WL_CONNECTION_LOST = 5, + WL_DISCONNECTED = 6 +} wl_status_t; + +#endif /* ESP32WIFITYPE_H_ */ diff --git a/libraries/Wire/keywords.txt b/libraries/Wire/keywords.txt new file mode 100644 index 00000000..3344011d --- /dev/null +++ b/libraries/Wire/keywords.txt @@ -0,0 +1,33 @@ +####################################### +# Syntax Coloring Map For Wire +####################################### + +####################################### +# Datatypes (KEYWORD1) +####################################### + +####################################### +# Methods and Functions (KEYWORD2) +####################################### + +begin KEYWORD2 +setClock KEYWORD2 +setClockStretchLimit KEYWORD2 +beginTransmission KEYWORD2 +endTransmission KEYWORD2 +requestFrom KEYWORD2 +send KEYWORD2 +receive KEYWORD2 +onReceive KEYWORD2 +onRequest KEYWORD2 + +####################################### +# Instances (KEYWORD2) +####################################### + +Wire KEYWORD2 + +####################################### +# Constants (LITERAL1) +####################################### + diff --git a/libraries/Wire/library.properties b/libraries/Wire/library.properties new file mode 100644 index 00000000..ef29154c --- /dev/null +++ b/libraries/Wire/library.properties @@ -0,0 +1,9 @@ +name=Wire +version=1.0 +author=Hristo Gochkov +maintainer=Hristo Gochkov +sentence=Allows the communication between devices or sensors connected via Two Wire Interface Bus. For esp8266 boards. +paragraph= +category=Signal Input/Output +url=http://arduino.cc/en/Reference/Wire +architectures=esp32 diff --git a/libraries/Wire/src/Wire.cpp b/libraries/Wire/src/Wire.cpp new file mode 100644 index 00000000..37b09c58 --- /dev/null +++ b/libraries/Wire/src/Wire.cpp @@ -0,0 +1,211 @@ +/* + TwoWire.cpp - TWI/I2C library for Arduino & Wiring + Copyright (c) 2006 Nicholas Zambetti. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Modified 2012 by Todd Krein (todd@krein.org) to implement repeated starts + Modified December 2014 by Ivan Grokhotkov (ivan@esp8266.com) - esp8266 support + Modified April 2015 by Hrsto Gochkov (ficeto@ficeto.com) - alternative esp8266 support +*/ + +extern "C" { +#include +#include +#include +} + +#include "esp32-hal-i2c.h" +#include "Wire.h" + +TwoWire::TwoWire(uint8_t bus_num) + :num(bus_num & 1) + ,sda(-1) + ,scl(-1) + ,i2c(NULL) + ,rxIndex(0) + ,rxLength(0) + ,txIndex(0) + ,txLength(0) + ,txAddress(0) + ,transmitting(0) +{} + +void TwoWire::begin(int sdaPin, int sclPin, uint32_t frequency) +{ + if(sdaPin < 0) { + if(num == 0) { + sdaPin = I2C0_DEFAULT_SDA_PIN; + } else { + return; + } + } + + if(sclPin < 0) { + if(num == 0) { + sclPin = I2C0_DEFAULT_SCL_PIN; + } else { + return; + } + } + + if(i2c == NULL) { + i2c = i2cInit(num, 0, false); + if(i2c == NULL) { + return; + } + } + + i2cSetFrequency(i2c, frequency); + + if(sda >= 0 && sda != sdaPin) { + i2cDetachSDA(i2c, sda); + } + + if(scl >= 0 && scl != sclPin) { + i2cDetachSCL(i2c, scl); + } + + sda = sdaPin; + scl = sclPin; + + i2cAttachSDA(i2c, sda); + i2cAttachSCL(i2c, scl); + + flush(); +} + +void TwoWire::setClock(uint32_t frequency) +{ + i2cSetFrequency(i2c, frequency); +} + +size_t TwoWire::requestFrom(uint8_t address, size_t size, bool sendStop) +{ + if(size > I2C_BUFFER_LENGTH) { + size = I2C_BUFFER_LENGTH; + } + size_t read = (i2cRead(i2c, address, false, rxBuffer, size, sendStop) == 0)?size:0; + rxIndex = 0; + rxLength = read; + return read; +} + +uint8_t TwoWire::endTransmission(uint8_t sendStop) +{ + int8_t ret = i2cWrite(i2c, txAddress, false, txBuffer, txLength, sendStop); + txIndex = 0; + txLength = 0; + transmitting = 0; + return ret; +} + +uint8_t TwoWire::requestFrom(uint8_t address, uint8_t quantity, uint8_t sendStop) +{ + return requestFrom(address, static_cast(quantity), static_cast(sendStop)); +} + +uint8_t TwoWire::requestFrom(uint8_t address, uint8_t quantity) +{ + return requestFrom(address, static_cast(quantity), true); +} + +uint8_t TwoWire::requestFrom(int address, int quantity) +{ + return requestFrom(static_cast(address), static_cast(quantity), true); +} + +uint8_t TwoWire::requestFrom(int address, int quantity, int sendStop) +{ + return requestFrom(static_cast(address), static_cast(quantity), static_cast(sendStop)); +} + +void TwoWire::beginTransmission(uint8_t address) +{ + transmitting = 1; + txAddress = address; + txIndex = 0; + txLength = 0; +} + +void TwoWire::beginTransmission(int address) +{ + beginTransmission((uint8_t)address); +} + +uint8_t TwoWire::endTransmission(void) +{ + return endTransmission(true); +} + +size_t TwoWire::write(uint8_t data) +{ + if(transmitting) { + if(txLength >= I2C_BUFFER_LENGTH) { + return 0; + } + txBuffer[txIndex] = data; + ++txIndex; + txLength = txIndex; + } + return 1; +} + +size_t TwoWire::write(const uint8_t *data, size_t quantity) +{ + if(transmitting) { + for(size_t i = 0; i < quantity; ++i) { + if(!write(data[i])) { + return i; + } + } + } + return quantity; +} + +int TwoWire::available(void) +{ + int result = rxLength - rxIndex; + return result; +} + +int TwoWire::read(void) +{ + int value = -1; + if(rxIndex < rxLength) { + value = rxBuffer[rxIndex]; + ++rxIndex; + } + return value; +} + +int TwoWire::peek(void) +{ + int value = -1; + if(rxIndex < rxLength) { + value = rxBuffer[rxIndex]; + } + return value; +} + +void TwoWire::flush(void) +{ + rxIndex = 0; + rxLength = 0; + txIndex = 0; + txLength = 0; +} + +TwoWire Wire = TwoWire(0); diff --git a/libraries/Wire/src/Wire.h b/libraries/Wire/src/Wire.h new file mode 100644 index 00000000..f54ac965 --- /dev/null +++ b/libraries/Wire/src/Wire.h @@ -0,0 +1,97 @@ +/* + TwoWire.h - TWI/I2C library for Arduino & Wiring + Copyright (c) 2006 Nicholas Zambetti. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Modified 2012 by Todd Krein (todd@krein.org) to implement repeated starts + Modified December 2014 by Ivan Grokhotkov (ivan@esp8266.com) - esp8266 support + Modified April 2015 by Hrsto Gochkov (ficeto@ficeto.com) - alternative esp8266 support +*/ + +#ifndef TwoWire_h +#define TwoWire_h + +#include +#include "freertos/FreeRTOS.h" +#include "freertos/queue.h" + +#define I2C_BUFFER_LENGTH 128 +#define I2C0_DEFAULT_SDA_PIN 21 +#define I2C0_DEFAULT_SCL_PIN 22 + +class TwoWire +{ +protected: + uint8_t num; + int8_t sda; + int8_t scl; + i2c_t * i2c; + + uint8_t rxBuffer[I2C_BUFFER_LENGTH]; + uint16_t rxIndex; + uint16_t rxLength; + + uint8_t txBuffer[I2C_BUFFER_LENGTH]; + uint16_t txIndex; + uint16_t txLength; + uint8_t txAddress; + + uint8_t transmitting; + +public: + TwoWire(uint8_t bus_num); + void begin(int sda=-1, int scl=-1, uint32_t frequency=100000); + void setClock(uint32_t); + void beginTransmission(uint8_t); + void beginTransmission(int); + uint8_t endTransmission(void); + uint8_t endTransmission(uint8_t); + size_t requestFrom(uint8_t address, size_t size, bool sendStop); + + uint8_t requestFrom(uint8_t, uint8_t); + uint8_t requestFrom(uint8_t, uint8_t, uint8_t); + uint8_t requestFrom(int, int); + uint8_t requestFrom(int, int, int); + + size_t write(uint8_t); + size_t write(const uint8_t *, size_t); + int available(void); + int read(void); + int peek(void); + void flush(void); + + inline size_t write(unsigned long n) + { + return write((uint8_t)n); + } + inline size_t write(long n) + { + return write((uint8_t)n); + } + inline size_t write(unsigned int n) + { + return write((uint8_t)n); + } + inline size_t write(int n) + { + return write((uint8_t)n); + } +}; + +extern TwoWire Wire; + +#endif + diff --git a/package/package_esp32_index.template.json b/package/package_esp32_index.template.json new file mode 100644 index 00000000..bc9f4057 --- /dev/null +++ b/package/package_esp32_index.template.json @@ -0,0 +1,76 @@ +{ + "packages": [ + { + "name": "esp32", + "maintainer": "Espressif Systems", + "websiteURL": "https://github.com/espressif/esp32-arduino", + "email": "hristo@espressif.com", + "help": { + "online": "http://esp32.com" + }, + "platforms": [ + { + "name": "esp32", + "architecture": "esp32", + "version": "", + "category": "ESP32", + "url": "", + "archiveFileName": "", + "checksum": "", + "size": "", + "help": { + "online": "" + }, + "boards": [ + { + "name": "ESP32 Dev Module" + } + ], + "toolsDependencies": [ + { + "packager": "esp32", + "name": "xtensa-esp32-elf-gcc", + "version": "1.22.0-59" + } + ] + } + ], + "tools": [ + { + "name": "xtensa-esp32-elf-gcc", + "version": "1.22.0-59", + "systems": [ + { + "host": "i686-mingw32", + "url": "https://dl.espressif.com/dl/xtensa-esp32-elf-win32-1.22.0-59.zip", + "archiveFileName": "xtensa-esp32-elf-win32-1.22.0-59.zip", + "checksum": "SHA-256:10476b9c11a7a90f40883413ddfb409f505b20692e316c4e597c4c175b4be09c", + "size": "153527527" + }, + { + "host": "x86_64-apple-darwin", + "url": "https://dl.espressif.com/dl/xtensa-esp32-elf-osx-1.22.0-59.tar.gz", + "archiveFileName": "xtensa-esp32-elf-osx-1.22.0-59.tar.gz", + "checksum": "SHA-256:0cf150193997bd1355e0f49d3d49711730035257bc1aee1eaaad619e56b9e4e6", + "size": "35385382" + }, + { + "host": "x86_64-pc-linux-gnu", + "url": "https://dl.espressif.com/dl/xtensa-esp32-elf-linux64-1.22.0-59.tar.gz", + "archiveFileName": "xtensa-esp32-elf-linux64-1.22.0-59.tar.gz", + "checksum": "SHA-256:46f057fbd8b320889a26167daf325038912096d09940b2a95489db92431473b7", + "size": "30262903" + }, + { + "host": "i686-pc-linux-gnu", + "url": "https://dl.espressif.com/dl/xtensa-esp32-elf-linux32-1.22.0-59.tar.gz", + "archiveFileName": "xtensa-esp32-elf-linux32-1.22.0-59.tar.gz", + "checksum": "SHA-256:b24817819f0078fb05895a640e806e0aca9aa96b47b80d2390ac8e2d9ddc955a", + "size": "32734156" + } + ] + } + ] + } + ] +} diff --git a/platform.txt b/platform.txt new file mode 100644 index 00000000..96415179 --- /dev/null +++ b/platform.txt @@ -0,0 +1,97 @@ + +name=ESP32 Arduino +version=0.0.1 + +runtime.tools.xtensa-esp32-elf-gcc.path={runtime.platform.path}/tools/xtensa-esp32-elf +runtime.tools.esptool.path={runtime.platform.path}/tools/esptool.py + +compiler.warning_flags=-w +compiler.warning_flags.none=-w +compiler.warning_flags.default= +compiler.warning_flags.more=-Wall +compiler.warning_flags.all=-Wall -Wextra + +compiler.path={runtime.tools.xtensa-esp32-elf-gcc.path}/bin/ +compiler.sdk.path={runtime.platform.path}/tools/sdk +compiler.cpreprocessor.flags=-DESP_PLATFORM -DMBEDTLS_CONFIG_FILE='"mbedtls/esp_config.h"' -DHAVE_CONFIG_H "-I{compiler.sdk.path}/include/config" "-I{compiler.sdk.path}/include/bt" "-I{compiler.sdk.path}/include/driver" "-I{compiler.sdk.path}/include/esp32" "-I{compiler.sdk.path}/include/freertos" "-I{compiler.sdk.path}/include/log" "-I{compiler.sdk.path}/include/newlib" "-I{compiler.sdk.path}/include/nvs_flash" "-I{compiler.sdk.path}/include/spi_flash" "-I{compiler.sdk.path}/include/tcpip_adapter" "-I{compiler.sdk.path}/include/expat" "-I{compiler.sdk.path}/include/json" "-I{compiler.sdk.path}/include/mbedtls" "-I{compiler.sdk.path}/include/nghttp" "-I{compiler.sdk.path}/include/lwip" + +compiler.c.cmd=xtensa-esp32-elf-gcc +compiler.c.flags=-c {compiler.warning_flags} -Os -g3 -Wpointer-arith -Wno-error=unused-function -Wno-error=unused-but-set-variable -Wno-error=unused-variable -ffunction-sections -fdata-sections -mlongcalls -nostdlib -MMD -std=gnu99 -fstrict-volatile-bitfields + +compiler.cpp.cmd=xtensa-esp32-elf-g++ +compiler.cpp.flags=-c {compiler.warning_flags} -Os -g3 -Wpointer-arith -Wno-error=unused-function -Wno-error=unused-but-set-variable -Wno-error=unused-variable -fno-rtti -ffunction-sections -fdata-sections -mlongcalls -nostdlib -MMD -std=gnu++11 -fno-exceptions -fstrict-volatile-bitfields + +compiler.S.cmd=xtensa-esp32-elf-gcc +compiler.S.flags=-c -g3 -x assembler-with-cpp -MMD -mlongcalls + +compiler.c.elf.cmd=xtensa-esp32-elf-gcc +compiler.c.elf.flags="-L{compiler.sdk.path}/lib" "-L{compiler.sdk.path}/ld" -nostdlib -T esp32_out.ld -T esp32.common.ld -T esp32.rom.ld -T esp32.peripherals.ld -u call_user_start_cpu0 -Wl,--gc-sections -Wl,-static -Wl,--undefined=uxTopUsedPriority +compiler.c.elf.libs=-lgcc -lc -lm -lhal -lcore -lnet80211 -lphy -lrtc -lpp -lwpa -lsmartconfig -lbtdm_app -lbt -ldriver -lesp32 -lcrypto -lexpat -lfreertos -ljson -llog -llwip -lmbedtls -lnghttp -lnvs_flash -lspi_flash -ltcpip_adapter + +compiler.as.cmd=xtensa-esp32-elf-as + +compiler.ar.cmd=xtensa-esp32-elf-ar +compiler.ar.flags=cru + +compiler.elf2hex.cmd=esptool.py +compiler.elf2hex.flags= + +compiler.size.cmd=xtensa-esp32-elf-size + +compiler.python.cmd=python +compiler.python.cmd.windows=python.exe + +# This can be overriden in boards.txt +build.extra_flags=-DESP32 + +# These can be overridden in platform.local.txt +compiler.c.extra_flags= +compiler.c.elf.extra_flags= +compiler.S.extra_flags= +compiler.cpp.extra_flags= +compiler.ar.extra_flags= +compiler.objcopy.eep.extra_flags= +compiler.elf2hex.extra_flags= + +## Compile c files +recipe.c.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.cpreprocessor.flags} {compiler.c.flags} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.c.extra_flags} {build.extra_flags} {includes} "{source_file}" -o "{object_file}" + +## Compile c++ files +recipe.cpp.o.pattern="{compiler.path}{compiler.cpp.cmd}" {compiler.cpreprocessor.flags} {compiler.cpp.flags} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.cpp.extra_flags} {build.extra_flags} {includes} "{source_file}" -o "{object_file}" + +## Compile S files +recipe.S.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.cpreprocessor.flags} {compiler.S.flags} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.c.extra_flags} {build.extra_flags} {includes} "{source_file}" -o "{object_file}" + +## Create archives +recipe.ar.pattern="{compiler.path}{compiler.ar.cmd}" {compiler.ar.flags} {compiler.ar.extra_flags} "{build.path}/arduino.ar" "{object_file}" + +## Combine gc-sections, archives, and objects +recipe.c.combine.pattern="{compiler.path}{compiler.c.elf.cmd}" {compiler.c.elf.flags} {compiler.c.elf.extra_flags} -Wl,--start-group {object_files} "{build.path}/arduino.ar" {compiler.c.elf.libs} -Wl,--end-group -o "{build.path}/{build.project_name}.elf" + +## Create eeprom +recipe.objcopy.eep.pattern= + +## Create hex +recipe.objcopy.hex.pattern="{compiler.python.cmd}" "{runtime.platform.path}/tools/esptool.py" --chip esp32 elf2image --flash_mode "{build.flash_mode}" --flash_freq "{build.flash_freq}" -o "{build.path}/{build.project_name}.bin" "{build.path}/{build.project_name}.elf" + +## Save hex +recipe.output.tmp_file={build.project_name}.bin +recipe.output.save_file={build.project_name}.{build.variant}.bin + +## Compute size +recipe.size.pattern="{compiler.path}{compiler.size.cmd}" -A "{build.path}/{build.project_name}.elf" +recipe.size.regex=^(?:\.iram0\.text|\.dram0\.text|\.flash\.text|\.dram0\.data|\.flash\.rodata|)\s+([0-9]+).* +recipe.size.regex.data=^(?:\.dram0\.data|\.flash\.rodata|\.dram0\.bss)\s+([0-9]+).* + +# ------------------------------ + +tools.esptool.cmd=python +tools.esptool.cmd.windows=python.exe +tools.esptool.path={runtime.platform.path}/tools/esptool.py +tools.esptool.network_cmd=python +tools.esptool.network_cmd.windows=python.exe + +tools.esptool.upload.protocol=esp32 +tools.esptool.upload.params.verbose= +tools.esptool.upload.params.quiet= +tools.esptool.upload.pattern="{cmd}" "{path}" --chip esp32 --port "{serial.port}" --baud {upload.speed} write_flash -z --flash_freq {build.flash_freq} --flash_mode {build.flash_mode} 0x1000 "{runtime.platform.path}/tools/sdk/bin/bootloader.bin" 0x4000 "{runtime.platform.path}/tools/sdk/bin/partitions_singleapp.bin" 0x10000 "{build.path}/{build.project_name}.bin" diff --git a/programmers.txt b/programmers.txt new file mode 100644 index 00000000..e69de29b diff --git a/tools/esptool.py b/tools/esptool.py new file mode 100755 index 00000000..42033cee --- /dev/null +++ b/tools/esptool.py @@ -0,0 +1,1816 @@ +#!/usr/bin/env python +# NB: Before sending a PR to change the above line to '#!/usr/bin/env python2', please read https://github.com/themadinventor/esptool/issues/21 +# +# ESP8266 & ESP32 ROM Bootloader Utility +# https://github.com/themadinventor/esptool +# +# Copyright (C) 2014-2016 Fredrik Ahlberg, Angus Gratton, Espressif Systems (Shanghai) PTE LTD, other contributors as noted. +# +# This program is free software; you can redistribute it and/or modify it under +# the terms of the GNU General Public License as published by the Free Software +# Foundation; either version 2 of the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +# FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License along with +# this program; if not, write to the Free Software Foundation, Inc., 51 Franklin +# Street, Fifth Floor, Boston, MA 02110-1301 USA. + +import argparse +import hashlib +import inspect +import os +import serial +import struct +import sys +import time +import base64 +import zlib + +__version__ = "2.0-dev" + + +MAX_UINT32 = 0xffffffff +MAX_UINT24 = 0xffffff + + +def check_supported_function(func, check_func): + """ + Decorator implementation that wraps a check around an ESPLoader + bootloader function to check if it's supported. + + This is used to capture the multidimensional differences in + functionality between the ESP8266 & ESP32 ROM loaders, and the + software stub that runs on both. Not possible to do this cleanly + via inheritance alone. + """ + def inner(*args, **kwargs): + obj = args[0] + if check_func(obj): + return func(*args, **kwargs) + else: + raise NotImplementedInROMError(obj) + return inner + + +def stub_function_only(func): + """ Attribute for a function only supported in the software stub loader """ + return check_supported_function(func, lambda o: o.IS_STUB) + + +def stub_and_esp32_function_only(func): + """ Attribute for a function only supported by software stubs or ESP32 ROM """ + return check_supported_function(func, lambda o: o.IS_STUB or o.CHIP_NAME == "ESP32") + + +def esp8266_function_only(func): + """ Attribute for a function only supported on ESP8266 """ + return check_supported_function(func, lambda o: o.CHIP_NAME == "ESP8266") + + +class ESPLoader(object): + """ Base class providing access to ESP ROM & softtware stub bootloaders. + Subclasses provide ESP8266 & ESP32 specific functionality. + + Don't instantiate this base class directly, either instantiate a subclass or + call ESPLoader.detect_chip() which will interrogate the chip and return the + appropriate subclass instance. + + """ + CHIP_NAME = "Espressif device" + IS_STUB = False + + DEFAULT_PORT = "/dev/ttyUSB0" + + # Commands supported by ESP8266 ROM bootloader + ESP_FLASH_BEGIN = 0x02 + ESP_FLASH_DATA = 0x03 + ESP_FLASH_END = 0x04 + ESP_MEM_BEGIN = 0x05 + ESP_MEM_END = 0x06 + ESP_MEM_DATA = 0x07 + ESP_SYNC = 0x08 + ESP_WRITE_REG = 0x09 + ESP_READ_REG = 0x0a + + # Some comands supported by ESP32 ROM bootloader (or -8266 w/ stub) + ESP_SPI_SET_PARAMS = 0x0B + ESP_SPI_ATTACH = 0x0D + + ESP_CHANGE_BAUDRATE = 0x0F + ESP_FLASH_DEFL_BEGIN = 0x10 + ESP_FLASH_DEFL_DATA = 0x11 + ESP_FLASH_DEFL_END = 0x12 + ESP_SPI_FLASH_MD5 = 0x13 + + # Some commands supported by stub only + ESP_ERASE_FLASH = 0xD0 + ESP_ERASE_REGION = 0xD1 + ESP_READ_FLASH = 0xD2 + ESP_GET_FLASH_ID = 0xD3 + + # Maximum block sized for RAM and Flash writes, respectively. + ESP_RAM_BLOCK = 0x1800 + ESP_FLASH_BLOCK = 0x400 + + FLASH_WRITE_SIZE = ESP_FLASH_BLOCK + + # Default baudrate. The ROM auto-bauds, so we can use more or less whatever we want. + ESP_ROM_BAUD = 115200 + + # First byte of the application image + ESP_IMAGE_MAGIC = 0xe9 + + # Initial state for the checksum routine + ESP_CHECKSUM_MAGIC = 0xef + + # Flash sector size, minimum unit of erase. + ESP_FLASH_SECTOR = 0x1000 + + UART_DATA_REG_ADDR = 0x60000078 + + # SPI peripheral "command" bitmasks + SPI_CMD_READ_ID = 0x10000000 + + # Memory addresses + IROM_MAP_START = 0x40200000 + IROM_MAP_END = 0x40300000 + + # The number of bytes in the response that signify command status + STATUS_BYTES_LENGTH = 2 + + def __init__(self, port=DEFAULT_PORT, baud=ESP_ROM_BAUD, do_connect=True): + """Base constructor for ESPLoader bootloader interaction + + Don't call this constructor, either instantiate ESP8266ROM + or ESP32ROM, or use ESPLoader.detect_chip(). + + This base class has all of the instance methods for bootloader + functionality supported across various chips & stub + loaders. Subclasses replace the functions they don't support + with ones which throw NotImplementedInROMError(). + + """ + if isinstance(port, serial.Serial): + self._port = port + else: + self._port = serial.Serial(port) + self._slip_reader = slip_reader(self._port) + # setting baud rate in a separate step is a workaround for + # CH341 driver on some Linux versions (this opens at 9600 then + # sets), shouldn't matter for other platforms/drivers. See + # https://github.com/themadinventor/esptool/issues/44#issuecomment-107094446 + self._port.baudrate = baud + if do_connect: + self.connect() + + @staticmethod + def detect_chip(port=DEFAULT_PORT, baud=ESP_ROM_BAUD): + """Use serial access to detect the chip type. + + We use the UART's datecode register for this, it's mapped at + the same address on ESP8266 & ESP32 so we can use one + memory read and compare to the datecode register for each chip + type. + + """ + detect_port = ESPLoader(port, baud, True) + sys.stdout.write('Detecting chip type... ') + date_reg = detect_port.read_reg(ESPLoader.UART_DATA_REG_ADDR) + + for cls in [ESP8266ROM, ESP32ROM]: + if date_reg == cls.DATE_REG_VALUE: + # don't connect a second time + inst = cls(detect_port._port, baud, False) + print '%s' % inst.CHIP_NAME + return inst + print '' + raise FatalError("Unexpected UART datecode value 0x%08x. Failed to autodetect chip type." % date_reg) + + """ Read a SLIP packet from the serial port """ + def read(self): + r = self._slip_reader.next() + return r + + """ Write bytes to the serial port while performing SLIP escaping """ + def write(self, packet): + buf = '\xc0' \ + + (packet.replace('\xdb','\xdb\xdd').replace('\xc0','\xdb\xdc')) \ + + '\xc0' + self._port.write(buf) + + """ Calculate checksum of a blob, as it is defined by the ROM """ + @staticmethod + def checksum(data, state=ESP_CHECKSUM_MAGIC): + for b in data: + state ^= ord(b) + return state + + """ Send a request and read the response """ + def command(self, op=None, data="", chk=0): + if op is not None: + pkt = struct.pack(' self.STATUS_BYTES_LENGTH: + return data[:-self.STATUS_BYTES_LENGTH] + else: # otherwise, just return the 'val' field which comes from the reply header (this is used by read_reg) + return val + + def flush_input(self): + self._port.flushInput() + self._slip_reader = slip_reader(self._port) + + def sync(self): + """ Perform a connection test """ + self.command(self.ESP_SYNC, '\x07\x07\x12\x20' + 32 * '\x55') + for i in xrange(7): + self.command() + + def connect(self): + """ Try connecting repeatedly until successful, or giving up """ + print 'Connecting...' + + for _ in xrange(4): + # issue reset-to-bootloader: + # RTS = either CH_PD or nRESET (both active low = chip in reset) + # DTR = GPIO0 (active low = boot to flasher) + self._port.setDTR(False) + self._port.setRTS(True) + time.sleep(0.05) + self._port.setDTR(True) + self._port.setRTS(False) + time.sleep(0.05) + self._port.setDTR(False) + + # worst-case latency timer should be 255ms (probably <20ms) + self._port.timeout = 0.3 + last_exception = None + for _ in xrange(4): + try: + self.flush_input() + self._port.flushOutput() + self.sync() + self._port.timeout = 5 + return + except FatalError as e: + last_exception = e + time.sleep(0.05) + raise FatalError('Failed to connect to %s: %s' % (self.CHIP_NAME, last_exception)) + + """ Read memory address in target """ + def read_reg(self, addr): + # we don't call check_command here because read_reg() function is called + # when detecting chip type, and the way we check for success (STATUS_BYTES_LENGTH) is different + # for different chip types (!) + val, data = self.command(self.ESP_READ_REG, struct.pack(' length: + raise FatalError('Read more than expected') + digest_frame = self.read() + if len(digest_frame) != 16: + raise FatalError('Expected digest, got: %s' % hexify(digest_frame)) + expected_digest = hexify(digest_frame).upper() + digest = hashlib.md5(data).hexdigest().upper() + if digest != expected_digest: + raise FatalError('Digest mismatch: expected %s, got %s' % (expected_digest, digest)) + return data + + def flash_spi_attach(self,is_hspi,is_legacy): + """Send SPI attach command to enable the SPI flash pins + + ESP8266 ROM does this when you send flash_begin, ESP32 ROM + has it as a SPI command. + """ + # last 3 bytes in ESP_SPI_ATTACH argument are reserved values + arg = struct.pack('> 24) | ((id1 & MAX_UINT24) << 8) + + def read_mac(self): + """ Read MAC from OTP ROM """ + mac0 = self.read_reg(self.ESP_OTP_MAC0) + mac1 = self.read_reg(self.ESP_OTP_MAC1) + mac3 = self.read_reg(self.ESP_OTP_MAC3) + if (mac3 != 0): + oui = ((mac3 >> 16) & 0xff, (mac3 >> 8) & 0xff, mac3 & 0xff) + elif ((mac1 >> 16) & 0xff) == 0: + oui = (0x18, 0xfe, 0x34) + elif ((mac1 >> 16) & 0xff) == 1: + oui = (0xac, 0xd0, 0x74) + else: + raise FatalError("Unknown OUI") + return oui + ((mac1 >> 8) & 0xff, mac1 & 0xff, (mac0 >> 24) & 0xff) + + def get_erase_size(self, offset, size): + """ Calculate an erase size given a specific size in bytes. + + Provides a workaround for the bootloader erase bug.""" + + sectors_per_block = 16 + sector_size = self.ESP_FLASH_SECTOR + num_sectors = (size + sector_size - 1) / sector_size + start_sector = offset / sector_size + + head_sectors = sectors_per_block - (start_sector % sectors_per_block) + if num_sectors < head_sectors: + head_sectors = num_sectors + + if num_sectors < 2 * head_sectors: + return (num_sectors + 1) / 2 * sector_size + else: + return (num_sectors - head_sectors) * sector_size + + +class ESP8266StubLoader(ESP8266ROM): + """ Access class for ESP8266 stub loader, runs on top of ROM. + """ + FLASH_WRITE_SIZE = 8192 # matches MAX_WRITE_BLOCK in stub_loader.c + IS_STUB = True + + def __init__(self, rom_loader): + self._port = rom_loader._port + self.flush_input() # resets _slip_reader + +ESP8266ROM.STUB_CLASS = ESP8266StubLoader + + +class ESP32ROM(ESPLoader): + """Access class for ESP32 ROM bootloader + + """ + CHIP_NAME = "ESP32" + IS_STUB = False + + DATE_REG_VALUE = 0x15122500 + + IROM_MAP_START = 0x400d0000 + IROM_MAP_END = 0x40400000 + DROM_MAP_START = 0x3F400000 + DROM_MAP_END = 0x3F700000 + + # ESP32 uses a 4 byte status reply + STATUS_BYTES_LENGTH = 4 + + SPI_CMD_REG_ADDR = 0x60003000 + SPI_W0_REG_ADDR = 0x60003040 + + EFUSE_BASE = 0x6001a000 + + FLASH_SIZES = { + '1MB':0x00, + '2MB':0x10, + '4MB':0x20, + '8MB':0x30, + '16MB':0x40 + } + + def read_efuse(self, n): + """ Read the nth word of the ESP3x EFUSE region. """ + return self.read_reg(self.EFUSE_BASE + (4 * n)) + + def chip_id(self): + word16 = self.read_efuse(16) + word17 = self.read_efuse(17) + return ((word17 & MAX_UINT24) << 24) | (word16 >> 8) & MAX_UINT24 + + def read_mac(self): + """ Read MAC from EFUSE region """ + word16 = self.read_efuse(16) + word17 = self.read_efuse(17) + word18 = self.read_efuse(18) + word19 = self.read_efuse(19) + wifi_mac = (((word17 >> 16) & 0xff), ((word17 >> 8) & 0xff), ((word17 >> 0) & 0xff), + ((word16 >> 24) & 0xff), ((word16 >> 16) & 0xff), ((word16 >> 8) & 0xff)) + bt_mac = (((word19 >> 16) & 0xff), ((word19 >> 8) & 0xff), ((word19 >> 0) & 0xff), + ((word18 >> 24) & 0xff), ((word18 >> 16) & 0xff), ((word18 >> 8) & 0xff)) + return (wifi_mac,bt_mac) + + def get_erase_size(self, offset, size): + return size + + +class ESP32StubLoader(ESP32ROM): + """ Access class for ESP32 stub loader, runs on top of ROM. + """ + FLASH_WRITE_SIZE = 8192 # matches MAX_WRITE_BLOCK in stub_loader.c + STATUS_BYTES_LENGTH = 2 # same as ESP8266, different to ESP32 ROM + IS_STUB = True + + def __init__(self, rom_loader): + self._port = rom_loader._port + self.flush_input() # resets _slip_reader + +ESP32ROM.STUB_CLASS = ESP32StubLoader + + +class ESPBOOTLOADER(object): + """ These are constants related to software ESP bootloader, working with 'v2' image files """ + + # First byte of the "v2" application image + IMAGE_V2_MAGIC = 0xea + + # First 'segment' value in a "v2" application image, appears to be a constant version value? + IMAGE_V2_SEGMENT = 4 + + +def LoadFirmwareImage(chip, filename): + """ Load a firmware image. Can be for ESP8266 or ESP32. ESP8266 images will be examined to determine if they are + original ROM firmware images (ESPFirmwareImage) or "v2" OTA bootloader images. + + Returns a BaseFirmwareImage subclass, either ESPFirmwareImage (v1) or OTAFirmwareImage (v2). + """ + with open(filename, 'rb') as f: + if chip == 'esp32': + return ESP32FirmwareImage(f) + else: # Otherwise, ESP8266 so look at magic to determine the image type + magic = ord(f.read(1)) + f.seek(0) + if magic == ESPLoader.ESP_IMAGE_MAGIC: + return ESPFirmwareImage(f) + elif magic == ESPBOOTLOADER.IMAGE_V2_MAGIC: + return OTAFirmwareImage(f) + else: + raise FatalError("Invalid image magic number: %d" % magic) + + +class ImageSegment(object): + """ Wrapper class for a segment in an ESP image + (very similar to a section in an ELFImage also) """ + def __init__(self, addr, data, file_offs=None): + self.addr = addr + # pad all ImageSegments to at least 4 bytes length + pad_mod = len(data) % 4 + if pad_mod != 0: + data += "\x00" * (4 - pad_mod) + self.data = data + self.file_offs = file_offs + + def copy_with_new_addr(self, new_addr): + """ Return a new ImageSegment with same data, but mapped at + a new address. """ + return ImageSegment(new_addr, self.data, 0) + + def __repr__(self): + r = "len 0x%05x load 0x%08x" % (len(self.data), self.addr) + if self.file_offs is not None: + r += " file_offs 0x%08x" % (self.file_offs) + return r + + +class ELFSection(ImageSegment): + """ Wrapper class for a section in an ELF image, has a section + name as well as the common properties of an ImageSegment. """ + def __init__(self, name, addr, data): + super(ELFSection, self).__init__(addr, data) + self.name = name + + def __repr__(self): + return "%s %s" % (self.name, super(ELFSection, self).__repr__()) + + +class BaseFirmwareImage(object): + SEG_HEADER_LEN = 8 + + """ Base class with common firmware image functions """ + def __init__(self): + self.segments = [] + self.entrypoint = 0 + + def load_common_header(self, load_file, expected_magic): + (magic, segments, self.flash_mode, self.flash_size_freq, self.entrypoint) = struct.unpack(' 16: + raise FatalError('Invalid firmware image magic=%d segments=%d' % (magic, segments)) + return segments + + def load_segment(self, f, is_irom_segment=False): + """ Load the next segment from the image file """ + file_offs = f.tell() + (offset, size) = struct.unpack(' 0x40200000 or offset < 0x3ffe0000 or size > 65536: + print('WARNING: Suspicious segment 0x%x, length %d' % (offset, size)) + segment_data = f.read(size) + if len(segment_data) < size: + raise FatalError('End of file reading segment 0x%x, length %d (actual length %d)' % (offset, size, len(segment_data))) + segment = ImageSegment(offset, segment_data, file_offs) + self.segments.append(segment) + return segment + + def save_segment(self, f, segment, checksum=None): + """ Save the next segment to the image file, return next checksum value if provided """ + f.write(struct.pack(' 0: + if len(irom_segments) != 1: + raise FatalError('Found %d segments that could be irom0. Bad ELF file?' % len(irom_segments)) + return irom_segments[0] + return None + + def get_non_irom_segments(self): + irom_segment = self.get_irom_segment() + return [s for s in self.segments if s != irom_segment] + + +class ESPFirmwareImage(BaseFirmwareImage): + """ 'Version 1' firmware image, segments loaded directly by the ROM bootloader. """ + def __init__(self, load_file=None): + super(ESPFirmwareImage, self).__init__() + self.flash_mode = 0 + self.flash_size_freq = 0 + self.version = 1 + + if load_file is not None: + segments = self.load_common_header(load_file, ESPLoader.ESP_IMAGE_MAGIC) + + for _ in xrange(segments): + self.load_segment(load_file) + self.checksum = self.read_checksum(load_file) + + def default_output_name(self, input_file): + """ Derive a default output name from the ELF name. """ + return input_file + '-' + + def save(self, basename): + """ Save a set of V1 images for flashing. Parameter is a base filename. """ + # IROM data goes in its own plain binary file + irom_segment = self.get_irom_segment() + if irom_segment is not None: + with open("%s0x%05x.bin" % (basename, irom_segment.addr), "wb") as f: + f.write(irom_segment.data) + + # everything but IROM goes at 0x00000 in an image file + normal_segments = self.get_non_irom_segments() + with open("%s0x00000.bin" % basename, 'wb') as f: + self.write_common_header(f, normal_segments) + checksum = ESPLoader.ESP_CHECKSUM_MAGIC + for segment in self.segments: + checksum = self.save_segment(f, segment, checksum) + self.append_checksum(f, checksum) + + +class OTAFirmwareImage(BaseFirmwareImage): + """ 'Version 2' firmware image, segments loaded by software bootloader stub + (ie Espressif bootloader or rboot) + """ + def __init__(self, load_file=None): + super(OTAFirmwareImage, self).__init__() + self.version = 2 + if load_file is not None: + segments = self.load_common_header(load_file, ESPBOOTLOADER.IMAGE_V2_MAGIC) + if segments != ESPBOOTLOADER.IMAGE_V2_SEGMENT: + # segment count is not really segment count here, but we expect to see '4' + print 'Warning: V2 header has unexpected "segment" count %d (usually 4)' % segments + + # irom segment comes before the second header + # + # the file is saved in the image with a zero load address + # in the header, so we need to calculate a load address + irom_offs = load_file.tell() + irom_segment = self.load_segment(load_file, True) + irom_segment.addr = irom_offs + self.IROM_MAP_START + + first_flash_mode = self.flash_mode + first_flash_size_freq = self.flash_size_freq + first_entrypoint = self.entrypoint + # load the second header + self.load_common_header(load_file, ESPLoader.ESP_IMAGE_MAGIC) + (magic, segments, self.flash_mode, self.flash_size_freq, self.entrypoint) = struct.unpack(' 0: + null = ImageSegment(0, '\x00' * pad_len, f.tell()) + checksum = self.save_segment(f, null, checksum) + padding_segments += 1 + # verify that after the 8 byte header is added, were are at the correct offset relative to the segment's vaddr + assert (f.tell() + 8) % IROM_ALIGN == segment.addr % IROM_ALIGN + checksum = self.save_segment(f, segment, checksum) + self.append_checksum(f, checksum) + # kinda hacky: go back to the initial header and write the new segment count + # that includes padding segments. Luckily(?) this header is not checksummed + f.seek(1) + f.write(chr(len(self.segments) + padding_segments)) + + +class ELFFile(object): + SEC_TYPE_PROGBITS = 0x01 + SEC_TYPE_STRTAB = 0x03 + + def __init__(self, name): + # Load sections from the ELF file + self.name = name + with open(self.name, 'rb') as f: + self._read_elf_file(f) + + def get_section(self, section_name): + for s in self.sections: + if s.name == section_name: + return s + raise ValueError("No section %s in ELF file" % section_name) + + def _read_elf_file(self, f): + # read the ELF file header + LEN_FILE_HEADER = 0x34 + try: + (ident,_type,machine,_version, + self.entrypoint,_phoff,shoff,_flags, + _ehsize, _phentsize,_phnum,_shentsize, + _shnum,shstrndx) = struct.unpack("<16sHHLLLLLHHHHHH", f.read(LEN_FILE_HEADER)) + except struct.error as e: + raise FatalError("Failed to read a valid ELF header from %s: %s" % (self.name, e)) + + if ident[0] != '\x7f' or ident[1:4] != 'ELF': + raise FatalError("%s has invalid ELF magic header" % self.name) + if machine != 0x5e: + raise FatalError("%s does not appear to be an Xtensa ELF file. e_machine=%04x" % (self.name, machine)) + self._read_sections(f, shoff, shstrndx) + + def _read_sections(self, f, section_header_offs, shstrndx): + f.seek(section_header_offs) + section_header = f.read() + LEN_SEC_HEADER = 0x28 + if len(section_header) == 0: + raise FatalError("No section header found at offset %04x in ELF file." % section_header_offs) + if len(section_header) % LEN_SEC_HEADER != 0: + print 'WARNING: Unexpected ELF section header length %04x is not mod-%02x' % (len(section_header),LEN_SEC_HEADER) + + # walk through the section header and extract all sections + section_header_offsets = range(0, len(section_header), LEN_SEC_HEADER) + + def read_section_header(offs): + name_offs,sec_type,_flags,lma,sec_offs,size = struct.unpack_from(", ) or a single +# argument. + + +def load_ram(esp, args): + image = LoadFirmwareImage(esp, args.filename) + + print 'RAM boot...' + for (offset, size, data) in image.segments: + print 'Downloading %d bytes at %08x...' % (size, offset), + sys.stdout.flush() + esp.mem_begin(size, div_roundup(size, esp.ESP_RAM_BLOCK), esp.ESP_RAM_BLOCK, offset) + + seq = 0 + while len(data) > 0: + esp.mem_block(data[0:esp.ESP_RAM_BLOCK], seq) + data = data[esp.ESP_RAM_BLOCK:] + seq += 1 + print 'done!' + + print 'All segments done, executing at %08x' % image.entrypoint + esp.mem_finish(image.entrypoint) + + +def read_mem(esp, args): + print '0x%08x = 0x%08x' % (args.address, esp.read_reg(args.address)) + + +def write_mem(esp, args): + esp.write_reg(args.address, args.value, args.mask, 0) + print 'Wrote %08x, mask %08x to %08x' % (args.value, args.mask, args.address) + + +def dump_mem(esp, args): + f = file(args.filename, 'wb') + for i in xrange(args.size / 4): + d = esp.read_reg(args.address + (i * 4)) + f.write(struct.pack(' flash_end: + raise FatalError("File %s (length %d) at offset %d will not fit in %d bytes of flash." + + "Use --flash-size argument, or change flashing address." + % (argfile.name, argfile.tell(), address, flash_end)) + argfile.seek(0) + + for address, argfile in args.addr_filename: + print 'Erasing flash...' + if args.compress: + uncimage = argfile.read() + calcmd5 = hashlib.md5(uncimage).hexdigest() + uncsize = len(uncimage) + image = zlib.compress(uncimage, 9) + blocks = div_roundup(len(image), esp.FLASH_WRITE_SIZE) + esp.flash_defl_begin(len(uncimage),len(image), address) + else: + image = argfile.read() + calcmd5 = hashlib.md5(image).hexdigest() + uncsize = len(image) + blocks = div_roundup(len(image), esp.FLASH_WRITE_SIZE) + esp.flash_begin(blocks * esp.FLASH_WRITE_SIZE, address) + argfile.seek(0) # in case we need it again + seq = 0 + written = 0 + t = time.time() + header_block = None + while len(image) > 0: + print '\rWriting at 0x%08x... (%d %%)' % (address + seq * esp.FLASH_WRITE_SIZE, 100 * (seq + 1) / blocks), + sys.stdout.flush() + block = image[0:esp.FLASH_WRITE_SIZE] + if args.compress: + esp.flash_defl_block(block, seq) + else: + # Pad the last block + block = block + '\xff' * (esp.FLASH_WRITE_SIZE - len(block)) + # Fix sflash config data + if address == 0 and seq == 0 and block[0] == '\xe9': + block = block[0:2] + flash_info + block[4:] + header_block = block + esp.flash_block(block, seq) + image = image[esp.FLASH_WRITE_SIZE:] + seq += 1 + written += len(block) + t = time.time() - t + print '\rWrote %d bytes at 0x%08x in %.1f seconds (%.1f kbit/s)...' % (written, address, t, written / t * 8 / 1000) + res = esp.flash_md5sum(address, uncsize) + if res != calcmd5: + print 'File md5: %s' % calcmd5 + print 'Flash md5: %s' % res + raise FatalError("MD5 of file does not match data in flash!") + else: + print 'Hash of data verified.' + print '\nLeaving...' + if args.flash_mode == 'dio' and esp.CHIP_NAME == "ESP8266": + esp.flash_unlock_dio() + else: + esp.flash_begin(0, 0) + if args.compress: + esp.flash_defl_finish(False) + else: + esp.flash_finish(False) + if args.verify: + print 'Verifying just-written flash...' + verify_flash(esp, args, header_block) + + +def image_info(args): + image = LoadFirmwareImage(args.chip, args.filename) + print('Image version: %d' % image.version) + print('Entry point: %08x' % image.entrypoint) if image.entrypoint != 0 else 'Entry point not set' + print '%d segments' % len(image.segments) + print + checksum = ESPLoader.ESP_CHECKSUM_MAGIC + idx = 0 + for seg in image.segments: + idx += 1 + print 'Segment %d: %r' % (idx, seg) + checksum = ESPLoader.checksum(seg.data, checksum) + print + print 'Checksum: %02x (%s)' % (image.checksum, 'valid' if image.checksum == checksum else 'invalid!') + + +def make_image(args): + image = ESPFirmwareImage() + if len(args.segfile) == 0: + raise FatalError('No segments specified') + if len(args.segfile) != len(args.segaddr): + raise FatalError('Number of specified files does not match number of specified addresses') + for (seg, addr) in zip(args.segfile, args.segaddr): + data = file(seg, 'rb').read() + image.segments.append(ImageSegment(addr, data)) + image.entrypoint = args.entrypoint + image.save(args.output) + + +def elf2image(args): + e = ELFFile(args.input) + if args.chip == 'auto': # Default to ESP8266 for backwards compatibility + print "Creating image for ESP8266..." + args.chip == 'esp8266' + + if args.chip == 'esp32': + image = ESP32FirmwareImage() + elif args.version == '1': # ESP8266 + image = ESPFirmwareImage() + else: + image = OTAFirmwareImage() + image.entrypoint = e.entrypoint + image.segments = e.sections # ELFSection is a subclass of ImageSegment + image.flash_mode = {'qio':0, 'qout':1, 'dio':2, 'dout': 3}[args.flash_mode] + image.flash_size_freq = ESP8266ROM.FLASH_SIZES[args.flash_size] + image.flash_size_freq += {'40m':0, '26m':1, '20m':2, '80m': 0xf}[args.flash_freq] + + if args.output is None: + args.output = image.default_output_name(args.input) + image.save(args.output) + + +def read_mac(esp, args): + mac = esp.read_mac() + print 'MAC: %s' % ':'.join(map(lambda x: '%02x' % x, mac)) + + +def chip_id(esp, args): + chipid = esp.chip_id() + print 'Chip ID: 0x%08x' % chipid + + +def erase_flash(esp, args): + print 'Erasing flash (this may take a while)...' + t = time.time() + esp.erase_flash() + print 'Chip erase completed successfully in %.1fs' % (time.time() - t) + + +def erase_region(esp, args): + print 'Erasing region (may be slow depending on size)...' + esp.erase_region(args.address, args.size) + print 'Erase completed successfully.' + + +def run(esp, args): + esp.run() + + +def flash_id(esp, args): + flash_id = esp.flash_id() + print 'Manufacturer: %02x' % (flash_id & 0xff) + print 'Device: %02x%02x' % ((flash_id >> 8) & 0xff, (flash_id >> 16) & 0xff) + + +def read_flash(esp, args): + if args.no_progress: + flash_progress = None + else: + def flash_progress(progress, length): + msg = '%d (%d %%)' % (progress, progress * 100.0 / length) + padding = '\b' * len(msg) + if progress == length: + padding = '\n' + sys.stdout.write(msg + padding) + sys.stdout.flush() + t = time.time() + data = esp.read_flash(args.address, args.size, flash_progress) + t = time.time() - t + print ('\rRead %d bytes at 0x%x in %.1f seconds (%.1f kbit/s)...' + % (len(data), args.address, t, len(data) / t * 8 / 1000)) + file(args.filename, 'wb').write(data) + + +def verify_flash(esp, args, flash_params=None): + differences = False + for address, argfile in args.addr_filename: + image = argfile.read() + argfile.seek(0) # rewind in case we need it again + if address == 0 and image[0] == '\xe9' and flash_params is not None: + image = image[0:2] + flash_params + image[4:] + image_size = len(image) + print 'Verifying 0x%x (%d) bytes @ 0x%08x in flash against %s...' % (image_size, image_size, address, argfile.name) + # Try digest first, only read if there are differences. + digest = esp.flash_md5sum(address, image_size) + expected_digest = hashlib.md5(image).hexdigest() + if digest == expected_digest: + print '-- verify OK (digest matched)' + continue + else: + differences = True + if getattr(args, 'diff', 'no') != 'yes': + print '-- verify FAILED (digest mismatch)' + continue + + flash = esp.read_flash(address, image_size) + assert flash != image + diff = [i for i in xrange(image_size) if flash[i] != image[i]] + print '-- verify FAILED: %d differences, first @ 0x%08x' % (len(diff), address + diff[0]) + for d in diff: + print ' %08x %02x %02x' % (address + d, ord(flash[d]), ord(image[d])) + if differences: + raise FatalError("Verify failed.") + + +def version(args): + print __version__ + +# +# End of operations functions +# + + +def main(): + parser = argparse.ArgumentParser(description='esptool.py v%s - ESP8266 ROM Bootloader Utility' % __version__, prog='esptool') + + parser.add_argument('--chip', '-c', + help='Target chip type', + choices=['auto', 'esp8266', 'esp31', 'esp32'], + default=os.environ.get('ESPTOOL_CHIP', 'auto')) + + parser.add_argument( + '--port', '-p', + help='Serial port device', + default=os.environ.get('ESPTOOL_PORT', ESPLoader.DEFAULT_PORT)) + + parser.add_argument( + '--baud', '-b', + help='Serial port baud rate used when flashing/reading', + type=arg_auto_int, + default=os.environ.get('ESPTOOL_BAUD', ESPLoader.ESP_ROM_BAUD)) + + parser.add_argument( + '--no-stub', + help="Disable launching the flasher stub, only talk to ROM bootloader. Some features will not be available.", + action='store_true') + + subparsers = parser.add_subparsers( + dest='operation', + help='Run esptool {command} -h for additional help') + + parser_load_ram = subparsers.add_parser( + 'load_ram', + help='Download an image to RAM and execute') + parser_load_ram.add_argument('filename', help='Firmware image') + + parser_dump_mem = subparsers.add_parser( + 'dump_mem', + help='Dump arbitrary memory to disk') + parser_dump_mem.add_argument('address', help='Base address', type=arg_auto_int) + parser_dump_mem.add_argument('size', help='Size of region to dump', type=arg_auto_int) + parser_dump_mem.add_argument('filename', help='Name of binary dump') + + parser_read_mem = subparsers.add_parser( + 'read_mem', + help='Read arbitrary memory location') + parser_read_mem.add_argument('address', help='Address to read', type=arg_auto_int) + + parser_write_mem = subparsers.add_parser( + 'write_mem', + help='Read-modify-write to arbitrary memory location') + parser_write_mem.add_argument('address', help='Address to write', type=arg_auto_int) + parser_write_mem.add_argument('value', help='Value', type=arg_auto_int) + parser_write_mem.add_argument('mask', help='Mask of bits to write', type=arg_auto_int) + + def add_spi_flash_subparsers(parent): + """ Add common parser arguments for SPI flash properties """ + parent.add_argument('--flash_freq', '-ff', help='SPI Flash frequency', + choices=['40m', '26m', '20m', '80m'], + default=os.environ.get('ESPTOOL_FF', '40m')) + parent.add_argument('--flash_mode', '-fm', help='SPI Flash mode', + choices=['qio', 'qout', 'dio', 'dout'], + default=os.environ.get('ESPTOOL_FM', 'qio')) + parent.add_argument('--flash_size', '-fs', help='SPI Flash size in MegaBytes (1MB, 2MB, 4MB, 8MB, 16M)' + ' plus ESP8266-only (256KB, 512KB, 2MB-c1, 4MB-c1, 4MB-2)', + action=FlashSizeAction, + default=os.environ.get('ESPTOOL_FS', '1MB')) + parent.add_argument('--ucIsHspi', '-ih', help='Config SPI PORT/PINS (Espressif internal feature)',action='store_true') + parent.add_argument('--ucIsLegacy', '-il', help='Config SPI LEGACY (Espressif internal feature)',action='store_true') + + parser_write_flash = subparsers.add_parser( + 'write_flash', + help='Write a binary blob to flash') + parser_write_flash.add_argument('addr_filename', metavar='
', help='Address followed by binary filename, separated by space', + action=AddrFilenamePairAction) + add_spi_flash_subparsers(parser_write_flash) + parser_write_flash.add_argument('--no-progress', '-p', help='Suppress progress output', action="store_true") + parser_write_flash.add_argument('--verify', help='Verify just-written data (only necessary if very cautious, data is already CRCed', action='store_true') + parser_write_flash.add_argument('--compress', '-z', help='Compress data in transfer',action="store_true") + + subparsers.add_parser( + 'run', + help='Run application code in flash') + + parser_image_info = subparsers.add_parser( + 'image_info', + help='Dump headers from an application image') + parser_image_info.add_argument('filename', help='Image file to parse') + + parser_make_image = subparsers.add_parser( + 'make_image', + help='Create an application image from binary files') + parser_make_image.add_argument('output', help='Output image file') + parser_make_image.add_argument('--segfile', '-f', action='append', help='Segment input file') + parser_make_image.add_argument('--segaddr', '-a', action='append', help='Segment base address', type=arg_auto_int) + parser_make_image.add_argument('--entrypoint', '-e', help='Address of entry point', type=arg_auto_int, default=0) + + parser_elf2image = subparsers.add_parser( + 'elf2image', + help='Create an application image from ELF file') + parser_elf2image.add_argument('input', help='Input ELF file') + parser_elf2image.add_argument('--output', '-o', help='Output filename prefix (for version 1 image), or filename (for version 2 single image)', type=str) + parser_elf2image.add_argument('--version', '-e', help='Output image version', choices=['1','2'], default='1') + add_spi_flash_subparsers(parser_elf2image) + + subparsers.add_parser( + 'read_mac', + help='Read MAC address from OTP ROM') + + subparsers.add_parser( + 'chip_id', + help='Read Chip ID from OTP ROM') + + subparsers.add_parser( + 'flash_id', + help='Read SPI flash manufacturer and device ID') + + parser_read_flash = subparsers.add_parser( + 'read_flash', + help='Read SPI flash content') + parser_read_flash.add_argument('address', help='Start address', type=arg_auto_int) + parser_read_flash.add_argument('size', help='Size of region to dump', type=arg_auto_int) + parser_read_flash.add_argument('filename', help='Name of binary dump') + parser_read_flash.add_argument('--no-progress', '-p', help='Suppress progress output', action="store_true") + + parser_verify_flash = subparsers.add_parser( + 'verify_flash', + help='Verify a binary blob against flash') + parser_verify_flash.add_argument('addr_filename', help='Address and binary file to verify there, separated by space', + action=AddrFilenamePairAction) + parser_verify_flash.add_argument('--diff', '-d', help='Show differences', + choices=['no', 'yes'], default='no') + + subparsers.add_parser( + 'erase_flash', + help='Perform Chip Erase on SPI flash') + + parser_erase_region = subparsers.add_parser( + 'erase_region', + help='Erase a region of the flash') + parser_erase_region.add_argument('address', help='Start address (must be multiple of 4096)', type=arg_auto_int) + parser_erase_region.add_argument('size', help='Size of region to erase (must be multiple of 4096)', type=arg_auto_int) + + subparsers.add_parser( + 'version', help='Print esptool version') + + # internal sanity check - every operation matches a module function of the same name + for operation in subparsers.choices.keys(): + assert operation in globals(), "%s should be a module function" % operation + + args = parser.parse_args() + + print 'esptool.py v%s' % __version__ + + # operation function can take 1 arg (args), 2 args (esp, arg) + # or be a member function of the ESPLoader class. + + operation_func = globals()[args.operation] + operation_args,_,_,_ = inspect.getargspec(operation_func) + if operation_args[0] == 'esp': # operation function takes an ESPLoader connection object + initial_baud = min(ESPLoader.ESP_ROM_BAUD, args.baud) # don't sync faster than the default baud rate + chip_constructor_fun = { + 'auto': ESPLoader.detect_chip, + 'esp8266': ESP8266ROM, + 'esp32': ESP32ROM, + }[args.chip] + esp = chip_constructor_fun(args.port, initial_baud) + + if not args.no_stub: + esp = esp.run_stub() + + if args.baud > initial_baud: + esp.change_baud(args.baud) + # TODO: handle a NotImplementedInROMError + + # override common SPI flash parameter stuff as required + if hasattr(args, "ucIsHspi"): + print "Attaching SPI flash..." + esp.flash_spi_attach(args.ucIsHspi,args.ucIsLegacy) + if hasattr(args, "flash_size"): + print "Configuring flash size..." + esp.flash_set_parameters(flash_size_bytes(args.flash_size)) + + operation_func(esp, args) + else: + operation_func(args) + + +class FlashSizeAction(argparse.Action): + """ Custom flash size parser class to support backwards compatibility with megabit size arguments. + + (At next major relase, remove deprecated sizes and this can become a 'normal' choices= argument again.) + """ + def __init__(self, option_strings, dest, nargs=1, **kwargs): + super(FlashSizeAction, self).__init__(option_strings, dest, nargs, **kwargs) + + def __call__(self, parser, namespace, values, option_string=None): + try: + value = { + '2m': '256KB', + '4m': '512KB', + '8m': '1MB', + '16m': '2MB', + '32m': '4MB', + '16m-c1': '2MB-c1', + '32m-c1': '4MB-c1', + '32m-c2': '4MB-c2' + }[values[0]] + print("WARNING: Flash size arguments in megabits like '%s' are deprecated." % (values[0])) + print("Please use the equivalent size '%s'." % (value)) + print("Megabit arguments may be removed in a future release.") + except KeyError: + value = values[0] + + known_sizes = dict(ESP8266ROM.FLASH_SIZES) + known_sizes.update(ESP32ROM.FLASH_SIZES) + if value not in known_sizes: + raise argparse.ArgumentError(self, '%s is not a known flash size. Known sizes: %s' % (value, ", ".join(known_sizes.keys()))) + setattr(namespace, self.dest, value) + + +class AddrFilenamePairAction(argparse.Action): + """ Custom parser class for the address/filename pairs passed as arguments """ + def __init__(self, option_strings, dest, nargs='+', **kwargs): + super(AddrFilenamePairAction, self).__init__(option_strings, dest, nargs, **kwargs) + + def __call__(self, parser, namespace, values, option_string=None): + # validate pair arguments + pairs = [] + for i in range(0,len(values),2): + try: + address = int(values[i],0) + except ValueError as e: + raise argparse.ArgumentError(self,'Address "%s" must be a number' % values[i]) + try: + argfile = open(values[i + 1], 'rb') + except IOError as e: + raise argparse.ArgumentError(self, e) + except IndexError: + raise argparse.ArgumentError(self,'Must be pairs of an address and the binary filename to write there') + pairs.append((address, argfile)) + setattr(namespace, self.dest, pairs) + +# Binary stub code (see flasher_stub dir for source & details) +ESP8266ROM.STUB_CODE = eval(zlib.decompress(base64.b64decode(b""" +eNrFPHl/1MbZX0VaG18YmJG00shAsl7McgR+NRAc0nfTWBpJIRSovXELobSf/dVzaUbaXRxy9Y+1NdJojue+Rv/evqjfX2wfBNvz942Zv1dR+1On8/daeQ211JCf0e17tv018/dWBXB3p/0TB8HmyRRuw/McLg7b\ +P0Wv4y50DNtbWe/2A5qLW/ehdXLR6wHrjNtfO6+OcBlJsKHmi7aTGqxPu2uj+tdN/aXfeUJTyI+G9QECa9I0hc1DbtCOLvTOo7ZH+rTtm7a/sdurbtsNjDFuX6kTAUl/y3lvy4iGk5+gx86j9nYBS2nm2xvtv0y2\ +3YKzrnipKcND7ewHQXJCEzY1dCl5FRbGfLHfTl0jtibP25tawV+AkfTjFXwLA7a3q2QJM3EPMzFhxjwK8H7+yOwfjHb3mTCsCR3c9DKCjFyf8grVEom1jTz5O8wByLJX8WoSyONHX/Ej7b8hU9bKo64qf9L+cThr\ +yVJ3e3HEb/NifnHevpu34LPtjaqahAzRxutfc/8artUFIPoL2BJguREsqyXGiIKg7WvGcBPI82PbvQVdnjKlxR2G2o4wezzp3n+6EbQspePpBGi1RY0uq9NTuuQu5bPpw7tda3QEfyN8B9aFe8DNJvOW3/PYASDa\ +D9oeFRN/lcFToJC2Q+qYott9Fb3ecNO8Dqgb8Yp3f6P/SkDE65H6aD5vt6Ra6qvrE/gD+Jq1nZEeYUUx07g595ElDGNaXFbmCaAD5AsQHSE/IGJTN5m1HfeOiKHaGS40CYimkt0JDUkfyx2KYQcm8PW07UmLC808\ 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+Gq8BSTyszf/0lOsbNdfRLD8prA9EDhq1je86+N/wXm0tAIEyMoygorUQ6P6BP1ry+Qv9jY0NXsa3/P+ut/Z+3fXwXNjwgNMK4TmsAewdSXafRMHf4NspejA3nXf2/FXlf1PCNQ79RjGorR+MafWK78nqQX89eB4N\ +2vGgnQza6aBtBm3bb+vBenSvv//1nH7Pid84XTa0/rCfvqQdfSYNXUZTl9HYsJ1e0s4uaZtPti8+0Xr7iVb/Oz2r2vaT7cWneOfS3+fybfpZMLr4jH0PV95cIgUGK9eDlegBFHVvvA2/cdVv9IbtFVrd8RvP/EYP\ +IT8NJM1gncWgbQftOl7BJfpP5OI/Wgr8VinxW6XIb5Uyv1UKXdb+zJ9W7ju7HQdmyHlU/jhmTku6g2wLhhp/jajjtFU6bu1OwQKGT8r7FnCS5SpRrUO8Xb+9WPzc3YxUHP3n/wHA2KlZ\ +"""))) +ESP32ROM.STUB_CODE = eval(zlib.decompress(base64.b64decode(b""" +eNp9Wmtz28YV/SsUZUukLTtYgAQWajKVZIeRbM/Edi1acZlpgAUQZybVNAoztVP3v3fPfWAXINUPFMF93N37OvcB/ed4237aHp9OjjefOjvxfxZ/3XwyiT4l0VP0sfk5ng78XO0/3eaTw0LMWeu/U/+N5+TB+pLn\ +S4MD8IxN1XhTudn6v1hTDKbmOKz/NcOv9d1gxQw7E+cvbScYWODYqadpGr8uGV0cHxOe7WiucwNOz/gk/dDgggWyIwBrL/yZ+Y0fzh8GFk3Oz8mS+WsXY3lEYijLAbt+wBLHn6MjwGrn11kvqArrc0xM/VoRvsG3\ +E0WQXPi0thEq+VAGdA7mndzY8SVqEK36jV4WtWfV+IEqkedEFrgRH3W5ueWpZrHL4u2QwVtlrwR7VsTg6PsCo+CtYn5sOR0p1oriyGxd9KNXKX6U/hptrfr1yyr+cTbRha/8kbrAhK1BzWSXZsd2307x1/9psjPM\ +DPm9OCIzOtuyIUD5icUyw8tqfKcjEVXpkTzQx+9tl+QiLLH8g1g5JN/y3n6l9cQaexbrIp35pzKFIVywlZQJX9T5QVeyNUDeTsd1r0tvdEvNqokueSX3UcoD645OgaGW5V9ipafTiawnORSsclOzNQM9WClf/ArL\ +FIyXWus/Lg9KF4JpfRhDSVpPhE4WrCCePox2TtgcBk5n07fws/r5GtwUK0hUgKvJBrr6gS87RJoTlolXOxsPK6US+VaNwGMhooM/yXxTCwYKpLSRgfdr3IrVP4Y1GxMR4thMBPP/Q7CRNYvdNcwYs3GajrXDNPS3\ +qadsqHx7uQGoDsWjQqkioZApVHvuSMKCEWcTWLog2M7W/L6rix8Du7tw7ZoCSR70Y9i9aB0Qk6zRJl+fl7Pe4+f2dDo5ORd7yeaXYPCSrOgj4H0qdxLP7JZ72Em86dns/tBk+ueb+Id3g4ZCyBlM8Snd3Z/uomFA\ +HzTvf+QHByyixkgwiFArvo4PBFs94k0wEhb662eeYt0IODQBcvbZEgWAanjq3r3ZeO+L6VkGRa4dqzcOJ3VEDe5fVUPQG4gW42UUwGrd0yrCPmFEYNmTttxYEx9jqf8r/rGNf3waKccMMoifJXOoFj0Q4J4fBRIO\ +qhD4bZQEmKrjK1t7JZ4GPopahXCyuQXe2Dtdd48yMN4Qx98hiAvc5F9HLpXHq+Ld3rwdJTtvNOy/4KWmupYQhFCUfxWOaun+Xlhlxh5pNFZbptojXnJ1j0m5cg8XTvC+jxIkkC1kSmnVj3h2soLEVUfAJKfUcgpw\ +Sc1DJcA3QahcSDRyya55vvi3R7K6QCZzroHgtb9Eocw+BwYsvvPEK8eENbj3yshVwywUVwZkbvI9KmiMbngOL3iA4baOCCYRVtURYZF4nX8rKR55whdxLQL7hLc3HQvGc3a3ufUZRY2kKH2pWH69ywrcETbatSwQ\ +5GR1c/StZIkVxY+fcPpEUsNKqgDM5vt9tjL7fFYURnMnyBdJO+Y+lH97xBtJHtV7vp7wf6uQXiz7sa0kKJW4bvELLHTFcErhHbmaJP0BIV4/iaIG/rTiKdZofu6XLz7cnF6/3mzOJdOmrX6ly3TRg/czzierJVuh\ +1gmlHF8RnQlEPkFIySb3h2jrTjXyZPN3M2x8dDjH12wBr3NJudgfcHyq+/3l+RUHkj457pju9kysZ5xOa+UwqIkSKRkD+WRP1UixKCTryeY4KkDiOxgbV2PusTy1Aq2/PiI92FQCoXMn9PSKvwAqS4FdwiH94Rzr\ +3f9IWL8+Wt70IP2KcyhaahZMKxd4QQVAuQ0cgh/mrBMS0uIggJTrlQ4YT19Oi5SliuDoDCWcL1n37OcH7FLkVnDuNjh3gpKkSUkXH/qsc9pN7st7DtSGU3YtzuxpF2Aq9c5EBayMlYLM5o9dw2LfoVKvkvOaPYEX\ +V3YFXx+iUuxqzEsxkgiwNHGjnEGvqKC2EwTeiNO0KmVf+DfLx0EOR4fwm2EDwg/qIYH3i+4wPYfJab5q4iSSpszFm832IirUk25/zuw0v9FjLCvTiTJKPSMTe0pDP4TySmT8tTYNaHDC8aRGdlIM01vYmgKfjrdt\ +uzuouXCS7VEl4Ez6Kv2VTBdnB+/FRZ1cvMjS7lJW5j+JO1Jzo+1mPO7y7zHeWV32Tk/7pbcgXzAV0sWgHS7MdPGMzRdhpsaM6cnSntXfKdOWKJbQAqotITNI1R0OyL3G8iJw6PKVcji8kaRFLv9B3VYPSQcE50QQ\ +wFzogiEDjzSp/lvgxGQE7NunknVk32xuVyw1yaYQdepSBVeENhDchjC/ZA+I9YlDMY94gawL4GmpNk53awpqDbhzGGbFVg2y5R4zYbLrPxGJU6l1iYK0Y6x7xuQsYfiad3btKSBixZ4T2hZcAoE3J6zYPWUt9OPM\ ++gW3//5Ur8jUoKk1lHC/xpH82+SUuaXouhgxCaG2et6ehAEBoTVrSguKAZO2L0OAN5rhcnOg1xZmjFpM1EbTVTXr9GlkRy5ZPRnFQUSV8iGTMCN1CWJJJldSxZKsn2m98DF4PQHRbrMQqz4oar6UDKyU6EsmkDOs\ +VG3oB2rnjAyzLtU5/GQbIISFHbj0s90eWSTjVWU69Ag6MOpgVOZVhPKWoPU2luBSWkD1tf0ATU2ZJpUNScjl3KirUMJSSj1Q2yQGsmwj0toooas45EO2b9gg73ccm6TYtzdiecuAmDaTDhYjAd822IVyvhIx9qKI\ +zIpkXY12xT0sGpNrUXqwp4ubJN9gVd8LFF9AdKrSkKKSf/Cih2FmHEjAxxB41ty8QIJho0CqDelSUBuBxRbgyx3ZHzWKOIbkVRPSRkNCoF1dDLqGRIioEyeYlUnUCezYr2dTDBfjYUpbzsUwKu61QciU0CAEowHK\ +wIyV2T1Nsky6kOarfaH13eia6ZQZrukBQEYPCxSPb0UZ5HkIBHFtxUnDKGPgljs9TMTtUxYztlDHGsVFrdl4fjUK81mUkehbGcui4BcGk4gmdqGI7NREYdz5wfA9gaEq5GAu5mEJusvfIJcpZD2vZpTZu9PNsQ0m\ +QkWqWKQGOESWRjo3zjyUyCIVUGMOxLg6edMh3QbHdeOtdIkaFbNAouOeJrjtIpi0kreNNegaUPJx6BjH/hZcRKOsvu1w/GLjWGKglRHiv4KRVOTANUMG7A27/I7tJBCg2ttNOP1tpKmu4ukL8yVfkTpImUS3ZsKB\ +nipkbamM5Okk2gLe66W+VZE5kRyzN6fuibvkDgSaLYlZKdzMlghSFyJ5DQ+CbZqnu1y7ilp/5vPrFeHb+tfNHdNQ358GPA1FsQ7a+XUICsGXZtO1WPki9lKpzNvdplfb7hnPtU4fplXU3LonrcKlKK3K6FyYd/5M\ +hTmFj5DnUFUu2VCNbAgSbih5eCaVIr39aqNmW3tVDYovhHjibKUvchDcapzRSmjqa8psDDILRRiGmqW2XGSzdVGXiKwICTOikNVWxJBMgC77lvKItA1JG1ioofLm6qO+ZnpczlZR37i/usPrIEK7lrbbuyj4G1bo\ +jqIaLjf5jp9jkgpfjlYRlJIHiopq3hOQgGxFPJ4KrXansmXEyP+JY9RSWwEMmAwV8+34lQWdnk6jDMMSpWN5qoXNVJrzpZyVonjIvvAR3Io54rIlsUfo1SxXw/ZlD7fxO51kdshBtrSHIDydi0vkIa/oNzhdKpmK\ +vAemdGPYBCe0PA7ZI3NAtKfhdN7whSXEP45PJsdNta3+8fu2usO/EJikyJZZWZa5zPC/FWgDB+vxzwbx+kWWmXxh/Ux7u7373A+mtsj/+z8+/soR\ +"""))) + +if __name__ == '__main__': + try: + main() + except FatalError as e: + print '\nA fatal error occurred: %s' % e + sys.exit(2) diff --git a/tools/get.py b/tools/get.py new file mode 100755 index 00000000..80bcb227 --- /dev/null +++ b/tools/get.py @@ -0,0 +1,116 @@ +#!/usr/bin/env python +# This script will download and extract required tools into the current directory. +# Tools list is obtained from package/package_esp8266com_index.template.json file. +# Written by Ivan Grokhotkov, 2015. +# +from __future__ import print_function +import os +import shutil +import errno +import os.path +import hashlib +import json +import platform +import sys +import tarfile +import zipfile +import re +if sys.version_info[0] == 3: + from urllib.request import urlretrieve +else: + # Not Python 3 - today, it is most likely to be Python 2 + from urllib import urlretrieve + +dist_dir = 'dist/' + +def sha256sum(filename, blocksize=65536): + hash = hashlib.sha256() + with open(filename, "rb") as f: + for block in iter(lambda: f.read(blocksize), b""): + hash.update(block) + return hash.hexdigest() + +def mkdir_p(path): + try: + os.makedirs(path) + except OSError as exc: + if exc.errno != errno.EEXIST or not os.path.isdir(path): + raise + +def report_progress(count, blockSize, totalSize): + percent = int(count*blockSize*100/totalSize) + percent = min(100, percent) + sys.stdout.write("\r%d%%" % percent) + sys.stdout.flush() + +def unpack(filename, destination): + dirname = '' + print('Extracting {0}'.format(filename)) + if filename.endswith('tar.gz'): + tfile = tarfile.open(filename, 'r:gz') + tfile.extractall(destination) + dirname= tfile.getnames()[0] + elif filename.endswith('zip'): + zfile = zipfile.ZipFile(filename) + zfile.extractall(destination) + dirname = zfile.namelist()[0] + else: + raise NotImplementedError('Unsupported archive type') + + # a little trick to rename tool directories so they don't contain version number + rename_to = re.match(r'^([a-z][^\-]*\-*)+', dirname).group(0).strip('-') + if rename_to != dirname: + print('Renaming {0} to {1}'.format(dirname, rename_to)) + if os.path.isdir(rename_to): + shutil.rmtree(rename_to) + shutil.move(dirname, rename_to) + +def get_tool(tool): + archive_name = tool['archiveFileName'] + local_path = dist_dir + archive_name + url = tool['url'] + #real_hash = tool['checksum'].split(':')[1] + if not os.path.isfile(local_path): + print('Downloading ' + archive_name); + urlretrieve(url, local_path, report_progress) + sys.stdout.write("\rDone\n") + sys.stdout.flush() + else: + print('Tool {0} already downloaded'.format(archive_name)) + #local_hash = sha256sum(local_path) + #if local_hash != real_hash: + # print('Hash mismatch for {0}, delete the file and try again'.format(local_path)) + # raise RuntimeError() + unpack(local_path, '.') + +def load_tools_list(filename, platform): + tools_info = json.load(open(filename))['packages'][0]['tools'] + tools_to_download = [] + for t in tools_info: + tool_platform = [p for p in t['systems'] if p['host'] == platform] + if len(tool_platform) == 0: + continue + tools_to_download.append(tool_platform[0]) + return tools_to_download + +def identify_platform(): + arduino_platform_names = {'Darwin' : {32 : 'i386-apple-darwin', 64 : 'x86_64-apple-darwin'}, + 'Linux' : {32 : 'i686-pc-linux-gnu', 64 : 'x86_64-pc-linux-gnu'}, + 'LinuxARM': {32 : 'arm-linux-gnueabihf', 64 : 'aarch64-linux-gnu'}, + 'Windows' : {32 : 'i686-mingw32', 64 : 'i686-mingw32'}} + bits = 32 + if sys.maxsize > 2**32: + bits = 64 + sys_name = platform.system() + if 'Linux' in sys_name and platform.platform().find('arm') > 0: + sys_name = 'LinuxARM' + if 'CYGWIN_NT' in sys_name: + sys_name = 'Windows' + return arduino_platform_names[sys_name][bits] + +if __name__ == '__main__': + print('Platform: {0}'.format(identify_platform())) + tools_to_download = load_tools_list('../package/package_esp32_index.template.json', identify_platform()) + mkdir_p(dist_dir) + for tool in tools_to_download: + get_tool(tool) diff --git a/tools/sdk/bin/bootloader.bin b/tools/sdk/bin/bootloader.bin new file mode 100644 index 00000000..d62d91ab Binary files /dev/null and b/tools/sdk/bin/bootloader.bin differ diff --git a/tools/sdk/bin/partitions_singleapp.bin b/tools/sdk/bin/partitions_singleapp.bin new file mode 100644 index 00000000..0c4252de Binary files /dev/null and b/tools/sdk/bin/partitions_singleapp.bin differ diff --git a/tools/sdk/include/bt/bt.h b/tools/sdk/include/bt/bt.h new file mode 100644 index 00000000..1e89f96a --- /dev/null +++ b/tools/sdk/include/bt/bt.h @@ -0,0 +1,69 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef __BT_H__ +#define __BT_H__ + +#include +#include "esp_err.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @brief Initialize BT controller + * + * This function should be called only once, before any other BT functions are called. + */ +void bt_controller_init(); + +/** @brief: vhci_host_callback + * used for vhci call host function to notify what host need to do + * + * notify_host_send_available: notify host can send packet to controller + * notify_host_recv: notify host that controller has packet send to host + */ +typedef struct vhci_host_callback { + + void (*notify_host_send_available)(void); + int (*notify_host_recv)(uint8_t *data, uint16_t len); +} vhci_host_callback_t; + +/** @brief: API_vhci_host_check_send_available + * used for check actively if the host can send packet to controller or not. + * return true for ready to send, false means cannot send packet + */ +bool API_vhci_host_check_send_available(void); + +/** @brief: API_vhci_host_send_packet + * host send packet to controller + * param data is the packet point, the param len is the packet length + * return void + */ +void API_vhci_host_send_packet(uint8_t *data, uint16_t len); + +/** @brief: API_vhci_host_register_callback + * register the vhci referece callback, the call back + * struct defined by vhci_host_callback structure. + * param is the vhci_host_callback type variable + */ +void API_vhci_host_register_callback(const vhci_host_callback_t *callback); + +#ifdef __cplusplus +} +#endif + +#endif /* __BT_H__ */ diff --git a/tools/sdk/include/config/sdkconfig.h b/tools/sdk/include/config/sdkconfig.h new file mode 100644 index 00000000..8c5fb802 --- /dev/null +++ b/tools/sdk/include/config/sdkconfig.h @@ -0,0 +1,49 @@ +/* + * + * Automatically generated file; DO NOT EDIT. + * Espressif IoT Development Framework Configuration + * + */ +#define CONFIG_TRACEMEM_RESERVE_DRAM 0x0 +#define CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE 1 +#define CONFIG_ESPTOOLPY_FLASHFREQ "80m" +#define CONFIG_NEWLIB_STDOUT_ADDCR 1 +#define CONFIG_FREERTOS_PANIC_PRINT_REBOOT 1 +#define CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS 1 +#define CONFIG_BT_RESERVE_DRAM 0x0 +#define CONFIG_LWIP_MAX_SOCKETS 4 +#define CONFIG_ESP32_DEFAULT_CPU_FREQ_160 1 +#define CONFIG_ULP_COPROC_RESERVE_MEM 0 +#define CONFIG_ESPTOOLPY_BAUD 921600 +#define CONFIG_LOG_DEFAULT_LEVEL_WARN 1 +#define CONFIG_TOOLPREFIX "xtensa-esp32-elf-" +#define CONFIG_LWIP_THREAD_LOCAL_STORAGE_INDEX 0 +#define CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN 16384 +#define CONFIG_ESP32_ENABLE_STACK_WIFI 1 +#define CONFIG_LOG_BOOTLOADER_LEVEL_WARN 1 +#define CONFIG_MAIN_TASK_STACK_SIZE 4096 +#define CONFIG_ESPTOOLPY_FLASHMODE "dio" +#define CONFIG_LOG_DEFAULT_LEVEL 2 +#define CONFIG_ESPTOOLPY_FLASHMODE_DIO 1 +#define CONFIG_PYTHON "python" +#define CONFIG_ESPTOOLPY_COMPRESSED 1 +#define CONFIG_PARTITION_TABLE_FILENAME "partitions_singleapp.csv" +#define CONFIG_PARTITION_TABLE_SINGLE_APP 1 +#define CONFIG_WIFI_ENABLED 1 +#define CONFIG_ESPTOOLPY_FLASHFREQ_80M 1 +#define CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE 2048 +#define CONFIG_PARTITION_TABLE_CUSTOM_APP_BIN_OFFSET 0x10000 +#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 160 +#define CONFIG_FREERTOS_HZ 1000 +#define CONFIG_FREERTOS_ASSERT_FAIL_ABORT 1 +#define CONFIG_LOG_BOOTLOADER_LEVEL 2 +#define CONFIG_ESPTOOLPY_BAUD_OTHER_VAL 115200 +#define CONFIG_LWIP_SO_REUSE 1 +#define CONFIG_FREERTOS_CORETIMER_0 1 +#define CONFIG_PARTITION_TABLE_CUSTOM_FILENAME "partitions.csv" +#define CONFIG_FREERTOS_DEBUG_OCDAWARE 1 +#define CONFIG_SYSTEM_EVENT_QUEUE_SIZE 32 +#define CONFIG_ESPTOOLPY_BAUD_921600B 1 +#define CONFIG_APP_OFFSET 0x10000 +#define CONFIG_MEMMAP_SMP 1 +#define CONFIG_ESPTOOLPY_PORT "/dev/tty.SLAB_USBtoUART" diff --git a/tools/sdk/include/driver/driver/gpio.h b/tools/sdk/include/driver/driver/gpio.h new file mode 100644 index 00000000..9b47c88e --- /dev/null +++ b/tools/sdk/include/driver/driver/gpio.h @@ -0,0 +1,462 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _DRIVER_GPIO_H_ +#define _DRIVER_GPIO_H_ +#include "esp_err.h" +#include +#include "soc/gpio_reg.h" +#include "soc/gpio_struct.h" +#include "soc/rtc_io_reg.h" +#include "soc/io_mux_reg.h" +#include "rom/gpio.h" +#include "esp_attr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define GPIO_SEL_0 (BIT(0)) /* Pin 0 selected */ +#define GPIO_SEL_1 (BIT(1)) /* Pin 1 selected */ +#define GPIO_SEL_2 (BIT(2)) /* Pin 2 selected */ +#define GPIO_SEL_3 (BIT(3)) /* Pin 3 selected */ +#define GPIO_SEL_4 (BIT(4)) /* Pin 4 selected */ +#define GPIO_SEL_5 (BIT(5)) /* Pin 5 selected */ +#define GPIO_SEL_6 (BIT(6)) /* Pin 6 selected */ +#define GPIO_SEL_7 (BIT(7)) /* Pin 7 selected */ +#define GPIO_SEL_8 (BIT(8)) /* Pin 8 selected */ +#define GPIO_SEL_9 (BIT(9)) /* Pin 9 selected */ +#define GPIO_SEL_10 (BIT(10)) /* Pin 10 selected */ +#define GPIO_SEL_11 (BIT(11)) /* Pin 11 selected */ +#define GPIO_SEL_12 (BIT(12)) /* Pin 12 selected */ +#define GPIO_SEL_13 (BIT(13)) /* Pin 13 selected */ +#define GPIO_SEL_14 (BIT(14)) /* Pin 14 selected */ +#define GPIO_SEL_15 (BIT(15)) /* Pin 15 selected */ +#define GPIO_SEL_16 (BIT(16)) /* Pin 16 selected */ +#define GPIO_SEL_17 (BIT(17)) /* Pin 17 selected */ +#define GPIO_SEL_18 (BIT(18)) /* Pin 18 selected */ +#define GPIO_SEL_19 (BIT(19)) /* Pin 19 selected */ + +#define GPIO_SEL_21 (BIT(21)) /* Pin 21 selected */ +#define GPIO_SEL_22 (BIT(22)) /* Pin 22 selected */ +#define GPIO_SEL_23 (BIT(23)) /* Pin 23 selected */ + +#define GPIO_SEL_25 (BIT(25)) /* Pin 25 selected */ +#define GPIO_SEL_26 (BIT(26)) /* Pin 26 selected */ +#define GPIO_SEL_27 (BIT(27)) /* Pin 27 selected */ + +#define GPIO_SEL_32 ((uint64_t)(((uint64_t)1)<<32)) /* Pin 32 selected */ +#define GPIO_SEL_33 ((uint64_t)(((uint64_t)1)<<33)) /* Pin 33 selected */ +#define GPIO_SEL_34 ((uint64_t)(((uint64_t)1)<<34)) /* Pin 34 selected */ +#define GPIO_SEL_35 ((uint64_t)(((uint64_t)1)<<35)) /* Pin 35 selected */ +#define GPIO_SEL_36 ((uint64_t)(((uint64_t)1)<<36)) /* Pin 36 selected */ +#define GPIO_SEL_37 ((uint64_t)(((uint64_t)1)<<37)) /* Pin 37 selected */ +#define GPIO_SEL_38 ((uint64_t)(((uint64_t)1)<<38)) /* Pin 38 selected */ +#define GPIO_SEL_39 ((uint64_t)(((uint64_t)1)<<39)) /* Pin 39 selected */ + +#define GPIO_PIN_REG_0 PERIPHS_IO_MUX_GPIO0_U +#define GPIO_PIN_REG_1 PERIPHS_IO_MUX_U0TXD_U +#define GPIO_PIN_REG_2 PERIPHS_IO_MUX_GPIO2_U +#define GPIO_PIN_REG_3 PERIPHS_IO_MUX_U0RXD_U +#define GPIO_PIN_REG_4 PERIPHS_IO_MUX_GPIO4_U +#define GPIO_PIN_REG_5 PERIPHS_IO_MUX_GPIO5_U +#define GPIO_PIN_REG_6 PERIPHS_IO_MUX_SD_CLK_U +#define GPIO_PIN_REG_7 PERIPHS_IO_MUX_SD_DATA0_U +#define GPIO_PIN_REG_8 PERIPHS_IO_MUX_SD_DATA1_U +#define GPIO_PIN_REG_9 PERIPHS_IO_MUX_SD_DATA2_U +#define GPIO_PIN_REG_10 PERIPHS_IO_MUX_SD_DATA3_U +#define GPIO_PIN_REG_11 PERIPHS_IO_MUX_SD_CMD_U +#define GPIO_PIN_REG_12 PERIPHS_IO_MUX_MTDI_U +#define GPIO_PIN_REG_13 PERIPHS_IO_MUX_MTCK_U +#define GPIO_PIN_REG_14 PERIPHS_IO_MUX_MTMS_U +#define GPIO_PIN_REG_15 PERIPHS_IO_MUX_MTDO_U +#define GPIO_PIN_REG_16 PERIPHS_IO_MUX_GPIO16_U +#define GPIO_PIN_REG_17 PERIPHS_IO_MUX_GPIO17_U +#define GPIO_PIN_REG_18 PERIPHS_IO_MUX_GPIO18_U +#define GPIO_PIN_REG_19 PERIPHS_IO_MUX_GPIO19_U +#define GPIO_PIN_REG_20 PERIPHS_IO_MUX_GPIO20_U +#define GPIO_PIN_REG_21 PERIPHS_IO_MUX_GPIO21_U +#define GPIO_PIN_REG_22 PERIPHS_IO_MUX_GPIO22_U +#define GPIO_PIN_REG_23 PERIPHS_IO_MUX_GPIO23_U +#define GPIO_PIN_REG_25 PERIPHS_IO_MUX_GPIO25_U +#define GPIO_PIN_REG_26 PERIPHS_IO_MUX_GPIO26_U +#define GPIO_PIN_REG_27 PERIPHS_IO_MUX_GPIO27_U +#define GPIO_PIN_REG_32 PERIPHS_IO_MUX_GPIO32_U +#define GPIO_PIN_REG_33 PERIPHS_IO_MUX_GPIO33_U +#define GPIO_PIN_REG_34 PERIPHS_IO_MUX_GPIO34_U +#define GPIO_PIN_REG_35 PERIPHS_IO_MUX_GPIO35_U +#define GPIO_PIN_REG_36 PERIPHS_IO_MUX_GPIO36_U +#define GPIO_PIN_REG_37 PERIPHS_IO_MUX_GPIO37_U +#define GPIO_PIN_REG_38 PERIPHS_IO_MUX_GPIO38_U +#define GPIO_PIN_REG_39 PERIPHS_IO_MUX_GPIO39_U + +#define GPIO_APP_CPU_INTR_ENA (BIT(0)) +#define GPIO_APP_CPU_NMI_INTR_ENA (BIT(1)) +#define GPIO_PRO_CPU_INTR_ENA (BIT(2)) +#define GPIO_PRO_CPU_NMI_INTR_ENA (BIT(3)) +#define GPIO_SDIO_EXT_INTR_ENA (BIT(4)) + +#define GPIO_MODE_DEF_INPUT (BIT0) +#define GPIO_MODE_DEF_OUTPUT (BIT1) +#define GPIO_MODE_DEF_OD (BIT2) + +#define GPIO_PIN_COUNT 40 +extern const uint32_t GPIO_PIN_MUX_REG[GPIO_PIN_COUNT]; +#define GPIO_IS_VALID_GPIO(gpio_num) ((gpio_num < GPIO_PIN_COUNT && GPIO_PIN_MUX_REG[gpio_num] != 0)) //to decide whether it is a valid GPIO number +#define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) ((GPIO_IS_VALID_GPIO(gpio_num)) && (gpio_num < 34)) //to decide whether it can be a valid GPIO number of output mode + +typedef enum { + GPIO_NUM_0 = 0, + GPIO_NUM_1 = 1, + GPIO_NUM_2 = 2, + GPIO_NUM_3 = 3, + GPIO_NUM_4 = 4, + GPIO_NUM_5 = 5, + GPIO_NUM_6 = 6, + GPIO_NUM_7 = 7, + GPIO_NUM_8 = 8, + GPIO_NUM_9 = 9, + GPIO_NUM_10 = 10, + GPIO_NUM_11 = 11, + GPIO_NUM_12 = 12, + GPIO_NUM_13 = 13, + GPIO_NUM_14 = 14, + GPIO_NUM_15 = 15, + GPIO_NUM_16 = 16, + GPIO_NUM_17 = 17, + GPIO_NUM_18 = 18, + GPIO_NUM_19 = 19, + + GPIO_NUM_21 = 21, + GPIO_NUM_22 = 22, + GPIO_NUM_23 = 23, + + GPIO_NUM_25 = 25, + GPIO_NUM_26 = 26, + GPIO_NUM_27 = 27, + + GPIO_NUM_32 = 32, + GPIO_NUM_33 = 33, + GPIO_NUM_34 = 34, /*input mode only */ + GPIO_NUM_35 = 35, /*input mode only */ + GPIO_NUM_36 = 36, /*input mode only */ + GPIO_NUM_37 = 37, /*input mode only */ + GPIO_NUM_38 = 38, /*input mode only */ + GPIO_NUM_39 = 39, /*input mode only */ +} gpio_num_t; + +typedef enum { + GPIO_INTR_DISABLE = 0, /* disable GPIO interrupt */ + GPIO_INTR_POSEDGE = 1, /* GPIO interrupt type : rising edge */ + GPIO_INTR_NEGEDGE = 2, /* GPIO interrupt type : falling edge */ + GPIO_INTR_ANYEDGE = 3, /* GPIO interrupt type : both rising and falling edge */ + GPIO_INTR_LOW_LEVEL = 4, /* GPIO interrupt type : input low level trigger */ + GPIO_INTR_HIGH_LEVEL = 5, /* GPIO interrupt type : input high level trigger */ + GPIO_INTR_MAX, +} gpio_int_type_t; + +typedef enum { + GPIO_MODE_INPUT = GPIO_MODE_DEF_INPUT, /* GPIO mode : input only */ + GPIO_MODE_OUTPUT = GPIO_MODE_DEF_OUTPUT, /* GPIO mode : output only mode */ + GPIO_MODE_OUTPUT_OD = ((GPIO_MODE_DEF_OUTPUT)|(GPIO_MODE_DEF_OD)), /* GPIO mode : output only with open-drain mode */ + GPIO_MODE_INPUT_OUTPUT_OD = ((GPIO_MODE_DEF_INPUT)|(GPIO_MODE_DEF_OUTPUT)|(GPIO_MODE_DEF_OD)), /* GPIO mode : output and input with open-drain mode*/ + GPIO_MODE_INPUT_OUTPUT = ((GPIO_MODE_DEF_INPUT)|(GPIO_MODE_DEF_OUTPUT)), /* GPIO mode : output and input mode */ +} gpio_mode_t; + +typedef enum { + GPIO_PULLUP_DISABLE = 0x0, /* disable GPIO pull-up resistor */ + GPIO_PULLUP_ENABLE = 0x1, /* enable GPIO pull-up resistor */ +} gpio_pullup_t; + +typedef enum { + GPIO_PULLDOWN_DISABLE = 0x0, /* disable GPIO pull-down resistor */ + GPIO_PULLDOWN_ENABLE = 0x1, /* enable GPIO pull-down resistor */ +} gpio_pulldown_t; + +typedef struct { + uint64_t pin_bit_mask; /* GPIO pin: set with bit mask, each bit maps to a GPIO */ + gpio_mode_t mode; /* GPIO mode: set input/output mode */ + gpio_pullup_t pull_up_en; /* GPIO pull-up */ + gpio_pulldown_t pull_down_en; /* GPIO pull-down */ + gpio_int_type_t intr_type; /* GPIO interrupt type */ +} gpio_config_t; + +typedef enum { + GPIO_LOW_LEVEL = 0, + GPIO_HIGH_LEVEL = 1, + GPIO_LEVEL_ERR, +} gpio_level_t; + +typedef enum { + GPIO_PULLUP_ONLY, /* Pad pull up */ + GPIO_PULLDOWN_ONLY, /* Pad pull down */ + GPIO_PULLUP_PULLDOWN, /* Pad pull up + pull down*/ + GPIO_FLOATING, /* Pad floating */ +} gpio_pull_mode_t; + +typedef void (*gpio_event_callback)(gpio_num_t gpio_intr_num); + +/** \defgroup Driver_APIs Driver APIs + * @brief Driver APIs + */ + +/** @addtogroup Driver_APIs + * @{ + */ + +/** \defgroup GPIO_Driver_APIs GPIO Driver APIs + * @brief GPIO APIs + */ + +/** @addtogroup GPIO_Driver_APIs + * @{ + */ + +/** + * @brief GPIO common configuration + * + * Use this Function ,Configure GPIO's Mode,pull-up,PullDown,IntrType + * + * @parameter[in] pGPIOConfig + * pGPIOConfig.pin_bit_mask : Configure GPIO pins bits,set this parameter with bit mask. + * If you want to configure GPIO34 and GPIO16, pin_bit_mask=GPIO_Pin_16|GPIO_Pin_34; + * pGPIOConfig.mode : Configure GPIO mode,such as output ,input... + * pGPIOConfig.pull_up_en : Enable or Disable pull-up + * pGPIOConfig.pull_down_en : Enable or Disable pull-down + * pGPIOConfig.intr_type : Configure GPIO interrupt trigger type + * @return ESP_OK: success ; + * ESP_ERR_INVALID_ARG: parameter error + * ESP_FAIL : GPIO error + * + */ +esp_err_t gpio_config(gpio_config_t *pGPIOConfig); + + +/** + * @brief GPIO set interrupt trigger type + * + * @parameter[in] gpio_num : GPIO number. + * If you want to set output level of GPIO16, gpio_num should be GPIO_NUM_16 (16); + * @parameter[in] intr_type: interrupt type, select from gpio_int_type_t + * + * @return ESP_OK : success + * ESP_ERR_INVALID_ARG: parameter error + * + */ +esp_err_t gpio_set_intr_type(gpio_num_t gpio_num, gpio_int_type_t intr_type); + +/** + * @brief enable GPIO module interrupt signal + * + * @parameter[in] gpio_num : GPIO number. + * If you want to set output level of GPIO16, gpio_num should be GPIO_NUM_16 (16); + * + * @return ESP_OK : success + * ESP_ERR_INVALID_ARG: parameter error + * + */ +esp_err_t gpio_intr_enable(gpio_num_t gpio_num); + +/** + * @brief disable GPIO module interrupt signal + * + * @parameter[in] gpio_num : GPIO number. + * If you want to set output level of GPIO16, gpio_num should be GPIO_NUM_16 (16); + * + * @return ESP_OK : success + * ESP_ERR_INVALID_ARG: parameter error + * + */ +esp_err_t gpio_intr_disable(gpio_num_t gpio_num); + +/** + * @brief GPIO set output level + * + * @parameter[in] gpio_num : GPIO number. + * If you want to set output level of GPIO16, gpio_num should be GPIO_NUM_16 (16); + * @parameter[in] level : Output level. 0: low ; 1: high + * + * @return ESP_OK : success + * ESP_FAIL : GPIO error + * + */ +esp_err_t gpio_set_level(gpio_num_t gpio_num, uint32_t level); + +/** + * @brief GPIO get input level + * + * @parameter[in] gpio_num : GPIO number. + * If you want to get level of pin GPIO16, gpio_num should be GPIO_NUM_16 (16); + * + * @return 0 : the GPIO input level is 0 + * 1 : the GPIO input level is 1 + * + */ +int gpio_get_level(gpio_num_t gpio_num); + +/** + * @brief GPIO set direction + * + * Configure GPIO direction,such as output_only,input_only,output_and_input + * + * @parameter[in] gpio_num : Configure GPIO pins number,it should be GPIO number. + * If you want to set direction of GPIO16, gpio_num should be GPIO_NUM_16 (16); + * @parameter[in] mode : Configure GPIO direction,such as output_only,input_only,... + * + * @return ESP_OK : success + * ESP_ERR_INVALID_ARG : fail + * ESP_FAIL : GPIO error + * + */ +esp_err_t gpio_set_direction(gpio_num_t gpio_num, gpio_mode_t mode); + +/** + * @brief GPIO set pull + * + * User this Function,configure GPIO pull mode,such as pull-up,pull-down + * + * @parameter[in] gpio_num : Configure GPIO pins number,it should be GPIO number. + * If you want to set pull up or down mode for GPIO16,gpio_num should be GPIO_NUM_16 (16); + * @parameter[in] pull : Configure GPIO pull up/down mode,such as pullup_only,pulldown_only,pullup_and_pulldown,... + * + * @return ESP_OK : success + * ESP_ERR_INVALID_ARG : fail + * ESP_FAIL : GPIO error + * + */ +esp_err_t gpio_set_pull_mode(gpio_num_t gpio_num, gpio_pull_mode_t pull); + +/** + * @brief enable GPIO wake-up function. + * + * @param gpio_num_t gpio_num : GPIO number. + * + * @param gpio_int_type_t intr_type : only GPIO_INTR_LOLEVEL\GPIO_INTR_HILEVEL can be used + * + * @return ESP_OK: success + * ESP_ERR_INVALID_ARG: parameter error + */ +esp_err_t gpio_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type); + +/** + * @brief disable GPIO wake-up function. + * + * @param gpio_num_t gpio_num: GPIO number + * + * @return ESP_OK: success + * ESP_ERR_INVALID_ARG: parameter error + */ +esp_err_t gpio_wakeup_disable(gpio_num_t gpio_num); + +/** + * @brief register GPIO interrupt handler, the handler is an ISR. + * The handler will be attached to the same CPU core that this function is running on. + * Users should know that which CPU is running and then pick a INUM that is not used by system. + * We can find the information of INUM and interrupt level in soc.h. + * TODO: to move INUM options to menu_config + * @parameter uint32_t gpio_intr_num : GPIO interrupt number,check the info in soc.h, and please see the core-isa.h for more details + * @parameter void (* fn)(void* ) : interrupt handler function. + * Note that the handler function MUST be defined with attribution of "IRAM_ATTR". + * @parameter void * arg : parameter for handler function + * + * @return ESP_OK : success ; + * ESP_FAIL: gpio error + */ +esp_err_t gpio_isr_register(uint32_t gpio_intr_num, void (*fn)(void*), void * arg); + +/** + * *************** ATTENTION ********************/ +/** + * + * Each GPIO has its own separate configuration register, so we do not use + * a lock to serialize access to them. This works under the assumption that + * no situation will occur where two tasks try to configure the same GPIO + * pin simultaneously. It is up to the application developer to guarantee this. + */ + + +/*----------EXAMPLE TO CONIFGURE GPIO AS OUTPUT ------------ */ +/* gpio_config_t io_conf; + * io_conf.intr_type = GPIO_INTR_DISABLE; //disable interrupt + * io_conf.mode = GPIO_MODE_OUTPUT; //set as output mode + * io_conf.pin_bit_mask = GPIO_SEL_18 | GPIO_SEL_19; //bit mask of the pins that you want to set,e.g.GPIO18/19 + * io_conf.pull_down_en = 0; //disable pull-down mode + * io_conf.pull_up_en = 0; //disable pull-up mode + * gpio_config(&io_conf); //configure GPIO with the given settings + **/ +/*----------EXAMPLE TO CONIFGURE GPIO AS OUTPUT ------------ */ +/* io_conf.intr_type = GPIO_INTR_POSEDGE; //set posedge interrupt + * io_conf.mode = GPIO_MODE_INPUT; //set as input + * io_conf.pin_bit_mask = GPIO_SEL_4 | GPIO_SEL_5; //bit mask of the pins that you want to set, e.g.,GPIO4/5 + * io_conf.pull_down_en = 0; //disable pull-down mode + * io_conf.pull_up_en = 1; //enable pull-up mode + * gpio_config(&io_conf); //configure GPIO with the given settings + *----------EXAMPLE TO SET ISR HANDLER ----------------------*/ +/* gpio_isr_register(18,gpio_intr_test,NULL); //hook the isr handler for GPIO interrupt + * //the first parameter is INUM, you can pick one form interrupt level 1/2 which is not used by the system. + * //NOTE1:user should arrange the INUMs that used, better not to use a same INUM for different interrupt. + * //NOTE2:do not pick the INUM that already occupied by the system. + * //NOTE3:refer to soc.h to check which INUMs that can be used. + *-------------EXAMPLE OF HANDLER FUNCTION-------------------*/ +/*#include "esp_attr.h" + * void IRAM_ATTR gpio_intr_test(void* arg) + *{ + * //GPIO intr process + * ets_printf("in gpio_intr\n"); + * uint32_t gpio_num = 0; + * uint32_t gpio_intr_status = READ_PERI_REG(GPIO_STATUS_REG); //read status to get interrupt status for GPIO0-31 + * uint32_t gpio_intr_status_h = READ_PERI_REG(GPIO_STATUS1_REG);//read status1 to get interrupt status for GPIO32-39 + * SET_PERI_REG_MASK(GPIO_STATUS_W1TC_REG, gpio_intr_status); //Clear intr for gpio0-gpio31 + * SET_PERI_REG_MASK(GPIO_STATUS1_W1TC_REG, gpio_intr_status_h); //Clear intr for gpio32-39 + * do { + * if(gpio_num < 32) { + * if(gpio_intr_status & BIT(gpio_num)) { //gpio0-gpio31 + * ets_printf("Intr GPIO%d ,val: %d\n",gpio_num,gpio_get_level(gpio_num)); + * //This is an isr handler, you should post an event to process it in RTOS queue. + * } + * } else { + * if(gpio_intr_status_h & BIT(gpio_num - 32)) { + * ets_printf("Intr GPIO%d, val : %d\n",gpio_num,gpio_get_level(gpio_num)); + * //This is an isr handler, you should post an event to process it in RTOS queue. + * } + * } + * } while(++gpio_num < GPIO_PIN_COUNT); + *} + *----EXAMPLE OF I2C CONFIG AND PICK SIGNAL FOR IO MATRIX---*/ +/* gpio_config_t io_conf; + * io_conf.intr_type = GPIO_INTR_DISABLE; //disable interrupt + * io_conf.mode = GPIO_MODE_INPUT_OUTPUT_OD; //set as output mode + * io_conf.pin_bit_mask = GPIO_SEL_21 | GPIO_SEL_22; //bit mask of the pins that you want to set,e.g.GPIO21/22 + * io_conf.pull_down_en = 0; //disable pull-down mode + * io_conf.pull_up_en = 1; //enable pull-up mode + * gpio_config(&io_conf); //configure GPIO with the given settings + * gpio_matrix_out(21, EXT_I2C_SCL_O_IDX, 0, 0); //set output signal for io_matrix + * gpio_matrix_out(22, EXT_I2C_SDA_O_IDX, 0, 0); //set output signal for io_matrix + * gpio_matrix_in( 22, EXT_I2C_SDA_I_IDX, 0); //set input signal for io_matrix + * + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_GPIO_H_ */ diff --git a/tools/sdk/include/driver/driver/ledc.h b/tools/sdk/include/driver/driver/ledc.h new file mode 100644 index 00000000..79a6c7f9 --- /dev/null +++ b/tools/sdk/include/driver/driver/ledc.h @@ -0,0 +1,406 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _DRIVER_LEDC_H_ +#define _DRIVER_LEDC_H_ +#include "esp_err.h" +#include "soc/soc.h" +#include "soc/ledc_reg.h" +#include "soc/ledc_reg.h" +#include "soc/ledc_struct.h" +#include "driver/gpio.h" +#include "driver/periph_ctrl.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define LEDC_APB_CLK_HZ (APB_CLK_FREQ) +#define LEDC_REF_CLK_HZ (1*1000000) + +typedef enum { + LEDC_HIGH_SPEED_MODE = 0, /*LEDC high speed speed_mode */ + //in this version, we only support high speed speed_mode. We will access low speed speed_mode later + //LEDC_LOW_SPEED_MODE, /*LEDC low speed speed_mode */ + LEDC_SPEED_MODE_MAX, +} ledc_mode_t; + +typedef enum { + LEDC_INTR_DISABLE = 0, /*Disable LEDC interrupt */ + LEDC_INTR_FADE_END, /*Enable LEDC interrupt */ +} ledc_intr_type_t; + +typedef enum { + LEDC_DUTY_DIR_DECREASE = 0, /*LEDC duty decrease direction */ + LEDC_DUTY_DIR_INCREASE = 1, /*LEDC duty increase direction */ +} ledc_duty_direction_t; + +typedef enum { + LEDC_REF_TICK = 0, /*LEDC timer clock divided from reference tick(1Mhz) */ + LEDC_APB_CLK, /*LEDC timer clock divided from APB clock(80Mhz)*/ +} ledc_clk_src_t; + +typedef enum { + LEDC_TIMER_0 = 0, /*LEDC source timer TIMER0 */ + LEDC_TIMER_1, /*LEDC source timer TIMER1 */ + LEDC_TIMER_2, /*LEDC source timer TIMER2 */ + LEDC_TIMER_3, /*LEDC source timer TIMER3 */ +} ledc_timer_t; + +typedef enum { + LEDC_CHANNEL_0 = 0, /*LEDC channel 0 */ + LEDC_CHANNEL_1, /*LEDC channel 1 */ + LEDC_CHANNEL_2, /*LEDC channel 2 */ + LEDC_CHANNEL_3, /*LEDC channel 3 */ + LEDC_CHANNEL_4, /*LEDC channel 4 */ + LEDC_CHANNEL_5, /*LEDC channel 5 */ + LEDC_CHANNEL_6, /*LEDC channel 6 */ + LEDC_CHANNEL_7, /*LEDC channel 7 */ +} ledc_channel_t; + +typedef enum { + LEDC_TIMER_10_BIT = 10, /*LEDC PWM depth 10Bit */ + LEDC_TIMER_11_BIT = 11, /*LEDC PWM depth 11Bit */ + LEDC_TIMER_12_BIT = 12, /*LEDC PWM depth 12Bit */ + LEDC_TIMER_13_BIT = 13, /*LEDC PWM depth 13Bit */ + LEDC_TIMER_14_BIT = 14, /*LEDC PWM depth 14Bit */ + LEDC_TIMER_15_BIT = 15, /*LEDC PWM depth 15Bit */ +} ledc_timer_bit_t; + +typedef struct { + int gpio_num; /*the LEDC output gpio_num, if you want to use gpio16, gpio_num = 16*/ + ledc_mode_t speed_mode; /*LEDC speed speed_mode, high-speed mode or low-speed mode*/ + ledc_channel_t channel; /*LEDC channel(0 - 7)*/ + ledc_intr_type_t intr_type; /*configure interrupt, Fade interrupt enable or Fade interrupt disable*/ + ledc_timer_t timer_sel; /*Select the timer source of channel (0 - 3)*/ + uint32_t duty; /*LEDC channel duty, the duty range is [0, (2**bit_num) - 1], */ +} ledc_channel_config_t; + +typedef struct { + ledc_mode_t speed_mode; /*LEDC speed speed_mode, high-speed mode or low-speed mode*/ + ledc_timer_bit_t bit_num; /*LEDC channel duty depth*/ + ledc_timer_t timer_num; /*The timer source of channel (0 - 3)*/ + uint32_t freq_hz; /*LEDC timer frequency(Hz)*/ +} ledc_timer_config_t; + + +/** + * @brief LEDC channel configuration + * + * User this Function, configure LEDC channel with the given channel/output gpio_num/interrupt/source timer/frequency(Hz)/LEDC depth + * + * @param[in] ledc_channel_config_t + * ledc_channel_config_t.speed_mode : LEDC speed speed_mode + * ledc_channel_config_t.gpio_num : LEDC output gpio_num, if you want to use gpio16, ledc_channel_config_t.gpio_num = 16 + * ledc_channel_config_t.channel : LEDC channel(0 - 7) + * ledc_channel_config_t.intr_type : configure interrupt, Fade interrupt enable or Fade interrupt disable + * ledc_channel_config_t.timer_sel : Select the timer source of channel (0 - 3), high speed channel must bind with high speed timer. + * ledc_channel_config_t.duty : LEDC channel duty, the duty range is [0, (2**timer_bit_num) - 1], + * @return ESP_OK: success + * ESP_ERR_INVALID_ARG: parameter error + * + */ +esp_err_t ledc_channel_config(ledc_channel_config_t* ledc_conf); + +/** + * @brief LEDC timer configuration + * + * User this Function, configure LEDC timer with the given source timer/frequency(Hz)/bit_num + * + * @param[in] ledc_timer_config_t + * ledc_timer_config_t.speed_mode : LEDC speed speed_mode + * ledc_timer_config_t.timer_num : Select the timer source of channel (0 - 3) + * ledc_timer_config_t.freq_hz : LEDC channel frequency(Hz), + * ledc_timer_config_t.bit_num : LEDC channel duty depth + * @return ESP_OK: success + * ESP_ERR_INVALID_ARG: parameter error + * ESP_FAIL: Can not find a proper pre-divider number base on the given frequency and the current bit_num. + * + */ +esp_err_t ledc_timer_config(ledc_timer_config_t* timer_conf); + +/** + * @brief LEDC update channel parameters + * + * Call this function to activate the LEDC updated parameters. + * After ledc_set_duty, ledc_set_fade, we need to call this function to update the settings. + * + * @param[in] speed_mode : select the LEDC speed_mode, high-speed mode and low-speed mode, now we only support high-speed mode. We will access low-speed mode in next version + * + * @param[in] channel : LEDC channel(0-7), select from ledc_channel_t + * + * @return ESP_OK: success + * ESP_ERR_INVALID_ARG: parameter error + * + */ +esp_err_t ledc_update_duty(ledc_mode_t speed_mode, ledc_channel_t channel); + +/** + * @brief LEDC stop + * + * Disable LEDC output, and set idle level + * + * @param[in] speed_mode : select the LEDC speed_mode, high-speed mode and low-speed mode, now we only support high-speed mode. We will access low-speed mode in next version + * + * @param[in] channel : LEDC channel(0-7), select from ledc_channel_t + * + * @return ESP_OK: success + * ESP_ERR_INVALID_ARG: parameter error + */ +esp_err_t ledc_stop(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t idle_level); + +/** + * @brief LEDC set channel frequency(Hz) + * + * Set LEDC frequency(Hz) + * + * @param[in] speed_mode : select the LEDC speed_mode, high-speed mode and low-speed mode, now we only support high-speed mode. We will access low-speed mode in next version + * + * @param[in] timer_num : LEDC timer index(0-3), select from ledc_timer_t + * + * @param[in] freq_hz : set the LEDC frequency + * + * @return ESP_OK: success + * ESP_ERR_INVALID_ARG: parameter error + * ESP_FAIL: Can not find a proper pre-divider number base on the given frequency and the current bit_num. + */ +esp_err_t ledc_set_freq(ledc_mode_t speed_mode, ledc_timer_t timer_num, uint32_t freq_hz); + +/** + * @brief LEDC get channel frequency(Hz) + * + * @param[in] speed_mode : select the LEDC speed_mode, high-speed mode and low-speed mode, now we only support high-speed mode. We will access low-speed mode in next version + * + * @param[in] timer_num : LEDC timer index(0-3), select from ledc_timer_t + * + * @return 0 : error + * others : current LEDC frequency + * + */ +uint32_t ledc_get_freq(ledc_mode_t speed_mode, ledc_timer_t timer_num); + +/** + * @brief LEDC set duty + * + * Set LEDC duty, After the function calls the ledc_update_duty function, the function can take effect. + * + * @param[in] speed_mode : select the LEDC speed_mode, high-speed mode and low-speed mode, now we only support high-speed mode. We will access low-speed mode in next version + * + * @param[in] channel : LEDC channel(0-7), select from ledc_channel_t + * + * @param[in] duty : set the LEDC duty, the duty range is [0, (2**bit_num) - 1] + * + * @return ESP_OK: success + * ESP_ERR_INVALID_ARG: parameter error + */ +esp_err_t ledc_set_duty(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t duty); + +/** + * @brief LEDC get duty + * + * @param[in] speed_mode : select the LEDC speed_mode, high-speed mode and low-speed mode, now we only support high-speed mode. We will access low-speed mode in next version + * + * @param[in] channel : LEDC channel(0-7), select from ledc_channel_t + * + * + * @return -1: parameter error + * other value: current LEDC duty + * + */ +int ledc_get_duty(ledc_mode_t speed_mode, ledc_channel_t channel); + +/** + * @brief LEDC set gradient + * + * Set LEDC gradient, After the function calls the ledc_update_duty function, the function can take effect. + * + * @param[in] speed_mode : select the LEDC speed_mode, high-speed mode and low-speed mode, now we only support high-speed mode. We will access low-speed mode in next version + * + * @param[in] channel : LEDC channel(0-7), select from ledc_channel_t + * + * @param[in] duty : set the start of the gradient duty, the duty range is [0, (2**bit_num) - 1] + * + * @param[in] gradule_direction : set the direction of the gradient + * + * @param[in] step_num : set the number of the gradient + * + * @param[in] duty_cyle_num : set how many LEDC tick each time the gradient lasts + * + * @param[in] duty_scale : set gradient change amplitude + * + * @return ESP_OK : success + * ESP_ERR_INVALID_ARG : parameter error + */ +esp_err_t ledc_set_fade(ledc_mode_t speed_mode, uint32_t channel, uint32_t duty, ledc_duty_direction_t gradule_direction, + uint32_t step_num, uint32_t duty_cyle_num, uint32_t duty_scale); + +/** + * @brief register LEDC interrupt handler, the handler is an ISR. + * The handler will be attached to the same CPU core that this function is running on. + * Users should know that which CPU is running and then pick a INUM that is not used by system. + * We can find the information of INUM and interrupt level in soc.h. + * TODO: to move INUM options to menu_config + * @param[in] uint32_t ledc_intr_num : LEDC interrupt number, check the info in soc.h, and please see the core-isa.h for more details + * @param[in] void (* fn)(void* ) : interrupt handler function. + * Note that the handler function MUST be defined with attribution of "IRAM_ATTR". + * @param[in] void * arg : parameter for handler function + * + * @return ESP_OK : success ; + * ESP_ERR_INVALID_ARG : function ptr error. + */ +esp_err_t ledc_isr_register(uint32_t ledc_intr_num, void (*fn)(void*), void * arg); + +/** + * @brief configure LEDC settings + * + * @param[in] speed_mode : select the LEDC speed_mode, high-speed mode and low-speed mode, now we only support high-speed mode. We will access low-speed mode in next version + * + * @param[in] timer_sel : timer index(0-3), there are 4 timers in LEDC module + * + * @param[in] div_num : timer clock divide number, the timer clock is divided from the selected clock source + * + * @param[in] bit_num : the count number of one period, counter range is 0 ~ ((2 ** bit_num) - 1) + * + * @param[in] clk_src : select LEDC source clock. + * + * @return -1: parameter error + * other value: current LEDC duty + * + */ +esp_err_t ledc_timer_set(ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t div_num, uint32_t bit_num, ledc_clk_src_t clk_src); + +/** + * @brief reset LEDC timer + * + * @param[in] speed_mode : select the LEDC speed_mode, high-speed mode and low-speed mode, now we only support high-speed mode. We will access low-speed mode in next version + * + * @param[in] timer_sel : LEDC timer index(0-3), select from ledc_timer_t + * + * + * @return ESP_ERR_INVALID_ARG: parameter error + * ESP_OK: success + * + */ +esp_err_t ledc_timer_rst(ledc_mode_t speed_mode, uint32_t timer_sel); + +/** + * @brief pause LEDC timer counter + * + * @param[in] speed_mode : select the LEDC speed_mode, high-speed mode and low-speed mode, now we only support high-speed mode. We will access low-speed mode in next version + * + * @param[in] timer_sel : LEDC timer index(0-3), select from ledc_timer_t + * + * + * @return ESP_ERR_INVALID_ARG: parameter error + * ESP_OK: success + * + */ +esp_err_t ledc_timer_pause(ledc_mode_t speed_mode, uint32_t timer_sel); + +/** + * @brief pause LEDC timer resume + * + * @param[in] speed_mode : select the LEDC speed_mode, high-speed mode and low-speed mode, now we only support high-speed mode. We will access low-speed mode in next version + * + * @param[in] timer_sel : LEDC timer index(0-3), select from ledc_timer_t + * + * + * @return ESP_ERR_INVALID_ARG: parameter error + * ESP_OK: success + * + */ +esp_err_t ledc_timer_resume(ledc_mode_t speed_mode, uint32_t timer_sel); + +/** + * @brief bind LEDC channel with the selected timer + * + * @param[in] speed_mode : select the LEDC speed_mode, high-speed mode and low-speed mode, now we only support high-speed mode. We will access low-speed mode in next version + * + * @param[in] channel : LEDC channel index(0-7), select from ledc_channel_t + * + * @param[in] timer_idx : LEDC timer index(0-3), select from ledc_timer_t + * + * + * @return ESP_ERR_INVALID_ARG: parameter error + * ESP_OK: success + * + */ +esp_err_t ledc_bind_channel_timer(ledc_mode_t speed_mode, uint32_t channel, uint32_t timer_idx); + +/***************************EXAMPLE********************************** + * + * + * ----------------EXAMPLE OF LEDC SETTING --------------------- + * //1. enable LEDC + * periph_module_enable(PERIPH_LEDC_MODULE); //enable LEDC module, or you can not set any register of it. + * + * //2. set LEDC timer + * ledc_timer_config_t timer_conf = { + * .bit_num = LEDC_TIMER_12_BIT, //set timer counter bit number + * .freq_hz = 1000, //set frequency of pwm, here, 1000Hz + * .speed_mode = LEDC_HIGH_SPEED_MODE //timer mode, + * .timer_num = LEDC_TIMER_0, //timer number + * }; + * ledc_timer_config(&timer_conf); //setup timer. + * + * //3. set LEDC channel + * ledc_channel_config_t ledc_conf = { + * .channel = LEDC_CHANNEL_0; //set LEDC channel 0 + * .duty = 1000; //set the duty for initialization.(duty range is 0 ~ ((2**bit_num)-1) + * .gpio_num = 16; //GPIO number + * .intr_type = LEDC_INTR_FADE_END; //GPIO INTR TYPE, as an example, we enable fade_end interrupt here. + * .speed_mode = LEDC_HIGH_SPEED_MODE; //set LEDC mode, from ledc_mode_t + * .timer_sel = LEDC_TIMER_0; //set LEDC timer source, if different channel use one timer, the frequency and bit_num of these channels should be the same + * } + * ledc_channel_config(&ledc_conf); //setup the configuration + * + * ----------------EXAMPLE OF SETTING DUTY --- ----------------- + * uint32_t ledc_channel = LEDC_CHANNEL_0; //LEDC channel(0-73) + * uint32_t duty = 2000; //duty range is 0 ~ ((2**bit_num)-1) + * LEDC_set_duty(LEDC_HIGH_SPEED_MODE, ledc_channel, duty); //set speed mode, channel, and duty. + * ledc_update_duty(LEDC_HIGH_SPEED_MODE, ledc_channel); //after set duty, we need to call ledc_update_duty to update the settings. + * + * + * ----------------EXAMPLE OF LEDC INTERRUPT ------------------ + * //we have fade_end interrupt and counter overflow interrupt. we just give an example of fade_end interrupt here. + * ledc_isr_register(18, ledc_isr_handler, NULL); //hook the isr handler for LEDC interrupt + * //the first parameter is INUM, you can pick one form interrupt level 1/2 which is not used by the system. + * //NOTE1:user should arrange the INUMs that used, better not to use a same INUM for different interrupt source. + * //NOTE2:do not pick the INUM that already occupied by the system. + * //NOTE3:refer to soc.h to check which INUMs that can be used. + * ----------------EXAMPLE OF INTERRUPT HANDLER --------------- + * #include "esp_attr.h" + * void IRAM_ATTR ledc_isr_handler(void* arg) //we should add 'IRAM_ATTR' attribution when we declare the isr function + * { + * uint32_t intr_st = LEDC.int_st.val; //read LEDC interrupt status. + * + * //you will find which channels have triggered fade_end interrupt here, + * //then, you can post some event to RTOS queue to process the event. + * //later we will add a queue in the driver code. + * + * LEDC.int_clr.val = intr_st; //clear LEDC interrupt status. + * } + * + * + *--------------------------END OF EXAMPLE -------------------------- + */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_LEDC_H_ */ diff --git a/tools/sdk/include/driver/driver/periph_ctrl.h b/tools/sdk/include/driver/driver/periph_ctrl.h new file mode 100644 index 00000000..3faa347b --- /dev/null +++ b/tools/sdk/include/driver/driver/periph_ctrl.h @@ -0,0 +1,70 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _DRIVER_PERIPH_CTRL_H_ +#define _DRIVER_PERIPH_CTRL_H_ +#include "esp_err.h" +#include "soc/soc.h" +#include "soc/dport_reg.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PERIPH_LEDC_MODULE = 0, + PERIPH_UART0_MODULE, + PERIPH_UART1_MODULE, + PERIPH_UART2_MODULE, + PERIPH_I2C0_MODULE, + PERIPH_I2C1_MODULE, + PERIPH_I2S0_MODULE, + PERIPH_I2S1_MODULE, + PERIPH_TIMG0_MODULE, + PERIPH_TIMG1_MODULE, + PERIPH_PWM0_MODULE, + PERIPH_PWM1_MODULE, + PERIPH_PWM2_MODULE, + PERIPH_PWM3_MODULE, + PERIPH_UHCI0_MODULE, + PERIPH_UHCI1_MODULE, +} periph_module_t; + +/** + * @brief enable peripheral module + * + * @param[in] periph : Peripheral module name + * + * + * @return NULL + * + */ +void periph_module_enable(periph_module_t periph); + +/** + * @brief disable peripheral module + * + * @param[in] periph : Peripheral module name + * + * + * @return NULL + * + */ +void periph_module_disable(periph_module_t periph); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_PERIPH_CTRL_H_ */ diff --git a/tools/sdk/include/esp32/esp_attr.h b/tools/sdk/include/esp32/esp_attr.h new file mode 100644 index 00000000..156d2957 --- /dev/null +++ b/tools/sdk/include/esp32/esp_attr.h @@ -0,0 +1,41 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef __ESP_ATTR_H__ +#define __ESP_ATTR_H__ + +#define ROMFN_ATTR + +//Normally, the linker script will put all code and rodata in flash, +//and all variables in shared RAM. These macros can be used to redirect +//particular functions/variables to other memory regions. + +// Forces code into IRAM instead of flash +#define IRAM_ATTR __attribute__((section(".iram1"))) + +// Forces data into DRAM instead of flash +#define DRAM_ATTR __attribute__((section(".dram1"))) + +// Forces code into RTC fast memory +#define RTC_IRAM_ATTR __attribute__((section(".rtc.text"))) + +// Forces data into RTC slow memory +// Any variable marked with this attribute will keep its value +// during a deep sleep / wake cycle. +#define RTC_DATA_ATTR __attribute__((section(".rtc.data"))) + +// Forces read-only data into RTC slow memory +// Makes constant data available to RTC wake stubs (see esp_deepsleep.h) +#define RTC_RODATA_ATTR __attribute__((section(".rtc.rodata"))) + +#endif /* __ESP_ATTR_H__ */ diff --git a/tools/sdk/include/esp32/esp_deepsleep.h b/tools/sdk/include/esp32/esp_deepsleep.h new file mode 100644 index 00000000..3683a8ee --- /dev/null +++ b/tools/sdk/include/esp32/esp_deepsleep.h @@ -0,0 +1,137 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef __ESP_DEEPSLEEP_H__ +#define __ESP_DEEPSLEEP_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup Deep_Sleep_API Deep Sleep API + * @brief API for putting device into deep sleep + */ + +/** @addtogroup Deep_Sleep_API + * @{ + */ + +/** + * @brief Set the chip to deep-sleep mode. + * + * The device will automatically wake up after the deep-sleep time set + * by the users. Upon waking up, the device boots up from user_init. + * + * @attention The parameter time_in_us to be "uint64" is for further development. + * Only the low 32 bits of parameter time_in_us are avalable now. + * + * @param uint64 time_in_us : deep-sleep time, only the low 32bits are avalable now. unit: microsecond + * + * @return null + */ +void system_deep_sleep(uint64_t time_in_us); + +/** + * @brief Default stub to run on wake from deep sleep. + * + * Allows for executing code immediately on wake from sleep, before + * the software bootloader or esp-idf app has started up. + * + * This function is weak-linked, so you can implement your own version + * to run code immediately when the chip wakes from + * sleep. + * + * For example: + * @code + * void RTC_IRAM_ATTR esp_wake_deep_sleep(void) { + * esp_default_wake_deep_sleep(); + * // Add additional functionality here + * } + * + * (Implementing this function is not required for normal operation, + * in the usual case your app will start normally when waking from + * deep sleep.) + * + * esp_wake_deep_sleep() functionality is limited: + * + * - Runs immediately on wake, so most of the SoC is freshly reset - + * flash is unmapped and hardware is otherwise uninitialised. + * + * - Can only call functions implemented in ROM, or marked RTC_IRAM_ATTR. + * + * - Static variables marked RTC_DATA_ATTR will have initial values on + * cold boot, and maintain these values between sleep/wake cycles. + * + * - Read-only data should be marked RTC_RODATA_ATTR. Strings must be + * declared as variables also using RTC_RODATA_ATTR, like this: + * RTC_RODATA_ATTR const char message[] = "Hello from very early boot!\n"; + * + * - Any other static memory will not be initialised (either to zero, + * or to any predefined value). + * + * + * - If you implement your own stub, the first call the stub makes + should be to esp_default_wake_deep_sleep(). + */ +void esp_wake_deep_sleep(void); + +/** + * @brief Function type for stub to run on wake from sleep. + * + */ +typedef void (*esp_deep_sleep_wake_stub_fn_t)(void); + +/** + * @brief Install a new stub at runtime to run on wake from deep sleep + * + * If implementing esp_wake_deep_sleep() then it is not necessary to + * call this function. + * + * However, it is possible to call this function to substitute a + * different deep sleep stub. Any function used as a deep sleep stub + * must be marked RTC_IRAM_ATTR, and must obey the same rules given + * for esp_wake_deep_sleep(). + */ +void esp_set_deep_sleep_wake_stub(esp_deep_sleep_wake_stub_fn_t new_stub); + +/** + * @brief Return current wake from deep sleep stub, or NULL if + * no stub is installed. + */ +esp_deep_sleep_wake_stub_fn_t esp_get_deep_sleep_wake_stub(void); + +/* The default esp-idf-provided esp_wake_deep_sleep() stub. + + If you replace esp_wake_deep_sleep() in your program, or use + esp_set_deep_sleep_wake_stub(), then it is recommended you call + esp_default_wake_deep_sleep() as the first function in your stub. +*/ +void esp_default_wake_deep_sleep(void); + +/** + * @} + */ + + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ESP_SYSTEM_H__ */ diff --git a/tools/sdk/include/esp32/esp_err.h b/tools/sdk/include/esp32/esp_err.h new file mode 100644 index 00000000..4f013f91 --- /dev/null +++ b/tools/sdk/include/esp32/esp_err.h @@ -0,0 +1,46 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef __ESP_ERR_H__ +#define __ESP_ERR_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef int32_t esp_err_t; + +/* Definitions for error constants. */ + +#define ESP_OK 0 +#define ESP_FAIL -1 + +#define ESP_ERR_NO_MEM 0x101 +#define ESP_ERR_INVALID_ARG 0x102 +#define ESP_ERR_INVALID_STATE 0x103 + +/** + * Macro which can be used to check the error code, + * and terminate the program in case the code is not ESP_OK. + * Prints the failed statement to serial output. + */ +#define ESP_ERROR_CHECK(x) do { esp_err_t rc = (x); if (rc != ESP_OK) { assert(0 && #x);} } while(0); + +#ifdef __cplusplus +} +#endif + +#endif /* __ESP_ERR_H__ */ diff --git a/tools/sdk/include/esp32/esp_event.h b/tools/sdk/include/esp32/esp_event.h new file mode 100644 index 00000000..0ca4ca90 --- /dev/null +++ b/tools/sdk/include/esp32/esp_event.h @@ -0,0 +1,141 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef __ESP_EVENT_H__ +#define __ESP_EVENT_H__ + +#include +#include + +#include "esp_err.h" +#include "esp_wifi_types.h" +#include "tcpip_adapter.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + SYSTEM_EVENT_WIFI_READY = 0, /**< ESP32 WiFi ready */ + SYSTEM_EVENT_SCAN_DONE, /**< ESP32 finish scanning AP */ + SYSTEM_EVENT_STA_START, /**< ESP32 station start */ + SYSTEM_EVENT_STA_STOP, /**< ESP32 station stop */ + SYSTEM_EVENT_STA_CONNECTED, /**< ESP32 station connected to AP */ + SYSTEM_EVENT_STA_DISCONNECTED, /**< ESP32 station disconnected from AP */ + SYSTEM_EVENT_STA_AUTHMODE_CHANGE, /**< the auth mode of AP connected by ESP32 station changed */ + SYSTEM_EVENT_STA_GOT_IP, /**< ESP32 station got IP from connected AP */ + SYSTEM_EVENT_AP_START, /**< ESP32 soft-AP start */ + SYSTEM_EVENT_AP_STOP, /**< ESP32 soft-AP stop */ + SYSTEM_EVENT_AP_STACONNECTED, /**< a station connected to ESP32 soft-AP */ + SYSTEM_EVENT_AP_STADISCONNECTED, /**< a station disconnected from ESP32 soft-AP */ + SYSTEM_EVENT_AP_PROBEREQRECVED, /**< Receive probe request packet in soft-AP interface */ + SYSTEM_EVENT_MAX +} system_event_id_t; + +typedef struct { + uint32_t status; /**< status of scanning APs */ + uint8_t number; + uint8_t scan_id; +} system_event_sta_scan_done_t; + +typedef struct { + uint8_t ssid[32]; /**< SSID of connected AP */ + uint8_t ssid_len; /**< SSID length of connected AP */ + uint8_t bssid[6]; /**< BSSID of connected AP*/ + uint8_t channel; /**< channel of connected AP*/ + wifi_auth_mode_t authmode; +} system_event_sta_connected_t; + +typedef struct { + uint8_t ssid[32]; /**< SSID of disconnected AP */ + uint8_t ssid_len; /**< SSID length of disconnected AP */ + uint8_t bssid[6]; /**< BSSID of disconnected AP */ + uint8_t reason; /**< reason of disconnection */ +} system_event_sta_disconnected_t; + +typedef struct { + wifi_auth_mode_t old_mode; /**< the old auth mode of AP */ + wifi_auth_mode_t new_mode; /**< the new auth mode of AP */ +} system_event_sta_authmode_change_t; + +typedef struct { + tcpip_adapter_ip_info_t ip_info; +} system_event_sta_got_ip_t; + +typedef struct { + uint8_t mac[6]; /**< MAC address of the station connected to ESP32 soft-AP */ + uint8_t aid; /**< the aid that ESP32 soft-AP gives to the station connected to */ +} system_event_ap_staconnected_t; + +typedef struct { + uint8_t mac[6]; /**< MAC address of the station disconnects to ESP32 soft-AP */ + uint8_t aid; /**< the aid that ESP32 soft-AP gave to the station disconnects to */ +} system_event_ap_stadisconnected_t; + +typedef struct { + int rssi; /**< Received probe request signal strength */ + uint8_t mac[6]; /**< MAC address of the station which send probe request */ +} system_event_ap_probe_req_rx_t; + +typedef union { + system_event_sta_connected_t connected; /**< ESP32 station connected to AP */ + system_event_sta_disconnected_t disconnected; /**< ESP32 station disconnected to AP */ + system_event_sta_scan_done_t scan_done; /**< ESP32 station scan (APs) done */ + system_event_sta_authmode_change_t auth_change; /**< the auth mode of AP ESP32 station connected to changed */ + system_event_sta_got_ip_t got_ip; /**< ESP32 station got IP */ + system_event_ap_staconnected_t sta_connected; /**< a station connected to ESP32 soft-AP */ + system_event_ap_stadisconnected_t sta_disconnected; /**< a station disconnected to ESP32 soft-AP */ + system_event_ap_probe_req_rx_t ap_probereqrecved; /**< ESP32 soft-AP receive probe request packet */ +} system_event_info_t; + +typedef struct { + system_event_id_t event_id; /**< event ID */ + system_event_info_t event_info; /**< event information */ +} system_event_t; + +typedef esp_err_t (*system_event_handler_t)(system_event_t *event); + +/** + * @brief Send a event to event task + * + * @attention 1. Other task/modules, such as the TCPIP module, can call this API to send an event to event task + * + * @param system_event_t * event : event + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_event_send(system_event_t *event); + +/** + * @brief Default event handler for system events + * + * This function performs default handling of system events. + * When using esp_event_loop APIs, it is called automatically before invoking the user-provided + * callback function. + * + * Applications which implement a custom event loop must call this function + * as part of event processing. + * + * @param event pointer to event to be handled + * @return ESP_OK if an event was handled successfully + */ +esp_err_t esp_event_process_default(system_event_t *event); + + +#ifdef __cplusplus +} +#endif + +#endif /* __ESP_EVENT_H__ */ diff --git a/tools/sdk/include/esp32/esp_event_loop.h b/tools/sdk/include/esp32/esp_event_loop.h new file mode 100644 index 00000000..97672aed --- /dev/null +++ b/tools/sdk/include/esp32/esp_event_loop.h @@ -0,0 +1,81 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef __ESP_EVENT_LOOP_H__ +#define __ESP_EVENT_LOOP_H__ + +#include +#include + +#include "esp_err.h" +#include "esp_event.h" +#include "freertos/FreeRTOS.h" +#include "freertos/queue.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Application specified event callback function + * + * @param void *ctx : reserved for user + * @param system_event_t *event : event type defined in this file + * + * @return ESP_OK : succeed + * @return others : fail + */ +typedef esp_err_t (*system_event_cb_t)(void *ctx, system_event_t *event); + +/** + * @brief Initialize event loop + * Create the event handler and task + * + * @param system_event_cb_t cb : application specified event callback, it can be modified by call esp_event_set_cb + * @param void *ctx : reserved for user + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_event_loop_init(system_event_cb_t cb, void *ctx); + +/** + * @brief Set application specified event callback function + * + * @attention 1. If cb is NULL, means application don't need to handle + * If cb is not NULL, it will be call when an event is received, after the default event callback is completed + * + * @param system_event_cb_t cb : callback + * @param void *ctx : reserved for user + * + * @return system_event_cb_t : old callback + */ +system_event_cb_t esp_event_loop_set_cb(system_event_cb_t cb, void *ctx); + +/** + * @brief Get the queue used by event loop + * + * @attention : currently this API is used to initialize "q" parameter + * of wifi_init structure. + * + * @return QueueHandle_t : event queue handle + */ +QueueHandle_t esp_event_loop_get_queue(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* __ESP_EVENT_LOOP_H__ */ diff --git a/tools/sdk/include/esp32/esp_intr.h b/tools/sdk/include/esp32/esp_intr.h new file mode 100644 index 00000000..e138133f --- /dev/null +++ b/tools/sdk/include/esp32/esp_intr.h @@ -0,0 +1,209 @@ +// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef __ESP_INTR_H__ +#define __ESP_INTR_H__ + +#include "rom/ets_sys.h" +#include "freertos/xtensa_api.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define ESP_CCOMPARE_INTR_ATTACH(func, arg) \ + xt_set_interrupt_handler(ETS_CCOMPARE_INUM, (func), (void *)(arg)) + +#define ESP_EPWM_INTR_ATTACH(func, arg) \ + xt_set_interrupt_handler(ETS_EPWM_INUM, (func), (void *)(arg)) + +#define ESP_MPWM_INTR_ATTACH(func, arg) \ + xt_set_interrupt_handler(ETS_MPWM_INUM, (func), (void *)(arg)) + +#define ESP_SPI1_INTR_ATTACH(func, arg) \ + xt_set_interrupt_handler(ETS_SPI1_INUM, (func), (void *)(arg)) + +#define ESP_SPI2_INTR_ATTACH(func, arg) \ + xt_set_interrupt_handler(ETS_SPI2_INUM, (func), (void *)(arg)) + +#define ESP_SPI3_INTR_ATTACH(func, arg) \ + xt_set_interrupt_handler(ETS_SPI3_INUM, (func), (void *)(arg)) + +#define ESP_I2S0_INTR_ATTACH(func, arg) \ + xt_set_interrupt_handler(ETS_I2S0_INUM, (func), (void *)(arg)) + +#define ESP_PCNT_INTR_ATTACH(func, arg) \ + xt_set_interrupt_handler(ETS_PCNT_INUM, (func), (void *)(arg)) + +#define ESP_LEDC_INTR_ATTACH(func, arg) \ + xt_set_interrupt_handler(ETS_LEDC_INUM, (func), (void *)(arg)) + +#define ESP_WMAC_INTR_ATTACH(func, arg) \ + xt_set_interrupt_handler(ETS_WMAC_INUM, (func), (void *)(arg)) + +#define ESP_FRC_TIMER1_INTR_ATTACH(func, arg) \ + xt_set_interrupt_handler(ETS_FRC_TIMER1_INUM, (func), (void *)(arg)) + +#define ESP_FRC_TIMER2_INTR_ATTACH(func, arg) \ + xt_set_interrupt_handler(ETS_FRC_TIMER2_INUM, (func), (void *)(arg)) + +#define ESP_GPIO_INTR_ATTACH(func, arg) \ + xt_set_interrupt_handler(ETS_GPIO_INUM, (func), (void *)(arg)) + +#define ESP_UART0_INTR_ATTACH(func, arg) \ + xt_set_interrupt_handler(ETS_UART0_INUM, (func), (void *)(arg)) + +#define ESP_WDT_INTR_ATTACH(func, arg) \ + xt_set_interrupt_handler(ETS_WDT_INUM, (func), (void *)(arg)) + +#define ESP_RTC_INTR_ATTACH(func, arg) \ + xt_set_interrupt_handler(ETS_RTC_INUM, (func), (void *)(arg)) + +#define ESP_SLC_INTR_ATTACH(func, arg) \ + xt_set_interrupt_handler(ETS_SLC_INUM, (func), (void *)(arg)) + +#define ESP_RMT_CTRL_INTRL(func,arg)\ + xt_set_interrupt_handler(ETS_RMT_CTRL_INUM, (func), (void *)(arg)) + +#define ESP_INTR_ENABLE(inum) \ + xt_ints_on((1< + +typedef void (*esp_ipc_func_t)(void* arg); + +/** + * @brief Inter-processor call APIs + * + * FreeRTOS provides several APIs which can be used to communicate between + * different tasks, including tasks running on different CPUs. + * This module provides additional APIs to run some code on the other CPU. + * + * These APIs can only be used when FreeRTOS scheduler is running. + */ + + +/** + * @brief Initialize inter-processor call module. + * + * This function start two tasks, one on each CPU. These tasks are started + * with high priority. These tasks are normally inactive, waiting until one of + * the esp_ipc_call_* functions to be used. One of these tasks will be + * woken up to execute the callback provided to esp_ipc_call_nonblocking or + * esp_ipc_call_blocking. + */ +void esp_ipc_init(); + + +/** + * @brief Execute function on the given CPU + * + * This will wake a high-priority task on CPU indicated by cpu_id argument, + * and run func(arg) in the context of that task. + * This function returns as soon as the high-priority task is woken up. + * If another IPC call is already being executed, this function will also wait + * for it to complete. + * + * In single-core mode, returns ESP_ERR_INVALID_ARG for cpu_id 1. + * + * @param cpu_id CPU where function should be executed (0 or 1) + * @param func pointer to a function which should be executed + * @param arg arbitrary argument to be passed into function + * + * @return ESP_ERR_INVALID_ARG if cpu_id is invalid + * ESP_ERR_INVALID_STATE if FreeRTOS scheduler is not running + * ESP_OK otherwise + */ +esp_err_t esp_ipc_call(uint32_t cpu_id, esp_ipc_func_t func, void* arg); + + +/** + * @brief Execute function on the given CPU and wait for it to finish + * + * This will wake a high-priority task on CPU indicated by cpu_id argument, + * and run func(arg) in the context of that task. + * This function waits for func to return. + * + * In single-core mode, returns ESP_ERR_INVALID_ARG for cpu_id 1. + * + * @param cpu_id CPU where function should be executed (0 or 1) + * @param func pointer to a function which should be executed + * @param arg arbitrary argument to be passed into function + * + * @return ESP_ERR_INVALID_ARG if cpu_id is invalid + * ESP_ERR_INVALID_STATE if FreeRTOS scheduler is not running + * ESP_OK otherwise + */ +esp_err_t esp_ipc_call_blocking(uint32_t cpu_id, esp_ipc_func_t func, void* arg); + + + +#endif /* __ESP_IPC_H__ */ diff --git a/tools/sdk/include/esp32/esp_smartconfig.h b/tools/sdk/include/esp32/esp_smartconfig.h new file mode 100644 index 00000000..b30ce1a1 --- /dev/null +++ b/tools/sdk/include/esp32/esp_smartconfig.h @@ -0,0 +1,143 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef __ESP_SMARTCONFIG_H__ +#define __ESP_SMARTCONFIG_H__ +#include +#include +#include "esp_err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + SC_STATUS_WAIT = 0, /**< waiting, do not start connection in this phase */ + SC_STATUS_FIND_CHANNEL, /**< find target channel, start connection by APP in this phase */ + SC_STATUS_GETTING_SSID_PSWD, /**< getting SSID and password of target AP */ + SC_STATUS_LINK, /**< connecting to target AP */ + SC_STATUS_LINK_OVER, /**< got IP, connect to AP successfully */ +} smartconfig_status_t; + +typedef enum { + SC_TYPE_ESPTOUCH = 0, /**< protocol: ESPTouch */ + SC_TYPE_AIRKISS, /**< protocol: AirKiss */ + SC_TYPE_ESPTOUCH_AIRKISS, /**< protocol: ESPTouch and AirKiss */ +} smartconfig_type_t; + +/** + * @brief The callback of SmartConfig, executed when smart-config status changed. + * + * @param smartconfig_status_t status : status of SmartConfig: + * - if status == SC_STATUS_GETTING_SSID_PSWD, parameter void *pdata is a pointer + of smartconfig_type_t, means SmartConfig type: AirKiss or ESP-TOUCH. + * - if status == SC_STATUS_LINK, parameter void *pdata is a pointer of struct station_config; + * - if status == SC_STATUS_LINK_OVER, parameter void *pdata is a pointer of mobile + * phone's IP address, 4 bytes. This is only available in ESPTOUCH, otherwise, + * it is NULL. + * - otherwise, parameter void *pdata is NULL. + * @param void *pdata : data of SmartConfig + * + * @return null + */ +typedef void (*sc_callback_t)(smartconfig_status_t status, void *pdata); + +/** + * @brief Get the version of SmartConfig. + * + * @param null + * + * @return SmartConfig version + */ +const char *esp_smartconfig_get_version(void); + +/** + * @brief Start SmartConfig mode. + * + * Start SmartConfig mode, to connect ESP32 station to AP, by sniffing + * for special packets from the air, containing SSID and password of desired AP. + * You need to broadcast the SSID and password (e.g. from mobile device or computer) + * with the SSID and password encoded. + * + * @attention 1. This API can only be called in station mode. + * @attention 2. During SmartConfig, ESP32 station and soft-AP are disabled. + * @attention 3. Can not call esp_smartconfig_start twice before it finish, please call + * esp_smartconfig_stop first. + * @attention 4. Don't call any other APIs during SmartConfig, please call esp_smartconfig_stop first. + * + * @param sc_callback_t cb : SmartConfig callback; executed when SmartConfig status changed; + * @param uint8 log : 1, UART output logs; otherwise, UART only outputs the result. + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_smartconfig_start(sc_callback_t cb, ...); + +/** + * @brief Stop SmartConfig, free the buffer taken by esp_smartconfig_start. + * + * @attention Whether connect to AP succeed or not, this API should be called to free + * memory taken by smartconfig_start. + * + * @param null + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_smartconfig_stop(void); + +/** + * @brief Set timeout of SmartConfig. + * + * @attention SmartConfig timeout start at SC_STATUS_FIND_CHANNEL, SmartConfig will + * restart if timeout. + * + * @param uint8 time_s : range 15s~255s, offset:45s. + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_esptouch_set_timeout(uint8_t time_s); + +/** + * @brief Set protocol type of SmartConfig. + * + * @attention If users need to set the SmartConfig type, please set it before calling + * esp_smartconfig_start. + * + * @param smartconfig_type_t type : AirKiss, ESP-TOUCH or both. + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_smartconfig_set_type(smartconfig_type_t type); + +/** + * @brief Set mode of SmartConfig. default normal mode. + * + * @attention If users need to set the SmartConfig mode, please set it before calling + * esp_smartconfig_start. Different mode should match different APP(phone). + * + * @param bool enable : false-disable(default); true-enable; + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_smartconfig_fast_mode(bool enable); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/tools/sdk/include/esp32/esp_ssc.h b/tools/sdk/include/esp32/esp_ssc.h new file mode 100644 index 00000000..02893ff4 --- /dev/null +++ b/tools/sdk/include/esp32/esp_ssc.h @@ -0,0 +1,119 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef __ESP_SSC_H__ +#define __ESP_SSC_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define CMD_T_ASYNC 0x01 +#define CMD_T_SYNC 0x02 + +typedef struct cmd_s { + char *cmd_str; + uint8_t flag; + uint8_t id; + void (* cmd_func)(void); + void (* cmd_callback)(void *arg); +} ssc_cmd_t; + +#define MAX_LINE_N 127 + +typedef enum { + SSC_BR_9600 = 9600, + SSC_BR_19200 = 19200, + SSC_BR_38400 = 38400, + SSC_BR_57600 = 57600, + SSC_BR_74880 = 74880, + SSC_BR_115200 = 115200, + SSC_BR_230400 = 230400, + SSC_BR_460800 = 460800, + SSC_BR_921600 = 921600 +} SscBaudRate; + +/** \defgroup SSC_APIs SSC APIs + * @brief SSC APIs + * + * SSC means simple serial command. + * SSC APIs allows users to define their own command, users can refer to spiffs_test/test_main.c. + * + */ + +/** @addtogroup SSC_APIs + * @{ + */ + +/** + * @brief Initial the ssc function. + * + * @attention param is no use, just compatible with ESP8266, default bandrate is 115200 + * + * @param SscBaudRate bandrate : baud rate + * + * @return null + */ +void ssc_attach(SscBaudRate bandrate); + +/** + * @brief Get the length of the simple serial command. + * + * @param null + * + * @return length of the command. + */ +int ssc_param_len(void); + +/** + * @brief Get the simple serial command string. + * + * @param null + * + * @return the command. + */ +char *ssc_param_str(void); + +/** + * @brief Parse the simple serial command (ssc). + * + * @param char *pLine : [input] the ssc string + * @param char *argv[] : [output] parameters of the ssc + * + * @return the number of parameters. + */ +int ssc_parse_param(char *pLine, char *argv[]); + +/** + * @brief Register the user-defined simple serial command (ssc) set. + * + * @param ssc_cmd_t *cmdset : the ssc set + * @param uint8 cmdnum : number of commands + * @param void (* help)(void) : callback of user-guide + * + * @return null + */ +void ssc_register(ssc_cmd_t *cmdset, uint8_t cmdnum, void (* help)(void)); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ESP_SSC_H__ */ diff --git a/tools/sdk/include/esp32/esp_system.h b/tools/sdk/include/esp32/esp_system.h new file mode 100644 index 00000000..84133366 --- /dev/null +++ b/tools/sdk/include/esp32/esp_system.h @@ -0,0 +1,187 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef __ESP_SYSTEM_H__ +#define __ESP_SYSTEM_H__ + +#include + +#include "esp_err.h" +#include "esp_deepsleep.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup System_APIs System APIs + * @brief System APIs + */ + +/** @addtogroup System_APIs + * @{ + */ + +/** + * @brief Get information of the SDK version. + * + * @param null + * + * @return Information of the SDK version. + */ +const char *system_get_sdk_version(void); + +/** + * @brief Reset to default settings. + * + * Reset to default settings of the following APIs : wifi_station_set_auto_connect, + * wifi_set_phy_mode, wifi_softap_set_config related, wifi_station_set_config + * related, and wifi_set_opmode. + * + * @param null + * + * @return null + */ +void system_restore(void); + +/** + * @brief Restart system. + * + * @param null + * + * @return null + */ +void system_restart(void); + +/** + * @brief Get system time, unit: microsecond. + * + * @param null + * + * @return System time, unit: microsecond. + */ +uint32_t system_get_time(void); + +/** + * @brief Get the size of available heap. + * + * @param null + * + * @return Available heap size. + */ +uint32_t system_get_free_heap_size(void); + +/** + * @brief Get RTC time, unit: RTC clock cycle. + * + * @param null + * + * @return RTC time. + */ +uint64_t system_get_rtc_time(void); + +/** + * @brief Read user data from the RTC memory. + * + * The user data segment (1024 bytes, as shown below) is used to store user data. + * + * |<---- system data(512 bytes) ---->|<----------- user data(1024 bytes) --------->| + * + * @attention Read and write unit for data stored in the RTC memory is 4 bytes. + * @attention src_addr is the block number (4 bytes per block). So when reading data + * at the beginning of the user data segment, src_addr will be 512/4 = 128, + * n will be data length. + * + * @param uint16 src : source address of rtc memory, src_addr >= 128 + * @param void *dst : data pointer + * @param uint16 n : data length, unit: byte + * + * @return true : succeed + * @return false : fail + */ +bool system_rtc_mem_read(uint16_t src, void *dst, uint16_t n); + +/** + * @brief Write user data to the RTC memory. + * + * During deep-sleep, only RTC is working. So users can store their data + * in RTC memory if it is needed. The user data segment below (1024 bytes) + * is used to store the user data. + * + * |<---- system data(512 bytes) ---->|<----------- user data(1024 bytes) --------->| + * + * @attention Read and write unit for data stored in the RTC memory is 4 bytes. + * @attention src_addr is the block number (4 bytes per block). So when storing data + * at the beginning of the user data segment, src_addr will be 512/4 = 128, + * n will be data length. + * + * @param uint16 src : source address of rtc memory, src_addr >= 128 + * @param void *dst : data pointer + * @param uint16 n : data length, unit: byte + * + * @return true : succeed + * @return false : fail + */ +bool system_rtc_mem_write(uint16_t dst, const void *src, uint16_t n); + +/** \defgroup System_boot_APIs Boot APIs + * @brief boot APIs + */ + +/** @addtogroup System_boot_APIs + * @{ + */ + +/** + * @} + */ + +/** \defgroup Hardware_MAC_APIs Hardware MAC APIs + * @brief Hardware MAC address APIs + * + * In WiFi MAC, only ESP32 station MAC is the hardware MAC, ESP32 softAP MAC is a software MAC + * calculated from ESP32 station MAC. + * So users need to call wifi_get_macaddr to query the ESP32 softAP MAC if ESP32 station MAC changed. + * + */ + +/** @addtogroup Hardware_MAC_APIs + * @{ + */ + +/** + * @brief Read hardware MAC address. + * + * @param uint8 mac[6] : the hardware MAC address, length: 6 bytes. + * + * @return esp_err_t + */ +esp_err_t system_efuse_read_mac(uint8_t mac[6]); + + +void system_init(void); + +/** + * @} + */ + + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ESP_SYSTEM_H__ */ diff --git a/tools/sdk/include/esp32/esp_task.h b/tools/sdk/include/esp32/esp_task.h new file mode 100644 index 00000000..bb028bf4 --- /dev/null +++ b/tools/sdk/include/esp32/esp_task.h @@ -0,0 +1,59 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/* Notes: + * 1. Put all task priority and stack size definition in this file + * 2. If the task priority is less than 10, use ESP_TASK_PRIO_MIN + X style, + * otherwise use ESP_TASK_PRIO_MAX - X style + * 3. If this is a daemon task, the macro prefix is ESP_TASKD_, otherwise + * it's ESP_TASK_ + * 4. If the configMAX_PRIORITIES is modified, please make all priority are + * greater than 0 + * 5. Make sure esp_task.h is consistent between wifi lib and idf + */ + +#ifndef _ESP_TASK_H_ +#define _ESP_TASK_H_ + +#include "sdkconfig.h" + +#define ESP_TASK_PRIO_MAX (configMAX_PRIORITIES) +#define ESP_TASK_PRIO_MIN (0) + +/* Wifi library task */ +#define ESP_TASKD_WATCHDOG_PRIO (ESP_TASK_PRIO_MAX - 1) +#define ESP_TASKD_WATCHDOG_STACK 2048 +#define ESP_TASK_WPA2_PRIO (ESP_TASK_PRIO_MAX - 1) +#define ESP_TASK_WPA2_STACK 2048 +#define ESP_TASKD_WIFI_PRIO (ESP_TASK_PRIO_MAX - 2) +#define ESP_TASKD_WIFI_STACK 8196 +#define ESP_TASKD_WIFI_TIMER_PRIO (ESP_TASK_PRIO_MAX - 3) +#define ESP_TASKD_WIFI_TIMER_STACK 2048 +#define ESP_TASK_WPS_PRIO (ESP_TASK_PRIO_MIN + 2) +#define ESP_TASK_WPS_STACK 2048 + +/* Bt contoller Task */ +/* controller */ +#define ESP_TASK_BT_CONTROLLER_PRIO (ESP_TASK_PRIO_MAX - 1) +#define ESP_TASK_BT_CONTROLLER_STACK 4096 + +/* idf task */ +#define ESP_TASKD_EVENT_PRIO (ESP_TASK_PRIO_MAX - 5) +#define ESP_TASKD_EVENT_STACK CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE +#define ESP_TASK_TCPIP_PRIO (ESP_TASK_PRIO_MAX - 7) +#define ESP_TASK_TCPIP_STACK 2048 +#define ESP_TASK_MAIN_PRIO (ESP_TASK_PRIO_MIN + 1) +#define ESP_TASK_MAIN_STACK CONFIG_MAIN_TASK_STACK_SIZE + +#endif diff --git a/tools/sdk/include/esp32/esp_types.h b/tools/sdk/include/esp32/esp_types.h new file mode 100755 index 00000000..c142aee6 --- /dev/null +++ b/tools/sdk/include/esp32/esp_types.h @@ -0,0 +1,73 @@ +// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef __ESP_TYPES_H__ +#define __ESP_TYPES_H__ + +#ifdef __GNUC__ +#include +#endif /*__GNUC__*/ +#include +#include +#include + +#define __ATTRIB_PACK __attribute__ ((packed)) +#define __ATTRIB_PRINTF __attribute__ ((format (printf, 1, 2))) +#define __ATTRIB_NORETURN __attribute__ ((noreturn)) +#define __ATTRIB_ALIGN(x) __attribute__ ((aligned((x)))) +#define INLINE __inline__ + +#define LOCAL static + +/* probably should not put STATUS here */ +typedef enum { + OK = 0, + FAIL, + PENDING, + BUSY, + CANCEL, +} STATUS; + +//#define _LITTLE_ENDIAN 1234 +//#define _BYTE_ORDER == _LITTLE_ENDIAN + +#define ASSERT( x ) do { \ + if (!(x)) { \ + printf("%s %u\n", __FILE__, __LINE__); \ + while (1) { \ + asm volatile("nop"); \ + }; \ + } \ +} while (0) + +/* #if __GNUC_PREREQ__(4, 1) */ +#ifndef __GNUC__ +#if 1 +#define __offsetof(type, field) __builtin_offsetof(type, field) +#else +#define __offsetof(type, field) ((size_t)(&((type *)0)->field)) +#endif +#endif /* __GNUC__ */ + + +/* Macros for counting and rounding. */ +#ifndef howmany +#define howmany(x, y) (((x)+((y)-1))/(y)) +#endif + +#define container_of(ptr, type, member) ({ \ + const typeof( ((type *)0)->member ) *__mptr = (ptr); \ + (type *)( (char *)__mptr - __offsetof(type,member) );}) + +#endif /* __ESP_TYPES_H__ */ diff --git a/tools/sdk/include/esp32/esp_wifi.h b/tools/sdk/include/esp32/esp_wifi.h new file mode 100644 index 00000000..12378f33 --- /dev/null +++ b/tools/sdk/include/esp32/esp_wifi.h @@ -0,0 +1,586 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +/* Notes about WiFi Programming + * + * The esp32 WiFi programming model can be depicted as following picture: + * + * + * default handler user handler + * ------------- --------------- --------------- + * | | event | | callback or | | + * | tcpip | ---------> | event | ----------> | application | + * | stack | | task | event | task | + * |-----------| |-------------| |-------------| + * /|\ | + * | | + * event | | + * | | + * | | + * --------------- | + * | | | + * | WiFi Driver |/__________________| + * | |\ API call + * | | + * |-------------| + * + * The WiFi driver can be consider as black box, it knows nothing about the high layer code, such as + * TCPIP stack, application task, event task etc, all it can do is to receive API call from high layer + * or post event queue to a specified Queue, which is initialized by API esp_wifi_init(). + * + * The event task is a daemon task, which receives events from WiFi driver or from other subsystem, such + * as TCPIP stack, event task will call the default callback function on receiving the event. For example, + * on receiving event SYSTEM_EVENT_STA_CONNECTED, it will call tcpip_adapter_start() to start the DHCP + * client in it's default handler. + * + * Application can register it's own event callback function by API esp_event_init, then the application callback + * function will be called after the default callback. Also, if application doesn't want to execute the callback + * in the event task, what it needs to do is to post the related event to application task in the application callback function. + * + * The application task (code) generally mixes all these thing together, it calls APIs to init the system/WiFi and + * handle the events when necessary. + * + */ + +#ifndef __ESP_WIFI_H__ +#define __ESP_WIFI_H__ + +#include +#include +#include "freertos/FreeRTOS.h" +#include "freertos/queue.h" +#include "rom/queue.h" +#include "esp_err.h" +#include "esp_wifi_types.h" +#include "esp_event.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + system_event_handler_t event_handler; /**< WiFi event handler */ +} wifi_init_config_t; + + +#define WIFI_INIT_CONFIG_DEFAULT() { \ + .event_handler = &esp_event_send, \ +}; + +/** + * @brief Init WiFi + * Alloc resource for WiFi driver, such as WiFi control structure, RX/TX buffer, + * WiFi NVS structure etc, this WiFi also start WiFi task + * + * @attention 1. This API must be called before all other WiFi API can be called + * @attention 2. Generally we should init event_q in *config, WiFi driver will post the event + * to this queue when event happens, such as, when station connects to WiFi, WiFi driver + * will post station connected event to this queue. If the queue is not initialized, WiFi + * will not post any events + * + * @param wifi_init_config_t *config : provide WiFi init configuration + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_wifi_init(wifi_init_config_t *config); + +/** + * @brief Deinit WiFi + * Free all resource allocated in esp_wifi_init and stop WiFi task + * + * @attention 1. This API should be called if you want to remove WiFi driver from the system + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_wifi_deinit(void); + +/** + * @brief Set the WiFi operating mode + * + * Set the WiFi operating mode as station, soft-AP or station+soft-AP, + * The default mode is soft-AP mode. + * + * @param wifi_mode_t mode : WiFi operating modes: + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_wifi_set_mode(wifi_mode_t mode); + +/** + * @brief Get current operating mode of WiFi + * + * @param wifi_mode_t *mode : store current WiFi mode + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_wifi_get_mode(wifi_mode_t *mode); + +/** + * @brief Start WiFi according to current configuration + * If mode is WIFI_MODE_STA, it create station control block and start station + * If mode is WIFI_MODE_AP, it create soft-AP control block and start soft-AP + * If mode is WIFI_MODE_APSTA, it create soft-AP and station control block and start soft-AP and station + * + * @param null + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_wifi_start(void); + +/** + * @brief Stop WiFi + If mode is WIFI_MODE_STA, it stop station and free station control block + * If mode is WIFI_MODE_AP, it stop soft-AP and free soft-AP control block + * If mode is WIFI_MODE_APSTA, it stop station/soft-AP and free station/soft-AP control block + * + * @param null + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_wifi_stop(void); + +/** + * @brief Connect the ESP32 WiFi station to the AP. + * + * @attention 1. This API only impact WIFI_MODE_STA or WIFI_MODE_APSTA mode + * @attention 2. If the ESP32 is connected to an AP, call esp_wifi_disconnect to disconnect. + * + * @param null + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_wifi_connect(void); + +/** + * @brief Disconnect the ESP32 WiFi station from the AP. + * + * @param null + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_wifi_disconnect(void); + +/** + * @brief Currently this API is just an stub API + * + * @param null + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_wifi_clear_fast_connect(void); + +/** + * @brief Kick the all station or associated id equals to aid + * + * @param uint16_t aid : when aid is 0, kick all stations, otherwise kick station whose associated id is aid + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_wifi_kick_station(uint16_t aid); + +/** + * @brief Scan all available APs. + * + * @attention If this API is called, the found APs are stored in WiFi driver dynamic allocated memory and the + * will be freed in esp_wifi_get_ap_list, so generally, call esp_wifi_get_ap_list to cause + * the memory to be freed once the scan is done + * + * @param struct scan_config *config : configuration of scanning + * @param bool block : if block is true, this API will block the caller until the scan is done, otherwise + * it will return immediately + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_wifi_scan_start(wifi_scan_config_t *conf, bool block); + +/** + * @brief Stop the scan in process + * + * @param null + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_wifi_scan_stop(void); + +/** + * @brief Get number of APs found in last scan + * + * @param uint16_t *number : store number of APIs found in last scan + * + * @attention This API can only be called when the scan is completed, otherwise it may get wrong value + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_wifi_get_ap_num(uint16_t *number); + +/** + * @brief Get AP list found in last scan + * + * @param uint16_t *number : as input param, it stores max AP number ap_list can hold, as output param, it store + the actual AP number this API returns + * @param wifi_ap_list_t *ap_list : a list to hold the found APs + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_wifi_get_ap_list(uint16_t *number, wifi_ap_list_t *ap_list); + +/** + * @brief Set current power save type + * + * @param wifi_ps_type_t type : power save type + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_wifi_set_ps(wifi_ps_type_t type); + +/** + * @brief Get current power save type + * + * @param wifi_ps_type_t *type : store current power save type + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_wifi_get_ps(wifi_ps_type_t *type); + +/** + * @brief Set protocol type of specified interface + * The default protocol is (WIFI_PROTOCOL_11B|WIFI_PROTOCOL_11G|WIFI_PROTOCOL_11N) + * + * @attention Currently we only support 802.11b or 802.11bg or 802.11bgn mode + * + * @param wifi_interface_t ifx : interfaces + * @param uint8_t protocol : WiFi protocol bitmap + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_wifi_set_protocol(wifi_interface_t ifx, uint8_t protocol_bitmap); + +/** + * @brief Get the current protocol bitmap of specified ifx + * + * @param wifi_interface_t ifx : interfaces + * @param uint8_t protocol : store current WiFi protocol bitmap of interface ifx + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_wifi_get_protocol(wifi_interface_t ifx, uint8_t *protocol_bitmap); + +/** + * @brief Set the bandwidth of ESP32 specified interface + * + * @attention 1. API return false if try to configure a interface that is not enable + * @attention 2. WIFI_BW_HT40 is supported only when the interface support 11N + * + * @param wifi_interface_t ifx : interface to be configured + * @param wifi_bandwidth_t bw : bandwidth + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_wifi_set_bandwidth(wifi_interface_t ifx, wifi_bandwidth_t bw); + +/** + * @brief Get the bandwidth of ESP32 specified interface + * + * @attention 1. API return false if try to get a interface that is not enable + * + * @param wifi_interface_t ifx : interface to be configured + * @param wifi_bandwidth_t *bw : store bandwidth of interface ifx + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_wifi_get_bandwidth(wifi_interface_t ifx, wifi_bandwidth_t *bw); + +/** + * @brief Set primary/second channel of ESP32 + * + * @attention 1. This is a special API for sniffer + * + * @param uint8_t primary : for HT20, primary is the channel number, for HT40, primary is the primary channel + * @param wifi_second_chan_t second : for HT20, second is ignored, for HT40, second is the second channel + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_wifi_set_channel(uint8_t primary, wifi_second_chan_t second); + +/** + * @brief Get the primary/second channel of ESP32 + * + * @attention 1. API return false if try to get a interface that is not enable + * + * @param uint8_t *primary : store current primary channel + * @param wifi_second_chan_t *second : store current second channel + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_wifi_get_channel(uint8_t *primary, wifi_second_chan_t *second); + +/** + * @brief Set country code + * The default value is WIFI_COUNTRY_CN + * + * @param wifi_country_t country : country type + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_wifi_set_country(wifi_country_t country); + +/** + * @brief Get country code + * + * @param wifi_country_t country : store current country + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_wifi_get_country(wifi_country_t *country); + +/** + * @brief Set MAC address of the ESP32 WiFi station or the soft-AP interface. + * + * @attention 1. This API can only be called when the interface is disabled + * @attention 2. ESP32 soft-AP and station have different MAC addresses, do not set them to be the same. + * - The bit0 of the first byte of ESP32 MAC address can not be 1. For example, the MAC address + * can set to be "1a:XX:XX:XX:XX:XX", but can not be "15:XX:XX:XX:XX:XX". + * + * @param wifi_interface_t ifx : interface + * @param uint8 mac[6]: the MAC address. + * + * @return true : succeed + * @return false : fail + */ +esp_err_t esp_wifi_set_mac(wifi_interface_t ifx, uint8_t mac[6]); + +/** + * @brief Get mac of specified interface + * + * @param uint8_t mac[6] : store mac of this interface ifx + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_wifi_get_mac(wifi_interface_t ifx, uint8_t mac[6]); + +/** + * @brief The RX callback function in the promiscuous mode. + * + * Each time a packet is received, the callback function will be called. + * + * @param void *buf : the data received + * @param uint16_t len : data length + * + * @return ESP_OK : succeed + * @return others : fail + */ +typedef void (* wifi_promiscuous_cb_t)(void *buf, uint16_t len); + +/** + * @brief Register the RX callback function in the promiscuous mode. + * + * Each time a packet is received, the registered callback function will be called. + * + * @param wifi_promiscuous_cb_t cb : callback + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_wifi_set_promiscuous_rx_cb(wifi_promiscuous_cb_t cb); + +/** + * @brief Enable the promiscuous mode. + * + * @param bool promiscuous : false - disable / true - enable + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_wifi_set_promiscuous(bool en); + +/** + * @brief Get the promiscuous mode. + * + * @param bool *enable : store the current status of promiscuous mode + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_wifi_get_promiscuous(bool *en); + +/** + * @brief Set the configuration of the ESP32 STA or AP + * + * @attention 1. This API can be called only when specified interface is enabled, otherwise, API fail + * @attention 2. For station configuration, bssid_set needs to be 0; and it needs to be 1 only when users need to check the MAC address of the AP. + * @attention 3. ESP32 is limited to only one channel, so when in the soft-AP+station mode, the soft-AP will adjust its channel automatically to be the same as + * the channel of the ESP32 station. + * + * @param wifi_interface_t ifx : interface + * @param wifi_config_t *conf : station or soft-AP configuration + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_wifi_set_config(wifi_interface_t ifx, wifi_config_t *conf); + +/** + * @brief Get configuration of specified interface + * + * @param wifi_interface_t ifx : interface + * @param wifi_config_t *conf : station or soft-AP configuration + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_wifi_get_config(wifi_interface_t ifx, wifi_config_t *conf); + +/** + * @brief Get STAs associated with soft-AP + * + * @attention SSC only API + * + * @param struct station_info **station : station list + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_wifi_get_station_list(struct station_info **station); + +esp_err_t esp_wifi_free_station_list(void); + +/** + * @brief Set the WiFi API configuration storage type + * + * @attention 1. The default value is WIFI_STORAGE_FLASH + * + * @param wifi_storage_t storage : storage type + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_wifi_set_storage(wifi_storage_t storage); + +/** + * @brief The WiFi RX callback function + * + * Each time the WiFi need to forward the packets to high layer, the callback function will be called + * + */ +typedef esp_err_t (*wifi_rxcb_t)(void *buffer, uint16_t len, void *eb); + +/** + * @brief Set the WiFi RX callback + * + * @attention 1. Currently we support only one RX callback for each interface + * + * @param wifi_interface_t ifx : interface + * @param wifi_rxcb_t fn : WiFi RX callback + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_wifi_reg_rxcb(wifi_interface_t ifx, wifi_rxcb_t fn); + +/** + * @brief Set auto connect + * The default value is true + * + * @attention 1. + * + * @param bool en : true - enable auto connect / false - disable auto connect + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_wifi_set_auto_connect(bool en); + +/** + * @brief Get the auto connect flag + * + * @param bool *en : store current auto connect configuration + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_wifi_get_auto_connect(bool *en); + +/** + * @brief Set vendor specific element + * + * @param bool enable : enable or not + * @param wifi_vendor_ie_type_t type : 0 - WIFI_VND_IE_TYPE_BEACON + * 1 - WIFI_VND_IE_TYPE_PROBE_REQ + * 2 - WIFI_VND_IE_TYPE_PROBE_RESP + * 3 - WIFI_VND_IE_TYPE_ASSOC_REQ + * 4 - WIFI_VND_IE_TYPE_ASSOC_RESP + * @param wifi_vendor_ie_id_t idx : 0 - WIFI_VND_IE_ID_0 + 1 - WIFI_VND_IE_ID_1 + * @param uint8_t *vnd_ie : pointer to a vendor specific element + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_wifi_set_vendor_ie(bool enable, wifi_vendor_ie_type_t type, wifi_vendor_ie_id_t idx, uint8_t *vnd_ie); + +/** + * @brief Define function pointer for vendor specific element callback + * @param void *ctx : reserved + * @param wifi_vendor_ie_type_t type : 0 - WIFI_VND_IE_TYPE_BEACON + * 1 - WIFI_VND_IE_TYPE_PROBE_REQ + * 2 - WIFI_VND_IE_TYPE_PROBE_RESP + * 3 - WIFI_VND_IE_TYPE_ASSOC_REQ + * 4 - WIFI_VND_IE_TYPE_ASSOC_RESP + * @param const uint8_t sa[6] : source address + * @param const uint8_t *vnd_ie : pointer to a vendor specific element + * @param int rssi : received signal strength indication + */ +typedef void (*esp_vendor_ie_cb_t) (void *ctx, wifi_vendor_ie_type_t type, const uint8_t sa[6], const uint8_t *vnd_ie, int rssi); + +/** + * @brief Set vendor specific element callback + * + * @param esp_vendor_ie_cb_t cb : callback function + * @param void *ctx : reserved + * + * @return ESP_OK : succeed + * @return others : fail + */ +esp_err_t esp_wifi_set_vendor_ie_cb(esp_vendor_ie_cb_t cb, void *ctx); + +#ifdef __cplusplus +} +#endif + +#endif /* __ESP_WIFI_H__ */ diff --git a/tools/sdk/include/esp32/esp_wifi_types.h b/tools/sdk/include/esp32/esp_wifi_types.h new file mode 100644 index 00000000..b3474769 --- /dev/null +++ b/tools/sdk/include/esp32/esp_wifi_types.h @@ -0,0 +1,190 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +#ifndef __ESP_WIFI_TYPES_H__ +#define __ESP_WIFI_TYPES_H__ + +#include +#include +#include "rom/queue.h" +#include "esp_err.h" +#include "esp_wifi_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + WIFI_MODE_NULL = 0, /**< null mode */ + WIFI_MODE_STA, /**< WiFi station mode */ + WIFI_MODE_AP, /**< WiFi soft-AP mode */ + WIFI_MODE_APSTA, /**< WiFi station + soft-AP mode */ + WIFI_MODE_MAX +} wifi_mode_t; + +typedef enum { + WIFI_IF_STA = 0, /**< ESP32 station interface */ + WIFI_IF_AP, /**< ESP32 soft-AP interface */ + WIFI_IF_MAX +} wifi_interface_t; + +typedef enum { + WIFI_COUNTRY_CN = 0, /**< country China, channel range [1, 14] */ + WIFI_COUNTRY_JP, /**< country Japan, channel range [1, 14] */ + WIFI_COUNTRY_US, /**< country USA, channel range [1, 11] */ + WIFI_COUNTRY_EU, /**< country Europe, channel range [1, 13] */ + WIFI_COUNTRY_MAX +} wifi_country_t; + +typedef enum { + WIFI_AUTH_OPEN = 0, /**< authenticate mode : open */ + WIFI_AUTH_WEP, /**< authenticate mode : WEP */ + WIFI_AUTH_WPA_PSK, /**< authenticate mode : WPA_PSK */ + WIFI_AUTH_WPA2_PSK, /**< authenticate mode : WPA2_PSK */ + WIFI_AUTH_WPA_WPA2_PSK, /**< authenticate mode : WPA_WPA2_PSK */ + WIFI_AUTH_MAX +} wifi_auth_mode_t; + +enum { + WIFI_REASON_UNSPECIFIED = 1, + WIFI_REASON_AUTH_EXPIRE = 2, + WIFI_REASON_AUTH_LEAVE = 3, + WIFI_REASON_ASSOC_EXPIRE = 4, + WIFI_REASON_ASSOC_TOOMANY = 5, + WIFI_REASON_NOT_AUTHED = 6, + WIFI_REASON_NOT_ASSOCED = 7, + WIFI_REASON_ASSOC_LEAVE = 8, + WIFI_REASON_ASSOC_NOT_AUTHED = 9, + WIFI_REASON_DISASSOC_PWRCAP_BAD = 10, + WIFI_REASON_DISASSOC_SUPCHAN_BAD = 11, + WIFI_REASON_IE_INVALID = 13, + WIFI_REASON_MIC_FAILURE = 14, + WIFI_REASON_4WAY_HANDSHAKE_TIMEOUT = 15, + WIFI_REASON_GROUP_KEY_UPDATE_TIMEOUT = 16, + WIFI_REASON_IE_IN_4WAY_DIFFERS = 17, + WIFI_REASON_GROUP_CIPHER_INVALID = 18, + WIFI_REASON_PAIRWISE_CIPHER_INVALID = 19, + WIFI_REASON_AKMP_INVALID = 20, + WIFI_REASON_UNSUPP_RSN_IE_VERSION = 21, + WIFI_REASON_INVALID_RSN_IE_CAP = 22, + WIFI_REASON_802_1X_AUTH_FAILED = 23, + WIFI_REASON_CIPHER_SUITE_REJECTED = 24, + + WIFI_REASON_BEACON_TIMEOUT = 200, + WIFI_REASON_NO_AP_FOUND = 201, + WIFI_REASON_AUTH_FAIL = 202, + WIFI_REASON_ASSOC_FAIL = 203, + WIFI_REASON_HANDSHAKE_TIMEOUT = 204, +}; + +typedef enum { + WIFI_SECOND_CHAN_NONE = 0, /**< the channel width is HT20 */ + WIFI_SECOND_CHAN_ABOVE, /**< the channel width is HT40 and the second channel is above the primary channel */ + WIFI_SECOND_CHAN_BELOW, /**< the channel width is HT40 and the second channel is below the primary channel */ +} wifi_second_chan_t; + +typedef struct { + char *ssid; /**< SSID of AP */ + uint8_t *bssid; /**< MAC address of AP */ + uint8_t channel; /**< channel, scan the specific channel */ + bool show_hidden; /**< enable to scan AP whose SSID is hidden */ +} wifi_scan_config_t; + +typedef struct { + uint8_t bssid[6]; /**< MAC address of AP */ + uint8_t ssid[32]; /**< SSID of AP */ + uint8_t primary; /**< channel of AP */ + wifi_second_chan_t second; /**< second channel of AP */ + int8_t rssi; /**< signal strength of AP */ + wifi_auth_mode_t authmode; /**< authmode of AP */ +} wifi_ap_list_t; + +typedef enum { + WIFI_PS_NONE, /**< No power save */ + WIFI_PS_MODEM, /**< Modem power save */ + WIFI_PS_LIGHT, /**< Light power save */ + WIFI_PS_MAC, /**< MAC power save */ +} wifi_ps_type_t; + +#define WIFI_PROTOCOL_11B 1 +#define WIFI_PROTOCOL_11G 2 +#define WIFI_PROTOCOL_11N 4 + +typedef enum { + WIFI_BW_HT20 = 0, /* Bandwidth is HT20 */ + WIFI_BW_HT40, /* Bandwidth is HT40 */ +} wifi_bandwidth_t; + +typedef struct { + char ssid[32]; /**< SSID of ESP32 soft-AP */ + char password[64]; /**< Password of ESP32 soft-AP */ + uint8_t ssid_len; /**< Length of SSID. If softap_config.ssid_len==0, check the SSID until there is a termination character; otherwise, set the SSID length according to softap_config.ssid_len. */ + uint8_t channel; /**< Channel of ESP32 soft-AP */ + wifi_auth_mode_t authmode; /**< Auth mode of ESP32 soft-AP. Do not support AUTH_WEP in soft-AP mode */ + uint8_t ssid_hidden; /**< Broadcast SSID or not, default 0, broadcast the SSID */ + uint8_t max_connection; /**< Max number of stations allowed to connect in, default 4, max 4 */ + uint16_t beacon_interval; /**< Beacon interval, 100 ~ 60000 ms, default 100 ms */ +} wifi_ap_config_t; + +typedef struct { + char ssid[32]; /**< SSID of target AP*/ + char password[64]; /**< password of target AP*/ + bool bssid_set; /**< whether set MAC address of target AP or not. Generally, station_config.bssid_set needs to be 0; and it needs to be 1 only when users need to check the MAC address of the AP.*/ + uint8_t bssid[6]; /**< MAC address of target AP*/ +} wifi_sta_config_t; + +typedef union { + wifi_ap_config_t ap; /**< configuration of AP */ + wifi_sta_config_t sta; /**< configuration of STA */ +} wifi_config_t; + +struct station_info { + STAILQ_ENTRY(station_info) next; + uint8_t bssid[6]; +}; + +typedef enum { + WIFI_STORAGE_FLASH, /**< all configuration will strore in both memory and flash */ + WIFI_STORAGE_RAM, /**< all configuration will only store in the memory */ +} wifi_storage_t; + +/** + * @brief Vendor IE type + * + */ +typedef enum { + WIFI_VND_IE_TYPE_BEACON, + WIFI_VND_IE_TYPE_PROBE_REQ, + WIFI_VND_IE_TYPE_PROBE_RESP, + WIFI_VND_IE_TYPE_ASSOC_REQ, + WIFI_VND_IE_TYPE_ASSOC_RESP, +} wifi_vendor_ie_type_t; + +/** + * @brief Vendor IE index + * + */ +typedef enum { + WIFI_VND_IE_ID_0, + WIFI_VND_IE_ID_1, +} wifi_vendor_ie_id_t; + + +#ifdef __cplusplus +} +#endif + + +#endif /* __ESP_WIFI_TYPES_H__ */ diff --git a/tools/sdk/include/esp32/hwcrypto/aes.h b/tools/sdk/include/esp32/hwcrypto/aes.h new file mode 100644 index 00000000..b6a632af --- /dev/null +++ b/tools/sdk/include/esp32/hwcrypto/aes.h @@ -0,0 +1,281 @@ +/** + * \brief AES block cipher, ESP32 hardware accelerated version + * Based on mbedTLS FIPS-197 compliant version. + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Additions Copyright (C) 2016, Espressif Systems (Shanghai) PTE Ltd + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * + */ + +#ifndef ESP_AES_H +#define ESP_AES_H + +#include "esp_types.h" +#include "rom/aes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* padlock.c and aesni.c rely on these values! */ +#define ESP_AES_ENCRYPT 1 +#define ESP_AES_DECRYPT 0 + +#define ERR_ESP_AES_INVALID_KEY_LENGTH -0x0020 /**< Invalid key length. */ +#define ERR_ESP_AES_INVALID_INPUT_LENGTH -0x0022 /**< Invalid data input length. */ + +typedef struct { + enum AES_BITS aesbits; + uint8_t key[32]; +} key_context, KEY_CTX; + +/** + * \brief AES context structure + * + * \note buf is able to hold 32 extra bytes, which can be used: + * - for alignment purposes if VIA padlock is used, and/or + * - to simplify key expansion in the 256-bit case by + * generating an extra round key + */ +typedef struct { + int nr; /*!< number of rounds */ + uint32_t *rk; /*!< AES round keys */ + KEY_CTX enc; + KEY_CTX dec; +} esp_aes_context; + +/** + * \brief Lock access to AES hardware unit + * + * AES hardware unit can only be used by one + * consumer at a time. + * + * esp_aes_xxx API calls automatically manage locking & unlocking of + * hardware, this function is only needed if you want to call + * ets_aes_xxx functions directly. + */ +void esp_aes_acquire_hardware( void ); + +/** + * \brief Unlock access to AES hardware unit + * + * esp_aes_xxx API calls automatically manage locking & unlocking of + * hardware, this function is only needed if you want to call + * ets_aes_xxx functions directly. + */ +void esp_aes_release_hardware( void ); + +/** + * \brief Initialize AES context + * + * \param ctx AES context to be initialized + */ +void esp_aes_init( esp_aes_context *ctx ); + +/** + * \brief Clear AES context + * + * \param ctx AES context to be cleared + */ +void esp_aes_free( esp_aes_context *ctx ); + +/** + * \brief AES key schedule (encryption) + * + * \param ctx AES context to be initialized + * \param key encryption key + * \param keybits must be 128, 192 or 256 + * + * \return 0 if successful, or ERR_AES_INVALID_KEY_LENGTH + */ +int esp_aes_setkey_enc( esp_aes_context *ctx, const unsigned char *key, unsigned int keybits ); + +/** + * \brief AES key schedule (decryption) + * + * \param ctx AES context to be initialized + * \param key decryption key + * \param keybits must be 128, 192 or 256 + * + * \return 0 if successful, or ERR_AES_INVALID_KEY_LENGTH + */ +int esp_aes_setkey_dec( esp_aes_context *ctx, const unsigned char *key, unsigned int keybits ); + +/** + * \brief AES-ECB block encryption/decryption + * + * \param ctx AES context + * \param mode AES_ENCRYPT or AES_DECRYPT + * \param input 16-byte input block + * \param output 16-byte output block + * + * \return 0 if successful + */ +int esp_aes_crypt_ecb( esp_aes_context *ctx, int mode, const unsigned char input[16], unsigned char output[16] ); + +/** + * \brief AES-CBC buffer encryption/decryption + * Length should be a multiple of the block + * size (16 bytes) + * + * \note Upon exit, the content of the IV is updated so that you can + * call the function same function again on the following + * block(s) of data and get the same result as if it was + * encrypted in one call. This allows a "streaming" usage. + * If on the other hand you need to retain the contents of the + * IV, you should either save it manually or use the cipher + * module instead. + * + * \param ctx AES context + * \param mode AES_ENCRYPT or AES_DECRYPT + * \param length length of the input data + * \param iv initialization vector (updated after use) + * \param input buffer holding the input data + * \param output buffer holding the output data + * + * \return 0 if successful, or ERR_AES_INVALID_INPUT_LENGTH + */ +int esp_aes_crypt_cbc( esp_aes_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); + + +/** + * \brief AES-CFB128 buffer encryption/decryption. + * + * Note: Due to the nature of CFB you should use the same key schedule for + * both encryption and decryption. So a context initialized with + * esp_aes_setkey_enc() for both AES_ENCRYPT and AES_DECRYPT. + * + * \note Upon exit, the content of the IV is updated so that you can + * call the function same function again on the following + * block(s) of data and get the same result as if it was + * encrypted in one call. This allows a "streaming" usage. + * If on the other hand you need to retain the contents of the + * IV, you should either save it manually or use the cipher + * module instead. + * + * \param ctx AES context + * \param mode AES_ENCRYPT or AES_DECRYPT + * \param length length of the input data + * \param iv_off offset in IV (updated after use) + * \param iv initialization vector (updated after use) + * \param input buffer holding the input data + * \param output buffer holding the output data + * + * \return 0 if successful + */ +int esp_aes_crypt_cfb128( esp_aes_context *ctx, + int mode, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); + +/** + * \brief AES-CFB8 buffer encryption/decryption. + * + * Note: Due to the nature of CFB you should use the same key schedule for + * both encryption and decryption. So a context initialized with + * esp_aes_setkey_enc() for both AES_ENCRYPT and AES_DECRYPT. + * + * \note Upon exit, the content of the IV is updated so that you can + * call the function same function again on the following + * block(s) of data and get the same result as if it was + * encrypted in one call. This allows a "streaming" usage. + * If on the other hand you need to retain the contents of the + * IV, you should either save it manually or use the cipher + * module instead. + * + * \param ctx AES context + * \param mode AES_ENCRYPT or AES_DECRYPT + * \param length length of the input data + * \param iv initialization vector (updated after use) + * \param input buffer holding the input data + * \param output buffer holding the output data + * + * \return 0 if successful + */ +int esp_aes_crypt_cfb8( esp_aes_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); + +/** + * \brief AES-CTR buffer encryption/decryption + * + * Warning: You have to keep the maximum use of your counter in mind! + * + * Note: Due to the nature of CTR you should use the same key schedule for + * both encryption and decryption. So a context initialized with + * esp_aes_setkey_enc() for both AES_ENCRYPT and AES_DECRYPT. + * + * \param ctx AES context + * \param length The length of the data + * \param nc_off The offset in the current stream_block (for resuming + * within current cipher stream). The offset pointer to + * should be 0 at the start of a stream. + * \param nonce_counter The 128-bit nonce and counter. + * \param stream_block The saved stream-block for resuming. Is overwritten + * by the function. + * \param input The input data stream + * \param output The output data stream + * + * \return 0 if successful + */ +int esp_aes_crypt_ctr( esp_aes_context *ctx, + size_t length, + size_t *nc_off, + unsigned char nonce_counter[16], + unsigned char stream_block[16], + const unsigned char *input, + unsigned char *output ); + + +/** + * \brief Internal AES block encryption function + * (Only exposed to allow overriding it, + * see AES_ENCRYPT_ALT) + * + * \param ctx AES context + * \param input Plaintext block + * \param output Output (ciphertext) block + */ +void esp_aes_encrypt( esp_aes_context *ctx, const unsigned char input[16], unsigned char output[16] ); + +/** + * \brief Internal AES block decryption function + * (Only exposed to allow overriding it, + * see AES_DECRYPT_ALT) + * + * \param ctx AES context + * \param input Ciphertext block + * \param output Output (plaintext) block + */ +void esp_aes_decrypt( esp_aes_context *ctx, const unsigned char input[16], unsigned char output[16] ); + +#ifdef __cplusplus +} +#endif + +#endif /* aes.h */ diff --git a/tools/sdk/include/esp32/hwcrypto/sha.h b/tools/sdk/include/esp32/hwcrypto/sha.h new file mode 100644 index 00000000..a165c46c --- /dev/null +++ b/tools/sdk/include/esp32/hwcrypto/sha.h @@ -0,0 +1,250 @@ +/* + * ESP32 hardware accelerated SHA1/256/512 implementation + * based on mbedTLS FIPS-197 compliant version. + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Additions Copyright (C) 2016, Espressif Systems (Shanghai) PTE Ltd + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef _ESP_SHA_H_ +#define _ESP_SHA_H_ + +#include "rom/sha.h" + +#include "esp_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief SHA-1 context structure + */ +typedef struct { + /* both types defined in rom/sha.h */ + SHA_CTX context; + enum SHA_TYPE context_type; +} esp_sha_context; + +/** + * \brief Lock access to SHA hardware unit + * + * SHA hardware unit can only be used by one + * consumer at a time. + * + * esp_sha_xxx API calls automatically manage locking & unlocking of + * hardware, this function is only needed if you want to call + * ets_sha_xxx functions directly. + */ +void esp_sha_acquire_hardware( void ); + +/** + * \brief Unlock access to SHA hardware unit + * + * esp_sha_xxx API calls automatically manage locking & unlocking of + * hardware, this function is only needed if you want to call + * ets_sha_xxx functions directly. + */ +void esp_sha_release_hardware( void ); + +/** + * \brief Initialize SHA-1 context + * + * \param ctx SHA-1 context to be initialized + */ +void esp_sha1_init( esp_sha_context *ctx ); + +/** + * \brief Clear SHA-1 context + * + * \param ctx SHA-1 context to be cleared + */ +void esp_sha1_free( esp_sha_context *ctx ); + +/** + * \brief Clone (the state of) a SHA-1 context + * + * \param dst The destination context + * \param src The context to be cloned + */ +void esp_sha1_clone( esp_sha_context *dst, const esp_sha_context *src ); + +/** + * \brief SHA-1 context setup + * + * \param ctx context to be initialized + */ +void esp_sha1_start( esp_sha_context *ctx ); + +/** + * \brief SHA-1 process buffer + * + * \param ctx SHA-1 context + * \param input buffer holding the data + * \param ilen length of the input data + */ +void esp_sha1_update( esp_sha_context *ctx, const unsigned char *input, size_t ilen ); + +/** + * \brief SHA-1 final digest + * + * \param ctx SHA-1 context + * \param output SHA-1 checksum result + */ +void esp_sha1_finish( esp_sha_context *ctx, unsigned char output[20] ); + +/** + * \brief Calculate SHA-1 of input buffer + * + * \param input buffer holding the data + * \param ilen length of the input data + * \param output SHA-1 checksum result + */ +void esp_sha1( const unsigned char *input, size_t ilen, unsigned char output[20] ); + +/** + * \brief SHA-256 context structure + */ + +/** + * \brief Initialize SHA-256 context + * + * \param ctx SHA-256 context to be initialized + */ +void esp_sha256_init( esp_sha_context *ctx ); + +/** + * \brief Clear SHA-256 context + * + * \param ctx SHA-256 context to be cleared + */ +void esp_sha256_free( esp_sha_context *ctx ); + +/** + * \brief Clone (the state of) a SHA-256 context + * + * \param dst The destination context + * \param src The context to be cloned + */ +void esp_sha256_clone( esp_sha_context *dst, const esp_sha_context *src ); + +/** + * \brief SHA-256 context setup + * + * \param ctx context to be initialized + * \param is224 0 = use SHA256, 1 = use SHA224 + */ +void esp_sha256_start( esp_sha_context *ctx, int is224 ); + +/** + * \brief SHA-256 process buffer + * + * \param ctx SHA-256 context + * \param input buffer holding the data + * \param ilen length of the input data + */ +void esp_sha256_update( esp_sha_context *ctx, const unsigned char *input, size_t ilen ); + +/** + * \brief SHA-256 final digest + * + * \param ctx SHA-256 context + * \param output SHA-224/256 checksum result + */ +void esp_sha256_finish( esp_sha_context *ctx, unsigned char output[32] ); + +/** + * \brief Calculate SHA-256 of input buffer + * + * \param input buffer holding the data + * \param ilen length of the input data + * \param output SHA-224/256 checksum result + * \param is224 0 = use SHA256, 1 = use SHA224 + */ +void esp_sha256( const unsigned char *input, size_t ilen, unsigned char output[32], int is224 ); + +// + +/** + * \brief SHA-512 context structure + */ + +/** + * \brief Initialize SHA-512 context + * + * \param ctx SHA-512 context to be initialized + */ +void esp_sha512_init( esp_sha_context *ctx ); + +/** + * \brief Clear SHA-512 context + * + * \param ctx SHA-512 context to be cleared + */ +void esp_sha512_free( esp_sha_context *ctx ); + +/** + * \brief Clone (the state of) a SHA-512 context + * + * \param dst The destination context + * \param src The context to be cloned + */ +void esp_sha512_clone( esp_sha_context *dst, const esp_sha_context *src ); + +/** + * \brief SHA-512 context setup + * + * \param ctx context to be initialized + * \param is384 0 = use SHA512, 1 = use SHA384 + */ +void esp_sha512_start( esp_sha_context *ctx, int is384 ); + +/** + * \brief SHA-512 process buffer + * + * \param ctx SHA-512 context + * \param input buffer holding the data + * \param ilen length of the input data + */ +void esp_sha512_update( esp_sha_context *ctx, const unsigned char *input, size_t ilen ); + +/** + * \brief SHA-512 final digest + * + * \param ctx SHA-512 context + * \param output SHA-384/512 checksum result + */ +void esp_sha512_finish( esp_sha_context *ctx, unsigned char output[64] ); + +/** + * \brief Calculate SHA-512 of input buffer. + * + * \param input buffer holding the data + * \param ilen length of the input data + * \param output SHA-384/512 checksum result + * \param is384 0 = use SHA512, 1 = use SHA384 + */ +void esp_sha512( const unsigned char *input, size_t ilen, unsigned char output[64], int is384 ); + +// + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/tools/sdk/include/esp32/rom/aes.h b/tools/sdk/include/esp32/rom/aes.h new file mode 100644 index 00000000..80eca973 --- /dev/null +++ b/tools/sdk/include/esp32/rom/aes.h @@ -0,0 +1,57 @@ +/* + ROM functions for hardware AES support. + + It is not recommended to use these functions directly, + use the wrapper functions in hwcrypto/aes.h instead. + + */ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _ROM_AES_H_ +#define _ROM_AES_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +//TODO, add comment for aes apis +enum AES_BITS { + AES128, + AES192, + AES256 +}; + +void ets_aes_enable(void); + +void ets_aes_disable(void); + +void ets_aes_set_endian(bool key_word_swap, bool key_byte_swap, + bool in_word_swap, bool in_byte_swap, + bool out_word_swap, bool out_byte_swap); + +bool ets_aes_setkey_enc(const uint8_t *key, enum AES_BITS bits); + +bool ets_aes_setkey_dec(const uint8_t *key, enum AES_BITS bits); + +void ets_aes_crypt(const uint8_t input[16], uint8_t output[16]); + +#ifdef __cplusplus +} +#endif + +#endif /* _ROM_AES_H_ */ diff --git a/tools/sdk/include/esp32/rom/bigint.h b/tools/sdk/include/esp32/rom/bigint.h new file mode 100644 index 00000000..97ad7220 --- /dev/null +++ b/tools/sdk/include/esp32/rom/bigint.h @@ -0,0 +1,62 @@ +/* + ROM functions for hardware bigint support. + + It is not recommended to use these functions directly, + use the wrapper functions in hwcrypto/mpi.h instead. + + */ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _ROM_BIGINT_H_ +#define _ROM_BIGINT_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +//TODO: add comment here +void ets_bigint_enable(void); + +void ets_bigint_disable(void); + +void ets_bigint_wait_finish(void); + +bool ets_bigint_mod_power_prepare(uint32_t *x, uint32_t *y, uint32_t *m, + uint32_t m_dash, uint32_t *rb, uint32_t len, bool again); + +bool ets_bigint_mod_power_getz(uint32_t *z, uint32_t len); + +bool ets_bigint_mult_prepare(uint32_t *x, uint32_t *y, uint32_t len); + +bool ets_bigint_mult_getz(uint32_t *z, uint32_t len); + +bool ets_bigint_montgomery_mult_prepare(uint32_t *x, uint32_t *y, uint32_t *m, + uint32_t m_dash, uint32_t len, bool again); + +bool ets_bigint_montgomery_mult_getz(uint32_t *z, uint32_t len); + +bool ets_bigint_mod_mult_prepare(uint32_t *x, uint32_t *y, uint32_t *m, + uint32_t m_dash, uint32_t *rb, uint32_t len, bool again); + +bool ets_bigint_mod_mult_getz(uint32_t *m, uint32_t *z, uint32_t len); + +#ifdef __cplusplus +} +#endif + +#endif /* _ROM_BIGINT_H_ */ diff --git a/tools/sdk/include/esp32/rom/cache.h b/tools/sdk/include/esp32/rom/cache.h new file mode 100644 index 00000000..fb84bca0 --- /dev/null +++ b/tools/sdk/include/esp32/rom/cache.h @@ -0,0 +1,146 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _ROM_CACHE_H_ +#define _ROM_CACHE_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup uart_apis, uart configuration and communication related apis + * @brief uart apis + */ + +/** @addtogroup uart_apis + * @{ + */ + +/** + * @brief Initialise cache mmu, mark all entries as invalid. + * Please do not call this function in your SDK application. + * + * @param int cpu_no : 0 for PRO cpu, 1 for APP cpu. + * + * @return None + */ +void mmu_init(int cpu_no); + +/** + * @brief Set Flash-Cache mmu mapping. + * Please do not call this function in your SDK application. + * + * @param int cpu_no : CPU number, 0 for PRO cpu, 1 for APP cpu. + * + * @param int pod : process identifier. Range 0~7. + * + * @param unsigned int vaddr : virtual address in CPU address space. + * Can be IRam0, IRam1, IRom0 and DRom0 memory address. + * Should be aligned by psize. + * + * @param unsigned int paddr : physical address in Flash. + * Should be aligned by psize. + * + * @param int psize : page size of flash, in kilobytes. Should be 64 here. + * + * @param int num : pages to be set. + * + * @return unsigned int: error status + * 0 : mmu set success + * 1 : vaddr or paddr is not aligned + * 2 : pid error + * 3 : psize error + * 4 : mmu table to be written is out of range + * 5 : vaddr is out of range + */ +unsigned int cache_flash_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num); + +/** + * @brief Set Ext-SRAM-Cache mmu mapping. + * Please do not call this function in your SDK application. + * + * @param int cpu_no : CPU number, 0 for PRO cpu, 1 for APP cpu. + * + * @param int pod : process identifier. Range 0~7. + * + * @param unsigned int vaddr : virtual address in CPU address space. + * Can be IRam0, IRam1, IRom0 and DRom0 memory address. + * Should be aligned by psize. + * + * @param unsigned int paddr : physical address in Ext-SRAM. + * Should be aligned by psize. + * + * @param int psize : page size of flash, in kilobytes. Should be 32 here. + * + * @param int num : pages to be set. + * + * @return unsigned int: error status + * 0 : mmu set success + * 1 : vaddr or paddr is not aligned + * 2 : pid error + * 3 : psize error + * 4 : mmu table to be written is out of range + * 5 : vaddr is out of range + */ +unsigned int cache_sram_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num); + +/** + * @brief Initialise cache access for the cpu. + * Please do not call this function in your SDK application. + * + * @param int cpu_no : 0 for PRO cpu, 1 for APP cpu. + * + * @return None + */ +void Cache_Read_Init(int cpu_no); + +/** + * @brief Flush the cache value for the cpu. + * Please do not call this function in your SDK application. + * + * @param int cpu_no : 0 for PRO cpu, 1 for APP cpu. + * + * @return None + */ +void Cache_Flush(int cpu_no); + +/** + * @brief Disable Cache access for the cpu. + * Please do not call this function in your SDK application. + * + * @param int cpu_no : 0 for PRO cpu, 1 for APP cpu. + * + * @return None + */ +void Cache_Read_Disable(int cpu_no); + +/** + * @brief Enable Cache access for the cpu. + * Please do not call this function in your SDK application. + * + * @param int cpu_no : 0 for PRO cpu, 1 for APP cpu. + * + * @return None + */ +void Cache_Read_Enable(int cpu_no); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* _ROM_CACHE_H_ */ diff --git a/tools/sdk/include/esp32/rom/crc.h b/tools/sdk/include/esp32/rom/crc.h new file mode 100644 index 00000000..84e17882 --- /dev/null +++ b/tools/sdk/include/esp32/rom/crc.h @@ -0,0 +1,127 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef ROM_CRC_H +#define ROM_CRC_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup uart_apis, uart configuration and communication related apis + * @brief uart apis + */ + +/** @addtogroup uart_apis + * @{ + */ + + +/* Standard CRC8/16/32 algorithms. */ +// CRC-8 x8+x2+x1+1 0x07 +// CRC16-CCITT x16+x12+x5+1 1021 ISO HDLC, ITU X.25, V.34/V.41/V.42, PPP-FCS +// CRC32: +//G(x) = x32 +x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x1 + 1 +//If your buf is not continuous, you can use the first result to be the second parameter. + +/** + * @brief Crc32 value that is in little endian. + * + * @param uint32_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +uint32_t crc32_le(uint32_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief Crc32 value that is in big endian. + * + * @param uint32_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +uint32_t crc32_be(uint32_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief Crc16 value that is in little endian. + * + * @param uint16_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +uint16_t crc16_le(uint16_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief Crc16 value that is in big endian. + * + * @param uint16_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +uint16_t crc16_be(uint16_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief Crc8 value that is in little endian. + * + * @param uint8_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +uint8_t crc8_le(uint8_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief Crc8 value that is in big endian. + * + * @param uint32_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +uint8_t crc8_be(uint8_t crc, uint8_t const *buf, uint32_t len); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif diff --git a/tools/sdk/include/esp32/rom/efuse.h b/tools/sdk/include/esp32/rom/efuse.h new file mode 100644 index 00000000..58cfdb20 --- /dev/null +++ b/tools/sdk/include/esp32/rom/efuse.h @@ -0,0 +1,112 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _ROM_EFUSE_H_ +#define _ROM_EFUSE_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup efuse_APIs efuse APIs + * @brief ESP32 efuse read/write APIs + * @attention + * + */ + +/** @addtogroup efuse_APIs + * @{ + */ + +/** + * @brief Do a efuse read operation, to update the efuse value to efuse read registers. + * + * @param null + * + * @return null + */ +void ets_efuse_read_op(void); + +/** + * @brief Do a efuse write operation, to update efuse write registers to efuse, then you need call ets_efuse_read_op again. + * + * @param null + * + * @return null + */ +void ets_efuse_program_op(void); + +/** + * @brief Read 8M Analog Clock value(8 bit) in efuse, the analog clock will not change with temperature. + * It can be used to test the external xtal frequency, do not touch this efuse field. + * + * @param null + * + * @return u32: 1 for 100KHZ, range is 0 to 255. + */ +uint32_t ets_efuse_get_8M_clock(void); + +/** + * @brief Read spi pad configuration, show gpio number of flash pad, includes 5 pads. + * + * @param null + * + * @return uint32_t: 0, invalid, flash pad decided by strapping + * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd + */ +uint32_t ets_efuse_get_spiconfig(void); + +#define EFUSE_SPICONFIG_RET_SPICLK_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPICLK_SHIFT 0 +#define EFUSE_SPICONFIG_RET_SPICLK(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICLK_SHIFT) & EFUSE_SPICONFIG_RET_SPICLK_MASK) + +#define EFUSE_SPICONFIG_RET_SPIQ_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPIQ_SHIFT 6 +#define EFUSE_SPICONFIG_RET_SPIQ(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIQ_SHIFT) & EFUSE_SPICONFIG_RET_SPIQ_MASK) + +#define EFUSE_SPICONFIG_RET_SPID_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPID_SHIFT 12 +#define EFUSE_SPICONFIG_RET_SPID(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPID_SHIFT) & EFUSE_SPICONFIG_RET_SPID_MASK) + +#define EFUSE_SPICONFIG_RET_SPICS0_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPICS0_SHIFT 18 +#define EFUSE_SPICONFIG_RET_SPICS0(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICS0_SHIFT) & EFUSE_SPICONFIG_RET_SPICS0_MASK) + + +#define EFUSE_SPICONFIG_RET_SPIHD_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPIHD_SHIFT 24 +#define EFUSE_SPICONFIG_RET_SPIHD(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIHD_SHIFT) & EFUSE_SPICONFIG_RET_SPIHD_MASK) + +/** + * @brief A crc8 algorithm used in efuse check. + * + * @param unsigned char const *p : Pointer to original data. + * + * @param unsigned int len : Data length in byte. + * + * @return unsigned char: Crc value. + */ +unsigned char esp_crc8(unsigned char const *p, unsigned int len); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* _ROM_EFUSE_H_ */ diff --git a/tools/sdk/include/esp32/rom/ets_sys.h b/tools/sdk/include/esp32/rom/ets_sys.h new file mode 100644 index 00000000..c412c9b4 --- /dev/null +++ b/tools/sdk/include/esp32/rom/ets_sys.h @@ -0,0 +1,616 @@ +// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _ROM_ETS_SYS_H_ +#define _ROM_ETS_SYS_H_ + +#include +#include + +#include "soc/soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup ets_sys_apis, ets system related apis + * @brief ets system apis + */ + +/** @addtogroup ets_sys_apis + * @{ + */ + +/************************************************************************ + * NOTE + * Many functions in this header files can't be run in FreeRTOS. + * Please see the comment of the Functions. + * There are also some functions that doesn't work on FreeRTOS + * without listed in the header, such as: + * xtos functions start with "_xtos_" in ld file. + * + *********************************************************************** + */ + +/** \defgroup ets_apis, Espressif Task Scheduler related apis + * @brief ets apis + */ + +/** @addtogroup ets_apis + * @{ + */ + +typedef enum { + ETS_OK = 0, /**< return successful in ets*/ + ETS_FAILED = 1 /**< return failed in ets*/ +} ETS_STATUS; + +typedef uint32_t ETSSignal; +typedef uint32_t ETSParam; + +typedef struct ETSEventTag ETSEvent; /**< Event transmit/receive in ets*/ + +struct ETSEventTag { + ETSSignal sig; /**< Event signal, in same task, different Event with different signal*/ + ETSParam par; /**< Event parameter, sometimes without usage, then will be set as 0*/ +}; + +typedef void (*ETSTask)(ETSEvent *e); /**< Type of the Task processer*/ +typedef void (* ets_idle_cb_t)(void *arg); /**< Type of the system idle callback*/ + +/** + * @brief Start the Espressif Task Scheduler, which is an infinit loop. Please do not add code after it. + * + * @param none + * + * @return none + */ +void ets_run(void); + +/** + * @brief Set the Idle callback, when Tasks are processed, will call the callback before CPU goto sleep. + * + * @param ets_idle_cb_t func : The callback function. + * + * @param void *arg : Argument of the callback. + * + * @return None + */ +void ets_set_idle_cb(ets_idle_cb_t func, void *arg); + +/** + * @brief Init a task with processer, priority, queue to receive Event, queue length. + * + * @param ETSTask task : The task processer. + * + * @param uint8_t prio : Task priority, 0-31, bigger num with high priority, one priority with one task. + * + * @param ETSEvent *queue : Queue belongs to the task, task always receives Events, Queue is circular used. + * + * @param uint8_t qlen : Queue length. + * + * @return None + */ +void ets_task(ETSTask task, uint8_t prio, ETSEvent *queue, uint8_t qlen); + +/** + * @brief Post an event to an Task. + * + * @param uint8_t prio : Priority of the Task. + * + * @param ETSSignal sig : Event signal. + * + * @param ETSParam par : Event parameter + * + * @return ETS_OK : post successful + * @return ETS_FAILED : post failed + */ +ETS_STATUS ets_post(uint8_t prio, ETSSignal sig, ETSParam par); + +/** + * @} + */ + +/** \defgroup ets_boot_apis, Boot routing related apis + * @brief ets boot apis + */ + +/** @addtogroup ets_apis + * @{ + */ + +extern const char *const exc_cause_table[40]; ///**< excption cause that defined by the core.*/ + +/** + * @brief Set Pro cpu Entry code, code can be called in PRO CPU when booting is not completed. + * When Pro CPU booting is completed, Pro CPU will call the Entry code if not NULL. + * + * @param uint32_t start : the PRO Entry code address value in uint32_t + * + * @return None + */ +void ets_set_user_start(uint32_t start); + +/** + * @brief Set Pro cpu Startup code, code can be called when booting is not completed, or in Entry code. + * When Entry code completed, CPU will call the Startup code if not NULL, else call ets_run. + * + * @param uint32_t callback : the Startup code address value in uint32_t + * + * @return None : post successful + */ +void ets_set_startup_callback(uint32_t callback); + +/** + * @brief Set App cpu Entry code, code can be called in PRO CPU. + * When APP booting is completed, APP CPU will call the Entry code if not NULL. + * + * @param uint32_t start : the APP Entry code address value in uint32_t, stored in register APPCPU_CTRL_REG_D. + * + * @return None + */ +void ets_set_appcpu_boot_addr(uint32_t start); + +/** + * @brief unpack the image in flash to iram and dram, no using cache. + * + * @param uint32_t pos : Flash physical address. + * + * @param uint32_t *entry_addr: the pointer of an variable that can store Entry code address. + * + * @param bool jump : Jump into the code in the function or not. + * + * @param bool config : Config the flash when unpacking the image, config should be done only once. + * + * @return ETS_OK : unpack successful + * @return ETS_FAILED : unpack failed + */ +ETS_STATUS ets_unpack_flash_code_legacy(uint32_t pos, uint32_t *entry_addr, bool jump, bool config); + +/** + * @brief unpack the image in flash to iram and dram, using cache, maybe decrypting. + * + * @param uint32_t pos : Flash physical address. + * + * @param uint32_t *entry_addr: the pointer of an variable that can store Entry code address. + * + * @param bool jump : Jump into the code in the function or not. + * + * @param bool sb_need_check : Do security boot check or not. + * + * @param bool config : Config the flash when unpacking the image, config should be done only once. + * + * @return ETS_OK : unpack successful + * @return ETS_FAILED : unpack failed + */ +ETS_STATUS ets_unpack_flash_code(uint32_t pos, uint32_t *entry_addr, bool jump, bool sb_need_check, bool config); + +/** + * @} + */ + +/** \defgroup ets_printf_apis, ets_printf related apis used in ets + * @brief ets printf apis + */ + +/** @addtogroup ets_printf_apis + * @{ + */ + +/** + * @brief Printf the strings to uart or other devices, similar with printf, simple than printf. + * Can not print float point data format, or longlong data format. + * So we maybe only use this in ROM. + * + * @param const char *fmt : See printf. + * + * @param ... : See printf. + * + * @return int : the length printed to the output device. + */ +int ets_printf(const char *fmt, ...); + +/** + * @brief Output a char to uart, which uart to output(which is in uart module in ROM) is not in scope of the function. + * Can not print float point data format, or longlong data format + * + * @param char c : char to output. + * + * @return None + */ +void ets_write_char_uart(char c); + +/** + * @brief Ets_printf have two output functions： putc1 and putc2, both of which will be called if need ouput. + * To install putc1, which is defaulted installed as ets_write_char_uart in none silent boot mode, as NULL in silent mode. + * + * @param void (*)(char) p: Output function to install. + * + * @return None + */ +void ets_install_putc1(void (*p)(char c)); + +/** + * @brief Ets_printf have two output functions： putc1 and putc2, both of which will be called if need ouput. + * To install putc2, which is defaulted installed as NULL. + * + * @param void (*)(char) p: Output function to install. + * + * @return None + */ +void ets_install_putc2(void (*p)(char c)); + +/** + * @brief Install putc1 as ets_write_char_uart. + * In silent boot mode(to void interfere the UART attached MCU), we can call this function, after booting ok. + * + * @param None + * + * @return None + */ +void ets_install_uart_printf(void); + +#define ETS_PRINTF(...) ets_printf(...) + +#define ETS_ASSERT(v) do { \ + if (!(v)) { \ + ets_printf("%s %u \n", __FILE__, __LINE__); \ + while (1) {}; \ + } \ +} while (0); + +/** + * @} + */ + +/** \defgroup ets_timer_apis, ets_timer related apis used in ets + * @brief ets timer apis + */ + +/** @addtogroup ets_timer_apis + * @{ + */ +typedef void ETSTimerFunc(void *timer_arg);/**< timer handler*/ + +typedef struct _ETSTIMER_ { + struct _ETSTIMER_ *timer_next; /**< timer linker*/ + uint32_t timer_expire; /**< abstruct time when timer expire*/ + uint32_t timer_period; /**< timer period, 0 means timer is not periodic repeated*/ + ETSTimerFunc *timer_func; /**< timer handler*/ + void *timer_arg; /**< timer handler argument*/ +} ETSTimer; + +/** + * @brief Init ets timer, this timer range is 640 us to 429496 ms + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ +void ets_timer_init(void); + +/** + * @brief Arm an ets timer, this timer range is 640 us to 429496 ms. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @param uint32_t tmout : Timer value in ms, range is 1 to 429496. + * + * @param bool repeat : Timer is periodic repeated. + * + * @return None + */ +void ets_timer_arm(ETSTimer *timer, uint32_t tmout, bool repeat); + +/** + * @brief Arm an ets timer, this timer range is 640 us to 429496 ms. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @param uint32_t tmout : Timer value in us, range is 1 to 429496729. + * + * @param bool repeat : Timer is periodic repeated. + * + * @return None + */ +void ets_timer_arm_us(ETSTimer *ptimer, uint32_t us, bool repeat); + +/** + * @brief Disarm an ets timer. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @return None + */ +void ets_timer_disarm(ETSTimer *timer); + +/** + * @brief Set timer callback and argument. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @param ETSTimerFunc *pfunction : Timer callback. + * + * @param void *parg : Timer callback argument. + * + * @return None + */ +void ets_timer_setfn(ETSTimer *ptimer, ETSTimerFunc *pfunction, void *parg); + +/** + * @brief Unset timer callback and argument to NULL. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @return None + */ +void ets_timer_done(ETSTimer *ptimer); + +/** + * @brief CPU do while loop for some time. + * In FreeRTOS task, please call FreeRTOS apis. + * + * @param uint32_t us : Delay time in us. + * + * @return None + */ +void ets_delay_us(uint32_t us); + +/** + * @brief Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate. + * Call this function when CPU frequency is changed. + * + * @param uint32_t ticks_per_us : CPU ticks per us. + * + * @return None + */ +void ets_update_cpu_frequency(uint32_t ticks_per_us); + +/** + * @brief Get the real CPU ticks per us to the ets. + * This function do not return real CPU ticks per us, just the record in ets. It can be used to check with the real CPU frequency. + * + * @param None + * + * @return uint32_t : CPU ticks per us record in ets. + */ +uint32_t ets_get_cpu_frequency(void); + +/** + * @brief Get xtal_freq/analog_8M*256 value calibrated in rtc module. + * + * @param None + * + * @return uint32_t : xtal_freq/analog_8M*256. + */ +uint32_t ets_get_xtal_scale(void); + +/** + * @brief Get xtal_freq value, If value not stored in RTC_STORE5, than store. + * + * @param None + * + * @return uint32_t : if rtc store the value (RTC_STORE5 high 16 bits and low 16 bits with same value), read from rtc register. + * clock = (REG_READ(RTC_STORE5) & 0xffff) << 12; + * else if analog_8M in efuse + * clock = ets_get_xtal_scale() * 15625 * ets_efuse_get_8M_clock() / 40; + * else clock = 26M. + */ +uint32_t ets_get_detected_xtal_freq(void); + +/** + * @} + */ + +/** \defgroup ets_intr_apis, ets interrupt configure related apis + * @brief ets intr apis + */ + +/** @addtogroup ets_intr_apis + * @{ + */ + +typedef void (* ets_isr_t)(void *);/**< interrupt handler type*/ + +/** + * @brief Attach a interrupt handler to a CPU interrupt number. + * This function equals to _xtos_set_interrupt_handler_arg(i, func, arg). + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param int i : CPU interrupt number. + * + * @param ets_isr_t func : Interrupt handler. + * + * @param void *arg : argument of the handler. + * + * @return None + */ +void ets_isr_attach(int i, ets_isr_t func, void *arg); + +/** + * @brief Mask the interrupts which show in mask bits. + * This function equals to _xtos_ints_off(mask). + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param uint32_t mask : BIT(i) means mask CPU interrupt number i. + * + * @return None + */ +void ets_isr_mask(uint32_t mask); + +/** + * @brief Unmask the interrupts which show in mask bits. + * This function equals to _xtos_ints_on(mask). + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param uint32_t mask : BIT(i) means mask CPU interrupt number i. + * + * @return None + */ +void ets_isr_unmask(uint32_t unmask); + +/** + * @brief Lock the interrupt to level 2. + * This function direct set the CPU registers. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ +void ets_intr_lock(void); + +/** + * @brief Unlock the interrupt to level 0. + * This function direct set the CPU registers. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ +void ets_intr_unlock(void); + +/** + * @brief Unlock the interrupt to level 0, and CPU will go into power save mode(wait interrupt). + * This function direct set the CPU registers. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ +void ets_waiti0(void); + +/** + * @brief Attach an CPU interrupt to a hardware source. + * We have 4 steps to use an interrupt: + * 1.Attach hardware interrupt source to CPU. intr_matrix_set(0, ETS_WIFI_MAC_INTR_SOURCE, ETS_WMAC_INUM); + * 2.Set interrupt handler. xt_set_interrupt_handler(ETS_WMAC_INUM, func, NULL); + * 3.Enable interrupt for CPU. xt_ints_on(1 << ETS_WMAC_INUM); + * 4.Enable interrupt in the module. + * + * @param int cpu_no : The CPU which the interrupt number belongs. + * + * @param uint32_t model_num : The interrupt hardware source number, please see the interrupt hardware source table. + * + * @param uint32_t intr_num : The interrupt number CPU, please see the interrupt cpu using table. + * + * @return None + */ +void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); + +#define _ETSTR(v) # v +#define _ETS_SET_INTLEVEL(intlevel) ({ unsigned __tmp; \ + __asm__ __volatile__( "rsil %0, " _ETSTR(intlevel) "\n" \ + : "=a" (__tmp) : : "memory" ); \ + }) + +#ifdef CONFIG_NONE_OS +#define ETS_INTR_LOCK() \ + ets_intr_lock() + +#define ETS_INTR_UNLOCK() \ + ets_intr_unlock() + +#define ETS_ISR_ATTACH \ + ets_isr_attach + +#define ETS_INTR_ENABLE(inum) \ + ets_isr_unmask((1< +#include + +#include "esp_attr.h" +#include "soc/gpio_reg.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup gpio_apis, uart configuration and communication related apis + * @brief gpio apis + */ + +/** @addtogroup gpio_apis + * @{ + */ + +#define GPIO_REG_READ(reg) READ_PERI_REG(reg) +#define GPIO_REG_WRITE(reg, val) WRITE_PERI_REG(reg, val) +#define GPIO_PIN_COUNT 40 +#define GPIO_ID_PIN0 0 +#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n)) +#define GPIO_PIN_ADDR(i) (GPIO_PIN0_REG + i*4) + +#define GPIO_ID_IS_PIN_REGISTER(reg_id) \ + ((reg_id >= GPIO_ID_PIN0) && (reg_id <= GPIO_ID_PIN(GPIO_PIN_COUNT-1))) + +#define GPIO_REGID_TO_PINIDX(reg_id) ((reg_id) - GPIO_ID_PIN0) + +typedef enum { + GPIO_PIN_INTR_DISABLE = 0, + GPIO_PIN_INTR_POSEDGE = 1, + GPIO_PIN_INTR_NEGEDGE = 2, + GPIO_PIN_INTR_ANYEGDE = 3, + GPIO_PIN_INTR_LOLEVEL = 4, + GPIO_PIN_INTR_HILEVEL = 5 +} GPIO_INT_TYPE; + +#define GPIO_OUTPUT_SET(gpio_no, bit_value) \ + ((gpio_no < 32) ? gpio_output_set(bit_value<>gpio_no)&BIT0) : ((gpio_input_get_high()>>(gpio_no - 32))&BIT0)) + +/* GPIO interrupt handler, registered through gpio_intr_handler_register */ +typedef void (* gpio_intr_handler_fn_t)(uint32_t intr_mask, bool high, void *arg); + +/** + * @brief Initialize GPIO. This includes reading the GPIO Configuration DataSet + * to initialize "output enables" and pin configurations for each gpio pin. + * Please do not call this function in SDK. + * + * @param None + * + * @return None + */ +void gpio_init(void); + +/** + * @brief Change GPIO(0-31) pin output by setting, clearing, or disabling pins, GPIO0<->BIT(0). + * There is no particular ordering guaranteed; so if the order of writes is significant, + * calling code should divide a single call into multiple calls. + * + * @param uint32_t set_mask : the gpios that need high level. + * + * @param uint32_t clear_mask : the gpios that need low level. + * + * @param uint32_t enable_mask : the gpios that need be changed. + * + * @param uint32_t disable_mask : the gpios that need diable output. + * + * @return None + */ +void gpio_output_set(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask); + +/** + * @brief Change GPIO(32-39) pin output by setting, clearing, or disabling pins, GPIO32<->BIT(0). + * There is no particular ordering guaranteed; so if the order of writes is significant, + * calling code should divide a single call into multiple calls. + * + * @param uint32_t set_mask : the gpios that need high level. + * + * @param uint32_t clear_mask : the gpios that need low level. + * + * @param uint32_t enable_mask : the gpios that need be changed. + * + * @param uint32_t disable_mask : the gpios that need diable output. + * + * @return None + */ +void gpio_output_set_high(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask); + +/** + * @brief Sample the value of GPIO input pins(0-31) and returns a bitmask. + * + * @param None + * + * @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO0. + */ +uint32_t gpio_input_get(void); + +/** + * @brief Sample the value of GPIO input pins(32-39) and returns a bitmask. + * + * @param None + * + * @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO32. + */ +uint32_t gpio_input_get_high(void); + +/** + * @brief Register an application-specific interrupt handler for GPIO pin interrupts. + * Once the interrupt handler is called, it will not be called again until after a call to gpio_intr_ack. + * Please do not call this function in SDK. + * + * @param gpio_intr_handler_fn_t fn : gpio application-specific interrupt handler + * + * @param void *arg : gpio application-specific interrupt handler argument. + * + * @return None + */ +void gpio_intr_handler_register(gpio_intr_handler_fn_t fn, void *arg); + +/** + * @brief Get gpio interrupts which happens but not processed. + * Please do not call this function in SDK. + * + * @param None + * + * @return uint32_t : bitmask for GPIO pending interrupts, BIT(0) for GPIO0. + */ +uint32_t gpio_intr_pending(void); + +/** + * @brief Get gpio interrupts which happens but not processed. + * Please do not call this function in SDK. + * + * @param None + * + * @return uint32_t : bitmask for GPIO pending interrupts, BIT(0) for GPIO32. + */ +uint32_t gpio_intr_pending_high(void); + +/** + * @brief Ack gpio interrupts to process pending interrupts. + * Please do not call this function in SDK. + * + * @param uint32_t ack_mask: bitmask for GPIO ack interrupts, BIT(0) for GPIO0. + * + * @return None + */ +void gpio_intr_ack(uint32_t ack_mask); + +/** + * @brief Ack gpio interrupts to process pending interrupts. + * Please do not call this function in SDK. + * + * @param uint32_t ack_mask: bitmask for GPIO ack interrupts, BIT(0) for GPIO32. + * + * @return None + */ +void gpio_intr_ack_high(uint32_t ack_mask); + +/** + * @brief Set GPIO to wakeup the ESP32. + * Please do not call this function in SDK. + * + * @param uint32_t i: gpio number. + * + * @param GPIO_INT_TYPE intr_state : only GPIO_PIN_INTR_LOLEVEL\GPIO_PIN_INTR_HILEVEL can be used + * + * @return None + */ +void gpio_pin_wakeup_enable(uint32_t i, GPIO_INT_TYPE intr_state); + +/** + * @brief disable GPIOs to wakeup the ESP32. + * Please do not call this function in SDK. + * + * @param None + * + * @return None + */ +void gpio_pin_wakeup_disable(void); + +/** + * @brief set gpio input to a signal, one gpio can input to several signals. + * + * @param uint32_t gpio : gpio number, 0~0x27 + * gpio == 0x30, input 0 to signal + * gpio == 0x34, ??? + * gpio == 0x38, input 1 to signal + * + * @param uint32_t signal_idx : signal index. + * + * @param bool inv : the signal is inv or not + * + * @return None + */ +void gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv); + +/** + * @brief set signal output to gpio, one signal can output to several gpios. + * + * @param uint32_t gpio : gpio number, 0~0x27 + * + * @param uint32_t signal_idx : signal index. + * signal_idx == 0x100, cancel output put to the gpio + * + * @param bool out_inv : the signal output is inv or not + * + * @param bool oen_inv : the signal output enable is inv or not + * + * @return None + */ +void gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, bool oen_inv); + +/** + * @brief Select pad as a gpio function from IOMUX. + * + * @param uint32_t gpio_num : gpio number, 0~0x27 + * + * @return None + */ +void gpio_pad_select_gpio(uint8_t gpio_num); + +/** + * @brief Set pad driver capability. + * + * @param uint32_t gpio_num : gpio number, 0~0x27 + * + * @param uint8_t drv : 0-3 + * + * @return None + */ +void gpio_pad_set_drv(uint8_t gpio_num, uint8_t drv); + +/** + * @brief Pull up the pad from gpio number. + * + * @param uint32_t gpio_num : gpio number, 0~0x27 + * + * @return None + */ +void gpio_pad_pullup(uint8_t gpio_num); + +/** + * @brief Pull down the pad from gpio number. + * + * @param uint32_t gpio_num : gpio number, 0~0x27 + * + * @return None + */ +void gpio_pad_pulldown(uint8_t gpio_num); + +/** + * @brief Unhold the pad from gpio number. + * + * @param uint32_t gpio_num : gpio number, 0~0x27 + * + * @return None + */ +void gpio_pad_unhold(uint8_t gpio_num); + +/** + * @brief Hold the pad from gpio number. + * + * @param uint32_t gpio_num : gpio number, 0~0x27 + * + * @return None + */ +void gpio_pad_hold(uint8_t gpio_num); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* _ROM_GPIO_H_ */ diff --git a/tools/sdk/include/esp32/rom/libc_stubs.h b/tools/sdk/include/esp32/rom/libc_stubs.h new file mode 100644 index 00000000..0c1876e5 --- /dev/null +++ b/tools/sdk/include/esp32/rom/libc_stubs.h @@ -0,0 +1,89 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _ROM_LIBC_STUBS_H_ +#define _ROM_LIBC_STUBS_H_ + +#include +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* +ESP32 ROM code contains implementations of some of C library functions. +Whenever a function in ROM needs to use a syscall, it calls a pointer to the corresponding syscall +implementation defined in the following struct. + +The table itself, by default, is not allocated in RAM. There are two pointers, `syscall_table_ptr_pro` and +`syscall_table_ptr_app`, which can be set to point to the locations of syscall tables of CPU 0 (aka PRO CPU) +and CPU 1 (aka APP CPU). Location of these pointers in .bss segment of ROM code is defined in linker script. + +So, before using any of the C library functions (except for pure functions and memcpy/memset functions), +application must allocate syscall table structure for each CPU being used, and populate it with pointers +to actual implementations of corresponding syscalls. +*/ + +struct syscall_stub_table +{ + struct _reent* (*__getreent)(void); + void* (*_malloc_r)(struct _reent *r, size_t); + void (*_free_r)(struct _reent *r, void*); + void* (*_realloc_r)(struct _reent *r, void*, size_t); + void* (*_calloc_r)(struct _reent *r, size_t, size_t); + void (*_abort)(void); + int (*_system_r)(struct _reent *r, const char*); + int (*_rename_r)(struct _reent *r, const char*, const char*); + clock_t (*_times_r)(struct _reent *r, struct tms *); + int (*_gettimeofday_r) (struct _reent *r, struct timeval *, void *); + void (*_raise_r)(struct _reent *r); + int (*_unlink_r)(struct _reent *r, const char*); + int (*_link_r)(struct _reent *r, const char*, const char*); + int (*_stat_r)(struct _reent *r, const char*, struct stat *); + int (*_fstat_r)(struct _reent *r, int, struct stat *); + void* (*_sbrk_r)(struct _reent *r, ptrdiff_t); + int (*_getpid_r)(struct _reent *r); + int (*_kill_r)(struct _reent *r, int, int); + void (*_exit_r)(struct _reent *r, int); + int (*_close_r)(struct _reent *r, int); + int (*_open_r)(struct _reent *r, const char *, int, int); + int (*_write_r)(struct _reent *r, int, const void *, int); + int (*_lseek_r)(struct _reent *r, int, int, int); + int (*_read_r)(struct _reent *r, int, void *, int); + void (*_lock_init)(_lock_t *lock); + void (*_lock_init_recursive)(_lock_t *lock); + void (*_lock_close)(_lock_t *lock); + void (*_lock_close_recursive)(_lock_t *lock); + void (*_lock_acquire)(_lock_t *lock); + void (*_lock_acquire_recursive)(_lock_t *lock); + int (*_lock_try_acquire)(_lock_t *lock); + int (*_lock_try_acquire_recursive)(_lock_t *lock); + void (*_lock_release)(_lock_t *lock); + void (*_lock_release_recursive)(_lock_t *lock); + int (*_printf_float)(struct _reent *data, void *pdata, FILE * fp, int (*pfunc) (struct _reent *, FILE *, _CONST char *, size_t len), va_list * ap); + int (*_scanf_float) (struct _reent *rptr, void *pdata, FILE *fp, va_list *ap); +}; + +extern struct syscall_stub_table* syscall_table_ptr_pro; +extern struct syscall_stub_table* syscall_table_ptr_app; + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif /* _ROM_LIBC_STUBS_H_ */ diff --git a/tools/sdk/include/esp32/rom/lldesc.h b/tools/sdk/include/esp32/rom/lldesc.h new file mode 100644 index 00000000..d027362a --- /dev/null +++ b/tools/sdk/include/esp32/rom/lldesc.h @@ -0,0 +1,176 @@ +// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _ROM_LLDESC_H_ +#define _ROM_LLDESC_H_ + +#include + +#include "queue.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define LLDESC_TX_MBLK_SIZE 268 /* */ +#define LLDESC_RX_SMBLK_SIZE 64 /* small block size, for small mgmt frame */ +#define LLDESC_RX_MBLK_SIZE 524 /* rx is large sinec we want to contain mgmt frame in one block*/ +#define LLDESC_RX_AMPDU_ENTRY_MBLK_SIZE 64 /* it is a small buffer which is a cycle link*/ +#define LLDESC_RX_AMPDU_LEN_MBLK_SIZE 256 /*for ampdu entry*/ +#ifdef ESP_MAC_5 +#define LLDESC_TX_MBLK_NUM 116 /* 64K / 256 */ +#define LLDESC_RX_MBLK_NUM 82 /* 64K / 512 MAX 172*/ +#define LLDESC_RX_AMPDU_ENTRY_MBLK_NUM 4 +#define LLDESC_RX_AMPDU_LEN_MLBK_NUM 12 +#else +#ifdef SBUF_RXTX +#define LLDESC_TX_MBLK_NUM_MAX (2 * 48) /* 23K / 260 - 8 */ +#define LLDESC_RX_MBLK_NUM_MAX (2 * 48) /* 23K / 524 */ +#define LLDESC_TX_MBLK_NUM_MIN (2 * 16) /* 23K / 260 - 8 */ +#define LLDESC_RX_MBLK_NUM_MIN (2 * 16) /* 23K / 524 */ +#endif +#define LLDESC_TX_MBLK_NUM 10 //(2 * 32) /* 23K / 260 - 8 */ + +#ifdef IEEE80211_RX_AMPDU +#define LLDESC_RX_MBLK_NUM 30 +#else +#define LLDESC_RX_MBLK_NUM 10 +#endif /*IEEE80211_RX_AMPDU*/ + +#define LLDESC_RX_AMPDU_ENTRY_MBLK_NUM 4 +#define LLDESC_RX_AMPDU_LEN_MLBK_NUM 8 +#endif /* !ESP_MAC_5 */ +/* + * SLC2 DMA Desc struct, aka lldesc_t + * + * -------------------------------------------------------------- + * | own | EoF | sub_sof | 5'b0 | length [11:0] | size [11:0] | + * -------------------------------------------------------------- + * | buf_ptr [31:0] | + * -------------------------------------------------------------- + * | next_desc_ptr [31:0] | + * -------------------------------------------------------------- + */ + +/* this bitfield is start from the LSB!!! */ +typedef struct lldesc_s { + volatile uint32_t size :12, + length:12, + offset: 5, /* h/w reserved 5bit, s/w use it as offset in buffer */ + sosf : 1, /* start of sub-frame */ + eof : 1, /* end of frame */ + owner : 1; /* hw or sw */ + volatile uint8_t *buf; /* point to buffer data */ + union{ + volatile uint32_t empty; + STAILQ_ENTRY(lldesc_s) qe; /* pointing to the next desc */ + }; +} lldesc_t; + +typedef struct tx_ampdu_entry_s{ + uint32_t sub_len :12, + dili_num : 7, + : 1, + null_byte: 2, + data : 1, + enc : 1, + seq : 8; +} tx_ampdu_entry_t; + +typedef struct lldesc_chain_s { + lldesc_t *head; + lldesc_t *tail; +} lldesc_chain_t; + +#ifdef SBUF_RXTX +enum sbuf_mask_s { + SBUF_MOVE_NO = 0, + SBUF_MOVE_TX2RX, + SBUF_MOVE_RX2TX, +} ; + +#define SBUF_MOVE_STEP 8 +#endif +#define LLDESC_SIZE sizeof(struct lldesc_s) + +/* SLC Descriptor */ +#define LLDESC_OWNER_MASK 0x80000000 +#define LLDESC_OWNER_SHIFT 31 +#define LLDESC_SW_OWNED 0 +#define LLDESC_HW_OWNED 1 + +#define LLDESC_EOF_MASK 0x40000000 +#define LLDESC_EOF_SHIFT 30 + +#define LLDESC_SOSF_MASK 0x20000000 +#define LLDESC_SOSF_SHIFT 29 + +#define LLDESC_LENGTH_MASK 0x00fff000 +#define LLDESC_LENGTH_SHIFT 12 + +#define LLDESC_SIZE_MASK 0x00000fff +#define LLDESC_SIZE_SHIFT 0 + +#define LLDESC_ADDR_MASK 0x000fffff + +void lldesc_build_chain(uint8_t *descptr, uint32_t desclen, uint8_t * mblkptr, uint32_t buflen, uint32_t blksz, uint8_t owner, + lldesc_t **head, +#ifdef TO_HOST_RESTART + lldesc_t ** one_before_tail, +#endif + lldesc_t **tail); + +lldesc_t *lldesc_num2link(lldesc_t * head, uint16_t nblks); + +lldesc_t *lldesc_set_owner(lldesc_t * head, uint16_t nblks, uint8_t owner); + +static inline uint32_t lldesc_get_chain_length(lldesc_t *head) +{ + lldesc_t *ds = head; + uint32_t len = 0; + + while (ds) { + len += ds->length; + ds = STAILQ_NEXT(ds, qe); + } + + return len; +} + +static inline void lldesc_config(lldesc_t *ds, uint8_t owner, uint8_t eof, uint8_t sosf, uint16_t len) +{ + ds->owner = owner; + ds->eof = eof; + ds->sosf = sosf; + ds->length = len; +} + +#define LLDESC_CONFIG(_desc, _owner, _eof, _sosf, _len) do { \ + (_desc)->owner = (_owner); \ + (_desc)->eof = (_eof); \ + (_desc)->sosf = (_sosf); \ + (_desc)->length = (_len); \ +} while(0) + +#define LLDESC_FROM_HOST_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, 0) + +#define LLDESC_MAC_RX_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, (ds)->size) + +#define LLDESC_TO_HOST_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, 0) + +#ifdef __cplusplus +} +#endif + +#endif /* _ROM_LLDESC_H_ */ diff --git a/tools/sdk/include/esp32/rom/md5_hash.h b/tools/sdk/include/esp32/rom/md5_hash.h new file mode 100755 index 00000000..f116f1e6 --- /dev/null +++ b/tools/sdk/include/esp32/rom/md5_hash.h @@ -0,0 +1,38 @@ +/* + * MD5 internal definitions + * Copyright (c) 2003-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +#ifndef _ROM_MD5_HASH_H_ +#define _ROM_MD5_HASH_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct MD5Context { + uint32_t buf[4]; + uint32_t bits[2]; + uint8_t in[64]; +}; + +void MD5Init(struct MD5Context *context); +void MD5Update(struct MD5Context *context, unsigned char const *buf, unsigned len); +void MD5Final(unsigned char digest[16], struct MD5Context *context); + +#ifdef __cplusplus +} +#endif + +#endif /* _ROM_MD5_HASH_H_ */ diff --git a/tools/sdk/include/esp32/rom/miniz.h b/tools/sdk/include/esp32/rom/miniz.h new file mode 100644 index 00000000..ed79beb2 --- /dev/null +++ b/tools/sdk/include/esp32/rom/miniz.h @@ -0,0 +1,777 @@ +#ifndef MINIZ_HEADER_INCLUDED +#define MINIZ_HEADER_INCLUDED + +#include + +// Defines to completely disable specific portions of miniz.c: +// If all macros here are defined the only functionality remaining will be CRC-32, adler-32, tinfl, and tdefl. + +// Define MINIZ_NO_STDIO to disable all usage and any functions which rely on stdio for file I/O. +#define MINIZ_NO_STDIO + +// If MINIZ_NO_TIME is specified then the ZIP archive functions will not be able to get the current time, or +// get/set file times, and the C run-time funcs that get/set times won't be called. +// The current downside is the times written to your archives will be from 1979. +#define MINIZ_NO_TIME + +// Define MINIZ_NO_ARCHIVE_APIS to disable all ZIP archive API's. +#define MINIZ_NO_ARCHIVE_APIS + +// Define MINIZ_NO_ARCHIVE_APIS to disable all writing related ZIP archive API's. +#define MINIZ_NO_ARCHIVE_WRITING_APIS + +// Define MINIZ_NO_ZLIB_APIS to remove all ZLIB-style compression/decompression API's. +#define MINIZ_NO_ZLIB_APIS + +// Define MINIZ_NO_ZLIB_COMPATIBLE_NAME to disable zlib names, to prevent conflicts against stock zlib. +#define MINIZ_NO_ZLIB_COMPATIBLE_NAMES + +// Define MINIZ_NO_MALLOC to disable all calls to malloc, free, and realloc. +// Note if MINIZ_NO_MALLOC is defined then the user must always provide custom user alloc/free/realloc +// callbacks to the zlib and archive API's, and a few stand-alone helper API's which don't provide custom user +// functions (such as tdefl_compress_mem_to_heap() and tinfl_decompress_mem_to_heap()) won't work. +#define MINIZ_NO_MALLOC + +#if defined(__TINYC__) && (defined(__linux) || defined(__linux__)) + // TODO: Work around "error: include file 'sys\utime.h' when compiling with tcc on Linux + #define MINIZ_NO_TIME +#endif + +#if !defined(MINIZ_NO_TIME) && !defined(MINIZ_NO_ARCHIVE_APIS) + #include +#endif + +//Hardcoded options for Xtensa - JD +#define MINIZ_X86_OR_X64_CPU 0 +#define MINIZ_LITTLE_ENDIAN 1 +#define MINIZ_USE_UNALIGNED_LOADS_AND_STORES 0 +#define MINIZ_HAS_64BIT_REGISTERS 0 +#define TINFL_USE_64BIT_BITBUF 0 + + +#if defined(_M_IX86) || defined(_M_X64) || defined(__i386__) || defined(__i386) || defined(__i486__) || defined(__i486) || defined(i386) || defined(__ia64__) || defined(__x86_64__) +// MINIZ_X86_OR_X64_CPU is only used to help set the below macros. +#define MINIZ_X86_OR_X64_CPU 1 +#endif + +#if (__BYTE_ORDER__==__ORDER_LITTLE_ENDIAN__) || MINIZ_X86_OR_X64_CPU +// Set MINIZ_LITTLE_ENDIAN to 1 if the processor is little endian. +#define MINIZ_LITTLE_ENDIAN 1 +#endif + +#if MINIZ_X86_OR_X64_CPU +// Set MINIZ_USE_UNALIGNED_LOADS_AND_STORES to 1 on CPU's that permit efficient integer loads and stores from unaligned addresses. +#define MINIZ_USE_UNALIGNED_LOADS_AND_STORES 1 +#endif + +#if defined(_M_X64) || defined(_WIN64) || defined(__MINGW64__) || defined(_LP64) || defined(__LP64__) || defined(__ia64__) || defined(__x86_64__) +// Set MINIZ_HAS_64BIT_REGISTERS to 1 if operations on 64-bit integers are reasonably fast (and don't involve compiler generated calls to helper functions). +#define MINIZ_HAS_64BIT_REGISTERS 1 +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +// ------------------- zlib-style API Definitions. + +// For more compatibility with zlib, miniz.c uses unsigned long for some parameters/struct members. Beware: mz_ulong can be either 32 or 64-bits! +typedef unsigned long mz_ulong; + +// mz_free() internally uses the MZ_FREE() macro (which by default calls free() unless you've modified the MZ_MALLOC macro) to release a block allocated from the heap. +void mz_free(void *p); + +#define MZ_ADLER32_INIT (1) +// mz_adler32() returns the initial adler-32 value to use when called with ptr==NULL. +mz_ulong mz_adler32(mz_ulong adler, const unsigned char *ptr, size_t buf_len); + +#define MZ_CRC32_INIT (0) +// mz_crc32() returns the initial CRC-32 value to use when called with ptr==NULL. +mz_ulong mz_crc32(mz_ulong crc, const unsigned char *ptr, size_t buf_len); + +// Compression strategies. +enum { MZ_DEFAULT_STRATEGY = 0, MZ_FILTERED = 1, MZ_HUFFMAN_ONLY = 2, MZ_RLE = 3, MZ_FIXED = 4 }; + +// Method +#define MZ_DEFLATED 8 + +#ifndef MINIZ_NO_ZLIB_APIS + +// Heap allocation callbacks. +// Note that mz_alloc_func parameter types purpsosely differ from zlib's: items/size is size_t, not unsigned long. +typedef void *(*mz_alloc_func)(void *opaque, size_t items, size_t size); +typedef void (*mz_free_func)(void *opaque, void *address); +typedef void *(*mz_realloc_func)(void *opaque, void *address, size_t items, size_t size); + +#define MZ_VERSION "9.1.15" +#define MZ_VERNUM 0x91F0 +#define MZ_VER_MAJOR 9 +#define MZ_VER_MINOR 1 +#define MZ_VER_REVISION 15 +#define MZ_VER_SUBREVISION 0 + +// Flush values. For typical usage you only need MZ_NO_FLUSH and MZ_FINISH. The other values are for advanced use (refer to the zlib docs). +enum { MZ_NO_FLUSH = 0, MZ_PARTIAL_FLUSH = 1, MZ_SYNC_FLUSH = 2, MZ_FULL_FLUSH = 3, MZ_FINISH = 4, MZ_BLOCK = 5 }; + +// Return status codes. MZ_PARAM_ERROR is non-standard. +enum { MZ_OK = 0, MZ_STREAM_END = 1, MZ_NEED_DICT = 2, MZ_ERRNO = -1, MZ_STREAM_ERROR = -2, MZ_DATA_ERROR = -3, MZ_MEM_ERROR = -4, MZ_BUF_ERROR = -5, MZ_VERSION_ERROR = -6, MZ_PARAM_ERROR = -10000 }; + +// Compression levels: 0-9 are the standard zlib-style levels, 10 is best possible compression (not zlib compatible, and may be very slow), MZ_DEFAULT_COMPRESSION=MZ_DEFAULT_LEVEL. +enum { MZ_NO_COMPRESSION = 0, MZ_BEST_SPEED = 1, MZ_BEST_COMPRESSION = 9, MZ_UBER_COMPRESSION = 10, MZ_DEFAULT_LEVEL = 6, MZ_DEFAULT_COMPRESSION = -1 }; + +// Window bits +#define MZ_DEFAULT_WINDOW_BITS 15 + +struct mz_internal_state; + +// Compression/decompression stream struct. +typedef struct mz_stream_s +{ + const unsigned char *next_in; // pointer to next byte to read + unsigned int avail_in; // number of bytes available at next_in + mz_ulong total_in; // total number of bytes consumed so far + + unsigned char *next_out; // pointer to next byte to write + unsigned int avail_out; // number of bytes that can be written to next_out + mz_ulong total_out; // total number of bytes produced so far + + char *msg; // error msg (unused) + struct mz_internal_state *state; // internal state, allocated by zalloc/zfree + + mz_alloc_func zalloc; // optional heap allocation function (defaults to malloc) + mz_free_func zfree; // optional heap free function (defaults to free) + void *opaque; // heap alloc function user pointer + + int data_type; // data_type (unused) + mz_ulong adler; // adler32 of the source or uncompressed data + mz_ulong reserved; // not used +} mz_stream; + +typedef mz_stream *mz_streamp; + +// Returns the version string of miniz.c. +const char *mz_version(void); + +// mz_deflateInit() initializes a compressor with default options: +// Parameters: +// pStream must point to an initialized mz_stream struct. +// level must be between [MZ_NO_COMPRESSION, MZ_BEST_COMPRESSION]. +// level 1 enables a specially optimized compression function that's been optimized purely for performance, not ratio. +// (This special func. is currently only enabled when MINIZ_USE_UNALIGNED_LOADS_AND_STORES and MINIZ_LITTLE_ENDIAN are defined.) +// Return values: +// MZ_OK on success. +// MZ_STREAM_ERROR if the stream is bogus. +// MZ_PARAM_ERROR if the input parameters are bogus. +// MZ_MEM_ERROR on out of memory. +int mz_deflateInit(mz_streamp pStream, int level); + +// mz_deflateInit2() is like mz_deflate(), except with more control: +// Additional parameters: +// method must be MZ_DEFLATED +// window_bits must be MZ_DEFAULT_WINDOW_BITS (to wrap the deflate stream with zlib header/adler-32 footer) or -MZ_DEFAULT_WINDOW_BITS (raw deflate/no header or footer) +// mem_level must be between [1, 9] (it's checked but ignored by miniz.c) +int mz_deflateInit2(mz_streamp pStream, int level, int method, int window_bits, int mem_level, int strategy); + +// Quickly resets a compressor without having to reallocate anything. Same as calling mz_deflateEnd() followed by mz_deflateInit()/mz_deflateInit2(). +int mz_deflateReset(mz_streamp pStream); + +// mz_deflate() compresses the input to output, consuming as much of the input and producing as much output as possible. +// Parameters: +// pStream is the stream to read from and write to. You must initialize/update the next_in, avail_in, next_out, and avail_out members. +// flush may be MZ_NO_FLUSH, MZ_PARTIAL_FLUSH/MZ_SYNC_FLUSH, MZ_FULL_FLUSH, or MZ_FINISH. +// Return values: +// MZ_OK on success (when flushing, or if more input is needed but not available, and/or there's more output to be written but the output buffer is full). +// MZ_STREAM_END if all input has been consumed and all output bytes have been written. Don't call mz_deflate() on the stream anymore. +// MZ_STREAM_ERROR if the stream is bogus. +// MZ_PARAM_ERROR if one of the parameters is invalid. +// MZ_BUF_ERROR if no forward progress is possible because the input and/or output buffers are empty. (Fill up the input buffer or free up some output space and try again.) +int mz_deflate(mz_streamp pStream, int flush); + +// mz_deflateEnd() deinitializes a compressor: +// Return values: +// MZ_OK on success. +// MZ_STREAM_ERROR if the stream is bogus. +int mz_deflateEnd(mz_streamp pStream); + +// mz_deflateBound() returns a (very) conservative upper bound on the amount of data that could be generated by deflate(), assuming flush is set to only MZ_NO_FLUSH or MZ_FINISH. +mz_ulong mz_deflateBound(mz_streamp pStream, mz_ulong source_len); + +// Single-call compression functions mz_compress() and mz_compress2(): +// Returns MZ_OK on success, or one of the error codes from mz_deflate() on failure. +int mz_compress(unsigned char *pDest, mz_ulong *pDest_len, const unsigned char *pSource, mz_ulong source_len); +int mz_compress2(unsigned char *pDest, mz_ulong *pDest_len, const unsigned char *pSource, mz_ulong source_len, int level); + +// mz_compressBound() returns a (very) conservative upper bound on the amount of data that could be generated by calling mz_compress(). +mz_ulong mz_compressBound(mz_ulong source_len); + +// Initializes a decompressor. +int mz_inflateInit(mz_streamp pStream); + +// mz_inflateInit2() is like mz_inflateInit() with an additional option that controls the window size and whether or not the stream has been wrapped with a zlib header/footer: +// window_bits must be MZ_DEFAULT_WINDOW_BITS (to parse zlib header/footer) or -MZ_DEFAULT_WINDOW_BITS (raw deflate). +int mz_inflateInit2(mz_streamp pStream, int window_bits); + +// Decompresses the input stream to the output, consuming only as much of the input as needed, and writing as much to the output as possible. +// Parameters: +// pStream is the stream to read from and write to. You must initialize/update the next_in, avail_in, next_out, and avail_out members. +// flush may be MZ_NO_FLUSH, MZ_SYNC_FLUSH, or MZ_FINISH. +// On the first call, if flush is MZ_FINISH it's assumed the input and output buffers are both sized large enough to decompress the entire stream in a single call (this is slightly faster). +// MZ_FINISH implies that there are no more source bytes available beside what's already in the input buffer, and that the output buffer is large enough to hold the rest of the decompressed data. +// Return values: +// MZ_OK on success. Either more input is needed but not available, and/or there's more output to be written but the output buffer is full. +// MZ_STREAM_END if all needed input has been consumed and all output bytes have been written. For zlib streams, the adler-32 of the decompressed data has also been verified. +// MZ_STREAM_ERROR if the stream is bogus. +// MZ_DATA_ERROR if the deflate stream is invalid. +// MZ_PARAM_ERROR if one of the parameters is invalid. +// MZ_BUF_ERROR if no forward progress is possible because the input buffer is empty but the inflater needs more input to continue, or if the output buffer is not large enough. Call mz_inflate() again +// with more input data, or with more room in the output buffer (except when using single call decompression, described above). +int mz_inflate(mz_streamp pStream, int flush); + +// Deinitializes a decompressor. +int mz_inflateEnd(mz_streamp pStream); + +// Single-call decompression. +// Returns MZ_OK on success, or one of the error codes from mz_inflate() on failure. +int mz_uncompress(unsigned char *pDest, mz_ulong *pDest_len, const unsigned char *pSource, mz_ulong source_len); + +// Returns a string description of the specified error code, or NULL if the error code is invalid. +const char *mz_error(int err); + +// Redefine zlib-compatible names to miniz equivalents, so miniz.c can be used as a drop-in replacement for the subset of zlib that miniz.c supports. +// Define MINIZ_NO_ZLIB_COMPATIBLE_NAMES to disable zlib-compatibility if you use zlib in the same project. +#ifndef MINIZ_NO_ZLIB_COMPATIBLE_NAMES + typedef unsigned char Byte; + typedef unsigned int uInt; + typedef mz_ulong uLong; + typedef Byte Bytef; + typedef uInt uIntf; + typedef char charf; + typedef int intf; + typedef void *voidpf; + typedef uLong uLongf; + typedef void *voidp; + typedef void *const voidpc; + #define Z_NULL 0 + #define Z_NO_FLUSH MZ_NO_FLUSH + #define Z_PARTIAL_FLUSH MZ_PARTIAL_FLUSH + #define Z_SYNC_FLUSH MZ_SYNC_FLUSH + #define Z_FULL_FLUSH MZ_FULL_FLUSH + #define Z_FINISH MZ_FINISH + #define Z_BLOCK MZ_BLOCK + #define Z_OK MZ_OK + #define Z_STREAM_END MZ_STREAM_END + #define Z_NEED_DICT MZ_NEED_DICT + #define Z_ERRNO MZ_ERRNO + #define Z_STREAM_ERROR MZ_STREAM_ERROR + #define Z_DATA_ERROR MZ_DATA_ERROR + #define Z_MEM_ERROR MZ_MEM_ERROR + #define Z_BUF_ERROR MZ_BUF_ERROR + #define Z_VERSION_ERROR MZ_VERSION_ERROR + #define Z_PARAM_ERROR MZ_PARAM_ERROR + #define Z_NO_COMPRESSION MZ_NO_COMPRESSION + #define Z_BEST_SPEED MZ_BEST_SPEED + #define Z_BEST_COMPRESSION MZ_BEST_COMPRESSION + #define Z_DEFAULT_COMPRESSION MZ_DEFAULT_COMPRESSION + #define Z_DEFAULT_STRATEGY MZ_DEFAULT_STRATEGY + #define Z_FILTERED MZ_FILTERED + #define Z_HUFFMAN_ONLY MZ_HUFFMAN_ONLY + #define Z_RLE MZ_RLE + #define Z_FIXED MZ_FIXED + #define Z_DEFLATED MZ_DEFLATED + #define Z_DEFAULT_WINDOW_BITS MZ_DEFAULT_WINDOW_BITS + #define alloc_func mz_alloc_func + #define free_func mz_free_func + #define internal_state mz_internal_state + #define z_stream mz_stream + #define deflateInit mz_deflateInit + #define deflateInit2 mz_deflateInit2 + #define deflateReset mz_deflateReset + #define deflate mz_deflate + #define deflateEnd mz_deflateEnd + #define deflateBound mz_deflateBound + #define compress mz_compress + #define compress2 mz_compress2 + #define compressBound mz_compressBound + #define inflateInit mz_inflateInit + #define inflateInit2 mz_inflateInit2 + #define inflate mz_inflate + #define inflateEnd mz_inflateEnd + #define uncompress mz_uncompress + #define crc32 mz_crc32 + #define adler32 mz_adler32 + #define MAX_WBITS 15 + #define MAX_MEM_LEVEL 9 + #define zError mz_error + #define ZLIB_VERSION MZ_VERSION + #define ZLIB_VERNUM MZ_VERNUM + #define ZLIB_VER_MAJOR MZ_VER_MAJOR + #define ZLIB_VER_MINOR MZ_VER_MINOR + #define ZLIB_VER_REVISION MZ_VER_REVISION + #define ZLIB_VER_SUBREVISION MZ_VER_SUBREVISION + #define zlibVersion mz_version + #define zlib_version mz_version() +#endif // #ifndef MINIZ_NO_ZLIB_COMPATIBLE_NAMES + +#endif // MINIZ_NO_ZLIB_APIS + +// ------------------- Types and macros + +typedef unsigned char mz_uint8; +typedef signed short mz_int16; +typedef unsigned short mz_uint16; +typedef unsigned int mz_uint32; +typedef unsigned int mz_uint; +typedef long long mz_int64; +typedef unsigned long long mz_uint64; +typedef int mz_bool; + +#define MZ_FALSE (0) +#define MZ_TRUE (1) + +// An attempt to work around MSVC's spammy "warning C4127: conditional expression is constant" message. +#ifdef _MSC_VER + #define MZ_MACRO_END while (0, 0) +#else + #define MZ_MACRO_END while (0) +#endif + +// ------------------- ZIP archive reading/writing + +#ifndef MINIZ_NO_ARCHIVE_APIS + +enum +{ + MZ_ZIP_MAX_IO_BUF_SIZE = 64*1024, + MZ_ZIP_MAX_ARCHIVE_FILENAME_SIZE = 260, + MZ_ZIP_MAX_ARCHIVE_FILE_COMMENT_SIZE = 256 +}; + +typedef struct +{ + mz_uint32 m_file_index; + mz_uint32 m_central_dir_ofs; + mz_uint16 m_version_made_by; + mz_uint16 m_version_needed; + mz_uint16 m_bit_flag; + mz_uint16 m_method; +#ifndef MINIZ_NO_TIME + time_t m_time; +#endif + mz_uint32 m_crc32; + mz_uint64 m_comp_size; + mz_uint64 m_uncomp_size; + mz_uint16 m_internal_attr; + mz_uint32 m_external_attr; + mz_uint64 m_local_header_ofs; + mz_uint32 m_comment_size; + char m_filename[MZ_ZIP_MAX_ARCHIVE_FILENAME_SIZE]; + char m_comment[MZ_ZIP_MAX_ARCHIVE_FILE_COMMENT_SIZE]; +} mz_zip_archive_file_stat; + +typedef size_t (*mz_file_read_func)(void *pOpaque, mz_uint64 file_ofs, void *pBuf, size_t n); +typedef size_t (*mz_file_write_func)(void *pOpaque, mz_uint64 file_ofs, const void *pBuf, size_t n); + +struct mz_zip_internal_state_tag; +typedef struct mz_zip_internal_state_tag mz_zip_internal_state; + +typedef enum +{ + MZ_ZIP_MODE_INVALID = 0, + MZ_ZIP_MODE_READING = 1, + MZ_ZIP_MODE_WRITING = 2, + MZ_ZIP_MODE_WRITING_HAS_BEEN_FINALIZED = 3 +} mz_zip_mode; + +typedef struct mz_zip_archive_tag +{ + mz_uint64 m_archive_size; + mz_uint64 m_central_directory_file_ofs; + mz_uint m_total_files; + mz_zip_mode m_zip_mode; + + mz_uint m_file_offset_alignment; + + mz_alloc_func m_pAlloc; + mz_free_func m_pFree; + mz_realloc_func m_pRealloc; + void *m_pAlloc_opaque; + + mz_file_read_func m_pRead; + mz_file_write_func m_pWrite; + void *m_pIO_opaque; + + mz_zip_internal_state *m_pState; + +} mz_zip_archive; + +typedef enum +{ + MZ_ZIP_FLAG_CASE_SENSITIVE = 0x0100, + MZ_ZIP_FLAG_IGNORE_PATH = 0x0200, + MZ_ZIP_FLAG_COMPRESSED_DATA = 0x0400, + MZ_ZIP_FLAG_DO_NOT_SORT_CENTRAL_DIRECTORY = 0x0800 +} mz_zip_flags; + +// ZIP archive reading + +// Inits a ZIP archive reader. +// These functions read and validate the archive's central directory. +mz_bool mz_zip_reader_init(mz_zip_archive *pZip, mz_uint64 size, mz_uint32 flags); +mz_bool mz_zip_reader_init_mem(mz_zip_archive *pZip, const void *pMem, size_t size, mz_uint32 flags); + +#ifndef MINIZ_NO_STDIO +mz_bool mz_zip_reader_init_file(mz_zip_archive *pZip, const char *pFilename, mz_uint32 flags); +#endif + +// Returns the total number of files in the archive. +mz_uint mz_zip_reader_get_num_files(mz_zip_archive *pZip); + +// Returns detailed information about an archive file entry. +mz_bool mz_zip_reader_file_stat(mz_zip_archive *pZip, mz_uint file_index, mz_zip_archive_file_stat *pStat); + +// Determines if an archive file entry is a directory entry. +mz_bool mz_zip_reader_is_file_a_directory(mz_zip_archive *pZip, mz_uint file_index); +mz_bool mz_zip_reader_is_file_encrypted(mz_zip_archive *pZip, mz_uint file_index); + +// Retrieves the filename of an archive file entry. +// Returns the number of bytes written to pFilename, or if filename_buf_size is 0 this function returns the number of bytes needed to fully store the filename. +mz_uint mz_zip_reader_get_filename(mz_zip_archive *pZip, mz_uint file_index, char *pFilename, mz_uint filename_buf_size); + +// Attempts to locates a file in the archive's central directory. +// Valid flags: MZ_ZIP_FLAG_CASE_SENSITIVE, MZ_ZIP_FLAG_IGNORE_PATH +// Returns -1 if the file cannot be found. +int mz_zip_reader_locate_file(mz_zip_archive *pZip, const char *pName, const char *pComment, mz_uint flags); + +// Extracts a archive file to a memory buffer using no memory allocation. +mz_bool mz_zip_reader_extract_to_mem_no_alloc(mz_zip_archive *pZip, mz_uint file_index, void *pBuf, size_t buf_size, mz_uint flags, void *pUser_read_buf, size_t user_read_buf_size); +mz_bool mz_zip_reader_extract_file_to_mem_no_alloc(mz_zip_archive *pZip, const char *pFilename, void *pBuf, size_t buf_size, mz_uint flags, void *pUser_read_buf, size_t user_read_buf_size); + +// Extracts a archive file to a memory buffer. +mz_bool mz_zip_reader_extract_to_mem(mz_zip_archive *pZip, mz_uint file_index, void *pBuf, size_t buf_size, mz_uint flags); +mz_bool mz_zip_reader_extract_file_to_mem(mz_zip_archive *pZip, const char *pFilename, void *pBuf, size_t buf_size, mz_uint flags); + +// Extracts a archive file to a dynamically allocated heap buffer. +void *mz_zip_reader_extract_to_heap(mz_zip_archive *pZip, mz_uint file_index, size_t *pSize, mz_uint flags); +void *mz_zip_reader_extract_file_to_heap(mz_zip_archive *pZip, const char *pFilename, size_t *pSize, mz_uint flags); + +// Extracts a archive file using a callback function to output the file's data. +mz_bool mz_zip_reader_extract_to_callback(mz_zip_archive *pZip, mz_uint file_index, mz_file_write_func pCallback, void *pOpaque, mz_uint flags); +mz_bool mz_zip_reader_extract_file_to_callback(mz_zip_archive *pZip, const char *pFilename, mz_file_write_func pCallback, void *pOpaque, mz_uint flags); + +#ifndef MINIZ_NO_STDIO +// Extracts a archive file to a disk file and sets its last accessed and modified times. +// This function only extracts files, not archive directory records. +mz_bool mz_zip_reader_extract_to_file(mz_zip_archive *pZip, mz_uint file_index, const char *pDst_filename, mz_uint flags); +mz_bool mz_zip_reader_extract_file_to_file(mz_zip_archive *pZip, const char *pArchive_filename, const char *pDst_filename, mz_uint flags); +#endif + +// Ends archive reading, freeing all allocations, and closing the input archive file if mz_zip_reader_init_file() was used. +mz_bool mz_zip_reader_end(mz_zip_archive *pZip); + +// ZIP archive writing + +#ifndef MINIZ_NO_ARCHIVE_WRITING_APIS + +// Inits a ZIP archive writer. +mz_bool mz_zip_writer_init(mz_zip_archive *pZip, mz_uint64 existing_size); +mz_bool mz_zip_writer_init_heap(mz_zip_archive *pZip, size_t size_to_reserve_at_beginning, size_t initial_allocation_size); + +#ifndef MINIZ_NO_STDIO +mz_bool mz_zip_writer_init_file(mz_zip_archive *pZip, const char *pFilename, mz_uint64 size_to_reserve_at_beginning); +#endif + +// Converts a ZIP archive reader object into a writer object, to allow efficient in-place file appends to occur on an existing archive. +// For archives opened using mz_zip_reader_init_file, pFilename must be the archive's filename so it can be reopened for writing. If the file can't be reopened, mz_zip_reader_end() will be called. +// For archives opened using mz_zip_reader_init_mem, the memory block must be growable using the realloc callback (which defaults to realloc unless you've overridden it). +// Finally, for archives opened using mz_zip_reader_init, the mz_zip_archive's user provided m_pWrite function cannot be NULL. +// Note: In-place archive modification is not recommended unless you know what you're doing, because if execution stops or something goes wrong before +// the archive is finalized the file's central directory will be hosed. +mz_bool mz_zip_writer_init_from_reader(mz_zip_archive *pZip, const char *pFilename); + +// Adds the contents of a memory buffer to an archive. These functions record the current local time into the archive. +// To add a directory entry, call this method with an archive name ending in a forwardslash with empty buffer. +// level_and_flags - compression level (0-10, see MZ_BEST_SPEED, MZ_BEST_COMPRESSION, etc.) logically OR'd with zero or more mz_zip_flags, or just set to MZ_DEFAULT_COMPRESSION. +mz_bool mz_zip_writer_add_mem(mz_zip_archive *pZip, const char *pArchive_name, const void *pBuf, size_t buf_size, mz_uint level_and_flags); +mz_bool mz_zip_writer_add_mem_ex(mz_zip_archive *pZip, const char *pArchive_name, const void *pBuf, size_t buf_size, const void *pComment, mz_uint16 comment_size, mz_uint level_and_flags, mz_uint64 uncomp_size, mz_uint32 uncomp_crc32); + +#ifndef MINIZ_NO_STDIO +// Adds the contents of a disk file to an archive. This function also records the disk file's modified time into the archive. +// level_and_flags - compression level (0-10, see MZ_BEST_SPEED, MZ_BEST_COMPRESSION, etc.) logically OR'd with zero or more mz_zip_flags, or just set to MZ_DEFAULT_COMPRESSION. +mz_bool mz_zip_writer_add_file(mz_zip_archive *pZip, const char *pArchive_name, const char *pSrc_filename, const void *pComment, mz_uint16 comment_size, mz_uint level_and_flags); +#endif + +// Adds a file to an archive by fully cloning the data from another archive. +// This function fully clones the source file's compressed data (no recompression), along with its full filename, extra data, and comment fields. +mz_bool mz_zip_writer_add_from_zip_reader(mz_zip_archive *pZip, mz_zip_archive *pSource_zip, mz_uint file_index); + +// Finalizes the archive by writing the central directory records followed by the end of central directory record. +// After an archive is finalized, the only valid call on the mz_zip_archive struct is mz_zip_writer_end(). +// An archive must be manually finalized by calling this function for it to be valid. +mz_bool mz_zip_writer_finalize_archive(mz_zip_archive *pZip); +mz_bool mz_zip_writer_finalize_heap_archive(mz_zip_archive *pZip, void **pBuf, size_t *pSize); + +// Ends archive writing, freeing all allocations, and closing the output file if mz_zip_writer_init_file() was used. +// Note for the archive to be valid, it must have been finalized before ending. +mz_bool mz_zip_writer_end(mz_zip_archive *pZip); + +// Misc. high-level helper functions: + +// mz_zip_add_mem_to_archive_file_in_place() efficiently (but not atomically) appends a memory blob to a ZIP archive. +// level_and_flags - compression level (0-10, see MZ_BEST_SPEED, MZ_BEST_COMPRESSION, etc.) logically OR'd with zero or more mz_zip_flags, or just set to MZ_DEFAULT_COMPRESSION. +mz_bool mz_zip_add_mem_to_archive_file_in_place(const char *pZip_filename, const char *pArchive_name, const void *pBuf, size_t buf_size, const void *pComment, mz_uint16 comment_size, mz_uint level_and_flags); + +// Reads a single file from an archive into a heap block. +// Returns NULL on failure. +void *mz_zip_extract_archive_file_to_heap(const char *pZip_filename, const char *pArchive_name, size_t *pSize, mz_uint zip_flags); + +#endif // #ifndef MINIZ_NO_ARCHIVE_WRITING_APIS + +#endif // #ifndef MINIZ_NO_ARCHIVE_APIS + +// ------------------- Low-level Decompression API Definitions + +// Decompression flags used by tinfl_decompress(). +// TINFL_FLAG_PARSE_ZLIB_HEADER: If set, the input has a valid zlib header and ends with an adler32 checksum (it's a valid zlib stream). Otherwise, the input is a raw deflate stream. +// TINFL_FLAG_HAS_MORE_INPUT: If set, there are more input bytes available beyond the end of the supplied input buffer. If clear, the input buffer contains all remaining input. +// TINFL_FLAG_USING_NON_WRAPPING_OUTPUT_BUF: If set, the output buffer is large enough to hold the entire decompressed stream. If clear, the output buffer is at least the size of the dictionary (typically 32KB). +// TINFL_FLAG_COMPUTE_ADLER32: Force adler-32 checksum computation of the decompressed bytes. +enum +{ + TINFL_FLAG_PARSE_ZLIB_HEADER = 1, + TINFL_FLAG_HAS_MORE_INPUT = 2, + TINFL_FLAG_USING_NON_WRAPPING_OUTPUT_BUF = 4, + TINFL_FLAG_COMPUTE_ADLER32 = 8 +}; + +// High level decompression functions: +// tinfl_decompress_mem_to_heap() decompresses a block in memory to a heap block allocated via malloc(). +// On entry: +// pSrc_buf, src_buf_len: Pointer and size of the Deflate or zlib source data to decompress. +// On return: +// Function returns a pointer to the decompressed data, or NULL on failure. +// *pOut_len will be set to the decompressed data's size, which could be larger than src_buf_len on uncompressible data. +// The caller must call mz_free() on the returned block when it's no longer needed. +void *tinfl_decompress_mem_to_heap(const void *pSrc_buf, size_t src_buf_len, size_t *pOut_len, int flags); + +// tinfl_decompress_mem_to_mem() decompresses a block in memory to another block in memory. +// Returns TINFL_DECOMPRESS_MEM_TO_MEM_FAILED on failure, or the number of bytes written on success. +#define TINFL_DECOMPRESS_MEM_TO_MEM_FAILED ((size_t)(-1)) +size_t tinfl_decompress_mem_to_mem(void *pOut_buf, size_t out_buf_len, const void *pSrc_buf, size_t src_buf_len, int flags); + +// tinfl_decompress_mem_to_callback() decompresses a block in memory to an internal 32KB buffer, and a user provided callback function will be called to flush the buffer. +// Returns 1 on success or 0 on failure. +typedef int (*tinfl_put_buf_func_ptr)(const void* pBuf, int len, void *pUser); +int tinfl_decompress_mem_to_callback(const void *pIn_buf, size_t *pIn_buf_size, tinfl_put_buf_func_ptr pPut_buf_func, void *pPut_buf_user, int flags); + +struct tinfl_decompressor_tag; typedef struct tinfl_decompressor_tag tinfl_decompressor; + +// Max size of LZ dictionary. +#define TINFL_LZ_DICT_SIZE 32768 + +// Return status. +typedef enum +{ + TINFL_STATUS_BAD_PARAM = -3, + TINFL_STATUS_ADLER32_MISMATCH = -2, + TINFL_STATUS_FAILED = -1, + TINFL_STATUS_DONE = 0, + TINFL_STATUS_NEEDS_MORE_INPUT = 1, + TINFL_STATUS_HAS_MORE_OUTPUT = 2 +} tinfl_status; + +// Initializes the decompressor to its initial state. +#define tinfl_init(r) do { (r)->m_state = 0; } MZ_MACRO_END +#define tinfl_get_adler32(r) (r)->m_check_adler32 + +// Main low-level decompressor coroutine function. This is the only function actually needed for decompression. All the other functions are just high-level helpers for improved usability. +// This is a universal API, i.e. it can be used as a building block to build any desired higher level decompression API. In the limit case, it can be called once per every byte input or output. +tinfl_status tinfl_decompress(tinfl_decompressor *r, const mz_uint8 *pIn_buf_next, size_t *pIn_buf_size, mz_uint8 *pOut_buf_start, mz_uint8 *pOut_buf_next, size_t *pOut_buf_size, const mz_uint32 decomp_flags); + +// Internal/private bits follow. +enum +{ + TINFL_MAX_HUFF_TABLES = 3, TINFL_MAX_HUFF_SYMBOLS_0 = 288, TINFL_MAX_HUFF_SYMBOLS_1 = 32, TINFL_MAX_HUFF_SYMBOLS_2 = 19, + TINFL_FAST_LOOKUP_BITS = 10, TINFL_FAST_LOOKUP_SIZE = 1 << TINFL_FAST_LOOKUP_BITS +}; + +typedef struct +{ + mz_uint8 m_code_size[TINFL_MAX_HUFF_SYMBOLS_0]; + mz_int16 m_look_up[TINFL_FAST_LOOKUP_SIZE], m_tree[TINFL_MAX_HUFF_SYMBOLS_0 * 2]; +} tinfl_huff_table; + +#if MINIZ_HAS_64BIT_REGISTERS + #define TINFL_USE_64BIT_BITBUF 1 +#endif + +#if TINFL_USE_64BIT_BITBUF + typedef mz_uint64 tinfl_bit_buf_t; + #define TINFL_BITBUF_SIZE (64) +#else + typedef mz_uint32 tinfl_bit_buf_t; + #define TINFL_BITBUF_SIZE (32) +#endif + +struct tinfl_decompressor_tag +{ + mz_uint32 m_state, m_num_bits, m_zhdr0, m_zhdr1, m_z_adler32, m_final, m_type, m_check_adler32, m_dist, m_counter, m_num_extra, m_table_sizes[TINFL_MAX_HUFF_TABLES]; + tinfl_bit_buf_t m_bit_buf; + size_t m_dist_from_out_buf_start; + tinfl_huff_table m_tables[TINFL_MAX_HUFF_TABLES]; + mz_uint8 m_raw_header[4], m_len_codes[TINFL_MAX_HUFF_SYMBOLS_0 + TINFL_MAX_HUFF_SYMBOLS_1 + 137]; +}; + +// ------------------- Low-level Compression API Definitions + +// Set TDEFL_LESS_MEMORY to 1 to use less memory (compression will be slightly slower, and raw/dynamic blocks will be output more frequently). +#define TDEFL_LESS_MEMORY 1 + +// tdefl_init() compression flags logically OR'd together (low 12 bits contain the max. number of probes per dictionary search): +// TDEFL_DEFAULT_MAX_PROBES: The compressor defaults to 128 dictionary probes per dictionary search. 0=Huffman only, 1=Huffman+LZ (fastest/crap compression), 4095=Huffman+LZ (slowest/best compression). +enum +{ + TDEFL_HUFFMAN_ONLY = 0, TDEFL_DEFAULT_MAX_PROBES = 128, TDEFL_MAX_PROBES_MASK = 0xFFF +}; + +// TDEFL_WRITE_ZLIB_HEADER: If set, the compressor outputs a zlib header before the deflate data, and the Adler-32 of the source data at the end. Otherwise, you'll get raw deflate data. +// TDEFL_COMPUTE_ADLER32: Always compute the adler-32 of the input data (even when not writing zlib headers). +// TDEFL_GREEDY_PARSING_FLAG: Set to use faster greedy parsing, instead of more efficient lazy parsing. +// TDEFL_NONDETERMINISTIC_PARSING_FLAG: Enable to decrease the compressor's initialization time to the minimum, but the output may vary from run to run given the same input (depending on the contents of memory). +// TDEFL_RLE_MATCHES: Only look for RLE matches (matches with a distance of 1) +// TDEFL_FILTER_MATCHES: Discards matches <= 5 chars if enabled. +// TDEFL_FORCE_ALL_STATIC_BLOCKS: Disable usage of optimized Huffman tables. +// TDEFL_FORCE_ALL_RAW_BLOCKS: Only use raw (uncompressed) deflate blocks. +// The low 12 bits are reserved to control the max # of hash probes per dictionary lookup (see TDEFL_MAX_PROBES_MASK). +enum +{ + TDEFL_WRITE_ZLIB_HEADER = 0x01000, + TDEFL_COMPUTE_ADLER32 = 0x02000, + TDEFL_GREEDY_PARSING_FLAG = 0x04000, + TDEFL_NONDETERMINISTIC_PARSING_FLAG = 0x08000, + TDEFL_RLE_MATCHES = 0x10000, + TDEFL_FILTER_MATCHES = 0x20000, + TDEFL_FORCE_ALL_STATIC_BLOCKS = 0x40000, + TDEFL_FORCE_ALL_RAW_BLOCKS = 0x80000 +}; + +// High level compression functions: +// tdefl_compress_mem_to_heap() compresses a block in memory to a heap block allocated via malloc(). +// On entry: +// pSrc_buf, src_buf_len: Pointer and size of source block to compress. +// flags: The max match finder probes (default is 128) logically OR'd against the above flags. Higher probes are slower but improve compression. +// On return: +// Function returns a pointer to the compressed data, or NULL on failure. +// *pOut_len will be set to the compressed data's size, which could be larger than src_buf_len on uncompressible data. +// The caller must free() the returned block when it's no longer needed. +void *tdefl_compress_mem_to_heap(const void *pSrc_buf, size_t src_buf_len, size_t *pOut_len, int flags); + +// tdefl_compress_mem_to_mem() compresses a block in memory to another block in memory. +// Returns 0 on failure. +size_t tdefl_compress_mem_to_mem(void *pOut_buf, size_t out_buf_len, const void *pSrc_buf, size_t src_buf_len, int flags); + +// Compresses an image to a compressed PNG file in memory. +// On entry: +// pImage, w, h, and num_chans describe the image to compress. num_chans may be 1, 2, 3, or 4. +// The image pitch in bytes per scanline will be w*num_chans. The leftmost pixel on the top scanline is stored first in memory. +// level may range from [0,10], use MZ_NO_COMPRESSION, MZ_BEST_SPEED, MZ_BEST_COMPRESSION, etc. or a decent default is MZ_DEFAULT_LEVEL +// If flip is true, the image will be flipped on the Y axis (useful for OpenGL apps). +// On return: +// Function returns a pointer to the compressed data, or NULL on failure. +// *pLen_out will be set to the size of the PNG image file. +// The caller must mz_free() the returned heap block (which will typically be larger than *pLen_out) when it's no longer needed. +void *tdefl_write_image_to_png_file_in_memory_ex(const void *pImage, int w, int h, int num_chans, size_t *pLen_out, mz_uint level, mz_bool flip); +void *tdefl_write_image_to_png_file_in_memory(const void *pImage, int w, int h, int num_chans, size_t *pLen_out); + +// Output stream interface. The compressor uses this interface to write compressed data. It'll typically be called TDEFL_OUT_BUF_SIZE at a time. +typedef mz_bool (*tdefl_put_buf_func_ptr)(const void* pBuf, int len, void *pUser); + +// tdefl_compress_mem_to_output() compresses a block to an output stream. The above helpers use this function internally. +mz_bool tdefl_compress_mem_to_output(const void *pBuf, size_t buf_len, tdefl_put_buf_func_ptr pPut_buf_func, void *pPut_buf_user, int flags); + +enum { TDEFL_MAX_HUFF_TABLES = 3, TDEFL_MAX_HUFF_SYMBOLS_0 = 288, TDEFL_MAX_HUFF_SYMBOLS_1 = 32, TDEFL_MAX_HUFF_SYMBOLS_2 = 19, TDEFL_LZ_DICT_SIZE = 32768, TDEFL_LZ_DICT_SIZE_MASK = TDEFL_LZ_DICT_SIZE - 1, TDEFL_MIN_MATCH_LEN = 3, TDEFL_MAX_MATCH_LEN = 258 }; + +// TDEFL_OUT_BUF_SIZE MUST be large enough to hold a single entire compressed output block (using static/fixed Huffman codes). +#if TDEFL_LESS_MEMORY +enum { TDEFL_LZ_CODE_BUF_SIZE = 24 * 1024, TDEFL_OUT_BUF_SIZE = (TDEFL_LZ_CODE_BUF_SIZE * 13 ) / 10, TDEFL_MAX_HUFF_SYMBOLS = 288, TDEFL_LZ_HASH_BITS = 12, TDEFL_LEVEL1_HASH_SIZE_MASK = 4095, TDEFL_LZ_HASH_SHIFT = (TDEFL_LZ_HASH_BITS + 2) / 3, TDEFL_LZ_HASH_SIZE = 1 << TDEFL_LZ_HASH_BITS }; +#else +enum { TDEFL_LZ_CODE_BUF_SIZE = 64 * 1024, TDEFL_OUT_BUF_SIZE = (TDEFL_LZ_CODE_BUF_SIZE * 13 ) / 10, TDEFL_MAX_HUFF_SYMBOLS = 288, TDEFL_LZ_HASH_BITS = 15, TDEFL_LEVEL1_HASH_SIZE_MASK = 4095, TDEFL_LZ_HASH_SHIFT = (TDEFL_LZ_HASH_BITS + 2) / 3, TDEFL_LZ_HASH_SIZE = 1 << TDEFL_LZ_HASH_BITS }; +#endif + +// The low-level tdefl functions below may be used directly if the above helper functions aren't flexible enough. The low-level functions don't make any heap allocations, unlike the above helper functions. +typedef enum +{ + TDEFL_STATUS_BAD_PARAM = -2, + TDEFL_STATUS_PUT_BUF_FAILED = -1, + TDEFL_STATUS_OKAY = 0, + TDEFL_STATUS_DONE = 1, +} tdefl_status; + +// Must map to MZ_NO_FLUSH, MZ_SYNC_FLUSH, etc. enums +typedef enum +{ + TDEFL_NO_FLUSH = 0, + TDEFL_SYNC_FLUSH = 2, + TDEFL_FULL_FLUSH = 3, + TDEFL_FINISH = 4 +} tdefl_flush; + +// tdefl's compression state structure. +typedef struct +{ + tdefl_put_buf_func_ptr m_pPut_buf_func; + void *m_pPut_buf_user; + mz_uint m_flags, m_max_probes[2]; + int m_greedy_parsing; + mz_uint m_adler32, m_lookahead_pos, m_lookahead_size, m_dict_size; + mz_uint8 *m_pLZ_code_buf, *m_pLZ_flags, *m_pOutput_buf, *m_pOutput_buf_end; + mz_uint m_num_flags_left, m_total_lz_bytes, m_lz_code_buf_dict_pos, m_bits_in, m_bit_buffer; + mz_uint m_saved_match_dist, m_saved_match_len, m_saved_lit, m_output_flush_ofs, m_output_flush_remaining, m_finished, m_block_index, m_wants_to_finish; + tdefl_status m_prev_return_status; + const void *m_pIn_buf; + void *m_pOut_buf; + size_t *m_pIn_buf_size, *m_pOut_buf_size; + tdefl_flush m_flush; + const mz_uint8 *m_pSrc; + size_t m_src_buf_left, m_out_buf_ofs; + mz_uint8 m_dict[TDEFL_LZ_DICT_SIZE + TDEFL_MAX_MATCH_LEN - 1]; + mz_uint16 m_huff_count[TDEFL_MAX_HUFF_TABLES][TDEFL_MAX_HUFF_SYMBOLS]; + mz_uint16 m_huff_codes[TDEFL_MAX_HUFF_TABLES][TDEFL_MAX_HUFF_SYMBOLS]; + mz_uint8 m_huff_code_sizes[TDEFL_MAX_HUFF_TABLES][TDEFL_MAX_HUFF_SYMBOLS]; + mz_uint8 m_lz_code_buf[TDEFL_LZ_CODE_BUF_SIZE]; + mz_uint16 m_next[TDEFL_LZ_DICT_SIZE]; + mz_uint16 m_hash[TDEFL_LZ_HASH_SIZE]; + mz_uint8 m_output_buf[TDEFL_OUT_BUF_SIZE]; +} tdefl_compressor; + +// Initializes the compressor. +// There is no corresponding deinit() function because the tdefl API's do not dynamically allocate memory. +// pBut_buf_func: If NULL, output data will be supplied to the specified callback. In this case, the user should call the tdefl_compress_buffer() API for compression. +// If pBut_buf_func is NULL the user should always call the tdefl_compress() API. +// flags: See the above enums (TDEFL_HUFFMAN_ONLY, TDEFL_WRITE_ZLIB_HEADER, etc.) +tdefl_status tdefl_init(tdefl_compressor *d, tdefl_put_buf_func_ptr pPut_buf_func, void *pPut_buf_user, int flags); + +// Compresses a block of data, consuming as much of the specified input buffer as possible, and writing as much compressed data to the specified output buffer as possible. +tdefl_status tdefl_compress(tdefl_compressor *d, const void *pIn_buf, size_t *pIn_buf_size, void *pOut_buf, size_t *pOut_buf_size, tdefl_flush flush); + +// tdefl_compress_buffer() is only usable when the tdefl_init() is called with a non-NULL tdefl_put_buf_func_ptr. +// tdefl_compress_buffer() always consumes the entire input buffer. +tdefl_status tdefl_compress_buffer(tdefl_compressor *d, const void *pIn_buf, size_t in_buf_size, tdefl_flush flush); + +tdefl_status tdefl_get_prev_return_status(tdefl_compressor *d); +mz_uint32 tdefl_get_adler32(tdefl_compressor *d); + +// Can't use tdefl_create_comp_flags_from_zip_params if MINIZ_NO_ZLIB_APIS isn't defined, because it uses some of its macros. +#ifndef MINIZ_NO_ZLIB_APIS +// Create tdefl_compress() flags given zlib-style compression parameters. +// level may range from [0,10] (where 10 is absolute max compression, but may be much slower on some files) +// window_bits may be -15 (raw deflate) or 15 (zlib) +// strategy may be either MZ_DEFAULT_STRATEGY, MZ_FILTERED, MZ_HUFFMAN_ONLY, MZ_RLE, or MZ_FIXED +mz_uint tdefl_create_comp_flags_from_zip_params(int level, int window_bits, int strategy); +#endif // #ifndef MINIZ_NO_ZLIB_APIS + +#ifdef __cplusplus +} +#endif + +#endif // MINIZ_HEADER_INCLUDED + diff --git a/tools/sdk/include/esp32/rom/queue.h b/tools/sdk/include/esp32/rom/queue.h new file mode 100755 index 00000000..29ee6706 --- /dev/null +++ b/tools/sdk/include/esp32/rom/queue.h @@ -0,0 +1,645 @@ +/*- + * Copyright (c) 1991, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)queue.h 8.5 (Berkeley) 8/20/94 + * $FreeBSD$ + */ + +#ifndef _SYS_QUEUE_H_ +#define _SYS_QUEUE_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This file defines four types of data structures: singly-linked lists, + * singly-linked tail queues, lists and tail queues. + * + * A singly-linked list is headed by a single forward pointer. The elements + * are singly linked for minimum space and pointer manipulation overhead at + * the expense of O(n) removal for arbitrary elements. New elements can be + * added to the list after an existing element or at the head of the list. + * Elements being removed from the head of the list should use the explicit + * macro for this purpose for optimum efficiency. A singly-linked list may + * only be traversed in the forward direction. Singly-linked lists are ideal + * for applications with large datasets and few or no removals or for + * implementing a LIFO queue. + * + * A singly-linked tail queue is headed by a pair of pointers, one to the + * head of the list and the other to the tail of the list. The elements are + * singly linked for minimum space and pointer manipulation overhead at the + * expense of O(n) removal for arbitrary elements. New elements can be added + * to the list after an existing element, at the head of the list, or at the + * end of the list. Elements being removed from the head of the tail queue + * should use the explicit macro for this purpose for optimum efficiency. + * A singly-linked tail queue may only be traversed in the forward direction. + * Singly-linked tail queues are ideal for applications with large datasets + * and few or no removals or for implementing a FIFO queue. + * + * A list is headed by a single forward pointer (or an array of forward + * pointers for a hash table header). The elements are doubly linked + * so that an arbitrary element can be removed without a need to + * traverse the list. New elements can be added to the list before + * or after an existing element or at the head of the list. A list + * may only be traversed in the forward direction. + * + * A tail queue is headed by a pair of pointers, one to the head of the + * list and the other to the tail of the list. The elements are doubly + * linked so that an arbitrary element can be removed without a need to + * traverse the list. New elements can be added to the list before or + * after an existing element, at the head of the list, or at the end of + * the list. A tail queue may be traversed in either direction. + * + * For details on the use of these macros, see the queue(3) manual page. + * + * + * SLIST LIST STAILQ TAILQ + * _HEAD + + + + + * _HEAD_INITIALIZER + + + + + * _ENTRY + + + + + * _INIT + + + + + * _EMPTY + + + + + * _FIRST + + + + + * _NEXT + + + + + * _PREV - - - + + * _LAST - - + + + * _FOREACH + + + + + * _FOREACH_SAFE + + + + + * _FOREACH_REVERSE - - - + + * _FOREACH_REVERSE_SAFE - - - + + * _INSERT_HEAD + + + + + * _INSERT_BEFORE - + - + + * _INSERT_AFTER + + + + + * _INSERT_TAIL - - + + + * _CONCAT - - + + + * _REMOVE_AFTER + - + - + * _REMOVE_HEAD + - + - + * _REMOVE + + + + + * + */ +#ifdef QUEUE_MACRO_DEBUG +/* Store the last 2 places the queue element or head was altered */ +struct qm_trace { + char * lastfile; + int lastline; + char * prevfile; + int prevline; +}; + +#define TRACEBUF struct qm_trace trace; +#define TRASHIT(x) do {(x) = (void *)-1;} while (0) +#define QMD_SAVELINK(name, link) void **name = (void *)&(link) + +#define QMD_TRACE_HEAD(head) do { \ + (head)->trace.prevline = (head)->trace.lastline; \ + (head)->trace.prevfile = (head)->trace.lastfile; \ + (head)->trace.lastline = __LINE__; \ + (head)->trace.lastfile = __FILE__; \ +} while (0) + +#define QMD_TRACE_ELEM(elem) do { \ + (elem)->trace.prevline = (elem)->trace.lastline; \ + (elem)->trace.prevfile = (elem)->trace.lastfile; \ + (elem)->trace.lastline = __LINE__; \ + (elem)->trace.lastfile = __FILE__; \ +} while (0) + +#else +#define QMD_TRACE_ELEM(elem) +#define QMD_TRACE_HEAD(head) +#define QMD_SAVELINK(name, link) +#define TRACEBUF +#define TRASHIT(x) +#endif /* QUEUE_MACRO_DEBUG */ + +/* + * Singly-linked List declarations. + */ +#define SLIST_HEAD(name, type) \ +struct name { \ + struct type *slh_first; /* first element */ \ +} + +#define SLIST_HEAD_INITIALIZER(head) \ + { NULL } + +#define SLIST_ENTRY(type) \ +struct { \ + struct type *sle_next; /* next element */ \ +} + +/* + * Singly-linked List functions. + */ +#define SLIST_EMPTY(head) ((head)->slh_first == NULL) + +#define SLIST_FIRST(head) ((head)->slh_first) + +#define SLIST_FOREACH(var, head, field) \ + for ((var) = SLIST_FIRST((head)); \ + (var); \ + (var) = SLIST_NEXT((var), field)) + +#define SLIST_FOREACH_SAFE(var, head, field, tvar) \ + for ((var) = SLIST_FIRST((head)); \ + (var) && ((tvar) = SLIST_NEXT((var), field), 1); \ + (var) = (tvar)) + +#define SLIST_FOREACH_PREVPTR(var, varp, head, field) \ + for ((varp) = &SLIST_FIRST((head)); \ + ((var) = *(varp)) != NULL; \ + (varp) = &SLIST_NEXT((var), field)) + +#define SLIST_INIT(head) do { \ + SLIST_FIRST((head)) = NULL; \ +} while (0) + +#define SLIST_INSERT_AFTER(slistelm, elm, field) do { \ + SLIST_NEXT((elm), field) = SLIST_NEXT((slistelm), field); \ + SLIST_NEXT((slistelm), field) = (elm); \ +} while (0) + +#define SLIST_INSERT_HEAD(head, elm, field) do { \ + SLIST_NEXT((elm), field) = SLIST_FIRST((head)); \ + SLIST_FIRST((head)) = (elm); \ +} while (0) + +#define SLIST_NEXT(elm, field) ((elm)->field.sle_next) + +#define SLIST_REMOVE(head, elm, type, field) do { \ + QMD_SAVELINK(oldnext, (elm)->field.sle_next); \ + if (SLIST_FIRST((head)) == (elm)) { \ + SLIST_REMOVE_HEAD((head), field); \ + } \ + else { \ + struct type *curelm = SLIST_FIRST((head)); \ + while (SLIST_NEXT(curelm, field) != (elm)) \ + curelm = SLIST_NEXT(curelm, field); \ + SLIST_REMOVE_AFTER(curelm, field); \ + } \ + TRASHIT(*oldnext); \ +} while (0) + +#define SLIST_REMOVE_AFTER(elm, field) do { \ + SLIST_NEXT(elm, field) = \ + SLIST_NEXT(SLIST_NEXT(elm, field), field); \ +} while (0) + +#define SLIST_REMOVE_HEAD(head, field) do { \ + SLIST_FIRST((head)) = SLIST_NEXT(SLIST_FIRST((head)), field); \ +} while (0) + +/* + * Singly-linked Tail queue declarations. + */ +#define STAILQ_HEAD(name, type) \ +struct name { \ + struct type *stqh_first;/* first element */ \ + struct type **stqh_last;/* addr of last next element */ \ +} + +#define STAILQ_HEAD_INITIALIZER(head) \ + { NULL, &(head).stqh_first } + +#define STAILQ_ENTRY(type) \ +struct { \ + struct type *stqe_next; /* next element */ \ +} + +/* + * Singly-linked Tail queue functions. + */ +#define STAILQ_CONCAT(head1, head2) do { \ + if (!STAILQ_EMPTY((head2))) { \ + *(head1)->stqh_last = (head2)->stqh_first; \ + (head1)->stqh_last = (head2)->stqh_last; \ + STAILQ_INIT((head2)); \ + } \ +} while (0) + +#define STAILQ_EMPTY(head) ((head)->stqh_first == NULL) + +#define STAILQ_FIRST(head) ((head)->stqh_first) + +#define STAILQ_FOREACH(var, head, field) \ + for((var) = STAILQ_FIRST((head)); \ + (var); \ + (var) = STAILQ_NEXT((var), field)) + + +#define STAILQ_FOREACH_SAFE(var, head, field, tvar) \ + for ((var) = STAILQ_FIRST((head)); \ + (var) && ((tvar) = STAILQ_NEXT((var), field), 1); \ + (var) = (tvar)) + +#define STAILQ_INIT(head) do { \ + STAILQ_FIRST((head)) = NULL; \ + (head)->stqh_last = &STAILQ_FIRST((head)); \ +} while (0) + +#define STAILQ_INSERT_AFTER(head, tqelm, elm, field) do { \ + if ((STAILQ_NEXT((elm), field) = STAILQ_NEXT((tqelm), field)) == NULL)\ + (head)->stqh_last = &STAILQ_NEXT((elm), field); \ + STAILQ_NEXT((tqelm), field) = (elm); \ +} while (0) + +#define STAILQ_INSERT_HEAD(head, elm, field) do { \ + if ((STAILQ_NEXT((elm), field) = STAILQ_FIRST((head))) == NULL) \ + (head)->stqh_last = &STAILQ_NEXT((elm), field); \ + STAILQ_FIRST((head)) = (elm); \ +} while (0) + +#define STAILQ_INSERT_TAIL(head, elm, field) do { \ + STAILQ_NEXT((elm), field) = NULL; \ + *(head)->stqh_last = (elm); \ + (head)->stqh_last = &STAILQ_NEXT((elm), field); \ +} while (0) + +#define STAILQ_LAST(head, type, field) \ + (STAILQ_EMPTY((head)) ? \ + NULL : \ + ((struct type *)(void *) \ + ((char *)((head)->stqh_last) - __offsetof(struct type, field)))) + +#define STAILQ_NEXT(elm, field) ((elm)->field.stqe_next) + +#define STAILQ_REMOVE(head, elm, type, field) do { \ + QMD_SAVELINK(oldnext, (elm)->field.stqe_next); \ + if (STAILQ_FIRST((head)) == (elm)) { \ + STAILQ_REMOVE_HEAD((head), field); \ + } \ + else { \ + struct type *curelm = STAILQ_FIRST((head)); \ + while (STAILQ_NEXT(curelm, field) != (elm)) \ + curelm = STAILQ_NEXT(curelm, field); \ + STAILQ_REMOVE_AFTER(head, curelm, field); \ + } \ + TRASHIT(*oldnext); \ +} while (0) + +#define STAILQ_REMOVE_HEAD(head, field) do { \ + if ((STAILQ_FIRST((head)) = \ + STAILQ_NEXT(STAILQ_FIRST((head)), field)) == NULL) \ + (head)->stqh_last = &STAILQ_FIRST((head)); \ +} while (0) + +#define STAILQ_REMOVE_AFTER(head, elm, field) do { \ + if ((STAILQ_NEXT(elm, field) = \ + STAILQ_NEXT(STAILQ_NEXT(elm, field), field)) == NULL) \ + (head)->stqh_last = &STAILQ_NEXT((elm), field); \ +} while (0) + +#define STAILQ_SWAP(head1, head2, type) do { \ + struct type *swap_first = STAILQ_FIRST(head1); \ + struct type **swap_last = (head1)->stqh_last; \ + STAILQ_FIRST(head1) = STAILQ_FIRST(head2); \ + (head1)->stqh_last = (head2)->stqh_last; \ + STAILQ_FIRST(head2) = swap_first; \ + (head2)->stqh_last = swap_last; \ + if (STAILQ_EMPTY(head1)) \ + (head1)->stqh_last = &STAILQ_FIRST(head1); \ + if (STAILQ_EMPTY(head2)) \ + (head2)->stqh_last = &STAILQ_FIRST(head2); \ +} while (0) + +#define STAILQ_INSERT_CHAIN_HEAD(head, elm_chead, elm_ctail, field) do { \ + if ((STAILQ_NEXT(elm_ctail, field) = STAILQ_FIRST(head)) == NULL ) { \ + (head)->stqh_last = &STAILQ_NEXT(elm_ctail, field); \ + } \ + STAILQ_FIRST(head) = (elm_chead); \ +} while (0) + + +/* + * List declarations. + */ +#define LIST_HEAD(name, type) \ +struct name { \ + struct type *lh_first; /* first element */ \ +} + +#define LIST_HEAD_INITIALIZER(head) \ + { NULL } + +#define LIST_ENTRY(type) \ +struct { \ + struct type *le_next; /* next element */ \ + struct type **le_prev; /* address of previous next element */ \ +} + +/* + * List functions. + */ + +#if (defined(_KERNEL) && defined(INVARIANTS)) +#define QMD_LIST_CHECK_HEAD(head, field) do { \ + if (LIST_FIRST((head)) != NULL && \ + LIST_FIRST((head))->field.le_prev != \ + &LIST_FIRST((head))) \ + panic("Bad list head %p first->prev != head", (head)); \ +} while (0) + +#define QMD_LIST_CHECK_NEXT(elm, field) do { \ + if (LIST_NEXT((elm), field) != NULL && \ + LIST_NEXT((elm), field)->field.le_prev != \ + &((elm)->field.le_next)) \ + panic("Bad link elm %p next->prev != elm", (elm)); \ +} while (0) + +#define QMD_LIST_CHECK_PREV(elm, field) do { \ + if (*(elm)->field.le_prev != (elm)) \ + panic("Bad link elm %p prev->next != elm", (elm)); \ +} while (0) +#else +#define QMD_LIST_CHECK_HEAD(head, field) +#define QMD_LIST_CHECK_NEXT(elm, field) +#define QMD_LIST_CHECK_PREV(elm, field) +#endif /* (_KERNEL && INVARIANTS) */ + +#define LIST_EMPTY(head) ((head)->lh_first == NULL) + +#define LIST_FIRST(head) ((head)->lh_first) + +#define LIST_FOREACH(var, head, field) \ + for ((var) = LIST_FIRST((head)); \ + (var); \ + (var) = LIST_NEXT((var), field)) + +#define LIST_FOREACH_SAFE(var, head, field, tvar) \ + for ((var) = LIST_FIRST((head)); \ + (var) && ((tvar) = LIST_NEXT((var), field), 1); \ + (var) = (tvar)) + +#define LIST_INIT(head) do { \ + LIST_FIRST((head)) = NULL; \ +} while (0) + +#define LIST_INSERT_AFTER(listelm, elm, field) do { \ + QMD_LIST_CHECK_NEXT(listelm, field); \ + if ((LIST_NEXT((elm), field) = LIST_NEXT((listelm), field)) != NULL)\ + LIST_NEXT((listelm), field)->field.le_prev = \ + &LIST_NEXT((elm), field); \ + LIST_NEXT((listelm), field) = (elm); \ + (elm)->field.le_prev = &LIST_NEXT((listelm), field); \ +} while (0) + +#define LIST_INSERT_BEFORE(listelm, elm, field) do { \ + QMD_LIST_CHECK_PREV(listelm, field); \ + (elm)->field.le_prev = (listelm)->field.le_prev; \ + LIST_NEXT((elm), field) = (listelm); \ + *(listelm)->field.le_prev = (elm); \ + (listelm)->field.le_prev = &LIST_NEXT((elm), field); \ +} while (0) + +#define LIST_INSERT_HEAD(head, elm, field) do { \ + QMD_LIST_CHECK_HEAD((head), field); \ + if ((LIST_NEXT((elm), field) = LIST_FIRST((head))) != NULL) \ + LIST_FIRST((head))->field.le_prev = &LIST_NEXT((elm), field);\ + LIST_FIRST((head)) = (elm); \ + (elm)->field.le_prev = &LIST_FIRST((head)); \ +} while (0) + +#define LIST_NEXT(elm, field) ((elm)->field.le_next) + +#define LIST_REMOVE(elm, field) do { \ + QMD_SAVELINK(oldnext, (elm)->field.le_next); \ + QMD_SAVELINK(oldprev, (elm)->field.le_prev); \ + QMD_LIST_CHECK_NEXT(elm, field); \ + QMD_LIST_CHECK_PREV(elm, field); \ + if (LIST_NEXT((elm), field) != NULL) \ + LIST_NEXT((elm), field)->field.le_prev = \ + (elm)->field.le_prev; \ + *(elm)->field.le_prev = LIST_NEXT((elm), field); \ + TRASHIT(*oldnext); \ + TRASHIT(*oldprev); \ +} while (0) + +#define LIST_SWAP(head1, head2, type, field) do { \ + struct type *swap_tmp = LIST_FIRST((head1)); \ + LIST_FIRST((head1)) = LIST_FIRST((head2)); \ + LIST_FIRST((head2)) = swap_tmp; \ + if ((swap_tmp = LIST_FIRST((head1))) != NULL) \ + swap_tmp->field.le_prev = &LIST_FIRST((head1)); \ + if ((swap_tmp = LIST_FIRST((head2))) != NULL) \ + swap_tmp->field.le_prev = &LIST_FIRST((head2)); \ +} while (0) + +/* + * Tail queue declarations. + */ +#define TAILQ_HEAD(name, type) \ +struct name { \ + struct type *tqh_first; /* first element */ \ + struct type **tqh_last; /* addr of last next element */ \ + TRACEBUF \ +} + +#define TAILQ_HEAD_INITIALIZER(head) \ + { NULL, &(head).tqh_first } + +#define TAILQ_ENTRY(type) \ +struct { \ + struct type *tqe_next; /* next element */ \ + struct type **tqe_prev; /* address of previous next element */ \ + TRACEBUF \ +} + +/* + * Tail queue functions. + */ +#if (defined(_KERNEL) && defined(INVARIANTS)) +#define QMD_TAILQ_CHECK_HEAD(head, field) do { \ + if (!TAILQ_EMPTY(head) && \ + TAILQ_FIRST((head))->field.tqe_prev != \ + &TAILQ_FIRST((head))) \ + panic("Bad tailq head %p first->prev != head", (head)); \ +} while (0) + +#define QMD_TAILQ_CHECK_TAIL(head, field) do { \ + if (*(head)->tqh_last != NULL) \ + panic("Bad tailq NEXT(%p->tqh_last) != NULL", (head)); \ +} while (0) + +#define QMD_TAILQ_CHECK_NEXT(elm, field) do { \ + if (TAILQ_NEXT((elm), field) != NULL && \ + TAILQ_NEXT((elm), field)->field.tqe_prev != \ + &((elm)->field.tqe_next)) \ + panic("Bad link elm %p next->prev != elm", (elm)); \ +} while (0) + +#define QMD_TAILQ_CHECK_PREV(elm, field) do { \ + if (*(elm)->field.tqe_prev != (elm)) \ + panic("Bad link elm %p prev->next != elm", (elm)); \ +} while (0) +#else +#define QMD_TAILQ_CHECK_HEAD(head, field) +#define QMD_TAILQ_CHECK_TAIL(head, headname) +#define QMD_TAILQ_CHECK_NEXT(elm, field) +#define QMD_TAILQ_CHECK_PREV(elm, field) +#endif /* (_KERNEL && INVARIANTS) */ + +#define TAILQ_CONCAT(head1, head2, field) do { \ + if (!TAILQ_EMPTY(head2)) { \ + *(head1)->tqh_last = (head2)->tqh_first; \ + (head2)->tqh_first->field.tqe_prev = (head1)->tqh_last; \ + (head1)->tqh_last = (head2)->tqh_last; \ + TAILQ_INIT((head2)); \ + QMD_TRACE_HEAD(head1); \ + QMD_TRACE_HEAD(head2); \ + } \ +} while (0) + +#define TAILQ_EMPTY(head) ((head)->tqh_first == NULL) + +#define TAILQ_FIRST(head) ((head)->tqh_first) + +#define TAILQ_FOREACH(var, head, field) \ + for ((var) = TAILQ_FIRST((head)); \ + (var); \ + (var) = TAILQ_NEXT((var), field)) + +#define TAILQ_FOREACH_SAFE(var, head, field, tvar) \ + for ((var) = TAILQ_FIRST((head)); \ + (var) && ((tvar) = TAILQ_NEXT((var), field), 1); \ + (var) = (tvar)) + +#define TAILQ_FOREACH_REVERSE(var, head, headname, field) \ + for ((var) = TAILQ_LAST((head), headname); \ + (var); \ + (var) = TAILQ_PREV((var), headname, field)) + +#define TAILQ_FOREACH_REVERSE_SAFE(var, head, headname, field, tvar) \ + for ((var) = TAILQ_LAST((head), headname); \ + (var) && ((tvar) = TAILQ_PREV((var), headname, field), 1); \ + (var) = (tvar)) + +#define TAILQ_INIT(head) do { \ + TAILQ_FIRST((head)) = NULL; \ + (head)->tqh_last = &TAILQ_FIRST((head)); \ + QMD_TRACE_HEAD(head); \ +} while (0) + +#define TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \ + QMD_TAILQ_CHECK_NEXT(listelm, field); \ + if ((TAILQ_NEXT((elm), field) = TAILQ_NEXT((listelm), field)) != NULL)\ + TAILQ_NEXT((elm), field)->field.tqe_prev = \ + &TAILQ_NEXT((elm), field); \ + else { \ + (head)->tqh_last = &TAILQ_NEXT((elm), field); \ + QMD_TRACE_HEAD(head); \ + } \ + TAILQ_NEXT((listelm), field) = (elm); \ + (elm)->field.tqe_prev = &TAILQ_NEXT((listelm), field); \ + QMD_TRACE_ELEM(&(elm)->field); \ + QMD_TRACE_ELEM(&listelm->field); \ +} while (0) + +#define TAILQ_INSERT_BEFORE(listelm, elm, field) do { \ + QMD_TAILQ_CHECK_PREV(listelm, field); \ + (elm)->field.tqe_prev = (listelm)->field.tqe_prev; \ + TAILQ_NEXT((elm), field) = (listelm); \ + *(listelm)->field.tqe_prev = (elm); \ + (listelm)->field.tqe_prev = &TAILQ_NEXT((elm), field); \ + QMD_TRACE_ELEM(&(elm)->field); \ + QMD_TRACE_ELEM(&listelm->field); \ +} while (0) + +#define TAILQ_INSERT_HEAD(head, elm, field) do { \ + QMD_TAILQ_CHECK_HEAD(head, field); \ + if ((TAILQ_NEXT((elm), field) = TAILQ_FIRST((head))) != NULL) \ + TAILQ_FIRST((head))->field.tqe_prev = \ + &TAILQ_NEXT((elm), field); \ + else \ + (head)->tqh_last = &TAILQ_NEXT((elm), field); \ + TAILQ_FIRST((head)) = (elm); \ + (elm)->field.tqe_prev = &TAILQ_FIRST((head)); \ + QMD_TRACE_HEAD(head); \ + QMD_TRACE_ELEM(&(elm)->field); \ +} while (0) + +#define TAILQ_INSERT_TAIL(head, elm, field) do { \ + QMD_TAILQ_CHECK_TAIL(head, field); \ + TAILQ_NEXT((elm), field) = NULL; \ + (elm)->field.tqe_prev = (head)->tqh_last; \ + *(head)->tqh_last = (elm); \ + (head)->tqh_last = &TAILQ_NEXT((elm), field); \ + QMD_TRACE_HEAD(head); \ + QMD_TRACE_ELEM(&(elm)->field); \ +} while (0) + +#define TAILQ_LAST(head, headname) \ + (*(((struct headname *)((head)->tqh_last))->tqh_last)) + +#define TAILQ_NEXT(elm, field) ((elm)->field.tqe_next) + +#define TAILQ_PREV(elm, headname, field) \ + (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last)) + +#define TAILQ_REMOVE(head, elm, field) do { \ + QMD_SAVELINK(oldnext, (elm)->field.tqe_next); \ + QMD_SAVELINK(oldprev, (elm)->field.tqe_prev); \ + QMD_TAILQ_CHECK_NEXT(elm, field); \ + QMD_TAILQ_CHECK_PREV(elm, field); \ + if ((TAILQ_NEXT((elm), field)) != NULL) \ + TAILQ_NEXT((elm), field)->field.tqe_prev = \ + (elm)->field.tqe_prev; \ + else { \ + (head)->tqh_last = (elm)->field.tqe_prev; \ + QMD_TRACE_HEAD(head); \ + } \ + *(elm)->field.tqe_prev = TAILQ_NEXT((elm), field); \ + TRASHIT(*oldnext); \ + TRASHIT(*oldprev); \ + QMD_TRACE_ELEM(&(elm)->field); \ +} while (0) + +#define TAILQ_SWAP(head1, head2, type, field) do { \ + struct type *swap_first = (head1)->tqh_first; \ + struct type **swap_last = (head1)->tqh_last; \ + (head1)->tqh_first = (head2)->tqh_first; \ + (head1)->tqh_last = (head2)->tqh_last; \ + (head2)->tqh_first = swap_first; \ + (head2)->tqh_last = swap_last; \ + if ((swap_first = (head1)->tqh_first) != NULL) \ + swap_first->field.tqe_prev = &(head1)->tqh_first; \ + else \ + (head1)->tqh_last = &(head1)->tqh_first; \ + if ((swap_first = (head2)->tqh_first) != NULL) \ + swap_first->field.tqe_prev = &(head2)->tqh_first; \ + else \ + (head2)->tqh_last = &(head2)->tqh_first; \ +} while (0) + +#ifdef __cplusplus +} +#endif + +#endif /* !_SYS_QUEUE_H_ */ diff --git a/tools/sdk/include/esp32/rom/rtc.h b/tools/sdk/include/esp32/rom/rtc.h new file mode 100644 index 00000000..1ff7f033 --- /dev/null +++ b/tools/sdk/include/esp32/rom/rtc.h @@ -0,0 +1,206 @@ +// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _ROM_RTC_H_ +#define _ROM_RTC_H_ + +#include "ets_sys.h" + +#include +#include + +#include "soc/soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup rtc_apis, rtc registers and memory related apis + * @brief rtc apis + */ + +/** @addtogroup rtc_apis + * @{ + */ + +/************************************************************************************** + * Note: * + * Some Rtc memory and registers are used, in ROM or in internal library. * + * Please do not use reserved or used rtc memory or registers. * + * * + ************************************************************************************* + * RTC Memory & Store Register usage + ************************************************************************************* + * rtc memory addr type size usage + * 0x3ff61000(0x50000000) Slow SIZE_CP Co-Processor code/Reset Entry + * 0x3ff61000+SIZE_CP Slow 4096-SIZE_CP + * 0x3ff62800 Slow 4096 Reserved + * + * 0x3ff80000(0x400c0000) Fast 8192 deep sleep entry code + * + ************************************************************************************* + * Rtc store registers usage + * RTC_CNTL_STORE0_REG + * RTC_CNTL_STORE1_REG + * RTC_CNTL_STORE2_REG + * RTC_CNTL_STORE3_REG + * RTC_CNTL_STORE4_REG Reserved + * RTC_CNTL_STORE5_REG External Xtal Frequency + * RTC_CNTL_STORE6_REG FAST_RTC_MEMORY_ENTRY + * RTC_CNTL_STORE7_REG FAST_RTC_MEMORY_CRC + ************************************************************************************* + */ +#define RTC_ENTRY_ADDR_REG RTC_CNTL_STORE6_REG +#define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG + + +typedef enum { + AWAKE = 0, // + +#ifdef __cplusplus +extern "C" { +#endif + +void ets_secure_boot_start(void); + +void ets_secure_boot_finish(void); + +void ets_secure_boot_hash(uint32_t *buf); + +void ets_secure_boot_obtain(void); + +int ets_secure_boot_check(uint32_t *buf); + +void ets_secure_boot_rd_iv(uint32_t *buf); + +void ets_secure_boot_rd_abstract(uint32_t *buf); + +bool ets_secure_boot_check_start(uint8_t abs_index, uint32_t iv_addr); + +int ets_secure_boot_check_finish(uint32_t *abstract); + +#ifdef __cplusplus +} +#endif + +#endif /* _ROM_SECURE_BOOT_H_ */ diff --git a/tools/sdk/include/esp32/rom/sha.h b/tools/sdk/include/esp32/rom/sha.h new file mode 100644 index 00000000..8082a394 --- /dev/null +++ b/tools/sdk/include/esp32/rom/sha.h @@ -0,0 +1,58 @@ +/* + ROM functions for hardware SHA support. + + It is not recommended to use these functions directly, + use the wrapper functions in hwcrypto/sha.h instead. + + */ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _ROM_SHA_H_ +#define _ROM_SHA_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct SHAContext { + bool start; + uint32_t total_input_bits[4]; +} SHA_CTX; + +enum SHA_TYPE { + SHA1 = 0, + SHA2_256, + SHA2_384, + SHA2_512, + SHA_INVALID = -1, +}; + +void ets_sha_init(SHA_CTX *ctx); + +void ets_sha_enable(void); + +void ets_sha_disable(void); + +void ets_sha_update(SHA_CTX *ctx, enum SHA_TYPE type, const uint8_t *input, size_t input_bits); + +void ets_sha_finish(SHA_CTX *ctx, enum SHA_TYPE type, uint8_t *output); + +#ifdef __cplusplus +} +#endif + +#endif /* _ROM_SHA_H_ */ diff --git a/tools/sdk/include/esp32/rom/spi_flash.h b/tools/sdk/include/esp32/rom/spi_flash.h new file mode 100644 index 00000000..ba8eebc2 --- /dev/null +++ b/tools/sdk/include/esp32/rom/spi_flash.h @@ -0,0 +1,514 @@ +// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _ROM_SPI_FLASH_H_ +#define _ROM_SPI_FLASH_H_ + +#include +#include + +#include "esp_attr.h" + +#include "soc/spi_reg.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup spi_flash_apis, spi flash operation related apis + * @brief spi_flash apis + */ + +/** @addtogroup spi_flash_apis + * @{ + */ + +/************************************************************* + * Note + ************************************************************* + * 1. ESP32 chip have 4 SPI slave/master, however, SPI0 is + * used as an SPI master to access Flash and ext-SRAM by + * Cache module. It will support Decryto read for Flash, + * read/write for ext-SRAM. And SPI1 is also used as an + * SPI master for Flash read/write and ext-SRAM read/write. + * It will support Encrypto write for Flash. + * 2. As an SPI master, SPI support Highest clock to 80M, + * however, Flash with 80M Clock should be configured + * for different Flash chips. If you want to use 80M + * clock We should use the SPI that is certified by + * Espressif. However, the certification is not started + * at the time, so please use 40M clock at the moment. + * 3. SPI Flash can use 2 lines or 4 lines mode. If you + * use 2 lines mode, you can save two pad SPIHD and + * SPIWP for gpio. ESP32 support configured SPI pad for + * Flash, the configuration is stored in efuse and flash. + * However, the configurations of pads should be certified + * by Espressif. If you use this function, please use 40M + * clock at the moment. + * 4. ESP32 support to use Common SPI command to configure + * Flash to QIO mode, if you failed to configure with fix + * command. With Common SPI Command, ESP32 can also provide + * a way to use same Common SPI command groups on different + * Flash chips. + * 5. This functions are not protected by packeting, Please use the + ************************************************************* + */ + +#define PERIPHS_SPI_FLASH_CMD SPI_CMD(1) +#define PERIPHS_SPI_FLASH_ADDR SPI_ADDR(1) +#define PERIPHS_SPI_FLASH_CTRL SPI_CTRL(1) +#define PERIPHS_SPI_FLASH_CTRL1 SPI_CTRL1(1) +#define PERIPHS_SPI_FLASH_STATUS SPI_RD_STATUS(1) +#define PERIPHS_SPI_FLASH_USRREG SPI_USER(1) +#define PERIPHS_SPI_FLASH_USRREG1 SPI_USER1(1) +#define PERIPHS_SPI_FLASH_USRREG2 SPI_USER2(1) +#define PERIPHS_SPI_FLASH_C0 SPI_W0(1) +#define PERIPHS_SPI_FLASH_C1 SPI_W1(1) +#define PERIPHS_SPI_FLASH_C2 SPI_W2(1) +#define PERIPHS_SPI_FLASH_C3 SPI_W3(1) +#define PERIPHS_SPI_FLASH_C4 SPI_W4(1) +#define PERIPHS_SPI_FLASH_C5 SPI_W5(1) +#define PERIPHS_SPI_FLASH_C6 SPI_W6(1) +#define PERIPHS_SPI_FLASH_C7 SPI_W7(1) +#define PERIPHS_SPI_FLASH_TX_CRC SPI_TX_CRC(1) + +#define SPI0_R_QIO_DUMMY_CYCLELEN 3 +#define SPI0_R_QIO_ADDR_BITSLEN 31 +#define SPI0_R_FAST_DUMMY_CYCLELEN 7 +#define SPI0_R_DIO_DUMMY_CYCLELEN 3 +#define SPI0_R_FAST_ADDR_BITSLEN 23 +#define SPI0_R_SIO_ADDR_BITSLEN 23 + +#define SPI1_R_QIO_DUMMY_CYCLELEN 3 +#define SPI1_R_QIO_ADDR_BITSLEN 31 +#define SPI1_R_FAST_DUMMY_CYCLELEN 7 +#define SPI1_R_DIO_DUMMY_CYCLELEN 3 +#define SPI1_R_DIO_ADDR_BITSLEN 31 +#define SPI1_R_FAST_ADDR_BITSLEN 23 +#define SPI1_R_SIO_ADDR_BITSLEN 23 + +#define SPI_W_SIO_ADDR_BITSLEN 23 + +#define TWO_BYTE_STATUS_EN SPI_WRSR_2B + +//SPI address register +#define SPI_FLASH_BYTES_LEN 24 +#define SPI_BUFF_BYTE_WRITE_NUM 32 +#define SPI_BUFF_BYTE_READ_NUM 64 +#define SPI_BUFF_BYTE_READ_BITS 0x3f + +//SPI status register +#define SPI_FLASH_BUSY_FLAG BIT0 +#define SPI_FLASH_WRENABLE_FLAG BIT1 +#define SPI_FLASH_BP0 BIT2 +#define SPI_FLASH_BP1 BIT3 +#define SPI_FLASH_BP2 BIT4 +#define FLASH_WR_PROTECT (SPI_FLASH_BP0|SPI_FLASH_BP1|SPI_FLASH_BP2) +#define SPI_FLASH_QE BIT9 + +typedef enum { + SPI_FLASH_QIO_MODE = 0, + SPI_FLASH_QOUT_MODE, + SPI_FLASH_DIO_MODE, + SPI_FLASH_DOUT_MODE, + SPI_FLASH_FASTRD_MODE, + SPI_FLASH_SLOWRD_MODE +} SpiFlashRdMode; + +typedef enum { + SPI_FLASH_RESULT_OK, + SPI_FLASH_RESULT_ERR, + SPI_FLASH_RESULT_TIMEOUT +} SpiFlashOpResult; + +typedef struct { + uint32_t deviceId; + uint32_t chip_size; // chip size in bytes + uint32_t block_size; + uint32_t sector_size; + uint32_t page_size; + uint32_t status_mask; +} SpiFlashChip; + +typedef struct { + uint8_t data_length; + uint8_t read_cmd0; + uint8_t read_cmd1; + uint8_t write_cmd; + uint16_t data_mask; + uint16_t data; +} SpiCommonCmd; + +/** + * @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed. + * Please do not call this function in SDK. + * + * @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write). + * + * @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M. + * + * @return None + */ +void spi_dummy_len_fix(uint8_t spi, uint8_t freqdiv); + +/** + * @brief Select SPI Flash to QIO mode when WP pad is read from Flash. + * Please do not call this function in SDK. + * + * @param uint8_t wp_gpio_num: WP gpio number. + * + * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping + * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd + * + * @return None + */ +void SelectSpiQIO(uint8_t wp_gpio_num, uint32_t ishspi); + +/** + * @brief Set SPI Flash pad drivers. + * Please do not call this function in SDK. + * + * @param uint8_t wp_gpio_num: WP gpio number. + * + * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping + * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd + * + * @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid + * drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp. + * Values usually read from falsh by rom code, function usually callde by rom code. + * if value with bit(3) set, the value is valid, bit[2:0] is the real value. + * + * @return None + */ +void SetSpiDrvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs); + +/** + * @brief Select SPI Flash function for pads. + * Please do not call this function in SDK. + * + * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping + * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd + * + * @return None + */ +void SelectSpiFunction(uint32_t ishspi); + +/** + * @brief SPI Flash init, clock divisor is 4, use 1 line Slow read mode. + * Please do not call this function in SDK. + * + * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping + * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd + * + * @param uint8_t legacy: In legacy mode, more SPI command is used in line. + * + * @return None + */ +void spi_flash_attach(uint32_t ishspi, bool legacy); + +/** + * @brief SPI Read Flash status register. We use CMD 0x05. + * Please do not call this function in SDK. + * + * @param SpiFlashChip *spi : The information for Flash, which is exported from ld file. + * + * @param uint32_t *status : The pointer to which to return the Flash status value. + * + * @return SPI_FLASH_RESULT_OK : read OK. + * SPI_FLASH_RESULT_ERR : read error. + * SPI_FLASH_RESULT_TIMEOUT : read timeout. + */ +SpiFlashOpResult SPI_read_status(SpiFlashChip *spi, uint32_t *status); + +/** + * @brief SPI Read Flash status register high 16 bit. We use CMD 0x35. + * Please do not call this function in SDK. + * + * @param SpiFlashChip *spi : The information for Flash, which is exported from ld file. + * + * @param uint32_t *status : The pointer to which to return the Flash status value. + * + * @return SPI_FLASH_RESULT_OK : read OK. + * SPI_FLASH_RESULT_ERR : read error. + * SPI_FLASH_RESULT_TIMEOUT : read timeout. + */ +SpiFlashOpResult SPI_read_status_high(SpiFlashChip *spi, uint32_t *status); + +/** + * @brief Write status to Falsh status register. + * Please do not call this function in SDK. + * + * @param SpiFlashChip *spi : The information for Flash, which is exported from ld file. + * + * @param uint32_t status_value : Value to . + * + * @return SPI_FLASH_RESULT_OK : write OK. + * SPI_FLASH_RESULT_ERR : write error. + * SPI_FLASH_RESULT_TIMEOUT : write timeout. + */ +SpiFlashOpResult SPI_write_status(SpiFlashChip *spi, uint32_t status_value); + +/** + * @brief Use a command to Read Flash status register. + * Please do not call this function in SDK. + * + * @param SpiFlashChip *spi : The information for Flash, which is exported from ld file. + * + * @param uint32_t*status : The pointer to which to return the Flash status value. + * + * @return SPI_FLASH_RESULT_OK : read OK. + * SPI_FLASH_RESULT_ERR : read error. + * SPI_FLASH_RESULT_TIMEOUT : read timeout. + */ +SpiFlashOpResult SPI_user_command_read(uint32_t *status, uint8_t cmd); + +/** + * @brief Config SPI Flash read mode when init. + * Please do not call this function in SDK. + * + * @param SpiFlashRdMode mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD. + * + * @param uint8_t legacy: In legacy mode, more SPI command is used in line. + * + * @return SPI_FLASH_RESULT_OK : config OK. + * SPI_FLASH_RESULT_ERR : config error. + * SPI_FLASH_RESULT_TIMEOUT : config timeout. + */ +SpiFlashOpResult SPIReadModeCnfig(SpiFlashRdMode mode, bool legacy); + +/** + * @brief Config SPI Flash read mode when Flash is running in some mode. + * Please do not call this function in SDK. + * + * @param SpiFlashRdMode mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD. + * + * @return SPI_FLASH_RESULT_OK : config OK. + * SPI_FLASH_RESULT_ERR : config error. + * SPI_FLASH_RESULT_TIMEOUT : config timeout. + */ +SpiFlashOpResult SPIMasterReadModeCnfig(SpiFlashRdMode mode); + +/** + * @brief Config SPI Flash clock divisor. + * Please do not call this function in SDK. + * + * @param uint8_t freqdiv: clock divisor. + * + * @param uint8_t spi: 0 for SPI0, 1 for SPI1. + * + * @return SPI_FLASH_RESULT_OK : config OK. + * SPI_FLASH_RESULT_ERR : config error. + * SPI_FLASH_RESULT_TIMEOUT : config timeout. + */ +SpiFlashOpResult SPIClkConfig(uint8_t freqdiv, uint8_t spi); + +/** + * @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD. + * Please do not call this function in SDK. + * + * @param SpiCommonCmd *cmd : A struct to show the action of a command. + * + * @return uint16_t 0 : do not send command any more. + * 1 : go to the next command. + * n > 1 : skip (n - 1) commands. + */ +uint16_t SPI_Common_Command(SpiCommonCmd *cmd); + +/** + * @brief Unlock SPI write protect. + * Please do not call this function in SDK. + * + * @param None. + * + * @return SPI_FLASH_RESULT_OK : Unlock OK. + * SPI_FLASH_RESULT_ERR : Unlock error. + * SPI_FLASH_RESULT_TIMEOUT : Unlock timeout. + */ +SpiFlashOpResult SPIUnlock(void); + +/** + * @brief SPI write protect. + * Please do not call this function in SDK. + * + * @param None. + * + * @return SPI_FLASH_RESULT_OK : Lock OK. + * SPI_FLASH_RESULT_ERR : Lock error. + * SPI_FLASH_RESULT_TIMEOUT : Lock timeout. + */ +SpiFlashOpResult SPILock(void); + +/** + * @brief Update SPI Flash parameter. + * Please do not call this function in SDK. + * + * @param uint32_t deviceId : Device ID read from SPI, the low 32 bit. + * + * @param uint32_t chip_size : The Flash size. + * + * @param uint32_t block_size : The Flash block size. + * + * @param uint32_t sector_size : The Flash sector size. + * + * @param uint32_t page_size : The Flash page size. + * + * @param uint32_t status_mask : The Mask used when read status from Flash(use single CMD). + * + * @return SPI_FLASH_RESULT_OK : Update OK. + * SPI_FLASH_RESULT_ERR : Update error. + * SPI_FLASH_RESULT_TIMEOUT : Update timeout. + */ +SpiFlashOpResult SPIParamCfg(uint32_t deviceId, uint32_t chip_size, uint32_t block_size, uint32_t sector_size, uint32_t page_size, uint32_t status_mask); + +/** + * @brief Erase whole flash chip. + * Please do not call this function in SDK. + * + * @param None + * + * @return SPI_FLASH_RESULT_OK : Erase OK. + * SPI_FLASH_RESULT_ERR : Erase error. + * SPI_FLASH_RESULT_TIMEOUT : Erase timeout. + */ +SpiFlashOpResult SPIEraseChip(void); + +/** + * @brief Erase a block of flash. + * Please do not call this function in SDK. + * + * @param uint32_t block_num : Which block to erase. + * + * @return SPI_FLASH_RESULT_OK : Erase OK. + * SPI_FLASH_RESULT_ERR : Erase error. + * SPI_FLASH_RESULT_TIMEOUT : Erase timeout. + */ +SpiFlashOpResult SPIEraseBlock(uint32_t block_num); + +/** + * @brief Erase a sector of flash. + * Please do not call this function in SDK. + * + * @param uint32_t sector_num : Which sector to erase. + * + * @return SPI_FLASH_RESULT_OK : Erase OK. + * SPI_FLASH_RESULT_ERR : Erase error. + * SPI_FLASH_RESULT_TIMEOUT : Erase timeout. + */ +SpiFlashOpResult SPIEraseSector(uint32_t sector_num); + +/** + * @brief Erase some sectors. + * Please do not call this function in SDK. + * + * @param uint32_t start_addr : Start addr to erase, should be sector aligned. + * + * @param uint32_t area_len : Length to erase, should be sector aligned. + * + * @return SPI_FLASH_RESULT_OK : Erase OK. + * SPI_FLASH_RESULT_ERR : Erase error. + * SPI_FLASH_RESULT_TIMEOUT : Erase timeout. + */ +SpiFlashOpResult SPIEraseArea(uint32_t start_addr, uint32_t area_len); + +/** + * @brief Write Data to Flash, you should Erase it yourself if need. + * Please do not call this function in SDK. + * + * @param uint32_t dest_addr : Address to write, should be 4 bytes aligned. + * + * @param const uint32_t *src : The pointer to data which is to write. + * + * @param uint32_t len : Length to write, should be 4 bytes aligned. + * + * @return SPI_FLASH_RESULT_OK : Write OK. + * SPI_FLASH_RESULT_ERR : Write error. + * SPI_FLASH_RESULT_TIMEOUT : Write timeout. + */ +SpiFlashOpResult SPIWrite(uint32_t dest_addr, const uint32_t *src, int32_t len); + +/** + * @brief Read Data from Flash, you should Erase it yourself if need. + * Please do not call this function in SDK. + * + * @param uint32_t src_addr : Address to read, should be 4 bytes aligned. + * + * @param uint32_t *dest : The buf to read the data. + * + * @param uint32_t len : Length to read, should be 4 bytes aligned. + * + * @return SPI_FLASH_RESULT_OK : Read OK. + * SPI_FLASH_RESULT_ERR : Read error. + * SPI_FLASH_RESULT_TIMEOUT : Read timeout. + */ +SpiFlashOpResult SPIRead(uint32_t src_addr, uint32_t *dest, int32_t len); + +/** + * @brief SPI1 go into encrypto mode. + * Please do not call this function in SDK. + * + * @param None + * + * @return None + */ +void SPI_Write_Encrypt_Enable(void); + +/** + * @brief Prepare 32 Bytes data to encrpto writing, you should Erase it yourself if need. + * Please do not call this function in SDK. + * + * @param uint32_t flash_addr : Address to write, should be 32 bytes aligned. + * + * @param uint32_t *data : The pointer to data which is to write. + * + * @return SPI_FLASH_RESULT_OK : Prepare OK. + * SPI_FLASH_RESULT_ERR : Prepare error. + * SPI_FLASH_RESULT_TIMEOUT : Prepare timeout. + */ +SpiFlashOpResult SPI_Prepare_Encrypt_Data(uint32_t flash_addr, uint32_t *data); + +/** + * @brief SPI1 go out of encrypto mode. + * Please do not call this function in SDK. + * + * @param None + * + * @return None + */ +void SPI_Write_Encrypt_Disable(void); + +/** + * @brief Encrpto writing data to flash, you should Erase it yourself if need. + * Please do not call this function in SDK. + * + * @param uint32_t flash_addr : Address to write, should be 32 bytes aligned. + * + * @param uint32_t *data : The pointer to data which is to write. + * + * @param uint32_t len : Length to write, should be 32 bytes aligned. + * + * @return SPI_FLASH_RESULT_OK : Encrypto write OK. + * SPI_FLASH_RESULT_ERR : Encrypto write error. + * SPI_FLASH_RESULT_TIMEOUT : Encrypto write timeout. + */ +SpiFlashOpResult SPI_Encrypt_Write(uint32_t flash_addr, uint32_t *data, uint32_t len); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* _ROM_SPI_FLASH_H_ */ diff --git a/tools/sdk/include/esp32/rom/tbconsole.h b/tools/sdk/include/esp32/rom/tbconsole.h new file mode 100644 index 00000000..891c2732 --- /dev/null +++ b/tools/sdk/include/esp32/rom/tbconsole.h @@ -0,0 +1,27 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _ROM_TBCONSOLE_H_ +#define _ROM_TBCONSOLE_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +void start_tb_console(); + +#ifdef __cplusplus +} +#endif + +#endif /* _ROM_TBCONSOLE_H_ */ diff --git a/tools/sdk/include/esp32/rom/tjpgd.h b/tools/sdk/include/esp32/rom/tjpgd.h new file mode 100644 index 00000000..31fbc97c --- /dev/null +++ b/tools/sdk/include/esp32/rom/tjpgd.h @@ -0,0 +1,99 @@ +/*----------------------------------------------------------------------------/ +/ TJpgDec - Tiny JPEG Decompressor include file (C)ChaN, 2012 +/----------------------------------------------------------------------------*/ +#ifndef _TJPGDEC +#define _TJPGDEC +/*---------------------------------------------------------------------------*/ +/* System Configurations */ + +#define JD_SZBUF 512 /* Size of stream input buffer */ +#define JD_FORMAT 0 /* Output pixel format 0:RGB888 (3 BYTE/pix), 1:RGB565 (1 WORD/pix) */ +#define JD_USE_SCALE 1 /* Use descaling feature for output */ +#define JD_TBLCLIP 1 /* Use table for saturation (might be a bit faster but increases 1K bytes of code size) */ + +/*---------------------------------------------------------------------------*/ + +#ifdef __cplusplus +extern "C" { +#endif + +/* These types must be 16-bit, 32-bit or larger integer */ +typedef int INT; +typedef unsigned int UINT; + +/* These types must be 8-bit integer */ +typedef char CHAR; +typedef unsigned char UCHAR; +typedef unsigned char BYTE; + +/* These types must be 16-bit integer */ +typedef short SHORT; +typedef unsigned short USHORT; +typedef unsigned short WORD; +typedef unsigned short WCHAR; + +/* These types must be 32-bit integer */ +typedef long LONG; +typedef unsigned long ULONG; +typedef unsigned long DWORD; + + +/* Error code */ +typedef enum { + JDR_OK = 0, /* 0: Succeeded */ + JDR_INTR, /* 1: Interrupted by output function */ + JDR_INP, /* 2: Device error or wrong termination of input stream */ + JDR_MEM1, /* 3: Insufficient memory pool for the image */ + JDR_MEM2, /* 4: Insufficient stream input buffer */ + JDR_PAR, /* 5: Parameter error */ + JDR_FMT1, /* 6: Data format error (may be damaged data) */ + JDR_FMT2, /* 7: Right format but not supported */ + JDR_FMT3 /* 8: Not supported JPEG standard */ +} JRESULT; + + + +/* Rectangular structure */ +typedef struct { + WORD left, right, top, bottom; +} JRECT; + + + +/* Decompressor object structure */ +typedef struct JDEC JDEC; +struct JDEC { + UINT dctr; /* Number of bytes available in the input buffer */ + BYTE* dptr; /* Current data read ptr */ + BYTE* inbuf; /* Bit stream input buffer */ + BYTE dmsk; /* Current bit in the current read byte */ + BYTE scale; /* Output scaling ratio */ + BYTE msx, msy; /* MCU size in unit of block (width, height) */ + BYTE qtid[3]; /* Quantization table ID of each component */ + SHORT dcv[3]; /* Previous DC element of each component */ + WORD nrst; /* Restart inverval */ + UINT width, height; /* Size of the input image (pixel) */ + BYTE* huffbits[2][2]; /* Huffman bit distribution tables [id][dcac] */ + WORD* huffcode[2][2]; /* Huffman code word tables [id][dcac] */ + BYTE* huffdata[2][2]; /* Huffman decoded data tables [id][dcac] */ + LONG* qttbl[4]; /* Dequaitizer tables [id] */ + void* workbuf; /* Working buffer for IDCT and RGB output */ + BYTE* mcubuf; /* Working buffer for the MCU */ + void* pool; /* Pointer to available memory pool */ + UINT sz_pool; /* Size of momory pool (bytes available) */ + UINT (*infunc)(JDEC*, BYTE*, UINT);/* Pointer to jpeg stream input function */ + void* device; /* Pointer to I/O device identifiler for the session */ +}; + + + +/* TJpgDec API functions */ +JRESULT jd_prepare (JDEC*, UINT(*)(JDEC*,BYTE*,UINT), void*, UINT, void*); +JRESULT jd_decomp (JDEC*, UINT(*)(JDEC*,void*,JRECT*), BYTE); + + +#ifdef __cplusplus +} +#endif + +#endif /* _TJPGDEC */ diff --git a/tools/sdk/include/esp32/rom/uart.h b/tools/sdk/include/esp32/rom/uart.h new file mode 100644 index 00000000..8e312513 --- /dev/null +++ b/tools/sdk/include/esp32/rom/uart.h @@ -0,0 +1,411 @@ +// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _ROM_UART_H_ +#define _ROM_UART_H_ + +#include "esp_types.h" +#include "esp_attr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup uart_apis, uart configuration and communication related apis + * @brief uart apis + */ + +/** @addtogroup uart_apis + * @{ + */ + +#define RX_BUFF_SIZE 0x100 +#define TX_BUFF_SIZE 100 + +//uart int enalbe register ctrl bits +#define UART_RCV_INTEN BIT0 +#define UART_TRX_INTEN BIT1 +#define UART_LINE_STATUS_INTEN BIT2 + +//uart int identification ctrl bits +#define UART_INT_FLAG_MASK 0x0E + +//uart fifo ctrl bits +#define UART_CLR_RCV_FIFO BIT1 +#define UART_CLR_TRX_FIFO BIT2 +#define UART_RCVFIFO_TRG_LVL_BITS BIT6 + +//uart line control bits +#define UART_DIV_LATCH_ACCESS_BIT BIT7 + +//uart line status bits +#define UART_RCV_DATA_RDY_FLAG BIT0 +#define UART_RCV_OVER_FLOW_FLAG BIT1 +#define UART_RCV_PARITY_ERR_FLAG BIT2 +#define UART_RCV_FRAME_ERR_FLAG BIT3 +#define UART_BRK_INT_FLAG BIT4 +#define UART_TRX_FIFO_EMPTY_FLAG BIT5 +#define UART_TRX_ALL_EMPTY_FLAG BIT6 // include fifo and shift reg +#define UART_RCV_ERR_FLAG BIT7 + +//send and receive message frame head +#define FRAME_FLAG 0x7E + +typedef enum { + UART_LINE_STATUS_INT_FLAG = 0x06, + UART_RCV_FIFO_INT_FLAG = 0x04, + UART_RCV_TMOUT_INT_FLAG = 0x0C, + UART_TXBUFF_EMPTY_INT_FLAG = 0x02 +} UartIntType; //consider bit0 for int_flag + +typedef enum { + RCV_ONE_BYTE = 0x0, + RCV_FOUR_BYTE = 0x1, + RCV_EIGHT_BYTE = 0x2, + RCV_FOURTEEN_BYTE = 0x3 +} UartRcvFifoTrgLvl; + +typedef enum { + FIVE_BITS = 0x0, + SIX_BITS = 0x1, + SEVEN_BITS = 0x2, + EIGHT_BITS = 0x3 +} UartBitsNum4Char; + +typedef enum { + ONE_STOP_BIT = 1, + ONE_HALF_STOP_BIT = 2, + TWO_STOP_BIT = 3 +} UartStopBitsNum; + +typedef enum { + NONE_BITS = 0, + ODD_BITS = 2, + EVEN_BITS = 3 + +} UartParityMode; + +typedef enum { + STICK_PARITY_DIS = 0, + STICK_PARITY_EN = 2 +} UartExistParity; + +typedef enum { + BIT_RATE_9600 = 9600, + BIT_RATE_19200 = 19200, + BIT_RATE_38400 = 38400, + BIT_RATE_57600 = 57600, + BIT_RATE_115200 = 115200, + BIT_RATE_230400 = 230400, + BIT_RATE_460800 = 460800, + BIT_RATE_921600 = 921600 +} UartBautRate; + +typedef enum { + NONE_CTRL, + HARDWARE_CTRL, + XON_XOFF_CTRL +} UartFlowCtrl; + +typedef enum { + EMPTY, + UNDER_WRITE, + WRITE_OVER +} RcvMsgBuffState; + +typedef struct { +// uint32_t RcvBuffSize; + uint8_t *pRcvMsgBuff; + uint8_t *pWritePos; + uint8_t *pReadPos; + uint8_t TrigLvl; + RcvMsgBuffState BuffState; +} RcvMsgBuff; + +typedef struct { + uint32_t TrxBuffSize; + uint8_t *pTrxBuff; +} TrxMsgBuff; + +typedef enum { + BAUD_RATE_DET, + WAIT_SYNC_FRM, + SRCH_MSG_HEAD, + RCV_MSG_BODY, + RCV_ESC_CHAR, +} RcvMsgState; + +typedef struct { + UartBautRate baut_rate; + UartBitsNum4Char data_bits; + UartExistParity exist_parity; + UartParityMode parity; // chip size in byte + UartStopBitsNum stop_bits; + UartFlowCtrl flow_ctrl; + uint8_t buff_uart_no; //indicate which uart use tx/rx buffer + uint8_t tx_uart_no; + RcvMsgBuff rcv_buff; +// TrxMsgBuff trx_buff; + RcvMsgState rcv_state; + int received; +} UartDevice; + +/** + * @brief Init uart device struct value and reset uart0/uart1 rx. + * Please do not call this function in SDK. + * + * @param None + * + * @return None + */ +void uartAttach(void); + +/** + * @brief Init uart0 or uart1 for UART download booting mode. + * Please do not call this function in SDK. + * + * @param uint8_t uart_no : 0 for UART0, else for UART1. + * + * @param uint32_t clock : clock used by uart module, to adjust baudrate. + * + * @return None + */ +void Uart_Init(uint8_t uart_no, uint32_t clock); + +/** + * @brief Modify uart baudrate. + * This function will reset RX/TX fifo for uart. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @param uint32_t DivLatchValue : (clock << 4)/baudrate. + * + * @return None + */ +void uart_div_modify(uint8_t uart_no, uint32_t DivLatchValue); + +/** + * @brief Init uart0 or uart1 for UART download booting mode. + * Please do not call this function in SDK. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @param uint8_t is_sync : 0, only one UART module, easy to detect, wait until detected; + * 1, two UART modules, hard to detect, detect and return. + * + * @return None + */ +int uart_baudrate_detect(uint8_t uart_no, uint8_t is_sync); + +/** + * @brief Switch printf channel of uart_tx_one_char. + * Please do not call this function when printf. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @return None + */ +void uart_tx_switch(uint8_t uart_no); + +/** + * @brief Switch message exchange channel for UART download booting. + * Please do not call this function in SDK. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @return None + */ +void uart_buff_switch(uint8_t uart_no); + +/** + * @brief Output a char to printf channel, wait until fifo not full. + * + * @param None + * + * @return OK. + */ +STATUS uart_tx_one_char(uint8_t TxChar); + +/** + * @brief Output a char to message exchange channel, wait until fifo not full. + * Please do not call this function in SDK. + * + * @param None + * + * @return OK. + */ +STATUS uart_tx_one_char2(uint8_t TxChar);//for send message + +/** + * @brief Wait until uart tx full empty. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @return None. + */ +void uart_tx_flush(uint8_t uart_no); + +/** + * @brief Wait until uart tx full empty and the last char send ok. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @return None. + */ +void uart_tx_wait_idle(uint8_t uart_no); + +/** + * @brief Get an input char from message channel. + * Please do not call this function in SDK. + * + * @param uint8_t *pRxChar : the pointer to store the char. + * + * @return OK for successful. + * FAIL for failed. + */ +STATUS uart_rx_one_char(uint8_t *pRxChar); + +/** + * @brief Get an input char to message channel, wait until successful. + * Please do not call this function in SDK. + * + * @param None + * + * @return char : input char value. + */ +char uart_rx_one_char_block(void); + +/** + * @brief Get an input string line from message channel. + * Please do not call this function in SDK. + * + * @param uint8_t *pString : the pointer to store the string. + * + * @param uint8_t MaxStrlen : the max string length, incude '\0'. + * + * @return OK. + */ +STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); + +/** + * @brief Process uart recevied information in the interrupt handler. + * Please do not call this function in SDK. + * + * @param void *para : the message receive buffer. + * + * @return None + */ +void uart_rx_intr_handler(void *para); + +/** + * @brief Get an char from receive buffer. + * Please do not call this function in SDK. + * + * @param RcvMsgBuff *pRxBuff : the pointer to the struct that include receive buffer. + * + * @param uint8_t *pRxByte : the pointer to store the char. + * + * @return OK for successful. + * FAIL for failed. + */ +STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); + +/** + * @brief Get all chars from receive buffer. + * Please do not call this function in SDK. + * + * @param uint8_t *pCmdLn : the pointer to store the string. + * + * @return OK for successful. + * FAIL for failed. + */ +STATUS UartGetCmdLn(uint8_t *pCmdLn); + +/** + * @brief Get uart configuration struct. + * Please do not call this function in SDK. + * + * @param None + * + * @return UartDevice * : uart configuration struct pointer. + */ +UartDevice *GetUartDevice(void); + +/** + * @brief Send an packet to download tool, with SLIP escaping. + * Please do not call this function in SDK. + * + * @param uint8_t *p : the pointer to output string. + * + * @param int len : the string length. + * + * @return None. + */ +void send_packet(uint8_t *p, int len); + +/** + * @brief Receive an packet from download tool, with SLIP escaping. + * Please do not call this function in SDK. + * + * @param uint8_t *p : the pointer to input string. + * + * @param int len : If string length > len, the string will be truncated. + * + * @param uint8_t is_sync : 0, only one UART module; + * 1, two UART modules. + * + * @return int : the length of the string. + */ +int recv_packet(uint8_t *p, int len, uint8_t is_sync); + +/** + * @brief Send an packet to download tool, with SLIP escaping. + * Please do not call this function in SDK. + * + * @param uint8_t *pData : the pointer to input string. + * + * @param uint16_t DataLen : the string length. + * + * @return OK for successful. + * FAIL for failed. + */ +STATUS SendMsg(uint8_t *pData, uint16_t DataLen); + +/** + * @brief Receive an packet from download tool, with SLIP escaping. + * Please do not call this function in SDK. + * + * @param uint8_t *pData : the pointer to input string. + * + * @param uint16_t MaxDataLen : If string length > MaxDataLen, the string will be truncated. + * + * @param uint8_t is_sync : 0, only one UART module; + * 1, two UART modules. + * + * @return OK for successful. + * FAIL for failed. + */ +STATUS RcvMsg(uint8_t *pData, uint16_t MaxDataLen, uint8_t is_sync); + +extern UartDevice UartDev; + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* _ROM_UART_H_ */ diff --git a/tools/sdk/include/esp32/soc/bb_reg.h b/tools/sdk/include/esp32/soc/bb_reg.h new file mode 100755 index 00000000..0b52f66a --- /dev/null +++ b/tools/sdk/include/esp32/soc/bb_reg.h @@ -0,0 +1,102 @@ +// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _SOC_BB_REG_H_ +#define _SOC_BB_REG_H_ + +#define apb_bb_offset 0x6001c000 + +#define BB_DLY apb_bb_offset + 0x00009b00 // reg 00 +#define BB_TEST apb_bb_offset + 0x00009b08 // reg 02 +#define BB_TM1 apb_bb_offset + 0x00009b0c // reg 03 +#define BB_TM_CNTL apb_bb_offset + 0x00009b14 // reg 05 +#define BB_DEL_CNTL apb_bb_offset + 0x00009b28 // reg 10 +#define BB_PARAL_CNTL apb_bb_offset + 0x00009b2c // reg 11 +#define BB_FSM1 apb_bb_offset + 0x00009b44 // reg 17 +#define BB_MXG apb_bb_offset + 0x00009b48 // reg 18 +#define BB_MNOF apb_bb_offset + 0x00009b4c // reg 19 +#define BB_SIZE apb_bb_offset + 0x00009b50 // reg 20 +#define BB_TM3a apb_bb_offset + 0x00009b54 // reg 21 +#define BB_TM4a apb_bb_offset + 0x00009b58 // reg 22 +#define BB_GAIN apb_bb_offset + 0x00009b5c // reg 23 +#define BB_CNTL apb_bb_offset + 0x00009b60 // reg 24 +#define BB_CAD apb_bb_offset + 0x00009b64 // reg 25 +#define BB_DET apb_bb_offset + 0x00009b68 // reg 26 +#define BB_DETL apb_bb_offset + 0x00009b6c // reg 27 + +#define BB_MASK_PCLL apb_bb_offset + 0x00009d08 // reg 66 +#define BB_MASK_PCLH apb_bb_offset + 0x00009d0c // reg 67 +#define BB_RX_CTRL4 apb_bb_offset + 0x00009d10 // reg 68 +#define BB_RX_CTRL apb_bb_offset + 0x00009d1c // reg 71 +#define BB_RX_CTRL2 apb_bb_offset + 0x00009d20 // reg 72 +#define BB_RX_CTRL3 apb_bb_offset + 0x00009d24 // reg 73 +#define BB_DEL4 apb_bb_offset + 0x00009d40 // reg 80 +#define BB_TM5 apb_bb_offset + 0x00009d44 // reg 81 +#define BB_TM6 apb_bb_offset + 0x00009d48 // reg 82 +#define BB_PMCTRL apb_bb_offset + 0x00009d4c // reg 83 +#define BB_PWR apb_bb_offset + 0x00009d68 // reg 90 +#define BB_BCTRL2 apb_bb_offset + 0x00009d70 // reg 92 + +#define BB_MASK_PL apb_bb_offset + 0x00009884 // reg 97 +#define BB_MASK_PCHL apb_bb_offset + 0x00009888 // reg 98 +#define BB_MASK_PCHH apb_bb_offset + 0x0000988c // reg 99 + +#define BB_MASK_CL apb_bb_offset + 0x0000989c // reg 103 +#define BB_TONE apb_bb_offset + 0x000098a0 // reg 104 +#define BB_MASK_CH apb_bb_offset + 0x000098d4 // reg 117 +#define BB_SER apb_bb_offset + 0x000098ec // reg 123 +#define BB_GN_TB apb_bb_offset + 0x00009e00 // reg 128 + +#define BB_MODE apb_bb_offset + 0x00009c00 // reg 640 +#define BB_TXCTRL apb_bb_offset + 0x00009c04 // reg 641 +#define BB_BCTRL3 apb_bb_offset + 0x00009c08 // reg 642 +#define BB_BCTRL apb_bb_offset + 0x00009c28 // reg 650 +#define BB_SMCTRL apb_bb_offset + 0x00009c48 // reg 658 +#define BB_SMCTRL2 apb_bb_offset + 0x00009c4C // reg 659 +#define BB_TXCNT apb_bb_offset + 0x00009c58 // reg 662 +#define BB_RXCTRL apb_bb_offset + 0x00009c68 // reg 666 + +#define BB_TXGAIN apb_bb_offset + 0x00009900 // reg 704 + +#define BB_RXS_CNTL apb_bb_offset + 0x00009988 // reg 738 +#define BB_MASK2_PCLL apb_bb_offset + 0x000099a8 // reg 746 +#define BB_MASK2_PCLH apb_bb_offset + 0x000099ac // reg 747 +#define BB_MASK_PH apb_bb_offset + 0x000099b0 // reg 748 +#define BB_MASK2_PCHL apb_bb_offset + 0x000099b8 // reg 750 +#define BB_MASK2_PCHH apb_bb_offset + 0x000099bc // reg 751 +// +#define BB_TX_TONE_CNTL apb_bb_offset + 0x000099f0 // reg 764 +#define BB_ADD_CNTL0 apb_bb_offset + 0x00009a28 // reg 778 +#define BB_ADD_CNTL2 apb_bb_offset + 0x00009a2c // reg 779 +#define BB_GAIN_CNTL0 apb_bb_offset + 0x00009a34 // reg 781 +#define BB_GAIN_CNTL1 apb_bb_offset + 0x00009a38 // reg 782 +#define BB_GAIN_CNTL2 apb_bb_offset + 0x00009a3c // reg 783 +#define BB_AGCMEM_CTRL apb_bb_offset + 0x00009a68 // reg 794 + +#define BB_11B_RECORD apb_bb_offset + 0x00009808 // reg 802 +#define BB_FILTER_CNTL apb_bb_offset + 0x0000980c // reg 803 +#define BB_ANALOG_CTRL1 apb_bb_offset + 0x00009838 +#define BB_ANALOG_CTRL2 apb_bb_offset + 0x0000983c //reg 815 +#define BB_ANALOG_CTRL3 apb_bb_offset + 0x00009840 //reg 816 +#define BB_RFCFG_CTRL0 apb_bb_offset + 0x00009844 //reg 817 +#define BB_RFCFG_CTRL1 apb_bb_offset + 0x00009848 //reg 818 + +#define BB_ADD_CNTL1 apb_bb_offset + 0x00009860 //reg824 +#define BB_PA_CNTL apb_bb_offset + 0x00009864 //reg825 +#define BB_RFCFG_CTRL2 apb_bb_offset + 0x0000986c //reg827 +#define BB_RXDEL_CTRL apb_bb_offset + 0x00009d18 +#define BB_RXLENGTH_CTRL apb_bb_offset + 0x00009d1c + +#endif /* _SOC_BB_REG_H_ */ + diff --git a/tools/sdk/include/esp32/soc/boot_mode.h b/tools/sdk/include/esp32/soc/boot_mode.h new file mode 100755 index 00000000..5106e10c --- /dev/null +++ b/tools/sdk/include/esp32/soc/boot_mode.h @@ -0,0 +1,104 @@ +// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _SOC_BOOT_MODE_H_ +#define _SOC_BOOT_MODE_H_ + +#include "soc.h" + +/*SPI Boot*/ +#define IS_1XXXX(v) (((v)&0x10)==0x10) + +/*HSPI Boot*/ +#define IS_010XX(v) (((v)&0x1c)==0x08) + +/*Download Boot, SDIO/UART0/UART1*/ +#define IS_00XXX(v) (((v)&0x18)==0x00) + +/*Download Boot, SDIO/UART0/UART1,FEI_FEO V2*/ +#define IS_00X00(v) (((v)&0x1b)==0x00) + +/*Download Boot, SDIO/UART0/UART1,FEI_REO V2*/ +#define IS_00X01(v) (((v)&0x1b)==0x01) + +/*Download Boot, SDIO/UART0/UART1,REI_FEO V2*/ +#define IS_00X10(v) (((v)&0x1b)==0x02) + +/*Download Boot, SDIO/UART0/UART1,REI_FEO V2*/ +#define IS_00X11(v) (((v)&0x1b)==0x03) + +/*ATE/ANALOG Mode*/ +#define IS_01110(v) (((v)&0x1f)==0x0e) + +/*Diagnostic Mode+UART0 download Mode*/ +#define IS_01111(v) (((v)&0x1f)==0x0f) + +/*legacy SPI Boot*/ +#define IS_01100(v) (((v)&0x1f)==0x0c) + +/*SDIO_Slave download Mode V1.1*/ +#define IS_01101(v) (((v)&0x1f)==0x0d) + + + +#define BOOT_MODE_GET() (GPIO_REG_READ(GPIO_STRAP)) + +/*do not include download mode*/ +#define ETS_IS_UART_BOOT() IS_01111(BOOT_MODE_GET()) + +/*all spi boot including spi/hspi/legacy*/ +#define ETS_IS_FLASH_BOOT() (IS_1XXXX(BOOT_MODE_GET()) || IS_010XX(BOOT_MODE_GET()) || IS_01100(BOOT_MODE_GET())) + +/*all faster spi boot including spi/hspi*/ +#define ETS_IS_FAST_FLASH_BOOT() (IS_1XXXX(BOOT_MODE_GET()) || IS_010XX(BOOT_MODE_GET())) + +/*all spi boot including spi/legacy*/ +#define ETS_IS_SPI_FLASH_BOOT() (IS_1XXXX(BOOT_MODE_GET()) || IS_01100(BOOT_MODE_GET())) + +/*all spi boot including hspi/legacy*/ +#define ETS_IS_HSPI_FLASH_BOOT() IS_010XX(BOOT_MODE_GET()) + +/*all sdio V2 of failing edge input, failing edge output*/ +#define ETS_IS_SDIO_FEI_FEO_V2_BOOT() IS_00X00(BOOT_MODE_GET()) + +/*all sdio V2 of failing edge input, raising edge output*/ +#define ETS_IS_SDIO_FEI_REO_V2_BOOT() IS_00X01(BOOT_MODE_GET()) + +/*all sdio V2 of raising edge input, failing edge output*/ +#define ETS_IS_SDIO_REI_FEO_V2_BOOT() IS_00X10(BOOT_MODE_GET()) + +/*all sdio V2 of raising edge input, raising edge output*/ +#define ETS_IS_SDIO_REI_REO_V2_BOOT() IS_00X11(BOOT_MODE_GET()) + +/*all sdio V1 of raising edge input, failing edge output*/ +#define ETS_IS_SDIO_REI_FEO_V1_BOOT() IS_01101(BOOT_MODE_GET()) + +/*do not include download mode*/ +#define ETS_IS_SDIO_BOOT() IS_01101(BOOT_MODE_GET()) + +/*joint download boot*/ +#define ETS_IS_SDIO_UART_BOOT() IS_00XXX(BOOT_MODE_GET()) + +/*ATE mode*/ +#define ETS_IS_ATE_BOOT() IS_01110(BOOT_MODE_GET()) + +/*A bit to control flash boot print*/ +#define ETS_IS_PRINT_BOOT() (BOOT_MODE_GET() & 0x2) + +/*used by ETS_IS_SDIO_UART_BOOT*/ +#define SEL_NO_BOOT 0 +#define SEL_SDIO_BOOT BIT0 +#define SEL_UART_BOOT BIT1 + +#endif /* _SOC_BOOT_MODE_H_ */ diff --git a/tools/sdk/include/esp32/soc/cpu.h b/tools/sdk/include/esp32/soc/cpu.h new file mode 100644 index 00000000..c74ba317 --- /dev/null +++ b/tools/sdk/include/esp32/soc/cpu.h @@ -0,0 +1,81 @@ +// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _SOC_CPU_H +#define _SOC_CPU_H + +#include "xtensa/corebits.h" + +/* C macros for xtensa special register read/write/exchange */ + +#define RSR(reg, curval) asm volatile ("rsr %0, " #reg : "=r" (curval)); +#define WSR(reg, newval) asm volatile ("wsr %0, " #reg : : "r" (newval)); +#define XSR(reg, swapval) asm volatile ("xsr %0, " #reg : "+r" (swapval)); + +/* Return true if the CPU is in an interrupt context + (PS.UM == 0) +*/ +static inline bool cpu_in_interrupt_context(void) +{ + uint32_t ps; + RSR(PS, ps); + return (ps & PS_UM) == 0; +} + +/* Functions to set page attributes for Region Protection option in the CPU. + * See Xtensa ISA Reference manual for explanation of arguments (section 4.6.3.2). + */ + +static inline void cpu_write_dtlb(uint32_t vpn, unsigned attr) +{ + asm volatile ("wdtlb %1, %0; dsync\n" :: "r" (vpn), "r" (attr)); +} + + +static inline void cpu_write_itlb(unsigned vpn, unsigned attr) +{ + asm volatile ("witlb %1, %0; isync\n" :: "r" (vpn), "r" (attr)); +} + +/* Make page 0 access raise an exception. + * Also protect some other unused pages so we can catch weirdness. + * Useful attribute values: + * 0 — cached, RW + * 2 — bypass cache, RWX (default value after CPU reset) + * 15 — no access, raise exception + */ + +static inline void cpu_configure_region_protection() +{ + const uint32_t pages_to_protect[] = {0x00000000, 0x80000000, 0xa0000000, 0xc0000000, 0xe0000000}; + for (int i = 0; i < sizeof(pages_to_protect)/sizeof(pages_to_protect[0]); ++i) { + cpu_write_dtlb(pages_to_protect[i], 0xf); + cpu_write_itlb(pages_to_protect[i], 0xf); + } + cpu_write_dtlb(0x20000000, 0); + cpu_write_itlb(0x20000000, 0); +} + + + +/* + * @brief Set CPU frequency to the value defined in menuconfig + * + * Called from cpu_start.c, not intended to be called from other places. + * This is a temporary function which will be replaced once dynamic + * CPU frequency changing is implemented. + */ +void esp_set_cpu_freq(void); + +#endif diff --git a/tools/sdk/include/esp32/soc/dport_reg.h b/tools/sdk/include/esp32/soc/dport_reg.h new file mode 100644 index 00000000..d65d9edb --- /dev/null +++ b/tools/sdk/include/esp32/soc/dport_reg.h @@ -0,0 +1,3838 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_DPORT_REG_H_ +#define _SOC_DPORT_REG_H_ + +#include "soc.h" + +#define DPORT_PRO_BOOT_REMAP_CTRL_REG (DR_REG_DPORT_BASE + 0x000) +/* DPORT_PRO_BOOT_REMAP : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_BOOT_REMAP (BIT(0)) +#define DPORT_PRO_BOOT_REMAP_M (BIT(0)) +#define DPORT_PRO_BOOT_REMAP_V 0x1 +#define DPORT_PRO_BOOT_REMAP_S 0 + +#define DPORT_APP_BOOT_REMAP_CTRL_REG (DR_REG_DPORT_BASE + 0x004) +/* DPORT_APP_BOOT_REMAP : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_BOOT_REMAP (BIT(0)) +#define DPORT_APP_BOOT_REMAP_M (BIT(0)) +#define DPORT_APP_BOOT_REMAP_V 0x1 +#define DPORT_APP_BOOT_REMAP_S 0 + +#define DPORT_ACCESS_CHECK_REG (DR_REG_DPORT_BASE + 0x008) +/* DPORT_ACCESS_CHECK_APP : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_ACCESS_CHECK_APP (BIT(8)) +#define DPORT_ACCESS_CHECK_APP_M (BIT(8)) +#define DPORT_ACCESS_CHECK_APP_V 0x1 +#define DPORT_ACCESS_CHECK_APP_S 8 +/* DPORT_ACCESS_CHECK_PRO : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_ACCESS_CHECK_PRO (BIT(0)) +#define DPORT_ACCESS_CHECK_PRO_M (BIT(0)) +#define DPORT_ACCESS_CHECK_PRO_V 0x1 +#define DPORT_ACCESS_CHECK_PRO_S 0 + +#define DPORT_PRO_DPORT_APB_MASK0_REG (DR_REG_DPORT_BASE + 0x00C) +/* DPORT_PRODPORT_APB_MASK0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define DPORT_PRODPORT_APB_MASK0 0xFFFFFFFF +#define DPORT_PRODPORT_APB_MASK0_M ((DPORT_PRODPORT_APB_MASK0_V)<<(DPORT_PRODPORT_APB_MASK0_S)) +#define DPORT_PRODPORT_APB_MASK0_V 0xFFFFFFFF +#define DPORT_PRODPORT_APB_MASK0_S 0 + +#define DPORT_PRO_DPORT_APB_MASK1_REG (DR_REG_DPORT_BASE + 0x010) +/* DPORT_PRODPORT_APB_MASK1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define DPORT_PRODPORT_APB_MASK1 0xFFFFFFFF +#define DPORT_PRODPORT_APB_MASK1_M ((DPORT_PRODPORT_APB_MASK1_V)<<(DPORT_PRODPORT_APB_MASK1_S)) +#define DPORT_PRODPORT_APB_MASK1_V 0xFFFFFFFF +#define DPORT_PRODPORT_APB_MASK1_S 0 + +#define DPORT_APP_DPORT_APB_MASK0_REG (DR_REG_DPORT_BASE + 0x014) +/* DPORT_APPDPORT_APB_MASK0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define DPORT_APPDPORT_APB_MASK0 0xFFFFFFFF +#define DPORT_APPDPORT_APB_MASK0_M ((DPORT_APPDPORT_APB_MASK0_V)<<(DPORT_APPDPORT_APB_MASK0_S)) +#define DPORT_APPDPORT_APB_MASK0_V 0xFFFFFFFF +#define DPORT_APPDPORT_APB_MASK0_S 0 + +#define DPORT_APP_DPORT_APB_MASK1_REG (DR_REG_DPORT_BASE + 0x018) +/* DPORT_APPDPORT_APB_MASK1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define DPORT_APPDPORT_APB_MASK1 0xFFFFFFFF +#define DPORT_APPDPORT_APB_MASK1_M ((DPORT_APPDPORT_APB_MASK1_V)<<(DPORT_APPDPORT_APB_MASK1_S)) +#define DPORT_APPDPORT_APB_MASK1_V 0xFFFFFFFF +#define DPORT_APPDPORT_APB_MASK1_S 0 + +#define DPORT_PERI_CLK_EN_REG (DR_REG_DPORT_BASE + 0x01C) +/* DPORT_PERI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define DPORT_PERI_CLK_EN 0xFFFFFFFF +#define DPORT_PERI_CLK_EN_M ((DPORT_PERI_CLK_EN_V)<<(DPORT_PERI_CLK_EN_S)) +#define DPORT_PERI_CLK_EN_V 0xFFFFFFFF +#define DPORT_PERI_CLK_EN_S 0 + +#define DPORT_PERI_RST_EN_REG (DR_REG_DPORT_BASE + 0x020) +/* DPORT_PERI_RST_EN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define DPORT_PERI_RST_EN 0xFFFFFFFF +#define DPORT_PERI_RST_EN_M ((DPORT_PERI_RST_EN_V)<<(DPORT_PERI_RST_EN_S)) +#define DPORT_PERI_RST_EN_V 0xFFFFFFFF +#define DPORT_PERI_RST_EN_S 0 + +#define DPORT_WIFI_BB_CFG_REG (DR_REG_DPORT_BASE + 0x024) +/* DPORT_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define DPORT_WIFI_BB_CFG 0xFFFFFFFF +#define DPORT_WIFI_BB_CFG_M ((DPORT_WIFI_BB_CFG_V)<<(DPORT_WIFI_BB_CFG_S)) +#define DPORT_WIFI_BB_CFG_V 0xFFFFFFFF +#define DPORT_WIFI_BB_CFG_S 0 + +#define DPORT_WIFI_BB_CFG_2_REG (DR_REG_DPORT_BASE + 0x028) +/* DPORT_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define DPORT_WIFI_BB_CFG_2 0xFFFFFFFF +#define DPORT_WIFI_BB_CFG_2_M ((DPORT_WIFI_BB_CFG_2_V)<<(DPORT_WIFI_BB_CFG_2_S)) +#define DPORT_WIFI_BB_CFG_2_V 0xFFFFFFFF +#define DPORT_WIFI_BB_CFG_2_S 0 + +#define DPORT_APPCPU_CTRL_A_REG (DR_REG_DPORT_BASE + 0x02C) +/* DPORT_APPCPU_RESETTING : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_APPCPU_RESETTING (BIT(0)) +#define DPORT_APPCPU_RESETTING_M (BIT(0)) +#define DPORT_APPCPU_RESETTING_V 0x1 +#define DPORT_APPCPU_RESETTING_S 0 + +#define DPORT_APPCPU_CTRL_B_REG (DR_REG_DPORT_BASE + 0x030) +/* DPORT_APPCPU_CLKGATE_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APPCPU_CLKGATE_EN (BIT(0)) +#define DPORT_APPCPU_CLKGATE_EN_M (BIT(0)) +#define DPORT_APPCPU_CLKGATE_EN_V 0x1 +#define DPORT_APPCPU_CLKGATE_EN_S 0 + +#define DPORT_APPCPU_CTRL_C_REG (DR_REG_DPORT_BASE + 0x034) +/* DPORT_APPCPU_RUNSTALL : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APPCPU_RUNSTALL (BIT(0)) +#define DPORT_APPCPU_RUNSTALL_M (BIT(0)) +#define DPORT_APPCPU_RUNSTALL_V 0x1 +#define DPORT_APPCPU_RUNSTALL_S 0 + +#define DPORT_APPCPU_CTRL_D_REG (DR_REG_DPORT_BASE + 0x038) +/* DPORT_APPCPU_BOOT_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define DPORT_APPCPU_BOOT_ADDR 0xFFFFFFFF +#define DPORT_APPCPU_BOOT_ADDR_M ((DPORT_APPCPU_BOOT_ADDR_V)<<(DPORT_APPCPU_BOOT_ADDR_S)) +#define DPORT_APPCPU_BOOT_ADDR_V 0xFFFFFFFF +#define DPORT_APPCPU_BOOT_ADDR_S 0 + +#define DPORT_CPU_PER_CONF_REG (DR_REG_DPORT_BASE + 0x03C) +/* DPORT_FAST_CLK_RTC_SEL : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_FAST_CLK_RTC_SEL (BIT(3)) +#define DPORT_FAST_CLK_RTC_SEL_M (BIT(3)) +#define DPORT_FAST_CLK_RTC_SEL_V 0x1 +#define DPORT_FAST_CLK_RTC_SEL_S 3 +/* DPORT_LOWSPEED_CLK_SEL : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_LOWSPEED_CLK_SEL (BIT(2)) +#define DPORT_LOWSPEED_CLK_SEL_M (BIT(2)) +#define DPORT_LOWSPEED_CLK_SEL_V 0x1 +#define DPORT_LOWSPEED_CLK_SEL_S 2 +/* DPORT_CPUPERIOD_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: */ +#define DPORT_CPUPERIOD_SEL 0x00000003 +#define DPORT_CPUPERIOD_SEL_M ((DPORT_CPUPERIOD_SEL_V)<<(DPORT_CPUPERIOD_SEL_S)) +#define DPORT_CPUPERIOD_SEL_V 0x3 +#define DPORT_CPUPERIOD_SEL_S 0 + +#define DPORT_PRO_CACHE_CTRL_REG (DR_REG_DPORT_BASE + 0x040) +/* DPORT_PRO_DRAM_HL : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_DRAM_HL (BIT(16)) +#define DPORT_PRO_DRAM_HL_M (BIT(16)) +#define DPORT_PRO_DRAM_HL_V 0x1 +#define DPORT_PRO_DRAM_HL_S 16 +/* DPORT_SLAVE_REQ : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_SLAVE_REQ (BIT(15)) +#define DPORT_SLAVE_REQ_M (BIT(15)) +#define DPORT_SLAVE_REQ_V 0x1 +#define DPORT_SLAVE_REQ_S 15 +/* DPORT_AHB_SPI_REQ : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_AHB_SPI_REQ (BIT(14)) +#define DPORT_AHB_SPI_REQ_M (BIT(14)) +#define DPORT_AHB_SPI_REQ_V 0x1 +#define DPORT_AHB_SPI_REQ_S 14 +/* DPORT_PRO_SLAVE_REQ : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_SLAVE_REQ (BIT(13)) +#define DPORT_PRO_SLAVE_REQ_M (BIT(13)) +#define DPORT_PRO_SLAVE_REQ_V 0x1 +#define DPORT_PRO_SLAVE_REQ_S 13 +/* DPORT_PRO_AHB_SPI_REQ : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_AHB_SPI_REQ (BIT(12)) +#define DPORT_PRO_AHB_SPI_REQ_M (BIT(12)) +#define DPORT_PRO_AHB_SPI_REQ_V 0x1 +#define DPORT_PRO_AHB_SPI_REQ_S 12 +/* DPORT_PRO_DRAM_SPLIT : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_DRAM_SPLIT (BIT(11)) +#define DPORT_PRO_DRAM_SPLIT_M (BIT(11)) +#define DPORT_PRO_DRAM_SPLIT_V 0x1 +#define DPORT_PRO_DRAM_SPLIT_S 11 +/* DPORT_PRO_SINGLE_IRAM_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_SINGLE_IRAM_ENA (BIT(10)) +#define DPORT_PRO_SINGLE_IRAM_ENA_M (BIT(10)) +#define DPORT_PRO_SINGLE_IRAM_ENA_V 0x1 +#define DPORT_PRO_SINGLE_IRAM_ENA_S 10 +/* DPORT_PRO_CACHE_LOCK_3_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_LOCK_3_EN (BIT(9)) +#define DPORT_PRO_CACHE_LOCK_3_EN_M (BIT(9)) +#define DPORT_PRO_CACHE_LOCK_3_EN_V 0x1 +#define DPORT_PRO_CACHE_LOCK_3_EN_S 9 +/* DPORT_PRO_CACHE_LOCK_2_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_LOCK_2_EN (BIT(8)) +#define DPORT_PRO_CACHE_LOCK_2_EN_M (BIT(8)) +#define DPORT_PRO_CACHE_LOCK_2_EN_V 0x1 +#define DPORT_PRO_CACHE_LOCK_2_EN_S 8 +/* DPORT_PRO_CACHE_LOCK_1_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_LOCK_1_EN (BIT(7)) +#define DPORT_PRO_CACHE_LOCK_1_EN_M (BIT(7)) +#define DPORT_PRO_CACHE_LOCK_1_EN_V 0x1 +#define DPORT_PRO_CACHE_LOCK_1_EN_S 7 +/* DPORT_PRO_CACHE_LOCK_0_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_LOCK_0_EN (BIT(6)) +#define DPORT_PRO_CACHE_LOCK_0_EN_M (BIT(6)) +#define DPORT_PRO_CACHE_LOCK_0_EN_V 0x1 +#define DPORT_PRO_CACHE_LOCK_0_EN_S 6 +/* DPORT_PRO_CACHE_FLUSH_DONE : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_FLUSH_DONE (BIT(5)) +#define DPORT_PRO_CACHE_FLUSH_DONE_M (BIT(5)) +#define DPORT_PRO_CACHE_FLUSH_DONE_V 0x1 +#define DPORT_PRO_CACHE_FLUSH_DONE_S 5 +/* DPORT_PRO_CACHE_FLUSH_ENA : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_PRO_CACHE_FLUSH_ENA (BIT(4)) +#define DPORT_PRO_CACHE_FLUSH_ENA_M (BIT(4)) +#define DPORT_PRO_CACHE_FLUSH_ENA_V 0x1 +#define DPORT_PRO_CACHE_FLUSH_ENA_S 4 +/* DPORT_PRO_CACHE_ENABLE : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_ENABLE (BIT(3)) +#define DPORT_PRO_CACHE_ENABLE_M (BIT(3)) +#define DPORT_PRO_CACHE_ENABLE_V 0x1 +#define DPORT_PRO_CACHE_ENABLE_S 3 +/* DPORT_PRO_CACHE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_MODE (BIT(2)) +#define DPORT_PRO_CACHE_MODE_M (BIT(2)) +#define DPORT_PRO_CACHE_MODE_V 0x1 +#define DPORT_PRO_CACHE_MODE_S 2 + +#define DPORT_PRO_CACHE_CTRL1_REG (DR_REG_DPORT_BASE + 0x044) +/* DPORT_PRO_CACHE_MMU_IA_CLR : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_MMU_IA_CLR (BIT(13)) +#define DPORT_PRO_CACHE_MMU_IA_CLR_M (BIT(13)) +#define DPORT_PRO_CACHE_MMU_IA_CLR_V 0x1 +#define DPORT_PRO_CACHE_MMU_IA_CLR_S 13 +/* DPORT_PRO_CMMU_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_CMMU_PD (BIT(12)) +#define DPORT_PRO_CMMU_PD_M (BIT(12)) +#define DPORT_PRO_CMMU_PD_V 0x1 +#define DPORT_PRO_CMMU_PD_S 12 +/* DPORT_PRO_CMMU_FORCE_ON : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_PRO_CMMU_FORCE_ON (BIT(11)) +#define DPORT_PRO_CMMU_FORCE_ON_M (BIT(11)) +#define DPORT_PRO_CMMU_FORCE_ON_V 0x1 +#define DPORT_PRO_CMMU_FORCE_ON_S 11 +/* DPORT_PRO_CMMU_FLASH_PAGE_MODE : R/W ;bitpos:[10:9] ;default: 2'b0 ; */ +/*description: */ +#define DPORT_PRO_CMMU_FLASH_PAGE_MODE 0x00000003 +#define DPORT_PRO_CMMU_FLASH_PAGE_MODE_M ((DPORT_PRO_CMMU_FLASH_PAGE_MODE_V)<<(DPORT_PRO_CMMU_FLASH_PAGE_MODE_S)) +#define DPORT_PRO_CMMU_FLASH_PAGE_MODE_V 0x3 +#define DPORT_PRO_CMMU_FLASH_PAGE_MODE_S 9 +/* DPORT_PRO_CMMU_SRAM_PAGE_MODE : R/W ;bitpos:[8:6] ;default: 3'd3 ; */ +/*description: */ +#define DPORT_PRO_CMMU_SRAM_PAGE_MODE 0x00000007 +#define DPORT_PRO_CMMU_SRAM_PAGE_MODE_M ((DPORT_PRO_CMMU_SRAM_PAGE_MODE_V)<<(DPORT_PRO_CMMU_SRAM_PAGE_MODE_S)) +#define DPORT_PRO_CMMU_SRAM_PAGE_MODE_V 0x7 +#define DPORT_PRO_CMMU_SRAM_PAGE_MODE_S 6 +/* DPORT_PRO_CACHE_MASK_OPSDRAM : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_PRO_CACHE_MASK_OPSDRAM (BIT(5)) +#define DPORT_PRO_CACHE_MASK_OPSDRAM_M (BIT(5)) +#define DPORT_PRO_CACHE_MASK_OPSDRAM_V 0x1 +#define DPORT_PRO_CACHE_MASK_OPSDRAM_S 5 +/* DPORT_PRO_CACHE_MASK_DROM0 : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_PRO_CACHE_MASK_DROM0 (BIT(4)) +#define DPORT_PRO_CACHE_MASK_DROM0_M (BIT(4)) +#define DPORT_PRO_CACHE_MASK_DROM0_V 0x1 +#define DPORT_PRO_CACHE_MASK_DROM0_S 4 +/* DPORT_PRO_CACHE_MASK_DRAM1 : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_PRO_CACHE_MASK_DRAM1 (BIT(3)) +#define DPORT_PRO_CACHE_MASK_DRAM1_M (BIT(3)) +#define DPORT_PRO_CACHE_MASK_DRAM1_V 0x1 +#define DPORT_PRO_CACHE_MASK_DRAM1_S 3 +/* DPORT_PRO_CACHE_MASK_IROM0 : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_PRO_CACHE_MASK_IROM0 (BIT(2)) +#define DPORT_PRO_CACHE_MASK_IROM0_M (BIT(2)) +#define DPORT_PRO_CACHE_MASK_IROM0_V 0x1 +#define DPORT_PRO_CACHE_MASK_IROM0_S 2 +/* DPORT_PRO_CACHE_MASK_IRAM1 : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_PRO_CACHE_MASK_IRAM1 (BIT(1)) +#define DPORT_PRO_CACHE_MASK_IRAM1_M (BIT(1)) +#define DPORT_PRO_CACHE_MASK_IRAM1_V 0x1 +#define DPORT_PRO_CACHE_MASK_IRAM1_S 1 +/* DPORT_PRO_CACHE_MASK_IRAM0 : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_PRO_CACHE_MASK_IRAM0 (BIT(0)) +#define DPORT_PRO_CACHE_MASK_IRAM0_M (BIT(0)) +#define DPORT_PRO_CACHE_MASK_IRAM0_V 0x1 +#define DPORT_PRO_CACHE_MASK_IRAM0_S 0 + +#define DPORT_PRO_CACHE_LOCK_0_ADDR_REG (DR_REG_DPORT_BASE + 0x048) +/* DPORT_PRO_CACHE_LOCK_0_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX 0x0000000F +#define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_M ((DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_S)) +#define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_V 0xF +#define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_S 18 +/* DPORT_PRO_CACHE_LOCK_0_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN 0x0000000F +#define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_M ((DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_S)) +#define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_V 0xF +#define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_S 14 +/* DPORT_PRO_CACHE_LOCK_0_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE 0x00003FFF +#define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_M ((DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_S)) +#define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_V 0x3FFF +#define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_S 0 + +#define DPORT_PRO_CACHE_LOCK_1_ADDR_REG (DR_REG_DPORT_BASE + 0x04C) +/* DPORT_PRO_CACHE_LOCK_1_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX 0x0000000F +#define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_M ((DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_S)) +#define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_V 0xF +#define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_S 18 +/* DPORT_PRO_CACHE_LOCK_1_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN 0x0000000F +#define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_M ((DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_S)) +#define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_V 0xF +#define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_S 14 +/* DPORT_PRO_CACHE_LOCK_1_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE 0x00003FFF +#define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_M ((DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_S)) +#define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_V 0x3FFF +#define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_S 0 + +#define DPORT_PRO_CACHE_LOCK_2_ADDR_REG (DR_REG_DPORT_BASE + 0x050) +/* DPORT_PRO_CACHE_LOCK_2_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX 0x0000000F +#define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_M ((DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_S)) +#define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_V 0xF +#define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_S 18 +/* DPORT_PRO_CACHE_LOCK_2_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN 0x0000000F +#define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_M ((DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_S)) +#define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_V 0xF +#define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_S 14 +/* DPORT_PRO_CACHE_LOCK_2_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE 0x00003FFF +#define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_M ((DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_S)) +#define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_V 0x3FFF +#define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_S 0 + +#define DPORT_PRO_CACHE_LOCK_3_ADDR_REG (DR_REG_DPORT_BASE + 0x054) +/* DPORT_PRO_CACHE_LOCK_3_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX 0x0000000F +#define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_M ((DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_S)) +#define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_V 0xF +#define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_S 18 +/* DPORT_PRO_CACHE_LOCK_3_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN 0x0000000F +#define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_M ((DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_S)) +#define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_V 0xF +#define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_S 14 +/* DPORT_PRO_CACHE_LOCK_3_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE 0x00003FFF +#define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_M ((DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_S)) +#define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_V 0x3FFF +#define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_S 0 + +#define DPORT_APP_CACHE_CTRL_REG (DR_REG_DPORT_BASE + 0x058) +/* DPORT_APP_DRAM_HL : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_DRAM_HL (BIT(14)) +#define DPORT_APP_DRAM_HL_M (BIT(14)) +#define DPORT_APP_DRAM_HL_V 0x1 +#define DPORT_APP_DRAM_HL_S 14 +/* DPORT_APP_SLAVE_REQ : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_SLAVE_REQ (BIT(13)) +#define DPORT_APP_SLAVE_REQ_M (BIT(13)) +#define DPORT_APP_SLAVE_REQ_V 0x1 +#define DPORT_APP_SLAVE_REQ_S 13 +/* DPORT_APP_AHB_SPI_REQ : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_AHB_SPI_REQ (BIT(12)) +#define DPORT_APP_AHB_SPI_REQ_M (BIT(12)) +#define DPORT_APP_AHB_SPI_REQ_V 0x1 +#define DPORT_APP_AHB_SPI_REQ_S 12 +/* DPORT_APP_DRAM_SPLIT : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_DRAM_SPLIT (BIT(11)) +#define DPORT_APP_DRAM_SPLIT_M (BIT(11)) +#define DPORT_APP_DRAM_SPLIT_V 0x1 +#define DPORT_APP_DRAM_SPLIT_S 11 +/* DPORT_APP_SINGLE_IRAM_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_SINGLE_IRAM_ENA (BIT(10)) +#define DPORT_APP_SINGLE_IRAM_ENA_M (BIT(10)) +#define DPORT_APP_SINGLE_IRAM_ENA_V 0x1 +#define DPORT_APP_SINGLE_IRAM_ENA_S 10 +/* DPORT_APP_CACHE_LOCK_3_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_CACHE_LOCK_3_EN (BIT(9)) +#define DPORT_APP_CACHE_LOCK_3_EN_M (BIT(9)) +#define DPORT_APP_CACHE_LOCK_3_EN_V 0x1 +#define DPORT_APP_CACHE_LOCK_3_EN_S 9 +/* DPORT_APP_CACHE_LOCK_2_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_CACHE_LOCK_2_EN (BIT(8)) +#define DPORT_APP_CACHE_LOCK_2_EN_M (BIT(8)) +#define DPORT_APP_CACHE_LOCK_2_EN_V 0x1 +#define DPORT_APP_CACHE_LOCK_2_EN_S 8 +/* DPORT_APP_CACHE_LOCK_1_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_CACHE_LOCK_1_EN (BIT(7)) +#define DPORT_APP_CACHE_LOCK_1_EN_M (BIT(7)) +#define DPORT_APP_CACHE_LOCK_1_EN_V 0x1 +#define DPORT_APP_CACHE_LOCK_1_EN_S 7 +/* DPORT_APP_CACHE_LOCK_0_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_CACHE_LOCK_0_EN (BIT(6)) +#define DPORT_APP_CACHE_LOCK_0_EN_M (BIT(6)) +#define DPORT_APP_CACHE_LOCK_0_EN_V 0x1 +#define DPORT_APP_CACHE_LOCK_0_EN_S 6 +/* DPORT_APP_CACHE_FLUSH_DONE : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_CACHE_FLUSH_DONE (BIT(5)) +#define DPORT_APP_CACHE_FLUSH_DONE_M (BIT(5)) +#define DPORT_APP_CACHE_FLUSH_DONE_V 0x1 +#define DPORT_APP_CACHE_FLUSH_DONE_S 5 +/* DPORT_APP_CACHE_FLUSH_ENA : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_APP_CACHE_FLUSH_ENA (BIT(4)) +#define DPORT_APP_CACHE_FLUSH_ENA_M (BIT(4)) +#define DPORT_APP_CACHE_FLUSH_ENA_V 0x1 +#define DPORT_APP_CACHE_FLUSH_ENA_S 4 +/* DPORT_APP_CACHE_ENABLE : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_CACHE_ENABLE (BIT(3)) +#define DPORT_APP_CACHE_ENABLE_M (BIT(3)) +#define DPORT_APP_CACHE_ENABLE_V 0x1 +#define DPORT_APP_CACHE_ENABLE_S 3 +/* DPORT_APP_CACHE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_CACHE_MODE (BIT(2)) +#define DPORT_APP_CACHE_MODE_M (BIT(2)) +#define DPORT_APP_CACHE_MODE_V 0x1 +#define DPORT_APP_CACHE_MODE_S 2 + +#define DPORT_APP_CACHE_CTRL1_REG (DR_REG_DPORT_BASE + 0x05C) +/* DPORT_APP_CACHE_MMU_IA_CLR : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_CACHE_MMU_IA_CLR (BIT(13)) +#define DPORT_APP_CACHE_MMU_IA_CLR_M (BIT(13)) +#define DPORT_APP_CACHE_MMU_IA_CLR_V 0x1 +#define DPORT_APP_CACHE_MMU_IA_CLR_S 13 +/* DPORT_APP_CMMU_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_CMMU_PD (BIT(12)) +#define DPORT_APP_CMMU_PD_M (BIT(12)) +#define DPORT_APP_CMMU_PD_V 0x1 +#define DPORT_APP_CMMU_PD_S 12 +/* DPORT_APP_CMMU_FORCE_ON : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_APP_CMMU_FORCE_ON (BIT(11)) +#define DPORT_APP_CMMU_FORCE_ON_M (BIT(11)) +#define DPORT_APP_CMMU_FORCE_ON_V 0x1 +#define DPORT_APP_CMMU_FORCE_ON_S 11 +/* DPORT_APP_CMMU_FLASH_PAGE_MODE : R/W ;bitpos:[10:9] ;default: 2'b0 ; */ +/*description: */ +#define DPORT_APP_CMMU_FLASH_PAGE_MODE 0x00000003 +#define DPORT_APP_CMMU_FLASH_PAGE_MODE_M ((DPORT_APP_CMMU_FLASH_PAGE_MODE_V)<<(DPORT_APP_CMMU_FLASH_PAGE_MODE_S)) +#define DPORT_APP_CMMU_FLASH_PAGE_MODE_V 0x3 +#define DPORT_APP_CMMU_FLASH_PAGE_MODE_S 9 +/* DPORT_APP_CMMU_SRAM_PAGE_MODE : R/W ;bitpos:[8:6] ;default: 3'd3 ; */ +/*description: */ +#define DPORT_APP_CMMU_SRAM_PAGE_MODE 0x00000007 +#define DPORT_APP_CMMU_SRAM_PAGE_MODE_M ((DPORT_APP_CMMU_SRAM_PAGE_MODE_V)<<(DPORT_APP_CMMU_SRAM_PAGE_MODE_S)) +#define DPORT_APP_CMMU_SRAM_PAGE_MODE_V 0x7 +#define DPORT_APP_CMMU_SRAM_PAGE_MODE_S 6 +/* DPORT_APP_CACHE_MASK_OPSDRAM : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_APP_CACHE_MASK_OPSDRAM (BIT(5)) +#define DPORT_APP_CACHE_MASK_OPSDRAM_M (BIT(5)) +#define DPORT_APP_CACHE_MASK_OPSDRAM_V 0x1 +#define DPORT_APP_CACHE_MASK_OPSDRAM_S 5 +/* DPORT_APP_CACHE_MASK_DROM0 : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_APP_CACHE_MASK_DROM0 (BIT(4)) +#define DPORT_APP_CACHE_MASK_DROM0_M (BIT(4)) +#define DPORT_APP_CACHE_MASK_DROM0_V 0x1 +#define DPORT_APP_CACHE_MASK_DROM0_S 4 +/* DPORT_APP_CACHE_MASK_DRAM1 : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_APP_CACHE_MASK_DRAM1 (BIT(3)) +#define DPORT_APP_CACHE_MASK_DRAM1_M (BIT(3)) +#define DPORT_APP_CACHE_MASK_DRAM1_V 0x1 +#define DPORT_APP_CACHE_MASK_DRAM1_S 3 +/* DPORT_APP_CACHE_MASK_IROM0 : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_APP_CACHE_MASK_IROM0 (BIT(2)) +#define DPORT_APP_CACHE_MASK_IROM0_M (BIT(2)) +#define DPORT_APP_CACHE_MASK_IROM0_V 0x1 +#define DPORT_APP_CACHE_MASK_IROM0_S 2 +/* DPORT_APP_CACHE_MASK_IRAM1 : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_APP_CACHE_MASK_IRAM1 (BIT(1)) +#define DPORT_APP_CACHE_MASK_IRAM1_M (BIT(1)) +#define DPORT_APP_CACHE_MASK_IRAM1_V 0x1 +#define DPORT_APP_CACHE_MASK_IRAM1_S 1 +/* DPORT_APP_CACHE_MASK_IRAM0 : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_APP_CACHE_MASK_IRAM0 (BIT(0)) +#define DPORT_APP_CACHE_MASK_IRAM0_M (BIT(0)) +#define DPORT_APP_CACHE_MASK_IRAM0_V 0x1 +#define DPORT_APP_CACHE_MASK_IRAM0_S 0 + +#define DPORT_APP_CACHE_LOCK_0_ADDR_REG (DR_REG_DPORT_BASE + 0x060) +/* DPORT_APP_CACHE_LOCK_0_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ +/*description: */ +#define DPORT_APP_CACHE_LOCK_0_ADDR_MAX 0x0000000F +#define DPORT_APP_CACHE_LOCK_0_ADDR_MAX_M ((DPORT_APP_CACHE_LOCK_0_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_0_ADDR_MAX_S)) +#define DPORT_APP_CACHE_LOCK_0_ADDR_MAX_V 0xF +#define DPORT_APP_CACHE_LOCK_0_ADDR_MAX_S 18 +/* DPORT_APP_CACHE_LOCK_0_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ +/*description: */ +#define DPORT_APP_CACHE_LOCK_0_ADDR_MIN 0x0000000F +#define DPORT_APP_CACHE_LOCK_0_ADDR_MIN_M ((DPORT_APP_CACHE_LOCK_0_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_0_ADDR_MIN_S)) +#define DPORT_APP_CACHE_LOCK_0_ADDR_MIN_V 0xF +#define DPORT_APP_CACHE_LOCK_0_ADDR_MIN_S 14 +/* DPORT_APP_CACHE_LOCK_0_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: */ +#define DPORT_APP_CACHE_LOCK_0_ADDR_PRE 0x00003FFF +#define DPORT_APP_CACHE_LOCK_0_ADDR_PRE_M ((DPORT_APP_CACHE_LOCK_0_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_0_ADDR_PRE_S)) +#define DPORT_APP_CACHE_LOCK_0_ADDR_PRE_V 0x3FFF +#define DPORT_APP_CACHE_LOCK_0_ADDR_PRE_S 0 + +#define DPORT_APP_CACHE_LOCK_1_ADDR_REG (DR_REG_DPORT_BASE + 0x064) +/* DPORT_APP_CACHE_LOCK_1_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ +/*description: */ +#define DPORT_APP_CACHE_LOCK_1_ADDR_MAX 0x0000000F +#define DPORT_APP_CACHE_LOCK_1_ADDR_MAX_M ((DPORT_APP_CACHE_LOCK_1_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_1_ADDR_MAX_S)) +#define DPORT_APP_CACHE_LOCK_1_ADDR_MAX_V 0xF +#define DPORT_APP_CACHE_LOCK_1_ADDR_MAX_S 18 +/* DPORT_APP_CACHE_LOCK_1_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ +/*description: */ +#define DPORT_APP_CACHE_LOCK_1_ADDR_MIN 0x0000000F +#define DPORT_APP_CACHE_LOCK_1_ADDR_MIN_M ((DPORT_APP_CACHE_LOCK_1_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_1_ADDR_MIN_S)) +#define DPORT_APP_CACHE_LOCK_1_ADDR_MIN_V 0xF +#define DPORT_APP_CACHE_LOCK_1_ADDR_MIN_S 14 +/* DPORT_APP_CACHE_LOCK_1_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: */ +#define DPORT_APP_CACHE_LOCK_1_ADDR_PRE 0x00003FFF +#define DPORT_APP_CACHE_LOCK_1_ADDR_PRE_M ((DPORT_APP_CACHE_LOCK_1_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_1_ADDR_PRE_S)) +#define DPORT_APP_CACHE_LOCK_1_ADDR_PRE_V 0x3FFF +#define DPORT_APP_CACHE_LOCK_1_ADDR_PRE_S 0 + +#define DPORT_APP_CACHE_LOCK_2_ADDR_REG (DR_REG_DPORT_BASE + 0x068) +/* DPORT_APP_CACHE_LOCK_2_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ +/*description: */ +#define DPORT_APP_CACHE_LOCK_2_ADDR_MAX 0x0000000F +#define DPORT_APP_CACHE_LOCK_2_ADDR_MAX_M ((DPORT_APP_CACHE_LOCK_2_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_2_ADDR_MAX_S)) +#define DPORT_APP_CACHE_LOCK_2_ADDR_MAX_V 0xF +#define DPORT_APP_CACHE_LOCK_2_ADDR_MAX_S 18 +/* DPORT_APP_CACHE_LOCK_2_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ +/*description: */ +#define DPORT_APP_CACHE_LOCK_2_ADDR_MIN 0x0000000F +#define DPORT_APP_CACHE_LOCK_2_ADDR_MIN_M ((DPORT_APP_CACHE_LOCK_2_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_2_ADDR_MIN_S)) +#define DPORT_APP_CACHE_LOCK_2_ADDR_MIN_V 0xF +#define DPORT_APP_CACHE_LOCK_2_ADDR_MIN_S 14 +/* DPORT_APP_CACHE_LOCK_2_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: */ +#define DPORT_APP_CACHE_LOCK_2_ADDR_PRE 0x00003FFF +#define DPORT_APP_CACHE_LOCK_2_ADDR_PRE_M ((DPORT_APP_CACHE_LOCK_2_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_2_ADDR_PRE_S)) +#define DPORT_APP_CACHE_LOCK_2_ADDR_PRE_V 0x3FFF +#define DPORT_APP_CACHE_LOCK_2_ADDR_PRE_S 0 + +#define DPORT_APP_CACHE_LOCK_3_ADDR_REG (DR_REG_DPORT_BASE + 0x06C) +/* DPORT_APP_CACHE_LOCK_3_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ +/*description: */ +#define DPORT_APP_CACHE_LOCK_3_ADDR_MAX 0x0000000F +#define DPORT_APP_CACHE_LOCK_3_ADDR_MAX_M ((DPORT_APP_CACHE_LOCK_3_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_3_ADDR_MAX_S)) +#define DPORT_APP_CACHE_LOCK_3_ADDR_MAX_V 0xF +#define DPORT_APP_CACHE_LOCK_3_ADDR_MAX_S 18 +/* DPORT_APP_CACHE_LOCK_3_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ +/*description: */ +#define DPORT_APP_CACHE_LOCK_3_ADDR_MIN 0x0000000F +#define DPORT_APP_CACHE_LOCK_3_ADDR_MIN_M ((DPORT_APP_CACHE_LOCK_3_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_3_ADDR_MIN_S)) +#define DPORT_APP_CACHE_LOCK_3_ADDR_MIN_V 0xF +#define DPORT_APP_CACHE_LOCK_3_ADDR_MIN_S 14 +/* DPORT_APP_CACHE_LOCK_3_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: */ +#define DPORT_APP_CACHE_LOCK_3_ADDR_PRE 0x00003FFF +#define DPORT_APP_CACHE_LOCK_3_ADDR_PRE_M ((DPORT_APP_CACHE_LOCK_3_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_3_ADDR_PRE_S)) +#define DPORT_APP_CACHE_LOCK_3_ADDR_PRE_V 0x3FFF +#define DPORT_APP_CACHE_LOCK_3_ADDR_PRE_S 0 + +#define DPORT_TRACEMEM_MUX_MODE_REG (DR_REG_DPORT_BASE + 0x070) +/* DPORT_TRACEMEM_MUX_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: */ +#define DPORT_TRACEMEM_MUX_MODE 0x00000003 +#define DPORT_TRACEMEM_MUX_MODE_M ((DPORT_TRACEMEM_MUX_MODE_V)<<(DPORT_TRACEMEM_MUX_MODE_S)) +#define DPORT_TRACEMEM_MUX_MODE_V 0x3 +#define DPORT_TRACEMEM_MUX_MODE_S 0 + +#define DPORT_PRO_TRACEMEM_ENA_REG (DR_REG_DPORT_BASE + 0x074) +/* DPORT_PRO_TRACEMEM_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_TRACEMEM_ENA (BIT(0)) +#define DPORT_PRO_TRACEMEM_ENA_M (BIT(0)) +#define DPORT_PRO_TRACEMEM_ENA_V 0x1 +#define DPORT_PRO_TRACEMEM_ENA_S 0 + +#define DPORT_APP_TRACEMEM_ENA_REG (DR_REG_DPORT_BASE + 0x078) +/* DPORT_APP_TRACEMEM_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_TRACEMEM_ENA (BIT(0)) +#define DPORT_APP_TRACEMEM_ENA_M (BIT(0)) +#define DPORT_APP_TRACEMEM_ENA_V 0x1 +#define DPORT_APP_TRACEMEM_ENA_S 0 + +#define DPORT_CACHE_MUX_MODE_REG (DR_REG_DPORT_BASE + 0x07C) +/* DPORT_CACHE_MUX_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: */ +#define DPORT_CACHE_MUX_MODE 0x00000003 +#define DPORT_CACHE_MUX_MODE_M ((DPORT_CACHE_MUX_MODE_V)<<(DPORT_CACHE_MUX_MODE_S)) +#define DPORT_CACHE_MUX_MODE_V 0x3 +#define DPORT_CACHE_MUX_MODE_S 0 + +#define DPORT_IMMU_PAGE_MODE_REG (DR_REG_DPORT_BASE + 0x080) +/* DPORT_IMMU_PAGE_MODE : R/W ;bitpos:[2:1] ;default: 2'b0 ; */ +/*description: */ +#define DPORT_IMMU_PAGE_MODE 0x00000003 +#define DPORT_IMMU_PAGE_MODE_M ((DPORT_IMMU_PAGE_MODE_V)<<(DPORT_IMMU_PAGE_MODE_S)) +#define DPORT_IMMU_PAGE_MODE_V 0x3 +#define DPORT_IMMU_PAGE_MODE_S 1 +/* DPORT_INTERNAL_SRAM_IMMU_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_INTERNAL_SRAM_IMMU_ENA (BIT(0)) +#define DPORT_INTERNAL_SRAM_IMMU_ENA_M (BIT(0)) +#define DPORT_INTERNAL_SRAM_IMMU_ENA_V 0x1 +#define DPORT_INTERNAL_SRAM_IMMU_ENA_S 0 + +#define DPORT_DMMU_PAGE_MODE_REG (DR_REG_DPORT_BASE + 0x084) +/* DPORT_DMMU_PAGE_MODE : R/W ;bitpos:[2:1] ;default: 2'b0 ; */ +/*description: */ +#define DPORT_DMMU_PAGE_MODE 0x00000003 +#define DPORT_DMMU_PAGE_MODE_M ((DPORT_DMMU_PAGE_MODE_V)<<(DPORT_DMMU_PAGE_MODE_S)) +#define DPORT_DMMU_PAGE_MODE_V 0x3 +#define DPORT_DMMU_PAGE_MODE_S 1 +/* DPORT_INTERNAL_SRAM_DMMU_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_INTERNAL_SRAM_DMMU_ENA (BIT(0)) +#define DPORT_INTERNAL_SRAM_DMMU_ENA_M (BIT(0)) +#define DPORT_INTERNAL_SRAM_DMMU_ENA_V 0x1 +#define DPORT_INTERNAL_SRAM_DMMU_ENA_S 0 + +#define DPORT_ROM_MPU_ENA_REG (DR_REG_DPORT_BASE + 0x088) +/* DPORT_APP_ROM_MPU_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_ROM_MPU_ENA (BIT(2)) +#define DPORT_APP_ROM_MPU_ENA_M (BIT(2)) +#define DPORT_APP_ROM_MPU_ENA_V 0x1 +#define DPORT_APP_ROM_MPU_ENA_S 2 +/* DPORT_PRO_ROM_MPU_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_ROM_MPU_ENA (BIT(1)) +#define DPORT_PRO_ROM_MPU_ENA_M (BIT(1)) +#define DPORT_PRO_ROM_MPU_ENA_V 0x1 +#define DPORT_PRO_ROM_MPU_ENA_S 1 +/* DPORT_SHARE_ROM_MPU_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_SHARE_ROM_MPU_ENA (BIT(0)) +#define DPORT_SHARE_ROM_MPU_ENA_M (BIT(0)) +#define DPORT_SHARE_ROM_MPU_ENA_V 0x1 +#define DPORT_SHARE_ROM_MPU_ENA_S 0 + +#define DPORT_MEM_PD_MASK_REG (DR_REG_DPORT_BASE + 0x08C) +/* DPORT_LSLP_MEM_PD_MASK : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_LSLP_MEM_PD_MASK (BIT(0)) +#define DPORT_LSLP_MEM_PD_MASK_M (BIT(0)) +#define DPORT_LSLP_MEM_PD_MASK_V 0x1 +#define DPORT_LSLP_MEM_PD_MASK_S 0 + +#define DPORT_ROM_PD_CTRL_REG (DR_REG_DPORT_BASE + 0x090) +/* DPORT_SHARE_ROM_PD : R/W ;bitpos:[7:2] ;default: 6'h0 ; */ +/*description: */ +#define DPORT_SHARE_ROM_PD 0x0000003F +#define DPORT_SHARE_ROM_PD_M ((DPORT_SHARE_ROM_PD_V)<<(DPORT_SHARE_ROM_PD_S)) +#define DPORT_SHARE_ROM_PD_V 0x3F +#define DPORT_SHARE_ROM_PD_S 2 +/* DPORT_APP_ROM_PD : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: */ +#define DPORT_APP_ROM_PD (BIT(1)) +#define DPORT_APP_ROM_PD_M (BIT(1)) +#define DPORT_APP_ROM_PD_V 0x1 +#define DPORT_APP_ROM_PD_S 1 +/* DPORT_PRO_ROM_PD : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define DPORT_PRO_ROM_PD (BIT(0)) +#define DPORT_PRO_ROM_PD_M (BIT(0)) +#define DPORT_PRO_ROM_PD_V 0x1 +#define DPORT_PRO_ROM_PD_S 0 + +#define DPORT_ROM_FO_CTRL_REG (DR_REG_DPORT_BASE + 0x094) +/* DPORT_SHARE_ROM_FO : R/W ;bitpos:[7:2] ;default: 6'h0 ; */ +/*description: */ +#define DPORT_SHARE_ROM_FO 0x0000003F +#define DPORT_SHARE_ROM_FO_M ((DPORT_SHARE_ROM_FO_V)<<(DPORT_SHARE_ROM_FO_S)) +#define DPORT_SHARE_ROM_FO_V 0x3F +#define DPORT_SHARE_ROM_FO_S 2 +/* DPORT_APP_ROM_FO : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/*description: */ +#define DPORT_APP_ROM_FO (BIT(1)) +#define DPORT_APP_ROM_FO_M (BIT(1)) +#define DPORT_APP_ROM_FO_V 0x1 +#define DPORT_APP_ROM_FO_S 1 +/* DPORT_PRO_ROM_FO : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/*description: */ +#define DPORT_PRO_ROM_FO (BIT(0)) +#define DPORT_PRO_ROM_FO_M (BIT(0)) +#define DPORT_PRO_ROM_FO_V 0x1 +#define DPORT_PRO_ROM_FO_S 0 + +#define DPORT_SRAM_PD_CTRL_0_REG (DR_REG_DPORT_BASE + 0x098) +/* DPORT_SRAM_PD_0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define DPORT_SRAM_PD_0 0xFFFFFFFF +#define DPORT_SRAM_PD_0_M ((DPORT_SRAM_PD_0_V)<<(DPORT_SRAM_PD_0_S)) +#define DPORT_SRAM_PD_0_V 0xFFFFFFFF +#define DPORT_SRAM_PD_0_S 0 + +#define DPORT_SRAM_PD_CTRL_1_REG (DR_REG_DPORT_BASE + 0x09C) +/* DPORT_SRAM_PD_1 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define DPORT_SRAM_PD_1 (BIT(0)) +#define DPORT_SRAM_PD_1_M (BIT(0)) +#define DPORT_SRAM_PD_1_V 0x1 +#define DPORT_SRAM_PD_1_S 0 + +#define DPORT_SRAM_FO_CTRL_0_REG (DR_REG_DPORT_BASE + 0x0A0) +/* DPORT_SRAM_FO_0 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/*description: */ +#define DPORT_SRAM_FO_0 0xFFFFFFFF +#define DPORT_SRAM_FO_0_M ((DPORT_SRAM_FO_0_V)<<(DPORT_SRAM_FO_0_S)) +#define DPORT_SRAM_FO_0_V 0xFFFFFFFF +#define DPORT_SRAM_FO_0_S 0 + +#define DPORT_SRAM_FO_CTRL_1_REG (DR_REG_DPORT_BASE + 0x0A4) +/* DPORT_SRAM_FO_1 : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/*description: */ +#define DPORT_SRAM_FO_1 (BIT(0)) +#define DPORT_SRAM_FO_1_M (BIT(0)) +#define DPORT_SRAM_FO_1_V 0x1 +#define DPORT_SRAM_FO_1_S 0 + +#define DPORT_IRAM_DRAM_AHB_SEL_REG (DR_REG_DPORT_BASE + 0x0A8) +/* DPORT_MAC_DUMP_MODE : R/W ;bitpos:[6:5] ;default: 2'h0 ; */ +/*description: */ +#define DPORT_MAC_DUMP_MODE 0x00000003 +#define DPORT_MAC_DUMP_MODE_M ((DPORT_MAC_DUMP_MODE_V)<<(DPORT_MAC_DUMP_MODE_S)) +#define DPORT_MAC_DUMP_MODE_V 0x3 +#define DPORT_MAC_DUMP_MODE_S 5 +/* DPORT_MASK_AHB : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_MASK_AHB (BIT(4)) +#define DPORT_MASK_AHB_M (BIT(4)) +#define DPORT_MASK_AHB_V 0x1 +#define DPORT_MASK_AHB_S 4 +/* DPORT_MASK_APP_DRAM : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_MASK_APP_DRAM (BIT(3)) +#define DPORT_MASK_APP_DRAM_M (BIT(3)) +#define DPORT_MASK_APP_DRAM_V 0x1 +#define DPORT_MASK_APP_DRAM_S 3 +/* DPORT_MASK_PRO_DRAM : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_MASK_PRO_DRAM (BIT(2)) +#define DPORT_MASK_PRO_DRAM_M (BIT(2)) +#define DPORT_MASK_PRO_DRAM_V 0x1 +#define DPORT_MASK_PRO_DRAM_S 2 +/* DPORT_MASK_APP_IRAM : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_MASK_APP_IRAM (BIT(1)) +#define DPORT_MASK_APP_IRAM_M (BIT(1)) +#define DPORT_MASK_APP_IRAM_V 0x1 +#define DPORT_MASK_APP_IRAM_S 1 +/* DPORT_MASK_PRO_IRAM : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_MASK_PRO_IRAM (BIT(0)) +#define DPORT_MASK_PRO_IRAM_M (BIT(0)) +#define DPORT_MASK_PRO_IRAM_V 0x1 +#define DPORT_MASK_PRO_IRAM_S 0 + +#define DPORT_TAG_FO_CTRL_REG (DR_REG_DPORT_BASE + 0x0AC) +/* DPORT_APP_CACHE_TAG_PD : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_CACHE_TAG_PD (BIT(9)) +#define DPORT_APP_CACHE_TAG_PD_M (BIT(9)) +#define DPORT_APP_CACHE_TAG_PD_V 0x1 +#define DPORT_APP_CACHE_TAG_PD_S 9 +/* DPORT_APP_CACHE_TAG_FORCE_ON : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_APP_CACHE_TAG_FORCE_ON (BIT(8)) +#define DPORT_APP_CACHE_TAG_FORCE_ON_M (BIT(8)) +#define DPORT_APP_CACHE_TAG_FORCE_ON_V 0x1 +#define DPORT_APP_CACHE_TAG_FORCE_ON_S 8 +/* DPORT_PRO_CACHE_TAG_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_TAG_PD (BIT(1)) +#define DPORT_PRO_CACHE_TAG_PD_M (BIT(1)) +#define DPORT_PRO_CACHE_TAG_PD_V 0x1 +#define DPORT_PRO_CACHE_TAG_PD_S 1 +/* DPORT_PRO_CACHE_TAG_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_PRO_CACHE_TAG_FORCE_ON (BIT(0)) +#define DPORT_PRO_CACHE_TAG_FORCE_ON_M (BIT(0)) +#define DPORT_PRO_CACHE_TAG_FORCE_ON_V 0x1 +#define DPORT_PRO_CACHE_TAG_FORCE_ON_S 0 + +#define DPORT_AHB_LITE_MASK_REG (DR_REG_DPORT_BASE + 0x0B0) +/* DPORT_AHB_LITE_SDHOST_PID_REG : R/W ;bitpos:[13:11] ;default: 3'b0 ; */ +/*description: */ +#define DPORT_AHB_LITE_SDHOST_PID_REG 0x00000007 +#define DPORT_AHB_LITE_SDHOST_PID_REG_M ((DPORT_AHB_LITE_SDHOST_PID_REG_V)<<(DPORT_AHB_LITE_SDHOST_PID_REG_S)) +#define DPORT_AHB_LITE_SDHOST_PID_REG_V 0x7 +#define DPORT_AHB_LITE_SDHOST_PID_REG_S 11 +/* DPORT_AHB_LITE_MASK_APPDPORT : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_AHB_LITE_MASK_APPDPORT (BIT(10)) +#define DPORT_AHB_LITE_MASK_APPDPORT_M (BIT(10)) +#define DPORT_AHB_LITE_MASK_APPDPORT_V 0x1 +#define DPORT_AHB_LITE_MASK_APPDPORT_S 10 +/* DPORT_AHB_LITE_MASK_PRODPORT : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_AHB_LITE_MASK_PRODPORT (BIT(9)) +#define DPORT_AHB_LITE_MASK_PRODPORT_M (BIT(9)) +#define DPORT_AHB_LITE_MASK_PRODPORT_V 0x1 +#define DPORT_AHB_LITE_MASK_PRODPORT_S 9 +/* DPORT_AHB_LITE_MASK_SDIO : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_AHB_LITE_MASK_SDIO (BIT(8)) +#define DPORT_AHB_LITE_MASK_SDIO_M (BIT(8)) +#define DPORT_AHB_LITE_MASK_SDIO_V 0x1 +#define DPORT_AHB_LITE_MASK_SDIO_S 8 +/* DPORT_AHB_LITE_MASK_APP : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_AHB_LITE_MASK_APP (BIT(4)) +#define DPORT_AHB_LITE_MASK_APP_M (BIT(4)) +#define DPORT_AHB_LITE_MASK_APP_V 0x1 +#define DPORT_AHB_LITE_MASK_APP_S 4 +/* DPORT_AHB_LITE_MASK_PRO : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_AHB_LITE_MASK_PRO (BIT(0)) +#define DPORT_AHB_LITE_MASK_PRO_M (BIT(0)) +#define DPORT_AHB_LITE_MASK_PRO_V 0x1 +#define DPORT_AHB_LITE_MASK_PRO_S 0 + +#define DPORT_AHB_MPU_TABLE_0_REG (DR_REG_DPORT_BASE + 0x0B4) +/* DPORT_AHB_ACCESS_GRANT_0 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/*description: */ +#define DPORT_AHB_ACCESS_GRANT_0 0xFFFFFFFF +#define DPORT_AHB_ACCESS_GRANT_0_M ((DPORT_AHB_ACCESS_GRANT_0_V)<<(DPORT_AHB_ACCESS_GRANT_0_S)) +#define DPORT_AHB_ACCESS_GRANT_0_V 0xFFFFFFFF +#define DPORT_AHB_ACCESS_GRANT_0_S 0 + +#define DPORT_AHB_MPU_TABLE_1_REG (DR_REG_DPORT_BASE + 0x0B8) +/* DPORT_AHB_ACCESS_GRANT_1 : R/W ;bitpos:[8:0] ;default: 9'h1ff ; */ +/*description: */ +#define DPORT_AHB_ACCESS_GRANT_1 0x000001FF +#define DPORT_AHB_ACCESS_GRANT_1_M ((DPORT_AHB_ACCESS_GRANT_1_V)<<(DPORT_AHB_ACCESS_GRANT_1_S)) +#define DPORT_AHB_ACCESS_GRANT_1_V 0x1FF +#define DPORT_AHB_ACCESS_GRANT_1_S 0 + +#define DPORT_HOST_INF_SEL_REG (DR_REG_DPORT_BASE + 0x0BC) +/* DPORT_LINK_DEVICE_SEL : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: */ +#define DPORT_LINK_DEVICE_SEL 0x000000FF +#define DPORT_LINK_DEVICE_SEL_M ((DPORT_LINK_DEVICE_SEL_V)<<(DPORT_LINK_DEVICE_SEL_S)) +#define DPORT_LINK_DEVICE_SEL_V 0xFF +#define DPORT_LINK_DEVICE_SEL_S 8 +/* DPORT_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define DPORT_PERI_IO_SWAP 0x000000FF +#define DPORT_PERI_IO_SWAP_M ((DPORT_PERI_IO_SWAP_V)<<(DPORT_PERI_IO_SWAP_S)) +#define DPORT_PERI_IO_SWAP_V 0xFF +#define DPORT_PERI_IO_SWAP_S 0 + +#define DPORT_PERIP_CLK_EN_REG (DR_REG_DPORT_BASE + 0x0C0) +/* DPORT_PERIP_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hf9c1e06f ; */ +/*description: */ +#define DPORT_PERIP_CLK_EN 0xFFFFFFFF +#define DPORT_PERIP_CLK_EN_M ((DPORT_PERIP_CLK_EN_V)<<(DPORT_PERIP_CLK_EN_S)) +#define DPORT_PERIP_CLK_EN_V 0xFFFFFFFF +#define DPORT_PERIP_CLK_EN_S 0 + +#define DPORT_PWM3_CLK_EN (BIT(26)) +#define DPORT_PWM2_CLK_EN (BIT(25)) +#define DPORT_UART_MEM_CLK_EN (BIT(24)) +#define DPORT_UART2_CLK_EN (BIT(23)) +#define DPORT_SPI_DMA_CLK_EN (BIT(22)) +#define DPORT_I2S1_CLK_EN (BIT(21)) +#define DPORT_PWM1_CLK_EN (BIT(20)) +#define DPORT_CAN_CLK_EN (BIT(19)) +#define DPORT_I2C_EXT1_CLK_EN (BIT(18)) +#define DPORT_PWM0_CLK_EN (BIT(17)) +#define DPORT_SPI_CLK_EN (BIT(16)) +#define DPORT_TIMERGROUP1_CLK_EN (BIT(15)) +#define DPORT_EFUSE_CLK_EN (BIT(14)) +#define DPORT_TIMERGROUP_CLK_EN (BIT(13)) +#define DPORT_UHCI1_CLK_EN (BIT(12)) +#define DPORT_LEDC_CLK_EN (BIT(11)) +#define DPORT_PCNT_CLK_EN (BIT(10)) +#define DPORT_RMT_CLK_EN (BIT(9)) +#define DPORT_UHCI0_CLK_EN (BIT(8)) +#define DPORT_I2C_EXT0_CLK_EN (BIT(7)) +#define DPORT_SPI_CLK_EN_2 (BIT(6)) +#define DPORT_UART1_CLK_EN (BIT(5)) +#define DPORT_I2S0_CLK_EN (BIT(4)) +#define DPORT_WDG_CLK_EN (BIT(3)) +#define DPORT_UART_CLK_EN (BIT(2)) +#define DPORT_SPI_CLK_EN_1 (BIT(1)) +#define DPORT_TIMERS_CLK_EN (BIT(0)) +#define DPORT_PERIP_RST_EN_REG (DR_REG_DPORT_BASE + 0x0C4) +/* DPORT_PERIP_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define DPORT_PERIP_RST 0xFFFFFFFF +#define DPORT_PERIP_RST_M ((DPORT_PERIP_RST_V)<<(DPORT_PERIP_RST_S)) +#define DPORT_PERIP_RST_V 0xFFFFFFFF +#define DPORT_PERIP_RST_S 0 +#define DPORT_PWM3_RST (BIT(26)) +#define DPORT_PWM2_RST (BIT(25)) +#define DPORT_UART_MEM_RST (BIT(24)) +#define DPORT_UART2_RST (BIT(23)) +#define DPORT_SPI_DMA_RST (BIT(22)) +#define DPORT_I2S1_RST (BIT(21)) +#define DPORT_PWM1_RST (BIT(20)) +#define DPORT_CAN_RST (BIT(19)) +#define DPORT_I2C_EXT1_RST (BIT(18)) +#define DPORT_PWM0_RST (BIT(17)) +#define DPORT_SPI_RST (BIT(16)) +#define DPORT_TIMERGROUP1_RST (BIT(15)) +#define DPORT_EFUSE_RST (BIT(14)) +#define DPORT_TIMERGROUP_RST (BIT(13)) +#define DPORT_UHCI1_RST (BIT(12)) +#define DPORT_LEDC_RST (BIT(11)) +#define DPORT_PCNT_RST (BIT(10)) +#define DPORT_RMT_RST (BIT(9)) +#define DPORT_UHCI0_RST (BIT(8)) +#define DPORT_I2C_EXT0_RST (BIT(7)) +#define DPORT_SPI_RST_2 (BIT(6)) +#define DPORT_UART1_RST (BIT(5)) +#define DPORT_I2S0_RST (BIT(4)) +#define DPORT_WDG_RST (BIT(3)) +#define DPORT_UART_RST (BIT(2)) +#define DPORT_SPI_RST_1 (BIT(1)) +#define DPORT_TIMERS_RST (BIT(0)) +#define DPORT_SLAVE_SPI_CONFIG_REG (DR_REG_DPORT_BASE + 0x0C8) +/* DPORT_SPI_DECRYPT_ENABLE : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_SPI_DECRYPT_ENABLE (BIT(12)) +#define DPORT_SPI_DECRYPT_ENABLE_M (BIT(12)) +#define DPORT_SPI_DECRYPT_ENABLE_V 0x1 +#define DPORT_SPI_DECRYPT_ENABLE_S 12 +/* DPORT_SPI_ENCRYPT_ENABLE : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_SPI_ENCRYPT_ENABLE (BIT(8)) +#define DPORT_SPI_ENCRYPT_ENABLE_M (BIT(8)) +#define DPORT_SPI_ENCRYPT_ENABLE_V 0x1 +#define DPORT_SPI_ENCRYPT_ENABLE_S 8 +/* DPORT_SLAVE_SPI_MASK_APP : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_SLAVE_SPI_MASK_APP (BIT(4)) +#define DPORT_SLAVE_SPI_MASK_APP_M (BIT(4)) +#define DPORT_SLAVE_SPI_MASK_APP_V 0x1 +#define DPORT_SLAVE_SPI_MASK_APP_S 4 +/* DPORT_SLAVE_SPI_MASK_PRO : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_SLAVE_SPI_MASK_PRO (BIT(0)) +#define DPORT_SLAVE_SPI_MASK_PRO_M (BIT(0)) +#define DPORT_SLAVE_SPI_MASK_PRO_V 0x1 +#define DPORT_SLAVE_SPI_MASK_PRO_S 0 + +#define DPORT_WIFI_CLK_EN_REG (DR_REG_DPORT_BASE + 0x0CC) +/* DPORT_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */ +/*description: */ +#define DPORT_WIFI_CLK_EN 0xFFFFFFFF +#define DPORT_WIFI_CLK_EN_M ((DPORT_WIFI_CLK_EN_V)<<(DPORT_WIFI_CLK_EN_S)) +#define DPORT_WIFI_CLK_EN_V 0xFFFFFFFF +#define DPORT_WIFI_CLK_EN_S 0 + +#define DPORT_WIFI_RST_EN_REG (DR_REG_DPORT_BASE + 0x0D0) +/* DPORT_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define DPORT_WIFI_RST 0xFFFFFFFF +#define DPORT_WIFI_RST_M ((DPORT_WIFI_RST_V)<<(DPORT_WIFI_RST_S)) +#define DPORT_WIFI_RST_V 0xFFFFFFFF +#define DPORT_WIFI_RST_S 0 + +#define DPORT_BT_LPCK_DIV_INT_REG (DR_REG_DPORT_BASE + 0x0D4) +/* DPORT_BTEXTWAKEUP_REQ : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_BTEXTWAKEUP_REQ (BIT(12)) +#define DPORT_BTEXTWAKEUP_REQ_M (BIT(12)) +#define DPORT_BTEXTWAKEUP_REQ_V 0x1 +#define DPORT_BTEXTWAKEUP_REQ_S 12 +/* DPORT_BT_LPCK_DIV_NUM : R/W ;bitpos:[11:0] ;default: 12'd255 ; */ +/*description: */ +#define DPORT_BT_LPCK_DIV_NUM 0x00000FFF +#define DPORT_BT_LPCK_DIV_NUM_M ((DPORT_BT_LPCK_DIV_NUM_V)<<(DPORT_BT_LPCK_DIV_NUM_S)) +#define DPORT_BT_LPCK_DIV_NUM_V 0xFFF +#define DPORT_BT_LPCK_DIV_NUM_S 0 + +#define DPORT_BT_LPCK_DIV_FRAC_REG (DR_REG_DPORT_BASE + 0x0D8) +/* DPORT_LPCLK_SEL_XTAL32K : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_LPCLK_SEL_XTAL32K (BIT(27)) +#define DPORT_LPCLK_SEL_XTAL32K_M (BIT(27)) +#define DPORT_LPCLK_SEL_XTAL32K_V 0x1 +#define DPORT_LPCLK_SEL_XTAL32K_S 27 +/* DPORT_LPCLK_SEL_XTAL : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_LPCLK_SEL_XTAL (BIT(26)) +#define DPORT_LPCLK_SEL_XTAL_M (BIT(26)) +#define DPORT_LPCLK_SEL_XTAL_V 0x1 +#define DPORT_LPCLK_SEL_XTAL_S 26 +/* DPORT_LPCLK_SEL_8M : R/W ;bitpos:[25] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_LPCLK_SEL_8M (BIT(25)) +#define DPORT_LPCLK_SEL_8M_M (BIT(25)) +#define DPORT_LPCLK_SEL_8M_V 0x1 +#define DPORT_LPCLK_SEL_8M_S 25 +/* DPORT_LPCLK_SEL_RTC_SLOW : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_LPCLK_SEL_RTC_SLOW (BIT(24)) +#define DPORT_LPCLK_SEL_RTC_SLOW_M (BIT(24)) +#define DPORT_LPCLK_SEL_RTC_SLOW_V 0x1 +#define DPORT_LPCLK_SEL_RTC_SLOW_S 24 +/* DPORT_BT_LPCK_DIV_A : R/W ;bitpos:[23:12] ;default: 12'd1 ; */ +/*description: */ +#define DPORT_BT_LPCK_DIV_A 0x00000FFF +#define DPORT_BT_LPCK_DIV_A_M ((DPORT_BT_LPCK_DIV_A_V)<<(DPORT_BT_LPCK_DIV_A_S)) +#define DPORT_BT_LPCK_DIV_A_V 0xFFF +#define DPORT_BT_LPCK_DIV_A_S 12 +/* DPORT_BT_LPCK_DIV_B : R/W ;bitpos:[11:0] ;default: 12'd1 ; */ +/*description: */ +#define DPORT_BT_LPCK_DIV_B 0x00000FFF +#define DPORT_BT_LPCK_DIV_B_M ((DPORT_BT_LPCK_DIV_B_V)<<(DPORT_BT_LPCK_DIV_B_S)) +#define DPORT_BT_LPCK_DIV_B_V 0xFFF +#define DPORT_BT_LPCK_DIV_B_S 0 + +#define DPORT_CPU_INTR_FROM_CPU_0_REG (DR_REG_DPORT_BASE + 0x0DC) +/* DPORT_CPU_INTR_FROM_CPU_0 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_CPU_INTR_FROM_CPU_0 (BIT(0)) +#define DPORT_CPU_INTR_FROM_CPU_0_M (BIT(0)) +#define DPORT_CPU_INTR_FROM_CPU_0_V 0x1 +#define DPORT_CPU_INTR_FROM_CPU_0_S 0 + +#define DPORT_CPU_INTR_FROM_CPU_1_REG (DR_REG_DPORT_BASE + 0x0E0) +/* DPORT_CPU_INTR_FROM_CPU_1 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_CPU_INTR_FROM_CPU_1 (BIT(0)) +#define DPORT_CPU_INTR_FROM_CPU_1_M (BIT(0)) +#define DPORT_CPU_INTR_FROM_CPU_1_V 0x1 +#define DPORT_CPU_INTR_FROM_CPU_1_S 0 + +#define DPORT_CPU_INTR_FROM_CPU_2_REG (DR_REG_DPORT_BASE + 0x0E4) +/* DPORT_CPU_INTR_FROM_CPU_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_CPU_INTR_FROM_CPU_2 (BIT(0)) +#define DPORT_CPU_INTR_FROM_CPU_2_M (BIT(0)) +#define DPORT_CPU_INTR_FROM_CPU_2_V 0x1 +#define DPORT_CPU_INTR_FROM_CPU_2_S 0 + +#define DPORT_CPU_INTR_FROM_CPU_3_REG (DR_REG_DPORT_BASE + 0x0E8) +/* DPORT_CPU_INTR_FROM_CPU_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_CPU_INTR_FROM_CPU_3 (BIT(0)) +#define DPORT_CPU_INTR_FROM_CPU_3_M (BIT(0)) +#define DPORT_CPU_INTR_FROM_CPU_3_V 0x1 +#define DPORT_CPU_INTR_FROM_CPU_3_S 0 + +#define DPORT_PRO_INTR_STATUS_0_REG (DR_REG_DPORT_BASE + 0x0EC) +/* DPORT_PRO_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define DPORT_PRO_INTR_STATUS_0 0xFFFFFFFF +#define DPORT_PRO_INTR_STATUS_0_M ((DPORT_PRO_INTR_STATUS_0_V)<<(DPORT_PRO_INTR_STATUS_0_S)) +#define DPORT_PRO_INTR_STATUS_0_V 0xFFFFFFFF +#define DPORT_PRO_INTR_STATUS_0_S 0 + +#define DPORT_PRO_INTR_STATUS_1_REG (DR_REG_DPORT_BASE + 0x0F0) +/* DPORT_PRO_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define DPORT_PRO_INTR_STATUS_1 0xFFFFFFFF +#define DPORT_PRO_INTR_STATUS_1_M ((DPORT_PRO_INTR_STATUS_1_V)<<(DPORT_PRO_INTR_STATUS_1_S)) +#define DPORT_PRO_INTR_STATUS_1_V 0xFFFFFFFF +#define DPORT_PRO_INTR_STATUS_1_S 0 + +#define DPORT_PRO_INTR_STATUS_2_REG (DR_REG_DPORT_BASE + 0x0F4) +/* DPORT_PRO_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define DPORT_PRO_INTR_STATUS_2 0xFFFFFFFF +#define DPORT_PRO_INTR_STATUS_2_M ((DPORT_PRO_INTR_STATUS_2_V)<<(DPORT_PRO_INTR_STATUS_2_S)) +#define DPORT_PRO_INTR_STATUS_2_V 0xFFFFFFFF +#define DPORT_PRO_INTR_STATUS_2_S 0 + +#define DPORT_APP_INTR_STATUS_0_REG (DR_REG_DPORT_BASE + 0x0F8) +/* DPORT_APP_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define DPORT_APP_INTR_STATUS_0 0xFFFFFFFF +#define DPORT_APP_INTR_STATUS_0_M ((DPORT_APP_INTR_STATUS_0_V)<<(DPORT_APP_INTR_STATUS_0_S)) +#define DPORT_APP_INTR_STATUS_0_V 0xFFFFFFFF +#define DPORT_APP_INTR_STATUS_0_S 0 + +#define DPORT_APP_INTR_STATUS_1_REG (DR_REG_DPORT_BASE + 0x0FC) +/* DPORT_APP_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define DPORT_APP_INTR_STATUS_1 0xFFFFFFFF +#define DPORT_APP_INTR_STATUS_1_M ((DPORT_APP_INTR_STATUS_1_V)<<(DPORT_APP_INTR_STATUS_1_S)) +#define DPORT_APP_INTR_STATUS_1_V 0xFFFFFFFF +#define DPORT_APP_INTR_STATUS_1_S 0 + +#define DPORT_APP_INTR_STATUS_2_REG (DR_REG_DPORT_BASE + 0x100) +/* DPORT_APP_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define DPORT_APP_INTR_STATUS_2 0xFFFFFFFF +#define DPORT_APP_INTR_STATUS_2_M ((DPORT_APP_INTR_STATUS_2_V)<<(DPORT_APP_INTR_STATUS_2_S)) +#define DPORT_APP_INTR_STATUS_2_V 0xFFFFFFFF +#define DPORT_APP_INTR_STATUS_2_S 0 + +#define DPORT_PRO_MAC_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x104) +/* DPORT_PRO_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_MAC_INTR_MAP 0x0000001F +#define DPORT_PRO_MAC_INTR_MAP_M ((DPORT_PRO_MAC_INTR_MAP_V)<<(DPORT_PRO_MAC_INTR_MAP_S)) +#define DPORT_PRO_MAC_INTR_MAP_V 0x1F +#define DPORT_PRO_MAC_INTR_MAP_S 0 + +#define DPORT_PRO_MAC_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x108) +/* DPORT_PRO_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_MAC_NMI_MAP 0x0000001F +#define DPORT_PRO_MAC_NMI_MAP_M ((DPORT_PRO_MAC_NMI_MAP_V)<<(DPORT_PRO_MAC_NMI_MAP_S)) +#define DPORT_PRO_MAC_NMI_MAP_V 0x1F +#define DPORT_PRO_MAC_NMI_MAP_S 0 + +#define DPORT_PRO_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x10C) +/* DPORT_PRO_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_BB_INT_MAP 0x0000001F +#define DPORT_PRO_BB_INT_MAP_M ((DPORT_PRO_BB_INT_MAP_V)<<(DPORT_PRO_BB_INT_MAP_S)) +#define DPORT_PRO_BB_INT_MAP_V 0x1F +#define DPORT_PRO_BB_INT_MAP_S 0 + +#define DPORT_PRO_BT_MAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x110) +/* DPORT_PRO_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_BT_MAC_INT_MAP 0x0000001F +#define DPORT_PRO_BT_MAC_INT_MAP_M ((DPORT_PRO_BT_MAC_INT_MAP_V)<<(DPORT_PRO_BT_MAC_INT_MAP_S)) +#define DPORT_PRO_BT_MAC_INT_MAP_V 0x1F +#define DPORT_PRO_BT_MAC_INT_MAP_S 0 + +#define DPORT_PRO_BT_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x114) +/* DPORT_PRO_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_BT_BB_INT_MAP 0x0000001F +#define DPORT_PRO_BT_BB_INT_MAP_M ((DPORT_PRO_BT_BB_INT_MAP_V)<<(DPORT_PRO_BT_BB_INT_MAP_S)) +#define DPORT_PRO_BT_BB_INT_MAP_V 0x1F +#define DPORT_PRO_BT_BB_INT_MAP_S 0 + +#define DPORT_PRO_BT_BB_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x118) +/* DPORT_PRO_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_BT_BB_NMI_MAP 0x0000001F +#define DPORT_PRO_BT_BB_NMI_MAP_M ((DPORT_PRO_BT_BB_NMI_MAP_V)<<(DPORT_PRO_BT_BB_NMI_MAP_S)) +#define DPORT_PRO_BT_BB_NMI_MAP_V 0x1F +#define DPORT_PRO_BT_BB_NMI_MAP_S 0 + +#define DPORT_PRO_RWBT_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x11C) +/* DPORT_PRO_RWBT_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_RWBT_IRQ_MAP 0x0000001F +#define DPORT_PRO_RWBT_IRQ_MAP_M ((DPORT_PRO_RWBT_IRQ_MAP_V)<<(DPORT_PRO_RWBT_IRQ_MAP_S)) +#define DPORT_PRO_RWBT_IRQ_MAP_V 0x1F +#define DPORT_PRO_RWBT_IRQ_MAP_S 0 + +#define DPORT_PRO_RWBLE_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x120) +/* DPORT_PRO_RWBLE_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_RWBLE_IRQ_MAP 0x0000001F +#define DPORT_PRO_RWBLE_IRQ_MAP_M ((DPORT_PRO_RWBLE_IRQ_MAP_V)<<(DPORT_PRO_RWBLE_IRQ_MAP_S)) +#define DPORT_PRO_RWBLE_IRQ_MAP_V 0x1F +#define DPORT_PRO_RWBLE_IRQ_MAP_S 0 + +#define DPORT_PRO_RWBT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x124) +/* DPORT_PRO_RWBT_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_RWBT_NMI_MAP 0x0000001F +#define DPORT_PRO_RWBT_NMI_MAP_M ((DPORT_PRO_RWBT_NMI_MAP_V)<<(DPORT_PRO_RWBT_NMI_MAP_S)) +#define DPORT_PRO_RWBT_NMI_MAP_V 0x1F +#define DPORT_PRO_RWBT_NMI_MAP_S 0 + +#define DPORT_PRO_RWBLE_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x128) +/* DPORT_PRO_RWBLE_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_RWBLE_NMI_MAP 0x0000001F +#define DPORT_PRO_RWBLE_NMI_MAP_M ((DPORT_PRO_RWBLE_NMI_MAP_V)<<(DPORT_PRO_RWBLE_NMI_MAP_S)) +#define DPORT_PRO_RWBLE_NMI_MAP_V 0x1F +#define DPORT_PRO_RWBLE_NMI_MAP_S 0 + +#define DPORT_PRO_SLC0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x12C) +/* DPORT_PRO_SLC0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_SLC0_INTR_MAP 0x0000001F +#define DPORT_PRO_SLC0_INTR_MAP_M ((DPORT_PRO_SLC0_INTR_MAP_V)<<(DPORT_PRO_SLC0_INTR_MAP_S)) +#define DPORT_PRO_SLC0_INTR_MAP_V 0x1F +#define DPORT_PRO_SLC0_INTR_MAP_S 0 + +#define DPORT_PRO_SLC1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x130) +/* DPORT_PRO_SLC1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_SLC1_INTR_MAP 0x0000001F +#define DPORT_PRO_SLC1_INTR_MAP_M ((DPORT_PRO_SLC1_INTR_MAP_V)<<(DPORT_PRO_SLC1_INTR_MAP_S)) +#define DPORT_PRO_SLC1_INTR_MAP_V 0x1F +#define DPORT_PRO_SLC1_INTR_MAP_S 0 + +#define DPORT_PRO_UHCI0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x134) +/* DPORT_PRO_UHCI0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_UHCI0_INTR_MAP 0x0000001F +#define DPORT_PRO_UHCI0_INTR_MAP_M ((DPORT_PRO_UHCI0_INTR_MAP_V)<<(DPORT_PRO_UHCI0_INTR_MAP_S)) +#define DPORT_PRO_UHCI0_INTR_MAP_V 0x1F +#define DPORT_PRO_UHCI0_INTR_MAP_S 0 + +#define DPORT_PRO_UHCI1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x138) +/* DPORT_PRO_UHCI1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_UHCI1_INTR_MAP 0x0000001F +#define DPORT_PRO_UHCI1_INTR_MAP_M ((DPORT_PRO_UHCI1_INTR_MAP_V)<<(DPORT_PRO_UHCI1_INTR_MAP_S)) +#define DPORT_PRO_UHCI1_INTR_MAP_V 0x1F +#define DPORT_PRO_UHCI1_INTR_MAP_S 0 + +#define DPORT_PRO_TG_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x13C) +/* DPORT_PRO_TG_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_TG_T0_LEVEL_INT_MAP 0x0000001F +#define DPORT_PRO_TG_T0_LEVEL_INT_MAP_M ((DPORT_PRO_TG_T0_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_T0_LEVEL_INT_MAP_S)) +#define DPORT_PRO_TG_T0_LEVEL_INT_MAP_V 0x1F +#define DPORT_PRO_TG_T0_LEVEL_INT_MAP_S 0 + +#define DPORT_PRO_TG_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x140) +/* DPORT_PRO_TG_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_TG_T1_LEVEL_INT_MAP 0x0000001F +#define DPORT_PRO_TG_T1_LEVEL_INT_MAP_M ((DPORT_PRO_TG_T1_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_T1_LEVEL_INT_MAP_S)) +#define DPORT_PRO_TG_T1_LEVEL_INT_MAP_V 0x1F +#define DPORT_PRO_TG_T1_LEVEL_INT_MAP_S 0 + +#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x144) +/* DPORT_PRO_TG_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP 0x0000001F +#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_M ((DPORT_PRO_TG_WDT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_WDT_LEVEL_INT_MAP_S)) +#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_V 0x1F +#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_S 0 + +#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x148) +/* DPORT_PRO_TG_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP 0x0000001F +#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_M ((DPORT_PRO_TG_LACT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_LACT_LEVEL_INT_MAP_S)) +#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_V 0x1F +#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_S 0 + +#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x14C) +/* DPORT_PRO_TG1_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP 0x0000001F +#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_T0_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_T0_LEVEL_INT_MAP_S)) +#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_V 0x1F +#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_S 0 + +#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x150) +/* DPORT_PRO_TG1_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP 0x0000001F +#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_T1_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_T1_LEVEL_INT_MAP_S)) +#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_V 0x1F +#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_S 0 + +#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x154) +/* DPORT_PRO_TG1_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP 0x0000001F +#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_S)) +#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_V 0x1F +#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_S 0 + +#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x158) +/* DPORT_PRO_TG1_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP 0x0000001F +#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_S)) +#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_V 0x1F +#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_S 0 + +#define DPORT_PRO_GPIO_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x15C) +/* DPORT_PRO_GPIO_INTERRUPT_PRO_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP 0x0000001F +#define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_M ((DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_V)<<(DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_S)) +#define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_V 0x1F +#define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_S 0 + +#define DPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x160) +/* DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000001F +#define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_M ((DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_V)<<(DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_S)) +#define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_V 0x1F +#define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_S 0 + +#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_DPORT_BASE + 0x164) +/* DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP 0x0000001F +#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_S)) +#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_V 0x1F +#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_S 0 + +#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_DPORT_BASE + 0x168) +/* DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP 0x0000001F +#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_S)) +#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_V 0x1F +#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_S 0 + +#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_DPORT_BASE + 0x16C) +/* DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP 0x0000001F +#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_S)) +#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_V 0x1F +#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_S 0 + +#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_DPORT_BASE + 0x170) +/* DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP 0x0000001F +#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_S)) +#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_V 0x1F +#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_S 0 + +#define DPORT_PRO_SPI_INTR_0_MAP_REG (DR_REG_DPORT_BASE + 0x174) +/* DPORT_PRO_SPI_INTR_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_SPI_INTR_0_MAP 0x0000001F +#define DPORT_PRO_SPI_INTR_0_MAP_M ((DPORT_PRO_SPI_INTR_0_MAP_V)<<(DPORT_PRO_SPI_INTR_0_MAP_S)) +#define DPORT_PRO_SPI_INTR_0_MAP_V 0x1F +#define DPORT_PRO_SPI_INTR_0_MAP_S 0 + +#define DPORT_PRO_SPI_INTR_1_MAP_REG (DR_REG_DPORT_BASE + 0x178) +/* DPORT_PRO_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_SPI_INTR_1_MAP 0x0000001F +#define DPORT_PRO_SPI_INTR_1_MAP_M ((DPORT_PRO_SPI_INTR_1_MAP_V)<<(DPORT_PRO_SPI_INTR_1_MAP_S)) +#define DPORT_PRO_SPI_INTR_1_MAP_V 0x1F +#define DPORT_PRO_SPI_INTR_1_MAP_S 0 + +#define DPORT_PRO_SPI_INTR_2_MAP_REG (DR_REG_DPORT_BASE + 0x17C) +/* DPORT_PRO_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_SPI_INTR_2_MAP 0x0000001F +#define DPORT_PRO_SPI_INTR_2_MAP_M ((DPORT_PRO_SPI_INTR_2_MAP_V)<<(DPORT_PRO_SPI_INTR_2_MAP_S)) +#define DPORT_PRO_SPI_INTR_2_MAP_V 0x1F +#define DPORT_PRO_SPI_INTR_2_MAP_S 0 + +#define DPORT_PRO_SPI_INTR_3_MAP_REG (DR_REG_DPORT_BASE + 0x180) +/* DPORT_PRO_SPI_INTR_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_SPI_INTR_3_MAP 0x0000001F +#define DPORT_PRO_SPI_INTR_3_MAP_M ((DPORT_PRO_SPI_INTR_3_MAP_V)<<(DPORT_PRO_SPI_INTR_3_MAP_S)) +#define DPORT_PRO_SPI_INTR_3_MAP_V 0x1F +#define DPORT_PRO_SPI_INTR_3_MAP_S 0 + +#define DPORT_PRO_I2S0_INT_MAP_REG (DR_REG_DPORT_BASE + 0x184) +/* DPORT_PRO_I2S0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_I2S0_INT_MAP 0x0000001F +#define DPORT_PRO_I2S0_INT_MAP_M ((DPORT_PRO_I2S0_INT_MAP_V)<<(DPORT_PRO_I2S0_INT_MAP_S)) +#define DPORT_PRO_I2S0_INT_MAP_V 0x1F +#define DPORT_PRO_I2S0_INT_MAP_S 0 + +#define DPORT_PRO_I2S1_INT_MAP_REG (DR_REG_DPORT_BASE + 0x188) +/* DPORT_PRO_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_I2S1_INT_MAP 0x0000001F +#define DPORT_PRO_I2S1_INT_MAP_M ((DPORT_PRO_I2S1_INT_MAP_V)<<(DPORT_PRO_I2S1_INT_MAP_S)) +#define DPORT_PRO_I2S1_INT_MAP_V 0x1F +#define DPORT_PRO_I2S1_INT_MAP_S 0 + +#define DPORT_PRO_UART_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x18C) +/* DPORT_PRO_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_UART_INTR_MAP 0x0000001F +#define DPORT_PRO_UART_INTR_MAP_M ((DPORT_PRO_UART_INTR_MAP_V)<<(DPORT_PRO_UART_INTR_MAP_S)) +#define DPORT_PRO_UART_INTR_MAP_V 0x1F +#define DPORT_PRO_UART_INTR_MAP_S 0 + +#define DPORT_PRO_UART1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x190) +/* DPORT_PRO_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_UART1_INTR_MAP 0x0000001F +#define DPORT_PRO_UART1_INTR_MAP_M ((DPORT_PRO_UART1_INTR_MAP_V)<<(DPORT_PRO_UART1_INTR_MAP_S)) +#define DPORT_PRO_UART1_INTR_MAP_V 0x1F +#define DPORT_PRO_UART1_INTR_MAP_S 0 + +#define DPORT_PRO_UART2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x194) +/* DPORT_PRO_UART2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_UART2_INTR_MAP 0x0000001F +#define DPORT_PRO_UART2_INTR_MAP_M ((DPORT_PRO_UART2_INTR_MAP_V)<<(DPORT_PRO_UART2_INTR_MAP_S)) +#define DPORT_PRO_UART2_INTR_MAP_V 0x1F +#define DPORT_PRO_UART2_INTR_MAP_S 0 + +#define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x198) +/* DPORT_PRO_SDIO_HOST_INTERRUPT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP 0x0000001F +#define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_M ((DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_V)<<(DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_S)) +#define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_V 0x1F +#define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_S 0 + +#define DPORT_PRO_EMAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x19C) +/* DPORT_PRO_EMAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_EMAC_INT_MAP 0x0000001F +#define DPORT_PRO_EMAC_INT_MAP_M ((DPORT_PRO_EMAC_INT_MAP_V)<<(DPORT_PRO_EMAC_INT_MAP_S)) +#define DPORT_PRO_EMAC_INT_MAP_V 0x1F +#define DPORT_PRO_EMAC_INT_MAP_S 0 + +#define DPORT_PRO_PWM0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1A0) +/* DPORT_PRO_PWM0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_PWM0_INTR_MAP 0x0000001F +#define DPORT_PRO_PWM0_INTR_MAP_M ((DPORT_PRO_PWM0_INTR_MAP_V)<<(DPORT_PRO_PWM0_INTR_MAP_S)) +#define DPORT_PRO_PWM0_INTR_MAP_V 0x1F +#define DPORT_PRO_PWM0_INTR_MAP_S 0 + +#define DPORT_PRO_PWM1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1A4) +/* DPORT_PRO_PWM1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_PWM1_INTR_MAP 0x0000001F +#define DPORT_PRO_PWM1_INTR_MAP_M ((DPORT_PRO_PWM1_INTR_MAP_V)<<(DPORT_PRO_PWM1_INTR_MAP_S)) +#define DPORT_PRO_PWM1_INTR_MAP_V 0x1F +#define DPORT_PRO_PWM1_INTR_MAP_S 0 + +#define DPORT_PRO_PWM2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1A8) +/* DPORT_PRO_PWM2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_PWM2_INTR_MAP 0x0000001F +#define DPORT_PRO_PWM2_INTR_MAP_M ((DPORT_PRO_PWM2_INTR_MAP_V)<<(DPORT_PRO_PWM2_INTR_MAP_S)) +#define DPORT_PRO_PWM2_INTR_MAP_V 0x1F +#define DPORT_PRO_PWM2_INTR_MAP_S 0 + +#define DPORT_PRO_PWM3_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1AC) +/* DPORT_PRO_PWM3_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_PWM3_INTR_MAP 0x0000001F +#define DPORT_PRO_PWM3_INTR_MAP_M ((DPORT_PRO_PWM3_INTR_MAP_V)<<(DPORT_PRO_PWM3_INTR_MAP_S)) +#define DPORT_PRO_PWM3_INTR_MAP_V 0x1F +#define DPORT_PRO_PWM3_INTR_MAP_S 0 + +#define DPORT_PRO_LEDC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1B0) +/* DPORT_PRO_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_LEDC_INT_MAP 0x0000001F +#define DPORT_PRO_LEDC_INT_MAP_M ((DPORT_PRO_LEDC_INT_MAP_V)<<(DPORT_PRO_LEDC_INT_MAP_S)) +#define DPORT_PRO_LEDC_INT_MAP_V 0x1F +#define DPORT_PRO_LEDC_INT_MAP_S 0 + +#define DPORT_PRO_EFUSE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1B4) +/* DPORT_PRO_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_EFUSE_INT_MAP 0x0000001F +#define DPORT_PRO_EFUSE_INT_MAP_M ((DPORT_PRO_EFUSE_INT_MAP_V)<<(DPORT_PRO_EFUSE_INT_MAP_S)) +#define DPORT_PRO_EFUSE_INT_MAP_V 0x1F +#define DPORT_PRO_EFUSE_INT_MAP_S 0 + +#define DPORT_PRO_CAN_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1B8) +/* DPORT_PRO_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_CAN_INT_MAP 0x0000001F +#define DPORT_PRO_CAN_INT_MAP_M ((DPORT_PRO_CAN_INT_MAP_V)<<(DPORT_PRO_CAN_INT_MAP_S)) +#define DPORT_PRO_CAN_INT_MAP_V 0x1F +#define DPORT_PRO_CAN_INT_MAP_S 0 + +#define DPORT_PRO_RTC_CORE_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1BC) +/* DPORT_PRO_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_RTC_CORE_INTR_MAP 0x0000001F +#define DPORT_PRO_RTC_CORE_INTR_MAP_M ((DPORT_PRO_RTC_CORE_INTR_MAP_V)<<(DPORT_PRO_RTC_CORE_INTR_MAP_S)) +#define DPORT_PRO_RTC_CORE_INTR_MAP_V 0x1F +#define DPORT_PRO_RTC_CORE_INTR_MAP_S 0 + +#define DPORT_PRO_RMT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1C0) +/* DPORT_PRO_RMT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_RMT_INTR_MAP 0x0000001F +#define DPORT_PRO_RMT_INTR_MAP_M ((DPORT_PRO_RMT_INTR_MAP_V)<<(DPORT_PRO_RMT_INTR_MAP_S)) +#define DPORT_PRO_RMT_INTR_MAP_V 0x1F +#define DPORT_PRO_RMT_INTR_MAP_S 0 + +#define DPORT_PRO_PCNT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1C4) +/* DPORT_PRO_PCNT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_PCNT_INTR_MAP 0x0000001F +#define DPORT_PRO_PCNT_INTR_MAP_M ((DPORT_PRO_PCNT_INTR_MAP_V)<<(DPORT_PRO_PCNT_INTR_MAP_S)) +#define DPORT_PRO_PCNT_INTR_MAP_V 0x1F +#define DPORT_PRO_PCNT_INTR_MAP_S 0 + +#define DPORT_PRO_I2C_EXT0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1C8) +/* DPORT_PRO_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_I2C_EXT0_INTR_MAP 0x0000001F +#define DPORT_PRO_I2C_EXT0_INTR_MAP_M ((DPORT_PRO_I2C_EXT0_INTR_MAP_V)<<(DPORT_PRO_I2C_EXT0_INTR_MAP_S)) +#define DPORT_PRO_I2C_EXT0_INTR_MAP_V 0x1F +#define DPORT_PRO_I2C_EXT0_INTR_MAP_S 0 + +#define DPORT_PRO_I2C_EXT1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1CC) +/* DPORT_PRO_I2C_EXT1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_I2C_EXT1_INTR_MAP 0x0000001F +#define DPORT_PRO_I2C_EXT1_INTR_MAP_M ((DPORT_PRO_I2C_EXT1_INTR_MAP_V)<<(DPORT_PRO_I2C_EXT1_INTR_MAP_S)) +#define DPORT_PRO_I2C_EXT1_INTR_MAP_V 0x1F +#define DPORT_PRO_I2C_EXT1_INTR_MAP_S 0 + +#define DPORT_PRO_RSA_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1D0) +/* DPORT_PRO_RSA_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_RSA_INTR_MAP 0x0000001F +#define DPORT_PRO_RSA_INTR_MAP_M ((DPORT_PRO_RSA_INTR_MAP_V)<<(DPORT_PRO_RSA_INTR_MAP_S)) +#define DPORT_PRO_RSA_INTR_MAP_V 0x1F +#define DPORT_PRO_RSA_INTR_MAP_S 0 + +#define DPORT_PRO_SPI1_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1D4) +/* DPORT_PRO_SPI1_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_SPI1_DMA_INT_MAP 0x0000001F +#define DPORT_PRO_SPI1_DMA_INT_MAP_M ((DPORT_PRO_SPI1_DMA_INT_MAP_V)<<(DPORT_PRO_SPI1_DMA_INT_MAP_S)) +#define DPORT_PRO_SPI1_DMA_INT_MAP_V 0x1F +#define DPORT_PRO_SPI1_DMA_INT_MAP_S 0 + +#define DPORT_PRO_SPI2_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1D8) +/* DPORT_PRO_SPI2_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_SPI2_DMA_INT_MAP 0x0000001F +#define DPORT_PRO_SPI2_DMA_INT_MAP_M ((DPORT_PRO_SPI2_DMA_INT_MAP_V)<<(DPORT_PRO_SPI2_DMA_INT_MAP_S)) +#define DPORT_PRO_SPI2_DMA_INT_MAP_V 0x1F +#define DPORT_PRO_SPI2_DMA_INT_MAP_S 0 + +#define DPORT_PRO_SPI3_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1DC) +/* DPORT_PRO_SPI3_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_SPI3_DMA_INT_MAP 0x0000001F +#define DPORT_PRO_SPI3_DMA_INT_MAP_M ((DPORT_PRO_SPI3_DMA_INT_MAP_V)<<(DPORT_PRO_SPI3_DMA_INT_MAP_S)) +#define DPORT_PRO_SPI3_DMA_INT_MAP_V 0x1F +#define DPORT_PRO_SPI3_DMA_INT_MAP_S 0 + +#define DPORT_PRO_WDG_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1E0) +/* DPORT_PRO_WDG_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_WDG_INT_MAP 0x0000001F +#define DPORT_PRO_WDG_INT_MAP_M ((DPORT_PRO_WDG_INT_MAP_V)<<(DPORT_PRO_WDG_INT_MAP_S)) +#define DPORT_PRO_WDG_INT_MAP_V 0x1F +#define DPORT_PRO_WDG_INT_MAP_S 0 + +#define DPORT_PRO_TIMER_INT1_MAP_REG (DR_REG_DPORT_BASE + 0x1E4) +/* DPORT_PRO_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_TIMER_INT1_MAP 0x0000001F +#define DPORT_PRO_TIMER_INT1_MAP_M ((DPORT_PRO_TIMER_INT1_MAP_V)<<(DPORT_PRO_TIMER_INT1_MAP_S)) +#define DPORT_PRO_TIMER_INT1_MAP_V 0x1F +#define DPORT_PRO_TIMER_INT1_MAP_S 0 + +#define DPORT_PRO_TIMER_INT2_MAP_REG (DR_REG_DPORT_BASE + 0x1E8) +/* DPORT_PRO_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_TIMER_INT2_MAP 0x0000001F +#define DPORT_PRO_TIMER_INT2_MAP_M ((DPORT_PRO_TIMER_INT2_MAP_V)<<(DPORT_PRO_TIMER_INT2_MAP_S)) +#define DPORT_PRO_TIMER_INT2_MAP_V 0x1F +#define DPORT_PRO_TIMER_INT2_MAP_S 0 + +#define DPORT_PRO_TG_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1EC) +/* DPORT_PRO_TG_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_TG_T0_EDGE_INT_MAP 0x0000001F +#define DPORT_PRO_TG_T0_EDGE_INT_MAP_M ((DPORT_PRO_TG_T0_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_T0_EDGE_INT_MAP_S)) +#define DPORT_PRO_TG_T0_EDGE_INT_MAP_V 0x1F +#define DPORT_PRO_TG_T0_EDGE_INT_MAP_S 0 + +#define DPORT_PRO_TG_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1F0) +/* DPORT_PRO_TG_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_TG_T1_EDGE_INT_MAP 0x0000001F +#define DPORT_PRO_TG_T1_EDGE_INT_MAP_M ((DPORT_PRO_TG_T1_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_T1_EDGE_INT_MAP_S)) +#define DPORT_PRO_TG_T1_EDGE_INT_MAP_V 0x1F +#define DPORT_PRO_TG_T1_EDGE_INT_MAP_S 0 + +#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1F4) +/* DPORT_PRO_TG_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_TG_WDT_EDGE_INT_MAP 0x0000001F +#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_M ((DPORT_PRO_TG_WDT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_WDT_EDGE_INT_MAP_S)) +#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_V 0x1F +#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_S 0 + +#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1F8) +/* DPORT_PRO_TG_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_TG_LACT_EDGE_INT_MAP 0x0000001F +#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_M ((DPORT_PRO_TG_LACT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_LACT_EDGE_INT_MAP_S)) +#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_V 0x1F +#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_S 0 + +#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1FC) +/* DPORT_PRO_TG1_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_TG1_T0_EDGE_INT_MAP 0x0000001F +#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_M ((DPORT_PRO_TG1_T0_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_T0_EDGE_INT_MAP_S)) +#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_V 0x1F +#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_S 0 + +#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x200) +/* DPORT_PRO_TG1_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_TG1_T1_EDGE_INT_MAP 0x0000001F +#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_M ((DPORT_PRO_TG1_T1_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_T1_EDGE_INT_MAP_S)) +#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_V 0x1F +#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_S 0 + +#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x204) +/* DPORT_PRO_TG1_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP 0x0000001F +#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_M ((DPORT_PRO_TG1_WDT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_WDT_EDGE_INT_MAP_S)) +#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_V 0x1F +#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_S 0 + +#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x208) +/* DPORT_PRO_TG1_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP 0x0000001F +#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_M ((DPORT_PRO_TG1_LACT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_LACT_EDGE_INT_MAP_S)) +#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_V 0x1F +#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_S 0 + +#define DPORT_PRO_MMU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x20C) +/* DPORT_PRO_MMU_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_MMU_IA_INT_MAP 0x0000001F +#define DPORT_PRO_MMU_IA_INT_MAP_M ((DPORT_PRO_MMU_IA_INT_MAP_V)<<(DPORT_PRO_MMU_IA_INT_MAP_S)) +#define DPORT_PRO_MMU_IA_INT_MAP_V 0x1F +#define DPORT_PRO_MMU_IA_INT_MAP_S 0 + +#define DPORT_PRO_MPU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x210) +/* DPORT_PRO_MPU_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_MPU_IA_INT_MAP 0x0000001F +#define DPORT_PRO_MPU_IA_INT_MAP_M ((DPORT_PRO_MPU_IA_INT_MAP_V)<<(DPORT_PRO_MPU_IA_INT_MAP_S)) +#define DPORT_PRO_MPU_IA_INT_MAP_V 0x1F +#define DPORT_PRO_MPU_IA_INT_MAP_S 0 + +#define DPORT_PRO_CACHE_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x214) +/* DPORT_PRO_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_CACHE_IA_INT_MAP 0x0000001F +#define DPORT_PRO_CACHE_IA_INT_MAP_M ((DPORT_PRO_CACHE_IA_INT_MAP_V)<<(DPORT_PRO_CACHE_IA_INT_MAP_S)) +#define DPORT_PRO_CACHE_IA_INT_MAP_V 0x1F +#define DPORT_PRO_CACHE_IA_INT_MAP_S 0 + +#define DPORT_APP_MAC_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x218) +/* DPORT_APP_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_MAC_INTR_MAP 0x0000001F +#define DPORT_APP_MAC_INTR_MAP_M ((DPORT_APP_MAC_INTR_MAP_V)<<(DPORT_APP_MAC_INTR_MAP_S)) +#define DPORT_APP_MAC_INTR_MAP_V 0x1F +#define DPORT_APP_MAC_INTR_MAP_S 0 + +#define DPORT_APP_MAC_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x21C) +/* DPORT_APP_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_MAC_NMI_MAP 0x0000001F +#define DPORT_APP_MAC_NMI_MAP_M ((DPORT_APP_MAC_NMI_MAP_V)<<(DPORT_APP_MAC_NMI_MAP_S)) +#define DPORT_APP_MAC_NMI_MAP_V 0x1F +#define DPORT_APP_MAC_NMI_MAP_S 0 + +#define DPORT_APP_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x220) +/* DPORT_APP_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_BB_INT_MAP 0x0000001F +#define DPORT_APP_BB_INT_MAP_M ((DPORT_APP_BB_INT_MAP_V)<<(DPORT_APP_BB_INT_MAP_S)) +#define DPORT_APP_BB_INT_MAP_V 0x1F +#define DPORT_APP_BB_INT_MAP_S 0 + +#define DPORT_APP_BT_MAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x224) +/* DPORT_APP_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_BT_MAC_INT_MAP 0x0000001F +#define DPORT_APP_BT_MAC_INT_MAP_M ((DPORT_APP_BT_MAC_INT_MAP_V)<<(DPORT_APP_BT_MAC_INT_MAP_S)) +#define DPORT_APP_BT_MAC_INT_MAP_V 0x1F +#define DPORT_APP_BT_MAC_INT_MAP_S 0 + +#define DPORT_APP_BT_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x228) +/* DPORT_APP_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_BT_BB_INT_MAP 0x0000001F +#define DPORT_APP_BT_BB_INT_MAP_M ((DPORT_APP_BT_BB_INT_MAP_V)<<(DPORT_APP_BT_BB_INT_MAP_S)) +#define DPORT_APP_BT_BB_INT_MAP_V 0x1F +#define DPORT_APP_BT_BB_INT_MAP_S 0 + +#define DPORT_APP_BT_BB_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x22C) +/* DPORT_APP_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_BT_BB_NMI_MAP 0x0000001F +#define DPORT_APP_BT_BB_NMI_MAP_M ((DPORT_APP_BT_BB_NMI_MAP_V)<<(DPORT_APP_BT_BB_NMI_MAP_S)) +#define DPORT_APP_BT_BB_NMI_MAP_V 0x1F +#define DPORT_APP_BT_BB_NMI_MAP_S 0 + +#define DPORT_APP_RWBT_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x230) +/* DPORT_APP_RWBT_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_RWBT_IRQ_MAP 0x0000001F +#define DPORT_APP_RWBT_IRQ_MAP_M ((DPORT_APP_RWBT_IRQ_MAP_V)<<(DPORT_APP_RWBT_IRQ_MAP_S)) +#define DPORT_APP_RWBT_IRQ_MAP_V 0x1F +#define DPORT_APP_RWBT_IRQ_MAP_S 0 + +#define DPORT_APP_RWBLE_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x234) +/* DPORT_APP_RWBLE_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_RWBLE_IRQ_MAP 0x0000001F +#define DPORT_APP_RWBLE_IRQ_MAP_M ((DPORT_APP_RWBLE_IRQ_MAP_V)<<(DPORT_APP_RWBLE_IRQ_MAP_S)) +#define DPORT_APP_RWBLE_IRQ_MAP_V 0x1F +#define DPORT_APP_RWBLE_IRQ_MAP_S 0 + +#define DPORT_APP_RWBT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x238) +/* DPORT_APP_RWBT_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_RWBT_NMI_MAP 0x0000001F +#define DPORT_APP_RWBT_NMI_MAP_M ((DPORT_APP_RWBT_NMI_MAP_V)<<(DPORT_APP_RWBT_NMI_MAP_S)) +#define DPORT_APP_RWBT_NMI_MAP_V 0x1F +#define DPORT_APP_RWBT_NMI_MAP_S 0 + +#define DPORT_APP_RWBLE_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x23C) +/* DPORT_APP_RWBLE_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_RWBLE_NMI_MAP 0x0000001F +#define DPORT_APP_RWBLE_NMI_MAP_M ((DPORT_APP_RWBLE_NMI_MAP_V)<<(DPORT_APP_RWBLE_NMI_MAP_S)) +#define DPORT_APP_RWBLE_NMI_MAP_V 0x1F +#define DPORT_APP_RWBLE_NMI_MAP_S 0 + +#define DPORT_APP_SLC0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x240) +/* DPORT_APP_SLC0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_SLC0_INTR_MAP 0x0000001F +#define DPORT_APP_SLC0_INTR_MAP_M ((DPORT_APP_SLC0_INTR_MAP_V)<<(DPORT_APP_SLC0_INTR_MAP_S)) +#define DPORT_APP_SLC0_INTR_MAP_V 0x1F +#define DPORT_APP_SLC0_INTR_MAP_S 0 + +#define DPORT_APP_SLC1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x244) +/* DPORT_APP_SLC1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_SLC1_INTR_MAP 0x0000001F +#define DPORT_APP_SLC1_INTR_MAP_M ((DPORT_APP_SLC1_INTR_MAP_V)<<(DPORT_APP_SLC1_INTR_MAP_S)) +#define DPORT_APP_SLC1_INTR_MAP_V 0x1F +#define DPORT_APP_SLC1_INTR_MAP_S 0 + +#define DPORT_APP_UHCI0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x248) +/* DPORT_APP_UHCI0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_UHCI0_INTR_MAP 0x0000001F +#define DPORT_APP_UHCI0_INTR_MAP_M ((DPORT_APP_UHCI0_INTR_MAP_V)<<(DPORT_APP_UHCI0_INTR_MAP_S)) +#define DPORT_APP_UHCI0_INTR_MAP_V 0x1F +#define DPORT_APP_UHCI0_INTR_MAP_S 0 + +#define DPORT_APP_UHCI1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x24C) +/* DPORT_APP_UHCI1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_UHCI1_INTR_MAP 0x0000001F +#define DPORT_APP_UHCI1_INTR_MAP_M ((DPORT_APP_UHCI1_INTR_MAP_V)<<(DPORT_APP_UHCI1_INTR_MAP_S)) +#define DPORT_APP_UHCI1_INTR_MAP_V 0x1F +#define DPORT_APP_UHCI1_INTR_MAP_S 0 + +#define DPORT_APP_TG_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x250) +/* DPORT_APP_TG_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_TG_T0_LEVEL_INT_MAP 0x0000001F +#define DPORT_APP_TG_T0_LEVEL_INT_MAP_M ((DPORT_APP_TG_T0_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_T0_LEVEL_INT_MAP_S)) +#define DPORT_APP_TG_T0_LEVEL_INT_MAP_V 0x1F +#define DPORT_APP_TG_T0_LEVEL_INT_MAP_S 0 + +#define DPORT_APP_TG_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x254) +/* DPORT_APP_TG_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_TG_T1_LEVEL_INT_MAP 0x0000001F +#define DPORT_APP_TG_T1_LEVEL_INT_MAP_M ((DPORT_APP_TG_T1_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_T1_LEVEL_INT_MAP_S)) +#define DPORT_APP_TG_T1_LEVEL_INT_MAP_V 0x1F +#define DPORT_APP_TG_T1_LEVEL_INT_MAP_S 0 + +#define DPORT_APP_TG_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x258) +/* DPORT_APP_TG_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_TG_WDT_LEVEL_INT_MAP 0x0000001F +#define DPORT_APP_TG_WDT_LEVEL_INT_MAP_M ((DPORT_APP_TG_WDT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_WDT_LEVEL_INT_MAP_S)) +#define DPORT_APP_TG_WDT_LEVEL_INT_MAP_V 0x1F +#define DPORT_APP_TG_WDT_LEVEL_INT_MAP_S 0 + +#define DPORT_APP_TG_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x25C) +/* DPORT_APP_TG_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_TG_LACT_LEVEL_INT_MAP 0x0000001F +#define DPORT_APP_TG_LACT_LEVEL_INT_MAP_M ((DPORT_APP_TG_LACT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_LACT_LEVEL_INT_MAP_S)) +#define DPORT_APP_TG_LACT_LEVEL_INT_MAP_V 0x1F +#define DPORT_APP_TG_LACT_LEVEL_INT_MAP_S 0 + +#define DPORT_APP_TG1_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x260) +/* DPORT_APP_TG1_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_TG1_T0_LEVEL_INT_MAP 0x0000001F +#define DPORT_APP_TG1_T0_LEVEL_INT_MAP_M ((DPORT_APP_TG1_T0_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_T0_LEVEL_INT_MAP_S)) +#define DPORT_APP_TG1_T0_LEVEL_INT_MAP_V 0x1F +#define DPORT_APP_TG1_T0_LEVEL_INT_MAP_S 0 + +#define DPORT_APP_TG1_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x264) +/* DPORT_APP_TG1_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_TG1_T1_LEVEL_INT_MAP 0x0000001F +#define DPORT_APP_TG1_T1_LEVEL_INT_MAP_M ((DPORT_APP_TG1_T1_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_T1_LEVEL_INT_MAP_S)) +#define DPORT_APP_TG1_T1_LEVEL_INT_MAP_V 0x1F +#define DPORT_APP_TG1_T1_LEVEL_INT_MAP_S 0 + +#define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x268) +/* DPORT_APP_TG1_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_TG1_WDT_LEVEL_INT_MAP 0x0000001F +#define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_M ((DPORT_APP_TG1_WDT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_WDT_LEVEL_INT_MAP_S)) +#define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_V 0x1F +#define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_S 0 + +#define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x26C) +/* DPORT_APP_TG1_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_TG1_LACT_LEVEL_INT_MAP 0x0000001F +#define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_M ((DPORT_APP_TG1_LACT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_LACT_LEVEL_INT_MAP_S)) +#define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_V 0x1F +#define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_S 0 + +#define DPORT_APP_GPIO_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x270) +/* DPORT_APP_GPIO_INTERRUPT_APP_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_GPIO_INTERRUPT_APP_MAP 0x0000001F +#define DPORT_APP_GPIO_INTERRUPT_APP_MAP_M ((DPORT_APP_GPIO_INTERRUPT_APP_MAP_V)<<(DPORT_APP_GPIO_INTERRUPT_APP_MAP_S)) +#define DPORT_APP_GPIO_INTERRUPT_APP_MAP_V 0x1F +#define DPORT_APP_GPIO_INTERRUPT_APP_MAP_S 0 + +#define DPORT_APP_GPIO_INTERRUPT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x274) +/* DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP 0x0000001F +#define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_M ((DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_V)<<(DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_S)) +#define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_V 0x1F +#define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_S 0 + +#define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_DPORT_BASE + 0x278) +/* DPORT_APP_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP 0x0000001F +#define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_M ((DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_S)) +#define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_V 0x1F +#define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_S 0 + +#define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_DPORT_BASE + 0x27C) +/* DPORT_APP_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP 0x0000001F +#define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_M ((DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_S)) +#define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_V 0x1F +#define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_S 0 + +#define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_DPORT_BASE + 0x280) +/* DPORT_APP_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP 0x0000001F +#define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_M ((DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_S)) +#define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_V 0x1F +#define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_S 0 + +#define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_DPORT_BASE + 0x284) +/* DPORT_APP_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP 0x0000001F +#define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_M ((DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_S)) +#define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_V 0x1F +#define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_S 0 + +#define DPORT_APP_SPI_INTR_0_MAP_REG (DR_REG_DPORT_BASE + 0x288) +/* DPORT_APP_SPI_INTR_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_SPI_INTR_0_MAP 0x0000001F +#define DPORT_APP_SPI_INTR_0_MAP_M ((DPORT_APP_SPI_INTR_0_MAP_V)<<(DPORT_APP_SPI_INTR_0_MAP_S)) +#define DPORT_APP_SPI_INTR_0_MAP_V 0x1F +#define DPORT_APP_SPI_INTR_0_MAP_S 0 + +#define DPORT_APP_SPI_INTR_1_MAP_REG (DR_REG_DPORT_BASE + 0x28C) +/* DPORT_APP_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_SPI_INTR_1_MAP 0x0000001F +#define DPORT_APP_SPI_INTR_1_MAP_M ((DPORT_APP_SPI_INTR_1_MAP_V)<<(DPORT_APP_SPI_INTR_1_MAP_S)) +#define DPORT_APP_SPI_INTR_1_MAP_V 0x1F +#define DPORT_APP_SPI_INTR_1_MAP_S 0 + +#define DPORT_APP_SPI_INTR_2_MAP_REG (DR_REG_DPORT_BASE + 0x290) +/* DPORT_APP_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_SPI_INTR_2_MAP 0x0000001F +#define DPORT_APP_SPI_INTR_2_MAP_M ((DPORT_APP_SPI_INTR_2_MAP_V)<<(DPORT_APP_SPI_INTR_2_MAP_S)) +#define DPORT_APP_SPI_INTR_2_MAP_V 0x1F +#define DPORT_APP_SPI_INTR_2_MAP_S 0 + +#define DPORT_APP_SPI_INTR_3_MAP_REG (DR_REG_DPORT_BASE + 0x294) +/* DPORT_APP_SPI_INTR_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_SPI_INTR_3_MAP 0x0000001F +#define DPORT_APP_SPI_INTR_3_MAP_M ((DPORT_APP_SPI_INTR_3_MAP_V)<<(DPORT_APP_SPI_INTR_3_MAP_S)) +#define DPORT_APP_SPI_INTR_3_MAP_V 0x1F +#define DPORT_APP_SPI_INTR_3_MAP_S 0 + +#define DPORT_APP_I2S0_INT_MAP_REG (DR_REG_DPORT_BASE + 0x298) +/* DPORT_APP_I2S0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_I2S0_INT_MAP 0x0000001F +#define DPORT_APP_I2S0_INT_MAP_M ((DPORT_APP_I2S0_INT_MAP_V)<<(DPORT_APP_I2S0_INT_MAP_S)) +#define DPORT_APP_I2S0_INT_MAP_V 0x1F +#define DPORT_APP_I2S0_INT_MAP_S 0 + +#define DPORT_APP_I2S1_INT_MAP_REG (DR_REG_DPORT_BASE + 0x29C) +/* DPORT_APP_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_I2S1_INT_MAP 0x0000001F +#define DPORT_APP_I2S1_INT_MAP_M ((DPORT_APP_I2S1_INT_MAP_V)<<(DPORT_APP_I2S1_INT_MAP_S)) +#define DPORT_APP_I2S1_INT_MAP_V 0x1F +#define DPORT_APP_I2S1_INT_MAP_S 0 + +#define DPORT_APP_UART_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2A0) +/* DPORT_APP_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_UART_INTR_MAP 0x0000001F +#define DPORT_APP_UART_INTR_MAP_M ((DPORT_APP_UART_INTR_MAP_V)<<(DPORT_APP_UART_INTR_MAP_S)) +#define DPORT_APP_UART_INTR_MAP_V 0x1F +#define DPORT_APP_UART_INTR_MAP_S 0 + +#define DPORT_APP_UART1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2A4) +/* DPORT_APP_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_UART1_INTR_MAP 0x0000001F +#define DPORT_APP_UART1_INTR_MAP_M ((DPORT_APP_UART1_INTR_MAP_V)<<(DPORT_APP_UART1_INTR_MAP_S)) +#define DPORT_APP_UART1_INTR_MAP_V 0x1F +#define DPORT_APP_UART1_INTR_MAP_S 0 + +#define DPORT_APP_UART2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2A8) +/* DPORT_APP_UART2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_UART2_INTR_MAP 0x0000001F +#define DPORT_APP_UART2_INTR_MAP_M ((DPORT_APP_UART2_INTR_MAP_V)<<(DPORT_APP_UART2_INTR_MAP_S)) +#define DPORT_APP_UART2_INTR_MAP_V 0x1F +#define DPORT_APP_UART2_INTR_MAP_S 0 + +#define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x2AC) +/* DPORT_APP_SDIO_HOST_INTERRUPT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_SDIO_HOST_INTERRUPT_MAP 0x0000001F +#define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_M ((DPORT_APP_SDIO_HOST_INTERRUPT_MAP_V)<<(DPORT_APP_SDIO_HOST_INTERRUPT_MAP_S)) +#define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_V 0x1F +#define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_S 0 + +#define DPORT_APP_EMAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2B0) +/* DPORT_APP_EMAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_EMAC_INT_MAP 0x0000001F +#define DPORT_APP_EMAC_INT_MAP_M ((DPORT_APP_EMAC_INT_MAP_V)<<(DPORT_APP_EMAC_INT_MAP_S)) +#define DPORT_APP_EMAC_INT_MAP_V 0x1F +#define DPORT_APP_EMAC_INT_MAP_S 0 + +#define DPORT_APP_PWM0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2B4) +/* DPORT_APP_PWM0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_PWM0_INTR_MAP 0x0000001F +#define DPORT_APP_PWM0_INTR_MAP_M ((DPORT_APP_PWM0_INTR_MAP_V)<<(DPORT_APP_PWM0_INTR_MAP_S)) +#define DPORT_APP_PWM0_INTR_MAP_V 0x1F +#define DPORT_APP_PWM0_INTR_MAP_S 0 + +#define DPORT_APP_PWM1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2B8) +/* DPORT_APP_PWM1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_PWM1_INTR_MAP 0x0000001F +#define DPORT_APP_PWM1_INTR_MAP_M ((DPORT_APP_PWM1_INTR_MAP_V)<<(DPORT_APP_PWM1_INTR_MAP_S)) +#define DPORT_APP_PWM1_INTR_MAP_V 0x1F +#define DPORT_APP_PWM1_INTR_MAP_S 0 + +#define DPORT_APP_PWM2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2BC) +/* DPORT_APP_PWM2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_PWM2_INTR_MAP 0x0000001F +#define DPORT_APP_PWM2_INTR_MAP_M ((DPORT_APP_PWM2_INTR_MAP_V)<<(DPORT_APP_PWM2_INTR_MAP_S)) +#define DPORT_APP_PWM2_INTR_MAP_V 0x1F +#define DPORT_APP_PWM2_INTR_MAP_S 0 + +#define DPORT_APP_PWM3_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2C0) +/* DPORT_APP_PWM3_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_PWM3_INTR_MAP 0x0000001F +#define DPORT_APP_PWM3_INTR_MAP_M ((DPORT_APP_PWM3_INTR_MAP_V)<<(DPORT_APP_PWM3_INTR_MAP_S)) +#define DPORT_APP_PWM3_INTR_MAP_V 0x1F +#define DPORT_APP_PWM3_INTR_MAP_S 0 + +#define DPORT_APP_LEDC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2C4) +/* DPORT_APP_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_LEDC_INT_MAP 0x0000001F +#define DPORT_APP_LEDC_INT_MAP_M ((DPORT_APP_LEDC_INT_MAP_V)<<(DPORT_APP_LEDC_INT_MAP_S)) +#define DPORT_APP_LEDC_INT_MAP_V 0x1F +#define DPORT_APP_LEDC_INT_MAP_S 0 + +#define DPORT_APP_EFUSE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2C8) +/* DPORT_APP_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_EFUSE_INT_MAP 0x0000001F +#define DPORT_APP_EFUSE_INT_MAP_M ((DPORT_APP_EFUSE_INT_MAP_V)<<(DPORT_APP_EFUSE_INT_MAP_S)) +#define DPORT_APP_EFUSE_INT_MAP_V 0x1F +#define DPORT_APP_EFUSE_INT_MAP_S 0 + +#define DPORT_APP_CAN_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2CC) +/* DPORT_APP_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_CAN_INT_MAP 0x0000001F +#define DPORT_APP_CAN_INT_MAP_M ((DPORT_APP_CAN_INT_MAP_V)<<(DPORT_APP_CAN_INT_MAP_S)) +#define DPORT_APP_CAN_INT_MAP_V 0x1F +#define DPORT_APP_CAN_INT_MAP_S 0 + +#define DPORT_APP_RTC_CORE_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2D0) +/* DPORT_APP_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_RTC_CORE_INTR_MAP 0x0000001F +#define DPORT_APP_RTC_CORE_INTR_MAP_M ((DPORT_APP_RTC_CORE_INTR_MAP_V)<<(DPORT_APP_RTC_CORE_INTR_MAP_S)) +#define DPORT_APP_RTC_CORE_INTR_MAP_V 0x1F +#define DPORT_APP_RTC_CORE_INTR_MAP_S 0 + +#define DPORT_APP_RMT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2D4) +/* DPORT_APP_RMT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_RMT_INTR_MAP 0x0000001F +#define DPORT_APP_RMT_INTR_MAP_M ((DPORT_APP_RMT_INTR_MAP_V)<<(DPORT_APP_RMT_INTR_MAP_S)) +#define DPORT_APP_RMT_INTR_MAP_V 0x1F +#define DPORT_APP_RMT_INTR_MAP_S 0 + +#define DPORT_APP_PCNT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2D8) +/* DPORT_APP_PCNT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_PCNT_INTR_MAP 0x0000001F +#define DPORT_APP_PCNT_INTR_MAP_M ((DPORT_APP_PCNT_INTR_MAP_V)<<(DPORT_APP_PCNT_INTR_MAP_S)) +#define DPORT_APP_PCNT_INTR_MAP_V 0x1F +#define DPORT_APP_PCNT_INTR_MAP_S 0 + +#define DPORT_APP_I2C_EXT0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2DC) +/* DPORT_APP_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_I2C_EXT0_INTR_MAP 0x0000001F +#define DPORT_APP_I2C_EXT0_INTR_MAP_M ((DPORT_APP_I2C_EXT0_INTR_MAP_V)<<(DPORT_APP_I2C_EXT0_INTR_MAP_S)) +#define DPORT_APP_I2C_EXT0_INTR_MAP_V 0x1F +#define DPORT_APP_I2C_EXT0_INTR_MAP_S 0 + +#define DPORT_APP_I2C_EXT1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2E0) +/* DPORT_APP_I2C_EXT1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_I2C_EXT1_INTR_MAP 0x0000001F +#define DPORT_APP_I2C_EXT1_INTR_MAP_M ((DPORT_APP_I2C_EXT1_INTR_MAP_V)<<(DPORT_APP_I2C_EXT1_INTR_MAP_S)) +#define DPORT_APP_I2C_EXT1_INTR_MAP_V 0x1F +#define DPORT_APP_I2C_EXT1_INTR_MAP_S 0 + +#define DPORT_APP_RSA_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2E4) +/* DPORT_APP_RSA_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_RSA_INTR_MAP 0x0000001F +#define DPORT_APP_RSA_INTR_MAP_M ((DPORT_APP_RSA_INTR_MAP_V)<<(DPORT_APP_RSA_INTR_MAP_S)) +#define DPORT_APP_RSA_INTR_MAP_V 0x1F +#define DPORT_APP_RSA_INTR_MAP_S 0 + +#define DPORT_APP_SPI1_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2E8) +/* DPORT_APP_SPI1_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_SPI1_DMA_INT_MAP 0x0000001F +#define DPORT_APP_SPI1_DMA_INT_MAP_M ((DPORT_APP_SPI1_DMA_INT_MAP_V)<<(DPORT_APP_SPI1_DMA_INT_MAP_S)) +#define DPORT_APP_SPI1_DMA_INT_MAP_V 0x1F +#define DPORT_APP_SPI1_DMA_INT_MAP_S 0 + +#define DPORT_APP_SPI2_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2EC) +/* DPORT_APP_SPI2_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_SPI2_DMA_INT_MAP 0x0000001F +#define DPORT_APP_SPI2_DMA_INT_MAP_M ((DPORT_APP_SPI2_DMA_INT_MAP_V)<<(DPORT_APP_SPI2_DMA_INT_MAP_S)) +#define DPORT_APP_SPI2_DMA_INT_MAP_V 0x1F +#define DPORT_APP_SPI2_DMA_INT_MAP_S 0 + +#define DPORT_APP_SPI3_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2F0) +/* DPORT_APP_SPI3_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_SPI3_DMA_INT_MAP 0x0000001F +#define DPORT_APP_SPI3_DMA_INT_MAP_M ((DPORT_APP_SPI3_DMA_INT_MAP_V)<<(DPORT_APP_SPI3_DMA_INT_MAP_S)) +#define DPORT_APP_SPI3_DMA_INT_MAP_V 0x1F +#define DPORT_APP_SPI3_DMA_INT_MAP_S 0 + +#define DPORT_APP_WDG_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2F4) +/* DPORT_APP_WDG_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_WDG_INT_MAP 0x0000001F +#define DPORT_APP_WDG_INT_MAP_M ((DPORT_APP_WDG_INT_MAP_V)<<(DPORT_APP_WDG_INT_MAP_S)) +#define DPORT_APP_WDG_INT_MAP_V 0x1F +#define DPORT_APP_WDG_INT_MAP_S 0 + +#define DPORT_APP_TIMER_INT1_MAP_REG (DR_REG_DPORT_BASE + 0x2F8) +/* DPORT_APP_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_TIMER_INT1_MAP 0x0000001F +#define DPORT_APP_TIMER_INT1_MAP_M ((DPORT_APP_TIMER_INT1_MAP_V)<<(DPORT_APP_TIMER_INT1_MAP_S)) +#define DPORT_APP_TIMER_INT1_MAP_V 0x1F +#define DPORT_APP_TIMER_INT1_MAP_S 0 + +#define DPORT_APP_TIMER_INT2_MAP_REG (DR_REG_DPORT_BASE + 0x2FC) +/* DPORT_APP_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_TIMER_INT2_MAP 0x0000001F +#define DPORT_APP_TIMER_INT2_MAP_M ((DPORT_APP_TIMER_INT2_MAP_V)<<(DPORT_APP_TIMER_INT2_MAP_S)) +#define DPORT_APP_TIMER_INT2_MAP_V 0x1F +#define DPORT_APP_TIMER_INT2_MAP_S 0 + +#define DPORT_APP_TG_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x300) +/* DPORT_APP_TG_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_TG_T0_EDGE_INT_MAP 0x0000001F +#define DPORT_APP_TG_T0_EDGE_INT_MAP_M ((DPORT_APP_TG_T0_EDGE_INT_MAP_V)<<(DPORT_APP_TG_T0_EDGE_INT_MAP_S)) +#define DPORT_APP_TG_T0_EDGE_INT_MAP_V 0x1F +#define DPORT_APP_TG_T0_EDGE_INT_MAP_S 0 + +#define DPORT_APP_TG_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x304) +/* DPORT_APP_TG_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_TG_T1_EDGE_INT_MAP 0x0000001F +#define DPORT_APP_TG_T1_EDGE_INT_MAP_M ((DPORT_APP_TG_T1_EDGE_INT_MAP_V)<<(DPORT_APP_TG_T1_EDGE_INT_MAP_S)) +#define DPORT_APP_TG_T1_EDGE_INT_MAP_V 0x1F +#define DPORT_APP_TG_T1_EDGE_INT_MAP_S 0 + +#define DPORT_APP_TG_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x308) +/* DPORT_APP_TG_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_TG_WDT_EDGE_INT_MAP 0x0000001F +#define DPORT_APP_TG_WDT_EDGE_INT_MAP_M ((DPORT_APP_TG_WDT_EDGE_INT_MAP_V)<<(DPORT_APP_TG_WDT_EDGE_INT_MAP_S)) +#define DPORT_APP_TG_WDT_EDGE_INT_MAP_V 0x1F +#define DPORT_APP_TG_WDT_EDGE_INT_MAP_S 0 + +#define DPORT_APP_TG_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x30C) +/* DPORT_APP_TG_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_TG_LACT_EDGE_INT_MAP 0x0000001F +#define DPORT_APP_TG_LACT_EDGE_INT_MAP_M ((DPORT_APP_TG_LACT_EDGE_INT_MAP_V)<<(DPORT_APP_TG_LACT_EDGE_INT_MAP_S)) +#define DPORT_APP_TG_LACT_EDGE_INT_MAP_V 0x1F +#define DPORT_APP_TG_LACT_EDGE_INT_MAP_S 0 + +#define DPORT_APP_TG1_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x310) +/* DPORT_APP_TG1_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_TG1_T0_EDGE_INT_MAP 0x0000001F +#define DPORT_APP_TG1_T0_EDGE_INT_MAP_M ((DPORT_APP_TG1_T0_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_T0_EDGE_INT_MAP_S)) +#define DPORT_APP_TG1_T0_EDGE_INT_MAP_V 0x1F +#define DPORT_APP_TG1_T0_EDGE_INT_MAP_S 0 + +#define DPORT_APP_TG1_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x314) +/* DPORT_APP_TG1_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_TG1_T1_EDGE_INT_MAP 0x0000001F +#define DPORT_APP_TG1_T1_EDGE_INT_MAP_M ((DPORT_APP_TG1_T1_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_T1_EDGE_INT_MAP_S)) +#define DPORT_APP_TG1_T1_EDGE_INT_MAP_V 0x1F +#define DPORT_APP_TG1_T1_EDGE_INT_MAP_S 0 + +#define DPORT_APP_TG1_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x318) +/* DPORT_APP_TG1_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_TG1_WDT_EDGE_INT_MAP 0x0000001F +#define DPORT_APP_TG1_WDT_EDGE_INT_MAP_M ((DPORT_APP_TG1_WDT_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_WDT_EDGE_INT_MAP_S)) +#define DPORT_APP_TG1_WDT_EDGE_INT_MAP_V 0x1F +#define DPORT_APP_TG1_WDT_EDGE_INT_MAP_S 0 + +#define DPORT_APP_TG1_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x31C) +/* DPORT_APP_TG1_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_TG1_LACT_EDGE_INT_MAP 0x0000001F +#define DPORT_APP_TG1_LACT_EDGE_INT_MAP_M ((DPORT_APP_TG1_LACT_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_LACT_EDGE_INT_MAP_S)) +#define DPORT_APP_TG1_LACT_EDGE_INT_MAP_V 0x1F +#define DPORT_APP_TG1_LACT_EDGE_INT_MAP_S 0 + +#define DPORT_APP_MMU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x320) +/* DPORT_APP_MMU_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_MMU_IA_INT_MAP 0x0000001F +#define DPORT_APP_MMU_IA_INT_MAP_M ((DPORT_APP_MMU_IA_INT_MAP_V)<<(DPORT_APP_MMU_IA_INT_MAP_S)) +#define DPORT_APP_MMU_IA_INT_MAP_V 0x1F +#define DPORT_APP_MMU_IA_INT_MAP_S 0 + +#define DPORT_APP_MPU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x324) +/* DPORT_APP_MPU_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_MPU_IA_INT_MAP 0x0000001F +#define DPORT_APP_MPU_IA_INT_MAP_M ((DPORT_APP_MPU_IA_INT_MAP_V)<<(DPORT_APP_MPU_IA_INT_MAP_S)) +#define DPORT_APP_MPU_IA_INT_MAP_V 0x1F +#define DPORT_APP_MPU_IA_INT_MAP_S 0 + +#define DPORT_APP_CACHE_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x328) +/* DPORT_APP_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_APP_CACHE_IA_INT_MAP 0x0000001F +#define DPORT_APP_CACHE_IA_INT_MAP_M ((DPORT_APP_CACHE_IA_INT_MAP_V)<<(DPORT_APP_CACHE_IA_INT_MAP_S)) +#define DPORT_APP_CACHE_IA_INT_MAP_V 0x1F +#define DPORT_APP_CACHE_IA_INT_MAP_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_UART_REG (DR_REG_DPORT_BASE + 0x32C) +/* DPORT_UART_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_UART_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_UART_ACCESS_GRANT_CONFIG_M ((DPORT_UART_ACCESS_GRANT_CONFIG_V)<<(DPORT_UART_ACCESS_GRANT_CONFIG_S)) +#define DPORT_UART_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_UART_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_SPI1_REG (DR_REG_DPORT_BASE + 0x330) +/* DPORT_SPI1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_SPI1_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_SPI1_ACCESS_GRANT_CONFIG_M ((DPORT_SPI1_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI1_ACCESS_GRANT_CONFIG_S)) +#define DPORT_SPI1_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_SPI1_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_SPI0_REG (DR_REG_DPORT_BASE + 0x334) +/* DPORT_SPI0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_SPI0_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_SPI0_ACCESS_GRANT_CONFIG_M ((DPORT_SPI0_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI0_ACCESS_GRANT_CONFIG_S)) +#define DPORT_SPI0_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_SPI0_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_GPIO_REG (DR_REG_DPORT_BASE + 0x338) +/* DPORT_GPIO_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_GPIO_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_GPIO_ACCESS_GRANT_CONFIG_M ((DPORT_GPIO_ACCESS_GRANT_CONFIG_V)<<(DPORT_GPIO_ACCESS_GRANT_CONFIG_S)) +#define DPORT_GPIO_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_GPIO_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_FE2_REG (DR_REG_DPORT_BASE + 0x33C) +/* DPORT_FE2_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_FE2_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_FE2_ACCESS_GRANT_CONFIG_M ((DPORT_FE2_ACCESS_GRANT_CONFIG_V)<<(DPORT_FE2_ACCESS_GRANT_CONFIG_S)) +#define DPORT_FE2_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_FE2_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_FE_REG (DR_REG_DPORT_BASE + 0x340) +/* DPORT_FE_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_FE_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_FE_ACCESS_GRANT_CONFIG_M ((DPORT_FE_ACCESS_GRANT_CONFIG_V)<<(DPORT_FE_ACCESS_GRANT_CONFIG_S)) +#define DPORT_FE_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_FE_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_TIMER_REG (DR_REG_DPORT_BASE + 0x344) +/* DPORT_TIMER_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_TIMER_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_TIMER_ACCESS_GRANT_CONFIG_M ((DPORT_TIMER_ACCESS_GRANT_CONFIG_V)<<(DPORT_TIMER_ACCESS_GRANT_CONFIG_S)) +#define DPORT_TIMER_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_TIMER_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_RTC_REG (DR_REG_DPORT_BASE + 0x348) +/* DPORT_RTC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_RTC_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_RTC_ACCESS_GRANT_CONFIG_M ((DPORT_RTC_ACCESS_GRANT_CONFIG_V)<<(DPORT_RTC_ACCESS_GRANT_CONFIG_S)) +#define DPORT_RTC_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_RTC_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_IO_MUX_REG (DR_REG_DPORT_BASE + 0x34C) +/* DPORT_IOMUX_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_IOMUX_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_IOMUX_ACCESS_GRANT_CONFIG_M ((DPORT_IOMUX_ACCESS_GRANT_CONFIG_V)<<(DPORT_IOMUX_ACCESS_GRANT_CONFIG_S)) +#define DPORT_IOMUX_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_IOMUX_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_WDG_REG (DR_REG_DPORT_BASE + 0x350) +/* DPORT_WDG_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_WDG_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_WDG_ACCESS_GRANT_CONFIG_M ((DPORT_WDG_ACCESS_GRANT_CONFIG_V)<<(DPORT_WDG_ACCESS_GRANT_CONFIG_S)) +#define DPORT_WDG_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_WDG_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_HINF_REG (DR_REG_DPORT_BASE + 0x354) +/* DPORT_HINF_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_HINF_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_HINF_ACCESS_GRANT_CONFIG_M ((DPORT_HINF_ACCESS_GRANT_CONFIG_V)<<(DPORT_HINF_ACCESS_GRANT_CONFIG_S)) +#define DPORT_HINF_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_HINF_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_UHCI1_REG (DR_REG_DPORT_BASE + 0x358) +/* DPORT_UHCI1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_UHCI1_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_UHCI1_ACCESS_GRANT_CONFIG_M ((DPORT_UHCI1_ACCESS_GRANT_CONFIG_V)<<(DPORT_UHCI1_ACCESS_GRANT_CONFIG_S)) +#define DPORT_UHCI1_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_UHCI1_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_MISC_REG (DR_REG_DPORT_BASE + 0x35C) +/* DPORT_MISC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_MISC_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_MISC_ACCESS_GRANT_CONFIG_M ((DPORT_MISC_ACCESS_GRANT_CONFIG_V)<<(DPORT_MISC_ACCESS_GRANT_CONFIG_S)) +#define DPORT_MISC_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_MISC_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_I2C_REG (DR_REG_DPORT_BASE + 0x360) +/* DPORT_I2C_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_I2C_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_I2C_ACCESS_GRANT_CONFIG_M ((DPORT_I2C_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2C_ACCESS_GRANT_CONFIG_S)) +#define DPORT_I2C_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_I2C_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_I2S0_REG (DR_REG_DPORT_BASE + 0x364) +/* DPORT_I2S0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_I2S0_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_I2S0_ACCESS_GRANT_CONFIG_M ((DPORT_I2S0_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2S0_ACCESS_GRANT_CONFIG_S)) +#define DPORT_I2S0_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_I2S0_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_UART1_REG (DR_REG_DPORT_BASE + 0x368) +/* DPORT_UART1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_UART1_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_UART1_ACCESS_GRANT_CONFIG_M ((DPORT_UART1_ACCESS_GRANT_CONFIG_V)<<(DPORT_UART1_ACCESS_GRANT_CONFIG_S)) +#define DPORT_UART1_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_UART1_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_BT_REG (DR_REG_DPORT_BASE + 0x36C) +/* DPORT_BT_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_BT_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_BT_ACCESS_GRANT_CONFIG_M ((DPORT_BT_ACCESS_GRANT_CONFIG_V)<<(DPORT_BT_ACCESS_GRANT_CONFIG_S)) +#define DPORT_BT_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_BT_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_BT_BUFFER_REG (DR_REG_DPORT_BASE + 0x370) +/* DPORT_BTBUFFER_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_M ((DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_V)<<(DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_S)) +#define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_I2C_EXT0_REG (DR_REG_DPORT_BASE + 0x374) +/* DPORT_I2CEXT0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_M ((DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_S)) +#define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_UHCI0_REG (DR_REG_DPORT_BASE + 0x378) +/* DPORT_UHCI0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_UHCI0_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_UHCI0_ACCESS_GRANT_CONFIG_M ((DPORT_UHCI0_ACCESS_GRANT_CONFIG_V)<<(DPORT_UHCI0_ACCESS_GRANT_CONFIG_S)) +#define DPORT_UHCI0_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_UHCI0_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_SLCHOST_REG (DR_REG_DPORT_BASE + 0x37C) +/* DPORT_SLCHOST_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_SLCHOST_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_SLCHOST_ACCESS_GRANT_CONFIG_M ((DPORT_SLCHOST_ACCESS_GRANT_CONFIG_V)<<(DPORT_SLCHOST_ACCESS_GRANT_CONFIG_S)) +#define DPORT_SLCHOST_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_SLCHOST_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_RMT_REG (DR_REG_DPORT_BASE + 0x380) +/* DPORT_RMT_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_RMT_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_RMT_ACCESS_GRANT_CONFIG_M ((DPORT_RMT_ACCESS_GRANT_CONFIG_V)<<(DPORT_RMT_ACCESS_GRANT_CONFIG_S)) +#define DPORT_RMT_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_RMT_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_PCNT_REG (DR_REG_DPORT_BASE + 0x384) +/* DPORT_PCNT_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_PCNT_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_PCNT_ACCESS_GRANT_CONFIG_M ((DPORT_PCNT_ACCESS_GRANT_CONFIG_V)<<(DPORT_PCNT_ACCESS_GRANT_CONFIG_S)) +#define DPORT_PCNT_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_PCNT_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_SLC_REG (DR_REG_DPORT_BASE + 0x388) +/* DPORT_SLC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_SLC_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_SLC_ACCESS_GRANT_CONFIG_M ((DPORT_SLC_ACCESS_GRANT_CONFIG_V)<<(DPORT_SLC_ACCESS_GRANT_CONFIG_S)) +#define DPORT_SLC_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_SLC_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_LEDC_REG (DR_REG_DPORT_BASE + 0x38C) +/* DPORT_LEDC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_LEDC_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_LEDC_ACCESS_GRANT_CONFIG_M ((DPORT_LEDC_ACCESS_GRANT_CONFIG_V)<<(DPORT_LEDC_ACCESS_GRANT_CONFIG_S)) +#define DPORT_LEDC_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_LEDC_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_EFUSE_REG (DR_REG_DPORT_BASE + 0x390) +/* DPORT_EFUSE_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_EFUSE_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_EFUSE_ACCESS_GRANT_CONFIG_M ((DPORT_EFUSE_ACCESS_GRANT_CONFIG_V)<<(DPORT_EFUSE_ACCESS_GRANT_CONFIG_S)) +#define DPORT_EFUSE_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_EFUSE_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG (DR_REG_DPORT_BASE + 0x394) +/* DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_M ((DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_S)) +#define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_BB_REG (DR_REG_DPORT_BASE + 0x398) +/* DPORT_BB_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_BB_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_BB_ACCESS_GRANT_CONFIG_M ((DPORT_BB_ACCESS_GRANT_CONFIG_V)<<(DPORT_BB_ACCESS_GRANT_CONFIG_S)) +#define DPORT_BB_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_BB_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_PWM0_REG (DR_REG_DPORT_BASE + 0x39C) +/* DPORT_PWM0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_PWM0_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_PWM0_ACCESS_GRANT_CONFIG_M ((DPORT_PWM0_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM0_ACCESS_GRANT_CONFIG_S)) +#define DPORT_PWM0_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_PWM0_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG (DR_REG_DPORT_BASE + 0x3A0) +/* DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_M ((DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_V)<<(DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_S)) +#define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG (DR_REG_DPORT_BASE + 0x3A4) +/* DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_M ((DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_V)<<(DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_S)) +#define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_SPI2_REG (DR_REG_DPORT_BASE + 0x3A8) +/* DPORT_SPI2_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_SPI2_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_SPI2_ACCESS_GRANT_CONFIG_M ((DPORT_SPI2_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI2_ACCESS_GRANT_CONFIG_S)) +#define DPORT_SPI2_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_SPI2_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_SPI3_REG (DR_REG_DPORT_BASE + 0x3AC) +/* DPORT_SPI3_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_SPI3_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_SPI3_ACCESS_GRANT_CONFIG_M ((DPORT_SPI3_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI3_ACCESS_GRANT_CONFIG_S)) +#define DPORT_SPI3_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_SPI3_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_APB_CTRL_REG (DR_REG_DPORT_BASE + 0x3B0) +/* DPORT_APBCTRL_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_APBCTRL_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_APBCTRL_ACCESS_GRANT_CONFIG_M ((DPORT_APBCTRL_ACCESS_GRANT_CONFIG_V)<<(DPORT_APBCTRL_ACCESS_GRANT_CONFIG_S)) +#define DPORT_APBCTRL_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_APBCTRL_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_I2C_EXT1_REG (DR_REG_DPORT_BASE + 0x3B4) +/* DPORT_I2CEXT1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_M ((DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_S)) +#define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_SDIO_HOST_REG (DR_REG_DPORT_BASE + 0x3B8) +/* DPORT_SDIOHOST_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_M ((DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_V)<<(DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_S)) +#define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_EMAC_REG (DR_REG_DPORT_BASE + 0x3BC) +/* DPORT_EMAC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_EMAC_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_EMAC_ACCESS_GRANT_CONFIG_M ((DPORT_EMAC_ACCESS_GRANT_CONFIG_V)<<(DPORT_EMAC_ACCESS_GRANT_CONFIG_S)) +#define DPORT_EMAC_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_EMAC_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_CAN_REG (DR_REG_DPORT_BASE + 0x3C0) +/* DPORT_CAN_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_CAN_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_CAN_ACCESS_GRANT_CONFIG_M ((DPORT_CAN_ACCESS_GRANT_CONFIG_V)<<(DPORT_CAN_ACCESS_GRANT_CONFIG_S)) +#define DPORT_CAN_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_CAN_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_PWM1_REG (DR_REG_DPORT_BASE + 0x3C4) +/* DPORT_PWM1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_PWM1_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_PWM1_ACCESS_GRANT_CONFIG_M ((DPORT_PWM1_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM1_ACCESS_GRANT_CONFIG_S)) +#define DPORT_PWM1_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_PWM1_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_I2S1_REG (DR_REG_DPORT_BASE + 0x3C8) +/* DPORT_I2S1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_I2S1_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_I2S1_ACCESS_GRANT_CONFIG_M ((DPORT_I2S1_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2S1_ACCESS_GRANT_CONFIG_S)) +#define DPORT_I2S1_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_I2S1_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_UART2_REG (DR_REG_DPORT_BASE + 0x3CC) +/* DPORT_UART2_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_UART2_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_UART2_ACCESS_GRANT_CONFIG_M ((DPORT_UART2_ACCESS_GRANT_CONFIG_V)<<(DPORT_UART2_ACCESS_GRANT_CONFIG_S)) +#define DPORT_UART2_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_UART2_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_PWM2_REG (DR_REG_DPORT_BASE + 0x3D0) +/* DPORT_PWM2_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_PWM2_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_PWM2_ACCESS_GRANT_CONFIG_M ((DPORT_PWM2_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM2_ACCESS_GRANT_CONFIG_S)) +#define DPORT_PWM2_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_PWM2_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_PWM3_REG (DR_REG_DPORT_BASE + 0x3D4) +/* DPORT_PWM3_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_PWM3_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_PWM3_ACCESS_GRANT_CONFIG_M ((DPORT_PWM3_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM3_ACCESS_GRANT_CONFIG_S)) +#define DPORT_PWM3_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_PWM3_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_RWBT_REG (DR_REG_DPORT_BASE + 0x3D8) +/* DPORT_RWBT_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_RWBT_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_RWBT_ACCESS_GRANT_CONFIG_M ((DPORT_RWBT_ACCESS_GRANT_CONFIG_V)<<(DPORT_RWBT_ACCESS_GRANT_CONFIG_S)) +#define DPORT_RWBT_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_RWBT_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_BTMAC_REG (DR_REG_DPORT_BASE + 0x3DC) +/* DPORT_BTMAC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_BTMAC_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_BTMAC_ACCESS_GRANT_CONFIG_M ((DPORT_BTMAC_ACCESS_GRANT_CONFIG_V)<<(DPORT_BTMAC_ACCESS_GRANT_CONFIG_S)) +#define DPORT_BTMAC_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_BTMAC_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_WIFIMAC_REG (DR_REG_DPORT_BASE + 0x3E0) +/* DPORT_WIFIMAC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_M ((DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_V)<<(DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_S)) +#define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_PWR_REG (DR_REG_DPORT_BASE + 0x3E4) +/* DPORT_PWR_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_PWR_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_PWR_ACCESS_GRANT_CONFIG_M ((DPORT_PWR_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWR_ACCESS_GRANT_CONFIG_S)) +#define DPORT_PWR_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_PWR_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_MEM_ACCESS_DBUG0_REG (DR_REG_DPORT_BASE + 0x3E8) +/* DPORT_INTERNAL_SRAM_MMU_MULTI_HIT : RO ;bitpos:[29:26] ;default: 4'b0 ; */ +/*description: */ +#define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT 0x0000000F +#define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_M ((DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_V)<<(DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_S)) +#define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_V 0xF +#define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_S 26 +/* DPORT_INTERNAL_SRAM_IA : RO ;bitpos:[25:14] ;default: 12'b0 ; */ +/*description: */ +#define DPORT_INTERNAL_SRAM_IA 0x00000FFF +#define DPORT_INTERNAL_SRAM_IA_M ((DPORT_INTERNAL_SRAM_IA_V)<<(DPORT_INTERNAL_SRAM_IA_S)) +#define DPORT_INTERNAL_SRAM_IA_V 0xFFF +#define DPORT_INTERNAL_SRAM_IA_S 14 +/* DPORT_INTERNAL_SRAM_MMU_AD : RO ;bitpos:[13:10] ;default: 4'b0 ; */ +/*description: */ +#define DPORT_INTERNAL_SRAM_MMU_AD 0x0000000F +#define DPORT_INTERNAL_SRAM_MMU_AD_M ((DPORT_INTERNAL_SRAM_MMU_AD_V)<<(DPORT_INTERNAL_SRAM_MMU_AD_S)) +#define DPORT_INTERNAL_SRAM_MMU_AD_V 0xF +#define DPORT_INTERNAL_SRAM_MMU_AD_S 10 +/* DPORT_SHARE_ROM_IA : RO ;bitpos:[9:6] ;default: 4'b0 ; */ +/*description: */ +#define DPORT_SHARE_ROM_IA 0x0000000F +#define DPORT_SHARE_ROM_IA_M ((DPORT_SHARE_ROM_IA_V)<<(DPORT_SHARE_ROM_IA_S)) +#define DPORT_SHARE_ROM_IA_V 0xF +#define DPORT_SHARE_ROM_IA_S 6 +/* DPORT_SHARE_ROM_MPU_AD : RO ;bitpos:[5:4] ;default: 2'b0 ; */ +/*description: */ +#define DPORT_SHARE_ROM_MPU_AD 0x00000003 +#define DPORT_SHARE_ROM_MPU_AD_M ((DPORT_SHARE_ROM_MPU_AD_V)<<(DPORT_SHARE_ROM_MPU_AD_S)) +#define DPORT_SHARE_ROM_MPU_AD_V 0x3 +#define DPORT_SHARE_ROM_MPU_AD_S 4 +/* DPORT_APP_ROM_IA : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_ROM_IA (BIT(3)) +#define DPORT_APP_ROM_IA_M (BIT(3)) +#define DPORT_APP_ROM_IA_V 0x1 +#define DPORT_APP_ROM_IA_S 3 +/* DPORT_APP_ROM_MPU_AD : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_ROM_MPU_AD (BIT(2)) +#define DPORT_APP_ROM_MPU_AD_M (BIT(2)) +#define DPORT_APP_ROM_MPU_AD_V 0x1 +#define DPORT_APP_ROM_MPU_AD_S 2 +/* DPORT_PRO_ROM_IA : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_ROM_IA (BIT(1)) +#define DPORT_PRO_ROM_IA_M (BIT(1)) +#define DPORT_PRO_ROM_IA_V 0x1 +#define DPORT_PRO_ROM_IA_S 1 +/* DPORT_PRO_ROM_MPU_AD : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_ROM_MPU_AD (BIT(0)) +#define DPORT_PRO_ROM_MPU_AD_M (BIT(0)) +#define DPORT_PRO_ROM_MPU_AD_V 0x1 +#define DPORT_PRO_ROM_MPU_AD_S 0 + +#define DPORT_MEM_ACCESS_DBUG1_REG (DR_REG_DPORT_BASE + 0x3EC) +/* DPORT_AHBLITE_IA : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_AHBLITE_IA (BIT(10)) +#define DPORT_AHBLITE_IA_M (BIT(10)) +#define DPORT_AHBLITE_IA_V 0x1 +#define DPORT_AHBLITE_IA_S 10 +/* DPORT_AHBLITE_ACCESS_DENY : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_AHBLITE_ACCESS_DENY (BIT(9)) +#define DPORT_AHBLITE_ACCESS_DENY_M (BIT(9)) +#define DPORT_AHBLITE_ACCESS_DENY_V 0x1 +#define DPORT_AHBLITE_ACCESS_DENY_S 9 +/* DPORT_AHB_ACCESS_DENY : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_AHB_ACCESS_DENY (BIT(8)) +#define DPORT_AHB_ACCESS_DENY_M (BIT(8)) +#define DPORT_AHB_ACCESS_DENY_V 0x1 +#define DPORT_AHB_ACCESS_DENY_S 8 +/* DPORT_PIDGEN_IA : RO ;bitpos:[7:6] ;default: 2'b0 ; */ +/*description: */ +#define DPORT_PIDGEN_IA 0x00000003 +#define DPORT_PIDGEN_IA_M ((DPORT_PIDGEN_IA_V)<<(DPORT_PIDGEN_IA_S)) +#define DPORT_PIDGEN_IA_V 0x3 +#define DPORT_PIDGEN_IA_S 6 +/* DPORT_ARB_IA : RO ;bitpos:[5:4] ;default: 2'b0 ; */ +/*description: */ +#define DPORT_ARB_IA 0x00000003 +#define DPORT_ARB_IA_M ((DPORT_ARB_IA_V)<<(DPORT_ARB_IA_S)) +#define DPORT_ARB_IA_V 0x3 +#define DPORT_ARB_IA_S 4 +/* DPORT_INTERNAL_SRAM_MMU_MISS : RO ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: */ +#define DPORT_INTERNAL_SRAM_MMU_MISS 0x0000000F +#define DPORT_INTERNAL_SRAM_MMU_MISS_M ((DPORT_INTERNAL_SRAM_MMU_MISS_V)<<(DPORT_INTERNAL_SRAM_MMU_MISS_S)) +#define DPORT_INTERNAL_SRAM_MMU_MISS_V 0xF +#define DPORT_INTERNAL_SRAM_MMU_MISS_S 0 + +#define DPORT_PRO_DCACHE_DBUG0_REG (DR_REG_DPORT_BASE + 0x3F0) +/* DPORT_PRO_RX_END : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_RX_END (BIT(23)) +#define DPORT_PRO_RX_END_M (BIT(23)) +#define DPORT_PRO_RX_END_V 0x1 +#define DPORT_PRO_RX_END_S 23 +/* DPORT_PRO_SLAVE_WDATA_V : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_SLAVE_WDATA_V (BIT(22)) +#define DPORT_PRO_SLAVE_WDATA_V_M (BIT(22)) +#define DPORT_PRO_SLAVE_WDATA_V_V 0x1 +#define DPORT_PRO_SLAVE_WDATA_V_S 22 +/* DPORT_PRO_SLAVE_WR : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_SLAVE_WR (BIT(21)) +#define DPORT_PRO_SLAVE_WR_M (BIT(21)) +#define DPORT_PRO_SLAVE_WR_V 0x1 +#define DPORT_PRO_SLAVE_WR_S 21 +/* DPORT_PRO_TX_END : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_TX_END (BIT(20)) +#define DPORT_PRO_TX_END_M (BIT(20)) +#define DPORT_PRO_TX_END_V 0x1 +#define DPORT_PRO_TX_END_S 20 +/* DPORT_PRO_WR_BAK_TO_READ : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_WR_BAK_TO_READ (BIT(19)) +#define DPORT_PRO_WR_BAK_TO_READ_M (BIT(19)) +#define DPORT_PRO_WR_BAK_TO_READ_V 0x1 +#define DPORT_PRO_WR_BAK_TO_READ_S 19 +/* DPORT_PRO_CACHE_STATE : RO ;bitpos:[18:7] ;default: 12'b0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_STATE 0x00000FFF +#define DPORT_PRO_CACHE_STATE_M ((DPORT_PRO_CACHE_STATE_V)<<(DPORT_PRO_CACHE_STATE_S)) +#define DPORT_PRO_CACHE_STATE_V 0xFFF +#define DPORT_PRO_CACHE_STATE_S 7 +/* DPORT_PRO_CACHE_IA : RO ;bitpos:[6:1] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_IA 0x0000003F +#define DPORT_PRO_CACHE_IA_M ((DPORT_PRO_CACHE_IA_V)<<(DPORT_PRO_CACHE_IA_S)) +#define DPORT_PRO_CACHE_IA_V 0x3F +#define DPORT_PRO_CACHE_IA_S 1 +/* DPORT_PRO_CACHE_MMU_IA : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_MMU_IA (BIT(0)) +#define DPORT_PRO_CACHE_MMU_IA_M (BIT(0)) +#define DPORT_PRO_CACHE_MMU_IA_V 0x1 +#define DPORT_PRO_CACHE_MMU_IA_S 0 + +#define DPORT_PRO_DCACHE_DBUG1_REG (DR_REG_DPORT_BASE + 0x3F4) +/* DPORT_PRO_CTAG_RAM_RDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define DPORT_PRO_CTAG_RAM_RDATA 0xFFFFFFFF +#define DPORT_PRO_CTAG_RAM_RDATA_M ((DPORT_PRO_CTAG_RAM_RDATA_V)<<(DPORT_PRO_CTAG_RAM_RDATA_S)) +#define DPORT_PRO_CTAG_RAM_RDATA_V 0xFFFFFFFF +#define DPORT_PRO_CTAG_RAM_RDATA_S 0 + +#define DPORT_PRO_DCACHE_DBUG2_REG (DR_REG_DPORT_BASE + 0x3F8) +/* DPORT_PRO_CACHE_VADDR : RO ;bitpos:[26:0] ;default: 27'b0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_VADDR 0x07FFFFFF +#define DPORT_PRO_CACHE_VADDR_M ((DPORT_PRO_CACHE_VADDR_V)<<(DPORT_PRO_CACHE_VADDR_S)) +#define DPORT_PRO_CACHE_VADDR_V 0x7FFFFFF +#define DPORT_PRO_CACHE_VADDR_S 0 + +#define DPORT_PRO_DCACHE_DBUG3_REG (DR_REG_DPORT_BASE + 0x3FC) +/* DPORT_PRO_CACHE_IRAM0_PID_ERROR : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_CACHE_IRAM0_PID_ERROR (BIT(15)) +#define DPORT_PRO_CACHE_IRAM0_PID_ERROR_M (BIT(15)) +#define DPORT_PRO_CACHE_IRAM0_PID_ERROR_V 0x1 +#define DPORT_PRO_CACHE_IRAM0_PID_ERROR_S 15 +/* DPORT_PRO_CPU_DISABLED_CACHE_IA : RO ;bitpos:[14:9] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_PRO_CPU_DISABLED_CACHE_IA 0x0000003F +#define DPORT_PRO_CPU_DISABLED_CACHE_IA_M ((DPORT_PRO_CPU_DISABLED_CACHE_IA_V)<<(DPORT_PRO_CPU_DISABLED_CACHE_IA_S)) +#define DPORT_PRO_CPU_DISABLED_CACHE_IA_V 0x3F +#define DPORT_PRO_CPU_DISABLED_CACHE_IA_S 9 +/* DPORT_PRO_MMU_RDATA : RO ;bitpos:[8:0] ;default: 9'h0 ; */ +/*description: */ +#define DPORT_PRO_MMU_RDATA 0x000001FF +#define DPORT_PRO_MMU_RDATA_M ((DPORT_PRO_MMU_RDATA_V)<<(DPORT_PRO_MMU_RDATA_S)) +#define DPORT_PRO_MMU_RDATA_V 0x1FF +#define DPORT_PRO_MMU_RDATA_S 0 + +#define DPORT_PRO_DCACHE_DBUG4_REG (DR_REG_DPORT_BASE + 0x400) +/* DPORT_PRO_DRAM1ADDR0_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: */ +#define DPORT_PRO_DRAM1ADDR0_IA 0x000FFFFF +#define DPORT_PRO_DRAM1ADDR0_IA_M ((DPORT_PRO_DRAM1ADDR0_IA_V)<<(DPORT_PRO_DRAM1ADDR0_IA_S)) +#define DPORT_PRO_DRAM1ADDR0_IA_V 0xFFFFF +#define DPORT_PRO_DRAM1ADDR0_IA_S 0 + +#define DPORT_PRO_DCACHE_DBUG5_REG (DR_REG_DPORT_BASE + 0x404) +/* DPORT_PRO_DROM0ADDR0_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: */ +#define DPORT_PRO_DROM0ADDR0_IA 0x000FFFFF +#define DPORT_PRO_DROM0ADDR0_IA_M ((DPORT_PRO_DROM0ADDR0_IA_V)<<(DPORT_PRO_DROM0ADDR0_IA_S)) +#define DPORT_PRO_DROM0ADDR0_IA_V 0xFFFFF +#define DPORT_PRO_DROM0ADDR0_IA_S 0 + +#define DPORT_PRO_DCACHE_DBUG6_REG (DR_REG_DPORT_BASE + 0x408) +/* DPORT_PRO_IRAM0ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: */ +#define DPORT_PRO_IRAM0ADDR_IA 0x000FFFFF +#define DPORT_PRO_IRAM0ADDR_IA_M ((DPORT_PRO_IRAM0ADDR_IA_V)<<(DPORT_PRO_IRAM0ADDR_IA_S)) +#define DPORT_PRO_IRAM0ADDR_IA_V 0xFFFFF +#define DPORT_PRO_IRAM0ADDR_IA_S 0 + +#define DPORT_PRO_DCACHE_DBUG7_REG (DR_REG_DPORT_BASE + 0x40C) +/* DPORT_PRO_IRAM1ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: */ +#define DPORT_PRO_IRAM1ADDR_IA 0x000FFFFF +#define DPORT_PRO_IRAM1ADDR_IA_M ((DPORT_PRO_IRAM1ADDR_IA_V)<<(DPORT_PRO_IRAM1ADDR_IA_S)) +#define DPORT_PRO_IRAM1ADDR_IA_V 0xFFFFF +#define DPORT_PRO_IRAM1ADDR_IA_S 0 + +#define DPORT_PRO_DCACHE_DBUG8_REG (DR_REG_DPORT_BASE + 0x410) +/* DPORT_PRO_IROM0ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: */ +#define DPORT_PRO_IROM0ADDR_IA 0x000FFFFF +#define DPORT_PRO_IROM0ADDR_IA_M ((DPORT_PRO_IROM0ADDR_IA_V)<<(DPORT_PRO_IROM0ADDR_IA_S)) +#define DPORT_PRO_IROM0ADDR_IA_V 0xFFFFF +#define DPORT_PRO_IROM0ADDR_IA_S 0 + +#define DPORT_PRO_DCACHE_DBUG9_REG (DR_REG_DPORT_BASE + 0x414) +/* DPORT_PRO_OPSDRAMADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: */ +#define DPORT_PRO_OPSDRAMADDR_IA 0x000FFFFF +#define DPORT_PRO_OPSDRAMADDR_IA_M ((DPORT_PRO_OPSDRAMADDR_IA_V)<<(DPORT_PRO_OPSDRAMADDR_IA_S)) +#define DPORT_PRO_OPSDRAMADDR_IA_V 0xFFFFF +#define DPORT_PRO_OPSDRAMADDR_IA_S 0 + +#define DPORT_APP_DCACHE_DBUG0_REG (DR_REG_DPORT_BASE + 0x418) +/* DPORT_APP_RX_END : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_RX_END (BIT(23)) +#define DPORT_APP_RX_END_M (BIT(23)) +#define DPORT_APP_RX_END_V 0x1 +#define DPORT_APP_RX_END_S 23 +/* DPORT_APP_SLAVE_WDATA_V : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_SLAVE_WDATA_V (BIT(22)) +#define DPORT_APP_SLAVE_WDATA_V_M (BIT(22)) +#define DPORT_APP_SLAVE_WDATA_V_V 0x1 +#define DPORT_APP_SLAVE_WDATA_V_S 22 +/* DPORT_APP_SLAVE_WR : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_SLAVE_WR (BIT(21)) +#define DPORT_APP_SLAVE_WR_M (BIT(21)) +#define DPORT_APP_SLAVE_WR_V 0x1 +#define DPORT_APP_SLAVE_WR_S 21 +/* DPORT_APP_TX_END : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_TX_END (BIT(20)) +#define DPORT_APP_TX_END_M (BIT(20)) +#define DPORT_APP_TX_END_V 0x1 +#define DPORT_APP_TX_END_S 20 +/* DPORT_APP_WR_BAK_TO_READ : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_WR_BAK_TO_READ (BIT(19)) +#define DPORT_APP_WR_BAK_TO_READ_M (BIT(19)) +#define DPORT_APP_WR_BAK_TO_READ_V 0x1 +#define DPORT_APP_WR_BAK_TO_READ_S 19 +/* DPORT_APP_CACHE_STATE : RO ;bitpos:[18:7] ;default: 12'b0 ; */ +/*description: */ +#define DPORT_APP_CACHE_STATE 0x00000FFF +#define DPORT_APP_CACHE_STATE_M ((DPORT_APP_CACHE_STATE_V)<<(DPORT_APP_CACHE_STATE_S)) +#define DPORT_APP_CACHE_STATE_V 0xFFF +#define DPORT_APP_CACHE_STATE_S 7 +/* DPORT_APP_CACHE_IA : RO ;bitpos:[6:1] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_APP_CACHE_IA 0x0000003F +#define DPORT_APP_CACHE_IA_M ((DPORT_APP_CACHE_IA_V)<<(DPORT_APP_CACHE_IA_S)) +#define DPORT_APP_CACHE_IA_V 0x3F +#define DPORT_APP_CACHE_IA_S 1 +/* DPORT_APP_CACHE_MMU_IA : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_CACHE_MMU_IA (BIT(0)) +#define DPORT_APP_CACHE_MMU_IA_M (BIT(0)) +#define DPORT_APP_CACHE_MMU_IA_V 0x1 +#define DPORT_APP_CACHE_MMU_IA_S 0 + +#define DPORT_APP_DCACHE_DBUG1_REG (DR_REG_DPORT_BASE + 0x41C) +/* DPORT_APP_CTAG_RAM_RDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define DPORT_APP_CTAG_RAM_RDATA 0xFFFFFFFF +#define DPORT_APP_CTAG_RAM_RDATA_M ((DPORT_APP_CTAG_RAM_RDATA_V)<<(DPORT_APP_CTAG_RAM_RDATA_S)) +#define DPORT_APP_CTAG_RAM_RDATA_V 0xFFFFFFFF +#define DPORT_APP_CTAG_RAM_RDATA_S 0 + +#define DPORT_APP_DCACHE_DBUG2_REG (DR_REG_DPORT_BASE + 0x420) +/* DPORT_APP_CACHE_VADDR : RO ;bitpos:[26:0] ;default: 27'b0 ; */ +/*description: */ +#define DPORT_APP_CACHE_VADDR 0x07FFFFFF +#define DPORT_APP_CACHE_VADDR_M ((DPORT_APP_CACHE_VADDR_V)<<(DPORT_APP_CACHE_VADDR_S)) +#define DPORT_APP_CACHE_VADDR_V 0x7FFFFFF +#define DPORT_APP_CACHE_VADDR_S 0 + +#define DPORT_APP_DCACHE_DBUG3_REG (DR_REG_DPORT_BASE + 0x424) +/* DPORT_APP_CACHE_IRAM0_PID_ERROR : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_CACHE_IRAM0_PID_ERROR (BIT(15)) +#define DPORT_APP_CACHE_IRAM0_PID_ERROR_M (BIT(15)) +#define DPORT_APP_CACHE_IRAM0_PID_ERROR_V 0x1 +#define DPORT_APP_CACHE_IRAM0_PID_ERROR_S 15 +/* DPORT_APP_CPU_DISABLED_CACHE_IA : RO ;bitpos:[14:9] ;default: 6'b0 ; */ +/*description: */ +#define DPORT_APP_CPU_DISABLED_CACHE_IA 0x0000003F +#define DPORT_APP_CPU_DISABLED_CACHE_IA_M ((DPORT_APP_CPU_DISABLED_CACHE_IA_V)<<(DPORT_APP_CPU_DISABLED_CACHE_IA_S)) +#define DPORT_APP_CPU_DISABLED_CACHE_IA_V 0x3F +#define DPORT_APP_CPU_DISABLED_CACHE_IA_S 9 +/* DPORT_APP_MMU_RDATA : RO ;bitpos:[8:0] ;default: 9'h0 ; */ +/*description: */ +#define DPORT_APP_MMU_RDATA 0x000001FF +#define DPORT_APP_MMU_RDATA_M ((DPORT_APP_MMU_RDATA_V)<<(DPORT_APP_MMU_RDATA_S)) +#define DPORT_APP_MMU_RDATA_V 0x1FF +#define DPORT_APP_MMU_RDATA_S 0 + +#define DPORT_APP_DCACHE_DBUG4_REG (DR_REG_DPORT_BASE + 0x428) +/* DPORT_APP_DRAM1ADDR0_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: */ +#define DPORT_APP_DRAM1ADDR0_IA 0x000FFFFF +#define DPORT_APP_DRAM1ADDR0_IA_M ((DPORT_APP_DRAM1ADDR0_IA_V)<<(DPORT_APP_DRAM1ADDR0_IA_S)) +#define DPORT_APP_DRAM1ADDR0_IA_V 0xFFFFF +#define DPORT_APP_DRAM1ADDR0_IA_S 0 + +#define DPORT_APP_DCACHE_DBUG5_REG (DR_REG_DPORT_BASE + 0x42C) +/* DPORT_APP_DROM0ADDR0_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: */ +#define DPORT_APP_DROM0ADDR0_IA 0x000FFFFF +#define DPORT_APP_DROM0ADDR0_IA_M ((DPORT_APP_DROM0ADDR0_IA_V)<<(DPORT_APP_DROM0ADDR0_IA_S)) +#define DPORT_APP_DROM0ADDR0_IA_V 0xFFFFF +#define DPORT_APP_DROM0ADDR0_IA_S 0 + +#define DPORT_APP_DCACHE_DBUG6_REG (DR_REG_DPORT_BASE + 0x430) +/* DPORT_APP_IRAM0ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: */ +#define DPORT_APP_IRAM0ADDR_IA 0x000FFFFF +#define DPORT_APP_IRAM0ADDR_IA_M ((DPORT_APP_IRAM0ADDR_IA_V)<<(DPORT_APP_IRAM0ADDR_IA_S)) +#define DPORT_APP_IRAM0ADDR_IA_V 0xFFFFF +#define DPORT_APP_IRAM0ADDR_IA_S 0 + +#define DPORT_APP_DCACHE_DBUG7_REG (DR_REG_DPORT_BASE + 0x434) +/* DPORT_APP_IRAM1ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: */ +#define DPORT_APP_IRAM1ADDR_IA 0x000FFFFF +#define DPORT_APP_IRAM1ADDR_IA_M ((DPORT_APP_IRAM1ADDR_IA_V)<<(DPORT_APP_IRAM1ADDR_IA_S)) +#define DPORT_APP_IRAM1ADDR_IA_V 0xFFFFF +#define DPORT_APP_IRAM1ADDR_IA_S 0 + +#define DPORT_APP_DCACHE_DBUG8_REG (DR_REG_DPORT_BASE + 0x438) +/* DPORT_APP_IROM0ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: */ +#define DPORT_APP_IROM0ADDR_IA 0x000FFFFF +#define DPORT_APP_IROM0ADDR_IA_M ((DPORT_APP_IROM0ADDR_IA_V)<<(DPORT_APP_IROM0ADDR_IA_S)) +#define DPORT_APP_IROM0ADDR_IA_V 0xFFFFF +#define DPORT_APP_IROM0ADDR_IA_S 0 + +#define DPORT_APP_DCACHE_DBUG9_REG (DR_REG_DPORT_BASE + 0x43C) +/* DPORT_APP_OPSDRAMADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: */ +#define DPORT_APP_OPSDRAMADDR_IA 0x000FFFFF +#define DPORT_APP_OPSDRAMADDR_IA_M ((DPORT_APP_OPSDRAMADDR_IA_V)<<(DPORT_APP_OPSDRAMADDR_IA_S)) +#define DPORT_APP_OPSDRAMADDR_IA_V 0xFFFFF +#define DPORT_APP_OPSDRAMADDR_IA_S 0 + +#define DPORT_PRO_CPU_RECORD_CTRL_REG (DR_REG_DPORT_BASE + 0x440) +/* DPORT_PRO_CPU_PDEBUG_ENABLE : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_PRO_CPU_PDEBUG_ENABLE (BIT(8)) +#define DPORT_PRO_CPU_PDEBUG_ENABLE_M (BIT(8)) +#define DPORT_PRO_CPU_PDEBUG_ENABLE_V 0x1 +#define DPORT_PRO_CPU_PDEBUG_ENABLE_S 8 +/* DPORT_PRO_CPU_RECORD_DISABLE : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_CPU_RECORD_DISABLE (BIT(4)) +#define DPORT_PRO_CPU_RECORD_DISABLE_M (BIT(4)) +#define DPORT_PRO_CPU_RECORD_DISABLE_V 0x1 +#define DPORT_PRO_CPU_RECORD_DISABLE_S 4 +/* DPORT_PRO_CPU_RECORD_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_CPU_RECORD_ENABLE (BIT(0)) +#define DPORT_PRO_CPU_RECORD_ENABLE_M (BIT(0)) +#define DPORT_PRO_CPU_RECORD_ENABLE_V 0x1 +#define DPORT_PRO_CPU_RECORD_ENABLE_S 0 + +#define DPORT_PRO_CPU_RECORD_STATUS_REG (DR_REG_DPORT_BASE + 0x444) +/* DPORT_PRO_CPU_RECORDING : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PRO_CPU_RECORDING (BIT(0)) +#define DPORT_PRO_CPU_RECORDING_M (BIT(0)) +#define DPORT_PRO_CPU_RECORDING_V 0x1 +#define DPORT_PRO_CPU_RECORDING_S 0 + +#define DPORT_PRO_CPU_RECORD_PID_REG (DR_REG_DPORT_BASE + 0x448) +/* DPORT_RECORD_PRO_PID : RO ;bitpos:[2:0] ;default: 3'd0 ; */ +/*description: */ +#define DPORT_RECORD_PRO_PID 0x00000007 +#define DPORT_RECORD_PRO_PID_M ((DPORT_RECORD_PRO_PID_V)<<(DPORT_RECORD_PRO_PID_S)) +#define DPORT_RECORD_PRO_PID_V 0x7 +#define DPORT_RECORD_PRO_PID_S 0 + +#define DPORT_PRO_CPU_RECORD_PDEBUGINST_REG (DR_REG_DPORT_BASE + 0x44C) +/* DPORT_RECORD_PRO_PDEBUGINST : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define DPORT_RECORD_PRO_PDEBUGINST 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGINST_M ((DPORT_RECORD_PRO_PDEBUGINST_V)<<(DPORT_RECORD_PRO_PDEBUGINST_S)) +#define DPORT_RECORD_PRO_PDEBUGINST_V 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGINST_S 0 + +#define DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_REG (DR_REG_DPORT_BASE + 0x450) +/* DPORT_RECORD_PRO_PDEBUGSTATUS : RO ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: */ +#define DPORT_RECORD_PRO_PDEBUGSTATUS 0x000000FF +#define DPORT_RECORD_PRO_PDEBUGSTATUS_M ((DPORT_RECORD_PRO_PDEBUGSTATUS_V)<<(DPORT_RECORD_PRO_PDEBUGSTATUS_S)) +#define DPORT_RECORD_PRO_PDEBUGSTATUS_V 0xFF +#define DPORT_RECORD_PRO_PDEBUGSTATUS_S 0 + +#define DPORT_PRO_CPU_RECORD_PDEBUGDATA_REG (DR_REG_DPORT_BASE + 0x454) +/* DPORT_RECORD_PRO_PDEBUGDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define DPORT_RECORD_PRO_PDEBUGDATA 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGDATA_M ((DPORT_RECORD_PRO_PDEBUGDATA_V)<<(DPORT_RECORD_PRO_PDEBUGDATA_S)) +#define DPORT_RECORD_PRO_PDEBUGDATA_V 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGDATA_S 0 + +#define DPORT_PRO_CPU_RECORD_PDEBUGPC_REG (DR_REG_DPORT_BASE + 0x458) +/* DPORT_RECORD_PRO_PDEBUGPC : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define DPORT_RECORD_PRO_PDEBUGPC 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGPC_M ((DPORT_RECORD_PRO_PDEBUGPC_V)<<(DPORT_RECORD_PRO_PDEBUGPC_S)) +#define DPORT_RECORD_PRO_PDEBUGPC_V 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGPC_S 0 + +#define DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_REG (DR_REG_DPORT_BASE + 0x45C) +/* DPORT_RECORD_PRO_PDEBUGLS0STAT : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define DPORT_RECORD_PRO_PDEBUGLS0STAT 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGLS0STAT_M ((DPORT_RECORD_PRO_PDEBUGLS0STAT_V)<<(DPORT_RECORD_PRO_PDEBUGLS0STAT_S)) +#define DPORT_RECORD_PRO_PDEBUGLS0STAT_V 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGLS0STAT_S 0 + +#define DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG (DR_REG_DPORT_BASE + 0x460) +/* DPORT_RECORD_PRO_PDEBUGLS0ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define DPORT_RECORD_PRO_PDEBUGLS0ADDR 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGLS0ADDR_M ((DPORT_RECORD_PRO_PDEBUGLS0ADDR_V)<<(DPORT_RECORD_PRO_PDEBUGLS0ADDR_S)) +#define DPORT_RECORD_PRO_PDEBUGLS0ADDR_V 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGLS0ADDR_S 0 + +#define DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG (DR_REG_DPORT_BASE + 0x464) +/* DPORT_RECORD_PRO_PDEBUGLS0DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define DPORT_RECORD_PRO_PDEBUGLS0DATA 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGLS0DATA_M ((DPORT_RECORD_PRO_PDEBUGLS0DATA_V)<<(DPORT_RECORD_PRO_PDEBUGLS0DATA_S)) +#define DPORT_RECORD_PRO_PDEBUGLS0DATA_V 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGLS0DATA_S 0 + +#define DPORT_APP_CPU_RECORD_CTRL_REG (DR_REG_DPORT_BASE + 0x468) +/* DPORT_APP_CPU_PDEBUG_ENABLE : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_APP_CPU_PDEBUG_ENABLE (BIT(8)) +#define DPORT_APP_CPU_PDEBUG_ENABLE_M (BIT(8)) +#define DPORT_APP_CPU_PDEBUG_ENABLE_V 0x1 +#define DPORT_APP_CPU_PDEBUG_ENABLE_S 8 +/* DPORT_APP_CPU_RECORD_DISABLE : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_CPU_RECORD_DISABLE (BIT(4)) +#define DPORT_APP_CPU_RECORD_DISABLE_M (BIT(4)) +#define DPORT_APP_CPU_RECORD_DISABLE_V 0x1 +#define DPORT_APP_CPU_RECORD_DISABLE_S 4 +/* DPORT_APP_CPU_RECORD_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_CPU_RECORD_ENABLE (BIT(0)) +#define DPORT_APP_CPU_RECORD_ENABLE_M (BIT(0)) +#define DPORT_APP_CPU_RECORD_ENABLE_V 0x1 +#define DPORT_APP_CPU_RECORD_ENABLE_S 0 + +#define DPORT_APP_CPU_RECORD_STATUS_REG (DR_REG_DPORT_BASE + 0x46C) +/* DPORT_APP_CPU_RECORDING : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APP_CPU_RECORDING (BIT(0)) +#define DPORT_APP_CPU_RECORDING_M (BIT(0)) +#define DPORT_APP_CPU_RECORDING_V 0x1 +#define DPORT_APP_CPU_RECORDING_S 0 + +#define DPORT_APP_CPU_RECORD_PID_REG (DR_REG_DPORT_BASE + 0x470) +/* DPORT_RECORD_APP_PID : RO ;bitpos:[2:0] ;default: 3'd0 ; */ +/*description: */ +#define DPORT_RECORD_APP_PID 0x00000007 +#define DPORT_RECORD_APP_PID_M ((DPORT_RECORD_APP_PID_V)<<(DPORT_RECORD_APP_PID_S)) +#define DPORT_RECORD_APP_PID_V 0x7 +#define DPORT_RECORD_APP_PID_S 0 + +#define DPORT_APP_CPU_RECORD_PDEBUGINST_REG (DR_REG_DPORT_BASE + 0x474) +/* DPORT_RECORD_APP_PDEBUGINST : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define DPORT_RECORD_APP_PDEBUGINST 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGINST_M ((DPORT_RECORD_APP_PDEBUGINST_V)<<(DPORT_RECORD_APP_PDEBUGINST_S)) +#define DPORT_RECORD_APP_PDEBUGINST_V 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGINST_S 0 + +#define DPORT_APP_CPU_RECORD_PDEBUGSTATUS_REG (DR_REG_DPORT_BASE + 0x478) +/* DPORT_RECORD_APP_PDEBUGSTATUS : RO ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: */ +#define DPORT_RECORD_APP_PDEBUGSTATUS 0x000000FF +#define DPORT_RECORD_APP_PDEBUGSTATUS_M ((DPORT_RECORD_APP_PDEBUGSTATUS_V)<<(DPORT_RECORD_APP_PDEBUGSTATUS_S)) +#define DPORT_RECORD_APP_PDEBUGSTATUS_V 0xFF +#define DPORT_RECORD_APP_PDEBUGSTATUS_S 0 + +#define DPORT_APP_CPU_RECORD_PDEBUGDATA_REG (DR_REG_DPORT_BASE + 0x47C) +/* DPORT_RECORD_APP_PDEBUGDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define DPORT_RECORD_APP_PDEBUGDATA 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGDATA_M ((DPORT_RECORD_APP_PDEBUGDATA_V)<<(DPORT_RECORD_APP_PDEBUGDATA_S)) +#define DPORT_RECORD_APP_PDEBUGDATA_V 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGDATA_S 0 + +#define DPORT_APP_CPU_RECORD_PDEBUGPC_REG (DR_REG_DPORT_BASE + 0x480) +/* DPORT_RECORD_APP_PDEBUGPC : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define DPORT_RECORD_APP_PDEBUGPC 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGPC_M ((DPORT_RECORD_APP_PDEBUGPC_V)<<(DPORT_RECORD_APP_PDEBUGPC_S)) +#define DPORT_RECORD_APP_PDEBUGPC_V 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGPC_S 0 + +#define DPORT_APP_CPU_RECORD_PDEBUGLS0STAT_REG (DR_REG_DPORT_BASE + 0x484) +/* DPORT_RECORD_APP_PDEBUGLS0STAT : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define DPORT_RECORD_APP_PDEBUGLS0STAT 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGLS0STAT_M ((DPORT_RECORD_APP_PDEBUGLS0STAT_V)<<(DPORT_RECORD_APP_PDEBUGLS0STAT_S)) +#define DPORT_RECORD_APP_PDEBUGLS0STAT_V 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGLS0STAT_S 0 + +#define DPORT_APP_CPU_RECORD_PDEBUGLS0ADDR_REG (DR_REG_DPORT_BASE + 0x488) +/* DPORT_RECORD_APP_PDEBUGLS0ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define DPORT_RECORD_APP_PDEBUGLS0ADDR 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGLS0ADDR_M ((DPORT_RECORD_APP_PDEBUGLS0ADDR_V)<<(DPORT_RECORD_APP_PDEBUGLS0ADDR_S)) +#define DPORT_RECORD_APP_PDEBUGLS0ADDR_V 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGLS0ADDR_S 0 + +#define DPORT_APP_CPU_RECORD_PDEBUGLS0DATA_REG (DR_REG_DPORT_BASE + 0x48C) +/* DPORT_RECORD_APP_PDEBUGLS0DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define DPORT_RECORD_APP_PDEBUGLS0DATA 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGLS0DATA_M ((DPORT_RECORD_APP_PDEBUGLS0DATA_V)<<(DPORT_RECORD_APP_PDEBUGLS0DATA_S)) +#define DPORT_RECORD_APP_PDEBUGLS0DATA_V 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGLS0DATA_S 0 + +#define DPORT_RSA_PD_CTRL_REG (DR_REG_DPORT_BASE + 0x490) +/* DPORT_RSA_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_RSA_PD (BIT(0)) +#define DPORT_RSA_PD_M (BIT(0)) +#define DPORT_RSA_PD_V 0x1 +#define DPORT_RSA_PD_S 0 + +#define DPORT_ROM_MPU_TABLE0_REG (DR_REG_DPORT_BASE + 0x494) +/* DPORT_ROM_MPU_TABLE0 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_ROM_MPU_TABLE0 0x00000003 +#define DPORT_ROM_MPU_TABLE0_M ((DPORT_ROM_MPU_TABLE0_V)<<(DPORT_ROM_MPU_TABLE0_S)) +#define DPORT_ROM_MPU_TABLE0_V 0x3 +#define DPORT_ROM_MPU_TABLE0_S 0 + +#define DPORT_ROM_MPU_TABLE1_REG (DR_REG_DPORT_BASE + 0x498) +/* DPORT_ROM_MPU_TABLE1 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_ROM_MPU_TABLE1 0x00000003 +#define DPORT_ROM_MPU_TABLE1_M ((DPORT_ROM_MPU_TABLE1_V)<<(DPORT_ROM_MPU_TABLE1_S)) +#define DPORT_ROM_MPU_TABLE1_V 0x3 +#define DPORT_ROM_MPU_TABLE1_S 0 + +#define DPORT_ROM_MPU_TABLE2_REG (DR_REG_DPORT_BASE + 0x49C) +/* DPORT_ROM_MPU_TABLE2 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_ROM_MPU_TABLE2 0x00000003 +#define DPORT_ROM_MPU_TABLE2_M ((DPORT_ROM_MPU_TABLE2_V)<<(DPORT_ROM_MPU_TABLE2_S)) +#define DPORT_ROM_MPU_TABLE2_V 0x3 +#define DPORT_ROM_MPU_TABLE2_S 0 + +#define DPORT_ROM_MPU_TABLE3_REG (DR_REG_DPORT_BASE + 0x4A0) +/* DPORT_ROM_MPU_TABLE3 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_ROM_MPU_TABLE3 0x00000003 +#define DPORT_ROM_MPU_TABLE3_M ((DPORT_ROM_MPU_TABLE3_V)<<(DPORT_ROM_MPU_TABLE3_S)) +#define DPORT_ROM_MPU_TABLE3_V 0x3 +#define DPORT_ROM_MPU_TABLE3_S 0 + +#define DPORT_SHROM_MPU_TABLE0_REG (DR_REG_DPORT_BASE + 0x4A4) +/* DPORT_SHROM_MPU_TABLE0 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE0 0x00000003 +#define DPORT_SHROM_MPU_TABLE0_M ((DPORT_SHROM_MPU_TABLE0_V)<<(DPORT_SHROM_MPU_TABLE0_S)) +#define DPORT_SHROM_MPU_TABLE0_V 0x3 +#define DPORT_SHROM_MPU_TABLE0_S 0 + +#define DPORT_SHROM_MPU_TABLE1_REG (DR_REG_DPORT_BASE + 0x4A8) +/* DPORT_SHROM_MPU_TABLE1 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE1 0x00000003 +#define DPORT_SHROM_MPU_TABLE1_M ((DPORT_SHROM_MPU_TABLE1_V)<<(DPORT_SHROM_MPU_TABLE1_S)) +#define DPORT_SHROM_MPU_TABLE1_V 0x3 +#define DPORT_SHROM_MPU_TABLE1_S 0 + +#define DPORT_SHROM_MPU_TABLE2_REG (DR_REG_DPORT_BASE + 0x4AC) +/* DPORT_SHROM_MPU_TABLE2 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE2 0x00000003 +#define DPORT_SHROM_MPU_TABLE2_M ((DPORT_SHROM_MPU_TABLE2_V)<<(DPORT_SHROM_MPU_TABLE2_S)) +#define DPORT_SHROM_MPU_TABLE2_V 0x3 +#define DPORT_SHROM_MPU_TABLE2_S 0 + +#define DPORT_SHROM_MPU_TABLE3_REG (DR_REG_DPORT_BASE + 0x4B0) +/* DPORT_SHROM_MPU_TABLE3 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE3 0x00000003 +#define DPORT_SHROM_MPU_TABLE3_M ((DPORT_SHROM_MPU_TABLE3_V)<<(DPORT_SHROM_MPU_TABLE3_S)) +#define DPORT_SHROM_MPU_TABLE3_V 0x3 +#define DPORT_SHROM_MPU_TABLE3_S 0 + +#define DPORT_SHROM_MPU_TABLE4_REG (DR_REG_DPORT_BASE + 0x4B4) +/* DPORT_SHROM_MPU_TABLE4 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE4 0x00000003 +#define DPORT_SHROM_MPU_TABLE4_M ((DPORT_SHROM_MPU_TABLE4_V)<<(DPORT_SHROM_MPU_TABLE4_S)) +#define DPORT_SHROM_MPU_TABLE4_V 0x3 +#define DPORT_SHROM_MPU_TABLE4_S 0 + +#define DPORT_SHROM_MPU_TABLE5_REG (DR_REG_DPORT_BASE + 0x4B8) +/* DPORT_SHROM_MPU_TABLE5 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE5 0x00000003 +#define DPORT_SHROM_MPU_TABLE5_M ((DPORT_SHROM_MPU_TABLE5_V)<<(DPORT_SHROM_MPU_TABLE5_S)) +#define DPORT_SHROM_MPU_TABLE5_V 0x3 +#define DPORT_SHROM_MPU_TABLE5_S 0 + +#define DPORT_SHROM_MPU_TABLE6_REG (DR_REG_DPORT_BASE + 0x4BC) +/* DPORT_SHROM_MPU_TABLE6 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE6 0x00000003 +#define DPORT_SHROM_MPU_TABLE6_M ((DPORT_SHROM_MPU_TABLE6_V)<<(DPORT_SHROM_MPU_TABLE6_S)) +#define DPORT_SHROM_MPU_TABLE6_V 0x3 +#define DPORT_SHROM_MPU_TABLE6_S 0 + +#define DPORT_SHROM_MPU_TABLE7_REG (DR_REG_DPORT_BASE + 0x4C0) +/* DPORT_SHROM_MPU_TABLE7 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE7 0x00000003 +#define DPORT_SHROM_MPU_TABLE7_M ((DPORT_SHROM_MPU_TABLE7_V)<<(DPORT_SHROM_MPU_TABLE7_S)) +#define DPORT_SHROM_MPU_TABLE7_V 0x3 +#define DPORT_SHROM_MPU_TABLE7_S 0 + +#define DPORT_SHROM_MPU_TABLE8_REG (DR_REG_DPORT_BASE + 0x4C4) +/* DPORT_SHROM_MPU_TABLE8 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE8 0x00000003 +#define DPORT_SHROM_MPU_TABLE8_M ((DPORT_SHROM_MPU_TABLE8_V)<<(DPORT_SHROM_MPU_TABLE8_S)) +#define DPORT_SHROM_MPU_TABLE8_V 0x3 +#define DPORT_SHROM_MPU_TABLE8_S 0 + +#define DPORT_SHROM_MPU_TABLE9_REG (DR_REG_DPORT_BASE + 0x4C8) +/* DPORT_SHROM_MPU_TABLE9 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE9 0x00000003 +#define DPORT_SHROM_MPU_TABLE9_M ((DPORT_SHROM_MPU_TABLE9_V)<<(DPORT_SHROM_MPU_TABLE9_S)) +#define DPORT_SHROM_MPU_TABLE9_V 0x3 +#define DPORT_SHROM_MPU_TABLE9_S 0 + +#define DPORT_SHROM_MPU_TABLE10_REG (DR_REG_DPORT_BASE + 0x4CC) +/* DPORT_SHROM_MPU_TABLE10 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE10 0x00000003 +#define DPORT_SHROM_MPU_TABLE10_M ((DPORT_SHROM_MPU_TABLE10_V)<<(DPORT_SHROM_MPU_TABLE10_S)) +#define DPORT_SHROM_MPU_TABLE10_V 0x3 +#define DPORT_SHROM_MPU_TABLE10_S 0 + +#define DPORT_SHROM_MPU_TABLE11_REG (DR_REG_DPORT_BASE + 0x4D0) +/* DPORT_SHROM_MPU_TABLE11 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE11 0x00000003 +#define DPORT_SHROM_MPU_TABLE11_M ((DPORT_SHROM_MPU_TABLE11_V)<<(DPORT_SHROM_MPU_TABLE11_S)) +#define DPORT_SHROM_MPU_TABLE11_V 0x3 +#define DPORT_SHROM_MPU_TABLE11_S 0 + +#define DPORT_SHROM_MPU_TABLE12_REG (DR_REG_DPORT_BASE + 0x4D4) +/* DPORT_SHROM_MPU_TABLE12 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE12 0x00000003 +#define DPORT_SHROM_MPU_TABLE12_M ((DPORT_SHROM_MPU_TABLE12_V)<<(DPORT_SHROM_MPU_TABLE12_S)) +#define DPORT_SHROM_MPU_TABLE12_V 0x3 +#define DPORT_SHROM_MPU_TABLE12_S 0 + +#define DPORT_SHROM_MPU_TABLE13_REG (DR_REG_DPORT_BASE + 0x4D8) +/* DPORT_SHROM_MPU_TABLE13 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE13 0x00000003 +#define DPORT_SHROM_MPU_TABLE13_M ((DPORT_SHROM_MPU_TABLE13_V)<<(DPORT_SHROM_MPU_TABLE13_S)) +#define DPORT_SHROM_MPU_TABLE13_V 0x3 +#define DPORT_SHROM_MPU_TABLE13_S 0 + +#define DPORT_SHROM_MPU_TABLE14_REG (DR_REG_DPORT_BASE + 0x4DC) +/* DPORT_SHROM_MPU_TABLE14 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE14 0x00000003 +#define DPORT_SHROM_MPU_TABLE14_M ((DPORT_SHROM_MPU_TABLE14_V)<<(DPORT_SHROM_MPU_TABLE14_S)) +#define DPORT_SHROM_MPU_TABLE14_V 0x3 +#define DPORT_SHROM_MPU_TABLE14_S 0 + +#define DPORT_SHROM_MPU_TABLE15_REG (DR_REG_DPORT_BASE + 0x4E0) +/* DPORT_SHROM_MPU_TABLE15 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE15 0x00000003 +#define DPORT_SHROM_MPU_TABLE15_M ((DPORT_SHROM_MPU_TABLE15_V)<<(DPORT_SHROM_MPU_TABLE15_S)) +#define DPORT_SHROM_MPU_TABLE15_V 0x3 +#define DPORT_SHROM_MPU_TABLE15_S 0 + +#define DPORT_SHROM_MPU_TABLE16_REG (DR_REG_DPORT_BASE + 0x4E4) +/* DPORT_SHROM_MPU_TABLE16 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE16 0x00000003 +#define DPORT_SHROM_MPU_TABLE16_M ((DPORT_SHROM_MPU_TABLE16_V)<<(DPORT_SHROM_MPU_TABLE16_S)) +#define DPORT_SHROM_MPU_TABLE16_V 0x3 +#define DPORT_SHROM_MPU_TABLE16_S 0 + +#define DPORT_SHROM_MPU_TABLE17_REG (DR_REG_DPORT_BASE + 0x4E8) +/* DPORT_SHROM_MPU_TABLE17 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE17 0x00000003 +#define DPORT_SHROM_MPU_TABLE17_M ((DPORT_SHROM_MPU_TABLE17_V)<<(DPORT_SHROM_MPU_TABLE17_S)) +#define DPORT_SHROM_MPU_TABLE17_V 0x3 +#define DPORT_SHROM_MPU_TABLE17_S 0 + +#define DPORT_SHROM_MPU_TABLE18_REG (DR_REG_DPORT_BASE + 0x4EC) +/* DPORT_SHROM_MPU_TABLE18 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE18 0x00000003 +#define DPORT_SHROM_MPU_TABLE18_M ((DPORT_SHROM_MPU_TABLE18_V)<<(DPORT_SHROM_MPU_TABLE18_S)) +#define DPORT_SHROM_MPU_TABLE18_V 0x3 +#define DPORT_SHROM_MPU_TABLE18_S 0 + +#define DPORT_SHROM_MPU_TABLE19_REG (DR_REG_DPORT_BASE + 0x4F0) +/* DPORT_SHROM_MPU_TABLE19 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE19 0x00000003 +#define DPORT_SHROM_MPU_TABLE19_M ((DPORT_SHROM_MPU_TABLE19_V)<<(DPORT_SHROM_MPU_TABLE19_S)) +#define DPORT_SHROM_MPU_TABLE19_V 0x3 +#define DPORT_SHROM_MPU_TABLE19_S 0 + +#define DPORT_SHROM_MPU_TABLE20_REG (DR_REG_DPORT_BASE + 0x4F4) +/* DPORT_SHROM_MPU_TABLE20 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE20 0x00000003 +#define DPORT_SHROM_MPU_TABLE20_M ((DPORT_SHROM_MPU_TABLE20_V)<<(DPORT_SHROM_MPU_TABLE20_S)) +#define DPORT_SHROM_MPU_TABLE20_V 0x3 +#define DPORT_SHROM_MPU_TABLE20_S 0 + +#define DPORT_SHROM_MPU_TABLE21_REG (DR_REG_DPORT_BASE + 0x4F8) +/* DPORT_SHROM_MPU_TABLE21 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE21 0x00000003 +#define DPORT_SHROM_MPU_TABLE21_M ((DPORT_SHROM_MPU_TABLE21_V)<<(DPORT_SHROM_MPU_TABLE21_S)) +#define DPORT_SHROM_MPU_TABLE21_V 0x3 +#define DPORT_SHROM_MPU_TABLE21_S 0 + +#define DPORT_SHROM_MPU_TABLE22_REG (DR_REG_DPORT_BASE + 0x4FC) +/* DPORT_SHROM_MPU_TABLE22 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE22 0x00000003 +#define DPORT_SHROM_MPU_TABLE22_M ((DPORT_SHROM_MPU_TABLE22_V)<<(DPORT_SHROM_MPU_TABLE22_S)) +#define DPORT_SHROM_MPU_TABLE22_V 0x3 +#define DPORT_SHROM_MPU_TABLE22_S 0 + +#define DPORT_SHROM_MPU_TABLE23_REG (DR_REG_DPORT_BASE + 0x500) +/* DPORT_SHROM_MPU_TABLE23 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: */ +#define DPORT_SHROM_MPU_TABLE23 0x00000003 +#define DPORT_SHROM_MPU_TABLE23_M ((DPORT_SHROM_MPU_TABLE23_V)<<(DPORT_SHROM_MPU_TABLE23_S)) +#define DPORT_SHROM_MPU_TABLE23_V 0x3 +#define DPORT_SHROM_MPU_TABLE23_S 0 + +#define DPORT_IMMU_TABLE0_REG (DR_REG_DPORT_BASE + 0x504) +/* DPORT_IMMU_TABLE0 : R/W ;bitpos:[6:0] ;default: 7'd0 ; */ +/*description: */ +#define DPORT_IMMU_TABLE0 0x0000007F +#define DPORT_IMMU_TABLE0_M ((DPORT_IMMU_TABLE0_V)<<(DPORT_IMMU_TABLE0_S)) +#define DPORT_IMMU_TABLE0_V 0x7F +#define DPORT_IMMU_TABLE0_S 0 + +#define DPORT_IMMU_TABLE1_REG (DR_REG_DPORT_BASE + 0x508) +/* DPORT_IMMU_TABLE1 : R/W ;bitpos:[6:0] ;default: 7'd1 ; */ +/*description: */ +#define DPORT_IMMU_TABLE1 0x0000007F +#define DPORT_IMMU_TABLE1_M ((DPORT_IMMU_TABLE1_V)<<(DPORT_IMMU_TABLE1_S)) +#define DPORT_IMMU_TABLE1_V 0x7F +#define DPORT_IMMU_TABLE1_S 0 + +#define DPORT_IMMU_TABLE2_REG (DR_REG_DPORT_BASE + 0x50C) +/* DPORT_IMMU_TABLE2 : R/W ;bitpos:[6:0] ;default: 7'd2 ; */ +/*description: */ +#define DPORT_IMMU_TABLE2 0x0000007F +#define DPORT_IMMU_TABLE2_M ((DPORT_IMMU_TABLE2_V)<<(DPORT_IMMU_TABLE2_S)) +#define DPORT_IMMU_TABLE2_V 0x7F +#define DPORT_IMMU_TABLE2_S 0 + +#define DPORT_IMMU_TABLE3_REG (DR_REG_DPORT_BASE + 0x510) +/* DPORT_IMMU_TABLE3 : R/W ;bitpos:[6:0] ;default: 7'd3 ; */ +/*description: */ +#define DPORT_IMMU_TABLE3 0x0000007F +#define DPORT_IMMU_TABLE3_M ((DPORT_IMMU_TABLE3_V)<<(DPORT_IMMU_TABLE3_S)) +#define DPORT_IMMU_TABLE3_V 0x7F +#define DPORT_IMMU_TABLE3_S 0 + +#define DPORT_IMMU_TABLE4_REG (DR_REG_DPORT_BASE + 0x514) +/* DPORT_IMMU_TABLE4 : R/W ;bitpos:[6:0] ;default: 7'd4 ; */ +/*description: */ +#define DPORT_IMMU_TABLE4 0x0000007F +#define DPORT_IMMU_TABLE4_M ((DPORT_IMMU_TABLE4_V)<<(DPORT_IMMU_TABLE4_S)) +#define DPORT_IMMU_TABLE4_V 0x7F +#define DPORT_IMMU_TABLE4_S 0 + +#define DPORT_IMMU_TABLE5_REG (DR_REG_DPORT_BASE + 0x518) +/* DPORT_IMMU_TABLE5 : R/W ;bitpos:[6:0] ;default: 7'd5 ; */ +/*description: */ +#define DPORT_IMMU_TABLE5 0x0000007F +#define DPORT_IMMU_TABLE5_M ((DPORT_IMMU_TABLE5_V)<<(DPORT_IMMU_TABLE5_S)) +#define DPORT_IMMU_TABLE5_V 0x7F +#define DPORT_IMMU_TABLE5_S 0 + +#define DPORT_IMMU_TABLE6_REG (DR_REG_DPORT_BASE + 0x51C) +/* DPORT_IMMU_TABLE6 : R/W ;bitpos:[6:0] ;default: 7'd6 ; */ +/*description: */ +#define DPORT_IMMU_TABLE6 0x0000007F +#define DPORT_IMMU_TABLE6_M ((DPORT_IMMU_TABLE6_V)<<(DPORT_IMMU_TABLE6_S)) +#define DPORT_IMMU_TABLE6_V 0x7F +#define DPORT_IMMU_TABLE6_S 0 + +#define DPORT_IMMU_TABLE7_REG (DR_REG_DPORT_BASE + 0x520) +/* DPORT_IMMU_TABLE7 : R/W ;bitpos:[6:0] ;default: 7'd7 ; */ +/*description: */ +#define DPORT_IMMU_TABLE7 0x0000007F +#define DPORT_IMMU_TABLE7_M ((DPORT_IMMU_TABLE7_V)<<(DPORT_IMMU_TABLE7_S)) +#define DPORT_IMMU_TABLE7_V 0x7F +#define DPORT_IMMU_TABLE7_S 0 + +#define DPORT_IMMU_TABLE8_REG (DR_REG_DPORT_BASE + 0x524) +/* DPORT_IMMU_TABLE8 : R/W ;bitpos:[6:0] ;default: 7'd8 ; */ +/*description: */ +#define DPORT_IMMU_TABLE8 0x0000007F +#define DPORT_IMMU_TABLE8_M ((DPORT_IMMU_TABLE8_V)<<(DPORT_IMMU_TABLE8_S)) +#define DPORT_IMMU_TABLE8_V 0x7F +#define DPORT_IMMU_TABLE8_S 0 + +#define DPORT_IMMU_TABLE9_REG (DR_REG_DPORT_BASE + 0x528) +/* DPORT_IMMU_TABLE9 : R/W ;bitpos:[6:0] ;default: 7'd9 ; */ +/*description: */ +#define DPORT_IMMU_TABLE9 0x0000007F +#define DPORT_IMMU_TABLE9_M ((DPORT_IMMU_TABLE9_V)<<(DPORT_IMMU_TABLE9_S)) +#define DPORT_IMMU_TABLE9_V 0x7F +#define DPORT_IMMU_TABLE9_S 0 + +#define DPORT_IMMU_TABLE10_REG (DR_REG_DPORT_BASE + 0x52C) +/* DPORT_IMMU_TABLE10 : R/W ;bitpos:[6:0] ;default: 7'd10 ; */ +/*description: */ +#define DPORT_IMMU_TABLE10 0x0000007F +#define DPORT_IMMU_TABLE10_M ((DPORT_IMMU_TABLE10_V)<<(DPORT_IMMU_TABLE10_S)) +#define DPORT_IMMU_TABLE10_V 0x7F +#define DPORT_IMMU_TABLE10_S 0 + +#define DPORT_IMMU_TABLE11_REG (DR_REG_DPORT_BASE + 0x530) +/* DPORT_IMMU_TABLE11 : R/W ;bitpos:[6:0] ;default: 7'd11 ; */ +/*description: */ +#define DPORT_IMMU_TABLE11 0x0000007F +#define DPORT_IMMU_TABLE11_M ((DPORT_IMMU_TABLE11_V)<<(DPORT_IMMU_TABLE11_S)) +#define DPORT_IMMU_TABLE11_V 0x7F +#define DPORT_IMMU_TABLE11_S 0 + +#define DPORT_IMMU_TABLE12_REG (DR_REG_DPORT_BASE + 0x534) +/* DPORT_IMMU_TABLE12 : R/W ;bitpos:[6:0] ;default: 7'd12 ; */ +/*description: */ +#define DPORT_IMMU_TABLE12 0x0000007F +#define DPORT_IMMU_TABLE12_M ((DPORT_IMMU_TABLE12_V)<<(DPORT_IMMU_TABLE12_S)) +#define DPORT_IMMU_TABLE12_V 0x7F +#define DPORT_IMMU_TABLE12_S 0 + +#define DPORT_IMMU_TABLE13_REG (DR_REG_DPORT_BASE + 0x538) +/* DPORT_IMMU_TABLE13 : R/W ;bitpos:[6:0] ;default: 7'd13 ; */ +/*description: */ +#define DPORT_IMMU_TABLE13 0x0000007F +#define DPORT_IMMU_TABLE13_M ((DPORT_IMMU_TABLE13_V)<<(DPORT_IMMU_TABLE13_S)) +#define DPORT_IMMU_TABLE13_V 0x7F +#define DPORT_IMMU_TABLE13_S 0 + +#define DPORT_IMMU_TABLE14_REG (DR_REG_DPORT_BASE + 0x53C) +/* DPORT_IMMU_TABLE14 : R/W ;bitpos:[6:0] ;default: 7'd14 ; */ +/*description: */ +#define DPORT_IMMU_TABLE14 0x0000007F +#define DPORT_IMMU_TABLE14_M ((DPORT_IMMU_TABLE14_V)<<(DPORT_IMMU_TABLE14_S)) +#define DPORT_IMMU_TABLE14_V 0x7F +#define DPORT_IMMU_TABLE14_S 0 + +#define DPORT_IMMU_TABLE15_REG (DR_REG_DPORT_BASE + 0x540) +/* DPORT_IMMU_TABLE15 : R/W ;bitpos:[6:0] ;default: 7'd15 ; */ +/*description: */ +#define DPORT_IMMU_TABLE15 0x0000007F +#define DPORT_IMMU_TABLE15_M ((DPORT_IMMU_TABLE15_V)<<(DPORT_IMMU_TABLE15_S)) +#define DPORT_IMMU_TABLE15_V 0x7F +#define DPORT_IMMU_TABLE15_S 0 + +#define DPORT_DMMU_TABLE0_REG (DR_REG_DPORT_BASE + 0x544) +/* DPORT_DMMU_TABLE0 : R/W ;bitpos:[6:0] ;default: 7'd0 ; */ +/*description: */ +#define DPORT_DMMU_TABLE0 0x0000007F +#define DPORT_DMMU_TABLE0_M ((DPORT_DMMU_TABLE0_V)<<(DPORT_DMMU_TABLE0_S)) +#define DPORT_DMMU_TABLE0_V 0x7F +#define DPORT_DMMU_TABLE0_S 0 + +#define DPORT_DMMU_TABLE1_REG (DR_REG_DPORT_BASE + 0x548) +/* DPORT_DMMU_TABLE1 : R/W ;bitpos:[6:0] ;default: 7'd1 ; */ +/*description: */ +#define DPORT_DMMU_TABLE1 0x0000007F +#define DPORT_DMMU_TABLE1_M ((DPORT_DMMU_TABLE1_V)<<(DPORT_DMMU_TABLE1_S)) +#define DPORT_DMMU_TABLE1_V 0x7F +#define DPORT_DMMU_TABLE1_S 0 + +#define DPORT_DMMU_TABLE2_REG (DR_REG_DPORT_BASE + 0x54C) +/* DPORT_DMMU_TABLE2 : R/W ;bitpos:[6:0] ;default: 7'd2 ; */ +/*description: */ +#define DPORT_DMMU_TABLE2 0x0000007F +#define DPORT_DMMU_TABLE2_M ((DPORT_DMMU_TABLE2_V)<<(DPORT_DMMU_TABLE2_S)) +#define DPORT_DMMU_TABLE2_V 0x7F +#define DPORT_DMMU_TABLE2_S 0 + +#define DPORT_DMMU_TABLE3_REG (DR_REG_DPORT_BASE + 0x550) +/* DPORT_DMMU_TABLE3 : R/W ;bitpos:[6:0] ;default: 7'd3 ; */ +/*description: */ +#define DPORT_DMMU_TABLE3 0x0000007F +#define DPORT_DMMU_TABLE3_M ((DPORT_DMMU_TABLE3_V)<<(DPORT_DMMU_TABLE3_S)) +#define DPORT_DMMU_TABLE3_V 0x7F +#define DPORT_DMMU_TABLE3_S 0 + +#define DPORT_DMMU_TABLE4_REG (DR_REG_DPORT_BASE + 0x554) +/* DPORT_DMMU_TABLE4 : R/W ;bitpos:[6:0] ;default: 7'd4 ; */ +/*description: */ +#define DPORT_DMMU_TABLE4 0x0000007F +#define DPORT_DMMU_TABLE4_M ((DPORT_DMMU_TABLE4_V)<<(DPORT_DMMU_TABLE4_S)) +#define DPORT_DMMU_TABLE4_V 0x7F +#define DPORT_DMMU_TABLE4_S 0 + +#define DPORT_DMMU_TABLE5_REG (DR_REG_DPORT_BASE + 0x558) +/* DPORT_DMMU_TABLE5 : R/W ;bitpos:[6:0] ;default: 7'd5 ; */ +/*description: */ +#define DPORT_DMMU_TABLE5 0x0000007F +#define DPORT_DMMU_TABLE5_M ((DPORT_DMMU_TABLE5_V)<<(DPORT_DMMU_TABLE5_S)) +#define DPORT_DMMU_TABLE5_V 0x7F +#define DPORT_DMMU_TABLE5_S 0 + +#define DPORT_DMMU_TABLE6_REG (DR_REG_DPORT_BASE + 0x55C) +/* DPORT_DMMU_TABLE6 : R/W ;bitpos:[6:0] ;default: 7'd6 ; */ +/*description: */ +#define DPORT_DMMU_TABLE6 0x0000007F +#define DPORT_DMMU_TABLE6_M ((DPORT_DMMU_TABLE6_V)<<(DPORT_DMMU_TABLE6_S)) +#define DPORT_DMMU_TABLE6_V 0x7F +#define DPORT_DMMU_TABLE6_S 0 + +#define DPORT_DMMU_TABLE7_REG (DR_REG_DPORT_BASE + 0x560) +/* DPORT_DMMU_TABLE7 : R/W ;bitpos:[6:0] ;default: 7'd7 ; */ +/*description: */ +#define DPORT_DMMU_TABLE7 0x0000007F +#define DPORT_DMMU_TABLE7_M ((DPORT_DMMU_TABLE7_V)<<(DPORT_DMMU_TABLE7_S)) +#define DPORT_DMMU_TABLE7_V 0x7F +#define DPORT_DMMU_TABLE7_S 0 + +#define DPORT_DMMU_TABLE8_REG (DR_REG_DPORT_BASE + 0x564) +/* DPORT_DMMU_TABLE8 : R/W ;bitpos:[6:0] ;default: 7'd8 ; */ +/*description: */ +#define DPORT_DMMU_TABLE8 0x0000007F +#define DPORT_DMMU_TABLE8_M ((DPORT_DMMU_TABLE8_V)<<(DPORT_DMMU_TABLE8_S)) +#define DPORT_DMMU_TABLE8_V 0x7F +#define DPORT_DMMU_TABLE8_S 0 + +#define DPORT_DMMU_TABLE9_REG (DR_REG_DPORT_BASE + 0x568) +/* DPORT_DMMU_TABLE9 : R/W ;bitpos:[6:0] ;default: 7'd9 ; */ +/*description: */ +#define DPORT_DMMU_TABLE9 0x0000007F +#define DPORT_DMMU_TABLE9_M ((DPORT_DMMU_TABLE9_V)<<(DPORT_DMMU_TABLE9_S)) +#define DPORT_DMMU_TABLE9_V 0x7F +#define DPORT_DMMU_TABLE9_S 0 + +#define DPORT_DMMU_TABLE10_REG (DR_REG_DPORT_BASE + 0x56C) +/* DPORT_DMMU_TABLE10 : R/W ;bitpos:[6:0] ;default: 7'd10 ; */ +/*description: */ +#define DPORT_DMMU_TABLE10 0x0000007F +#define DPORT_DMMU_TABLE10_M ((DPORT_DMMU_TABLE10_V)<<(DPORT_DMMU_TABLE10_S)) +#define DPORT_DMMU_TABLE10_V 0x7F +#define DPORT_DMMU_TABLE10_S 0 + +#define DPORT_DMMU_TABLE11_REG (DR_REG_DPORT_BASE + 0x570) +/* DPORT_DMMU_TABLE11 : R/W ;bitpos:[6:0] ;default: 7'd11 ; */ +/*description: */ +#define DPORT_DMMU_TABLE11 0x0000007F +#define DPORT_DMMU_TABLE11_M ((DPORT_DMMU_TABLE11_V)<<(DPORT_DMMU_TABLE11_S)) +#define DPORT_DMMU_TABLE11_V 0x7F +#define DPORT_DMMU_TABLE11_S 0 + +#define DPORT_DMMU_TABLE12_REG (DR_REG_DPORT_BASE + 0x574) +/* DPORT_DMMU_TABLE12 : R/W ;bitpos:[6:0] ;default: 7'd12 ; */ +/*description: */ +#define DPORT_DMMU_TABLE12 0x0000007F +#define DPORT_DMMU_TABLE12_M ((DPORT_DMMU_TABLE12_V)<<(DPORT_DMMU_TABLE12_S)) +#define DPORT_DMMU_TABLE12_V 0x7F +#define DPORT_DMMU_TABLE12_S 0 + +#define DPORT_DMMU_TABLE13_REG (DR_REG_DPORT_BASE + 0x578) +/* DPORT_DMMU_TABLE13 : R/W ;bitpos:[6:0] ;default: 7'd13 ; */ +/*description: */ +#define DPORT_DMMU_TABLE13 0x0000007F +#define DPORT_DMMU_TABLE13_M ((DPORT_DMMU_TABLE13_V)<<(DPORT_DMMU_TABLE13_S)) +#define DPORT_DMMU_TABLE13_V 0x7F +#define DPORT_DMMU_TABLE13_S 0 + +#define DPORT_DMMU_TABLE14_REG (DR_REG_DPORT_BASE + 0x57C) +/* DPORT_DMMU_TABLE14 : R/W ;bitpos:[6:0] ;default: 7'd14 ; */ +/*description: */ +#define DPORT_DMMU_TABLE14 0x0000007F +#define DPORT_DMMU_TABLE14_M ((DPORT_DMMU_TABLE14_V)<<(DPORT_DMMU_TABLE14_S)) +#define DPORT_DMMU_TABLE14_V 0x7F +#define DPORT_DMMU_TABLE14_S 0 + +#define DPORT_DMMU_TABLE15_REG (DR_REG_DPORT_BASE + 0x580) +/* DPORT_DMMU_TABLE15 : R/W ;bitpos:[6:0] ;default: 7'd15 ; */ +/*description: */ +#define DPORT_DMMU_TABLE15 0x0000007F +#define DPORT_DMMU_TABLE15_M ((DPORT_DMMU_TABLE15_V)<<(DPORT_DMMU_TABLE15_S)) +#define DPORT_DMMU_TABLE15_V 0x7F +#define DPORT_DMMU_TABLE15_S 0 + +#define DPORT_PRO_INTRUSION_CTRL_REG (DR_REG_DPORT_BASE + 0x584) +/* DPORT_PRO_INTRUSION_RECORD_RESET_N : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_PRO_INTRUSION_RECORD_RESET_N (BIT(0)) +#define DPORT_PRO_INTRUSION_RECORD_RESET_N_M (BIT(0)) +#define DPORT_PRO_INTRUSION_RECORD_RESET_N_V 0x1 +#define DPORT_PRO_INTRUSION_RECORD_RESET_N_S 0 + +#define DPORT_PRO_INTRUSION_STATUS_REG (DR_REG_DPORT_BASE + 0x588) +/* DPORT_PRO_INTRUSION_RECORD : RO ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: */ +#define DPORT_PRO_INTRUSION_RECORD 0x0000000F +#define DPORT_PRO_INTRUSION_RECORD_M ((DPORT_PRO_INTRUSION_RECORD_V)<<(DPORT_PRO_INTRUSION_RECORD_S)) +#define DPORT_PRO_INTRUSION_RECORD_V 0xF +#define DPORT_PRO_INTRUSION_RECORD_S 0 + +#define DPORT_APP_INTRUSION_CTRL_REG (DR_REG_DPORT_BASE + 0x58C) +/* DPORT_APP_INTRUSION_RECORD_RESET_N : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_APP_INTRUSION_RECORD_RESET_N (BIT(0)) +#define DPORT_APP_INTRUSION_RECORD_RESET_N_M (BIT(0)) +#define DPORT_APP_INTRUSION_RECORD_RESET_N_V 0x1 +#define DPORT_APP_INTRUSION_RECORD_RESET_N_S 0 + +#define DPORT_APP_INTRUSION_STATUS_REG (DR_REG_DPORT_BASE + 0x590) +/* DPORT_APP_INTRUSION_RECORD : RO ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: */ +#define DPORT_APP_INTRUSION_RECORD 0x0000000F +#define DPORT_APP_INTRUSION_RECORD_M ((DPORT_APP_INTRUSION_RECORD_V)<<(DPORT_APP_INTRUSION_RECORD_S)) +#define DPORT_APP_INTRUSION_RECORD_V 0xF +#define DPORT_APP_INTRUSION_RECORD_S 0 + +#define DPORT_FRONT_END_MEM_PD_REG (DR_REG_DPORT_BASE + 0x594) +/* DPORT_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_PBUS_MEM_FORCE_PD (BIT(3)) +#define DPORT_PBUS_MEM_FORCE_PD_M (BIT(3)) +#define DPORT_PBUS_MEM_FORCE_PD_V 0x1 +#define DPORT_PBUS_MEM_FORCE_PD_S 3 +/* DPORT_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_PBUS_MEM_FORCE_PU (BIT(2)) +#define DPORT_PBUS_MEM_FORCE_PU_M (BIT(2)) +#define DPORT_PBUS_MEM_FORCE_PU_V 0x1 +#define DPORT_PBUS_MEM_FORCE_PU_S 2 +/* DPORT_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_AGC_MEM_FORCE_PD (BIT(1)) +#define DPORT_AGC_MEM_FORCE_PD_M (BIT(1)) +#define DPORT_AGC_MEM_FORCE_PD_V 0x1 +#define DPORT_AGC_MEM_FORCE_PD_S 1 +/* DPORT_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_AGC_MEM_FORCE_PU (BIT(0)) +#define DPORT_AGC_MEM_FORCE_PU_M (BIT(0)) +#define DPORT_AGC_MEM_FORCE_PU_V 0x1 +#define DPORT_AGC_MEM_FORCE_PU_S 0 + +#define DPORT_MMU_IA_INT_EN_REG (DR_REG_DPORT_BASE + 0x598) +/* DPORT_MMU_IA_INT_EN : R/W ;bitpos:[23:0] ;default: 24'b0 ; */ +/*description: */ +#define DPORT_MMU_IA_INT_EN 0x00FFFFFF +#define DPORT_MMU_IA_INT_EN_M ((DPORT_MMU_IA_INT_EN_V)<<(DPORT_MMU_IA_INT_EN_S)) +#define DPORT_MMU_IA_INT_EN_V 0xFFFFFF +#define DPORT_MMU_IA_INT_EN_S 0 + +#define DPORT_MPU_IA_INT_EN_REG (DR_REG_DPORT_BASE + 0x59C) +/* DPORT_MPU_IA_INT_EN : R/W ;bitpos:[16:0] ;default: 17'b0 ; */ +/*description: */ +#define DPORT_MPU_IA_INT_EN 0x0001FFFF +#define DPORT_MPU_IA_INT_EN_M ((DPORT_MPU_IA_INT_EN_V)<<(DPORT_MPU_IA_INT_EN_S)) +#define DPORT_MPU_IA_INT_EN_V 0x1FFFF +#define DPORT_MPU_IA_INT_EN_S 0 + +#define DPORT_CACHE_IA_INT_EN_REG (DR_REG_DPORT_BASE + 0x5A0) +/* DPORT_CACHE_IA_INT_EN : R/W ;bitpos:[27:0] ;default: 28'b0 ; */ +/*description: */ +#define DPORT_CACHE_IA_INT_EN 0x0FFFFFFF +#define DPORT_CACHE_IA_INT_EN_M ((DPORT_CACHE_IA_INT_EN_V)<<(DPORT_CACHE_IA_INT_EN_S)) +#define DPORT_CACHE_IA_INT_EN_V 0xFFFFFFF +#define DPORT_CACHE_IA_INT_EN_S 0 + +#define DPORT_SECURE_BOOT_CTRL_REG (DR_REG_DPORT_BASE + 0x5A4) +/* DPORT_SW_BOOTLOADER_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_SW_BOOTLOADER_SEL (BIT(0)) +#define DPORT_SW_BOOTLOADER_SEL_M (BIT(0)) +#define DPORT_SW_BOOTLOADER_SEL_V 0x1 +#define DPORT_SW_BOOTLOADER_SEL_S 0 + +#define DPORT_SPI_DMA_CHAN_SEL_REG (DR_REG_DPORT_BASE + 0x5A8) +/* DPORT_SPI3_DMA_CHAN_SEL : R/W ;bitpos:[5:4] ;default: 2'b00 ; */ +/*description: */ +#define DPORT_SPI3_DMA_CHAN_SEL 0x00000003 +#define DPORT_SPI3_DMA_CHAN_SEL_M ((DPORT_SPI3_DMA_CHAN_SEL_V)<<(DPORT_SPI3_DMA_CHAN_SEL_S)) +#define DPORT_SPI3_DMA_CHAN_SEL_V 0x3 +#define DPORT_SPI3_DMA_CHAN_SEL_S 4 +/* DPORT_SPI2_DMA_CHAN_SEL : R/W ;bitpos:[3:2] ;default: 2'b00 ; */ +/*description: */ +#define DPORT_SPI2_DMA_CHAN_SEL 0x00000003 +#define DPORT_SPI2_DMA_CHAN_SEL_M ((DPORT_SPI2_DMA_CHAN_SEL_V)<<(DPORT_SPI2_DMA_CHAN_SEL_S)) +#define DPORT_SPI2_DMA_CHAN_SEL_V 0x3 +#define DPORT_SPI2_DMA_CHAN_SEL_S 2 +/* DPORT_SPI1_DMA_CHAN_SEL : R/W ;bitpos:[1:0] ;default: 2'b00 ; */ +/*description: */ +#define DPORT_SPI1_DMA_CHAN_SEL 0x00000003 +#define DPORT_SPI1_DMA_CHAN_SEL_M ((DPORT_SPI1_DMA_CHAN_SEL_V)<<(DPORT_SPI1_DMA_CHAN_SEL_S)) +#define DPORT_SPI1_DMA_CHAN_SEL_V 0x3 +#define DPORT_SPI1_DMA_CHAN_SEL_S 0 + +#define DPORT_PRO_VECBASE_CTRL_REG (DR_REG_DPORT_BASE + 0x5AC) +/* DPORT_PRO_OUT_VECBASE_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: */ +#define DPORT_PRO_OUT_VECBASE_SEL 0x00000003 +#define DPORT_PRO_OUT_VECBASE_SEL_M ((DPORT_PRO_OUT_VECBASE_SEL_V)<<(DPORT_PRO_OUT_VECBASE_SEL_S)) +#define DPORT_PRO_OUT_VECBASE_SEL_V 0x3 +#define DPORT_PRO_OUT_VECBASE_SEL_S 0 + +#define DPORT_PRO_VECBASE_SET_REG (DR_REG_DPORT_BASE + 0x5B0) +/* DPORT_PRO_OUT_VECBASE_REG : R/W ;bitpos:[21:0] ;default: 22'b0 ; */ +/*description: */ +#define DPORT_PRO_OUT_VECBASE_REG 0x003FFFFF +#define DPORT_PRO_OUT_VECBASE_REG_M ((DPORT_PRO_OUT_VECBASE_REG_V)<<(DPORT_PRO_OUT_VECBASE_REG_S)) +#define DPORT_PRO_OUT_VECBASE_REG_V 0x3FFFFF +#define DPORT_PRO_OUT_VECBASE_REG_S 0 + +#define DPORT_APP_VECBASE_CTRL_REG (DR_REG_DPORT_BASE + 0x5B4) +/* DPORT_APP_OUT_VECBASE_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: */ +#define DPORT_APP_OUT_VECBASE_SEL 0x00000003 +#define DPORT_APP_OUT_VECBASE_SEL_M ((DPORT_APP_OUT_VECBASE_SEL_V)<<(DPORT_APP_OUT_VECBASE_SEL_S)) +#define DPORT_APP_OUT_VECBASE_SEL_V 0x3 +#define DPORT_APP_OUT_VECBASE_SEL_S 0 + +#define DPORT_APP_VECBASE_SET_REG (DR_REG_DPORT_BASE + 0x5B8) +/* DPORT_APP_OUT_VECBASE_REG : R/W ;bitpos:[21:0] ;default: 22'b0 ; */ +/*description: */ +#define DPORT_APP_OUT_VECBASE_REG 0x003FFFFF +#define DPORT_APP_OUT_VECBASE_REG_M ((DPORT_APP_OUT_VECBASE_REG_V)<<(DPORT_APP_OUT_VECBASE_REG_S)) +#define DPORT_APP_OUT_VECBASE_REG_V 0x3FFFFF +#define DPORT_APP_OUT_VECBASE_REG_S 0 + +#define DPORT_DATE_REG (DR_REG_DPORT_BASE + 0xFFC) +/* DPORT_DATE : R/W ;bitpos:[27:0] ;default: 28'h1605190 ; */ +/*description: */ +#define DPORT_DATE 0x0FFFFFFF +#define DPORT_DATE_M ((DPORT_DATE_V)<<(DPORT_DATE_S)) +#define DPORT_DATE_V 0xFFFFFFF +#define DPORT_DATE_S 0 +#define DPORT_DPORT_DATE_VERSION 0x1605190 + + + + +#endif /*_SOC_DPORT_REG_H_ */ + + diff --git a/tools/sdk/include/esp32/soc/efuse_reg.h b/tools/sdk/include/esp32/soc/efuse_reg.h new file mode 100644 index 00000000..a0f0a07d --- /dev/null +++ b/tools/sdk/include/esp32/soc/efuse_reg.h @@ -0,0 +1,986 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_EFUSE_REG_H_ +#define _SOC_EFUSE_REG_H_ + + +#include "soc.h" +#define EFUSE_BLK0_RDATA0_REG (DR_REG_EFUSE_BASE + 0x000) +/* EFUSE_RD_FLASH_CRYPT_CNT : RO ;bitpos:[27:20] ;default: 8'b0 ; */ +/*description: read for flash_crypt_cnt*/ +#define EFUSE_RD_FLASH_CRYPT_CNT 0x000000FF +#define EFUSE_RD_FLASH_CRYPT_CNT_M ((EFUSE_RD_FLASH_CRYPT_CNT_V)<<(EFUSE_RD_FLASH_CRYPT_CNT_S)) +#define EFUSE_RD_FLASH_CRYPT_CNT_V 0xFF +#define EFUSE_RD_FLASH_CRYPT_CNT_S 20 +/* EFUSE_RD_EFUSE_RD_DIS : RO ;bitpos:[19:16] ;default: 4'b0 ; */ +/*description: read for efuse_rd_disable*/ +#define EFUSE_RD_EFUSE_RD_DIS 0x0000000F +#define EFUSE_RD_EFUSE_RD_DIS_M ((EFUSE_RD_EFUSE_RD_DIS_V)<<(EFUSE_RD_EFUSE_RD_DIS_S)) +#define EFUSE_RD_EFUSE_RD_DIS_V 0xF +#define EFUSE_RD_EFUSE_RD_DIS_S 16 +/* EFUSE_RD_EFUSE_WR_DIS : RO ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: read for efuse_wr_disable*/ +#define EFUSE_RD_EFUSE_WR_DIS 0x0000FFFF +#define EFUSE_RD_EFUSE_WR_DIS_M ((EFUSE_RD_EFUSE_WR_DIS_V)<<(EFUSE_RD_EFUSE_WR_DIS_S)) +#define EFUSE_RD_EFUSE_WR_DIS_V 0xFFFF +#define EFUSE_RD_EFUSE_WR_DIS_S 0 + +#define EFUSE_BLK0_RDATA1_REG (DR_REG_EFUSE_BASE + 0x004) +/* EFUSE_RD_WIFI_MAC_CRC_LOW : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: read for low 32bit WIFI_MAC_Address*/ +#define EFUSE_RD_WIFI_MAC_CRC_LOW 0xFFFFFFFF +#define EFUSE_RD_WIFI_MAC_CRC_LOW_M ((EFUSE_RD_WIFI_MAC_CRC_LOW_V)<<(EFUSE_RD_WIFI_MAC_CRC_LOW_S)) +#define EFUSE_RD_WIFI_MAC_CRC_LOW_V 0xFFFFFFFF +#define EFUSE_RD_WIFI_MAC_CRC_LOW_S 0 + +#define EFUSE_BLK0_RDATA2_REG (DR_REG_EFUSE_BASE + 0x008) +/* EFUSE_RD_WIFI_MAC_CRC_HIGH : RO ;bitpos:[23:0] ;default: 24'b0 ; */ +/*description: read for high 24bit WIFI_MAC_Address*/ +#define EFUSE_RD_WIFI_MAC_CRC_HIGH 0x00FFFFFF +#define EFUSE_RD_WIFI_MAC_CRC_HIGH_M ((EFUSE_RD_WIFI_MAC_CRC_HIGH_V)<<(EFUSE_RD_WIFI_MAC_CRC_HIGH_S)) +#define EFUSE_RD_WIFI_MAC_CRC_HIGH_V 0xFFFFFF +#define EFUSE_RD_WIFI_MAC_CRC_HIGH_S 0 + +#define EFUSE_BLK0_RDATA3_REG (DR_REG_EFUSE_BASE + 0x00c) +/* EFUSE_RD_CHIP_VER_RESERVE : RO ;bitpos:[16:9] ;default: 8'b0 ; */ +/*description: */ +#define EFUSE_RD_CHIP_VER_RESERVE 0x000000FF +#define EFUSE_RD_CHIP_VER_RESERVE_M ((EFUSE_RD_CHIP_VER_RESERVE_V)<<(EFUSE_RD_CHIP_VER_RESERVE_S)) +#define EFUSE_RD_CHIP_VER_RESERVE_V 0xFF +#define EFUSE_RD_CHIP_VER_RESERVE_S 9 +/* EFUSE_RD_SPI_PAD_CONFIG_HD : RO ;bitpos:[8:4] ;default: 5'b0 ; */ +/*description: read for SPI_pad_config_hd*/ +#define EFUSE_RD_SPI_PAD_CONFIG_HD 0x0000001F +#define EFUSE_RD_SPI_PAD_CONFIG_HD_M ((EFUSE_RD_SPI_PAD_CONFIG_HD_V)<<(EFUSE_RD_SPI_PAD_CONFIG_HD_S)) +#define EFUSE_RD_SPI_PAD_CONFIG_HD_V 0x1F +#define EFUSE_RD_SPI_PAD_CONFIG_HD_S 4 +/* EFUSE_RD_CHIP_VER_DIS_CACHE : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define EFUSE_RD_CHIP_VER_DIS_CACHE (BIT(3)) +#define EFUSE_RD_CHIP_VER_DIS_CACHE_M (BIT(3)) +#define EFUSE_RD_CHIP_VER_DIS_CACHE_V 0x1 +#define EFUSE_RD_CHIP_VER_DIS_CACHE_S 3 +/* EFUSE_RD_CHIP_VER_32PAD : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define EFUSE_RD_CHIP_VER_32PAD (BIT(2)) +#define EFUSE_RD_CHIP_VER_32PAD_M (BIT(2)) +#define EFUSE_RD_CHIP_VER_32PAD_V 0x1 +#define EFUSE_RD_CHIP_VER_32PAD_S 2 +/* EFUSE_RD_CHIP_VER_DIS_BT : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define EFUSE_RD_CHIP_VER_DIS_BT (BIT(1)) +#define EFUSE_RD_CHIP_VER_DIS_BT_M (BIT(1)) +#define EFUSE_RD_CHIP_VER_DIS_BT_V 0x1 +#define EFUSE_RD_CHIP_VER_DIS_BT_S 1 +/* EFUSE_RD_CHIP_VER_DIS_APP_CPU : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define EFUSE_RD_CHIP_VER_DIS_APP_CPU (BIT(0)) +#define EFUSE_RD_CHIP_VER_DIS_APP_CPU_M (BIT(0)) +#define EFUSE_RD_CHIP_VER_DIS_APP_CPU_V 0x1 +#define EFUSE_RD_CHIP_VER_DIS_APP_CPU_S 0 + +#define EFUSE_BLK0_RDATA4_REG (DR_REG_EFUSE_BASE + 0x010) +/* EFUSE_RD_SDIO_FORCE : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: read for sdio_force*/ +#define EFUSE_RD_SDIO_FORCE (BIT(16)) +#define EFUSE_RD_SDIO_FORCE_M (BIT(16)) +#define EFUSE_RD_SDIO_FORCE_V 0x1 +#define EFUSE_RD_SDIO_FORCE_S 16 +/* EFUSE_RD_SDIO_TIEH : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: read for SDIO_TIEH*/ +#define EFUSE_RD_SDIO_TIEH (BIT(15)) +#define EFUSE_RD_SDIO_TIEH_M (BIT(15)) +#define EFUSE_RD_SDIO_TIEH_V 0x1 +#define EFUSE_RD_SDIO_TIEH_S 15 +/* EFUSE_RD_XPD_SDIO_REG : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: read for XPD_SDIO_REG*/ +#define EFUSE_RD_XPD_SDIO_REG (BIT(14)) +#define EFUSE_RD_XPD_SDIO_REG_M (BIT(14)) +#define EFUSE_RD_XPD_SDIO_REG_V 0x1 +#define EFUSE_RD_XPD_SDIO_REG_S 14 +/* EFUSE_RD_SDIO_DREFL : RO ;bitpos:[13:12] ;default: 2'b0 ; */ +/*description: */ +#define EFUSE_RD_SDIO_DREFL 0x00000003 +#define EFUSE_RD_SDIO_DREFL_M ((EFUSE_RD_SDIO_DREFL_V)<<(EFUSE_RD_SDIO_DREFL_S)) +#define EFUSE_RD_SDIO_DREFL_V 0x3 +#define EFUSE_RD_SDIO_DREFL_S 12 +/* EFUSE_RD_SDIO_DREFM : RO ;bitpos:[11:10] ;default: 2'b0 ; */ +/*description: */ +#define EFUSE_RD_SDIO_DREFM 0x00000003 +#define EFUSE_RD_SDIO_DREFM_M ((EFUSE_RD_SDIO_DREFM_V)<<(EFUSE_RD_SDIO_DREFM_S)) +#define EFUSE_RD_SDIO_DREFM_V 0x3 +#define EFUSE_RD_SDIO_DREFM_S 10 +/* EFUSE_RD_SDIO_DREFH : RO ;bitpos:[9:8] ;default: 2'b0 ; */ +/*description: */ +#define EFUSE_RD_SDIO_DREFH 0x00000003 +#define EFUSE_RD_SDIO_DREFH_M ((EFUSE_RD_SDIO_DREFH_V)<<(EFUSE_RD_SDIO_DREFH_S)) +#define EFUSE_RD_SDIO_DREFH_V 0x3 +#define EFUSE_RD_SDIO_DREFH_S 8 +/* EFUSE_RD_CK8M_FREQ : RO ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: */ +#define EFUSE_RD_CK8M_FREQ 0x000000FF +#define EFUSE_RD_CK8M_FREQ_M ((EFUSE_RD_CK8M_FREQ_V)<<(EFUSE_RD_CK8M_FREQ_S)) +#define EFUSE_RD_CK8M_FREQ_V 0xFF +#define EFUSE_RD_CK8M_FREQ_S 0 + +#define EFUSE_BLK0_RDATA5_REG (DR_REG_EFUSE_BASE + 0x014) +/* EFUSE_RD_FLASH_CRYPT_CONFIG : RO ;bitpos:[31:28] ;default: 4'b0 ; */ +/*description: read for flash_crypt_config*/ +#define EFUSE_RD_FLASH_CRYPT_CONFIG 0x0000000F +#define EFUSE_RD_FLASH_CRYPT_CONFIG_M ((EFUSE_RD_FLASH_CRYPT_CONFIG_V)<<(EFUSE_RD_FLASH_CRYPT_CONFIG_S)) +#define EFUSE_RD_FLASH_CRYPT_CONFIG_V 0xF +#define EFUSE_RD_FLASH_CRYPT_CONFIG_S 28 +/* EFUSE_RD_INST_CONFIG : RO ;bitpos:[27:20] ;default: 8'b0 ; */ +/*description: */ +#define EFUSE_RD_INST_CONFIG 0x000000FF +#define EFUSE_RD_INST_CONFIG_M ((EFUSE_RD_INST_CONFIG_V)<<(EFUSE_RD_INST_CONFIG_S)) +#define EFUSE_RD_INST_CONFIG_V 0xFF +#define EFUSE_RD_INST_CONFIG_S 20 +/* EFUSE_RD_SPI_PAD_CONFIG_CS0 : RO ;bitpos:[19:15] ;default: 5'b0 ; */ +/*description: read for SPI_pad_config_cs0*/ +#define EFUSE_RD_SPI_PAD_CONFIG_CS0 0x0000001F +#define EFUSE_RD_SPI_PAD_CONFIG_CS0_M ((EFUSE_RD_SPI_PAD_CONFIG_CS0_V)<<(EFUSE_RD_SPI_PAD_CONFIG_CS0_S)) +#define EFUSE_RD_SPI_PAD_CONFIG_CS0_V 0x1F +#define EFUSE_RD_SPI_PAD_CONFIG_CS0_S 15 +/* EFUSE_RD_SPI_PAD_CONFIG_D : RO ;bitpos:[14:10] ;default: 5'b0 ; */ +/*description: read for SPI_pad_config_d*/ +#define EFUSE_RD_SPI_PAD_CONFIG_D 0x0000001F +#define EFUSE_RD_SPI_PAD_CONFIG_D_M ((EFUSE_RD_SPI_PAD_CONFIG_D_V)<<(EFUSE_RD_SPI_PAD_CONFIG_D_S)) +#define EFUSE_RD_SPI_PAD_CONFIG_D_V 0x1F +#define EFUSE_RD_SPI_PAD_CONFIG_D_S 10 +/* EFUSE_RD_SPI_PAD_CONFIG_Q : RO ;bitpos:[9:5] ;default: 5'b0 ; */ +/*description: read for SPI_pad_config_q*/ +#define EFUSE_RD_SPI_PAD_CONFIG_Q 0x0000001F +#define EFUSE_RD_SPI_PAD_CONFIG_Q_M ((EFUSE_RD_SPI_PAD_CONFIG_Q_V)<<(EFUSE_RD_SPI_PAD_CONFIG_Q_S)) +#define EFUSE_RD_SPI_PAD_CONFIG_Q_V 0x1F +#define EFUSE_RD_SPI_PAD_CONFIG_Q_S 5 +/* EFUSE_RD_SPI_PAD_CONFIG_CLK : RO ;bitpos:[4:0] ;default: 5'b0 ; */ +/*description: read for SPI_pad_config_clk*/ +#define EFUSE_RD_SPI_PAD_CONFIG_CLK 0x0000001F +#define EFUSE_RD_SPI_PAD_CONFIG_CLK_M ((EFUSE_RD_SPI_PAD_CONFIG_CLK_V)<<(EFUSE_RD_SPI_PAD_CONFIG_CLK_S)) +#define EFUSE_RD_SPI_PAD_CONFIG_CLK_V 0x1F +#define EFUSE_RD_SPI_PAD_CONFIG_CLK_S 0 + +#define EFUSE_BLK0_RDATA6_REG (DR_REG_EFUSE_BASE + 0x018) +/* EFUSE_RD_KEY_STATUS : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: read for key_status*/ +#define EFUSE_RD_KEY_STATUS (BIT(10)) +#define EFUSE_RD_KEY_STATUS_M (BIT(10)) +#define EFUSE_RD_KEY_STATUS_V 0x1 +#define EFUSE_RD_KEY_STATUS_S 10 +/* EFUSE_RD_DISABLE_DL_CACHE : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: read for download_dis_cache*/ +#define EFUSE_RD_DISABLE_DL_CACHE (BIT(9)) +#define EFUSE_RD_DISABLE_DL_CACHE_M (BIT(9)) +#define EFUSE_RD_DISABLE_DL_CACHE_V 0x1 +#define EFUSE_RD_DISABLE_DL_CACHE_S 9 +/* EFUSE_RD_DISABLE_DL_DECRYPT : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: read for download_dis_decrypt*/ +#define EFUSE_RD_DISABLE_DL_DECRYPT (BIT(8)) +#define EFUSE_RD_DISABLE_DL_DECRYPT_M (BIT(8)) +#define EFUSE_RD_DISABLE_DL_DECRYPT_V 0x1 +#define EFUSE_RD_DISABLE_DL_DECRYPT_S 8 +/* EFUSE_RD_DISABLE_DL_ENCRYPT : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: read for download_dis_encrypt*/ +#define EFUSE_RD_DISABLE_DL_ENCRYPT (BIT(7)) +#define EFUSE_RD_DISABLE_DL_ENCRYPT_M (BIT(7)) +#define EFUSE_RD_DISABLE_DL_ENCRYPT_V 0x1 +#define EFUSE_RD_DISABLE_DL_ENCRYPT_S 7 +/* EFUSE_RD_DISABLE_JTAG : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: read for JTAG_disable*/ +#define EFUSE_RD_DISABLE_JTAG (BIT(6)) +#define EFUSE_RD_DISABLE_JTAG_M (BIT(6)) +#define EFUSE_RD_DISABLE_JTAG_V 0x1 +#define EFUSE_RD_DISABLE_JTAG_S 6 +/* EFUSE_RD_ABS_DONE_1 : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: read for abstract_done_1*/ +#define EFUSE_RD_ABS_DONE_1 (BIT(5)) +#define EFUSE_RD_ABS_DONE_1_M (BIT(5)) +#define EFUSE_RD_ABS_DONE_1_V 0x1 +#define EFUSE_RD_ABS_DONE_1_S 5 +/* EFUSE_RD_ABS_DONE_0 : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: read for abstract_done_0*/ +#define EFUSE_RD_ABS_DONE_0 (BIT(4)) +#define EFUSE_RD_ABS_DONE_0_M (BIT(4)) +#define EFUSE_RD_ABS_DONE_0_V 0x1 +#define EFUSE_RD_ABS_DONE_0_S 4 +/* EFUSE_RD_DISABLE_SDIO_HOST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define EFUSE_RD_DISABLE_SDIO_HOST (BIT(3)) +#define EFUSE_RD_DISABLE_SDIO_HOST_M (BIT(3)) +#define EFUSE_RD_DISABLE_SDIO_HOST_V 0x1 +#define EFUSE_RD_DISABLE_SDIO_HOST_S 3 +/* EFUSE_RD_CONSOLE_DEBUG_DISABLE : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: read for console_debug_disable*/ +#define EFUSE_RD_CONSOLE_DEBUG_DISABLE (BIT(2)) +#define EFUSE_RD_CONSOLE_DEBUG_DISABLE_M (BIT(2)) +#define EFUSE_RD_CONSOLE_DEBUG_DISABLE_V 0x1 +#define EFUSE_RD_CONSOLE_DEBUG_DISABLE_S 2 +/* EFUSE_RD_CODING_SCHEME : RO ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: read for coding_scheme*/ +#define EFUSE_RD_CODING_SCHEME 0x00000003 +#define EFUSE_RD_CODING_SCHEME_M ((EFUSE_RD_CODING_SCHEME_V)<<(EFUSE_RD_CODING_SCHEME_S)) +#define EFUSE_RD_CODING_SCHEME_V 0x3 +#define EFUSE_RD_CODING_SCHEME_S 0 + +#define EFUSE_BLK0_WDATA0_REG (DR_REG_EFUSE_BASE + 0x01c) +/* EFUSE_FLASH_CRYPT_CNT : R/W ;bitpos:[27:20] ;default: 8'b0 ; */ +/*description: program for flash_crypt_cnt*/ +#define EFUSE_FLASH_CRYPT_CNT 0x000000FF +#define EFUSE_FLASH_CRYPT_CNT_M ((EFUSE_FLASH_CRYPT_CNT_V)<<(EFUSE_FLASH_CRYPT_CNT_S)) +#define EFUSE_FLASH_CRYPT_CNT_V 0xFF +#define EFUSE_FLASH_CRYPT_CNT_S 20 +/* EFUSE_RD_DIS : R/W ;bitpos:[19:16] ;default: 4'b0 ; */ +/*description: program for efuse_rd_disable*/ +#define EFUSE_RD_DIS 0x0000000F +#define EFUSE_RD_DIS_M ((EFUSE_RD_DIS_V)<<(EFUSE_RD_DIS_S)) +#define EFUSE_RD_DIS_V 0xF +#define EFUSE_RD_DIS_S 16 +/* EFUSE_WR_DIS : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: program for efuse_wr_disable*/ +#define EFUSE_WR_DIS 0x0000FFFF +#define EFUSE_WR_DIS_M ((EFUSE_WR_DIS_V)<<(EFUSE_WR_DIS_S)) +#define EFUSE_WR_DIS_V 0xFFFF +#define EFUSE_WR_DIS_S 0 + +#define EFUSE_BLK0_WDATA1_REG (DR_REG_EFUSE_BASE + 0x020) +/* EFUSE_WIFI_MAC_CRC_LOW : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: program for low 32bit WIFI_MAC_Address*/ +#define EFUSE_WIFI_MAC_CRC_LOW 0xFFFFFFFF +#define EFUSE_WIFI_MAC_CRC_LOW_M ((EFUSE_WIFI_MAC_CRC_LOW_V)<<(EFUSE_WIFI_MAC_CRC_LOW_S)) +#define EFUSE_WIFI_MAC_CRC_LOW_V 0xFFFFFFFF +#define EFUSE_WIFI_MAC_CRC_LOW_S 0 + +#define EFUSE_BLK0_WDATA2_REG (DR_REG_EFUSE_BASE + 0x024) +/* EFUSE_WIFI_MAC_CRC_HIGH : R/W ;bitpos:[23:0] ;default: 24'b0 ; */ +/*description: program for high 24bit WIFI_MAC_Address*/ +#define EFUSE_WIFI_MAC_CRC_HIGH 0x00FFFFFF +#define EFUSE_WIFI_MAC_CRC_HIGH_M ((EFUSE_WIFI_MAC_CRC_HIGH_V)<<(EFUSE_WIFI_MAC_CRC_HIGH_S)) +#define EFUSE_WIFI_MAC_CRC_HIGH_V 0xFFFFFF +#define EFUSE_WIFI_MAC_CRC_HIGH_S 0 + +#define EFUSE_BLK0_WDATA3_REG (DR_REG_EFUSE_BASE + 0x028) +/* EFUSE_CHIP_VER_RESERVE : R/W ;bitpos:[16:9] ;default: 8'b0 ; */ +/*description: */ +#define EFUSE_CHIP_VER_RESERVE 0x000000FF +#define EFUSE_CHIP_VER_RESERVE_M ((EFUSE_CHIP_VER_RESERVE_V)<<(EFUSE_CHIP_VER_RESERVE_S)) +#define EFUSE_CHIP_VER_RESERVE_V 0xFF +#define EFUSE_CHIP_VER_RESERVE_S 9 +/* EFUSE_SPI_PAD_CONFIG_HD : R/W ;bitpos:[8:4] ;default: 5'b0 ; */ +/*description: program for SPI_pad_config_hd*/ +#define EFUSE_SPI_PAD_CONFIG_HD 0x0000001F +#define EFUSE_SPI_PAD_CONFIG_HD_M ((EFUSE_SPI_PAD_CONFIG_HD_V)<<(EFUSE_SPI_PAD_CONFIG_HD_S)) +#define EFUSE_SPI_PAD_CONFIG_HD_V 0x1F +#define EFUSE_SPI_PAD_CONFIG_HD_S 4 +/* EFUSE_CHIP_VER_DIS_CACHE : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define EFUSE_CHIP_VER_DIS_CACHE (BIT(3)) +#define EFUSE_CHIP_VER_DIS_CACHE_M (BIT(3)) +#define EFUSE_CHIP_VER_DIS_CACHE_V 0x1 +#define EFUSE_CHIP_VER_DIS_CACHE_S 3 +/* EFUSE_CHIP_VER_32PAD : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define EFUSE_CHIP_VER_32PAD (BIT(2)) +#define EFUSE_CHIP_VER_32PAD_M (BIT(2)) +#define EFUSE_CHIP_VER_32PAD_V 0x1 +#define EFUSE_CHIP_VER_32PAD_S 2 +/* EFUSE_CHIP_VER_DIS_BT : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define EFUSE_CHIP_VER_DIS_BT (BIT(1)) +#define EFUSE_CHIP_VER_DIS_BT_M (BIT(1)) +#define EFUSE_CHIP_VER_DIS_BT_V 0x1 +#define EFUSE_CHIP_VER_DIS_BT_S 1 +/* EFUSE_CHIP_VER_DIS_APP_CPU : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define EFUSE_CHIP_VER_DIS_APP_CPU (BIT(0)) +#define EFUSE_CHIP_VER_DIS_APP_CPU_M (BIT(0)) +#define EFUSE_CHIP_VER_DIS_APP_CPU_V 0x1 +#define EFUSE_CHIP_VER_DIS_APP_CPU_S 0 + +#define EFUSE_BLK0_WDATA4_REG (DR_REG_EFUSE_BASE + 0x02c) +/* EFUSE_SDIO_FORCE : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: program for sdio_force*/ +#define EFUSE_SDIO_FORCE (BIT(16)) +#define EFUSE_SDIO_FORCE_M (BIT(16)) +#define EFUSE_SDIO_FORCE_V 0x1 +#define EFUSE_SDIO_FORCE_S 16 +/* EFUSE_SDIO_TIEH : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: program for SDIO_TIEH*/ +#define EFUSE_SDIO_TIEH (BIT(15)) +#define EFUSE_SDIO_TIEH_M (BIT(15)) +#define EFUSE_SDIO_TIEH_V 0x1 +#define EFUSE_SDIO_TIEH_S 15 +/* EFUSE_XPD_SDIO_REG : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: program for XPD_SDIO_REG*/ +#define EFUSE_XPD_SDIO_REG (BIT(14)) +#define EFUSE_XPD_SDIO_REG_M (BIT(14)) +#define EFUSE_XPD_SDIO_REG_V 0x1 +#define EFUSE_XPD_SDIO_REG_S 14 +/* EFUSE_SDIO_DREFL : R/W ;bitpos:[13:12] ;default: 2'b0 ; */ +/*description: */ +#define EFUSE_SDIO_DREFL 0x00000003 +#define EFUSE_SDIO_DREFL_M ((EFUSE_SDIO_DREFL_V)<<(EFUSE_SDIO_DREFL_S)) +#define EFUSE_SDIO_DREFL_V 0x3 +#define EFUSE_SDIO_DREFL_S 12 +/* EFUSE_SDIO_DREFM : R/W ;bitpos:[11:10] ;default: 2'b0 ; */ +/*description: */ +#define EFUSE_SDIO_DREFM 0x00000003 +#define EFUSE_SDIO_DREFM_M ((EFUSE_SDIO_DREFM_V)<<(EFUSE_SDIO_DREFM_S)) +#define EFUSE_SDIO_DREFM_V 0x3 +#define EFUSE_SDIO_DREFM_S 10 +/* EFUSE_SDIO_DREFH : R/W ;bitpos:[9:8] ;default: 2'b0 ; */ +/*description: */ +#define EFUSE_SDIO_DREFH 0x00000003 +#define EFUSE_SDIO_DREFH_M ((EFUSE_SDIO_DREFH_V)<<(EFUSE_SDIO_DREFH_S)) +#define EFUSE_SDIO_DREFH_V 0x3 +#define EFUSE_SDIO_DREFH_S 8 +/* EFUSE_CK8M_FREQ : R/W ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: */ +#define EFUSE_CK8M_FREQ 0x000000FF +#define EFUSE_CK8M_FREQ_M ((EFUSE_CK8M_FREQ_V)<<(EFUSE_CK8M_FREQ_S)) +#define EFUSE_CK8M_FREQ_V 0xFF +#define EFUSE_CK8M_FREQ_S 0 + +#define EFUSE_BLK0_WDATA5_REG (DR_REG_EFUSE_BASE + 0x030) +/* EFUSE_FLASH_CRYPT_CONFIG : R/W ;bitpos:[31:28] ;default: 4'b0 ; */ +/*description: program for flash_crypt_config*/ +#define EFUSE_FLASH_CRYPT_CONFIG 0x0000000F +#define EFUSE_FLASH_CRYPT_CONFIG_M ((EFUSE_FLASH_CRYPT_CONFIG_V)<<(EFUSE_FLASH_CRYPT_CONFIG_S)) +#define EFUSE_FLASH_CRYPT_CONFIG_V 0xF +#define EFUSE_FLASH_CRYPT_CONFIG_S 28 +/* EFUSE_INST_CONFIG : R/W ;bitpos:[27:20] ;default: 8'b0 ; */ +/*description: */ +#define EFUSE_INST_CONFIG 0x000000FF +#define EFUSE_INST_CONFIG_M ((EFUSE_INST_CONFIG_V)<<(EFUSE_INST_CONFIG_S)) +#define EFUSE_INST_CONFIG_V 0xFF +#define EFUSE_INST_CONFIG_S 20 +/* EFUSE_SPI_PAD_CONFIG_CS0 : R/W ;bitpos:[19:15] ;default: 5'b0 ; */ +/*description: program for SPI_pad_config_cs0*/ +#define EFUSE_SPI_PAD_CONFIG_CS0 0x0000001F +#define EFUSE_SPI_PAD_CONFIG_CS0_M ((EFUSE_SPI_PAD_CONFIG_CS0_V)<<(EFUSE_SPI_PAD_CONFIG_CS0_S)) +#define EFUSE_SPI_PAD_CONFIG_CS0_V 0x1F +#define EFUSE_SPI_PAD_CONFIG_CS0_S 15 +/* EFUSE_SPI_PAD_CONFIG_D : R/W ;bitpos:[14:10] ;default: 5'b0 ; */ +/*description: program for SPI_pad_config_d*/ +#define EFUSE_SPI_PAD_CONFIG_D 0x0000001F +#define EFUSE_SPI_PAD_CONFIG_D_M ((EFUSE_SPI_PAD_CONFIG_D_V)<<(EFUSE_SPI_PAD_CONFIG_D_S)) +#define EFUSE_SPI_PAD_CONFIG_D_V 0x1F +#define EFUSE_SPI_PAD_CONFIG_D_S 10 +/* EFUSE_SPI_PAD_CONFIG_Q : R/W ;bitpos:[9:5] ;default: 5'b0 ; */ +/*description: program for SPI_pad_config_q*/ +#define EFUSE_SPI_PAD_CONFIG_Q 0x0000001F +#define EFUSE_SPI_PAD_CONFIG_Q_M ((EFUSE_SPI_PAD_CONFIG_Q_V)<<(EFUSE_SPI_PAD_CONFIG_Q_S)) +#define EFUSE_SPI_PAD_CONFIG_Q_V 0x1F +#define EFUSE_SPI_PAD_CONFIG_Q_S 5 +/* EFUSE_SPI_PAD_CONFIG_CLK : R/W ;bitpos:[4:0] ;default: 5'b0 ; */ +/*description: program for SPI_pad_config_clk*/ +#define EFUSE_SPI_PAD_CONFIG_CLK 0x0000001F +#define EFUSE_SPI_PAD_CONFIG_CLK_M ((EFUSE_SPI_PAD_CONFIG_CLK_V)<<(EFUSE_SPI_PAD_CONFIG_CLK_S)) +#define EFUSE_SPI_PAD_CONFIG_CLK_V 0x1F +#define EFUSE_SPI_PAD_CONFIG_CLK_S 0 + +#define EFUSE_BLK0_WDATA6_REG (DR_REG_EFUSE_BASE + 0x034) +/* EFUSE_KEY_STATUS : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: program for key_status*/ +#define EFUSE_KEY_STATUS (BIT(10)) +#define EFUSE_KEY_STATUS_M (BIT(10)) +#define EFUSE_KEY_STATUS_V 0x1 +#define EFUSE_KEY_STATUS_S 10 +/* EFUSE_DISABLE_DL_CACHE : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: program for download_dis_cache*/ +#define EFUSE_DISABLE_DL_CACHE (BIT(9)) +#define EFUSE_DISABLE_DL_CACHE_M (BIT(9)) +#define EFUSE_DISABLE_DL_CACHE_V 0x1 +#define EFUSE_DISABLE_DL_CACHE_S 9 +/* EFUSE_DISABLE_DL_DECRYPT : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: program for download_dis_decrypt*/ +#define EFUSE_DISABLE_DL_DECRYPT (BIT(8)) +#define EFUSE_DISABLE_DL_DECRYPT_M (BIT(8)) +#define EFUSE_DISABLE_DL_DECRYPT_V 0x1 +#define EFUSE_DISABLE_DL_DECRYPT_S 8 +/* EFUSE_DISABLE_DL_ENCRYPT : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: program for download_dis_encrypt*/ +#define EFUSE_DISABLE_DL_ENCRYPT (BIT(7)) +#define EFUSE_DISABLE_DL_ENCRYPT_M (BIT(7)) +#define EFUSE_DISABLE_DL_ENCRYPT_V 0x1 +#define EFUSE_DISABLE_DL_ENCRYPT_S 7 +/* EFUSE_DISABLE_JTAG : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: program for JTAG_disable*/ +#define EFUSE_DISABLE_JTAG (BIT(6)) +#define EFUSE_DISABLE_JTAG_M (BIT(6)) +#define EFUSE_DISABLE_JTAG_V 0x1 +#define EFUSE_DISABLE_JTAG_S 6 +/* EFUSE_ABS_DONE_1 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: program for abstract_done_1*/ +#define EFUSE_ABS_DONE_1 (BIT(5)) +#define EFUSE_ABS_DONE_1_M (BIT(5)) +#define EFUSE_ABS_DONE_1_V 0x1 +#define EFUSE_ABS_DONE_1_S 5 +/* EFUSE_ABS_DONE_0 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: program for abstract_done_0*/ +#define EFUSE_ABS_DONE_0 (BIT(4)) +#define EFUSE_ABS_DONE_0_M (BIT(4)) +#define EFUSE_ABS_DONE_0_V 0x1 +#define EFUSE_ABS_DONE_0_S 4 +/* EFUSE_DISABLE_SDIO_HOST : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define EFUSE_DISABLE_SDIO_HOST (BIT(3)) +#define EFUSE_DISABLE_SDIO_HOST_M (BIT(3)) +#define EFUSE_DISABLE_SDIO_HOST_V 0x1 +#define EFUSE_DISABLE_SDIO_HOST_S 3 +/* EFUSE_CONSOLE_DEBUG_DISABLE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: program for console_debug_disable*/ +#define EFUSE_CONSOLE_DEBUG_DISABLE (BIT(2)) +#define EFUSE_CONSOLE_DEBUG_DISABLE_M (BIT(2)) +#define EFUSE_CONSOLE_DEBUG_DISABLE_V 0x1 +#define EFUSE_CONSOLE_DEBUG_DISABLE_S 2 +/* EFUSE_CODING_SCHEME : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: program for coding_scheme*/ +#define EFUSE_CODING_SCHEME 0x00000003 +#define EFUSE_CODING_SCHEME_M ((EFUSE_CODING_SCHEME_V)<<(EFUSE_CODING_SCHEME_S)) +#define EFUSE_CODING_SCHEME_V 0x3 +#define EFUSE_CODING_SCHEME_S 0 + +#define EFUSE_BLK1_RDATA0_REG (DR_REG_EFUSE_BASE + 0x038) +/* EFUSE_BLK1_DOUT0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK1*/ +#define EFUSE_BLK1_DOUT0 0xFFFFFFFF +#define EFUSE_BLK1_DOUT0_M ((EFUSE_BLK1_DOUT0_V)<<(EFUSE_BLK1_DOUT0_S)) +#define EFUSE_BLK1_DOUT0_V 0xFFFFFFFF +#define EFUSE_BLK1_DOUT0_S 0 + +#define EFUSE_BLK1_RDATA1_REG (DR_REG_EFUSE_BASE + 0x03c) +/* EFUSE_BLK1_DOUT1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK1*/ +#define EFUSE_BLK1_DOUT1 0xFFFFFFFF +#define EFUSE_BLK1_DOUT1_M ((EFUSE_BLK1_DOUT1_V)<<(EFUSE_BLK1_DOUT1_S)) +#define EFUSE_BLK1_DOUT1_V 0xFFFFFFFF +#define EFUSE_BLK1_DOUT1_S 0 + +#define EFUSE_BLK1_RDATA2_REG (DR_REG_EFUSE_BASE + 0x040) +/* EFUSE_BLK1_DOUT2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK1*/ +#define EFUSE_BLK1_DOUT2 0xFFFFFFFF +#define EFUSE_BLK1_DOUT2_M ((EFUSE_BLK1_DOUT2_V)<<(EFUSE_BLK1_DOUT2_S)) +#define EFUSE_BLK1_DOUT2_V 0xFFFFFFFF +#define EFUSE_BLK1_DOUT2_S 0 + +#define EFUSE_BLK1_RDATA3_REG (DR_REG_EFUSE_BASE + 0x044) +/* EFUSE_BLK1_DOUT3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK1*/ +#define EFUSE_BLK1_DOUT3 0xFFFFFFFF +#define EFUSE_BLK1_DOUT3_M ((EFUSE_BLK1_DOUT3_V)<<(EFUSE_BLK1_DOUT3_S)) +#define EFUSE_BLK1_DOUT3_V 0xFFFFFFFF +#define EFUSE_BLK1_DOUT3_S 0 + +#define EFUSE_BLK1_RDATA4_REG (DR_REG_EFUSE_BASE + 0x048) +/* EFUSE_BLK1_DOUT4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK1*/ +#define EFUSE_BLK1_DOUT4 0xFFFFFFFF +#define EFUSE_BLK1_DOUT4_M ((EFUSE_BLK1_DOUT4_V)<<(EFUSE_BLK1_DOUT4_S)) +#define EFUSE_BLK1_DOUT4_V 0xFFFFFFFF +#define EFUSE_BLK1_DOUT4_S 0 + +#define EFUSE_BLK1_RDATA5_REG (DR_REG_EFUSE_BASE + 0x04c) +/* EFUSE_BLK1_DOUT5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK1*/ +#define EFUSE_BLK1_DOUT5 0xFFFFFFFF +#define EFUSE_BLK1_DOUT5_M ((EFUSE_BLK1_DOUT5_V)<<(EFUSE_BLK1_DOUT5_S)) +#define EFUSE_BLK1_DOUT5_V 0xFFFFFFFF +#define EFUSE_BLK1_DOUT5_S 0 + +#define EFUSE_BLK1_RDATA6_REG (DR_REG_EFUSE_BASE + 0x050) +/* EFUSE_BLK1_DOUT6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK1*/ +#define EFUSE_BLK1_DOUT6 0xFFFFFFFF +#define EFUSE_BLK1_DOUT6_M ((EFUSE_BLK1_DOUT6_V)<<(EFUSE_BLK1_DOUT6_S)) +#define EFUSE_BLK1_DOUT6_V 0xFFFFFFFF +#define EFUSE_BLK1_DOUT6_S 0 + +#define EFUSE_BLK1_RDATA7_REG (DR_REG_EFUSE_BASE + 0x054) +/* EFUSE_BLK1_DOUT7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK1*/ +#define EFUSE_BLK1_DOUT7 0xFFFFFFFF +#define EFUSE_BLK1_DOUT7_M ((EFUSE_BLK1_DOUT7_V)<<(EFUSE_BLK1_DOUT7_S)) +#define EFUSE_BLK1_DOUT7_V 0xFFFFFFFF +#define EFUSE_BLK1_DOUT7_S 0 + +#define EFUSE_BLK2_RDATA0_REG (DR_REG_EFUSE_BASE + 0x058) +/* EFUSE_BLK2_DOUT0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK2*/ +#define EFUSE_BLK2_DOUT0 0xFFFFFFFF +#define EFUSE_BLK2_DOUT0_M ((EFUSE_BLK2_DOUT0_V)<<(EFUSE_BLK2_DOUT0_S)) +#define EFUSE_BLK2_DOUT0_V 0xFFFFFFFF +#define EFUSE_BLK2_DOUT0_S 0 + +#define EFUSE_BLK2_RDATA1_REG (DR_REG_EFUSE_BASE + 0x05c) +/* EFUSE_BLK2_DOUT1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK2*/ +#define EFUSE_BLK2_DOUT1 0xFFFFFFFF +#define EFUSE_BLK2_DOUT1_M ((EFUSE_BLK2_DOUT1_V)<<(EFUSE_BLK2_DOUT1_S)) +#define EFUSE_BLK2_DOUT1_V 0xFFFFFFFF +#define EFUSE_BLK2_DOUT1_S 0 + +#define EFUSE_BLK2_RDATA2_REG (DR_REG_EFUSE_BASE + 0x060) +/* EFUSE_BLK2_DOUT2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK2*/ +#define EFUSE_BLK2_DOUT2 0xFFFFFFFF +#define EFUSE_BLK2_DOUT2_M ((EFUSE_BLK2_DOUT2_V)<<(EFUSE_BLK2_DOUT2_S)) +#define EFUSE_BLK2_DOUT2_V 0xFFFFFFFF +#define EFUSE_BLK2_DOUT2_S 0 + +#define EFUSE_BLK2_RDATA3_REG (DR_REG_EFUSE_BASE + 0x064) +/* EFUSE_BLK2_DOUT3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK2*/ +#define EFUSE_BLK2_DOUT3 0xFFFFFFFF +#define EFUSE_BLK2_DOUT3_M ((EFUSE_BLK2_DOUT3_V)<<(EFUSE_BLK2_DOUT3_S)) +#define EFUSE_BLK2_DOUT3_V 0xFFFFFFFF +#define EFUSE_BLK2_DOUT3_S 0 + +#define EFUSE_BLK2_RDATA4_REG (DR_REG_EFUSE_BASE + 0x068) +/* EFUSE_BLK2_DOUT4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK2*/ +#define EFUSE_BLK2_DOUT4 0xFFFFFFFF +#define EFUSE_BLK2_DOUT4_M ((EFUSE_BLK2_DOUT4_V)<<(EFUSE_BLK2_DOUT4_S)) +#define EFUSE_BLK2_DOUT4_V 0xFFFFFFFF +#define EFUSE_BLK2_DOUT4_S 0 + +#define EFUSE_BLK2_RDATA5_REG (DR_REG_EFUSE_BASE + 0x06c) +/* EFUSE_BLK2_DOUT5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK2*/ +#define EFUSE_BLK2_DOUT5 0xFFFFFFFF +#define EFUSE_BLK2_DOUT5_M ((EFUSE_BLK2_DOUT5_V)<<(EFUSE_BLK2_DOUT5_S)) +#define EFUSE_BLK2_DOUT5_V 0xFFFFFFFF +#define EFUSE_BLK2_DOUT5_S 0 + +#define EFUSE_BLK2_RDATA6_REG (DR_REG_EFUSE_BASE + 0x070) +/* EFUSE_BLK2_DOUT6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK2*/ +#define EFUSE_BLK2_DOUT6 0xFFFFFFFF +#define EFUSE_BLK2_DOUT6_M ((EFUSE_BLK2_DOUT6_V)<<(EFUSE_BLK2_DOUT6_S)) +#define EFUSE_BLK2_DOUT6_V 0xFFFFFFFF +#define EFUSE_BLK2_DOUT6_S 0 + +#define EFUSE_BLK2_RDATA7_REG (DR_REG_EFUSE_BASE + 0x074) +/* EFUSE_BLK2_DOUT7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK2*/ +#define EFUSE_BLK2_DOUT7 0xFFFFFFFF +#define EFUSE_BLK2_DOUT7_M ((EFUSE_BLK2_DOUT7_V)<<(EFUSE_BLK2_DOUT7_S)) +#define EFUSE_BLK2_DOUT7_V 0xFFFFFFFF +#define EFUSE_BLK2_DOUT7_S 0 + +#define EFUSE_BLK3_RDATA0_REG (DR_REG_EFUSE_BASE + 0x078) +/* EFUSE_BLK3_DOUT0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK3*/ +#define EFUSE_BLK3_DOUT0 0xFFFFFFFF +#define EFUSE_BLK3_DOUT0_M ((EFUSE_BLK3_DOUT0_V)<<(EFUSE_BLK3_DOUT0_S)) +#define EFUSE_BLK3_DOUT0_V 0xFFFFFFFF +#define EFUSE_BLK3_DOUT0_S 0 + +#define EFUSE_BLK3_RDATA1_REG (DR_REG_EFUSE_BASE + 0x07c) +/* EFUSE_BLK3_DOUT1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK3*/ +#define EFUSE_BLK3_DOUT1 0xFFFFFFFF +#define EFUSE_BLK3_DOUT1_M ((EFUSE_BLK3_DOUT1_V)<<(EFUSE_BLK3_DOUT1_S)) +#define EFUSE_BLK3_DOUT1_V 0xFFFFFFFF +#define EFUSE_BLK3_DOUT1_S 0 + +#define EFUSE_BLK3_RDATA2_REG (DR_REG_EFUSE_BASE + 0x080) +/* EFUSE_BLK3_DOUT2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK3*/ +#define EFUSE_BLK3_DOUT2 0xFFFFFFFF +#define EFUSE_BLK3_DOUT2_M ((EFUSE_BLK3_DOUT2_V)<<(EFUSE_BLK3_DOUT2_S)) +#define EFUSE_BLK3_DOUT2_V 0xFFFFFFFF +#define EFUSE_BLK3_DOUT2_S 0 + +#define EFUSE_BLK3_RDATA3_REG (DR_REG_EFUSE_BASE + 0x084) +/* EFUSE_BLK3_DOUT3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK3*/ +#define EFUSE_BLK3_DOUT3 0xFFFFFFFF +#define EFUSE_BLK3_DOUT3_M ((EFUSE_BLK3_DOUT3_V)<<(EFUSE_BLK3_DOUT3_S)) +#define EFUSE_BLK3_DOUT3_V 0xFFFFFFFF +#define EFUSE_BLK3_DOUT3_S 0 + +#define EFUSE_BLK3_RDATA4_REG (DR_REG_EFUSE_BASE + 0x088) +/* EFUSE_BLK3_DOUT4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK3*/ +#define EFUSE_BLK3_DOUT4 0xFFFFFFFF +#define EFUSE_BLK3_DOUT4_M ((EFUSE_BLK3_DOUT4_V)<<(EFUSE_BLK3_DOUT4_S)) +#define EFUSE_BLK3_DOUT4_V 0xFFFFFFFF +#define EFUSE_BLK3_DOUT4_S 0 + +#define EFUSE_BLK3_RDATA5_REG (DR_REG_EFUSE_BASE + 0x08c) +/* EFUSE_BLK3_DOUT5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK3*/ +#define EFUSE_BLK3_DOUT5 0xFFFFFFFF +#define EFUSE_BLK3_DOUT5_M ((EFUSE_BLK3_DOUT5_V)<<(EFUSE_BLK3_DOUT5_S)) +#define EFUSE_BLK3_DOUT5_V 0xFFFFFFFF +#define EFUSE_BLK3_DOUT5_S 0 + +#define EFUSE_BLK3_RDATA6_REG (DR_REG_EFUSE_BASE + 0x090) +/* EFUSE_BLK3_DOUT6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK3*/ +#define EFUSE_BLK3_DOUT6 0xFFFFFFFF +#define EFUSE_BLK3_DOUT6_M ((EFUSE_BLK3_DOUT6_V)<<(EFUSE_BLK3_DOUT6_S)) +#define EFUSE_BLK3_DOUT6_V 0xFFFFFFFF +#define EFUSE_BLK3_DOUT6_S 0 + +#define EFUSE_BLK3_RDATA7_REG (DR_REG_EFUSE_BASE + 0x094) +/* EFUSE_BLK3_DOUT7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: read for BLOCK3*/ +#define EFUSE_BLK3_DOUT7 0xFFFFFFFF +#define EFUSE_BLK3_DOUT7_M ((EFUSE_BLK3_DOUT7_V)<<(EFUSE_BLK3_DOUT7_S)) +#define EFUSE_BLK3_DOUT7_V 0xFFFFFFFF +#define EFUSE_BLK3_DOUT7_S 0 + +#define EFUSE_BLK1_WDATA0_REG (DR_REG_EFUSE_BASE + 0x098) +/* EFUSE_BLK1_DIN0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK1*/ +#define EFUSE_BLK1_DIN0 0xFFFFFFFF +#define EFUSE_BLK1_DIN0_M ((EFUSE_BLK1_DIN0_V)<<(EFUSE_BLK1_DIN0_S)) +#define EFUSE_BLK1_DIN0_V 0xFFFFFFFF +#define EFUSE_BLK1_DIN0_S 0 + +#define EFUSE_BLK1_WDATA1_REG (DR_REG_EFUSE_BASE + 0x09c) +/* EFUSE_BLK1_DIN1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK1*/ +#define EFUSE_BLK1_DIN1 0xFFFFFFFF +#define EFUSE_BLK1_DIN1_M ((EFUSE_BLK1_DIN1_V)<<(EFUSE_BLK1_DIN1_S)) +#define EFUSE_BLK1_DIN1_V 0xFFFFFFFF +#define EFUSE_BLK1_DIN1_S 0 + +#define EFUSE_BLK1_WDATA2_REG (DR_REG_EFUSE_BASE + 0x0a0) +/* EFUSE_BLK1_DIN2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK1*/ +#define EFUSE_BLK1_DIN2 0xFFFFFFFF +#define EFUSE_BLK1_DIN2_M ((EFUSE_BLK1_DIN2_V)<<(EFUSE_BLK1_DIN2_S)) +#define EFUSE_BLK1_DIN2_V 0xFFFFFFFF +#define EFUSE_BLK1_DIN2_S 0 + +#define EFUSE_BLK1_WDATA3_REG (DR_REG_EFUSE_BASE + 0x0a4) +/* EFUSE_BLK1_DIN3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK1*/ +#define EFUSE_BLK1_DIN3 0xFFFFFFFF +#define EFUSE_BLK1_DIN3_M ((EFUSE_BLK1_DIN3_V)<<(EFUSE_BLK1_DIN3_S)) +#define EFUSE_BLK1_DIN3_V 0xFFFFFFFF +#define EFUSE_BLK1_DIN3_S 0 + +#define EFUSE_BLK1_WDATA4_REG (DR_REG_EFUSE_BASE + 0x0a8) +/* EFUSE_BLK1_DIN4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK1*/ +#define EFUSE_BLK1_DIN4 0xFFFFFFFF +#define EFUSE_BLK1_DIN4_M ((EFUSE_BLK1_DIN4_V)<<(EFUSE_BLK1_DIN4_S)) +#define EFUSE_BLK1_DIN4_V 0xFFFFFFFF +#define EFUSE_BLK1_DIN4_S 0 + +#define EFUSE_BLK1_WDATA5_REG (DR_REG_EFUSE_BASE + 0x0ac) +/* EFUSE_BLK1_DIN5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK1*/ +#define EFUSE_BLK1_DIN5 0xFFFFFFFF +#define EFUSE_BLK1_DIN5_M ((EFUSE_BLK1_DIN5_V)<<(EFUSE_BLK1_DIN5_S)) +#define EFUSE_BLK1_DIN5_V 0xFFFFFFFF +#define EFUSE_BLK1_DIN5_S 0 + +#define EFUSE_BLK1_WDATA6_REG (DR_REG_EFUSE_BASE + 0x0b0) +/* EFUSE_BLK1_DIN6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK1*/ +#define EFUSE_BLK1_DIN6 0xFFFFFFFF +#define EFUSE_BLK1_DIN6_M ((EFUSE_BLK1_DIN6_V)<<(EFUSE_BLK1_DIN6_S)) +#define EFUSE_BLK1_DIN6_V 0xFFFFFFFF +#define EFUSE_BLK1_DIN6_S 0 + +#define EFUSE_BLK1_WDATA7_REG (DR_REG_EFUSE_BASE + 0x0b4) +/* EFUSE_BLK1_DIN7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK1*/ +#define EFUSE_BLK1_DIN7 0xFFFFFFFF +#define EFUSE_BLK1_DIN7_M ((EFUSE_BLK1_DIN7_V)<<(EFUSE_BLK1_DIN7_S)) +#define EFUSE_BLK1_DIN7_V 0xFFFFFFFF +#define EFUSE_BLK1_DIN7_S 0 + +#define EFUSE_BLK2_WDATA0_REG (DR_REG_EFUSE_BASE + 0x0b8) +/* EFUSE_BLK2_DIN0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK2*/ +#define EFUSE_BLK2_DIN0 0xFFFFFFFF +#define EFUSE_BLK2_DIN0_M ((EFUSE_BLK2_DIN0_V)<<(EFUSE_BLK2_DIN0_S)) +#define EFUSE_BLK2_DIN0_V 0xFFFFFFFF +#define EFUSE_BLK2_DIN0_S 0 + +#define EFUSE_BLK2_WDATA1_REG (DR_REG_EFUSE_BASE + 0x0bc) +/* EFUSE_BLK2_DIN1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK2*/ +#define EFUSE_BLK2_DIN1 0xFFFFFFFF +#define EFUSE_BLK2_DIN1_M ((EFUSE_BLK2_DIN1_V)<<(EFUSE_BLK2_DIN1_S)) +#define EFUSE_BLK2_DIN1_V 0xFFFFFFFF +#define EFUSE_BLK2_DIN1_S 0 + +#define EFUSE_BLK2_WDATA2_REG (DR_REG_EFUSE_BASE + 0x0c0) +/* EFUSE_BLK2_DIN2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK2*/ +#define EFUSE_BLK2_DIN2 0xFFFFFFFF +#define EFUSE_BLK2_DIN2_M ((EFUSE_BLK2_DIN2_V)<<(EFUSE_BLK2_DIN2_S)) +#define EFUSE_BLK2_DIN2_V 0xFFFFFFFF +#define EFUSE_BLK2_DIN2_S 0 + +#define EFUSE_BLK2_WDATA3_REG (DR_REG_EFUSE_BASE + 0x0c4) +/* EFUSE_BLK2_DIN3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK2*/ +#define EFUSE_BLK2_DIN3 0xFFFFFFFF +#define EFUSE_BLK2_DIN3_M ((EFUSE_BLK2_DIN3_V)<<(EFUSE_BLK2_DIN3_S)) +#define EFUSE_BLK2_DIN3_V 0xFFFFFFFF +#define EFUSE_BLK2_DIN3_S 0 + +#define EFUSE_BLK2_WDATA4_REG (DR_REG_EFUSE_BASE + 0x0c8) +/* EFUSE_BLK2_DIN4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK2*/ +#define EFUSE_BLK2_DIN4 0xFFFFFFFF +#define EFUSE_BLK2_DIN4_M ((EFUSE_BLK2_DIN4_V)<<(EFUSE_BLK2_DIN4_S)) +#define EFUSE_BLK2_DIN4_V 0xFFFFFFFF +#define EFUSE_BLK2_DIN4_S 0 + +#define EFUSE_BLK2_WDATA5_REG (DR_REG_EFUSE_BASE + 0x0cc) +/* EFUSE_BLK2_DIN5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK2*/ +#define EFUSE_BLK2_DIN5 0xFFFFFFFF +#define EFUSE_BLK2_DIN5_M ((EFUSE_BLK2_DIN5_V)<<(EFUSE_BLK2_DIN5_S)) +#define EFUSE_BLK2_DIN5_V 0xFFFFFFFF +#define EFUSE_BLK2_DIN5_S 0 + +#define EFUSE_BLK2_WDATA6_REG (DR_REG_EFUSE_BASE + 0x0d0) +/* EFUSE_BLK2_DIN6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK2*/ +#define EFUSE_BLK2_DIN6 0xFFFFFFFF +#define EFUSE_BLK2_DIN6_M ((EFUSE_BLK2_DIN6_V)<<(EFUSE_BLK2_DIN6_S)) +#define EFUSE_BLK2_DIN6_V 0xFFFFFFFF +#define EFUSE_BLK2_DIN6_S 0 + +#define EFUSE_BLK2_WDATA7_REG (DR_REG_EFUSE_BASE + 0x0d4) +/* EFUSE_BLK2_DIN7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK2*/ +#define EFUSE_BLK2_DIN7 0xFFFFFFFF +#define EFUSE_BLK2_DIN7_M ((EFUSE_BLK2_DIN7_V)<<(EFUSE_BLK2_DIN7_S)) +#define EFUSE_BLK2_DIN7_V 0xFFFFFFFF +#define EFUSE_BLK2_DIN7_S 0 + +#define EFUSE_BLK3_WDATA0_REG (DR_REG_EFUSE_BASE + 0x0d8) +/* EFUSE_BLK3_DIN0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK3*/ +#define EFUSE_BLK3_DIN0 0xFFFFFFFF +#define EFUSE_BLK3_DIN0_M ((EFUSE_BLK3_DIN0_V)<<(EFUSE_BLK3_DIN0_S)) +#define EFUSE_BLK3_DIN0_V 0xFFFFFFFF +#define EFUSE_BLK3_DIN0_S 0 + +#define EFUSE_BLK3_WDATA1_REG (DR_REG_EFUSE_BASE + 0x0dc) +/* EFUSE_BLK3_DIN1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK3*/ +#define EFUSE_BLK3_DIN1 0xFFFFFFFF +#define EFUSE_BLK3_DIN1_M ((EFUSE_BLK3_DIN1_V)<<(EFUSE_BLK3_DIN1_S)) +#define EFUSE_BLK3_DIN1_V 0xFFFFFFFF +#define EFUSE_BLK3_DIN1_S 0 + +#define EFUSE_BLK3_WDATA2_REG (DR_REG_EFUSE_BASE + 0x0e0) +/* EFUSE_BLK3_DIN2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK3*/ +#define EFUSE_BLK3_DIN2 0xFFFFFFFF +#define EFUSE_BLK3_DIN2_M ((EFUSE_BLK3_DIN2_V)<<(EFUSE_BLK3_DIN2_S)) +#define EFUSE_BLK3_DIN2_V 0xFFFFFFFF +#define EFUSE_BLK3_DIN2_S 0 + +#define EFUSE_BLK3_WDATA3_REG (DR_REG_EFUSE_BASE + 0x0e4) +/* EFUSE_BLK3_DIN3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK3*/ +#define EFUSE_BLK3_DIN3 0xFFFFFFFF +#define EFUSE_BLK3_DIN3_M ((EFUSE_BLK3_DIN3_V)<<(EFUSE_BLK3_DIN3_S)) +#define EFUSE_BLK3_DIN3_V 0xFFFFFFFF +#define EFUSE_BLK3_DIN3_S 0 + +#define EFUSE_BLK3_WDATA4_REG (DR_REG_EFUSE_BASE + 0x0e8) +/* EFUSE_BLK3_DIN4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK3*/ +#define EFUSE_BLK3_DIN4 0xFFFFFFFF +#define EFUSE_BLK3_DIN4_M ((EFUSE_BLK3_DIN4_V)<<(EFUSE_BLK3_DIN4_S)) +#define EFUSE_BLK3_DIN4_V 0xFFFFFFFF +#define EFUSE_BLK3_DIN4_S 0 + +#define EFUSE_BLK3_WDATA5_REG (DR_REG_EFUSE_BASE + 0x0ec) +/* EFUSE_BLK3_DIN5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK3*/ +#define EFUSE_BLK3_DIN5 0xFFFFFFFF +#define EFUSE_BLK3_DIN5_M ((EFUSE_BLK3_DIN5_V)<<(EFUSE_BLK3_DIN5_S)) +#define EFUSE_BLK3_DIN5_V 0xFFFFFFFF +#define EFUSE_BLK3_DIN5_S 0 + +#define EFUSE_BLK3_WDATA6_REG (DR_REG_EFUSE_BASE + 0x0f0) +/* EFUSE_BLK3_DIN6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK3*/ +#define EFUSE_BLK3_DIN6 0xFFFFFFFF +#define EFUSE_BLK3_DIN6_M ((EFUSE_BLK3_DIN6_V)<<(EFUSE_BLK3_DIN6_S)) +#define EFUSE_BLK3_DIN6_V 0xFFFFFFFF +#define EFUSE_BLK3_DIN6_S 0 + +#define EFUSE_BLK3_WDATA7_REG (DR_REG_EFUSE_BASE + 0x0f4) +/* EFUSE_BLK3_DIN7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: program for BLOCK3*/ +#define EFUSE_BLK3_DIN7 0xFFFFFFFF +#define EFUSE_BLK3_DIN7_M ((EFUSE_BLK3_DIN7_V)<<(EFUSE_BLK3_DIN7_S)) +#define EFUSE_BLK3_DIN7_V 0xFFFFFFFF +#define EFUSE_BLK3_DIN7_S 0 + +#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x0f8) +/* EFUSE_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define EFUSE_CLK_EN (BIT(16)) +#define EFUSE_CLK_EN_M (BIT(16)) +#define EFUSE_CLK_EN_V 0x1 +#define EFUSE_CLK_EN_S 16 +/* EFUSE_CLK_SEL1 : R/W ;bitpos:[15:8] ;default: 8'h40 ; */ +/*description: efuse timing configure*/ +#define EFUSE_CLK_SEL1 0x000000FF +#define EFUSE_CLK_SEL1_M ((EFUSE_CLK_SEL1_V)<<(EFUSE_CLK_SEL1_S)) +#define EFUSE_CLK_SEL1_V 0xFF +#define EFUSE_CLK_SEL1_S 8 +/* EFUSE_CLK_SEL0 : R/W ;bitpos:[7:0] ;default: 8'h52 ; */ +/*description: efuse timing configure*/ +#define EFUSE_CLK_SEL0 0x000000FF +#define EFUSE_CLK_SEL0_M ((EFUSE_CLK_SEL0_V)<<(EFUSE_CLK_SEL0_S)) +#define EFUSE_CLK_SEL0_V 0xFF +#define EFUSE_CLK_SEL0_S 0 + +#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x0fc) +/* EFUSE_FORCE_NO_WR_RD_DIS : R/W ;bitpos:[16] ;default: 1'h1 ; */ +/*description: */ +#define EFUSE_FORCE_NO_WR_RD_DIS (BIT(16)) +#define EFUSE_FORCE_NO_WR_RD_DIS_M (BIT(16)) +#define EFUSE_FORCE_NO_WR_RD_DIS_V 0x1 +#define EFUSE_FORCE_NO_WR_RD_DIS_S 16 +/* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: efuse operation code*/ +#define EFUSE_OP_CODE 0x0000FFFF +#define EFUSE_OP_CODE_M ((EFUSE_OP_CODE_V)<<(EFUSE_OP_CODE_S)) +#define EFUSE_OP_CODE_V 0xFFFF +#define EFUSE_OP_CODE_S 0 + +#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x100) +/* EFUSE_DEBUG : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define EFUSE_DEBUG 0xFFFFFFFF +#define EFUSE_DEBUG_M ((EFUSE_DEBUG_V)<<(EFUSE_DEBUG_S)) +#define EFUSE_DEBUG_V 0xFFFFFFFF +#define EFUSE_DEBUG_S 0 + +#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x104) +/* EFUSE_PGM_CMD : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: command for program*/ +#define EFUSE_PGM_CMD (BIT(1)) +#define EFUSE_PGM_CMD_M (BIT(1)) +#define EFUSE_PGM_CMD_V 0x1 +#define EFUSE_PGM_CMD_S 1 +/* EFUSE_READ_CMD : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: command for read*/ +#define EFUSE_READ_CMD (BIT(0)) +#define EFUSE_READ_CMD_M (BIT(0)) +#define EFUSE_READ_CMD_V 0x1 +#define EFUSE_READ_CMD_S 0 + +#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x108) +/* EFUSE_PGM_DONE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: program done interrupt raw status*/ +#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) +#define EFUSE_PGM_DONE_INT_RAW_M (BIT(1)) +#define EFUSE_PGM_DONE_INT_RAW_V 0x1 +#define EFUSE_PGM_DONE_INT_RAW_S 1 +/* EFUSE_READ_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: read done interrupt raw status*/ +#define EFUSE_READ_DONE_INT_RAW (BIT(0)) +#define EFUSE_READ_DONE_INT_RAW_M (BIT(0)) +#define EFUSE_READ_DONE_INT_RAW_V 0x1 +#define EFUSE_READ_DONE_INT_RAW_S 0 + +#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x10c) +/* EFUSE_PGM_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: program done interrupt status*/ +#define EFUSE_PGM_DONE_INT_ST (BIT(1)) +#define EFUSE_PGM_DONE_INT_ST_M (BIT(1)) +#define EFUSE_PGM_DONE_INT_ST_V 0x1 +#define EFUSE_PGM_DONE_INT_ST_S 1 +/* EFUSE_READ_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: read done interrupt status*/ +#define EFUSE_READ_DONE_INT_ST (BIT(0)) +#define EFUSE_READ_DONE_INT_ST_M (BIT(0)) +#define EFUSE_READ_DONE_INT_ST_V 0x1 +#define EFUSE_READ_DONE_INT_ST_S 0 + +#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x110) +/* EFUSE_PGM_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: program done interrupt enable*/ +#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) +#define EFUSE_PGM_DONE_INT_ENA_M (BIT(1)) +#define EFUSE_PGM_DONE_INT_ENA_V 0x1 +#define EFUSE_PGM_DONE_INT_ENA_S 1 +/* EFUSE_READ_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: read done interrupt enable*/ +#define EFUSE_READ_DONE_INT_ENA (BIT(0)) +#define EFUSE_READ_DONE_INT_ENA_M (BIT(0)) +#define EFUSE_READ_DONE_INT_ENA_V 0x1 +#define EFUSE_READ_DONE_INT_ENA_S 0 + +#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x114) +/* EFUSE_PGM_DONE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: program done interrupt clear*/ +#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) +#define EFUSE_PGM_DONE_INT_CLR_M (BIT(1)) +#define EFUSE_PGM_DONE_INT_CLR_V 0x1 +#define EFUSE_PGM_DONE_INT_CLR_S 1 +/* EFUSE_READ_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: read done interrupt clear*/ +#define EFUSE_READ_DONE_INT_CLR (BIT(0)) +#define EFUSE_READ_DONE_INT_CLR_M (BIT(0)) +#define EFUSE_READ_DONE_INT_CLR_V 0x1 +#define EFUSE_READ_DONE_INT_CLR_S 0 + +#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x118) +/* EFUSE_DAC_CLK_PAD_SEL : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) +#define EFUSE_DAC_CLK_PAD_SEL_M (BIT(8)) +#define EFUSE_DAC_CLK_PAD_SEL_V 0x1 +#define EFUSE_DAC_CLK_PAD_SEL_S 8 +/* EFUSE_DAC_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd40 ; */ +/*description: efuse timing configure*/ +#define EFUSE_DAC_CLK_DIV 0x000000FF +#define EFUSE_DAC_CLK_DIV_M ((EFUSE_DAC_CLK_DIV_V)<<(EFUSE_DAC_CLK_DIV_S)) +#define EFUSE_DAC_CLK_DIV_V 0xFF +#define EFUSE_DAC_CLK_DIV_S 0 + +#define EFUSE_DEC_STATUS_REG (DR_REG_EFUSE_BASE + 0x11c) +/* EFUSE_DEC_WARNINGS : RO ;bitpos:[11:0] ;default: 12'b0 ; */ +/*description: the decode result of 3/4 coding scheme has warning*/ +#define EFUSE_DEC_WARNINGS 0x00000FFF +#define EFUSE_DEC_WARNINGS_M ((EFUSE_DEC_WARNINGS_V)<<(EFUSE_DEC_WARNINGS_S)) +#define EFUSE_DEC_WARNINGS_V 0xFFF +#define EFUSE_DEC_WARNINGS_S 0 + +#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1FC) +/* EFUSE_DATE : R/W ;bitpos:[31:0] ;default: 32'h16042600 ; */ +/*description: */ +#define EFUSE_DATE 0xFFFFFFFF +#define EFUSE_DATE_M ((EFUSE_DATE_V)<<(EFUSE_DATE_S)) +#define EFUSE_DATE_V 0xFFFFFFFF +#define EFUSE_DATE_S 0 + + + + +#endif /*_SOC_EFUSE_REG_H_ */ + + diff --git a/tools/sdk/include/esp32/soc/gpio_reg.h b/tools/sdk/include/esp32/soc/gpio_reg.h new file mode 100644 index 00000000..1f4b08d4 --- /dev/null +++ b/tools/sdk/include/esp32/soc/gpio_reg.h @@ -0,0 +1,8239 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_GPIO_REG_H_ +#define _SOC_GPIO_REG_H_ + +#include "soc.h" +#define GPIO_BT_SELECT_REG (DR_REG_GPIO_BASE + 0x0000) +/* GPIO_BT_SEL : R/W ;bitpos:[31:0] ;default: x ; */ +/*description: NA*/ +#define GPIO_BT_SEL 0xFFFFFFFF +#define GPIO_BT_SEL_M ((GPIO_BT_SEL_V)<<(GPIO_BT_SEL_S)) +#define GPIO_BT_SEL_V 0xFFFFFFFF +#define GPIO_BT_SEL_S 0 + +#define GPIO_OUT_REG (DR_REG_GPIO_BASE + 0x0004) +/* GPIO_OUT_DATA : R/W ;bitpos:[31:0] ;default: x ; */ +/*description: GPIO0~31 output value*/ +#define GPIO_OUT_DATA 0xFFFFFFFF +#define GPIO_OUT_DATA_M ((GPIO_OUT_DATA_V)<<(GPIO_OUT_DATA_S)) +#define GPIO_OUT_DATA_V 0xFFFFFFFF +#define GPIO_OUT_DATA_S 0 + +#define GPIO_OUT_W1TS_REG (DR_REG_GPIO_BASE + 0x0008) +/* GPIO_OUT_DATA_W1TS : R/W ;bitpos:[31:0] ;default: x ; */ +/*description: GPIO0~31 output value write 1 to set*/ +#define GPIO_OUT_DATA_W1TS 0xFFFFFFFF +#define GPIO_OUT_DATA_W1TS_M ((GPIO_OUT_DATA_W1TS_V)<<(GPIO_OUT_DATA_W1TS_S)) +#define GPIO_OUT_DATA_W1TS_V 0xFFFFFFFF +#define GPIO_OUT_DATA_W1TS_S 0 + +#define GPIO_OUT_W1TC_REG (DR_REG_GPIO_BASE + 0x000c) +/* GPIO_OUT_DATA_W1TC : R/W ;bitpos:[31:0] ;default: x ; */ +/*description: GPIO0~31 output value write 1 to clear*/ +#define GPIO_OUT_DATA_W1TC 0xFFFFFFFF +#define GPIO_OUT_DATA_W1TC_M ((GPIO_OUT_DATA_W1TC_V)<<(GPIO_OUT_DATA_W1TC_S)) +#define GPIO_OUT_DATA_W1TC_V 0xFFFFFFFF +#define GPIO_OUT_DATA_W1TC_S 0 + +#define GPIO_OUT1_REG (DR_REG_GPIO_BASE + 0x0010) +/* GPIO_OUT1_DATA : R/W ;bitpos:[7:0] ;default: x ; */ +/*description: GPIO32~39 output value*/ +#define GPIO_OUT1_DATA 0x000000FF +#define GPIO_OUT1_DATA_M ((GPIO_OUT1_DATA_V)<<(GPIO_OUT1_DATA_S)) +#define GPIO_OUT1_DATA_V 0xFF +#define GPIO_OUT1_DATA_S 0 + +#define GPIO_OUT1_W1TS_REG (DR_REG_GPIO_BASE + 0x0014) +/* GPIO_OUT1_DATA_W1TS : R/W ;bitpos:[7:0] ;default: x ; */ +/*description: GPIO32~39 output value write 1 to set*/ +#define GPIO_OUT1_DATA_W1TS 0x000000FF +#define GPIO_OUT1_DATA_W1TS_M ((GPIO_OUT1_DATA_W1TS_V)<<(GPIO_OUT1_DATA_W1TS_S)) +#define GPIO_OUT1_DATA_W1TS_V 0xFF +#define GPIO_OUT1_DATA_W1TS_S 0 + +#define GPIO_OUT1_W1TC_REG (DR_REG_GPIO_BASE + 0x0018) +/* GPIO_OUT1_DATA_W1TC : R/W ;bitpos:[7:0] ;default: x ; */ +/*description: GPIO32~39 output value write 1 to clear*/ +#define GPIO_OUT1_DATA_W1TC 0x000000FF +#define GPIO_OUT1_DATA_W1TC_M ((GPIO_OUT1_DATA_W1TC_V)<<(GPIO_OUT1_DATA_W1TC_S)) +#define GPIO_OUT1_DATA_W1TC_V 0xFF +#define GPIO_OUT1_DATA_W1TC_S 0 + +#define GPIO_SDIO_SELECT_REG (DR_REG_GPIO_BASE + 0x001c) +/* GPIO_SDIO_SEL : R/W ;bitpos:[7:0] ;default: x ; */ +/*description: SDIO PADS on/off control from outside*/ +#define GPIO_SDIO_SEL 0x000000FF +#define GPIO_SDIO_SEL_M ((GPIO_SDIO_SEL_V)<<(GPIO_SDIO_SEL_S)) +#define GPIO_SDIO_SEL_V 0xFF +#define GPIO_SDIO_SEL_S 0 + +#define GPIO_ENABLE_REG (DR_REG_GPIO_BASE + 0x0020) +/* GPIO_ENABLE_DATA : R/W ;bitpos:[31:0] ;default: x ; */ +/*description: GPIO0~31 output enable*/ +#define GPIO_ENABLE_DATA 0xFFFFFFFF +#define GPIO_ENABLE_DATA_M ((GPIO_ENABLE_DATA_V)<<(GPIO_ENABLE_DATA_S)) +#define GPIO_ENABLE_DATA_V 0xFFFFFFFF +#define GPIO_ENABLE_DATA_S 0 + +#define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x0024) +/* GPIO_ENABLE_DATA_W1TS : R/W ;bitpos:[31:0] ;default: x ; */ +/*description: GPIO0~31 output enable write 1 to set*/ +#define GPIO_ENABLE_DATA_W1TS 0xFFFFFFFF +#define GPIO_ENABLE_DATA_W1TS_M ((GPIO_ENABLE_DATA_W1TS_V)<<(GPIO_ENABLE_DATA_W1TS_S)) +#define GPIO_ENABLE_DATA_W1TS_V 0xFFFFFFFF +#define GPIO_ENABLE_DATA_W1TS_S 0 + +#define GPIO_ENABLE_W1TC_REG (DR_REG_GPIO_BASE + 0x0028) +/* GPIO_ENABLE_DATA_W1TC : R/W ;bitpos:[31:0] ;default: x ; */ +/*description: GPIO0~31 output enable write 1 to clear*/ +#define GPIO_ENABLE_DATA_W1TC 0xFFFFFFFF +#define GPIO_ENABLE_DATA_W1TC_M ((GPIO_ENABLE_DATA_W1TC_V)<<(GPIO_ENABLE_DATA_W1TC_S)) +#define GPIO_ENABLE_DATA_W1TC_V 0xFFFFFFFF +#define GPIO_ENABLE_DATA_W1TC_S 0 + +#define GPIO_ENABLE1_REG (DR_REG_GPIO_BASE + 0x002c) +/* GPIO_ENABLE1_DATA : R/W ;bitpos:[7:0] ;default: x ; */ +/*description: GPIO32~39 output enable*/ +#define GPIO_ENABLE1_DATA 0x000000FF +#define GPIO_ENABLE1_DATA_M ((GPIO_ENABLE1_DATA_V)<<(GPIO_ENABLE1_DATA_S)) +#define GPIO_ENABLE1_DATA_V 0xFF +#define GPIO_ENABLE1_DATA_S 0 + +#define GPIO_ENABLE1_W1TS_REG (DR_REG_GPIO_BASE + 0x0030) +/* GPIO_ENABLE1_DATA_W1TS : R/W ;bitpos:[7:0] ;default: x ; */ +/*description: GPIO32~39 output enable write 1 to set*/ +#define GPIO_ENABLE1_DATA_W1TS 0x000000FF +#define GPIO_ENABLE1_DATA_W1TS_M ((GPIO_ENABLE1_DATA_W1TS_V)<<(GPIO_ENABLE1_DATA_W1TS_S)) +#define GPIO_ENABLE1_DATA_W1TS_V 0xFF +#define GPIO_ENABLE1_DATA_W1TS_S 0 + +#define GPIO_ENABLE1_W1TC_REG (DR_REG_GPIO_BASE + 0x0034) +/* GPIO_ENABLE1_DATA_W1TC : R/W ;bitpos:[7:0] ;default: x ; */ +/*description: GPIO32~39 output enable write 1 to clear*/ +#define GPIO_ENABLE1_DATA_W1TC 0x000000FF +#define GPIO_ENABLE1_DATA_W1TC_M ((GPIO_ENABLE1_DATA_W1TC_V)<<(GPIO_ENABLE1_DATA_W1TC_S)) +#define GPIO_ENABLE1_DATA_W1TC_V 0xFF +#define GPIO_ENABLE1_DATA_W1TC_S 0 + +#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x0038) +/* GPIO_STRAPPING : RO ;bitpos:[15:0] ;default: ; */ +/*description: GPIO strapping results: {2'd0 boot_sel_dig[7:1] vsdio_boot_sel + boot_sel_chip[5:0]}. Boot_sel_dig[7:1]: {U0RXD SD_CLK SD_CMD SD_DATA0 SD_DATA1 SD_DATA2 SD_DATA3}. vsdio_boot_sel: MTDI. boot_sel_chip[5:0]: {GPIO0 U0TXD GPIO2 GPIO4 MTDO GPIO5}*/ +#define GPIO_STRAPPING 0x0000FFFF +#define GPIO_STRAPPING_M ((GPIO_STRAPPING_V)<<(GPIO_STRAPPING_S)) +#define GPIO_STRAPPING_V 0xFFFF +#define GPIO_STRAPPING_S 0 + +#define GPIO_IN_REG (DR_REG_GPIO_BASE + 0x003c) +/* GPIO_IN_DATA : RO ;bitpos:[31:0] ;default: ; */ +/*description: GPIO0~31 input value*/ +#define GPIO_IN_DATA 0xFFFFFFFF +#define GPIO_IN_DATA_M ((GPIO_IN_DATA_V)<<(GPIO_IN_DATA_S)) +#define GPIO_IN_DATA_V 0xFFFFFFFF +#define GPIO_IN_DATA_S 0 + +#define GPIO_IN1_REG (DR_REG_GPIO_BASE + 0x0040) +/* GPIO_IN1_DATA : RO ;bitpos:[7:0] ;default: ; */ +/*description: GPIO32~39 input value*/ +#define GPIO_IN1_DATA 0x000000FF +#define GPIO_IN1_DATA_M ((GPIO_IN1_DATA_V)<<(GPIO_IN1_DATA_S)) +#define GPIO_IN1_DATA_V 0xFF +#define GPIO_IN1_DATA_S 0 + +#define GPIO_STATUS_REG (DR_REG_GPIO_BASE + 0x0044) +/* GPIO_STATUS_INT : R/W ;bitpos:[31:0] ;default: x ; */ +/*description: GPIO0~31 interrupt status*/ +#define GPIO_STATUS_INT 0xFFFFFFFF +#define GPIO_STATUS_INT_M ((GPIO_STATUS_INT_V)<<(GPIO_STATUS_INT_S)) +#define GPIO_STATUS_INT_V 0xFFFFFFFF +#define GPIO_STATUS_INT_S 0 + +#define GPIO_STATUS_W1TS_REG (DR_REG_GPIO_BASE + 0x0048) +/* GPIO_STATUS_INT_W1TS : R/W ;bitpos:[31:0] ;default: x ; */ +/*description: GPIO0~31 interrupt status write 1 to set*/ +#define GPIO_STATUS_INT_W1TS 0xFFFFFFFF +#define GPIO_STATUS_INT_W1TS_M ((GPIO_STATUS_INT_W1TS_V)<<(GPIO_STATUS_INT_W1TS_S)) +#define GPIO_STATUS_INT_W1TS_V 0xFFFFFFFF +#define GPIO_STATUS_INT_W1TS_S 0 + +#define GPIO_STATUS_W1TC_REG (DR_REG_GPIO_BASE + 0x004c) +/* GPIO_STATUS_INT_W1TC : R/W ;bitpos:[31:0] ;default: x ; */ +/*description: GPIO0~31 interrupt status write 1 to clear*/ +#define GPIO_STATUS_INT_W1TC 0xFFFFFFFF +#define GPIO_STATUS_INT_W1TC_M ((GPIO_STATUS_INT_W1TC_V)<<(GPIO_STATUS_INT_W1TC_S)) +#define GPIO_STATUS_INT_W1TC_V 0xFFFFFFFF +#define GPIO_STATUS_INT_W1TC_S 0 + +#define GPIO_STATUS1_REG (DR_REG_GPIO_BASE + 0x0050) +/* GPIO_STATUS1_INT : R/W ;bitpos:[7:0] ;default: x ; */ +/*description: GPIO32~39 interrupt status*/ +#define GPIO_STATUS1_INT 0x000000FF +#define GPIO_STATUS1_INT_M ((GPIO_STATUS1_INT_V)<<(GPIO_STATUS1_INT_S)) +#define GPIO_STATUS1_INT_V 0xFF +#define GPIO_STATUS1_INT_S 0 + +#define GPIO_STATUS1_W1TS_REG (DR_REG_GPIO_BASE + 0x0054) +/* GPIO_STATUS1_INT_W1TS : R/W ;bitpos:[7:0] ;default: x ; */ +/*description: GPIO32~39 interrupt status write 1 to set*/ +#define GPIO_STATUS1_INT_W1TS 0x000000FF +#define GPIO_STATUS1_INT_W1TS_M ((GPIO_STATUS1_INT_W1TS_V)<<(GPIO_STATUS1_INT_W1TS_S)) +#define GPIO_STATUS1_INT_W1TS_V 0xFF +#define GPIO_STATUS1_INT_W1TS_S 0 + +#define GPIO_STATUS1_W1TC_REG (DR_REG_GPIO_BASE + 0x0058) +/* GPIO_STATUS1_INT_W1TC : R/W ;bitpos:[7:0] ;default: x ; */ +/*description: GPIO32~39 interrupt status write 1 to clear*/ +#define GPIO_STATUS1_INT_W1TC 0x000000FF +#define GPIO_STATUS1_INT_W1TC_M ((GPIO_STATUS1_INT_W1TC_V)<<(GPIO_STATUS1_INT_W1TC_S)) +#define GPIO_STATUS1_INT_W1TC_V 0xFF +#define GPIO_STATUS1_INT_W1TC_S 0 + +#define GPIO_ACPU_INT_REG (DR_REG_GPIO_BASE + 0x0060) +/* GPIO_APPCPU_INT : RO ;bitpos:[31:0] ;default: x ; */ +/*description: GPIO0~31 APP CPU interrupt status*/ +#define GPIO_APPCPU_INT 0xFFFFFFFF +#define GPIO_APPCPU_INT_M ((GPIO_APPCPU_INT_V)<<(GPIO_APPCPU_INT_S)) +#define GPIO_APPCPU_INT_V 0xFFFFFFFF +#define GPIO_APPCPU_INT_S 0 + +#define GPIO_ACPU_NMI_INT_REG (DR_REG_GPIO_BASE + 0x0064) +/* GPIO_APPCPU_NMI_INT : RO ;bitpos:[31:0] ;default: x ; */ +/*description: GPIO0~31 APP CPU non-maskable interrupt status*/ +#define GPIO_APPCPU_NMI_INT 0xFFFFFFFF +#define GPIO_APPCPU_NMI_INT_M ((GPIO_APPCPU_NMI_INT_V)<<(GPIO_APPCPU_NMI_INT_S)) +#define GPIO_APPCPU_NMI_INT_V 0xFFFFFFFF +#define GPIO_APPCPU_NMI_INT_S 0 + +#define GPIO_PCPU_INT_REG (DR_REG_GPIO_BASE + 0x0068) +/* GPIO_PROCPU_INT : RO ;bitpos:[31:0] ;default: x ; */ +/*description: GPIO0~31 PRO CPU interrupt status*/ +#define GPIO_PROCPU_INT 0xFFFFFFFF +#define GPIO_PROCPU_INT_M ((GPIO_PROCPU_INT_V)<<(GPIO_PROCPU_INT_S)) +#define GPIO_PROCPU_INT_V 0xFFFFFFFF +#define GPIO_PROCPU_INT_S 0 + +#define GPIO_PCPU_NMI_INT_REG (DR_REG_GPIO_BASE + 0x006c) +/* GPIO_PROCPU_NMI_INT : RO ;bitpos:[31:0] ;default: x ; */ +/*description: GPIO0~31 PRO CPU non-maskable interrupt status*/ +#define GPIO_PROCPU_NMI_INT 0xFFFFFFFF +#define GPIO_PROCPU_NMI_INT_M ((GPIO_PROCPU_NMI_INT_V)<<(GPIO_PROCPU_NMI_INT_S)) +#define GPIO_PROCPU_NMI_INT_V 0xFFFFFFFF +#define GPIO_PROCPU_NMI_INT_S 0 + +#define GPIO_CPUSDIO_INT_REG (DR_REG_GPIO_BASE + 0x0070) +/* GPIO_SDIO_INT : RO ;bitpos:[31:0] ;default: x ; */ +/*description: SDIO's extent GPIO0~31 interrupt*/ +#define GPIO_SDIO_INT 0xFFFFFFFF +#define GPIO_SDIO_INT_M ((GPIO_SDIO_INT_V)<<(GPIO_SDIO_INT_S)) +#define GPIO_SDIO_INT_V 0xFFFFFFFF +#define GPIO_SDIO_INT_S 0 + +#define GPIO_ACPU_INT1_REG (DR_REG_GPIO_BASE + 0x0074) +/* GPIO_APPCPU_INT_H : RO ;bitpos:[7:0] ;default: x ; */ +/*description: GPIO32~39 APP CPU interrupt status*/ +#define GPIO_APPCPU_INT_H 0x000000FF +#define GPIO_APPCPU_INT_H_M ((GPIO_APPCPU_INT_H_V)<<(GPIO_APPCPU_INT_H_S)) +#define GPIO_APPCPU_INT_H_V 0xFF +#define GPIO_APPCPU_INT_H_S 0 + +#define GPIO_ACPU_NMI_INT1_REG (DR_REG_GPIO_BASE + 0x0078) +/* GPIO_APPCPU_NMI_INT_H : RO ;bitpos:[7:0] ;default: x ; */ +/*description: GPIO32~39 APP CPU non-maskable interrupt status*/ +#define GPIO_APPCPU_NMI_INT_H 0x000000FF +#define GPIO_APPCPU_NMI_INT_H_M ((GPIO_APPCPU_NMI_INT_H_V)<<(GPIO_APPCPU_NMI_INT_H_S)) +#define GPIO_APPCPU_NMI_INT_H_V 0xFF +#define GPIO_APPCPU_NMI_INT_H_S 0 + +#define GPIO_PCPU_INT1_REG (DR_REG_GPIO_BASE + 0x007c) +/* GPIO_PROCPU_INT_H : RO ;bitpos:[7:0] ;default: x ; */ +/*description: GPIO32~39 PRO CPU interrupt status*/ +#define GPIO_PROCPU_INT_H 0x000000FF +#define GPIO_PROCPU_INT_H_M ((GPIO_PROCPU_INT_H_V)<<(GPIO_PROCPU_INT_H_S)) +#define GPIO_PROCPU_INT_H_V 0xFF +#define GPIO_PROCPU_INT_H_S 0 + +#define GPIO_PCPU_NMI_INT1_REG (DR_REG_GPIO_BASE + 0x0080) +/* GPIO_PROCPU_NMI_INT_H : RO ;bitpos:[7:0] ;default: x ; */ +/*description: GPIO32~39 PRO CPU non-maskable interrupt status*/ +#define GPIO_PROCPU_NMI_INT_H 0x000000FF +#define GPIO_PROCPU_NMI_INT_H_M ((GPIO_PROCPU_NMI_INT_H_V)<<(GPIO_PROCPU_NMI_INT_H_S)) +#define GPIO_PROCPU_NMI_INT_H_V 0xFF +#define GPIO_PROCPU_NMI_INT_H_S 0 + +#define GPIO_CPUSDIO_INT1_REG (DR_REG_GPIO_BASE + 0x0084) +/* GPIO_SDIO_INT_H : RO ;bitpos:[7:0] ;default: x ; */ +/*description: SDIO's extent GPIO32~39 interrupt*/ +#define GPIO_SDIO_INT_H 0x000000FF +#define GPIO_SDIO_INT_H_M ((GPIO_SDIO_INT_H_V)<<(GPIO_SDIO_INT_H_S)) +#define GPIO_SDIO_INT_H_V 0xFF +#define GPIO_SDIO_INT_H_S 0 + +#define GPIO_REG(io_num) (GPIO_PIN0_REG + (io_num)*0x4) +#define GPIO_PIN_INT_ENA 0x0000001F +#define GPIO_PIN_INT_ENA_M ((GPIO_PIN_INT_ENA_V)<<(GPIO_PIN_INT_ENA_S)) +#define GPIO_PIN_INT_ENA_V 0x0000001F +#define GPIO_PIN_INT_ENA_S 13 +#define GPIO_PIN_CONFIG 0x00000003 +#define GPIO_PIN_CONFIG_M ((GPIO_PIN_CONFIG_V)<<(GPIO_PIN_CONFIG_S)) +#define GPIO_PIN_CONFIG_V 0x00000003 +#define GPIO_PIN_CONFIG_S 11 +#define GPIO_PIN_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN_WAKEUP_ENABLE_S 10 +#define GPIO_PIN_INT_TYPE 0x00000007 +#define GPIO_PIN_INT_TYPE_M ((GPIO_PIN_INT_TYPE_V)<<(GPIO_PIN_INT_TYPE_S)) +#define GPIO_PIN_INT_TYPE_V 0x00000007 +#define GPIO_PIN_INT_TYPE_S 7 +#define GPIO_PIN_PAD_DRIVER (BIT(2)) +#define GPIO_PIN_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN_PAD_DRIVER_V 0x1 +#define GPIO_PIN_PAD_DRIVER_S 2 + +#define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0x0088) +/* GPIO_PIN0_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN0_INT_ENA 0x0000001F +#define GPIO_PIN0_INT_ENA_M ((GPIO_PIN0_INT_ENA_V)<<(GPIO_PIN0_INT_ENA_S)) +#define GPIO_PIN0_INT_ENA_V 0x1F +#define GPIO_PIN0_INT_ENA_S 13 +/* GPIO_PIN0_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN0_CONFIG 0x00000003 +#define GPIO_PIN0_CONFIG_M ((GPIO_PIN0_CONFIG_V)<<(GPIO_PIN0_CONFIG_S)) +#define GPIO_PIN0_CONFIG_V 0x3 +#define GPIO_PIN0_CONFIG_S 11 +/* GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN0_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN0_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN0_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN0_WAKEUP_ENABLE_S 10 +/* GPIO_PIN0_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN0_INT_TYPE 0x00000007 +#define GPIO_PIN0_INT_TYPE_M ((GPIO_PIN0_INT_TYPE_V)<<(GPIO_PIN0_INT_TYPE_S)) +#define GPIO_PIN0_INT_TYPE_V 0x7 +#define GPIO_PIN0_INT_TYPE_S 7 +/* GPIO_PIN0_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN0_PAD_DRIVER (BIT(2)) +#define GPIO_PIN0_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN0_PAD_DRIVER_V 0x1 +#define GPIO_PIN0_PAD_DRIVER_S 2 + +#define GPIO_PIN1_REG (DR_REG_GPIO_BASE + 0x008c) +/* GPIO_PIN1_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN1_INT_ENA 0x0000001F +#define GPIO_PIN1_INT_ENA_M ((GPIO_PIN1_INT_ENA_V)<<(GPIO_PIN1_INT_ENA_S)) +#define GPIO_PIN1_INT_ENA_V 0x1F +#define GPIO_PIN1_INT_ENA_S 13 +/* GPIO_PIN1_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN1_CONFIG 0x00000003 +#define GPIO_PIN1_CONFIG_M ((GPIO_PIN1_CONFIG_V)<<(GPIO_PIN1_CONFIG_S)) +#define GPIO_PIN1_CONFIG_V 0x3 +#define GPIO_PIN1_CONFIG_S 11 +/* GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN1_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN1_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN1_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN1_WAKEUP_ENABLE_S 10 +/* GPIO_PIN1_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN1_INT_TYPE 0x00000007 +#define GPIO_PIN1_INT_TYPE_M ((GPIO_PIN1_INT_TYPE_V)<<(GPIO_PIN1_INT_TYPE_S)) +#define GPIO_PIN1_INT_TYPE_V 0x7 +#define GPIO_PIN1_INT_TYPE_S 7 +/* GPIO_PIN1_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN1_PAD_DRIVER (BIT(2)) +#define GPIO_PIN1_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN1_PAD_DRIVER_V 0x1 +#define GPIO_PIN1_PAD_DRIVER_S 2 + +#define GPIO_PIN2_REG (DR_REG_GPIO_BASE + 0x0090) +/* GPIO_PIN2_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN2_INT_ENA 0x0000001F +#define GPIO_PIN2_INT_ENA_M ((GPIO_PIN2_INT_ENA_V)<<(GPIO_PIN2_INT_ENA_S)) +#define GPIO_PIN2_INT_ENA_V 0x1F +#define GPIO_PIN2_INT_ENA_S 13 +/* GPIO_PIN2_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN2_CONFIG 0x00000003 +#define GPIO_PIN2_CONFIG_M ((GPIO_PIN2_CONFIG_V)<<(GPIO_PIN2_CONFIG_S)) +#define GPIO_PIN2_CONFIG_V 0x3 +#define GPIO_PIN2_CONFIG_S 11 +/* GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN2_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN2_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN2_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN2_WAKEUP_ENABLE_S 10 +/* GPIO_PIN2_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN2_INT_TYPE 0x00000007 +#define GPIO_PIN2_INT_TYPE_M ((GPIO_PIN2_INT_TYPE_V)<<(GPIO_PIN2_INT_TYPE_S)) +#define GPIO_PIN2_INT_TYPE_V 0x7 +#define GPIO_PIN2_INT_TYPE_S 7 +/* GPIO_PIN2_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN2_PAD_DRIVER (BIT(2)) +#define GPIO_PIN2_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN2_PAD_DRIVER_V 0x1 +#define GPIO_PIN2_PAD_DRIVER_S 2 + +#define GPIO_PIN3_REG (DR_REG_GPIO_BASE + 0x0094) +/* GPIO_PIN3_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN3_INT_ENA 0x0000001F +#define GPIO_PIN3_INT_ENA_M ((GPIO_PIN3_INT_ENA_V)<<(GPIO_PIN3_INT_ENA_S)) +#define GPIO_PIN3_INT_ENA_V 0x1F +#define GPIO_PIN3_INT_ENA_S 13 +/* GPIO_PIN3_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN3_CONFIG 0x00000003 +#define GPIO_PIN3_CONFIG_M ((GPIO_PIN3_CONFIG_V)<<(GPIO_PIN3_CONFIG_S)) +#define GPIO_PIN3_CONFIG_V 0x3 +#define GPIO_PIN3_CONFIG_S 11 +/* GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN3_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN3_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN3_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN3_WAKEUP_ENABLE_S 10 +/* GPIO_PIN3_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN3_INT_TYPE 0x00000007 +#define GPIO_PIN3_INT_TYPE_M ((GPIO_PIN3_INT_TYPE_V)<<(GPIO_PIN3_INT_TYPE_S)) +#define GPIO_PIN3_INT_TYPE_V 0x7 +#define GPIO_PIN3_INT_TYPE_S 7 +/* GPIO_PIN3_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN3_PAD_DRIVER (BIT(2)) +#define GPIO_PIN3_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN3_PAD_DRIVER_V 0x1 +#define GPIO_PIN3_PAD_DRIVER_S 2 + +#define GPIO_PIN4_REG (DR_REG_GPIO_BASE + 0x0098) +/* GPIO_PIN4_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN4_INT_ENA 0x0000001F +#define GPIO_PIN4_INT_ENA_M ((GPIO_PIN4_INT_ENA_V)<<(GPIO_PIN4_INT_ENA_S)) +#define GPIO_PIN4_INT_ENA_V 0x1F +#define GPIO_PIN4_INT_ENA_S 13 +/* GPIO_PIN4_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN4_CONFIG 0x00000003 +#define GPIO_PIN4_CONFIG_M ((GPIO_PIN4_CONFIG_V)<<(GPIO_PIN4_CONFIG_S)) +#define GPIO_PIN4_CONFIG_V 0x3 +#define GPIO_PIN4_CONFIG_S 11 +/* GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN4_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN4_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN4_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN4_WAKEUP_ENABLE_S 10 +/* GPIO_PIN4_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN4_INT_TYPE 0x00000007 +#define GPIO_PIN4_INT_TYPE_M ((GPIO_PIN4_INT_TYPE_V)<<(GPIO_PIN4_INT_TYPE_S)) +#define GPIO_PIN4_INT_TYPE_V 0x7 +#define GPIO_PIN4_INT_TYPE_S 7 +/* GPIO_PIN4_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN4_PAD_DRIVER (BIT(2)) +#define GPIO_PIN4_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN4_PAD_DRIVER_V 0x1 +#define GPIO_PIN4_PAD_DRIVER_S 2 + +#define GPIO_PIN5_REG (DR_REG_GPIO_BASE + 0x009c) +/* GPIO_PIN5_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN5_INT_ENA 0x0000001F +#define GPIO_PIN5_INT_ENA_M ((GPIO_PIN5_INT_ENA_V)<<(GPIO_PIN5_INT_ENA_S)) +#define GPIO_PIN5_INT_ENA_V 0x1F +#define GPIO_PIN5_INT_ENA_S 13 +/* GPIO_PIN5_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN5_CONFIG 0x00000003 +#define GPIO_PIN5_CONFIG_M ((GPIO_PIN5_CONFIG_V)<<(GPIO_PIN5_CONFIG_S)) +#define GPIO_PIN5_CONFIG_V 0x3 +#define GPIO_PIN5_CONFIG_S 11 +/* GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN5_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN5_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN5_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN5_WAKEUP_ENABLE_S 10 +/* GPIO_PIN5_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN5_INT_TYPE 0x00000007 +#define GPIO_PIN5_INT_TYPE_M ((GPIO_PIN5_INT_TYPE_V)<<(GPIO_PIN5_INT_TYPE_S)) +#define GPIO_PIN5_INT_TYPE_V 0x7 +#define GPIO_PIN5_INT_TYPE_S 7 +/* GPIO_PIN5_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN5_PAD_DRIVER (BIT(2)) +#define GPIO_PIN5_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN5_PAD_DRIVER_V 0x1 +#define GPIO_PIN5_PAD_DRIVER_S 2 + +#define GPIO_PIN6_REG (DR_REG_GPIO_BASE + 0x00a0) +/* GPIO_PIN6_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN6_INT_ENA 0x0000001F +#define GPIO_PIN6_INT_ENA_M ((GPIO_PIN6_INT_ENA_V)<<(GPIO_PIN6_INT_ENA_S)) +#define GPIO_PIN6_INT_ENA_V 0x1F +#define GPIO_PIN6_INT_ENA_S 13 +/* GPIO_PIN6_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN6_CONFIG 0x00000003 +#define GPIO_PIN6_CONFIG_M ((GPIO_PIN6_CONFIG_V)<<(GPIO_PIN6_CONFIG_S)) +#define GPIO_PIN6_CONFIG_V 0x3 +#define GPIO_PIN6_CONFIG_S 11 +/* GPIO_PIN6_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN6_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN6_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN6_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN6_WAKEUP_ENABLE_S 10 +/* GPIO_PIN6_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN6_INT_TYPE 0x00000007 +#define GPIO_PIN6_INT_TYPE_M ((GPIO_PIN6_INT_TYPE_V)<<(GPIO_PIN6_INT_TYPE_S)) +#define GPIO_PIN6_INT_TYPE_V 0x7 +#define GPIO_PIN6_INT_TYPE_S 7 +/* GPIO_PIN6_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN6_PAD_DRIVER (BIT(2)) +#define GPIO_PIN6_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN6_PAD_DRIVER_V 0x1 +#define GPIO_PIN6_PAD_DRIVER_S 2 + +#define GPIO_PIN7_REG (DR_REG_GPIO_BASE + 0x00a4) +/* GPIO_PIN7_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN7_INT_ENA 0x0000001F +#define GPIO_PIN7_INT_ENA_M ((GPIO_PIN7_INT_ENA_V)<<(GPIO_PIN7_INT_ENA_S)) +#define GPIO_PIN7_INT_ENA_V 0x1F +#define GPIO_PIN7_INT_ENA_S 13 +/* GPIO_PIN7_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN7_CONFIG 0x00000003 +#define GPIO_PIN7_CONFIG_M ((GPIO_PIN7_CONFIG_V)<<(GPIO_PIN7_CONFIG_S)) +#define GPIO_PIN7_CONFIG_V 0x3 +#define GPIO_PIN7_CONFIG_S 11 +/* GPIO_PIN7_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN7_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN7_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN7_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN7_WAKEUP_ENABLE_S 10 +/* GPIO_PIN7_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN7_INT_TYPE 0x00000007 +#define GPIO_PIN7_INT_TYPE_M ((GPIO_PIN7_INT_TYPE_V)<<(GPIO_PIN7_INT_TYPE_S)) +#define GPIO_PIN7_INT_TYPE_V 0x7 +#define GPIO_PIN7_INT_TYPE_S 7 +/* GPIO_PIN7_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN7_PAD_DRIVER (BIT(2)) +#define GPIO_PIN7_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN7_PAD_DRIVER_V 0x1 +#define GPIO_PIN7_PAD_DRIVER_S 2 + +#define GPIO_PIN8_REG (DR_REG_GPIO_BASE + 0x00a8) +/* GPIO_PIN8_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN8_INT_ENA 0x0000001F +#define GPIO_PIN8_INT_ENA_M ((GPIO_PIN8_INT_ENA_V)<<(GPIO_PIN8_INT_ENA_S)) +#define GPIO_PIN8_INT_ENA_V 0x1F +#define GPIO_PIN8_INT_ENA_S 13 +/* GPIO_PIN8_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN8_CONFIG 0x00000003 +#define GPIO_PIN8_CONFIG_M ((GPIO_PIN8_CONFIG_V)<<(GPIO_PIN8_CONFIG_S)) +#define GPIO_PIN8_CONFIG_V 0x3 +#define GPIO_PIN8_CONFIG_S 11 +/* GPIO_PIN8_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN8_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN8_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN8_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN8_WAKEUP_ENABLE_S 10 +/* GPIO_PIN8_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN8_INT_TYPE 0x00000007 +#define GPIO_PIN8_INT_TYPE_M ((GPIO_PIN8_INT_TYPE_V)<<(GPIO_PIN8_INT_TYPE_S)) +#define GPIO_PIN8_INT_TYPE_V 0x7 +#define GPIO_PIN8_INT_TYPE_S 7 +/* GPIO_PIN8_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN8_PAD_DRIVER (BIT(2)) +#define GPIO_PIN8_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN8_PAD_DRIVER_V 0x1 +#define GPIO_PIN8_PAD_DRIVER_S 2 + +#define GPIO_PIN9_REG (DR_REG_GPIO_BASE + 0x00ac) +/* GPIO_PIN9_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN9_INT_ENA 0x0000001F +#define GPIO_PIN9_INT_ENA_M ((GPIO_PIN9_INT_ENA_V)<<(GPIO_PIN9_INT_ENA_S)) +#define GPIO_PIN9_INT_ENA_V 0x1F +#define GPIO_PIN9_INT_ENA_S 13 +/* GPIO_PIN9_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN9_CONFIG 0x00000003 +#define GPIO_PIN9_CONFIG_M ((GPIO_PIN9_CONFIG_V)<<(GPIO_PIN9_CONFIG_S)) +#define GPIO_PIN9_CONFIG_V 0x3 +#define GPIO_PIN9_CONFIG_S 11 +/* GPIO_PIN9_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN9_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN9_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN9_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN9_WAKEUP_ENABLE_S 10 +/* GPIO_PIN9_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN9_INT_TYPE 0x00000007 +#define GPIO_PIN9_INT_TYPE_M ((GPIO_PIN9_INT_TYPE_V)<<(GPIO_PIN9_INT_TYPE_S)) +#define GPIO_PIN9_INT_TYPE_V 0x7 +#define GPIO_PIN9_INT_TYPE_S 7 +/* GPIO_PIN9_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN9_PAD_DRIVER (BIT(2)) +#define GPIO_PIN9_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN9_PAD_DRIVER_V 0x1 +#define GPIO_PIN9_PAD_DRIVER_S 2 + +#define GPIO_PIN10_REG (DR_REG_GPIO_BASE + 0x00b0) +/* GPIO_PIN10_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN10_INT_ENA 0x0000001F +#define GPIO_PIN10_INT_ENA_M ((GPIO_PIN10_INT_ENA_V)<<(GPIO_PIN10_INT_ENA_S)) +#define GPIO_PIN10_INT_ENA_V 0x1F +#define GPIO_PIN10_INT_ENA_S 13 +/* GPIO_PIN10_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN10_CONFIG 0x00000003 +#define GPIO_PIN10_CONFIG_M ((GPIO_PIN10_CONFIG_V)<<(GPIO_PIN10_CONFIG_S)) +#define GPIO_PIN10_CONFIG_V 0x3 +#define GPIO_PIN10_CONFIG_S 11 +/* GPIO_PIN10_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN10_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN10_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN10_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN10_WAKEUP_ENABLE_S 10 +/* GPIO_PIN10_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN10_INT_TYPE 0x00000007 +#define GPIO_PIN10_INT_TYPE_M ((GPIO_PIN10_INT_TYPE_V)<<(GPIO_PIN10_INT_TYPE_S)) +#define GPIO_PIN10_INT_TYPE_V 0x7 +#define GPIO_PIN10_INT_TYPE_S 7 +/* GPIO_PIN10_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN10_PAD_DRIVER (BIT(2)) +#define GPIO_PIN10_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN10_PAD_DRIVER_V 0x1 +#define GPIO_PIN10_PAD_DRIVER_S 2 + +#define GPIO_PIN11_REG (DR_REG_GPIO_BASE + 0x00b4) +/* GPIO_PIN11_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN11_INT_ENA 0x0000001F +#define GPIO_PIN11_INT_ENA_M ((GPIO_PIN11_INT_ENA_V)<<(GPIO_PIN11_INT_ENA_S)) +#define GPIO_PIN11_INT_ENA_V 0x1F +#define GPIO_PIN11_INT_ENA_S 13 +/* GPIO_PIN11_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN11_CONFIG 0x00000003 +#define GPIO_PIN11_CONFIG_M ((GPIO_PIN11_CONFIG_V)<<(GPIO_PIN11_CONFIG_S)) +#define GPIO_PIN11_CONFIG_V 0x3 +#define GPIO_PIN11_CONFIG_S 11 +/* GPIO_PIN11_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN11_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN11_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN11_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN11_WAKEUP_ENABLE_S 10 +/* GPIO_PIN11_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN11_INT_TYPE 0x00000007 +#define GPIO_PIN11_INT_TYPE_M ((GPIO_PIN11_INT_TYPE_V)<<(GPIO_PIN11_INT_TYPE_S)) +#define GPIO_PIN11_INT_TYPE_V 0x7 +#define GPIO_PIN11_INT_TYPE_S 7 +/* GPIO_PIN11_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN11_PAD_DRIVER (BIT(2)) +#define GPIO_PIN11_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN11_PAD_DRIVER_V 0x1 +#define GPIO_PIN11_PAD_DRIVER_S 2 + +#define GPIO_PIN12_REG (DR_REG_GPIO_BASE + 0x00b8) +/* GPIO_PIN12_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN12_INT_ENA 0x0000001F +#define GPIO_PIN12_INT_ENA_M ((GPIO_PIN12_INT_ENA_V)<<(GPIO_PIN12_INT_ENA_S)) +#define GPIO_PIN12_INT_ENA_V 0x1F +#define GPIO_PIN12_INT_ENA_S 13 +/* GPIO_PIN12_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN12_CONFIG 0x00000003 +#define GPIO_PIN12_CONFIG_M ((GPIO_PIN12_CONFIG_V)<<(GPIO_PIN12_CONFIG_S)) +#define GPIO_PIN12_CONFIG_V 0x3 +#define GPIO_PIN12_CONFIG_S 11 +/* GPIO_PIN12_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN12_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN12_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN12_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN12_WAKEUP_ENABLE_S 10 +/* GPIO_PIN12_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN12_INT_TYPE 0x00000007 +#define GPIO_PIN12_INT_TYPE_M ((GPIO_PIN12_INT_TYPE_V)<<(GPIO_PIN12_INT_TYPE_S)) +#define GPIO_PIN12_INT_TYPE_V 0x7 +#define GPIO_PIN12_INT_TYPE_S 7 +/* GPIO_PIN12_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN12_PAD_DRIVER (BIT(2)) +#define GPIO_PIN12_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN12_PAD_DRIVER_V 0x1 +#define GPIO_PIN12_PAD_DRIVER_S 2 + +#define GPIO_PIN13_REG (DR_REG_GPIO_BASE + 0x00bc) +/* GPIO_PIN13_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN13_INT_ENA 0x0000001F +#define GPIO_PIN13_INT_ENA_M ((GPIO_PIN13_INT_ENA_V)<<(GPIO_PIN13_INT_ENA_S)) +#define GPIO_PIN13_INT_ENA_V 0x1F +#define GPIO_PIN13_INT_ENA_S 13 +/* GPIO_PIN13_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN13_CONFIG 0x00000003 +#define GPIO_PIN13_CONFIG_M ((GPIO_PIN13_CONFIG_V)<<(GPIO_PIN13_CONFIG_S)) +#define GPIO_PIN13_CONFIG_V 0x3 +#define GPIO_PIN13_CONFIG_S 11 +/* GPIO_PIN13_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN13_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN13_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN13_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN13_WAKEUP_ENABLE_S 10 +/* GPIO_PIN13_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN13_INT_TYPE 0x00000007 +#define GPIO_PIN13_INT_TYPE_M ((GPIO_PIN13_INT_TYPE_V)<<(GPIO_PIN13_INT_TYPE_S)) +#define GPIO_PIN13_INT_TYPE_V 0x7 +#define GPIO_PIN13_INT_TYPE_S 7 +/* GPIO_PIN13_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN13_PAD_DRIVER (BIT(2)) +#define GPIO_PIN13_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN13_PAD_DRIVER_V 0x1 +#define GPIO_PIN13_PAD_DRIVER_S 2 + +#define GPIO_PIN14_REG (DR_REG_GPIO_BASE + 0x00c0) +/* GPIO_PIN14_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN14_INT_ENA 0x0000001F +#define GPIO_PIN14_INT_ENA_M ((GPIO_PIN14_INT_ENA_V)<<(GPIO_PIN14_INT_ENA_S)) +#define GPIO_PIN14_INT_ENA_V 0x1F +#define GPIO_PIN14_INT_ENA_S 13 +/* GPIO_PIN14_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN14_CONFIG 0x00000003 +#define GPIO_PIN14_CONFIG_M ((GPIO_PIN14_CONFIG_V)<<(GPIO_PIN14_CONFIG_S)) +#define GPIO_PIN14_CONFIG_V 0x3 +#define GPIO_PIN14_CONFIG_S 11 +/* GPIO_PIN14_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN14_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN14_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN14_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN14_WAKEUP_ENABLE_S 10 +/* GPIO_PIN14_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN14_INT_TYPE 0x00000007 +#define GPIO_PIN14_INT_TYPE_M ((GPIO_PIN14_INT_TYPE_V)<<(GPIO_PIN14_INT_TYPE_S)) +#define GPIO_PIN14_INT_TYPE_V 0x7 +#define GPIO_PIN14_INT_TYPE_S 7 +/* GPIO_PIN14_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN14_PAD_DRIVER (BIT(2)) +#define GPIO_PIN14_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN14_PAD_DRIVER_V 0x1 +#define GPIO_PIN14_PAD_DRIVER_S 2 + +#define GPIO_PIN15_REG (DR_REG_GPIO_BASE + 0x00c4) +/* GPIO_PIN15_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN15_INT_ENA 0x0000001F +#define GPIO_PIN15_INT_ENA_M ((GPIO_PIN15_INT_ENA_V)<<(GPIO_PIN15_INT_ENA_S)) +#define GPIO_PIN15_INT_ENA_V 0x1F +#define GPIO_PIN15_INT_ENA_S 13 +/* GPIO_PIN15_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN15_CONFIG 0x00000003 +#define GPIO_PIN15_CONFIG_M ((GPIO_PIN15_CONFIG_V)<<(GPIO_PIN15_CONFIG_S)) +#define GPIO_PIN15_CONFIG_V 0x3 +#define GPIO_PIN15_CONFIG_S 11 +/* GPIO_PIN15_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN15_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN15_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN15_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN15_WAKEUP_ENABLE_S 10 +/* GPIO_PIN15_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN15_INT_TYPE 0x00000007 +#define GPIO_PIN15_INT_TYPE_M ((GPIO_PIN15_INT_TYPE_V)<<(GPIO_PIN15_INT_TYPE_S)) +#define GPIO_PIN15_INT_TYPE_V 0x7 +#define GPIO_PIN15_INT_TYPE_S 7 +/* GPIO_PIN15_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN15_PAD_DRIVER (BIT(2)) +#define GPIO_PIN15_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN15_PAD_DRIVER_V 0x1 +#define GPIO_PIN15_PAD_DRIVER_S 2 + +#define GPIO_PIN16_REG (DR_REG_GPIO_BASE + 0x00c8) +/* GPIO_PIN16_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN16_INT_ENA 0x0000001F +#define GPIO_PIN16_INT_ENA_M ((GPIO_PIN16_INT_ENA_V)<<(GPIO_PIN16_INT_ENA_S)) +#define GPIO_PIN16_INT_ENA_V 0x1F +#define GPIO_PIN16_INT_ENA_S 13 +/* GPIO_PIN16_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN16_CONFIG 0x00000003 +#define GPIO_PIN16_CONFIG_M ((GPIO_PIN16_CONFIG_V)<<(GPIO_PIN16_CONFIG_S)) +#define GPIO_PIN16_CONFIG_V 0x3 +#define GPIO_PIN16_CONFIG_S 11 +/* GPIO_PIN16_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN16_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN16_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN16_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN16_WAKEUP_ENABLE_S 10 +/* GPIO_PIN16_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN16_INT_TYPE 0x00000007 +#define GPIO_PIN16_INT_TYPE_M ((GPIO_PIN16_INT_TYPE_V)<<(GPIO_PIN16_INT_TYPE_S)) +#define GPIO_PIN16_INT_TYPE_V 0x7 +#define GPIO_PIN16_INT_TYPE_S 7 +/* GPIO_PIN16_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN16_PAD_DRIVER (BIT(2)) +#define GPIO_PIN16_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN16_PAD_DRIVER_V 0x1 +#define GPIO_PIN16_PAD_DRIVER_S 2 + +#define GPIO_PIN17_REG (DR_REG_GPIO_BASE + 0x00cc) +/* GPIO_PIN17_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN17_INT_ENA 0x0000001F +#define GPIO_PIN17_INT_ENA_M ((GPIO_PIN17_INT_ENA_V)<<(GPIO_PIN17_INT_ENA_S)) +#define GPIO_PIN17_INT_ENA_V 0x1F +#define GPIO_PIN17_INT_ENA_S 13 +/* GPIO_PIN17_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN17_CONFIG 0x00000003 +#define GPIO_PIN17_CONFIG_M ((GPIO_PIN17_CONFIG_V)<<(GPIO_PIN17_CONFIG_S)) +#define GPIO_PIN17_CONFIG_V 0x3 +#define GPIO_PIN17_CONFIG_S 11 +/* GPIO_PIN17_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN17_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN17_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN17_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN17_WAKEUP_ENABLE_S 10 +/* GPIO_PIN17_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN17_INT_TYPE 0x00000007 +#define GPIO_PIN17_INT_TYPE_M ((GPIO_PIN17_INT_TYPE_V)<<(GPIO_PIN17_INT_TYPE_S)) +#define GPIO_PIN17_INT_TYPE_V 0x7 +#define GPIO_PIN17_INT_TYPE_S 7 +/* GPIO_PIN17_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN17_PAD_DRIVER (BIT(2)) +#define GPIO_PIN17_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN17_PAD_DRIVER_V 0x1 +#define GPIO_PIN17_PAD_DRIVER_S 2 + +#define GPIO_PIN18_REG (DR_REG_GPIO_BASE + 0x00d0) +/* GPIO_PIN18_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN18_INT_ENA 0x0000001F +#define GPIO_PIN18_INT_ENA_M ((GPIO_PIN18_INT_ENA_V)<<(GPIO_PIN18_INT_ENA_S)) +#define GPIO_PIN18_INT_ENA_V 0x1F +#define GPIO_PIN18_INT_ENA_S 13 +/* GPIO_PIN18_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN18_CONFIG 0x00000003 +#define GPIO_PIN18_CONFIG_M ((GPIO_PIN18_CONFIG_V)<<(GPIO_PIN18_CONFIG_S)) +#define GPIO_PIN18_CONFIG_V 0x3 +#define GPIO_PIN18_CONFIG_S 11 +/* GPIO_PIN18_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN18_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN18_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN18_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN18_WAKEUP_ENABLE_S 10 +/* GPIO_PIN18_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN18_INT_TYPE 0x00000007 +#define GPIO_PIN18_INT_TYPE_M ((GPIO_PIN18_INT_TYPE_V)<<(GPIO_PIN18_INT_TYPE_S)) +#define GPIO_PIN18_INT_TYPE_V 0x7 +#define GPIO_PIN18_INT_TYPE_S 7 +/* GPIO_PIN18_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN18_PAD_DRIVER (BIT(2)) +#define GPIO_PIN18_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN18_PAD_DRIVER_V 0x1 +#define GPIO_PIN18_PAD_DRIVER_S 2 + +#define GPIO_PIN19_REG (DR_REG_GPIO_BASE + 0x00d4) +/* GPIO_PIN19_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN19_INT_ENA 0x0000001F +#define GPIO_PIN19_INT_ENA_M ((GPIO_PIN19_INT_ENA_V)<<(GPIO_PIN19_INT_ENA_S)) +#define GPIO_PIN19_INT_ENA_V 0x1F +#define GPIO_PIN19_INT_ENA_S 13 +/* GPIO_PIN19_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN19_CONFIG 0x00000003 +#define GPIO_PIN19_CONFIG_M ((GPIO_PIN19_CONFIG_V)<<(GPIO_PIN19_CONFIG_S)) +#define GPIO_PIN19_CONFIG_V 0x3 +#define GPIO_PIN19_CONFIG_S 11 +/* GPIO_PIN19_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN19_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN19_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN19_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN19_WAKEUP_ENABLE_S 10 +/* GPIO_PIN19_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN19_INT_TYPE 0x00000007 +#define GPIO_PIN19_INT_TYPE_M ((GPIO_PIN19_INT_TYPE_V)<<(GPIO_PIN19_INT_TYPE_S)) +#define GPIO_PIN19_INT_TYPE_V 0x7 +#define GPIO_PIN19_INT_TYPE_S 7 +/* GPIO_PIN19_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN19_PAD_DRIVER (BIT(2)) +#define GPIO_PIN19_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN19_PAD_DRIVER_V 0x1 +#define GPIO_PIN19_PAD_DRIVER_S 2 + +#define GPIO_PIN20_REG (DR_REG_GPIO_BASE + 0x00d8) +/* GPIO_PIN20_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-mask interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-mask interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN20_INT_ENA 0x0000001F +#define GPIO_PIN20_INT_ENA_M ((GPIO_PIN20_INT_ENA_V)<<(GPIO_PIN20_INT_ENA_S)) +#define GPIO_PIN20_INT_ENA_V 0x1F +#define GPIO_PIN20_INT_ENA_S 13 +/* GPIO_PIN20_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN20_CONFIG 0x00000003 +#define GPIO_PIN20_CONFIG_M ((GPIO_PIN20_CONFIG_V)<<(GPIO_PIN20_CONFIG_S)) +#define GPIO_PIN20_CONFIG_V 0x3 +#define GPIO_PIN20_CONFIG_S 11 +/* GPIO_PIN20_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN20_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN20_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN20_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN20_WAKEUP_ENABLE_S 10 +/* GPIO_PIN20_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN20_INT_TYPE 0x00000007 +#define GPIO_PIN20_INT_TYPE_M ((GPIO_PIN20_INT_TYPE_V)<<(GPIO_PIN20_INT_TYPE_S)) +#define GPIO_PIN20_INT_TYPE_V 0x7 +#define GPIO_PIN20_INT_TYPE_S 7 +/* GPIO_PIN20_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN20_PAD_DRIVER (BIT(2)) +#define GPIO_PIN20_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN20_PAD_DRIVER_V 0x1 +#define GPIO_PIN20_PAD_DRIVER_S 2 + +#define GPIO_PIN21_REG (DR_REG_GPIO_BASE + 0x00dc) +/* GPIO_PIN21_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN21_INT_ENA 0x0000001F +#define GPIO_PIN21_INT_ENA_M ((GPIO_PIN21_INT_ENA_V)<<(GPIO_PIN21_INT_ENA_S)) +#define GPIO_PIN21_INT_ENA_V 0x1F +#define GPIO_PIN21_INT_ENA_S 13 +/* GPIO_PIN21_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN21_CONFIG 0x00000003 +#define GPIO_PIN21_CONFIG_M ((GPIO_PIN21_CONFIG_V)<<(GPIO_PIN21_CONFIG_S)) +#define GPIO_PIN21_CONFIG_V 0x3 +#define GPIO_PIN21_CONFIG_S 11 +/* GPIO_PIN21_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN21_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN21_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN21_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN21_WAKEUP_ENABLE_S 10 +/* GPIO_PIN21_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN21_INT_TYPE 0x00000007 +#define GPIO_PIN21_INT_TYPE_M ((GPIO_PIN21_INT_TYPE_V)<<(GPIO_PIN21_INT_TYPE_S)) +#define GPIO_PIN21_INT_TYPE_V 0x7 +#define GPIO_PIN21_INT_TYPE_S 7 +/* GPIO_PIN21_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN21_PAD_DRIVER (BIT(2)) +#define GPIO_PIN21_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN21_PAD_DRIVER_V 0x1 +#define GPIO_PIN21_PAD_DRIVER_S 2 + +#define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0x00e0) +/* GPIO_PIN22_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: */ +#define GPIO_PIN22_INT_ENA 0x0000001F +#define GPIO_PIN22_INT_ENA_M ((GPIO_PIN22_INT_ENA_V)<<(GPIO_PIN22_INT_ENA_S)) +#define GPIO_PIN22_INT_ENA_V 0x1F +#define GPIO_PIN22_INT_ENA_S 13 +/* GPIO_PIN22_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN22_CONFIG 0x00000003 +#define GPIO_PIN22_CONFIG_M ((GPIO_PIN22_CONFIG_V)<<(GPIO_PIN22_CONFIG_S)) +#define GPIO_PIN22_CONFIG_V 0x3 +#define GPIO_PIN22_CONFIG_S 11 +/* GPIO_PIN22_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN22_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN22_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN22_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN22_WAKEUP_ENABLE_S 10 +/* GPIO_PIN22_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN22_INT_TYPE 0x00000007 +#define GPIO_PIN22_INT_TYPE_M ((GPIO_PIN22_INT_TYPE_V)<<(GPIO_PIN22_INT_TYPE_S)) +#define GPIO_PIN22_INT_TYPE_V 0x7 +#define GPIO_PIN22_INT_TYPE_S 7 +/* GPIO_PIN22_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: */ +#define GPIO_PIN22_PAD_DRIVER (BIT(2)) +#define GPIO_PIN22_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN22_PAD_DRIVER_V 0x1 +#define GPIO_PIN22_PAD_DRIVER_S 2 + +#define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0x00e4) +/* GPIO_PIN23_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN23_INT_ENA 0x0000001F +#define GPIO_PIN23_INT_ENA_M ((GPIO_PIN23_INT_ENA_V)<<(GPIO_PIN23_INT_ENA_S)) +#define GPIO_PIN23_INT_ENA_V 0x1F +#define GPIO_PIN23_INT_ENA_S 13 +/* GPIO_PIN23_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN23_CONFIG 0x00000003 +#define GPIO_PIN23_CONFIG_M ((GPIO_PIN23_CONFIG_V)<<(GPIO_PIN23_CONFIG_S)) +#define GPIO_PIN23_CONFIG_V 0x3 +#define GPIO_PIN23_CONFIG_S 11 +/* GPIO_PIN23_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN23_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN23_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN23_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN23_WAKEUP_ENABLE_S 10 +/* GPIO_PIN23_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN23_INT_TYPE 0x00000007 +#define GPIO_PIN23_INT_TYPE_M ((GPIO_PIN23_INT_TYPE_V)<<(GPIO_PIN23_INT_TYPE_S)) +#define GPIO_PIN23_INT_TYPE_V 0x7 +#define GPIO_PIN23_INT_TYPE_S 7 +/* GPIO_PIN23_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN23_PAD_DRIVER (BIT(2)) +#define GPIO_PIN23_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN23_PAD_DRIVER_V 0x1 +#define GPIO_PIN23_PAD_DRIVER_S 2 + +#define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0x00e8) +/* GPIO_PIN24_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN24_INT_ENA 0x0000001F +#define GPIO_PIN24_INT_ENA_M ((GPIO_PIN24_INT_ENA_V)<<(GPIO_PIN24_INT_ENA_S)) +#define GPIO_PIN24_INT_ENA_V 0x1F +#define GPIO_PIN24_INT_ENA_S 13 +/* GPIO_PIN24_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN24_CONFIG 0x00000003 +#define GPIO_PIN24_CONFIG_M ((GPIO_PIN24_CONFIG_V)<<(GPIO_PIN24_CONFIG_S)) +#define GPIO_PIN24_CONFIG_V 0x3 +#define GPIO_PIN24_CONFIG_S 11 +/* GPIO_PIN24_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN24_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN24_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN24_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN24_WAKEUP_ENABLE_S 10 +/* GPIO_PIN24_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN24_INT_TYPE 0x00000007 +#define GPIO_PIN24_INT_TYPE_M ((GPIO_PIN24_INT_TYPE_V)<<(GPIO_PIN24_INT_TYPE_S)) +#define GPIO_PIN24_INT_TYPE_V 0x7 +#define GPIO_PIN24_INT_TYPE_S 7 +/* GPIO_PIN24_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN24_PAD_DRIVER (BIT(2)) +#define GPIO_PIN24_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN24_PAD_DRIVER_V 0x1 +#define GPIO_PIN24_PAD_DRIVER_S 2 + +#define GPIO_PIN25_REG (DR_REG_GPIO_BASE + 0x00ec) +/* GPIO_PIN25_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN25_INT_ENA 0x0000001F +#define GPIO_PIN25_INT_ENA_M ((GPIO_PIN25_INT_ENA_V)<<(GPIO_PIN25_INT_ENA_S)) +#define GPIO_PIN25_INT_ENA_V 0x1F +#define GPIO_PIN25_INT_ENA_S 13 +/* GPIO_PIN25_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN25_CONFIG 0x00000003 +#define GPIO_PIN25_CONFIG_M ((GPIO_PIN25_CONFIG_V)<<(GPIO_PIN25_CONFIG_S)) +#define GPIO_PIN25_CONFIG_V 0x3 +#define GPIO_PIN25_CONFIG_S 11 +/* GPIO_PIN25_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN25_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN25_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN25_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN25_WAKEUP_ENABLE_S 10 +/* GPIO_PIN25_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN25_INT_TYPE 0x00000007 +#define GPIO_PIN25_INT_TYPE_M ((GPIO_PIN25_INT_TYPE_V)<<(GPIO_PIN25_INT_TYPE_S)) +#define GPIO_PIN25_INT_TYPE_V 0x7 +#define GPIO_PIN25_INT_TYPE_S 7 +/* GPIO_PIN25_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN25_PAD_DRIVER (BIT(2)) +#define GPIO_PIN25_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN25_PAD_DRIVER_V 0x1 +#define GPIO_PIN25_PAD_DRIVER_S 2 + +#define GPIO_PIN26_REG (DR_REG_GPIO_BASE + 0x00f0) +/* GPIO_PIN26_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN26_INT_ENA 0x0000001F +#define GPIO_PIN26_INT_ENA_M ((GPIO_PIN26_INT_ENA_V)<<(GPIO_PIN26_INT_ENA_S)) +#define GPIO_PIN26_INT_ENA_V 0x1F +#define GPIO_PIN26_INT_ENA_S 13 +/* GPIO_PIN26_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN26_CONFIG 0x00000003 +#define GPIO_PIN26_CONFIG_M ((GPIO_PIN26_CONFIG_V)<<(GPIO_PIN26_CONFIG_S)) +#define GPIO_PIN26_CONFIG_V 0x3 +#define GPIO_PIN26_CONFIG_S 11 +/* GPIO_PIN26_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN26_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN26_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN26_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN26_WAKEUP_ENABLE_S 10 +/* GPIO_PIN26_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN26_INT_TYPE 0x00000007 +#define GPIO_PIN26_INT_TYPE_M ((GPIO_PIN26_INT_TYPE_V)<<(GPIO_PIN26_INT_TYPE_S)) +#define GPIO_PIN26_INT_TYPE_V 0x7 +#define GPIO_PIN26_INT_TYPE_S 7 +/* GPIO_PIN26_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN26_PAD_DRIVER (BIT(2)) +#define GPIO_PIN26_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN26_PAD_DRIVER_V 0x1 +#define GPIO_PIN26_PAD_DRIVER_S 2 + +#define GPIO_PIN27_REG (DR_REG_GPIO_BASE + 0x00f4) +/* GPIO_PIN27_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN27_INT_ENA 0x0000001F +#define GPIO_PIN27_INT_ENA_M ((GPIO_PIN27_INT_ENA_V)<<(GPIO_PIN27_INT_ENA_S)) +#define GPIO_PIN27_INT_ENA_V 0x1F +#define GPIO_PIN27_INT_ENA_S 13 +/* GPIO_PIN27_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN27_CONFIG 0x00000003 +#define GPIO_PIN27_CONFIG_M ((GPIO_PIN27_CONFIG_V)<<(GPIO_PIN27_CONFIG_S)) +#define GPIO_PIN27_CONFIG_V 0x3 +#define GPIO_PIN27_CONFIG_S 11 +/* GPIO_PIN27_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN27_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN27_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN27_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN27_WAKEUP_ENABLE_S 10 +/* GPIO_PIN27_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN27_INT_TYPE 0x00000007 +#define GPIO_PIN27_INT_TYPE_M ((GPIO_PIN27_INT_TYPE_V)<<(GPIO_PIN27_INT_TYPE_S)) +#define GPIO_PIN27_INT_TYPE_V 0x7 +#define GPIO_PIN27_INT_TYPE_S 7 +/* GPIO_PIN27_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN27_PAD_DRIVER (BIT(2)) +#define GPIO_PIN27_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN27_PAD_DRIVER_V 0x1 +#define GPIO_PIN27_PAD_DRIVER_S 2 + +#define GPIO_PIN28_REG (DR_REG_GPIO_BASE + 0x00f8) +/* GPIO_PIN28_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN28_INT_ENA 0x0000001F +#define GPIO_PIN28_INT_ENA_M ((GPIO_PIN28_INT_ENA_V)<<(GPIO_PIN28_INT_ENA_S)) +#define GPIO_PIN28_INT_ENA_V 0x1F +#define GPIO_PIN28_INT_ENA_S 13 +/* GPIO_PIN28_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN28_CONFIG 0x00000003 +#define GPIO_PIN28_CONFIG_M ((GPIO_PIN28_CONFIG_V)<<(GPIO_PIN28_CONFIG_S)) +#define GPIO_PIN28_CONFIG_V 0x3 +#define GPIO_PIN28_CONFIG_S 11 +/* GPIO_PIN28_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN28_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN28_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN28_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN28_WAKEUP_ENABLE_S 10 +/* GPIO_PIN28_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN28_INT_TYPE 0x00000007 +#define GPIO_PIN28_INT_TYPE_M ((GPIO_PIN28_INT_TYPE_V)<<(GPIO_PIN28_INT_TYPE_S)) +#define GPIO_PIN28_INT_TYPE_V 0x7 +#define GPIO_PIN28_INT_TYPE_S 7 +/* GPIO_PIN28_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN28_PAD_DRIVER (BIT(2)) +#define GPIO_PIN28_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN28_PAD_DRIVER_V 0x1 +#define GPIO_PIN28_PAD_DRIVER_S 2 + +#define GPIO_PIN29_REG (DR_REG_GPIO_BASE + 0x00fc) +/* GPIO_PIN29_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN29_INT_ENA 0x0000001F +#define GPIO_PIN29_INT_ENA_M ((GPIO_PIN29_INT_ENA_V)<<(GPIO_PIN29_INT_ENA_S)) +#define GPIO_PIN29_INT_ENA_V 0x1F +#define GPIO_PIN29_INT_ENA_S 13 +/* GPIO_PIN29_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN29_CONFIG 0x00000003 +#define GPIO_PIN29_CONFIG_M ((GPIO_PIN29_CONFIG_V)<<(GPIO_PIN29_CONFIG_S)) +#define GPIO_PIN29_CONFIG_V 0x3 +#define GPIO_PIN29_CONFIG_S 11 +/* GPIO_PIN29_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN29_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN29_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN29_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN29_WAKEUP_ENABLE_S 10 +/* GPIO_PIN29_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN29_INT_TYPE 0x00000007 +#define GPIO_PIN29_INT_TYPE_M ((GPIO_PIN29_INT_TYPE_V)<<(GPIO_PIN29_INT_TYPE_S)) +#define GPIO_PIN29_INT_TYPE_V 0x7 +#define GPIO_PIN29_INT_TYPE_S 7 +/* GPIO_PIN29_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN29_PAD_DRIVER (BIT(2)) +#define GPIO_PIN29_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN29_PAD_DRIVER_V 0x1 +#define GPIO_PIN29_PAD_DRIVER_S 2 + +#define GPIO_PIN30_REG (DR_REG_GPIO_BASE + 0x0100) +/* GPIO_PIN30_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN30_INT_ENA 0x0000001F +#define GPIO_PIN30_INT_ENA_M ((GPIO_PIN30_INT_ENA_V)<<(GPIO_PIN30_INT_ENA_S)) +#define GPIO_PIN30_INT_ENA_V 0x1F +#define GPIO_PIN30_INT_ENA_S 13 +/* GPIO_PIN30_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN30_CONFIG 0x00000003 +#define GPIO_PIN30_CONFIG_M ((GPIO_PIN30_CONFIG_V)<<(GPIO_PIN30_CONFIG_S)) +#define GPIO_PIN30_CONFIG_V 0x3 +#define GPIO_PIN30_CONFIG_S 11 +/* GPIO_PIN30_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN30_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN30_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN30_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN30_WAKEUP_ENABLE_S 10 +/* GPIO_PIN30_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN30_INT_TYPE 0x00000007 +#define GPIO_PIN30_INT_TYPE_M ((GPIO_PIN30_INT_TYPE_V)<<(GPIO_PIN30_INT_TYPE_S)) +#define GPIO_PIN30_INT_TYPE_V 0x7 +#define GPIO_PIN30_INT_TYPE_S 7 +/* GPIO_PIN30_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN30_PAD_DRIVER (BIT(2)) +#define GPIO_PIN30_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN30_PAD_DRIVER_V 0x1 +#define GPIO_PIN30_PAD_DRIVER_S 2 + +#define GPIO_PIN31_REG (DR_REG_GPIO_BASE + 0x0104) +/* GPIO_PIN31_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN31_INT_ENA 0x0000001F +#define GPIO_PIN31_INT_ENA_M ((GPIO_PIN31_INT_ENA_V)<<(GPIO_PIN31_INT_ENA_S)) +#define GPIO_PIN31_INT_ENA_V 0x1F +#define GPIO_PIN31_INT_ENA_S 13 +/* GPIO_PIN31_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN31_CONFIG 0x00000003 +#define GPIO_PIN31_CONFIG_M ((GPIO_PIN31_CONFIG_V)<<(GPIO_PIN31_CONFIG_S)) +#define GPIO_PIN31_CONFIG_V 0x3 +#define GPIO_PIN31_CONFIG_S 11 +/* GPIO_PIN31_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN31_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN31_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN31_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN31_WAKEUP_ENABLE_S 10 +/* GPIO_PIN31_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN31_INT_TYPE 0x00000007 +#define GPIO_PIN31_INT_TYPE_M ((GPIO_PIN31_INT_TYPE_V)<<(GPIO_PIN31_INT_TYPE_S)) +#define GPIO_PIN31_INT_TYPE_V 0x7 +#define GPIO_PIN31_INT_TYPE_S 7 +/* GPIO_PIN31_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN31_PAD_DRIVER (BIT(2)) +#define GPIO_PIN31_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN31_PAD_DRIVER_V 0x1 +#define GPIO_PIN31_PAD_DRIVER_S 2 + +#define GPIO_PIN32_REG (DR_REG_GPIO_BASE + 0x0108) +/* GPIO_PIN32_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN32_INT_ENA 0x0000001F +#define GPIO_PIN32_INT_ENA_M ((GPIO_PIN32_INT_ENA_V)<<(GPIO_PIN32_INT_ENA_S)) +#define GPIO_PIN32_INT_ENA_V 0x1F +#define GPIO_PIN32_INT_ENA_S 13 +/* GPIO_PIN32_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN32_CONFIG 0x00000003 +#define GPIO_PIN32_CONFIG_M ((GPIO_PIN32_CONFIG_V)<<(GPIO_PIN32_CONFIG_S)) +#define GPIO_PIN32_CONFIG_V 0x3 +#define GPIO_PIN32_CONFIG_S 11 +/* GPIO_PIN32_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN32_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN32_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN32_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN32_WAKEUP_ENABLE_S 10 +/* GPIO_PIN32_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN32_INT_TYPE 0x00000007 +#define GPIO_PIN32_INT_TYPE_M ((GPIO_PIN32_INT_TYPE_V)<<(GPIO_PIN32_INT_TYPE_S)) +#define GPIO_PIN32_INT_TYPE_V 0x7 +#define GPIO_PIN32_INT_TYPE_S 7 +/* GPIO_PIN32_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN32_PAD_DRIVER (BIT(2)) +#define GPIO_PIN32_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN32_PAD_DRIVER_V 0x1 +#define GPIO_PIN32_PAD_DRIVER_S 2 + +#define GPIO_PIN33_REG (DR_REG_GPIO_BASE + 0x010c) +/* GPIO_PIN33_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN33_INT_ENA 0x0000001F +#define GPIO_PIN33_INT_ENA_M ((GPIO_PIN33_INT_ENA_V)<<(GPIO_PIN33_INT_ENA_S)) +#define GPIO_PIN33_INT_ENA_V 0x1F +#define GPIO_PIN33_INT_ENA_S 13 +/* GPIO_PIN33_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN33_CONFIG 0x00000003 +#define GPIO_PIN33_CONFIG_M ((GPIO_PIN33_CONFIG_V)<<(GPIO_PIN33_CONFIG_S)) +#define GPIO_PIN33_CONFIG_V 0x3 +#define GPIO_PIN33_CONFIG_S 11 +/* GPIO_PIN33_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN33_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN33_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN33_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN33_WAKEUP_ENABLE_S 10 +/* GPIO_PIN33_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN33_INT_TYPE 0x00000007 +#define GPIO_PIN33_INT_TYPE_M ((GPIO_PIN33_INT_TYPE_V)<<(GPIO_PIN33_INT_TYPE_S)) +#define GPIO_PIN33_INT_TYPE_V 0x7 +#define GPIO_PIN33_INT_TYPE_S 7 +/* GPIO_PIN33_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN33_PAD_DRIVER (BIT(2)) +#define GPIO_PIN33_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN33_PAD_DRIVER_V 0x1 +#define GPIO_PIN33_PAD_DRIVER_S 2 + +#define GPIO_PIN34_REG (DR_REG_GPIO_BASE + 0x0110) +/* GPIO_PIN34_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN34_INT_ENA 0x0000001F +#define GPIO_PIN34_INT_ENA_M ((GPIO_PIN34_INT_ENA_V)<<(GPIO_PIN34_INT_ENA_S)) +#define GPIO_PIN34_INT_ENA_V 0x1F +#define GPIO_PIN34_INT_ENA_S 13 +/* GPIO_PIN34_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN34_CONFIG 0x00000003 +#define GPIO_PIN34_CONFIG_M ((GPIO_PIN34_CONFIG_V)<<(GPIO_PIN34_CONFIG_S)) +#define GPIO_PIN34_CONFIG_V 0x3 +#define GPIO_PIN34_CONFIG_S 11 +/* GPIO_PIN34_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN34_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN34_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN34_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN34_WAKEUP_ENABLE_S 10 +/* GPIO_PIN34_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN34_INT_TYPE 0x00000007 +#define GPIO_PIN34_INT_TYPE_M ((GPIO_PIN34_INT_TYPE_V)<<(GPIO_PIN34_INT_TYPE_S)) +#define GPIO_PIN34_INT_TYPE_V 0x7 +#define GPIO_PIN34_INT_TYPE_S 7 +/* GPIO_PIN34_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN34_PAD_DRIVER (BIT(2)) +#define GPIO_PIN34_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN34_PAD_DRIVER_V 0x1 +#define GPIO_PIN34_PAD_DRIVER_S 2 + +#define GPIO_PIN35_REG (DR_REG_GPIO_BASE + 0x0114) +/* GPIO_PIN35_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN35_INT_ENA 0x0000001F +#define GPIO_PIN35_INT_ENA_M ((GPIO_PIN35_INT_ENA_V)<<(GPIO_PIN35_INT_ENA_S)) +#define GPIO_PIN35_INT_ENA_V 0x1F +#define GPIO_PIN35_INT_ENA_S 13 +/* GPIO_PIN35_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN35_CONFIG 0x00000003 +#define GPIO_PIN35_CONFIG_M ((GPIO_PIN35_CONFIG_V)<<(GPIO_PIN35_CONFIG_S)) +#define GPIO_PIN35_CONFIG_V 0x3 +#define GPIO_PIN35_CONFIG_S 11 +/* GPIO_PIN35_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN35_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN35_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN35_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN35_WAKEUP_ENABLE_S 10 +/* GPIO_PIN35_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN35_INT_TYPE 0x00000007 +#define GPIO_PIN35_INT_TYPE_M ((GPIO_PIN35_INT_TYPE_V)<<(GPIO_PIN35_INT_TYPE_S)) +#define GPIO_PIN35_INT_TYPE_V 0x7 +#define GPIO_PIN35_INT_TYPE_S 7 +/* GPIO_PIN35_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN35_PAD_DRIVER (BIT(2)) +#define GPIO_PIN35_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN35_PAD_DRIVER_V 0x1 +#define GPIO_PIN35_PAD_DRIVER_S 2 + +#define GPIO_PIN36_REG (DR_REG_GPIO_BASE + 0x0118) +/* GPIO_PIN36_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN36_INT_ENA 0x0000001F +#define GPIO_PIN36_INT_ENA_M ((GPIO_PIN36_INT_ENA_V)<<(GPIO_PIN36_INT_ENA_S)) +#define GPIO_PIN36_INT_ENA_V 0x1F +#define GPIO_PIN36_INT_ENA_S 13 +/* GPIO_PIN36_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN36_CONFIG 0x00000003 +#define GPIO_PIN36_CONFIG_M ((GPIO_PIN36_CONFIG_V)<<(GPIO_PIN36_CONFIG_S)) +#define GPIO_PIN36_CONFIG_V 0x3 +#define GPIO_PIN36_CONFIG_S 11 +/* GPIO_PIN36_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN36_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN36_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN36_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN36_WAKEUP_ENABLE_S 10 +/* GPIO_PIN36_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN36_INT_TYPE 0x00000007 +#define GPIO_PIN36_INT_TYPE_M ((GPIO_PIN36_INT_TYPE_V)<<(GPIO_PIN36_INT_TYPE_S)) +#define GPIO_PIN36_INT_TYPE_V 0x7 +#define GPIO_PIN36_INT_TYPE_S 7 +/* GPIO_PIN36_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN36_PAD_DRIVER (BIT(2)) +#define GPIO_PIN36_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN36_PAD_DRIVER_V 0x1 +#define GPIO_PIN36_PAD_DRIVER_S 2 + +#define GPIO_PIN37_REG (DR_REG_GPIO_BASE + 0x011c) +/* GPIO_PIN37_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN37_INT_ENA 0x0000001F +#define GPIO_PIN37_INT_ENA_M ((GPIO_PIN37_INT_ENA_V)<<(GPIO_PIN37_INT_ENA_S)) +#define GPIO_PIN37_INT_ENA_V 0x1F +#define GPIO_PIN37_INT_ENA_S 13 +/* GPIO_PIN37_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN37_CONFIG 0x00000003 +#define GPIO_PIN37_CONFIG_M ((GPIO_PIN37_CONFIG_V)<<(GPIO_PIN37_CONFIG_S)) +#define GPIO_PIN37_CONFIG_V 0x3 +#define GPIO_PIN37_CONFIG_S 11 +/* GPIO_PIN37_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN37_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN37_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN37_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN37_WAKEUP_ENABLE_S 10 +/* GPIO_PIN37_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN37_INT_TYPE 0x00000007 +#define GPIO_PIN37_INT_TYPE_M ((GPIO_PIN37_INT_TYPE_V)<<(GPIO_PIN37_INT_TYPE_S)) +#define GPIO_PIN37_INT_TYPE_V 0x7 +#define GPIO_PIN37_INT_TYPE_S 7 +/* GPIO_PIN37_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN37_PAD_DRIVER (BIT(2)) +#define GPIO_PIN37_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN37_PAD_DRIVER_V 0x1 +#define GPIO_PIN37_PAD_DRIVER_S 2 + +#define GPIO_PIN38_REG (DR_REG_GPIO_BASE + 0x0120) +/* GPIO_PIN38_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN38_INT_ENA 0x0000001F +#define GPIO_PIN38_INT_ENA_M ((GPIO_PIN38_INT_ENA_V)<<(GPIO_PIN38_INT_ENA_S)) +#define GPIO_PIN38_INT_ENA_V 0x1F +#define GPIO_PIN38_INT_ENA_S 13 +/* GPIO_PIN38_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN38_CONFIG 0x00000003 +#define GPIO_PIN38_CONFIG_M ((GPIO_PIN38_CONFIG_V)<<(GPIO_PIN38_CONFIG_S)) +#define GPIO_PIN38_CONFIG_V 0x3 +#define GPIO_PIN38_CONFIG_S 11 +/* GPIO_PIN38_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN38_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN38_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN38_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN38_WAKEUP_ENABLE_S 10 +/* GPIO_PIN38_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN38_INT_TYPE 0x00000007 +#define GPIO_PIN38_INT_TYPE_M ((GPIO_PIN38_INT_TYPE_V)<<(GPIO_PIN38_INT_TYPE_S)) +#define GPIO_PIN38_INT_TYPE_V 0x7 +#define GPIO_PIN38_INT_TYPE_S 7 +/* GPIO_PIN38_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN38_PAD_DRIVER (BIT(2)) +#define GPIO_PIN38_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN38_PAD_DRIVER_V 0x1 +#define GPIO_PIN38_PAD_DRIVER_S 2 + +#define GPIO_PIN39_REG (DR_REG_GPIO_BASE + 0x0124) +/* GPIO_PIN39_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ +#define GPIO_PIN39_INT_ENA 0x0000001F +#define GPIO_PIN39_INT_ENA_M ((GPIO_PIN39_INT_ENA_V)<<(GPIO_PIN39_INT_ENA_S)) +#define GPIO_PIN39_INT_ENA_V 0x1F +#define GPIO_PIN39_INT_ENA_S 13 +/* GPIO_PIN39_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/*description: NA*/ +#define GPIO_PIN39_CONFIG 0x00000003 +#define GPIO_PIN39_CONFIG_M ((GPIO_PIN39_CONFIG_V)<<(GPIO_PIN39_CONFIG_S)) +#define GPIO_PIN39_CONFIG_V 0x3 +#define GPIO_PIN39_CONFIG_S 11 +/* GPIO_PIN39_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define GPIO_PIN39_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN39_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN39_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN39_WAKEUP_ENABLE_S 10 +/* GPIO_PIN39_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define GPIO_PIN39_INT_TYPE 0x00000007 +#define GPIO_PIN39_INT_TYPE_M ((GPIO_PIN39_INT_TYPE_V)<<(GPIO_PIN39_INT_TYPE_S)) +#define GPIO_PIN39_INT_TYPE_V 0x7 +#define GPIO_PIN39_INT_TYPE_S 7 +/* GPIO_PIN39_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define GPIO_PIN39_PAD_DRIVER (BIT(2)) +#define GPIO_PIN39_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN39_PAD_DRIVER_V 0x1 +#define GPIO_PIN39_PAD_DRIVER_S 2 + +#define GPIO_cali_conf_REG (DR_REG_GPIO_BASE + 0x0128) +/* GPIO_CALI_START : R/W ;bitpos:[31] ;default: x ; */ +/*description: */ +#define GPIO_CALI_START (BIT(31)) +#define GPIO_CALI_START_M (BIT(31)) +#define GPIO_CALI_START_V 0x1 +#define GPIO_CALI_START_S 31 +/* GPIO_CALI_RTC_MAX : R/W ;bitpos:[9:0] ;default: x ; */ +/*description: */ +#define GPIO_CALI_RTC_MAX 0x000003FF +#define GPIO_CALI_RTC_MAX_M ((GPIO_CALI_RTC_MAX_V)<<(GPIO_CALI_RTC_MAX_S)) +#define GPIO_CALI_RTC_MAX_V 0x3FF +#define GPIO_CALI_RTC_MAX_S 0 + +#define GPIO_cali_data_REG (DR_REG_GPIO_BASE + 0x012c) +/* GPIO_CALI_RDY_SYNC2 : RO ;bitpos:[31] ;default: ; */ +/*description: */ +#define GPIO_CALI_RDY_SYNC2 (BIT(31)) +#define GPIO_CALI_RDY_SYNC2_M (BIT(31)) +#define GPIO_CALI_RDY_SYNC2_V 0x1 +#define GPIO_CALI_RDY_SYNC2_S 31 +/* GPIO_CALI_RDY_REAL : RO ;bitpos:[30] ;default: ; */ +/*description: */ +#define GPIO_CALI_RDY_REAL (BIT(30)) +#define GPIO_CALI_RDY_REAL_M (BIT(30)) +#define GPIO_CALI_RDY_REAL_V 0x1 +#define GPIO_CALI_RDY_REAL_S 30 +/* GPIO_CALI_VALUE_SYNC2 : RO ;bitpos:[19:0] ;default: ; */ +/*description: */ +#define GPIO_CALI_VALUE_SYNC2 0x000FFFFF +#define GPIO_CALI_VALUE_SYNC2_M ((GPIO_CALI_VALUE_SYNC2_V)<<(GPIO_CALI_VALUE_SYNC2_S)) +#define GPIO_CALI_VALUE_SYNC2_V 0xFFFFF +#define GPIO_CALI_VALUE_SYNC2_S 0 + +#define GPIO_FUNC0_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0130) +/* GPIO_SIG0_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG0_IN_SEL (BIT(7)) +#define GPIO_SIG0_IN_SEL_M (BIT(7)) +#define GPIO_SIG0_IN_SEL_V 0x1 +#define GPIO_SIG0_IN_SEL_S 7 +/* GPIO_FUNC0_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC0_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC0_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC0_IN_INV_SEL_V 0x1 +#define GPIO_FUNC0_IN_INV_SEL_S 6 +/* GPIO_FUNC0_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC0_IN_SEL 0x0000003F +#define GPIO_FUNC0_IN_SEL_M ((GPIO_FUNC0_IN_SEL_V)<<(GPIO_FUNC0_IN_SEL_S)) +#define GPIO_FUNC0_IN_SEL_V 0x3F +#define GPIO_FUNC0_IN_SEL_S 0 + +#define GPIO_FUNC1_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0134) +/* GPIO_SIG1_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG1_IN_SEL (BIT(7)) +#define GPIO_SIG1_IN_SEL_M (BIT(7)) +#define GPIO_SIG1_IN_SEL_V 0x1 +#define GPIO_SIG1_IN_SEL_S 7 +/* GPIO_FUNC1_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC1_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC1_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC1_IN_INV_SEL_V 0x1 +#define GPIO_FUNC1_IN_INV_SEL_S 6 +/* GPIO_FUNC1_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC1_IN_SEL 0x0000003F +#define GPIO_FUNC1_IN_SEL_M ((GPIO_FUNC1_IN_SEL_V)<<(GPIO_FUNC1_IN_SEL_S)) +#define GPIO_FUNC1_IN_SEL_V 0x3F +#define GPIO_FUNC1_IN_SEL_S 0 + +#define GPIO_FUNC2_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0138) +/* GPIO_SIG2_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG2_IN_SEL (BIT(7)) +#define GPIO_SIG2_IN_SEL_M (BIT(7)) +#define GPIO_SIG2_IN_SEL_V 0x1 +#define GPIO_SIG2_IN_SEL_S 7 +/* GPIO_FUNC2_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC2_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC2_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC2_IN_INV_SEL_V 0x1 +#define GPIO_FUNC2_IN_INV_SEL_S 6 +/* GPIO_FUNC2_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC2_IN_SEL 0x0000003F +#define GPIO_FUNC2_IN_SEL_M ((GPIO_FUNC2_IN_SEL_V)<<(GPIO_FUNC2_IN_SEL_S)) +#define GPIO_FUNC2_IN_SEL_V 0x3F +#define GPIO_FUNC2_IN_SEL_S 0 + +#define GPIO_FUNC3_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x013c) +/* GPIO_SIG3_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG3_IN_SEL (BIT(7)) +#define GPIO_SIG3_IN_SEL_M (BIT(7)) +#define GPIO_SIG3_IN_SEL_V 0x1 +#define GPIO_SIG3_IN_SEL_S 7 +/* GPIO_FUNC3_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC3_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC3_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC3_IN_INV_SEL_V 0x1 +#define GPIO_FUNC3_IN_INV_SEL_S 6 +/* GPIO_FUNC3_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC3_IN_SEL 0x0000003F +#define GPIO_FUNC3_IN_SEL_M ((GPIO_FUNC3_IN_SEL_V)<<(GPIO_FUNC3_IN_SEL_S)) +#define GPIO_FUNC3_IN_SEL_V 0x3F +#define GPIO_FUNC3_IN_SEL_S 0 + +#define GPIO_FUNC4_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0140) +/* GPIO_SIG4_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG4_IN_SEL (BIT(7)) +#define GPIO_SIG4_IN_SEL_M (BIT(7)) +#define GPIO_SIG4_IN_SEL_V 0x1 +#define GPIO_SIG4_IN_SEL_S 7 +/* GPIO_FUNC4_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC4_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC4_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC4_IN_INV_SEL_V 0x1 +#define GPIO_FUNC4_IN_INV_SEL_S 6 +/* GPIO_FUNC4_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC4_IN_SEL 0x0000003F +#define GPIO_FUNC4_IN_SEL_M ((GPIO_FUNC4_IN_SEL_V)<<(GPIO_FUNC4_IN_SEL_S)) +#define GPIO_FUNC4_IN_SEL_V 0x3F +#define GPIO_FUNC4_IN_SEL_S 0 + +#define GPIO_FUNC5_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0144) +/* GPIO_SIG5_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG5_IN_SEL (BIT(7)) +#define GPIO_SIG5_IN_SEL_M (BIT(7)) +#define GPIO_SIG5_IN_SEL_V 0x1 +#define GPIO_SIG5_IN_SEL_S 7 +/* GPIO_FUNC5_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC5_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC5_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC5_IN_INV_SEL_V 0x1 +#define GPIO_FUNC5_IN_INV_SEL_S 6 +/* GPIO_FUNC5_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC5_IN_SEL 0x0000003F +#define GPIO_FUNC5_IN_SEL_M ((GPIO_FUNC5_IN_SEL_V)<<(GPIO_FUNC5_IN_SEL_S)) +#define GPIO_FUNC5_IN_SEL_V 0x3F +#define GPIO_FUNC5_IN_SEL_S 0 + +#define GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0148) +/* GPIO_SIG6_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG6_IN_SEL (BIT(7)) +#define GPIO_SIG6_IN_SEL_M (BIT(7)) +#define GPIO_SIG6_IN_SEL_V 0x1 +#define GPIO_SIG6_IN_SEL_S 7 +/* GPIO_FUNC6_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC6_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC6_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC6_IN_INV_SEL_V 0x1 +#define GPIO_FUNC6_IN_INV_SEL_S 6 +/* GPIO_FUNC6_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC6_IN_SEL 0x0000003F +#define GPIO_FUNC6_IN_SEL_M ((GPIO_FUNC6_IN_SEL_V)<<(GPIO_FUNC6_IN_SEL_S)) +#define GPIO_FUNC6_IN_SEL_V 0x3F +#define GPIO_FUNC6_IN_SEL_S 0 + +#define GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x014c) +/* GPIO_SIG7_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG7_IN_SEL (BIT(7)) +#define GPIO_SIG7_IN_SEL_M (BIT(7)) +#define GPIO_SIG7_IN_SEL_V 0x1 +#define GPIO_SIG7_IN_SEL_S 7 +/* GPIO_FUNC7_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC7_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC7_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC7_IN_INV_SEL_V 0x1 +#define GPIO_FUNC7_IN_INV_SEL_S 6 +/* GPIO_FUNC7_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC7_IN_SEL 0x0000003F +#define GPIO_FUNC7_IN_SEL_M ((GPIO_FUNC7_IN_SEL_V)<<(GPIO_FUNC7_IN_SEL_S)) +#define GPIO_FUNC7_IN_SEL_V 0x3F +#define GPIO_FUNC7_IN_SEL_S 0 + +#define GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0150) +/* GPIO_SIG8_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG8_IN_SEL (BIT(7)) +#define GPIO_SIG8_IN_SEL_M (BIT(7)) +#define GPIO_SIG8_IN_SEL_V 0x1 +#define GPIO_SIG8_IN_SEL_S 7 +/* GPIO_FUNC8_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC8_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC8_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC8_IN_INV_SEL_V 0x1 +#define GPIO_FUNC8_IN_INV_SEL_S 6 +/* GPIO_FUNC8_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC8_IN_SEL 0x0000003F +#define GPIO_FUNC8_IN_SEL_M ((GPIO_FUNC8_IN_SEL_V)<<(GPIO_FUNC8_IN_SEL_S)) +#define GPIO_FUNC8_IN_SEL_V 0x3F +#define GPIO_FUNC8_IN_SEL_S 0 + +#define GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0154) +/* GPIO_SIG9_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG9_IN_SEL (BIT(7)) +#define GPIO_SIG9_IN_SEL_M (BIT(7)) +#define GPIO_SIG9_IN_SEL_V 0x1 +#define GPIO_SIG9_IN_SEL_S 7 +/* GPIO_FUNC9_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC9_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC9_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC9_IN_INV_SEL_V 0x1 +#define GPIO_FUNC9_IN_INV_SEL_S 6 +/* GPIO_FUNC9_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC9_IN_SEL 0x0000003F +#define GPIO_FUNC9_IN_SEL_M ((GPIO_FUNC9_IN_SEL_V)<<(GPIO_FUNC9_IN_SEL_S)) +#define GPIO_FUNC9_IN_SEL_V 0x3F +#define GPIO_FUNC9_IN_SEL_S 0 + +#define GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0158) +/* GPIO_SIG10_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG10_IN_SEL (BIT(7)) +#define GPIO_SIG10_IN_SEL_M (BIT(7)) +#define GPIO_SIG10_IN_SEL_V 0x1 +#define GPIO_SIG10_IN_SEL_S 7 +/* GPIO_FUNC10_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC10_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC10_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC10_IN_INV_SEL_V 0x1 +#define GPIO_FUNC10_IN_INV_SEL_S 6 +/* GPIO_FUNC10_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC10_IN_SEL 0x0000003F +#define GPIO_FUNC10_IN_SEL_M ((GPIO_FUNC10_IN_SEL_V)<<(GPIO_FUNC10_IN_SEL_S)) +#define GPIO_FUNC10_IN_SEL_V 0x3F +#define GPIO_FUNC10_IN_SEL_S 0 + +#define GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x015c) +/* GPIO_SIG11_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG11_IN_SEL (BIT(7)) +#define GPIO_SIG11_IN_SEL_M (BIT(7)) +#define GPIO_SIG11_IN_SEL_V 0x1 +#define GPIO_SIG11_IN_SEL_S 7 +/* GPIO_FUNC11_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC11_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC11_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC11_IN_INV_SEL_V 0x1 +#define GPIO_FUNC11_IN_INV_SEL_S 6 +/* GPIO_FUNC11_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC11_IN_SEL 0x0000003F +#define GPIO_FUNC11_IN_SEL_M ((GPIO_FUNC11_IN_SEL_V)<<(GPIO_FUNC11_IN_SEL_S)) +#define GPIO_FUNC11_IN_SEL_V 0x3F +#define GPIO_FUNC11_IN_SEL_S 0 + +#define GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0160) +/* GPIO_SIG12_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG12_IN_SEL (BIT(7)) +#define GPIO_SIG12_IN_SEL_M (BIT(7)) +#define GPIO_SIG12_IN_SEL_V 0x1 +#define GPIO_SIG12_IN_SEL_S 7 +/* GPIO_FUNC12_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC12_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC12_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC12_IN_INV_SEL_V 0x1 +#define GPIO_FUNC12_IN_INV_SEL_S 6 +/* GPIO_FUNC12_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC12_IN_SEL 0x0000003F +#define GPIO_FUNC12_IN_SEL_M ((GPIO_FUNC12_IN_SEL_V)<<(GPIO_FUNC12_IN_SEL_S)) +#define GPIO_FUNC12_IN_SEL_V 0x3F +#define GPIO_FUNC12_IN_SEL_S 0 + +#define GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0164) +/* GPIO_SIG13_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG13_IN_SEL (BIT(7)) +#define GPIO_SIG13_IN_SEL_M (BIT(7)) +#define GPIO_SIG13_IN_SEL_V 0x1 +#define GPIO_SIG13_IN_SEL_S 7 +/* GPIO_FUNC13_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC13_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC13_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC13_IN_INV_SEL_V 0x1 +#define GPIO_FUNC13_IN_INV_SEL_S 6 +/* GPIO_FUNC13_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC13_IN_SEL 0x0000003F +#define GPIO_FUNC13_IN_SEL_M ((GPIO_FUNC13_IN_SEL_V)<<(GPIO_FUNC13_IN_SEL_S)) +#define GPIO_FUNC13_IN_SEL_V 0x3F +#define GPIO_FUNC13_IN_SEL_S 0 + +#define GPIO_FUNC14_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0168) +/* GPIO_SIG14_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG14_IN_SEL (BIT(7)) +#define GPIO_SIG14_IN_SEL_M (BIT(7)) +#define GPIO_SIG14_IN_SEL_V 0x1 +#define GPIO_SIG14_IN_SEL_S 7 +/* GPIO_FUNC14_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC14_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC14_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC14_IN_INV_SEL_V 0x1 +#define GPIO_FUNC14_IN_INV_SEL_S 6 +/* GPIO_FUNC14_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC14_IN_SEL 0x0000003F +#define GPIO_FUNC14_IN_SEL_M ((GPIO_FUNC14_IN_SEL_V)<<(GPIO_FUNC14_IN_SEL_S)) +#define GPIO_FUNC14_IN_SEL_V 0x3F +#define GPIO_FUNC14_IN_SEL_S 0 + +#define GPIO_FUNC15_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x016c) +/* GPIO_SIG15_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG15_IN_SEL (BIT(7)) +#define GPIO_SIG15_IN_SEL_M (BIT(7)) +#define GPIO_SIG15_IN_SEL_V 0x1 +#define GPIO_SIG15_IN_SEL_S 7 +/* GPIO_FUNC15_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC15_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC15_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC15_IN_INV_SEL_V 0x1 +#define GPIO_FUNC15_IN_INV_SEL_S 6 +/* GPIO_FUNC15_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC15_IN_SEL 0x0000003F +#define GPIO_FUNC15_IN_SEL_M ((GPIO_FUNC15_IN_SEL_V)<<(GPIO_FUNC15_IN_SEL_S)) +#define GPIO_FUNC15_IN_SEL_V 0x3F +#define GPIO_FUNC15_IN_SEL_S 0 + +#define GPIO_FUNC16_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0170) +/* GPIO_SIG16_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG16_IN_SEL (BIT(7)) +#define GPIO_SIG16_IN_SEL_M (BIT(7)) +#define GPIO_SIG16_IN_SEL_V 0x1 +#define GPIO_SIG16_IN_SEL_S 7 +/* GPIO_FUNC16_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC16_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC16_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC16_IN_INV_SEL_V 0x1 +#define GPIO_FUNC16_IN_INV_SEL_S 6 +/* GPIO_FUNC16_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC16_IN_SEL 0x0000003F +#define GPIO_FUNC16_IN_SEL_M ((GPIO_FUNC16_IN_SEL_V)<<(GPIO_FUNC16_IN_SEL_S)) +#define GPIO_FUNC16_IN_SEL_V 0x3F +#define GPIO_FUNC16_IN_SEL_S 0 + +#define GPIO_FUNC17_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0174) +/* GPIO_SIG17_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG17_IN_SEL (BIT(7)) +#define GPIO_SIG17_IN_SEL_M (BIT(7)) +#define GPIO_SIG17_IN_SEL_V 0x1 +#define GPIO_SIG17_IN_SEL_S 7 +/* GPIO_FUNC17_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC17_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC17_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC17_IN_INV_SEL_V 0x1 +#define GPIO_FUNC17_IN_INV_SEL_S 6 +/* GPIO_FUNC17_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC17_IN_SEL 0x0000003F +#define GPIO_FUNC17_IN_SEL_M ((GPIO_FUNC17_IN_SEL_V)<<(GPIO_FUNC17_IN_SEL_S)) +#define GPIO_FUNC17_IN_SEL_V 0x3F +#define GPIO_FUNC17_IN_SEL_S 0 + +#define GPIO_FUNC18_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0178) +/* GPIO_SIG18_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG18_IN_SEL (BIT(7)) +#define GPIO_SIG18_IN_SEL_M (BIT(7)) +#define GPIO_SIG18_IN_SEL_V 0x1 +#define GPIO_SIG18_IN_SEL_S 7 +/* GPIO_FUNC18_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC18_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC18_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC18_IN_INV_SEL_V 0x1 +#define GPIO_FUNC18_IN_INV_SEL_S 6 +/* GPIO_FUNC18_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC18_IN_SEL 0x0000003F +#define GPIO_FUNC18_IN_SEL_M ((GPIO_FUNC18_IN_SEL_V)<<(GPIO_FUNC18_IN_SEL_S)) +#define GPIO_FUNC18_IN_SEL_V 0x3F +#define GPIO_FUNC18_IN_SEL_S 0 + +#define GPIO_FUNC19_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x017c) +/* GPIO_SIG19_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG19_IN_SEL (BIT(7)) +#define GPIO_SIG19_IN_SEL_M (BIT(7)) +#define GPIO_SIG19_IN_SEL_V 0x1 +#define GPIO_SIG19_IN_SEL_S 7 +/* GPIO_FUNC19_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC19_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC19_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC19_IN_INV_SEL_V 0x1 +#define GPIO_FUNC19_IN_INV_SEL_S 6 +/* GPIO_FUNC19_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC19_IN_SEL 0x0000003F +#define GPIO_FUNC19_IN_SEL_M ((GPIO_FUNC19_IN_SEL_V)<<(GPIO_FUNC19_IN_SEL_S)) +#define GPIO_FUNC19_IN_SEL_V 0x3F +#define GPIO_FUNC19_IN_SEL_S 0 + +#define GPIO_FUNC20_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0180) +/* GPIO_SIG20_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG20_IN_SEL (BIT(7)) +#define GPIO_SIG20_IN_SEL_M (BIT(7)) +#define GPIO_SIG20_IN_SEL_V 0x1 +#define GPIO_SIG20_IN_SEL_S 7 +/* GPIO_FUNC20_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC20_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC20_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC20_IN_INV_SEL_V 0x1 +#define GPIO_FUNC20_IN_INV_SEL_S 6 +/* GPIO_FUNC20_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC20_IN_SEL 0x0000003F +#define GPIO_FUNC20_IN_SEL_M ((GPIO_FUNC20_IN_SEL_V)<<(GPIO_FUNC20_IN_SEL_S)) +#define GPIO_FUNC20_IN_SEL_V 0x3F +#define GPIO_FUNC20_IN_SEL_S 0 + +#define GPIO_FUNC21_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0184) +/* GPIO_SIG21_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG21_IN_SEL (BIT(7)) +#define GPIO_SIG21_IN_SEL_M (BIT(7)) +#define GPIO_SIG21_IN_SEL_V 0x1 +#define GPIO_SIG21_IN_SEL_S 7 +/* GPIO_FUNC21_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC21_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC21_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC21_IN_INV_SEL_V 0x1 +#define GPIO_FUNC21_IN_INV_SEL_S 6 +/* GPIO_FUNC21_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC21_IN_SEL 0x0000003F +#define GPIO_FUNC21_IN_SEL_M ((GPIO_FUNC21_IN_SEL_V)<<(GPIO_FUNC21_IN_SEL_S)) +#define GPIO_FUNC21_IN_SEL_V 0x3F +#define GPIO_FUNC21_IN_SEL_S 0 + +#define GPIO_FUNC22_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0188) +/* GPIO_SIG22_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG22_IN_SEL (BIT(7)) +#define GPIO_SIG22_IN_SEL_M (BIT(7)) +#define GPIO_SIG22_IN_SEL_V 0x1 +#define GPIO_SIG22_IN_SEL_S 7 +/* GPIO_FUNC22_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC22_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC22_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC22_IN_INV_SEL_V 0x1 +#define GPIO_FUNC22_IN_INV_SEL_S 6 +/* GPIO_FUNC22_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC22_IN_SEL 0x0000003F +#define GPIO_FUNC22_IN_SEL_M ((GPIO_FUNC22_IN_SEL_V)<<(GPIO_FUNC22_IN_SEL_S)) +#define GPIO_FUNC22_IN_SEL_V 0x3F +#define GPIO_FUNC22_IN_SEL_S 0 + +#define GPIO_FUNC23_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x018c) +/* GPIO_SIG23_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG23_IN_SEL (BIT(7)) +#define GPIO_SIG23_IN_SEL_M (BIT(7)) +#define GPIO_SIG23_IN_SEL_V 0x1 +#define GPIO_SIG23_IN_SEL_S 7 +/* GPIO_FUNC23_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC23_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC23_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC23_IN_INV_SEL_V 0x1 +#define GPIO_FUNC23_IN_INV_SEL_S 6 +/* GPIO_FUNC23_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC23_IN_SEL 0x0000003F +#define GPIO_FUNC23_IN_SEL_M ((GPIO_FUNC23_IN_SEL_V)<<(GPIO_FUNC23_IN_SEL_S)) +#define GPIO_FUNC23_IN_SEL_V 0x3F +#define GPIO_FUNC23_IN_SEL_S 0 + +#define GPIO_FUNC24_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0190) +/* GPIO_SIG24_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG24_IN_SEL (BIT(7)) +#define GPIO_SIG24_IN_SEL_M (BIT(7)) +#define GPIO_SIG24_IN_SEL_V 0x1 +#define GPIO_SIG24_IN_SEL_S 7 +/* GPIO_FUNC24_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC24_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC24_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC24_IN_INV_SEL_V 0x1 +#define GPIO_FUNC24_IN_INV_SEL_S 6 +/* GPIO_FUNC24_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC24_IN_SEL 0x0000003F +#define GPIO_FUNC24_IN_SEL_M ((GPIO_FUNC24_IN_SEL_V)<<(GPIO_FUNC24_IN_SEL_S)) +#define GPIO_FUNC24_IN_SEL_V 0x3F +#define GPIO_FUNC24_IN_SEL_S 0 + +#define GPIO_FUNC25_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0194) +/* GPIO_SIG25_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG25_IN_SEL (BIT(7)) +#define GPIO_SIG25_IN_SEL_M (BIT(7)) +#define GPIO_SIG25_IN_SEL_V 0x1 +#define GPIO_SIG25_IN_SEL_S 7 +/* GPIO_FUNC25_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC25_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC25_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC25_IN_INV_SEL_V 0x1 +#define GPIO_FUNC25_IN_INV_SEL_S 6 +/* GPIO_FUNC25_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC25_IN_SEL 0x0000003F +#define GPIO_FUNC25_IN_SEL_M ((GPIO_FUNC25_IN_SEL_V)<<(GPIO_FUNC25_IN_SEL_S)) +#define GPIO_FUNC25_IN_SEL_V 0x3F +#define GPIO_FUNC25_IN_SEL_S 0 + +#define GPIO_FUNC26_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0198) +/* GPIO_SIG26_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG26_IN_SEL (BIT(7)) +#define GPIO_SIG26_IN_SEL_M (BIT(7)) +#define GPIO_SIG26_IN_SEL_V 0x1 +#define GPIO_SIG26_IN_SEL_S 7 +/* GPIO_FUNC26_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC26_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC26_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC26_IN_INV_SEL_V 0x1 +#define GPIO_FUNC26_IN_INV_SEL_S 6 +/* GPIO_FUNC26_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC26_IN_SEL 0x0000003F +#define GPIO_FUNC26_IN_SEL_M ((GPIO_FUNC26_IN_SEL_V)<<(GPIO_FUNC26_IN_SEL_S)) +#define GPIO_FUNC26_IN_SEL_V 0x3F +#define GPIO_FUNC26_IN_SEL_S 0 + +#define GPIO_FUNC27_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x019c) +/* GPIO_SIG27_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG27_IN_SEL (BIT(7)) +#define GPIO_SIG27_IN_SEL_M (BIT(7)) +#define GPIO_SIG27_IN_SEL_V 0x1 +#define GPIO_SIG27_IN_SEL_S 7 +/* GPIO_FUNC27_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC27_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC27_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC27_IN_INV_SEL_V 0x1 +#define GPIO_FUNC27_IN_INV_SEL_S 6 +/* GPIO_FUNC27_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC27_IN_SEL 0x0000003F +#define GPIO_FUNC27_IN_SEL_M ((GPIO_FUNC27_IN_SEL_V)<<(GPIO_FUNC27_IN_SEL_S)) +#define GPIO_FUNC27_IN_SEL_V 0x3F +#define GPIO_FUNC27_IN_SEL_S 0 + +#define GPIO_FUNC28_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01a0) +/* GPIO_SIG28_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG28_IN_SEL (BIT(7)) +#define GPIO_SIG28_IN_SEL_M (BIT(7)) +#define GPIO_SIG28_IN_SEL_V 0x1 +#define GPIO_SIG28_IN_SEL_S 7 +/* GPIO_FUNC28_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC28_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC28_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC28_IN_INV_SEL_V 0x1 +#define GPIO_FUNC28_IN_INV_SEL_S 6 +/* GPIO_FUNC28_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC28_IN_SEL 0x0000003F +#define GPIO_FUNC28_IN_SEL_M ((GPIO_FUNC28_IN_SEL_V)<<(GPIO_FUNC28_IN_SEL_S)) +#define GPIO_FUNC28_IN_SEL_V 0x3F +#define GPIO_FUNC28_IN_SEL_S 0 + +#define GPIO_FUNC29_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01a4) +/* GPIO_SIG29_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG29_IN_SEL (BIT(7)) +#define GPIO_SIG29_IN_SEL_M (BIT(7)) +#define GPIO_SIG29_IN_SEL_V 0x1 +#define GPIO_SIG29_IN_SEL_S 7 +/* GPIO_FUNC29_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC29_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC29_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC29_IN_INV_SEL_V 0x1 +#define GPIO_FUNC29_IN_INV_SEL_S 6 +/* GPIO_FUNC29_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC29_IN_SEL 0x0000003F +#define GPIO_FUNC29_IN_SEL_M ((GPIO_FUNC29_IN_SEL_V)<<(GPIO_FUNC29_IN_SEL_S)) +#define GPIO_FUNC29_IN_SEL_V 0x3F +#define GPIO_FUNC29_IN_SEL_S 0 + +#define GPIO_FUNC30_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01a8) +/* GPIO_SIG30_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG30_IN_SEL (BIT(7)) +#define GPIO_SIG30_IN_SEL_M (BIT(7)) +#define GPIO_SIG30_IN_SEL_V 0x1 +#define GPIO_SIG30_IN_SEL_S 7 +/* GPIO_FUNC30_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC30_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC30_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC30_IN_INV_SEL_V 0x1 +#define GPIO_FUNC30_IN_INV_SEL_S 6 +/* GPIO_FUNC30_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC30_IN_SEL 0x0000003F +#define GPIO_FUNC30_IN_SEL_M ((GPIO_FUNC30_IN_SEL_V)<<(GPIO_FUNC30_IN_SEL_S)) +#define GPIO_FUNC30_IN_SEL_V 0x3F +#define GPIO_FUNC30_IN_SEL_S 0 + +#define GPIO_FUNC31_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01ac) +/* GPIO_SIG31_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG31_IN_SEL (BIT(7)) +#define GPIO_SIG31_IN_SEL_M (BIT(7)) +#define GPIO_SIG31_IN_SEL_V 0x1 +#define GPIO_SIG31_IN_SEL_S 7 +/* GPIO_FUNC31_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC31_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC31_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC31_IN_INV_SEL_V 0x1 +#define GPIO_FUNC31_IN_INV_SEL_S 6 +/* GPIO_FUNC31_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC31_IN_SEL 0x0000003F +#define GPIO_FUNC31_IN_SEL_M ((GPIO_FUNC31_IN_SEL_V)<<(GPIO_FUNC31_IN_SEL_S)) +#define GPIO_FUNC31_IN_SEL_V 0x3F +#define GPIO_FUNC31_IN_SEL_S 0 + +#define GPIO_FUNC32_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01b0) +/* GPIO_SIG32_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG32_IN_SEL (BIT(7)) +#define GPIO_SIG32_IN_SEL_M (BIT(7)) +#define GPIO_SIG32_IN_SEL_V 0x1 +#define GPIO_SIG32_IN_SEL_S 7 +/* GPIO_FUNC32_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC32_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC32_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC32_IN_INV_SEL_V 0x1 +#define GPIO_FUNC32_IN_INV_SEL_S 6 +/* GPIO_FUNC32_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC32_IN_SEL 0x0000003F +#define GPIO_FUNC32_IN_SEL_M ((GPIO_FUNC32_IN_SEL_V)<<(GPIO_FUNC32_IN_SEL_S)) +#define GPIO_FUNC32_IN_SEL_V 0x3F +#define GPIO_FUNC32_IN_SEL_S 0 + +#define GPIO_FUNC33_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01b4) +/* GPIO_SIG33_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG33_IN_SEL (BIT(7)) +#define GPIO_SIG33_IN_SEL_M (BIT(7)) +#define GPIO_SIG33_IN_SEL_V 0x1 +#define GPIO_SIG33_IN_SEL_S 7 +/* GPIO_FUNC33_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC33_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC33_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC33_IN_INV_SEL_V 0x1 +#define GPIO_FUNC33_IN_INV_SEL_S 6 +/* GPIO_FUNC33_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC33_IN_SEL 0x0000003F +#define GPIO_FUNC33_IN_SEL_M ((GPIO_FUNC33_IN_SEL_V)<<(GPIO_FUNC33_IN_SEL_S)) +#define GPIO_FUNC33_IN_SEL_V 0x3F +#define GPIO_FUNC33_IN_SEL_S 0 + +#define GPIO_FUNC34_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01b8) +/* GPIO_SIG34_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG34_IN_SEL (BIT(7)) +#define GPIO_SIG34_IN_SEL_M (BIT(7)) +#define GPIO_SIG34_IN_SEL_V 0x1 +#define GPIO_SIG34_IN_SEL_S 7 +/* GPIO_FUNC34_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC34_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC34_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC34_IN_INV_SEL_V 0x1 +#define GPIO_FUNC34_IN_INV_SEL_S 6 +/* GPIO_FUNC34_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC34_IN_SEL 0x0000003F +#define GPIO_FUNC34_IN_SEL_M ((GPIO_FUNC34_IN_SEL_V)<<(GPIO_FUNC34_IN_SEL_S)) +#define GPIO_FUNC34_IN_SEL_V 0x3F +#define GPIO_FUNC34_IN_SEL_S 0 + +#define GPIO_FUNC35_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01bc) +/* GPIO_SIG35_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG35_IN_SEL (BIT(7)) +#define GPIO_SIG35_IN_SEL_M (BIT(7)) +#define GPIO_SIG35_IN_SEL_V 0x1 +#define GPIO_SIG35_IN_SEL_S 7 +/* GPIO_FUNC35_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC35_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC35_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC35_IN_INV_SEL_V 0x1 +#define GPIO_FUNC35_IN_INV_SEL_S 6 +/* GPIO_FUNC35_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC35_IN_SEL 0x0000003F +#define GPIO_FUNC35_IN_SEL_M ((GPIO_FUNC35_IN_SEL_V)<<(GPIO_FUNC35_IN_SEL_S)) +#define GPIO_FUNC35_IN_SEL_V 0x3F +#define GPIO_FUNC35_IN_SEL_S 0 + +#define GPIO_FUNC36_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01c0) +/* GPIO_SIG36_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG36_IN_SEL (BIT(7)) +#define GPIO_SIG36_IN_SEL_M (BIT(7)) +#define GPIO_SIG36_IN_SEL_V 0x1 +#define GPIO_SIG36_IN_SEL_S 7 +/* GPIO_FUNC36_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC36_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC36_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC36_IN_INV_SEL_V 0x1 +#define GPIO_FUNC36_IN_INV_SEL_S 6 +/* GPIO_FUNC36_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC36_IN_SEL 0x0000003F +#define GPIO_FUNC36_IN_SEL_M ((GPIO_FUNC36_IN_SEL_V)<<(GPIO_FUNC36_IN_SEL_S)) +#define GPIO_FUNC36_IN_SEL_V 0x3F +#define GPIO_FUNC36_IN_SEL_S 0 + +#define GPIO_FUNC37_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01c4) +/* GPIO_SIG37_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG37_IN_SEL (BIT(7)) +#define GPIO_SIG37_IN_SEL_M (BIT(7)) +#define GPIO_SIG37_IN_SEL_V 0x1 +#define GPIO_SIG37_IN_SEL_S 7 +/* GPIO_FUNC37_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC37_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC37_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC37_IN_INV_SEL_V 0x1 +#define GPIO_FUNC37_IN_INV_SEL_S 6 +/* GPIO_FUNC37_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC37_IN_SEL 0x0000003F +#define GPIO_FUNC37_IN_SEL_M ((GPIO_FUNC37_IN_SEL_V)<<(GPIO_FUNC37_IN_SEL_S)) +#define GPIO_FUNC37_IN_SEL_V 0x3F +#define GPIO_FUNC37_IN_SEL_S 0 + +#define GPIO_FUNC38_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01c8) +/* GPIO_SIG38_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG38_IN_SEL (BIT(7)) +#define GPIO_SIG38_IN_SEL_M (BIT(7)) +#define GPIO_SIG38_IN_SEL_V 0x1 +#define GPIO_SIG38_IN_SEL_S 7 +/* GPIO_FUNC38_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC38_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC38_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC38_IN_INV_SEL_V 0x1 +#define GPIO_FUNC38_IN_INV_SEL_S 6 +/* GPIO_FUNC38_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC38_IN_SEL 0x0000003F +#define GPIO_FUNC38_IN_SEL_M ((GPIO_FUNC38_IN_SEL_V)<<(GPIO_FUNC38_IN_SEL_S)) +#define GPIO_FUNC38_IN_SEL_V 0x3F +#define GPIO_FUNC38_IN_SEL_S 0 + +#define GPIO_FUNC39_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01cc) +/* GPIO_SIG39_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG39_IN_SEL (BIT(7)) +#define GPIO_SIG39_IN_SEL_M (BIT(7)) +#define GPIO_SIG39_IN_SEL_V 0x1 +#define GPIO_SIG39_IN_SEL_S 7 +/* GPIO_FUNC39_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC39_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC39_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC39_IN_INV_SEL_V 0x1 +#define GPIO_FUNC39_IN_INV_SEL_S 6 +/* GPIO_FUNC39_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC39_IN_SEL 0x0000003F +#define GPIO_FUNC39_IN_SEL_M ((GPIO_FUNC39_IN_SEL_V)<<(GPIO_FUNC39_IN_SEL_S)) +#define GPIO_FUNC39_IN_SEL_V 0x3F +#define GPIO_FUNC39_IN_SEL_S 0 + +#define GPIO_FUNC40_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01d0) +/* GPIO_SIG40_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG40_IN_SEL (BIT(7)) +#define GPIO_SIG40_IN_SEL_M (BIT(7)) +#define GPIO_SIG40_IN_SEL_V 0x1 +#define GPIO_SIG40_IN_SEL_S 7 +/* GPIO_FUNC40_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC40_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC40_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC40_IN_INV_SEL_V 0x1 +#define GPIO_FUNC40_IN_INV_SEL_S 6 +/* GPIO_FUNC40_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC40_IN_SEL 0x0000003F +#define GPIO_FUNC40_IN_SEL_M ((GPIO_FUNC40_IN_SEL_V)<<(GPIO_FUNC40_IN_SEL_S)) +#define GPIO_FUNC40_IN_SEL_V 0x3F +#define GPIO_FUNC40_IN_SEL_S 0 + +#define GPIO_FUNC41_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01d4) +/* GPIO_SIG41_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG41_IN_SEL (BIT(7)) +#define GPIO_SIG41_IN_SEL_M (BIT(7)) +#define GPIO_SIG41_IN_SEL_V 0x1 +#define GPIO_SIG41_IN_SEL_S 7 +/* GPIO_FUNC41_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC41_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC41_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC41_IN_INV_SEL_V 0x1 +#define GPIO_FUNC41_IN_INV_SEL_S 6 +/* GPIO_FUNC41_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC41_IN_SEL 0x0000003F +#define GPIO_FUNC41_IN_SEL_M ((GPIO_FUNC41_IN_SEL_V)<<(GPIO_FUNC41_IN_SEL_S)) +#define GPIO_FUNC41_IN_SEL_V 0x3F +#define GPIO_FUNC41_IN_SEL_S 0 + +#define GPIO_FUNC42_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01d8) +/* GPIO_SIG42_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG42_IN_SEL (BIT(7)) +#define GPIO_SIG42_IN_SEL_M (BIT(7)) +#define GPIO_SIG42_IN_SEL_V 0x1 +#define GPIO_SIG42_IN_SEL_S 7 +/* GPIO_FUNC42_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC42_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC42_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC42_IN_INV_SEL_V 0x1 +#define GPIO_FUNC42_IN_INV_SEL_S 6 +/* GPIO_FUNC42_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC42_IN_SEL 0x0000003F +#define GPIO_FUNC42_IN_SEL_M ((GPIO_FUNC42_IN_SEL_V)<<(GPIO_FUNC42_IN_SEL_S)) +#define GPIO_FUNC42_IN_SEL_V 0x3F +#define GPIO_FUNC42_IN_SEL_S 0 + +#define GPIO_FUNC43_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01dc) +/* GPIO_SIG43_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG43_IN_SEL (BIT(7)) +#define GPIO_SIG43_IN_SEL_M (BIT(7)) +#define GPIO_SIG43_IN_SEL_V 0x1 +#define GPIO_SIG43_IN_SEL_S 7 +/* GPIO_FUNC43_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC43_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC43_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC43_IN_INV_SEL_V 0x1 +#define GPIO_FUNC43_IN_INV_SEL_S 6 +/* GPIO_FUNC43_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC43_IN_SEL 0x0000003F +#define GPIO_FUNC43_IN_SEL_M ((GPIO_FUNC43_IN_SEL_V)<<(GPIO_FUNC43_IN_SEL_S)) +#define GPIO_FUNC43_IN_SEL_V 0x3F +#define GPIO_FUNC43_IN_SEL_S 0 + +#define GPIO_FUNC44_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01e0) +/* GPIO_SIG44_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG44_IN_SEL (BIT(7)) +#define GPIO_SIG44_IN_SEL_M (BIT(7)) +#define GPIO_SIG44_IN_SEL_V 0x1 +#define GPIO_SIG44_IN_SEL_S 7 +/* GPIO_FUNC44_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC44_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC44_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC44_IN_INV_SEL_V 0x1 +#define GPIO_FUNC44_IN_INV_SEL_S 6 +/* GPIO_FUNC44_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC44_IN_SEL 0x0000003F +#define GPIO_FUNC44_IN_SEL_M ((GPIO_FUNC44_IN_SEL_V)<<(GPIO_FUNC44_IN_SEL_S)) +#define GPIO_FUNC44_IN_SEL_V 0x3F +#define GPIO_FUNC44_IN_SEL_S 0 + +#define GPIO_FUNC45_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01e4) +/* GPIO_SIG45_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG45_IN_SEL (BIT(7)) +#define GPIO_SIG45_IN_SEL_M (BIT(7)) +#define GPIO_SIG45_IN_SEL_V 0x1 +#define GPIO_SIG45_IN_SEL_S 7 +/* GPIO_FUNC45_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC45_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC45_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC45_IN_INV_SEL_V 0x1 +#define GPIO_FUNC45_IN_INV_SEL_S 6 +/* GPIO_FUNC45_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC45_IN_SEL 0x0000003F +#define GPIO_FUNC45_IN_SEL_M ((GPIO_FUNC45_IN_SEL_V)<<(GPIO_FUNC45_IN_SEL_S)) +#define GPIO_FUNC45_IN_SEL_V 0x3F +#define GPIO_FUNC45_IN_SEL_S 0 + +#define GPIO_FUNC46_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01e8) +/* GPIO_SIG46_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG46_IN_SEL (BIT(7)) +#define GPIO_SIG46_IN_SEL_M (BIT(7)) +#define GPIO_SIG46_IN_SEL_V 0x1 +#define GPIO_SIG46_IN_SEL_S 7 +/* GPIO_FUNC46_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC46_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC46_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC46_IN_INV_SEL_V 0x1 +#define GPIO_FUNC46_IN_INV_SEL_S 6 +/* GPIO_FUNC46_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC46_IN_SEL 0x0000003F +#define GPIO_FUNC46_IN_SEL_M ((GPIO_FUNC46_IN_SEL_V)<<(GPIO_FUNC46_IN_SEL_S)) +#define GPIO_FUNC46_IN_SEL_V 0x3F +#define GPIO_FUNC46_IN_SEL_S 0 + +#define GPIO_FUNC47_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01ec) +/* GPIO_SIG47_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG47_IN_SEL (BIT(7)) +#define GPIO_SIG47_IN_SEL_M (BIT(7)) +#define GPIO_SIG47_IN_SEL_V 0x1 +#define GPIO_SIG47_IN_SEL_S 7 +/* GPIO_FUNC47_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC47_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC47_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC47_IN_INV_SEL_V 0x1 +#define GPIO_FUNC47_IN_INV_SEL_S 6 +/* GPIO_FUNC47_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC47_IN_SEL 0x0000003F +#define GPIO_FUNC47_IN_SEL_M ((GPIO_FUNC47_IN_SEL_V)<<(GPIO_FUNC47_IN_SEL_S)) +#define GPIO_FUNC47_IN_SEL_V 0x3F +#define GPIO_FUNC47_IN_SEL_S 0 + +#define GPIO_FUNC48_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01f0) +/* GPIO_SIG48_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG48_IN_SEL (BIT(7)) +#define GPIO_SIG48_IN_SEL_M (BIT(7)) +#define GPIO_SIG48_IN_SEL_V 0x1 +#define GPIO_SIG48_IN_SEL_S 7 +/* GPIO_FUNC48_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC48_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC48_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC48_IN_INV_SEL_V 0x1 +#define GPIO_FUNC48_IN_INV_SEL_S 6 +/* GPIO_FUNC48_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC48_IN_SEL 0x0000003F +#define GPIO_FUNC48_IN_SEL_M ((GPIO_FUNC48_IN_SEL_V)<<(GPIO_FUNC48_IN_SEL_S)) +#define GPIO_FUNC48_IN_SEL_V 0x3F +#define GPIO_FUNC48_IN_SEL_S 0 + +#define GPIO_FUNC49_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01f4) +/* GPIO_SIG49_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG49_IN_SEL (BIT(7)) +#define GPIO_SIG49_IN_SEL_M (BIT(7)) +#define GPIO_SIG49_IN_SEL_V 0x1 +#define GPIO_SIG49_IN_SEL_S 7 +/* GPIO_FUNC49_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC49_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC49_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC49_IN_INV_SEL_V 0x1 +#define GPIO_FUNC49_IN_INV_SEL_S 6 +/* GPIO_FUNC49_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC49_IN_SEL 0x0000003F +#define GPIO_FUNC49_IN_SEL_M ((GPIO_FUNC49_IN_SEL_V)<<(GPIO_FUNC49_IN_SEL_S)) +#define GPIO_FUNC49_IN_SEL_V 0x3F +#define GPIO_FUNC49_IN_SEL_S 0 + +#define GPIO_FUNC50_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01f8) +/* GPIO_SIG50_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG50_IN_SEL (BIT(7)) +#define GPIO_SIG50_IN_SEL_M (BIT(7)) +#define GPIO_SIG50_IN_SEL_V 0x1 +#define GPIO_SIG50_IN_SEL_S 7 +/* GPIO_FUNC50_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC50_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC50_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC50_IN_INV_SEL_V 0x1 +#define GPIO_FUNC50_IN_INV_SEL_S 6 +/* GPIO_FUNC50_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC50_IN_SEL 0x0000003F +#define GPIO_FUNC50_IN_SEL_M ((GPIO_FUNC50_IN_SEL_V)<<(GPIO_FUNC50_IN_SEL_S)) +#define GPIO_FUNC50_IN_SEL_V 0x3F +#define GPIO_FUNC50_IN_SEL_S 0 + +#define GPIO_FUNC51_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01fc) +/* GPIO_SIG51_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG51_IN_SEL (BIT(7)) +#define GPIO_SIG51_IN_SEL_M (BIT(7)) +#define GPIO_SIG51_IN_SEL_V 0x1 +#define GPIO_SIG51_IN_SEL_S 7 +/* GPIO_FUNC51_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC51_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC51_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC51_IN_INV_SEL_V 0x1 +#define GPIO_FUNC51_IN_INV_SEL_S 6 +/* GPIO_FUNC51_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC51_IN_SEL 0x0000003F +#define GPIO_FUNC51_IN_SEL_M ((GPIO_FUNC51_IN_SEL_V)<<(GPIO_FUNC51_IN_SEL_S)) +#define GPIO_FUNC51_IN_SEL_V 0x3F +#define GPIO_FUNC51_IN_SEL_S 0 + +#define GPIO_FUNC52_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0200) +/* GPIO_SIG52_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG52_IN_SEL (BIT(7)) +#define GPIO_SIG52_IN_SEL_M (BIT(7)) +#define GPIO_SIG52_IN_SEL_V 0x1 +#define GPIO_SIG52_IN_SEL_S 7 +/* GPIO_FUNC52_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC52_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC52_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC52_IN_INV_SEL_V 0x1 +#define GPIO_FUNC52_IN_INV_SEL_S 6 +/* GPIO_FUNC52_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC52_IN_SEL 0x0000003F +#define GPIO_FUNC52_IN_SEL_M ((GPIO_FUNC52_IN_SEL_V)<<(GPIO_FUNC52_IN_SEL_S)) +#define GPIO_FUNC52_IN_SEL_V 0x3F +#define GPIO_FUNC52_IN_SEL_S 0 + +#define GPIO_FUNC53_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0204) +/* GPIO_SIG53_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG53_IN_SEL (BIT(7)) +#define GPIO_SIG53_IN_SEL_M (BIT(7)) +#define GPIO_SIG53_IN_SEL_V 0x1 +#define GPIO_SIG53_IN_SEL_S 7 +/* GPIO_FUNC53_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC53_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC53_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC53_IN_INV_SEL_V 0x1 +#define GPIO_FUNC53_IN_INV_SEL_S 6 +/* GPIO_FUNC53_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC53_IN_SEL 0x0000003F +#define GPIO_FUNC53_IN_SEL_M ((GPIO_FUNC53_IN_SEL_V)<<(GPIO_FUNC53_IN_SEL_S)) +#define GPIO_FUNC53_IN_SEL_V 0x3F +#define GPIO_FUNC53_IN_SEL_S 0 + +#define GPIO_FUNC54_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0208) +/* GPIO_SIG54_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG54_IN_SEL (BIT(7)) +#define GPIO_SIG54_IN_SEL_M (BIT(7)) +#define GPIO_SIG54_IN_SEL_V 0x1 +#define GPIO_SIG54_IN_SEL_S 7 +/* GPIO_FUNC54_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC54_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC54_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC54_IN_INV_SEL_V 0x1 +#define GPIO_FUNC54_IN_INV_SEL_S 6 +/* GPIO_FUNC54_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC54_IN_SEL 0x0000003F +#define GPIO_FUNC54_IN_SEL_M ((GPIO_FUNC54_IN_SEL_V)<<(GPIO_FUNC54_IN_SEL_S)) +#define GPIO_FUNC54_IN_SEL_V 0x3F +#define GPIO_FUNC54_IN_SEL_S 0 + +#define GPIO_FUNC55_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x020c) +/* GPIO_SIG55_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG55_IN_SEL (BIT(7)) +#define GPIO_SIG55_IN_SEL_M (BIT(7)) +#define GPIO_SIG55_IN_SEL_V 0x1 +#define GPIO_SIG55_IN_SEL_S 7 +/* GPIO_FUNC55_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC55_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC55_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC55_IN_INV_SEL_V 0x1 +#define GPIO_FUNC55_IN_INV_SEL_S 6 +/* GPIO_FUNC55_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC55_IN_SEL 0x0000003F +#define GPIO_FUNC55_IN_SEL_M ((GPIO_FUNC55_IN_SEL_V)<<(GPIO_FUNC55_IN_SEL_S)) +#define GPIO_FUNC55_IN_SEL_V 0x3F +#define GPIO_FUNC55_IN_SEL_S 0 + +#define GPIO_FUNC56_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0210) +/* GPIO_SIG56_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG56_IN_SEL (BIT(7)) +#define GPIO_SIG56_IN_SEL_M (BIT(7)) +#define GPIO_SIG56_IN_SEL_V 0x1 +#define GPIO_SIG56_IN_SEL_S 7 +/* GPIO_FUNC56_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC56_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC56_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC56_IN_INV_SEL_V 0x1 +#define GPIO_FUNC56_IN_INV_SEL_S 6 +/* GPIO_FUNC56_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC56_IN_SEL 0x0000003F +#define GPIO_FUNC56_IN_SEL_M ((GPIO_FUNC56_IN_SEL_V)<<(GPIO_FUNC56_IN_SEL_S)) +#define GPIO_FUNC56_IN_SEL_V 0x3F +#define GPIO_FUNC56_IN_SEL_S 0 + +#define GPIO_FUNC57_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0214) +/* GPIO_SIG57_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG57_IN_SEL (BIT(7)) +#define GPIO_SIG57_IN_SEL_M (BIT(7)) +#define GPIO_SIG57_IN_SEL_V 0x1 +#define GPIO_SIG57_IN_SEL_S 7 +/* GPIO_FUNC57_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC57_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC57_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC57_IN_INV_SEL_V 0x1 +#define GPIO_FUNC57_IN_INV_SEL_S 6 +/* GPIO_FUNC57_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC57_IN_SEL 0x0000003F +#define GPIO_FUNC57_IN_SEL_M ((GPIO_FUNC57_IN_SEL_V)<<(GPIO_FUNC57_IN_SEL_S)) +#define GPIO_FUNC57_IN_SEL_V 0x3F +#define GPIO_FUNC57_IN_SEL_S 0 + +#define GPIO_FUNC58_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0218) +/* GPIO_SIG58_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG58_IN_SEL (BIT(7)) +#define GPIO_SIG58_IN_SEL_M (BIT(7)) +#define GPIO_SIG58_IN_SEL_V 0x1 +#define GPIO_SIG58_IN_SEL_S 7 +/* GPIO_FUNC58_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC58_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC58_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC58_IN_INV_SEL_V 0x1 +#define GPIO_FUNC58_IN_INV_SEL_S 6 +/* GPIO_FUNC58_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC58_IN_SEL 0x0000003F +#define GPIO_FUNC58_IN_SEL_M ((GPIO_FUNC58_IN_SEL_V)<<(GPIO_FUNC58_IN_SEL_S)) +#define GPIO_FUNC58_IN_SEL_V 0x3F +#define GPIO_FUNC58_IN_SEL_S 0 + +#define GPIO_FUNC59_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x021c) +/* GPIO_SIG59_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG59_IN_SEL (BIT(7)) +#define GPIO_SIG59_IN_SEL_M (BIT(7)) +#define GPIO_SIG59_IN_SEL_V 0x1 +#define GPIO_SIG59_IN_SEL_S 7 +/* GPIO_FUNC59_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC59_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC59_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC59_IN_INV_SEL_V 0x1 +#define GPIO_FUNC59_IN_INV_SEL_S 6 +/* GPIO_FUNC59_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC59_IN_SEL 0x0000003F +#define GPIO_FUNC59_IN_SEL_M ((GPIO_FUNC59_IN_SEL_V)<<(GPIO_FUNC59_IN_SEL_S)) +#define GPIO_FUNC59_IN_SEL_V 0x3F +#define GPIO_FUNC59_IN_SEL_S 0 + +#define GPIO_FUNC60_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0220) +/* GPIO_SIG60_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG60_IN_SEL (BIT(7)) +#define GPIO_SIG60_IN_SEL_M (BIT(7)) +#define GPIO_SIG60_IN_SEL_V 0x1 +#define GPIO_SIG60_IN_SEL_S 7 +/* GPIO_FUNC60_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC60_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC60_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC60_IN_INV_SEL_V 0x1 +#define GPIO_FUNC60_IN_INV_SEL_S 6 +/* GPIO_FUNC60_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC60_IN_SEL 0x0000003F +#define GPIO_FUNC60_IN_SEL_M ((GPIO_FUNC60_IN_SEL_V)<<(GPIO_FUNC60_IN_SEL_S)) +#define GPIO_FUNC60_IN_SEL_V 0x3F +#define GPIO_FUNC60_IN_SEL_S 0 + +#define GPIO_FUNC61_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0224) +/* GPIO_SIG61_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG61_IN_SEL (BIT(7)) +#define GPIO_SIG61_IN_SEL_M (BIT(7)) +#define GPIO_SIG61_IN_SEL_V 0x1 +#define GPIO_SIG61_IN_SEL_S 7 +/* GPIO_FUNC61_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC61_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC61_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC61_IN_INV_SEL_V 0x1 +#define GPIO_FUNC61_IN_INV_SEL_S 6 +/* GPIO_FUNC61_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC61_IN_SEL 0x0000003F +#define GPIO_FUNC61_IN_SEL_M ((GPIO_FUNC61_IN_SEL_V)<<(GPIO_FUNC61_IN_SEL_S)) +#define GPIO_FUNC61_IN_SEL_V 0x3F +#define GPIO_FUNC61_IN_SEL_S 0 + +#define GPIO_FUNC62_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0228) +/* GPIO_SIG62_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG62_IN_SEL (BIT(7)) +#define GPIO_SIG62_IN_SEL_M (BIT(7)) +#define GPIO_SIG62_IN_SEL_V 0x1 +#define GPIO_SIG62_IN_SEL_S 7 +/* GPIO_FUNC62_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC62_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC62_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC62_IN_INV_SEL_V 0x1 +#define GPIO_FUNC62_IN_INV_SEL_S 6 +/* GPIO_FUNC62_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC62_IN_SEL 0x0000003F +#define GPIO_FUNC62_IN_SEL_M ((GPIO_FUNC62_IN_SEL_V)<<(GPIO_FUNC62_IN_SEL_S)) +#define GPIO_FUNC62_IN_SEL_V 0x3F +#define GPIO_FUNC62_IN_SEL_S 0 + +#define GPIO_FUNC63_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x022c) +/* GPIO_SIG63_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG63_IN_SEL (BIT(7)) +#define GPIO_SIG63_IN_SEL_M (BIT(7)) +#define GPIO_SIG63_IN_SEL_V 0x1 +#define GPIO_SIG63_IN_SEL_S 7 +/* GPIO_FUNC63_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC63_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC63_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC63_IN_INV_SEL_V 0x1 +#define GPIO_FUNC63_IN_INV_SEL_S 6 +/* GPIO_FUNC63_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC63_IN_SEL 0x0000003F +#define GPIO_FUNC63_IN_SEL_M ((GPIO_FUNC63_IN_SEL_V)<<(GPIO_FUNC63_IN_SEL_S)) +#define GPIO_FUNC63_IN_SEL_V 0x3F +#define GPIO_FUNC63_IN_SEL_S 0 + +#define GPIO_FUNC64_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0230) +/* GPIO_SIG64_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG64_IN_SEL (BIT(7)) +#define GPIO_SIG64_IN_SEL_M (BIT(7)) +#define GPIO_SIG64_IN_SEL_V 0x1 +#define GPIO_SIG64_IN_SEL_S 7 +/* GPIO_FUNC64_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC64_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC64_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC64_IN_INV_SEL_V 0x1 +#define GPIO_FUNC64_IN_INV_SEL_S 6 +/* GPIO_FUNC64_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC64_IN_SEL 0x0000003F +#define GPIO_FUNC64_IN_SEL_M ((GPIO_FUNC64_IN_SEL_V)<<(GPIO_FUNC64_IN_SEL_S)) +#define GPIO_FUNC64_IN_SEL_V 0x3F +#define GPIO_FUNC64_IN_SEL_S 0 + +#define GPIO_FUNC65_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0234) +/* GPIO_SIG65_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG65_IN_SEL (BIT(7)) +#define GPIO_SIG65_IN_SEL_M (BIT(7)) +#define GPIO_SIG65_IN_SEL_V 0x1 +#define GPIO_SIG65_IN_SEL_S 7 +/* GPIO_FUNC65_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC65_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC65_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC65_IN_INV_SEL_V 0x1 +#define GPIO_FUNC65_IN_INV_SEL_S 6 +/* GPIO_FUNC65_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC65_IN_SEL 0x0000003F +#define GPIO_FUNC65_IN_SEL_M ((GPIO_FUNC65_IN_SEL_V)<<(GPIO_FUNC65_IN_SEL_S)) +#define GPIO_FUNC65_IN_SEL_V 0x3F +#define GPIO_FUNC65_IN_SEL_S 0 + +#define GPIO_FUNC66_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0238) +/* GPIO_SIG66_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG66_IN_SEL (BIT(7)) +#define GPIO_SIG66_IN_SEL_M (BIT(7)) +#define GPIO_SIG66_IN_SEL_V 0x1 +#define GPIO_SIG66_IN_SEL_S 7 +/* GPIO_FUNC66_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC66_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC66_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC66_IN_INV_SEL_V 0x1 +#define GPIO_FUNC66_IN_INV_SEL_S 6 +/* GPIO_FUNC66_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC66_IN_SEL 0x0000003F +#define GPIO_FUNC66_IN_SEL_M ((GPIO_FUNC66_IN_SEL_V)<<(GPIO_FUNC66_IN_SEL_S)) +#define GPIO_FUNC66_IN_SEL_V 0x3F +#define GPIO_FUNC66_IN_SEL_S 0 + +#define GPIO_FUNC67_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x023c) +/* GPIO_SIG67_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG67_IN_SEL (BIT(7)) +#define GPIO_SIG67_IN_SEL_M (BIT(7)) +#define GPIO_SIG67_IN_SEL_V 0x1 +#define GPIO_SIG67_IN_SEL_S 7 +/* GPIO_FUNC67_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC67_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC67_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC67_IN_INV_SEL_V 0x1 +#define GPIO_FUNC67_IN_INV_SEL_S 6 +/* GPIO_FUNC67_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC67_IN_SEL 0x0000003F +#define GPIO_FUNC67_IN_SEL_M ((GPIO_FUNC67_IN_SEL_V)<<(GPIO_FUNC67_IN_SEL_S)) +#define GPIO_FUNC67_IN_SEL_V 0x3F +#define GPIO_FUNC67_IN_SEL_S 0 + +#define GPIO_FUNC68_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0240) +/* GPIO_SIG68_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG68_IN_SEL (BIT(7)) +#define GPIO_SIG68_IN_SEL_M (BIT(7)) +#define GPIO_SIG68_IN_SEL_V 0x1 +#define GPIO_SIG68_IN_SEL_S 7 +/* GPIO_FUNC68_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC68_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC68_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC68_IN_INV_SEL_V 0x1 +#define GPIO_FUNC68_IN_INV_SEL_S 6 +/* GPIO_FUNC68_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC68_IN_SEL 0x0000003F +#define GPIO_FUNC68_IN_SEL_M ((GPIO_FUNC68_IN_SEL_V)<<(GPIO_FUNC68_IN_SEL_S)) +#define GPIO_FUNC68_IN_SEL_V 0x3F +#define GPIO_FUNC68_IN_SEL_S 0 + +#define GPIO_FUNC69_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0244) +/* GPIO_SIG69_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG69_IN_SEL (BIT(7)) +#define GPIO_SIG69_IN_SEL_M (BIT(7)) +#define GPIO_SIG69_IN_SEL_V 0x1 +#define GPIO_SIG69_IN_SEL_S 7 +/* GPIO_FUNC69_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC69_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC69_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC69_IN_INV_SEL_V 0x1 +#define GPIO_FUNC69_IN_INV_SEL_S 6 +/* GPIO_FUNC69_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC69_IN_SEL 0x0000003F +#define GPIO_FUNC69_IN_SEL_M ((GPIO_FUNC69_IN_SEL_V)<<(GPIO_FUNC69_IN_SEL_S)) +#define GPIO_FUNC69_IN_SEL_V 0x3F +#define GPIO_FUNC69_IN_SEL_S 0 + +#define GPIO_FUNC70_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0248) +/* GPIO_SIG70_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG70_IN_SEL (BIT(7)) +#define GPIO_SIG70_IN_SEL_M (BIT(7)) +#define GPIO_SIG70_IN_SEL_V 0x1 +#define GPIO_SIG70_IN_SEL_S 7 +/* GPIO_FUNC70_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC70_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC70_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC70_IN_INV_SEL_V 0x1 +#define GPIO_FUNC70_IN_INV_SEL_S 6 +/* GPIO_FUNC70_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC70_IN_SEL 0x0000003F +#define GPIO_FUNC70_IN_SEL_M ((GPIO_FUNC70_IN_SEL_V)<<(GPIO_FUNC70_IN_SEL_S)) +#define GPIO_FUNC70_IN_SEL_V 0x3F +#define GPIO_FUNC70_IN_SEL_S 0 + +#define GPIO_FUNC71_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x024c) +/* GPIO_SIG71_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG71_IN_SEL (BIT(7)) +#define GPIO_SIG71_IN_SEL_M (BIT(7)) +#define GPIO_SIG71_IN_SEL_V 0x1 +#define GPIO_SIG71_IN_SEL_S 7 +/* GPIO_FUNC71_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC71_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC71_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC71_IN_INV_SEL_V 0x1 +#define GPIO_FUNC71_IN_INV_SEL_S 6 +/* GPIO_FUNC71_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC71_IN_SEL 0x0000003F +#define GPIO_FUNC71_IN_SEL_M ((GPIO_FUNC71_IN_SEL_V)<<(GPIO_FUNC71_IN_SEL_S)) +#define GPIO_FUNC71_IN_SEL_V 0x3F +#define GPIO_FUNC71_IN_SEL_S 0 + +#define GPIO_FUNC72_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0250) +/* GPIO_SIG72_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG72_IN_SEL (BIT(7)) +#define GPIO_SIG72_IN_SEL_M (BIT(7)) +#define GPIO_SIG72_IN_SEL_V 0x1 +#define GPIO_SIG72_IN_SEL_S 7 +/* GPIO_FUNC72_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC72_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC72_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC72_IN_INV_SEL_V 0x1 +#define GPIO_FUNC72_IN_INV_SEL_S 6 +/* GPIO_FUNC72_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC72_IN_SEL 0x0000003F +#define GPIO_FUNC72_IN_SEL_M ((GPIO_FUNC72_IN_SEL_V)<<(GPIO_FUNC72_IN_SEL_S)) +#define GPIO_FUNC72_IN_SEL_V 0x3F +#define GPIO_FUNC72_IN_SEL_S 0 + +#define GPIO_FUNC73_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0254) +/* GPIO_SIG73_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG73_IN_SEL (BIT(7)) +#define GPIO_SIG73_IN_SEL_M (BIT(7)) +#define GPIO_SIG73_IN_SEL_V 0x1 +#define GPIO_SIG73_IN_SEL_S 7 +/* GPIO_FUNC73_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC73_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC73_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC73_IN_INV_SEL_V 0x1 +#define GPIO_FUNC73_IN_INV_SEL_S 6 +/* GPIO_FUNC73_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC73_IN_SEL 0x0000003F +#define GPIO_FUNC73_IN_SEL_M ((GPIO_FUNC73_IN_SEL_V)<<(GPIO_FUNC73_IN_SEL_S)) +#define GPIO_FUNC73_IN_SEL_V 0x3F +#define GPIO_FUNC73_IN_SEL_S 0 + +#define GPIO_FUNC74_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0258) +/* GPIO_SIG74_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG74_IN_SEL (BIT(7)) +#define GPIO_SIG74_IN_SEL_M (BIT(7)) +#define GPIO_SIG74_IN_SEL_V 0x1 +#define GPIO_SIG74_IN_SEL_S 7 +/* GPIO_FUNC74_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC74_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC74_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC74_IN_INV_SEL_V 0x1 +#define GPIO_FUNC74_IN_INV_SEL_S 6 +/* GPIO_FUNC74_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC74_IN_SEL 0x0000003F +#define GPIO_FUNC74_IN_SEL_M ((GPIO_FUNC74_IN_SEL_V)<<(GPIO_FUNC74_IN_SEL_S)) +#define GPIO_FUNC74_IN_SEL_V 0x3F +#define GPIO_FUNC74_IN_SEL_S 0 + +#define GPIO_FUNC75_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x025c) +/* GPIO_SIG75_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG75_IN_SEL (BIT(7)) +#define GPIO_SIG75_IN_SEL_M (BIT(7)) +#define GPIO_SIG75_IN_SEL_V 0x1 +#define GPIO_SIG75_IN_SEL_S 7 +/* GPIO_FUNC75_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC75_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC75_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC75_IN_INV_SEL_V 0x1 +#define GPIO_FUNC75_IN_INV_SEL_S 6 +/* GPIO_FUNC75_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC75_IN_SEL 0x0000003F +#define GPIO_FUNC75_IN_SEL_M ((GPIO_FUNC75_IN_SEL_V)<<(GPIO_FUNC75_IN_SEL_S)) +#define GPIO_FUNC75_IN_SEL_V 0x3F +#define GPIO_FUNC75_IN_SEL_S 0 + +#define GPIO_FUNC76_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0260) +/* GPIO_SIG76_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG76_IN_SEL (BIT(7)) +#define GPIO_SIG76_IN_SEL_M (BIT(7)) +#define GPIO_SIG76_IN_SEL_V 0x1 +#define GPIO_SIG76_IN_SEL_S 7 +/* GPIO_FUNC76_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC76_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC76_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC76_IN_INV_SEL_V 0x1 +#define GPIO_FUNC76_IN_INV_SEL_S 6 +/* GPIO_FUNC76_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC76_IN_SEL 0x0000003F +#define GPIO_FUNC76_IN_SEL_M ((GPIO_FUNC76_IN_SEL_V)<<(GPIO_FUNC76_IN_SEL_S)) +#define GPIO_FUNC76_IN_SEL_V 0x3F +#define GPIO_FUNC76_IN_SEL_S 0 + +#define GPIO_FUNC77_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0264) +/* GPIO_SIG77_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG77_IN_SEL (BIT(7)) +#define GPIO_SIG77_IN_SEL_M (BIT(7)) +#define GPIO_SIG77_IN_SEL_V 0x1 +#define GPIO_SIG77_IN_SEL_S 7 +/* GPIO_FUNC77_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC77_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC77_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC77_IN_INV_SEL_V 0x1 +#define GPIO_FUNC77_IN_INV_SEL_S 6 +/* GPIO_FUNC77_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC77_IN_SEL 0x0000003F +#define GPIO_FUNC77_IN_SEL_M ((GPIO_FUNC77_IN_SEL_V)<<(GPIO_FUNC77_IN_SEL_S)) +#define GPIO_FUNC77_IN_SEL_V 0x3F +#define GPIO_FUNC77_IN_SEL_S 0 + +#define GPIO_FUNC78_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0268) +/* GPIO_SIG78_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG78_IN_SEL (BIT(7)) +#define GPIO_SIG78_IN_SEL_M (BIT(7)) +#define GPIO_SIG78_IN_SEL_V 0x1 +#define GPIO_SIG78_IN_SEL_S 7 +/* GPIO_FUNC78_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC78_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC78_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC78_IN_INV_SEL_V 0x1 +#define GPIO_FUNC78_IN_INV_SEL_S 6 +/* GPIO_FUNC78_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC78_IN_SEL 0x0000003F +#define GPIO_FUNC78_IN_SEL_M ((GPIO_FUNC78_IN_SEL_V)<<(GPIO_FUNC78_IN_SEL_S)) +#define GPIO_FUNC78_IN_SEL_V 0x3F +#define GPIO_FUNC78_IN_SEL_S 0 + +#define GPIO_FUNC79_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x026c) +/* GPIO_SIG79_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG79_IN_SEL (BIT(7)) +#define GPIO_SIG79_IN_SEL_M (BIT(7)) +#define GPIO_SIG79_IN_SEL_V 0x1 +#define GPIO_SIG79_IN_SEL_S 7 +/* GPIO_FUNC79_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC79_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC79_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC79_IN_INV_SEL_V 0x1 +#define GPIO_FUNC79_IN_INV_SEL_S 6 +/* GPIO_FUNC79_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC79_IN_SEL 0x0000003F +#define GPIO_FUNC79_IN_SEL_M ((GPIO_FUNC79_IN_SEL_V)<<(GPIO_FUNC79_IN_SEL_S)) +#define GPIO_FUNC79_IN_SEL_V 0x3F +#define GPIO_FUNC79_IN_SEL_S 0 + +#define GPIO_FUNC80_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0270) +/* GPIO_SIG80_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG80_IN_SEL (BIT(7)) +#define GPIO_SIG80_IN_SEL_M (BIT(7)) +#define GPIO_SIG80_IN_SEL_V 0x1 +#define GPIO_SIG80_IN_SEL_S 7 +/* GPIO_FUNC80_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC80_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC80_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC80_IN_INV_SEL_V 0x1 +#define GPIO_FUNC80_IN_INV_SEL_S 6 +/* GPIO_FUNC80_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC80_IN_SEL 0x0000003F +#define GPIO_FUNC80_IN_SEL_M ((GPIO_FUNC80_IN_SEL_V)<<(GPIO_FUNC80_IN_SEL_S)) +#define GPIO_FUNC80_IN_SEL_V 0x3F +#define GPIO_FUNC80_IN_SEL_S 0 + +#define GPIO_FUNC81_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0274) +/* GPIO_SIG81_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG81_IN_SEL (BIT(7)) +#define GPIO_SIG81_IN_SEL_M (BIT(7)) +#define GPIO_SIG81_IN_SEL_V 0x1 +#define GPIO_SIG81_IN_SEL_S 7 +/* GPIO_FUNC81_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC81_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC81_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC81_IN_INV_SEL_V 0x1 +#define GPIO_FUNC81_IN_INV_SEL_S 6 +/* GPIO_FUNC81_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC81_IN_SEL 0x0000003F +#define GPIO_FUNC81_IN_SEL_M ((GPIO_FUNC81_IN_SEL_V)<<(GPIO_FUNC81_IN_SEL_S)) +#define GPIO_FUNC81_IN_SEL_V 0x3F +#define GPIO_FUNC81_IN_SEL_S 0 + +#define GPIO_FUNC82_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0278) +/* GPIO_SIG82_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG82_IN_SEL (BIT(7)) +#define GPIO_SIG82_IN_SEL_M (BIT(7)) +#define GPIO_SIG82_IN_SEL_V 0x1 +#define GPIO_SIG82_IN_SEL_S 7 +/* GPIO_FUNC82_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC82_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC82_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC82_IN_INV_SEL_V 0x1 +#define GPIO_FUNC82_IN_INV_SEL_S 6 +/* GPIO_FUNC82_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC82_IN_SEL 0x0000003F +#define GPIO_FUNC82_IN_SEL_M ((GPIO_FUNC82_IN_SEL_V)<<(GPIO_FUNC82_IN_SEL_S)) +#define GPIO_FUNC82_IN_SEL_V 0x3F +#define GPIO_FUNC82_IN_SEL_S 0 + +#define GPIO_FUNC83_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x027c) +/* GPIO_SIG83_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG83_IN_SEL (BIT(7)) +#define GPIO_SIG83_IN_SEL_M (BIT(7)) +#define GPIO_SIG83_IN_SEL_V 0x1 +#define GPIO_SIG83_IN_SEL_S 7 +/* GPIO_FUNC83_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC83_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC83_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC83_IN_INV_SEL_V 0x1 +#define GPIO_FUNC83_IN_INV_SEL_S 6 +/* GPIO_FUNC83_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC83_IN_SEL 0x0000003F +#define GPIO_FUNC83_IN_SEL_M ((GPIO_FUNC83_IN_SEL_V)<<(GPIO_FUNC83_IN_SEL_S)) +#define GPIO_FUNC83_IN_SEL_V 0x3F +#define GPIO_FUNC83_IN_SEL_S 0 + +#define GPIO_FUNC84_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0280) +/* GPIO_SIG84_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG84_IN_SEL (BIT(7)) +#define GPIO_SIG84_IN_SEL_M (BIT(7)) +#define GPIO_SIG84_IN_SEL_V 0x1 +#define GPIO_SIG84_IN_SEL_S 7 +/* GPIO_FUNC84_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC84_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC84_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC84_IN_INV_SEL_V 0x1 +#define GPIO_FUNC84_IN_INV_SEL_S 6 +/* GPIO_FUNC84_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC84_IN_SEL 0x0000003F +#define GPIO_FUNC84_IN_SEL_M ((GPIO_FUNC84_IN_SEL_V)<<(GPIO_FUNC84_IN_SEL_S)) +#define GPIO_FUNC84_IN_SEL_V 0x3F +#define GPIO_FUNC84_IN_SEL_S 0 + +#define GPIO_FUNC85_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0284) +/* GPIO_SIG85_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG85_IN_SEL (BIT(7)) +#define GPIO_SIG85_IN_SEL_M (BIT(7)) +#define GPIO_SIG85_IN_SEL_V 0x1 +#define GPIO_SIG85_IN_SEL_S 7 +/* GPIO_FUNC85_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC85_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC85_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC85_IN_INV_SEL_V 0x1 +#define GPIO_FUNC85_IN_INV_SEL_S 6 +/* GPIO_FUNC85_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC85_IN_SEL 0x0000003F +#define GPIO_FUNC85_IN_SEL_M ((GPIO_FUNC85_IN_SEL_V)<<(GPIO_FUNC85_IN_SEL_S)) +#define GPIO_FUNC85_IN_SEL_V 0x3F +#define GPIO_FUNC85_IN_SEL_S 0 + +#define GPIO_FUNC86_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0288) +/* GPIO_SIG86_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG86_IN_SEL (BIT(7)) +#define GPIO_SIG86_IN_SEL_M (BIT(7)) +#define GPIO_SIG86_IN_SEL_V 0x1 +#define GPIO_SIG86_IN_SEL_S 7 +/* GPIO_FUNC86_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC86_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC86_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC86_IN_INV_SEL_V 0x1 +#define GPIO_FUNC86_IN_INV_SEL_S 6 +/* GPIO_FUNC86_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC86_IN_SEL 0x0000003F +#define GPIO_FUNC86_IN_SEL_M ((GPIO_FUNC86_IN_SEL_V)<<(GPIO_FUNC86_IN_SEL_S)) +#define GPIO_FUNC86_IN_SEL_V 0x3F +#define GPIO_FUNC86_IN_SEL_S 0 + +#define GPIO_FUNC87_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x028c) +/* GPIO_SIG87_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG87_IN_SEL (BIT(7)) +#define GPIO_SIG87_IN_SEL_M (BIT(7)) +#define GPIO_SIG87_IN_SEL_V 0x1 +#define GPIO_SIG87_IN_SEL_S 7 +/* GPIO_FUNC87_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC87_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC87_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC87_IN_INV_SEL_V 0x1 +#define GPIO_FUNC87_IN_INV_SEL_S 6 +/* GPIO_FUNC87_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC87_IN_SEL 0x0000003F +#define GPIO_FUNC87_IN_SEL_M ((GPIO_FUNC87_IN_SEL_V)<<(GPIO_FUNC87_IN_SEL_S)) +#define GPIO_FUNC87_IN_SEL_V 0x3F +#define GPIO_FUNC87_IN_SEL_S 0 + +#define GPIO_FUNC88_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0290) +/* GPIO_SIG88_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG88_IN_SEL (BIT(7)) +#define GPIO_SIG88_IN_SEL_M (BIT(7)) +#define GPIO_SIG88_IN_SEL_V 0x1 +#define GPIO_SIG88_IN_SEL_S 7 +/* GPIO_FUNC88_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC88_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC88_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC88_IN_INV_SEL_V 0x1 +#define GPIO_FUNC88_IN_INV_SEL_S 6 +/* GPIO_FUNC88_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC88_IN_SEL 0x0000003F +#define GPIO_FUNC88_IN_SEL_M ((GPIO_FUNC88_IN_SEL_V)<<(GPIO_FUNC88_IN_SEL_S)) +#define GPIO_FUNC88_IN_SEL_V 0x3F +#define GPIO_FUNC88_IN_SEL_S 0 + +#define GPIO_FUNC89_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0294) +/* GPIO_SIG89_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG89_IN_SEL (BIT(7)) +#define GPIO_SIG89_IN_SEL_M (BIT(7)) +#define GPIO_SIG89_IN_SEL_V 0x1 +#define GPIO_SIG89_IN_SEL_S 7 +/* GPIO_FUNC89_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC89_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC89_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC89_IN_INV_SEL_V 0x1 +#define GPIO_FUNC89_IN_INV_SEL_S 6 +/* GPIO_FUNC89_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC89_IN_SEL 0x0000003F +#define GPIO_FUNC89_IN_SEL_M ((GPIO_FUNC89_IN_SEL_V)<<(GPIO_FUNC89_IN_SEL_S)) +#define GPIO_FUNC89_IN_SEL_V 0x3F +#define GPIO_FUNC89_IN_SEL_S 0 + +#define GPIO_FUNC90_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0298) +/* GPIO_SIG90_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG90_IN_SEL (BIT(7)) +#define GPIO_SIG90_IN_SEL_M (BIT(7)) +#define GPIO_SIG90_IN_SEL_V 0x1 +#define GPIO_SIG90_IN_SEL_S 7 +/* GPIO_FUNC90_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC90_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC90_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC90_IN_INV_SEL_V 0x1 +#define GPIO_FUNC90_IN_INV_SEL_S 6 +/* GPIO_FUNC90_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC90_IN_SEL 0x0000003F +#define GPIO_FUNC90_IN_SEL_M ((GPIO_FUNC90_IN_SEL_V)<<(GPIO_FUNC90_IN_SEL_S)) +#define GPIO_FUNC90_IN_SEL_V 0x3F +#define GPIO_FUNC90_IN_SEL_S 0 + +#define GPIO_FUNC91_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x029c) +/* GPIO_SIG91_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG91_IN_SEL (BIT(7)) +#define GPIO_SIG91_IN_SEL_M (BIT(7)) +#define GPIO_SIG91_IN_SEL_V 0x1 +#define GPIO_SIG91_IN_SEL_S 7 +/* GPIO_FUNC91_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC91_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC91_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC91_IN_INV_SEL_V 0x1 +#define GPIO_FUNC91_IN_INV_SEL_S 6 +/* GPIO_FUNC91_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC91_IN_SEL 0x0000003F +#define GPIO_FUNC91_IN_SEL_M ((GPIO_FUNC91_IN_SEL_V)<<(GPIO_FUNC91_IN_SEL_S)) +#define GPIO_FUNC91_IN_SEL_V 0x3F +#define GPIO_FUNC91_IN_SEL_S 0 + +#define GPIO_FUNC92_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02a0) +/* GPIO_SIG92_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG92_IN_SEL (BIT(7)) +#define GPIO_SIG92_IN_SEL_M (BIT(7)) +#define GPIO_SIG92_IN_SEL_V 0x1 +#define GPIO_SIG92_IN_SEL_S 7 +/* GPIO_FUNC92_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC92_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC92_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC92_IN_INV_SEL_V 0x1 +#define GPIO_FUNC92_IN_INV_SEL_S 6 +/* GPIO_FUNC92_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC92_IN_SEL 0x0000003F +#define GPIO_FUNC92_IN_SEL_M ((GPIO_FUNC92_IN_SEL_V)<<(GPIO_FUNC92_IN_SEL_S)) +#define GPIO_FUNC92_IN_SEL_V 0x3F +#define GPIO_FUNC92_IN_SEL_S 0 + +#define GPIO_FUNC93_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02a4) +/* GPIO_SIG93_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG93_IN_SEL (BIT(7)) +#define GPIO_SIG93_IN_SEL_M (BIT(7)) +#define GPIO_SIG93_IN_SEL_V 0x1 +#define GPIO_SIG93_IN_SEL_S 7 +/* GPIO_FUNC93_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC93_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC93_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC93_IN_INV_SEL_V 0x1 +#define GPIO_FUNC93_IN_INV_SEL_S 6 +/* GPIO_FUNC93_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC93_IN_SEL 0x0000003F +#define GPIO_FUNC93_IN_SEL_M ((GPIO_FUNC93_IN_SEL_V)<<(GPIO_FUNC93_IN_SEL_S)) +#define GPIO_FUNC93_IN_SEL_V 0x3F +#define GPIO_FUNC93_IN_SEL_S 0 + +#define GPIO_FUNC94_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02a8) +/* GPIO_SIG94_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG94_IN_SEL (BIT(7)) +#define GPIO_SIG94_IN_SEL_M (BIT(7)) +#define GPIO_SIG94_IN_SEL_V 0x1 +#define GPIO_SIG94_IN_SEL_S 7 +/* GPIO_FUNC94_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC94_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC94_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC94_IN_INV_SEL_V 0x1 +#define GPIO_FUNC94_IN_INV_SEL_S 6 +/* GPIO_FUNC94_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC94_IN_SEL 0x0000003F +#define GPIO_FUNC94_IN_SEL_M ((GPIO_FUNC94_IN_SEL_V)<<(GPIO_FUNC94_IN_SEL_S)) +#define GPIO_FUNC94_IN_SEL_V 0x3F +#define GPIO_FUNC94_IN_SEL_S 0 + +#define GPIO_FUNC95_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02ac) +/* GPIO_SIG95_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG95_IN_SEL (BIT(7)) +#define GPIO_SIG95_IN_SEL_M (BIT(7)) +#define GPIO_SIG95_IN_SEL_V 0x1 +#define GPIO_SIG95_IN_SEL_S 7 +/* GPIO_FUNC95_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC95_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC95_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC95_IN_INV_SEL_V 0x1 +#define GPIO_FUNC95_IN_INV_SEL_S 6 +/* GPIO_FUNC95_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC95_IN_SEL 0x0000003F +#define GPIO_FUNC95_IN_SEL_M ((GPIO_FUNC95_IN_SEL_V)<<(GPIO_FUNC95_IN_SEL_S)) +#define GPIO_FUNC95_IN_SEL_V 0x3F +#define GPIO_FUNC95_IN_SEL_S 0 + +#define GPIO_FUNC96_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02b0) +/* GPIO_SIG96_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG96_IN_SEL (BIT(7)) +#define GPIO_SIG96_IN_SEL_M (BIT(7)) +#define GPIO_SIG96_IN_SEL_V 0x1 +#define GPIO_SIG96_IN_SEL_S 7 +/* GPIO_FUNC96_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC96_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC96_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC96_IN_INV_SEL_V 0x1 +#define GPIO_FUNC96_IN_INV_SEL_S 6 +/* GPIO_FUNC96_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC96_IN_SEL 0x0000003F +#define GPIO_FUNC96_IN_SEL_M ((GPIO_FUNC96_IN_SEL_V)<<(GPIO_FUNC96_IN_SEL_S)) +#define GPIO_FUNC96_IN_SEL_V 0x3F +#define GPIO_FUNC96_IN_SEL_S 0 + +#define GPIO_FUNC97_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02b4) +/* GPIO_SIG97_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG97_IN_SEL (BIT(7)) +#define GPIO_SIG97_IN_SEL_M (BIT(7)) +#define GPIO_SIG97_IN_SEL_V 0x1 +#define GPIO_SIG97_IN_SEL_S 7 +/* GPIO_FUNC97_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC97_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC97_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC97_IN_INV_SEL_V 0x1 +#define GPIO_FUNC97_IN_INV_SEL_S 6 +/* GPIO_FUNC97_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC97_IN_SEL 0x0000003F +#define GPIO_FUNC97_IN_SEL_M ((GPIO_FUNC97_IN_SEL_V)<<(GPIO_FUNC97_IN_SEL_S)) +#define GPIO_FUNC97_IN_SEL_V 0x3F +#define GPIO_FUNC97_IN_SEL_S 0 + +#define GPIO_FUNC98_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02b8) +/* GPIO_SIG98_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG98_IN_SEL (BIT(7)) +#define GPIO_SIG98_IN_SEL_M (BIT(7)) +#define GPIO_SIG98_IN_SEL_V 0x1 +#define GPIO_SIG98_IN_SEL_S 7 +/* GPIO_FUNC98_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC98_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC98_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC98_IN_INV_SEL_V 0x1 +#define GPIO_FUNC98_IN_INV_SEL_S 6 +/* GPIO_FUNC98_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC98_IN_SEL 0x0000003F +#define GPIO_FUNC98_IN_SEL_M ((GPIO_FUNC98_IN_SEL_V)<<(GPIO_FUNC98_IN_SEL_S)) +#define GPIO_FUNC98_IN_SEL_V 0x3F +#define GPIO_FUNC98_IN_SEL_S 0 + +#define GPIO_FUNC99_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02bc) +/* GPIO_SIG99_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG99_IN_SEL (BIT(7)) +#define GPIO_SIG99_IN_SEL_M (BIT(7)) +#define GPIO_SIG99_IN_SEL_V 0x1 +#define GPIO_SIG99_IN_SEL_S 7 +/* GPIO_FUNC99_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC99_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC99_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC99_IN_INV_SEL_V 0x1 +#define GPIO_FUNC99_IN_INV_SEL_S 6 +/* GPIO_FUNC99_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC99_IN_SEL 0x0000003F +#define GPIO_FUNC99_IN_SEL_M ((GPIO_FUNC99_IN_SEL_V)<<(GPIO_FUNC99_IN_SEL_S)) +#define GPIO_FUNC99_IN_SEL_V 0x3F +#define GPIO_FUNC99_IN_SEL_S 0 + +#define GPIO_FUNC100_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02c0) +/* GPIO_SIG100_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG100_IN_SEL (BIT(7)) +#define GPIO_SIG100_IN_SEL_M (BIT(7)) +#define GPIO_SIG100_IN_SEL_V 0x1 +#define GPIO_SIG100_IN_SEL_S 7 +/* GPIO_FUNC100_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC100_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC100_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC100_IN_INV_SEL_V 0x1 +#define GPIO_FUNC100_IN_INV_SEL_S 6 +/* GPIO_FUNC100_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC100_IN_SEL 0x0000003F +#define GPIO_FUNC100_IN_SEL_M ((GPIO_FUNC100_IN_SEL_V)<<(GPIO_FUNC100_IN_SEL_S)) +#define GPIO_FUNC100_IN_SEL_V 0x3F +#define GPIO_FUNC100_IN_SEL_S 0 + +#define GPIO_FUNC101_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02c4) +/* GPIO_SIG101_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG101_IN_SEL (BIT(7)) +#define GPIO_SIG101_IN_SEL_M (BIT(7)) +#define GPIO_SIG101_IN_SEL_V 0x1 +#define GPIO_SIG101_IN_SEL_S 7 +/* GPIO_FUNC101_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC101_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC101_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC101_IN_INV_SEL_V 0x1 +#define GPIO_FUNC101_IN_INV_SEL_S 6 +/* GPIO_FUNC101_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC101_IN_SEL 0x0000003F +#define GPIO_FUNC101_IN_SEL_M ((GPIO_FUNC101_IN_SEL_V)<<(GPIO_FUNC101_IN_SEL_S)) +#define GPIO_FUNC101_IN_SEL_V 0x3F +#define GPIO_FUNC101_IN_SEL_S 0 + +#define GPIO_FUNC102_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02c8) +/* GPIO_SIG102_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG102_IN_SEL (BIT(7)) +#define GPIO_SIG102_IN_SEL_M (BIT(7)) +#define GPIO_SIG102_IN_SEL_V 0x1 +#define GPIO_SIG102_IN_SEL_S 7 +/* GPIO_FUNC102_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC102_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC102_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC102_IN_INV_SEL_V 0x1 +#define GPIO_FUNC102_IN_INV_SEL_S 6 +/* GPIO_FUNC102_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC102_IN_SEL 0x0000003F +#define GPIO_FUNC102_IN_SEL_M ((GPIO_FUNC102_IN_SEL_V)<<(GPIO_FUNC102_IN_SEL_S)) +#define GPIO_FUNC102_IN_SEL_V 0x3F +#define GPIO_FUNC102_IN_SEL_S 0 + +#define GPIO_FUNC103_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02cc) +/* GPIO_SIG103_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG103_IN_SEL (BIT(7)) +#define GPIO_SIG103_IN_SEL_M (BIT(7)) +#define GPIO_SIG103_IN_SEL_V 0x1 +#define GPIO_SIG103_IN_SEL_S 7 +/* GPIO_FUNC103_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC103_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC103_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC103_IN_INV_SEL_V 0x1 +#define GPIO_FUNC103_IN_INV_SEL_S 6 +/* GPIO_FUNC103_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC103_IN_SEL 0x0000003F +#define GPIO_FUNC103_IN_SEL_M ((GPIO_FUNC103_IN_SEL_V)<<(GPIO_FUNC103_IN_SEL_S)) +#define GPIO_FUNC103_IN_SEL_V 0x3F +#define GPIO_FUNC103_IN_SEL_S 0 + +#define GPIO_FUNC104_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02d0) +/* GPIO_SIG104_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG104_IN_SEL (BIT(7)) +#define GPIO_SIG104_IN_SEL_M (BIT(7)) +#define GPIO_SIG104_IN_SEL_V 0x1 +#define GPIO_SIG104_IN_SEL_S 7 +/* GPIO_FUNC104_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC104_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC104_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC104_IN_INV_SEL_V 0x1 +#define GPIO_FUNC104_IN_INV_SEL_S 6 +/* GPIO_FUNC104_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC104_IN_SEL 0x0000003F +#define GPIO_FUNC104_IN_SEL_M ((GPIO_FUNC104_IN_SEL_V)<<(GPIO_FUNC104_IN_SEL_S)) +#define GPIO_FUNC104_IN_SEL_V 0x3F +#define GPIO_FUNC104_IN_SEL_S 0 + +#define GPIO_FUNC105_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02d4) +/* GPIO_SIG105_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG105_IN_SEL (BIT(7)) +#define GPIO_SIG105_IN_SEL_M (BIT(7)) +#define GPIO_SIG105_IN_SEL_V 0x1 +#define GPIO_SIG105_IN_SEL_S 7 +/* GPIO_FUNC105_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC105_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC105_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC105_IN_INV_SEL_V 0x1 +#define GPIO_FUNC105_IN_INV_SEL_S 6 +/* GPIO_FUNC105_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC105_IN_SEL 0x0000003F +#define GPIO_FUNC105_IN_SEL_M ((GPIO_FUNC105_IN_SEL_V)<<(GPIO_FUNC105_IN_SEL_S)) +#define GPIO_FUNC105_IN_SEL_V 0x3F +#define GPIO_FUNC105_IN_SEL_S 0 + +#define GPIO_FUNC106_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02d8) +/* GPIO_SIG106_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG106_IN_SEL (BIT(7)) +#define GPIO_SIG106_IN_SEL_M (BIT(7)) +#define GPIO_SIG106_IN_SEL_V 0x1 +#define GPIO_SIG106_IN_SEL_S 7 +/* GPIO_FUNC106_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC106_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC106_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC106_IN_INV_SEL_V 0x1 +#define GPIO_FUNC106_IN_INV_SEL_S 6 +/* GPIO_FUNC106_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC106_IN_SEL 0x0000003F +#define GPIO_FUNC106_IN_SEL_M ((GPIO_FUNC106_IN_SEL_V)<<(GPIO_FUNC106_IN_SEL_S)) +#define GPIO_FUNC106_IN_SEL_V 0x3F +#define GPIO_FUNC106_IN_SEL_S 0 + +#define GPIO_FUNC107_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02dc) +/* GPIO_SIG107_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG107_IN_SEL (BIT(7)) +#define GPIO_SIG107_IN_SEL_M (BIT(7)) +#define GPIO_SIG107_IN_SEL_V 0x1 +#define GPIO_SIG107_IN_SEL_S 7 +/* GPIO_FUNC107_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC107_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC107_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC107_IN_INV_SEL_V 0x1 +#define GPIO_FUNC107_IN_INV_SEL_S 6 +/* GPIO_FUNC107_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC107_IN_SEL 0x0000003F +#define GPIO_FUNC107_IN_SEL_M ((GPIO_FUNC107_IN_SEL_V)<<(GPIO_FUNC107_IN_SEL_S)) +#define GPIO_FUNC107_IN_SEL_V 0x3F +#define GPIO_FUNC107_IN_SEL_S 0 + +#define GPIO_FUNC108_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02e0) +/* GPIO_SIG108_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG108_IN_SEL (BIT(7)) +#define GPIO_SIG108_IN_SEL_M (BIT(7)) +#define GPIO_SIG108_IN_SEL_V 0x1 +#define GPIO_SIG108_IN_SEL_S 7 +/* GPIO_FUNC108_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC108_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC108_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC108_IN_INV_SEL_V 0x1 +#define GPIO_FUNC108_IN_INV_SEL_S 6 +/* GPIO_FUNC108_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC108_IN_SEL 0x0000003F +#define GPIO_FUNC108_IN_SEL_M ((GPIO_FUNC108_IN_SEL_V)<<(GPIO_FUNC108_IN_SEL_S)) +#define GPIO_FUNC108_IN_SEL_V 0x3F +#define GPIO_FUNC108_IN_SEL_S 0 + +#define GPIO_FUNC109_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02e4) +/* GPIO_SIG109_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG109_IN_SEL (BIT(7)) +#define GPIO_SIG109_IN_SEL_M (BIT(7)) +#define GPIO_SIG109_IN_SEL_V 0x1 +#define GPIO_SIG109_IN_SEL_S 7 +/* GPIO_FUNC109_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC109_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC109_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC109_IN_INV_SEL_V 0x1 +#define GPIO_FUNC109_IN_INV_SEL_S 6 +/* GPIO_FUNC109_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC109_IN_SEL 0x0000003F +#define GPIO_FUNC109_IN_SEL_M ((GPIO_FUNC109_IN_SEL_V)<<(GPIO_FUNC109_IN_SEL_S)) +#define GPIO_FUNC109_IN_SEL_V 0x3F +#define GPIO_FUNC109_IN_SEL_S 0 + +#define GPIO_FUNC110_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02e8) +/* GPIO_SIG110_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG110_IN_SEL (BIT(7)) +#define GPIO_SIG110_IN_SEL_M (BIT(7)) +#define GPIO_SIG110_IN_SEL_V 0x1 +#define GPIO_SIG110_IN_SEL_S 7 +/* GPIO_FUNC110_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC110_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC110_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC110_IN_INV_SEL_V 0x1 +#define GPIO_FUNC110_IN_INV_SEL_S 6 +/* GPIO_FUNC110_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC110_IN_SEL 0x0000003F +#define GPIO_FUNC110_IN_SEL_M ((GPIO_FUNC110_IN_SEL_V)<<(GPIO_FUNC110_IN_SEL_S)) +#define GPIO_FUNC110_IN_SEL_V 0x3F +#define GPIO_FUNC110_IN_SEL_S 0 + +#define GPIO_FUNC111_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02ec) +/* GPIO_SIG111_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG111_IN_SEL (BIT(7)) +#define GPIO_SIG111_IN_SEL_M (BIT(7)) +#define GPIO_SIG111_IN_SEL_V 0x1 +#define GPIO_SIG111_IN_SEL_S 7 +/* GPIO_FUNC111_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC111_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC111_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC111_IN_INV_SEL_V 0x1 +#define GPIO_FUNC111_IN_INV_SEL_S 6 +/* GPIO_FUNC111_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC111_IN_SEL 0x0000003F +#define GPIO_FUNC111_IN_SEL_M ((GPIO_FUNC111_IN_SEL_V)<<(GPIO_FUNC111_IN_SEL_S)) +#define GPIO_FUNC111_IN_SEL_V 0x3F +#define GPIO_FUNC111_IN_SEL_S 0 + +#define GPIO_FUNC112_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02f0) +/* GPIO_SIG112_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG112_IN_SEL (BIT(7)) +#define GPIO_SIG112_IN_SEL_M (BIT(7)) +#define GPIO_SIG112_IN_SEL_V 0x1 +#define GPIO_SIG112_IN_SEL_S 7 +/* GPIO_FUNC112_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC112_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC112_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC112_IN_INV_SEL_V 0x1 +#define GPIO_FUNC112_IN_INV_SEL_S 6 +/* GPIO_FUNC112_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC112_IN_SEL 0x0000003F +#define GPIO_FUNC112_IN_SEL_M ((GPIO_FUNC112_IN_SEL_V)<<(GPIO_FUNC112_IN_SEL_S)) +#define GPIO_FUNC112_IN_SEL_V 0x3F +#define GPIO_FUNC112_IN_SEL_S 0 + +#define GPIO_FUNC113_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02f4) +/* GPIO_SIG113_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG113_IN_SEL (BIT(7)) +#define GPIO_SIG113_IN_SEL_M (BIT(7)) +#define GPIO_SIG113_IN_SEL_V 0x1 +#define GPIO_SIG113_IN_SEL_S 7 +/* GPIO_FUNC113_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC113_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC113_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC113_IN_INV_SEL_V 0x1 +#define GPIO_FUNC113_IN_INV_SEL_S 6 +/* GPIO_FUNC113_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC113_IN_SEL 0x0000003F +#define GPIO_FUNC113_IN_SEL_M ((GPIO_FUNC113_IN_SEL_V)<<(GPIO_FUNC113_IN_SEL_S)) +#define GPIO_FUNC113_IN_SEL_V 0x3F +#define GPIO_FUNC113_IN_SEL_S 0 + +#define GPIO_FUNC114_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02f8) +/* GPIO_SIG114_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG114_IN_SEL (BIT(7)) +#define GPIO_SIG114_IN_SEL_M (BIT(7)) +#define GPIO_SIG114_IN_SEL_V 0x1 +#define GPIO_SIG114_IN_SEL_S 7 +/* GPIO_FUNC114_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC114_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC114_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC114_IN_INV_SEL_V 0x1 +#define GPIO_FUNC114_IN_INV_SEL_S 6 +/* GPIO_FUNC114_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC114_IN_SEL 0x0000003F +#define GPIO_FUNC114_IN_SEL_M ((GPIO_FUNC114_IN_SEL_V)<<(GPIO_FUNC114_IN_SEL_S)) +#define GPIO_FUNC114_IN_SEL_V 0x3F +#define GPIO_FUNC114_IN_SEL_S 0 + +#define GPIO_FUNC115_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02fc) +/* GPIO_SIG115_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG115_IN_SEL (BIT(7)) +#define GPIO_SIG115_IN_SEL_M (BIT(7)) +#define GPIO_SIG115_IN_SEL_V 0x1 +#define GPIO_SIG115_IN_SEL_S 7 +/* GPIO_FUNC115_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC115_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC115_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC115_IN_INV_SEL_V 0x1 +#define GPIO_FUNC115_IN_INV_SEL_S 6 +/* GPIO_FUNC115_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC115_IN_SEL 0x0000003F +#define GPIO_FUNC115_IN_SEL_M ((GPIO_FUNC115_IN_SEL_V)<<(GPIO_FUNC115_IN_SEL_S)) +#define GPIO_FUNC115_IN_SEL_V 0x3F +#define GPIO_FUNC115_IN_SEL_S 0 + +#define GPIO_FUNC116_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0300) +/* GPIO_SIG116_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG116_IN_SEL (BIT(7)) +#define GPIO_SIG116_IN_SEL_M (BIT(7)) +#define GPIO_SIG116_IN_SEL_V 0x1 +#define GPIO_SIG116_IN_SEL_S 7 +/* GPIO_FUNC116_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC116_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC116_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC116_IN_INV_SEL_V 0x1 +#define GPIO_FUNC116_IN_INV_SEL_S 6 +/* GPIO_FUNC116_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC116_IN_SEL 0x0000003F +#define GPIO_FUNC116_IN_SEL_M ((GPIO_FUNC116_IN_SEL_V)<<(GPIO_FUNC116_IN_SEL_S)) +#define GPIO_FUNC116_IN_SEL_V 0x3F +#define GPIO_FUNC116_IN_SEL_S 0 + +#define GPIO_FUNC117_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0304) +/* GPIO_SIG117_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG117_IN_SEL (BIT(7)) +#define GPIO_SIG117_IN_SEL_M (BIT(7)) +#define GPIO_SIG117_IN_SEL_V 0x1 +#define GPIO_SIG117_IN_SEL_S 7 +/* GPIO_FUNC117_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC117_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC117_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC117_IN_INV_SEL_V 0x1 +#define GPIO_FUNC117_IN_INV_SEL_S 6 +/* GPIO_FUNC117_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC117_IN_SEL 0x0000003F +#define GPIO_FUNC117_IN_SEL_M ((GPIO_FUNC117_IN_SEL_V)<<(GPIO_FUNC117_IN_SEL_S)) +#define GPIO_FUNC117_IN_SEL_V 0x3F +#define GPIO_FUNC117_IN_SEL_S 0 + +#define GPIO_FUNC118_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0308) +/* GPIO_SIG118_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG118_IN_SEL (BIT(7)) +#define GPIO_SIG118_IN_SEL_M (BIT(7)) +#define GPIO_SIG118_IN_SEL_V 0x1 +#define GPIO_SIG118_IN_SEL_S 7 +/* GPIO_FUNC118_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC118_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC118_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC118_IN_INV_SEL_V 0x1 +#define GPIO_FUNC118_IN_INV_SEL_S 6 +/* GPIO_FUNC118_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC118_IN_SEL 0x0000003F +#define GPIO_FUNC118_IN_SEL_M ((GPIO_FUNC118_IN_SEL_V)<<(GPIO_FUNC118_IN_SEL_S)) +#define GPIO_FUNC118_IN_SEL_V 0x3F +#define GPIO_FUNC118_IN_SEL_S 0 + +#define GPIO_FUNC119_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x030c) +/* GPIO_SIG119_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG119_IN_SEL (BIT(7)) +#define GPIO_SIG119_IN_SEL_M (BIT(7)) +#define GPIO_SIG119_IN_SEL_V 0x1 +#define GPIO_SIG119_IN_SEL_S 7 +/* GPIO_FUNC119_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC119_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC119_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC119_IN_INV_SEL_V 0x1 +#define GPIO_FUNC119_IN_INV_SEL_S 6 +/* GPIO_FUNC119_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC119_IN_SEL 0x0000003F +#define GPIO_FUNC119_IN_SEL_M ((GPIO_FUNC119_IN_SEL_V)<<(GPIO_FUNC119_IN_SEL_S)) +#define GPIO_FUNC119_IN_SEL_V 0x3F +#define GPIO_FUNC119_IN_SEL_S 0 + +#define GPIO_FUNC120_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0310) +/* GPIO_SIG120_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG120_IN_SEL (BIT(7)) +#define GPIO_SIG120_IN_SEL_M (BIT(7)) +#define GPIO_SIG120_IN_SEL_V 0x1 +#define GPIO_SIG120_IN_SEL_S 7 +/* GPIO_FUNC120_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC120_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC120_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC120_IN_INV_SEL_V 0x1 +#define GPIO_FUNC120_IN_INV_SEL_S 6 +/* GPIO_FUNC120_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC120_IN_SEL 0x0000003F +#define GPIO_FUNC120_IN_SEL_M ((GPIO_FUNC120_IN_SEL_V)<<(GPIO_FUNC120_IN_SEL_S)) +#define GPIO_FUNC120_IN_SEL_V 0x3F +#define GPIO_FUNC120_IN_SEL_S 0 + +#define GPIO_FUNC121_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0314) +/* GPIO_SIG121_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG121_IN_SEL (BIT(7)) +#define GPIO_SIG121_IN_SEL_M (BIT(7)) +#define GPIO_SIG121_IN_SEL_V 0x1 +#define GPIO_SIG121_IN_SEL_S 7 +/* GPIO_FUNC121_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC121_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC121_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC121_IN_INV_SEL_V 0x1 +#define GPIO_FUNC121_IN_INV_SEL_S 6 +/* GPIO_FUNC121_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC121_IN_SEL 0x0000003F +#define GPIO_FUNC121_IN_SEL_M ((GPIO_FUNC121_IN_SEL_V)<<(GPIO_FUNC121_IN_SEL_S)) +#define GPIO_FUNC121_IN_SEL_V 0x3F +#define GPIO_FUNC121_IN_SEL_S 0 + +#define GPIO_FUNC122_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0318) +/* GPIO_SIG122_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG122_IN_SEL (BIT(7)) +#define GPIO_SIG122_IN_SEL_M (BIT(7)) +#define GPIO_SIG122_IN_SEL_V 0x1 +#define GPIO_SIG122_IN_SEL_S 7 +/* GPIO_FUNC122_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC122_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC122_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC122_IN_INV_SEL_V 0x1 +#define GPIO_FUNC122_IN_INV_SEL_S 6 +/* GPIO_FUNC122_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC122_IN_SEL 0x0000003F +#define GPIO_FUNC122_IN_SEL_M ((GPIO_FUNC122_IN_SEL_V)<<(GPIO_FUNC122_IN_SEL_S)) +#define GPIO_FUNC122_IN_SEL_V 0x3F +#define GPIO_FUNC122_IN_SEL_S 0 + +#define GPIO_FUNC123_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x031c) +/* GPIO_SIG123_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG123_IN_SEL (BIT(7)) +#define GPIO_SIG123_IN_SEL_M (BIT(7)) +#define GPIO_SIG123_IN_SEL_V 0x1 +#define GPIO_SIG123_IN_SEL_S 7 +/* GPIO_FUNC123_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC123_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC123_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC123_IN_INV_SEL_V 0x1 +#define GPIO_FUNC123_IN_INV_SEL_S 6 +/* GPIO_FUNC123_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC123_IN_SEL 0x0000003F +#define GPIO_FUNC123_IN_SEL_M ((GPIO_FUNC123_IN_SEL_V)<<(GPIO_FUNC123_IN_SEL_S)) +#define GPIO_FUNC123_IN_SEL_V 0x3F +#define GPIO_FUNC123_IN_SEL_S 0 + +#define GPIO_FUNC124_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0320) +/* GPIO_SIG124_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG124_IN_SEL (BIT(7)) +#define GPIO_SIG124_IN_SEL_M (BIT(7)) +#define GPIO_SIG124_IN_SEL_V 0x1 +#define GPIO_SIG124_IN_SEL_S 7 +/* GPIO_FUNC124_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC124_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC124_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC124_IN_INV_SEL_V 0x1 +#define GPIO_FUNC124_IN_INV_SEL_S 6 +/* GPIO_FUNC124_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC124_IN_SEL 0x0000003F +#define GPIO_FUNC124_IN_SEL_M ((GPIO_FUNC124_IN_SEL_V)<<(GPIO_FUNC124_IN_SEL_S)) +#define GPIO_FUNC124_IN_SEL_V 0x3F +#define GPIO_FUNC124_IN_SEL_S 0 + +#define GPIO_FUNC125_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0324) +/* GPIO_SIG125_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG125_IN_SEL (BIT(7)) +#define GPIO_SIG125_IN_SEL_M (BIT(7)) +#define GPIO_SIG125_IN_SEL_V 0x1 +#define GPIO_SIG125_IN_SEL_S 7 +/* GPIO_FUNC125_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC125_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC125_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC125_IN_INV_SEL_V 0x1 +#define GPIO_FUNC125_IN_INV_SEL_S 6 +/* GPIO_FUNC125_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC125_IN_SEL 0x0000003F +#define GPIO_FUNC125_IN_SEL_M ((GPIO_FUNC125_IN_SEL_V)<<(GPIO_FUNC125_IN_SEL_S)) +#define GPIO_FUNC125_IN_SEL_V 0x3F +#define GPIO_FUNC125_IN_SEL_S 0 + +#define GPIO_FUNC126_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0328) +/* GPIO_SIG126_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG126_IN_SEL (BIT(7)) +#define GPIO_SIG126_IN_SEL_M (BIT(7)) +#define GPIO_SIG126_IN_SEL_V 0x1 +#define GPIO_SIG126_IN_SEL_S 7 +/* GPIO_FUNC126_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC126_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC126_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC126_IN_INV_SEL_V 0x1 +#define GPIO_FUNC126_IN_INV_SEL_S 6 +/* GPIO_FUNC126_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC126_IN_SEL 0x0000003F +#define GPIO_FUNC126_IN_SEL_M ((GPIO_FUNC126_IN_SEL_V)<<(GPIO_FUNC126_IN_SEL_S)) +#define GPIO_FUNC126_IN_SEL_V 0x3F +#define GPIO_FUNC126_IN_SEL_S 0 + +#define GPIO_FUNC127_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x032c) +/* GPIO_SIG127_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG127_IN_SEL (BIT(7)) +#define GPIO_SIG127_IN_SEL_M (BIT(7)) +#define GPIO_SIG127_IN_SEL_V 0x1 +#define GPIO_SIG127_IN_SEL_S 7 +/* GPIO_FUNC127_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC127_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC127_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC127_IN_INV_SEL_V 0x1 +#define GPIO_FUNC127_IN_INV_SEL_S 6 +/* GPIO_FUNC127_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC127_IN_SEL 0x0000003F +#define GPIO_FUNC127_IN_SEL_M ((GPIO_FUNC127_IN_SEL_V)<<(GPIO_FUNC127_IN_SEL_S)) +#define GPIO_FUNC127_IN_SEL_V 0x3F +#define GPIO_FUNC127_IN_SEL_S 0 + +#define GPIO_FUNC128_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0330) +/* GPIO_SIG128_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG128_IN_SEL (BIT(7)) +#define GPIO_SIG128_IN_SEL_M (BIT(7)) +#define GPIO_SIG128_IN_SEL_V 0x1 +#define GPIO_SIG128_IN_SEL_S 7 +/* GPIO_FUNC128_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC128_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC128_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC128_IN_INV_SEL_V 0x1 +#define GPIO_FUNC128_IN_INV_SEL_S 6 +/* GPIO_FUNC128_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC128_IN_SEL 0x0000003F +#define GPIO_FUNC128_IN_SEL_M ((GPIO_FUNC128_IN_SEL_V)<<(GPIO_FUNC128_IN_SEL_S)) +#define GPIO_FUNC128_IN_SEL_V 0x3F +#define GPIO_FUNC128_IN_SEL_S 0 + +#define GPIO_FUNC129_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0334) +/* GPIO_SIG129_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG129_IN_SEL (BIT(7)) +#define GPIO_SIG129_IN_SEL_M (BIT(7)) +#define GPIO_SIG129_IN_SEL_V 0x1 +#define GPIO_SIG129_IN_SEL_S 7 +/* GPIO_FUNC129_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC129_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC129_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC129_IN_INV_SEL_V 0x1 +#define GPIO_FUNC129_IN_INV_SEL_S 6 +/* GPIO_FUNC129_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC129_IN_SEL 0x0000003F +#define GPIO_FUNC129_IN_SEL_M ((GPIO_FUNC129_IN_SEL_V)<<(GPIO_FUNC129_IN_SEL_S)) +#define GPIO_FUNC129_IN_SEL_V 0x3F +#define GPIO_FUNC129_IN_SEL_S 0 + +#define GPIO_FUNC130_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0338) +/* GPIO_SIG130_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG130_IN_SEL (BIT(7)) +#define GPIO_SIG130_IN_SEL_M (BIT(7)) +#define GPIO_SIG130_IN_SEL_V 0x1 +#define GPIO_SIG130_IN_SEL_S 7 +/* GPIO_FUNC130_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC130_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC130_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC130_IN_INV_SEL_V 0x1 +#define GPIO_FUNC130_IN_INV_SEL_S 6 +/* GPIO_FUNC130_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC130_IN_SEL 0x0000003F +#define GPIO_FUNC130_IN_SEL_M ((GPIO_FUNC130_IN_SEL_V)<<(GPIO_FUNC130_IN_SEL_S)) +#define GPIO_FUNC130_IN_SEL_V 0x3F +#define GPIO_FUNC130_IN_SEL_S 0 + +#define GPIO_FUNC131_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x033c) +/* GPIO_SIG131_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG131_IN_SEL (BIT(7)) +#define GPIO_SIG131_IN_SEL_M (BIT(7)) +#define GPIO_SIG131_IN_SEL_V 0x1 +#define GPIO_SIG131_IN_SEL_S 7 +/* GPIO_FUNC131_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC131_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC131_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC131_IN_INV_SEL_V 0x1 +#define GPIO_FUNC131_IN_INV_SEL_S 6 +/* GPIO_FUNC131_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC131_IN_SEL 0x0000003F +#define GPIO_FUNC131_IN_SEL_M ((GPIO_FUNC131_IN_SEL_V)<<(GPIO_FUNC131_IN_SEL_S)) +#define GPIO_FUNC131_IN_SEL_V 0x3F +#define GPIO_FUNC131_IN_SEL_S 0 + +#define GPIO_FUNC132_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0340) +/* GPIO_SIG132_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG132_IN_SEL (BIT(7)) +#define GPIO_SIG132_IN_SEL_M (BIT(7)) +#define GPIO_SIG132_IN_SEL_V 0x1 +#define GPIO_SIG132_IN_SEL_S 7 +/* GPIO_FUNC132_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC132_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC132_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC132_IN_INV_SEL_V 0x1 +#define GPIO_FUNC132_IN_INV_SEL_S 6 +/* GPIO_FUNC132_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC132_IN_SEL 0x0000003F +#define GPIO_FUNC132_IN_SEL_M ((GPIO_FUNC132_IN_SEL_V)<<(GPIO_FUNC132_IN_SEL_S)) +#define GPIO_FUNC132_IN_SEL_V 0x3F +#define GPIO_FUNC132_IN_SEL_S 0 + +#define GPIO_FUNC133_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0344) +/* GPIO_SIG133_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG133_IN_SEL (BIT(7)) +#define GPIO_SIG133_IN_SEL_M (BIT(7)) +#define GPIO_SIG133_IN_SEL_V 0x1 +#define GPIO_SIG133_IN_SEL_S 7 +/* GPIO_FUNC133_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC133_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC133_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC133_IN_INV_SEL_V 0x1 +#define GPIO_FUNC133_IN_INV_SEL_S 6 +/* GPIO_FUNC133_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC133_IN_SEL 0x0000003F +#define GPIO_FUNC133_IN_SEL_M ((GPIO_FUNC133_IN_SEL_V)<<(GPIO_FUNC133_IN_SEL_S)) +#define GPIO_FUNC133_IN_SEL_V 0x3F +#define GPIO_FUNC133_IN_SEL_S 0 + +#define GPIO_FUNC134_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0348) +/* GPIO_SIG134_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG134_IN_SEL (BIT(7)) +#define GPIO_SIG134_IN_SEL_M (BIT(7)) +#define GPIO_SIG134_IN_SEL_V 0x1 +#define GPIO_SIG134_IN_SEL_S 7 +/* GPIO_FUNC134_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC134_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC134_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC134_IN_INV_SEL_V 0x1 +#define GPIO_FUNC134_IN_INV_SEL_S 6 +/* GPIO_FUNC134_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC134_IN_SEL 0x0000003F +#define GPIO_FUNC134_IN_SEL_M ((GPIO_FUNC134_IN_SEL_V)<<(GPIO_FUNC134_IN_SEL_S)) +#define GPIO_FUNC134_IN_SEL_V 0x3F +#define GPIO_FUNC134_IN_SEL_S 0 + +#define GPIO_FUNC135_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x034c) +/* GPIO_SIG135_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG135_IN_SEL (BIT(7)) +#define GPIO_SIG135_IN_SEL_M (BIT(7)) +#define GPIO_SIG135_IN_SEL_V 0x1 +#define GPIO_SIG135_IN_SEL_S 7 +/* GPIO_FUNC135_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC135_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC135_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC135_IN_INV_SEL_V 0x1 +#define GPIO_FUNC135_IN_INV_SEL_S 6 +/* GPIO_FUNC135_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC135_IN_SEL 0x0000003F +#define GPIO_FUNC135_IN_SEL_M ((GPIO_FUNC135_IN_SEL_V)<<(GPIO_FUNC135_IN_SEL_S)) +#define GPIO_FUNC135_IN_SEL_V 0x3F +#define GPIO_FUNC135_IN_SEL_S 0 + +#define GPIO_FUNC136_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0350) +/* GPIO_SIG136_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG136_IN_SEL (BIT(7)) +#define GPIO_SIG136_IN_SEL_M (BIT(7)) +#define GPIO_SIG136_IN_SEL_V 0x1 +#define GPIO_SIG136_IN_SEL_S 7 +/* GPIO_FUNC136_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC136_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC136_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC136_IN_INV_SEL_V 0x1 +#define GPIO_FUNC136_IN_INV_SEL_S 6 +/* GPIO_FUNC136_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC136_IN_SEL 0x0000003F +#define GPIO_FUNC136_IN_SEL_M ((GPIO_FUNC136_IN_SEL_V)<<(GPIO_FUNC136_IN_SEL_S)) +#define GPIO_FUNC136_IN_SEL_V 0x3F +#define GPIO_FUNC136_IN_SEL_S 0 + +#define GPIO_FUNC137_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0354) +/* GPIO_SIG137_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG137_IN_SEL (BIT(7)) +#define GPIO_SIG137_IN_SEL_M (BIT(7)) +#define GPIO_SIG137_IN_SEL_V 0x1 +#define GPIO_SIG137_IN_SEL_S 7 +/* GPIO_FUNC137_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC137_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC137_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC137_IN_INV_SEL_V 0x1 +#define GPIO_FUNC137_IN_INV_SEL_S 6 +/* GPIO_FUNC137_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC137_IN_SEL 0x0000003F +#define GPIO_FUNC137_IN_SEL_M ((GPIO_FUNC137_IN_SEL_V)<<(GPIO_FUNC137_IN_SEL_S)) +#define GPIO_FUNC137_IN_SEL_V 0x3F +#define GPIO_FUNC137_IN_SEL_S 0 + +#define GPIO_FUNC138_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0358) +/* GPIO_SIG138_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG138_IN_SEL (BIT(7)) +#define GPIO_SIG138_IN_SEL_M (BIT(7)) +#define GPIO_SIG138_IN_SEL_V 0x1 +#define GPIO_SIG138_IN_SEL_S 7 +/* GPIO_FUNC138_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC138_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC138_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC138_IN_INV_SEL_V 0x1 +#define GPIO_FUNC138_IN_INV_SEL_S 6 +/* GPIO_FUNC138_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC138_IN_SEL 0x0000003F +#define GPIO_FUNC138_IN_SEL_M ((GPIO_FUNC138_IN_SEL_V)<<(GPIO_FUNC138_IN_SEL_S)) +#define GPIO_FUNC138_IN_SEL_V 0x3F +#define GPIO_FUNC138_IN_SEL_S 0 + +#define GPIO_FUNC139_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x035c) +/* GPIO_SIG139_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG139_IN_SEL (BIT(7)) +#define GPIO_SIG139_IN_SEL_M (BIT(7)) +#define GPIO_SIG139_IN_SEL_V 0x1 +#define GPIO_SIG139_IN_SEL_S 7 +/* GPIO_FUNC139_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC139_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC139_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC139_IN_INV_SEL_V 0x1 +#define GPIO_FUNC139_IN_INV_SEL_S 6 +/* GPIO_FUNC139_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC139_IN_SEL 0x0000003F +#define GPIO_FUNC139_IN_SEL_M ((GPIO_FUNC139_IN_SEL_V)<<(GPIO_FUNC139_IN_SEL_S)) +#define GPIO_FUNC139_IN_SEL_V 0x3F +#define GPIO_FUNC139_IN_SEL_S 0 + +#define GPIO_FUNC140_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0360) +/* GPIO_SIG140_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG140_IN_SEL (BIT(7)) +#define GPIO_SIG140_IN_SEL_M (BIT(7)) +#define GPIO_SIG140_IN_SEL_V 0x1 +#define GPIO_SIG140_IN_SEL_S 7 +/* GPIO_FUNC140_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC140_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC140_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC140_IN_INV_SEL_V 0x1 +#define GPIO_FUNC140_IN_INV_SEL_S 6 +/* GPIO_FUNC140_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC140_IN_SEL 0x0000003F +#define GPIO_FUNC140_IN_SEL_M ((GPIO_FUNC140_IN_SEL_V)<<(GPIO_FUNC140_IN_SEL_S)) +#define GPIO_FUNC140_IN_SEL_V 0x3F +#define GPIO_FUNC140_IN_SEL_S 0 + +#define GPIO_FUNC141_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0364) +/* GPIO_SIG141_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG141_IN_SEL (BIT(7)) +#define GPIO_SIG141_IN_SEL_M (BIT(7)) +#define GPIO_SIG141_IN_SEL_V 0x1 +#define GPIO_SIG141_IN_SEL_S 7 +/* GPIO_FUNC141_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC141_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC141_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC141_IN_INV_SEL_V 0x1 +#define GPIO_FUNC141_IN_INV_SEL_S 6 +/* GPIO_FUNC141_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC141_IN_SEL 0x0000003F +#define GPIO_FUNC141_IN_SEL_M ((GPIO_FUNC141_IN_SEL_V)<<(GPIO_FUNC141_IN_SEL_S)) +#define GPIO_FUNC141_IN_SEL_V 0x3F +#define GPIO_FUNC141_IN_SEL_S 0 + +#define GPIO_FUNC142_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0368) +/* GPIO_SIG142_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG142_IN_SEL (BIT(7)) +#define GPIO_SIG142_IN_SEL_M (BIT(7)) +#define GPIO_SIG142_IN_SEL_V 0x1 +#define GPIO_SIG142_IN_SEL_S 7 +/* GPIO_FUNC142_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC142_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC142_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC142_IN_INV_SEL_V 0x1 +#define GPIO_FUNC142_IN_INV_SEL_S 6 +/* GPIO_FUNC142_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC142_IN_SEL 0x0000003F +#define GPIO_FUNC142_IN_SEL_M ((GPIO_FUNC142_IN_SEL_V)<<(GPIO_FUNC142_IN_SEL_S)) +#define GPIO_FUNC142_IN_SEL_V 0x3F +#define GPIO_FUNC142_IN_SEL_S 0 + +#define GPIO_FUNC143_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x036c) +/* GPIO_SIG143_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG143_IN_SEL (BIT(7)) +#define GPIO_SIG143_IN_SEL_M (BIT(7)) +#define GPIO_SIG143_IN_SEL_V 0x1 +#define GPIO_SIG143_IN_SEL_S 7 +/* GPIO_FUNC143_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC143_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC143_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC143_IN_INV_SEL_V 0x1 +#define GPIO_FUNC143_IN_INV_SEL_S 6 +/* GPIO_FUNC143_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC143_IN_SEL 0x0000003F +#define GPIO_FUNC143_IN_SEL_M ((GPIO_FUNC143_IN_SEL_V)<<(GPIO_FUNC143_IN_SEL_S)) +#define GPIO_FUNC143_IN_SEL_V 0x3F +#define GPIO_FUNC143_IN_SEL_S 0 + +#define GPIO_FUNC144_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0370) +/* GPIO_SIG144_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG144_IN_SEL (BIT(7)) +#define GPIO_SIG144_IN_SEL_M (BIT(7)) +#define GPIO_SIG144_IN_SEL_V 0x1 +#define GPIO_SIG144_IN_SEL_S 7 +/* GPIO_FUNC144_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC144_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC144_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC144_IN_INV_SEL_V 0x1 +#define GPIO_FUNC144_IN_INV_SEL_S 6 +/* GPIO_FUNC144_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC144_IN_SEL 0x0000003F +#define GPIO_FUNC144_IN_SEL_M ((GPIO_FUNC144_IN_SEL_V)<<(GPIO_FUNC144_IN_SEL_S)) +#define GPIO_FUNC144_IN_SEL_V 0x3F +#define GPIO_FUNC144_IN_SEL_S 0 + +#define GPIO_FUNC145_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0374) +/* GPIO_SIG145_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG145_IN_SEL (BIT(7)) +#define GPIO_SIG145_IN_SEL_M (BIT(7)) +#define GPIO_SIG145_IN_SEL_V 0x1 +#define GPIO_SIG145_IN_SEL_S 7 +/* GPIO_FUNC145_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC145_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC145_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC145_IN_INV_SEL_V 0x1 +#define GPIO_FUNC145_IN_INV_SEL_S 6 +/* GPIO_FUNC145_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC145_IN_SEL 0x0000003F +#define GPIO_FUNC145_IN_SEL_M ((GPIO_FUNC145_IN_SEL_V)<<(GPIO_FUNC145_IN_SEL_S)) +#define GPIO_FUNC145_IN_SEL_V 0x3F +#define GPIO_FUNC145_IN_SEL_S 0 + +#define GPIO_FUNC146_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0378) +/* GPIO_SIG146_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG146_IN_SEL (BIT(7)) +#define GPIO_SIG146_IN_SEL_M (BIT(7)) +#define GPIO_SIG146_IN_SEL_V 0x1 +#define GPIO_SIG146_IN_SEL_S 7 +/* GPIO_FUNC146_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC146_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC146_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC146_IN_INV_SEL_V 0x1 +#define GPIO_FUNC146_IN_INV_SEL_S 6 +/* GPIO_FUNC146_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC146_IN_SEL 0x0000003F +#define GPIO_FUNC146_IN_SEL_M ((GPIO_FUNC146_IN_SEL_V)<<(GPIO_FUNC146_IN_SEL_S)) +#define GPIO_FUNC146_IN_SEL_V 0x3F +#define GPIO_FUNC146_IN_SEL_S 0 + +#define GPIO_FUNC147_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x037c) +/* GPIO_SIG147_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG147_IN_SEL (BIT(7)) +#define GPIO_SIG147_IN_SEL_M (BIT(7)) +#define GPIO_SIG147_IN_SEL_V 0x1 +#define GPIO_SIG147_IN_SEL_S 7 +/* GPIO_FUNC147_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC147_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC147_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC147_IN_INV_SEL_V 0x1 +#define GPIO_FUNC147_IN_INV_SEL_S 6 +/* GPIO_FUNC147_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC147_IN_SEL 0x0000003F +#define GPIO_FUNC147_IN_SEL_M ((GPIO_FUNC147_IN_SEL_V)<<(GPIO_FUNC147_IN_SEL_S)) +#define GPIO_FUNC147_IN_SEL_V 0x3F +#define GPIO_FUNC147_IN_SEL_S 0 + +#define GPIO_FUNC148_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0380) +/* GPIO_SIG148_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG148_IN_SEL (BIT(7)) +#define GPIO_SIG148_IN_SEL_M (BIT(7)) +#define GPIO_SIG148_IN_SEL_V 0x1 +#define GPIO_SIG148_IN_SEL_S 7 +/* GPIO_FUNC148_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC148_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC148_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC148_IN_INV_SEL_V 0x1 +#define GPIO_FUNC148_IN_INV_SEL_S 6 +/* GPIO_FUNC148_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC148_IN_SEL 0x0000003F +#define GPIO_FUNC148_IN_SEL_M ((GPIO_FUNC148_IN_SEL_V)<<(GPIO_FUNC148_IN_SEL_S)) +#define GPIO_FUNC148_IN_SEL_V 0x3F +#define GPIO_FUNC148_IN_SEL_S 0 + +#define GPIO_FUNC149_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0384) +/* GPIO_SIG149_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG149_IN_SEL (BIT(7)) +#define GPIO_SIG149_IN_SEL_M (BIT(7)) +#define GPIO_SIG149_IN_SEL_V 0x1 +#define GPIO_SIG149_IN_SEL_S 7 +/* GPIO_FUNC149_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC149_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC149_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC149_IN_INV_SEL_V 0x1 +#define GPIO_FUNC149_IN_INV_SEL_S 6 +/* GPIO_FUNC149_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC149_IN_SEL 0x0000003F +#define GPIO_FUNC149_IN_SEL_M ((GPIO_FUNC149_IN_SEL_V)<<(GPIO_FUNC149_IN_SEL_S)) +#define GPIO_FUNC149_IN_SEL_V 0x3F +#define GPIO_FUNC149_IN_SEL_S 0 + +#define GPIO_FUNC150_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0388) +/* GPIO_SIG150_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG150_IN_SEL (BIT(7)) +#define GPIO_SIG150_IN_SEL_M (BIT(7)) +#define GPIO_SIG150_IN_SEL_V 0x1 +#define GPIO_SIG150_IN_SEL_S 7 +/* GPIO_FUNC150_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC150_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC150_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC150_IN_INV_SEL_V 0x1 +#define GPIO_FUNC150_IN_INV_SEL_S 6 +/* GPIO_FUNC150_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC150_IN_SEL 0x0000003F +#define GPIO_FUNC150_IN_SEL_M ((GPIO_FUNC150_IN_SEL_V)<<(GPIO_FUNC150_IN_SEL_S)) +#define GPIO_FUNC150_IN_SEL_V 0x3F +#define GPIO_FUNC150_IN_SEL_S 0 + +#define GPIO_FUNC151_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x038c) +/* GPIO_SIG151_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG151_IN_SEL (BIT(7)) +#define GPIO_SIG151_IN_SEL_M (BIT(7)) +#define GPIO_SIG151_IN_SEL_V 0x1 +#define GPIO_SIG151_IN_SEL_S 7 +/* GPIO_FUNC151_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC151_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC151_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC151_IN_INV_SEL_V 0x1 +#define GPIO_FUNC151_IN_INV_SEL_S 6 +/* GPIO_FUNC151_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC151_IN_SEL 0x0000003F +#define GPIO_FUNC151_IN_SEL_M ((GPIO_FUNC151_IN_SEL_V)<<(GPIO_FUNC151_IN_SEL_S)) +#define GPIO_FUNC151_IN_SEL_V 0x3F +#define GPIO_FUNC151_IN_SEL_S 0 + +#define GPIO_FUNC152_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0390) +/* GPIO_SIG152_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG152_IN_SEL (BIT(7)) +#define GPIO_SIG152_IN_SEL_M (BIT(7)) +#define GPIO_SIG152_IN_SEL_V 0x1 +#define GPIO_SIG152_IN_SEL_S 7 +/* GPIO_FUNC152_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC152_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC152_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC152_IN_INV_SEL_V 0x1 +#define GPIO_FUNC152_IN_INV_SEL_S 6 +/* GPIO_FUNC152_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC152_IN_SEL 0x0000003F +#define GPIO_FUNC152_IN_SEL_M ((GPIO_FUNC152_IN_SEL_V)<<(GPIO_FUNC152_IN_SEL_S)) +#define GPIO_FUNC152_IN_SEL_V 0x3F +#define GPIO_FUNC152_IN_SEL_S 0 + +#define GPIO_FUNC153_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0394) +/* GPIO_SIG153_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG153_IN_SEL (BIT(7)) +#define GPIO_SIG153_IN_SEL_M (BIT(7)) +#define GPIO_SIG153_IN_SEL_V 0x1 +#define GPIO_SIG153_IN_SEL_S 7 +/* GPIO_FUNC153_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC153_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC153_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC153_IN_INV_SEL_V 0x1 +#define GPIO_FUNC153_IN_INV_SEL_S 6 +/* GPIO_FUNC153_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC153_IN_SEL 0x0000003F +#define GPIO_FUNC153_IN_SEL_M ((GPIO_FUNC153_IN_SEL_V)<<(GPIO_FUNC153_IN_SEL_S)) +#define GPIO_FUNC153_IN_SEL_V 0x3F +#define GPIO_FUNC153_IN_SEL_S 0 + +#define GPIO_FUNC154_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0398) +/* GPIO_SIG154_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG154_IN_SEL (BIT(7)) +#define GPIO_SIG154_IN_SEL_M (BIT(7)) +#define GPIO_SIG154_IN_SEL_V 0x1 +#define GPIO_SIG154_IN_SEL_S 7 +/* GPIO_FUNC154_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC154_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC154_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC154_IN_INV_SEL_V 0x1 +#define GPIO_FUNC154_IN_INV_SEL_S 6 +/* GPIO_FUNC154_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC154_IN_SEL 0x0000003F +#define GPIO_FUNC154_IN_SEL_M ((GPIO_FUNC154_IN_SEL_V)<<(GPIO_FUNC154_IN_SEL_S)) +#define GPIO_FUNC154_IN_SEL_V 0x3F +#define GPIO_FUNC154_IN_SEL_S 0 + +#define GPIO_FUNC155_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x039c) +/* GPIO_SIG155_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG155_IN_SEL (BIT(7)) +#define GPIO_SIG155_IN_SEL_M (BIT(7)) +#define GPIO_SIG155_IN_SEL_V 0x1 +#define GPIO_SIG155_IN_SEL_S 7 +/* GPIO_FUNC155_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC155_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC155_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC155_IN_INV_SEL_V 0x1 +#define GPIO_FUNC155_IN_INV_SEL_S 6 +/* GPIO_FUNC155_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC155_IN_SEL 0x0000003F +#define GPIO_FUNC155_IN_SEL_M ((GPIO_FUNC155_IN_SEL_V)<<(GPIO_FUNC155_IN_SEL_S)) +#define GPIO_FUNC155_IN_SEL_V 0x3F +#define GPIO_FUNC155_IN_SEL_S 0 + +#define GPIO_FUNC156_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03a0) +/* GPIO_SIG156_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG156_IN_SEL (BIT(7)) +#define GPIO_SIG156_IN_SEL_M (BIT(7)) +#define GPIO_SIG156_IN_SEL_V 0x1 +#define GPIO_SIG156_IN_SEL_S 7 +/* GPIO_FUNC156_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC156_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC156_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC156_IN_INV_SEL_V 0x1 +#define GPIO_FUNC156_IN_INV_SEL_S 6 +/* GPIO_FUNC156_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC156_IN_SEL 0x0000003F +#define GPIO_FUNC156_IN_SEL_M ((GPIO_FUNC156_IN_SEL_V)<<(GPIO_FUNC156_IN_SEL_S)) +#define GPIO_FUNC156_IN_SEL_V 0x3F +#define GPIO_FUNC156_IN_SEL_S 0 + +#define GPIO_FUNC157_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03a4) +/* GPIO_SIG157_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG157_IN_SEL (BIT(7)) +#define GPIO_SIG157_IN_SEL_M (BIT(7)) +#define GPIO_SIG157_IN_SEL_V 0x1 +#define GPIO_SIG157_IN_SEL_S 7 +/* GPIO_FUNC157_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC157_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC157_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC157_IN_INV_SEL_V 0x1 +#define GPIO_FUNC157_IN_INV_SEL_S 6 +/* GPIO_FUNC157_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC157_IN_SEL 0x0000003F +#define GPIO_FUNC157_IN_SEL_M ((GPIO_FUNC157_IN_SEL_V)<<(GPIO_FUNC157_IN_SEL_S)) +#define GPIO_FUNC157_IN_SEL_V 0x3F +#define GPIO_FUNC157_IN_SEL_S 0 + +#define GPIO_FUNC158_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03a8) +/* GPIO_SIG158_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG158_IN_SEL (BIT(7)) +#define GPIO_SIG158_IN_SEL_M (BIT(7)) +#define GPIO_SIG158_IN_SEL_V 0x1 +#define GPIO_SIG158_IN_SEL_S 7 +/* GPIO_FUNC158_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC158_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC158_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC158_IN_INV_SEL_V 0x1 +#define GPIO_FUNC158_IN_INV_SEL_S 6 +/* GPIO_FUNC158_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC158_IN_SEL 0x0000003F +#define GPIO_FUNC158_IN_SEL_M ((GPIO_FUNC158_IN_SEL_V)<<(GPIO_FUNC158_IN_SEL_S)) +#define GPIO_FUNC158_IN_SEL_V 0x3F +#define GPIO_FUNC158_IN_SEL_S 0 + +#define GPIO_FUNC159_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03ac) +/* GPIO_SIG159_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG159_IN_SEL (BIT(7)) +#define GPIO_SIG159_IN_SEL_M (BIT(7)) +#define GPIO_SIG159_IN_SEL_V 0x1 +#define GPIO_SIG159_IN_SEL_S 7 +/* GPIO_FUNC159_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC159_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC159_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC159_IN_INV_SEL_V 0x1 +#define GPIO_FUNC159_IN_INV_SEL_S 6 +/* GPIO_FUNC159_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC159_IN_SEL 0x0000003F +#define GPIO_FUNC159_IN_SEL_M ((GPIO_FUNC159_IN_SEL_V)<<(GPIO_FUNC159_IN_SEL_S)) +#define GPIO_FUNC159_IN_SEL_V 0x3F +#define GPIO_FUNC159_IN_SEL_S 0 + +#define GPIO_FUNC160_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03b0) +/* GPIO_SIG160_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG160_IN_SEL (BIT(7)) +#define GPIO_SIG160_IN_SEL_M (BIT(7)) +#define GPIO_SIG160_IN_SEL_V 0x1 +#define GPIO_SIG160_IN_SEL_S 7 +/* GPIO_FUNC160_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC160_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC160_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC160_IN_INV_SEL_V 0x1 +#define GPIO_FUNC160_IN_INV_SEL_S 6 +/* GPIO_FUNC160_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC160_IN_SEL 0x0000003F +#define GPIO_FUNC160_IN_SEL_M ((GPIO_FUNC160_IN_SEL_V)<<(GPIO_FUNC160_IN_SEL_S)) +#define GPIO_FUNC160_IN_SEL_V 0x3F +#define GPIO_FUNC160_IN_SEL_S 0 + +#define GPIO_FUNC161_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03b4) +/* GPIO_SIG161_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG161_IN_SEL (BIT(7)) +#define GPIO_SIG161_IN_SEL_M (BIT(7)) +#define GPIO_SIG161_IN_SEL_V 0x1 +#define GPIO_SIG161_IN_SEL_S 7 +/* GPIO_FUNC161_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC161_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC161_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC161_IN_INV_SEL_V 0x1 +#define GPIO_FUNC161_IN_INV_SEL_S 6 +/* GPIO_FUNC161_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC161_IN_SEL 0x0000003F +#define GPIO_FUNC161_IN_SEL_M ((GPIO_FUNC161_IN_SEL_V)<<(GPIO_FUNC161_IN_SEL_S)) +#define GPIO_FUNC161_IN_SEL_V 0x3F +#define GPIO_FUNC161_IN_SEL_S 0 + +#define GPIO_FUNC162_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03b8) +/* GPIO_SIG162_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG162_IN_SEL (BIT(7)) +#define GPIO_SIG162_IN_SEL_M (BIT(7)) +#define GPIO_SIG162_IN_SEL_V 0x1 +#define GPIO_SIG162_IN_SEL_S 7 +/* GPIO_FUNC162_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC162_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC162_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC162_IN_INV_SEL_V 0x1 +#define GPIO_FUNC162_IN_INV_SEL_S 6 +/* GPIO_FUNC162_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC162_IN_SEL 0x0000003F +#define GPIO_FUNC162_IN_SEL_M ((GPIO_FUNC162_IN_SEL_V)<<(GPIO_FUNC162_IN_SEL_S)) +#define GPIO_FUNC162_IN_SEL_V 0x3F +#define GPIO_FUNC162_IN_SEL_S 0 + +#define GPIO_FUNC163_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03bc) +/* GPIO_SIG163_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG163_IN_SEL (BIT(7)) +#define GPIO_SIG163_IN_SEL_M (BIT(7)) +#define GPIO_SIG163_IN_SEL_V 0x1 +#define GPIO_SIG163_IN_SEL_S 7 +/* GPIO_FUNC163_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC163_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC163_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC163_IN_INV_SEL_V 0x1 +#define GPIO_FUNC163_IN_INV_SEL_S 6 +/* GPIO_FUNC163_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC163_IN_SEL 0x0000003F +#define GPIO_FUNC163_IN_SEL_M ((GPIO_FUNC163_IN_SEL_V)<<(GPIO_FUNC163_IN_SEL_S)) +#define GPIO_FUNC163_IN_SEL_V 0x3F +#define GPIO_FUNC163_IN_SEL_S 0 + +#define GPIO_FUNC164_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03c0) +/* GPIO_SIG164_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG164_IN_SEL (BIT(7)) +#define GPIO_SIG164_IN_SEL_M (BIT(7)) +#define GPIO_SIG164_IN_SEL_V 0x1 +#define GPIO_SIG164_IN_SEL_S 7 +/* GPIO_FUNC164_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC164_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC164_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC164_IN_INV_SEL_V 0x1 +#define GPIO_FUNC164_IN_INV_SEL_S 6 +/* GPIO_FUNC164_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC164_IN_SEL 0x0000003F +#define GPIO_FUNC164_IN_SEL_M ((GPIO_FUNC164_IN_SEL_V)<<(GPIO_FUNC164_IN_SEL_S)) +#define GPIO_FUNC164_IN_SEL_V 0x3F +#define GPIO_FUNC164_IN_SEL_S 0 + +#define GPIO_FUNC165_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03c4) +/* GPIO_SIG165_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG165_IN_SEL (BIT(7)) +#define GPIO_SIG165_IN_SEL_M (BIT(7)) +#define GPIO_SIG165_IN_SEL_V 0x1 +#define GPIO_SIG165_IN_SEL_S 7 +/* GPIO_FUNC165_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC165_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC165_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC165_IN_INV_SEL_V 0x1 +#define GPIO_FUNC165_IN_INV_SEL_S 6 +/* GPIO_FUNC165_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC165_IN_SEL 0x0000003F +#define GPIO_FUNC165_IN_SEL_M ((GPIO_FUNC165_IN_SEL_V)<<(GPIO_FUNC165_IN_SEL_S)) +#define GPIO_FUNC165_IN_SEL_V 0x3F +#define GPIO_FUNC165_IN_SEL_S 0 + +#define GPIO_FUNC166_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03c8) +/* GPIO_SIG166_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG166_IN_SEL (BIT(7)) +#define GPIO_SIG166_IN_SEL_M (BIT(7)) +#define GPIO_SIG166_IN_SEL_V 0x1 +#define GPIO_SIG166_IN_SEL_S 7 +/* GPIO_FUNC166_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC166_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC166_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC166_IN_INV_SEL_V 0x1 +#define GPIO_FUNC166_IN_INV_SEL_S 6 +/* GPIO_FUNC166_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC166_IN_SEL 0x0000003F +#define GPIO_FUNC166_IN_SEL_M ((GPIO_FUNC166_IN_SEL_V)<<(GPIO_FUNC166_IN_SEL_S)) +#define GPIO_FUNC166_IN_SEL_V 0x3F +#define GPIO_FUNC166_IN_SEL_S 0 + +#define GPIO_FUNC167_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03cc) +/* GPIO_SIG167_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG167_IN_SEL (BIT(7)) +#define GPIO_SIG167_IN_SEL_M (BIT(7)) +#define GPIO_SIG167_IN_SEL_V 0x1 +#define GPIO_SIG167_IN_SEL_S 7 +/* GPIO_FUNC167_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC167_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC167_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC167_IN_INV_SEL_V 0x1 +#define GPIO_FUNC167_IN_INV_SEL_S 6 +/* GPIO_FUNC167_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC167_IN_SEL 0x0000003F +#define GPIO_FUNC167_IN_SEL_M ((GPIO_FUNC167_IN_SEL_V)<<(GPIO_FUNC167_IN_SEL_S)) +#define GPIO_FUNC167_IN_SEL_V 0x3F +#define GPIO_FUNC167_IN_SEL_S 0 + +#define GPIO_FUNC168_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03d0) +/* GPIO_SIG168_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG168_IN_SEL (BIT(7)) +#define GPIO_SIG168_IN_SEL_M (BIT(7)) +#define GPIO_SIG168_IN_SEL_V 0x1 +#define GPIO_SIG168_IN_SEL_S 7 +/* GPIO_FUNC168_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC168_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC168_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC168_IN_INV_SEL_V 0x1 +#define GPIO_FUNC168_IN_INV_SEL_S 6 +/* GPIO_FUNC168_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC168_IN_SEL 0x0000003F +#define GPIO_FUNC168_IN_SEL_M ((GPIO_FUNC168_IN_SEL_V)<<(GPIO_FUNC168_IN_SEL_S)) +#define GPIO_FUNC168_IN_SEL_V 0x3F +#define GPIO_FUNC168_IN_SEL_S 0 + +#define GPIO_FUNC169_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03d4) +/* GPIO_SIG169_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG169_IN_SEL (BIT(7)) +#define GPIO_SIG169_IN_SEL_M (BIT(7)) +#define GPIO_SIG169_IN_SEL_V 0x1 +#define GPIO_SIG169_IN_SEL_S 7 +/* GPIO_FUNC169_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC169_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC169_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC169_IN_INV_SEL_V 0x1 +#define GPIO_FUNC169_IN_INV_SEL_S 6 +/* GPIO_FUNC169_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC169_IN_SEL 0x0000003F +#define GPIO_FUNC169_IN_SEL_M ((GPIO_FUNC169_IN_SEL_V)<<(GPIO_FUNC169_IN_SEL_S)) +#define GPIO_FUNC169_IN_SEL_V 0x3F +#define GPIO_FUNC169_IN_SEL_S 0 + +#define GPIO_FUNC170_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03d8) +/* GPIO_SIG170_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG170_IN_SEL (BIT(7)) +#define GPIO_SIG170_IN_SEL_M (BIT(7)) +#define GPIO_SIG170_IN_SEL_V 0x1 +#define GPIO_SIG170_IN_SEL_S 7 +/* GPIO_FUNC170_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC170_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC170_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC170_IN_INV_SEL_V 0x1 +#define GPIO_FUNC170_IN_INV_SEL_S 6 +/* GPIO_FUNC170_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC170_IN_SEL 0x0000003F +#define GPIO_FUNC170_IN_SEL_M ((GPIO_FUNC170_IN_SEL_V)<<(GPIO_FUNC170_IN_SEL_S)) +#define GPIO_FUNC170_IN_SEL_V 0x3F +#define GPIO_FUNC170_IN_SEL_S 0 + +#define GPIO_FUNC171_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03dc) +/* GPIO_SIG171_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG171_IN_SEL (BIT(7)) +#define GPIO_SIG171_IN_SEL_M (BIT(7)) +#define GPIO_SIG171_IN_SEL_V 0x1 +#define GPIO_SIG171_IN_SEL_S 7 +/* GPIO_FUNC171_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC171_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC171_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC171_IN_INV_SEL_V 0x1 +#define GPIO_FUNC171_IN_INV_SEL_S 6 +/* GPIO_FUNC171_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC171_IN_SEL 0x0000003F +#define GPIO_FUNC171_IN_SEL_M ((GPIO_FUNC171_IN_SEL_V)<<(GPIO_FUNC171_IN_SEL_S)) +#define GPIO_FUNC171_IN_SEL_V 0x3F +#define GPIO_FUNC171_IN_SEL_S 0 + +#define GPIO_FUNC172_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03e0) +/* GPIO_SIG172_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG172_IN_SEL (BIT(7)) +#define GPIO_SIG172_IN_SEL_M (BIT(7)) +#define GPIO_SIG172_IN_SEL_V 0x1 +#define GPIO_SIG172_IN_SEL_S 7 +/* GPIO_FUNC172_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC172_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC172_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC172_IN_INV_SEL_V 0x1 +#define GPIO_FUNC172_IN_INV_SEL_S 6 +/* GPIO_FUNC172_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC172_IN_SEL 0x0000003F +#define GPIO_FUNC172_IN_SEL_M ((GPIO_FUNC172_IN_SEL_V)<<(GPIO_FUNC172_IN_SEL_S)) +#define GPIO_FUNC172_IN_SEL_V 0x3F +#define GPIO_FUNC172_IN_SEL_S 0 + +#define GPIO_FUNC173_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03e4) +/* GPIO_SIG173_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG173_IN_SEL (BIT(7)) +#define GPIO_SIG173_IN_SEL_M (BIT(7)) +#define GPIO_SIG173_IN_SEL_V 0x1 +#define GPIO_SIG173_IN_SEL_S 7 +/* GPIO_FUNC173_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC173_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC173_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC173_IN_INV_SEL_V 0x1 +#define GPIO_FUNC173_IN_INV_SEL_S 6 +/* GPIO_FUNC173_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC173_IN_SEL 0x0000003F +#define GPIO_FUNC173_IN_SEL_M ((GPIO_FUNC173_IN_SEL_V)<<(GPIO_FUNC173_IN_SEL_S)) +#define GPIO_FUNC173_IN_SEL_V 0x3F +#define GPIO_FUNC173_IN_SEL_S 0 + +#define GPIO_FUNC174_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03e8) +/* GPIO_SIG174_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG174_IN_SEL (BIT(7)) +#define GPIO_SIG174_IN_SEL_M (BIT(7)) +#define GPIO_SIG174_IN_SEL_V 0x1 +#define GPIO_SIG174_IN_SEL_S 7 +/* GPIO_FUNC174_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC174_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC174_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC174_IN_INV_SEL_V 0x1 +#define GPIO_FUNC174_IN_INV_SEL_S 6 +/* GPIO_FUNC174_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC174_IN_SEL 0x0000003F +#define GPIO_FUNC174_IN_SEL_M ((GPIO_FUNC174_IN_SEL_V)<<(GPIO_FUNC174_IN_SEL_S)) +#define GPIO_FUNC174_IN_SEL_V 0x3F +#define GPIO_FUNC174_IN_SEL_S 0 + +#define GPIO_FUNC175_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03ec) +/* GPIO_SIG175_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG175_IN_SEL (BIT(7)) +#define GPIO_SIG175_IN_SEL_M (BIT(7)) +#define GPIO_SIG175_IN_SEL_V 0x1 +#define GPIO_SIG175_IN_SEL_S 7 +/* GPIO_FUNC175_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC175_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC175_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC175_IN_INV_SEL_V 0x1 +#define GPIO_FUNC175_IN_INV_SEL_S 6 +/* GPIO_FUNC175_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC175_IN_SEL 0x0000003F +#define GPIO_FUNC175_IN_SEL_M ((GPIO_FUNC175_IN_SEL_V)<<(GPIO_FUNC175_IN_SEL_S)) +#define GPIO_FUNC175_IN_SEL_V 0x3F +#define GPIO_FUNC175_IN_SEL_S 0 + +#define GPIO_FUNC176_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03f0) +/* GPIO_SIG176_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG176_IN_SEL (BIT(7)) +#define GPIO_SIG176_IN_SEL_M (BIT(7)) +#define GPIO_SIG176_IN_SEL_V 0x1 +#define GPIO_SIG176_IN_SEL_S 7 +/* GPIO_FUNC176_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC176_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC176_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC176_IN_INV_SEL_V 0x1 +#define GPIO_FUNC176_IN_INV_SEL_S 6 +/* GPIO_FUNC176_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC176_IN_SEL 0x0000003F +#define GPIO_FUNC176_IN_SEL_M ((GPIO_FUNC176_IN_SEL_V)<<(GPIO_FUNC176_IN_SEL_S)) +#define GPIO_FUNC176_IN_SEL_V 0x3F +#define GPIO_FUNC176_IN_SEL_S 0 + +#define GPIO_FUNC177_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03f4) +/* GPIO_SIG177_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG177_IN_SEL (BIT(7)) +#define GPIO_SIG177_IN_SEL_M (BIT(7)) +#define GPIO_SIG177_IN_SEL_V 0x1 +#define GPIO_SIG177_IN_SEL_S 7 +/* GPIO_FUNC177_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC177_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC177_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC177_IN_INV_SEL_V 0x1 +#define GPIO_FUNC177_IN_INV_SEL_S 6 +/* GPIO_FUNC177_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC177_IN_SEL 0x0000003F +#define GPIO_FUNC177_IN_SEL_M ((GPIO_FUNC177_IN_SEL_V)<<(GPIO_FUNC177_IN_SEL_S)) +#define GPIO_FUNC177_IN_SEL_V 0x3F +#define GPIO_FUNC177_IN_SEL_S 0 + +#define GPIO_FUNC178_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03f8) +/* GPIO_SIG178_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG178_IN_SEL (BIT(7)) +#define GPIO_SIG178_IN_SEL_M (BIT(7)) +#define GPIO_SIG178_IN_SEL_V 0x1 +#define GPIO_SIG178_IN_SEL_S 7 +/* GPIO_FUNC178_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC178_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC178_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC178_IN_INV_SEL_V 0x1 +#define GPIO_FUNC178_IN_INV_SEL_S 6 +/* GPIO_FUNC178_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC178_IN_SEL 0x0000003F +#define GPIO_FUNC178_IN_SEL_M ((GPIO_FUNC178_IN_SEL_V)<<(GPIO_FUNC178_IN_SEL_S)) +#define GPIO_FUNC178_IN_SEL_V 0x3F +#define GPIO_FUNC178_IN_SEL_S 0 + +#define GPIO_FUNC179_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03fc) +/* GPIO_SIG179_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG179_IN_SEL (BIT(7)) +#define GPIO_SIG179_IN_SEL_M (BIT(7)) +#define GPIO_SIG179_IN_SEL_V 0x1 +#define GPIO_SIG179_IN_SEL_S 7 +/* GPIO_FUNC179_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC179_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC179_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC179_IN_INV_SEL_V 0x1 +#define GPIO_FUNC179_IN_INV_SEL_S 6 +/* GPIO_FUNC179_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC179_IN_SEL 0x0000003F +#define GPIO_FUNC179_IN_SEL_M ((GPIO_FUNC179_IN_SEL_V)<<(GPIO_FUNC179_IN_SEL_S)) +#define GPIO_FUNC179_IN_SEL_V 0x3F +#define GPIO_FUNC179_IN_SEL_S 0 + +#define GPIO_FUNC180_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0400) +/* GPIO_SIG180_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG180_IN_SEL (BIT(7)) +#define GPIO_SIG180_IN_SEL_M (BIT(7)) +#define GPIO_SIG180_IN_SEL_V 0x1 +#define GPIO_SIG180_IN_SEL_S 7 +/* GPIO_FUNC180_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC180_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC180_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC180_IN_INV_SEL_V 0x1 +#define GPIO_FUNC180_IN_INV_SEL_S 6 +/* GPIO_FUNC180_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC180_IN_SEL 0x0000003F +#define GPIO_FUNC180_IN_SEL_M ((GPIO_FUNC180_IN_SEL_V)<<(GPIO_FUNC180_IN_SEL_S)) +#define GPIO_FUNC180_IN_SEL_V 0x3F +#define GPIO_FUNC180_IN_SEL_S 0 + +#define GPIO_FUNC181_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0404) +/* GPIO_SIG181_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG181_IN_SEL (BIT(7)) +#define GPIO_SIG181_IN_SEL_M (BIT(7)) +#define GPIO_SIG181_IN_SEL_V 0x1 +#define GPIO_SIG181_IN_SEL_S 7 +/* GPIO_FUNC181_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC181_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC181_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC181_IN_INV_SEL_V 0x1 +#define GPIO_FUNC181_IN_INV_SEL_S 6 +/* GPIO_FUNC181_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC181_IN_SEL 0x0000003F +#define GPIO_FUNC181_IN_SEL_M ((GPIO_FUNC181_IN_SEL_V)<<(GPIO_FUNC181_IN_SEL_S)) +#define GPIO_FUNC181_IN_SEL_V 0x3F +#define GPIO_FUNC181_IN_SEL_S 0 + +#define GPIO_FUNC182_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0408) +/* GPIO_SIG182_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG182_IN_SEL (BIT(7)) +#define GPIO_SIG182_IN_SEL_M (BIT(7)) +#define GPIO_SIG182_IN_SEL_V 0x1 +#define GPIO_SIG182_IN_SEL_S 7 +/* GPIO_FUNC182_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC182_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC182_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC182_IN_INV_SEL_V 0x1 +#define GPIO_FUNC182_IN_INV_SEL_S 6 +/* GPIO_FUNC182_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC182_IN_SEL 0x0000003F +#define GPIO_FUNC182_IN_SEL_M ((GPIO_FUNC182_IN_SEL_V)<<(GPIO_FUNC182_IN_SEL_S)) +#define GPIO_FUNC182_IN_SEL_V 0x3F +#define GPIO_FUNC182_IN_SEL_S 0 + +#define GPIO_FUNC183_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x040c) +/* GPIO_SIG183_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG183_IN_SEL (BIT(7)) +#define GPIO_SIG183_IN_SEL_M (BIT(7)) +#define GPIO_SIG183_IN_SEL_V 0x1 +#define GPIO_SIG183_IN_SEL_S 7 +/* GPIO_FUNC183_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC183_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC183_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC183_IN_INV_SEL_V 0x1 +#define GPIO_FUNC183_IN_INV_SEL_S 6 +/* GPIO_FUNC183_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC183_IN_SEL 0x0000003F +#define GPIO_FUNC183_IN_SEL_M ((GPIO_FUNC183_IN_SEL_V)<<(GPIO_FUNC183_IN_SEL_S)) +#define GPIO_FUNC183_IN_SEL_V 0x3F +#define GPIO_FUNC183_IN_SEL_S 0 + +#define GPIO_FUNC184_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0410) +/* GPIO_SIG184_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG184_IN_SEL (BIT(7)) +#define GPIO_SIG184_IN_SEL_M (BIT(7)) +#define GPIO_SIG184_IN_SEL_V 0x1 +#define GPIO_SIG184_IN_SEL_S 7 +/* GPIO_FUNC184_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC184_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC184_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC184_IN_INV_SEL_V 0x1 +#define GPIO_FUNC184_IN_INV_SEL_S 6 +/* GPIO_FUNC184_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC184_IN_SEL 0x0000003F +#define GPIO_FUNC184_IN_SEL_M ((GPIO_FUNC184_IN_SEL_V)<<(GPIO_FUNC184_IN_SEL_S)) +#define GPIO_FUNC184_IN_SEL_V 0x3F +#define GPIO_FUNC184_IN_SEL_S 0 + +#define GPIO_FUNC185_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0414) +/* GPIO_SIG185_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG185_IN_SEL (BIT(7)) +#define GPIO_SIG185_IN_SEL_M (BIT(7)) +#define GPIO_SIG185_IN_SEL_V 0x1 +#define GPIO_SIG185_IN_SEL_S 7 +/* GPIO_FUNC185_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC185_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC185_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC185_IN_INV_SEL_V 0x1 +#define GPIO_FUNC185_IN_INV_SEL_S 6 +/* GPIO_FUNC185_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC185_IN_SEL 0x0000003F +#define GPIO_FUNC185_IN_SEL_M ((GPIO_FUNC185_IN_SEL_V)<<(GPIO_FUNC185_IN_SEL_S)) +#define GPIO_FUNC185_IN_SEL_V 0x3F +#define GPIO_FUNC185_IN_SEL_S 0 + +#define GPIO_FUNC186_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0418) +/* GPIO_SIG186_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG186_IN_SEL (BIT(7)) +#define GPIO_SIG186_IN_SEL_M (BIT(7)) +#define GPIO_SIG186_IN_SEL_V 0x1 +#define GPIO_SIG186_IN_SEL_S 7 +/* GPIO_FUNC186_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC186_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC186_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC186_IN_INV_SEL_V 0x1 +#define GPIO_FUNC186_IN_INV_SEL_S 6 +/* GPIO_FUNC186_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC186_IN_SEL 0x0000003F +#define GPIO_FUNC186_IN_SEL_M ((GPIO_FUNC186_IN_SEL_V)<<(GPIO_FUNC186_IN_SEL_S)) +#define GPIO_FUNC186_IN_SEL_V 0x3F +#define GPIO_FUNC186_IN_SEL_S 0 + +#define GPIO_FUNC187_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x041c) +/* GPIO_SIG187_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG187_IN_SEL (BIT(7)) +#define GPIO_SIG187_IN_SEL_M (BIT(7)) +#define GPIO_SIG187_IN_SEL_V 0x1 +#define GPIO_SIG187_IN_SEL_S 7 +/* GPIO_FUNC187_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC187_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC187_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC187_IN_INV_SEL_V 0x1 +#define GPIO_FUNC187_IN_INV_SEL_S 6 +/* GPIO_FUNC187_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC187_IN_SEL 0x0000003F +#define GPIO_FUNC187_IN_SEL_M ((GPIO_FUNC187_IN_SEL_V)<<(GPIO_FUNC187_IN_SEL_S)) +#define GPIO_FUNC187_IN_SEL_V 0x3F +#define GPIO_FUNC187_IN_SEL_S 0 + +#define GPIO_FUNC188_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0420) +/* GPIO_SIG188_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG188_IN_SEL (BIT(7)) +#define GPIO_SIG188_IN_SEL_M (BIT(7)) +#define GPIO_SIG188_IN_SEL_V 0x1 +#define GPIO_SIG188_IN_SEL_S 7 +/* GPIO_FUNC188_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC188_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC188_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC188_IN_INV_SEL_V 0x1 +#define GPIO_FUNC188_IN_INV_SEL_S 6 +/* GPIO_FUNC188_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC188_IN_SEL 0x0000003F +#define GPIO_FUNC188_IN_SEL_M ((GPIO_FUNC188_IN_SEL_V)<<(GPIO_FUNC188_IN_SEL_S)) +#define GPIO_FUNC188_IN_SEL_V 0x3F +#define GPIO_FUNC188_IN_SEL_S 0 + +#define GPIO_FUNC189_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0424) +/* GPIO_SIG189_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG189_IN_SEL (BIT(7)) +#define GPIO_SIG189_IN_SEL_M (BIT(7)) +#define GPIO_SIG189_IN_SEL_V 0x1 +#define GPIO_SIG189_IN_SEL_S 7 +/* GPIO_FUNC189_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC189_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC189_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC189_IN_INV_SEL_V 0x1 +#define GPIO_FUNC189_IN_INV_SEL_S 6 +/* GPIO_FUNC189_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC189_IN_SEL 0x0000003F +#define GPIO_FUNC189_IN_SEL_M ((GPIO_FUNC189_IN_SEL_V)<<(GPIO_FUNC189_IN_SEL_S)) +#define GPIO_FUNC189_IN_SEL_V 0x3F +#define GPIO_FUNC189_IN_SEL_S 0 + +#define GPIO_FUNC190_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0428) +/* GPIO_SIG190_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG190_IN_SEL (BIT(7)) +#define GPIO_SIG190_IN_SEL_M (BIT(7)) +#define GPIO_SIG190_IN_SEL_V 0x1 +#define GPIO_SIG190_IN_SEL_S 7 +/* GPIO_FUNC190_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC190_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC190_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC190_IN_INV_SEL_V 0x1 +#define GPIO_FUNC190_IN_INV_SEL_S 6 +/* GPIO_FUNC190_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC190_IN_SEL 0x0000003F +#define GPIO_FUNC190_IN_SEL_M ((GPIO_FUNC190_IN_SEL_V)<<(GPIO_FUNC190_IN_SEL_S)) +#define GPIO_FUNC190_IN_SEL_V 0x3F +#define GPIO_FUNC190_IN_SEL_S 0 + +#define GPIO_FUNC191_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x042c) +/* GPIO_SIG191_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG191_IN_SEL (BIT(7)) +#define GPIO_SIG191_IN_SEL_M (BIT(7)) +#define GPIO_SIG191_IN_SEL_V 0x1 +#define GPIO_SIG191_IN_SEL_S 7 +/* GPIO_FUNC191_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC191_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC191_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC191_IN_INV_SEL_V 0x1 +#define GPIO_FUNC191_IN_INV_SEL_S 6 +/* GPIO_FUNC191_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC191_IN_SEL 0x0000003F +#define GPIO_FUNC191_IN_SEL_M ((GPIO_FUNC191_IN_SEL_V)<<(GPIO_FUNC191_IN_SEL_S)) +#define GPIO_FUNC191_IN_SEL_V 0x3F +#define GPIO_FUNC191_IN_SEL_S 0 + +#define GPIO_FUNC192_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0430) +/* GPIO_SIG192_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG192_IN_SEL (BIT(7)) +#define GPIO_SIG192_IN_SEL_M (BIT(7)) +#define GPIO_SIG192_IN_SEL_V 0x1 +#define GPIO_SIG192_IN_SEL_S 7 +/* GPIO_FUNC192_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC192_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC192_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC192_IN_INV_SEL_V 0x1 +#define GPIO_FUNC192_IN_INV_SEL_S 6 +/* GPIO_FUNC192_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC192_IN_SEL 0x0000003F +#define GPIO_FUNC192_IN_SEL_M ((GPIO_FUNC192_IN_SEL_V)<<(GPIO_FUNC192_IN_SEL_S)) +#define GPIO_FUNC192_IN_SEL_V 0x3F +#define GPIO_FUNC192_IN_SEL_S 0 + +#define GPIO_FUNC193_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0434) +/* GPIO_SIG193_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG193_IN_SEL (BIT(7)) +#define GPIO_SIG193_IN_SEL_M (BIT(7)) +#define GPIO_SIG193_IN_SEL_V 0x1 +#define GPIO_SIG193_IN_SEL_S 7 +/* GPIO_FUNC193_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC193_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC193_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC193_IN_INV_SEL_V 0x1 +#define GPIO_FUNC193_IN_INV_SEL_S 6 +/* GPIO_FUNC193_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC193_IN_SEL 0x0000003F +#define GPIO_FUNC193_IN_SEL_M ((GPIO_FUNC193_IN_SEL_V)<<(GPIO_FUNC193_IN_SEL_S)) +#define GPIO_FUNC193_IN_SEL_V 0x3F +#define GPIO_FUNC193_IN_SEL_S 0 + +#define GPIO_FUNC194_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0438) +/* GPIO_SIG194_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG194_IN_SEL (BIT(7)) +#define GPIO_SIG194_IN_SEL_M (BIT(7)) +#define GPIO_SIG194_IN_SEL_V 0x1 +#define GPIO_SIG194_IN_SEL_S 7 +/* GPIO_FUNC194_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC194_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC194_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC194_IN_INV_SEL_V 0x1 +#define GPIO_FUNC194_IN_INV_SEL_S 6 +/* GPIO_FUNC194_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC194_IN_SEL 0x0000003F +#define GPIO_FUNC194_IN_SEL_M ((GPIO_FUNC194_IN_SEL_V)<<(GPIO_FUNC194_IN_SEL_S)) +#define GPIO_FUNC194_IN_SEL_V 0x3F +#define GPIO_FUNC194_IN_SEL_S 0 + +#define GPIO_FUNC195_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x043c) +/* GPIO_SIG195_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG195_IN_SEL (BIT(7)) +#define GPIO_SIG195_IN_SEL_M (BIT(7)) +#define GPIO_SIG195_IN_SEL_V 0x1 +#define GPIO_SIG195_IN_SEL_S 7 +/* GPIO_FUNC195_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC195_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC195_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC195_IN_INV_SEL_V 0x1 +#define GPIO_FUNC195_IN_INV_SEL_S 6 +/* GPIO_FUNC195_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC195_IN_SEL 0x0000003F +#define GPIO_FUNC195_IN_SEL_M ((GPIO_FUNC195_IN_SEL_V)<<(GPIO_FUNC195_IN_SEL_S)) +#define GPIO_FUNC195_IN_SEL_V 0x3F +#define GPIO_FUNC195_IN_SEL_S 0 + +#define GPIO_FUNC196_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0440) +/* GPIO_SIG196_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG196_IN_SEL (BIT(7)) +#define GPIO_SIG196_IN_SEL_M (BIT(7)) +#define GPIO_SIG196_IN_SEL_V 0x1 +#define GPIO_SIG196_IN_SEL_S 7 +/* GPIO_FUNC196_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC196_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC196_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC196_IN_INV_SEL_V 0x1 +#define GPIO_FUNC196_IN_INV_SEL_S 6 +/* GPIO_FUNC196_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC196_IN_SEL 0x0000003F +#define GPIO_FUNC196_IN_SEL_M ((GPIO_FUNC196_IN_SEL_V)<<(GPIO_FUNC196_IN_SEL_S)) +#define GPIO_FUNC196_IN_SEL_V 0x3F +#define GPIO_FUNC196_IN_SEL_S 0 + +#define GPIO_FUNC197_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0444) +/* GPIO_SIG197_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG197_IN_SEL (BIT(7)) +#define GPIO_SIG197_IN_SEL_M (BIT(7)) +#define GPIO_SIG197_IN_SEL_V 0x1 +#define GPIO_SIG197_IN_SEL_S 7 +/* GPIO_FUNC197_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC197_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC197_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC197_IN_INV_SEL_V 0x1 +#define GPIO_FUNC197_IN_INV_SEL_S 6 +/* GPIO_FUNC197_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC197_IN_SEL 0x0000003F +#define GPIO_FUNC197_IN_SEL_M ((GPIO_FUNC197_IN_SEL_V)<<(GPIO_FUNC197_IN_SEL_S)) +#define GPIO_FUNC197_IN_SEL_V 0x3F +#define GPIO_FUNC197_IN_SEL_S 0 + +#define GPIO_FUNC198_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0448) +/* GPIO_SIG198_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG198_IN_SEL (BIT(7)) +#define GPIO_SIG198_IN_SEL_M (BIT(7)) +#define GPIO_SIG198_IN_SEL_V 0x1 +#define GPIO_SIG198_IN_SEL_S 7 +/* GPIO_FUNC198_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC198_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC198_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC198_IN_INV_SEL_V 0x1 +#define GPIO_FUNC198_IN_INV_SEL_S 6 +/* GPIO_FUNC198_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC198_IN_SEL 0x0000003F +#define GPIO_FUNC198_IN_SEL_M ((GPIO_FUNC198_IN_SEL_V)<<(GPIO_FUNC198_IN_SEL_S)) +#define GPIO_FUNC198_IN_SEL_V 0x3F +#define GPIO_FUNC198_IN_SEL_S 0 + +#define GPIO_FUNC199_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x044c) +/* GPIO_SIG199_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG199_IN_SEL (BIT(7)) +#define GPIO_SIG199_IN_SEL_M (BIT(7)) +#define GPIO_SIG199_IN_SEL_V 0x1 +#define GPIO_SIG199_IN_SEL_S 7 +/* GPIO_FUNC199_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC199_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC199_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC199_IN_INV_SEL_V 0x1 +#define GPIO_FUNC199_IN_INV_SEL_S 6 +/* GPIO_FUNC199_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC199_IN_SEL 0x0000003F +#define GPIO_FUNC199_IN_SEL_M ((GPIO_FUNC199_IN_SEL_V)<<(GPIO_FUNC199_IN_SEL_S)) +#define GPIO_FUNC199_IN_SEL_V 0x3F +#define GPIO_FUNC199_IN_SEL_S 0 + +#define GPIO_FUNC200_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0450) +/* GPIO_SIG200_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG200_IN_SEL (BIT(7)) +#define GPIO_SIG200_IN_SEL_M (BIT(7)) +#define GPIO_SIG200_IN_SEL_V 0x1 +#define GPIO_SIG200_IN_SEL_S 7 +/* GPIO_FUNC200_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC200_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC200_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC200_IN_INV_SEL_V 0x1 +#define GPIO_FUNC200_IN_INV_SEL_S 6 +/* GPIO_FUNC200_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC200_IN_SEL 0x0000003F +#define GPIO_FUNC200_IN_SEL_M ((GPIO_FUNC200_IN_SEL_V)<<(GPIO_FUNC200_IN_SEL_S)) +#define GPIO_FUNC200_IN_SEL_V 0x3F +#define GPIO_FUNC200_IN_SEL_S 0 + +#define GPIO_FUNC201_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0454) +/* GPIO_SIG201_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG201_IN_SEL (BIT(7)) +#define GPIO_SIG201_IN_SEL_M (BIT(7)) +#define GPIO_SIG201_IN_SEL_V 0x1 +#define GPIO_SIG201_IN_SEL_S 7 +/* GPIO_FUNC201_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC201_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC201_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC201_IN_INV_SEL_V 0x1 +#define GPIO_FUNC201_IN_INV_SEL_S 6 +/* GPIO_FUNC201_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC201_IN_SEL 0x0000003F +#define GPIO_FUNC201_IN_SEL_M ((GPIO_FUNC201_IN_SEL_V)<<(GPIO_FUNC201_IN_SEL_S)) +#define GPIO_FUNC201_IN_SEL_V 0x3F +#define GPIO_FUNC201_IN_SEL_S 0 + +#define GPIO_FUNC202_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0458) +/* GPIO_SIG202_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG202_IN_SEL (BIT(7)) +#define GPIO_SIG202_IN_SEL_M (BIT(7)) +#define GPIO_SIG202_IN_SEL_V 0x1 +#define GPIO_SIG202_IN_SEL_S 7 +/* GPIO_FUNC202_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC202_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC202_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC202_IN_INV_SEL_V 0x1 +#define GPIO_FUNC202_IN_INV_SEL_S 6 +/* GPIO_FUNC202_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC202_IN_SEL 0x0000003F +#define GPIO_FUNC202_IN_SEL_M ((GPIO_FUNC202_IN_SEL_V)<<(GPIO_FUNC202_IN_SEL_S)) +#define GPIO_FUNC202_IN_SEL_V 0x3F +#define GPIO_FUNC202_IN_SEL_S 0 + +#define GPIO_FUNC203_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x045c) +/* GPIO_SIG203_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG203_IN_SEL (BIT(7)) +#define GPIO_SIG203_IN_SEL_M (BIT(7)) +#define GPIO_SIG203_IN_SEL_V 0x1 +#define GPIO_SIG203_IN_SEL_S 7 +/* GPIO_FUNC203_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC203_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC203_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC203_IN_INV_SEL_V 0x1 +#define GPIO_FUNC203_IN_INV_SEL_S 6 +/* GPIO_FUNC203_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC203_IN_SEL 0x0000003F +#define GPIO_FUNC203_IN_SEL_M ((GPIO_FUNC203_IN_SEL_V)<<(GPIO_FUNC203_IN_SEL_S)) +#define GPIO_FUNC203_IN_SEL_V 0x3F +#define GPIO_FUNC203_IN_SEL_S 0 + +#define GPIO_FUNC204_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0460) +/* GPIO_SIG204_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG204_IN_SEL (BIT(7)) +#define GPIO_SIG204_IN_SEL_M (BIT(7)) +#define GPIO_SIG204_IN_SEL_V 0x1 +#define GPIO_SIG204_IN_SEL_S 7 +/* GPIO_FUNC204_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC204_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC204_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC204_IN_INV_SEL_V 0x1 +#define GPIO_FUNC204_IN_INV_SEL_S 6 +/* GPIO_FUNC204_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC204_IN_SEL 0x0000003F +#define GPIO_FUNC204_IN_SEL_M ((GPIO_FUNC204_IN_SEL_V)<<(GPIO_FUNC204_IN_SEL_S)) +#define GPIO_FUNC204_IN_SEL_V 0x3F +#define GPIO_FUNC204_IN_SEL_S 0 + +#define GPIO_FUNC205_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0464) +/* GPIO_SIG205_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG205_IN_SEL (BIT(7)) +#define GPIO_SIG205_IN_SEL_M (BIT(7)) +#define GPIO_SIG205_IN_SEL_V 0x1 +#define GPIO_SIG205_IN_SEL_S 7 +/* GPIO_FUNC205_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC205_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC205_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC205_IN_INV_SEL_V 0x1 +#define GPIO_FUNC205_IN_INV_SEL_S 6 +/* GPIO_FUNC205_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC205_IN_SEL 0x0000003F +#define GPIO_FUNC205_IN_SEL_M ((GPIO_FUNC205_IN_SEL_V)<<(GPIO_FUNC205_IN_SEL_S)) +#define GPIO_FUNC205_IN_SEL_V 0x3F +#define GPIO_FUNC205_IN_SEL_S 0 + +#define GPIO_FUNC206_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0468) +/* GPIO_SIG206_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG206_IN_SEL (BIT(7)) +#define GPIO_SIG206_IN_SEL_M (BIT(7)) +#define GPIO_SIG206_IN_SEL_V 0x1 +#define GPIO_SIG206_IN_SEL_S 7 +/* GPIO_FUNC206_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC206_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC206_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC206_IN_INV_SEL_V 0x1 +#define GPIO_FUNC206_IN_INV_SEL_S 6 +/* GPIO_FUNC206_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC206_IN_SEL 0x0000003F +#define GPIO_FUNC206_IN_SEL_M ((GPIO_FUNC206_IN_SEL_V)<<(GPIO_FUNC206_IN_SEL_S)) +#define GPIO_FUNC206_IN_SEL_V 0x3F +#define GPIO_FUNC206_IN_SEL_S 0 + +#define GPIO_FUNC207_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x046c) +/* GPIO_SIG207_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG207_IN_SEL (BIT(7)) +#define GPIO_SIG207_IN_SEL_M (BIT(7)) +#define GPIO_SIG207_IN_SEL_V 0x1 +#define GPIO_SIG207_IN_SEL_S 7 +/* GPIO_FUNC207_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC207_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC207_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC207_IN_INV_SEL_V 0x1 +#define GPIO_FUNC207_IN_INV_SEL_S 6 +/* GPIO_FUNC207_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC207_IN_SEL 0x0000003F +#define GPIO_FUNC207_IN_SEL_M ((GPIO_FUNC207_IN_SEL_V)<<(GPIO_FUNC207_IN_SEL_S)) +#define GPIO_FUNC207_IN_SEL_V 0x3F +#define GPIO_FUNC207_IN_SEL_S 0 + +#define GPIO_FUNC208_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0470) +/* GPIO_SIG208_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG208_IN_SEL (BIT(7)) +#define GPIO_SIG208_IN_SEL_M (BIT(7)) +#define GPIO_SIG208_IN_SEL_V 0x1 +#define GPIO_SIG208_IN_SEL_S 7 +/* GPIO_FUNC208_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC208_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC208_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC208_IN_INV_SEL_V 0x1 +#define GPIO_FUNC208_IN_INV_SEL_S 6 +/* GPIO_FUNC208_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC208_IN_SEL 0x0000003F +#define GPIO_FUNC208_IN_SEL_M ((GPIO_FUNC208_IN_SEL_V)<<(GPIO_FUNC208_IN_SEL_S)) +#define GPIO_FUNC208_IN_SEL_V 0x3F +#define GPIO_FUNC208_IN_SEL_S 0 + +#define GPIO_FUNC209_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0474) +/* GPIO_SIG209_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG209_IN_SEL (BIT(7)) +#define GPIO_SIG209_IN_SEL_M (BIT(7)) +#define GPIO_SIG209_IN_SEL_V 0x1 +#define GPIO_SIG209_IN_SEL_S 7 +/* GPIO_FUNC209_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC209_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC209_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC209_IN_INV_SEL_V 0x1 +#define GPIO_FUNC209_IN_INV_SEL_S 6 +/* GPIO_FUNC209_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC209_IN_SEL 0x0000003F +#define GPIO_FUNC209_IN_SEL_M ((GPIO_FUNC209_IN_SEL_V)<<(GPIO_FUNC209_IN_SEL_S)) +#define GPIO_FUNC209_IN_SEL_V 0x3F +#define GPIO_FUNC209_IN_SEL_S 0 + +#define GPIO_FUNC210_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0478) +/* GPIO_SIG210_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG210_IN_SEL (BIT(7)) +#define GPIO_SIG210_IN_SEL_M (BIT(7)) +#define GPIO_SIG210_IN_SEL_V 0x1 +#define GPIO_SIG210_IN_SEL_S 7 +/* GPIO_FUNC210_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC210_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC210_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC210_IN_INV_SEL_V 0x1 +#define GPIO_FUNC210_IN_INV_SEL_S 6 +/* GPIO_FUNC210_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC210_IN_SEL 0x0000003F +#define GPIO_FUNC210_IN_SEL_M ((GPIO_FUNC210_IN_SEL_V)<<(GPIO_FUNC210_IN_SEL_S)) +#define GPIO_FUNC210_IN_SEL_V 0x3F +#define GPIO_FUNC210_IN_SEL_S 0 + +#define GPIO_FUNC211_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x047c) +/* GPIO_SIG211_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG211_IN_SEL (BIT(7)) +#define GPIO_SIG211_IN_SEL_M (BIT(7)) +#define GPIO_SIG211_IN_SEL_V 0x1 +#define GPIO_SIG211_IN_SEL_S 7 +/* GPIO_FUNC211_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC211_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC211_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC211_IN_INV_SEL_V 0x1 +#define GPIO_FUNC211_IN_INV_SEL_S 6 +/* GPIO_FUNC211_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC211_IN_SEL 0x0000003F +#define GPIO_FUNC211_IN_SEL_M ((GPIO_FUNC211_IN_SEL_V)<<(GPIO_FUNC211_IN_SEL_S)) +#define GPIO_FUNC211_IN_SEL_V 0x3F +#define GPIO_FUNC211_IN_SEL_S 0 + +#define GPIO_FUNC212_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0480) +/* GPIO_SIG212_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG212_IN_SEL (BIT(7)) +#define GPIO_SIG212_IN_SEL_M (BIT(7)) +#define GPIO_SIG212_IN_SEL_V 0x1 +#define GPIO_SIG212_IN_SEL_S 7 +/* GPIO_FUNC212_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC212_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC212_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC212_IN_INV_SEL_V 0x1 +#define GPIO_FUNC212_IN_INV_SEL_S 6 +/* GPIO_FUNC212_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC212_IN_SEL 0x0000003F +#define GPIO_FUNC212_IN_SEL_M ((GPIO_FUNC212_IN_SEL_V)<<(GPIO_FUNC212_IN_SEL_S)) +#define GPIO_FUNC212_IN_SEL_V 0x3F +#define GPIO_FUNC212_IN_SEL_S 0 + +#define GPIO_FUNC213_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0484) +/* GPIO_SIG213_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG213_IN_SEL (BIT(7)) +#define GPIO_SIG213_IN_SEL_M (BIT(7)) +#define GPIO_SIG213_IN_SEL_V 0x1 +#define GPIO_SIG213_IN_SEL_S 7 +/* GPIO_FUNC213_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC213_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC213_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC213_IN_INV_SEL_V 0x1 +#define GPIO_FUNC213_IN_INV_SEL_S 6 +/* GPIO_FUNC213_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC213_IN_SEL 0x0000003F +#define GPIO_FUNC213_IN_SEL_M ((GPIO_FUNC213_IN_SEL_V)<<(GPIO_FUNC213_IN_SEL_S)) +#define GPIO_FUNC213_IN_SEL_V 0x3F +#define GPIO_FUNC213_IN_SEL_S 0 + +#define GPIO_FUNC214_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0488) +/* GPIO_SIG214_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG214_IN_SEL (BIT(7)) +#define GPIO_SIG214_IN_SEL_M (BIT(7)) +#define GPIO_SIG214_IN_SEL_V 0x1 +#define GPIO_SIG214_IN_SEL_S 7 +/* GPIO_FUNC214_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC214_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC214_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC214_IN_INV_SEL_V 0x1 +#define GPIO_FUNC214_IN_INV_SEL_S 6 +/* GPIO_FUNC214_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC214_IN_SEL 0x0000003F +#define GPIO_FUNC214_IN_SEL_M ((GPIO_FUNC214_IN_SEL_V)<<(GPIO_FUNC214_IN_SEL_S)) +#define GPIO_FUNC214_IN_SEL_V 0x3F +#define GPIO_FUNC214_IN_SEL_S 0 + +#define GPIO_FUNC215_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x048c) +/* GPIO_SIG215_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG215_IN_SEL (BIT(7)) +#define GPIO_SIG215_IN_SEL_M (BIT(7)) +#define GPIO_SIG215_IN_SEL_V 0x1 +#define GPIO_SIG215_IN_SEL_S 7 +/* GPIO_FUNC215_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC215_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC215_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC215_IN_INV_SEL_V 0x1 +#define GPIO_FUNC215_IN_INV_SEL_S 6 +/* GPIO_FUNC215_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC215_IN_SEL 0x0000003F +#define GPIO_FUNC215_IN_SEL_M ((GPIO_FUNC215_IN_SEL_V)<<(GPIO_FUNC215_IN_SEL_S)) +#define GPIO_FUNC215_IN_SEL_V 0x3F +#define GPIO_FUNC215_IN_SEL_S 0 + +#define GPIO_FUNC216_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0490) +/* GPIO_SIG216_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG216_IN_SEL (BIT(7)) +#define GPIO_SIG216_IN_SEL_M (BIT(7)) +#define GPIO_SIG216_IN_SEL_V 0x1 +#define GPIO_SIG216_IN_SEL_S 7 +/* GPIO_FUNC216_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC216_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC216_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC216_IN_INV_SEL_V 0x1 +#define GPIO_FUNC216_IN_INV_SEL_S 6 +/* GPIO_FUNC216_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC216_IN_SEL 0x0000003F +#define GPIO_FUNC216_IN_SEL_M ((GPIO_FUNC216_IN_SEL_V)<<(GPIO_FUNC216_IN_SEL_S)) +#define GPIO_FUNC216_IN_SEL_V 0x3F +#define GPIO_FUNC216_IN_SEL_S 0 + +#define GPIO_FUNC217_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0494) +/* GPIO_SIG217_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG217_IN_SEL (BIT(7)) +#define GPIO_SIG217_IN_SEL_M (BIT(7)) +#define GPIO_SIG217_IN_SEL_V 0x1 +#define GPIO_SIG217_IN_SEL_S 7 +/* GPIO_FUNC217_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC217_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC217_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC217_IN_INV_SEL_V 0x1 +#define GPIO_FUNC217_IN_INV_SEL_S 6 +/* GPIO_FUNC217_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC217_IN_SEL 0x0000003F +#define GPIO_FUNC217_IN_SEL_M ((GPIO_FUNC217_IN_SEL_V)<<(GPIO_FUNC217_IN_SEL_S)) +#define GPIO_FUNC217_IN_SEL_V 0x3F +#define GPIO_FUNC217_IN_SEL_S 0 + +#define GPIO_FUNC218_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0498) +/* GPIO_SIG218_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG218_IN_SEL (BIT(7)) +#define GPIO_SIG218_IN_SEL_M (BIT(7)) +#define GPIO_SIG218_IN_SEL_V 0x1 +#define GPIO_SIG218_IN_SEL_S 7 +/* GPIO_FUNC218_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC218_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC218_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC218_IN_INV_SEL_V 0x1 +#define GPIO_FUNC218_IN_INV_SEL_S 6 +/* GPIO_FUNC218_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC218_IN_SEL 0x0000003F +#define GPIO_FUNC218_IN_SEL_M ((GPIO_FUNC218_IN_SEL_V)<<(GPIO_FUNC218_IN_SEL_S)) +#define GPIO_FUNC218_IN_SEL_V 0x3F +#define GPIO_FUNC218_IN_SEL_S 0 + +#define GPIO_FUNC219_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x049c) +/* GPIO_SIG219_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG219_IN_SEL (BIT(7)) +#define GPIO_SIG219_IN_SEL_M (BIT(7)) +#define GPIO_SIG219_IN_SEL_V 0x1 +#define GPIO_SIG219_IN_SEL_S 7 +/* GPIO_FUNC219_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC219_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC219_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC219_IN_INV_SEL_V 0x1 +#define GPIO_FUNC219_IN_INV_SEL_S 6 +/* GPIO_FUNC219_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC219_IN_SEL 0x0000003F +#define GPIO_FUNC219_IN_SEL_M ((GPIO_FUNC219_IN_SEL_V)<<(GPIO_FUNC219_IN_SEL_S)) +#define GPIO_FUNC219_IN_SEL_V 0x3F +#define GPIO_FUNC219_IN_SEL_S 0 + +#define GPIO_FUNC220_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04a0) +/* GPIO_SIG220_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG220_IN_SEL (BIT(7)) +#define GPIO_SIG220_IN_SEL_M (BIT(7)) +#define GPIO_SIG220_IN_SEL_V 0x1 +#define GPIO_SIG220_IN_SEL_S 7 +/* GPIO_FUNC220_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC220_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC220_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC220_IN_INV_SEL_V 0x1 +#define GPIO_FUNC220_IN_INV_SEL_S 6 +/* GPIO_FUNC220_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC220_IN_SEL 0x0000003F +#define GPIO_FUNC220_IN_SEL_M ((GPIO_FUNC220_IN_SEL_V)<<(GPIO_FUNC220_IN_SEL_S)) +#define GPIO_FUNC220_IN_SEL_V 0x3F +#define GPIO_FUNC220_IN_SEL_S 0 + +#define GPIO_FUNC221_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04a4) +/* GPIO_SIG221_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG221_IN_SEL (BIT(7)) +#define GPIO_SIG221_IN_SEL_M (BIT(7)) +#define GPIO_SIG221_IN_SEL_V 0x1 +#define GPIO_SIG221_IN_SEL_S 7 +/* GPIO_FUNC221_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC221_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC221_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC221_IN_INV_SEL_V 0x1 +#define GPIO_FUNC221_IN_INV_SEL_S 6 +/* GPIO_FUNC221_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC221_IN_SEL 0x0000003F +#define GPIO_FUNC221_IN_SEL_M ((GPIO_FUNC221_IN_SEL_V)<<(GPIO_FUNC221_IN_SEL_S)) +#define GPIO_FUNC221_IN_SEL_V 0x3F +#define GPIO_FUNC221_IN_SEL_S 0 + +#define GPIO_FUNC222_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04a8) +/* GPIO_SIG222_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG222_IN_SEL (BIT(7)) +#define GPIO_SIG222_IN_SEL_M (BIT(7)) +#define GPIO_SIG222_IN_SEL_V 0x1 +#define GPIO_SIG222_IN_SEL_S 7 +/* GPIO_FUNC222_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC222_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC222_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC222_IN_INV_SEL_V 0x1 +#define GPIO_FUNC222_IN_INV_SEL_S 6 +/* GPIO_FUNC222_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC222_IN_SEL 0x0000003F +#define GPIO_FUNC222_IN_SEL_M ((GPIO_FUNC222_IN_SEL_V)<<(GPIO_FUNC222_IN_SEL_S)) +#define GPIO_FUNC222_IN_SEL_V 0x3F +#define GPIO_FUNC222_IN_SEL_S 0 + +#define GPIO_FUNC223_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04ac) +/* GPIO_SIG223_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG223_IN_SEL (BIT(7)) +#define GPIO_SIG223_IN_SEL_M (BIT(7)) +#define GPIO_SIG223_IN_SEL_V 0x1 +#define GPIO_SIG223_IN_SEL_S 7 +/* GPIO_FUNC223_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC223_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC223_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC223_IN_INV_SEL_V 0x1 +#define GPIO_FUNC223_IN_INV_SEL_S 6 +/* GPIO_FUNC223_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC223_IN_SEL 0x0000003F +#define GPIO_FUNC223_IN_SEL_M ((GPIO_FUNC223_IN_SEL_V)<<(GPIO_FUNC223_IN_SEL_S)) +#define GPIO_FUNC223_IN_SEL_V 0x3F +#define GPIO_FUNC223_IN_SEL_S 0 + +#define GPIO_FUNC224_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04b0) +/* GPIO_SIG224_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG224_IN_SEL (BIT(7)) +#define GPIO_SIG224_IN_SEL_M (BIT(7)) +#define GPIO_SIG224_IN_SEL_V 0x1 +#define GPIO_SIG224_IN_SEL_S 7 +/* GPIO_FUNC224_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC224_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC224_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC224_IN_INV_SEL_V 0x1 +#define GPIO_FUNC224_IN_INV_SEL_S 6 +/* GPIO_FUNC224_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC224_IN_SEL 0x0000003F +#define GPIO_FUNC224_IN_SEL_M ((GPIO_FUNC224_IN_SEL_V)<<(GPIO_FUNC224_IN_SEL_S)) +#define GPIO_FUNC224_IN_SEL_V 0x3F +#define GPIO_FUNC224_IN_SEL_S 0 + +#define GPIO_FUNC225_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04b4) +/* GPIO_SIG225_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG225_IN_SEL (BIT(7)) +#define GPIO_SIG225_IN_SEL_M (BIT(7)) +#define GPIO_SIG225_IN_SEL_V 0x1 +#define GPIO_SIG225_IN_SEL_S 7 +/* GPIO_FUNC225_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC225_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC225_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC225_IN_INV_SEL_V 0x1 +#define GPIO_FUNC225_IN_INV_SEL_S 6 +/* GPIO_FUNC225_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC225_IN_SEL 0x0000003F +#define GPIO_FUNC225_IN_SEL_M ((GPIO_FUNC225_IN_SEL_V)<<(GPIO_FUNC225_IN_SEL_S)) +#define GPIO_FUNC225_IN_SEL_V 0x3F +#define GPIO_FUNC225_IN_SEL_S 0 + +#define GPIO_FUNC226_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04b8) +/* GPIO_SIG226_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG226_IN_SEL (BIT(7)) +#define GPIO_SIG226_IN_SEL_M (BIT(7)) +#define GPIO_SIG226_IN_SEL_V 0x1 +#define GPIO_SIG226_IN_SEL_S 7 +/* GPIO_FUNC226_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC226_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC226_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC226_IN_INV_SEL_V 0x1 +#define GPIO_FUNC226_IN_INV_SEL_S 6 +/* GPIO_FUNC226_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC226_IN_SEL 0x0000003F +#define GPIO_FUNC226_IN_SEL_M ((GPIO_FUNC226_IN_SEL_V)<<(GPIO_FUNC226_IN_SEL_S)) +#define GPIO_FUNC226_IN_SEL_V 0x3F +#define GPIO_FUNC226_IN_SEL_S 0 + +#define GPIO_FUNC227_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04bc) +/* GPIO_SIG227_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG227_IN_SEL (BIT(7)) +#define GPIO_SIG227_IN_SEL_M (BIT(7)) +#define GPIO_SIG227_IN_SEL_V 0x1 +#define GPIO_SIG227_IN_SEL_S 7 +/* GPIO_FUNC227_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC227_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC227_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC227_IN_INV_SEL_V 0x1 +#define GPIO_FUNC227_IN_INV_SEL_S 6 +/* GPIO_FUNC227_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC227_IN_SEL 0x0000003F +#define GPIO_FUNC227_IN_SEL_M ((GPIO_FUNC227_IN_SEL_V)<<(GPIO_FUNC227_IN_SEL_S)) +#define GPIO_FUNC227_IN_SEL_V 0x3F +#define GPIO_FUNC227_IN_SEL_S 0 + +#define GPIO_FUNC228_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04c0) +/* GPIO_SIG228_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG228_IN_SEL (BIT(7)) +#define GPIO_SIG228_IN_SEL_M (BIT(7)) +#define GPIO_SIG228_IN_SEL_V 0x1 +#define GPIO_SIG228_IN_SEL_S 7 +/* GPIO_FUNC228_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC228_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC228_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC228_IN_INV_SEL_V 0x1 +#define GPIO_FUNC228_IN_INV_SEL_S 6 +/* GPIO_FUNC228_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC228_IN_SEL 0x0000003F +#define GPIO_FUNC228_IN_SEL_M ((GPIO_FUNC228_IN_SEL_V)<<(GPIO_FUNC228_IN_SEL_S)) +#define GPIO_FUNC228_IN_SEL_V 0x3F +#define GPIO_FUNC228_IN_SEL_S 0 + +#define GPIO_FUNC229_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04c4) +/* GPIO_SIG229_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG229_IN_SEL (BIT(7)) +#define GPIO_SIG229_IN_SEL_M (BIT(7)) +#define GPIO_SIG229_IN_SEL_V 0x1 +#define GPIO_SIG229_IN_SEL_S 7 +/* GPIO_FUNC229_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC229_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC229_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC229_IN_INV_SEL_V 0x1 +#define GPIO_FUNC229_IN_INV_SEL_S 6 +/* GPIO_FUNC229_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC229_IN_SEL 0x0000003F +#define GPIO_FUNC229_IN_SEL_M ((GPIO_FUNC229_IN_SEL_V)<<(GPIO_FUNC229_IN_SEL_S)) +#define GPIO_FUNC229_IN_SEL_V 0x3F +#define GPIO_FUNC229_IN_SEL_S 0 + +#define GPIO_FUNC230_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04c8) +/* GPIO_SIG230_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG230_IN_SEL (BIT(7)) +#define GPIO_SIG230_IN_SEL_M (BIT(7)) +#define GPIO_SIG230_IN_SEL_V 0x1 +#define GPIO_SIG230_IN_SEL_S 7 +/* GPIO_FUNC230_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC230_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC230_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC230_IN_INV_SEL_V 0x1 +#define GPIO_FUNC230_IN_INV_SEL_S 6 +/* GPIO_FUNC230_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC230_IN_SEL 0x0000003F +#define GPIO_FUNC230_IN_SEL_M ((GPIO_FUNC230_IN_SEL_V)<<(GPIO_FUNC230_IN_SEL_S)) +#define GPIO_FUNC230_IN_SEL_V 0x3F +#define GPIO_FUNC230_IN_SEL_S 0 + +#define GPIO_FUNC231_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04cc) +/* GPIO_SIG231_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG231_IN_SEL (BIT(7)) +#define GPIO_SIG231_IN_SEL_M (BIT(7)) +#define GPIO_SIG231_IN_SEL_V 0x1 +#define GPIO_SIG231_IN_SEL_S 7 +/* GPIO_FUNC231_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC231_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC231_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC231_IN_INV_SEL_V 0x1 +#define GPIO_FUNC231_IN_INV_SEL_S 6 +/* GPIO_FUNC231_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC231_IN_SEL 0x0000003F +#define GPIO_FUNC231_IN_SEL_M ((GPIO_FUNC231_IN_SEL_V)<<(GPIO_FUNC231_IN_SEL_S)) +#define GPIO_FUNC231_IN_SEL_V 0x3F +#define GPIO_FUNC231_IN_SEL_S 0 + +#define GPIO_FUNC232_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04d0) +/* GPIO_SIG232_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG232_IN_SEL (BIT(7)) +#define GPIO_SIG232_IN_SEL_M (BIT(7)) +#define GPIO_SIG232_IN_SEL_V 0x1 +#define GPIO_SIG232_IN_SEL_S 7 +/* GPIO_FUNC232_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC232_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC232_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC232_IN_INV_SEL_V 0x1 +#define GPIO_FUNC232_IN_INV_SEL_S 6 +/* GPIO_FUNC232_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC232_IN_SEL 0x0000003F +#define GPIO_FUNC232_IN_SEL_M ((GPIO_FUNC232_IN_SEL_V)<<(GPIO_FUNC232_IN_SEL_S)) +#define GPIO_FUNC232_IN_SEL_V 0x3F +#define GPIO_FUNC232_IN_SEL_S 0 + +#define GPIO_FUNC233_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04d4) +/* GPIO_SIG233_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG233_IN_SEL (BIT(7)) +#define GPIO_SIG233_IN_SEL_M (BIT(7)) +#define GPIO_SIG233_IN_SEL_V 0x1 +#define GPIO_SIG233_IN_SEL_S 7 +/* GPIO_FUNC233_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC233_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC233_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC233_IN_INV_SEL_V 0x1 +#define GPIO_FUNC233_IN_INV_SEL_S 6 +/* GPIO_FUNC233_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC233_IN_SEL 0x0000003F +#define GPIO_FUNC233_IN_SEL_M ((GPIO_FUNC233_IN_SEL_V)<<(GPIO_FUNC233_IN_SEL_S)) +#define GPIO_FUNC233_IN_SEL_V 0x3F +#define GPIO_FUNC233_IN_SEL_S 0 + +#define GPIO_FUNC234_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04d8) +/* GPIO_SIG234_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG234_IN_SEL (BIT(7)) +#define GPIO_SIG234_IN_SEL_M (BIT(7)) +#define GPIO_SIG234_IN_SEL_V 0x1 +#define GPIO_SIG234_IN_SEL_S 7 +/* GPIO_FUNC234_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC234_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC234_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC234_IN_INV_SEL_V 0x1 +#define GPIO_FUNC234_IN_INV_SEL_S 6 +/* GPIO_FUNC234_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC234_IN_SEL 0x0000003F +#define GPIO_FUNC234_IN_SEL_M ((GPIO_FUNC234_IN_SEL_V)<<(GPIO_FUNC234_IN_SEL_S)) +#define GPIO_FUNC234_IN_SEL_V 0x3F +#define GPIO_FUNC234_IN_SEL_S 0 + +#define GPIO_FUNC235_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04dc) +/* GPIO_SIG235_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG235_IN_SEL (BIT(7)) +#define GPIO_SIG235_IN_SEL_M (BIT(7)) +#define GPIO_SIG235_IN_SEL_V 0x1 +#define GPIO_SIG235_IN_SEL_S 7 +/* GPIO_FUNC235_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC235_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC235_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC235_IN_INV_SEL_V 0x1 +#define GPIO_FUNC235_IN_INV_SEL_S 6 +/* GPIO_FUNC235_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC235_IN_SEL 0x0000003F +#define GPIO_FUNC235_IN_SEL_M ((GPIO_FUNC235_IN_SEL_V)<<(GPIO_FUNC235_IN_SEL_S)) +#define GPIO_FUNC235_IN_SEL_V 0x3F +#define GPIO_FUNC235_IN_SEL_S 0 + +#define GPIO_FUNC236_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04e0) +/* GPIO_SIG236_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG236_IN_SEL (BIT(7)) +#define GPIO_SIG236_IN_SEL_M (BIT(7)) +#define GPIO_SIG236_IN_SEL_V 0x1 +#define GPIO_SIG236_IN_SEL_S 7 +/* GPIO_FUNC236_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC236_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC236_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC236_IN_INV_SEL_V 0x1 +#define GPIO_FUNC236_IN_INV_SEL_S 6 +/* GPIO_FUNC236_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC236_IN_SEL 0x0000003F +#define GPIO_FUNC236_IN_SEL_M ((GPIO_FUNC236_IN_SEL_V)<<(GPIO_FUNC236_IN_SEL_S)) +#define GPIO_FUNC236_IN_SEL_V 0x3F +#define GPIO_FUNC236_IN_SEL_S 0 + +#define GPIO_FUNC237_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04e4) +/* GPIO_SIG237_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG237_IN_SEL (BIT(7)) +#define GPIO_SIG237_IN_SEL_M (BIT(7)) +#define GPIO_SIG237_IN_SEL_V 0x1 +#define GPIO_SIG237_IN_SEL_S 7 +/* GPIO_FUNC237_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC237_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC237_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC237_IN_INV_SEL_V 0x1 +#define GPIO_FUNC237_IN_INV_SEL_S 6 +/* GPIO_FUNC237_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC237_IN_SEL 0x0000003F +#define GPIO_FUNC237_IN_SEL_M ((GPIO_FUNC237_IN_SEL_V)<<(GPIO_FUNC237_IN_SEL_S)) +#define GPIO_FUNC237_IN_SEL_V 0x3F +#define GPIO_FUNC237_IN_SEL_S 0 + +#define GPIO_FUNC238_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04e8) +/* GPIO_SIG238_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG238_IN_SEL (BIT(7)) +#define GPIO_SIG238_IN_SEL_M (BIT(7)) +#define GPIO_SIG238_IN_SEL_V 0x1 +#define GPIO_SIG238_IN_SEL_S 7 +/* GPIO_FUNC238_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC238_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC238_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC238_IN_INV_SEL_V 0x1 +#define GPIO_FUNC238_IN_INV_SEL_S 6 +/* GPIO_FUNC238_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC238_IN_SEL 0x0000003F +#define GPIO_FUNC238_IN_SEL_M ((GPIO_FUNC238_IN_SEL_V)<<(GPIO_FUNC238_IN_SEL_S)) +#define GPIO_FUNC238_IN_SEL_V 0x3F +#define GPIO_FUNC238_IN_SEL_S 0 + +#define GPIO_FUNC239_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04ec) +/* GPIO_SIG239_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG239_IN_SEL (BIT(7)) +#define GPIO_SIG239_IN_SEL_M (BIT(7)) +#define GPIO_SIG239_IN_SEL_V 0x1 +#define GPIO_SIG239_IN_SEL_S 7 +/* GPIO_FUNC239_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC239_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC239_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC239_IN_INV_SEL_V 0x1 +#define GPIO_FUNC239_IN_INV_SEL_S 6 +/* GPIO_FUNC239_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC239_IN_SEL 0x0000003F +#define GPIO_FUNC239_IN_SEL_M ((GPIO_FUNC239_IN_SEL_V)<<(GPIO_FUNC239_IN_SEL_S)) +#define GPIO_FUNC239_IN_SEL_V 0x3F +#define GPIO_FUNC239_IN_SEL_S 0 + +#define GPIO_FUNC240_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04f0) +/* GPIO_SIG240_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG240_IN_SEL (BIT(7)) +#define GPIO_SIG240_IN_SEL_M (BIT(7)) +#define GPIO_SIG240_IN_SEL_V 0x1 +#define GPIO_SIG240_IN_SEL_S 7 +/* GPIO_FUNC240_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC240_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC240_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC240_IN_INV_SEL_V 0x1 +#define GPIO_FUNC240_IN_INV_SEL_S 6 +/* GPIO_FUNC240_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC240_IN_SEL 0x0000003F +#define GPIO_FUNC240_IN_SEL_M ((GPIO_FUNC240_IN_SEL_V)<<(GPIO_FUNC240_IN_SEL_S)) +#define GPIO_FUNC240_IN_SEL_V 0x3F +#define GPIO_FUNC240_IN_SEL_S 0 + +#define GPIO_FUNC241_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04f4) +/* GPIO_SIG241_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG241_IN_SEL (BIT(7)) +#define GPIO_SIG241_IN_SEL_M (BIT(7)) +#define GPIO_SIG241_IN_SEL_V 0x1 +#define GPIO_SIG241_IN_SEL_S 7 +/* GPIO_FUNC241_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC241_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC241_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC241_IN_INV_SEL_V 0x1 +#define GPIO_FUNC241_IN_INV_SEL_S 6 +/* GPIO_FUNC241_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC241_IN_SEL 0x0000003F +#define GPIO_FUNC241_IN_SEL_M ((GPIO_FUNC241_IN_SEL_V)<<(GPIO_FUNC241_IN_SEL_S)) +#define GPIO_FUNC241_IN_SEL_V 0x3F +#define GPIO_FUNC241_IN_SEL_S 0 + +#define GPIO_FUNC242_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04f8) +/* GPIO_SIG242_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG242_IN_SEL (BIT(7)) +#define GPIO_SIG242_IN_SEL_M (BIT(7)) +#define GPIO_SIG242_IN_SEL_V 0x1 +#define GPIO_SIG242_IN_SEL_S 7 +/* GPIO_FUNC242_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC242_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC242_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC242_IN_INV_SEL_V 0x1 +#define GPIO_FUNC242_IN_INV_SEL_S 6 +/* GPIO_FUNC242_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC242_IN_SEL 0x0000003F +#define GPIO_FUNC242_IN_SEL_M ((GPIO_FUNC242_IN_SEL_V)<<(GPIO_FUNC242_IN_SEL_S)) +#define GPIO_FUNC242_IN_SEL_V 0x3F +#define GPIO_FUNC242_IN_SEL_S 0 + +#define GPIO_FUNC243_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04fc) +/* GPIO_SIG243_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG243_IN_SEL (BIT(7)) +#define GPIO_SIG243_IN_SEL_M (BIT(7)) +#define GPIO_SIG243_IN_SEL_V 0x1 +#define GPIO_SIG243_IN_SEL_S 7 +/* GPIO_FUNC243_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC243_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC243_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC243_IN_INV_SEL_V 0x1 +#define GPIO_FUNC243_IN_INV_SEL_S 6 +/* GPIO_FUNC243_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC243_IN_SEL 0x0000003F +#define GPIO_FUNC243_IN_SEL_M ((GPIO_FUNC243_IN_SEL_V)<<(GPIO_FUNC243_IN_SEL_S)) +#define GPIO_FUNC243_IN_SEL_V 0x3F +#define GPIO_FUNC243_IN_SEL_S 0 + +#define GPIO_FUNC244_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0500) +/* GPIO_SIG244_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG244_IN_SEL (BIT(7)) +#define GPIO_SIG244_IN_SEL_M (BIT(7)) +#define GPIO_SIG244_IN_SEL_V 0x1 +#define GPIO_SIG244_IN_SEL_S 7 +/* GPIO_FUNC244_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC244_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC244_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC244_IN_INV_SEL_V 0x1 +#define GPIO_FUNC244_IN_INV_SEL_S 6 +/* GPIO_FUNC244_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC244_IN_SEL 0x0000003F +#define GPIO_FUNC244_IN_SEL_M ((GPIO_FUNC244_IN_SEL_V)<<(GPIO_FUNC244_IN_SEL_S)) +#define GPIO_FUNC244_IN_SEL_V 0x3F +#define GPIO_FUNC244_IN_SEL_S 0 + +#define GPIO_FUNC245_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0504) +/* GPIO_SIG245_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG245_IN_SEL (BIT(7)) +#define GPIO_SIG245_IN_SEL_M (BIT(7)) +#define GPIO_SIG245_IN_SEL_V 0x1 +#define GPIO_SIG245_IN_SEL_S 7 +/* GPIO_FUNC245_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC245_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC245_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC245_IN_INV_SEL_V 0x1 +#define GPIO_FUNC245_IN_INV_SEL_S 6 +/* GPIO_FUNC245_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC245_IN_SEL 0x0000003F +#define GPIO_FUNC245_IN_SEL_M ((GPIO_FUNC245_IN_SEL_V)<<(GPIO_FUNC245_IN_SEL_S)) +#define GPIO_FUNC245_IN_SEL_V 0x3F +#define GPIO_FUNC245_IN_SEL_S 0 + +#define GPIO_FUNC246_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0508) +/* GPIO_SIG246_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG246_IN_SEL (BIT(7)) +#define GPIO_SIG246_IN_SEL_M (BIT(7)) +#define GPIO_SIG246_IN_SEL_V 0x1 +#define GPIO_SIG246_IN_SEL_S 7 +/* GPIO_FUNC246_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC246_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC246_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC246_IN_INV_SEL_V 0x1 +#define GPIO_FUNC246_IN_INV_SEL_S 6 +/* GPIO_FUNC246_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC246_IN_SEL 0x0000003F +#define GPIO_FUNC246_IN_SEL_M ((GPIO_FUNC246_IN_SEL_V)<<(GPIO_FUNC246_IN_SEL_S)) +#define GPIO_FUNC246_IN_SEL_V 0x3F +#define GPIO_FUNC246_IN_SEL_S 0 + +#define GPIO_FUNC247_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x050c) +/* GPIO_SIG247_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG247_IN_SEL (BIT(7)) +#define GPIO_SIG247_IN_SEL_M (BIT(7)) +#define GPIO_SIG247_IN_SEL_V 0x1 +#define GPIO_SIG247_IN_SEL_S 7 +/* GPIO_FUNC247_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC247_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC247_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC247_IN_INV_SEL_V 0x1 +#define GPIO_FUNC247_IN_INV_SEL_S 6 +/* GPIO_FUNC247_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC247_IN_SEL 0x0000003F +#define GPIO_FUNC247_IN_SEL_M ((GPIO_FUNC247_IN_SEL_V)<<(GPIO_FUNC247_IN_SEL_S)) +#define GPIO_FUNC247_IN_SEL_V 0x3F +#define GPIO_FUNC247_IN_SEL_S 0 + +#define GPIO_FUNC248_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0510) +/* GPIO_SIG248_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG248_IN_SEL (BIT(7)) +#define GPIO_SIG248_IN_SEL_M (BIT(7)) +#define GPIO_SIG248_IN_SEL_V 0x1 +#define GPIO_SIG248_IN_SEL_S 7 +/* GPIO_FUNC248_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC248_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC248_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC248_IN_INV_SEL_V 0x1 +#define GPIO_FUNC248_IN_INV_SEL_S 6 +/* GPIO_FUNC248_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC248_IN_SEL 0x0000003F +#define GPIO_FUNC248_IN_SEL_M ((GPIO_FUNC248_IN_SEL_V)<<(GPIO_FUNC248_IN_SEL_S)) +#define GPIO_FUNC248_IN_SEL_V 0x3F +#define GPIO_FUNC248_IN_SEL_S 0 + +#define GPIO_FUNC249_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0514) +/* GPIO_SIG249_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG249_IN_SEL (BIT(7)) +#define GPIO_SIG249_IN_SEL_M (BIT(7)) +#define GPIO_SIG249_IN_SEL_V 0x1 +#define GPIO_SIG249_IN_SEL_S 7 +/* GPIO_FUNC249_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC249_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC249_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC249_IN_INV_SEL_V 0x1 +#define GPIO_FUNC249_IN_INV_SEL_S 6 +/* GPIO_FUNC249_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC249_IN_SEL 0x0000003F +#define GPIO_FUNC249_IN_SEL_M ((GPIO_FUNC249_IN_SEL_V)<<(GPIO_FUNC249_IN_SEL_S)) +#define GPIO_FUNC249_IN_SEL_V 0x3F +#define GPIO_FUNC249_IN_SEL_S 0 + +#define GPIO_FUNC250_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0518) +/* GPIO_SIG250_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG250_IN_SEL (BIT(7)) +#define GPIO_SIG250_IN_SEL_M (BIT(7)) +#define GPIO_SIG250_IN_SEL_V 0x1 +#define GPIO_SIG250_IN_SEL_S 7 +/* GPIO_FUNC250_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC250_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC250_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC250_IN_INV_SEL_V 0x1 +#define GPIO_FUNC250_IN_INV_SEL_S 6 +/* GPIO_FUNC250_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC250_IN_SEL 0x0000003F +#define GPIO_FUNC250_IN_SEL_M ((GPIO_FUNC250_IN_SEL_V)<<(GPIO_FUNC250_IN_SEL_S)) +#define GPIO_FUNC250_IN_SEL_V 0x3F +#define GPIO_FUNC250_IN_SEL_S 0 + +#define GPIO_FUNC251_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x051c) +/* GPIO_SIG251_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG251_IN_SEL (BIT(7)) +#define GPIO_SIG251_IN_SEL_M (BIT(7)) +#define GPIO_SIG251_IN_SEL_V 0x1 +#define GPIO_SIG251_IN_SEL_S 7 +/* GPIO_FUNC251_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC251_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC251_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC251_IN_INV_SEL_V 0x1 +#define GPIO_FUNC251_IN_INV_SEL_S 6 +/* GPIO_FUNC251_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC251_IN_SEL 0x0000003F +#define GPIO_FUNC251_IN_SEL_M ((GPIO_FUNC251_IN_SEL_V)<<(GPIO_FUNC251_IN_SEL_S)) +#define GPIO_FUNC251_IN_SEL_V 0x3F +#define GPIO_FUNC251_IN_SEL_S 0 + +#define GPIO_FUNC252_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0520) +/* GPIO_SIG252_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG252_IN_SEL (BIT(7)) +#define GPIO_SIG252_IN_SEL_M (BIT(7)) +#define GPIO_SIG252_IN_SEL_V 0x1 +#define GPIO_SIG252_IN_SEL_S 7 +/* GPIO_FUNC252_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC252_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC252_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC252_IN_INV_SEL_V 0x1 +#define GPIO_FUNC252_IN_INV_SEL_S 6 +/* GPIO_FUNC252_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC252_IN_SEL 0x0000003F +#define GPIO_FUNC252_IN_SEL_M ((GPIO_FUNC252_IN_SEL_V)<<(GPIO_FUNC252_IN_SEL_S)) +#define GPIO_FUNC252_IN_SEL_V 0x3F +#define GPIO_FUNC252_IN_SEL_S 0 + +#define GPIO_FUNC253_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0524) +/* GPIO_SIG253_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG253_IN_SEL (BIT(7)) +#define GPIO_SIG253_IN_SEL_M (BIT(7)) +#define GPIO_SIG253_IN_SEL_V 0x1 +#define GPIO_SIG253_IN_SEL_S 7 +/* GPIO_FUNC253_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC253_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC253_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC253_IN_INV_SEL_V 0x1 +#define GPIO_FUNC253_IN_INV_SEL_S 6 +/* GPIO_FUNC253_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC253_IN_SEL 0x0000003F +#define GPIO_FUNC253_IN_SEL_M ((GPIO_FUNC253_IN_SEL_V)<<(GPIO_FUNC253_IN_SEL_S)) +#define GPIO_FUNC253_IN_SEL_V 0x3F +#define GPIO_FUNC253_IN_SEL_S 0 + +#define GPIO_FUNC254_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0528) +/* GPIO_SIG254_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG254_IN_SEL (BIT(7)) +#define GPIO_SIG254_IN_SEL_M (BIT(7)) +#define GPIO_SIG254_IN_SEL_V 0x1 +#define GPIO_SIG254_IN_SEL_S 7 +/* GPIO_FUNC254_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC254_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC254_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC254_IN_INV_SEL_V 0x1 +#define GPIO_FUNC254_IN_INV_SEL_S 6 +/* GPIO_FUNC254_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC254_IN_SEL 0x0000003F +#define GPIO_FUNC254_IN_SEL_M ((GPIO_FUNC254_IN_SEL_V)<<(GPIO_FUNC254_IN_SEL_S)) +#define GPIO_FUNC254_IN_SEL_V 0x3F +#define GPIO_FUNC254_IN_SEL_S 0 + +#define GPIO_FUNC255_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x052c) +/* GPIO_SIG255_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/*description: if the slow signal bypass the io matrix or not if you want setting + the value to 1*/ +#define GPIO_SIG255_IN_SEL (BIT(7)) +#define GPIO_SIG255_IN_SEL_M (BIT(7)) +#define GPIO_SIG255_IN_SEL_V 0x1 +#define GPIO_SIG255_IN_SEL_S 7 +/* GPIO_FUNC255_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/*description: revert the value of the input if you want to revert please set the value to 1*/ +#define GPIO_FUNC255_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC255_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC255_IN_INV_SEL_V 0x1 +#define GPIO_FUNC255_IN_INV_SEL_S 6 +/* GPIO_FUNC255_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/*description: select one of the 256 inputs*/ +#define GPIO_FUNC255_IN_SEL 0x0000003F +#define GPIO_FUNC255_IN_SEL_M ((GPIO_FUNC255_IN_SEL_V)<<(GPIO_FUNC255_IN_SEL_S)) +#define GPIO_FUNC255_IN_SEL_V 0x3F +#define GPIO_FUNC255_IN_SEL_S 0 + +#define GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0530) +/* GPIO_FUNC0_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC0_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC0_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC0_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC0_OEN_INV_SEL_S 11 +/* GPIO_FUNC0_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC0_OEN_SEL (BIT(10)) +#define GPIO_FUNC0_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC0_OEN_SEL_V 0x1 +#define GPIO_FUNC0_OEN_SEL_S 10 +/* GPIO_FUNC0_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC0_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC0_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC0_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC0_OUT_INV_SEL_S 9 +/* GPIO_FUNC0_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC0_OUT_SEL 0x000001FF +#define GPIO_FUNC0_OUT_SEL_M ((GPIO_FUNC0_OUT_SEL_V)<<(GPIO_FUNC0_OUT_SEL_S)) +#define GPIO_FUNC0_OUT_SEL_V 0x1FF +#define GPIO_FUNC0_OUT_SEL_S 0 + +#define GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0534) +/* GPIO_FUNC1_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC1_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC1_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC1_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC1_OEN_INV_SEL_S 11 +/* GPIO_FUNC1_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC1_OEN_SEL (BIT(10)) +#define GPIO_FUNC1_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC1_OEN_SEL_V 0x1 +#define GPIO_FUNC1_OEN_SEL_S 10 +/* GPIO_FUNC1_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC1_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC1_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC1_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC1_OUT_INV_SEL_S 9 +/* GPIO_FUNC1_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC1_OUT_SEL 0x000001FF +#define GPIO_FUNC1_OUT_SEL_M ((GPIO_FUNC1_OUT_SEL_V)<<(GPIO_FUNC1_OUT_SEL_S)) +#define GPIO_FUNC1_OUT_SEL_V 0x1FF +#define GPIO_FUNC1_OUT_SEL_S 0 + +#define GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0538) +/* GPIO_FUNC2_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC2_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC2_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC2_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC2_OEN_INV_SEL_S 11 +/* GPIO_FUNC2_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC2_OEN_SEL (BIT(10)) +#define GPIO_FUNC2_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC2_OEN_SEL_V 0x1 +#define GPIO_FUNC2_OEN_SEL_S 10 +/* GPIO_FUNC2_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC2_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC2_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC2_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC2_OUT_INV_SEL_S 9 +/* GPIO_FUNC2_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC2_OUT_SEL 0x000001FF +#define GPIO_FUNC2_OUT_SEL_M ((GPIO_FUNC2_OUT_SEL_V)<<(GPIO_FUNC2_OUT_SEL_S)) +#define GPIO_FUNC2_OUT_SEL_V 0x1FF +#define GPIO_FUNC2_OUT_SEL_S 0 + +#define GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x053c) +/* GPIO_FUNC3_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC3_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC3_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC3_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC3_OEN_INV_SEL_S 11 +/* GPIO_FUNC3_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC3_OEN_SEL (BIT(10)) +#define GPIO_FUNC3_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC3_OEN_SEL_V 0x1 +#define GPIO_FUNC3_OEN_SEL_S 10 +/* GPIO_FUNC3_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC3_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC3_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC3_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC3_OUT_INV_SEL_S 9 +/* GPIO_FUNC3_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC3_OUT_SEL 0x000001FF +#define GPIO_FUNC3_OUT_SEL_M ((GPIO_FUNC3_OUT_SEL_V)<<(GPIO_FUNC3_OUT_SEL_S)) +#define GPIO_FUNC3_OUT_SEL_V 0x1FF +#define GPIO_FUNC3_OUT_SEL_S 0 + +#define GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0540) +/* GPIO_FUNC4_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC4_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC4_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC4_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC4_OEN_INV_SEL_S 11 +/* GPIO_FUNC4_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC4_OEN_SEL (BIT(10)) +#define GPIO_FUNC4_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC4_OEN_SEL_V 0x1 +#define GPIO_FUNC4_OEN_SEL_S 10 +/* GPIO_FUNC4_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC4_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC4_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC4_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC4_OUT_INV_SEL_S 9 +/* GPIO_FUNC4_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC4_OUT_SEL 0x000001FF +#define GPIO_FUNC4_OUT_SEL_M ((GPIO_FUNC4_OUT_SEL_V)<<(GPIO_FUNC4_OUT_SEL_S)) +#define GPIO_FUNC4_OUT_SEL_V 0x1FF +#define GPIO_FUNC4_OUT_SEL_S 0 + +#define GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0544) +/* GPIO_FUNC5_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC5_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC5_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC5_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC5_OEN_INV_SEL_S 11 +/* GPIO_FUNC5_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC5_OEN_SEL (BIT(10)) +#define GPIO_FUNC5_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC5_OEN_SEL_V 0x1 +#define GPIO_FUNC5_OEN_SEL_S 10 +/* GPIO_FUNC5_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC5_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC5_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC5_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC5_OUT_INV_SEL_S 9 +/* GPIO_FUNC5_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC5_OUT_SEL 0x000001FF +#define GPIO_FUNC5_OUT_SEL_M ((GPIO_FUNC5_OUT_SEL_V)<<(GPIO_FUNC5_OUT_SEL_S)) +#define GPIO_FUNC5_OUT_SEL_V 0x1FF +#define GPIO_FUNC5_OUT_SEL_S 0 + +#define GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0548) +/* GPIO_FUNC6_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC6_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC6_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC6_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC6_OEN_INV_SEL_S 11 +/* GPIO_FUNC6_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC6_OEN_SEL (BIT(10)) +#define GPIO_FUNC6_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC6_OEN_SEL_V 0x1 +#define GPIO_FUNC6_OEN_SEL_S 10 +/* GPIO_FUNC6_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC6_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC6_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC6_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC6_OUT_INV_SEL_S 9 +/* GPIO_FUNC6_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC6_OUT_SEL 0x000001FF +#define GPIO_FUNC6_OUT_SEL_M ((GPIO_FUNC6_OUT_SEL_V)<<(GPIO_FUNC6_OUT_SEL_S)) +#define GPIO_FUNC6_OUT_SEL_V 0x1FF +#define GPIO_FUNC6_OUT_SEL_S 0 + +#define GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x054c) +/* GPIO_FUNC7_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC7_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC7_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC7_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC7_OEN_INV_SEL_S 11 +/* GPIO_FUNC7_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC7_OEN_SEL (BIT(10)) +#define GPIO_FUNC7_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC7_OEN_SEL_V 0x1 +#define GPIO_FUNC7_OEN_SEL_S 10 +/* GPIO_FUNC7_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC7_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC7_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC7_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC7_OUT_INV_SEL_S 9 +/* GPIO_FUNC7_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC7_OUT_SEL 0x000001FF +#define GPIO_FUNC7_OUT_SEL_M ((GPIO_FUNC7_OUT_SEL_V)<<(GPIO_FUNC7_OUT_SEL_S)) +#define GPIO_FUNC7_OUT_SEL_V 0x1FF +#define GPIO_FUNC7_OUT_SEL_S 0 + +#define GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0550) +/* GPIO_FUNC8_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC8_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC8_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC8_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC8_OEN_INV_SEL_S 11 +/* GPIO_FUNC8_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC8_OEN_SEL (BIT(10)) +#define GPIO_FUNC8_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC8_OEN_SEL_V 0x1 +#define GPIO_FUNC8_OEN_SEL_S 10 +/* GPIO_FUNC8_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC8_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC8_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC8_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC8_OUT_INV_SEL_S 9 +/* GPIO_FUNC8_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC8_OUT_SEL 0x000001FF +#define GPIO_FUNC8_OUT_SEL_M ((GPIO_FUNC8_OUT_SEL_V)<<(GPIO_FUNC8_OUT_SEL_S)) +#define GPIO_FUNC8_OUT_SEL_V 0x1FF +#define GPIO_FUNC8_OUT_SEL_S 0 + +#define GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0554) +/* GPIO_FUNC9_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC9_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC9_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC9_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC9_OEN_INV_SEL_S 11 +/* GPIO_FUNC9_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC9_OEN_SEL (BIT(10)) +#define GPIO_FUNC9_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC9_OEN_SEL_V 0x1 +#define GPIO_FUNC9_OEN_SEL_S 10 +/* GPIO_FUNC9_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC9_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC9_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC9_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC9_OUT_INV_SEL_S 9 +/* GPIO_FUNC9_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC9_OUT_SEL 0x000001FF +#define GPIO_FUNC9_OUT_SEL_M ((GPIO_FUNC9_OUT_SEL_V)<<(GPIO_FUNC9_OUT_SEL_S)) +#define GPIO_FUNC9_OUT_SEL_V 0x1FF +#define GPIO_FUNC9_OUT_SEL_S 0 + +#define GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0558) +/* GPIO_FUNC10_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC10_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC10_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC10_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC10_OEN_INV_SEL_S 11 +/* GPIO_FUNC10_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC10_OEN_SEL (BIT(10)) +#define GPIO_FUNC10_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC10_OEN_SEL_V 0x1 +#define GPIO_FUNC10_OEN_SEL_S 10 +/* GPIO_FUNC10_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC10_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC10_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC10_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC10_OUT_INV_SEL_S 9 +/* GPIO_FUNC10_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC10_OUT_SEL 0x000001FF +#define GPIO_FUNC10_OUT_SEL_M ((GPIO_FUNC10_OUT_SEL_V)<<(GPIO_FUNC10_OUT_SEL_S)) +#define GPIO_FUNC10_OUT_SEL_V 0x1FF +#define GPIO_FUNC10_OUT_SEL_S 0 + +#define GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x055c) +/* GPIO_FUNC11_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC11_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC11_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC11_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC11_OEN_INV_SEL_S 11 +/* GPIO_FUNC11_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC11_OEN_SEL (BIT(10)) +#define GPIO_FUNC11_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC11_OEN_SEL_V 0x1 +#define GPIO_FUNC11_OEN_SEL_S 10 +/* GPIO_FUNC11_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC11_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC11_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC11_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC11_OUT_INV_SEL_S 9 +/* GPIO_FUNC11_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC11_OUT_SEL 0x000001FF +#define GPIO_FUNC11_OUT_SEL_M ((GPIO_FUNC11_OUT_SEL_V)<<(GPIO_FUNC11_OUT_SEL_S)) +#define GPIO_FUNC11_OUT_SEL_V 0x1FF +#define GPIO_FUNC11_OUT_SEL_S 0 + +#define GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0560) +/* GPIO_FUNC12_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC12_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC12_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC12_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC12_OEN_INV_SEL_S 11 +/* GPIO_FUNC12_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC12_OEN_SEL (BIT(10)) +#define GPIO_FUNC12_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC12_OEN_SEL_V 0x1 +#define GPIO_FUNC12_OEN_SEL_S 10 +/* GPIO_FUNC12_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC12_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC12_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC12_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC12_OUT_INV_SEL_S 9 +/* GPIO_FUNC12_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC12_OUT_SEL 0x000001FF +#define GPIO_FUNC12_OUT_SEL_M ((GPIO_FUNC12_OUT_SEL_V)<<(GPIO_FUNC12_OUT_SEL_S)) +#define GPIO_FUNC12_OUT_SEL_V 0x1FF +#define GPIO_FUNC12_OUT_SEL_S 0 + +#define GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0564) +/* GPIO_FUNC13_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC13_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC13_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC13_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC13_OEN_INV_SEL_S 11 +/* GPIO_FUNC13_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC13_OEN_SEL (BIT(10)) +#define GPIO_FUNC13_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC13_OEN_SEL_V 0x1 +#define GPIO_FUNC13_OEN_SEL_S 10 +/* GPIO_FUNC13_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC13_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC13_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC13_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC13_OUT_INV_SEL_S 9 +/* GPIO_FUNC13_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC13_OUT_SEL 0x000001FF +#define GPIO_FUNC13_OUT_SEL_M ((GPIO_FUNC13_OUT_SEL_V)<<(GPIO_FUNC13_OUT_SEL_S)) +#define GPIO_FUNC13_OUT_SEL_V 0x1FF +#define GPIO_FUNC13_OUT_SEL_S 0 + +#define GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0568) +/* GPIO_FUNC14_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC14_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC14_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC14_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC14_OEN_INV_SEL_S 11 +/* GPIO_FUNC14_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC14_OEN_SEL (BIT(10)) +#define GPIO_FUNC14_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC14_OEN_SEL_V 0x1 +#define GPIO_FUNC14_OEN_SEL_S 10 +/* GPIO_FUNC14_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC14_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC14_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC14_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC14_OUT_INV_SEL_S 9 +/* GPIO_FUNC14_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC14_OUT_SEL 0x000001FF +#define GPIO_FUNC14_OUT_SEL_M ((GPIO_FUNC14_OUT_SEL_V)<<(GPIO_FUNC14_OUT_SEL_S)) +#define GPIO_FUNC14_OUT_SEL_V 0x1FF +#define GPIO_FUNC14_OUT_SEL_S 0 + +#define GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x056c) +/* GPIO_FUNC15_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC15_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC15_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC15_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC15_OEN_INV_SEL_S 11 +/* GPIO_FUNC15_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC15_OEN_SEL (BIT(10)) +#define GPIO_FUNC15_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC15_OEN_SEL_V 0x1 +#define GPIO_FUNC15_OEN_SEL_S 10 +/* GPIO_FUNC15_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC15_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC15_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC15_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC15_OUT_INV_SEL_S 9 +/* GPIO_FUNC15_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC15_OUT_SEL 0x000001FF +#define GPIO_FUNC15_OUT_SEL_M ((GPIO_FUNC15_OUT_SEL_V)<<(GPIO_FUNC15_OUT_SEL_S)) +#define GPIO_FUNC15_OUT_SEL_V 0x1FF +#define GPIO_FUNC15_OUT_SEL_S 0 + +#define GPIO_FUNC16_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0570) +/* GPIO_FUNC16_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC16_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC16_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC16_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC16_OEN_INV_SEL_S 11 +/* GPIO_FUNC16_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC16_OEN_SEL (BIT(10)) +#define GPIO_FUNC16_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC16_OEN_SEL_V 0x1 +#define GPIO_FUNC16_OEN_SEL_S 10 +/* GPIO_FUNC16_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC16_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC16_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC16_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC16_OUT_INV_SEL_S 9 +/* GPIO_FUNC16_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC16_OUT_SEL 0x000001FF +#define GPIO_FUNC16_OUT_SEL_M ((GPIO_FUNC16_OUT_SEL_V)<<(GPIO_FUNC16_OUT_SEL_S)) +#define GPIO_FUNC16_OUT_SEL_V 0x1FF +#define GPIO_FUNC16_OUT_SEL_S 0 + +#define GPIO_FUNC17_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0574) +/* GPIO_FUNC17_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC17_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC17_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC17_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC17_OEN_INV_SEL_S 11 +/* GPIO_FUNC17_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC17_OEN_SEL (BIT(10)) +#define GPIO_FUNC17_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC17_OEN_SEL_V 0x1 +#define GPIO_FUNC17_OEN_SEL_S 10 +/* GPIO_FUNC17_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC17_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC17_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC17_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC17_OUT_INV_SEL_S 9 +/* GPIO_FUNC17_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC17_OUT_SEL 0x000001FF +#define GPIO_FUNC17_OUT_SEL_M ((GPIO_FUNC17_OUT_SEL_V)<<(GPIO_FUNC17_OUT_SEL_S)) +#define GPIO_FUNC17_OUT_SEL_V 0x1FF +#define GPIO_FUNC17_OUT_SEL_S 0 + +#define GPIO_FUNC18_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0578) +/* GPIO_FUNC18_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC18_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC18_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC18_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC18_OEN_INV_SEL_S 11 +/* GPIO_FUNC18_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC18_OEN_SEL (BIT(10)) +#define GPIO_FUNC18_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC18_OEN_SEL_V 0x1 +#define GPIO_FUNC18_OEN_SEL_S 10 +/* GPIO_FUNC18_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC18_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC18_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC18_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC18_OUT_INV_SEL_S 9 +/* GPIO_FUNC18_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC18_OUT_SEL 0x000001FF +#define GPIO_FUNC18_OUT_SEL_M ((GPIO_FUNC18_OUT_SEL_V)<<(GPIO_FUNC18_OUT_SEL_S)) +#define GPIO_FUNC18_OUT_SEL_V 0x1FF +#define GPIO_FUNC18_OUT_SEL_S 0 + +#define GPIO_FUNC19_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x057c) +/* GPIO_FUNC19_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC19_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC19_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC19_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC19_OEN_INV_SEL_S 11 +/* GPIO_FUNC19_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC19_OEN_SEL (BIT(10)) +#define GPIO_FUNC19_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC19_OEN_SEL_V 0x1 +#define GPIO_FUNC19_OEN_SEL_S 10 +/* GPIO_FUNC19_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC19_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC19_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC19_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC19_OUT_INV_SEL_S 9 +/* GPIO_FUNC19_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC19_OUT_SEL 0x000001FF +#define GPIO_FUNC19_OUT_SEL_M ((GPIO_FUNC19_OUT_SEL_V)<<(GPIO_FUNC19_OUT_SEL_S)) +#define GPIO_FUNC19_OUT_SEL_V 0x1FF +#define GPIO_FUNC19_OUT_SEL_S 0 + +#define GPIO_FUNC20_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0580) +/* GPIO_FUNC20_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC20_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC20_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC20_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC20_OEN_INV_SEL_S 11 +/* GPIO_FUNC20_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC20_OEN_SEL (BIT(10)) +#define GPIO_FUNC20_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC20_OEN_SEL_V 0x1 +#define GPIO_FUNC20_OEN_SEL_S 10 +/* GPIO_FUNC20_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC20_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC20_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC20_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC20_OUT_INV_SEL_S 9 +/* GPIO_FUNC20_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC20_OUT_SEL 0x000001FF +#define GPIO_FUNC20_OUT_SEL_M ((GPIO_FUNC20_OUT_SEL_V)<<(GPIO_FUNC20_OUT_SEL_S)) +#define GPIO_FUNC20_OUT_SEL_V 0x1FF +#define GPIO_FUNC20_OUT_SEL_S 0 + +#define GPIO_FUNC21_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0584) +/* GPIO_FUNC21_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC21_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC21_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC21_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC21_OEN_INV_SEL_S 11 +/* GPIO_FUNC21_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC21_OEN_SEL (BIT(10)) +#define GPIO_FUNC21_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC21_OEN_SEL_V 0x1 +#define GPIO_FUNC21_OEN_SEL_S 10 +/* GPIO_FUNC21_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC21_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC21_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC21_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC21_OUT_INV_SEL_S 9 +/* GPIO_FUNC21_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC21_OUT_SEL 0x000001FF +#define GPIO_FUNC21_OUT_SEL_M ((GPIO_FUNC21_OUT_SEL_V)<<(GPIO_FUNC21_OUT_SEL_S)) +#define GPIO_FUNC21_OUT_SEL_V 0x1FF +#define GPIO_FUNC21_OUT_SEL_S 0 + +#define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0588) +/* GPIO_FUNC22_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC22_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC22_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC22_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC22_OEN_INV_SEL_S 11 +/* GPIO_FUNC22_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC22_OEN_SEL (BIT(10)) +#define GPIO_FUNC22_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC22_OEN_SEL_V 0x1 +#define GPIO_FUNC22_OEN_SEL_S 10 +/* GPIO_FUNC22_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC22_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC22_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC22_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC22_OUT_INV_SEL_S 9 +/* GPIO_FUNC22_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC22_OUT_SEL 0x000001FF +#define GPIO_FUNC22_OUT_SEL_M ((GPIO_FUNC22_OUT_SEL_V)<<(GPIO_FUNC22_OUT_SEL_S)) +#define GPIO_FUNC22_OUT_SEL_V 0x1FF +#define GPIO_FUNC22_OUT_SEL_S 0 + +#define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x058c) +/* GPIO_FUNC23_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC23_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC23_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC23_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC23_OEN_INV_SEL_S 11 +/* GPIO_FUNC23_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC23_OEN_SEL (BIT(10)) +#define GPIO_FUNC23_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC23_OEN_SEL_V 0x1 +#define GPIO_FUNC23_OEN_SEL_S 10 +/* GPIO_FUNC23_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC23_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC23_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC23_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC23_OUT_INV_SEL_S 9 +/* GPIO_FUNC23_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC23_OUT_SEL 0x000001FF +#define GPIO_FUNC23_OUT_SEL_M ((GPIO_FUNC23_OUT_SEL_V)<<(GPIO_FUNC23_OUT_SEL_S)) +#define GPIO_FUNC23_OUT_SEL_V 0x1FF +#define GPIO_FUNC23_OUT_SEL_S 0 + +#define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0590) +/* GPIO_FUNC24_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC24_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC24_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC24_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC24_OEN_INV_SEL_S 11 +/* GPIO_FUNC24_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC24_OEN_SEL (BIT(10)) +#define GPIO_FUNC24_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC24_OEN_SEL_V 0x1 +#define GPIO_FUNC24_OEN_SEL_S 10 +/* GPIO_FUNC24_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC24_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC24_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC24_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC24_OUT_INV_SEL_S 9 +/* GPIO_FUNC24_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC24_OUT_SEL 0x000001FF +#define GPIO_FUNC24_OUT_SEL_M ((GPIO_FUNC24_OUT_SEL_V)<<(GPIO_FUNC24_OUT_SEL_S)) +#define GPIO_FUNC24_OUT_SEL_V 0x1FF +#define GPIO_FUNC24_OUT_SEL_S 0 + +#define GPIO_FUNC25_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0594) +/* GPIO_FUNC25_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC25_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC25_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC25_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC25_OEN_INV_SEL_S 11 +/* GPIO_FUNC25_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC25_OEN_SEL (BIT(10)) +#define GPIO_FUNC25_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC25_OEN_SEL_V 0x1 +#define GPIO_FUNC25_OEN_SEL_S 10 +/* GPIO_FUNC25_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC25_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC25_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC25_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC25_OUT_INV_SEL_S 9 +/* GPIO_FUNC25_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC25_OUT_SEL 0x000001FF +#define GPIO_FUNC25_OUT_SEL_M ((GPIO_FUNC25_OUT_SEL_V)<<(GPIO_FUNC25_OUT_SEL_S)) +#define GPIO_FUNC25_OUT_SEL_V 0x1FF +#define GPIO_FUNC25_OUT_SEL_S 0 + +#define GPIO_FUNC26_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0598) +/* GPIO_FUNC26_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC26_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC26_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC26_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC26_OEN_INV_SEL_S 11 +/* GPIO_FUNC26_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC26_OEN_SEL (BIT(10)) +#define GPIO_FUNC26_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC26_OEN_SEL_V 0x1 +#define GPIO_FUNC26_OEN_SEL_S 10 +/* GPIO_FUNC26_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC26_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC26_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC26_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC26_OUT_INV_SEL_S 9 +/* GPIO_FUNC26_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC26_OUT_SEL 0x000001FF +#define GPIO_FUNC26_OUT_SEL_M ((GPIO_FUNC26_OUT_SEL_V)<<(GPIO_FUNC26_OUT_SEL_S)) +#define GPIO_FUNC26_OUT_SEL_V 0x1FF +#define GPIO_FUNC26_OUT_SEL_S 0 + +#define GPIO_FUNC27_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x059c) +/* GPIO_FUNC27_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC27_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC27_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC27_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC27_OEN_INV_SEL_S 11 +/* GPIO_FUNC27_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC27_OEN_SEL (BIT(10)) +#define GPIO_FUNC27_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC27_OEN_SEL_V 0x1 +#define GPIO_FUNC27_OEN_SEL_S 10 +/* GPIO_FUNC27_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC27_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC27_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC27_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC27_OUT_INV_SEL_S 9 +/* GPIO_FUNC27_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC27_OUT_SEL 0x000001FF +#define GPIO_FUNC27_OUT_SEL_M ((GPIO_FUNC27_OUT_SEL_V)<<(GPIO_FUNC27_OUT_SEL_S)) +#define GPIO_FUNC27_OUT_SEL_V 0x1FF +#define GPIO_FUNC27_OUT_SEL_S 0 + +#define GPIO_FUNC28_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05a0) +/* GPIO_FUNC28_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC28_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC28_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC28_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC28_OEN_INV_SEL_S 11 +/* GPIO_FUNC28_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC28_OEN_SEL (BIT(10)) +#define GPIO_FUNC28_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC28_OEN_SEL_V 0x1 +#define GPIO_FUNC28_OEN_SEL_S 10 +/* GPIO_FUNC28_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC28_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC28_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC28_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC28_OUT_INV_SEL_S 9 +/* GPIO_FUNC28_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC28_OUT_SEL 0x000001FF +#define GPIO_FUNC28_OUT_SEL_M ((GPIO_FUNC28_OUT_SEL_V)<<(GPIO_FUNC28_OUT_SEL_S)) +#define GPIO_FUNC28_OUT_SEL_V 0x1FF +#define GPIO_FUNC28_OUT_SEL_S 0 + +#define GPIO_FUNC29_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05a4) +/* GPIO_FUNC29_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC29_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC29_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC29_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC29_OEN_INV_SEL_S 11 +/* GPIO_FUNC29_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC29_OEN_SEL (BIT(10)) +#define GPIO_FUNC29_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC29_OEN_SEL_V 0x1 +#define GPIO_FUNC29_OEN_SEL_S 10 +/* GPIO_FUNC29_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC29_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC29_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC29_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC29_OUT_INV_SEL_S 9 +/* GPIO_FUNC29_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC29_OUT_SEL 0x000001FF +#define GPIO_FUNC29_OUT_SEL_M ((GPIO_FUNC29_OUT_SEL_V)<<(GPIO_FUNC29_OUT_SEL_S)) +#define GPIO_FUNC29_OUT_SEL_V 0x1FF +#define GPIO_FUNC29_OUT_SEL_S 0 + +#define GPIO_FUNC30_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05a8) +/* GPIO_FUNC30_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC30_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC30_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC30_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC30_OEN_INV_SEL_S 11 +/* GPIO_FUNC30_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC30_OEN_SEL (BIT(10)) +#define GPIO_FUNC30_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC30_OEN_SEL_V 0x1 +#define GPIO_FUNC30_OEN_SEL_S 10 +/* GPIO_FUNC30_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC30_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC30_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC30_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC30_OUT_INV_SEL_S 9 +/* GPIO_FUNC30_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC30_OUT_SEL 0x000001FF +#define GPIO_FUNC30_OUT_SEL_M ((GPIO_FUNC30_OUT_SEL_V)<<(GPIO_FUNC30_OUT_SEL_S)) +#define GPIO_FUNC30_OUT_SEL_V 0x1FF +#define GPIO_FUNC30_OUT_SEL_S 0 + +#define GPIO_FUNC31_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05ac) +/* GPIO_FUNC31_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC31_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC31_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC31_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC31_OEN_INV_SEL_S 11 +/* GPIO_FUNC31_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC31_OEN_SEL (BIT(10)) +#define GPIO_FUNC31_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC31_OEN_SEL_V 0x1 +#define GPIO_FUNC31_OEN_SEL_S 10 +/* GPIO_FUNC31_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC31_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC31_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC31_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC31_OUT_INV_SEL_S 9 +/* GPIO_FUNC31_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC31_OUT_SEL 0x000001FF +#define GPIO_FUNC31_OUT_SEL_M ((GPIO_FUNC31_OUT_SEL_V)<<(GPIO_FUNC31_OUT_SEL_S)) +#define GPIO_FUNC31_OUT_SEL_V 0x1FF +#define GPIO_FUNC31_OUT_SEL_S 0 + +#define GPIO_FUNC32_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05b0) +/* GPIO_FUNC32_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC32_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC32_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC32_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC32_OEN_INV_SEL_S 11 +/* GPIO_FUNC32_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC32_OEN_SEL (BIT(10)) +#define GPIO_FUNC32_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC32_OEN_SEL_V 0x1 +#define GPIO_FUNC32_OEN_SEL_S 10 +/* GPIO_FUNC32_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC32_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC32_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC32_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC32_OUT_INV_SEL_S 9 +/* GPIO_FUNC32_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC32_OUT_SEL 0x000001FF +#define GPIO_FUNC32_OUT_SEL_M ((GPIO_FUNC32_OUT_SEL_V)<<(GPIO_FUNC32_OUT_SEL_S)) +#define GPIO_FUNC32_OUT_SEL_V 0x1FF +#define GPIO_FUNC32_OUT_SEL_S 0 + +#define GPIO_FUNC33_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05b4) +/* GPIO_FUNC33_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC33_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC33_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC33_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC33_OEN_INV_SEL_S 11 +/* GPIO_FUNC33_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC33_OEN_SEL (BIT(10)) +#define GPIO_FUNC33_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC33_OEN_SEL_V 0x1 +#define GPIO_FUNC33_OEN_SEL_S 10 +/* GPIO_FUNC33_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC33_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC33_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC33_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC33_OUT_INV_SEL_S 9 +/* GPIO_FUNC33_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC33_OUT_SEL 0x000001FF +#define GPIO_FUNC33_OUT_SEL_M ((GPIO_FUNC33_OUT_SEL_V)<<(GPIO_FUNC33_OUT_SEL_S)) +#define GPIO_FUNC33_OUT_SEL_V 0x1FF +#define GPIO_FUNC33_OUT_SEL_S 0 + +#define GPIO_FUNC34_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05b8) +/* GPIO_FUNC34_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC34_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC34_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC34_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC34_OEN_INV_SEL_S 11 +/* GPIO_FUNC34_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC34_OEN_SEL (BIT(10)) +#define GPIO_FUNC34_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC34_OEN_SEL_V 0x1 +#define GPIO_FUNC34_OEN_SEL_S 10 +/* GPIO_FUNC34_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC34_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC34_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC34_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC34_OUT_INV_SEL_S 9 +/* GPIO_FUNC34_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC34_OUT_SEL 0x000001FF +#define GPIO_FUNC34_OUT_SEL_M ((GPIO_FUNC34_OUT_SEL_V)<<(GPIO_FUNC34_OUT_SEL_S)) +#define GPIO_FUNC34_OUT_SEL_V 0x1FF +#define GPIO_FUNC34_OUT_SEL_S 0 + +#define GPIO_FUNC35_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05bc) +/* GPIO_FUNC35_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC35_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC35_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC35_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC35_OEN_INV_SEL_S 11 +/* GPIO_FUNC35_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC35_OEN_SEL (BIT(10)) +#define GPIO_FUNC35_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC35_OEN_SEL_V 0x1 +#define GPIO_FUNC35_OEN_SEL_S 10 +/* GPIO_FUNC35_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC35_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC35_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC35_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC35_OUT_INV_SEL_S 9 +/* GPIO_FUNC35_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC35_OUT_SEL 0x000001FF +#define GPIO_FUNC35_OUT_SEL_M ((GPIO_FUNC35_OUT_SEL_V)<<(GPIO_FUNC35_OUT_SEL_S)) +#define GPIO_FUNC35_OUT_SEL_V 0x1FF +#define GPIO_FUNC35_OUT_SEL_S 0 + +#define GPIO_FUNC36_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05c0) +/* GPIO_FUNC36_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC36_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC36_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC36_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC36_OEN_INV_SEL_S 11 +/* GPIO_FUNC36_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC36_OEN_SEL (BIT(10)) +#define GPIO_FUNC36_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC36_OEN_SEL_V 0x1 +#define GPIO_FUNC36_OEN_SEL_S 10 +/* GPIO_FUNC36_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC36_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC36_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC36_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC36_OUT_INV_SEL_S 9 +/* GPIO_FUNC36_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC36_OUT_SEL 0x000001FF +#define GPIO_FUNC36_OUT_SEL_M ((GPIO_FUNC36_OUT_SEL_V)<<(GPIO_FUNC36_OUT_SEL_S)) +#define GPIO_FUNC36_OUT_SEL_V 0x1FF +#define GPIO_FUNC36_OUT_SEL_S 0 + +#define GPIO_FUNC37_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05c4) +/* GPIO_FUNC37_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC37_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC37_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC37_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC37_OEN_INV_SEL_S 11 +/* GPIO_FUNC37_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC37_OEN_SEL (BIT(10)) +#define GPIO_FUNC37_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC37_OEN_SEL_V 0x1 +#define GPIO_FUNC37_OEN_SEL_S 10 +/* GPIO_FUNC37_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC37_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC37_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC37_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC37_OUT_INV_SEL_S 9 +/* GPIO_FUNC37_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC37_OUT_SEL 0x000001FF +#define GPIO_FUNC37_OUT_SEL_M ((GPIO_FUNC37_OUT_SEL_V)<<(GPIO_FUNC37_OUT_SEL_S)) +#define GPIO_FUNC37_OUT_SEL_V 0x1FF +#define GPIO_FUNC37_OUT_SEL_S 0 + +#define GPIO_FUNC38_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05c8) +/* GPIO_FUNC38_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC38_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC38_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC38_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC38_OEN_INV_SEL_S 11 +/* GPIO_FUNC38_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC38_OEN_SEL (BIT(10)) +#define GPIO_FUNC38_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC38_OEN_SEL_V 0x1 +#define GPIO_FUNC38_OEN_SEL_S 10 +/* GPIO_FUNC38_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC38_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC38_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC38_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC38_OUT_INV_SEL_S 9 +/* GPIO_FUNC38_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC38_OUT_SEL 0x000001FF +#define GPIO_FUNC38_OUT_SEL_M ((GPIO_FUNC38_OUT_SEL_V)<<(GPIO_FUNC38_OUT_SEL_S)) +#define GPIO_FUNC38_OUT_SEL_V 0x1FF +#define GPIO_FUNC38_OUT_SEL_S 0 + +#define GPIO_FUNC39_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05cc) +/* GPIO_FUNC39_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/*description: invert the output enable value if you want to revert the output + enable value setting the value to 1*/ +#define GPIO_FUNC39_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC39_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC39_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC39_OEN_INV_SEL_S 11 +/* GPIO_FUNC39_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/*description: weather using the logical oen signal or not using the value setting + by the register*/ +#define GPIO_FUNC39_OEN_SEL (BIT(10)) +#define GPIO_FUNC39_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC39_OEN_SEL_V 0x1 +#define GPIO_FUNC39_OEN_SEL_S 10 +/* GPIO_FUNC39_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/*description: invert the output value if you want to revert the output value + setting the value to 1*/ +#define GPIO_FUNC39_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC39_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC39_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC39_OUT_INV_SEL_S 9 +/* GPIO_FUNC39_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/*description: select one of the 256 output to 40 GPIO*/ +#define GPIO_FUNC39_OUT_SEL 0x000001FF +#define GPIO_FUNC39_OUT_SEL_M ((GPIO_FUNC39_OUT_SEL_V)<<(GPIO_FUNC39_OUT_SEL_S)) +#define GPIO_FUNC39_OUT_SEL_V 0x1FF +#define GPIO_FUNC39_OUT_SEL_S 0 + + + + +#endif /*_SOC_GPIO_REG_H_ */ + + diff --git a/tools/sdk/include/esp32/soc/gpio_sd_reg.h b/tools/sdk/include/esp32/soc/gpio_sd_reg.h new file mode 100644 index 00000000..be39fcf2 --- /dev/null +++ b/tools/sdk/include/esp32/soc/gpio_sd_reg.h @@ -0,0 +1,160 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_GPIO_SD_REG_H_ +#define _SOC_GPIO_SD_REG_H_ + +#include "soc.h" +#define GPIO_SIGMADELTA0_REG (DR_REG_GPIO_SD_BASE + 0x0000) +/* GPIO_SD0_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ +/*description: */ +#define GPIO_SD0_PRESCALE 0x000000FF +#define GPIO_SD0_PRESCALE_M ((GPIO_SD0_PRESCALE_V)<<(GPIO_SD0_PRESCALE_S)) +#define GPIO_SD0_PRESCALE_V 0xFF +#define GPIO_SD0_PRESCALE_S 8 +/* GPIO_SD0_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define GPIO_SD0_IN 0x000000FF +#define GPIO_SD0_IN_M ((GPIO_SD0_IN_V)<<(GPIO_SD0_IN_S)) +#define GPIO_SD0_IN_V 0xFF +#define GPIO_SD0_IN_S 0 + +#define GPIO_SIGMADELTA1_REG (DR_REG_GPIO_SD_BASE + 0x0004) +/* GPIO_SD1_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ +/*description: */ +#define GPIO_SD1_PRESCALE 0x000000FF +#define GPIO_SD1_PRESCALE_M ((GPIO_SD1_PRESCALE_V)<<(GPIO_SD1_PRESCALE_S)) +#define GPIO_SD1_PRESCALE_V 0xFF +#define GPIO_SD1_PRESCALE_S 8 +/* GPIO_SD1_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define GPIO_SD1_IN 0x000000FF +#define GPIO_SD1_IN_M ((GPIO_SD1_IN_V)<<(GPIO_SD1_IN_S)) +#define GPIO_SD1_IN_V 0xFF +#define GPIO_SD1_IN_S 0 + +#define GPIO_SIGMADELTA2_REG (DR_REG_GPIO_SD_BASE + 0x0008) +/* GPIO_SD2_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ +/*description: */ +#define GPIO_SD2_PRESCALE 0x000000FF +#define GPIO_SD2_PRESCALE_M ((GPIO_SD2_PRESCALE_V)<<(GPIO_SD2_PRESCALE_S)) +#define GPIO_SD2_PRESCALE_V 0xFF +#define GPIO_SD2_PRESCALE_S 8 +/* GPIO_SD2_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define GPIO_SD2_IN 0x000000FF +#define GPIO_SD2_IN_M ((GPIO_SD2_IN_V)<<(GPIO_SD2_IN_S)) +#define GPIO_SD2_IN_V 0xFF +#define GPIO_SD2_IN_S 0 + +#define GPIO_SIGMADELTA3_REG (DR_REG_GPIO_SD_BASE + 0x000c) +/* GPIO_SD3_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ +/*description: */ +#define GPIO_SD3_PRESCALE 0x000000FF +#define GPIO_SD3_PRESCALE_M ((GPIO_SD3_PRESCALE_V)<<(GPIO_SD3_PRESCALE_S)) +#define GPIO_SD3_PRESCALE_V 0xFF +#define GPIO_SD3_PRESCALE_S 8 +/* GPIO_SD3_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define GPIO_SD3_IN 0x000000FF +#define GPIO_SD3_IN_M ((GPIO_SD3_IN_V)<<(GPIO_SD3_IN_S)) +#define GPIO_SD3_IN_V 0xFF +#define GPIO_SD3_IN_S 0 + +#define GPIO_SIGMADELTA4_REG (DR_REG_GPIO_SD_BASE + 0x0010) +/* GPIO_SD4_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ +/*description: */ +#define GPIO_SD4_PRESCALE 0x000000FF +#define GPIO_SD4_PRESCALE_M ((GPIO_SD4_PRESCALE_V)<<(GPIO_SD4_PRESCALE_S)) +#define GPIO_SD4_PRESCALE_V 0xFF +#define GPIO_SD4_PRESCALE_S 8 +/* GPIO_SD4_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define GPIO_SD4_IN 0x000000FF +#define GPIO_SD4_IN_M ((GPIO_SD4_IN_V)<<(GPIO_SD4_IN_S)) +#define GPIO_SD4_IN_V 0xFF +#define GPIO_SD4_IN_S 0 + +#define GPIO_SIGMADELTA5_REG (DR_REG_GPIO_SD_BASE + 0x0014) +/* GPIO_SD5_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ +/*description: */ +#define GPIO_SD5_PRESCALE 0x000000FF +#define GPIO_SD5_PRESCALE_M ((GPIO_SD5_PRESCALE_V)<<(GPIO_SD5_PRESCALE_S)) +#define GPIO_SD5_PRESCALE_V 0xFF +#define GPIO_SD5_PRESCALE_S 8 +/* GPIO_SD5_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define GPIO_SD5_IN 0x000000FF +#define GPIO_SD5_IN_M ((GPIO_SD5_IN_V)<<(GPIO_SD5_IN_S)) +#define GPIO_SD5_IN_V 0xFF +#define GPIO_SD5_IN_S 0 + +#define GPIO_SIGMADELTA6_REG (DR_REG_GPIO_SD_BASE + 0x0018) +/* GPIO_SD6_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ +/*description: */ +#define GPIO_SD6_PRESCALE 0x000000FF +#define GPIO_SD6_PRESCALE_M ((GPIO_SD6_PRESCALE_V)<<(GPIO_SD6_PRESCALE_S)) +#define GPIO_SD6_PRESCALE_V 0xFF +#define GPIO_SD6_PRESCALE_S 8 +/* GPIO_SD6_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define GPIO_SD6_IN 0x000000FF +#define GPIO_SD6_IN_M ((GPIO_SD6_IN_V)<<(GPIO_SD6_IN_S)) +#define GPIO_SD6_IN_V 0xFF +#define GPIO_SD6_IN_S 0 + +#define GPIO_SIGMADELTA7_REG (DR_REG_GPIO_SD_BASE + 0x001c) +/* GPIO_SD7_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ +/*description: */ +#define GPIO_SD7_PRESCALE 0x000000FF +#define GPIO_SD7_PRESCALE_M ((GPIO_SD7_PRESCALE_V)<<(GPIO_SD7_PRESCALE_S)) +#define GPIO_SD7_PRESCALE_V 0xFF +#define GPIO_SD7_PRESCALE_S 8 +/* GPIO_SD7_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define GPIO_SD7_IN 0x000000FF +#define GPIO_SD7_IN_M ((GPIO_SD7_IN_V)<<(GPIO_SD7_IN_S)) +#define GPIO_SD7_IN_V 0xFF +#define GPIO_SD7_IN_S 0 + +#define GPIO_SIGMADELTA_CG_REG (DR_REG_GPIO_SD_BASE + 0x0020) +/* GPIO_SD_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SD_CLK_EN (BIT(31)) +#define GPIO_SD_CLK_EN_M (BIT(31)) +#define GPIO_SD_CLK_EN_V 0x1 +#define GPIO_SD_CLK_EN_S 31 + +#define GPIO_SIGMADELTA_MISC_REG (DR_REG_GPIO_SD_BASE + 0x0024) +/* GPIO_SPI_SWAP : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SPI_SWAP (BIT(31)) +#define GPIO_SPI_SWAP_M (BIT(31)) +#define GPIO_SPI_SWAP_V 0x1 +#define GPIO_SPI_SWAP_S 31 + +#define GPIO_SIGMADELTA_VERSION_REG (DR_REG_GPIO_SD_BASE + 0x0028) +/* GPIO_SD_DATE : R/W ;bitpos:[27:0] ;default: 28'h1506190 ; */ +/*description: */ +#define GPIO_SD_DATE 0x0FFFFFFF +#define GPIO_SD_DATE_M ((GPIO_SD_DATE_V)<<(GPIO_SD_DATE_S)) +#define GPIO_SD_DATE_V 0xFFFFFFF +#define GPIO_SD_DATE_S 0 +#define SIGMADELTA_GPIO_SD_DATE_VERSION 0x1506190 + + + + +#endif /*_SOC_GPIO_SD_REG_H_ */ + + diff --git a/tools/sdk/include/esp32/soc/gpio_sd_struct.h b/tools/sdk/include/esp32/soc/gpio_sd_struct.h new file mode 100644 index 00000000..94ddd5ba --- /dev/null +++ b/tools/sdk/include/esp32/soc/gpio_sd_struct.h @@ -0,0 +1,48 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_GPIO_SD_STRUCT_H_ +#define _SOC_GPIO_SD_STRUCT_H_ +typedef volatile struct { + union { + struct { + uint32_t duty: 8; + uint32_t prescale: 8; + uint32_t reserved16: 16; + }; + uint32_t val; + } channel[8]; + union { + struct { + uint32_t reserved0: 31; + uint32_t clk_en: 1; + }; + uint32_t val; + } cg; + union { + struct { + uint32_t reserved0: 31; + uint32_t spi_swap: 1; + }; + uint32_t val; + } misc; + union { + struct { + uint32_t date: 28; + uint32_t reserved28: 4; + }; + uint32_t val; + } version; +} gpio_sd_dev_t; +extern gpio_sd_dev_t SIGMADELTA; +#endif /* _SOC_GPIO_SD_STRUCT_H_ */ diff --git a/tools/sdk/include/esp32/soc/gpio_sig_map.h b/tools/sdk/include/esp32/soc/gpio_sig_map.h new file mode 100644 index 00000000..dad22f92 --- /dev/null +++ b/tools/sdk/include/esp32/soc/gpio_sig_map.h @@ -0,0 +1,422 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_GPIO_SIG_MAP_H_ +#define _SOC_GPIO_SIG_MAP_H_ + +#define SPICLK_IN_IDX 0 +#define SPICLK_OUT_IDX 0 +#define SPIQ_IN_IDX 1 +#define SPIQ_OUT_IDX 1 +#define SPID_IN_IDX 2 +#define SPID_OUT_IDX 2 +#define SPIHD_IN_IDX 3 +#define SPIHD_OUT_IDX 3 +#define SPIWP_IN_IDX 4 +#define SPIWP_OUT_IDX 4 +#define SPICS0_IN_IDX 5 +#define SPICS0_OUT_IDX 5 +#define SPICS1_IN_IDX 6 +#define SPICS1_OUT_IDX 6 +#define SPICS2_IN_IDX 7 +#define SPICS2_OUT_IDX 7 +#define HSPICLK_IN_IDX 8 +#define HSPICLK_OUT_IDX 8 +#define HSPIQ_IN_IDX 9 +#define HSPIQ_OUT_IDX 9 +#define HSPID_IN_IDX 10 +#define HSPID_OUT_IDX 10 +#define HSPICS0_IN_IDX 11 +#define HSPICS0_OUT_IDX 11 +#define HSPIHD_IN_IDX 12 +#define HSPIHD_OUT_IDX 12 +#define HSPIWP_IN_IDX 13 +#define HSPIWP_OUT_IDX 13 +#define U0RXD_IN_IDX 14 +#define U0TXD_OUT_IDX 14 +#define U0CTS_IN_IDX 15 +#define U0RTS_OUT_IDX 15 +#define U0DSR_IN_IDX 16 +#define U0DTR_OUT_IDX 16 +#define U1RXD_IN_IDX 17 +#define U1TXD_OUT_IDX 17 +#define U1CTS_IN_IDX 18 +#define U1RTS_OUT_IDX 18 +#define I2CM_SCL_O_IDX 19 +#define I2CM_SDA_I_IDX 20 +#define I2CM_SDA_O_IDX 20 +#define EXT_I2C_SCL_O_IDX 21 +#define EXT_I2C_SDA_O_IDX 22 +#define EXT_I2C_SDA_I_IDX 22 +#define I2S0O_BCK_IN_IDX 23 +#define I2S0O_BCK_OUT_IDX 23 +#define I2S1O_BCK_IN_IDX 24 +#define I2S1O_BCK_OUT_IDX 24 +#define I2S0O_WS_IN_IDX 25 +#define I2S0O_WS_OUT_IDX 25 +#define I2S1O_WS_IN_IDX 26 +#define I2S1O_WS_OUT_IDX 26 +#define I2S0I_BCK_IN_IDX 27 +#define I2S0I_BCK_OUT_IDX 27 +#define I2S0I_WS_IN_IDX 28 +#define I2S0I_WS_OUT_IDX 28 +#define I2CEXT0_SCL_IN_IDX 29 +#define I2CEXT0_SCL_OUT_IDX 29 +#define I2CEXT0_SDA_IN_IDX 30 +#define I2CEXT0_SDA_OUT_IDX 30 +#define PWM0_SYNC0_IN_IDX 31 +#define SDIO_TOHOST_INT_OUT_IDX 31 +#define PWM0_SYNC1_IN_IDX 32 +#define PWM0_OUT0A_IDX 32 +#define PWM0_SYNC2_IN_IDX 33 +#define PWM0_OUT0B_IDX 33 +#define PWM0_F0_IN_IDX 34 +#define PWM0_OUT1A_IDX 34 +#define PWM0_F1_IN_IDX 35 +#define PWM0_OUT1B_IDX 35 +#define PWM0_F2_IN_IDX 36 +#define PWM0_OUT2A_IDX 36 +#define GPIO_BT_ACTIVE_IDX 37 +#define PWM0_OUT2B_IDX 37 +#define GPIO_BT_PRIORITY_IDX 38 +#define PCNT_SIG_CH0_IN0_IDX 39 +#define PCNT_SIG_CH1_IN0_IDX 40 +#define GPIO_WLAN_ACTIVE_IDX 40 +#define PCNT_CTRL_CH0_IN0_IDX 41 +#define BB_DIAG0_IDX 41 +#define PCNT_CTRL_CH1_IN0_IDX 42 +#define BB_DIAG1_IDX 42 +#define PCNT_SIG_CH0_IN1_IDX 43 +#define BB_DIAG2_IDX 43 +#define PCNT_SIG_CH1_IN1_IDX 44 +#define BB_DIAG3_IDX 44 +#define PCNT_CTRL_CH0_IN1_IDX 45 +#define BB_DIAG4_IDX 45 +#define PCNT_CTRL_CH1_IN1_IDX 46 +#define BB_DIAG5_IDX 46 +#define PCNT_SIG_CH0_IN2_IDX 47 +#define BB_DIAG6_IDX 47 +#define PCNT_SIG_CH1_IN2_IDX 48 +#define BB_DIAG7_IDX 48 +#define PCNT_CTRL_CH0_IN2_IDX 49 +#define BB_DIAG8_IDX 49 +#define PCNT_CTRL_CH1_IN2_IDX 50 +#define BB_DIAG9_IDX 50 +#define PCNT_SIG_CH0_IN3_IDX 51 +#define BB_DIAG10_IDX 51 +#define PCNT_SIG_CH1_IN3_IDX 52 +#define BB_DIAG11_IDX 52 +#define PCNT_CTRL_CH0_IN3_IDX 53 +#define BB_DIAG12_IDX 53 +#define PCNT_CTRL_CH1_IN3_IDX 54 +#define BB_DIAG13_IDX 54 +#define PCNT_SIG_CH0_IN4_IDX 55 +#define BB_DIAG14_IDX 55 +#define PCNT_SIG_CH1_IN4_IDX 56 +#define BB_DIAG15_IDX 56 +#define PCNT_CTRL_CH0_IN4_IDX 57 +#define BB_DIAG16_IDX 57 +#define PCNT_CTRL_CH1_IN4_IDX 58 +#define BB_DIAG17_IDX 58 +#define BB_DIAG18_IDX 59 +#define BB_DIAG19_IDX 60 +#define HSPICS1_IN_IDX 61 +#define HSPICS1_OUT_IDX 61 +#define HSPICS2_IN_IDX 62 +#define HSPICS2_OUT_IDX 62 +#define VSPICLK_IN_IDX 63 +#define VSPICLK_OUT_MUX_IDX 63 +#define VSPIQ_IN_IDX 64 +#define VSPIQ_OUT_IDX 64 +#define VSPID_IN_IDX 65 +#define VSPID_OUT_IDX 65 +#define VSPIHD_IN_IDX 66 +#define VSPIHD_OUT_IDX 66 +#define VSPIWP_IN_IDX 67 +#define VSPIWP_OUT_IDX 67 +#define VSPICS0_IN_IDX 68 +#define VSPICS0_OUT_IDX 68 +#define VSPICS1_IN_IDX 69 +#define VSPICS1_OUT_IDX 69 +#define VSPICS2_IN_IDX 70 +#define VSPICS2_OUT_IDX 70 +#define PCNT_SIG_CH0_IN5_IDX 71 +#define LEDC_HS_SIG_OUT0_IDX 71 +#define PCNT_SIG_CH1_IN5_IDX 72 +#define LEDC_HS_SIG_OUT1_IDX 72 +#define PCNT_CTRL_CH0_IN5_IDX 73 +#define LEDC_HS_SIG_OUT2_IDX 73 +#define PCNT_CTRL_CH1_IN5_IDX 74 +#define LEDC_HS_SIG_OUT3_IDX 74 +#define PCNT_SIG_CH0_IN6_IDX 75 +#define LEDC_HS_SIG_OUT4_IDX 75 +#define PCNT_SIG_CH1_IN6_IDX 76 +#define LEDC_HS_SIG_OUT5_IDX 76 +#define PCNT_CTRL_CH0_IN6_IDX 77 +#define LEDC_HS_SIG_OUT6_IDX 77 +#define PCNT_CTRL_CH1_IN6_IDX 78 +#define LEDC_HS_SIG_OUT7_IDX 78 +#define PCNT_SIG_CH0_IN7_IDX 79 +#define LEDC_LS_SIG_OUT0_IDX 79 +#define PCNT_SIG_CH1_IN7_IDX 80 +#define LEDC_LS_SIG_OUT1_IDX 80 +#define PCNT_CTRL_CH0_IN7_IDX 81 +#define LEDC_LS_SIG_OUT2_IDX 81 +#define PCNT_CTRL_CH1_IN7_IDX 82 +#define LEDC_LS_SIG_OUT3_IDX 82 +#define RMT_SIG_IN0_IDX 83 +#define LEDC_LS_SIG_OUT4_IDX 83 +#define RMT_SIG_IN1_IDX 84 +#define LEDC_LS_SIG_OUT5_IDX 84 +#define RMT_SIG_IN2_IDX 85 +#define LEDC_LS_SIG_OUT6_IDX 85 +#define RMT_SIG_IN3_IDX 86 +#define LEDC_LS_SIG_OUT7_IDX 86 +#define RMT_SIG_IN4_IDX 87 +#define RMT_SIG_OUT0_IDX 87 +#define RMT_SIG_IN5_IDX 88 +#define RMT_SIG_OUT1_IDX 88 +#define RMT_SIG_IN6_IDX 89 +#define RMT_SIG_OUT2_IDX 89 +#define RMT_SIG_IN7_IDX 90 +#define RMT_SIG_OUT3_IDX 90 +#define RMT_SIG_OUT4_IDX 91 +#define RMT_SIG_OUT5_IDX 92 +#define EXT_ADC_START_IDX 93 +#define RMT_SIG_OUT6_IDX 93 +#define CAN_RX_IDX 94 +#define RMT_SIG_OUT7_IDX 94 +#define I2CEXT1_SCL_IN_IDX 95 +#define I2CEXT1_SCL_OUT_IDX 95 +#define I2CEXT1_SDA_IN_IDX 96 +#define I2CEXT1_SDA_OUT_IDX 96 +#define HOST_CARD_DETECT_N_1_IDX 97 +#define HOST_CCMD_OD_PULLUP_EN_N_IDX 97 +#define HOST_CARD_DETECT_N_2_IDX 98 +#define HOST_RST_N_1_IDX 98 +#define HOST_CARD_WRITE_PRT_1_IDX 99 +#define HOST_RST_N_2_IDX 99 +#define HOST_CARD_WRITE_PRT_2_IDX 100 +#define GPIO_SD0_OUT_IDX 100 +#define HOST_CARD_INT_N_1_IDX 101 +#define GPIO_SD1_OUT_IDX 101 +#define HOST_CARD_INT_N_2_IDX 102 +#define GPIO_SD2_OUT_IDX 102 +#define PWM1_SYNC0_IN_IDX 103 +#define GPIO_SD3_OUT_IDX 103 +#define PWM1_SYNC1_IN_IDX 104 +#define GPIO_SD4_OUT_IDX 104 +#define PWM1_SYNC2_IN_IDX 105 +#define GPIO_SD5_OUT_IDX 105 +#define PWM1_F0_IN_IDX 106 +#define GPIO_SD6_OUT_IDX 106 +#define PWM1_F1_IN_IDX 107 +#define GPIO_SD7_OUT_IDX 107 +#define PWM1_F2_IN_IDX 108 +#define PWM1_OUT0A_IDX 108 +#define PWM0_CAP0_IN_IDX 109 +#define PWM1_OUT0B_IDX 109 +#define PWM0_CAP1_IN_IDX 110 +#define PWM1_OUT1A_IDX 110 +#define PWM0_CAP2_IN_IDX 111 +#define PWM1_OUT1B_IDX 111 +#define PWM1_CAP0_IN_IDX 112 +#define PWM1_OUT2A_IDX 112 +#define PWM1_CAP1_IN_IDX 113 +#define PWM1_OUT2B_IDX 113 +#define PWM1_CAP2_IN_IDX 114 +#define PWM2_OUT1H_IDX 114 +#define PWM2_FLTA_IDX 115 +#define PWM2_OUT1L_IDX 115 +#define PWM2_FLTB_IDX 116 +#define PWM2_OUT2H_IDX 116 +#define PWM2_CAP1_IN_IDX 117 +#define PWM2_OUT2L_IDX 117 +#define PWM2_CAP2_IN_IDX 118 +#define PWM2_OUT3H_IDX 118 +#define PWM2_CAP3_IN_IDX 119 +#define PWM2_OUT3L_IDX 119 +#define PWM3_FLTA_IDX 120 +#define PWM2_OUT4H_IDX 120 +#define PWM3_FLTB_IDX 121 +#define PWM2_OUT4L_IDX 121 +#define PWM3_CAP1_IN_IDX 122 +#define PWM3_CAP2_IN_IDX 123 +#define CAN_TX_IDX 123 +#define PWM3_CAP3_IN_IDX 124 +#define CAN_BUS_OFF_ON_IDX 124 +#define CAN_CLKOUT_IDX 125 +#define SPID4_IN_IDX 128 +#define SPID4_OUT_IDX 128 +#define SPID5_IN_IDX 129 +#define SPID5_OUT_IDX 129 +#define SPID6_IN_IDX 130 +#define SPID6_OUT_IDX 130 +#define SPID7_IN_IDX 131 +#define SPID7_OUT_IDX 131 +#define HSPID4_IN_IDX 132 +#define HSPID4_OUT_IDX 132 +#define HSPID5_IN_IDX 133 +#define HSPID5_OUT_IDX 133 +#define HSPID6_IN_IDX 134 +#define HSPID6_OUT_IDX 134 +#define HSPID7_IN_IDX 135 +#define HSPID7_OUT_IDX 135 +#define VSPID4_IN_IDX 136 +#define VSPID4_OUT_IDX 136 +#define VSPID5_IN_IDX 137 +#define VSPID5_OUT_IDX 137 +#define VSPID6_IN_IDX 138 +#define VSPID6_OUT_IDX 138 +#define VSPID7_IN_IDX 139 +#define VSPID7_OUT_IDX 139 +#define I2S0I_DATA_IN0_IDX 140 +#define I2S0O_DATA_OUT0_IDX 140 +#define I2S0I_DATA_IN1_IDX 141 +#define I2S0O_DATA_OUT1_IDX 141 +#define I2S0I_DATA_IN2_IDX 142 +#define I2S0O_DATA_OUT2_IDX 142 +#define I2S0I_DATA_IN3_IDX 143 +#define I2S0O_DATA_OUT3_IDX 143 +#define I2S0I_DATA_IN4_IDX 144 +#define I2S0O_DATA_OUT4_IDX 144 +#define I2S0I_DATA_IN5_IDX 145 +#define I2S0O_DATA_OUT5_IDX 145 +#define I2S0I_DATA_IN6_IDX 146 +#define I2S0O_DATA_OUT6_IDX 146 +#define I2S0I_DATA_IN7_IDX 147 +#define I2S0O_DATA_OUT7_IDX 147 +#define I2S0I_DATA_IN8_IDX 148 +#define I2S0O_DATA_OUT8_IDX 148 +#define I2S0I_DATA_IN9_IDX 149 +#define I2S0O_DATA_OUT9_IDX 149 +#define I2S0I_DATA_IN10_IDX 150 +#define I2S0O_DATA_OUT10_IDX 150 +#define I2S0I_DATA_IN11_IDX 151 +#define I2S0O_DATA_OUT11_IDX 151 +#define I2S0I_DATA_IN12_IDX 152 +#define I2S0O_DATA_OUT12_IDX 152 +#define I2S0I_DATA_IN13_IDX 153 +#define I2S0O_DATA_OUT13_IDX 153 +#define I2S0I_DATA_IN14_IDX 154 +#define I2S0O_DATA_OUT14_IDX 154 +#define I2S0I_DATA_IN15_IDX 155 +#define I2S0O_DATA_OUT15_IDX 155 +#define I2S0O_DATA_OUT16_IDX 156 +#define I2S0O_DATA_OUT17_IDX 157 +#define I2S0O_DATA_OUT18_IDX 158 +#define I2S0O_DATA_OUT19_IDX 159 +#define I2S0O_DATA_OUT20_IDX 160 +#define I2S0O_DATA_OUT21_IDX 161 +#define I2S0O_DATA_OUT22_IDX 162 +#define I2S0O_DATA_OUT23_IDX 163 +#define I2S1I_BCK_IN_IDX 164 +#define I2S1I_BCK_OUT_IDX 164 +#define I2S1I_WS_IN_IDX 165 +#define I2S1I_WS_OUT_IDX 165 +#define I2S1I_DATA_IN0_IDX 166 +#define I2S1O_DATA_OUT0_IDX 166 +#define I2S1I_DATA_IN1_IDX 167 +#define I2S1O_DATA_OUT1_IDX 167 +#define I2S1I_DATA_IN2_IDX 168 +#define I2S1O_DATA_OUT2_IDX 168 +#define I2S1I_DATA_IN3_IDX 169 +#define I2S1O_DATA_OUT3_IDX 169 +#define I2S1I_DATA_IN4_IDX 170 +#define I2S1O_DATA_OUT4_IDX 170 +#define I2S1I_DATA_IN5_IDX 171 +#define I2S1O_DATA_OUT5_IDX 171 +#define I2S1I_DATA_IN6_IDX 172 +#define I2S1O_DATA_OUT6_IDX 172 +#define I2S1I_DATA_IN7_IDX 173 +#define I2S1O_DATA_OUT7_IDX 173 +#define I2S1I_DATA_IN8_IDX 174 +#define I2S1O_DATA_OUT8_IDX 174 +#define I2S1I_DATA_IN9_IDX 175 +#define I2S1O_DATA_OUT9_IDX 175 +#define I2S1I_DATA_IN10_IDX 176 +#define I2S1O_DATA_OUT10_IDX 176 +#define I2S1I_DATA_IN11_IDX 177 +#define I2S1O_DATA_OUT11_IDX 177 +#define I2S1I_DATA_IN12_IDX 178 +#define I2S1O_DATA_OUT12_IDX 178 +#define I2S1I_DATA_IN13_IDX 179 +#define I2S1O_DATA_OUT13_IDX 179 +#define I2S1I_DATA_IN14_IDX 180 +#define I2S1O_DATA_OUT14_IDX 180 +#define I2S1I_DATA_IN15_IDX 181 +#define I2S1O_DATA_OUT15_IDX 181 +#define I2S1O_DATA_OUT16_IDX 182 +#define I2S1O_DATA_OUT17_IDX 183 +#define I2S1O_DATA_OUT18_IDX 184 +#define I2S1O_DATA_OUT19_IDX 185 +#define I2S1O_DATA_OUT20_IDX 186 +#define I2S1O_DATA_OUT21_IDX 187 +#define I2S1O_DATA_OUT22_IDX 188 +#define I2S1O_DATA_OUT23_IDX 189 +#define I2S0I_H_SYNC_IDX 190 +#define PWM3_OUT1H_IDX 190 +#define I2S0I_V_SYNC_IDX 191 +#define PWM3_OUT1L_IDX 191 +#define I2S0I_H_ENABLE_IDX 192 +#define PWM3_OUT2H_IDX 192 +#define I2S1I_H_SYNC_IDX 193 +#define PWM3_OUT2L_IDX 193 +#define I2S1I_V_SYNC_IDX 194 +#define PWM3_OUT3H_IDX 194 +#define I2S1I_H_ENABLE_IDX 195 +#define PWM3_OUT3L_IDX 195 +#define PWM3_OUT4H_IDX 196 +#define PWM3_OUT4L_IDX 197 +#define U2RXD_IN_IDX 198 +#define U2TXD_OUT_IDX 198 +#define U2CTS_IN_IDX 199 +#define U2RTS_OUT_IDX 199 +#define EMAC_MDC_I_IDX 200 +#define EMAC_MDC_O_IDX 200 +#define EMAC_MDI_I_IDX 201 +#define EMAC_MDO_O_IDX 201 +#define EMAC_CRS_I_IDX 202 +#define EMAC_CRS_O_IDX 202 +#define EMAC_COL_I_IDX 203 +#define EMAC_COL_O_IDX 203 +#define PCMFSYNC_IN_IDX 204 +#define BT_AUDIO0_IRQ_IDX 204 +#define PCMCLK_IN_IDX 205 +#define BT_AUDIO1_IRQ_IDX 205 +#define PCMDIN_IDX 206 +#define BT_AUDIO2_IRQ_IDX 206 +#define BLE_AUDIO0_IRQ_IDX 207 +#define BLE_AUDIO1_IRQ_IDX 208 +#define BLE_AUDIO2_IRQ_IDX 209 +#define PCMFSYNC_OUT_IDX 210 +#define PCMCLK_OUT_IDX 211 +#define PCMDOUT_IDX 212 +#define BLE_AUDIO_SYNC0_P_IDX 213 +#define BLE_AUDIO_SYNC1_P_IDX 214 +#define BLE_AUDIO_SYNC2_P_IDX 215 +#define ANT_SEL0_IDX 216 +#define ANT_SEL1_IDX 217 +#define ANT_SEL2_IDX 218 +#define ANT_SEL3_IDX 219 +#define ANT_SEL4_IDX 220 +#define ANT_SEL5_IDX 221 +#define ANT_SEL6_IDX 222 +#define ANT_SEL7_IDX 223 +#define SIG_IN_FUNC224_IDX 224 +#define SIG_IN_FUNC225_IDX 225 +#define SIG_IN_FUNC226_IDX 226 +#define SIG_IN_FUNC227_IDX 227 +#define SIG_IN_FUNC228_IDX 228 + +#endif /* _SOC_GPIO_SIG_MAP_H_ */ diff --git a/tools/sdk/include/esp32/soc/gpio_struct.h b/tools/sdk/include/esp32/soc/gpio_struct.h new file mode 100644 index 00000000..7a90b71a --- /dev/null +++ b/tools/sdk/include/esp32/soc/gpio_struct.h @@ -0,0 +1,204 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_GPIO_STRUCT_H_ +#define _SOC_GPIO_STRUCT_H_ +typedef volatile struct { + uint32_t bt_select; /*NA*/ + uint32_t out; /*GPIO0~31 output value*/ + uint32_t out_w1ts; /*GPIO0~31 output value write 1 to set*/ + uint32_t out_w1tc; /*GPIO0~31 output value write 1 to clear*/ + union { + struct { + uint32_t data: 8; /*GPIO32~39 output value*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } out1; + union { + struct { + uint32_t data: 8; /*GPIO32~39 output value write 1 to set*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } out1_w1ts; + union { + struct { + uint32_t data: 8; /*GPIO32~39 output value write 1 to clear*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } out1_w1tc; + union { + struct { + uint32_t sel: 8; /*SDIO PADS on/off control from outside*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } sdio_select; + uint32_t enable; /*GPIO0~31 output enable*/ + uint32_t enable_w1ts; /*GPIO0~31 output enable write 1 to set*/ + uint32_t enable_w1tc; /*GPIO0~31 output enable write 1 to clear*/ + union { + struct { + uint32_t data: 8; /*GPIO32~39 output enable*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } enable1; + union { + struct { + uint32_t data: 8; /*GPIO32~39 output enable write 1 to set*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } enable1_w1ts; + union { + struct { + uint32_t data: 8; /*GPIO32~39 output enable write 1 to clear*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } enable1_w1tc; + union { + struct { + uint32_t strapping: 16; /*GPIO strapping results: {2'd0 boot_sel_dig[7:1] vsdio_boot_sel boot_sel_chip[5:0]} . Boot_sel_dig[7:1]: {U0RXD SD_CLK SD_CMD SD_DATA0 SD_DATA1 SD_DATA2 SD_DATA3} . vsdio_boot_sel: MTDI. boot_sel_chip[5:0]: {GPIO0 U0TXD GPIO2 GPIO4 MTDO GPIO5} */ + uint32_t reserved16:16; + }; + uint32_t val; + } strap; + uint32_t in; /*GPIO0~31 input value*/ + union { + struct { + uint32_t data: 8; /*GPIO32~39 input value*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } in1; + uint32_t status; /*GPIO0~31 interrupt status*/ + uint32_t status_w1ts; /*GPIO0~31 interrupt status write 1 to set*/ + uint32_t status_w1tc; /*GPIO0~31 interrupt status write 1 to clear*/ + union { + struct { + uint32_t intr_st: 8; /*GPIO32~39 interrupt status*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } status1; + union { + struct { + uint32_t intr_st: 8; /*GPIO32~39 interrupt status write 1 to set*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } status1_w1ts; + union { + struct { + uint32_t intr_st: 8; /*GPIO32~39 interrupt status write 1 to clear*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } status1_w1tc; + uint32_t reserved_5c; + uint32_t acpu_int; /*GPIO0~31 APP CPU interrupt status*/ + uint32_t acpu_nmi_int; /*GPIO0~31 APP CPU non-maskable interrupt status*/ + uint32_t pcpu_int; /*GPIO0~31 PRO CPU interrupt status*/ + uint32_t pcpu_nmi_int; /*GPIO0~31 PRO CPU non-maskable interrupt status*/ + uint32_t cpusdio_int; /*SDIO's extent GPIO0~31 interrupt*/ + union { + struct { + uint32_t intr: 8; /*GPIO32~39 APP CPU interrupt status*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } acpu_int1; + union { + struct { + uint32_t intr: 8; /*GPIO32~39 APP CPU non-maskable interrupt status*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } acpu_nmi_int1; + union { + struct { + uint32_t intr: 8; /*GPIO32~39 PRO CPU interrupt status*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } pcpu_int1; + union { + struct { + uint32_t intr: 8; /*GPIO32~39 PRO CPU non-maskable interrupt status*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } pcpu_nmi_int1; + union { + struct { + uint32_t intr: 8; /*SDIO's extent GPIO32~39 interrupt*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } cpusdio_int1; + union { + struct { + uint32_t reserved0: 2; + uint32_t pad_driver: 1; /*if set to 0: normal output if set to 1: open drain*/ + uint32_t reserved3: 4; + uint32_t int_type: 3; /*if set to 0: GPIO interrupt disable if set to 1: rising edge trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ + uint32_t wakeup_enable: 1; /*GPIO wake up enable only available in light sleep*/ + uint32_t config: 2; /*NA*/ + uint32_t int_ena: 5; /*bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ + uint32_t reserved18: 14; + }; + uint32_t val; + } pin[40]; + union { + struct { + uint32_t rtc_max: 10; + uint32_t reserved10: 21; + uint32_t start: 1; + }; + uint32_t val; + } cali_conf; + union { + struct { + uint32_t value_sync2: 20; + uint32_t reserved20: 10; + uint32_t rdy_real: 1; + uint32_t rdy_sync2: 1; + }; + uint32_t val; + } cali_data; + union { + struct { + uint32_t func_sel: 6; /*select one of the 256 inputs*/ + uint32_t sig_in_inv: 1; /*revert the value of the input if you want to revert please set the value to 1*/ + uint32_t sig_in_sel: 1; /*if the slow signal bypass the io matrix or not if you want setting the value to 1*/ + uint32_t reserved8: 24; /*The 256 registers below are selection control for 256 input signals connected to GPIO matrix's 40 GPIO input if GPIO_FUNCx_IN_SEL is set to n(0<=n<40): it means GPIOn input is used for input signal x if GPIO_FUNCx_IN_SEL is set to 0x38: the input signal x is set to 1 if GPIO_FUNCx_IN_SEL is set to 0x30: the input signal x is set to 0*/ + }; + uint32_t val; + } func_in_sel_cfg[256]; + union { + struct { + uint32_t func_sel: 9; /*select one of the 256 output to 40 GPIO*/ + uint32_t inv_sel: 1; /*invert the output value if you want to revert the output value setting the value to 1*/ + uint32_t oen_sel: 1; /*weather using the logical oen signal or not using the value setting by the register*/ + uint32_t oen_inv_sel: 1; /*invert the output enable value if you want to revert the output enable value setting the value to 1*/ + uint32_t reserved12: 20; /*The 40 registers below are selection control for 40 GPIO output if GPIO_FUNCx_OUT_SEL is set to n(0<=n<256): it means GPIOn input is used for output signal x if GPIO_FUNCx_OUT_INV_SEL is set to 1 the output signal x is set to ~value. if GPIO_FUNC0_OUT_SEL is 256 or GPIO_FUNC0_OEN_SEL is 1 using GPIO_ENABLE_DATA[x] for the enable value else using the signal enable*/ + }; + uint32_t val; + } func_out_sel_cfg[40]; +} gpio_dev_t; +extern gpio_dev_t GPIO; +#endif /* _SOC_GPIO_STRUCT_H_ */ diff --git a/tools/sdk/include/esp32/soc/i2c_reg.h b/tools/sdk/include/esp32/soc/i2c_reg.h new file mode 100644 index 00000000..d5c9858a --- /dev/null +++ b/tools/sdk/include/esp32/soc/i2c_reg.h @@ -0,0 +1,949 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_I2C_REG_H_ +#define _SOC_I2C_REG_H_ + + +#include "soc.h" + +#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 ) + +#define I2C_SCL_LOW_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0000) +/* I2C_SCL_LOW_PERIOD : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This register is used to configure the low level width of SCL clock.*/ +#define I2C_SCL_LOW_PERIOD 0x00003FFF +#define I2C_SCL_LOW_PERIOD_M ((I2C_SCL_LOW_PERIOD_V)<<(I2C_SCL_LOW_PERIOD_S)) +#define I2C_SCL_LOW_PERIOD_V 0x3FFF +#define I2C_SCL_LOW_PERIOD_S 0 + +#define I2C_CTR_REG(i) (REG_I2C_BASE(i) + 0x0004) +/* I2C_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: This is the clock gating control bit for reading or writing registers.*/ +#define I2C_CLK_EN (BIT(8)) +#define I2C_CLK_EN_M (BIT(8)) +#define I2C_CLK_EN_V 0x1 +#define I2C_CLK_EN_S 8 +/* I2C_RX_LSB_FIRST : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: This bit is used to control the storage mode for received datas. + 1: receive data from most significant bit 0: receive data from least significant bit*/ +#define I2C_RX_LSB_FIRST (BIT(7)) +#define I2C_RX_LSB_FIRST_M (BIT(7)) +#define I2C_RX_LSB_FIRST_V 0x1 +#define I2C_RX_LSB_FIRST_S 7 +/* I2C_TX_LSB_FIRST : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This bit is used to control the sending mode for data need to + be send. 1: receive data from most significant bit 0: receive data from least significant bit*/ +#define I2C_TX_LSB_FIRST (BIT(6)) +#define I2C_TX_LSB_FIRST_M (BIT(6)) +#define I2C_TX_LSB_FIRST_V 0x1 +#define I2C_TX_LSB_FIRST_S 6 +/* I2C_TRANS_START : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to start sending data in txfifo.*/ +#define I2C_TRANS_START (BIT(5)) +#define I2C_TRANS_START_M (BIT(5)) +#define I2C_TRANS_START_V 0x1 +#define I2C_TRANS_START_S 5 +/* I2C_MS_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to configure the module as i2c master clear this + bit to configure the module as i2c slave.*/ +#define I2C_MS_MODE (BIT(4)) +#define I2C_MS_MODE_M (BIT(4)) +#define I2C_MS_MODE_V 0x1 +#define I2C_MS_MODE_S 4 +/* I2C_SAMPLE_SCL_LEVEL : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to sample data in SCL low level. clear this bit + to sample data in SCL high level.*/ +#define I2C_SAMPLE_SCL_LEVEL (BIT(2)) +#define I2C_SAMPLE_SCL_LEVEL_M (BIT(2)) +#define I2C_SAMPLE_SCL_LEVEL_V 0x1 +#define I2C_SAMPLE_SCL_LEVEL_S 2 +/* I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: 1: normally ouput scl clock 0: exchange the function of scl_o + and scl_oe (scl_o is the original internal output scl signal scl_oe is the enable bit for the internal output scl signal)*/ +#define I2C_SCL_FORCE_OUT (BIT(1)) +#define I2C_SCL_FORCE_OUT_M (BIT(1)) +#define I2C_SCL_FORCE_OUT_V 0x1 +#define I2C_SCL_FORCE_OUT_S 1 +/* I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: 1: normally ouput sda data 0: exchange the function of sda_o + and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal)*/ +#define I2C_SDA_FORCE_OUT (BIT(0)) +#define I2C_SDA_FORCE_OUT_M (BIT(0)) +#define I2C_SDA_FORCE_OUT_V 0x1 +#define I2C_SDA_FORCE_OUT_S 0 + +#define I2C_SR_REG(i) (REG_I2C_BASE(i) + 0x0008) +/* I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */ +/*description: This register stores the value of state machine to produce SCL. + 3'h0: SCL_IDLE 3'h1:SCL_START 3'h2:SCL_LOW_EDGE 3'h3: SCL_LOW 3'h4:SCL_HIGH_EDGE 3'h5:SCL_HIGH 3'h6:SCL_STOP*/ +#define I2C_SCL_STATE_LAST 0x00000007 +#define I2C_SCL_STATE_LAST_M ((I2C_SCL_STATE_LAST_V)<<(I2C_SCL_STATE_LAST_S)) +#define I2C_SCL_STATE_LAST_V 0x7 +#define I2C_SCL_STATE_LAST_S 28 +/* I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */ +/*description: This register stores the value of state machine for i2c module. + 3'h0: SCL_MAIN_IDLE 3'h1: SCL_ADDRESS_SHIFT 3'h2: SCL_ACK_ADDRESS 3'h3: SCL_RX_DATA 3'h4 SCL_TX_DATA 3'h5:SCL_SEND_ACK 3'h6:SCL_WAIT_ACK*/ +#define I2C_SCL_MAIN_STATE_LAST 0x00000007 +#define I2C_SCL_MAIN_STATE_LAST_M ((I2C_SCL_MAIN_STATE_LAST_V)<<(I2C_SCL_MAIN_STATE_LAST_S)) +#define I2C_SCL_MAIN_STATE_LAST_V 0x7 +#define I2C_SCL_MAIN_STATE_LAST_S 24 +/* I2C_TXFIFO_CNT : RO ;bitpos:[23:18] ;default: 6'b0 ; */ +/*description: This register stores the amount of received data in ram.*/ +#define I2C_TXFIFO_CNT 0x0000003F +#define I2C_TXFIFO_CNT_M ((I2C_TXFIFO_CNT_V)<<(I2C_TXFIFO_CNT_S)) +#define I2C_TXFIFO_CNT_V 0x3F +#define I2C_TXFIFO_CNT_S 18 +/* I2C_RXFIFO_CNT : RO ;bitpos:[13:8] ;default: 6'b0 ; */ +/*description: This register represent the amount of data need to send.*/ +#define I2C_RXFIFO_CNT 0x0000003F +#define I2C_RXFIFO_CNT_M ((I2C_RXFIFO_CNT_V)<<(I2C_RXFIFO_CNT_S)) +#define I2C_RXFIFO_CNT_V 0x3F +#define I2C_RXFIFO_CNT_S 8 +/* I2C_BYTE_TRANS : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This register changes to high level when one byte is transferred.*/ +#define I2C_BYTE_TRANS (BIT(6)) +#define I2C_BYTE_TRANS_M (BIT(6)) +#define I2C_BYTE_TRANS_V 0x1 +#define I2C_BYTE_TRANS_S 6 +/* I2C_SLAVE_ADDRESSED : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: when configured as i2c slave and the address send by master + is equal to slave's address then this bit will be high level.*/ +#define I2C_SLAVE_ADDRESSED (BIT(5)) +#define I2C_SLAVE_ADDRESSED_M (BIT(5)) +#define I2C_SLAVE_ADDRESSED_V 0x1 +#define I2C_SLAVE_ADDRESSED_S 5 +/* I2C_BUS_BUSY : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: 1:I2C bus is busy transferring data. 0:I2C bus is in idle state.*/ +#define I2C_BUS_BUSY (BIT(4)) +#define I2C_BUS_BUSY_M (BIT(4)) +#define I2C_BUS_BUSY_V 0x1 +#define I2C_BUS_BUSY_S 4 +/* I2C_ARB_LOST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: when I2C lost control of SDA line this register changes to high level.*/ +#define I2C_ARB_LOST (BIT(3)) +#define I2C_ARB_LOST_M (BIT(3)) +#define I2C_ARB_LOST_V 0x1 +#define I2C_ARB_LOST_S 3 +/* I2C_TIME_OUT : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: when I2C takes more than time_out_reg clocks to receive a data + then this register changes to high level.*/ +#define I2C_TIME_OUT (BIT(2)) +#define I2C_TIME_OUT_M (BIT(2)) +#define I2C_TIME_OUT_V 0x1 +#define I2C_TIME_OUT_S 2 +/* I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: when in slave mode 1: master read slave 0: master write slave.*/ +#define I2C_SLAVE_RW (BIT(1)) +#define I2C_SLAVE_RW_M (BIT(1)) +#define I2C_SLAVE_RW_V 0x1 +#define I2C_SLAVE_RW_S 1 +/* I2C_ACK_REC : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This register stores the value of ACK bit.*/ +#define I2C_ACK_REC (BIT(0)) +#define I2C_ACK_REC_M (BIT(0)) +#define I2C_ACK_REC_V 0x1 +#define I2C_ACK_REC_S 0 + +#define I2C_TO_REG(i) (REG_I2C_BASE(i) + 0x000c) +/* I2C_TIME_OUT_REG : R/W ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: This register is used to configure the max clock number of receiving a data.*/ +#define I2C_TIME_OUT_REG 0x000FFFFF +#define I2C_TIME_OUT_REG_M ((I2C_TIME_OUT_REG_V)<<(I2C_TIME_OUT_REG_S)) +#define I2C_TIME_OUT_REG_V 0xFFFFF +#define I2C_TIME_OUT_REG_S 0 + +#define I2C_SLAVE_ADDR_REG(i) (REG_I2C_BASE(i) + 0x0010) +/* I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: This register is used to enable slave 10bit address mode.*/ +#define I2C_ADDR_10BIT_EN (BIT(31)) +#define I2C_ADDR_10BIT_EN_M (BIT(31)) +#define I2C_ADDR_10BIT_EN_V 0x1 +#define I2C_ADDR_10BIT_EN_S 31 +/* I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */ +/*description: when configured as i2c slave this register is used to configure + slave's address.*/ +#define I2C_SLAVE_ADDR 0x00007FFF +#define I2C_SLAVE_ADDR_M ((I2C_SLAVE_ADDR_V)<<(I2C_SLAVE_ADDR_S)) +#define I2C_SLAVE_ADDR_V 0x7FFF +#define I2C_SLAVE_ADDR_S 0 + +#define I2C_RXFIFO_ST_REG(i) (REG_I2C_BASE(i) + 0x0014) +/* I2C_TXFIFO_END_ADDR : RO ;bitpos:[19:15] ;default: 5'b0 ; */ +/*description: This is the offset address of the last sending data as described + in nonfifo_tx_thres register.*/ +#define I2C_TXFIFO_END_ADDR 0x0000001F +#define I2C_TXFIFO_END_ADDR_M ((I2C_TXFIFO_END_ADDR_V)<<(I2C_TXFIFO_END_ADDR_S)) +#define I2C_TXFIFO_END_ADDR_V 0x1F +#define I2C_TXFIFO_END_ADDR_S 15 +/* I2C_TXFIFO_START_ADDR : RO ;bitpos:[14:10] ;default: 5'b0 ; */ +/*description: This is the offset address of the first sending data as described + in nonfifo_tx_thres register.*/ +#define I2C_TXFIFO_START_ADDR 0x0000001F +#define I2C_TXFIFO_START_ADDR_M ((I2C_TXFIFO_START_ADDR_V)<<(I2C_TXFIFO_START_ADDR_S)) +#define I2C_TXFIFO_START_ADDR_V 0x1F +#define I2C_TXFIFO_START_ADDR_S 10 +/* I2C_RXFIFO_END_ADDR : RO ;bitpos:[9:5] ;default: 5'b0 ; */ +/*description: This is the offset address of the first receiving data as described + in nonfifo_rx_thres_register.*/ +#define I2C_RXFIFO_END_ADDR 0x0000001F +#define I2C_RXFIFO_END_ADDR_M ((I2C_RXFIFO_END_ADDR_V)<<(I2C_RXFIFO_END_ADDR_S)) +#define I2C_RXFIFO_END_ADDR_V 0x1F +#define I2C_RXFIFO_END_ADDR_S 5 +/* I2C_RXFIFO_START_ADDR : RO ;bitpos:[4:0] ;default: 5'b0 ; */ +/*description: This is the offset address of the last receiving data as described + in nonfifo_rx_thres_register.*/ +#define I2C_RXFIFO_START_ADDR 0x0000001F +#define I2C_RXFIFO_START_ADDR_M ((I2C_RXFIFO_START_ADDR_V)<<(I2C_RXFIFO_START_ADDR_S)) +#define I2C_RXFIFO_START_ADDR_V 0x1F +#define I2C_RXFIFO_START_ADDR_S 0 + +#define I2C_FIFO_CONF_REG(i) (REG_I2C_BASE(i) + 0x0018) +/* I2C_NONFIFO_TX_THRES : R/W ;bitpos:[25:20] ;default: 6'h15 ; */ +/*description: when I2C sends more than nonfifo_tx_thres data it will produce + tx_send_empty_int_raw interrupt and update the current offset address of the sending data.*/ +#define I2C_NONFIFO_TX_THRES 0x0000003F +#define I2C_NONFIFO_TX_THRES_M ((I2C_NONFIFO_TX_THRES_V)<<(I2C_NONFIFO_TX_THRES_S)) +#define I2C_NONFIFO_TX_THRES_V 0x3F +#define I2C_NONFIFO_TX_THRES_S 20 +/* I2C_NONFIFO_RX_THRES : R/W ;bitpos:[19:14] ;default: 6'h15 ; */ +/*description: when I2C receives more than nonfifo_rx_thres data it will produce + rx_send_full_int_raw interrupt and update the current offset address of the receiving data.*/ +#define I2C_NONFIFO_RX_THRES 0x0000003F +#define I2C_NONFIFO_RX_THRES_M ((I2C_NONFIFO_RX_THRES_V)<<(I2C_NONFIFO_RX_THRES_S)) +#define I2C_NONFIFO_RX_THRES_V 0x3F +#define I2C_NONFIFO_RX_THRES_S 14 +/* I2C_TX_FIFO_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Set this bit to reset tx fifo when using apb fifo access.*/ +#define I2C_TX_FIFO_RST (BIT(13)) +#define I2C_TX_FIFO_RST_M (BIT(13)) +#define I2C_TX_FIFO_RST_V 0x1 +#define I2C_TX_FIFO_RST_S 13 +/* I2C_RX_FIFO_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to reset rx fifo when using apb fifo access.*/ +#define I2C_RX_FIFO_RST (BIT(12)) +#define I2C_RX_FIFO_RST_M (BIT(12)) +#define I2C_RX_FIFO_RST_V 0x1 +#define I2C_RX_FIFO_RST_S 12 +/* I2C_FIFO_ADDR_CFG_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: When this bit is set to 1 then the byte after address represent + the offset address of I2C Slave's ram.*/ +#define I2C_FIFO_ADDR_CFG_EN (BIT(11)) +#define I2C_FIFO_ADDR_CFG_EN_M (BIT(11)) +#define I2C_FIFO_ADDR_CFG_EN_V 0x1 +#define I2C_FIFO_ADDR_CFG_EN_S 11 +/* I2C_NONFIFO_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to enble apb nonfifo access.*/ +#define I2C_NONFIFO_EN (BIT(10)) +#define I2C_NONFIFO_EN_M (BIT(10)) +#define I2C_NONFIFO_EN_V 0x1 +#define I2C_NONFIFO_EN_S 10 +/* I2C_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[9:5] ;default: 5'h4 ; */ +/*description: Config txfifo empty threhd value when using apb fifo access*/ +#define I2C_TXFIFO_EMPTY_THRHD 0x0000001F +#define I2C_TXFIFO_EMPTY_THRHD_M ((I2C_TXFIFO_EMPTY_THRHD_V)<<(I2C_TXFIFO_EMPTY_THRHD_S)) +#define I2C_TXFIFO_EMPTY_THRHD_V 0x1F +#define I2C_TXFIFO_EMPTY_THRHD_S 5 +/* I2C_RXFIFO_FULL_THRHD : R/W ;bitpos:[4:0] ;default: 5'hb ; */ +/*description: */ +#define I2C_RXFIFO_FULL_THRHD 0x0000001F +#define I2C_RXFIFO_FULL_THRHD_M ((I2C_RXFIFO_FULL_THRHD_V)<<(I2C_RXFIFO_FULL_THRHD_S)) +#define I2C_RXFIFO_FULL_THRHD_V 0x1F +#define I2C_RXFIFO_FULL_THRHD_S 0 + +#define I2C_DATA_REG(i) (REG_I2C_BASE(i) + 0x001c) +/* I2C_FIFO_RDATA : RO ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: The register represent the byte data read from rxfifo when use apb fifo access*/ +#define I2C_FIFO_RDATA 0x000000FF +#define I2C_FIFO_RDATA_M ((I2C_FIFO_RDATA_V)<<(I2C_FIFO_RDATA_S)) +#define I2C_FIFO_RDATA_V 0xFF +#define I2C_FIFO_RDATA_S 0 + +#define I2C_INT_RAW_REG(i) (REG_I2C_BASE(i) + 0x0020) +/* I2C_TX_SEND_EMPTY_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for tx_send_empty_int interrupt.when + I2C sends more data than nonfifo_tx_thres it will produce tx_send_empty_int interrupt..*/ +#define I2C_TX_SEND_EMPTY_INT_RAW (BIT(12)) +#define I2C_TX_SEND_EMPTY_INT_RAW_M (BIT(12)) +#define I2C_TX_SEND_EMPTY_INT_RAW_V 0x1 +#define I2C_TX_SEND_EMPTY_INT_RAW_S 12 +/* I2C_RX_REC_FULL_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for rx_rec_full_int interrupt. when + I2C receives more data than nonfifo_rx_thres it will produce rx_rec_full_int interrupt.*/ +#define I2C_RX_REC_FULL_INT_RAW (BIT(11)) +#define I2C_RX_REC_FULL_INT_RAW_M (BIT(11)) +#define I2C_RX_REC_FULL_INT_RAW_V 0x1 +#define I2C_RX_REC_FULL_INT_RAW_S 11 +/* I2C_ACK_ERR_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for ack_err_int interrupt. when + I2C receives a wrong ACK bit it will produce ack_err_int interrupt..*/ +#define I2C_ACK_ERR_INT_RAW (BIT(10)) +#define I2C_ACK_ERR_INT_RAW_M (BIT(10)) +#define I2C_ACK_ERR_INT_RAW_V 0x1 +#define I2C_ACK_ERR_INT_RAW_S 10 +/* I2C_TRANS_START_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for trans_start_int interrupt. when + I2C sends the START bit it will produce trans_start_int interrupt.*/ +#define I2C_TRANS_START_INT_RAW (BIT(9)) +#define I2C_TRANS_START_INT_RAW_M (BIT(9)) +#define I2C_TRANS_START_INT_RAW_V 0x1 +#define I2C_TRANS_START_INT_RAW_S 9 +/* I2C_TIME_OUT_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for time_out_int interrupt. when + I2C takes a lot of time to receive a data it will produce time_out_int interrupt.*/ +#define I2C_TIME_OUT_INT_RAW (BIT(8)) +#define I2C_TIME_OUT_INT_RAW_M (BIT(8)) +#define I2C_TIME_OUT_INT_RAW_V 0x1 +#define I2C_TIME_OUT_INT_RAW_S 8 +/* I2C_TRANS_COMPLETE_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for trans_complete_int interrupt. + when I2C Master finished STOP command it will produce trans_complete_int interrupt.*/ +#define I2C_TRANS_COMPLETE_INT_RAW (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_RAW_M (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_RAW_V 0x1 +#define I2C_TRANS_COMPLETE_INT_RAW_S 7 +/* I2C_MASTER_TRAN_COMP_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for master_tra_comp_int interrupt. + when I2C Master sends or receives a byte it will produce master_tran_comp_int interrupt.*/ +#define I2C_MASTER_TRAN_COMP_INT_RAW (BIT(6)) +#define I2C_MASTER_TRAN_COMP_INT_RAW_M (BIT(6)) +#define I2C_MASTER_TRAN_COMP_INT_RAW_V 0x1 +#define I2C_MASTER_TRAN_COMP_INT_RAW_S 6 +/* I2C_ARBITRATION_LOST_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for arbitration_lost_int interrupt.when + I2C lost the usage right of I2C BUS it will produce arbitration_lost_int interrupt.*/ +#define I2C_ARBITRATION_LOST_INT_RAW (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_RAW_M (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_RAW_V 0x1 +#define I2C_ARBITRATION_LOST_INT_RAW_S 5 +/* I2C_SLAVE_TRAN_COMP_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for slave_tran_comp_int interrupt. + when I2C Slave detectsthe STOP bit it will produce slave_tran_comp_int interrupt.*/ +#define I2C_SLAVE_TRAN_COMP_INT_RAW (BIT(4)) +#define I2C_SLAVE_TRAN_COMP_INT_RAW_M (BIT(4)) +#define I2C_SLAVE_TRAN_COMP_INT_RAW_V 0x1 +#define I2C_SLAVE_TRAN_COMP_INT_RAW_S 4 +/* I2C_END_DETECT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for end_detect_int interrupt. when + I2C deals with the END command it will produce end_detect_int interrupt.*/ +#define I2C_END_DETECT_INT_RAW (BIT(3)) +#define I2C_END_DETECT_INT_RAW_M (BIT(3)) +#define I2C_END_DETECT_INT_RAW_V 0x1 +#define I2C_END_DETECT_INT_RAW_S 3 +/* I2C_RXFIFO_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for receiving data overflow when + use apb fifo access.*/ +#define I2C_RXFIFO_OVF_INT_RAW (BIT(2)) +#define I2C_RXFIFO_OVF_INT_RAW_M (BIT(2)) +#define I2C_RXFIFO_OVF_INT_RAW_V 0x1 +#define I2C_RXFIFO_OVF_INT_RAW_S 2 +/* I2C_TXFIFO_EMPTY_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for txfifo empty when use apb fifo access.*/ +#define I2C_TXFIFO_EMPTY_INT_RAW (BIT(1)) +#define I2C_TXFIFO_EMPTY_INT_RAW_M (BIT(1)) +#define I2C_TXFIFO_EMPTY_INT_RAW_V 0x1 +#define I2C_TXFIFO_EMPTY_INT_RAW_S 1 +/* I2C_RXFIFO_FULL_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for rxfifo full when use apb fifo access.*/ +#define I2C_RXFIFO_FULL_INT_RAW (BIT(0)) +#define I2C_RXFIFO_FULL_INT_RAW_M (BIT(0)) +#define I2C_RXFIFO_FULL_INT_RAW_V 0x1 +#define I2C_RXFIFO_FULL_INT_RAW_S 0 + +#define I2C_INT_CLR_REG(i) (REG_I2C_BASE(i) + 0x0024) +/* I2C_TX_SEND_EMPTY_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to clear the tx_send_empty_int interrupt.*/ +#define I2C_TX_SEND_EMPTY_INT_CLR (BIT(12)) +#define I2C_TX_SEND_EMPTY_INT_CLR_M (BIT(12)) +#define I2C_TX_SEND_EMPTY_INT_CLR_V 0x1 +#define I2C_TX_SEND_EMPTY_INT_CLR_S 12 +/* I2C_RX_REC_FULL_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rx_rec_full_int interrupt.*/ +#define I2C_RX_REC_FULL_INT_CLR (BIT(11)) +#define I2C_RX_REC_FULL_INT_CLR_M (BIT(11)) +#define I2C_RX_REC_FULL_INT_CLR_V 0x1 +#define I2C_RX_REC_FULL_INT_CLR_S 11 +/* I2C_ACK_ERR_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to clear the ack_err_int interrupt.*/ +#define I2C_ACK_ERR_INT_CLR (BIT(10)) +#define I2C_ACK_ERR_INT_CLR_M (BIT(10)) +#define I2C_ACK_ERR_INT_CLR_V 0x1 +#define I2C_ACK_ERR_INT_CLR_S 10 +/* I2C_TRANS_START_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to clear the trans_start_int interrupt.*/ +#define I2C_TRANS_START_INT_CLR (BIT(9)) +#define I2C_TRANS_START_INT_CLR_M (BIT(9)) +#define I2C_TRANS_START_INT_CLR_V 0x1 +#define I2C_TRANS_START_INT_CLR_S 9 +/* I2C_TIME_OUT_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to clear the time_out_int interrupt.*/ +#define I2C_TIME_OUT_INT_CLR (BIT(8)) +#define I2C_TIME_OUT_INT_CLR_M (BIT(8)) +#define I2C_TIME_OUT_INT_CLR_V 0x1 +#define I2C_TIME_OUT_INT_CLR_S 8 +/* I2C_TRANS_COMPLETE_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to clear the trans_complete_int interrupt.*/ +#define I2C_TRANS_COMPLETE_INT_CLR (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_CLR_M (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_CLR_V 0x1 +#define I2C_TRANS_COMPLETE_INT_CLR_S 7 +/* I2C_MASTER_TRAN_COMP_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to clear the master_tran_comp interrupt.*/ +#define I2C_MASTER_TRAN_COMP_INT_CLR (BIT(6)) +#define I2C_MASTER_TRAN_COMP_INT_CLR_M (BIT(6)) +#define I2C_MASTER_TRAN_COMP_INT_CLR_V 0x1 +#define I2C_MASTER_TRAN_COMP_INT_CLR_S 6 +/* I2C_ARBITRATION_LOST_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to clear the arbitration_lost_int interrupt.*/ +#define I2C_ARBITRATION_LOST_INT_CLR (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_CLR_M (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_CLR_V 0x1 +#define I2C_ARBITRATION_LOST_INT_CLR_S 5 +/* I2C_SLAVE_TRAN_COMP_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to clear the slave_tran_comp_int interrupt.*/ +#define I2C_SLAVE_TRAN_COMP_INT_CLR (BIT(4)) +#define I2C_SLAVE_TRAN_COMP_INT_CLR_M (BIT(4)) +#define I2C_SLAVE_TRAN_COMP_INT_CLR_V 0x1 +#define I2C_SLAVE_TRAN_COMP_INT_CLR_S 4 +/* I2C_END_DETECT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear the end_detect_int interrupt.*/ +#define I2C_END_DETECT_INT_CLR (BIT(3)) +#define I2C_END_DETECT_INT_CLR_M (BIT(3)) +#define I2C_END_DETECT_INT_CLR_V 0x1 +#define I2C_END_DETECT_INT_CLR_S 3 +/* I2C_RXFIFO_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rxfifo_ovf_int interrupt.*/ +#define I2C_RXFIFO_OVF_INT_CLR (BIT(2)) +#define I2C_RXFIFO_OVF_INT_CLR_M (BIT(2)) +#define I2C_RXFIFO_OVF_INT_CLR_V 0x1 +#define I2C_RXFIFO_OVF_INT_CLR_S 2 +/* I2C_TXFIFO_EMPTY_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear the txfifo_empty_int interrupt.*/ +#define I2C_TXFIFO_EMPTY_INT_CLR (BIT(1)) +#define I2C_TXFIFO_EMPTY_INT_CLR_M (BIT(1)) +#define I2C_TXFIFO_EMPTY_INT_CLR_V 0x1 +#define I2C_TXFIFO_EMPTY_INT_CLR_S 1 +/* I2C_RXFIFO_FULL_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rxfifo_full_int interrupt.*/ +#define I2C_RXFIFO_FULL_INT_CLR (BIT(0)) +#define I2C_RXFIFO_FULL_INT_CLR_M (BIT(0)) +#define I2C_RXFIFO_FULL_INT_CLR_V 0x1 +#define I2C_RXFIFO_FULL_INT_CLR_S 0 + +#define I2C_INT_ENA_REG(i) (REG_I2C_BASE(i) + 0x0028) +/* I2C_TX_SEND_EMPTY_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The enable bit for tx_send_empty_int interrupt.*/ +#define I2C_TX_SEND_EMPTY_INT_ENA (BIT(12)) +#define I2C_TX_SEND_EMPTY_INT_ENA_M (BIT(12)) +#define I2C_TX_SEND_EMPTY_INT_ENA_V 0x1 +#define I2C_TX_SEND_EMPTY_INT_ENA_S 12 +/* I2C_RX_REC_FULL_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The enable bit for rx_rec_full_int interrupt.*/ +#define I2C_RX_REC_FULL_INT_ENA (BIT(11)) +#define I2C_RX_REC_FULL_INT_ENA_M (BIT(11)) +#define I2C_RX_REC_FULL_INT_ENA_V 0x1 +#define I2C_RX_REC_FULL_INT_ENA_S 11 +/* I2C_ACK_ERR_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The enable bit for ack_err_int interrupt.*/ +#define I2C_ACK_ERR_INT_ENA (BIT(10)) +#define I2C_ACK_ERR_INT_ENA_M (BIT(10)) +#define I2C_ACK_ERR_INT_ENA_V 0x1 +#define I2C_ACK_ERR_INT_ENA_S 10 +/* I2C_TRANS_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The enable bit for trans_start_int interrupt.*/ +#define I2C_TRANS_START_INT_ENA (BIT(9)) +#define I2C_TRANS_START_INT_ENA_M (BIT(9)) +#define I2C_TRANS_START_INT_ENA_V 0x1 +#define I2C_TRANS_START_INT_ENA_S 9 +/* I2C_TIME_OUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The enable bit for time_out_int interrupt.*/ +#define I2C_TIME_OUT_INT_ENA (BIT(8)) +#define I2C_TIME_OUT_INT_ENA_M (BIT(8)) +#define I2C_TIME_OUT_INT_ENA_V 0x1 +#define I2C_TIME_OUT_INT_ENA_S 8 +/* I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The enable bit for trans_complete_int interrupt.*/ +#define I2C_TRANS_COMPLETE_INT_ENA (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ENA_M (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ENA_V 0x1 +#define I2C_TRANS_COMPLETE_INT_ENA_S 7 +/* I2C_MASTER_TRAN_COMP_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The enable bit for master_tran_comp_int interrupt.*/ +#define I2C_MASTER_TRAN_COMP_INT_ENA (BIT(6)) +#define I2C_MASTER_TRAN_COMP_INT_ENA_M (BIT(6)) +#define I2C_MASTER_TRAN_COMP_INT_ENA_V 0x1 +#define I2C_MASTER_TRAN_COMP_INT_ENA_S 6 +/* I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The enable bit for arbitration_lost_int interrupt.*/ +#define I2C_ARBITRATION_LOST_INT_ENA (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ENA_M (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ENA_V 0x1 +#define I2C_ARBITRATION_LOST_INT_ENA_S 5 +/* I2C_SLAVE_TRAN_COMP_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The enable bit for slave_tran_comp_int interrupt.*/ +#define I2C_SLAVE_TRAN_COMP_INT_ENA (BIT(4)) +#define I2C_SLAVE_TRAN_COMP_INT_ENA_M (BIT(4)) +#define I2C_SLAVE_TRAN_COMP_INT_ENA_V 0x1 +#define I2C_SLAVE_TRAN_COMP_INT_ENA_S 4 +/* I2C_END_DETECT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The enable bit for end_detect_int interrupt.*/ +#define I2C_END_DETECT_INT_ENA (BIT(3)) +#define I2C_END_DETECT_INT_ENA_M (BIT(3)) +#define I2C_END_DETECT_INT_ENA_V 0x1 +#define I2C_END_DETECT_INT_ENA_S 3 +/* I2C_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The enable bit for rxfifo_ovf_int interrupt.*/ +#define I2C_RXFIFO_OVF_INT_ENA (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ENA_M (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ENA_V 0x1 +#define I2C_RXFIFO_OVF_INT_ENA_S 2 +/* I2C_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The enable bit for txfifo_empty_int interrupt.*/ +#define I2C_TXFIFO_EMPTY_INT_ENA (BIT(1)) +#define I2C_TXFIFO_EMPTY_INT_ENA_M (BIT(1)) +#define I2C_TXFIFO_EMPTY_INT_ENA_V 0x1 +#define I2C_TXFIFO_EMPTY_INT_ENA_S 1 +/* I2C_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The enable bit for rxfifo_full_int interrupt.*/ +#define I2C_RXFIFO_FULL_INT_ENA (BIT(0)) +#define I2C_RXFIFO_FULL_INT_ENA_M (BIT(0)) +#define I2C_RXFIFO_FULL_INT_ENA_V 0x1 +#define I2C_RXFIFO_FULL_INT_ENA_S 0 + +#define I2C_INT_STATUS_REG(i) (REG_I2C_BASE(i) + 0x002c) +/* I2C_TX_SEND_EMPTY_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The masked interrupt status for tx_send_empty_int interrupt.*/ +#define I2C_TX_SEND_EMPTY_INT_ST (BIT(12)) +#define I2C_TX_SEND_EMPTY_INT_ST_M (BIT(12)) +#define I2C_TX_SEND_EMPTY_INT_ST_V 0x1 +#define I2C_TX_SEND_EMPTY_INT_ST_S 12 +/* I2C_RX_REC_FULL_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The masked interrupt status for rx_rec_full_int interrupt.*/ +#define I2C_RX_REC_FULL_INT_ST (BIT(11)) +#define I2C_RX_REC_FULL_INT_ST_M (BIT(11)) +#define I2C_RX_REC_FULL_INT_ST_V 0x1 +#define I2C_RX_REC_FULL_INT_ST_S 11 +/* I2C_ACK_ERR_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The masked interrupt status for ack_err_int interrupt.*/ +#define I2C_ACK_ERR_INT_ST (BIT(10)) +#define I2C_ACK_ERR_INT_ST_M (BIT(10)) +#define I2C_ACK_ERR_INT_ST_V 0x1 +#define I2C_ACK_ERR_INT_ST_S 10 +/* I2C_TRANS_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The masked interrupt status for trans_start_int interrupt.*/ +#define I2C_TRANS_START_INT_ST (BIT(9)) +#define I2C_TRANS_START_INT_ST_M (BIT(9)) +#define I2C_TRANS_START_INT_ST_V 0x1 +#define I2C_TRANS_START_INT_ST_S 9 +/* I2C_TIME_OUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The masked interrupt status for time_out_int interrupt.*/ +#define I2C_TIME_OUT_INT_ST (BIT(8)) +#define I2C_TIME_OUT_INT_ST_M (BIT(8)) +#define I2C_TIME_OUT_INT_ST_V 0x1 +#define I2C_TIME_OUT_INT_ST_S 8 +/* I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The masked interrupt status for trans_complete_int interrupt.*/ +#define I2C_TRANS_COMPLETE_INT_ST (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ST_M (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ST_V 0x1 +#define I2C_TRANS_COMPLETE_INT_ST_S 7 +/* I2C_MASTER_TRAN_COMP_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The masked interrupt status for master_tran_comp_int interrupt.*/ +#define I2C_MASTER_TRAN_COMP_INT_ST (BIT(6)) +#define I2C_MASTER_TRAN_COMP_INT_ST_M (BIT(6)) +#define I2C_MASTER_TRAN_COMP_INT_ST_V 0x1 +#define I2C_MASTER_TRAN_COMP_INT_ST_S 6 +/* I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The masked interrupt status for arbitration_lost_int interrupt.*/ +#define I2C_ARBITRATION_LOST_INT_ST (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ST_M (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ST_V 0x1 +#define I2C_ARBITRATION_LOST_INT_ST_S 5 +/* I2C_SLAVE_TRAN_COMP_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The masked interrupt status for slave_tran_comp_int interrupt.*/ +#define I2C_SLAVE_TRAN_COMP_INT_ST (BIT(4)) +#define I2C_SLAVE_TRAN_COMP_INT_ST_M (BIT(4)) +#define I2C_SLAVE_TRAN_COMP_INT_ST_V 0x1 +#define I2C_SLAVE_TRAN_COMP_INT_ST_S 4 +/* I2C_END_DETECT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The masked interrupt status for end_detect_int interrupt.*/ +#define I2C_END_DETECT_INT_ST (BIT(3)) +#define I2C_END_DETECT_INT_ST_M (BIT(3)) +#define I2C_END_DETECT_INT_ST_V 0x1 +#define I2C_END_DETECT_INT_ST_S 3 +/* I2C_RXFIFO_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The masked interrupt status for rxfifo_ovf_int interrupt.*/ +#define I2C_RXFIFO_OVF_INT_ST (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ST_M (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ST_V 0x1 +#define I2C_RXFIFO_OVF_INT_ST_S 2 +/* I2C_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The masked interrupt status for txfifo_empty_int interrupt.*/ +#define I2C_TXFIFO_EMPTY_INT_ST (BIT(1)) +#define I2C_TXFIFO_EMPTY_INT_ST_M (BIT(1)) +#define I2C_TXFIFO_EMPTY_INT_ST_V 0x1 +#define I2C_TXFIFO_EMPTY_INT_ST_S 1 +/* I2C_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The masked interrupt status for rxfifo_full_int interrupt.*/ +#define I2C_RXFIFO_FULL_INT_ST (BIT(0)) +#define I2C_RXFIFO_FULL_INT_ST_M (BIT(0)) +#define I2C_RXFIFO_FULL_INT_ST_V 0x1 +#define I2C_RXFIFO_FULL_INT_ST_S 0 + +#define I2C_SDA_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0030) +/* I2C_SDA_HOLD_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */ +/*description: This register is used to configure the clock num I2C used to + hold the data after the negedge of SCL.*/ +#define I2C_SDA_HOLD_TIME 0x000003FF +#define I2C_SDA_HOLD_TIME_M ((I2C_SDA_HOLD_TIME_V)<<(I2C_SDA_HOLD_TIME_S)) +#define I2C_SDA_HOLD_TIME_V 0x3FF +#define I2C_SDA_HOLD_TIME_S 0 + +#define I2C_SDA_SAMPLE_REG(i) (REG_I2C_BASE(i) + 0x0034) +/* I2C_SDA_SAMPLE_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */ +/*description: This register is used to configure the clock num I2C used to + sample data on SDA after the posedge of SCL*/ +#define I2C_SDA_SAMPLE_TIME 0x000003FF +#define I2C_SDA_SAMPLE_TIME_M ((I2C_SDA_SAMPLE_TIME_V)<<(I2C_SDA_SAMPLE_TIME_S)) +#define I2C_SDA_SAMPLE_TIME_V 0x3FF +#define I2C_SDA_SAMPLE_TIME_S 0 + +#define I2C_SCL_HIGH_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0038) +/* I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This register is used to configure the clock num during SCL is low level.*/ +#define I2C_SCL_HIGH_PERIOD 0x00003FFF +#define I2C_SCL_HIGH_PERIOD_M ((I2C_SCL_HIGH_PERIOD_V)<<(I2C_SCL_HIGH_PERIOD_S)) +#define I2C_SCL_HIGH_PERIOD_V 0x3FFF +#define I2C_SCL_HIGH_PERIOD_S 0 + +#define I2C_SCL_START_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0040) +/* I2C_SCL_START_HOLD_TIME : R/W ;bitpos:[9:0] ;default: 10'b1000 ; */ +/*description: This register is used to configure the clock num between the + negedge of SDA and negedge of SCL for start mark.*/ +#define I2C_SCL_START_HOLD_TIME 0x000003FF +#define I2C_SCL_START_HOLD_TIME_M ((I2C_SCL_START_HOLD_TIME_V)<<(I2C_SCL_START_HOLD_TIME_S)) +#define I2C_SCL_START_HOLD_TIME_V 0x3FF +#define I2C_SCL_START_HOLD_TIME_S 0 + +#define I2C_SCL_RSTART_SETUP_REG(i) (REG_I2C_BASE(i) + 0x0044) +/* I2C_SCL_RSTART_SETUP_TIME : R/W ;bitpos:[9:0] ;default: 10'b1000 ; */ +/*description: This register is used to configure the clock num between the + posedge of SCL and the negedge of SDA for restart mark.*/ +#define I2C_SCL_RSTART_SETUP_TIME 0x000003FF +#define I2C_SCL_RSTART_SETUP_TIME_M ((I2C_SCL_RSTART_SETUP_TIME_V)<<(I2C_SCL_RSTART_SETUP_TIME_S)) +#define I2C_SCL_RSTART_SETUP_TIME_V 0x3FF +#define I2C_SCL_RSTART_SETUP_TIME_S 0 + +#define I2C_SCL_STOP_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0048) +/* I2C_SCL_STOP_HOLD_TIME : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This register is used to configure the clock num after the STOP bit's posedge.*/ +#define I2C_SCL_STOP_HOLD_TIME 0x00003FFF +#define I2C_SCL_STOP_HOLD_TIME_M ((I2C_SCL_STOP_HOLD_TIME_V)<<(I2C_SCL_STOP_HOLD_TIME_S)) +#define I2C_SCL_STOP_HOLD_TIME_V 0x3FFF +#define I2C_SCL_STOP_HOLD_TIME_S 0 + +#define I2C_SCL_STOP_SETUP_REG(i) (REG_I2C_BASE(i) + 0x004C) +/* I2C_SCL_STOP_SETUP_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */ +/*description: This register is used to configure the clock num between the + posedge of SCL and the posedge of SDA.*/ +#define I2C_SCL_STOP_SETUP_TIME 0x000003FF +#define I2C_SCL_STOP_SETUP_TIME_M ((I2C_SCL_STOP_SETUP_TIME_V)<<(I2C_SCL_STOP_SETUP_TIME_S)) +#define I2C_SCL_STOP_SETUP_TIME_V 0x3FF +#define I2C_SCL_STOP_SETUP_TIME_S 0 + +#define I2C_SCL_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x0050) +/* I2C_SCL_FILTER_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: This is the filter enable bit for SCL.*/ +#define I2C_SCL_FILTER_EN (BIT(3)) +#define I2C_SCL_FILTER_EN_M (BIT(3)) +#define I2C_SCL_FILTER_EN_V 0x1 +#define I2C_SCL_FILTER_EN_S 3 +/* I2C_SCL_FILTER_THRES : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: When input SCL's pulse width is smaller than this register value + I2C ignores this pulse.*/ +#define I2C_SCL_FILTER_THRES 0x00000007 +#define I2C_SCL_FILTER_THRES_M ((I2C_SCL_FILTER_THRES_V)<<(I2C_SCL_FILTER_THRES_S)) +#define I2C_SCL_FILTER_THRES_V 0x7 +#define I2C_SCL_FILTER_THRES_S 0 + +#define I2C_SDA_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x0054) +/* I2C_SDA_FILTER_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: This is the filter enable bit for SDA.*/ +#define I2C_SDA_FILTER_EN (BIT(3)) +#define I2C_SDA_FILTER_EN_M (BIT(3)) +#define I2C_SDA_FILTER_EN_V 0x1 +#define I2C_SDA_FILTER_EN_S 3 +/* I2C_SDA_FILTER_THRES : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: When input SCL's pulse width is smaller than this register value + I2C ignores this pulse.*/ +#define I2C_SDA_FILTER_THRES 0x00000007 +#define I2C_SDA_FILTER_THRES_M ((I2C_SDA_FILTER_THRES_V)<<(I2C_SDA_FILTER_THRES_S)) +#define I2C_SDA_FILTER_THRES_V 0x7 +#define I2C_SDA_FILTER_THRES_S 0 + +#define I2C_COMD0_REG(i) (REG_I2C_BASE(i) + 0x0058) +/* I2C_COMMAND0_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command0 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND0_DONE (BIT(31)) +#define I2C_COMMAND0_DONE_M (BIT(31)) +#define I2C_COMMAND0_DONE_V 0x1 +#define I2C_COMMAND0_DONE_S 31 +/* I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command0. It consists of three part. op_code + is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND0 0x00003FFF +#define I2C_COMMAND0_M ((I2C_COMMAND0_V)<<(I2C_COMMAND0_S)) +#define I2C_COMMAND0_V 0x3FFF +#define I2C_COMMAND0_S 0 + +#define I2C_COMD1_REG(i) (REG_I2C_BASE(i) + 0x005C) +/* I2C_COMMAND1_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command1 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND1_DONE (BIT(31)) +#define I2C_COMMAND1_DONE_M (BIT(31)) +#define I2C_COMMAND1_DONE_V 0x1 +#define I2C_COMMAND1_DONE_S 31 +/* I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command1. It consists of three part. op_code + is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND1 0x00003FFF +#define I2C_COMMAND1_M ((I2C_COMMAND1_V)<<(I2C_COMMAND1_S)) +#define I2C_COMMAND1_V 0x3FFF +#define I2C_COMMAND1_S 0 + +#define I2C_COMD2_REG(i) (REG_I2C_BASE(i) + 0x0060) +/* I2C_COMMAND2_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command2 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND2_DONE (BIT(31)) +#define I2C_COMMAND2_DONE_M (BIT(31)) +#define I2C_COMMAND2_DONE_V 0x1 +#define I2C_COMMAND2_DONE_S 31 +/* I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command2. It consists of three part. op_code + is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND2 0x00003FFF +#define I2C_COMMAND2_M ((I2C_COMMAND2_V)<<(I2C_COMMAND2_S)) +#define I2C_COMMAND2_V 0x3FFF +#define I2C_COMMAND2_S 0 + +#define I2C_COMD3_REG(i) (REG_I2C_BASE(i) + 0x0064) +/* I2C_COMMAND3_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command3 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND3_DONE (BIT(31)) +#define I2C_COMMAND3_DONE_M (BIT(31)) +#define I2C_COMMAND3_DONE_V 0x1 +#define I2C_COMMAND3_DONE_S 31 +/* I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command3. It consists of three part. op_code + is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND3 0x00003FFF +#define I2C_COMMAND3_M ((I2C_COMMAND3_V)<<(I2C_COMMAND3_S)) +#define I2C_COMMAND3_V 0x3FFF +#define I2C_COMMAND3_S 0 + +#define I2C_COMD4_REG(i) (REG_I2C_BASE(i) + 0x0068) +/* I2C_COMMAND4_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command4 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND4_DONE (BIT(31)) +#define I2C_COMMAND4_DONE_M (BIT(31)) +#define I2C_COMMAND4_DONE_V 0x1 +#define I2C_COMMAND4_DONE_S 31 +/* I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command4. It consists of three part. op_code + is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND4 0x00003FFF +#define I2C_COMMAND4_M ((I2C_COMMAND4_V)<<(I2C_COMMAND4_S)) +#define I2C_COMMAND4_V 0x3FFF +#define I2C_COMMAND4_S 0 + +#define I2C_COMD5_REG(i) (REG_I2C_BASE(i) + 0x006C) +/* I2C_COMMAND5_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command5 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND5_DONE (BIT(31)) +#define I2C_COMMAND5_DONE_M (BIT(31)) +#define I2C_COMMAND5_DONE_V 0x1 +#define I2C_COMMAND5_DONE_S 31 +/* I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command5. It consists of three part. op_code + is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND5 0x00003FFF +#define I2C_COMMAND5_M ((I2C_COMMAND5_V)<<(I2C_COMMAND5_S)) +#define I2C_COMMAND5_V 0x3FFF +#define I2C_COMMAND5_S 0 + +#define I2C_COMD6_REG(i) (REG_I2C_BASE(i) + 0x0070) +/* I2C_COMMAND6_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command6 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND6_DONE (BIT(31)) +#define I2C_COMMAND6_DONE_M (BIT(31)) +#define I2C_COMMAND6_DONE_V 0x1 +#define I2C_COMMAND6_DONE_S 31 +/* I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command6. It consists of three part. op_code + is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND6 0x00003FFF +#define I2C_COMMAND6_M ((I2C_COMMAND6_V)<<(I2C_COMMAND6_S)) +#define I2C_COMMAND6_V 0x3FFF +#define I2C_COMMAND6_S 0 + +#define I2C_COMD7_REG(i) (REG_I2C_BASE(i) + 0x0074) +/* I2C_COMMAND7_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command7 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND7_DONE (BIT(31)) +#define I2C_COMMAND7_DONE_M (BIT(31)) +#define I2C_COMMAND7_DONE_V 0x1 +#define I2C_COMMAND7_DONE_S 31 +/* I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command7. It consists of three part. op_code + is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND7 0x00003FFF +#define I2C_COMMAND7_M ((I2C_COMMAND7_V)<<(I2C_COMMAND7_S)) +#define I2C_COMMAND7_V 0x3FFF +#define I2C_COMMAND7_S 0 + +#define I2C_COMD8_REG(i) (REG_I2C_BASE(i) + 0x0078) +/* I2C_COMMAND8_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command8 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND8_DONE (BIT(31)) +#define I2C_COMMAND8_DONE_M (BIT(31)) +#define I2C_COMMAND8_DONE_V 0x1 +#define I2C_COMMAND8_DONE_S 31 +/* I2C_COMMAND8 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command8. It consists of three part. op_code + is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND8 0x00003FFF +#define I2C_COMMAND8_M ((I2C_COMMAND8_V)<<(I2C_COMMAND8_S)) +#define I2C_COMMAND8_V 0x3FFF +#define I2C_COMMAND8_S 0 + +#define I2C_COMD9_REG(i) (REG_I2C_BASE(i) + 0x007C) +/* I2C_COMMAND9_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command9 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND9_DONE (BIT(31)) +#define I2C_COMMAND9_DONE_M (BIT(31)) +#define I2C_COMMAND9_DONE_V 0x1 +#define I2C_COMMAND9_DONE_S 31 +/* I2C_COMMAND9 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command9. It consists of three part. op_code + is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND9 0x00003FFF +#define I2C_COMMAND9_M ((I2C_COMMAND9_V)<<(I2C_COMMAND9_S)) +#define I2C_COMMAND9_V 0x3FFF +#define I2C_COMMAND9_S 0 + +#define I2C_COMD10_REG(i) (REG_I2C_BASE(i) + 0x0080) +/* I2C_COMMAND10_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command10 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND10_DONE (BIT(31)) +#define I2C_COMMAND10_DONE_M (BIT(31)) +#define I2C_COMMAND10_DONE_V 0x1 +#define I2C_COMMAND10_DONE_S 31 +/* I2C_COMMAND10 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command10. It consists of three part. + op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND10 0x00003FFF +#define I2C_COMMAND10_M ((I2C_COMMAND10_V)<<(I2C_COMMAND10_S)) +#define I2C_COMMAND10_V 0x3FFF +#define I2C_COMMAND10_S 0 + +#define I2C_COMD11_REG(i) (REG_I2C_BASE(i) + 0x0084) +/* I2C_COMMAND11_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command11 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND11_DONE (BIT(31)) +#define I2C_COMMAND11_DONE_M (BIT(31)) +#define I2C_COMMAND11_DONE_V 0x1 +#define I2C_COMMAND11_DONE_S 31 +/* I2C_COMMAND11 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command11. It consists of three part. + op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND11 0x00003FFF +#define I2C_COMMAND11_M ((I2C_COMMAND11_V)<<(I2C_COMMAND11_S)) +#define I2C_COMMAND11_V 0x3FFF +#define I2C_COMMAND11_S 0 + +#define I2C_COMD12_REG(i) (REG_I2C_BASE(i) + 0x0088) +/* I2C_COMMAND12_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command12 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND12_DONE (BIT(31)) +#define I2C_COMMAND12_DONE_M (BIT(31)) +#define I2C_COMMAND12_DONE_V 0x1 +#define I2C_COMMAND12_DONE_S 31 +/* I2C_COMMAND12 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command12. It consists of three part. + op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND12 0x00003FFF +#define I2C_COMMAND12_M ((I2C_COMMAND12_V)<<(I2C_COMMAND12_S)) +#define I2C_COMMAND12_V 0x3FFF +#define I2C_COMMAND12_S 0 + +#define I2C_COMD13_REG(i) (REG_I2C_BASE(i) + 0x008C) +/* I2C_COMMAND13_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command13 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND13_DONE (BIT(31)) +#define I2C_COMMAND13_DONE_M (BIT(31)) +#define I2C_COMMAND13_DONE_V 0x1 +#define I2C_COMMAND13_DONE_S 31 +/* I2C_COMMAND13 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command13. It consists of three part. + op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND13 0x00003FFF +#define I2C_COMMAND13_M ((I2C_COMMAND13_V)<<(I2C_COMMAND13_S)) +#define I2C_COMMAND13_V 0x3FFF +#define I2C_COMMAND13_S 0 + +#define I2C_COMD14_REG(i) (REG_I2C_BASE(i) + 0x0090) +/* I2C_COMMAND14_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command14 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND14_DONE (BIT(31)) +#define I2C_COMMAND14_DONE_M (BIT(31)) +#define I2C_COMMAND14_DONE_V 0x1 +#define I2C_COMMAND14_DONE_S 31 +/* I2C_COMMAND14 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command14. It consists of three part. + op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND14 0x00003FFF +#define I2C_COMMAND14_M ((I2C_COMMAND14_V)<<(I2C_COMMAND14_S)) +#define I2C_COMMAND14_V 0x3FFF +#define I2C_COMMAND14_S 0 + +#define I2C_COMD15_REG(i) (REG_I2C_BASE(i) + 0x0094) +/* I2C_COMMAND15_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command15 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND15_DONE (BIT(31)) +#define I2C_COMMAND15_DONE_M (BIT(31)) +#define I2C_COMMAND15_DONE_V 0x1 +#define I2C_COMMAND15_DONE_S 31 +/* I2C_COMMAND15 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command15. It consists of three part. + op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND15 0x00003FFF +#define I2C_COMMAND15_M ((I2C_COMMAND15_V)<<(I2C_COMMAND15_S)) +#define I2C_COMMAND15_V 0x3FFF +#define I2C_COMMAND15_S 0 + +#define I2C_DATE_REG(i) (REG_I2C_BASE(i) + 0x00F8) +/* I2C_DATE : R/W ;bitpos:[31:0] ;default: 32'h16042000 ; */ +/*description: */ +#define I2C_DATE 0xFFFFFFFF +#define I2C_DATE_M ((I2C_DATE_V)<<(I2C_DATE_S)) +#define I2C_DATE_V 0xFFFFFFFF +#define I2C_DATE_S 0 + +#define I2C_FIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x0100) + + + + +#endif /*_SOC_I2C_REG_H_ */ + + diff --git a/tools/sdk/include/esp32/soc/i2c_struct.h b/tools/sdk/include/esp32/soc/i2c_struct.h new file mode 100644 index 00000000..a29a9c52 --- /dev/null +++ b/tools/sdk/include/esp32/soc/i2c_struct.h @@ -0,0 +1,289 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_I2C_STRUCT_H_ +#define _SOC_I2C_STRUCT_H_ +typedef volatile struct { + union { + struct { + uint32_t scl_low_period:14; /*This register is used to configure the low level width of SCL clock.*/ + uint32_t reserved14: 18; + }; + uint32_t val; + } scl_low_period; + union { + struct { + uint32_t sda_force_out: 1; /*1：normally output sda data 0: exchange the function of sda_o and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal)*/ + uint32_t scl_force_out: 1; /*1：normally output scl clock 0: exchange the function of scl_o and scl_oe (scl_o is the original internal output scl signal scl_oe is the enable bit for the internal output scl signal)*/ + uint32_t sample_scl_level: 1; /*Set this bit to sample data in SCL low level. clear this bit to sample data in SCL high level.*/ + uint32_t reserved3: 1; + uint32_t ms_mode: 1; /*Set this bit to configure the module as i2c master clear this bit to configure the module as i2c slave.*/ + uint32_t trans_start: 1; /*Set this bit to start sending data in tx_fifo.*/ + uint32_t tx_lsb_first: 1; /*This bit is used to control the sending mode for data need to be send. 1：receive data from most significant bit 0：receive data from least significant bit*/ + uint32_t rx_lsb_first: 1; /*This bit is used to control the storage mode for received data. 1：receive data from most significant bit 0：receive data from least significant bit*/ + uint32_t clk_en: 1; /*This is the clock gating control bit for reading or writing registers.*/ + uint32_t reserved9: 23; + }; + uint32_t val; + } ctr; + union { + struct { + uint32_t ack_rec: 1; /*This register stores the value of ACK bit.*/ + uint32_t slave_rw: 1; /*when in slave mode 1：master read slave 0: master write slave.*/ + uint32_t time_out: 1; /*when I2C takes more than time_out_reg clocks to receive a data then this register changes to high level.*/ + uint32_t arb_lost: 1; /*when I2C lost control of SDA line this register changes to high level.*/ + uint32_t bus_busy: 1; /*1:I2C bus is busy transferring data. 0:I2C bus is in idle state.*/ + uint32_t slave_addressed: 1; /*when configured as i2c slave and the address send by master is equal to slave's address then this bit will be high level.*/ + uint32_t byte_trans: 1; /*This register changes to high level when one byte is transferred.*/ + uint32_t reserved7: 1; + uint32_t rx_fifo_cnt: 6; /*This register represent the amount of data need to send.*/ + uint32_t reserved14: 4; + uint32_t tx_fifo_cnt: 6; /*This register stores the amount of received data in ram.*/ + uint32_t scl_main_state_last: 3; /*This register stores the value of state machine for i2c module. 3'h0: SCL_MAIN_IDLE 3'h1: SCL_ADDRESS_SHIFT 3'h2: SCL_ACK_ADDRESS 3'h3: SCL_RX_DATA 3'h4 SCL_TX_DATA 3'h5:SCL_SEND_ACK 3'h6:SCL_WAIT_ACK*/ + uint32_t reserved27: 1; + uint32_t scl_state_last: 3; /*This register stores the value of state machine to produce SCL. 3'h0: SCL_IDLE 3'h1:SCL_START 3'h2:SCL_LOW_EDGE 3'h3: SCL_LOW 3'h4:SCL_HIGH_EDGE 3'h5:SCL_HIGH 3'h6:SCL_STOP*/ + uint32_t reserved31: 1; + }; + uint32_t val; + } status_reg; + union { + struct { + uint32_t tout: 20; /*This register is used to configure the max clock number of receiving a data.*/ + uint32_t reserved20:12; + }; + uint32_t val; + } timeout; + union { + struct { + uint32_t addr: 15; /*when configured as i2c slave this register is used to configure slave's address.*/ + uint32_t reserved15: 16; + uint32_t en_10bit: 1; /*This register is used to enable slave 10bit address mode.*/ + }; + uint32_t val; + } slave_addr; + union { + struct { + uint32_t rx_fifo_start_addr: 5; /*This is the offset address of the last receiving data as described in nonfifo_rx_thres_register.*/ + uint32_t rx_fifo_end_addr: 5; /*This is the offset address of the first receiving data as described in nonfifo_rx_thres_register.*/ + uint32_t tx_fifo_start_addr: 5; /*This is the offset address of the first sending data as described in nonfifo_tx_thres register.*/ + uint32_t tx_fifo_end_addr: 5; /*This is the offset address of the last sending data as described in nonfifo_tx_thres register.*/ + uint32_t reserved20: 12; + }; + uint32_t val; + } fifo_st; + union { + struct { + uint32_t rx_fifo_full_thrhd: 5; + uint32_t tx_fifo_empty_thrhd:5; /*Config tx_fifo empty threhd value when using apb fifo access*/ + uint32_t nonfifo_en: 1; /*Set this bit to enble apb nonfifo access.*/ + uint32_t fifo_addr_cfg_en: 1; /*When this bit is set to 1 then the byte after address represent the offset address of I2C Slave's ram.*/ + uint32_t rx_fifo_rst: 1; /*Set this bit to reset rx fifo when using apb fifo access.*/ + uint32_t tx_fifo_rst: 1; /*Set this bit to reset tx fifo when using apb fifo access.*/ + uint32_t nonfifo_rx_thres: 6; /*when I2C receives more than nonfifo_rx_thres data it will produce rx_send_full_int_raw interrupt and update the current offset address of the receiving data.*/ + uint32_t nonfifo_tx_thres: 6; /*when I2C sends more than nonfifo_tx_thres data it will produce tx_send_empty_int_raw interrupt and update the current offset address of the sending data.*/ + uint32_t reserved26: 6; + }; + uint32_t val; + } fifo_conf; + union { + struct { + uint8_t data; /*The register represent the byte data read from rx_fifo when use apb fifo access*/ + uint8_t reserved[3]; + }; + uint32_t val; + } fifo_data; + union { + struct { + uint32_t rx_fifo_full: 1; /*The raw interrupt status bit for rx_fifo full when use apb fifo access.*/ + uint32_t tx_fifo_empty: 1; /*The raw interrupt status bit for tx_fifo empty when use apb fifo access.*/ + uint32_t rx_fifo_ovf: 1; /*The raw interrupt status bit for receiving data overflow when use apb fifo access.*/ + uint32_t end_detect: 1; /*The raw interrupt status bit for end_detect_int interrupt. when I2C deals with the END command it will produce end_detect_int interrupt.*/ + uint32_t slave_tran_comp: 1; /*The raw interrupt status bit for slave_tran_comp_int interrupt. when I2C Slave detects the STOP bit it will produce slave_tran_comp_int interrupt.*/ + uint32_t arbitration_lost: 1; /*The raw interrupt status bit for arbitration_lost_int interrupt.when I2C lost the usage right of I2C BUS it will produce arbitration_lost_int interrupt.*/ + uint32_t master_tran_comp: 1; /*The raw interrupt status bit for master_tra_comp_int interrupt. when I2C Master sends or receives a byte it will produce master_tran_comp_int interrupt.*/ + uint32_t trans_complete: 1; /*The raw interrupt status bit for trans_complete_int interrupt. when I2C Master finished STOP command it will produce trans_complete_int interrupt.*/ + uint32_t time_out: 1; /*The raw interrupt status bit for time_out_int interrupt. when I2C takes a lot of time to receive a data it will produce time_out_int interrupt.*/ + uint32_t trans_start: 1; /*The raw interrupt status bit for trans_start_int interrupt. when I2C sends the START bit it will produce trans_start_int interrupt.*/ + uint32_t ack_err: 1; /*The raw interrupt status bit for ack_err_int interrupt. when I2C receives a wrong ACK bit it will produce ack_err_int interrupt..*/ + uint32_t rx_rec_full: 1; /*The raw interrupt status bit for rx_rec_full_int interrupt. when I2C receives more data than nonfifo_rx_thres it will produce rx_rec_full_int interrupt.*/ + uint32_t tx_send_empty: 1; /*The raw interrupt status bit for tx_send_empty_int interrupt.when I2C sends more data than nonfifo_tx_thres it will produce tx_send_empty_int interrupt..*/ + uint32_t reserved13: 19; + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t rx_fifo_full: 1; /*Set this bit to clear the rx_fifo_full_int interrupt.*/ + uint32_t tx_fifo_empty: 1; /*Set this bit to clear the tx_fifo_empty_int interrupt.*/ + uint32_t rx_fifo_ovf: 1; /*Set this bit to clear the rx_fifo_ovf_int interrupt.*/ + uint32_t end_detect: 1; /*Set this bit to clear the end_detect_int interrupt.*/ + uint32_t slave_tran_comp: 1; /*Set this bit to clear the slave_tran_comp_int interrupt.*/ + uint32_t arbitration_lost: 1; /*Set this bit to clear the arbitration_lost_int interrupt.*/ + uint32_t master_tran_comp: 1; /*Set this bit to clear the master_tran_comp interrupt.*/ + uint32_t trans_complete: 1; /*Set this bit to clear the trans_complete_int interrupt.*/ + uint32_t time_out: 1; /*Set this bit to clear the time_out_int interrupt.*/ + uint32_t trans_start: 1; /*Set this bit to clear the trans_start_int interrupt.*/ + uint32_t ack_err: 1; /*Set this bit to clear the ack_err_int interrupt.*/ + uint32_t rx_rec_full: 1; /*Set this bit to clear the rx_rec_full_int interrupt.*/ + uint32_t tx_send_empty: 1; /*Set this bit to clear the tx_send_empty_int interrupt.*/ + uint32_t reserved13: 19; + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t rx_fifo_full: 1; /*The enable bit for rx_fifo_full_int interrupt.*/ + uint32_t tx_fifo_empty: 1; /*The enable bit for tx_fifo_empty_int interrupt.*/ + uint32_t rx_fifo_ovf: 1; /*The enable bit for rx_fifo_ovf_int interrupt.*/ + uint32_t end_detect: 1; /*The enable bit for end_detect_int interrupt.*/ + uint32_t slave_tran_comp: 1; /*The enable bit for slave_tran_comp_int interrupt.*/ + uint32_t arbitration_lost: 1; /*The enable bit for arbitration_lost_int interrupt.*/ + uint32_t master_tran_comp: 1; /*The enable bit for master_tran_comp_int interrupt.*/ + uint32_t trans_complete: 1; /*The enable bit for trans_complete_int interrupt.*/ + uint32_t time_out: 1; /*The enable bit for time_out_int interrupt.*/ + uint32_t trans_start: 1; /*The enable bit for trans_start_int interrupt.*/ + uint32_t ack_err: 1; /*The enable bit for ack_err_int interrupt.*/ + uint32_t rx_rec_full: 1; /*The enable bit for rx_rec_full_int interrupt.*/ + uint32_t tx_send_empty: 1; /*The enable bit for tx_send_empty_int interrupt.*/ + uint32_t reserved13: 19; + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t rx_fifo_full: 1; /*The masked interrupt status for rx_fifo_full_int interrupt.*/ + uint32_t tx_fifo_empty: 1; /*The masked interrupt status for tx_fifo_empty_int interrupt.*/ + uint32_t rx_fifo_ovf: 1; /*The masked interrupt status for rx_fifo_ovf_int interrupt.*/ + uint32_t end_detect: 1; /*The masked interrupt status for end_detect_int interrupt.*/ + uint32_t slave_tran_comp: 1; /*The masked interrupt status for slave_tran_comp_int interrupt.*/ + uint32_t arbitration_lost: 1; /*The masked interrupt status for arbitration_lost_int interrupt.*/ + uint32_t master_tran_comp: 1; /*The masked interrupt status for master_tran_comp_int interrupt.*/ + uint32_t trans_complete: 1; /*The masked interrupt status for trans_complete_int interrupt.*/ + uint32_t time_out: 1; /*The masked interrupt status for time_out_int interrupt.*/ + uint32_t trans_start: 1; /*The masked interrupt status for trans_start_int interrupt.*/ + uint32_t ack_err: 1; /*The masked interrupt status for ack_err_int interrupt.*/ + uint32_t rx_rec_full: 1; /*The masked interrupt status for rx_rec_full_int interrupt.*/ + uint32_t tx_send_empty: 1; /*The masked interrupt status for tx_send_empty_int interrupt.*/ + uint32_t reserved13: 19; + }; + uint32_t val; + } int_status; + union { + struct { + uint32_t time: 10; /*This register is used to configure the clock num I2C used to hold the data after the negedge of SCL.*/ + uint32_t reserved10: 22; + }; + uint32_t val; + } sda_hold; + union { + struct { + uint32_t time: 10; /*This register is used to configure the clock num I2C used to sample data on SDA after the posedge of SCL*/ + uint32_t reserved10: 22; + }; + uint32_t val; + } sda_sample; + union { + struct { + uint32_t period: 14; /*This register is used to configure the clock num during SCL is low level.*/ + uint32_t reserved14: 18; + }; + uint32_t val; + } scl_high_period; + uint32_t reserved_3c; + union { + struct { + uint32_t time: 10; /*This register is used to configure the clock num between the negedge of SDA and negedge of SCL for start mark.*/ + uint32_t reserved10: 22; + }; + uint32_t val; + } scl_start_hold; + union { + struct { + uint32_t time: 10; /*This register is used to configure the clock num between the posedge of SCL and the negedge of SDA for restart mark.*/ + uint32_t reserved10: 22; + }; + uint32_t val; + } scl_rstart_setup; + union { + struct { + uint32_t time: 14; /*This register is used to configure the clock num after the STOP bit's posedge.*/ + uint32_t reserved14: 18; + }; + uint32_t val; + } scl_stop_hold; + union { + struct { + uint32_t time: 10; /*This register is used to configure the clock num between the posedge of SCL and the posedge of SDA.*/ + uint32_t reserved10: 22; + }; + uint32_t val; + } scl_stop_setup; + union { + struct { + uint32_t thres: 3; /*When input SCL's pulse width is smaller than this register value I2C ignores this pulse.*/ + uint32_t en: 1; /*This is the filter enable bit for SCL.*/ + uint32_t reserved4: 28; + }; + uint32_t val; + } scl_filter_cfg; + union { + struct { + uint32_t thres: 3; /*When input SCL's pulse width is smaller than this register value I2C ignores this pulse.*/ + uint32_t en: 1; /*This is the filter enable bit for SDA.*/ + uint32_t reserved4: 28; + }; + uint32_t val; + } sda_filter_cfg; + union { + struct { + uint32_t byte_num: 8; /*Byte_num represent the number of data need to be send or data need to be received.*/ + uint32_t ack_en: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ + uint32_t ack_exp: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ + uint32_t ack_val: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ + uint32_t op_code: 3; /*op_code is the command 0：RSTART 1：WRITE 2：READ 3：STOP . 4:END.*/ + uint32_t reserved14: 17; + uint32_t done: 1; /*When command0 is done in I2C Master mode this bit changes to high level.*/ + }; + uint32_t val; + } command[16]; + uint32_t reserved_98; + uint32_t reserved_9c; + uint32_t reserved_a0; + uint32_t reserved_a4; + uint32_t reserved_a8; + uint32_t reserved_ac; + uint32_t reserved_b0; + uint32_t reserved_b4; + uint32_t reserved_b8; + uint32_t reserved_bc; + uint32_t reserved_c0; + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t reserved_cc; + uint32_t reserved_d0; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t date; /**/ + uint32_t reserved_fc; + uint32_t fifo_start_addr; /*This the start address for ram when use apb nonfifo access.*/ +} i2c_dev_t; +extern i2c_dev_t I2C0; +extern i2c_dev_t I2C1; +#endif /* _SOC_I2C_STRUCT_H_ */ diff --git a/tools/sdk/include/esp32/soc/i2s_reg.h b/tools/sdk/include/esp32/soc/i2s_reg.h new file mode 100644 index 00000000..3473c087 --- /dev/null +++ b/tools/sdk/include/esp32/soc/i2s_reg.h @@ -0,0 +1,1527 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_I2S_REG_H_ +#define _SOC_I2S_REG_H_ + +#include "soc.h" + +#define REG_I2S_BASE( i ) ( DR_REG_I2S_BASE + ((i)*0x1E000)) + + +#define I2S_CONF_REG(i) (REG_I2S_BASE(i) + 0x0008) +/* I2S_SIG_LOOPBACK : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define I2S_SIG_LOOPBACK (BIT(18)) +#define I2S_SIG_LOOPBACK_M (BIT(18)) +#define I2S_SIG_LOOPBACK_V 0x1 +#define I2S_SIG_LOOPBACK_S 18 +/* I2S_RX_MSB_RIGHT : R/W ;bitpos:[17] ;default: 1'b1 ; */ +/*description: */ +#define I2S_RX_MSB_RIGHT (BIT(17)) +#define I2S_RX_MSB_RIGHT_M (BIT(17)) +#define I2S_RX_MSB_RIGHT_V 0x1 +#define I2S_RX_MSB_RIGHT_S 17 +/* I2S_TX_MSB_RIGHT : R/W ;bitpos:[16] ;default: 1'b1 ; */ +/*description: */ +#define I2S_TX_MSB_RIGHT (BIT(16)) +#define I2S_TX_MSB_RIGHT_M (BIT(16)) +#define I2S_TX_MSB_RIGHT_V 0x1 +#define I2S_TX_MSB_RIGHT_S 16 +/* I2S_RX_MONO : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_MONO (BIT(15)) +#define I2S_RX_MONO_M (BIT(15)) +#define I2S_RX_MONO_V 0x1 +#define I2S_RX_MONO_S 15 +/* I2S_TX_MONO : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_MONO (BIT(14)) +#define I2S_TX_MONO_M (BIT(14)) +#define I2S_TX_MONO_V 0x1 +#define I2S_TX_MONO_S 14 +/* I2S_RX_SHORT_SYNC : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_SHORT_SYNC (BIT(13)) +#define I2S_RX_SHORT_SYNC_M (BIT(13)) +#define I2S_RX_SHORT_SYNC_V 0x1 +#define I2S_RX_SHORT_SYNC_S 13 +/* I2S_TX_SHORT_SYNC : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_SHORT_SYNC (BIT(12)) +#define I2S_TX_SHORT_SYNC_M (BIT(12)) +#define I2S_TX_SHORT_SYNC_V 0x1 +#define I2S_TX_SHORT_SYNC_S 12 +/* I2S_RX_MSB_SHIFT : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_MSB_SHIFT (BIT(11)) +#define I2S_RX_MSB_SHIFT_M (BIT(11)) +#define I2S_RX_MSB_SHIFT_V 0x1 +#define I2S_RX_MSB_SHIFT_S 11 +/* I2S_TX_MSB_SHIFT : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_MSB_SHIFT (BIT(10)) +#define I2S_TX_MSB_SHIFT_M (BIT(10)) +#define I2S_TX_MSB_SHIFT_V 0x1 +#define I2S_TX_MSB_SHIFT_S 10 +/* I2S_RX_RIGHT_FIRST : R/W ;bitpos:[9] ;default: 1'b1 ; */ +/*description: */ +#define I2S_RX_RIGHT_FIRST (BIT(9)) +#define I2S_RX_RIGHT_FIRST_M (BIT(9)) +#define I2S_RX_RIGHT_FIRST_V 0x1 +#define I2S_RX_RIGHT_FIRST_S 9 +/* I2S_TX_RIGHT_FIRST : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: */ +#define I2S_TX_RIGHT_FIRST (BIT(8)) +#define I2S_TX_RIGHT_FIRST_M (BIT(8)) +#define I2S_TX_RIGHT_FIRST_V 0x1 +#define I2S_TX_RIGHT_FIRST_S 8 +/* I2S_RX_SLAVE_MOD : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_SLAVE_MOD (BIT(7)) +#define I2S_RX_SLAVE_MOD_M (BIT(7)) +#define I2S_RX_SLAVE_MOD_V 0x1 +#define I2S_RX_SLAVE_MOD_S 7 +/* I2S_TX_SLAVE_MOD : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_SLAVE_MOD (BIT(6)) +#define I2S_TX_SLAVE_MOD_M (BIT(6)) +#define I2S_TX_SLAVE_MOD_V 0x1 +#define I2S_TX_SLAVE_MOD_S 6 +/* I2S_RX_START : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_START (BIT(5)) +#define I2S_RX_START_M (BIT(5)) +#define I2S_RX_START_V 0x1 +#define I2S_RX_START_S 5 +/* I2S_TX_START : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_START (BIT(4)) +#define I2S_TX_START_M (BIT(4)) +#define I2S_TX_START_V 0x1 +#define I2S_TX_START_S 4 +/* I2S_RX_FIFO_RESET : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_FIFO_RESET (BIT(3)) +#define I2S_RX_FIFO_RESET_M (BIT(3)) +#define I2S_RX_FIFO_RESET_V 0x1 +#define I2S_RX_FIFO_RESET_S 3 +/* I2S_TX_FIFO_RESET : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_FIFO_RESET (BIT(2)) +#define I2S_TX_FIFO_RESET_M (BIT(2)) +#define I2S_TX_FIFO_RESET_V 0x1 +#define I2S_TX_FIFO_RESET_S 2 +/* I2S_RX_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_RESET (BIT(1)) +#define I2S_RX_RESET_M (BIT(1)) +#define I2S_RX_RESET_V 0x1 +#define I2S_RX_RESET_S 1 +/* I2S_TX_RESET : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_RESET (BIT(0)) +#define I2S_TX_RESET_M (BIT(0)) +#define I2S_TX_RESET_V 0x1 +#define I2S_TX_RESET_S 0 + +#define I2S_INT_RAW_REG(i) (REG_I2S_BASE(i) + 0x000c) +/* I2S_OUT_TOTAL_EOF_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUT_TOTAL_EOF_INT_RAW (BIT(16)) +#define I2S_OUT_TOTAL_EOF_INT_RAW_M (BIT(16)) +#define I2S_OUT_TOTAL_EOF_INT_RAW_V 0x1 +#define I2S_OUT_TOTAL_EOF_INT_RAW_S 16 +/* I2S_IN_DSCR_EMPTY_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define I2S_IN_DSCR_EMPTY_INT_RAW (BIT(15)) +#define I2S_IN_DSCR_EMPTY_INT_RAW_M (BIT(15)) +#define I2S_IN_DSCR_EMPTY_INT_RAW_V 0x1 +#define I2S_IN_DSCR_EMPTY_INT_RAW_S 15 +/* I2S_OUT_DSCR_ERR_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUT_DSCR_ERR_INT_RAW (BIT(14)) +#define I2S_OUT_DSCR_ERR_INT_RAW_M (BIT(14)) +#define I2S_OUT_DSCR_ERR_INT_RAW_V 0x1 +#define I2S_OUT_DSCR_ERR_INT_RAW_S 14 +/* I2S_IN_DSCR_ERR_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define I2S_IN_DSCR_ERR_INT_RAW (BIT(13)) +#define I2S_IN_DSCR_ERR_INT_RAW_M (BIT(13)) +#define I2S_IN_DSCR_ERR_INT_RAW_V 0x1 +#define I2S_IN_DSCR_ERR_INT_RAW_S 13 +/* I2S_OUT_EOF_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUT_EOF_INT_RAW (BIT(12)) +#define I2S_OUT_EOF_INT_RAW_M (BIT(12)) +#define I2S_OUT_EOF_INT_RAW_V 0x1 +#define I2S_OUT_EOF_INT_RAW_S 12 +/* I2S_OUT_DONE_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUT_DONE_INT_RAW (BIT(11)) +#define I2S_OUT_DONE_INT_RAW_M (BIT(11)) +#define I2S_OUT_DONE_INT_RAW_V 0x1 +#define I2S_OUT_DONE_INT_RAW_S 11 +/* I2S_IN_ERR_EOF_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define I2S_IN_ERR_EOF_INT_RAW (BIT(10)) +#define I2S_IN_ERR_EOF_INT_RAW_M (BIT(10)) +#define I2S_IN_ERR_EOF_INT_RAW_V 0x1 +#define I2S_IN_ERR_EOF_INT_RAW_S 10 +/* I2S_IN_SUC_EOF_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define I2S_IN_SUC_EOF_INT_RAW (BIT(9)) +#define I2S_IN_SUC_EOF_INT_RAW_M (BIT(9)) +#define I2S_IN_SUC_EOF_INT_RAW_V 0x1 +#define I2S_IN_SUC_EOF_INT_RAW_S 9 +/* I2S_IN_DONE_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define I2S_IN_DONE_INT_RAW (BIT(8)) +#define I2S_IN_DONE_INT_RAW_M (BIT(8)) +#define I2S_IN_DONE_INT_RAW_V 0x1 +#define I2S_IN_DONE_INT_RAW_S 8 +/* I2S_TX_HUNG_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_HUNG_INT_RAW (BIT(7)) +#define I2S_TX_HUNG_INT_RAW_M (BIT(7)) +#define I2S_TX_HUNG_INT_RAW_V 0x1 +#define I2S_TX_HUNG_INT_RAW_S 7 +/* I2S_RX_HUNG_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_HUNG_INT_RAW (BIT(6)) +#define I2S_RX_HUNG_INT_RAW_M (BIT(6)) +#define I2S_RX_HUNG_INT_RAW_V 0x1 +#define I2S_RX_HUNG_INT_RAW_S 6 +/* I2S_TX_REMPTY_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_REMPTY_INT_RAW (BIT(5)) +#define I2S_TX_REMPTY_INT_RAW_M (BIT(5)) +#define I2S_TX_REMPTY_INT_RAW_V 0x1 +#define I2S_TX_REMPTY_INT_RAW_S 5 +/* I2S_TX_WFULL_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_WFULL_INT_RAW (BIT(4)) +#define I2S_TX_WFULL_INT_RAW_M (BIT(4)) +#define I2S_TX_WFULL_INT_RAW_V 0x1 +#define I2S_TX_WFULL_INT_RAW_S 4 +/* I2S_RX_REMPTY_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_REMPTY_INT_RAW (BIT(3)) +#define I2S_RX_REMPTY_INT_RAW_M (BIT(3)) +#define I2S_RX_REMPTY_INT_RAW_V 0x1 +#define I2S_RX_REMPTY_INT_RAW_S 3 +/* I2S_RX_WFULL_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_WFULL_INT_RAW (BIT(2)) +#define I2S_RX_WFULL_INT_RAW_M (BIT(2)) +#define I2S_RX_WFULL_INT_RAW_V 0x1 +#define I2S_RX_WFULL_INT_RAW_S 2 +/* I2S_TX_PUT_DATA_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_PUT_DATA_INT_RAW (BIT(1)) +#define I2S_TX_PUT_DATA_INT_RAW_M (BIT(1)) +#define I2S_TX_PUT_DATA_INT_RAW_V 0x1 +#define I2S_TX_PUT_DATA_INT_RAW_S 1 +/* I2S_RX_TAKE_DATA_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_TAKE_DATA_INT_RAW (BIT(0)) +#define I2S_RX_TAKE_DATA_INT_RAW_M (BIT(0)) +#define I2S_RX_TAKE_DATA_INT_RAW_V 0x1 +#define I2S_RX_TAKE_DATA_INT_RAW_S 0 + +#define I2S_INT_ST_REG(i) (REG_I2S_BASE(i) + 0x0010) +/* I2S_OUT_TOTAL_EOF_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUT_TOTAL_EOF_INT_ST (BIT(16)) +#define I2S_OUT_TOTAL_EOF_INT_ST_M (BIT(16)) +#define I2S_OUT_TOTAL_EOF_INT_ST_V 0x1 +#define I2S_OUT_TOTAL_EOF_INT_ST_S 16 +/* I2S_IN_DSCR_EMPTY_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define I2S_IN_DSCR_EMPTY_INT_ST (BIT(15)) +#define I2S_IN_DSCR_EMPTY_INT_ST_M (BIT(15)) +#define I2S_IN_DSCR_EMPTY_INT_ST_V 0x1 +#define I2S_IN_DSCR_EMPTY_INT_ST_S 15 +/* I2S_OUT_DSCR_ERR_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUT_DSCR_ERR_INT_ST (BIT(14)) +#define I2S_OUT_DSCR_ERR_INT_ST_M (BIT(14)) +#define I2S_OUT_DSCR_ERR_INT_ST_V 0x1 +#define I2S_OUT_DSCR_ERR_INT_ST_S 14 +/* I2S_IN_DSCR_ERR_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define I2S_IN_DSCR_ERR_INT_ST (BIT(13)) +#define I2S_IN_DSCR_ERR_INT_ST_M (BIT(13)) +#define I2S_IN_DSCR_ERR_INT_ST_V 0x1 +#define I2S_IN_DSCR_ERR_INT_ST_S 13 +/* I2S_OUT_EOF_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUT_EOF_INT_ST (BIT(12)) +#define I2S_OUT_EOF_INT_ST_M (BIT(12)) +#define I2S_OUT_EOF_INT_ST_V 0x1 +#define I2S_OUT_EOF_INT_ST_S 12 +/* I2S_OUT_DONE_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUT_DONE_INT_ST (BIT(11)) +#define I2S_OUT_DONE_INT_ST_M (BIT(11)) +#define I2S_OUT_DONE_INT_ST_V 0x1 +#define I2S_OUT_DONE_INT_ST_S 11 +/* I2S_IN_ERR_EOF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define I2S_IN_ERR_EOF_INT_ST (BIT(10)) +#define I2S_IN_ERR_EOF_INT_ST_M (BIT(10)) +#define I2S_IN_ERR_EOF_INT_ST_V 0x1 +#define I2S_IN_ERR_EOF_INT_ST_S 10 +/* I2S_IN_SUC_EOF_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define I2S_IN_SUC_EOF_INT_ST (BIT(9)) +#define I2S_IN_SUC_EOF_INT_ST_M (BIT(9)) +#define I2S_IN_SUC_EOF_INT_ST_V 0x1 +#define I2S_IN_SUC_EOF_INT_ST_S 9 +/* I2S_IN_DONE_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define I2S_IN_DONE_INT_ST (BIT(8)) +#define I2S_IN_DONE_INT_ST_M (BIT(8)) +#define I2S_IN_DONE_INT_ST_V 0x1 +#define I2S_IN_DONE_INT_ST_S 8 +/* I2S_TX_HUNG_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_HUNG_INT_ST (BIT(7)) +#define I2S_TX_HUNG_INT_ST_M (BIT(7)) +#define I2S_TX_HUNG_INT_ST_V 0x1 +#define I2S_TX_HUNG_INT_ST_S 7 +/* I2S_RX_HUNG_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_HUNG_INT_ST (BIT(6)) +#define I2S_RX_HUNG_INT_ST_M (BIT(6)) +#define I2S_RX_HUNG_INT_ST_V 0x1 +#define I2S_RX_HUNG_INT_ST_S 6 +/* I2S_TX_REMPTY_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_REMPTY_INT_ST (BIT(5)) +#define I2S_TX_REMPTY_INT_ST_M (BIT(5)) +#define I2S_TX_REMPTY_INT_ST_V 0x1 +#define I2S_TX_REMPTY_INT_ST_S 5 +/* I2S_TX_WFULL_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_WFULL_INT_ST (BIT(4)) +#define I2S_TX_WFULL_INT_ST_M (BIT(4)) +#define I2S_TX_WFULL_INT_ST_V 0x1 +#define I2S_TX_WFULL_INT_ST_S 4 +/* I2S_RX_REMPTY_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_REMPTY_INT_ST (BIT(3)) +#define I2S_RX_REMPTY_INT_ST_M (BIT(3)) +#define I2S_RX_REMPTY_INT_ST_V 0x1 +#define I2S_RX_REMPTY_INT_ST_S 3 +/* I2S_RX_WFULL_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_WFULL_INT_ST (BIT(2)) +#define I2S_RX_WFULL_INT_ST_M (BIT(2)) +#define I2S_RX_WFULL_INT_ST_V 0x1 +#define I2S_RX_WFULL_INT_ST_S 2 +/* I2S_TX_PUT_DATA_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_PUT_DATA_INT_ST (BIT(1)) +#define I2S_TX_PUT_DATA_INT_ST_M (BIT(1)) +#define I2S_TX_PUT_DATA_INT_ST_V 0x1 +#define I2S_TX_PUT_DATA_INT_ST_S 1 +/* I2S_RX_TAKE_DATA_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_TAKE_DATA_INT_ST (BIT(0)) +#define I2S_RX_TAKE_DATA_INT_ST_M (BIT(0)) +#define I2S_RX_TAKE_DATA_INT_ST_V 0x1 +#define I2S_RX_TAKE_DATA_INT_ST_S 0 + +#define I2S_INT_ENA_REG(i) (REG_I2S_BASE(i) + 0x0014) +/* I2S_OUT_TOTAL_EOF_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUT_TOTAL_EOF_INT_ENA (BIT(16)) +#define I2S_OUT_TOTAL_EOF_INT_ENA_M (BIT(16)) +#define I2S_OUT_TOTAL_EOF_INT_ENA_V 0x1 +#define I2S_OUT_TOTAL_EOF_INT_ENA_S 16 +/* I2S_IN_DSCR_EMPTY_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define I2S_IN_DSCR_EMPTY_INT_ENA (BIT(15)) +#define I2S_IN_DSCR_EMPTY_INT_ENA_M (BIT(15)) +#define I2S_IN_DSCR_EMPTY_INT_ENA_V 0x1 +#define I2S_IN_DSCR_EMPTY_INT_ENA_S 15 +/* I2S_OUT_DSCR_ERR_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUT_DSCR_ERR_INT_ENA (BIT(14)) +#define I2S_OUT_DSCR_ERR_INT_ENA_M (BIT(14)) +#define I2S_OUT_DSCR_ERR_INT_ENA_V 0x1 +#define I2S_OUT_DSCR_ERR_INT_ENA_S 14 +/* I2S_IN_DSCR_ERR_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define I2S_IN_DSCR_ERR_INT_ENA (BIT(13)) +#define I2S_IN_DSCR_ERR_INT_ENA_M (BIT(13)) +#define I2S_IN_DSCR_ERR_INT_ENA_V 0x1 +#define I2S_IN_DSCR_ERR_INT_ENA_S 13 +/* I2S_OUT_EOF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUT_EOF_INT_ENA (BIT(12)) +#define I2S_OUT_EOF_INT_ENA_M (BIT(12)) +#define I2S_OUT_EOF_INT_ENA_V 0x1 +#define I2S_OUT_EOF_INT_ENA_S 12 +/* I2S_OUT_DONE_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUT_DONE_INT_ENA (BIT(11)) +#define I2S_OUT_DONE_INT_ENA_M (BIT(11)) +#define I2S_OUT_DONE_INT_ENA_V 0x1 +#define I2S_OUT_DONE_INT_ENA_S 11 +/* I2S_IN_ERR_EOF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define I2S_IN_ERR_EOF_INT_ENA (BIT(10)) +#define I2S_IN_ERR_EOF_INT_ENA_M (BIT(10)) +#define I2S_IN_ERR_EOF_INT_ENA_V 0x1 +#define I2S_IN_ERR_EOF_INT_ENA_S 10 +/* I2S_IN_SUC_EOF_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define I2S_IN_SUC_EOF_INT_ENA (BIT(9)) +#define I2S_IN_SUC_EOF_INT_ENA_M (BIT(9)) +#define I2S_IN_SUC_EOF_INT_ENA_V 0x1 +#define I2S_IN_SUC_EOF_INT_ENA_S 9 +/* I2S_IN_DONE_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define I2S_IN_DONE_INT_ENA (BIT(8)) +#define I2S_IN_DONE_INT_ENA_M (BIT(8)) +#define I2S_IN_DONE_INT_ENA_V 0x1 +#define I2S_IN_DONE_INT_ENA_S 8 +/* I2S_TX_HUNG_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_HUNG_INT_ENA (BIT(7)) +#define I2S_TX_HUNG_INT_ENA_M (BIT(7)) +#define I2S_TX_HUNG_INT_ENA_V 0x1 +#define I2S_TX_HUNG_INT_ENA_S 7 +/* I2S_RX_HUNG_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_HUNG_INT_ENA (BIT(6)) +#define I2S_RX_HUNG_INT_ENA_M (BIT(6)) +#define I2S_RX_HUNG_INT_ENA_V 0x1 +#define I2S_RX_HUNG_INT_ENA_S 6 +/* I2S_TX_REMPTY_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_REMPTY_INT_ENA (BIT(5)) +#define I2S_TX_REMPTY_INT_ENA_M (BIT(5)) +#define I2S_TX_REMPTY_INT_ENA_V 0x1 +#define I2S_TX_REMPTY_INT_ENA_S 5 +/* I2S_TX_WFULL_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_WFULL_INT_ENA (BIT(4)) +#define I2S_TX_WFULL_INT_ENA_M (BIT(4)) +#define I2S_TX_WFULL_INT_ENA_V 0x1 +#define I2S_TX_WFULL_INT_ENA_S 4 +/* I2S_RX_REMPTY_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_REMPTY_INT_ENA (BIT(3)) +#define I2S_RX_REMPTY_INT_ENA_M (BIT(3)) +#define I2S_RX_REMPTY_INT_ENA_V 0x1 +#define I2S_RX_REMPTY_INT_ENA_S 3 +/* I2S_RX_WFULL_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_WFULL_INT_ENA (BIT(2)) +#define I2S_RX_WFULL_INT_ENA_M (BIT(2)) +#define I2S_RX_WFULL_INT_ENA_V 0x1 +#define I2S_RX_WFULL_INT_ENA_S 2 +/* I2S_TX_PUT_DATA_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_PUT_DATA_INT_ENA (BIT(1)) +#define I2S_TX_PUT_DATA_INT_ENA_M (BIT(1)) +#define I2S_TX_PUT_DATA_INT_ENA_V 0x1 +#define I2S_TX_PUT_DATA_INT_ENA_S 1 +/* I2S_RX_TAKE_DATA_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_TAKE_DATA_INT_ENA (BIT(0)) +#define I2S_RX_TAKE_DATA_INT_ENA_M (BIT(0)) +#define I2S_RX_TAKE_DATA_INT_ENA_V 0x1 +#define I2S_RX_TAKE_DATA_INT_ENA_S 0 + +#define I2S_INT_CLR_REG(i) (REG_I2S_BASE(i) + 0x0018) +/* I2S_OUT_TOTAL_EOF_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUT_TOTAL_EOF_INT_CLR (BIT(16)) +#define I2S_OUT_TOTAL_EOF_INT_CLR_M (BIT(16)) +#define I2S_OUT_TOTAL_EOF_INT_CLR_V 0x1 +#define I2S_OUT_TOTAL_EOF_INT_CLR_S 16 +/* I2S_IN_DSCR_EMPTY_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define I2S_IN_DSCR_EMPTY_INT_CLR (BIT(15)) +#define I2S_IN_DSCR_EMPTY_INT_CLR_M (BIT(15)) +#define I2S_IN_DSCR_EMPTY_INT_CLR_V 0x1 +#define I2S_IN_DSCR_EMPTY_INT_CLR_S 15 +/* I2S_OUT_DSCR_ERR_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUT_DSCR_ERR_INT_CLR (BIT(14)) +#define I2S_OUT_DSCR_ERR_INT_CLR_M (BIT(14)) +#define I2S_OUT_DSCR_ERR_INT_CLR_V 0x1 +#define I2S_OUT_DSCR_ERR_INT_CLR_S 14 +/* I2S_IN_DSCR_ERR_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define I2S_IN_DSCR_ERR_INT_CLR (BIT(13)) +#define I2S_IN_DSCR_ERR_INT_CLR_M (BIT(13)) +#define I2S_IN_DSCR_ERR_INT_CLR_V 0x1 +#define I2S_IN_DSCR_ERR_INT_CLR_S 13 +/* I2S_OUT_EOF_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUT_EOF_INT_CLR (BIT(12)) +#define I2S_OUT_EOF_INT_CLR_M (BIT(12)) +#define I2S_OUT_EOF_INT_CLR_V 0x1 +#define I2S_OUT_EOF_INT_CLR_S 12 +/* I2S_OUT_DONE_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUT_DONE_INT_CLR (BIT(11)) +#define I2S_OUT_DONE_INT_CLR_M (BIT(11)) +#define I2S_OUT_DONE_INT_CLR_V 0x1 +#define I2S_OUT_DONE_INT_CLR_S 11 +/* I2S_IN_ERR_EOF_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define I2S_IN_ERR_EOF_INT_CLR (BIT(10)) +#define I2S_IN_ERR_EOF_INT_CLR_M (BIT(10)) +#define I2S_IN_ERR_EOF_INT_CLR_V 0x1 +#define I2S_IN_ERR_EOF_INT_CLR_S 10 +/* I2S_IN_SUC_EOF_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define I2S_IN_SUC_EOF_INT_CLR (BIT(9)) +#define I2S_IN_SUC_EOF_INT_CLR_M (BIT(9)) +#define I2S_IN_SUC_EOF_INT_CLR_V 0x1 +#define I2S_IN_SUC_EOF_INT_CLR_S 9 +/* I2S_IN_DONE_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define I2S_IN_DONE_INT_CLR (BIT(8)) +#define I2S_IN_DONE_INT_CLR_M (BIT(8)) +#define I2S_IN_DONE_INT_CLR_V 0x1 +#define I2S_IN_DONE_INT_CLR_S 8 +/* I2S_TX_HUNG_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_HUNG_INT_CLR (BIT(7)) +#define I2S_TX_HUNG_INT_CLR_M (BIT(7)) +#define I2S_TX_HUNG_INT_CLR_V 0x1 +#define I2S_TX_HUNG_INT_CLR_S 7 +/* I2S_RX_HUNG_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_HUNG_INT_CLR (BIT(6)) +#define I2S_RX_HUNG_INT_CLR_M (BIT(6)) +#define I2S_RX_HUNG_INT_CLR_V 0x1 +#define I2S_RX_HUNG_INT_CLR_S 6 +/* I2S_TX_REMPTY_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_REMPTY_INT_CLR (BIT(5)) +#define I2S_TX_REMPTY_INT_CLR_M (BIT(5)) +#define I2S_TX_REMPTY_INT_CLR_V 0x1 +#define I2S_TX_REMPTY_INT_CLR_S 5 +/* I2S_TX_WFULL_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_WFULL_INT_CLR (BIT(4)) +#define I2S_TX_WFULL_INT_CLR_M (BIT(4)) +#define I2S_TX_WFULL_INT_CLR_V 0x1 +#define I2S_TX_WFULL_INT_CLR_S 4 +/* I2S_RX_REMPTY_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_REMPTY_INT_CLR (BIT(3)) +#define I2S_RX_REMPTY_INT_CLR_M (BIT(3)) +#define I2S_RX_REMPTY_INT_CLR_V 0x1 +#define I2S_RX_REMPTY_INT_CLR_S 3 +/* I2S_RX_WFULL_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_WFULL_INT_CLR (BIT(2)) +#define I2S_RX_WFULL_INT_CLR_M (BIT(2)) +#define I2S_RX_WFULL_INT_CLR_V 0x1 +#define I2S_RX_WFULL_INT_CLR_S 2 +/* I2S_PUT_DATA_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define I2S_PUT_DATA_INT_CLR (BIT(1)) +#define I2S_PUT_DATA_INT_CLR_M (BIT(1)) +#define I2S_PUT_DATA_INT_CLR_V 0x1 +#define I2S_PUT_DATA_INT_CLR_S 1 +/* I2S_TAKE_DATA_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TAKE_DATA_INT_CLR (BIT(0)) +#define I2S_TAKE_DATA_INT_CLR_M (BIT(0)) +#define I2S_TAKE_DATA_INT_CLR_V 0x1 +#define I2S_TAKE_DATA_INT_CLR_S 0 + +#define I2S_TIMING_REG(i) (REG_I2S_BASE(i) + 0x001c) +/* I2S_TX_BCK_IN_INV : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_BCK_IN_INV (BIT(24)) +#define I2S_TX_BCK_IN_INV_M (BIT(24)) +#define I2S_TX_BCK_IN_INV_V 0x1 +#define I2S_TX_BCK_IN_INV_S 24 +/* I2S_DATA_ENABLE_DELAY : R/W ;bitpos:[23:22] ;default: 2'b0 ; */ +/*description: */ +#define I2S_DATA_ENABLE_DELAY 0x00000003 +#define I2S_DATA_ENABLE_DELAY_M ((I2S_DATA_ENABLE_DELAY_V)<<(I2S_DATA_ENABLE_DELAY_S)) +#define I2S_DATA_ENABLE_DELAY_V 0x3 +#define I2S_DATA_ENABLE_DELAY_S 22 +/* I2S_RX_DSYNC_SW : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_DSYNC_SW (BIT(21)) +#define I2S_RX_DSYNC_SW_M (BIT(21)) +#define I2S_RX_DSYNC_SW_V 0x1 +#define I2S_RX_DSYNC_SW_S 21 +/* I2S_TX_DSYNC_SW : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_DSYNC_SW (BIT(20)) +#define I2S_TX_DSYNC_SW_M (BIT(20)) +#define I2S_TX_DSYNC_SW_V 0x1 +#define I2S_TX_DSYNC_SW_S 20 +/* I2S_RX_BCK_OUT_DELAY : R/W ;bitpos:[19:18] ;default: 2'b0 ; */ +/*description: */ +#define I2S_RX_BCK_OUT_DELAY 0x00000003 +#define I2S_RX_BCK_OUT_DELAY_M ((I2S_RX_BCK_OUT_DELAY_V)<<(I2S_RX_BCK_OUT_DELAY_S)) +#define I2S_RX_BCK_OUT_DELAY_V 0x3 +#define I2S_RX_BCK_OUT_DELAY_S 18 +/* I2S_RX_WS_OUT_DELAY : R/W ;bitpos:[17:16] ;default: 2'b0 ; */ +/*description: */ +#define I2S_RX_WS_OUT_DELAY 0x00000003 +#define I2S_RX_WS_OUT_DELAY_M ((I2S_RX_WS_OUT_DELAY_V)<<(I2S_RX_WS_OUT_DELAY_S)) +#define I2S_RX_WS_OUT_DELAY_V 0x3 +#define I2S_RX_WS_OUT_DELAY_S 16 +/* I2S_TX_SD_OUT_DELAY : R/W ;bitpos:[15:14] ;default: 2'b0 ; */ +/*description: */ +#define I2S_TX_SD_OUT_DELAY 0x00000003 +#define I2S_TX_SD_OUT_DELAY_M ((I2S_TX_SD_OUT_DELAY_V)<<(I2S_TX_SD_OUT_DELAY_S)) +#define I2S_TX_SD_OUT_DELAY_V 0x3 +#define I2S_TX_SD_OUT_DELAY_S 14 +/* I2S_TX_WS_OUT_DELAY : R/W ;bitpos:[13:12] ;default: 2'b0 ; */ +/*description: */ +#define I2S_TX_WS_OUT_DELAY 0x00000003 +#define I2S_TX_WS_OUT_DELAY_M ((I2S_TX_WS_OUT_DELAY_V)<<(I2S_TX_WS_OUT_DELAY_S)) +#define I2S_TX_WS_OUT_DELAY_V 0x3 +#define I2S_TX_WS_OUT_DELAY_S 12 +/* I2S_TX_BCK_OUT_DELAY : R/W ;bitpos:[11:10] ;default: 2'b0 ; */ +/*description: */ +#define I2S_TX_BCK_OUT_DELAY 0x00000003 +#define I2S_TX_BCK_OUT_DELAY_M ((I2S_TX_BCK_OUT_DELAY_V)<<(I2S_TX_BCK_OUT_DELAY_S)) +#define I2S_TX_BCK_OUT_DELAY_V 0x3 +#define I2S_TX_BCK_OUT_DELAY_S 10 +/* I2S_RX_SD_IN_DELAY : R/W ;bitpos:[9:8] ;default: 2'b0 ; */ +/*description: */ +#define I2S_RX_SD_IN_DELAY 0x00000003 +#define I2S_RX_SD_IN_DELAY_M ((I2S_RX_SD_IN_DELAY_V)<<(I2S_RX_SD_IN_DELAY_S)) +#define I2S_RX_SD_IN_DELAY_V 0x3 +#define I2S_RX_SD_IN_DELAY_S 8 +/* I2S_RX_WS_IN_DELAY : R/W ;bitpos:[7:6] ;default: 2'b0 ; */ +/*description: */ +#define I2S_RX_WS_IN_DELAY 0x00000003 +#define I2S_RX_WS_IN_DELAY_M ((I2S_RX_WS_IN_DELAY_V)<<(I2S_RX_WS_IN_DELAY_S)) +#define I2S_RX_WS_IN_DELAY_V 0x3 +#define I2S_RX_WS_IN_DELAY_S 6 +/* I2S_RX_BCK_IN_DELAY : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ +/*description: */ +#define I2S_RX_BCK_IN_DELAY 0x00000003 +#define I2S_RX_BCK_IN_DELAY_M ((I2S_RX_BCK_IN_DELAY_V)<<(I2S_RX_BCK_IN_DELAY_S)) +#define I2S_RX_BCK_IN_DELAY_V 0x3 +#define I2S_RX_BCK_IN_DELAY_S 4 +/* I2S_TX_WS_IN_DELAY : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ +/*description: */ +#define I2S_TX_WS_IN_DELAY 0x00000003 +#define I2S_TX_WS_IN_DELAY_M ((I2S_TX_WS_IN_DELAY_V)<<(I2S_TX_WS_IN_DELAY_S)) +#define I2S_TX_WS_IN_DELAY_V 0x3 +#define I2S_TX_WS_IN_DELAY_S 2 +/* I2S_TX_BCK_IN_DELAY : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: */ +#define I2S_TX_BCK_IN_DELAY 0x00000003 +#define I2S_TX_BCK_IN_DELAY_M ((I2S_TX_BCK_IN_DELAY_V)<<(I2S_TX_BCK_IN_DELAY_S)) +#define I2S_TX_BCK_IN_DELAY_V 0x3 +#define I2S_TX_BCK_IN_DELAY_S 0 + +#define I2S_FIFO_CONF_REG(i) (REG_I2S_BASE(i) + 0x0020) +/* I2S_RX_FIFO_MOD_FORCE_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define I2S_RX_FIFO_MOD_FORCE_EN (BIT(20)) +#define I2S_RX_FIFO_MOD_FORCE_EN_M (BIT(20)) +#define I2S_RX_FIFO_MOD_FORCE_EN_V 0x1 +#define I2S_RX_FIFO_MOD_FORCE_EN_S 20 +/* I2S_TX_FIFO_MOD_FORCE_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define I2S_TX_FIFO_MOD_FORCE_EN (BIT(19)) +#define I2S_TX_FIFO_MOD_FORCE_EN_M (BIT(19)) +#define I2S_TX_FIFO_MOD_FORCE_EN_V 0x1 +#define I2S_TX_FIFO_MOD_FORCE_EN_S 19 +/* I2S_RX_FIFO_MOD : R/W ;bitpos:[18:16] ;default: 3'b0 ; */ +/*description: */ +#define I2S_RX_FIFO_MOD 0x00000007 +#define I2S_RX_FIFO_MOD_M ((I2S_RX_FIFO_MOD_V)<<(I2S_RX_FIFO_MOD_S)) +#define I2S_RX_FIFO_MOD_V 0x7 +#define I2S_RX_FIFO_MOD_S 16 +/* I2S_TX_FIFO_MOD : R/W ;bitpos:[15:13] ;default: 3'b0 ; */ +/*description: */ +#define I2S_TX_FIFO_MOD 0x00000007 +#define I2S_TX_FIFO_MOD_M ((I2S_TX_FIFO_MOD_V)<<(I2S_TX_FIFO_MOD_S)) +#define I2S_TX_FIFO_MOD_V 0x7 +#define I2S_TX_FIFO_MOD_S 13 +/* I2S_DSCR_EN : R/W ;bitpos:[12] ;default: 1'd1 ; */ +/*description: */ +#define I2S_DSCR_EN (BIT(12)) +#define I2S_DSCR_EN_M (BIT(12)) +#define I2S_DSCR_EN_V 0x1 +#define I2S_DSCR_EN_S 12 +/* I2S_TX_DATA_NUM : R/W ;bitpos:[11:6] ;default: 6'd32 ; */ +/*description: */ +#define I2S_TX_DATA_NUM 0x0000003F +#define I2S_TX_DATA_NUM_M ((I2S_TX_DATA_NUM_V)<<(I2S_TX_DATA_NUM_S)) +#define I2S_TX_DATA_NUM_V 0x3F +#define I2S_TX_DATA_NUM_S 6 +/* I2S_RX_DATA_NUM : R/W ;bitpos:[5:0] ;default: 6'd32 ; */ +/*description: */ +#define I2S_RX_DATA_NUM 0x0000003F +#define I2S_RX_DATA_NUM_M ((I2S_RX_DATA_NUM_V)<<(I2S_RX_DATA_NUM_S)) +#define I2S_RX_DATA_NUM_V 0x3F +#define I2S_RX_DATA_NUM_S 0 + +#define I2S_RXEOF_NUM_REG(i) (REG_I2S_BASE(i) + 0x0024) +/* I2S_RX_EOF_NUM : R/W ;bitpos:[31:0] ;default: 32'd64 ; */ +/*description: */ +#define I2S_RX_EOF_NUM 0xFFFFFFFF +#define I2S_RX_EOF_NUM_M ((I2S_RX_EOF_NUM_V)<<(I2S_RX_EOF_NUM_S)) +#define I2S_RX_EOF_NUM_V 0xFFFFFFFF +#define I2S_RX_EOF_NUM_S 0 + +#define I2S_CONF_SIGLE_DATA_REG(i) (REG_I2S_BASE(i) + 0x0028) +/* I2S_SIGLE_DATA : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: */ +#define I2S_SIGLE_DATA 0xFFFFFFFF +#define I2S_SIGLE_DATA_M ((I2S_SIGLE_DATA_V)<<(I2S_SIGLE_DATA_S)) +#define I2S_SIGLE_DATA_V 0xFFFFFFFF +#define I2S_SIGLE_DATA_S 0 + +#define I2S_CONF_CHAN_REG(i) (REG_I2S_BASE(i) + 0x002c) +/* I2S_RX_CHAN_MOD : R/W ;bitpos:[4:3] ;default: 2'b0 ; */ +/*description: */ +#define I2S_RX_CHAN_MOD 0x00000003 +#define I2S_RX_CHAN_MOD_M ((I2S_RX_CHAN_MOD_V)<<(I2S_RX_CHAN_MOD_S)) +#define I2S_RX_CHAN_MOD_V 0x3 +#define I2S_RX_CHAN_MOD_S 3 +/* I2S_TX_CHAN_MOD : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: */ +#define I2S_TX_CHAN_MOD 0x00000007 +#define I2S_TX_CHAN_MOD_M ((I2S_TX_CHAN_MOD_V)<<(I2S_TX_CHAN_MOD_S)) +#define I2S_TX_CHAN_MOD_V 0x7 +#define I2S_TX_CHAN_MOD_S 0 + +#define I2S_OUT_LINK_REG(i) (REG_I2S_BASE(i) + 0x0030) +/* I2S_OUTLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define I2S_OUTLINK_PARK (BIT(31)) +#define I2S_OUTLINK_PARK_M (BIT(31)) +#define I2S_OUTLINK_PARK_V 0x1 +#define I2S_OUTLINK_PARK_S 31 +/* I2S_OUTLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUTLINK_RESTART (BIT(30)) +#define I2S_OUTLINK_RESTART_M (BIT(30)) +#define I2S_OUTLINK_RESTART_V 0x1 +#define I2S_OUTLINK_RESTART_S 30 +/* I2S_OUTLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUTLINK_START (BIT(29)) +#define I2S_OUTLINK_START_M (BIT(29)) +#define I2S_OUTLINK_START_V 0x1 +#define I2S_OUTLINK_START_S 29 +/* I2S_OUTLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUTLINK_STOP (BIT(28)) +#define I2S_OUTLINK_STOP_M (BIT(28)) +#define I2S_OUTLINK_STOP_V 0x1 +#define I2S_OUTLINK_STOP_S 28 +/* I2S_OUTLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: */ +#define I2S_OUTLINK_ADDR 0x000FFFFF +#define I2S_OUTLINK_ADDR_M ((I2S_OUTLINK_ADDR_V)<<(I2S_OUTLINK_ADDR_S)) +#define I2S_OUTLINK_ADDR_V 0xFFFFF +#define I2S_OUTLINK_ADDR_S 0 + +#define I2S_IN_LINK_REG(i) (REG_I2S_BASE(i) + 0x0034) +/* I2S_INLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define I2S_INLINK_PARK (BIT(31)) +#define I2S_INLINK_PARK_M (BIT(31)) +#define I2S_INLINK_PARK_V 0x1 +#define I2S_INLINK_PARK_S 31 +/* I2S_INLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define I2S_INLINK_RESTART (BIT(30)) +#define I2S_INLINK_RESTART_M (BIT(30)) +#define I2S_INLINK_RESTART_V 0x1 +#define I2S_INLINK_RESTART_S 30 +/* I2S_INLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define I2S_INLINK_START (BIT(29)) +#define I2S_INLINK_START_M (BIT(29)) +#define I2S_INLINK_START_V 0x1 +#define I2S_INLINK_START_S 29 +/* I2S_INLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define I2S_INLINK_STOP (BIT(28)) +#define I2S_INLINK_STOP_M (BIT(28)) +#define I2S_INLINK_STOP_V 0x1 +#define I2S_INLINK_STOP_S 28 +/* I2S_INLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: */ +#define I2S_INLINK_ADDR 0x000FFFFF +#define I2S_INLINK_ADDR_M ((I2S_INLINK_ADDR_V)<<(I2S_INLINK_ADDR_S)) +#define I2S_INLINK_ADDR_V 0xFFFFF +#define I2S_INLINK_ADDR_S 0 + +#define I2S_OUT_EOF_DES_ADDR_REG(i) (REG_I2S_BASE(i) + 0x0038) +/* I2S_OUT_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define I2S_OUT_EOF_DES_ADDR 0xFFFFFFFF +#define I2S_OUT_EOF_DES_ADDR_M ((I2S_OUT_EOF_DES_ADDR_V)<<(I2S_OUT_EOF_DES_ADDR_S)) +#define I2S_OUT_EOF_DES_ADDR_V 0xFFFFFFFF +#define I2S_OUT_EOF_DES_ADDR_S 0 + +#define I2S_IN_EOF_DES_ADDR_REG(i) (REG_I2S_BASE(i) + 0x003c) +/* I2S_IN_SUC_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define I2S_IN_SUC_EOF_DES_ADDR 0xFFFFFFFF +#define I2S_IN_SUC_EOF_DES_ADDR_M ((I2S_IN_SUC_EOF_DES_ADDR_V)<<(I2S_IN_SUC_EOF_DES_ADDR_S)) +#define I2S_IN_SUC_EOF_DES_ADDR_V 0xFFFFFFFF +#define I2S_IN_SUC_EOF_DES_ADDR_S 0 + +#define I2S_OUT_EOF_BFR_DES_ADDR_REG(i) (REG_I2S_BASE(i) + 0x0040) +/* I2S_OUT_EOF_BFR_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define I2S_OUT_EOF_BFR_DES_ADDR 0xFFFFFFFF +#define I2S_OUT_EOF_BFR_DES_ADDR_M ((I2S_OUT_EOF_BFR_DES_ADDR_V)<<(I2S_OUT_EOF_BFR_DES_ADDR_S)) +#define I2S_OUT_EOF_BFR_DES_ADDR_V 0xFFFFFFFF +#define I2S_OUT_EOF_BFR_DES_ADDR_S 0 + +#define I2S_AHB_TEST_REG(i) (REG_I2S_BASE(i) + 0x0044) +/* I2S_AHB_TESTADDR : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ +/*description: */ +#define I2S_AHB_TESTADDR 0x00000003 +#define I2S_AHB_TESTADDR_M ((I2S_AHB_TESTADDR_V)<<(I2S_AHB_TESTADDR_S)) +#define I2S_AHB_TESTADDR_V 0x3 +#define I2S_AHB_TESTADDR_S 4 +/* I2S_AHB_TESTMODE : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: */ +#define I2S_AHB_TESTMODE 0x00000007 +#define I2S_AHB_TESTMODE_M ((I2S_AHB_TESTMODE_V)<<(I2S_AHB_TESTMODE_S)) +#define I2S_AHB_TESTMODE_V 0x7 +#define I2S_AHB_TESTMODE_S 0 + +#define I2S_INLINK_DSCR_REG(i) (REG_I2S_BASE(i) + 0x0048) +/* I2S_INLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define I2S_INLINK_DSCR 0xFFFFFFFF +#define I2S_INLINK_DSCR_M ((I2S_INLINK_DSCR_V)<<(I2S_INLINK_DSCR_S)) +#define I2S_INLINK_DSCR_V 0xFFFFFFFF +#define I2S_INLINK_DSCR_S 0 + +#define I2S_INLINK_DSCR_BF0_REG(i) (REG_I2S_BASE(i) + 0x004C) +/* I2S_INLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define I2S_INLINK_DSCR_BF0 0xFFFFFFFF +#define I2S_INLINK_DSCR_BF0_M ((I2S_INLINK_DSCR_BF0_V)<<(I2S_INLINK_DSCR_BF0_S)) +#define I2S_INLINK_DSCR_BF0_V 0xFFFFFFFF +#define I2S_INLINK_DSCR_BF0_S 0 + +#define I2S_INLINK_DSCR_BF1_REG(i) (REG_I2S_BASE(i) + 0x0050) +/* I2S_INLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define I2S_INLINK_DSCR_BF1 0xFFFFFFFF +#define I2S_INLINK_DSCR_BF1_M ((I2S_INLINK_DSCR_BF1_V)<<(I2S_INLINK_DSCR_BF1_S)) +#define I2S_INLINK_DSCR_BF1_V 0xFFFFFFFF +#define I2S_INLINK_DSCR_BF1_S 0 + +#define I2S_OUTLINK_DSCR_REG(i) (REG_I2S_BASE(i) + 0x0054) +/* I2S_OUTLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define I2S_OUTLINK_DSCR 0xFFFFFFFF +#define I2S_OUTLINK_DSCR_M ((I2S_OUTLINK_DSCR_V)<<(I2S_OUTLINK_DSCR_S)) +#define I2S_OUTLINK_DSCR_V 0xFFFFFFFF +#define I2S_OUTLINK_DSCR_S 0 + +#define I2S_OUTLINK_DSCR_BF0_REG(i) (REG_I2S_BASE(i) + 0x0058) +/* I2S_OUTLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define I2S_OUTLINK_DSCR_BF0 0xFFFFFFFF +#define I2S_OUTLINK_DSCR_BF0_M ((I2S_OUTLINK_DSCR_BF0_V)<<(I2S_OUTLINK_DSCR_BF0_S)) +#define I2S_OUTLINK_DSCR_BF0_V 0xFFFFFFFF +#define I2S_OUTLINK_DSCR_BF0_S 0 + +#define I2S_OUTLINK_DSCR_BF1_REG(i) (REG_I2S_BASE(i) + 0x005C) +/* I2S_OUTLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define I2S_OUTLINK_DSCR_BF1 0xFFFFFFFF +#define I2S_OUTLINK_DSCR_BF1_M ((I2S_OUTLINK_DSCR_BF1_V)<<(I2S_OUTLINK_DSCR_BF1_S)) +#define I2S_OUTLINK_DSCR_BF1_V 0xFFFFFFFF +#define I2S_OUTLINK_DSCR_BF1_S 0 + +#define I2S_LC_CONF_REG(i) (REG_I2S_BASE(i) + 0x0060) +/* I2S_MEM_TRANS_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define I2S_MEM_TRANS_EN (BIT(13)) +#define I2S_MEM_TRANS_EN_M (BIT(13)) +#define I2S_MEM_TRANS_EN_V 0x1 +#define I2S_MEM_TRANS_EN_S 13 +/* I2S_CHECK_OWNER : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define I2S_CHECK_OWNER (BIT(12)) +#define I2S_CHECK_OWNER_M (BIT(12)) +#define I2S_CHECK_OWNER_V 0x1 +#define I2S_CHECK_OWNER_S 12 +/* I2S_OUT_DATA_BURST_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUT_DATA_BURST_EN (BIT(11)) +#define I2S_OUT_DATA_BURST_EN_M (BIT(11)) +#define I2S_OUT_DATA_BURST_EN_V 0x1 +#define I2S_OUT_DATA_BURST_EN_S 11 +/* I2S_INDSCR_BURST_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define I2S_INDSCR_BURST_EN (BIT(10)) +#define I2S_INDSCR_BURST_EN_M (BIT(10)) +#define I2S_INDSCR_BURST_EN_V 0x1 +#define I2S_INDSCR_BURST_EN_S 10 +/* I2S_OUTDSCR_BURST_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUTDSCR_BURST_EN (BIT(9)) +#define I2S_OUTDSCR_BURST_EN_M (BIT(9)) +#define I2S_OUTDSCR_BURST_EN_V 0x1 +#define I2S_OUTDSCR_BURST_EN_S 9 +/* I2S_OUT_EOF_MODE : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: */ +#define I2S_OUT_EOF_MODE (BIT(8)) +#define I2S_OUT_EOF_MODE_M (BIT(8)) +#define I2S_OUT_EOF_MODE_V 0x1 +#define I2S_OUT_EOF_MODE_S 8 +/* I2S_OUT_NO_RESTART_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUT_NO_RESTART_CLR (BIT(7)) +#define I2S_OUT_NO_RESTART_CLR_M (BIT(7)) +#define I2S_OUT_NO_RESTART_CLR_V 0x1 +#define I2S_OUT_NO_RESTART_CLR_S 7 +/* I2S_OUT_AUTO_WRBACK : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUT_AUTO_WRBACK (BIT(6)) +#define I2S_OUT_AUTO_WRBACK_M (BIT(6)) +#define I2S_OUT_AUTO_WRBACK_V 0x1 +#define I2S_OUT_AUTO_WRBACK_S 6 +/* I2S_IN_LOOP_TEST : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define I2S_IN_LOOP_TEST (BIT(5)) +#define I2S_IN_LOOP_TEST_M (BIT(5)) +#define I2S_IN_LOOP_TEST_V 0x1 +#define I2S_IN_LOOP_TEST_S 5 +/* I2S_OUT_LOOP_TEST : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUT_LOOP_TEST (BIT(4)) +#define I2S_OUT_LOOP_TEST_M (BIT(4)) +#define I2S_OUT_LOOP_TEST_V 0x1 +#define I2S_OUT_LOOP_TEST_S 4 +/* I2S_AHBM_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define I2S_AHBM_RST (BIT(3)) +#define I2S_AHBM_RST_M (BIT(3)) +#define I2S_AHBM_RST_V 0x1 +#define I2S_AHBM_RST_S 3 +/* I2S_AHBM_FIFO_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define I2S_AHBM_FIFO_RST (BIT(2)) +#define I2S_AHBM_FIFO_RST_M (BIT(2)) +#define I2S_AHBM_FIFO_RST_V 0x1 +#define I2S_AHBM_FIFO_RST_S 2 +/* I2S_OUT_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define I2S_OUT_RST (BIT(1)) +#define I2S_OUT_RST_M (BIT(1)) +#define I2S_OUT_RST_V 0x1 +#define I2S_OUT_RST_S 1 +/* I2S_IN_RST : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define I2S_IN_RST (BIT(0)) +#define I2S_IN_RST_M (BIT(0)) +#define I2S_IN_RST_V 0x1 +#define I2S_IN_RST_S 0 + +#define I2S_OUTFIFO_PUSH_REG(i) (REG_I2S_BASE(i) + 0x0064) +/* I2S_OUTFIFO_PUSH : R/W ;bitpos:[16] ;default: 1'h0 ; */ +/*description: */ +#define I2S_OUTFIFO_PUSH (BIT(16)) +#define I2S_OUTFIFO_PUSH_M (BIT(16)) +#define I2S_OUTFIFO_PUSH_V 0x1 +#define I2S_OUTFIFO_PUSH_S 16 +/* I2S_OUTFIFO_WDATA : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ +/*description: */ +#define I2S_OUTFIFO_WDATA 0x000001FF +#define I2S_OUTFIFO_WDATA_M ((I2S_OUTFIFO_WDATA_V)<<(I2S_OUTFIFO_WDATA_S)) +#define I2S_OUTFIFO_WDATA_V 0x1FF +#define I2S_OUTFIFO_WDATA_S 0 + +#define I2S_INFIFO_POP_REG(i) (REG_I2S_BASE(i) + 0x0068) +/* I2S_INFIFO_POP : R/W ;bitpos:[16] ;default: 1'h0 ; */ +/*description: */ +#define I2S_INFIFO_POP (BIT(16)) +#define I2S_INFIFO_POP_M (BIT(16)) +#define I2S_INFIFO_POP_V 0x1 +#define I2S_INFIFO_POP_S 16 +/* I2S_INFIFO_RDATA : RO ;bitpos:[11:0] ;default: 12'h0 ; */ +/*description: */ +#define I2S_INFIFO_RDATA 0x00000FFF +#define I2S_INFIFO_RDATA_M ((I2S_INFIFO_RDATA_V)<<(I2S_INFIFO_RDATA_S)) +#define I2S_INFIFO_RDATA_V 0xFFF +#define I2S_INFIFO_RDATA_S 0 + +#define I2S_LC_STATE0_REG(i) (REG_I2S_BASE(i) + 0x006C) +/* I2S_LC_STATE0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define I2S_LC_STATE0 0xFFFFFFFF +#define I2S_LC_STATE0_M ((I2S_LC_STATE0_V)<<(I2S_LC_STATE0_S)) +#define I2S_LC_STATE0_V 0xFFFFFFFF +#define I2S_LC_STATE0_S 0 + +#define I2S_LC_STATE1_REG(i) (REG_I2S_BASE(i) + 0x0070) +/* I2S_LC_STATE1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define I2S_LC_STATE1 0xFFFFFFFF +#define I2S_LC_STATE1_M ((I2S_LC_STATE1_V)<<(I2S_LC_STATE1_S)) +#define I2S_LC_STATE1_V 0xFFFFFFFF +#define I2S_LC_STATE1_S 0 + +#define I2S_LC_HUNG_CONF_REG(i) (REG_I2S_BASE(i) + 0x0074) +/* I2S_LC_FIFO_TIMEOUT_ENA : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: */ +#define I2S_LC_FIFO_TIMEOUT_ENA (BIT(11)) +#define I2S_LC_FIFO_TIMEOUT_ENA_M (BIT(11)) +#define I2S_LC_FIFO_TIMEOUT_ENA_V 0x1 +#define I2S_LC_FIFO_TIMEOUT_ENA_S 11 +/* I2S_LC_FIFO_TIMEOUT_SHIFT : R/W ;bitpos:[10:8] ;default: 3'b0 ; */ +/*description: */ +#define I2S_LC_FIFO_TIMEOUT_SHIFT 0x00000007 +#define I2S_LC_FIFO_TIMEOUT_SHIFT_M ((I2S_LC_FIFO_TIMEOUT_SHIFT_V)<<(I2S_LC_FIFO_TIMEOUT_SHIFT_S)) +#define I2S_LC_FIFO_TIMEOUT_SHIFT_V 0x7 +#define I2S_LC_FIFO_TIMEOUT_SHIFT_S 8 +/* I2S_LC_FIFO_TIMEOUT : R/W ;bitpos:[7:0] ;default: 8'h10 ; */ +/*description: */ +#define I2S_LC_FIFO_TIMEOUT 0x000000FF +#define I2S_LC_FIFO_TIMEOUT_M ((I2S_LC_FIFO_TIMEOUT_V)<<(I2S_LC_FIFO_TIMEOUT_S)) +#define I2S_LC_FIFO_TIMEOUT_V 0xFF +#define I2S_LC_FIFO_TIMEOUT_S 0 + +#define I2S_CVSD_CONF0_REG(i) (REG_I2S_BASE(i) + 0x0080) +/* I2S_CVSD_Y_MIN : R/W ;bitpos:[31:16] ;default: 16'h8000 ; */ +/*description: */ +#define I2S_CVSD_Y_MIN 0x0000FFFF +#define I2S_CVSD_Y_MIN_M ((I2S_CVSD_Y_MIN_V)<<(I2S_CVSD_Y_MIN_S)) +#define I2S_CVSD_Y_MIN_V 0xFFFF +#define I2S_CVSD_Y_MIN_S 16 +/* I2S_CVSD_Y_MAX : R/W ;bitpos:[15:0] ;default: 16'h7fff ; */ +/*description: */ +#define I2S_CVSD_Y_MAX 0x0000FFFF +#define I2S_CVSD_Y_MAX_M ((I2S_CVSD_Y_MAX_V)<<(I2S_CVSD_Y_MAX_S)) +#define I2S_CVSD_Y_MAX_V 0xFFFF +#define I2S_CVSD_Y_MAX_S 0 + +#define I2S_CVSD_CONF1_REG(i) (REG_I2S_BASE(i) + 0x0084) +/* I2S_CVSD_SIGMA_MIN : R/W ;bitpos:[31:16] ;default: 16'd10 ; */ +/*description: */ +#define I2S_CVSD_SIGMA_MIN 0x0000FFFF +#define I2S_CVSD_SIGMA_MIN_M ((I2S_CVSD_SIGMA_MIN_V)<<(I2S_CVSD_SIGMA_MIN_S)) +#define I2S_CVSD_SIGMA_MIN_V 0xFFFF +#define I2S_CVSD_SIGMA_MIN_S 16 +/* I2S_CVSD_SIGMA_MAX : R/W ;bitpos:[15:0] ;default: 16'd1280 ; */ +/*description: */ +#define I2S_CVSD_SIGMA_MAX 0x0000FFFF +#define I2S_CVSD_SIGMA_MAX_M ((I2S_CVSD_SIGMA_MAX_V)<<(I2S_CVSD_SIGMA_MAX_S)) +#define I2S_CVSD_SIGMA_MAX_V 0xFFFF +#define I2S_CVSD_SIGMA_MAX_S 0 + +#define I2S_CVSD_CONF2_REG(i) (REG_I2S_BASE(i) + 0x0088) +/* I2S_CVSD_H : R/W ;bitpos:[18:16] ;default: 3'd5 ; */ +/*description: */ +#define I2S_CVSD_H 0x00000007 +#define I2S_CVSD_H_M ((I2S_CVSD_H_V)<<(I2S_CVSD_H_S)) +#define I2S_CVSD_H_V 0x7 +#define I2S_CVSD_H_S 16 +/* I2S_CVSD_BETA : R/W ;bitpos:[15:6] ;default: 10'd10 ; */ +/*description: */ +#define I2S_CVSD_BETA 0x000003FF +#define I2S_CVSD_BETA_M ((I2S_CVSD_BETA_V)<<(I2S_CVSD_BETA_S)) +#define I2S_CVSD_BETA_V 0x3FF +#define I2S_CVSD_BETA_S 6 +/* I2S_CVSD_J : R/W ;bitpos:[5:3] ;default: 3'h4 ; */ +/*description: */ +#define I2S_CVSD_J 0x00000007 +#define I2S_CVSD_J_M ((I2S_CVSD_J_V)<<(I2S_CVSD_J_S)) +#define I2S_CVSD_J_V 0x7 +#define I2S_CVSD_J_S 3 +/* I2S_CVSD_K : R/W ;bitpos:[2:0] ;default: 3'h4 ; */ +/*description: */ +#define I2S_CVSD_K 0x00000007 +#define I2S_CVSD_K_M ((I2S_CVSD_K_V)<<(I2S_CVSD_K_S)) +#define I2S_CVSD_K_V 0x7 +#define I2S_CVSD_K_S 0 + +#define I2S_PLC_CONF0_REG(i) (REG_I2S_BASE(i) + 0x008C) +/* I2S_N_MIN_ERR : R/W ;bitpos:[27:25] ;default: 3'd4 ; */ +/*description: */ +#define I2S_N_MIN_ERR 0x00000007 +#define I2S_N_MIN_ERR_M ((I2S_N_MIN_ERR_V)<<(I2S_N_MIN_ERR_S)) +#define I2S_N_MIN_ERR_V 0x7 +#define I2S_N_MIN_ERR_S 25 +/* I2S_PACK_LEN_8K : R/W ;bitpos:[24:20] ;default: 5'd10 ; */ +/*description: */ +#define I2S_PACK_LEN_8K 0x0000001F +#define I2S_PACK_LEN_8K_M ((I2S_PACK_LEN_8K_V)<<(I2S_PACK_LEN_8K_S)) +#define I2S_PACK_LEN_8K_V 0x1F +#define I2S_PACK_LEN_8K_S 20 +/* I2S_MAX_SLIDE_SAMPLE : R/W ;bitpos:[19:12] ;default: 8'd128 ; */ +/*description: */ +#define I2S_MAX_SLIDE_SAMPLE 0x000000FF +#define I2S_MAX_SLIDE_SAMPLE_M ((I2S_MAX_SLIDE_SAMPLE_V)<<(I2S_MAX_SLIDE_SAMPLE_S)) +#define I2S_MAX_SLIDE_SAMPLE_V 0xFF +#define I2S_MAX_SLIDE_SAMPLE_S 12 +/* I2S_SHIFT_RATE : R/W ;bitpos:[11:9] ;default: 3'h1 ; */ +/*description: */ +#define I2S_SHIFT_RATE 0x00000007 +#define I2S_SHIFT_RATE_M ((I2S_SHIFT_RATE_V)<<(I2S_SHIFT_RATE_S)) +#define I2S_SHIFT_RATE_V 0x7 +#define I2S_SHIFT_RATE_S 9 +/* I2S_N_ERR_SEG : R/W ;bitpos:[8:6] ;default: 3'h4 ; */ +/*description: */ +#define I2S_N_ERR_SEG 0x00000007 +#define I2S_N_ERR_SEG_M ((I2S_N_ERR_SEG_V)<<(I2S_N_ERR_SEG_S)) +#define I2S_N_ERR_SEG_V 0x7 +#define I2S_N_ERR_SEG_S 6 +/* I2S_GOOD_PACK_MAX : R/W ;bitpos:[5:0] ;default: 6'h39 ; */ +/*description: */ +#define I2S_GOOD_PACK_MAX 0x0000003F +#define I2S_GOOD_PACK_MAX_M ((I2S_GOOD_PACK_MAX_V)<<(I2S_GOOD_PACK_MAX_S)) +#define I2S_GOOD_PACK_MAX_V 0x3F +#define I2S_GOOD_PACK_MAX_S 0 + +#define I2S_PLC_CONF1_REG(i) (REG_I2S_BASE(i) + 0x0090) +/* I2S_SLIDE_WIN_LEN : R/W ;bitpos:[31:24] ;default: 8'd160 ; */ +/*description: */ +#define I2S_SLIDE_WIN_LEN 0x000000FF +#define I2S_SLIDE_WIN_LEN_M ((I2S_SLIDE_WIN_LEN_V)<<(I2S_SLIDE_WIN_LEN_S)) +#define I2S_SLIDE_WIN_LEN_V 0xFF +#define I2S_SLIDE_WIN_LEN_S 24 +/* I2S_BAD_OLA_WIN2_PARA : R/W ;bitpos:[23:16] ;default: 8'd23 ; */ +/*description: */ +#define I2S_BAD_OLA_WIN2_PARA 0x000000FF +#define I2S_BAD_OLA_WIN2_PARA_M ((I2S_BAD_OLA_WIN2_PARA_V)<<(I2S_BAD_OLA_WIN2_PARA_S)) +#define I2S_BAD_OLA_WIN2_PARA_V 0xFF +#define I2S_BAD_OLA_WIN2_PARA_S 16 +/* I2S_BAD_OLA_WIN2_PARA_SHIFT : R/W ;bitpos:[15:12] ;default: 4'd8 ; */ +/*description: */ +#define I2S_BAD_OLA_WIN2_PARA_SHIFT 0x0000000F +#define I2S_BAD_OLA_WIN2_PARA_SHIFT_M ((I2S_BAD_OLA_WIN2_PARA_SHIFT_V)<<(I2S_BAD_OLA_WIN2_PARA_SHIFT_S)) +#define I2S_BAD_OLA_WIN2_PARA_SHIFT_V 0xF +#define I2S_BAD_OLA_WIN2_PARA_SHIFT_S 12 +/* I2S_BAD_CEF_ATTEN_PARA_SHIFT : R/W ;bitpos:[11:8] ;default: 4'd10 ; */ +/*description: */ +#define I2S_BAD_CEF_ATTEN_PARA_SHIFT 0x0000000F +#define I2S_BAD_CEF_ATTEN_PARA_SHIFT_M ((I2S_BAD_CEF_ATTEN_PARA_SHIFT_V)<<(I2S_BAD_CEF_ATTEN_PARA_SHIFT_S)) +#define I2S_BAD_CEF_ATTEN_PARA_SHIFT_V 0xF +#define I2S_BAD_CEF_ATTEN_PARA_SHIFT_S 8 +/* I2S_BAD_CEF_ATTEN_PARA : R/W ;bitpos:[7:0] ;default: 8'd5 ; */ +/*description: */ +#define I2S_BAD_CEF_ATTEN_PARA 0x000000FF +#define I2S_BAD_CEF_ATTEN_PARA_M ((I2S_BAD_CEF_ATTEN_PARA_V)<<(I2S_BAD_CEF_ATTEN_PARA_S)) +#define I2S_BAD_CEF_ATTEN_PARA_V 0xFF +#define I2S_BAD_CEF_ATTEN_PARA_S 0 + +#define I2S_PLC_CONF2_REG(i) (REG_I2S_BASE(i) + 0x0094) +/* I2S_MIN_PERIOD : R/W ;bitpos:[6:2] ;default: 5'd10 ; */ +/*description: */ +#define I2S_MIN_PERIOD 0x0000001F +#define I2S_MIN_PERIOD_M ((I2S_MIN_PERIOD_V)<<(I2S_MIN_PERIOD_S)) +#define I2S_MIN_PERIOD_V 0x1F +#define I2S_MIN_PERIOD_S 2 +/* I2S_CVSD_SEG_MOD : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: */ +#define I2S_CVSD_SEG_MOD 0x00000003 +#define I2S_CVSD_SEG_MOD_M ((I2S_CVSD_SEG_MOD_V)<<(I2S_CVSD_SEG_MOD_S)) +#define I2S_CVSD_SEG_MOD_V 0x3 +#define I2S_CVSD_SEG_MOD_S 0 + +#define I2S_ESCO_CONF0_REG(i) (REG_I2S_BASE(i) + 0x0098) +/* I2S_PLC2DMA_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define I2S_PLC2DMA_EN (BIT(12)) +#define I2S_PLC2DMA_EN_M (BIT(12)) +#define I2S_PLC2DMA_EN_V 0x1 +#define I2S_PLC2DMA_EN_S 12 +/* I2S_PLC_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define I2S_PLC_EN (BIT(11)) +#define I2S_PLC_EN_M (BIT(11)) +#define I2S_PLC_EN_V 0x1 +#define I2S_PLC_EN_S 11 +/* I2S_CVSD_DEC_RESET : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define I2S_CVSD_DEC_RESET (BIT(10)) +#define I2S_CVSD_DEC_RESET_M (BIT(10)) +#define I2S_CVSD_DEC_RESET_V 0x1 +#define I2S_CVSD_DEC_RESET_S 10 +/* I2S_CVSD_DEC_START : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define I2S_CVSD_DEC_START (BIT(9)) +#define I2S_CVSD_DEC_START_M (BIT(9)) +#define I2S_CVSD_DEC_START_V 0x1 +#define I2S_CVSD_DEC_START_S 9 +/* I2S_ESCO_CVSD_INF_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define I2S_ESCO_CVSD_INF_EN (BIT(8)) +#define I2S_ESCO_CVSD_INF_EN_M (BIT(8)) +#define I2S_ESCO_CVSD_INF_EN_V 0x1 +#define I2S_ESCO_CVSD_INF_EN_S 8 +/* I2S_ESCO_CVSD_PACK_LEN_8K : R/W ;bitpos:[7:3] ;default: 5'b0 ; */ +/*description: */ +#define I2S_ESCO_CVSD_PACK_LEN_8K 0x0000001F +#define I2S_ESCO_CVSD_PACK_LEN_8K_M ((I2S_ESCO_CVSD_PACK_LEN_8K_V)<<(I2S_ESCO_CVSD_PACK_LEN_8K_S)) +#define I2S_ESCO_CVSD_PACK_LEN_8K_V 0x1F +#define I2S_ESCO_CVSD_PACK_LEN_8K_S 3 +/* I2S_ESCO_CVSD_DEC_PACK_ERR : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define I2S_ESCO_CVSD_DEC_PACK_ERR (BIT(2)) +#define I2S_ESCO_CVSD_DEC_PACK_ERR_M (BIT(2)) +#define I2S_ESCO_CVSD_DEC_PACK_ERR_V 0x1 +#define I2S_ESCO_CVSD_DEC_PACK_ERR_S 2 +/* I2S_ESCO_CHAN_MOD : R/W ;bitpos:[1] ;default: 1'd0 ; */ +/*description: */ +#define I2S_ESCO_CHAN_MOD (BIT(1)) +#define I2S_ESCO_CHAN_MOD_M (BIT(1)) +#define I2S_ESCO_CHAN_MOD_V 0x1 +#define I2S_ESCO_CHAN_MOD_S 1 +/* I2S_ESCO_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define I2S_ESCO_EN (BIT(0)) +#define I2S_ESCO_EN_M (BIT(0)) +#define I2S_ESCO_EN_V 0x1 +#define I2S_ESCO_EN_S 0 + +#define I2S_SCO_CONF0_REG(i) (REG_I2S_BASE(i) + 0x009c) +/* I2S_CVSD_ENC_RESET : R/W ;bitpos:[3] ;default: 1'd0 ; */ +/*description: */ +#define I2S_CVSD_ENC_RESET (BIT(3)) +#define I2S_CVSD_ENC_RESET_M (BIT(3)) +#define I2S_CVSD_ENC_RESET_V 0x1 +#define I2S_CVSD_ENC_RESET_S 3 +/* I2S_CVSD_ENC_START : R/W ;bitpos:[2] ;default: 1'd0 ; */ +/*description: */ +#define I2S_CVSD_ENC_START (BIT(2)) +#define I2S_CVSD_ENC_START_M (BIT(2)) +#define I2S_CVSD_ENC_START_V 0x1 +#define I2S_CVSD_ENC_START_S 2 +/* I2S_SCO_NO_I2S_EN : R/W ;bitpos:[1] ;default: 1'd0 ; */ +/*description: */ +#define I2S_SCO_NO_I2S_EN (BIT(1)) +#define I2S_SCO_NO_I2S_EN_M (BIT(1)) +#define I2S_SCO_NO_I2S_EN_V 0x1 +#define I2S_SCO_NO_I2S_EN_S 1 +/* I2S_SCO_WITH_I2S_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define I2S_SCO_WITH_I2S_EN (BIT(0)) +#define I2S_SCO_WITH_I2S_EN_M (BIT(0)) +#define I2S_SCO_WITH_I2S_EN_V 0x1 +#define I2S_SCO_WITH_I2S_EN_S 0 + +#define I2S_CONF1_REG(i) (REG_I2S_BASE(i) + 0x00a0) +/* I2S_TX_ZEROS_RM_EN : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: */ +#define I2S_TX_ZEROS_RM_EN (BIT(9)) +#define I2S_TX_ZEROS_RM_EN_M (BIT(9)) +#define I2S_TX_ZEROS_RM_EN_V 0x1 +#define I2S_TX_ZEROS_RM_EN_S 9 +/* I2S_TX_STOP_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: */ +#define I2S_TX_STOP_EN (BIT(8)) +#define I2S_TX_STOP_EN_M (BIT(8)) +#define I2S_TX_STOP_EN_V 0x1 +#define I2S_TX_STOP_EN_S 8 +/* I2S_RX_PCM_BYPASS : R/W ;bitpos:[7] ;default: 1'h1 ; */ +/*description: */ +#define I2S_RX_PCM_BYPASS (BIT(7)) +#define I2S_RX_PCM_BYPASS_M (BIT(7)) +#define I2S_RX_PCM_BYPASS_V 0x1 +#define I2S_RX_PCM_BYPASS_S 7 +/* I2S_RX_PCM_CONF : R/W ;bitpos:[6:4] ;default: 3'h0 ; */ +/*description: */ +#define I2S_RX_PCM_CONF 0x00000007 +#define I2S_RX_PCM_CONF_M ((I2S_RX_PCM_CONF_V)<<(I2S_RX_PCM_CONF_S)) +#define I2S_RX_PCM_CONF_V 0x7 +#define I2S_RX_PCM_CONF_S 4 +/* I2S_TX_PCM_BYPASS : R/W ;bitpos:[3] ;default: 1'h1 ; */ +/*description: */ +#define I2S_TX_PCM_BYPASS (BIT(3)) +#define I2S_TX_PCM_BYPASS_M (BIT(3)) +#define I2S_TX_PCM_BYPASS_V 0x1 +#define I2S_TX_PCM_BYPASS_S 3 +/* I2S_TX_PCM_CONF : R/W ;bitpos:[2:0] ;default: 3'h1 ; */ +/*description: */ +#define I2S_TX_PCM_CONF 0x00000007 +#define I2S_TX_PCM_CONF_M ((I2S_TX_PCM_CONF_V)<<(I2S_TX_PCM_CONF_S)) +#define I2S_TX_PCM_CONF_V 0x7 +#define I2S_TX_PCM_CONF_S 0 + +#define I2S_PD_CONF_REG(i) (REG_I2S_BASE(i) + 0x00a4) +/* I2S_PLC_MEM_FORCE_PU : R/W ;bitpos:[3] ;default: 1'h1 ; */ +/*description: */ +#define I2S_PLC_MEM_FORCE_PU (BIT(3)) +#define I2S_PLC_MEM_FORCE_PU_M (BIT(3)) +#define I2S_PLC_MEM_FORCE_PU_V 0x1 +#define I2S_PLC_MEM_FORCE_PU_S 3 +/* I2S_PLC_MEM_FORCE_PD : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define I2S_PLC_MEM_FORCE_PD (BIT(2)) +#define I2S_PLC_MEM_FORCE_PD_M (BIT(2)) +#define I2S_PLC_MEM_FORCE_PD_V 0x1 +#define I2S_PLC_MEM_FORCE_PD_S 2 +/* I2S_FIFO_FORCE_PU : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/*description: */ +#define I2S_FIFO_FORCE_PU (BIT(1)) +#define I2S_FIFO_FORCE_PU_M (BIT(1)) +#define I2S_FIFO_FORCE_PU_V 0x1 +#define I2S_FIFO_FORCE_PU_S 1 +/* I2S_FIFO_FORCE_PD : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define I2S_FIFO_FORCE_PD (BIT(0)) +#define I2S_FIFO_FORCE_PD_M (BIT(0)) +#define I2S_FIFO_FORCE_PD_V 0x1 +#define I2S_FIFO_FORCE_PD_S 0 + +#define I2S_CONF2_REG(i) (REG_I2S_BASE(i) + 0x00a8) +/* I2S_INTER_VALID_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define I2S_INTER_VALID_EN (BIT(7)) +#define I2S_INTER_VALID_EN_M (BIT(7)) +#define I2S_INTER_VALID_EN_V 0x1 +#define I2S_INTER_VALID_EN_S 7 +/* I2S_EXT_ADC_START_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define I2S_EXT_ADC_START_EN (BIT(6)) +#define I2S_EXT_ADC_START_EN_M (BIT(6)) +#define I2S_EXT_ADC_START_EN_V 0x1 +#define I2S_EXT_ADC_START_EN_S 6 +/* I2S_LCD_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define I2S_LCD_EN (BIT(5)) +#define I2S_LCD_EN_M (BIT(5)) +#define I2S_LCD_EN_V 0x1 +#define I2S_LCD_EN_S 5 +/* I2S_DATA_ENABLE : R/W ;bitpos:[4] ;default: 1'h0 ; */ +/*description: */ +#define I2S_DATA_ENABLE (BIT(4)) +#define I2S_DATA_ENABLE_M (BIT(4)) +#define I2S_DATA_ENABLE_V 0x1 +#define I2S_DATA_ENABLE_S 4 +/* I2S_DATA_ENABLE_TEST_EN : R/W ;bitpos:[3] ;default: 1'h0 ; */ +/*description: */ +#define I2S_DATA_ENABLE_TEST_EN (BIT(3)) +#define I2S_DATA_ENABLE_TEST_EN_M (BIT(3)) +#define I2S_DATA_ENABLE_TEST_EN_V 0x1 +#define I2S_DATA_ENABLE_TEST_EN_S 3 +/* I2S_LCD_TX_SDX2_EN : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define I2S_LCD_TX_SDX2_EN (BIT(2)) +#define I2S_LCD_TX_SDX2_EN_M (BIT(2)) +#define I2S_LCD_TX_SDX2_EN_V 0x1 +#define I2S_LCD_TX_SDX2_EN_S 2 +/* I2S_LCD_TX_WRX2_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: */ +#define I2S_LCD_TX_WRX2_EN (BIT(1)) +#define I2S_LCD_TX_WRX2_EN_M (BIT(1)) +#define I2S_LCD_TX_WRX2_EN_V 0x1 +#define I2S_LCD_TX_WRX2_EN_S 1 +/* I2S_CAMERA_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define I2S_CAMERA_EN (BIT(0)) +#define I2S_CAMERA_EN_M (BIT(0)) +#define I2S_CAMERA_EN_V 0x1 +#define I2S_CAMERA_EN_S 0 + +#define I2S_CLKM_CONF_REG(i) (REG_I2S_BASE(i) + 0x00ac) +/* I2S_CLKA_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define I2S_CLKA_ENA (BIT(21)) +#define I2S_CLKA_ENA_M (BIT(21)) +#define I2S_CLKA_ENA_V 0x1 +#define I2S_CLKA_ENA_S 21 +/* I2S_CLK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define I2S_CLK_EN (BIT(20)) +#define I2S_CLK_EN_M (BIT(20)) +#define I2S_CLK_EN_V 0x1 +#define I2S_CLK_EN_S 20 +/* I2S_CLKM_DIV_A : R/W ;bitpos:[19:14] ;default: 6'h0 ; */ +/*description: */ +#define I2S_CLKM_DIV_A 0x0000003F +#define I2S_CLKM_DIV_A_M ((I2S_CLKM_DIV_A_V)<<(I2S_CLKM_DIV_A_S)) +#define I2S_CLKM_DIV_A_V 0x3F +#define I2S_CLKM_DIV_A_S 14 +/* I2S_CLKM_DIV_B : R/W ;bitpos:[13:8] ;default: 6'h0 ; */ +/*description: */ +#define I2S_CLKM_DIV_B 0x0000003F +#define I2S_CLKM_DIV_B_M ((I2S_CLKM_DIV_B_V)<<(I2S_CLKM_DIV_B_S)) +#define I2S_CLKM_DIV_B_V 0x3F +#define I2S_CLKM_DIV_B_S 8 +/* I2S_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd4 ; */ +/*description: */ +#define I2S_CLKM_DIV_NUM 0x000000FF +#define I2S_CLKM_DIV_NUM_M ((I2S_CLKM_DIV_NUM_V)<<(I2S_CLKM_DIV_NUM_S)) +#define I2S_CLKM_DIV_NUM_V 0xFF +#define I2S_CLKM_DIV_NUM_S 0 + +#define I2S_SAMPLE_RATE_CONF_REG(i) (REG_I2S_BASE(i) + 0x00b0) +/* I2S_RX_BITS_MOD : R/W ;bitpos:[23:18] ;default: 6'd16 ; */ +/*description: */ +#define I2S_RX_BITS_MOD 0x0000003F +#define I2S_RX_BITS_MOD_M ((I2S_RX_BITS_MOD_V)<<(I2S_RX_BITS_MOD_S)) +#define I2S_RX_BITS_MOD_V 0x3F +#define I2S_RX_BITS_MOD_S 18 +/* I2S_TX_BITS_MOD : R/W ;bitpos:[17:12] ;default: 6'd16 ; */ +/*description: */ +#define I2S_TX_BITS_MOD 0x0000003F +#define I2S_TX_BITS_MOD_M ((I2S_TX_BITS_MOD_V)<<(I2S_TX_BITS_MOD_S)) +#define I2S_TX_BITS_MOD_V 0x3F +#define I2S_TX_BITS_MOD_S 12 +/* I2S_RX_BCK_DIV_NUM : R/W ;bitpos:[11:6] ;default: 6'd6 ; */ +/*description: */ +#define I2S_RX_BCK_DIV_NUM 0x0000003F +#define I2S_RX_BCK_DIV_NUM_M ((I2S_RX_BCK_DIV_NUM_V)<<(I2S_RX_BCK_DIV_NUM_S)) +#define I2S_RX_BCK_DIV_NUM_V 0x3F +#define I2S_RX_BCK_DIV_NUM_S 6 +/* I2S_TX_BCK_DIV_NUM : R/W ;bitpos:[5:0] ;default: 6'd6 ; */ +/*description: */ +#define I2S_TX_BCK_DIV_NUM 0x0000003F +#define I2S_TX_BCK_DIV_NUM_M ((I2S_TX_BCK_DIV_NUM_V)<<(I2S_TX_BCK_DIV_NUM_S)) +#define I2S_TX_BCK_DIV_NUM_V 0x3F +#define I2S_TX_BCK_DIV_NUM_S 0 + +#define I2S_PDM_CONF_REG(i) (REG_I2S_BASE(i) + 0x00b4) +/* I2S_TX_PDM_HP_BYPASS : R/W ;bitpos:[25] ;default: 1'h0 ; */ +/*description: */ +#define I2S_TX_PDM_HP_BYPASS (BIT(25)) +#define I2S_TX_PDM_HP_BYPASS_M (BIT(25)) +#define I2S_TX_PDM_HP_BYPASS_V 0x1 +#define I2S_TX_PDM_HP_BYPASS_S 25 +/* I2S_RX_PDM_SINC_DSR_16_EN : R/W ;bitpos:[24] ;default: 1'h1 ; */ +/*description: */ +#define I2S_RX_PDM_SINC_DSR_16_EN (BIT(24)) +#define I2S_RX_PDM_SINC_DSR_16_EN_M (BIT(24)) +#define I2S_RX_PDM_SINC_DSR_16_EN_V 0x1 +#define I2S_RX_PDM_SINC_DSR_16_EN_S 24 +/* I2S_TX_PDM_SIGMADELTA_IN_SHIFT : R/W ;bitpos:[23:22] ;default: 2'h1 ; */ +/*description: */ +#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT 0x00000003 +#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_M ((I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V)<<(I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S)) +#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V 0x3 +#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S 22 +/* I2S_TX_PDM_SINC_IN_SHIFT : R/W ;bitpos:[21:20] ;default: 2'h1 ; */ +/*description: */ +#define I2S_TX_PDM_SINC_IN_SHIFT 0x00000003 +#define I2S_TX_PDM_SINC_IN_SHIFT_M ((I2S_TX_PDM_SINC_IN_SHIFT_V)<<(I2S_TX_PDM_SINC_IN_SHIFT_S)) +#define I2S_TX_PDM_SINC_IN_SHIFT_V 0x3 +#define I2S_TX_PDM_SINC_IN_SHIFT_S 20 +/* I2S_TX_PDM_LP_IN_SHIFT : R/W ;bitpos:[19:18] ;default: 2'h1 ; */ +/*description: */ +#define I2S_TX_PDM_LP_IN_SHIFT 0x00000003 +#define I2S_TX_PDM_LP_IN_SHIFT_M ((I2S_TX_PDM_LP_IN_SHIFT_V)<<(I2S_TX_PDM_LP_IN_SHIFT_S)) +#define I2S_TX_PDM_LP_IN_SHIFT_V 0x3 +#define I2S_TX_PDM_LP_IN_SHIFT_S 18 +/* I2S_TX_PDM_HP_IN_SHIFT : R/W ;bitpos:[17:16] ;default: 2'h1 ; */ +/*description: */ +#define I2S_TX_PDM_HP_IN_SHIFT 0x00000003 +#define I2S_TX_PDM_HP_IN_SHIFT_M ((I2S_TX_PDM_HP_IN_SHIFT_V)<<(I2S_TX_PDM_HP_IN_SHIFT_S)) +#define I2S_TX_PDM_HP_IN_SHIFT_V 0x3 +#define I2S_TX_PDM_HP_IN_SHIFT_S 16 +/* I2S_TX_PDM_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: */ +#define I2S_TX_PDM_PRESCALE 0x000000FF +#define I2S_TX_PDM_PRESCALE_M ((I2S_TX_PDM_PRESCALE_V)<<(I2S_TX_PDM_PRESCALE_S)) +#define I2S_TX_PDM_PRESCALE_V 0xFF +#define I2S_TX_PDM_PRESCALE_S 8 +/* I2S_TX_PDM_SINC_OSR2 : R/W ;bitpos:[7:4] ;default: 4'h2 ; */ +/*description: */ +#define I2S_TX_PDM_SINC_OSR2 0x0000000F +#define I2S_TX_PDM_SINC_OSR2_M ((I2S_TX_PDM_SINC_OSR2_V)<<(I2S_TX_PDM_SINC_OSR2_S)) +#define I2S_TX_PDM_SINC_OSR2_V 0xF +#define I2S_TX_PDM_SINC_OSR2_S 4 +/* I2S_PDM2PCM_CONV_EN : R/W ;bitpos:[3] ;default: 1'h0 ; */ +/*description: */ +#define I2S_PDM2PCM_CONV_EN (BIT(3)) +#define I2S_PDM2PCM_CONV_EN_M (BIT(3)) +#define I2S_PDM2PCM_CONV_EN_V 0x1 +#define I2S_PDM2PCM_CONV_EN_S 3 +/* I2S_PCM2PDM_CONV_EN : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define I2S_PCM2PDM_CONV_EN (BIT(2)) +#define I2S_PCM2PDM_CONV_EN_M (BIT(2)) +#define I2S_PCM2PDM_CONV_EN_V 0x1 +#define I2S_PCM2PDM_CONV_EN_S 2 +/* I2S_RX_PDM_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: */ +#define I2S_RX_PDM_EN (BIT(1)) +#define I2S_RX_PDM_EN_M (BIT(1)) +#define I2S_RX_PDM_EN_V 0x1 +#define I2S_RX_PDM_EN_S 1 +/* I2S_TX_PDM_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define I2S_TX_PDM_EN (BIT(0)) +#define I2S_TX_PDM_EN_M (BIT(0)) +#define I2S_TX_PDM_EN_V 0x1 +#define I2S_TX_PDM_EN_S 0 + +#define I2S_PDM_FREQ_CONF_REG(i) (REG_I2S_BASE(i) + 0x00b8) +/* I2S_TX_PDM_FP : R/W ;bitpos:[19:10] ;default: 10'd960 ; */ +/*description: */ +#define I2S_TX_PDM_FP 0x000003FF +#define I2S_TX_PDM_FP_M ((I2S_TX_PDM_FP_V)<<(I2S_TX_PDM_FP_S)) +#define I2S_TX_PDM_FP_V 0x3FF +#define I2S_TX_PDM_FP_S 10 +/* I2S_TX_PDM_FS : R/W ;bitpos:[9:0] ;default: 10'd480 ; */ +/*description: */ +#define I2S_TX_PDM_FS 0x000003FF +#define I2S_TX_PDM_FS_M ((I2S_TX_PDM_FS_V)<<(I2S_TX_PDM_FS_S)) +#define I2S_TX_PDM_FS_V 0x3FF +#define I2S_TX_PDM_FS_S 0 + +#define I2S_STATE_REG(i) (REG_I2S_BASE(i) + 0x00bc) +/* I2S_RX_FIFO_RESET_BACK : RO ;bitpos:[2] ;default: 1'b1 ; */ +/*description: */ +#define I2S_RX_FIFO_RESET_BACK (BIT(2)) +#define I2S_RX_FIFO_RESET_BACK_M (BIT(2)) +#define I2S_RX_FIFO_RESET_BACK_V 0x1 +#define I2S_RX_FIFO_RESET_BACK_S 2 +/* I2S_TX_FIFO_RESET_BACK : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: */ +#define I2S_TX_FIFO_RESET_BACK (BIT(1)) +#define I2S_TX_FIFO_RESET_BACK_M (BIT(1)) +#define I2S_TX_FIFO_RESET_BACK_V 0x1 +#define I2S_TX_FIFO_RESET_BACK_S 1 +/* I2S_TX_IDLE : RO ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define I2S_TX_IDLE (BIT(0)) +#define I2S_TX_IDLE_M (BIT(0)) +#define I2S_TX_IDLE_V 0x1 +#define I2S_TX_IDLE_S 0 + +#define I2S_DATE_REG(i) (REG_I2S_BASE(i) + 0x00fc) +/* I2S_I2SDATE : R/W ;bitpos:[31:0] ;default: 32'h1604201 ; */ +/*description: */ +#define I2S_I2SDATE 0xFFFFFFFF +#define I2S_I2SDATE_M ((I2S_I2SDATE_V)<<(I2S_I2SDATE_S)) +#define I2S_I2SDATE_V 0xFFFFFFFF +#define I2S_I2SDATE_S 0 + + + + +#endif /*_SOC_I2S_REG_H_ */ + + diff --git a/tools/sdk/include/esp32/soc/i2s_struct.h b/tools/sdk/include/esp32/soc/i2s_struct.h new file mode 100644 index 00000000..6d9fcbab --- /dev/null +++ b/tools/sdk/include/esp32/soc/i2s_struct.h @@ -0,0 +1,461 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_I2S_STRUCT_H_ +#define _SOC_I2S_STRUCT_H_ +typedef volatile struct { + uint32_t reserved_0; + uint32_t reserved_4; + union { + struct { + uint32_t tx_reset: 1; + uint32_t rx_reset: 1; + uint32_t tx_fifo_reset: 1; + uint32_t rx_fifo_reset: 1; + uint32_t tx_start: 1; + uint32_t rx_start: 1; + uint32_t tx_slave_mod: 1; + uint32_t rx_slave_mod: 1; + uint32_t tx_right_first: 1; + uint32_t rx_right_first: 1; + uint32_t tx_msb_shift: 1; + uint32_t rx_msb_shift: 1; + uint32_t tx_short_sync: 1; + uint32_t rx_short_sync: 1; + uint32_t tx_mono: 1; + uint32_t rx_mono: 1; + uint32_t tx_msb_right: 1; + uint32_t rx_msb_right: 1; + uint32_t sig_loopback: 1; + uint32_t reserved19: 13; + }; + uint32_t val; + } conf; + union { + struct { + uint32_t rx_take_data: 1; + uint32_t tx_put_data: 1; + uint32_t rx_wfull: 1; + uint32_t rx_rempty: 1; + uint32_t tx_wfull: 1; + uint32_t tx_rempty: 1; + uint32_t rx_hung: 1; + uint32_t tx_hung: 1; + uint32_t in_done: 1; + uint32_t in_suc_eof: 1; + uint32_t in_err_eof: 1; + uint32_t out_done: 1; + uint32_t out_eof: 1; + uint32_t in_dscr_err: 1; + uint32_t out_dscr_err: 1; + uint32_t in_dscr_empty: 1; + uint32_t out_total_eof: 1; + uint32_t reserved17: 15; + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t rx_take_data: 1; + uint32_t tx_put_data: 1; + uint32_t rx_wfull: 1; + uint32_t rx_rempty: 1; + uint32_t tx_wfull: 1; + uint32_t tx_rempty: 1; + uint32_t rx_hung: 1; + uint32_t tx_hung: 1; + uint32_t in_done: 1; + uint32_t in_suc_eof: 1; + uint32_t in_err_eof: 1; + uint32_t out_done: 1; + uint32_t out_eof: 1; + uint32_t in_dscr_err: 1; + uint32_t out_dscr_err: 1; + uint32_t in_dscr_empty: 1; + uint32_t out_total_eof: 1; + uint32_t reserved17: 15; + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t rx_take_data: 1; + uint32_t tx_put_data: 1; + uint32_t rx_wfull: 1; + uint32_t rx_rempty: 1; + uint32_t tx_wfull: 1; + uint32_t tx_rempty: 1; + uint32_t rx_hung: 1; + uint32_t tx_hung: 1; + uint32_t in_done: 1; + uint32_t in_suc_eof: 1; + uint32_t in_err_eof: 1; + uint32_t out_done: 1; + uint32_t out_eof: 1; + uint32_t in_dscr_err: 1; + uint32_t out_dscr_err: 1; + uint32_t in_dscr_empty: 1; + uint32_t out_total_eof: 1; + uint32_t reserved17: 15; + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t take_data: 1; + uint32_t put_data: 1; + uint32_t rx_wfull: 1; + uint32_t rx_rempty: 1; + uint32_t tx_wfull: 1; + uint32_t tx_rempty: 1; + uint32_t rx_hung: 1; + uint32_t tx_hung: 1; + uint32_t in_done: 1; + uint32_t in_suc_eof: 1; + uint32_t in_err_eof: 1; + uint32_t out_done: 1; + uint32_t out_eof: 1; + uint32_t in_dscr_err: 1; + uint32_t out_dscr_err: 1; + uint32_t in_dscr_empty: 1; + uint32_t out_total_eof: 1; + uint32_t reserved17: 15; + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t tx_bck_in_delay: 2; + uint32_t tx_ws_in_delay: 2; + uint32_t rx_bck_in_delay: 2; + uint32_t rx_ws_in_delay: 2; + uint32_t rx_sd_in_delay: 2; + uint32_t tx_bck_out_delay: 2; + uint32_t tx_ws_out_delay: 2; + uint32_t tx_sd_out_delay: 2; + uint32_t rx_ws_out_delay: 2; + uint32_t rx_bck_out_delay: 2; + uint32_t tx_dsync_sw: 1; + uint32_t rx_dsync_sw: 1; + uint32_t data_enable_delay: 2; + uint32_t tx_bck_in_inv: 1; + uint32_t reserved25: 7; + }; + uint32_t val; + } timing; + union { + struct { + uint32_t rx_data_num: 6; + uint32_t tx_data_num: 6; + uint32_t dscr_en: 1; + uint32_t tx_fifo_mod: 3; + uint32_t rx_fifo_mod: 3; + uint32_t tx_fifo_mod_force_en: 1; + uint32_t rx_fifo_mod_force_en: 1; + uint32_t reserved21: 11; + }; + uint32_t val; + } fifo_conf; + uint32_t rx_eof_num; + uint32_t conf_single_data; + union { + struct { + uint32_t tx_chan_mod: 3; + uint32_t rx_chan_mod: 2; + uint32_t reserved5: 27; + }; + uint32_t val; + } conf_chan; + union { + struct { + uint32_t addr: 20; + uint32_t reserved20: 8; + uint32_t stop: 1; + uint32_t start: 1; + uint32_t restart: 1; + uint32_t park: 1; + }; + uint32_t val; + } out_link; + union { + struct { + uint32_t addr: 20; + uint32_t reserved20: 8; + uint32_t stop: 1; + uint32_t start: 1; + uint32_t restart: 1; + uint32_t park: 1; + }; + uint32_t val; + } in_link; + uint32_t out_eof_des_addr; + uint32_t in_eof_des_addr; + uint32_t out_eof_bfr_des_addr; + union { + struct { + uint32_t mode: 3; + uint32_t reserved3: 1; + uint32_t addr: 2; + uint32_t reserved6: 26; + }; + uint32_t val; + } ahb_test; + uint32_t in_link_dscr; + uint32_t in_link_dscr_bf0; + uint32_t in_link_dscr_bf1; + uint32_t out_link_dscr; + uint32_t out_link_dscr_bf0; + uint32_t out_link_dscr_bf1; + union { + struct { + uint32_t in_rst: 1; + uint32_t out_rst: 1; + uint32_t ahbm_fifo_rst: 1; + uint32_t ahbm_rst: 1; + uint32_t out_loop_test: 1; + uint32_t in_loop_test: 1; + uint32_t out_auto_wrback: 1; + uint32_t out_no_restart_clr: 1; + uint32_t out_eof_mode: 1; + uint32_t outdscr_burst_en: 1; + uint32_t indscr_burst_en: 1; + uint32_t out_data_burst_en: 1; + uint32_t check_owner: 1; + uint32_t mem_trans_en: 1; + uint32_t reserved14: 18; + }; + uint32_t val; + } lc_conf; + union { + struct { + uint32_t wdata: 9; + uint32_t reserved9: 7; + uint32_t push: 1; + uint32_t reserved17: 15; + }; + uint32_t val; + } out_fifo_push; + union { + struct { + uint32_t rdata: 12; + uint32_t reserved12: 4; + uint32_t pop: 1; + uint32_t reserved17: 15; + }; + uint32_t val; + } in_fifo_pop; + uint32_t lc_state0; + uint32_t lc_state1; + union { + struct { + uint32_t fifo_timeout: 8; + uint32_t fifo_timeout_shift: 3; + uint32_t fifo_timeout_ena: 1; + uint32_t reserved12: 20; + }; + uint32_t val; + } lc_hung_conf; + uint32_t reserved_78; + uint32_t reserved_7c; + union { + struct { + uint32_t y_max:16; + uint32_t y_min:16; + }; + uint32_t val; + } cvsd_conf0; + union { + struct { + uint32_t sigma_max:16; + uint32_t sigma_min:16; + }; + uint32_t val; + } cvsd_conf1; + union { + struct { + uint32_t cvsd_k: 3; + uint32_t cvsd_j: 3; + uint32_t cvsd_beta: 10; + uint32_t cvsd_h: 3; + uint32_t reserved19:13; + }; + uint32_t val; + } cvsd_conf2; + union { + struct { + uint32_t good_pack_max: 6; + uint32_t n_err_seg: 3; + uint32_t shift_rate: 3; + uint32_t max_slide_sample: 8; + uint32_t pack_len_8k: 5; + uint32_t n_min_err: 3; + uint32_t reserved28: 4; + }; + uint32_t val; + } plc_conf0; + union { + struct { + uint32_t bad_cef_atten_para: 8; + uint32_t bad_cef_atten_para_shift: 4; + uint32_t bad_ola_win2_para_shift: 4; + uint32_t bad_ola_win2_para: 8; + uint32_t slide_win_len: 8; + }; + uint32_t val; + } plc_conf1; + union { + struct { + uint32_t cvsd_seg_mod: 2; + uint32_t min_period: 5; + uint32_t reserved7: 25; + }; + uint32_t val; + } plc_conf2; + union { + struct { + uint32_t en: 1; + uint32_t chan_mod: 1; + uint32_t cvsd_dec_pack_err: 1; + uint32_t cvsd_pack_len_8k: 5; + uint32_t cvsd_inf_en: 1; + uint32_t cvsd_dec_start: 1; + uint32_t cvsd_dec_reset: 1; + uint32_t plc_en: 1; + uint32_t plc2dma_en: 1; + uint32_t reserved13: 19; + }; + uint32_t val; + } esco_conf0; + union { + struct { + uint32_t with_en: 1; + uint32_t no_en: 1; + uint32_t cvsd_enc_start: 1; + uint32_t cvsd_enc_reset: 1; + uint32_t reserved4: 28; + }; + uint32_t val; + } sco_conf0; + union { + struct { + uint32_t tx_pcm_conf: 3; + uint32_t tx_pcm_bypass: 1; + uint32_t rx_pcm_conf: 3; + uint32_t rx_pcm_bypass: 1; + uint32_t tx_stop_en: 1; + uint32_t tx_zeros_rm_en: 1; + uint32_t reserved10: 22; + }; + uint32_t val; + } conf1; + union { + struct { + uint32_t fifo_force_pd: 1; + uint32_t fifo_force_pu: 1; + uint32_t plc_mem_force_pd: 1; + uint32_t plc_mem_force_pu: 1; + uint32_t reserved4: 28; + }; + uint32_t val; + } pd_conf; + union { + struct { + uint32_t camera_en: 1; + uint32_t lcd_tx_wrx2_en: 1; + uint32_t lcd_tx_sdx2_en: 1; + uint32_t data_enable_test_en: 1; + uint32_t data_enable: 1; + uint32_t lcd_en: 1; + uint32_t ext_adc_start_en: 1; + uint32_t inter_valid_en: 1; + uint32_t reserved8: 24; + }; + uint32_t val; + } conf2; + union { + struct { + uint32_t clkm_div_num: 8; + uint32_t clkm_div_b: 6; + uint32_t clkm_div_a: 6; + uint32_t clk_en: 1; + uint32_t clka_en: 1; + uint32_t reserved22: 10; + }; + uint32_t val; + } clkm_conf; + union { + struct { + uint32_t tx_bck_div_num: 6; + uint32_t rx_bck_div_num: 6; + uint32_t tx_bits_mod: 6; + uint32_t rx_bits_mod: 6; + uint32_t reserved24: 8; + }; + uint32_t val; + } sample_rate_conf; + union { + struct { + uint32_t tx_pdm_en: 1; + uint32_t rx_pdm_en: 1; + uint32_t pcm2pdm_conv_en: 1; + uint32_t pdm2pcm_conv_en: 1; + uint32_t tx_sinc_osr2: 4; + uint32_t tx_prescale: 8; + uint32_t tx_hp_in_shift: 2; + uint32_t tx_lp_in_shift: 2; + uint32_t tx_sinc_in_shift: 2; + uint32_t tx_sigmadelta_in_shift: 2; + uint32_t rx_sinc_dsr_16_en: 1; + uint32_t txhp_bypass: 1; + uint32_t reserved26: 6; + }; + uint32_t val; + } pdm_conf; + union { + struct { + uint32_t tx_pdm_fs: 10; + uint32_t tx_pdm_fp: 10; + uint32_t reserved20:12; + }; + uint32_t val; + } pdm_freq_conf; + union { + struct { + uint32_t tx_idle: 1; + uint32_t tx_fifo_reset_back: 1; + uint32_t rx_fifo_reset_back: 1; + uint32_t reserved3: 29; + }; + uint32_t val; + } state; + uint32_t reserved_c0; + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t reserved_cc; + uint32_t reserved_d0; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t reserved_f8; + uint32_t date; /**/ +} i2s_dev_t; +extern i2s_dev_t I2S0; +extern i2s_dev_t I2S1; + +#endif /* _SOC_I2S_STRUCT_H_ */ diff --git a/tools/sdk/include/esp32/soc/io_mux_reg.h b/tools/sdk/include/esp32/soc/io_mux_reg.h new file mode 100644 index 00000000..208a6070 --- /dev/null +++ b/tools/sdk/include/esp32/soc/io_mux_reg.h @@ -0,0 +1,267 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_IO_MUX_REG_H_ +#define _SOC_IO_MUX_REG_H_ + +#include "soc.h" + +#define SLP_OE (BIT(0)) +#define SLP_SEL (BIT(1)) +#define SLP_PD (BIT(2)) +#define SLP_PU (BIT(3)) +#define SLP_IE (BIT(4)) +#define SLP_DRV 0x3 +#define SLP_DRV_S 5 +#define FUN_PD (BIT(7)) +#define FUN_PU (BIT(8)) +#define FUN_IE (BIT(9)) +#define FUN_DRV 0x3 +#define FUN_DRV_S 10 +#define MCU_SEL 0x7 +#define MCU_SEL_S 12 + +#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE) +#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE) +#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv)); +#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU) +#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU) +#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD) +#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD) +#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC) + +#define PIN_FUNC_GPIO 2 + +#define PIN_CTRL (DR_REG_IO_MUX_BASE +0x00) +#define CLK_OUT3 0xf +#define CLK_OUT3_S 8 +#define CLK_OUT2 0xf +#define CLK_OUT2_S 4 +#define CLK_OUT1 0xf +#define CLK_OUT1_S 0 + +#define PERIPHS_IO_MUX_GPIO0_U (DR_REG_IO_MUX_BASE +0x44) +#define FUNC_GPIO0_EMAC_TX_CLK 5 +#define FUNC_GPIO0_GPIO0 2 +#define FUNC_GPIO0_CLK_OUT1 1 +#define FUNC_GPIO0_GPIO0_0 0 + +#define PERIPHS_IO_MUX_U0TXD_U (DR_REG_IO_MUX_BASE +0x88) +#define FUNC_U0TXD_EMAC_RXD2 3 +#define FUNC_U0TXD_GPIO1 2 +#define FUNC_U0TXD_CLK_OUT3 1 +#define FUNC_U0TXD_U0TXD 0 + +#define PERIPHS_IO_MUX_GPIO2_U (DR_REG_IO_MUX_BASE +0x40) +#define FUNC_GPIO2_SD_DATA0 4 +#define FUNC_GPIO2_HS2_DATA0 3 +#define FUNC_GPIO2_GPIO2 2 +#define FUNC_GPIO2_HSPIWP 1 +#define FUNC_GPIO2_GPIO2_0 0 + +#define PERIPHS_IO_MUX_U0RXD_U (DR_REG_IO_MUX_BASE +0x84) +#define FUNC_U0RXD_GPIO3 2 +#define FUNC_U0RXD_CLK_OUT2 1 +#define FUNC_U0RXD_U0RXD 0 + +#define PERIPHS_IO_MUX_GPIO4_U (DR_REG_IO_MUX_BASE +0x48) +#define FUNC_GPIO4_EMAC_TX_ER 5 +#define FUNC_GPIO4_SD_DATA1 4 +#define FUNC_GPIO4_HS2_DATA1 3 +#define FUNC_GPIO4_GPIO4 2 +#define FUNC_GPIO4_HSPIHD 1 +#define FUNC_GPIO4_GPIO4_0 0 + +#define PERIPHS_IO_MUX_GPIO5_U (DR_REG_IO_MUX_BASE +0x6c) +#define FUNC_GPIO5_EMAC_RX_CLK 5 +#define FUNC_GPIO5_HS1_DATA6 3 +#define FUNC_GPIO5_GPIO5 2 +#define FUNC_GPIO5_VSPICS0 1 +#define FUNC_GPIO5_GPIO5_0 0 + +#define PERIPHS_IO_MUX_SD_CLK_U (DR_REG_IO_MUX_BASE +0x60) +#define FUNC_SD_CLK_U1CTS 4 +#define FUNC_SD_CLK_HS1_CLK 3 +#define FUNC_SD_CLK_GPIO6 2 +#define FUNC_SD_CLK_SPICLK 1 +#define FUNC_SD_CLK_SD_CLK 0 + +#define PERIPHS_IO_MUX_SD_DATA0_U (DR_REG_IO_MUX_BASE +0x64) +#define FUNC_SD_DATA0_U2RTS 4 +#define FUNC_SD_DATA0_HS1_DATA0 3 +#define FUNC_SD_DATA0_GPIO7 2 +#define FUNC_SD_DATA0_SPIQ 1 +#define FUNC_SD_DATA0_SD_DATA0 0 + +#define PERIPHS_IO_MUX_SD_DATA1_U (DR_REG_IO_MUX_BASE +0x68) +#define FUNC_SD_DATA1_U2CTS 4 +#define FUNC_SD_DATA1_HS1_DATA1 3 +#define FUNC_SD_DATA1_GPIO8 2 +#define FUNC_SD_DATA1_SPID 1 +#define FUNC_SD_DATA1_SD_DATA1 0 + +#define PERIPHS_IO_MUX_SD_DATA2_U (DR_REG_IO_MUX_BASE +0x54) +#define FUNC_SD_DATA2_U1RXD 4 +#define FUNC_SD_DATA2_HS1_DATA2 3 +#define FUNC_SD_DATA2_GPIO9 2 +#define FUNC_SD_DATA2_SPIHD 1 +#define FUNC_SD_DATA2_SD_DATA2 0 + +#define PERIPHS_IO_MUX_SD_DATA3_U (DR_REG_IO_MUX_BASE +0x58) +#define FUNC_SD_DATA3_U1TXD 4 +#define FUNC_SD_DATA3_HS1_DATA3 3 +#define FUNC_SD_DATA3_GPIO10 2 +#define FUNC_SD_DATA3_SPIWP 1 +#define FUNC_SD_DATA3_SD_DATA3 0 + +#define PERIPHS_IO_MUX_SD_CMD_U (DR_REG_IO_MUX_BASE +0x5c) +#define FUNC_SD_CMD_U1RTS 4 +#define FUNC_SD_CMD_HS1_CMD 3 +#define FUNC_SD_CMD_GPIO11 2 +#define FUNC_SD_CMD_SPICS0 1 +#define FUNC_SD_CMD_SD_CMD 0 + +#define PERIPHS_IO_MUX_MTDI_U (DR_REG_IO_MUX_BASE +0x34) +#define FUNC_MTDI_EMAC_TXD3 5 +#define FUNC_MTDI_SD_DATA2 4 +#define FUNC_MTDI_HS2_DATA2 3 +#define FUNC_MTDI_GPIO12 2 +#define FUNC_MTDI_HSPIQ 1 +#define FUNC_MTDI_MTDI 0 + +#define PERIPHS_IO_MUX_MTCK_U (DR_REG_IO_MUX_BASE +0x38) +#define FUNC_MTCK_EMAC_RX_ER 5 +#define FUNC_MTCK_SD_DATA3 4 +#define FUNC_MTCK_HS2_DATA3 3 +#define FUNC_MTCK_GPIO13 2 +#define FUNC_MTCK_HSPID 1 +#define FUNC_MTCK_MTCK 0 + +#define PERIPHS_IO_MUX_MTMS_U (DR_REG_IO_MUX_BASE +0x30) +#define FUNC_MTMS_EMAC_TXD2 5 +#define FUNC_MTMS_SD_CLK 4 +#define FUNC_MTMS_HS2_CLk 3 +#define FUNC_MTMS_GPIO14 2 +#define FUNC_MTMS_HSPICLK 1 +#define FUNC_MTMS_MTMS 0 + +#define PERIPHS_IO_MUX_MTDO_U (DR_REG_IO_MUX_BASE +0x3c) +#define FUNC_MTDO_EMAC_RXD3 5 +#define FUNC_MTDO_SD_CMD 4 +#define FUNC_MTDO_HS2_CMD 3 +#define FUNC_MTDO_GPIO15 2 +#define FUNC_MTDO_HSPICS0 1 +#define FUNC_MTDO_MTDO 0 + +#define PERIPHS_IO_MUX_GPIO16_U (DR_REG_IO_MUX_BASE +0x4c) +#define FUNC_GPIO16_EMAC_CLK_OUT 5 +#define FUNC_GPIO16_U2RXD 4 +#define FUNC_GPIO16_HS1_DATA4 3 +#define FUNC_GPIO16_GPIO16 2 +#define FUNC_GPIO16_GPIO16_0 0 + +#define PERIPHS_IO_MUX_GPIO17_U (DR_REG_IO_MUX_BASE +0x50) +#define FUNC_GPIO17_EMAC_CLK_OUT_180 5 +#define FUNC_GPIO17_U2TXD 4 +#define FUNC_GPIO17_HS1_DATA5 3 +#define FUNC_GPIO17_GPIO17 2 +#define FUNC_GPIO17_GPIO17_0 0 + +#define PERIPHS_IO_MUX_GPIO18_U (DR_REG_IO_MUX_BASE +0x70) +#define FUNC_GPIO18_HS1_DATA7 3 +#define FUNC_GPIO18_GPIO18 2 +#define FUNC_GPIO18_VSPICLK 1 +#define FUNC_GPIO18_GPIO18_0 0 + +#define PERIPHS_IO_MUX_GPIO19_U (DR_REG_IO_MUX_BASE +0x74) +#define FUNC_GPIO19_EMAC_TXD0 5 +#define FUNC_GPIO19_U0CTS 3 +#define FUNC_GPIO19_GPIO19 2 +#define FUNC_GPIO19_VSPIQ 1 +#define FUNC_GPIO19_GPIO19_0 0 + +#define PERIPHS_IO_MUX_GPIO20_U (DR_REG_IO_MUX_BASE +0x78) +#define FUNC_GPIO20_GPIO20 2 +#define FUNC_GPIO20_GPIO20_0 0 + +#define PERIPHS_IO_MUX_GPIO21_U (DR_REG_IO_MUX_BASE +0x7c) +#define FUNC_GPIO21_EMAC_TX_EN 5 +#define FUNC_GPIO21_GPIO21 2 +#define FUNC_GPIO21_VSPIHD 1 +#define FUNC_GPIO21_GPIO21_0 0 + +#define PERIPHS_IO_MUX_GPIO22_U (DR_REG_IO_MUX_BASE +0x80) +#define FUNC_GPIO22_EMAC_TXD1 5 +#define FUNC_GPIO22_U0RTS 3 +#define FUNC_GPIO22_GPIO22 2 +#define FUNC_GPIO22_VSPIWP 1 +#define FUNC_GPIO22_GPIO22_0 0 + +#define PERIPHS_IO_MUX_GPIO23_U (DR_REG_IO_MUX_BASE +0x8c) +#define FUNC_GPIO23_HS1_STROBE 3 +#define FUNC_GPIO23_GPIO23 2 +#define FUNC_GPIO23_VSPID 1 +#define FUNC_GPIO23_GPIO23_0 0 + +#define PERIPHS_IO_MUX_GPIO24_U (DR_REG_IO_MUX_BASE +0x90) +#define FUNC_GPIO24_GPIO24 2 +#define FUNC_GPIO24_GPIO24_0 0 + +#define PERIPHS_IO_MUX_GPIO25_U (DR_REG_IO_MUX_BASE +0x24) +#define FUNC_GPIO25_EMAC_RXD0 5 +#define FUNC_GPIO25_GPIO25 2 +#define FUNC_GPIO25_GPIO25_0 0 + +#define PERIPHS_IO_MUX_GPIO26_U (DR_REG_IO_MUX_BASE +0x28) +#define FUNC_GPIO26_EMAC_RXD1 5 +#define FUNC_GPIO26_GPIO26 2 +#define FUNC_GPIO26_GPIO26_0 0 + +#define PERIPHS_IO_MUX_GPIO27_U (DR_REG_IO_MUX_BASE +0x2c) +#define FUNC_GPIO27_EMAC_RX_DV 5 +#define FUNC_GPIO27_GPIO27 2 +#define FUNC_GPIO27_GPIO27_0 0 + +#define PERIPHS_IO_MUX_GPIO32_U (DR_REG_IO_MUX_BASE +0x1c) +#define FUNC_GPIO32_GPIO32 2 +#define FUNC_GPIO32_GPIO32_0 0 + +#define PERIPHS_IO_MUX_GPIO33_U (DR_REG_IO_MUX_BASE +0x20) +#define FUNC_GPIO33_GPIO33 2 +#define FUNC_GPIO33_GPIO33_0 0 + +#define PERIPHS_IO_MUX_GPIO34_U (DR_REG_IO_MUX_BASE +0x14) +#define FUNC_GPIO34_GPIO34 2 +#define FUNC_GPIO34_GPIO34_0 0 + +#define PERIPHS_IO_MUX_GPIO35_U (DR_REG_IO_MUX_BASE +0x18) +#define FUNC_GPIO35_GPIO35 2 +#define FUNC_GPIO35_GPIO35_0 0 + +#define PERIPHS_IO_MUX_GPIO36_U (DR_REG_IO_MUX_BASE +0x04) +#define FUNC_GPIO36_GPIO36 2 +#define FUNC_GPIO36_GPIO36_0 0 + +#define PERIPHS_IO_MUX_GPIO37_U (DR_REG_IO_MUX_BASE +0x08) +#define FUNC_GPIO37_GPIO37 2 +#define FUNC_GPIO37_GPIO37_0 0 + +#define PERIPHS_IO_MUX_GPIO38_U (DR_REG_IO_MUX_BASE +0x0c) +#define FUNC_GPIO38_GPIO38 2 +#define FUNC_GPIO38_GPIO38_0 0 + +#define PERIPHS_IO_MUX_GPIO39_U (DR_REG_IO_MUX_BASE +0x10) +#define FUNC_GPIO39_GPIO39 2 +#define FUNC_GPIO39_GPIO39_0 0 + +#endif /* _SOC_IO_MUX_REG_H_ */ diff --git a/tools/sdk/include/esp32/soc/ledc_reg.h b/tools/sdk/include/esp32/soc/ledc_reg.h new file mode 100644 index 00000000..1137e3da --- /dev/null +++ b/tools/sdk/include/esp32/soc/ledc_reg.h @@ -0,0 +1,2423 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_LEDC_REG_H_ +#define _SOC_LEDC_REG_H_ + + +#include "soc.h" +#define LEDC_HSCH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0000) +/* LEDC_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: This bit is clock gating control signal. when software config + LED_PWM internal registers it controls the register clock.*/ +#define LEDC_CLK_EN (BIT(31)) +#define LEDC_CLK_EN_M (BIT(31)) +#define LEDC_CLK_EN_V 0x1 +#define LEDC_CLK_EN_S 31 +/* LEDC_IDLE_LV_HSCH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when high speed channel0 is off.*/ +#define LEDC_IDLE_LV_HSCH0 (BIT(3)) +#define LEDC_IDLE_LV_HSCH0_M (BIT(3)) +#define LEDC_IDLE_LV_HSCH0_V 0x1 +#define LEDC_IDLE_LV_HSCH0_S 3 +/* LEDC_SIG_OUT_EN_HSCH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for high speed channel0*/ +#define LEDC_SIG_OUT_EN_HSCH0 (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH0_M (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH0_V 0x1 +#define LEDC_SIG_OUT_EN_HSCH0_S 2 +/* LEDC_TIMER_SEL_HSCH0 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four high speed timers the two bits are used to select + one of them for high speed channel0. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ +#define LEDC_TIMER_SEL_HSCH0 0x00000003 +#define LEDC_TIMER_SEL_HSCH0_M ((LEDC_TIMER_SEL_HSCH0_V)<<(LEDC_TIMER_SEL_HSCH0_S)) +#define LEDC_TIMER_SEL_HSCH0_V 0x3 +#define LEDC_TIMER_SEL_HSCH0_S 0 + +#define LEDC_HSCH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x0004) +/* LEDC_HPOINT_HSCH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when htimerx(x=[0 3]) selected + by high speed channel0 has reached reg_hpoint_hsch0[19:0]*/ +#define LEDC_HPOINT_HSCH0 0x000FFFFF +#define LEDC_HPOINT_HSCH0_M ((LEDC_HPOINT_HSCH0_V)<<(LEDC_HPOINT_HSCH0_S)) +#define LEDC_HPOINT_HSCH0_V 0xFFFFF +#define LEDC_HPOINT_HSCH0_S 0 + +#define LEDC_HSCH0_DUTY_REG (DR_REG_LEDC_BASE + 0x0008) +/* LEDC_DUTY_HSCH0 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When hstimerx(x=[0 + 3]) choosed by high speed channel0 has reached reg_lpoint_hsch0 the output signal changes to low. reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4]) (1) reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_HSCH0 0x01FFFFFF +#define LEDC_DUTY_HSCH0_M ((LEDC_DUTY_HSCH0_V)<<(LEDC_DUTY_HSCH0_S)) +#define LEDC_DUTY_HSCH0_V 0x1FFFFFF +#define LEDC_DUTY_HSCH0_S 0 + +#define LEDC_HSCH0_CONF1_REG (DR_REG_LEDC_BASE + 0x000C) +/* LEDC_DUTY_START_HSCH0 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch0 reg_duty_cycle_hsch0 and reg_duty_scale_hsch0 + has been configured. these register won't take effect until set reg_duty_start_hsch0. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_HSCH0 (BIT(31)) +#define LEDC_DUTY_START_HSCH0_M (BIT(31)) +#define LEDC_DUTY_START_HSCH0_V 0x1 +#define LEDC_DUTY_START_HSCH0_S 31 +/* LEDC_DUTY_INC_HSCH0 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for high speed channel0.*/ +#define LEDC_DUTY_INC_HSCH0 (BIT(30)) +#define LEDC_DUTY_INC_HSCH0_M (BIT(30)) +#define LEDC_DUTY_INC_HSCH0_V 0x1 +#define LEDC_DUTY_INC_HSCH0_S 30 +/* LEDC_DUTY_NUM_HSCH0 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for high speed channel0.*/ +#define LEDC_DUTY_NUM_HSCH0 0x000003FF +#define LEDC_DUTY_NUM_HSCH0_M ((LEDC_DUTY_NUM_HSCH0_V)<<(LEDC_DUTY_NUM_HSCH0_S)) +#define LEDC_DUTY_NUM_HSCH0_V 0x3FF +#define LEDC_DUTY_NUM_HSCH0_S 20 +/* LEDC_DUTY_CYCLE_HSCH0 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_hsch0 cycles for high speed channel0.*/ +#define LEDC_DUTY_CYCLE_HSCH0 0x000003FF +#define LEDC_DUTY_CYCLE_HSCH0_M ((LEDC_DUTY_CYCLE_HSCH0_V)<<(LEDC_DUTY_CYCLE_HSCH0_S)) +#define LEDC_DUTY_CYCLE_HSCH0_V 0x3FF +#define LEDC_DUTY_CYCLE_HSCH0_S 10 +/* LEDC_DUTY_SCALE_HSCH0 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + high speed channel0.*/ +#define LEDC_DUTY_SCALE_HSCH0 0x000003FF +#define LEDC_DUTY_SCALE_HSCH0_M ((LEDC_DUTY_SCALE_HSCH0_V)<<(LEDC_DUTY_SCALE_HSCH0_S)) +#define LEDC_DUTY_SCALE_HSCH0_V 0x3FF +#define LEDC_DUTY_SCALE_HSCH0_S 0 + +#define LEDC_HSCH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0010) +/* LEDC_DUTY_HSCH0 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for high speed channel0.*/ +#define LEDC_DUTY_HSCH0 0x01FFFFFF +#define LEDC_DUTY_HSCH0_M ((LEDC_DUTY_HSCH0_V)<<(LEDC_DUTY_HSCH0_S)) +#define LEDC_DUTY_HSCH0_V 0x1FFFFFF +#define LEDC_DUTY_HSCH0_S 0 + +#define LEDC_HSCH1_CONF0_REG (DR_REG_LEDC_BASE + 0x0014) +/* LEDC_IDLE_LV_HSCH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when high speed channel1 is off.*/ +#define LEDC_IDLE_LV_HSCH1 (BIT(3)) +#define LEDC_IDLE_LV_HSCH1_M (BIT(3)) +#define LEDC_IDLE_LV_HSCH1_V 0x1 +#define LEDC_IDLE_LV_HSCH1_S 3 +/* LEDC_SIG_OUT_EN_HSCH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for high speed channel1*/ +#define LEDC_SIG_OUT_EN_HSCH1 (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH1_M (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH1_V 0x1 +#define LEDC_SIG_OUT_EN_HSCH1_S 2 +/* LEDC_TIMER_SEL_HSCH1 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four high speed timers the two bits are used to select + one of them for high speed channel1. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ +#define LEDC_TIMER_SEL_HSCH1 0x00000003 +#define LEDC_TIMER_SEL_HSCH1_M ((LEDC_TIMER_SEL_HSCH1_V)<<(LEDC_TIMER_SEL_HSCH1_S)) +#define LEDC_TIMER_SEL_HSCH1_V 0x3 +#define LEDC_TIMER_SEL_HSCH1_S 0 + +#define LEDC_HSCH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x0018) +/* LEDC_HPOINT_HSCH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when htimerx(x=[0 3]) selected + by high speed channel1 has reached reg_hpoint_hsch1[19:0]*/ +#define LEDC_HPOINT_HSCH1 0x000FFFFF +#define LEDC_HPOINT_HSCH1_M ((LEDC_HPOINT_HSCH1_V)<<(LEDC_HPOINT_HSCH1_S)) +#define LEDC_HPOINT_HSCH1_V 0xFFFFF +#define LEDC_HPOINT_HSCH1_S 0 + +#define LEDC_HSCH1_DUTY_REG (DR_REG_LEDC_BASE + 0x001C) +/* LEDC_DUTY_HSCH1 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When hstimerx(x=[0 + 3]) choosed by high speed channel1 has reached reg_lpoint_hsch1 the output signal changes to low. reg_lpoint_hsch1=(reg_hpoint_hsch1[19:0]+reg_duty_hsch1[24:4]) (1) reg_lpoint_hsch1=(reg_hpoint_hsch1[19:0]+reg_duty_hsch1[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_HSCH1 0x01FFFFFF +#define LEDC_DUTY_HSCH1_M ((LEDC_DUTY_HSCH1_V)<<(LEDC_DUTY_HSCH1_S)) +#define LEDC_DUTY_HSCH1_V 0x1FFFFFF +#define LEDC_DUTY_HSCH1_S 0 + +#define LEDC_HSCH1_CONF1_REG (DR_REG_LEDC_BASE + 0x0020) +/* LEDC_DUTY_START_HSCH1 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 + has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_HSCH1 (BIT(31)) +#define LEDC_DUTY_START_HSCH1_M (BIT(31)) +#define LEDC_DUTY_START_HSCH1_V 0x1 +#define LEDC_DUTY_START_HSCH1_S 31 +/* LEDC_DUTY_INC_HSCH1 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for high speed channel1.*/ +#define LEDC_DUTY_INC_HSCH1 (BIT(30)) +#define LEDC_DUTY_INC_HSCH1_M (BIT(30)) +#define LEDC_DUTY_INC_HSCH1_V 0x1 +#define LEDC_DUTY_INC_HSCH1_S 30 +/* LEDC_DUTY_NUM_HSCH1 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for high speed channel1.*/ +#define LEDC_DUTY_NUM_HSCH1 0x000003FF +#define LEDC_DUTY_NUM_HSCH1_M ((LEDC_DUTY_NUM_HSCH1_V)<<(LEDC_DUTY_NUM_HSCH1_S)) +#define LEDC_DUTY_NUM_HSCH1_V 0x3FF +#define LEDC_DUTY_NUM_HSCH1_S 20 +/* LEDC_DUTY_CYCLE_HSCH1 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_hsch1 cycles for high speed channel1.*/ +#define LEDC_DUTY_CYCLE_HSCH1 0x000003FF +#define LEDC_DUTY_CYCLE_HSCH1_M ((LEDC_DUTY_CYCLE_HSCH1_V)<<(LEDC_DUTY_CYCLE_HSCH1_S)) +#define LEDC_DUTY_CYCLE_HSCH1_V 0x3FF +#define LEDC_DUTY_CYCLE_HSCH1_S 10 +/* LEDC_DUTY_SCALE_HSCH1 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + high speed channel1.*/ +#define LEDC_DUTY_SCALE_HSCH1 0x000003FF +#define LEDC_DUTY_SCALE_HSCH1_M ((LEDC_DUTY_SCALE_HSCH1_V)<<(LEDC_DUTY_SCALE_HSCH1_S)) +#define LEDC_DUTY_SCALE_HSCH1_V 0x3FF +#define LEDC_DUTY_SCALE_HSCH1_S 0 + +#define LEDC_HSCH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0024) +/* LEDC_DUTY_HSCH1 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for high speed channel1.*/ +#define LEDC_DUTY_HSCH1 0x01FFFFFF +#define LEDC_DUTY_HSCH1_M ((LEDC_DUTY_HSCH1_V)<<(LEDC_DUTY_HSCH1_S)) +#define LEDC_DUTY_HSCH1_V 0x1FFFFFF +#define LEDC_DUTY_HSCH1_S 0 + +#define LEDC_HSCH2_CONF0_REG (DR_REG_LEDC_BASE + 0x0028) +/* LEDC_IDLE_LV_HSCH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when high speed channel2 is off.*/ +#define LEDC_IDLE_LV_HSCH2 (BIT(3)) +#define LEDC_IDLE_LV_HSCH2_M (BIT(3)) +#define LEDC_IDLE_LV_HSCH2_V 0x1 +#define LEDC_IDLE_LV_HSCH2_S 3 +/* LEDC_SIG_OUT_EN_HSCH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for high speed channel2*/ +#define LEDC_SIG_OUT_EN_HSCH2 (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH2_M (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH2_V 0x1 +#define LEDC_SIG_OUT_EN_HSCH2_S 2 +/* LEDC_TIMER_SEL_HSCH2 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four high speed timers the two bits are used to select + one of them for high speed channel2. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ +#define LEDC_TIMER_SEL_HSCH2 0x00000003 +#define LEDC_TIMER_SEL_HSCH2_M ((LEDC_TIMER_SEL_HSCH2_V)<<(LEDC_TIMER_SEL_HSCH2_S)) +#define LEDC_TIMER_SEL_HSCH2_V 0x3 +#define LEDC_TIMER_SEL_HSCH2_S 0 + +#define LEDC_HSCH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x002C) +/* LEDC_HPOINT_HSCH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when htimerx(x=[0 3]) selected + by high speed channel2 has reached reg_hpoint_hsch2[19:0]*/ +#define LEDC_HPOINT_HSCH2 0x000FFFFF +#define LEDC_HPOINT_HSCH2_M ((LEDC_HPOINT_HSCH2_V)<<(LEDC_HPOINT_HSCH2_S)) +#define LEDC_HPOINT_HSCH2_V 0xFFFFF +#define LEDC_HPOINT_HSCH2_S 0 + +#define LEDC_HSCH2_DUTY_REG (DR_REG_LEDC_BASE + 0x0030) +/* LEDC_DUTY_HSCH2 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When hstimerx(x=[0 + 3]) choosed by high speed channel2 has reached reg_lpoint_hsch2 the output signal changes to low. reg_lpoint_hsch2=(reg_hpoint_hsch2[19:0]+reg_duty_hsch2[24:4]) (1) reg_lpoint_hsch2=(reg_hpoint_hsch2[19:0]+reg_duty_hsch2[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_HSCH2 0x01FFFFFF +#define LEDC_DUTY_HSCH2_M ((LEDC_DUTY_HSCH2_V)<<(LEDC_DUTY_HSCH2_S)) +#define LEDC_DUTY_HSCH2_V 0x1FFFFFF +#define LEDC_DUTY_HSCH2_S 0 + +#define LEDC_HSCH2_CONF1_REG (DR_REG_LEDC_BASE + 0x0034) +/* LEDC_DUTY_START_HSCH2 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch2 reg_duty_cycle_hsch2 and reg_duty_scale_hsch2 + has been configured. these register won't take effect until set reg_duty_start_hsch2. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_HSCH2 (BIT(31)) +#define LEDC_DUTY_START_HSCH2_M (BIT(31)) +#define LEDC_DUTY_START_HSCH2_V 0x1 +#define LEDC_DUTY_START_HSCH2_S 31 +/* LEDC_DUTY_INC_HSCH2 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for high speed channel2.*/ +#define LEDC_DUTY_INC_HSCH2 (BIT(30)) +#define LEDC_DUTY_INC_HSCH2_M (BIT(30)) +#define LEDC_DUTY_INC_HSCH2_V 0x1 +#define LEDC_DUTY_INC_HSCH2_S 30 +/* LEDC_DUTY_NUM_HSCH2 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for high speed channel2.*/ +#define LEDC_DUTY_NUM_HSCH2 0x000003FF +#define LEDC_DUTY_NUM_HSCH2_M ((LEDC_DUTY_NUM_HSCH2_V)<<(LEDC_DUTY_NUM_HSCH2_S)) +#define LEDC_DUTY_NUM_HSCH2_V 0x3FF +#define LEDC_DUTY_NUM_HSCH2_S 20 +/* LEDC_DUTY_CYCLE_HSCH2 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_hsch2 cycles for high speed channel2.*/ +#define LEDC_DUTY_CYCLE_HSCH2 0x000003FF +#define LEDC_DUTY_CYCLE_HSCH2_M ((LEDC_DUTY_CYCLE_HSCH2_V)<<(LEDC_DUTY_CYCLE_HSCH2_S)) +#define LEDC_DUTY_CYCLE_HSCH2_V 0x3FF +#define LEDC_DUTY_CYCLE_HSCH2_S 10 +/* LEDC_DUTY_SCALE_HSCH2 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + high speed channel2.*/ +#define LEDC_DUTY_SCALE_HSCH2 0x000003FF +#define LEDC_DUTY_SCALE_HSCH2_M ((LEDC_DUTY_SCALE_HSCH2_V)<<(LEDC_DUTY_SCALE_HSCH2_S)) +#define LEDC_DUTY_SCALE_HSCH2_V 0x3FF +#define LEDC_DUTY_SCALE_HSCH2_S 0 + +#define LEDC_HSCH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0038) +/* LEDC_DUTY_HSCH2 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for high speed channel2.*/ +#define LEDC_DUTY_HSCH2 0x01FFFFFF +#define LEDC_DUTY_HSCH2_M ((LEDC_DUTY_HSCH2_V)<<(LEDC_DUTY_HSCH2_S)) +#define LEDC_DUTY_HSCH2_V 0x1FFFFFF +#define LEDC_DUTY_HSCH2_S 0 + +#define LEDC_HSCH3_CONF0_REG (DR_REG_LEDC_BASE + 0x003C) +/* LEDC_IDLE_LV_HSCH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when high speed channel3 is off.*/ +#define LEDC_IDLE_LV_HSCH3 (BIT(3)) +#define LEDC_IDLE_LV_HSCH3_M (BIT(3)) +#define LEDC_IDLE_LV_HSCH3_V 0x1 +#define LEDC_IDLE_LV_HSCH3_S 3 +/* LEDC_SIG_OUT_EN_HSCH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for high speed channel3*/ +#define LEDC_SIG_OUT_EN_HSCH3 (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH3_M (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH3_V 0x1 +#define LEDC_SIG_OUT_EN_HSCH3_S 2 +/* LEDC_TIMER_SEL_HSCH3 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four high speed timers the two bits are used to select + one of them for high speed channel3. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ +#define LEDC_TIMER_SEL_HSCH3 0x00000003 +#define LEDC_TIMER_SEL_HSCH3_M ((LEDC_TIMER_SEL_HSCH3_V)<<(LEDC_TIMER_SEL_HSCH3_S)) +#define LEDC_TIMER_SEL_HSCH3_V 0x3 +#define LEDC_TIMER_SEL_HSCH3_S 0 + +#define LEDC_HSCH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x0040) +/* LEDC_HPOINT_HSCH3 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when htimerx(x=[0 3]) selected + by high speed channel3 has reached reg_hpoint_hsch3[19:0]*/ +#define LEDC_HPOINT_HSCH3 0x000FFFFF +#define LEDC_HPOINT_HSCH3_M ((LEDC_HPOINT_HSCH3_V)<<(LEDC_HPOINT_HSCH3_S)) +#define LEDC_HPOINT_HSCH3_V 0xFFFFF +#define LEDC_HPOINT_HSCH3_S 0 + +#define LEDC_HSCH3_DUTY_REG (DR_REG_LEDC_BASE + 0x0044) +/* LEDC_DUTY_HSCH3 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When hstimerx(x=[0 + 3]) choosed by high speed channel3 has reached reg_lpoint_hsch3 the output signal changes to low. reg_lpoint_hsch3=(reg_hpoint_hsch3[19:0]+reg_duty_hsch3[24:4]) (1) reg_lpoint_hsch3=(reg_hpoint_hsch3[19:0]+reg_duty_hsch3[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_HSCH3 0x01FFFFFF +#define LEDC_DUTY_HSCH3_M ((LEDC_DUTY_HSCH3_V)<<(LEDC_DUTY_HSCH3_S)) +#define LEDC_DUTY_HSCH3_V 0x1FFFFFF +#define LEDC_DUTY_HSCH3_S 0 + +#define LEDC_HSCH3_CONF1_REG (DR_REG_LEDC_BASE + 0x0048) +/* LEDC_DUTY_START_HSCH3 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch3 reg_duty_cycle_hsch3 and reg_duty_scale_hsch3 + has been configured. these register won't take effect until set reg_duty_start_hsch3. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_HSCH3 (BIT(31)) +#define LEDC_DUTY_START_HSCH3_M (BIT(31)) +#define LEDC_DUTY_START_HSCH3_V 0x1 +#define LEDC_DUTY_START_HSCH3_S 31 +/* LEDC_DUTY_INC_HSCH3 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for high speed channel3.*/ +#define LEDC_DUTY_INC_HSCH3 (BIT(30)) +#define LEDC_DUTY_INC_HSCH3_M (BIT(30)) +#define LEDC_DUTY_INC_HSCH3_V 0x1 +#define LEDC_DUTY_INC_HSCH3_S 30 +/* LEDC_DUTY_NUM_HSCH3 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for high speed channel3.*/ +#define LEDC_DUTY_NUM_HSCH3 0x000003FF +#define LEDC_DUTY_NUM_HSCH3_M ((LEDC_DUTY_NUM_HSCH3_V)<<(LEDC_DUTY_NUM_HSCH3_S)) +#define LEDC_DUTY_NUM_HSCH3_V 0x3FF +#define LEDC_DUTY_NUM_HSCH3_S 20 +/* LEDC_DUTY_CYCLE_HSCH3 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_hsch3 cycles for high speed channel3.*/ +#define LEDC_DUTY_CYCLE_HSCH3 0x000003FF +#define LEDC_DUTY_CYCLE_HSCH3_M ((LEDC_DUTY_CYCLE_HSCH3_V)<<(LEDC_DUTY_CYCLE_HSCH3_S)) +#define LEDC_DUTY_CYCLE_HSCH3_V 0x3FF +#define LEDC_DUTY_CYCLE_HSCH3_S 10 +/* LEDC_DUTY_SCALE_HSCH3 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + high speed channel3.*/ +#define LEDC_DUTY_SCALE_HSCH3 0x000003FF +#define LEDC_DUTY_SCALE_HSCH3_M ((LEDC_DUTY_SCALE_HSCH3_V)<<(LEDC_DUTY_SCALE_HSCH3_S)) +#define LEDC_DUTY_SCALE_HSCH3_V 0x3FF +#define LEDC_DUTY_SCALE_HSCH3_S 0 + +#define LEDC_HSCH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x004C) +/* LEDC_DUTY_HSCH3 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for high speed channel3.*/ +#define LEDC_DUTY_HSCH3 0x01FFFFFF +#define LEDC_DUTY_HSCH3_M ((LEDC_DUTY_HSCH3_V)<<(LEDC_DUTY_HSCH3_S)) +#define LEDC_DUTY_HSCH3_V 0x1FFFFFF +#define LEDC_DUTY_HSCH3_S 0 + +#define LEDC_HSCH4_CONF0_REG (DR_REG_LEDC_BASE + 0x0050) +/* LEDC_IDLE_LV_HSCH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when high speed channel4 is off.*/ +#define LEDC_IDLE_LV_HSCH4 (BIT(3)) +#define LEDC_IDLE_LV_HSCH4_M (BIT(3)) +#define LEDC_IDLE_LV_HSCH4_V 0x1 +#define LEDC_IDLE_LV_HSCH4_S 3 +/* LEDC_SIG_OUT_EN_HSCH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for high speed channel4*/ +#define LEDC_SIG_OUT_EN_HSCH4 (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH4_M (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH4_V 0x1 +#define LEDC_SIG_OUT_EN_HSCH4_S 2 +/* LEDC_TIMER_SEL_HSCH4 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four high speed timers the two bits are used to select + one of them for high speed channel4. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ +#define LEDC_TIMER_SEL_HSCH4 0x00000003 +#define LEDC_TIMER_SEL_HSCH4_M ((LEDC_TIMER_SEL_HSCH4_V)<<(LEDC_TIMER_SEL_HSCH4_S)) +#define LEDC_TIMER_SEL_HSCH4_V 0x3 +#define LEDC_TIMER_SEL_HSCH4_S 0 + +#define LEDC_HSCH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x0054) +/* LEDC_HPOINT_HSCH4 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when htimerx(x=[0 3]) selected + by high speed channel4 has reached reg_hpoint_hsch4[19:0]*/ +#define LEDC_HPOINT_HSCH4 0x000FFFFF +#define LEDC_HPOINT_HSCH4_M ((LEDC_HPOINT_HSCH4_V)<<(LEDC_HPOINT_HSCH4_S)) +#define LEDC_HPOINT_HSCH4_V 0xFFFFF +#define LEDC_HPOINT_HSCH4_S 0 + +#define LEDC_HSCH4_DUTY_REG (DR_REG_LEDC_BASE + 0x0058) +/* LEDC_DUTY_HSCH4 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When hstimerx(x=[0 + 3]) choosed by high speed channel4 has reached reg_lpoint_hsch4 the output signal changes to low. reg_lpoint_hsch4=(reg_hpoint_hsch4[19:0]+reg_duty_hsch4[24:4]) (1) reg_lpoint_hsch4=(reg_hpoint_hsch4[19:0]+reg_duty_hsch4[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_HSCH4 0x01FFFFFF +#define LEDC_DUTY_HSCH4_M ((LEDC_DUTY_HSCH4_V)<<(LEDC_DUTY_HSCH4_S)) +#define LEDC_DUTY_HSCH4_V 0x1FFFFFF +#define LEDC_DUTY_HSCH4_S 0 + +#define LEDC_HSCH4_CONF1_REG (DR_REG_LEDC_BASE + 0x005C) +/* LEDC_DUTY_START_HSCH4 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 + has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_HSCH4 (BIT(31)) +#define LEDC_DUTY_START_HSCH4_M (BIT(31)) +#define LEDC_DUTY_START_HSCH4_V 0x1 +#define LEDC_DUTY_START_HSCH4_S 31 +/* LEDC_DUTY_INC_HSCH4 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for high speed channel4.*/ +#define LEDC_DUTY_INC_HSCH4 (BIT(30)) +#define LEDC_DUTY_INC_HSCH4_M (BIT(30)) +#define LEDC_DUTY_INC_HSCH4_V 0x1 +#define LEDC_DUTY_INC_HSCH4_S 30 +/* LEDC_DUTY_NUM_HSCH4 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for high speed channel1.*/ +#define LEDC_DUTY_NUM_HSCH4 0x000003FF +#define LEDC_DUTY_NUM_HSCH4_M ((LEDC_DUTY_NUM_HSCH4_V)<<(LEDC_DUTY_NUM_HSCH4_S)) +#define LEDC_DUTY_NUM_HSCH4_V 0x3FF +#define LEDC_DUTY_NUM_HSCH4_S 20 +/* LEDC_DUTY_CYCLE_HSCH4 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_hsch4 cycles for high speed channel4.*/ +#define LEDC_DUTY_CYCLE_HSCH4 0x000003FF +#define LEDC_DUTY_CYCLE_HSCH4_M ((LEDC_DUTY_CYCLE_HSCH4_V)<<(LEDC_DUTY_CYCLE_HSCH4_S)) +#define LEDC_DUTY_CYCLE_HSCH4_V 0x3FF +#define LEDC_DUTY_CYCLE_HSCH4_S 10 +/* LEDC_DUTY_SCALE_HSCH4 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + high speed channel4.*/ +#define LEDC_DUTY_SCALE_HSCH4 0x000003FF +#define LEDC_DUTY_SCALE_HSCH4_M ((LEDC_DUTY_SCALE_HSCH4_V)<<(LEDC_DUTY_SCALE_HSCH4_S)) +#define LEDC_DUTY_SCALE_HSCH4_V 0x3FF +#define LEDC_DUTY_SCALE_HSCH4_S 0 + +#define LEDC_HSCH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0060) +/* LEDC_DUTY_HSCH4 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for high speed channel4.*/ +#define LEDC_DUTY_HSCH4 0x01FFFFFF +#define LEDC_DUTY_HSCH4_M ((LEDC_DUTY_HSCH4_V)<<(LEDC_DUTY_HSCH4_S)) +#define LEDC_DUTY_HSCH4_V 0x1FFFFFF +#define LEDC_DUTY_HSCH4_S 0 + +#define LEDC_HSCH5_CONF0_REG (DR_REG_LEDC_BASE + 0x0064) +/* LEDC_IDLE_LV_HSCH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when high speed channel5 is off.*/ +#define LEDC_IDLE_LV_HSCH5 (BIT(3)) +#define LEDC_IDLE_LV_HSCH5_M (BIT(3)) +#define LEDC_IDLE_LV_HSCH5_V 0x1 +#define LEDC_IDLE_LV_HSCH5_S 3 +/* LEDC_SIG_OUT_EN_HSCH5 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for high speed channel5.*/ +#define LEDC_SIG_OUT_EN_HSCH5 (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH5_M (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH5_V 0x1 +#define LEDC_SIG_OUT_EN_HSCH5_S 2 +/* LEDC_TIMER_SEL_HSCH5 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four high speed timers the two bits are used to select + one of them for high speed channel5. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ +#define LEDC_TIMER_SEL_HSCH5 0x00000003 +#define LEDC_TIMER_SEL_HSCH5_M ((LEDC_TIMER_SEL_HSCH5_V)<<(LEDC_TIMER_SEL_HSCH5_S)) +#define LEDC_TIMER_SEL_HSCH5_V 0x3 +#define LEDC_TIMER_SEL_HSCH5_S 0 + +#define LEDC_HSCH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x0068) +/* LEDC_HPOINT_HSCH5 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when htimerx(x=[0 3]) selected + by high speed channel5 has reached reg_hpoint_hsch5[19:0]*/ +#define LEDC_HPOINT_HSCH5 0x000FFFFF +#define LEDC_HPOINT_HSCH5_M ((LEDC_HPOINT_HSCH5_V)<<(LEDC_HPOINT_HSCH5_S)) +#define LEDC_HPOINT_HSCH5_V 0xFFFFF +#define LEDC_HPOINT_HSCH5_S 0 + +#define LEDC_HSCH5_DUTY_REG (DR_REG_LEDC_BASE + 0x006C) +/* LEDC_DUTY_HSCH5 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When hstimerx(x=[0 + 3]) choosed by high speed channel5 has reached reg_lpoint_hsch5 the output signal changes to low. reg_lpoint_hsch5=(reg_hpoint_hsch5[19:0]+reg_duty_hsch5[24:4]) (1) reg_lpoint_hsch5=(reg_hpoint_hsch5[19:0]+reg_duty_hsch5[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_HSCH5 0x01FFFFFF +#define LEDC_DUTY_HSCH5_M ((LEDC_DUTY_HSCH5_V)<<(LEDC_DUTY_HSCH5_S)) +#define LEDC_DUTY_HSCH5_V 0x1FFFFFF +#define LEDC_DUTY_HSCH5_S 0 + +#define LEDC_HSCH5_CONF1_REG (DR_REG_LEDC_BASE + 0x0070) +/* LEDC_DUTY_START_HSCH5 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch5 reg_duty_cycle_hsch5 and reg_duty_scale_hsch5 + has been configured. these register won't take effect until set reg_duty_start_hsch5. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_HSCH5 (BIT(31)) +#define LEDC_DUTY_START_HSCH5_M (BIT(31)) +#define LEDC_DUTY_START_HSCH5_V 0x1 +#define LEDC_DUTY_START_HSCH5_S 31 +/* LEDC_DUTY_INC_HSCH5 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for high speed channel5.*/ +#define LEDC_DUTY_INC_HSCH5 (BIT(30)) +#define LEDC_DUTY_INC_HSCH5_M (BIT(30)) +#define LEDC_DUTY_INC_HSCH5_V 0x1 +#define LEDC_DUTY_INC_HSCH5_S 30 +/* LEDC_DUTY_NUM_HSCH5 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for high speed channel5.*/ +#define LEDC_DUTY_NUM_HSCH5 0x000003FF +#define LEDC_DUTY_NUM_HSCH5_M ((LEDC_DUTY_NUM_HSCH5_V)<<(LEDC_DUTY_NUM_HSCH5_S)) +#define LEDC_DUTY_NUM_HSCH5_V 0x3FF +#define LEDC_DUTY_NUM_HSCH5_S 20 +/* LEDC_DUTY_CYCLE_HSCH5 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_hsch5 cycles for high speed channel5.*/ +#define LEDC_DUTY_CYCLE_HSCH5 0x000003FF +#define LEDC_DUTY_CYCLE_HSCH5_M ((LEDC_DUTY_CYCLE_HSCH5_V)<<(LEDC_DUTY_CYCLE_HSCH5_S)) +#define LEDC_DUTY_CYCLE_HSCH5_V 0x3FF +#define LEDC_DUTY_CYCLE_HSCH5_S 10 +/* LEDC_DUTY_SCALE_HSCH5 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + high speed channel5.*/ +#define LEDC_DUTY_SCALE_HSCH5 0x000003FF +#define LEDC_DUTY_SCALE_HSCH5_M ((LEDC_DUTY_SCALE_HSCH5_V)<<(LEDC_DUTY_SCALE_HSCH5_S)) +#define LEDC_DUTY_SCALE_HSCH5_V 0x3FF +#define LEDC_DUTY_SCALE_HSCH5_S 0 + +#define LEDC_HSCH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0074) +/* LEDC_DUTY_HSCH5 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for high speed channel5.*/ +#define LEDC_DUTY_HSCH5 0x01FFFFFF +#define LEDC_DUTY_HSCH5_M ((LEDC_DUTY_HSCH5_V)<<(LEDC_DUTY_HSCH5_S)) +#define LEDC_DUTY_HSCH5_V 0x1FFFFFF +#define LEDC_DUTY_HSCH5_S 0 + +#define LEDC_HSCH6_CONF0_REG (DR_REG_LEDC_BASE + 0x0078) +/* LEDC_IDLE_LV_HSCH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when high speed channel6 is off.*/ +#define LEDC_IDLE_LV_HSCH6 (BIT(3)) +#define LEDC_IDLE_LV_HSCH6_M (BIT(3)) +#define LEDC_IDLE_LV_HSCH6_V 0x1 +#define LEDC_IDLE_LV_HSCH6_S 3 +/* LEDC_SIG_OUT_EN_HSCH6 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for high speed channel6*/ +#define LEDC_SIG_OUT_EN_HSCH6 (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH6_M (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH6_V 0x1 +#define LEDC_SIG_OUT_EN_HSCH6_S 2 +/* LEDC_TIMER_SEL_HSCH6 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four high speed timers the two bits are used to select + one of them for high speed channel6. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ +#define LEDC_TIMER_SEL_HSCH6 0x00000003 +#define LEDC_TIMER_SEL_HSCH6_M ((LEDC_TIMER_SEL_HSCH6_V)<<(LEDC_TIMER_SEL_HSCH6_S)) +#define LEDC_TIMER_SEL_HSCH6_V 0x3 +#define LEDC_TIMER_SEL_HSCH6_S 0 + +#define LEDC_HSCH6_HPOINT_REG (DR_REG_LEDC_BASE + 0x007C) +/* LEDC_HPOINT_HSCH6 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when htimerx(x=[0 3]) selected + by high speed channel6 has reached reg_hpoint_hsch6[19:0]*/ +#define LEDC_HPOINT_HSCH6 0x000FFFFF +#define LEDC_HPOINT_HSCH6_M ((LEDC_HPOINT_HSCH6_V)<<(LEDC_HPOINT_HSCH6_S)) +#define LEDC_HPOINT_HSCH6_V 0xFFFFF +#define LEDC_HPOINT_HSCH6_S 0 + +#define LEDC_HSCH6_DUTY_REG (DR_REG_LEDC_BASE + 0x0080) +/* LEDC_DUTY_HSCH6 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When hstimerx(x=[0 + 3]) choosed by high speed channel6 has reached reg_lpoint_hsch6 the output signal changes to low. reg_lpoint_hsch6=(reg_hpoint_hsch6[19:0]+reg_duty_hsch6[24:4]) (1) reg_lpoint_hsch6=(reg_hpoint_hsch6[19:0]+reg_duty_hsch6[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_HSCH6 0x01FFFFFF +#define LEDC_DUTY_HSCH6_M ((LEDC_DUTY_HSCH6_V)<<(LEDC_DUTY_HSCH6_S)) +#define LEDC_DUTY_HSCH6_V 0x1FFFFFF +#define LEDC_DUTY_HSCH6_S 0 + +#define LEDC_HSCH6_CONF1_REG (DR_REG_LEDC_BASE + 0x0084) +/* LEDC_DUTY_START_HSCH6 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 + has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_HSCH6 (BIT(31)) +#define LEDC_DUTY_START_HSCH6_M (BIT(31)) +#define LEDC_DUTY_START_HSCH6_V 0x1 +#define LEDC_DUTY_START_HSCH6_S 31 +/* LEDC_DUTY_INC_HSCH6 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for high speed channel6.*/ +#define LEDC_DUTY_INC_HSCH6 (BIT(30)) +#define LEDC_DUTY_INC_HSCH6_M (BIT(30)) +#define LEDC_DUTY_INC_HSCH6_V 0x1 +#define LEDC_DUTY_INC_HSCH6_S 30 +/* LEDC_DUTY_NUM_HSCH6 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for high speed channel6.*/ +#define LEDC_DUTY_NUM_HSCH6 0x000003FF +#define LEDC_DUTY_NUM_HSCH6_M ((LEDC_DUTY_NUM_HSCH6_V)<<(LEDC_DUTY_NUM_HSCH6_S)) +#define LEDC_DUTY_NUM_HSCH6_V 0x3FF +#define LEDC_DUTY_NUM_HSCH6_S 20 +/* LEDC_DUTY_CYCLE_HSCH6 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_hsch6 cycles for high speed channel6.*/ +#define LEDC_DUTY_CYCLE_HSCH6 0x000003FF +#define LEDC_DUTY_CYCLE_HSCH6_M ((LEDC_DUTY_CYCLE_HSCH6_V)<<(LEDC_DUTY_CYCLE_HSCH6_S)) +#define LEDC_DUTY_CYCLE_HSCH6_V 0x3FF +#define LEDC_DUTY_CYCLE_HSCH6_S 10 +/* LEDC_DUTY_SCALE_HSCH6 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + high speed channel6.*/ +#define LEDC_DUTY_SCALE_HSCH6 0x000003FF +#define LEDC_DUTY_SCALE_HSCH6_M ((LEDC_DUTY_SCALE_HSCH6_V)<<(LEDC_DUTY_SCALE_HSCH6_S)) +#define LEDC_DUTY_SCALE_HSCH6_V 0x3FF +#define LEDC_DUTY_SCALE_HSCH6_S 0 + +#define LEDC_HSCH6_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0088) +/* LEDC_DUTY_HSCH6 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for high speed channel6.*/ +#define LEDC_DUTY_HSCH6 0x01FFFFFF +#define LEDC_DUTY_HSCH6_M ((LEDC_DUTY_HSCH6_V)<<(LEDC_DUTY_HSCH6_S)) +#define LEDC_DUTY_HSCH6_V 0x1FFFFFF +#define LEDC_DUTY_HSCH6_S 0 + +#define LEDC_HSCH7_CONF0_REG (DR_REG_LEDC_BASE + 0x008C) +/* LEDC_IDLE_LV_HSCH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when high speed channel7 is off.*/ +#define LEDC_IDLE_LV_HSCH7 (BIT(3)) +#define LEDC_IDLE_LV_HSCH7_M (BIT(3)) +#define LEDC_IDLE_LV_HSCH7_V 0x1 +#define LEDC_IDLE_LV_HSCH7_S 3 +/* LEDC_SIG_OUT_EN_HSCH7 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for high speed channel7.*/ +#define LEDC_SIG_OUT_EN_HSCH7 (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH7_M (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH7_V 0x1 +#define LEDC_SIG_OUT_EN_HSCH7_S 2 +/* LEDC_TIMER_SEL_HSCH7 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four high speed timers the two bits are used to select + one of them for high speed channel7. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ +#define LEDC_TIMER_SEL_HSCH7 0x00000003 +#define LEDC_TIMER_SEL_HSCH7_M ((LEDC_TIMER_SEL_HSCH7_V)<<(LEDC_TIMER_SEL_HSCH7_S)) +#define LEDC_TIMER_SEL_HSCH7_V 0x3 +#define LEDC_TIMER_SEL_HSCH7_S 0 + +#define LEDC_HSCH7_HPOINT_REG (DR_REG_LEDC_BASE + 0x0090) +/* LEDC_HPOINT_HSCH7 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when htimerx(x=[0 3]) selected + by high speed channel7 has reached reg_hpoint_hsch7[19:0]*/ +#define LEDC_HPOINT_HSCH7 0x000FFFFF +#define LEDC_HPOINT_HSCH7_M ((LEDC_HPOINT_HSCH7_V)<<(LEDC_HPOINT_HSCH7_S)) +#define LEDC_HPOINT_HSCH7_V 0xFFFFF +#define LEDC_HPOINT_HSCH7_S 0 + +#define LEDC_HSCH7_DUTY_REG (DR_REG_LEDC_BASE + 0x0094) +/* LEDC_DUTY_HSCH7 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When hstimerx(x=[0 + 3]) choosed by high speed channel7 has reached reg_lpoint_hsch7 the output signal changes to low. reg_lpoint_hsch7=(reg_hpoint_hsch7[19:0]+reg_duty_hsch7[24:4]) (1) reg_lpoint_hsch7=(reg_hpoint_hsch7[19:0]+reg_duty_hsch7[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_HSCH7 0x01FFFFFF +#define LEDC_DUTY_HSCH7_M ((LEDC_DUTY_HSCH7_V)<<(LEDC_DUTY_HSCH7_S)) +#define LEDC_DUTY_HSCH7_V 0x1FFFFFF +#define LEDC_DUTY_HSCH7_S 0 + +#define LEDC_HSCH7_CONF1_REG (DR_REG_LEDC_BASE + 0x0098) +/* LEDC_DUTY_START_HSCH7 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 + has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_HSCH7 (BIT(31)) +#define LEDC_DUTY_START_HSCH7_M (BIT(31)) +#define LEDC_DUTY_START_HSCH7_V 0x1 +#define LEDC_DUTY_START_HSCH7_S 31 +/* LEDC_DUTY_INC_HSCH7 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for high speed channel6.*/ +#define LEDC_DUTY_INC_HSCH7 (BIT(30)) +#define LEDC_DUTY_INC_HSCH7_M (BIT(30)) +#define LEDC_DUTY_INC_HSCH7_V 0x1 +#define LEDC_DUTY_INC_HSCH7_S 30 +/* LEDC_DUTY_NUM_HSCH7 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for high speed channel6.*/ +#define LEDC_DUTY_NUM_HSCH7 0x000003FF +#define LEDC_DUTY_NUM_HSCH7_M ((LEDC_DUTY_NUM_HSCH7_V)<<(LEDC_DUTY_NUM_HSCH7_S)) +#define LEDC_DUTY_NUM_HSCH7_V 0x3FF +#define LEDC_DUTY_NUM_HSCH7_S 20 +/* LEDC_DUTY_CYCLE_HSCH7 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_hsch7 cycles for high speed channel7.*/ +#define LEDC_DUTY_CYCLE_HSCH7 0x000003FF +#define LEDC_DUTY_CYCLE_HSCH7_M ((LEDC_DUTY_CYCLE_HSCH7_V)<<(LEDC_DUTY_CYCLE_HSCH7_S)) +#define LEDC_DUTY_CYCLE_HSCH7_V 0x3FF +#define LEDC_DUTY_CYCLE_HSCH7_S 10 +/* LEDC_DUTY_SCALE_HSCH7 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + high speed channel7.*/ +#define LEDC_DUTY_SCALE_HSCH7 0x000003FF +#define LEDC_DUTY_SCALE_HSCH7_M ((LEDC_DUTY_SCALE_HSCH7_V)<<(LEDC_DUTY_SCALE_HSCH7_S)) +#define LEDC_DUTY_SCALE_HSCH7_V 0x3FF +#define LEDC_DUTY_SCALE_HSCH7_S 0 + +#define LEDC_HSCH7_DUTY_R_REG (DR_REG_LEDC_BASE + 0x009C) +/* LEDC_DUTY_HSCH7 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for high speed channel7.*/ +#define LEDC_DUTY_HSCH7 0x01FFFFFF +#define LEDC_DUTY_HSCH7_M ((LEDC_DUTY_HSCH7_V)<<(LEDC_DUTY_HSCH7_S)) +#define LEDC_DUTY_HSCH7_V 0x1FFFFFF +#define LEDC_DUTY_HSCH7_S 0 + +#define LEDC_LSCH0_CONF0_REG (DR_REG_LEDC_BASE + 0x00A0) +/* LEDC_PARA_UP_LSCH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This bit is used to update register LEDC_LSCH0_HPOINT and LEDC_LSCH0_DUTY + for low speed channel0.*/ +#define LEDC_PARA_UP_LSCH0 (BIT(4)) +#define LEDC_PARA_UP_LSCH0_M (BIT(4)) +#define LEDC_PARA_UP_LSCH0_V 0x1 +#define LEDC_PARA_UP_LSCH0_S 4 +/* LEDC_IDLE_LV_LSCH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when low speed channel0 is off.*/ +#define LEDC_IDLE_LV_LSCH0 (BIT(3)) +#define LEDC_IDLE_LV_LSCH0_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH0_V 0x1 +#define LEDC_IDLE_LV_LSCH0_S 3 +/* LEDC_SIG_OUT_EN_LSCH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for low speed channel0.*/ +#define LEDC_SIG_OUT_EN_LSCH0 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH0_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH0_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH0_S 2 +/* LEDC_TIMER_SEL_LSCH0 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four low speed timers the two bits are used to select + one of them for low speed channel0. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ +#define LEDC_TIMER_SEL_LSCH0 0x00000003 +#define LEDC_TIMER_SEL_LSCH0_M ((LEDC_TIMER_SEL_LSCH0_V)<<(LEDC_TIMER_SEL_LSCH0_S)) +#define LEDC_TIMER_SEL_LSCH0_V 0x3 +#define LEDC_TIMER_SEL_LSCH0_S 0 + +#define LEDC_LSCH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x00A4) +/* LEDC_HPOINT_LSCH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when lstimerx(x=[0 3]) selected + by low speed channel0 has reached reg_hpoint_lsch0[19:0]*/ +#define LEDC_HPOINT_LSCH0 0x000FFFFF +#define LEDC_HPOINT_LSCH0_M ((LEDC_HPOINT_LSCH0_V)<<(LEDC_HPOINT_LSCH0_S)) +#define LEDC_HPOINT_LSCH0_V 0xFFFFF +#define LEDC_HPOINT_LSCH0_S 0 + +#define LEDC_LSCH0_DUTY_REG (DR_REG_LEDC_BASE + 0x00A8) +/* LEDC_DUTY_LSCH0 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When lstimerx(x=[0 + 3]) choosed by low speed channel0 has reached reg_lpoint_lsch0 the output signal changes to low. reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4]) (1) reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_LSCH0 0x01FFFFFF +#define LEDC_DUTY_LSCH0_M ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S)) +#define LEDC_DUTY_LSCH0_V 0x1FFFFFF +#define LEDC_DUTY_LSCH0_S 0 + +#define LEDC_LSCH0_CONF1_REG (DR_REG_LEDC_BASE + 0x00AC) +/* LEDC_DUTY_START_LSCH0 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 + has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_LSCH0 (BIT(31)) +#define LEDC_DUTY_START_LSCH0_M (BIT(31)) +#define LEDC_DUTY_START_LSCH0_V 0x1 +#define LEDC_DUTY_START_LSCH0_S 31 +/* LEDC_DUTY_INC_LSCH0 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for low speed channel6.*/ +#define LEDC_DUTY_INC_LSCH0 (BIT(30)) +#define LEDC_DUTY_INC_LSCH0_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH0_V 0x1 +#define LEDC_DUTY_INC_LSCH0_S 30 +/* LEDC_DUTY_NUM_LSCH0 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for low speed channel6.*/ +#define LEDC_DUTY_NUM_LSCH0 0x000003FF +#define LEDC_DUTY_NUM_LSCH0_M ((LEDC_DUTY_NUM_LSCH0_V)<<(LEDC_DUTY_NUM_LSCH0_S)) +#define LEDC_DUTY_NUM_LSCH0_V 0x3FF +#define LEDC_DUTY_NUM_LSCH0_S 20 +/* LEDC_DUTY_CYCLE_LSCH0 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_lsch0 cycles for low speed channel0.*/ +#define LEDC_DUTY_CYCLE_LSCH0 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH0_M ((LEDC_DUTY_CYCLE_LSCH0_V)<<(LEDC_DUTY_CYCLE_LSCH0_S)) +#define LEDC_DUTY_CYCLE_LSCH0_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH0_S 10 +/* LEDC_DUTY_SCALE_LSCH0 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + low speed channel0.*/ +#define LEDC_DUTY_SCALE_LSCH0 0x000003FF +#define LEDC_DUTY_SCALE_LSCH0_M ((LEDC_DUTY_SCALE_LSCH0_V)<<(LEDC_DUTY_SCALE_LSCH0_S)) +#define LEDC_DUTY_SCALE_LSCH0_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH0_S 0 + +#define LEDC_LSCH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00B0) +/* LEDC_DUTY_LSCH0 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for low speed channel0.*/ +#define LEDC_DUTY_LSCH0 0x01FFFFFF +#define LEDC_DUTY_LSCH0_M ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S)) +#define LEDC_DUTY_LSCH0_V 0x1FFFFFF +#define LEDC_DUTY_LSCH0_S 0 + +#define LEDC_LSCH1_CONF0_REG (DR_REG_LEDC_BASE + 0x00B4) +/* LEDC_PARA_UP_LSCH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This bit is used to update register LEDC_LSCH1_HPOINT and LEDC_LSCH1_DUTY + for low speed channel1.*/ +#define LEDC_PARA_UP_LSCH1 (BIT(4)) +#define LEDC_PARA_UP_LSCH1_M (BIT(4)) +#define LEDC_PARA_UP_LSCH1_V 0x1 +#define LEDC_PARA_UP_LSCH1_S 4 +/* LEDC_IDLE_LV_LSCH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when low speed channel1 is off.*/ +#define LEDC_IDLE_LV_LSCH1 (BIT(3)) +#define LEDC_IDLE_LV_LSCH1_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH1_V 0x1 +#define LEDC_IDLE_LV_LSCH1_S 3 +/* LEDC_SIG_OUT_EN_LSCH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for low speed channel1.*/ +#define LEDC_SIG_OUT_EN_LSCH1 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH1_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH1_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH1_S 2 +/* LEDC_TIMER_SEL_LSCH1 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four low speed timers the two bits are used to select + one of them for low speed channel1. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ +#define LEDC_TIMER_SEL_LSCH1 0x00000003 +#define LEDC_TIMER_SEL_LSCH1_M ((LEDC_TIMER_SEL_LSCH1_V)<<(LEDC_TIMER_SEL_LSCH1_S)) +#define LEDC_TIMER_SEL_LSCH1_V 0x3 +#define LEDC_TIMER_SEL_LSCH1_S 0 + +#define LEDC_LSCH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x00B8) +/* LEDC_HPOINT_LSCH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when lstimerx(x=[0 3]) selected + by low speed channel1 has reached reg_hpoint_lsch1[19:0]*/ +#define LEDC_HPOINT_LSCH1 0x000FFFFF +#define LEDC_HPOINT_LSCH1_M ((LEDC_HPOINT_LSCH1_V)<<(LEDC_HPOINT_LSCH1_S)) +#define LEDC_HPOINT_LSCH1_V 0xFFFFF +#define LEDC_HPOINT_LSCH1_S 0 + +#define LEDC_LSCH1_DUTY_REG (DR_REG_LEDC_BASE + 0x00BC) +/* LEDC_DUTY_LSCH1 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When lstimerx(x=[0 + 3]) choosed by low speed channel1 has reached reg_lpoint_lsch1 the output signal changes to low. reg_lpoint_lsch1=(reg_hpoint_lsch1[19:0]+reg_duty_lsch1[24:4]) (1) reg_lpoint_lsch1=(reg_hpoint_lsch1[19:0]+reg_duty_lsch1[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_LSCH1 0x01FFFFFF +#define LEDC_DUTY_LSCH1_M ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S)) +#define LEDC_DUTY_LSCH1_V 0x1FFFFFF +#define LEDC_DUTY_LSCH1_S 0 + +#define LEDC_LSCH1_CONF1_REG (DR_REG_LEDC_BASE + 0x00C0) +/* LEDC_DUTY_START_LSCH1 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 + has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_LSCH1 (BIT(31)) +#define LEDC_DUTY_START_LSCH1_M (BIT(31)) +#define LEDC_DUTY_START_LSCH1_V 0x1 +#define LEDC_DUTY_START_LSCH1_S 31 +/* LEDC_DUTY_INC_LSCH1 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for low speed channel1.*/ +#define LEDC_DUTY_INC_LSCH1 (BIT(30)) +#define LEDC_DUTY_INC_LSCH1_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH1_V 0x1 +#define LEDC_DUTY_INC_LSCH1_S 30 +/* LEDC_DUTY_NUM_LSCH1 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for low speed channel1.*/ +#define LEDC_DUTY_NUM_LSCH1 0x000003FF +#define LEDC_DUTY_NUM_LSCH1_M ((LEDC_DUTY_NUM_LSCH1_V)<<(LEDC_DUTY_NUM_LSCH1_S)) +#define LEDC_DUTY_NUM_LSCH1_V 0x3FF +#define LEDC_DUTY_NUM_LSCH1_S 20 +/* LEDC_DUTY_CYCLE_LSCH1 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_lsch1 cycles for low speed channel1.*/ +#define LEDC_DUTY_CYCLE_LSCH1 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH1_M ((LEDC_DUTY_CYCLE_LSCH1_V)<<(LEDC_DUTY_CYCLE_LSCH1_S)) +#define LEDC_DUTY_CYCLE_LSCH1_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH1_S 10 +/* LEDC_DUTY_SCALE_LSCH1 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + low speed channel1.*/ +#define LEDC_DUTY_SCALE_LSCH1 0x000003FF +#define LEDC_DUTY_SCALE_LSCH1_M ((LEDC_DUTY_SCALE_LSCH1_V)<<(LEDC_DUTY_SCALE_LSCH1_S)) +#define LEDC_DUTY_SCALE_LSCH1_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH1_S 0 + +#define LEDC_LSCH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00C4) +/* LEDC_DUTY_LSCH1 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for low speed channel1.*/ +#define LEDC_DUTY_LSCH1 0x01FFFFFF +#define LEDC_DUTY_LSCH1_M ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S)) +#define LEDC_DUTY_LSCH1_V 0x1FFFFFF +#define LEDC_DUTY_LSCH1_S 0 + +#define LEDC_LSCH2_CONF0_REG (DR_REG_LEDC_BASE + 0x00C8) +/* LEDC_PARA_UP_LSCH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This bit is used to update register LEDC_LSCH2_HPOINT and LEDC_LSCH2_DUTY + for low speed channel2.*/ +#define LEDC_PARA_UP_LSCH2 (BIT(4)) +#define LEDC_PARA_UP_LSCH2_M (BIT(4)) +#define LEDC_PARA_UP_LSCH2_V 0x1 +#define LEDC_PARA_UP_LSCH2_S 4 +/* LEDC_IDLE_LV_LSCH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when low speed channel2 is off.*/ +#define LEDC_IDLE_LV_LSCH2 (BIT(3)) +#define LEDC_IDLE_LV_LSCH2_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH2_V 0x1 +#define LEDC_IDLE_LV_LSCH2_S 3 +/* LEDC_SIG_OUT_EN_LSCH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for low speed channel2.*/ +#define LEDC_SIG_OUT_EN_LSCH2 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH2_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH2_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH2_S 2 +/* LEDC_TIMER_SEL_LSCH2 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four low speed timers the two bits are used to select + one of them for low speed channel2. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ +#define LEDC_TIMER_SEL_LSCH2 0x00000003 +#define LEDC_TIMER_SEL_LSCH2_M ((LEDC_TIMER_SEL_LSCH2_V)<<(LEDC_TIMER_SEL_LSCH2_S)) +#define LEDC_TIMER_SEL_LSCH2_V 0x3 +#define LEDC_TIMER_SEL_LSCH2_S 0 + +#define LEDC_LSCH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x00CC) +/* LEDC_HPOINT_LSCH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when lstimerx(x=[0 3]) selected + by low speed channel2 has reached reg_hpoint_lsch2[19:0]*/ +#define LEDC_HPOINT_LSCH2 0x000FFFFF +#define LEDC_HPOINT_LSCH2_M ((LEDC_HPOINT_LSCH2_V)<<(LEDC_HPOINT_LSCH2_S)) +#define LEDC_HPOINT_LSCH2_V 0xFFFFF +#define LEDC_HPOINT_LSCH2_S 0 + +#define LEDC_LSCH2_DUTY_REG (DR_REG_LEDC_BASE + 0x00D0) +/* LEDC_DUTY_LSCH2 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When lstimerx(x=[0 + 3]) choosed by low speed channel2 has reached reg_lpoint_lsch2 the output signal changes to low. reg_lpoint_lsch2=(reg_hpoint_lsch2[19:0]+reg_duty_lsch2[24:4]) (1) reg_lpoint_lsch2=(reg_hpoint_lsch2[19:0]+reg_duty_lsch2[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_LSCH2 0x01FFFFFF +#define LEDC_DUTY_LSCH2_M ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S)) +#define LEDC_DUTY_LSCH2_V 0x1FFFFFF +#define LEDC_DUTY_LSCH2_S 0 + +#define LEDC_LSCH2_CONF1_REG (DR_REG_LEDC_BASE + 0x00D4) +/* LEDC_DUTY_START_LSCH2 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch2 reg_duty_cycle_hsch2 and reg_duty_scale_hsch2 + has been configured. these register won't take effect until set reg_duty_start_hsch2. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_LSCH2 (BIT(31)) +#define LEDC_DUTY_START_LSCH2_M (BIT(31)) +#define LEDC_DUTY_START_LSCH2_V 0x1 +#define LEDC_DUTY_START_LSCH2_S 31 +/* LEDC_DUTY_INC_LSCH2 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for low speed channel2.*/ +#define LEDC_DUTY_INC_LSCH2 (BIT(30)) +#define LEDC_DUTY_INC_LSCH2_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH2_V 0x1 +#define LEDC_DUTY_INC_LSCH2_S 30 +/* LEDC_DUTY_NUM_LSCH2 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for low speed channel2.*/ +#define LEDC_DUTY_NUM_LSCH2 0x000003FF +#define LEDC_DUTY_NUM_LSCH2_M ((LEDC_DUTY_NUM_LSCH2_V)<<(LEDC_DUTY_NUM_LSCH2_S)) +#define LEDC_DUTY_NUM_LSCH2_V 0x3FF +#define LEDC_DUTY_NUM_LSCH2_S 20 +/* LEDC_DUTY_CYCLE_LSCH2 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_lsch2 cycles for low speed channel2.*/ +#define LEDC_DUTY_CYCLE_LSCH2 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH2_M ((LEDC_DUTY_CYCLE_LSCH2_V)<<(LEDC_DUTY_CYCLE_LSCH2_S)) +#define LEDC_DUTY_CYCLE_LSCH2_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH2_S 10 +/* LEDC_DUTY_SCALE_LSCH2 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + low speed channel2.*/ +#define LEDC_DUTY_SCALE_LSCH2 0x000003FF +#define LEDC_DUTY_SCALE_LSCH2_M ((LEDC_DUTY_SCALE_LSCH2_V)<<(LEDC_DUTY_SCALE_LSCH2_S)) +#define LEDC_DUTY_SCALE_LSCH2_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH2_S 0 + +#define LEDC_LSCH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00D8) +/* LEDC_DUTY_LSCH2 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for low speed channel2.*/ +#define LEDC_DUTY_LSCH2 0x01FFFFFF +#define LEDC_DUTY_LSCH2_M ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S)) +#define LEDC_DUTY_LSCH2_V 0x1FFFFFF +#define LEDC_DUTY_LSCH2_S 0 + +#define LEDC_LSCH3_CONF0_REG (DR_REG_LEDC_BASE + 0x00DC) +/* LEDC_PARA_UP_LSCH3 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This bit is used to update register LEDC_LSCH3_HPOINT and LEDC_LSCH3_DUTY + for low speed channel3.*/ +#define LEDC_PARA_UP_LSCH3 (BIT(4)) +#define LEDC_PARA_UP_LSCH3_M (BIT(4)) +#define LEDC_PARA_UP_LSCH3_V 0x1 +#define LEDC_PARA_UP_LSCH3_S 4 +/* LEDC_IDLE_LV_LSCH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when low speed channel3 is off.*/ +#define LEDC_IDLE_LV_LSCH3 (BIT(3)) +#define LEDC_IDLE_LV_LSCH3_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH3_V 0x1 +#define LEDC_IDLE_LV_LSCH3_S 3 +/* LEDC_SIG_OUT_EN_LSCH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for low speed channel3.*/ +#define LEDC_SIG_OUT_EN_LSCH3 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH3_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH3_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH3_S 2 +/* LEDC_TIMER_SEL_LSCH3 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four low speed timers the two bits are used to select + one of them for low speed channel3. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ +#define LEDC_TIMER_SEL_LSCH3 0x00000003 +#define LEDC_TIMER_SEL_LSCH3_M ((LEDC_TIMER_SEL_LSCH3_V)<<(LEDC_TIMER_SEL_LSCH3_S)) +#define LEDC_TIMER_SEL_LSCH3_V 0x3 +#define LEDC_TIMER_SEL_LSCH3_S 0 + +#define LEDC_LSCH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x00E0) +/* LEDC_HPOINT_LSCH3 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when lstimerx(x=[0 3]) selected + by low speed channel3 has reached reg_hpoint_lsch3[19:0]*/ +#define LEDC_HPOINT_LSCH3 0x000FFFFF +#define LEDC_HPOINT_LSCH3_M ((LEDC_HPOINT_LSCH3_V)<<(LEDC_HPOINT_LSCH3_S)) +#define LEDC_HPOINT_LSCH3_V 0xFFFFF +#define LEDC_HPOINT_LSCH3_S 0 + +#define LEDC_LSCH3_DUTY_REG (DR_REG_LEDC_BASE + 0x00E4) +/* LEDC_DUTY_LSCH3 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When lstimerx(x=[0 + 3]) choosed by low speed channel3 has reached reg_lpoint_lsch3 the output signal changes to low. reg_lpoint_lsch3=(reg_hpoint_lsch3[19:0]+reg_duty_lsch3[24:4]) (1) reg_lpoint_lsch3=(reg_hpoint_lsch3[19:0]+reg_duty_lsch3[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_LSCH3 0x01FFFFFF +#define LEDC_DUTY_LSCH3_M ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S)) +#define LEDC_DUTY_LSCH3_V 0x1FFFFFF +#define LEDC_DUTY_LSCH3_S 0 + +#define LEDC_LSCH3_CONF1_REG (DR_REG_LEDC_BASE + 0x00E8) +/* LEDC_DUTY_START_LSCH3 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch3 reg_duty_cycle_hsch3 and reg_duty_scale_hsch3 + has been configured. these register won't take effect until set reg_duty_start_hsch3. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_LSCH3 (BIT(31)) +#define LEDC_DUTY_START_LSCH3_M (BIT(31)) +#define LEDC_DUTY_START_LSCH3_V 0x1 +#define LEDC_DUTY_START_LSCH3_S 31 +/* LEDC_DUTY_INC_LSCH3 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for low speed channel3.*/ +#define LEDC_DUTY_INC_LSCH3 (BIT(30)) +#define LEDC_DUTY_INC_LSCH3_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH3_V 0x1 +#define LEDC_DUTY_INC_LSCH3_S 30 +/* LEDC_DUTY_NUM_LSCH3 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for low speed channel3.*/ +#define LEDC_DUTY_NUM_LSCH3 0x000003FF +#define LEDC_DUTY_NUM_LSCH3_M ((LEDC_DUTY_NUM_LSCH3_V)<<(LEDC_DUTY_NUM_LSCH3_S)) +#define LEDC_DUTY_NUM_LSCH3_V 0x3FF +#define LEDC_DUTY_NUM_LSCH3_S 20 +/* LEDC_DUTY_CYCLE_LSCH3 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_lsch3 cycles for low speed channel3.*/ +#define LEDC_DUTY_CYCLE_LSCH3 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH3_M ((LEDC_DUTY_CYCLE_LSCH3_V)<<(LEDC_DUTY_CYCLE_LSCH3_S)) +#define LEDC_DUTY_CYCLE_LSCH3_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH3_S 10 +/* LEDC_DUTY_SCALE_LSCH3 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + low speed channel3.*/ +#define LEDC_DUTY_SCALE_LSCH3 0x000003FF +#define LEDC_DUTY_SCALE_LSCH3_M ((LEDC_DUTY_SCALE_LSCH3_V)<<(LEDC_DUTY_SCALE_LSCH3_S)) +#define LEDC_DUTY_SCALE_LSCH3_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH3_S 0 + +#define LEDC_LSCH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00EC) +/* LEDC_DUTY_LSCH3 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for low speed channel3.*/ +#define LEDC_DUTY_LSCH3 0x01FFFFFF +#define LEDC_DUTY_LSCH3_M ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S)) +#define LEDC_DUTY_LSCH3_V 0x1FFFFFF +#define LEDC_DUTY_LSCH3_S 0 + +#define LEDC_LSCH4_CONF0_REG (DR_REG_LEDC_BASE + 0x00F0) +/* LEDC_PARA_UP_LSCH4 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This bit is used to update register LEDC_LSCH4_HPOINT and LEDC_LSCH4_DUTY + for low speed channel4.*/ +#define LEDC_PARA_UP_LSCH4 (BIT(4)) +#define LEDC_PARA_UP_LSCH4_M (BIT(4)) +#define LEDC_PARA_UP_LSCH4_V 0x1 +#define LEDC_PARA_UP_LSCH4_S 4 +/* LEDC_IDLE_LV_LSCH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when low speed channel4 is off.*/ +#define LEDC_IDLE_LV_LSCH4 (BIT(3)) +#define LEDC_IDLE_LV_LSCH4_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH4_V 0x1 +#define LEDC_IDLE_LV_LSCH4_S 3 +/* LEDC_SIG_OUT_EN_LSCH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for low speed channel4.*/ +#define LEDC_SIG_OUT_EN_LSCH4 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH4_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH4_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH4_S 2 +/* LEDC_TIMER_SEL_LSCH4 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four low speed timers the two bits are used to select + one of them for low speed channel4. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ +#define LEDC_TIMER_SEL_LSCH4 0x00000003 +#define LEDC_TIMER_SEL_LSCH4_M ((LEDC_TIMER_SEL_LSCH4_V)<<(LEDC_TIMER_SEL_LSCH4_S)) +#define LEDC_TIMER_SEL_LSCH4_V 0x3 +#define LEDC_TIMER_SEL_LSCH4_S 0 + +#define LEDC_LSCH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x00F4) +/* LEDC_HPOINT_LSCH4 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when lstimerx(x=[0 3]) selected + by low speed channel4 has reached reg_hpoint_lsch4[19:0]*/ +#define LEDC_HPOINT_LSCH4 0x000FFFFF +#define LEDC_HPOINT_LSCH4_M ((LEDC_HPOINT_LSCH4_V)<<(LEDC_HPOINT_LSCH4_S)) +#define LEDC_HPOINT_LSCH4_V 0xFFFFF +#define LEDC_HPOINT_LSCH4_S 0 + +#define LEDC_LSCH4_DUTY_REG (DR_REG_LEDC_BASE + 0x00F8) +/* LEDC_DUTY_LSCH4 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When lstimerx(x=[0 + 3]) choosed by low speed channel4 has reached reg_lpoint_lsch4 the output signal changes to low. reg_lpoint_lsch4=(reg_hpoint_lsch4[19:0]+reg_duty_lsch4[24:4]) (1) reg_lpoint_lsch4=(reg_hpoint_lsch4[19:0]+reg_duty_lsch4[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_LSCH4 0x01FFFFFF +#define LEDC_DUTY_LSCH4_M ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S)) +#define LEDC_DUTY_LSCH4_V 0x1FFFFFF +#define LEDC_DUTY_LSCH4_S 0 + +#define LEDC_LSCH4_CONF1_REG (DR_REG_LEDC_BASE + 0x00FC) +/* LEDC_DUTY_START_LSCH4 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch4 reg_duty_cycle_hsch4 and reg_duty_scale_hsch4 + has been configured. these register won't take effect until set reg_duty_start_hsch4. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_LSCH4 (BIT(31)) +#define LEDC_DUTY_START_LSCH4_M (BIT(31)) +#define LEDC_DUTY_START_LSCH4_V 0x1 +#define LEDC_DUTY_START_LSCH4_S 31 +/* LEDC_DUTY_INC_LSCH4 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for low speed channel4.*/ +#define LEDC_DUTY_INC_LSCH4 (BIT(30)) +#define LEDC_DUTY_INC_LSCH4_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH4_V 0x1 +#define LEDC_DUTY_INC_LSCH4_S 30 +/* LEDC_DUTY_NUM_LSCH4 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for low speed channel4.*/ +#define LEDC_DUTY_NUM_LSCH4 0x000003FF +#define LEDC_DUTY_NUM_LSCH4_M ((LEDC_DUTY_NUM_LSCH4_V)<<(LEDC_DUTY_NUM_LSCH4_S)) +#define LEDC_DUTY_NUM_LSCH4_V 0x3FF +#define LEDC_DUTY_NUM_LSCH4_S 20 +/* LEDC_DUTY_CYCLE_LSCH4 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_lsch4 cycles for low speed channel4.*/ +#define LEDC_DUTY_CYCLE_LSCH4 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH4_M ((LEDC_DUTY_CYCLE_LSCH4_V)<<(LEDC_DUTY_CYCLE_LSCH4_S)) +#define LEDC_DUTY_CYCLE_LSCH4_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH4_S 10 +/* LEDC_DUTY_SCALE_LSCH4 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + low speed channel4.*/ +#define LEDC_DUTY_SCALE_LSCH4 0x000003FF +#define LEDC_DUTY_SCALE_LSCH4_M ((LEDC_DUTY_SCALE_LSCH4_V)<<(LEDC_DUTY_SCALE_LSCH4_S)) +#define LEDC_DUTY_SCALE_LSCH4_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH4_S 0 + +#define LEDC_LSCH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0100) +/* LEDC_DUTY_LSCH4 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for low speed channel4.*/ +#define LEDC_DUTY_LSCH4 0x01FFFFFF +#define LEDC_DUTY_LSCH4_M ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S)) +#define LEDC_DUTY_LSCH4_V 0x1FFFFFF +#define LEDC_DUTY_LSCH4_S 0 + +#define LEDC_LSCH5_CONF0_REG (DR_REG_LEDC_BASE + 0x0104) +/* LEDC_PARA_UP_LSCH5 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This bit is used to update register LEDC_LSCH5_HPOINT and LEDC_LSCH5_DUTY + for low speed channel5.*/ +#define LEDC_PARA_UP_LSCH5 (BIT(4)) +#define LEDC_PARA_UP_LSCH5_M (BIT(4)) +#define LEDC_PARA_UP_LSCH5_V 0x1 +#define LEDC_PARA_UP_LSCH5_S 4 +/* LEDC_IDLE_LV_LSCH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when low speed channel5 is off.*/ +#define LEDC_IDLE_LV_LSCH5 (BIT(3)) +#define LEDC_IDLE_LV_LSCH5_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH5_V 0x1 +#define LEDC_IDLE_LV_LSCH5_S 3 +/* LEDC_SIG_OUT_EN_LSCH5 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for low speed channel5.*/ +#define LEDC_SIG_OUT_EN_LSCH5 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH5_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH5_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH5_S 2 +/* LEDC_TIMER_SEL_LSCH5 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four low speed timers the two bits are used to select + one of them for low speed channel5. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ +#define LEDC_TIMER_SEL_LSCH5 0x00000003 +#define LEDC_TIMER_SEL_LSCH5_M ((LEDC_TIMER_SEL_LSCH5_V)<<(LEDC_TIMER_SEL_LSCH5_S)) +#define LEDC_TIMER_SEL_LSCH5_V 0x3 +#define LEDC_TIMER_SEL_LSCH5_S 0 + +#define LEDC_LSCH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x0108) +/* LEDC_HPOINT_LSCH5 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when lstimerx(x=[0 3]) selected + by low speed channel5 has reached reg_hpoint_lsch5[19:0]*/ +#define LEDC_HPOINT_LSCH5 0x000FFFFF +#define LEDC_HPOINT_LSCH5_M ((LEDC_HPOINT_LSCH5_V)<<(LEDC_HPOINT_LSCH5_S)) +#define LEDC_HPOINT_LSCH5_V 0xFFFFF +#define LEDC_HPOINT_LSCH5_S 0 + +#define LEDC_LSCH5_DUTY_REG (DR_REG_LEDC_BASE + 0x010C) +/* LEDC_DUTY_LSCH5 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When lstimerx(x=[0 + 3]) choosed by low speed channel5 has reached reg_lpoint_lsch5 the output signal changes to low. reg_lpoint_lsch5=(reg_hpoint_lsch5[19:0]+reg_duty_lsch5[24:4]) (1) reg_lpoint_lsch5=(reg_hpoint_lsch5[19:0]+reg_duty_lsch5[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_LSCH5 0x01FFFFFF +#define LEDC_DUTY_LSCH5_M ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S)) +#define LEDC_DUTY_LSCH5_V 0x1FFFFFF +#define LEDC_DUTY_LSCH5_S 0 + +#define LEDC_LSCH5_CONF1_REG (DR_REG_LEDC_BASE + 0x0110) +/* LEDC_DUTY_START_LSCH5 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch4 reg_duty_cycle_hsch4 and reg_duty_scale_hsch4 + has been configured. these register won't take effect until set reg_duty_start_hsch4. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_LSCH5 (BIT(31)) +#define LEDC_DUTY_START_LSCH5_M (BIT(31)) +#define LEDC_DUTY_START_LSCH5_V 0x1 +#define LEDC_DUTY_START_LSCH5_S 31 +/* LEDC_DUTY_INC_LSCH5 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for low speed channel5.*/ +#define LEDC_DUTY_INC_LSCH5 (BIT(30)) +#define LEDC_DUTY_INC_LSCH5_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH5_V 0x1 +#define LEDC_DUTY_INC_LSCH5_S 30 +/* LEDC_DUTY_NUM_LSCH5 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for low speed channel5.*/ +#define LEDC_DUTY_NUM_LSCH5 0x000003FF +#define LEDC_DUTY_NUM_LSCH5_M ((LEDC_DUTY_NUM_LSCH5_V)<<(LEDC_DUTY_NUM_LSCH5_S)) +#define LEDC_DUTY_NUM_LSCH5_V 0x3FF +#define LEDC_DUTY_NUM_LSCH5_S 20 +/* LEDC_DUTY_CYCLE_LSCH5 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_lsch5 cycles for low speed channel4.*/ +#define LEDC_DUTY_CYCLE_LSCH5 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH5_M ((LEDC_DUTY_CYCLE_LSCH5_V)<<(LEDC_DUTY_CYCLE_LSCH5_S)) +#define LEDC_DUTY_CYCLE_LSCH5_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH5_S 10 +/* LEDC_DUTY_SCALE_LSCH5 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + low speed channel5.*/ +#define LEDC_DUTY_SCALE_LSCH5 0x000003FF +#define LEDC_DUTY_SCALE_LSCH5_M ((LEDC_DUTY_SCALE_LSCH5_V)<<(LEDC_DUTY_SCALE_LSCH5_S)) +#define LEDC_DUTY_SCALE_LSCH5_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH5_S 0 + +#define LEDC_LSCH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0114) +/* LEDC_DUTY_LSCH5 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for low speed channel5.*/ +#define LEDC_DUTY_LSCH5 0x01FFFFFF +#define LEDC_DUTY_LSCH5_M ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S)) +#define LEDC_DUTY_LSCH5_V 0x1FFFFFF +#define LEDC_DUTY_LSCH5_S 0 + +#define LEDC_LSCH6_CONF0_REG (DR_REG_LEDC_BASE + 0x0118) +/* LEDC_PARA_UP_LSCH6 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This bit is used to update register LEDC_LSCH6_HPOINT and LEDC_LSCH6_DUTY + for low speed channel6.*/ +#define LEDC_PARA_UP_LSCH6 (BIT(4)) +#define LEDC_PARA_UP_LSCH6_M (BIT(4)) +#define LEDC_PARA_UP_LSCH6_V 0x1 +#define LEDC_PARA_UP_LSCH6_S 4 +/* LEDC_IDLE_LV_LSCH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when low speed channel6 is off.*/ +#define LEDC_IDLE_LV_LSCH6 (BIT(3)) +#define LEDC_IDLE_LV_LSCH6_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH6_V 0x1 +#define LEDC_IDLE_LV_LSCH6_S 3 +/* LEDC_SIG_OUT_EN_LSCH6 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for low speed channel6.*/ +#define LEDC_SIG_OUT_EN_LSCH6 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH6_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH6_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH6_S 2 +/* LEDC_TIMER_SEL_LSCH6 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four low speed timers the two bits are used to select + one of them for low speed channel6. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ +#define LEDC_TIMER_SEL_LSCH6 0x00000003 +#define LEDC_TIMER_SEL_LSCH6_M ((LEDC_TIMER_SEL_LSCH6_V)<<(LEDC_TIMER_SEL_LSCH6_S)) +#define LEDC_TIMER_SEL_LSCH6_V 0x3 +#define LEDC_TIMER_SEL_LSCH6_S 0 + +#define LEDC_LSCH6_HPOINT_REG (DR_REG_LEDC_BASE + 0x011C) +/* LEDC_HPOINT_LSCH6 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when lstimerx(x=[0 3]) selected + by low speed channel6 has reached reg_hpoint_lsch6[19:0]*/ +#define LEDC_HPOINT_LSCH6 0x000FFFFF +#define LEDC_HPOINT_LSCH6_M ((LEDC_HPOINT_LSCH6_V)<<(LEDC_HPOINT_LSCH6_S)) +#define LEDC_HPOINT_LSCH6_V 0xFFFFF +#define LEDC_HPOINT_LSCH6_S 0 + +#define LEDC_LSCH6_DUTY_REG (DR_REG_LEDC_BASE + 0x0120) +/* LEDC_DUTY_LSCH6 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When lstimerx(x=[0 + 3]) choosed by low speed channel6 has reached reg_lpoint_lsch6 the output signal changes to low. reg_lpoint_lsch6=(reg_hpoint_lsch6[19:0]+reg_duty_lsch6[24:4]) (1) reg_lpoint_lsch6=(reg_hpoint_lsch6[19:0]+reg_duty_lsch6[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_LSCH6 0x01FFFFFF +#define LEDC_DUTY_LSCH6_M ((LEDC_DUTY_LSCH6_V)<<(LEDC_DUTY_LSCH6_S)) +#define LEDC_DUTY_LSCH6_V 0x1FFFFFF +#define LEDC_DUTY_LSCH6_S 0 + +#define LEDC_LSCH6_CONF1_REG (DR_REG_LEDC_BASE + 0x0124) +/* LEDC_DUTY_START_LSCH6 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch6 reg_duty_cycle_hsch6 and reg_duty_scale_hsch6 + has been configured. these register won't take effect until set reg_duty_start_hsch6. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_LSCH6 (BIT(31)) +#define LEDC_DUTY_START_LSCH6_M (BIT(31)) +#define LEDC_DUTY_START_LSCH6_V 0x1 +#define LEDC_DUTY_START_LSCH6_S 31 +/* LEDC_DUTY_INC_LSCH6 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for low speed channel6.*/ +#define LEDC_DUTY_INC_LSCH6 (BIT(30)) +#define LEDC_DUTY_INC_LSCH6_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH6_V 0x1 +#define LEDC_DUTY_INC_LSCH6_S 30 +/* LEDC_DUTY_NUM_LSCH6 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for low speed channel6.*/ +#define LEDC_DUTY_NUM_LSCH6 0x000003FF +#define LEDC_DUTY_NUM_LSCH6_M ((LEDC_DUTY_NUM_LSCH6_V)<<(LEDC_DUTY_NUM_LSCH6_S)) +#define LEDC_DUTY_NUM_LSCH6_V 0x3FF +#define LEDC_DUTY_NUM_LSCH6_S 20 +/* LEDC_DUTY_CYCLE_LSCH6 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_lsch6 cycles for low speed channel6.*/ +#define LEDC_DUTY_CYCLE_LSCH6 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH6_M ((LEDC_DUTY_CYCLE_LSCH6_V)<<(LEDC_DUTY_CYCLE_LSCH6_S)) +#define LEDC_DUTY_CYCLE_LSCH6_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH6_S 10 +/* LEDC_DUTY_SCALE_LSCH6 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + low speed channel6.*/ +#define LEDC_DUTY_SCALE_LSCH6 0x000003FF +#define LEDC_DUTY_SCALE_LSCH6_M ((LEDC_DUTY_SCALE_LSCH6_V)<<(LEDC_DUTY_SCALE_LSCH6_S)) +#define LEDC_DUTY_SCALE_LSCH6_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH6_S 0 + +#define LEDC_LSCH6_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0128) +/* LEDC_DUTY_LSCH6 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for low speed channel6.*/ +#define LEDC_DUTY_LSCH6 0x01FFFFFF +#define LEDC_DUTY_LSCH6_M ((LEDC_DUTY_LSCH6_V)<<(LEDC_DUTY_LSCH6_S)) +#define LEDC_DUTY_LSCH6_V 0x1FFFFFF +#define LEDC_DUTY_LSCH6_S 0 + +#define LEDC_LSCH7_CONF0_REG (DR_REG_LEDC_BASE + 0x012C) +/* LEDC_PARA_UP_LSCH7 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This bit is used to update register LEDC_LSCH7_HPOINT and LEDC_LSCH7_DUTY + for low speed channel7.*/ +#define LEDC_PARA_UP_LSCH7 (BIT(4)) +#define LEDC_PARA_UP_LSCH7_M (BIT(4)) +#define LEDC_PARA_UP_LSCH7_V 0x1 +#define LEDC_PARA_UP_LSCH7_S 4 +/* LEDC_IDLE_LV_LSCH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when low speed channel7 is off.*/ +#define LEDC_IDLE_LV_LSCH7 (BIT(3)) +#define LEDC_IDLE_LV_LSCH7_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH7_V 0x1 +#define LEDC_IDLE_LV_LSCH7_S 3 +/* LEDC_SIG_OUT_EN_LSCH7 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for low speed channel7.*/ +#define LEDC_SIG_OUT_EN_LSCH7 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH7_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH7_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH7_S 2 +/* LEDC_TIMER_SEL_LSCH7 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four low speed timers the two bits are used to select + one of them for low speed channel7. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ +#define LEDC_TIMER_SEL_LSCH7 0x00000003 +#define LEDC_TIMER_SEL_LSCH7_M ((LEDC_TIMER_SEL_LSCH7_V)<<(LEDC_TIMER_SEL_LSCH7_S)) +#define LEDC_TIMER_SEL_LSCH7_V 0x3 +#define LEDC_TIMER_SEL_LSCH7_S 0 + +#define LEDC_LSCH7_HPOINT_REG (DR_REG_LEDC_BASE + 0x0130) +/* LEDC_HPOINT_LSCH7 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when lstimerx(x=[0 3]) selected + by low speed channel7 has reached reg_hpoint_lsch7[19:0]*/ +#define LEDC_HPOINT_LSCH7 0x000FFFFF +#define LEDC_HPOINT_LSCH7_M ((LEDC_HPOINT_LSCH7_V)<<(LEDC_HPOINT_LSCH7_S)) +#define LEDC_HPOINT_LSCH7_V 0xFFFFF +#define LEDC_HPOINT_LSCH7_S 0 + +#define LEDC_LSCH7_DUTY_REG (DR_REG_LEDC_BASE + 0x0134) +/* LEDC_DUTY_LSCH7 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When lstimerx(x=[0 + 3]) choosed by low speed channel7 has reached reg_lpoint_lsch7 the output signal changes to low. reg_lpoint_lsch7=(reg_hpoint_lsch7[19:0]+reg_duty_lsch7[24:4]) (1) reg_lpoint_lsch7=(reg_hpoint_lsch7[19:0]+reg_duty_lsch7[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_LSCH7 0x01FFFFFF +#define LEDC_DUTY_LSCH7_M ((LEDC_DUTY_LSCH7_V)<<(LEDC_DUTY_LSCH7_S)) +#define LEDC_DUTY_LSCH7_V 0x1FFFFFF +#define LEDC_DUTY_LSCH7_S 0 + +#define LEDC_LSCH7_CONF1_REG (DR_REG_LEDC_BASE + 0x0138) +/* LEDC_DUTY_START_LSCH7 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch4 reg_duty_cycle_hsch4 and reg_duty_scale_hsch4 + has been configured. these register won't take effect until set reg_duty_start_hsch4. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_LSCH7 (BIT(31)) +#define LEDC_DUTY_START_LSCH7_M (BIT(31)) +#define LEDC_DUTY_START_LSCH7_V 0x1 +#define LEDC_DUTY_START_LSCH7_S 31 +/* LEDC_DUTY_INC_LSCH7 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for low speed channel4.*/ +#define LEDC_DUTY_INC_LSCH7 (BIT(30)) +#define LEDC_DUTY_INC_LSCH7_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH7_V 0x1 +#define LEDC_DUTY_INC_LSCH7_S 30 +/* LEDC_DUTY_NUM_LSCH7 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for low speed channel4.*/ +#define LEDC_DUTY_NUM_LSCH7 0x000003FF +#define LEDC_DUTY_NUM_LSCH7_M ((LEDC_DUTY_NUM_LSCH7_V)<<(LEDC_DUTY_NUM_LSCH7_S)) +#define LEDC_DUTY_NUM_LSCH7_V 0x3FF +#define LEDC_DUTY_NUM_LSCH7_S 20 +/* LEDC_DUTY_CYCLE_LSCH7 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_lsch7 cycles for low speed channel7.*/ +#define LEDC_DUTY_CYCLE_LSCH7 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH7_M ((LEDC_DUTY_CYCLE_LSCH7_V)<<(LEDC_DUTY_CYCLE_LSCH7_S)) +#define LEDC_DUTY_CYCLE_LSCH7_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH7_S 10 +/* LEDC_DUTY_SCALE_LSCH7 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + low speed channel7.*/ +#define LEDC_DUTY_SCALE_LSCH7 0x000003FF +#define LEDC_DUTY_SCALE_LSCH7_M ((LEDC_DUTY_SCALE_LSCH7_V)<<(LEDC_DUTY_SCALE_LSCH7_S)) +#define LEDC_DUTY_SCALE_LSCH7_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH7_S 0 + +#define LEDC_LSCH7_DUTY_R_REG (DR_REG_LEDC_BASE + 0x013C) +/* LEDC_DUTY_LSCH7 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for low speed channel7.*/ +#define LEDC_DUTY_LSCH7 0x01FFFFFF +#define LEDC_DUTY_LSCH7_M ((LEDC_DUTY_LSCH7_V)<<(LEDC_DUTY_LSCH7_S)) +#define LEDC_DUTY_LSCH7_V 0x1FFFFFF +#define LEDC_DUTY_LSCH7_S 0 + +#define LEDC_HSTIMER0_CONF_REG (DR_REG_LEDC_BASE + 0x0140) +/* LEDC_TICK_SEL_HSTIMER0 : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: This bit is used to choose apb_clk or ref_tick for high speed + timer0. 1'b1:apb_clk 0:ref_tick*/ +#define LEDC_TICK_SEL_HSTIMER0 (BIT(25)) +#define LEDC_TICK_SEL_HSTIMER0_M (BIT(25)) +#define LEDC_TICK_SEL_HSTIMER0_V 0x1 +#define LEDC_TICK_SEL_HSTIMER0_S 25 +/* LEDC_HSTIMER0_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: This bit is used to reset high speed timer0 the counter will be 0 after reset.*/ +#define LEDC_HSTIMER0_RST (BIT(24)) +#define LEDC_HSTIMER0_RST_M (BIT(24)) +#define LEDC_HSTIMER0_RST_V 0x1 +#define LEDC_HSTIMER0_RST_S 24 +/* LEDC_HSTIMER0_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: This bit is used to pause the counter in high speed timer0*/ +#define LEDC_HSTIMER0_PAUSE (BIT(23)) +#define LEDC_HSTIMER0_PAUSE_M (BIT(23)) +#define LEDC_HSTIMER0_PAUSE_V 0x1 +#define LEDC_HSTIMER0_PAUSE_S 23 +/* LEDC_DIV_NUM_HSTIMER0 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ +/*description: This register is used to configure parameter for divider in high + speed timer0 the least significant eight bits represent the decimal part.*/ +#define LEDC_DIV_NUM_HSTIMER0 0x0003FFFF +#define LEDC_DIV_NUM_HSTIMER0_M ((LEDC_DIV_NUM_HSTIMER0_V)<<(LEDC_DIV_NUM_HSTIMER0_S)) +#define LEDC_DIV_NUM_HSTIMER0_V 0x3FFFF +#define LEDC_DIV_NUM_HSTIMER0_S 5 +/* LEDC_HSTIMER0_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: This register controls the range of the counter in high speed + timer0. the counter range is [0 2**reg_hstimer0_lim] the max bit width for counter is 20.*/ +#define LEDC_HSTIMER0_LIM 0x0000001F +#define LEDC_HSTIMER0_LIM_M ((LEDC_HSTIMER0_LIM_V)<<(LEDC_HSTIMER0_LIM_S)) +#define LEDC_HSTIMER0_LIM_V 0x1F +#define LEDC_HSTIMER0_LIM_S 0 + +#define LEDC_HSTIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0x0144) +/* LEDC_HSTIMER0_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: software can read this register to get the current counter value + in high speed timer0*/ +#define LEDC_HSTIMER0_CNT 0x000FFFFF +#define LEDC_HSTIMER0_CNT_M ((LEDC_HSTIMER0_CNT_V)<<(LEDC_HSTIMER0_CNT_S)) +#define LEDC_HSTIMER0_CNT_V 0xFFFFF +#define LEDC_HSTIMER0_CNT_S 0 + +#define LEDC_HSTIMER1_CONF_REG (DR_REG_LEDC_BASE + 0x0148) +/* LEDC_TICK_SEL_HSTIMER1 : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: This bit is used to choose apb_clk or ref_tick for high speed + timer1. 1'b1:apb_clk 0:ref_tick*/ +#define LEDC_TICK_SEL_HSTIMER1 (BIT(25)) +#define LEDC_TICK_SEL_HSTIMER1_M (BIT(25)) +#define LEDC_TICK_SEL_HSTIMER1_V 0x1 +#define LEDC_TICK_SEL_HSTIMER1_S 25 +/* LEDC_HSTIMER1_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: This bit is used to reset high speed timer1 the counter will be 0 after reset.*/ +#define LEDC_HSTIMER1_RST (BIT(24)) +#define LEDC_HSTIMER1_RST_M (BIT(24)) +#define LEDC_HSTIMER1_RST_V 0x1 +#define LEDC_HSTIMER1_RST_S 24 +/* LEDC_HSTIMER1_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: This bit is used to pause the counter in high speed timer1*/ +#define LEDC_HSTIMER1_PAUSE (BIT(23)) +#define LEDC_HSTIMER1_PAUSE_M (BIT(23)) +#define LEDC_HSTIMER1_PAUSE_V 0x1 +#define LEDC_HSTIMER1_PAUSE_S 23 +/* LEDC_DIV_NUM_HSTIMER1 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ +/*description: This register is used to configure parameter for divider in high + speed timer1 the least significant eight bits represent the decimal part.*/ +#define LEDC_DIV_NUM_HSTIMER1 0x0003FFFF +#define LEDC_DIV_NUM_HSTIMER1_M ((LEDC_DIV_NUM_HSTIMER1_V)<<(LEDC_DIV_NUM_HSTIMER1_S)) +#define LEDC_DIV_NUM_HSTIMER1_V 0x3FFFF +#define LEDC_DIV_NUM_HSTIMER1_S 5 +/* LEDC_HSTIMER1_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: This register controls the range of the counter in high speed + timer1. the counter range is [0 2**reg_hstimer1_lim] the max bit width for counter is 20.*/ +#define LEDC_HSTIMER1_LIM 0x0000001F +#define LEDC_HSTIMER1_LIM_M ((LEDC_HSTIMER1_LIM_V)<<(LEDC_HSTIMER1_LIM_S)) +#define LEDC_HSTIMER1_LIM_V 0x1F +#define LEDC_HSTIMER1_LIM_S 0 + +#define LEDC_HSTIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0x014C) +/* LEDC_HSTIMER1_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: software can read this register to get the current counter value + in high speed timer1.*/ +#define LEDC_HSTIMER1_CNT 0x000FFFFF +#define LEDC_HSTIMER1_CNT_M ((LEDC_HSTIMER1_CNT_V)<<(LEDC_HSTIMER1_CNT_S)) +#define LEDC_HSTIMER1_CNT_V 0xFFFFF +#define LEDC_HSTIMER1_CNT_S 0 + +#define LEDC_HSTIMER2_CONF_REG (DR_REG_LEDC_BASE + 0x0150) +/* LEDC_TICK_SEL_HSTIMER2 : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: This bit is used to choose apb_clk or ref_tick for high speed + timer2. 1'b1:apb_clk 0:ref_tick*/ +#define LEDC_TICK_SEL_HSTIMER2 (BIT(25)) +#define LEDC_TICK_SEL_HSTIMER2_M (BIT(25)) +#define LEDC_TICK_SEL_HSTIMER2_V 0x1 +#define LEDC_TICK_SEL_HSTIMER2_S 25 +/* LEDC_HSTIMER2_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: This bit is used to reset high speed timer2 the counter will be 0 after reset.*/ +#define LEDC_HSTIMER2_RST (BIT(24)) +#define LEDC_HSTIMER2_RST_M (BIT(24)) +#define LEDC_HSTIMER2_RST_V 0x1 +#define LEDC_HSTIMER2_RST_S 24 +/* LEDC_HSTIMER2_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: This bit is used to pause the counter in high speed timer2*/ +#define LEDC_HSTIMER2_PAUSE (BIT(23)) +#define LEDC_HSTIMER2_PAUSE_M (BIT(23)) +#define LEDC_HSTIMER2_PAUSE_V 0x1 +#define LEDC_HSTIMER2_PAUSE_S 23 +/* LEDC_DIV_NUM_HSTIMER2 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ +/*description: This register is used to configure parameter for divider in high + speed timer2 the least significant eight bits represent the decimal part.*/ +#define LEDC_DIV_NUM_HSTIMER2 0x0003FFFF +#define LEDC_DIV_NUM_HSTIMER2_M ((LEDC_DIV_NUM_HSTIMER2_V)<<(LEDC_DIV_NUM_HSTIMER2_S)) +#define LEDC_DIV_NUM_HSTIMER2_V 0x3FFFF +#define LEDC_DIV_NUM_HSTIMER2_S 5 +/* LEDC_HSTIMER2_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: This register controls the range of the counter in high speed + timer2. the counter range is [0 2**reg_hstimer2_lim] the max bit width for counter is 20.*/ +#define LEDC_HSTIMER2_LIM 0x0000001F +#define LEDC_HSTIMER2_LIM_M ((LEDC_HSTIMER2_LIM_V)<<(LEDC_HSTIMER2_LIM_S)) +#define LEDC_HSTIMER2_LIM_V 0x1F +#define LEDC_HSTIMER2_LIM_S 0 + +#define LEDC_HSTIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0x0154) +/* LEDC_HSTIMER2_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: software can read this register to get the current counter value + in high speed timer2*/ +#define LEDC_HSTIMER2_CNT 0x000FFFFF +#define LEDC_HSTIMER2_CNT_M ((LEDC_HSTIMER2_CNT_V)<<(LEDC_HSTIMER2_CNT_S)) +#define LEDC_HSTIMER2_CNT_V 0xFFFFF +#define LEDC_HSTIMER2_CNT_S 0 + +#define LEDC_HSTIMER3_CONF_REG (DR_REG_LEDC_BASE + 0x0158) +/* LEDC_TICK_SEL_HSTIMER3 : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: This bit is used to choose apb_clk or ref_tick for high speed + timer3. 1'b1:apb_clk 0:ref_tick*/ +#define LEDC_TICK_SEL_HSTIMER3 (BIT(25)) +#define LEDC_TICK_SEL_HSTIMER3_M (BIT(25)) +#define LEDC_TICK_SEL_HSTIMER3_V 0x1 +#define LEDC_TICK_SEL_HSTIMER3_S 25 +/* LEDC_HSTIMER3_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: This bit is used to reset high speed timer3 the counter will be 0 after reset.*/ +#define LEDC_HSTIMER3_RST (BIT(24)) +#define LEDC_HSTIMER3_RST_M (BIT(24)) +#define LEDC_HSTIMER3_RST_V 0x1 +#define LEDC_HSTIMER3_RST_S 24 +/* LEDC_HSTIMER3_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: This bit is used to pause the counter in high speed timer3*/ +#define LEDC_HSTIMER3_PAUSE (BIT(23)) +#define LEDC_HSTIMER3_PAUSE_M (BIT(23)) +#define LEDC_HSTIMER3_PAUSE_V 0x1 +#define LEDC_HSTIMER3_PAUSE_S 23 +/* LEDC_DIV_NUM_HSTIMER3 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ +/*description: This register is used to configure parameter for divider in high + speed timer3 the least significant eight bits represent the decimal part.*/ +#define LEDC_DIV_NUM_HSTIMER3 0x0003FFFF +#define LEDC_DIV_NUM_HSTIMER3_M ((LEDC_DIV_NUM_HSTIMER3_V)<<(LEDC_DIV_NUM_HSTIMER3_S)) +#define LEDC_DIV_NUM_HSTIMER3_V 0x3FFFF +#define LEDC_DIV_NUM_HSTIMER3_S 5 +/* LEDC_HSTIMER3_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: This register controls the range of the counter in high speed + timer3. the counter range is [0 2**reg_hstimer3_lim] the max bit width for counter is 20.*/ +#define LEDC_HSTIMER3_LIM 0x0000001F +#define LEDC_HSTIMER3_LIM_M ((LEDC_HSTIMER3_LIM_V)<<(LEDC_HSTIMER3_LIM_S)) +#define LEDC_HSTIMER3_LIM_V 0x1F +#define LEDC_HSTIMER3_LIM_S 0 + +#define LEDC_HSTIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0x015C) +/* LEDC_HSTIMER3_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: software can read this register to get the current counter value + in high speed timer3*/ +#define LEDC_HSTIMER3_CNT 0x000FFFFF +#define LEDC_HSTIMER3_CNT_M ((LEDC_HSTIMER3_CNT_V)<<(LEDC_HSTIMER3_CNT_S)) +#define LEDC_HSTIMER3_CNT_V 0xFFFFF +#define LEDC_HSTIMER3_CNT_S 0 + +#define LEDC_LSTIMER0_CONF_REG (DR_REG_LEDC_BASE + 0x0160) +/* LEDC_LSTIMER0_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */ +/*description: Set this bit to update reg_div_num_lstime0 and reg_lstimer0_lim.*/ +#define LEDC_LSTIMER0_PARA_UP (BIT(26)) +#define LEDC_LSTIMER0_PARA_UP_M (BIT(26)) +#define LEDC_LSTIMER0_PARA_UP_V 0x1 +#define LEDC_LSTIMER0_PARA_UP_S 26 +/* LEDC_TICK_SEL_LSTIMER0 : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: This bit is used to choose slow_clk or ref_tick for low speed + timer0. 1'b1:slow_clk 0:ref_tick*/ +#define LEDC_TICK_SEL_LSTIMER0 (BIT(25)) +#define LEDC_TICK_SEL_LSTIMER0_M (BIT(25)) +#define LEDC_TICK_SEL_LSTIMER0_V 0x1 +#define LEDC_TICK_SEL_LSTIMER0_S 25 +/* LEDC_LSTIMER0_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: This bit is used to reset low speed timer0 the counter will be 0 after reset.*/ +#define LEDC_LSTIMER0_RST (BIT(24)) +#define LEDC_LSTIMER0_RST_M (BIT(24)) +#define LEDC_LSTIMER0_RST_V 0x1 +#define LEDC_LSTIMER0_RST_S 24 +/* LEDC_LSTIMER0_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: This bit is used to pause the counter in low speed timer0.*/ +#define LEDC_LSTIMER0_PAUSE (BIT(23)) +#define LEDC_LSTIMER0_PAUSE_M (BIT(23)) +#define LEDC_LSTIMER0_PAUSE_V 0x1 +#define LEDC_LSTIMER0_PAUSE_S 23 +/* LEDC_DIV_NUM_LSTIMER0 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ +/*description: This register is used to configure parameter for divider in low + speed timer0 the least significant eight bits represent the decimal part.*/ +#define LEDC_DIV_NUM_LSTIMER0 0x0003FFFF +#define LEDC_DIV_NUM_LSTIMER0_M ((LEDC_DIV_NUM_LSTIMER0_V)<<(LEDC_DIV_NUM_LSTIMER0_S)) +#define LEDC_DIV_NUM_LSTIMER0_V 0x3FFFF +#define LEDC_DIV_NUM_LSTIMER0_S 5 +/* LEDC_LSTIMER0_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: This register controls the range of the counter in low speed + timer0. the counter range is [0 2**reg_lstimer0_lim] the max bit width for counter is 20.*/ +#define LEDC_LSTIMER0_LIM 0x0000001F +#define LEDC_LSTIMER0_LIM_M ((LEDC_LSTIMER0_LIM_V)<<(LEDC_LSTIMER0_LIM_S)) +#define LEDC_LSTIMER0_LIM_V 0x1F +#define LEDC_LSTIMER0_LIM_S 0 + +#define LEDC_LSTIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0x0164) +/* LEDC_LSTIMER0_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: software can read this register to get the current counter value + in low speed timer0.*/ +#define LEDC_LSTIMER0_CNT 0x000FFFFF +#define LEDC_LSTIMER0_CNT_M ((LEDC_LSTIMER0_CNT_V)<<(LEDC_LSTIMER0_CNT_S)) +#define LEDC_LSTIMER0_CNT_V 0xFFFFF +#define LEDC_LSTIMER0_CNT_S 0 + +#define LEDC_LSTIMER1_CONF_REG (DR_REG_LEDC_BASE + 0x0168) +/* LEDC_LSTIMER1_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */ +/*description: Set this bit to update reg_div_num_lstime1 and reg_lstimer1_lim.*/ +#define LEDC_LSTIMER1_PARA_UP (BIT(26)) +#define LEDC_LSTIMER1_PARA_UP_M (BIT(26)) +#define LEDC_LSTIMER1_PARA_UP_V 0x1 +#define LEDC_LSTIMER1_PARA_UP_S 26 +/* LEDC_TICK_SEL_LSTIMER1 : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: This bit is used to choose slow_clk or ref_tick for low speed + timer1. 1'b1:slow_clk 0:ref_tick*/ +#define LEDC_TICK_SEL_LSTIMER1 (BIT(25)) +#define LEDC_TICK_SEL_LSTIMER1_M (BIT(25)) +#define LEDC_TICK_SEL_LSTIMER1_V 0x1 +#define LEDC_TICK_SEL_LSTIMER1_S 25 +/* LEDC_LSTIMER1_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: This bit is used to reset low speed timer1 the counter will be 0 after reset.*/ +#define LEDC_LSTIMER1_RST (BIT(24)) +#define LEDC_LSTIMER1_RST_M (BIT(24)) +#define LEDC_LSTIMER1_RST_V 0x1 +#define LEDC_LSTIMER1_RST_S 24 +/* LEDC_LSTIMER1_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: This bit is used to pause the counter in low speed timer1.*/ +#define LEDC_LSTIMER1_PAUSE (BIT(23)) +#define LEDC_LSTIMER1_PAUSE_M (BIT(23)) +#define LEDC_LSTIMER1_PAUSE_V 0x1 +#define LEDC_LSTIMER1_PAUSE_S 23 +/* LEDC_DIV_NUM_LSTIMER1 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ +/*description: This register is used to configure parameter for divider in low + speed timer1 the least significant eight bits represent the decimal part.*/ +#define LEDC_DIV_NUM_LSTIMER1 0x0003FFFF +#define LEDC_DIV_NUM_LSTIMER1_M ((LEDC_DIV_NUM_LSTIMER1_V)<<(LEDC_DIV_NUM_LSTIMER1_S)) +#define LEDC_DIV_NUM_LSTIMER1_V 0x3FFFF +#define LEDC_DIV_NUM_LSTIMER1_S 5 +/* LEDC_LSTIMER1_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: This register controls the range of the counter in low speed + timer1. the counter range is [0 2**reg_lstimer1_lim] the max bit width for counter is 20.*/ +#define LEDC_LSTIMER1_LIM 0x0000001F +#define LEDC_LSTIMER1_LIM_M ((LEDC_LSTIMER1_LIM_V)<<(LEDC_LSTIMER1_LIM_S)) +#define LEDC_LSTIMER1_LIM_V 0x1F +#define LEDC_LSTIMER1_LIM_S 0 + +#define LEDC_LSTIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0x016C) +/* LEDC_LSTIMER1_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: software can read this register to get the current counter value + in low speed timer1.*/ +#define LEDC_LSTIMER1_CNT 0x000FFFFF +#define LEDC_LSTIMER1_CNT_M ((LEDC_LSTIMER1_CNT_V)<<(LEDC_LSTIMER1_CNT_S)) +#define LEDC_LSTIMER1_CNT_V 0xFFFFF +#define LEDC_LSTIMER1_CNT_S 0 + +#define LEDC_LSTIMER2_CONF_REG (DR_REG_LEDC_BASE + 0x0170) +/* LEDC_LSTIMER2_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */ +/*description: Set this bit to update reg_div_num_lstime2 and reg_lstimer2_lim.*/ +#define LEDC_LSTIMER2_PARA_UP (BIT(26)) +#define LEDC_LSTIMER2_PARA_UP_M (BIT(26)) +#define LEDC_LSTIMER2_PARA_UP_V 0x1 +#define LEDC_LSTIMER2_PARA_UP_S 26 +/* LEDC_TICK_SEL_LSTIMER2 : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: This bit is used to choose slow_clk or ref_tick for low speed + timer2. 1'b1:slow_clk 0:ref_tick*/ +#define LEDC_TICK_SEL_LSTIMER2 (BIT(25)) +#define LEDC_TICK_SEL_LSTIMER2_M (BIT(25)) +#define LEDC_TICK_SEL_LSTIMER2_V 0x1 +#define LEDC_TICK_SEL_LSTIMER2_S 25 +/* LEDC_LSTIMER2_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: This bit is used to reset low speed timer2 the counter will be 0 after reset.*/ +#define LEDC_LSTIMER2_RST (BIT(24)) +#define LEDC_LSTIMER2_RST_M (BIT(24)) +#define LEDC_LSTIMER2_RST_V 0x1 +#define LEDC_LSTIMER2_RST_S 24 +/* LEDC_LSTIMER2_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: This bit is used to pause the counter in low speed timer2.*/ +#define LEDC_LSTIMER2_PAUSE (BIT(23)) +#define LEDC_LSTIMER2_PAUSE_M (BIT(23)) +#define LEDC_LSTIMER2_PAUSE_V 0x1 +#define LEDC_LSTIMER2_PAUSE_S 23 +/* LEDC_DIV_NUM_LSTIMER2 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ +/*description: This register is used to configure parameter for divider in low + speed timer2 the least significant eight bits represent the decimal part.*/ +#define LEDC_DIV_NUM_LSTIMER2 0x0003FFFF +#define LEDC_DIV_NUM_LSTIMER2_M ((LEDC_DIV_NUM_LSTIMER2_V)<<(LEDC_DIV_NUM_LSTIMER2_S)) +#define LEDC_DIV_NUM_LSTIMER2_V 0x3FFFF +#define LEDC_DIV_NUM_LSTIMER2_S 5 +/* LEDC_LSTIMER2_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: This register controls the range of the counter in low speed + timer2. the counter range is [0 2**reg_lstimer2_lim] the max bit width for counter is 20.*/ +#define LEDC_LSTIMER2_LIM 0x0000001F +#define LEDC_LSTIMER2_LIM_M ((LEDC_LSTIMER2_LIM_V)<<(LEDC_LSTIMER2_LIM_S)) +#define LEDC_LSTIMER2_LIM_V 0x1F +#define LEDC_LSTIMER2_LIM_S 0 + +#define LEDC_LSTIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0x0174) +/* LEDC_LSTIMER2_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: software can read this register to get the current counter value + in low speed timer2.*/ +#define LEDC_LSTIMER2_CNT 0x000FFFFF +#define LEDC_LSTIMER2_CNT_M ((LEDC_LSTIMER2_CNT_V)<<(LEDC_LSTIMER2_CNT_S)) +#define LEDC_LSTIMER2_CNT_V 0xFFFFF +#define LEDC_LSTIMER2_CNT_S 0 + +#define LEDC_LSTIMER3_CONF_REG (DR_REG_LEDC_BASE + 0x0178) +/* LEDC_LSTIMER3_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */ +/*description: Set this bit to update reg_div_num_lstime3 and reg_lstimer3_lim.*/ +#define LEDC_LSTIMER3_PARA_UP (BIT(26)) +#define LEDC_LSTIMER3_PARA_UP_M (BIT(26)) +#define LEDC_LSTIMER3_PARA_UP_V 0x1 +#define LEDC_LSTIMER3_PARA_UP_S 26 +/* LEDC_TICK_SEL_LSTIMER3 : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: This bit is used to choose slow_clk or ref_tick for low speed + timer3. 1'b1:slow_clk 0:ref_tick*/ +#define LEDC_TICK_SEL_LSTIMER3 (BIT(25)) +#define LEDC_TICK_SEL_LSTIMER3_M (BIT(25)) +#define LEDC_TICK_SEL_LSTIMER3_V 0x1 +#define LEDC_TICK_SEL_LSTIMER3_S 25 +/* LEDC_LSTIMER3_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: This bit is used to reset low speed timer3 the counter will be 0 after reset.*/ +#define LEDC_LSTIMER3_RST (BIT(24)) +#define LEDC_LSTIMER3_RST_M (BIT(24)) +#define LEDC_LSTIMER3_RST_V 0x1 +#define LEDC_LSTIMER3_RST_S 24 +/* LEDC_LSTIMER3_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: This bit is used to pause the counter in low speed timer3.*/ +#define LEDC_LSTIMER3_PAUSE (BIT(23)) +#define LEDC_LSTIMER3_PAUSE_M (BIT(23)) +#define LEDC_LSTIMER3_PAUSE_V 0x1 +#define LEDC_LSTIMER3_PAUSE_S 23 +/* LEDC_DIV_NUM_LSTIMER3 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ +/*description: This register is used to configure parameter for divider in low + speed timer3 the least significant eight bits represent the decimal part.*/ +#define LEDC_DIV_NUM_LSTIMER3 0x0003FFFF +#define LEDC_DIV_NUM_LSTIMER3_M ((LEDC_DIV_NUM_LSTIMER3_V)<<(LEDC_DIV_NUM_LSTIMER3_S)) +#define LEDC_DIV_NUM_LSTIMER3_V 0x3FFFF +#define LEDC_DIV_NUM_LSTIMER3_S 5 +/* LEDC_LSTIMER3_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: This register controls the range of the counter in low speed + timer3. the counter range is [0 2**reg_lstimer3_lim] the max bit width for counter is 20.*/ +#define LEDC_LSTIMER3_LIM 0x0000001F +#define LEDC_LSTIMER3_LIM_M ((LEDC_LSTIMER3_LIM_V)<<(LEDC_LSTIMER3_LIM_S)) +#define LEDC_LSTIMER3_LIM_V 0x1F +#define LEDC_LSTIMER3_LIM_S 0 + +#define LEDC_LSTIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0x017C) +/* LEDC_LSTIMER3_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: software can read this register to get the current counter value + in low speed timer3.*/ +#define LEDC_LSTIMER3_CNT 0x000FFFFF +#define LEDC_LSTIMER3_CNT_M ((LEDC_LSTIMER3_CNT_V)<<(LEDC_LSTIMER3_CNT_S)) +#define LEDC_LSTIMER3_CNT_V 0xFFFFF +#define LEDC_LSTIMER3_CNT_S 0 + +#define LEDC_INT_RAW_REG (DR_REG_LEDC_BASE + 0x0180) +/* LEDC_DUTY_CHNG_END_LSCH7_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel 7 duty change done.*/ +#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW (BIT(23)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_M (BIT(23)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_S 23 +/* LEDC_DUTY_CHNG_END_LSCH6_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel 6 duty change done.*/ +#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW (BIT(22)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_M (BIT(22)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_S 22 +/* LEDC_DUTY_CHNG_END_LSCH5_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel 5 duty change done.*/ +#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW (BIT(21)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_M (BIT(21)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_S 21 +/* LEDC_DUTY_CHNG_END_LSCH4_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel 4 duty change done.*/ +#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW (BIT(20)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_M (BIT(20)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_S 20 +/* LEDC_DUTY_CHNG_END_LSCH3_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel 3 duty change done.*/ +#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW (BIT(19)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_M (BIT(19)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_S 19 +/* LEDC_DUTY_CHNG_END_LSCH2_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel 2 duty change done.*/ +#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW (BIT(18)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_M (BIT(18)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_S 18 +/* LEDC_DUTY_CHNG_END_LSCH1_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel 1 duty change done.*/ +#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW (BIT(17)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_M (BIT(17)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_S 17 +/* LEDC_DUTY_CHNG_END_LSCH0_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel 0 duty change done.*/ +#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW (BIT(16)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_M (BIT(16)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_S 16 +/* LEDC_DUTY_CHNG_END_HSCH7_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel 7 duty change done.*/ +#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW (BIT(15)) +#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW_M (BIT(15)) +#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW_S 15 +/* LEDC_DUTY_CHNG_END_HSCH6_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel 6 duty change done.*/ +#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW (BIT(14)) +#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_M (BIT(14)) +#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_S 14 +/* LEDC_DUTY_CHNG_END_HSCH5_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel 5 duty change done.*/ +#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW (BIT(13)) +#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW_M (BIT(13)) +#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW_S 13 +/* LEDC_DUTY_CHNG_END_HSCH4_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel 4 duty change done.*/ +#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW (BIT(12)) +#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW_M (BIT(12)) +#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW_S 12 +/* LEDC_DUTY_CHNG_END_HSCH3_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel 3 duty change done.*/ +#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW (BIT(11)) +#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_M (BIT(11)) +#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_S 11 +/* LEDC_DUTY_CHNG_END_HSCH2_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel 2 duty change done.*/ +#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW (BIT(10)) +#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW_M (BIT(10)) +#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW_S 10 +/* LEDC_DUTY_CHNG_END_HSCH1_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel 1 duty change done.*/ +#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW (BIT(9)) +#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW_M (BIT(9)) +#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW_S 9 +/* LEDC_DUTY_CHNG_END_HSCH0_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel 0 duty change done.*/ +#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW (BIT(8)) +#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_M (BIT(8)) +#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_S 8 +/* LEDC_LSTIMER3_OVF_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel3 counter overflow.*/ +#define LEDC_LSTIMER3_OVF_INT_RAW (BIT(7)) +#define LEDC_LSTIMER3_OVF_INT_RAW_M (BIT(7)) +#define LEDC_LSTIMER3_OVF_INT_RAW_V 0x1 +#define LEDC_LSTIMER3_OVF_INT_RAW_S 7 +/* LEDC_LSTIMER2_OVF_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel2 counter overflow.*/ +#define LEDC_LSTIMER2_OVF_INT_RAW (BIT(6)) +#define LEDC_LSTIMER2_OVF_INT_RAW_M (BIT(6)) +#define LEDC_LSTIMER2_OVF_INT_RAW_V 0x1 +#define LEDC_LSTIMER2_OVF_INT_RAW_S 6 +/* LEDC_LSTIMER1_OVF_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel1 counter overflow.*/ +#define LEDC_LSTIMER1_OVF_INT_RAW (BIT(5)) +#define LEDC_LSTIMER1_OVF_INT_RAW_M (BIT(5)) +#define LEDC_LSTIMER1_OVF_INT_RAW_V 0x1 +#define LEDC_LSTIMER1_OVF_INT_RAW_S 5 +/* LEDC_LSTIMER0_OVF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel0 counter overflow.*/ +#define LEDC_LSTIMER0_OVF_INT_RAW (BIT(4)) +#define LEDC_LSTIMER0_OVF_INT_RAW_M (BIT(4)) +#define LEDC_LSTIMER0_OVF_INT_RAW_V 0x1 +#define LEDC_LSTIMER0_OVF_INT_RAW_S 4 +/* LEDC_HSTIMER3_OVF_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel3 counter overflow.*/ +#define LEDC_HSTIMER3_OVF_INT_RAW (BIT(3)) +#define LEDC_HSTIMER3_OVF_INT_RAW_M (BIT(3)) +#define LEDC_HSTIMER3_OVF_INT_RAW_V 0x1 +#define LEDC_HSTIMER3_OVF_INT_RAW_S 3 +/* LEDC_HSTIMER2_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel2 counter overflow.*/ +#define LEDC_HSTIMER2_OVF_INT_RAW (BIT(2)) +#define LEDC_HSTIMER2_OVF_INT_RAW_M (BIT(2)) +#define LEDC_HSTIMER2_OVF_INT_RAW_V 0x1 +#define LEDC_HSTIMER2_OVF_INT_RAW_S 2 +/* LEDC_HSTIMER1_OVF_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel1 counter overflow.*/ +#define LEDC_HSTIMER1_OVF_INT_RAW (BIT(1)) +#define LEDC_HSTIMER1_OVF_INT_RAW_M (BIT(1)) +#define LEDC_HSTIMER1_OVF_INT_RAW_V 0x1 +#define LEDC_HSTIMER1_OVF_INT_RAW_S 1 +/* LEDC_HSTIMER0_OVF_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel0 counter overflow.*/ +#define LEDC_HSTIMER0_OVF_INT_RAW (BIT(0)) +#define LEDC_HSTIMER0_OVF_INT_RAW_M (BIT(0)) +#define LEDC_HSTIMER0_OVF_INT_RAW_V 0x1 +#define LEDC_HSTIMER0_OVF_INT_RAW_S 0 + +#define LEDC_INT_ST_REG (DR_REG_LEDC_BASE + 0x0184) +/* LEDC_DUTY_CHNG_END_LSCH7_INT_ST : RO ;bitpos:[23] ;default: 1'h0 ; */ +/*description: The interrupt status bit for low speed channel 7 duty change done event*/ +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST (BIT(23)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_M (BIT(23)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_S 23 +/* LEDC_DUTY_CHNG_END_LSCH6_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel 6 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST (BIT(22)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_M (BIT(22)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_S 22 +/* LEDC_DUTY_CHNG_END_LSCH5_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel 5 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST (BIT(21)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_M (BIT(21)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_S 21 +/* LEDC_DUTY_CHNG_END_LSCH4_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel 4 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST (BIT(20)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_M (BIT(20)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_S 20 +/* LEDC_DUTY_CHNG_END_LSCH3_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel 3 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST (BIT(19)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_M (BIT(19)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_S 19 +/* LEDC_DUTY_CHNG_END_LSCH2_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel 2 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST (BIT(18)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_M (BIT(18)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_S 18 +/* LEDC_DUTY_CHNG_END_LSCH1_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel 1 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST (BIT(17)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_M (BIT(17)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_S 17 +/* LEDC_DUTY_CHNG_END_LSCH0_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel 0 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST (BIT(16)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_M (BIT(16)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_S 16 +/* LEDC_DUTY_CHNG_END_HSCH7_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel 7 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST (BIT(15)) +#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_M (BIT(15)) +#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_S 15 +/* LEDC_DUTY_CHNG_END_HSCH6_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel 6 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST (BIT(14)) +#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST_M (BIT(14)) +#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST_S 14 +/* LEDC_DUTY_CHNG_END_HSCH5_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel 5 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST (BIT(13)) +#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST_M (BIT(13)) +#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST_S 13 +/* LEDC_DUTY_CHNG_END_HSCH4_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel 4 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST (BIT(12)) +#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_M (BIT(12)) +#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_S 12 +/* LEDC_DUTY_CHNG_END_HSCH3_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel 3 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST (BIT(11)) +#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST_M (BIT(11)) +#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST_S 11 +/* LEDC_DUTY_CHNG_END_HSCH2_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel 2 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST (BIT(10)) +#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST_M (BIT(10)) +#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST_S 10 +/* LEDC_DUTY_CHNG_END_HSCH1_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel 1 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST (BIT(9)) +#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_M (BIT(9)) +#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_S 9 +/* LEDC_DUTY_CHNG_END_HSCH0_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel 0 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST (BIT(8)) +#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST_M (BIT(8)) +#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST_S 8 +/* LEDC_LSTIMER3_OVF_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel3 counter overflow event.*/ +#define LEDC_LSTIMER3_OVF_INT_ST (BIT(7)) +#define LEDC_LSTIMER3_OVF_INT_ST_M (BIT(7)) +#define LEDC_LSTIMER3_OVF_INT_ST_V 0x1 +#define LEDC_LSTIMER3_OVF_INT_ST_S 7 +/* LEDC_LSTIMER2_OVF_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel2 counter overflow event.*/ +#define LEDC_LSTIMER2_OVF_INT_ST (BIT(6)) +#define LEDC_LSTIMER2_OVF_INT_ST_M (BIT(6)) +#define LEDC_LSTIMER2_OVF_INT_ST_V 0x1 +#define LEDC_LSTIMER2_OVF_INT_ST_S 6 +/* LEDC_LSTIMER1_OVF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel1 counter overflow event.*/ +#define LEDC_LSTIMER1_OVF_INT_ST (BIT(5)) +#define LEDC_LSTIMER1_OVF_INT_ST_M (BIT(5)) +#define LEDC_LSTIMER1_OVF_INT_ST_V 0x1 +#define LEDC_LSTIMER1_OVF_INT_ST_S 5 +/* LEDC_LSTIMER0_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel0 counter overflow event.*/ +#define LEDC_LSTIMER0_OVF_INT_ST (BIT(4)) +#define LEDC_LSTIMER0_OVF_INT_ST_M (BIT(4)) +#define LEDC_LSTIMER0_OVF_INT_ST_V 0x1 +#define LEDC_LSTIMER0_OVF_INT_ST_S 4 +/* LEDC_HSTIMER3_OVF_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel3 counter overflow event.*/ +#define LEDC_HSTIMER3_OVF_INT_ST (BIT(3)) +#define LEDC_HSTIMER3_OVF_INT_ST_M (BIT(3)) +#define LEDC_HSTIMER3_OVF_INT_ST_V 0x1 +#define LEDC_HSTIMER3_OVF_INT_ST_S 3 +/* LEDC_HSTIMER2_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel2 counter overflow event.*/ +#define LEDC_HSTIMER2_OVF_INT_ST (BIT(2)) +#define LEDC_HSTIMER2_OVF_INT_ST_M (BIT(2)) +#define LEDC_HSTIMER2_OVF_INT_ST_V 0x1 +#define LEDC_HSTIMER2_OVF_INT_ST_S 2 +/* LEDC_HSTIMER1_OVF_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel1 counter overflow event.*/ +#define LEDC_HSTIMER1_OVF_INT_ST (BIT(1)) +#define LEDC_HSTIMER1_OVF_INT_ST_M (BIT(1)) +#define LEDC_HSTIMER1_OVF_INT_ST_V 0x1 +#define LEDC_HSTIMER1_OVF_INT_ST_S 1 +/* LEDC_HSTIMER0_OVF_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel0 counter overflow event.*/ +#define LEDC_HSTIMER0_OVF_INT_ST (BIT(0)) +#define LEDC_HSTIMER0_OVF_INT_ST_M (BIT(0)) +#define LEDC_HSTIMER0_OVF_INT_ST_V 0x1 +#define LEDC_HSTIMER0_OVF_INT_ST_S 0 + +#define LEDC_INT_ENA_REG (DR_REG_LEDC_BASE + 0x0188) +/* LEDC_DUTY_CHNG_END_LSCH7_INT_ENA : R/W ;bitpos:[23] ;default: 1'h0 ; */ +/*description: The interrupt enable bit for low speed channel 7 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA (BIT(23)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_M (BIT(23)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_S 23 +/* LEDC_DUTY_CHNG_END_LSCH6_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel 6 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA (BIT(22)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_M (BIT(22)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_S 22 +/* LEDC_DUTY_CHNG_END_LSCH5_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel 5 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA (BIT(21)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_M (BIT(21)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_S 21 +/* LEDC_DUTY_CHNG_END_LSCH4_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel 4 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA (BIT(20)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_M (BIT(20)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_S 20 +/* LEDC_DUTY_CHNG_END_LSCH3_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel 3 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA (BIT(19)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_M (BIT(19)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_S 19 +/* LEDC_DUTY_CHNG_END_LSCH2_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel 2 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA (BIT(18)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_M (BIT(18)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_S 18 +/* LEDC_DUTY_CHNG_END_LSCH1_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel 1 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA (BIT(17)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_M (BIT(17)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_S 17 +/* LEDC_DUTY_CHNG_END_LSCH0_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel 0 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA (BIT(16)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_M (BIT(16)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S 16 +/* LEDC_DUTY_CHNG_END_HSCH7_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel 7 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA (BIT(15)) +#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA_M (BIT(15)) +#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA_S 15 +/* LEDC_DUTY_CHNG_END_HSCH6_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel 6 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA (BIT(14)) +#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_M (BIT(14)) +#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_S 14 +/* LEDC_DUTY_CHNG_END_HSCH5_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel 5 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA (BIT(13)) +#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA_M (BIT(13)) +#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA_S 13 +/* LEDC_DUTY_CHNG_END_HSCH4_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel 4 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA (BIT(12)) +#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA_M (BIT(12)) +#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA_S 12 +/* LEDC_DUTY_CHNG_END_HSCH3_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel 3 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA (BIT(11)) +#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_M (BIT(11)) +#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_S 11 +/* LEDC_DUTY_CHNG_END_HSCH2_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel 2 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA (BIT(10)) +#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA_M (BIT(10)) +#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA_S 10 +/* LEDC_DUTY_CHNG_END_HSCH1_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel 1 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA (BIT(9)) +#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA_M (BIT(9)) +#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA_S 9 +/* LEDC_DUTY_CHNG_END_HSCH0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel 0 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA (BIT(8)) +#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_M (BIT(8)) +#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_S 8 +/* LEDC_LSTIMER3_OVF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel3 counter overflow interrupt.*/ +#define LEDC_LSTIMER3_OVF_INT_ENA (BIT(7)) +#define LEDC_LSTIMER3_OVF_INT_ENA_M (BIT(7)) +#define LEDC_LSTIMER3_OVF_INT_ENA_V 0x1 +#define LEDC_LSTIMER3_OVF_INT_ENA_S 7 +/* LEDC_LSTIMER2_OVF_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel2 counter overflow interrupt.*/ +#define LEDC_LSTIMER2_OVF_INT_ENA (BIT(6)) +#define LEDC_LSTIMER2_OVF_INT_ENA_M (BIT(6)) +#define LEDC_LSTIMER2_OVF_INT_ENA_V 0x1 +#define LEDC_LSTIMER2_OVF_INT_ENA_S 6 +/* LEDC_LSTIMER1_OVF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel1 counter overflow interrupt.*/ +#define LEDC_LSTIMER1_OVF_INT_ENA (BIT(5)) +#define LEDC_LSTIMER1_OVF_INT_ENA_M (BIT(5)) +#define LEDC_LSTIMER1_OVF_INT_ENA_V 0x1 +#define LEDC_LSTIMER1_OVF_INT_ENA_S 5 +/* LEDC_LSTIMER0_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel0 counter overflow interrupt.*/ +#define LEDC_LSTIMER0_OVF_INT_ENA (BIT(4)) +#define LEDC_LSTIMER0_OVF_INT_ENA_M (BIT(4)) +#define LEDC_LSTIMER0_OVF_INT_ENA_V 0x1 +#define LEDC_LSTIMER0_OVF_INT_ENA_S 4 +/* LEDC_HSTIMER3_OVF_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel3 counter overflow interrupt.*/ +#define LEDC_HSTIMER3_OVF_INT_ENA (BIT(3)) +#define LEDC_HSTIMER3_OVF_INT_ENA_M (BIT(3)) +#define LEDC_HSTIMER3_OVF_INT_ENA_V 0x1 +#define LEDC_HSTIMER3_OVF_INT_ENA_S 3 +/* LEDC_HSTIMER2_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel2 counter overflow interrupt.*/ +#define LEDC_HSTIMER2_OVF_INT_ENA (BIT(2)) +#define LEDC_HSTIMER2_OVF_INT_ENA_M (BIT(2)) +#define LEDC_HSTIMER2_OVF_INT_ENA_V 0x1 +#define LEDC_HSTIMER2_OVF_INT_ENA_S 2 +/* LEDC_HSTIMER1_OVF_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel1 counter overflow interrupt.*/ +#define LEDC_HSTIMER1_OVF_INT_ENA (BIT(1)) +#define LEDC_HSTIMER1_OVF_INT_ENA_M (BIT(1)) +#define LEDC_HSTIMER1_OVF_INT_ENA_V 0x1 +#define LEDC_HSTIMER1_OVF_INT_ENA_S 1 +/* LEDC_HSTIMER0_OVF_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel0 counter overflow interrupt.*/ +#define LEDC_HSTIMER0_OVF_INT_ENA (BIT(0)) +#define LEDC_HSTIMER0_OVF_INT_ENA_M (BIT(0)) +#define LEDC_HSTIMER0_OVF_INT_ENA_V 0x1 +#define LEDC_HSTIMER0_OVF_INT_ENA_S 0 + +#define LEDC_INT_CLR_REG (DR_REG_LEDC_BASE + 0x018C) +/* LEDC_DUTY_CHNG_END_LSCH7_INT_CLR : WO ;bitpos:[23] ;default: 1'h0 ; */ +/*description: Set this bit to clear low speed channel 7 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR (BIT(23)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_M (BIT(23)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_S 23 +/* LEDC_DUTY_CHNG_END_LSCH6_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel 6 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR (BIT(22)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_M (BIT(22)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_S 22 +/* LEDC_DUTY_CHNG_END_LSCH5_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel 5 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR (BIT(21)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_M (BIT(21)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_S 21 +/* LEDC_DUTY_CHNG_END_LSCH4_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel 4 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR (BIT(20)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_M (BIT(20)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_S 20 +/* LEDC_DUTY_CHNG_END_LSCH3_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel 3 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR (BIT(19)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_M (BIT(19)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_S 19 +/* LEDC_DUTY_CHNG_END_LSCH2_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel 2 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR (BIT(18)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_M (BIT(18)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_S 18 +/* LEDC_DUTY_CHNG_END_LSCH1_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel 1 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR (BIT(17)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_M (BIT(17)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_S 17 +/* LEDC_DUTY_CHNG_END_LSCH0_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel 0 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR (BIT(16)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_M (BIT(16)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_S 16 +/* LEDC_DUTY_CHNG_END_HSCH7_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel 7 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR (BIT(15)) +#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR_M (BIT(15)) +#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR_S 15 +/* LEDC_DUTY_CHNG_END_HSCH6_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel 6 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR (BIT(14)) +#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR_M (BIT(14)) +#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR_S 14 +/* LEDC_DUTY_CHNG_END_HSCH5_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel 5 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR (BIT(13)) +#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_M (BIT(13)) +#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_S 13 +/* LEDC_DUTY_CHNG_END_HSCH4_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel 4 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR (BIT(12)) +#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR_M (BIT(12)) +#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR_S 12 +/* LEDC_DUTY_CHNG_END_HSCH3_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel 3 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR (BIT(11)) +#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR_M (BIT(11)) +#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR_S 11 +/* LEDC_DUTY_CHNG_END_HSCH2_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel 2 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR (BIT(10)) +#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_M (BIT(10)) +#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_S 10 +/* LEDC_DUTY_CHNG_END_HSCH1_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel 1 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR (BIT(9)) +#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR_M (BIT(9)) +#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR_S 9 +/* LEDC_DUTY_CHNG_END_HSCH0_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel 0 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR (BIT(8)) +#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR_M (BIT(8)) +#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR_S 8 +/* LEDC_LSTIMER3_OVF_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel3 counter overflow interrupt.*/ +#define LEDC_LSTIMER3_OVF_INT_CLR (BIT(7)) +#define LEDC_LSTIMER3_OVF_INT_CLR_M (BIT(7)) +#define LEDC_LSTIMER3_OVF_INT_CLR_V 0x1 +#define LEDC_LSTIMER3_OVF_INT_CLR_S 7 +/* LEDC_LSTIMER2_OVF_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel2 counter overflow interrupt.*/ +#define LEDC_LSTIMER2_OVF_INT_CLR (BIT(6)) +#define LEDC_LSTIMER2_OVF_INT_CLR_M (BIT(6)) +#define LEDC_LSTIMER2_OVF_INT_CLR_V 0x1 +#define LEDC_LSTIMER2_OVF_INT_CLR_S 6 +/* LEDC_LSTIMER1_OVF_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel1 counter overflow interrupt.*/ +#define LEDC_LSTIMER1_OVF_INT_CLR (BIT(5)) +#define LEDC_LSTIMER1_OVF_INT_CLR_M (BIT(5)) +#define LEDC_LSTIMER1_OVF_INT_CLR_V 0x1 +#define LEDC_LSTIMER1_OVF_INT_CLR_S 5 +/* LEDC_LSTIMER0_OVF_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel0 counter overflow interrupt.*/ +#define LEDC_LSTIMER0_OVF_INT_CLR (BIT(4)) +#define LEDC_LSTIMER0_OVF_INT_CLR_M (BIT(4)) +#define LEDC_LSTIMER0_OVF_INT_CLR_V 0x1 +#define LEDC_LSTIMER0_OVF_INT_CLR_S 4 +/* LEDC_HSTIMER3_OVF_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel3 counter overflow interrupt.*/ +#define LEDC_HSTIMER3_OVF_INT_CLR (BIT(3)) +#define LEDC_HSTIMER3_OVF_INT_CLR_M (BIT(3)) +#define LEDC_HSTIMER3_OVF_INT_CLR_V 0x1 +#define LEDC_HSTIMER3_OVF_INT_CLR_S 3 +/* LEDC_HSTIMER2_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel2 counter overflow interrupt.*/ +#define LEDC_HSTIMER2_OVF_INT_CLR (BIT(2)) +#define LEDC_HSTIMER2_OVF_INT_CLR_M (BIT(2)) +#define LEDC_HSTIMER2_OVF_INT_CLR_V 0x1 +#define LEDC_HSTIMER2_OVF_INT_CLR_S 2 +/* LEDC_HSTIMER1_OVF_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel1 counter overflow interrupt.*/ +#define LEDC_HSTIMER1_OVF_INT_CLR (BIT(1)) +#define LEDC_HSTIMER1_OVF_INT_CLR_M (BIT(1)) +#define LEDC_HSTIMER1_OVF_INT_CLR_V 0x1 +#define LEDC_HSTIMER1_OVF_INT_CLR_S 1 +/* LEDC_HSTIMER0_OVF_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel0 counter overflow interrupt.*/ +#define LEDC_HSTIMER0_OVF_INT_CLR (BIT(0)) +#define LEDC_HSTIMER0_OVF_INT_CLR_M (BIT(0)) +#define LEDC_HSTIMER0_OVF_INT_CLR_V 0x1 +#define LEDC_HSTIMER0_OVF_INT_CLR_S 0 + +#define LEDC_CONF_REG (DR_REG_LEDC_BASE + 0x0190) +/* LEDC_APB_CLK_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit is used to set the frequency of slow_clk. 1'b1:80mhz 1'b0:8mhz*/ +#define LEDC_APB_CLK_SEL (BIT(0)) +#define LEDC_APB_CLK_SEL_M (BIT(0)) +#define LEDC_APB_CLK_SEL_V 0x1 +#define LEDC_APB_CLK_SEL_S 0 + +#define LEDC_DATE_REG (DR_REG_LEDC_BASE + 0x01FC) +/* LEDC_DATE : R/W ;bitpos:[31:0] ;default: 32'h16031700 ; */ +/*description: This register represents the version .*/ +#define LEDC_DATE 0xFFFFFFFF +#define LEDC_DATE_M ((LEDC_DATE_V)<<(LEDC_DATE_S)) +#define LEDC_DATE_V 0xFFFFFFFF +#define LEDC_DATE_S 0 + + + + +#endif /*_SOC_LEDC_REG_H_ */ + + diff --git a/tools/sdk/include/esp32/soc/ledc_struct.h b/tools/sdk/include/esp32/soc/ledc_struct.h new file mode 100644 index 00000000..d119289a --- /dev/null +++ b/tools/sdk/include/esp32/soc/ledc_struct.h @@ -0,0 +1,240 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_LEDC_STRUCT_H_ +#define _SOC_LEDC_STRUCT_H_ +typedef volatile struct { + struct { + struct { + union { + struct { + uint32_t timer_sel: 2; /*There are four high speed timers the two bits are used to select one of them for high speed channel. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ + uint32_t sig_out_en: 1; /*This is the output enable control bit for high speed channel*/ + uint32_t idle_lv: 1; /*This bit is used to control the output value when high speed channel is off.*/ + uint32_t reserved4: 27; + uint32_t clk_en: 1; /*This bit is clock gating control signal. when software configure LED_PWM internal registers it controls the register clock.*/ + }; + uint32_t val; + } conf0; + union { + struct { + uint32_t hpoint: 20; /*The output value changes to high when htimerx(x=[0 3]) selected by high speed channel has reached reg_hpoint_hsch0[19:0]*/ + uint32_t reserved20: 12; + }; + uint32_t val; + } hpoint; + union { + struct { + uint32_t duty: 25; /*The register is used to control output duty. When hstimerx(x=[0 3]) chosen by high speed channel has reached reg_lpoint_hsch0 the output signal changes to low. reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4]) (1) reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ + uint32_t reserved25: 7; + }; + uint32_t val; + } duty; + union { + struct { + uint32_t duty_scale:10; /*This register controls the increase or decrease step scale for high speed channel.*/ + uint32_t duty_cycle:10; /*This register is used to increase or decrease the duty every reg_duty_cycle_hsch0 cycles for high speed channel.*/ + uint32_t duty_num: 10; /*This register is used to control the number of increased or decreased times for high speed channel.*/ + uint32_t duty_inc: 1; /*This register is used to increase the duty of output signal or decrease the duty of output signal for high speed channel.*/ + uint32_t duty_start: 1; /*When reg_duty_num_hsch0 reg_duty_cycle_hsch0 and reg_duty_scale_hsch0 has been configured. these register won't take effect until set reg_duty_start_hsch0. this bit is automatically cleared by hardware.*/ + }; + uint32_t val; + } conf1; + union { + struct { + uint32_t duty_read: 25; /*This register represents the current duty of the output signal for high speed channel.*/ + uint32_t reserved25: 7; + }; + uint32_t val; + } duty_rd; + } channel[8]; + } channel_group[2]; /*two channel groups : 0: high-speed channels; 1: low-speed channels*/ + struct { + struct { + union { + struct { + uint32_t bit_num: 5; /*This register controls the range of the counter in high speed timer. the counter range is [0 2**reg_hstimer0_lim] the max bit width for counter is 20.*/ + uint32_t div_num: 18; /*This register is used to configure parameter for divider in high speed timer the least significant eight bits represent the decimal part.*/ + uint32_t pause: 1; /*This bit is used to pause the counter in high speed timer*/ + uint32_t rst: 1; /*This bit is used to reset high speed timer the counter will be 0 after reset.*/ + uint32_t tick_sel: 1; /*This bit is used to choose apb_clk or ref_tick for high speed timer. 1'b1:apb_clk 0:ref_tick*/ + uint32_t low_speed_update: 1; /*This bit is only useful for low speed timer channels, reserved for high speed timers*/ + uint32_t reserved26: 5; + }; + uint32_t val; + } conf; + union { + struct { + uint32_t timer_cnt: 20; /*software can read this register to get the current counter value in high speed timer*/ + uint32_t reserved20: 12; + }; + uint32_t val; + } value; + } timer[4]; + } timer_group[2]; /*two channel groups : 0: high-speed channels; 1: low-speed channels*/ + union { + struct { + uint32_t hstimer0_ovf: 1; /*The interrupt raw bit for high speed channel0 counter overflow.*/ + uint32_t hstimer1_ovf: 1; /*The interrupt raw bit for high speed channel1 counter overflow.*/ + uint32_t hstimer2_ovf: 1; /*The interrupt raw bit for high speed channel2 counter overflow.*/ + uint32_t hstimer3_ovf: 1; /*The interrupt raw bit for high speed channel3 counter overflow.*/ + uint32_t lstimer0_ovf: 1; /*The interrupt raw bit for low speed channel0 counter overflow.*/ + uint32_t lstimer1_ovf: 1; /*The interrupt raw bit for low speed channel1 counter overflow.*/ + uint32_t lstimer2_ovf: 1; /*The interrupt raw bit for low speed channel2 counter overflow.*/ + uint32_t lstimer3_ovf: 1; /*The interrupt raw bit for low speed channel3 counter overflow.*/ + uint32_t duty_chng_end_hsch0: 1; /*The interrupt raw bit for high speed channel 0 duty change done.*/ + uint32_t duty_chng_end_hsch1: 1; /*The interrupt raw bit for high speed channel 1 duty change done.*/ + uint32_t duty_chng_end_hsch2: 1; /*The interrupt raw bit for high speed channel 2 duty change done.*/ + uint32_t duty_chng_end_hsch3: 1; /*The interrupt raw bit for high speed channel 3 duty change done.*/ + uint32_t duty_chng_end_hsch4: 1; /*The interrupt raw bit for high speed channel 4 duty change done.*/ + uint32_t duty_chng_end_hsch5: 1; /*The interrupt raw bit for high speed channel 5 duty change done.*/ + uint32_t duty_chng_end_hsch6: 1; /*The interrupt raw bit for high speed channel 6 duty change done.*/ + uint32_t duty_chng_end_hsch7: 1; /*The interrupt raw bit for high speed channel 7 duty change done.*/ + uint32_t duty_chng_end_lsch0: 1; /*The interrupt raw bit for low speed channel 0 duty change done.*/ + uint32_t duty_chng_end_lsch1: 1; /*The interrupt raw bit for low speed channel 1 duty change done.*/ + uint32_t duty_chng_end_lsch2: 1; /*The interrupt raw bit for low speed channel 2 duty change done.*/ + uint32_t duty_chng_end_lsch3: 1; /*The interrupt raw bit for low speed channel 3 duty change done.*/ + uint32_t duty_chng_end_lsch4: 1; /*The interrupt raw bit for low speed channel 4 duty change done.*/ + uint32_t duty_chng_end_lsch5: 1; /*The interrupt raw bit for low speed channel 5 duty change done.*/ + uint32_t duty_chng_end_lsch6: 1; /*The interrupt raw bit for low speed channel 6 duty change done.*/ + uint32_t duty_chng_end_lsch7: 1; /*The interrupt raw bit for low speed channel 7 duty change done.*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t hstimer0_ovf: 1; /*The interrupt status bit for high speed channel0 counter overflow event.*/ + uint32_t hstimer1_ovf: 1; /*The interrupt status bit for high speed channel1 counter overflow event.*/ + uint32_t hstimer2_ovf: 1; /*The interrupt status bit for high speed channel2 counter overflow event.*/ + uint32_t hstimer3_ovf: 1; /*The interrupt status bit for high speed channel3 counter overflow event.*/ + uint32_t lstimer0_ovf: 1; /*The interrupt status bit for low speed channel0 counter overflow event.*/ + uint32_t lstimer1_ovf: 1; /*The interrupt status bit for low speed channel1 counter overflow event.*/ + uint32_t lstimer2_ovf: 1; /*The interrupt status bit for low speed channel2 counter overflow event.*/ + uint32_t lstimer3_ovf: 1; /*The interrupt status bit for low speed channel3 counter overflow event.*/ + uint32_t duty_chng_end_hsch1: 1; /*The interrupt status bit for high speed channel 1 duty change done event.*/ + uint32_t duty_chng_end_hsch2: 1; /*The interrupt status bit for high speed channel 2 duty change done event.*/ + uint32_t duty_chng_end_hsch3: 1; /*The interrupt status bit for high speed channel 3 duty change done event.*/ + uint32_t duty_chng_end_hsch4: 1; /*The interrupt status bit for high speed channel 4 duty change done event.*/ + uint32_t duty_chng_end_hsch5: 1; /*The interrupt status bit for high speed channel 5 duty change done event.*/ + uint32_t duty_chng_end_hsch6: 1; /*The interrupt status bit for high speed channel 6 duty change done event.*/ + uint32_t duty_chng_end_hsch7: 1; /*The interrupt status bit for high speed channel 7 duty change done event.*/ + uint32_t duty_chng_end_lsch0: 1; /*The interrupt status bit for low speed channel 0 duty change done event.*/ + uint32_t duty_chng_end_lsch1: 1; /*The interrupt status bit for low speed channel 1 duty change done event.*/ + uint32_t duty_chng_end_lsch2: 1; /*The interrupt status bit for low speed channel 2 duty change done event.*/ + uint32_t duty_chng_end_lsch3: 1; /*The interrupt status bit for low speed channel 3 duty change done event.*/ + uint32_t duty_chng_end_lsch4: 1; /*The interrupt status bit for low speed channel 4 duty change done event.*/ + uint32_t duty_chng_end_lsch5: 1; /*The interrupt status bit for low speed channel 5 duty change done event.*/ + uint32_t duty_chng_end_lsch6: 1; /*The interrupt status bit for low speed channel 6 duty change done event.*/ + uint32_t duty_chng_end_lsch7: 1; /*The interrupt status bit for low speed channel 7 duty change done event*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t hstimer0_ovf: 1; /*The interrupt enable bit for high speed channel0 counter overflow interrupt.*/ + uint32_t hstimer1_ovf: 1; /*The interrupt enable bit for high speed channel1 counter overflow interrupt.*/ + uint32_t hstimer2_ovf: 1; /*The interrupt enable bit for high speed channel2 counter overflow interrupt.*/ + uint32_t hstimer3_ovf: 1; /*The interrupt enable bit for high speed channel3 counter overflow interrupt.*/ + uint32_t lstimer0_ovf: 1; /*The interrupt enable bit for low speed channel0 counter overflow interrupt.*/ + uint32_t lstimer1_ovf: 1; /*The interrupt enable bit for low speed channel1 counter overflow interrupt.*/ + uint32_t lstimer2_ovf: 1; /*The interrupt enable bit for low speed channel2 counter overflow interrupt.*/ + uint32_t lstimer3_ovf: 1; /*The interrupt enable bit for low speed channel3 counter overflow interrupt.*/ + uint32_t duty_chng_end_hsch0: 1; /*The interrupt enable bit for high speed channel 0 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch1: 1; /*The interrupt enable bit for high speed channel 1 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch2: 1; /*The interrupt enable bit for high speed channel 2 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch3: 1; /*The interrupt enable bit for high speed channel 3 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch4: 1; /*The interrupt enable bit for high speed channel 4 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch5: 1; /*The interrupt enable bit for high speed channel 5 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch6: 1; /*The interrupt enable bit for high speed channel 6 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch7: 1; /*The interrupt enable bit for high speed channel 7 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch0: 1; /*The interrupt enable bit for low speed channel 0 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch1: 1; /*The interrupt enable bit for low speed channel 1 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch2: 1; /*The interrupt enable bit for low speed channel 2 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch3: 1; /*The interrupt enable bit for low speed channel 3 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch4: 1; /*The interrupt enable bit for low speed channel 4 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch5: 1; /*The interrupt enable bit for low speed channel 5 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch6: 1; /*The interrupt enable bit for low speed channel 6 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch7: 1; /*The interrupt enable bit for low speed channel 7 duty change done interrupt.*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t hstimer0_ovf: 1; /*Set this bit to clear high speed channel0 counter overflow interrupt.*/ + uint32_t hstimer1_ovf: 1; /*Set this bit to clear high speed channel1 counter overflow interrupt.*/ + uint32_t hstimer2_ovf: 1; /*Set this bit to clear high speed channel2 counter overflow interrupt.*/ + uint32_t hstimer3_ovf: 1; /*Set this bit to clear high speed channel3 counter overflow interrupt.*/ + uint32_t lstimer0_ovf: 1; /*Set this bit to clear low speed channel0 counter overflow interrupt.*/ + uint32_t lstimer1_ovf: 1; /*Set this bit to clear low speed channel1 counter overflow interrupt.*/ + uint32_t lstimer2_ovf: 1; /*Set this bit to clear low speed channel2 counter overflow interrupt.*/ + uint32_t lstimer3_ovf: 1; /*Set this bit to clear low speed channel3 counter overflow interrupt.*/ + uint32_t duty_chng_end_hsch0: 1; /*Set this bit to clear high speed channel 0 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch1: 1; /*Set this bit to clear high speed channel 1 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch2: 1; /*Set this bit to clear high speed channel 2 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch3: 1; /*Set this bit to clear high speed channel 3 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch4: 1; /*Set this bit to clear high speed channel 4 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch5: 1; /*Set this bit to clear high speed channel 5 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch6: 1; /*Set this bit to clear high speed channel 6 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch7: 1; /*Set this bit to clear high speed channel 7 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch0: 1; /*Set this bit to clear low speed channel 0 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch1: 1; /*Set this bit to clear low speed channel 1 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch2: 1; /*Set this bit to clear low speed channel 2 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch3: 1; /*Set this bit to clear low speed channel 3 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch4: 1; /*Set this bit to clear low speed channel 4 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch5: 1; /*Set this bit to clear low speed channel 5 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch6: 1; /*Set this bit to clear low speed channel 6 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch7: 1; /*Set this bit to clear low speed channel 7 duty change done interrupt.*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t apb_clk_sel: 1; /*This bit is used to set the frequency of slow_clk. 1'b1:80mhz 1'b0:8mhz*/ + uint32_t reserved1: 31; + }; + uint32_t val; + } conf; + uint32_t reserved_194; + uint32_t reserved_198; + uint32_t reserved_19c; + uint32_t reserved_1a0; + uint32_t reserved_1a4; + uint32_t reserved_1a8; + uint32_t reserved_1ac; + uint32_t reserved_1b0; + uint32_t reserved_1b4; + uint32_t reserved_1b8; + uint32_t reserved_1bc; + uint32_t reserved_1c0; + uint32_t reserved_1c4; + uint32_t reserved_1c8; + uint32_t reserved_1cc; + uint32_t reserved_1d0; + uint32_t reserved_1d4; + uint32_t reserved_1d8; + uint32_t reserved_1dc; + uint32_t reserved_1e0; + uint32_t reserved_1e4; + uint32_t reserved_1e8; + uint32_t reserved_1ec; + uint32_t reserved_1f0; + uint32_t reserved_1f4; + uint32_t reserved_1f8; + uint32_t date; /*This register represents the version .*/ +} ledc_dev_t; +extern ledc_dev_t LEDC; +#endif /* _SOC_LEDC_STRUCT_H_ */ diff --git a/tools/sdk/include/esp32/soc/pcnt_reg.h b/tools/sdk/include/esp32/soc/pcnt_reg.h new file mode 100644 index 00000000..7a3a78bf --- /dev/null +++ b/tools/sdk/include/esp32/soc/pcnt_reg.h @@ -0,0 +1,1496 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_PCNT_REG_H_ +#define _SOC_PCNT_REG_H_ + + +#include "soc.h" +#define PCNT_U0_CONF0_REG (DR_REG_PCNT_BASE + 0x0000) +/* PCNT_CH1_LCTRL_MODE_U0 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's low control + signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_LCTRL_MODE_U0 0x00000003 +#define PCNT_CH1_LCTRL_MODE_U0_M ((PCNT_CH1_LCTRL_MODE_U0_V)<<(PCNT_CH1_LCTRL_MODE_U0_S)) +#define PCNT_CH1_LCTRL_MODE_U0_V 0x3 +#define PCNT_CH1_LCTRL_MODE_U0_S 30 +/* PCNT_CH1_HCTRL_MODE_U0 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's high + control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_HCTRL_MODE_U0 0x00000003 +#define PCNT_CH1_HCTRL_MODE_U0_M ((PCNT_CH1_HCTRL_MODE_U0_V)<<(PCNT_CH1_HCTRL_MODE_U0_S)) +#define PCNT_CH1_HCTRL_MODE_U0_V 0x3 +#define PCNT_CH1_HCTRL_MODE_U0_S 28 +/* PCNT_CH1_POS_MODE_U0 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + posedge signal for unit0. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH1_POS_MODE_U0 0x00000003 +#define PCNT_CH1_POS_MODE_U0_M ((PCNT_CH1_POS_MODE_U0_V)<<(PCNT_CH1_POS_MODE_U0_S)) +#define PCNT_CH1_POS_MODE_U0_V 0x3 +#define PCNT_CH1_POS_MODE_U0_S 26 +/* PCNT_CH1_NEG_MODE_U0 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + negedge signal for unit0. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH1_NEG_MODE_U0 0x00000003 +#define PCNT_CH1_NEG_MODE_U0_M ((PCNT_CH1_NEG_MODE_U0_V)<<(PCNT_CH1_NEG_MODE_U0_S)) +#define PCNT_CH1_NEG_MODE_U0_V 0x3 +#define PCNT_CH1_NEG_MODE_U0_S 24 +/* PCNT_CH0_LCTRL_MODE_U0 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's low control + signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_LCTRL_MODE_U0 0x00000003 +#define PCNT_CH0_LCTRL_MODE_U0_M ((PCNT_CH0_LCTRL_MODE_U0_V)<<(PCNT_CH0_LCTRL_MODE_U0_S)) +#define PCNT_CH0_LCTRL_MODE_U0_V 0x3 +#define PCNT_CH0_LCTRL_MODE_U0_S 22 +/* PCNT_CH0_HCTRL_MODE_U0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's high + control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_HCTRL_MODE_U0 0x00000003 +#define PCNT_CH0_HCTRL_MODE_U0_M ((PCNT_CH0_HCTRL_MODE_U0_V)<<(PCNT_CH0_HCTRL_MODE_U0_S)) +#define PCNT_CH0_HCTRL_MODE_U0_V 0x3 +#define PCNT_CH0_HCTRL_MODE_U0_S 20 +/* PCNT_CH0_POS_MODE_U0 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + posedge signal for unit0. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH0_POS_MODE_U0 0x00000003 +#define PCNT_CH0_POS_MODE_U0_M ((PCNT_CH0_POS_MODE_U0_V)<<(PCNT_CH0_POS_MODE_U0_S)) +#define PCNT_CH0_POS_MODE_U0_V 0x3 +#define PCNT_CH0_POS_MODE_U0_S 18 +/* PCNT_CH0_NEG_MODE_U0 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + negedge signal for unit0. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH0_NEG_MODE_U0 0x00000003 +#define PCNT_CH0_NEG_MODE_U0_M ((PCNT_CH0_NEG_MODE_U0_V)<<(PCNT_CH0_NEG_MODE_U0_S)) +#define PCNT_CH0_NEG_MODE_U0_V 0x3 +#define PCNT_CH0_NEG_MODE_U0_S 16 +/* PCNT_THR_THRES1_EN_U0 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit0's count with thres1 value .*/ +#define PCNT_THR_THRES1_EN_U0 (BIT(15)) +#define PCNT_THR_THRES1_EN_U0_M (BIT(15)) +#define PCNT_THR_THRES1_EN_U0_V 0x1 +#define PCNT_THR_THRES1_EN_U0_S 15 +/* PCNT_THR_THRES0_EN_U0 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit0's count with thres0 value.*/ +#define PCNT_THR_THRES0_EN_U0 (BIT(14)) +#define PCNT_THR_THRES0_EN_U0_M (BIT(14)) +#define PCNT_THR_THRES0_EN_U0_V 0x1 +#define PCNT_THR_THRES0_EN_U0_S 14 +/* PCNT_THR_L_LIM_EN_U0 : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit0's count with thr_l_lim value.*/ +#define PCNT_THR_L_LIM_EN_U0 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U0_M (BIT(13)) +#define PCNT_THR_L_LIM_EN_U0_V 0x1 +#define PCNT_THR_L_LIM_EN_U0_S 13 +/* PCNT_THR_H_LIM_EN_U0 : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit0's count with thr_h_lim value.*/ +#define PCNT_THR_H_LIM_EN_U0 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U0_M (BIT(12)) +#define PCNT_THR_H_LIM_EN_U0_V 0x1 +#define PCNT_THR_H_LIM_EN_U0_S 12 +/* PCNT_THR_ZERO_EN_U0 : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit0's count with 0 value.*/ +#define PCNT_THR_ZERO_EN_U0 (BIT(11)) +#define PCNT_THR_ZERO_EN_U0_M (BIT(11)) +#define PCNT_THR_ZERO_EN_U0_V 0x1 +#define PCNT_THR_ZERO_EN_U0_S 11 +/* PCNT_FILTER_EN_U0 : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: This is the enable bit for filtering input signals for unit0.*/ +#define PCNT_FILTER_EN_U0 (BIT(10)) +#define PCNT_FILTER_EN_U0_M (BIT(10)) +#define PCNT_FILTER_EN_U0_V 0x1 +#define PCNT_FILTER_EN_U0_S 10 +/* PCNT_FILTER_THRES_U0 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ +/*description: This register is used to filter pluse whose width is smaller + than this value for unit0.*/ +#define PCNT_FILTER_THRES_U0 0x000003FF +#define PCNT_FILTER_THRES_U0_M ((PCNT_FILTER_THRES_U0_V)<<(PCNT_FILTER_THRES_U0_S)) +#define PCNT_FILTER_THRES_U0_V 0x3FF +#define PCNT_FILTER_THRES_U0_S 0 + +#define PCNT_U0_CONF1_REG (DR_REG_PCNT_BASE + 0x0004) +/* PCNT_CNT_THRES1_U0 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to configure thres1 value for unit0.*/ +#define PCNT_CNT_THRES1_U0 0x0000FFFF +#define PCNT_CNT_THRES1_U0_M ((PCNT_CNT_THRES1_U0_V)<<(PCNT_CNT_THRES1_U0_S)) +#define PCNT_CNT_THRES1_U0_V 0xFFFF +#define PCNT_CNT_THRES1_U0_S 16 +/* PCNT_CNT_THRES0_U0 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thres0 value for unit0.*/ +#define PCNT_CNT_THRES0_U0 0x0000FFFF +#define PCNT_CNT_THRES0_U0_M ((PCNT_CNT_THRES0_U0_V)<<(PCNT_CNT_THRES0_U0_S)) +#define PCNT_CNT_THRES0_U0_V 0xFFFF +#define PCNT_CNT_THRES0_U0_S 0 + +#define PCNT_U0_CONF2_REG (DR_REG_PCNT_BASE + 0x0008) +/* PCNT_CNT_L_LIM_U0 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to confiugre thr_l_lim value for unit0.*/ +#define PCNT_CNT_L_LIM_U0 0x0000FFFF +#define PCNT_CNT_L_LIM_U0_M ((PCNT_CNT_L_LIM_U0_V)<<(PCNT_CNT_L_LIM_U0_S)) +#define PCNT_CNT_L_LIM_U0_V 0xFFFF +#define PCNT_CNT_L_LIM_U0_S 16 +/* PCNT_CNT_H_LIM_U0 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thr_h_lim value for unit0.*/ +#define PCNT_CNT_H_LIM_U0 0x0000FFFF +#define PCNT_CNT_H_LIM_U0_M ((PCNT_CNT_H_LIM_U0_V)<<(PCNT_CNT_H_LIM_U0_S)) +#define PCNT_CNT_H_LIM_U0_V 0xFFFF +#define PCNT_CNT_H_LIM_U0_S 0 + +#define PCNT_U1_CONF0_REG (DR_REG_PCNT_BASE + 0x000c) +/* PCNT_CH1_LCTRL_MODE_U1 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's low control + signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_LCTRL_MODE_U1 0x00000003 +#define PCNT_CH1_LCTRL_MODE_U1_M ((PCNT_CH1_LCTRL_MODE_U1_V)<<(PCNT_CH1_LCTRL_MODE_U1_S)) +#define PCNT_CH1_LCTRL_MODE_U1_V 0x3 +#define PCNT_CH1_LCTRL_MODE_U1_S 30 +/* PCNT_CH1_HCTRL_MODE_U1 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's high + control signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_HCTRL_MODE_U1 0x00000003 +#define PCNT_CH1_HCTRL_MODE_U1_M ((PCNT_CH1_HCTRL_MODE_U1_V)<<(PCNT_CH1_HCTRL_MODE_U1_S)) +#define PCNT_CH1_HCTRL_MODE_U1_V 0x3 +#define PCNT_CH1_HCTRL_MODE_U1_S 28 +/* PCNT_CH1_POS_MODE_U1 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + posedge signal for unit1. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH1_POS_MODE_U1 0x00000003 +#define PCNT_CH1_POS_MODE_U1_M ((PCNT_CH1_POS_MODE_U1_V)<<(PCNT_CH1_POS_MODE_U1_S)) +#define PCNT_CH1_POS_MODE_U1_V 0x3 +#define PCNT_CH1_POS_MODE_U1_S 26 +/* PCNT_CH1_NEG_MODE_U1 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + negedge signal for unit1. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH1_NEG_MODE_U1 0x00000003 +#define PCNT_CH1_NEG_MODE_U1_M ((PCNT_CH1_NEG_MODE_U1_V)<<(PCNT_CH1_NEG_MODE_U1_S)) +#define PCNT_CH1_NEG_MODE_U1_V 0x3 +#define PCNT_CH1_NEG_MODE_U1_S 24 +/* PCNT_CH0_LCTRL_MODE_U1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's low control + signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_LCTRL_MODE_U1 0x00000003 +#define PCNT_CH0_LCTRL_MODE_U1_M ((PCNT_CH0_LCTRL_MODE_U1_V)<<(PCNT_CH0_LCTRL_MODE_U1_S)) +#define PCNT_CH0_LCTRL_MODE_U1_V 0x3 +#define PCNT_CH0_LCTRL_MODE_U1_S 22 +/* PCNT_CH0_HCTRL_MODE_U1 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's high + control signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_HCTRL_MODE_U1 0x00000003 +#define PCNT_CH0_HCTRL_MODE_U1_M ((PCNT_CH0_HCTRL_MODE_U1_V)<<(PCNT_CH0_HCTRL_MODE_U1_S)) +#define PCNT_CH0_HCTRL_MODE_U1_V 0x3 +#define PCNT_CH0_HCTRL_MODE_U1_S 20 +/* PCNT_CH0_POS_MODE_U1 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + posedge signal for unit1. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH0_POS_MODE_U1 0x00000003 +#define PCNT_CH0_POS_MODE_U1_M ((PCNT_CH0_POS_MODE_U1_V)<<(PCNT_CH0_POS_MODE_U1_S)) +#define PCNT_CH0_POS_MODE_U1_V 0x3 +#define PCNT_CH0_POS_MODE_U1_S 18 +/* PCNT_CH0_NEG_MODE_U1 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + negedge signal for unit1. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH0_NEG_MODE_U1 0x00000003 +#define PCNT_CH0_NEG_MODE_U1_M ((PCNT_CH0_NEG_MODE_U1_V)<<(PCNT_CH0_NEG_MODE_U1_S)) +#define PCNT_CH0_NEG_MODE_U1_V 0x3 +#define PCNT_CH0_NEG_MODE_U1_S 16 +/* PCNT_THR_THRES1_EN_U1 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit1's count with thres1 value .*/ +#define PCNT_THR_THRES1_EN_U1 (BIT(15)) +#define PCNT_THR_THRES1_EN_U1_M (BIT(15)) +#define PCNT_THR_THRES1_EN_U1_V 0x1 +#define PCNT_THR_THRES1_EN_U1_S 15 +/* PCNT_THR_THRES0_EN_U1 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit1's count with thres0 value.*/ +#define PCNT_THR_THRES0_EN_U1 (BIT(14)) +#define PCNT_THR_THRES0_EN_U1_M (BIT(14)) +#define PCNT_THR_THRES0_EN_U1_V 0x1 +#define PCNT_THR_THRES0_EN_U1_S 14 +/* PCNT_THR_L_LIM_EN_U1 : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit1's count with thr_l_lim value.*/ +#define PCNT_THR_L_LIM_EN_U1 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U1_M (BIT(13)) +#define PCNT_THR_L_LIM_EN_U1_V 0x1 +#define PCNT_THR_L_LIM_EN_U1_S 13 +/* PCNT_THR_H_LIM_EN_U1 : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit1's count with thr_h_lim value.*/ +#define PCNT_THR_H_LIM_EN_U1 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U1_M (BIT(12)) +#define PCNT_THR_H_LIM_EN_U1_V 0x1 +#define PCNT_THR_H_LIM_EN_U1_S 12 +/* PCNT_THR_ZERO_EN_U1 : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit1's count with 0 value.*/ +#define PCNT_THR_ZERO_EN_U1 (BIT(11)) +#define PCNT_THR_ZERO_EN_U1_M (BIT(11)) +#define PCNT_THR_ZERO_EN_U1_V 0x1 +#define PCNT_THR_ZERO_EN_U1_S 11 +/* PCNT_FILTER_EN_U1 : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: This is the enable bit for filtering input signals for unit1.*/ +#define PCNT_FILTER_EN_U1 (BIT(10)) +#define PCNT_FILTER_EN_U1_M (BIT(10)) +#define PCNT_FILTER_EN_U1_V 0x1 +#define PCNT_FILTER_EN_U1_S 10 +/* PCNT_FILTER_THRES_U1 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ +/*description: This register is used to filter pluse whose width is smaller + than this value for unit1.*/ +#define PCNT_FILTER_THRES_U1 0x000003FF +#define PCNT_FILTER_THRES_U1_M ((PCNT_FILTER_THRES_U1_V)<<(PCNT_FILTER_THRES_U1_S)) +#define PCNT_FILTER_THRES_U1_V 0x3FF +#define PCNT_FILTER_THRES_U1_S 0 + +#define PCNT_U1_CONF1_REG (DR_REG_PCNT_BASE + 0x0010) +/* PCNT_CNT_THRES1_U1 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to configure thres1 value for unit1.*/ +#define PCNT_CNT_THRES1_U1 0x0000FFFF +#define PCNT_CNT_THRES1_U1_M ((PCNT_CNT_THRES1_U1_V)<<(PCNT_CNT_THRES1_U1_S)) +#define PCNT_CNT_THRES1_U1_V 0xFFFF +#define PCNT_CNT_THRES1_U1_S 16 +/* PCNT_CNT_THRES0_U1 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thres0 value for unit1.*/ +#define PCNT_CNT_THRES0_U1 0x0000FFFF +#define PCNT_CNT_THRES0_U1_M ((PCNT_CNT_THRES0_U1_V)<<(PCNT_CNT_THRES0_U1_S)) +#define PCNT_CNT_THRES0_U1_V 0xFFFF +#define PCNT_CNT_THRES0_U1_S 0 + +#define PCNT_U1_CONF2_REG (DR_REG_PCNT_BASE + 0x0014) +/* PCNT_CNT_L_LIM_U1 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to confiugre thr_l_lim value for unit1.*/ +#define PCNT_CNT_L_LIM_U1 0x0000FFFF +#define PCNT_CNT_L_LIM_U1_M ((PCNT_CNT_L_LIM_U1_V)<<(PCNT_CNT_L_LIM_U1_S)) +#define PCNT_CNT_L_LIM_U1_V 0xFFFF +#define PCNT_CNT_L_LIM_U1_S 16 +/* PCNT_CNT_H_LIM_U1 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thr_h_lim value for unit1.*/ +#define PCNT_CNT_H_LIM_U1 0x0000FFFF +#define PCNT_CNT_H_LIM_U1_M ((PCNT_CNT_H_LIM_U1_V)<<(PCNT_CNT_H_LIM_U1_S)) +#define PCNT_CNT_H_LIM_U1_V 0xFFFF +#define PCNT_CNT_H_LIM_U1_S 0 + +#define PCNT_U2_CONF0_REG (DR_REG_PCNT_BASE + 0x0018) +/* PCNT_CH1_LCTRL_MODE_U2 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's low control + signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_LCTRL_MODE_U2 0x00000003 +#define PCNT_CH1_LCTRL_MODE_U2_M ((PCNT_CH1_LCTRL_MODE_U2_V)<<(PCNT_CH1_LCTRL_MODE_U2_S)) +#define PCNT_CH1_LCTRL_MODE_U2_V 0x3 +#define PCNT_CH1_LCTRL_MODE_U2_S 30 +/* PCNT_CH1_HCTRL_MODE_U2 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's high + control signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_HCTRL_MODE_U2 0x00000003 +#define PCNT_CH1_HCTRL_MODE_U2_M ((PCNT_CH1_HCTRL_MODE_U2_V)<<(PCNT_CH1_HCTRL_MODE_U2_S)) +#define PCNT_CH1_HCTRL_MODE_U2_V 0x3 +#define PCNT_CH1_HCTRL_MODE_U2_S 28 +/* PCNT_CH1_POS_MODE_U2 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + posedge signal for unit2. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH1_POS_MODE_U2 0x00000003 +#define PCNT_CH1_POS_MODE_U2_M ((PCNT_CH1_POS_MODE_U2_V)<<(PCNT_CH1_POS_MODE_U2_S)) +#define PCNT_CH1_POS_MODE_U2_V 0x3 +#define PCNT_CH1_POS_MODE_U2_S 26 +/* PCNT_CH1_NEG_MODE_U2 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + negedge signal for unit2. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH1_NEG_MODE_U2 0x00000003 +#define PCNT_CH1_NEG_MODE_U2_M ((PCNT_CH1_NEG_MODE_U2_V)<<(PCNT_CH1_NEG_MODE_U2_S)) +#define PCNT_CH1_NEG_MODE_U2_V 0x3 +#define PCNT_CH1_NEG_MODE_U2_S 24 +/* PCNT_CH0_LCTRL_MODE_U2 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's low control + signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_LCTRL_MODE_U2 0x00000003 +#define PCNT_CH0_LCTRL_MODE_U2_M ((PCNT_CH0_LCTRL_MODE_U2_V)<<(PCNT_CH0_LCTRL_MODE_U2_S)) +#define PCNT_CH0_LCTRL_MODE_U2_V 0x3 +#define PCNT_CH0_LCTRL_MODE_U2_S 22 +/* PCNT_CH0_HCTRL_MODE_U2 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's high + control signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_HCTRL_MODE_U2 0x00000003 +#define PCNT_CH0_HCTRL_MODE_U2_M ((PCNT_CH0_HCTRL_MODE_U2_V)<<(PCNT_CH0_HCTRL_MODE_U2_S)) +#define PCNT_CH0_HCTRL_MODE_U2_V 0x3 +#define PCNT_CH0_HCTRL_MODE_U2_S 20 +/* PCNT_CH0_POS_MODE_U2 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + posedge signal for unit2. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH0_POS_MODE_U2 0x00000003 +#define PCNT_CH0_POS_MODE_U2_M ((PCNT_CH0_POS_MODE_U2_V)<<(PCNT_CH0_POS_MODE_U2_S)) +#define PCNT_CH0_POS_MODE_U2_V 0x3 +#define PCNT_CH0_POS_MODE_U2_S 18 +/* PCNT_CH0_NEG_MODE_U2 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + negedge signal for unit2. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH0_NEG_MODE_U2 0x00000003 +#define PCNT_CH0_NEG_MODE_U2_M ((PCNT_CH0_NEG_MODE_U2_V)<<(PCNT_CH0_NEG_MODE_U2_S)) +#define PCNT_CH0_NEG_MODE_U2_V 0x3 +#define PCNT_CH0_NEG_MODE_U2_S 16 +/* PCNT_THR_THRES1_EN_U2 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit2's count with thres1 value .*/ +#define PCNT_THR_THRES1_EN_U2 (BIT(15)) +#define PCNT_THR_THRES1_EN_U2_M (BIT(15)) +#define PCNT_THR_THRES1_EN_U2_V 0x1 +#define PCNT_THR_THRES1_EN_U2_S 15 +/* PCNT_THR_THRES0_EN_U2 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit2's count with thres0 value.*/ +#define PCNT_THR_THRES0_EN_U2 (BIT(14)) +#define PCNT_THR_THRES0_EN_U2_M (BIT(14)) +#define PCNT_THR_THRES0_EN_U2_V 0x1 +#define PCNT_THR_THRES0_EN_U2_S 14 +/* PCNT_THR_L_LIM_EN_U2 : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit2's count with thr_l_lim value.*/ +#define PCNT_THR_L_LIM_EN_U2 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U2_M (BIT(13)) +#define PCNT_THR_L_LIM_EN_U2_V 0x1 +#define PCNT_THR_L_LIM_EN_U2_S 13 +/* PCNT_THR_H_LIM_EN_U2 : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit2's count with thr_h_lim value.*/ +#define PCNT_THR_H_LIM_EN_U2 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U2_M (BIT(12)) +#define PCNT_THR_H_LIM_EN_U2_V 0x1 +#define PCNT_THR_H_LIM_EN_U2_S 12 +/* PCNT_THR_ZERO_EN_U2 : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit2's count with 0 value.*/ +#define PCNT_THR_ZERO_EN_U2 (BIT(11)) +#define PCNT_THR_ZERO_EN_U2_M (BIT(11)) +#define PCNT_THR_ZERO_EN_U2_V 0x1 +#define PCNT_THR_ZERO_EN_U2_S 11 +/* PCNT_FILTER_EN_U2 : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: This is the enable bit for filtering input signals for unit2.*/ +#define PCNT_FILTER_EN_U2 (BIT(10)) +#define PCNT_FILTER_EN_U2_M (BIT(10)) +#define PCNT_FILTER_EN_U2_V 0x1 +#define PCNT_FILTER_EN_U2_S 10 +/* PCNT_FILTER_THRES_U2 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ +/*description: This register is used to filter pluse whose width is smaller + than this value for unit2.*/ +#define PCNT_FILTER_THRES_U2 0x000003FF +#define PCNT_FILTER_THRES_U2_M ((PCNT_FILTER_THRES_U2_V)<<(PCNT_FILTER_THRES_U2_S)) +#define PCNT_FILTER_THRES_U2_V 0x3FF +#define PCNT_FILTER_THRES_U2_S 0 + +#define PCNT_U2_CONF1_REG (DR_REG_PCNT_BASE + 0x001c) +/* PCNT_CNT_THRES1_U2 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to configure thres1 value for unit2.*/ +#define PCNT_CNT_THRES1_U2 0x0000FFFF +#define PCNT_CNT_THRES1_U2_M ((PCNT_CNT_THRES1_U2_V)<<(PCNT_CNT_THRES1_U2_S)) +#define PCNT_CNT_THRES1_U2_V 0xFFFF +#define PCNT_CNT_THRES1_U2_S 16 +/* PCNT_CNT_THRES0_U2 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thres0 value for unit2.*/ +#define PCNT_CNT_THRES0_U2 0x0000FFFF +#define PCNT_CNT_THRES0_U2_M ((PCNT_CNT_THRES0_U2_V)<<(PCNT_CNT_THRES0_U2_S)) +#define PCNT_CNT_THRES0_U2_V 0xFFFF +#define PCNT_CNT_THRES0_U2_S 0 + +#define PCNT_U2_CONF2_REG (DR_REG_PCNT_BASE + 0x0020) +/* PCNT_CNT_L_LIM_U2 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to confiugre thr_l_lim value for unit2.*/ +#define PCNT_CNT_L_LIM_U2 0x0000FFFF +#define PCNT_CNT_L_LIM_U2_M ((PCNT_CNT_L_LIM_U2_V)<<(PCNT_CNT_L_LIM_U2_S)) +#define PCNT_CNT_L_LIM_U2_V 0xFFFF +#define PCNT_CNT_L_LIM_U2_S 16 +/* PCNT_CNT_H_LIM_U2 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thr_h_lim value for unit2.*/ +#define PCNT_CNT_H_LIM_U2 0x0000FFFF +#define PCNT_CNT_H_LIM_U2_M ((PCNT_CNT_H_LIM_U2_V)<<(PCNT_CNT_H_LIM_U2_S)) +#define PCNT_CNT_H_LIM_U2_V 0xFFFF +#define PCNT_CNT_H_LIM_U2_S 0 + +#define PCNT_U3_CONF0_REG (DR_REG_PCNT_BASE + 0x0024) +/* PCNT_CH1_LCTRL_MODE_U3 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's low control + signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_LCTRL_MODE_U3 0x00000003 +#define PCNT_CH1_LCTRL_MODE_U3_M ((PCNT_CH1_LCTRL_MODE_U3_V)<<(PCNT_CH1_LCTRL_MODE_U3_S)) +#define PCNT_CH1_LCTRL_MODE_U3_V 0x3 +#define PCNT_CH1_LCTRL_MODE_U3_S 30 +/* PCNT_CH1_HCTRL_MODE_U3 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's high + control signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_HCTRL_MODE_U3 0x00000003 +#define PCNT_CH1_HCTRL_MODE_U3_M ((PCNT_CH1_HCTRL_MODE_U3_V)<<(PCNT_CH1_HCTRL_MODE_U3_S)) +#define PCNT_CH1_HCTRL_MODE_U3_V 0x3 +#define PCNT_CH1_HCTRL_MODE_U3_S 28 +/* PCNT_CH1_POS_MODE_U3 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + posedge signal for unit3. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH1_POS_MODE_U3 0x00000003 +#define PCNT_CH1_POS_MODE_U3_M ((PCNT_CH1_POS_MODE_U3_V)<<(PCNT_CH1_POS_MODE_U3_S)) +#define PCNT_CH1_POS_MODE_U3_V 0x3 +#define PCNT_CH1_POS_MODE_U3_S 26 +/* PCNT_CH1_NEG_MODE_U3 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + negedge signal for unit3. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH1_NEG_MODE_U3 0x00000003 +#define PCNT_CH1_NEG_MODE_U3_M ((PCNT_CH1_NEG_MODE_U3_V)<<(PCNT_CH1_NEG_MODE_U3_S)) +#define PCNT_CH1_NEG_MODE_U3_V 0x3 +#define PCNT_CH1_NEG_MODE_U3_S 24 +/* PCNT_CH0_LCTRL_MODE_U3 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's low control + signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_LCTRL_MODE_U3 0x00000003 +#define PCNT_CH0_LCTRL_MODE_U3_M ((PCNT_CH0_LCTRL_MODE_U3_V)<<(PCNT_CH0_LCTRL_MODE_U3_S)) +#define PCNT_CH0_LCTRL_MODE_U3_V 0x3 +#define PCNT_CH0_LCTRL_MODE_U3_S 22 +/* PCNT_CH0_HCTRL_MODE_U3 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's high + control signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_HCTRL_MODE_U3 0x00000003 +#define PCNT_CH0_HCTRL_MODE_U3_M ((PCNT_CH0_HCTRL_MODE_U3_V)<<(PCNT_CH0_HCTRL_MODE_U3_S)) +#define PCNT_CH0_HCTRL_MODE_U3_V 0x3 +#define PCNT_CH0_HCTRL_MODE_U3_S 20 +/* PCNT_CH0_POS_MODE_U3 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + posedge signal for unit3. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH0_POS_MODE_U3 0x00000003 +#define PCNT_CH0_POS_MODE_U3_M ((PCNT_CH0_POS_MODE_U3_V)<<(PCNT_CH0_POS_MODE_U3_S)) +#define PCNT_CH0_POS_MODE_U3_V 0x3 +#define PCNT_CH0_POS_MODE_U3_S 18 +/* PCNT_CH0_NEG_MODE_U3 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + negedge signal for unit3. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH0_NEG_MODE_U3 0x00000003 +#define PCNT_CH0_NEG_MODE_U3_M ((PCNT_CH0_NEG_MODE_U3_V)<<(PCNT_CH0_NEG_MODE_U3_S)) +#define PCNT_CH0_NEG_MODE_U3_V 0x3 +#define PCNT_CH0_NEG_MODE_U3_S 16 +/* PCNT_THR_THRES1_EN_U3 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit3's count with thres1 value .*/ +#define PCNT_THR_THRES1_EN_U3 (BIT(15)) +#define PCNT_THR_THRES1_EN_U3_M (BIT(15)) +#define PCNT_THR_THRES1_EN_U3_V 0x1 +#define PCNT_THR_THRES1_EN_U3_S 15 +/* PCNT_THR_THRES0_EN_U3 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit3's count with thres0 value.*/ +#define PCNT_THR_THRES0_EN_U3 (BIT(14)) +#define PCNT_THR_THRES0_EN_U3_M (BIT(14)) +#define PCNT_THR_THRES0_EN_U3_V 0x1 +#define PCNT_THR_THRES0_EN_U3_S 14 +/* PCNT_THR_L_LIM_EN_U3 : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit3's count with thr_l_lim value.*/ +#define PCNT_THR_L_LIM_EN_U3 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U3_M (BIT(13)) +#define PCNT_THR_L_LIM_EN_U3_V 0x1 +#define PCNT_THR_L_LIM_EN_U3_S 13 +/* PCNT_THR_H_LIM_EN_U3 : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit3's count with thr_h_lim value.*/ +#define PCNT_THR_H_LIM_EN_U3 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U3_M (BIT(12)) +#define PCNT_THR_H_LIM_EN_U3_V 0x1 +#define PCNT_THR_H_LIM_EN_U3_S 12 +/* PCNT_THR_ZERO_EN_U3 : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit3's count with 0 value.*/ +#define PCNT_THR_ZERO_EN_U3 (BIT(11)) +#define PCNT_THR_ZERO_EN_U3_M (BIT(11)) +#define PCNT_THR_ZERO_EN_U3_V 0x1 +#define PCNT_THR_ZERO_EN_U3_S 11 +/* PCNT_FILTER_EN_U3 : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: This is the enable bit for filtering input signals for unit3.*/ +#define PCNT_FILTER_EN_U3 (BIT(10)) +#define PCNT_FILTER_EN_U3_M (BIT(10)) +#define PCNT_FILTER_EN_U3_V 0x1 +#define PCNT_FILTER_EN_U3_S 10 +/* PCNT_FILTER_THRES_U3 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ +/*description: This register is used to filter pluse whose width is smaller + than this value for unit3.*/ +#define PCNT_FILTER_THRES_U3 0x000003FF +#define PCNT_FILTER_THRES_U3_M ((PCNT_FILTER_THRES_U3_V)<<(PCNT_FILTER_THRES_U3_S)) +#define PCNT_FILTER_THRES_U3_V 0x3FF +#define PCNT_FILTER_THRES_U3_S 0 + +#define PCNT_U3_CONF1_REG (DR_REG_PCNT_BASE + 0x0028) +/* PCNT_CNT_THRES1_U3 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to configure thres1 value for unit3.*/ +#define PCNT_CNT_THRES1_U3 0x0000FFFF +#define PCNT_CNT_THRES1_U3_M ((PCNT_CNT_THRES1_U3_V)<<(PCNT_CNT_THRES1_U3_S)) +#define PCNT_CNT_THRES1_U3_V 0xFFFF +#define PCNT_CNT_THRES1_U3_S 16 +/* PCNT_CNT_THRES0_U3 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thres0 value for unit3.*/ +#define PCNT_CNT_THRES0_U3 0x0000FFFF +#define PCNT_CNT_THRES0_U3_M ((PCNT_CNT_THRES0_U3_V)<<(PCNT_CNT_THRES0_U3_S)) +#define PCNT_CNT_THRES0_U3_V 0xFFFF +#define PCNT_CNT_THRES0_U3_S 0 + +#define PCNT_U3_CONF2_REG (DR_REG_PCNT_BASE + 0x002c) +/* PCNT_CNT_L_LIM_U3 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to confiugre thr_l_lim value for unit3.*/ +#define PCNT_CNT_L_LIM_U3 0x0000FFFF +#define PCNT_CNT_L_LIM_U3_M ((PCNT_CNT_L_LIM_U3_V)<<(PCNT_CNT_L_LIM_U3_S)) +#define PCNT_CNT_L_LIM_U3_V 0xFFFF +#define PCNT_CNT_L_LIM_U3_S 16 +/* PCNT_CNT_H_LIM_U3 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thr_h_lim value for unit3.*/ +#define PCNT_CNT_H_LIM_U3 0x0000FFFF +#define PCNT_CNT_H_LIM_U3_M ((PCNT_CNT_H_LIM_U3_V)<<(PCNT_CNT_H_LIM_U3_S)) +#define PCNT_CNT_H_LIM_U3_V 0xFFFF +#define PCNT_CNT_H_LIM_U3_S 0 + +#define PCNT_U4_CONF0_REG (DR_REG_PCNT_BASE + 0x0030) +/* PCNT_CH1_LCTRL_MODE_U4 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's low control + signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_LCTRL_MODE_U4 0x00000003 +#define PCNT_CH1_LCTRL_MODE_U4_M ((PCNT_CH1_LCTRL_MODE_U4_V)<<(PCNT_CH1_LCTRL_MODE_U4_S)) +#define PCNT_CH1_LCTRL_MODE_U4_V 0x3 +#define PCNT_CH1_LCTRL_MODE_U4_S 30 +/* PCNT_CH1_HCTRL_MODE_U4 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's high + control signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_HCTRL_MODE_U4 0x00000003 +#define PCNT_CH1_HCTRL_MODE_U4_M ((PCNT_CH1_HCTRL_MODE_U4_V)<<(PCNT_CH1_HCTRL_MODE_U4_S)) +#define PCNT_CH1_HCTRL_MODE_U4_V 0x3 +#define PCNT_CH1_HCTRL_MODE_U4_S 28 +/* PCNT_CH1_POS_MODE_U4 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + posedge signal for unit4. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH1_POS_MODE_U4 0x00000003 +#define PCNT_CH1_POS_MODE_U4_M ((PCNT_CH1_POS_MODE_U4_V)<<(PCNT_CH1_POS_MODE_U4_S)) +#define PCNT_CH1_POS_MODE_U4_V 0x3 +#define PCNT_CH1_POS_MODE_U4_S 26 +/* PCNT_CH1_NEG_MODE_U4 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + negedge signal for unit4. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH1_NEG_MODE_U4 0x00000003 +#define PCNT_CH1_NEG_MODE_U4_M ((PCNT_CH1_NEG_MODE_U4_V)<<(PCNT_CH1_NEG_MODE_U4_S)) +#define PCNT_CH1_NEG_MODE_U4_V 0x3 +#define PCNT_CH1_NEG_MODE_U4_S 24 +/* PCNT_CH0_LCTRL_MODE_U4 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's low control + signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_LCTRL_MODE_U4 0x00000003 +#define PCNT_CH0_LCTRL_MODE_U4_M ((PCNT_CH0_LCTRL_MODE_U4_V)<<(PCNT_CH0_LCTRL_MODE_U4_S)) +#define PCNT_CH0_LCTRL_MODE_U4_V 0x3 +#define PCNT_CH0_LCTRL_MODE_U4_S 22 +/* PCNT_CH0_HCTRL_MODE_U4 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's high + control signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_HCTRL_MODE_U4 0x00000003 +#define PCNT_CH0_HCTRL_MODE_U4_M ((PCNT_CH0_HCTRL_MODE_U4_V)<<(PCNT_CH0_HCTRL_MODE_U4_S)) +#define PCNT_CH0_HCTRL_MODE_U4_V 0x3 +#define PCNT_CH0_HCTRL_MODE_U4_S 20 +/* PCNT_CH0_POS_MODE_U4 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + posedge signal for unit4. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH0_POS_MODE_U4 0x00000003 +#define PCNT_CH0_POS_MODE_U4_M ((PCNT_CH0_POS_MODE_U4_V)<<(PCNT_CH0_POS_MODE_U4_S)) +#define PCNT_CH0_POS_MODE_U4_V 0x3 +#define PCNT_CH0_POS_MODE_U4_S 18 +/* PCNT_CH0_NEG_MODE_U4 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + negedge signal for unit4. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH0_NEG_MODE_U4 0x00000003 +#define PCNT_CH0_NEG_MODE_U4_M ((PCNT_CH0_NEG_MODE_U4_V)<<(PCNT_CH0_NEG_MODE_U4_S)) +#define PCNT_CH0_NEG_MODE_U4_V 0x3 +#define PCNT_CH0_NEG_MODE_U4_S 16 +/* PCNT_THR_THRES1_EN_U4 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit4's count with thres1 value .*/ +#define PCNT_THR_THRES1_EN_U4 (BIT(15)) +#define PCNT_THR_THRES1_EN_U4_M (BIT(15)) +#define PCNT_THR_THRES1_EN_U4_V 0x1 +#define PCNT_THR_THRES1_EN_U4_S 15 +/* PCNT_THR_THRES0_EN_U4 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit4's count with thres0 value.*/ +#define PCNT_THR_THRES0_EN_U4 (BIT(14)) +#define PCNT_THR_THRES0_EN_U4_M (BIT(14)) +#define PCNT_THR_THRES0_EN_U4_V 0x1 +#define PCNT_THR_THRES0_EN_U4_S 14 +/* PCNT_THR_L_LIM_EN_U4 : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit4's count with thr_l_lim value.*/ +#define PCNT_THR_L_LIM_EN_U4 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U4_M (BIT(13)) +#define PCNT_THR_L_LIM_EN_U4_V 0x1 +#define PCNT_THR_L_LIM_EN_U4_S 13 +/* PCNT_THR_H_LIM_EN_U4 : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit4's count with thr_h_lim value.*/ +#define PCNT_THR_H_LIM_EN_U4 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U4_M (BIT(12)) +#define PCNT_THR_H_LIM_EN_U4_V 0x1 +#define PCNT_THR_H_LIM_EN_U4_S 12 +/* PCNT_THR_ZERO_EN_U4 : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit4's count with 0 value.*/ +#define PCNT_THR_ZERO_EN_U4 (BIT(11)) +#define PCNT_THR_ZERO_EN_U4_M (BIT(11)) +#define PCNT_THR_ZERO_EN_U4_V 0x1 +#define PCNT_THR_ZERO_EN_U4_S 11 +/* PCNT_FILTER_EN_U4 : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: This is the enable bit for filtering input signals for unit4.*/ +#define PCNT_FILTER_EN_U4 (BIT(10)) +#define PCNT_FILTER_EN_U4_M (BIT(10)) +#define PCNT_FILTER_EN_U4_V 0x1 +#define PCNT_FILTER_EN_U4_S 10 +/* PCNT_FILTER_THRES_U4 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ +/*description: This register is used to filter pluse whose width is smaller + than this value for unit4.*/ +#define PCNT_FILTER_THRES_U4 0x000003FF +#define PCNT_FILTER_THRES_U4_M ((PCNT_FILTER_THRES_U4_V)<<(PCNT_FILTER_THRES_U4_S)) +#define PCNT_FILTER_THRES_U4_V 0x3FF +#define PCNT_FILTER_THRES_U4_S 0 + +#define PCNT_U4_CONF1_REG (DR_REG_PCNT_BASE + 0x0034) +/* PCNT_CNT_THRES1_U4 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to configure thres1 value for unit4.*/ +#define PCNT_CNT_THRES1_U4 0x0000FFFF +#define PCNT_CNT_THRES1_U4_M ((PCNT_CNT_THRES1_U4_V)<<(PCNT_CNT_THRES1_U4_S)) +#define PCNT_CNT_THRES1_U4_V 0xFFFF +#define PCNT_CNT_THRES1_U4_S 16 +/* PCNT_CNT_THRES0_U4 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thres0 value for unit4.*/ +#define PCNT_CNT_THRES0_U4 0x0000FFFF +#define PCNT_CNT_THRES0_U4_M ((PCNT_CNT_THRES0_U4_V)<<(PCNT_CNT_THRES0_U4_S)) +#define PCNT_CNT_THRES0_U4_V 0xFFFF +#define PCNT_CNT_THRES0_U4_S 0 + +#define PCNT_U4_CONF2_REG (DR_REG_PCNT_BASE + 0x0038) +/* PCNT_CNT_L_LIM_U4 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to confiugre thr_l_lim value for unit4.*/ +#define PCNT_CNT_L_LIM_U4 0x0000FFFF +#define PCNT_CNT_L_LIM_U4_M ((PCNT_CNT_L_LIM_U4_V)<<(PCNT_CNT_L_LIM_U4_S)) +#define PCNT_CNT_L_LIM_U4_V 0xFFFF +#define PCNT_CNT_L_LIM_U4_S 16 +/* PCNT_CNT_H_LIM_U4 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thr_h_lim value for unit4.*/ +#define PCNT_CNT_H_LIM_U4 0x0000FFFF +#define PCNT_CNT_H_LIM_U4_M ((PCNT_CNT_H_LIM_U4_V)<<(PCNT_CNT_H_LIM_U4_S)) +#define PCNT_CNT_H_LIM_U4_V 0xFFFF +#define PCNT_CNT_H_LIM_U4_S 0 + +#define PCNT_U5_CONF0_REG (DR_REG_PCNT_BASE + 0x003c) +/* PCNT_CH1_LCTRL_MODE_U5 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's low control + signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_LCTRL_MODE_U5 0x00000003 +#define PCNT_CH1_LCTRL_MODE_U5_M ((PCNT_CH1_LCTRL_MODE_U5_V)<<(PCNT_CH1_LCTRL_MODE_U5_S)) +#define PCNT_CH1_LCTRL_MODE_U5_V 0x3 +#define PCNT_CH1_LCTRL_MODE_U5_S 30 +/* PCNT_CH1_HCTRL_MODE_U5 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's high + control signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_HCTRL_MODE_U5 0x00000003 +#define PCNT_CH1_HCTRL_MODE_U5_M ((PCNT_CH1_HCTRL_MODE_U5_V)<<(PCNT_CH1_HCTRL_MODE_U5_S)) +#define PCNT_CH1_HCTRL_MODE_U5_V 0x3 +#define PCNT_CH1_HCTRL_MODE_U5_S 28 +/* PCNT_CH1_POS_MODE_U5 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + posedge signal for unit5. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH1_POS_MODE_U5 0x00000003 +#define PCNT_CH1_POS_MODE_U5_M ((PCNT_CH1_POS_MODE_U5_V)<<(PCNT_CH1_POS_MODE_U5_S)) +#define PCNT_CH1_POS_MODE_U5_V 0x3 +#define PCNT_CH1_POS_MODE_U5_S 26 +/* PCNT_CH1_NEG_MODE_U5 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + negedge signal for unit5. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH1_NEG_MODE_U5 0x00000003 +#define PCNT_CH1_NEG_MODE_U5_M ((PCNT_CH1_NEG_MODE_U5_V)<<(PCNT_CH1_NEG_MODE_U5_S)) +#define PCNT_CH1_NEG_MODE_U5_V 0x3 +#define PCNT_CH1_NEG_MODE_U5_S 24 +/* PCNT_CH0_LCTRL_MODE_U5 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's low control + signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_LCTRL_MODE_U5 0x00000003 +#define PCNT_CH0_LCTRL_MODE_U5_M ((PCNT_CH0_LCTRL_MODE_U5_V)<<(PCNT_CH0_LCTRL_MODE_U5_S)) +#define PCNT_CH0_LCTRL_MODE_U5_V 0x3 +#define PCNT_CH0_LCTRL_MODE_U5_S 22 +/* PCNT_CH0_HCTRL_MODE_U5 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's high + control signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_HCTRL_MODE_U5 0x00000003 +#define PCNT_CH0_HCTRL_MODE_U5_M ((PCNT_CH0_HCTRL_MODE_U5_V)<<(PCNT_CH0_HCTRL_MODE_U5_S)) +#define PCNT_CH0_HCTRL_MODE_U5_V 0x3 +#define PCNT_CH0_HCTRL_MODE_U5_S 20 +/* PCNT_CH0_POS_MODE_U5 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + posedge signal for unit5. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH0_POS_MODE_U5 0x00000003 +#define PCNT_CH0_POS_MODE_U5_M ((PCNT_CH0_POS_MODE_U5_V)<<(PCNT_CH0_POS_MODE_U5_S)) +#define PCNT_CH0_POS_MODE_U5_V 0x3 +#define PCNT_CH0_POS_MODE_U5_S 18 +/* PCNT_CH0_NEG_MODE_U5 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + negedge signal for unit5. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH0_NEG_MODE_U5 0x00000003 +#define PCNT_CH0_NEG_MODE_U5_M ((PCNT_CH0_NEG_MODE_U5_V)<<(PCNT_CH0_NEG_MODE_U5_S)) +#define PCNT_CH0_NEG_MODE_U5_V 0x3 +#define PCNT_CH0_NEG_MODE_U5_S 16 +/* PCNT_THR_THRES1_EN_U5 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit5's count with thres1 value .*/ +#define PCNT_THR_THRES1_EN_U5 (BIT(15)) +#define PCNT_THR_THRES1_EN_U5_M (BIT(15)) +#define PCNT_THR_THRES1_EN_U5_V 0x1 +#define PCNT_THR_THRES1_EN_U5_S 15 +/* PCNT_THR_THRES0_EN_U5 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit5's count with thres0 value.*/ +#define PCNT_THR_THRES0_EN_U5 (BIT(14)) +#define PCNT_THR_THRES0_EN_U5_M (BIT(14)) +#define PCNT_THR_THRES0_EN_U5_V 0x1 +#define PCNT_THR_THRES0_EN_U5_S 14 +/* PCNT_THR_L_LIM_EN_U5 : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit5's count with thr_l_lim value.*/ +#define PCNT_THR_L_LIM_EN_U5 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U5_M (BIT(13)) +#define PCNT_THR_L_LIM_EN_U5_V 0x1 +#define PCNT_THR_L_LIM_EN_U5_S 13 +/* PCNT_THR_H_LIM_EN_U5 : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit5's count with thr_h_lim value.*/ +#define PCNT_THR_H_LIM_EN_U5 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U5_M (BIT(12)) +#define PCNT_THR_H_LIM_EN_U5_V 0x1 +#define PCNT_THR_H_LIM_EN_U5_S 12 +/* PCNT_THR_ZERO_EN_U5 : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit5's count with 0 value.*/ +#define PCNT_THR_ZERO_EN_U5 (BIT(11)) +#define PCNT_THR_ZERO_EN_U5_M (BIT(11)) +#define PCNT_THR_ZERO_EN_U5_V 0x1 +#define PCNT_THR_ZERO_EN_U5_S 11 +/* PCNT_FILTER_EN_U5 : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: This is the enable bit for filtering input signals for unit5.*/ +#define PCNT_FILTER_EN_U5 (BIT(10)) +#define PCNT_FILTER_EN_U5_M (BIT(10)) +#define PCNT_FILTER_EN_U5_V 0x1 +#define PCNT_FILTER_EN_U5_S 10 +/* PCNT_FILTER_THRES_U5 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ +/*description: This register is used to filter pluse whose width is smaller + than this value for unit5.*/ +#define PCNT_FILTER_THRES_U5 0x000003FF +#define PCNT_FILTER_THRES_U5_M ((PCNT_FILTER_THRES_U5_V)<<(PCNT_FILTER_THRES_U5_S)) +#define PCNT_FILTER_THRES_U5_V 0x3FF +#define PCNT_FILTER_THRES_U5_S 0 + +#define PCNT_U5_CONF1_REG (DR_REG_PCNT_BASE + 0x0040) +/* PCNT_CNT_THRES1_U5 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to configure thres1 value for unit5.*/ +#define PCNT_CNT_THRES1_U5 0x0000FFFF +#define PCNT_CNT_THRES1_U5_M ((PCNT_CNT_THRES1_U5_V)<<(PCNT_CNT_THRES1_U5_S)) +#define PCNT_CNT_THRES1_U5_V 0xFFFF +#define PCNT_CNT_THRES1_U5_S 16 +/* PCNT_CNT_THRES0_U5 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thres0 value for unit5.*/ +#define PCNT_CNT_THRES0_U5 0x0000FFFF +#define PCNT_CNT_THRES0_U5_M ((PCNT_CNT_THRES0_U5_V)<<(PCNT_CNT_THRES0_U5_S)) +#define PCNT_CNT_THRES0_U5_V 0xFFFF +#define PCNT_CNT_THRES0_U5_S 0 + +#define PCNT_U5_CONF2_REG (DR_REG_PCNT_BASE + 0x0044) +/* PCNT_CNT_L_LIM_U5 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to confiugre thr_l_lim value for unit5.*/ +#define PCNT_CNT_L_LIM_U5 0x0000FFFF +#define PCNT_CNT_L_LIM_U5_M ((PCNT_CNT_L_LIM_U5_V)<<(PCNT_CNT_L_LIM_U5_S)) +#define PCNT_CNT_L_LIM_U5_V 0xFFFF +#define PCNT_CNT_L_LIM_U5_S 16 +/* PCNT_CNT_H_LIM_U5 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thr_h_lim value for unit5.*/ +#define PCNT_CNT_H_LIM_U5 0x0000FFFF +#define PCNT_CNT_H_LIM_U5_M ((PCNT_CNT_H_LIM_U5_V)<<(PCNT_CNT_H_LIM_U5_S)) +#define PCNT_CNT_H_LIM_U5_V 0xFFFF +#define PCNT_CNT_H_LIM_U5_S 0 + +#define PCNT_U6_CONF0_REG (DR_REG_PCNT_BASE + 0x0048) +/* PCNT_CH1_LCTRL_MODE_U6 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's low control + signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_LCTRL_MODE_U6 0x00000003 +#define PCNT_CH1_LCTRL_MODE_U6_M ((PCNT_CH1_LCTRL_MODE_U6_V)<<(PCNT_CH1_LCTRL_MODE_U6_S)) +#define PCNT_CH1_LCTRL_MODE_U6_V 0x3 +#define PCNT_CH1_LCTRL_MODE_U6_S 30 +/* PCNT_CH1_HCTRL_MODE_U6 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's high + control signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_HCTRL_MODE_U6 0x00000003 +#define PCNT_CH1_HCTRL_MODE_U6_M ((PCNT_CH1_HCTRL_MODE_U6_V)<<(PCNT_CH1_HCTRL_MODE_U6_S)) +#define PCNT_CH1_HCTRL_MODE_U6_V 0x3 +#define PCNT_CH1_HCTRL_MODE_U6_S 28 +/* PCNT_CH1_POS_MODE_U6 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + posedge signal for unit6. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH1_POS_MODE_U6 0x00000003 +#define PCNT_CH1_POS_MODE_U6_M ((PCNT_CH1_POS_MODE_U6_V)<<(PCNT_CH1_POS_MODE_U6_S)) +#define PCNT_CH1_POS_MODE_U6_V 0x3 +#define PCNT_CH1_POS_MODE_U6_S 26 +/* PCNT_CH1_NEG_MODE_U6 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + negedge signal for unit6. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH1_NEG_MODE_U6 0x00000003 +#define PCNT_CH1_NEG_MODE_U6_M ((PCNT_CH1_NEG_MODE_U6_V)<<(PCNT_CH1_NEG_MODE_U6_S)) +#define PCNT_CH1_NEG_MODE_U6_V 0x3 +#define PCNT_CH1_NEG_MODE_U6_S 24 +/* PCNT_CH0_LCTRL_MODE_U6 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's low control + signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_LCTRL_MODE_U6 0x00000003 +#define PCNT_CH0_LCTRL_MODE_U6_M ((PCNT_CH0_LCTRL_MODE_U6_V)<<(PCNT_CH0_LCTRL_MODE_U6_S)) +#define PCNT_CH0_LCTRL_MODE_U6_V 0x3 +#define PCNT_CH0_LCTRL_MODE_U6_S 22 +/* PCNT_CH0_HCTRL_MODE_U6 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's high + control signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_HCTRL_MODE_U6 0x00000003 +#define PCNT_CH0_HCTRL_MODE_U6_M ((PCNT_CH0_HCTRL_MODE_U6_V)<<(PCNT_CH0_HCTRL_MODE_U6_S)) +#define PCNT_CH0_HCTRL_MODE_U6_V 0x3 +#define PCNT_CH0_HCTRL_MODE_U6_S 20 +/* PCNT_CH0_POS_MODE_U6 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + posedge signal for unit6. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH0_POS_MODE_U6 0x00000003 +#define PCNT_CH0_POS_MODE_U6_M ((PCNT_CH0_POS_MODE_U6_V)<<(PCNT_CH0_POS_MODE_U6_S)) +#define PCNT_CH0_POS_MODE_U6_V 0x3 +#define PCNT_CH0_POS_MODE_U6_S 18 +/* PCNT_CH0_NEG_MODE_U6 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + negedge signal for unit6. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH0_NEG_MODE_U6 0x00000003 +#define PCNT_CH0_NEG_MODE_U6_M ((PCNT_CH0_NEG_MODE_U6_V)<<(PCNT_CH0_NEG_MODE_U6_S)) +#define PCNT_CH0_NEG_MODE_U6_V 0x3 +#define PCNT_CH0_NEG_MODE_U6_S 16 +/* PCNT_THR_THRES1_EN_U6 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit6's count with thres1 value .*/ +#define PCNT_THR_THRES1_EN_U6 (BIT(15)) +#define PCNT_THR_THRES1_EN_U6_M (BIT(15)) +#define PCNT_THR_THRES1_EN_U6_V 0x1 +#define PCNT_THR_THRES1_EN_U6_S 15 +/* PCNT_THR_THRES0_EN_U6 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit6's count with thres0 value.*/ +#define PCNT_THR_THRES0_EN_U6 (BIT(14)) +#define PCNT_THR_THRES0_EN_U6_M (BIT(14)) +#define PCNT_THR_THRES0_EN_U6_V 0x1 +#define PCNT_THR_THRES0_EN_U6_S 14 +/* PCNT_THR_L_LIM_EN_U6 : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit6's count with thr_l_lim value.*/ +#define PCNT_THR_L_LIM_EN_U6 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U6_M (BIT(13)) +#define PCNT_THR_L_LIM_EN_U6_V 0x1 +#define PCNT_THR_L_LIM_EN_U6_S 13 +/* PCNT_THR_H_LIM_EN_U6 : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit6's count with thr_h_lim value.*/ +#define PCNT_THR_H_LIM_EN_U6 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U6_M (BIT(12)) +#define PCNT_THR_H_LIM_EN_U6_V 0x1 +#define PCNT_THR_H_LIM_EN_U6_S 12 +/* PCNT_THR_ZERO_EN_U6 : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit6's count with 0 value.*/ +#define PCNT_THR_ZERO_EN_U6 (BIT(11)) +#define PCNT_THR_ZERO_EN_U6_M (BIT(11)) +#define PCNT_THR_ZERO_EN_U6_V 0x1 +#define PCNT_THR_ZERO_EN_U6_S 11 +/* PCNT_FILTER_EN_U6 : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: This is the enable bit for filtering input signals for unit6.*/ +#define PCNT_FILTER_EN_U6 (BIT(10)) +#define PCNT_FILTER_EN_U6_M (BIT(10)) +#define PCNT_FILTER_EN_U6_V 0x1 +#define PCNT_FILTER_EN_U6_S 10 +/* PCNT_FILTER_THRES_U6 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ +/*description: This register is used to filter pluse whose width is smaller + than this value for unit6.*/ +#define PCNT_FILTER_THRES_U6 0x000003FF +#define PCNT_FILTER_THRES_U6_M ((PCNT_FILTER_THRES_U6_V)<<(PCNT_FILTER_THRES_U6_S)) +#define PCNT_FILTER_THRES_U6_V 0x3FF +#define PCNT_FILTER_THRES_U6_S 0 + +#define PCNT_U6_CONF1_REG (DR_REG_PCNT_BASE + 0x004c) +/* PCNT_CNT_THRES1_U6 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to configure thres1 value for unit6.*/ +#define PCNT_CNT_THRES1_U6 0x0000FFFF +#define PCNT_CNT_THRES1_U6_M ((PCNT_CNT_THRES1_U6_V)<<(PCNT_CNT_THRES1_U6_S)) +#define PCNT_CNT_THRES1_U6_V 0xFFFF +#define PCNT_CNT_THRES1_U6_S 16 +/* PCNT_CNT_THRES0_U6 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thres0 value for unit6.*/ +#define PCNT_CNT_THRES0_U6 0x0000FFFF +#define PCNT_CNT_THRES0_U6_M ((PCNT_CNT_THRES0_U6_V)<<(PCNT_CNT_THRES0_U6_S)) +#define PCNT_CNT_THRES0_U6_V 0xFFFF +#define PCNT_CNT_THRES0_U6_S 0 + +#define PCNT_U6_CONF2_REG (DR_REG_PCNT_BASE + 0x0050) +/* PCNT_CNT_L_LIM_U6 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to confiugre thr_l_lim value for unit6.*/ +#define PCNT_CNT_L_LIM_U6 0x0000FFFF +#define PCNT_CNT_L_LIM_U6_M ((PCNT_CNT_L_LIM_U6_V)<<(PCNT_CNT_L_LIM_U6_S)) +#define PCNT_CNT_L_LIM_U6_V 0xFFFF +#define PCNT_CNT_L_LIM_U6_S 16 +/* PCNT_CNT_H_LIM_U6 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thr_h_lim value for unit6.*/ +#define PCNT_CNT_H_LIM_U6 0x0000FFFF +#define PCNT_CNT_H_LIM_U6_M ((PCNT_CNT_H_LIM_U6_V)<<(PCNT_CNT_H_LIM_U6_S)) +#define PCNT_CNT_H_LIM_U6_V 0xFFFF +#define PCNT_CNT_H_LIM_U6_S 0 + +#define PCNT_U7_CONF0_REG (DR_REG_PCNT_BASE + 0x0054) +/* PCNT_CH1_LCTRL_MODE_U7 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's low control + signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_LCTRL_MODE_U7 0x00000003 +#define PCNT_CH1_LCTRL_MODE_U7_M ((PCNT_CH1_LCTRL_MODE_U7_V)<<(PCNT_CH1_LCTRL_MODE_U7_S)) +#define PCNT_CH1_LCTRL_MODE_U7_V 0x3 +#define PCNT_CH1_LCTRL_MODE_U7_S 30 +/* PCNT_CH1_HCTRL_MODE_U7 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's high + control signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_HCTRL_MODE_U7 0x00000003 +#define PCNT_CH1_HCTRL_MODE_U7_M ((PCNT_CH1_HCTRL_MODE_U7_V)<<(PCNT_CH1_HCTRL_MODE_U7_S)) +#define PCNT_CH1_HCTRL_MODE_U7_V 0x3 +#define PCNT_CH1_HCTRL_MODE_U7_S 28 +/* PCNT_CH1_POS_MODE_U7 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + posedge signal for unit7. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH1_POS_MODE_U7 0x00000003 +#define PCNT_CH1_POS_MODE_U7_M ((PCNT_CH1_POS_MODE_U7_V)<<(PCNT_CH1_POS_MODE_U7_S)) +#define PCNT_CH1_POS_MODE_U7_V 0x3 +#define PCNT_CH1_POS_MODE_U7_S 26 +/* PCNT_CH1_NEG_MODE_U7 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + negedge signal for unit7. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH1_NEG_MODE_U7 0x00000003 +#define PCNT_CH1_NEG_MODE_U7_M ((PCNT_CH1_NEG_MODE_U7_V)<<(PCNT_CH1_NEG_MODE_U7_S)) +#define PCNT_CH1_NEG_MODE_U7_V 0x3 +#define PCNT_CH1_NEG_MODE_U7_S 24 +/* PCNT_CH0_LCTRL_MODE_U7 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's low control + signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_LCTRL_MODE_U7 0x00000003 +#define PCNT_CH0_LCTRL_MODE_U7_M ((PCNT_CH0_LCTRL_MODE_U7_V)<<(PCNT_CH0_LCTRL_MODE_U7_S)) +#define PCNT_CH0_LCTRL_MODE_U7_V 0x3 +#define PCNT_CH0_LCTRL_MODE_U7_S 22 +/* PCNT_CH0_HCTRL_MODE_U7 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's high + control signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_HCTRL_MODE_U7 0x00000003 +#define PCNT_CH0_HCTRL_MODE_U7_M ((PCNT_CH0_HCTRL_MODE_U7_V)<<(PCNT_CH0_HCTRL_MODE_U7_S)) +#define PCNT_CH0_HCTRL_MODE_U7_V 0x3 +#define PCNT_CH0_HCTRL_MODE_U7_S 20 +/* PCNT_CH0_POS_MODE_U7 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + posedge signal for unit7. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH0_POS_MODE_U7 0x00000003 +#define PCNT_CH0_POS_MODE_U7_M ((PCNT_CH0_POS_MODE_U7_V)<<(PCNT_CH0_POS_MODE_U7_S)) +#define PCNT_CH0_POS_MODE_U7_V 0x3 +#define PCNT_CH0_POS_MODE_U7_S 18 +/* PCNT_CH0_NEG_MODE_U7 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + negedge signal for unit7. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH0_NEG_MODE_U7 0x00000003 +#define PCNT_CH0_NEG_MODE_U7_M ((PCNT_CH0_NEG_MODE_U7_V)<<(PCNT_CH0_NEG_MODE_U7_S)) +#define PCNT_CH0_NEG_MODE_U7_V 0x3 +#define PCNT_CH0_NEG_MODE_U7_S 16 +/* PCNT_THR_THRES1_EN_U7 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit7's count with thres1 value .*/ +#define PCNT_THR_THRES1_EN_U7 (BIT(15)) +#define PCNT_THR_THRES1_EN_U7_M (BIT(15)) +#define PCNT_THR_THRES1_EN_U7_V 0x1 +#define PCNT_THR_THRES1_EN_U7_S 15 +/* PCNT_THR_THRES0_EN_U7 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit7's count with thres0 value.*/ +#define PCNT_THR_THRES0_EN_U7 (BIT(14)) +#define PCNT_THR_THRES0_EN_U7_M (BIT(14)) +#define PCNT_THR_THRES0_EN_U7_V 0x1 +#define PCNT_THR_THRES0_EN_U7_S 14 +/* PCNT_THR_L_LIM_EN_U7 : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit7's count with thr_l_lim value.*/ +#define PCNT_THR_L_LIM_EN_U7 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U7_M (BIT(13)) +#define PCNT_THR_L_LIM_EN_U7_V 0x1 +#define PCNT_THR_L_LIM_EN_U7_S 13 +/* PCNT_THR_H_LIM_EN_U7 : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit7's count with thr_h_lim value.*/ +#define PCNT_THR_H_LIM_EN_U7 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U7_M (BIT(12)) +#define PCNT_THR_H_LIM_EN_U7_V 0x1 +#define PCNT_THR_H_LIM_EN_U7_S 12 +/* PCNT_THR_ZERO_EN_U7 : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit7's count with 0 value.*/ +#define PCNT_THR_ZERO_EN_U7 (BIT(11)) +#define PCNT_THR_ZERO_EN_U7_M (BIT(11)) +#define PCNT_THR_ZERO_EN_U7_V 0x1 +#define PCNT_THR_ZERO_EN_U7_S 11 +/* PCNT_FILTER_EN_U7 : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: This is the enable bit for filtering input signals for unit7.*/ +#define PCNT_FILTER_EN_U7 (BIT(10)) +#define PCNT_FILTER_EN_U7_M (BIT(10)) +#define PCNT_FILTER_EN_U7_V 0x1 +#define PCNT_FILTER_EN_U7_S 10 +/* PCNT_FILTER_THRES_U7 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ +/*description: This register is used to filter pluse whose width is smaller + than this value for unit7.*/ +#define PCNT_FILTER_THRES_U7 0x000003FF +#define PCNT_FILTER_THRES_U7_M ((PCNT_FILTER_THRES_U7_V)<<(PCNT_FILTER_THRES_U7_S)) +#define PCNT_FILTER_THRES_U7_V 0x3FF +#define PCNT_FILTER_THRES_U7_S 0 + +#define PCNT_U7_CONF1_REG (DR_REG_PCNT_BASE + 0x0058) +/* PCNT_CNT_THRES1_U7 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to configure thres1 value for unit7.*/ +#define PCNT_CNT_THRES1_U7 0x0000FFFF +#define PCNT_CNT_THRES1_U7_M ((PCNT_CNT_THRES1_U7_V)<<(PCNT_CNT_THRES1_U7_S)) +#define PCNT_CNT_THRES1_U7_V 0xFFFF +#define PCNT_CNT_THRES1_U7_S 16 +/* PCNT_CNT_THRES0_U7 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thres0 value for unit7.*/ +#define PCNT_CNT_THRES0_U7 0x0000FFFF +#define PCNT_CNT_THRES0_U7_M ((PCNT_CNT_THRES0_U7_V)<<(PCNT_CNT_THRES0_U7_S)) +#define PCNT_CNT_THRES0_U7_V 0xFFFF +#define PCNT_CNT_THRES0_U7_S 0 + +#define PCNT_U7_CONF2_REG (DR_REG_PCNT_BASE + 0x005c) +/* PCNT_CNT_L_LIM_U7 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to confiugre thr_l_lim value for unit7.*/ +#define PCNT_CNT_L_LIM_U7 0x0000FFFF +#define PCNT_CNT_L_LIM_U7_M ((PCNT_CNT_L_LIM_U7_V)<<(PCNT_CNT_L_LIM_U7_S)) +#define PCNT_CNT_L_LIM_U7_V 0xFFFF +#define PCNT_CNT_L_LIM_U7_S 16 +/* PCNT_CNT_H_LIM_U7 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thr_h_lim value for unit7.*/ +#define PCNT_CNT_H_LIM_U7 0x0000FFFF +#define PCNT_CNT_H_LIM_U7_M ((PCNT_CNT_H_LIM_U7_V)<<(PCNT_CNT_H_LIM_U7_S)) +#define PCNT_CNT_H_LIM_U7_V 0xFFFF +#define PCNT_CNT_H_LIM_U7_S 0 + +#define PCNT_U0_CNT_REG (DR_REG_PCNT_BASE + 0x0060) +/* PCNT_PLUS_CNT_U0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: This register stores the current pulse count value for unit0.*/ +#define PCNT_PLUS_CNT_U0 0x0000FFFF +#define PCNT_PLUS_CNT_U0_M ((PCNT_PLUS_CNT_U0_V)<<(PCNT_PLUS_CNT_U0_S)) +#define PCNT_PLUS_CNT_U0_V 0xFFFF +#define PCNT_PLUS_CNT_U0_S 0 + +#define PCNT_U1_CNT_REG (DR_REG_PCNT_BASE + 0x0064) +/* PCNT_PLUS_CNT_U1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: This register stores the current pulse count value for unit1.*/ +#define PCNT_PLUS_CNT_U1 0x0000FFFF +#define PCNT_PLUS_CNT_U1_M ((PCNT_PLUS_CNT_U1_V)<<(PCNT_PLUS_CNT_U1_S)) +#define PCNT_PLUS_CNT_U1_V 0xFFFF +#define PCNT_PLUS_CNT_U1_S 0 + +#define PCNT_U2_CNT_REG (DR_REG_PCNT_BASE + 0x0068) +/* PCNT_PLUS_CNT_U2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: This register stores the current pulse count value for unit2.*/ +#define PCNT_PLUS_CNT_U2 0x0000FFFF +#define PCNT_PLUS_CNT_U2_M ((PCNT_PLUS_CNT_U2_V)<<(PCNT_PLUS_CNT_U2_S)) +#define PCNT_PLUS_CNT_U2_V 0xFFFF +#define PCNT_PLUS_CNT_U2_S 0 + +#define PCNT_U3_CNT_REG (DR_REG_PCNT_BASE + 0x006c) +/* PCNT_PLUS_CNT_U3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: This register stores the current pulse count value for unit3.*/ +#define PCNT_PLUS_CNT_U3 0x0000FFFF +#define PCNT_PLUS_CNT_U3_M ((PCNT_PLUS_CNT_U3_V)<<(PCNT_PLUS_CNT_U3_S)) +#define PCNT_PLUS_CNT_U3_V 0xFFFF +#define PCNT_PLUS_CNT_U3_S 0 + +#define PCNT_U4_CNT_REG (DR_REG_PCNT_BASE + 0x0070) +/* PCNT_PLUS_CNT_U4 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: This register stores the current pulse count value for unit4.*/ +#define PCNT_PLUS_CNT_U4 0x0000FFFF +#define PCNT_PLUS_CNT_U4_M ((PCNT_PLUS_CNT_U4_V)<<(PCNT_PLUS_CNT_U4_S)) +#define PCNT_PLUS_CNT_U4_V 0xFFFF +#define PCNT_PLUS_CNT_U4_S 0 + +#define PCNT_U5_CNT_REG (DR_REG_PCNT_BASE + 0x0074) +/* PCNT_PLUS_CNT_U5 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: This register stores the current pulse count value for unit5.*/ +#define PCNT_PLUS_CNT_U5 0x0000FFFF +#define PCNT_PLUS_CNT_U5_M ((PCNT_PLUS_CNT_U5_V)<<(PCNT_PLUS_CNT_U5_S)) +#define PCNT_PLUS_CNT_U5_V 0xFFFF +#define PCNT_PLUS_CNT_U5_S 0 + +#define PCNT_U6_CNT_REG (DR_REG_PCNT_BASE + 0x0078) +/* PCNT_PLUS_CNT_U6 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: This register stores the current pulse count value for unit6.*/ +#define PCNT_PLUS_CNT_U6 0x0000FFFF +#define PCNT_PLUS_CNT_U6_M ((PCNT_PLUS_CNT_U6_V)<<(PCNT_PLUS_CNT_U6_S)) +#define PCNT_PLUS_CNT_U6_V 0xFFFF +#define PCNT_PLUS_CNT_U6_S 0 + +#define PCNT_U7_CNT_REG (DR_REG_PCNT_BASE + 0x007c) +/* PCNT_PLUS_CNT_U7 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: This register stores the current pulse count value for unit7.*/ +#define PCNT_PLUS_CNT_U7 0x0000FFFF +#define PCNT_PLUS_CNT_U7_M ((PCNT_PLUS_CNT_U7_V)<<(PCNT_PLUS_CNT_U7_S)) +#define PCNT_PLUS_CNT_U7_V 0xFFFF +#define PCNT_PLUS_CNT_U7_S 0 + +#define PCNT_INT_RAW_REG (DR_REG_PCNT_BASE + 0x0080) +/* PCNT_CNT_THR_EVENT_U7_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the interrupt raw bit for channel7 event.*/ +#define PCNT_CNT_THR_EVENT_U7_INT_RAW (BIT(7)) +#define PCNT_CNT_THR_EVENT_U7_INT_RAW_M (BIT(7)) +#define PCNT_CNT_THR_EVENT_U7_INT_RAW_V 0x1 +#define PCNT_CNT_THR_EVENT_U7_INT_RAW_S 7 +/* PCNT_CNT_THR_EVENT_U6_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This is the interrupt raw bit for channel6 event.*/ +#define PCNT_CNT_THR_EVENT_U6_INT_RAW (BIT(6)) +#define PCNT_CNT_THR_EVENT_U6_INT_RAW_M (BIT(6)) +#define PCNT_CNT_THR_EVENT_U6_INT_RAW_V 0x1 +#define PCNT_CNT_THR_EVENT_U6_INT_RAW_S 6 +/* PCNT_CNT_THR_EVENT_U5_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This is the interrupt raw bit for channel5 event.*/ +#define PCNT_CNT_THR_EVENT_U5_INT_RAW (BIT(5)) +#define PCNT_CNT_THR_EVENT_U5_INT_RAW_M (BIT(5)) +#define PCNT_CNT_THR_EVENT_U5_INT_RAW_V 0x1 +#define PCNT_CNT_THR_EVENT_U5_INT_RAW_S 5 +/* PCNT_CNT_THR_EVENT_U4_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This is the interrupt raw bit for channel4 event.*/ +#define PCNT_CNT_THR_EVENT_U4_INT_RAW (BIT(4)) +#define PCNT_CNT_THR_EVENT_U4_INT_RAW_M (BIT(4)) +#define PCNT_CNT_THR_EVENT_U4_INT_RAW_V 0x1 +#define PCNT_CNT_THR_EVENT_U4_INT_RAW_S 4 +/* PCNT_CNT_THR_EVENT_U3_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This is the interrupt raw bit for channel3 event.*/ +#define PCNT_CNT_THR_EVENT_U3_INT_RAW (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_RAW_M (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_RAW_V 0x1 +#define PCNT_CNT_THR_EVENT_U3_INT_RAW_S 3 +/* PCNT_CNT_THR_EVENT_U2_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the interrupt raw bit for channel2 event.*/ +#define PCNT_CNT_THR_EVENT_U2_INT_RAW (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_RAW_M (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_RAW_V 0x1 +#define PCNT_CNT_THR_EVENT_U2_INT_RAW_S 2 +/* PCNT_CNT_THR_EVENT_U1_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: This is the interrupt raw bit for channel1 event.*/ +#define PCNT_CNT_THR_EVENT_U1_INT_RAW (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_RAW_M (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_RAW_V 0x1 +#define PCNT_CNT_THR_EVENT_U1_INT_RAW_S 1 +/* PCNT_CNT_THR_EVENT_U0_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This is the interrupt raw bit for channel0 event.*/ +#define PCNT_CNT_THR_EVENT_U0_INT_RAW (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_RAW_M (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_RAW_V 0x1 +#define PCNT_CNT_THR_EVENT_U0_INT_RAW_S 0 + +#define PCNT_INT_ST_REG (DR_REG_PCNT_BASE + 0x0084) +/* PCNT_CNT_THR_EVENT_U7_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the interrupt status bit for channel7 event.*/ +#define PCNT_CNT_THR_EVENT_U7_INT_ST (BIT(7)) +#define PCNT_CNT_THR_EVENT_U7_INT_ST_M (BIT(7)) +#define PCNT_CNT_THR_EVENT_U7_INT_ST_V 0x1 +#define PCNT_CNT_THR_EVENT_U7_INT_ST_S 7 +/* PCNT_CNT_THR_EVENT_U6_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This is the interrupt status bit for channel6 event.*/ +#define PCNT_CNT_THR_EVENT_U6_INT_ST (BIT(6)) +#define PCNT_CNT_THR_EVENT_U6_INT_ST_M (BIT(6)) +#define PCNT_CNT_THR_EVENT_U6_INT_ST_V 0x1 +#define PCNT_CNT_THR_EVENT_U6_INT_ST_S 6 +/* PCNT_CNT_THR_EVENT_U5_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This is the interrupt status bit for channel5 event.*/ +#define PCNT_CNT_THR_EVENT_U5_INT_ST (BIT(5)) +#define PCNT_CNT_THR_EVENT_U5_INT_ST_M (BIT(5)) +#define PCNT_CNT_THR_EVENT_U5_INT_ST_V 0x1 +#define PCNT_CNT_THR_EVENT_U5_INT_ST_S 5 +/* PCNT_CNT_THR_EVENT_U4_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This is the interrupt status bit for channel4 event.*/ +#define PCNT_CNT_THR_EVENT_U4_INT_ST (BIT(4)) +#define PCNT_CNT_THR_EVENT_U4_INT_ST_M (BIT(4)) +#define PCNT_CNT_THR_EVENT_U4_INT_ST_V 0x1 +#define PCNT_CNT_THR_EVENT_U4_INT_ST_S 4 +/* PCNT_CNT_THR_EVENT_U3_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This is the interrupt status bit for channel3 event.*/ +#define PCNT_CNT_THR_EVENT_U3_INT_ST (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_ST_M (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_ST_V 0x1 +#define PCNT_CNT_THR_EVENT_U3_INT_ST_S 3 +/* PCNT_CNT_THR_EVENT_U2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the interrupt status bit for channel2 event.*/ +#define PCNT_CNT_THR_EVENT_U2_INT_ST (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_ST_M (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_ST_V 0x1 +#define PCNT_CNT_THR_EVENT_U2_INT_ST_S 2 +/* PCNT_CNT_THR_EVENT_U1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: This is the interrupt status bit for channel1 event.*/ +#define PCNT_CNT_THR_EVENT_U1_INT_ST (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_ST_M (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_ST_V 0x1 +#define PCNT_CNT_THR_EVENT_U1_INT_ST_S 1 +/* PCNT_CNT_THR_EVENT_U0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This is the interrupt status bit for channel0 event.*/ +#define PCNT_CNT_THR_EVENT_U0_INT_ST (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_ST_M (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_ST_V 0x1 +#define PCNT_CNT_THR_EVENT_U0_INT_ST_S 0 + +#define PCNT_INT_ENA_REG (DR_REG_PCNT_BASE + 0x0088) +/* PCNT_CNT_THR_EVENT_U7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the interrupt enable bit for channel7 event.*/ +#define PCNT_CNT_THR_EVENT_U7_INT_ENA (BIT(7)) +#define PCNT_CNT_THR_EVENT_U7_INT_ENA_M (BIT(7)) +#define PCNT_CNT_THR_EVENT_U7_INT_ENA_V 0x1 +#define PCNT_CNT_THR_EVENT_U7_INT_ENA_S 7 +/* PCNT_CNT_THR_EVENT_U6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This is the interrupt enable bit for channel6 event.*/ +#define PCNT_CNT_THR_EVENT_U6_INT_ENA (BIT(6)) +#define PCNT_CNT_THR_EVENT_U6_INT_ENA_M (BIT(6)) +#define PCNT_CNT_THR_EVENT_U6_INT_ENA_V 0x1 +#define PCNT_CNT_THR_EVENT_U6_INT_ENA_S 6 +/* PCNT_CNT_THR_EVENT_U5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This is the interrupt enable bit for channel5 event.*/ +#define PCNT_CNT_THR_EVENT_U5_INT_ENA (BIT(5)) +#define PCNT_CNT_THR_EVENT_U5_INT_ENA_M (BIT(5)) +#define PCNT_CNT_THR_EVENT_U5_INT_ENA_V 0x1 +#define PCNT_CNT_THR_EVENT_U5_INT_ENA_S 5 +/* PCNT_CNT_THR_EVENT_U4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This is the interrupt enable bit for channel4 event.*/ +#define PCNT_CNT_THR_EVENT_U4_INT_ENA (BIT(4)) +#define PCNT_CNT_THR_EVENT_U4_INT_ENA_M (BIT(4)) +#define PCNT_CNT_THR_EVENT_U4_INT_ENA_V 0x1 +#define PCNT_CNT_THR_EVENT_U4_INT_ENA_S 4 +/* PCNT_CNT_THR_EVENT_U3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This is the interrupt enable bit for channel3 event.*/ +#define PCNT_CNT_THR_EVENT_U3_INT_ENA (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_ENA_M (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_ENA_V 0x1 +#define PCNT_CNT_THR_EVENT_U3_INT_ENA_S 3 +/* PCNT_CNT_THR_EVENT_U2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the interrupt enable bit for channel2 event.*/ +#define PCNT_CNT_THR_EVENT_U2_INT_ENA (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_ENA_M (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_ENA_V 0x1 +#define PCNT_CNT_THR_EVENT_U2_INT_ENA_S 2 +/* PCNT_CNT_THR_EVENT_U1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: This is the interrupt enable bit for channel1 event.*/ +#define PCNT_CNT_THR_EVENT_U1_INT_ENA (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_ENA_M (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_ENA_V 0x1 +#define PCNT_CNT_THR_EVENT_U1_INT_ENA_S 1 +/* PCNT_CNT_THR_EVENT_U0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This is the interrupt enable bit for channel0 event.*/ +#define PCNT_CNT_THR_EVENT_U0_INT_ENA (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_ENA_M (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_ENA_V 0x1 +#define PCNT_CNT_THR_EVENT_U0_INT_ENA_S 0 + +#define PCNT_INT_CLR_REG (DR_REG_PCNT_BASE + 0x008c) +/* PCNT_CNT_THR_EVENT_U7_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to clear channel7 event interrupt.*/ +#define PCNT_CNT_THR_EVENT_U7_INT_CLR (BIT(7)) +#define PCNT_CNT_THR_EVENT_U7_INT_CLR_M (BIT(7)) +#define PCNT_CNT_THR_EVENT_U7_INT_CLR_V 0x1 +#define PCNT_CNT_THR_EVENT_U7_INT_CLR_S 7 +/* PCNT_CNT_THR_EVENT_U6_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to clear channel6 event interrupt.*/ +#define PCNT_CNT_THR_EVENT_U6_INT_CLR (BIT(6)) +#define PCNT_CNT_THR_EVENT_U6_INT_CLR_M (BIT(6)) +#define PCNT_CNT_THR_EVENT_U6_INT_CLR_V 0x1 +#define PCNT_CNT_THR_EVENT_U6_INT_CLR_S 6 +/* PCNT_CNT_THR_EVENT_U5_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to clear channel5 event interrupt.*/ +#define PCNT_CNT_THR_EVENT_U5_INT_CLR (BIT(5)) +#define PCNT_CNT_THR_EVENT_U5_INT_CLR_M (BIT(5)) +#define PCNT_CNT_THR_EVENT_U5_INT_CLR_V 0x1 +#define PCNT_CNT_THR_EVENT_U5_INT_CLR_S 5 +/* PCNT_CNT_THR_EVENT_U4_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to clear channel4 event interrupt.*/ +#define PCNT_CNT_THR_EVENT_U4_INT_CLR (BIT(4)) +#define PCNT_CNT_THR_EVENT_U4_INT_CLR_M (BIT(4)) +#define PCNT_CNT_THR_EVENT_U4_INT_CLR_V 0x1 +#define PCNT_CNT_THR_EVENT_U4_INT_CLR_S 4 +/* PCNT_CNT_THR_EVENT_U3_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear channel3 event interrupt.*/ +#define PCNT_CNT_THR_EVENT_U3_INT_CLR (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_CLR_M (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_CLR_V 0x1 +#define PCNT_CNT_THR_EVENT_U3_INT_CLR_S 3 +/* PCNT_CNT_THR_EVENT_U2_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear channel2 event interrupt.*/ +#define PCNT_CNT_THR_EVENT_U2_INT_CLR (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_CLR_M (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_CLR_V 0x1 +#define PCNT_CNT_THR_EVENT_U2_INT_CLR_S 2 +/* PCNT_CNT_THR_EVENT_U1_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear channel1 event interrupt.*/ +#define PCNT_CNT_THR_EVENT_U1_INT_CLR (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_CLR_M (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_CLR_V 0x1 +#define PCNT_CNT_THR_EVENT_U1_INT_CLR_S 1 +/* PCNT_CNT_THR_EVENT_U0_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear channel0 event interrupt.*/ +#define PCNT_CNT_THR_EVENT_U0_INT_CLR (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_CLR_M (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_CLR_V 0x1 +#define PCNT_CNT_THR_EVENT_U0_INT_CLR_S 0 + +#define PCNT_U0_STATUS_REG (DR_REG_PCNT_BASE + 0x0090) +/* PCNT_CORE_STATUS_U0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define PCNT_CORE_STATUS_U0 0xFFFFFFFF +#define PCNT_CORE_STATUS_U0_M ((PCNT_CORE_STATUS_U0_V)<<(PCNT_CORE_STATUS_U0_S)) +#define PCNT_CORE_STATUS_U0_V 0xFFFFFFFF +#define PCNT_CORE_STATUS_U0_S 0 + +#define PCNT_U1_STATUS_REG (DR_REG_PCNT_BASE + 0x0094) +/* PCNT_CORE_STATUS_U1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define PCNT_CORE_STATUS_U1 0xFFFFFFFF +#define PCNT_CORE_STATUS_U1_M ((PCNT_CORE_STATUS_U1_V)<<(PCNT_CORE_STATUS_U1_S)) +#define PCNT_CORE_STATUS_U1_V 0xFFFFFFFF +#define PCNT_CORE_STATUS_U1_S 0 + +#define PCNT_U2_STATUS_REG (DR_REG_PCNT_BASE + 0x0098) +/* PCNT_CORE_STATUS_U2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define PCNT_CORE_STATUS_U2 0xFFFFFFFF +#define PCNT_CORE_STATUS_U2_M ((PCNT_CORE_STATUS_U2_V)<<(PCNT_CORE_STATUS_U2_S)) +#define PCNT_CORE_STATUS_U2_V 0xFFFFFFFF +#define PCNT_CORE_STATUS_U2_S 0 + +#define PCNT_U3_STATUS_REG (DR_REG_PCNT_BASE + 0x009c) +/* PCNT_CORE_STATUS_U3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define PCNT_CORE_STATUS_U3 0xFFFFFFFF +#define PCNT_CORE_STATUS_U3_M ((PCNT_CORE_STATUS_U3_V)<<(PCNT_CORE_STATUS_U3_S)) +#define PCNT_CORE_STATUS_U3_V 0xFFFFFFFF +#define PCNT_CORE_STATUS_U3_S 0 + +#define PCNT_U4_STATUS_REG (DR_REG_PCNT_BASE + 0x00a0) +/* PCNT_CORE_STATUS_U4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define PCNT_CORE_STATUS_U4 0xFFFFFFFF +#define PCNT_CORE_STATUS_U4_M ((PCNT_CORE_STATUS_U4_V)<<(PCNT_CORE_STATUS_U4_S)) +#define PCNT_CORE_STATUS_U4_V 0xFFFFFFFF +#define PCNT_CORE_STATUS_U4_S 0 + +#define PCNT_U5_STATUS_REG (DR_REG_PCNT_BASE + 0x00a4) +/* PCNT_CORE_STATUS_U5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define PCNT_CORE_STATUS_U5 0xFFFFFFFF +#define PCNT_CORE_STATUS_U5_M ((PCNT_CORE_STATUS_U5_V)<<(PCNT_CORE_STATUS_U5_S)) +#define PCNT_CORE_STATUS_U5_V 0xFFFFFFFF +#define PCNT_CORE_STATUS_U5_S 0 + +#define PCNT_U6_STATUS_REG (DR_REG_PCNT_BASE + 0x00a8) +/* PCNT_CORE_STATUS_U6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define PCNT_CORE_STATUS_U6 0xFFFFFFFF +#define PCNT_CORE_STATUS_U6_M ((PCNT_CORE_STATUS_U6_V)<<(PCNT_CORE_STATUS_U6_S)) +#define PCNT_CORE_STATUS_U6_V 0xFFFFFFFF +#define PCNT_CORE_STATUS_U6_S 0 + +#define PCNT_U7_STATUS_REG (DR_REG_PCNT_BASE + 0x00ac) +/* PCNT_CORE_STATUS_U7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define PCNT_CORE_STATUS_U7 0xFFFFFFFF +#define PCNT_CORE_STATUS_U7_M ((PCNT_CORE_STATUS_U7_V)<<(PCNT_CORE_STATUS_U7_S)) +#define PCNT_CORE_STATUS_U7_V 0xFFFFFFFF +#define PCNT_CORE_STATUS_U7_S 0 + +#define PCNT_CTRL_REG (DR_REG_PCNT_BASE + 0x00b0) +/* PCNT_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CLK_EN (BIT(16)) +#define PCNT_CLK_EN_M (BIT(16)) +#define PCNT_CLK_EN_V 0x1 +#define PCNT_CLK_EN_S 16 +/* PCNT_CNT_PAUSE_U7 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: Set this bit to pause unit7's counter.*/ +#define PCNT_CNT_PAUSE_U7 (BIT(15)) +#define PCNT_CNT_PAUSE_U7_M (BIT(15)) +#define PCNT_CNT_PAUSE_U7_V 0x1 +#define PCNT_CNT_PAUSE_U7_S 15 +/* PCNT_PLUS_CNT_RST_U7 : R/W ;bitpos:[14] ;default: 1'b1 ; */ +/*description: Set this bit to clear unit7's counter.*/ +#define PCNT_PLUS_CNT_RST_U7 (BIT(14)) +#define PCNT_PLUS_CNT_RST_U7_M (BIT(14)) +#define PCNT_PLUS_CNT_RST_U7_V 0x1 +#define PCNT_PLUS_CNT_RST_U7_S 14 +/* PCNT_CNT_PAUSE_U6 : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Set this bit to pause unit6's counter.*/ +#define PCNT_CNT_PAUSE_U6 (BIT(13)) +#define PCNT_CNT_PAUSE_U6_M (BIT(13)) +#define PCNT_CNT_PAUSE_U6_V 0x1 +#define PCNT_CNT_PAUSE_U6_S 13 +/* PCNT_PLUS_CNT_RST_U6 : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: Set this bit to clear unit6's counter.*/ +#define PCNT_PLUS_CNT_RST_U6 (BIT(12)) +#define PCNT_PLUS_CNT_RST_U6_M (BIT(12)) +#define PCNT_PLUS_CNT_RST_U6_V 0x1 +#define PCNT_PLUS_CNT_RST_U6_S 12 +/* PCNT_CNT_PAUSE_U5 : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Set this bit to pause unit5's counter.*/ +#define PCNT_CNT_PAUSE_U5 (BIT(11)) +#define PCNT_CNT_PAUSE_U5_M (BIT(11)) +#define PCNT_CNT_PAUSE_U5_V 0x1 +#define PCNT_CNT_PAUSE_U5_S 11 +/* PCNT_PLUS_CNT_RST_U5 : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: Set this bit to clear unit5's counter.*/ +#define PCNT_PLUS_CNT_RST_U5 (BIT(10)) +#define PCNT_PLUS_CNT_RST_U5_M (BIT(10)) +#define PCNT_PLUS_CNT_RST_U5_V 0x1 +#define PCNT_PLUS_CNT_RST_U5_S 10 +/* PCNT_CNT_PAUSE_U4 : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to pause unit4's counter.*/ +#define PCNT_CNT_PAUSE_U4 (BIT(9)) +#define PCNT_CNT_PAUSE_U4_M (BIT(9)) +#define PCNT_CNT_PAUSE_U4_V 0x1 +#define PCNT_CNT_PAUSE_U4_S 9 +/* PCNT_PLUS_CNT_RST_U4 : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: Set this bit to clear unit4's counter.*/ +#define PCNT_PLUS_CNT_RST_U4 (BIT(8)) +#define PCNT_PLUS_CNT_RST_U4_M (BIT(8)) +#define PCNT_PLUS_CNT_RST_U4_V 0x1 +#define PCNT_PLUS_CNT_RST_U4_S 8 +/* PCNT_CNT_PAUSE_U3 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to pause unit3's counter.*/ +#define PCNT_CNT_PAUSE_U3 (BIT(7)) +#define PCNT_CNT_PAUSE_U3_M (BIT(7)) +#define PCNT_CNT_PAUSE_U3_V 0x1 +#define PCNT_CNT_PAUSE_U3_S 7 +/* PCNT_PLUS_CNT_RST_U3 : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: Set this bit to clear unit3's counter.*/ +#define PCNT_PLUS_CNT_RST_U3 (BIT(6)) +#define PCNT_PLUS_CNT_RST_U3_M (BIT(6)) +#define PCNT_PLUS_CNT_RST_U3_V 0x1 +#define PCNT_PLUS_CNT_RST_U3_S 6 +/* PCNT_CNT_PAUSE_U2 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to pause unit2's counter.*/ +#define PCNT_CNT_PAUSE_U2 (BIT(5)) +#define PCNT_CNT_PAUSE_U2_M (BIT(5)) +#define PCNT_CNT_PAUSE_U2_V 0x1 +#define PCNT_CNT_PAUSE_U2_S 5 +/* PCNT_PLUS_CNT_RST_U2 : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: Set this bit to clear unit2's counter.*/ +#define PCNT_PLUS_CNT_RST_U2 (BIT(4)) +#define PCNT_PLUS_CNT_RST_U2_M (BIT(4)) +#define PCNT_PLUS_CNT_RST_U2_V 0x1 +#define PCNT_PLUS_CNT_RST_U2_S 4 +/* PCNT_CNT_PAUSE_U1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to pause unit1's counter.*/ +#define PCNT_CNT_PAUSE_U1 (BIT(3)) +#define PCNT_CNT_PAUSE_U1_M (BIT(3)) +#define PCNT_CNT_PAUSE_U1_V 0x1 +#define PCNT_CNT_PAUSE_U1_S 3 +/* PCNT_PLUS_CNT_RST_U1 : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: Set this bit to clear unit1's counter.*/ +#define PCNT_PLUS_CNT_RST_U1 (BIT(2)) +#define PCNT_PLUS_CNT_RST_U1_M (BIT(2)) +#define PCNT_PLUS_CNT_RST_U1_V 0x1 +#define PCNT_PLUS_CNT_RST_U1_S 2 +/* PCNT_CNT_PAUSE_U0 : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to pause unit0's counter.*/ +#define PCNT_CNT_PAUSE_U0 (BIT(1)) +#define PCNT_CNT_PAUSE_U0_M (BIT(1)) +#define PCNT_CNT_PAUSE_U0_V 0x1 +#define PCNT_CNT_PAUSE_U0_S 1 +/* PCNT_PLUS_CNT_RST_U0 : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: Set this bit to clear unit0's counter.*/ +#define PCNT_PLUS_CNT_RST_U0 (BIT(0)) +#define PCNT_PLUS_CNT_RST_U0_M (BIT(0)) +#define PCNT_PLUS_CNT_RST_U0_V 0x1 +#define PCNT_PLUS_CNT_RST_U0_S 0 + +#define PCNT_DATE_REG (DR_REG_PCNT_BASE + 0x00fc) +/* PCNT_DATE : R/W ;bitpos:[31:0] ;default: 32'h14122600 ; */ +/*description: */ +#define PCNT_DATE 0xFFFFFFFF +#define PCNT_DATE_M ((PCNT_DATE_V)<<(PCNT_DATE_S)) +#define PCNT_DATE_V 0xFFFFFFFF +#define PCNT_DATE_S 0 + + + + +#endif /*_SOC_PCNT_REG_H_ */ + + diff --git a/tools/sdk/include/esp32/soc/pcnt_struct.h b/tools/sdk/include/esp32/soc/pcnt_struct.h new file mode 100644 index 00000000..eef64a33 --- /dev/null +++ b/tools/sdk/include/esp32/soc/pcnt_struct.h @@ -0,0 +1,161 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_PCNT_STRUCT_H_ +#define _SOC_PCNT_STRUCT_H_ +typedef volatile struct { + struct{ + union { + struct { + uint32_t filter_thres: 10; /*This register is used to filter pulse whose width is smaller than this value for unit0.*/ + uint32_t filter_en: 1; /*This is the enable bit for filtering input signals for unit0.*/ + uint32_t thr_zero_en: 1; /*This is the enable bit for comparing unit0's count with 0 value.*/ + uint32_t thr_h_lim_en: 1; /*This is the enable bit for comparing unit0's count with thr_h_lim value.*/ + uint32_t thr_l_lim_en: 1; /*This is the enable bit for comparing unit0's count with thr_l_lim value.*/ + uint32_t thr_thres0_en: 1; /*This is the enable bit for comparing unit0's count with thres0 value.*/ + uint32_t thr_thres1_en: 1; /*This is the enable bit for comparing unit0's count with thres1 value .*/ + uint32_t ch0_neg_mode: 2; /*This register is used to control the mode of channel0's input neg-edge signal for unit0. 2'd1：increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ + uint32_t ch0_pos_mode: 2; /*This register is used to control the mode of channel0's input pos-edge signal for unit0. 2'd1：increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ + uint32_t ch0_hctrl_mode: 2; /*This register is used to control the mode of channel0's high control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/ + uint32_t ch0_lctrl_mode: 2; /*This register is used to control the mode of channel0's low control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/ + uint32_t ch1_neg_mode: 2; /*This register is used to control the mode of channel1's input neg-edge signal for unit0. 2'd1：increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ + uint32_t ch1_pos_mode: 2; /*This register is used to control the mode of channel1's input pos-edge signal for unit0. 2'd1：increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ + uint32_t ch1_hctrl_mode: 2; /*This register is used to control the mode of channel1's high control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/ + uint32_t ch1_lctrl_mode: 2; /*This register is used to control the mode of channel1's low control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/ + }; + uint32_t val; + } conf0; + union { + struct { + uint32_t cnt_thres0:16; /*This register is used to configure thres0 value for unit0.*/ + uint32_t cnt_thres1:16; /*This register is used to configure thres1 value for unit0.*/ + }; + uint32_t val; + } conf1; + union { + struct { + uint32_t cnt_h_lim:16; /*This register is used to configure thr_h_lim value for unit0.*/ + uint32_t cnt_l_lim:16; /*This register is used to configure thr_l_lim value for unit0.*/ + }; + uint32_t val; + } conf2; + } conf_unit[8]; + union { + struct { + uint32_t cnt_val : 16; /*This register stores the current pulse count value for unit0.*/ + uint32_t reserved16: 16; + }; + uint32_t val; + } cnt_unit[8]; + union { + struct { + uint32_t cnt_thr_event_u0: 1; /*This is the interrupt raw bit for channel0 event.*/ + uint32_t cnt_thr_event_u1: 1; /*This is the interrupt raw bit for channel1 event.*/ + uint32_t cnt_thr_event_u2: 1; /*This is the interrupt raw bit for channel2 event.*/ + uint32_t cnt_thr_event_u3: 1; /*This is the interrupt raw bit for channel3 event.*/ + uint32_t cnt_thr_event_u4: 1; /*This is the interrupt raw bit for channel4 event.*/ + uint32_t cnt_thr_event_u5: 1; /*This is the interrupt raw bit for channel5 event.*/ + uint32_t cnt_thr_event_u6: 1; /*This is the interrupt raw bit for channel6 event.*/ + uint32_t cnt_thr_event_u7: 1; /*This is the interrupt raw bit for channel7 event.*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t cnt_thr_event_u0: 1; /*This is the interrupt status bit for channel0 event.*/ + uint32_t cnt_thr_event_u1: 1; /*This is the interrupt status bit for channel1 event.*/ + uint32_t cnt_thr_event_u2: 1; /*This is the interrupt status bit for channel2 event.*/ + uint32_t cnt_thr_event_u3: 1; /*This is the interrupt status bit for channel3 event.*/ + uint32_t cnt_thr_event_u4: 1; /*This is the interrupt status bit for channel4 event.*/ + uint32_t cnt_thr_event_u5: 1; /*This is the interrupt status bit for channel5 event.*/ + uint32_t cnt_thr_event_u6: 1; /*This is the interrupt status bit for channel6 event.*/ + uint32_t cnt_thr_event_u7: 1; /*This is the interrupt status bit for channel7 event.*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t cnt_thr_event_u0: 1; /*This is the interrupt enable bit for channel0 event.*/ + uint32_t cnt_thr_event_u1: 1; /*This is the interrupt enable bit for channel1 event.*/ + uint32_t cnt_thr_event_u2: 1; /*This is the interrupt enable bit for channel2 event.*/ + uint32_t cnt_thr_event_u3: 1; /*This is the interrupt enable bit for channel3 event.*/ + uint32_t cnt_thr_event_u4: 1; /*This is the interrupt enable bit for channel4 event.*/ + uint32_t cnt_thr_event_u5: 1; /*This is the interrupt enable bit for channel5 event.*/ + uint32_t cnt_thr_event_u6: 1; /*This is the interrupt enable bit for channel6 event.*/ + uint32_t cnt_thr_event_u7: 1; /*This is the interrupt enable bit for channel7 event.*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t cnt_thr_event_u0: 1; /*Set this bit to clear channel0 event interrupt.*/ + uint32_t cnt_thr_event_u1: 1; /*Set this bit to clear channel1 event interrupt.*/ + uint32_t cnt_thr_event_u2: 1; /*Set this bit to clear channel2 event interrupt.*/ + uint32_t cnt_thr_event_u3: 1; /*Set this bit to clear channel3 event interrupt.*/ + uint32_t cnt_thr_event_u4: 1; /*Set this bit to clear channel4 event interrupt.*/ + uint32_t cnt_thr_event_u5: 1; /*Set this bit to clear channel5 event interrupt.*/ + uint32_t cnt_thr_event_u6: 1; /*Set this bit to clear channel6 event interrupt.*/ + uint32_t cnt_thr_event_u7: 1; /*Set this bit to clear channel7 event interrupt.*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } int_clr; + uint32_t status_unit[8]; + union { + struct { + uint32_t cnt_rst_u0: 1; /*Set this bit to clear unit0's counter.*/ + uint32_t cnt_pause_u0: 1; /*Set this bit to pause unit0's counter.*/ + uint32_t cnt_rst_u1: 1; /*Set this bit to clear unit1's counter.*/ + uint32_t cnt_pause_u1: 1; /*Set this bit to pause unit1's counter.*/ + uint32_t cnt_rst_u2: 1; /*Set this bit to clear unit2's counter.*/ + uint32_t cnt_pause_u2: 1; /*Set this bit to pause unit2's counter.*/ + uint32_t cnt_rst_u3: 1; /*Set this bit to clear unit3's counter.*/ + uint32_t cnt_pause_u3: 1; /*Set this bit to pause unit3's counter.*/ + uint32_t cnt_rst_u4: 1; /*Set this bit to clear unit4's counter.*/ + uint32_t cnt_pause_u4: 1; /*Set this bit to pause unit4's counter.*/ + uint32_t cnt_rst_u5: 1; /*Set this bit to clear unit5's counter.*/ + uint32_t cnt_pause_u5: 1; /*Set this bit to pause unit5's counter.*/ + uint32_t cnt_rst_u6: 1; /*Set this bit to clear unit6's counter.*/ + uint32_t cnt_pause_u6: 1; /*Set this bit to pause unit6's counter.*/ + uint32_t cnt_rst_u7: 1; /*Set this bit to clear unit7's counter.*/ + uint32_t cnt_pause_u7: 1; /*Set this bit to pause unit7's counter.*/ + uint32_t clk_en: 1; + uint32_t reserved17: 15; + }; + uint32_t val; + } ctrl; + uint32_t reserved_b4; + uint32_t reserved_b8; + uint32_t reserved_bc; + uint32_t reserved_c0; + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t reserved_cc; + uint32_t reserved_d0; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t reserved_f8; + uint32_t date; /**/ +} pcnt_dev_t; +extern pcnt_dev_t PCNT; +#endif /* _SOC_PCNT_STRUCT_H_ */ diff --git a/tools/sdk/include/esp32/soc/pid.h b/tools/sdk/include/esp32/soc/pid.h new file mode 100644 index 00000000..bd4e9f26 --- /dev/null +++ b/tools/sdk/include/esp32/soc/pid.h @@ -0,0 +1,65 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_PID_H_ +#define _SOC_PID_H_ + +#define PROPID_GEN_BASE 0x3FF1F000 +//Bits 1..7: 1 if interrupt will be triggering PID change +#define PROPID_CONFIG_INTERRUPT_ENABLE ((PROPID_GEN_BASE)+0x000) +//Vectors for the various interrupt handlers +#define PROPID_CONFIG_INTERRUPT_ADDR_1 ((PROPID_GEN_BASE)+0x004) +#define PROPID_CONFIG_INTERRUPT_ADDR_2 ((PROPID_GEN_BASE)+0x008) +#define PROPID_CONFIG_INTERRUPT_ADDR_3 ((PROPID_GEN_BASE)+0x00C) +#define PROPID_CONFIG_INTERRUPT_ADDR_4 ((PROPID_GEN_BASE)+0x010) +#define PROPID_CONFIG_INTERRUPT_ADDR_5 ((PROPID_GEN_BASE)+0x014) +#define PROPID_CONFIG_INTERRUPT_ADDR_6 ((PROPID_GEN_BASE)+0x018) +#define PROPID_CONFIG_INTERRUPT_ADDR_7 ((PROPID_GEN_BASE)+0x01C) + +//Delay, in CPU cycles, before switching to new PID +#define PROPID_CONFIG_PID_DELAY ((PROPID_GEN_BASE)+0x020) +#define PROPID_CONFIG_NMI_DELAY ((PROPID_GEN_BASE)+0x024) + +//Last detected interrupt. Set by hw on int. +#define PROPID_TABLE_LEVEL ((PROPID_GEN_BASE)+0x028) +//PID/prev int data for each int +#define PROPID_FROM_1 ((PROPID_GEN_BASE)+0x02C) +#define PROPID_FROM_2 ((PROPID_GEN_BASE)+0x030) +#define PROPID_FROM_3 ((PROPID_GEN_BASE)+0x034) +#define PROPID_FROM_4 ((PROPID_GEN_BASE)+0x038) +#define PROPID_FROM_5 ((PROPID_GEN_BASE)+0x03C) +#define PROPID_FROM_6 ((PROPID_GEN_BASE)+0x040) +#define PROPID_FROM_7 ((PROPID_GEN_BASE)+0x044) +#define PROPID_FROM_PID_MASK 0x7 +#define PROPID_FROM_PID_S 0 +#define PROPID_FROM_INT_MASK 0xF +#define PROPID_FROM_INT_S 3 + +//PID to be set after confirm routine +#define PROPID_PID_NEW ((PROPID_GEN_BASE)+0x048) +//Write to kick off PID change +#define PROPID_PID_CONFIRM ((PROPID_GEN_BASE)+0x04c) +//current PID? +#define PROPID_PID_REG ((PROPID_GEN_BASE)+0x050) + +//Write to mask NMI +#define PROPID_PID_NMI_MASK_HW_ENABLE ((PROPID_GEN_BASE)+0x054) +//Write to unmask NMI +#define PROPID_PID_NMI_MASK_HW_DISABLE ((PROPID_GEN_BASE)+0x058) +#define PROPID_PID_NMI_MASK_HW_REG ((PROPID_GEN_BASE)+0x05c) + +//Debug regs +#define PROPID_PID ((PROPID_GEN_BASE)+0x060) +#define PROPID_NMI_MASK_HW ((PROPID_GEN_BASE)+0x064) + +#endif /* _SOC_PID_H_ */ diff --git a/tools/sdk/include/esp32/soc/rmt_reg.h b/tools/sdk/include/esp32/soc/rmt_reg.h new file mode 100644 index 00000000..a95aa6c0 --- /dev/null +++ b/tools/sdk/include/esp32/soc/rmt_reg.h @@ -0,0 +1,2171 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_RMT_REG_H_ +#define _SOC_RMT_REG_H_ + +#include "soc.h" +#define RMT_CH0DATA_REG (DR_REG_RMT_BASE + 0x0000) + +#define RMT_CH1DATA_REG (DR_REG_RMT_BASE + 0x0004) + +#define RMT_CH2DATA_REG (DR_REG_RMT_BASE + 0x0008) + +#define RMT_CH3DATA_REG (DR_REG_RMT_BASE + 0x000c) + +#define RMT_CH4DATA_REG (DR_REG_RMT_BASE + 0x0010) + +#define RMT_CH5DATA_REG (DR_REG_RMT_BASE + 0x0014) + +#define RMT_CH6DATA_REG (DR_REG_RMT_BASE + 0x0018) + +#define RMT_CH7DATA_REG (DR_REG_RMT_BASE + 0x001c) + +#define RMT_CH0CONF0_REG (DR_REG_RMT_BASE + 0x0020) +/* RMT_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: This bit is used to control clock.when software config RMT + internal registers it controls the register clock.*/ +#define RMT_CLK_EN (BIT(31)) +#define RMT_CLK_EN_M (BIT(31)) +#define RMT_CLK_EN_V 0x1 +#define RMT_CLK_EN_S 31 +/* RMT_MEM_PD : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: This bit is used to reduce power consumed by mem. 1:mem is in low power state.*/ +#define RMT_MEM_PD (BIT(30)) +#define RMT_MEM_PD_M (BIT(30)) +#define RMT_MEM_PD_V 0x1 +#define RMT_MEM_PD_S 30 +/* RMT_CARRIER_OUT_LV_CH0 : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: This bit is used to configure the way carrier wave is modulated + for channel0.1'b1:transmit on low output level 1'b0:transmit on high output level.*/ +#define RMT_CARRIER_OUT_LV_CH0 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH0_M (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH0_V 0x1 +#define RMT_CARRIER_OUT_LV_CH0_S 29 +/* RMT_CARRIER_EN_CH0 : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: This is the carrier modulation enable control bit for channel0.*/ +#define RMT_CARRIER_EN_CH0 (BIT(28)) +#define RMT_CARRIER_EN_CH0_M (BIT(28)) +#define RMT_CARRIER_EN_CH0_V 0x1 +#define RMT_CARRIER_EN_CH0_S 28 +/* RMT_MEM_SIZE_CH0 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ +/*description: This register is used to configure the the amount of memory blocks + allocated to channel0.*/ +#define RMT_MEM_SIZE_CH0 0x0000000F +#define RMT_MEM_SIZE_CH0_M ((RMT_MEM_SIZE_CH0_V)<<(RMT_MEM_SIZE_CH0_S)) +#define RMT_MEM_SIZE_CH0_V 0xF +#define RMT_MEM_SIZE_CH0_S 24 +/* RMT_IDLE_THRES_CH0 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ +/*description: In receive mode when no edge is detected on the input signal + for longer than reg_idle_thres_ch0 then the receive process is done.*/ +#define RMT_IDLE_THRES_CH0 0x0000FFFF +#define RMT_IDLE_THRES_CH0_M ((RMT_IDLE_THRES_CH0_V)<<(RMT_IDLE_THRES_CH0_S)) +#define RMT_IDLE_THRES_CH0_V 0xFFFF +#define RMT_IDLE_THRES_CH0_S 8 +/* RMT_DIV_CNT_CH0 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ +/*description: This register is used to configure the frequency divider's factor in channel0.*/ +#define RMT_DIV_CNT_CH0 0x000000FF +#define RMT_DIV_CNT_CH0_M ((RMT_DIV_CNT_CH0_V)<<(RMT_DIV_CNT_CH0_S)) +#define RMT_DIV_CNT_CH0_V 0xFF +#define RMT_DIV_CNT_CH0_S 0 + +#define RMT_CH0CONF1_REG (DR_REG_RMT_BASE + 0x0024) +/* RMT_IDLE_OUT_EN_CH0 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for channel0 in IDLE state.*/ +#define RMT_IDLE_OUT_EN_CH0 (BIT(19)) +#define RMT_IDLE_OUT_EN_CH0_M (BIT(19)) +#define RMT_IDLE_OUT_EN_CH0_V 0x1 +#define RMT_IDLE_OUT_EN_CH0_S 19 +/* RMT_IDLE_OUT_LV_CH0 : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This bit configures the output signal's level for channel0 in IDLE state.*/ +#define RMT_IDLE_OUT_LV_CH0 (BIT(18)) +#define RMT_IDLE_OUT_LV_CH0_M (BIT(18)) +#define RMT_IDLE_OUT_LV_CH0_V 0x1 +#define RMT_IDLE_OUT_LV_CH0_S 18 +/* RMT_REF_ALWAYS_ON_CH0 : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ +#define RMT_REF_ALWAYS_ON_CH0 (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH0_M (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH0_V 0x1 +#define RMT_REF_ALWAYS_ON_CH0_S 17 +/* RMT_REF_CNT_RST_CH0 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This bit is used to reset divider in channel0.*/ +#define RMT_REF_CNT_RST_CH0 (BIT(16)) +#define RMT_REF_CNT_RST_CH0_M (BIT(16)) +#define RMT_REF_CNT_RST_CH0_V 0x1 +#define RMT_REF_CNT_RST_CH0_S 16 +/* RMT_RX_FILTER_THRES_CH0 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ +/*description: in receive mode channel0 ignore input pulse when the pulse width + is smaller then this value.*/ +#define RMT_RX_FILTER_THRES_CH0 0x000000FF +#define RMT_RX_FILTER_THRES_CH0_M ((RMT_RX_FILTER_THRES_CH0_V)<<(RMT_RX_FILTER_THRES_CH0_S)) +#define RMT_RX_FILTER_THRES_CH0_V 0xFF +#define RMT_RX_FILTER_THRES_CH0_S 8 +/* RMT_RX_FILTER_EN_CH0 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the receive filter enable bit for channel0.*/ +#define RMT_RX_FILTER_EN_CH0 (BIT(7)) +#define RMT_RX_FILTER_EN_CH0_M (BIT(7)) +#define RMT_RX_FILTER_EN_CH0_V 0x1 +#define RMT_RX_FILTER_EN_CH0_S 7 +/* RMT_TX_CONTI_MODE_CH0 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to continue sending from the first data to the + last data in channel0 again and again.*/ +#define RMT_TX_CONTI_MODE_CH0 (BIT(6)) +#define RMT_TX_CONTI_MODE_CH0_M (BIT(6)) +#define RMT_TX_CONTI_MODE_CH0_V 0x1 +#define RMT_TX_CONTI_MODE_CH0_S 6 +/* RMT_MEM_OWNER_CH0 : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: This is the mark of channel0's ram usage right.1'b1：receiver + uses the ram 0：transmitter uses the ram*/ +#define RMT_MEM_OWNER_CH0 (BIT(5)) +#define RMT_MEM_OWNER_CH0_M (BIT(5)) +#define RMT_MEM_OWNER_CH0_V 0x1 +#define RMT_MEM_OWNER_CH0_S 5 +/* RMT_APB_MEM_RST_CH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to reset W/R ram address for channel0 by apb fifo access*/ +#define RMT_APB_MEM_RST_CH0 (BIT(4)) +#define RMT_APB_MEM_RST_CH0_M (BIT(4)) +#define RMT_APB_MEM_RST_CH0_V 0x1 +#define RMT_APB_MEM_RST_CH0_S 4 +/* RMT_MEM_RD_RST_CH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to reset read ram address for channel0 by transmitter access.*/ +#define RMT_MEM_RD_RST_CH0 (BIT(3)) +#define RMT_MEM_RD_RST_CH0_M (BIT(3)) +#define RMT_MEM_RD_RST_CH0_V 0x1 +#define RMT_MEM_RD_RST_CH0_S 3 +/* RMT_MEM_WR_RST_CH0 : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Set this bit to reset write ram address for channel0 by receiver access.*/ +#define RMT_MEM_WR_RST_CH0 (BIT(2)) +#define RMT_MEM_WR_RST_CH0_M (BIT(2)) +#define RMT_MEM_WR_RST_CH0_V 0x1 +#define RMT_MEM_WR_RST_CH0_S 2 +/* RMT_RX_EN_CH0 : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: Set this bit to enbale receving data for channel0.*/ +#define RMT_RX_EN_CH0 (BIT(1)) +#define RMT_RX_EN_CH0_M (BIT(1)) +#define RMT_RX_EN_CH0_V 0x1 +#define RMT_RX_EN_CH0_S 1 +/* RMT_TX_START_CH0 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to start sending data for channel0.*/ +#define RMT_TX_START_CH0 (BIT(0)) +#define RMT_TX_START_CH0_M (BIT(0)) +#define RMT_TX_START_CH0_V 0x1 +#define RMT_TX_START_CH0_S 0 + +#define RMT_CH1CONF0_REG (DR_REG_RMT_BASE + 0x0028) +/* RMT_CARRIER_OUT_LV_CH1 : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: This bit is used to configure the way carrier wave is modulated + for channel1.1'b1:transmit on low output level 1'b0:transmit on high output level.*/ +#define RMT_CARRIER_OUT_LV_CH1 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH1_M (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH1_V 0x1 +#define RMT_CARRIER_OUT_LV_CH1_S 29 +/* RMT_CARRIER_EN_CH1 : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: This is the carrier modulation enable control bit for channel1.*/ +#define RMT_CARRIER_EN_CH1 (BIT(28)) +#define RMT_CARRIER_EN_CH1_M (BIT(28)) +#define RMT_CARRIER_EN_CH1_V 0x1 +#define RMT_CARRIER_EN_CH1_S 28 +/* RMT_MEM_SIZE_CH1 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ +/*description: This register is used to configure the the amount of memory blocks + allocated to channel1.*/ +#define RMT_MEM_SIZE_CH1 0x0000000F +#define RMT_MEM_SIZE_CH1_M ((RMT_MEM_SIZE_CH1_V)<<(RMT_MEM_SIZE_CH1_S)) +#define RMT_MEM_SIZE_CH1_V 0xF +#define RMT_MEM_SIZE_CH1_S 24 +/* RMT_IDLE_THRES_CH1 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ +/*description: This register is used to configure the the amount of memory blocks + allocated to channel1.*/ +#define RMT_IDLE_THRES_CH1 0x0000FFFF +#define RMT_IDLE_THRES_CH1_M ((RMT_IDLE_THRES_CH1_V)<<(RMT_IDLE_THRES_CH1_S)) +#define RMT_IDLE_THRES_CH1_V 0xFFFF +#define RMT_IDLE_THRES_CH1_S 8 +/* RMT_DIV_CNT_CH1 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ +/*description: This register is used to configure the frequency divider's factor in channel1.*/ +#define RMT_DIV_CNT_CH1 0x000000FF +#define RMT_DIV_CNT_CH1_M ((RMT_DIV_CNT_CH1_V)<<(RMT_DIV_CNT_CH1_S)) +#define RMT_DIV_CNT_CH1_V 0xFF +#define RMT_DIV_CNT_CH1_S 0 + +#define RMT_CH1CONF1_REG (DR_REG_RMT_BASE + 0x002c) +/* RMT_IDLE_OUT_EN_CH1 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for channel1 in IDLE state.*/ +#define RMT_IDLE_OUT_EN_CH1 (BIT(19)) +#define RMT_IDLE_OUT_EN_CH1_M (BIT(19)) +#define RMT_IDLE_OUT_EN_CH1_V 0x1 +#define RMT_IDLE_OUT_EN_CH1_S 19 +/* RMT_IDLE_OUT_LV_CH1 : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This bit configures the output signal's level for channel1 in IDLE state.*/ +#define RMT_IDLE_OUT_LV_CH1 (BIT(18)) +#define RMT_IDLE_OUT_LV_CH1_M (BIT(18)) +#define RMT_IDLE_OUT_LV_CH1_V 0x1 +#define RMT_IDLE_OUT_LV_CH1_S 18 +/* RMT_REF_ALWAYS_ON_CH1 : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ +#define RMT_REF_ALWAYS_ON_CH1 (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH1_M (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH1_V 0x1 +#define RMT_REF_ALWAYS_ON_CH1_S 17 +/* RMT_REF_CNT_RST_CH1 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This bit is used to reset divider in channel1.*/ +#define RMT_REF_CNT_RST_CH1 (BIT(16)) +#define RMT_REF_CNT_RST_CH1_M (BIT(16)) +#define RMT_REF_CNT_RST_CH1_V 0x1 +#define RMT_REF_CNT_RST_CH1_S 16 +/* RMT_RX_FILTER_THRES_CH1 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ +/*description: in receive mode channel1 ignore input pulse when the pulse width + is smaller then this value.*/ +#define RMT_RX_FILTER_THRES_CH1 0x000000FF +#define RMT_RX_FILTER_THRES_CH1_M ((RMT_RX_FILTER_THRES_CH1_V)<<(RMT_RX_FILTER_THRES_CH1_S)) +#define RMT_RX_FILTER_THRES_CH1_V 0xFF +#define RMT_RX_FILTER_THRES_CH1_S 8 +/* RMT_RX_FILTER_EN_CH1 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the receive filter enable bit for channel1.*/ +#define RMT_RX_FILTER_EN_CH1 (BIT(7)) +#define RMT_RX_FILTER_EN_CH1_M (BIT(7)) +#define RMT_RX_FILTER_EN_CH1_V 0x1 +#define RMT_RX_FILTER_EN_CH1_S 7 +/* RMT_TX_CONTI_MODE_CH1 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to continue sending from the first data to the + last data in channel1 again and again.*/ +#define RMT_TX_CONTI_MODE_CH1 (BIT(6)) +#define RMT_TX_CONTI_MODE_CH1_M (BIT(6)) +#define RMT_TX_CONTI_MODE_CH1_V 0x1 +#define RMT_TX_CONTI_MODE_CH1_S 6 +/* RMT_MEM_OWNER_CH1 : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: This is the mark of channel1's ram usage right.1'b1：receiver + uses the ram 0：transmitter uses the ram*/ +#define RMT_MEM_OWNER_CH1 (BIT(5)) +#define RMT_MEM_OWNER_CH1_M (BIT(5)) +#define RMT_MEM_OWNER_CH1_V 0x1 +#define RMT_MEM_OWNER_CH1_S 5 +/* RMT_APB_MEM_RST_CH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to reset W/R ram address for channel1 by apb fifo access*/ +#define RMT_APB_MEM_RST_CH1 (BIT(4)) +#define RMT_APB_MEM_RST_CH1_M (BIT(4)) +#define RMT_APB_MEM_RST_CH1_V 0x1 +#define RMT_APB_MEM_RST_CH1_S 4 +/* RMT_MEM_RD_RST_CH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to reset read ram address for channel1 by transmitter access.*/ +#define RMT_MEM_RD_RST_CH1 (BIT(3)) +#define RMT_MEM_RD_RST_CH1_M (BIT(3)) +#define RMT_MEM_RD_RST_CH1_V 0x1 +#define RMT_MEM_RD_RST_CH1_S 3 +/* RMT_MEM_WR_RST_CH1 : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Set this bit to reset write ram address for channel1 by receiver access.*/ +#define RMT_MEM_WR_RST_CH1 (BIT(2)) +#define RMT_MEM_WR_RST_CH1_M (BIT(2)) +#define RMT_MEM_WR_RST_CH1_V 0x1 +#define RMT_MEM_WR_RST_CH1_S 2 +/* RMT_RX_EN_CH1 : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: Set this bit to enbale receving data for channel1.*/ +#define RMT_RX_EN_CH1 (BIT(1)) +#define RMT_RX_EN_CH1_M (BIT(1)) +#define RMT_RX_EN_CH1_V 0x1 +#define RMT_RX_EN_CH1_S 1 +/* RMT_TX_START_CH1 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to start sending data for channel1.*/ +#define RMT_TX_START_CH1 (BIT(0)) +#define RMT_TX_START_CH1_M (BIT(0)) +#define RMT_TX_START_CH1_V 0x1 +#define RMT_TX_START_CH1_S 0 + +#define RMT_CH2CONF0_REG (DR_REG_RMT_BASE + 0x0030) +/* RMT_CARRIER_OUT_LV_CH2 : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: This bit is used to configure carrier wave's position for channel2.1'b1:add + on low level 1'b0:add on high level.*/ +#define RMT_CARRIER_OUT_LV_CH2 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH2_M (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH2_V 0x1 +#define RMT_CARRIER_OUT_LV_CH2_S 29 +/* RMT_CARRIER_EN_CH2 : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: This is the carrier modulation enable control bit for channel2.*/ +#define RMT_CARRIER_EN_CH2 (BIT(28)) +#define RMT_CARRIER_EN_CH2_M (BIT(28)) +#define RMT_CARRIER_EN_CH2_V 0x1 +#define RMT_CARRIER_EN_CH2_S 28 +/* RMT_MEM_SIZE_CH2 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ +/*description: This register is used to configure the the amount of memory blocks + allocated to channel2.*/ +#define RMT_MEM_SIZE_CH2 0x0000000F +#define RMT_MEM_SIZE_CH2_M ((RMT_MEM_SIZE_CH2_V)<<(RMT_MEM_SIZE_CH2_S)) +#define RMT_MEM_SIZE_CH2_V 0xF +#define RMT_MEM_SIZE_CH2_S 24 +/* RMT_IDLE_THRES_CH2 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ +/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch2 + then the receive process is done.*/ +#define RMT_IDLE_THRES_CH2 0x0000FFFF +#define RMT_IDLE_THRES_CH2_M ((RMT_IDLE_THRES_CH2_V)<<(RMT_IDLE_THRES_CH2_S)) +#define RMT_IDLE_THRES_CH2_V 0xFFFF +#define RMT_IDLE_THRES_CH2_S 8 +/* RMT_DIV_CNT_CH2 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ +/*description: This register is used to configure the frequency divider's factor in channel2.*/ +#define RMT_DIV_CNT_CH2 0x000000FF +#define RMT_DIV_CNT_CH2_M ((RMT_DIV_CNT_CH2_V)<<(RMT_DIV_CNT_CH2_S)) +#define RMT_DIV_CNT_CH2_V 0xFF +#define RMT_DIV_CNT_CH2_S 0 + +#define RMT_CH2CONF1_REG (DR_REG_RMT_BASE + 0x0034) +/* RMT_IDLE_OUT_EN_CH2 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for channel2 in IDLE state.*/ +#define RMT_IDLE_OUT_EN_CH2 (BIT(19)) +#define RMT_IDLE_OUT_EN_CH2_M (BIT(19)) +#define RMT_IDLE_OUT_EN_CH2_V 0x1 +#define RMT_IDLE_OUT_EN_CH2_S 19 +/* RMT_IDLE_OUT_LV_CH2 : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This bit configures the output signal's level for channel2 in IDLE state.*/ +#define RMT_IDLE_OUT_LV_CH2 (BIT(18)) +#define RMT_IDLE_OUT_LV_CH2_M (BIT(18)) +#define RMT_IDLE_OUT_LV_CH2_V 0x1 +#define RMT_IDLE_OUT_LV_CH2_S 18 +/* RMT_REF_ALWAYS_ON_CH2 : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ +#define RMT_REF_ALWAYS_ON_CH2 (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH2_M (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH2_V 0x1 +#define RMT_REF_ALWAYS_ON_CH2_S 17 +/* RMT_REF_CNT_RST_CH2 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This bit is used to reset divider in channel2.*/ +#define RMT_REF_CNT_RST_CH2 (BIT(16)) +#define RMT_REF_CNT_RST_CH2_M (BIT(16)) +#define RMT_REF_CNT_RST_CH2_V 0x1 +#define RMT_REF_CNT_RST_CH2_S 16 +/* RMT_RX_FILTER_THRES_CH2 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ +/*description: in receive mode channel2 ignore input pulse when the pulse width + is smaller then this value.*/ +#define RMT_RX_FILTER_THRES_CH2 0x000000FF +#define RMT_RX_FILTER_THRES_CH2_M ((RMT_RX_FILTER_THRES_CH2_V)<<(RMT_RX_FILTER_THRES_CH2_S)) +#define RMT_RX_FILTER_THRES_CH2_V 0xFF +#define RMT_RX_FILTER_THRES_CH2_S 8 +/* RMT_RX_FILTER_EN_CH2 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the receive filter enable bit for channel2.*/ +#define RMT_RX_FILTER_EN_CH2 (BIT(7)) +#define RMT_RX_FILTER_EN_CH2_M (BIT(7)) +#define RMT_RX_FILTER_EN_CH2_V 0x1 +#define RMT_RX_FILTER_EN_CH2_S 7 +/* RMT_TX_CONTI_MODE_CH2 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to continue sending from the first data to the + last data in channel2.*/ +#define RMT_TX_CONTI_MODE_CH2 (BIT(6)) +#define RMT_TX_CONTI_MODE_CH2_M (BIT(6)) +#define RMT_TX_CONTI_MODE_CH2_V 0x1 +#define RMT_TX_CONTI_MODE_CH2_S 6 +/* RMT_MEM_OWNER_CH2 : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: This is the mark of channel2's ram usage right.1'b1：receiver + uses the ram 0：transmitter uses the ram*/ +#define RMT_MEM_OWNER_CH2 (BIT(5)) +#define RMT_MEM_OWNER_CH2_M (BIT(5)) +#define RMT_MEM_OWNER_CH2_V 0x1 +#define RMT_MEM_OWNER_CH2_S 5 +/* RMT_APB_MEM_RST_CH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to reset W/R ram address for channel2 by apb fifo access*/ +#define RMT_APB_MEM_RST_CH2 (BIT(4)) +#define RMT_APB_MEM_RST_CH2_M (BIT(4)) +#define RMT_APB_MEM_RST_CH2_V 0x1 +#define RMT_APB_MEM_RST_CH2_S 4 +/* RMT_MEM_RD_RST_CH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to reset read ram address for channel2 by transmitter access.*/ +#define RMT_MEM_RD_RST_CH2 (BIT(3)) +#define RMT_MEM_RD_RST_CH2_M (BIT(3)) +#define RMT_MEM_RD_RST_CH2_V 0x1 +#define RMT_MEM_RD_RST_CH2_S 3 +/* RMT_MEM_WR_RST_CH2 : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Set this bit to reset write ram address for channel2 by receiver access.*/ +#define RMT_MEM_WR_RST_CH2 (BIT(2)) +#define RMT_MEM_WR_RST_CH2_M (BIT(2)) +#define RMT_MEM_WR_RST_CH2_V 0x1 +#define RMT_MEM_WR_RST_CH2_S 2 +/* RMT_RX_EN_CH2 : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: Set this bit to enbale receving data for channel2.*/ +#define RMT_RX_EN_CH2 (BIT(1)) +#define RMT_RX_EN_CH2_M (BIT(1)) +#define RMT_RX_EN_CH2_V 0x1 +#define RMT_RX_EN_CH2_S 1 +/* RMT_TX_START_CH2 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to start sending data for channel2.*/ +#define RMT_TX_START_CH2 (BIT(0)) +#define RMT_TX_START_CH2_M (BIT(0)) +#define RMT_TX_START_CH2_V 0x1 +#define RMT_TX_START_CH2_S 0 + +#define RMT_CH3CONF0_REG (DR_REG_RMT_BASE + 0x0038) +/* RMT_CARRIER_OUT_LV_CH3 : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: This bit is used to configure carrier wave's position for channel3.1'b1:add + on low level 1'b0:add on high level.*/ +#define RMT_CARRIER_OUT_LV_CH3 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH3_M (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH3_V 0x1 +#define RMT_CARRIER_OUT_LV_CH3_S 29 +/* RMT_CARRIER_EN_CH3 : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: This is the carrier modulation enable control bit for channel3.*/ +#define RMT_CARRIER_EN_CH3 (BIT(28)) +#define RMT_CARRIER_EN_CH3_M (BIT(28)) +#define RMT_CARRIER_EN_CH3_V 0x1 +#define RMT_CARRIER_EN_CH3_S 28 +/* RMT_MEM_SIZE_CH3 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ +/*description: This register is used to configure the the amount of memory blocks + allocated to channel3.*/ +#define RMT_MEM_SIZE_CH3 0x0000000F +#define RMT_MEM_SIZE_CH3_M ((RMT_MEM_SIZE_CH3_V)<<(RMT_MEM_SIZE_CH3_S)) +#define RMT_MEM_SIZE_CH3_V 0xF +#define RMT_MEM_SIZE_CH3_S 24 +/* RMT_IDLE_THRES_CH3 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ +/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch3 + then the receive process is done.*/ +#define RMT_IDLE_THRES_CH3 0x0000FFFF +#define RMT_IDLE_THRES_CH3_M ((RMT_IDLE_THRES_CH3_V)<<(RMT_IDLE_THRES_CH3_S)) +#define RMT_IDLE_THRES_CH3_V 0xFFFF +#define RMT_IDLE_THRES_CH3_S 8 +/* RMT_DIV_CNT_CH3 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ +/*description: This register is used to configure the frequency divider's factor in channel3.*/ +#define RMT_DIV_CNT_CH3 0x000000FF +#define RMT_DIV_CNT_CH3_M ((RMT_DIV_CNT_CH3_V)<<(RMT_DIV_CNT_CH3_S)) +#define RMT_DIV_CNT_CH3_V 0xFF +#define RMT_DIV_CNT_CH3_S 0 + +#define RMT_CH3CONF1_REG (DR_REG_RMT_BASE + 0x003c) +/* RMT_IDLE_OUT_EN_CH3 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for channel3 in IDLE state.*/ +#define RMT_IDLE_OUT_EN_CH3 (BIT(19)) +#define RMT_IDLE_OUT_EN_CH3_M (BIT(19)) +#define RMT_IDLE_OUT_EN_CH3_V 0x1 +#define RMT_IDLE_OUT_EN_CH3_S 19 +/* RMT_IDLE_OUT_LV_CH3 : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This bit configures the output signal's level for channel3 in IDLE state.*/ +#define RMT_IDLE_OUT_LV_CH3 (BIT(18)) +#define RMT_IDLE_OUT_LV_CH3_M (BIT(18)) +#define RMT_IDLE_OUT_LV_CH3_V 0x1 +#define RMT_IDLE_OUT_LV_CH3_S 18 +/* RMT_REF_ALWAYS_ON_CH3 : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ +#define RMT_REF_ALWAYS_ON_CH3 (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH3_M (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH3_V 0x1 +#define RMT_REF_ALWAYS_ON_CH3_S 17 +/* RMT_REF_CNT_RST_CH3 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This bit is used to reset divider in channel3.*/ +#define RMT_REF_CNT_RST_CH3 (BIT(16)) +#define RMT_REF_CNT_RST_CH3_M (BIT(16)) +#define RMT_REF_CNT_RST_CH3_V 0x1 +#define RMT_REF_CNT_RST_CH3_S 16 +/* RMT_RX_FILTER_THRES_CH3 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ +/*description: in receive mode channel3 ignore input pulse when the pulse width + is smaller then this value.*/ +#define RMT_RX_FILTER_THRES_CH3 0x000000FF +#define RMT_RX_FILTER_THRES_CH3_M ((RMT_RX_FILTER_THRES_CH3_V)<<(RMT_RX_FILTER_THRES_CH3_S)) +#define RMT_RX_FILTER_THRES_CH3_V 0xFF +#define RMT_RX_FILTER_THRES_CH3_S 8 +/* RMT_RX_FILTER_EN_CH3 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the receive filter enable bit for channel3.*/ +#define RMT_RX_FILTER_EN_CH3 (BIT(7)) +#define RMT_RX_FILTER_EN_CH3_M (BIT(7)) +#define RMT_RX_FILTER_EN_CH3_V 0x1 +#define RMT_RX_FILTER_EN_CH3_S 7 +/* RMT_TX_CONTI_MODE_CH3 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to continue sending from the first data to the + last data in channel3.*/ +#define RMT_TX_CONTI_MODE_CH3 (BIT(6)) +#define RMT_TX_CONTI_MODE_CH3_M (BIT(6)) +#define RMT_TX_CONTI_MODE_CH3_V 0x1 +#define RMT_TX_CONTI_MODE_CH3_S 6 +/* RMT_MEM_OWNER_CH3 : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: This is the mark of channel3's ram usage right.1'b1：receiver + uses the ram 0：transmitter uses the ram*/ +#define RMT_MEM_OWNER_CH3 (BIT(5)) +#define RMT_MEM_OWNER_CH3_M (BIT(5)) +#define RMT_MEM_OWNER_CH3_V 0x1 +#define RMT_MEM_OWNER_CH3_S 5 +/* RMT_APB_MEM_RST_CH3 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to reset W/R ram address for channel3 by apb fifo access*/ +#define RMT_APB_MEM_RST_CH3 (BIT(4)) +#define RMT_APB_MEM_RST_CH3_M (BIT(4)) +#define RMT_APB_MEM_RST_CH3_V 0x1 +#define RMT_APB_MEM_RST_CH3_S 4 +/* RMT_MEM_RD_RST_CH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to reset read ram address for channel3 by transmitter access.*/ +#define RMT_MEM_RD_RST_CH3 (BIT(3)) +#define RMT_MEM_RD_RST_CH3_M (BIT(3)) +#define RMT_MEM_RD_RST_CH3_V 0x1 +#define RMT_MEM_RD_RST_CH3_S 3 +/* RMT_MEM_WR_RST_CH3 : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Set this bit to reset write ram address for channel3 by receiver access.*/ +#define RMT_MEM_WR_RST_CH3 (BIT(2)) +#define RMT_MEM_WR_RST_CH3_M (BIT(2)) +#define RMT_MEM_WR_RST_CH3_V 0x1 +#define RMT_MEM_WR_RST_CH3_S 2 +/* RMT_RX_EN_CH3 : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: Set this bit to enbale receving data for channel3.*/ +#define RMT_RX_EN_CH3 (BIT(1)) +#define RMT_RX_EN_CH3_M (BIT(1)) +#define RMT_RX_EN_CH3_V 0x1 +#define RMT_RX_EN_CH3_S 1 +/* RMT_TX_START_CH3 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to start sending data for channel3.*/ +#define RMT_TX_START_CH3 (BIT(0)) +#define RMT_TX_START_CH3_M (BIT(0)) +#define RMT_TX_START_CH3_V 0x1 +#define RMT_TX_START_CH3_S 0 + +#define RMT_CH4CONF0_REG (DR_REG_RMT_BASE + 0x0040) +/* RMT_CARRIER_OUT_LV_CH4 : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: This bit is used to configure carrier wave's position for channel4.1'b1:add + on low level 1'b0:add on high level.*/ +#define RMT_CARRIER_OUT_LV_CH4 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH4_M (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH4_V 0x1 +#define RMT_CARRIER_OUT_LV_CH4_S 29 +/* RMT_CARRIER_EN_CH4 : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: This is the carrier modulation enable control bit for channel4.*/ +#define RMT_CARRIER_EN_CH4 (BIT(28)) +#define RMT_CARRIER_EN_CH4_M (BIT(28)) +#define RMT_CARRIER_EN_CH4_V 0x1 +#define RMT_CARRIER_EN_CH4_S 28 +/* RMT_MEM_SIZE_CH4 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ +/*description: This register is used to configure the the amount of memory blocks + allocated to channel4.*/ +#define RMT_MEM_SIZE_CH4 0x0000000F +#define RMT_MEM_SIZE_CH4_M ((RMT_MEM_SIZE_CH4_V)<<(RMT_MEM_SIZE_CH4_S)) +#define RMT_MEM_SIZE_CH4_V 0xF +#define RMT_MEM_SIZE_CH4_S 24 +/* RMT_IDLE_THRES_CH4 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ +/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch4 + then the receive process is done.*/ +#define RMT_IDLE_THRES_CH4 0x0000FFFF +#define RMT_IDLE_THRES_CH4_M ((RMT_IDLE_THRES_CH4_V)<<(RMT_IDLE_THRES_CH4_S)) +#define RMT_IDLE_THRES_CH4_V 0xFFFF +#define RMT_IDLE_THRES_CH4_S 8 +/* RMT_DIV_CNT_CH4 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ +/*description: This register is used to configure the frequency divider's factor in channel4.*/ +#define RMT_DIV_CNT_CH4 0x000000FF +#define RMT_DIV_CNT_CH4_M ((RMT_DIV_CNT_CH4_V)<<(RMT_DIV_CNT_CH4_S)) +#define RMT_DIV_CNT_CH4_V 0xFF +#define RMT_DIV_CNT_CH4_S 0 + +#define RMT_CH4CONF1_REG (DR_REG_RMT_BASE + 0x0044) +/* RMT_IDLE_OUT_EN_CH4 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for channel4 in IDLE state.*/ +#define RMT_IDLE_OUT_EN_CH4 (BIT(19)) +#define RMT_IDLE_OUT_EN_CH4_M (BIT(19)) +#define RMT_IDLE_OUT_EN_CH4_V 0x1 +#define RMT_IDLE_OUT_EN_CH4_S 19 +/* RMT_IDLE_OUT_LV_CH4 : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This bit configures the output signal's level for channel4 in IDLE state.*/ +#define RMT_IDLE_OUT_LV_CH4 (BIT(18)) +#define RMT_IDLE_OUT_LV_CH4_M (BIT(18)) +#define RMT_IDLE_OUT_LV_CH4_V 0x1 +#define RMT_IDLE_OUT_LV_CH4_S 18 +/* RMT_REF_ALWAYS_ON_CH4 : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ +#define RMT_REF_ALWAYS_ON_CH4 (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH4_M (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH4_V 0x1 +#define RMT_REF_ALWAYS_ON_CH4_S 17 +/* RMT_REF_CNT_RST_CH4 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This bit is used to reset divider in channel4.*/ +#define RMT_REF_CNT_RST_CH4 (BIT(16)) +#define RMT_REF_CNT_RST_CH4_M (BIT(16)) +#define RMT_REF_CNT_RST_CH4_V 0x1 +#define RMT_REF_CNT_RST_CH4_S 16 +/* RMT_RX_FILTER_THRES_CH4 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ +/*description: in receive mode channel4 ignore input pulse when the pulse width + is smaller then this value.*/ +#define RMT_RX_FILTER_THRES_CH4 0x000000FF +#define RMT_RX_FILTER_THRES_CH4_M ((RMT_RX_FILTER_THRES_CH4_V)<<(RMT_RX_FILTER_THRES_CH4_S)) +#define RMT_RX_FILTER_THRES_CH4_V 0xFF +#define RMT_RX_FILTER_THRES_CH4_S 8 +/* RMT_RX_FILTER_EN_CH4 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the receive filter enable bit for channel4.*/ +#define RMT_RX_FILTER_EN_CH4 (BIT(7)) +#define RMT_RX_FILTER_EN_CH4_M (BIT(7)) +#define RMT_RX_FILTER_EN_CH4_V 0x1 +#define RMT_RX_FILTER_EN_CH4_S 7 +/* RMT_TX_CONTI_MODE_CH4 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to continue sending from the first data to the + last data in channel4.*/ +#define RMT_TX_CONTI_MODE_CH4 (BIT(6)) +#define RMT_TX_CONTI_MODE_CH4_M (BIT(6)) +#define RMT_TX_CONTI_MODE_CH4_V 0x1 +#define RMT_TX_CONTI_MODE_CH4_S 6 +/* RMT_MEM_OWNER_CH4 : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: This is the mark of channel4's ram usage right.1'b1：receiver + uses the ram 0：transmitter uses the ram*/ +#define RMT_MEM_OWNER_CH4 (BIT(5)) +#define RMT_MEM_OWNER_CH4_M (BIT(5)) +#define RMT_MEM_OWNER_CH4_V 0x1 +#define RMT_MEM_OWNER_CH4_S 5 +/* RMT_APB_MEM_RST_CH4 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to reset W/R ram address for channel4 by apb fifo access*/ +#define RMT_APB_MEM_RST_CH4 (BIT(4)) +#define RMT_APB_MEM_RST_CH4_M (BIT(4)) +#define RMT_APB_MEM_RST_CH4_V 0x1 +#define RMT_APB_MEM_RST_CH4_S 4 +/* RMT_MEM_RD_RST_CH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to reset read ram address for channel4 by transmitter access.*/ +#define RMT_MEM_RD_RST_CH4 (BIT(3)) +#define RMT_MEM_RD_RST_CH4_M (BIT(3)) +#define RMT_MEM_RD_RST_CH4_V 0x1 +#define RMT_MEM_RD_RST_CH4_S 3 +/* RMT_MEM_WR_RST_CH4 : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Set this bit to reset write ram address for channel4 by receiver access.*/ +#define RMT_MEM_WR_RST_CH4 (BIT(2)) +#define RMT_MEM_WR_RST_CH4_M (BIT(2)) +#define RMT_MEM_WR_RST_CH4_V 0x1 +#define RMT_MEM_WR_RST_CH4_S 2 +/* RMT_RX_EN_CH4 : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: Set this bit to enbale receving data for channel4.*/ +#define RMT_RX_EN_CH4 (BIT(1)) +#define RMT_RX_EN_CH4_M (BIT(1)) +#define RMT_RX_EN_CH4_V 0x1 +#define RMT_RX_EN_CH4_S 1 +/* RMT_TX_START_CH4 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to start sending data for channel4.*/ +#define RMT_TX_START_CH4 (BIT(0)) +#define RMT_TX_START_CH4_M (BIT(0)) +#define RMT_TX_START_CH4_V 0x1 +#define RMT_TX_START_CH4_S 0 + +#define RMT_CH5CONF0_REG (DR_REG_RMT_BASE + 0x0048) +/* RMT_CARRIER_OUT_LV_CH5 : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: This bit is used to configure carrier wave's position for channel5.1'b1:add + on low level 1'b0:add on high level.*/ +#define RMT_CARRIER_OUT_LV_CH5 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH5_M (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH5_V 0x1 +#define RMT_CARRIER_OUT_LV_CH5_S 29 +/* RMT_CARRIER_EN_CH5 : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: This is the carrier modulation enable control bit for channel5.*/ +#define RMT_CARRIER_EN_CH5 (BIT(28)) +#define RMT_CARRIER_EN_CH5_M (BIT(28)) +#define RMT_CARRIER_EN_CH5_V 0x1 +#define RMT_CARRIER_EN_CH5_S 28 +/* RMT_MEM_SIZE_CH5 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ +/*description: This register is used to configure the the amount of memory blocks + allocated to channel5.*/ +#define RMT_MEM_SIZE_CH5 0x0000000F +#define RMT_MEM_SIZE_CH5_M ((RMT_MEM_SIZE_CH5_V)<<(RMT_MEM_SIZE_CH5_S)) +#define RMT_MEM_SIZE_CH5_V 0xF +#define RMT_MEM_SIZE_CH5_S 24 +/* RMT_IDLE_THRES_CH5 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ +/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch5 + then the receive process is done.*/ +#define RMT_IDLE_THRES_CH5 0x0000FFFF +#define RMT_IDLE_THRES_CH5_M ((RMT_IDLE_THRES_CH5_V)<<(RMT_IDLE_THRES_CH5_S)) +#define RMT_IDLE_THRES_CH5_V 0xFFFF +#define RMT_IDLE_THRES_CH5_S 8 +/* RMT_DIV_CNT_CH5 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ +/*description: This register is used to configure the frequency divider's factor in channel5.*/ +#define RMT_DIV_CNT_CH5 0x000000FF +#define RMT_DIV_CNT_CH5_M ((RMT_DIV_CNT_CH5_V)<<(RMT_DIV_CNT_CH5_S)) +#define RMT_DIV_CNT_CH5_V 0xFF +#define RMT_DIV_CNT_CH5_S 0 + +#define RMT_CH5CONF1_REG (DR_REG_RMT_BASE + 0x004c) +/* RMT_IDLE_OUT_EN_CH5 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for channel5 in IDLE state.*/ +#define RMT_IDLE_OUT_EN_CH5 (BIT(19)) +#define RMT_IDLE_OUT_EN_CH5_M (BIT(19)) +#define RMT_IDLE_OUT_EN_CH5_V 0x1 +#define RMT_IDLE_OUT_EN_CH5_S 19 +/* RMT_IDLE_OUT_LV_CH5 : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This bit configures the output signal's level for channel5 in IDLE state.*/ +#define RMT_IDLE_OUT_LV_CH5 (BIT(18)) +#define RMT_IDLE_OUT_LV_CH5_M (BIT(18)) +#define RMT_IDLE_OUT_LV_CH5_V 0x1 +#define RMT_IDLE_OUT_LV_CH5_S 18 +/* RMT_REF_ALWAYS_ON_CH5 : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ +#define RMT_REF_ALWAYS_ON_CH5 (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH5_M (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH5_V 0x1 +#define RMT_REF_ALWAYS_ON_CH5_S 17 +/* RMT_REF_CNT_RST_CH5 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This bit is used to reset divider in channel5.*/ +#define RMT_REF_CNT_RST_CH5 (BIT(16)) +#define RMT_REF_CNT_RST_CH5_M (BIT(16)) +#define RMT_REF_CNT_RST_CH5_V 0x1 +#define RMT_REF_CNT_RST_CH5_S 16 +/* RMT_RX_FILTER_THRES_CH5 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ +/*description: in receive mode channel5 ignore input pulse when the pulse width + is smaller then this value.*/ +#define RMT_RX_FILTER_THRES_CH5 0x000000FF +#define RMT_RX_FILTER_THRES_CH5_M ((RMT_RX_FILTER_THRES_CH5_V)<<(RMT_RX_FILTER_THRES_CH5_S)) +#define RMT_RX_FILTER_THRES_CH5_V 0xFF +#define RMT_RX_FILTER_THRES_CH5_S 8 +/* RMT_RX_FILTER_EN_CH5 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the receive filter enable bit for channel5.*/ +#define RMT_RX_FILTER_EN_CH5 (BIT(7)) +#define RMT_RX_FILTER_EN_CH5_M (BIT(7)) +#define RMT_RX_FILTER_EN_CH5_V 0x1 +#define RMT_RX_FILTER_EN_CH5_S 7 +/* RMT_TX_CONTI_MODE_CH5 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to continue sending from the first data to the + last data in channel5.*/ +#define RMT_TX_CONTI_MODE_CH5 (BIT(6)) +#define RMT_TX_CONTI_MODE_CH5_M (BIT(6)) +#define RMT_TX_CONTI_MODE_CH5_V 0x1 +#define RMT_TX_CONTI_MODE_CH5_S 6 +/* RMT_MEM_OWNER_CH5 : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: This is the mark of channel5's ram usage right.1'b1：receiver + uses the ram 0：transmitter uses the ram*/ +#define RMT_MEM_OWNER_CH5 (BIT(5)) +#define RMT_MEM_OWNER_CH5_M (BIT(5)) +#define RMT_MEM_OWNER_CH5_V 0x1 +#define RMT_MEM_OWNER_CH5_S 5 +/* RMT_APB_MEM_RST_CH5 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to reset W/R ram address for channel5 by apb fifo access*/ +#define RMT_APB_MEM_RST_CH5 (BIT(4)) +#define RMT_APB_MEM_RST_CH5_M (BIT(4)) +#define RMT_APB_MEM_RST_CH5_V 0x1 +#define RMT_APB_MEM_RST_CH5_S 4 +/* RMT_MEM_RD_RST_CH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to reset read ram address for channel5 by transmitter access.*/ +#define RMT_MEM_RD_RST_CH5 (BIT(3)) +#define RMT_MEM_RD_RST_CH5_M (BIT(3)) +#define RMT_MEM_RD_RST_CH5_V 0x1 +#define RMT_MEM_RD_RST_CH5_S 3 +/* RMT_MEM_WR_RST_CH5 : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Set this bit to reset write ram address for channel5 by receiver access.*/ +#define RMT_MEM_WR_RST_CH5 (BIT(2)) +#define RMT_MEM_WR_RST_CH5_M (BIT(2)) +#define RMT_MEM_WR_RST_CH5_V 0x1 +#define RMT_MEM_WR_RST_CH5_S 2 +/* RMT_RX_EN_CH5 : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: Set this bit to enbale receving data for channel5.*/ +#define RMT_RX_EN_CH5 (BIT(1)) +#define RMT_RX_EN_CH5_M (BIT(1)) +#define RMT_RX_EN_CH5_V 0x1 +#define RMT_RX_EN_CH5_S 1 +/* RMT_TX_START_CH5 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to start sending data for channel5.*/ +#define RMT_TX_START_CH5 (BIT(0)) +#define RMT_TX_START_CH5_M (BIT(0)) +#define RMT_TX_START_CH5_V 0x1 +#define RMT_TX_START_CH5_S 0 + +#define RMT_CH6CONF0_REG (DR_REG_RMT_BASE + 0x0050) +/* RMT_CARRIER_OUT_LV_CH6 : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: This bit is used to configure carrier wave's position for channel6.1'b1:add + on low level 1'b0:add on high level.*/ +#define RMT_CARRIER_OUT_LV_CH6 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH6_M (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH6_V 0x1 +#define RMT_CARRIER_OUT_LV_CH6_S 29 +/* RMT_CARRIER_EN_CH6 : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: This is the carrier modulation enable control bit for channel6.*/ +#define RMT_CARRIER_EN_CH6 (BIT(28)) +#define RMT_CARRIER_EN_CH6_M (BIT(28)) +#define RMT_CARRIER_EN_CH6_V 0x1 +#define RMT_CARRIER_EN_CH6_S 28 +/* RMT_MEM_SIZE_CH6 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ +/*description: This register is used to configure the the amount of memory blocks + allocated to channel6.*/ +#define RMT_MEM_SIZE_CH6 0x0000000F +#define RMT_MEM_SIZE_CH6_M ((RMT_MEM_SIZE_CH6_V)<<(RMT_MEM_SIZE_CH6_S)) +#define RMT_MEM_SIZE_CH6_V 0xF +#define RMT_MEM_SIZE_CH6_S 24 +/* RMT_IDLE_THRES_CH6 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ +/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch6 + then the receive process is done.*/ +#define RMT_IDLE_THRES_CH6 0x0000FFFF +#define RMT_IDLE_THRES_CH6_M ((RMT_IDLE_THRES_CH6_V)<<(RMT_IDLE_THRES_CH6_S)) +#define RMT_IDLE_THRES_CH6_V 0xFFFF +#define RMT_IDLE_THRES_CH6_S 8 +/* RMT_DIV_CNT_CH6 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ +/*description: This register is used to configure the frequency divider's factor in channel6.*/ +#define RMT_DIV_CNT_CH6 0x000000FF +#define RMT_DIV_CNT_CH6_M ((RMT_DIV_CNT_CH6_V)<<(RMT_DIV_CNT_CH6_S)) +#define RMT_DIV_CNT_CH6_V 0xFF +#define RMT_DIV_CNT_CH6_S 0 + +#define RMT_CH6CONF1_REG (DR_REG_RMT_BASE + 0x0054) +/* RMT_IDLE_OUT_EN_CH6 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for channel6 in IDLE state.*/ +#define RMT_IDLE_OUT_EN_CH6 (BIT(19)) +#define RMT_IDLE_OUT_EN_CH6_M (BIT(19)) +#define RMT_IDLE_OUT_EN_CH6_V 0x1 +#define RMT_IDLE_OUT_EN_CH6_S 19 +/* RMT_IDLE_OUT_LV_CH6 : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This bit configures the output signal's level for channel6 in IDLE state.*/ +#define RMT_IDLE_OUT_LV_CH6 (BIT(18)) +#define RMT_IDLE_OUT_LV_CH6_M (BIT(18)) +#define RMT_IDLE_OUT_LV_CH6_V 0x1 +#define RMT_IDLE_OUT_LV_CH6_S 18 +/* RMT_REF_ALWAYS_ON_CH6 : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ +#define RMT_REF_ALWAYS_ON_CH6 (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH6_M (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH6_V 0x1 +#define RMT_REF_ALWAYS_ON_CH6_S 17 +/* RMT_REF_CNT_RST_CH6 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This bit is used to reset divider in channel6.*/ +#define RMT_REF_CNT_RST_CH6 (BIT(16)) +#define RMT_REF_CNT_RST_CH6_M (BIT(16)) +#define RMT_REF_CNT_RST_CH6_V 0x1 +#define RMT_REF_CNT_RST_CH6_S 16 +/* RMT_RX_FILTER_THRES_CH6 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ +/*description: in receive mode channel6 ignore input pulse when the pulse width + is smaller then this value.*/ +#define RMT_RX_FILTER_THRES_CH6 0x000000FF +#define RMT_RX_FILTER_THRES_CH6_M ((RMT_RX_FILTER_THRES_CH6_V)<<(RMT_RX_FILTER_THRES_CH6_S)) +#define RMT_RX_FILTER_THRES_CH6_V 0xFF +#define RMT_RX_FILTER_THRES_CH6_S 8 +/* RMT_RX_FILTER_EN_CH6 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the receive filter enable bit for channel6.*/ +#define RMT_RX_FILTER_EN_CH6 (BIT(7)) +#define RMT_RX_FILTER_EN_CH6_M (BIT(7)) +#define RMT_RX_FILTER_EN_CH6_V 0x1 +#define RMT_RX_FILTER_EN_CH6_S 7 +/* RMT_TX_CONTI_MODE_CH6 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to continue sending from the first data to the + last data in channel6.*/ +#define RMT_TX_CONTI_MODE_CH6 (BIT(6)) +#define RMT_TX_CONTI_MODE_CH6_M (BIT(6)) +#define RMT_TX_CONTI_MODE_CH6_V 0x1 +#define RMT_TX_CONTI_MODE_CH6_S 6 +/* RMT_MEM_OWNER_CH6 : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: This is the mark of channel6's ram usage right.1'b1：receiver + uses the ram 0：transmitter uses the ram*/ +#define RMT_MEM_OWNER_CH6 (BIT(5)) +#define RMT_MEM_OWNER_CH6_M (BIT(5)) +#define RMT_MEM_OWNER_CH6_V 0x1 +#define RMT_MEM_OWNER_CH6_S 5 +/* RMT_APB_MEM_RST_CH6 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to reset W/R ram address for channel6 by apb fifo access*/ +#define RMT_APB_MEM_RST_CH6 (BIT(4)) +#define RMT_APB_MEM_RST_CH6_M (BIT(4)) +#define RMT_APB_MEM_RST_CH6_V 0x1 +#define RMT_APB_MEM_RST_CH6_S 4 +/* RMT_MEM_RD_RST_CH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to reset read ram address for channel6 by transmitter access.*/ +#define RMT_MEM_RD_RST_CH6 (BIT(3)) +#define RMT_MEM_RD_RST_CH6_M (BIT(3)) +#define RMT_MEM_RD_RST_CH6_V 0x1 +#define RMT_MEM_RD_RST_CH6_S 3 +/* RMT_MEM_WR_RST_CH6 : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Set this bit to reset write ram address for channel6 by receiver access.*/ +#define RMT_MEM_WR_RST_CH6 (BIT(2)) +#define RMT_MEM_WR_RST_CH6_M (BIT(2)) +#define RMT_MEM_WR_RST_CH6_V 0x1 +#define RMT_MEM_WR_RST_CH6_S 2 +/* RMT_RX_EN_CH6 : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: Set this bit to enbale receving data for channel6.*/ +#define RMT_RX_EN_CH6 (BIT(1)) +#define RMT_RX_EN_CH6_M (BIT(1)) +#define RMT_RX_EN_CH6_V 0x1 +#define RMT_RX_EN_CH6_S 1 +/* RMT_TX_START_CH6 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to start sending data for channel6.*/ +#define RMT_TX_START_CH6 (BIT(0)) +#define RMT_TX_START_CH6_M (BIT(0)) +#define RMT_TX_START_CH6_V 0x1 +#define RMT_TX_START_CH6_S 0 + +#define RMT_CH7CONF0_REG (DR_REG_RMT_BASE + 0x0058) +/* RMT_CARRIER_OUT_LV_CH7 : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: This bit is used to configure carrier wave's position for channel7.1'b1:add + on low level 1'b0:add on high level.*/ +#define RMT_CARRIER_OUT_LV_CH7 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH7_M (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH7_V 0x1 +#define RMT_CARRIER_OUT_LV_CH7_S 29 +/* RMT_CARRIER_EN_CH7 : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: This is the carrier modulation enable control bit for channel7.*/ +#define RMT_CARRIER_EN_CH7 (BIT(28)) +#define RMT_CARRIER_EN_CH7_M (BIT(28)) +#define RMT_CARRIER_EN_CH7_V 0x1 +#define RMT_CARRIER_EN_CH7_S 28 +/* RMT_MEM_SIZE_CH7 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ +/*description: This register is used to configure the the amount of memory blocks + allocated to channel7.*/ +#define RMT_MEM_SIZE_CH7 0x0000000F +#define RMT_MEM_SIZE_CH7_M ((RMT_MEM_SIZE_CH7_V)<<(RMT_MEM_SIZE_CH7_S)) +#define RMT_MEM_SIZE_CH7_V 0xF +#define RMT_MEM_SIZE_CH7_S 24 +/* RMT_IDLE_THRES_CH7 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ +/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch7 + then the receive process is done.*/ +#define RMT_IDLE_THRES_CH7 0x0000FFFF +#define RMT_IDLE_THRES_CH7_M ((RMT_IDLE_THRES_CH7_V)<<(RMT_IDLE_THRES_CH7_S)) +#define RMT_IDLE_THRES_CH7_V 0xFFFF +#define RMT_IDLE_THRES_CH7_S 8 +/* RMT_DIV_CNT_CH7 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ +/*description: This register is used to configure the frequency divider's factor in channel7.*/ +#define RMT_DIV_CNT_CH7 0x000000FF +#define RMT_DIV_CNT_CH7_M ((RMT_DIV_CNT_CH7_V)<<(RMT_DIV_CNT_CH7_S)) +#define RMT_DIV_CNT_CH7_V 0xFF +#define RMT_DIV_CNT_CH7_S 0 + +#define RMT_CH7CONF1_REG (DR_REG_RMT_BASE + 0x005c) +/* RMT_IDLE_OUT_EN_CH7 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for channel6 in IDLE state.*/ +#define RMT_IDLE_OUT_EN_CH7 (BIT(19)) +#define RMT_IDLE_OUT_EN_CH7_M (BIT(19)) +#define RMT_IDLE_OUT_EN_CH7_V 0x1 +#define RMT_IDLE_OUT_EN_CH7_S 19 +/* RMT_IDLE_OUT_LV_CH7 : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This bit configures the output signal's level for channel7 in IDLE state.*/ +#define RMT_IDLE_OUT_LV_CH7 (BIT(18)) +#define RMT_IDLE_OUT_LV_CH7_M (BIT(18)) +#define RMT_IDLE_OUT_LV_CH7_V 0x1 +#define RMT_IDLE_OUT_LV_CH7_S 18 +/* RMT_REF_ALWAYS_ON_CH7 : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ +#define RMT_REF_ALWAYS_ON_CH7 (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH7_M (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH7_V 0x1 +#define RMT_REF_ALWAYS_ON_CH7_S 17 +/* RMT_REF_CNT_RST_CH7 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This bit is used to reset divider in channel7.*/ +#define RMT_REF_CNT_RST_CH7 (BIT(16)) +#define RMT_REF_CNT_RST_CH7_M (BIT(16)) +#define RMT_REF_CNT_RST_CH7_V 0x1 +#define RMT_REF_CNT_RST_CH7_S 16 +/* RMT_RX_FILTER_THRES_CH7 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ +/*description: in receive mode channel7 ignore input pulse when the pulse width + is smaller then this value.*/ +#define RMT_RX_FILTER_THRES_CH7 0x000000FF +#define RMT_RX_FILTER_THRES_CH7_M ((RMT_RX_FILTER_THRES_CH7_V)<<(RMT_RX_FILTER_THRES_CH7_S)) +#define RMT_RX_FILTER_THRES_CH7_V 0xFF +#define RMT_RX_FILTER_THRES_CH7_S 8 +/* RMT_RX_FILTER_EN_CH7 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the receive filter enable bit for channel7.*/ +#define RMT_RX_FILTER_EN_CH7 (BIT(7)) +#define RMT_RX_FILTER_EN_CH7_M (BIT(7)) +#define RMT_RX_FILTER_EN_CH7_V 0x1 +#define RMT_RX_FILTER_EN_CH7_S 7 +/* RMT_TX_CONTI_MODE_CH7 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to continue sending from the first data to the + last data in channel7.*/ +#define RMT_TX_CONTI_MODE_CH7 (BIT(6)) +#define RMT_TX_CONTI_MODE_CH7_M (BIT(6)) +#define RMT_TX_CONTI_MODE_CH7_V 0x1 +#define RMT_TX_CONTI_MODE_CH7_S 6 +/* RMT_MEM_OWNER_CH7 : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: This is the mark of channel7's ram usage right.1'b1：receiver + uses the ram 0：transmitter uses the ram*/ +#define RMT_MEM_OWNER_CH7 (BIT(5)) +#define RMT_MEM_OWNER_CH7_M (BIT(5)) +#define RMT_MEM_OWNER_CH7_V 0x1 +#define RMT_MEM_OWNER_CH7_S 5 +/* RMT_APB_MEM_RST_CH7 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to reset W/R ram address for channel7 by apb fifo access*/ +#define RMT_APB_MEM_RST_CH7 (BIT(4)) +#define RMT_APB_MEM_RST_CH7_M (BIT(4)) +#define RMT_APB_MEM_RST_CH7_V 0x1 +#define RMT_APB_MEM_RST_CH7_S 4 +/* RMT_MEM_RD_RST_CH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to reset read ram address for channel7 by transmitter access.*/ +#define RMT_MEM_RD_RST_CH7 (BIT(3)) +#define RMT_MEM_RD_RST_CH7_M (BIT(3)) +#define RMT_MEM_RD_RST_CH7_V 0x1 +#define RMT_MEM_RD_RST_CH7_S 3 +/* RMT_MEM_WR_RST_CH7 : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Set this bit to reset write ram address for channel7 by receiver access.*/ +#define RMT_MEM_WR_RST_CH7 (BIT(2)) +#define RMT_MEM_WR_RST_CH7_M (BIT(2)) +#define RMT_MEM_WR_RST_CH7_V 0x1 +#define RMT_MEM_WR_RST_CH7_S 2 +/* RMT_RX_EN_CH7 : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: Set this bit to enbale receving data for channel7.*/ +#define RMT_RX_EN_CH7 (BIT(1)) +#define RMT_RX_EN_CH7_M (BIT(1)) +#define RMT_RX_EN_CH7_V 0x1 +#define RMT_RX_EN_CH7_S 1 +/* RMT_TX_START_CH7 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to start sending data for channel7.*/ +#define RMT_TX_START_CH7 (BIT(0)) +#define RMT_TX_START_CH7_M (BIT(0)) +#define RMT_TX_START_CH7_V 0x1 +#define RMT_TX_START_CH7_S 0 + +#define RMT_CH0STATUS_REG (DR_REG_RMT_BASE + 0x0060) +/* RMT_STATUS_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The status for channel0*/ +#define RMT_STATUS_CH0 0xFFFFFFFF +#define RMT_STATUS_CH0_M ((RMT_STATUS_CH0_V)<<(RMT_STATUS_CH0_S)) +#define RMT_STATUS_CH0_V 0xFFFFFFFF +#define RMT_STATUS_CH0_S 0 + +#define RMT_CH1STATUS_REG (DR_REG_RMT_BASE + 0x0064) +/* RMT_STATUS_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The status for channel1*/ +#define RMT_STATUS_CH1 0xFFFFFFFF +#define RMT_STATUS_CH1_M ((RMT_STATUS_CH1_V)<<(RMT_STATUS_CH1_S)) +#define RMT_STATUS_CH1_V 0xFFFFFFFF +#define RMT_STATUS_CH1_S 0 + +#define RMT_CH2STATUS_REG (DR_REG_RMT_BASE + 0x0068) +/* RMT_STATUS_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The status for channel2*/ +#define RMT_STATUS_CH2 0xFFFFFFFF +#define RMT_STATUS_CH2_M ((RMT_STATUS_CH2_V)<<(RMT_STATUS_CH2_S)) +#define RMT_STATUS_CH2_V 0xFFFFFFFF +#define RMT_STATUS_CH2_S 0 + +#define RMT_CH3STATUS_REG (DR_REG_RMT_BASE + 0x006c) +/* RMT_STATUS_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The status for channel3*/ +#define RMT_STATUS_CH3 0xFFFFFFFF +#define RMT_STATUS_CH3_M ((RMT_STATUS_CH3_V)<<(RMT_STATUS_CH3_S)) +#define RMT_STATUS_CH3_V 0xFFFFFFFF +#define RMT_STATUS_CH3_S 0 + +#define RMT_CH4STATUS_REG (DR_REG_RMT_BASE + 0x0070) +/* RMT_STATUS_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The status for channel4*/ +#define RMT_STATUS_CH4 0xFFFFFFFF +#define RMT_STATUS_CH4_M ((RMT_STATUS_CH4_V)<<(RMT_STATUS_CH4_S)) +#define RMT_STATUS_CH4_V 0xFFFFFFFF +#define RMT_STATUS_CH4_S 0 + +#define RMT_CH5STATUS_REG (DR_REG_RMT_BASE + 0x0074) +/* RMT_STATUS_CH5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The status for channel5*/ +#define RMT_STATUS_CH5 0xFFFFFFFF +#define RMT_STATUS_CH5_M ((RMT_STATUS_CH5_V)<<(RMT_STATUS_CH5_S)) +#define RMT_STATUS_CH5_V 0xFFFFFFFF +#define RMT_STATUS_CH5_S 0 + +#define RMT_CH6STATUS_REG (DR_REG_RMT_BASE + 0x0078) +/* RMT_STATUS_CH6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The status for channel6*/ +#define RMT_STATUS_CH6 0xFFFFFFFF +#define RMT_STATUS_CH6_M ((RMT_STATUS_CH6_V)<<(RMT_STATUS_CH6_S)) +#define RMT_STATUS_CH6_V 0xFFFFFFFF +#define RMT_STATUS_CH6_S 0 + +#define RMT_CH7STATUS_REG (DR_REG_RMT_BASE + 0x007c) +/* RMT_STATUS_CH7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The status for channel7*/ +#define RMT_STATUS_CH7 0xFFFFFFFF +#define RMT_STATUS_CH7_M ((RMT_STATUS_CH7_V)<<(RMT_STATUS_CH7_S)) +#define RMT_STATUS_CH7_V 0xFFFFFFFF +#define RMT_STATUS_CH7_S 0 + +#define RMT_CH0ADDR_REG (DR_REG_RMT_BASE + 0x0080) +/* RMT_APB_MEM_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The ram relative address in channel0 by apb fifo access*/ +#define RMT_APB_MEM_ADDR_CH0 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH0_M ((RMT_APB_MEM_ADDR_CH0_V)<<(RMT_APB_MEM_ADDR_CH0_S)) +#define RMT_APB_MEM_ADDR_CH0_V 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH0_S 0 + +#define RMT_CH1ADDR_REG (DR_REG_RMT_BASE + 0x0084) +/* RMT_APB_MEM_ADDR_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The ram relative address in channel1 by apb fifo access*/ +#define RMT_APB_MEM_ADDR_CH1 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH1_M ((RMT_APB_MEM_ADDR_CH1_V)<<(RMT_APB_MEM_ADDR_CH1_S)) +#define RMT_APB_MEM_ADDR_CH1_V 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH1_S 0 + +#define RMT_CH2ADDR_REG (DR_REG_RMT_BASE + 0x0088) +/* RMT_APB_MEM_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The ram relative address in channel2 by apb fifo access*/ +#define RMT_APB_MEM_ADDR_CH2 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH2_M ((RMT_APB_MEM_ADDR_CH2_V)<<(RMT_APB_MEM_ADDR_CH2_S)) +#define RMT_APB_MEM_ADDR_CH2_V 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH2_S 0 + +#define RMT_CH3ADDR_REG (DR_REG_RMT_BASE + 0x008c) +/* RMT_APB_MEM_ADDR_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The ram relative address in channel3 by apb fifo access*/ +#define RMT_APB_MEM_ADDR_CH3 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH3_M ((RMT_APB_MEM_ADDR_CH3_V)<<(RMT_APB_MEM_ADDR_CH3_S)) +#define RMT_APB_MEM_ADDR_CH3_V 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH3_S 0 + +#define RMT_CH4ADDR_REG (DR_REG_RMT_BASE + 0x0090) +/* RMT_APB_MEM_ADDR_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The ram relative address in channel4 by apb fifo access*/ +#define RMT_APB_MEM_ADDR_CH4 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH4_M ((RMT_APB_MEM_ADDR_CH4_V)<<(RMT_APB_MEM_ADDR_CH4_S)) +#define RMT_APB_MEM_ADDR_CH4_V 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH4_S 0 + +#define RMT_CH5ADDR_REG (DR_REG_RMT_BASE + 0x0094) +/* RMT_APB_MEM_ADDR_CH5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The ram relative address in channel5 by apb fifo access*/ +#define RMT_APB_MEM_ADDR_CH5 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH5_M ((RMT_APB_MEM_ADDR_CH5_V)<<(RMT_APB_MEM_ADDR_CH5_S)) +#define RMT_APB_MEM_ADDR_CH5_V 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH5_S 0 + +#define RMT_CH6ADDR_REG (DR_REG_RMT_BASE + 0x0098) +/* RMT_APB_MEM_ADDR_CH6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The ram relative address in channel6 by apb fifo access*/ +#define RMT_APB_MEM_ADDR_CH6 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH6_M ((RMT_APB_MEM_ADDR_CH6_V)<<(RMT_APB_MEM_ADDR_CH6_S)) +#define RMT_APB_MEM_ADDR_CH6_V 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH6_S 0 + +#define RMT_CH7ADDR_REG (DR_REG_RMT_BASE + 0x009c) +/* RMT_APB_MEM_ADDR_CH7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The ram relative address in channel7 by apb fifo access*/ +#define RMT_APB_MEM_ADDR_CH7 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH7_M ((RMT_APB_MEM_ADDR_CH7_V)<<(RMT_APB_MEM_ADDR_CH7_S)) +#define RMT_APB_MEM_ADDR_CH7_V 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH7_S 0 + +#define RMT_INT_RAW_REG (DR_REG_RMT_BASE + 0x00a0) +/* RMT_CH7_TX_THR_EVENT_INT_RAW : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 7 turns to high level when + transmitter in channle7 have send datas more than reg_rmt_tx_lim_ch7 after detecting this interrupt software can updata the old datas with new datas.*/ +#define RMT_CH7_TX_THR_EVENT_INT_RAW (BIT(31)) +#define RMT_CH7_TX_THR_EVENT_INT_RAW_M (BIT(31)) +#define RMT_CH7_TX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH7_TX_THR_EVENT_INT_RAW_S 31 +/* RMT_CH6_TX_THR_EVENT_INT_RAW : RO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 6 turns to high level when + transmitter in channle6 have send datas more than reg_rmt_tx_lim_ch6 after detecting this interrupt software can updata the old datas with new datas.*/ +#define RMT_CH6_TX_THR_EVENT_INT_RAW (BIT(30)) +#define RMT_CH6_TX_THR_EVENT_INT_RAW_M (BIT(30)) +#define RMT_CH6_TX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH6_TX_THR_EVENT_INT_RAW_S 30 +/* RMT_CH5_TX_THR_EVENT_INT_RAW : RO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 5 turns to high level when + transmitter in channle5 have send datas more than reg_rmt_tx_lim_ch5 after detecting this interrupt software can updata the old datas with new datas.*/ +#define RMT_CH5_TX_THR_EVENT_INT_RAW (BIT(29)) +#define RMT_CH5_TX_THR_EVENT_INT_RAW_M (BIT(29)) +#define RMT_CH5_TX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH5_TX_THR_EVENT_INT_RAW_S 29 +/* RMT_CH4_TX_THR_EVENT_INT_RAW : RO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 4 turns to high level when + transmitter in channle4 have send datas more than reg_rmt_tx_lim_ch4 after detecting this interrupt software can updata the old datas with new datas.*/ +#define RMT_CH4_TX_THR_EVENT_INT_RAW (BIT(28)) +#define RMT_CH4_TX_THR_EVENT_INT_RAW_M (BIT(28)) +#define RMT_CH4_TX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH4_TX_THR_EVENT_INT_RAW_S 28 +/* RMT_CH3_TX_THR_EVENT_INT_RAW : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 3 turns to high level when + transmitter in channle3 have send datas more than reg_rmt_tx_lim_ch3 after detecting this interrupt software can updata the old datas with new datas.*/ +#define RMT_CH3_TX_THR_EVENT_INT_RAW (BIT(27)) +#define RMT_CH3_TX_THR_EVENT_INT_RAW_M (BIT(27)) +#define RMT_CH3_TX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH3_TX_THR_EVENT_INT_RAW_S 27 +/* RMT_CH2_TX_THR_EVENT_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 2 turns to high level when + transmitter in channle2 have send datas more than reg_rmt_tx_lim_ch2 after detecting this interrupt software can updata the old datas with new datas.*/ +#define RMT_CH2_TX_THR_EVENT_INT_RAW (BIT(26)) +#define RMT_CH2_TX_THR_EVENT_INT_RAW_M (BIT(26)) +#define RMT_CH2_TX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH2_TX_THR_EVENT_INT_RAW_S 26 +/* RMT_CH1_TX_THR_EVENT_INT_RAW : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 1 turns to high level when + transmitter in channle1 have send datas more than reg_rmt_tx_lim_ch1 after detecting this interrupt software can updata the old datas with new datas.*/ +#define RMT_CH1_TX_THR_EVENT_INT_RAW (BIT(25)) +#define RMT_CH1_TX_THR_EVENT_INT_RAW_M (BIT(25)) +#define RMT_CH1_TX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH1_TX_THR_EVENT_INT_RAW_S 25 +/* RMT_CH0_TX_THR_EVENT_INT_RAW : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 0 turns to high level when + transmitter in channle0 have send datas more than reg_rmt_tx_lim_ch0 after detecting this interrupt software can updata the old datas with new datas.*/ +#define RMT_CH0_TX_THR_EVENT_INT_RAW (BIT(24)) +#define RMT_CH0_TX_THR_EVENT_INT_RAW_M (BIT(24)) +#define RMT_CH0_TX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH0_TX_THR_EVENT_INT_RAW_S 24 +/* RMT_CH7_ERR_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 7 turns to high level when + channle 7 detects some errors.*/ +#define RMT_CH7_ERR_INT_RAW (BIT(23)) +#define RMT_CH7_ERR_INT_RAW_M (BIT(23)) +#define RMT_CH7_ERR_INT_RAW_V 0x1 +#define RMT_CH7_ERR_INT_RAW_S 23 +/* RMT_CH7_RX_END_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 7 turns to high level when + the receive process is done.*/ +#define RMT_CH7_RX_END_INT_RAW (BIT(22)) +#define RMT_CH7_RX_END_INT_RAW_M (BIT(22)) +#define RMT_CH7_RX_END_INT_RAW_V 0x1 +#define RMT_CH7_RX_END_INT_RAW_S 22 +/* RMT_CH7_TX_END_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 7 turns to high level when + the transmit process is done.*/ +#define RMT_CH7_TX_END_INT_RAW (BIT(21)) +#define RMT_CH7_TX_END_INT_RAW_M (BIT(21)) +#define RMT_CH7_TX_END_INT_RAW_V 0x1 +#define RMT_CH7_TX_END_INT_RAW_S 21 +/* RMT_CH6_ERR_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 6 turns to high level when + channle 6 detects some errors.*/ +#define RMT_CH6_ERR_INT_RAW (BIT(20)) +#define RMT_CH6_ERR_INT_RAW_M (BIT(20)) +#define RMT_CH6_ERR_INT_RAW_V 0x1 +#define RMT_CH6_ERR_INT_RAW_S 20 +/* RMT_CH6_RX_END_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 6 turns to high level when + the receive process is done.*/ +#define RMT_CH6_RX_END_INT_RAW (BIT(19)) +#define RMT_CH6_RX_END_INT_RAW_M (BIT(19)) +#define RMT_CH6_RX_END_INT_RAW_V 0x1 +#define RMT_CH6_RX_END_INT_RAW_S 19 +/* RMT_CH6_TX_END_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 6 turns to high level when + the transmit process is done.*/ +#define RMT_CH6_TX_END_INT_RAW (BIT(18)) +#define RMT_CH6_TX_END_INT_RAW_M (BIT(18)) +#define RMT_CH6_TX_END_INT_RAW_V 0x1 +#define RMT_CH6_TX_END_INT_RAW_S 18 +/* RMT_CH5_ERR_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 5 turns to high level when + channle 5 detects some errors.*/ +#define RMT_CH5_ERR_INT_RAW (BIT(17)) +#define RMT_CH5_ERR_INT_RAW_M (BIT(17)) +#define RMT_CH5_ERR_INT_RAW_V 0x1 +#define RMT_CH5_ERR_INT_RAW_S 17 +/* RMT_CH5_RX_END_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 5 turns to high level when + the receive process is done.*/ +#define RMT_CH5_RX_END_INT_RAW (BIT(16)) +#define RMT_CH5_RX_END_INT_RAW_M (BIT(16)) +#define RMT_CH5_RX_END_INT_RAW_V 0x1 +#define RMT_CH5_RX_END_INT_RAW_S 16 +/* RMT_CH5_TX_END_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 5 turns to high level when + the transmit process is done.*/ +#define RMT_CH5_TX_END_INT_RAW (BIT(15)) +#define RMT_CH5_TX_END_INT_RAW_M (BIT(15)) +#define RMT_CH5_TX_END_INT_RAW_V 0x1 +#define RMT_CH5_TX_END_INT_RAW_S 15 +/* RMT_CH4_ERR_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 4 turns to high level when + channle 4 detects some errors.*/ +#define RMT_CH4_ERR_INT_RAW (BIT(14)) +#define RMT_CH4_ERR_INT_RAW_M (BIT(14)) +#define RMT_CH4_ERR_INT_RAW_V 0x1 +#define RMT_CH4_ERR_INT_RAW_S 14 +/* RMT_CH4_RX_END_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 4 turns to high level when + the receive process is done.*/ +#define RMT_CH4_RX_END_INT_RAW (BIT(13)) +#define RMT_CH4_RX_END_INT_RAW_M (BIT(13)) +#define RMT_CH4_RX_END_INT_RAW_V 0x1 +#define RMT_CH4_RX_END_INT_RAW_S 13 +/* RMT_CH4_TX_END_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 4 turns to high level when + the transmit process is done.*/ +#define RMT_CH4_TX_END_INT_RAW (BIT(12)) +#define RMT_CH4_TX_END_INT_RAW_M (BIT(12)) +#define RMT_CH4_TX_END_INT_RAW_V 0x1 +#define RMT_CH4_TX_END_INT_RAW_S 12 +/* RMT_CH3_ERR_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 3 turns to high level when + channle 3 detects some errors.*/ +#define RMT_CH3_ERR_INT_RAW (BIT(11)) +#define RMT_CH3_ERR_INT_RAW_M (BIT(11)) +#define RMT_CH3_ERR_INT_RAW_V 0x1 +#define RMT_CH3_ERR_INT_RAW_S 11 +/* RMT_CH3_RX_END_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 3 turns to high level when + the receive process is done.*/ +#define RMT_CH3_RX_END_INT_RAW (BIT(10)) +#define RMT_CH3_RX_END_INT_RAW_M (BIT(10)) +#define RMT_CH3_RX_END_INT_RAW_V 0x1 +#define RMT_CH3_RX_END_INT_RAW_S 10 +/* RMT_CH3_TX_END_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 3 turns to high level when + the transmit process is done.*/ +#define RMT_CH3_TX_END_INT_RAW (BIT(9)) +#define RMT_CH3_TX_END_INT_RAW_M (BIT(9)) +#define RMT_CH3_TX_END_INT_RAW_V 0x1 +#define RMT_CH3_TX_END_INT_RAW_S 9 +/* RMT_CH2_ERR_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 2 turns to high level when + channle 2 detects some errors.*/ +#define RMT_CH2_ERR_INT_RAW (BIT(8)) +#define RMT_CH2_ERR_INT_RAW_M (BIT(8)) +#define RMT_CH2_ERR_INT_RAW_V 0x1 +#define RMT_CH2_ERR_INT_RAW_S 8 +/* RMT_CH2_RX_END_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 2 turns to high level when + the receive process is done.*/ +#define RMT_CH2_RX_END_INT_RAW (BIT(7)) +#define RMT_CH2_RX_END_INT_RAW_M (BIT(7)) +#define RMT_CH2_RX_END_INT_RAW_V 0x1 +#define RMT_CH2_RX_END_INT_RAW_S 7 +/* RMT_CH2_TX_END_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 2 turns to high level when + the transmit process is done.*/ +#define RMT_CH2_TX_END_INT_RAW (BIT(6)) +#define RMT_CH2_TX_END_INT_RAW_M (BIT(6)) +#define RMT_CH2_TX_END_INT_RAW_V 0x1 +#define RMT_CH2_TX_END_INT_RAW_S 6 +/* RMT_CH1_ERR_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 1 turns to high level when + channle 1 detects some errors.*/ +#define RMT_CH1_ERR_INT_RAW (BIT(5)) +#define RMT_CH1_ERR_INT_RAW_M (BIT(5)) +#define RMT_CH1_ERR_INT_RAW_V 0x1 +#define RMT_CH1_ERR_INT_RAW_S 5 +/* RMT_CH1_RX_END_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 1 turns to high level when + the receive process is done.*/ +#define RMT_CH1_RX_END_INT_RAW (BIT(4)) +#define RMT_CH1_RX_END_INT_RAW_M (BIT(4)) +#define RMT_CH1_RX_END_INT_RAW_V 0x1 +#define RMT_CH1_RX_END_INT_RAW_S 4 +/* RMT_CH1_TX_END_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 1 turns to high level when + the transmit process is done.*/ +#define RMT_CH1_TX_END_INT_RAW (BIT(3)) +#define RMT_CH1_TX_END_INT_RAW_M (BIT(3)) +#define RMT_CH1_TX_END_INT_RAW_V 0x1 +#define RMT_CH1_TX_END_INT_RAW_S 3 +/* RMT_CH0_ERR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 0 turns to high level when + channle 0 detects some errors.*/ +#define RMT_CH0_ERR_INT_RAW (BIT(2)) +#define RMT_CH0_ERR_INT_RAW_M (BIT(2)) +#define RMT_CH0_ERR_INT_RAW_V 0x1 +#define RMT_CH0_ERR_INT_RAW_S 2 +/* RMT_CH0_RX_END_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 0 turns to high level when + the receive process is done.*/ +#define RMT_CH0_RX_END_INT_RAW (BIT(1)) +#define RMT_CH0_RX_END_INT_RAW_M (BIT(1)) +#define RMT_CH0_RX_END_INT_RAW_V 0x1 +#define RMT_CH0_RX_END_INT_RAW_S 1 +/* RMT_CH0_TX_END_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 0 turns to high level when + the transmit process is done.*/ +#define RMT_CH0_TX_END_INT_RAW (BIT(0)) +#define RMT_CH0_TX_END_INT_RAW_M (BIT(0)) +#define RMT_CH0_TX_END_INT_RAW_V 0x1 +#define RMT_CH0_TX_END_INT_RAW_S 0 + +#define RMT_INT_ST_REG (DR_REG_RMT_BASE + 0x00a4) +/* RMT_CH7_TX_THR_EVENT_INT_ST : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 7's rmt_ch7_tx_thr_event_int_raw + when mt_ch7_tx_thr_event_int_ena is set to 1.*/ +#define RMT_CH7_TX_THR_EVENT_INT_ST (BIT(31)) +#define RMT_CH7_TX_THR_EVENT_INT_ST_M (BIT(31)) +#define RMT_CH7_TX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH7_TX_THR_EVENT_INT_ST_S 31 +/* RMT_CH6_TX_THR_EVENT_INT_ST : RO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 6's rmt_ch6_tx_thr_event_int_raw + when mt_ch6_tx_thr_event_int_ena is set to 1.*/ +#define RMT_CH6_TX_THR_EVENT_INT_ST (BIT(30)) +#define RMT_CH6_TX_THR_EVENT_INT_ST_M (BIT(30)) +#define RMT_CH6_TX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH6_TX_THR_EVENT_INT_ST_S 30 +/* RMT_CH5_TX_THR_EVENT_INT_ST : RO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 5's rmt_ch5_tx_thr_event_int_raw + when mt_ch5_tx_thr_event_int_ena is set to 1.*/ +#define RMT_CH5_TX_THR_EVENT_INT_ST (BIT(29)) +#define RMT_CH5_TX_THR_EVENT_INT_ST_M (BIT(29)) +#define RMT_CH5_TX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH5_TX_THR_EVENT_INT_ST_S 29 +/* RMT_CH4_TX_THR_EVENT_INT_ST : RO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 4's rmt_ch4_tx_thr_event_int_raw + when mt_ch4_tx_thr_event_int_ena is set to 1.*/ +#define RMT_CH4_TX_THR_EVENT_INT_ST (BIT(28)) +#define RMT_CH4_TX_THR_EVENT_INT_ST_M (BIT(28)) +#define RMT_CH4_TX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH4_TX_THR_EVENT_INT_ST_S 28 +/* RMT_CH3_TX_THR_EVENT_INT_ST : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 3's rmt_ch3_tx_thr_event_int_raw + when mt_ch3_tx_thr_event_int_ena is set to 1.*/ +#define RMT_CH3_TX_THR_EVENT_INT_ST (BIT(27)) +#define RMT_CH3_TX_THR_EVENT_INT_ST_M (BIT(27)) +#define RMT_CH3_TX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH3_TX_THR_EVENT_INT_ST_S 27 +/* RMT_CH2_TX_THR_EVENT_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 2's rmt_ch2_tx_thr_event_int_raw + when mt_ch2_tx_thr_event_int_ena is set to 1.*/ +#define RMT_CH2_TX_THR_EVENT_INT_ST (BIT(26)) +#define RMT_CH2_TX_THR_EVENT_INT_ST_M (BIT(26)) +#define RMT_CH2_TX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH2_TX_THR_EVENT_INT_ST_S 26 +/* RMT_CH1_TX_THR_EVENT_INT_ST : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 1's rmt_ch1_tx_thr_event_int_raw + when mt_ch1_tx_thr_event_int_ena is set to 1.*/ +#define RMT_CH1_TX_THR_EVENT_INT_ST (BIT(25)) +#define RMT_CH1_TX_THR_EVENT_INT_ST_M (BIT(25)) +#define RMT_CH1_TX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH1_TX_THR_EVENT_INT_ST_S 25 +/* RMT_CH0_TX_THR_EVENT_INT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 0's rmt_ch0_tx_thr_event_int_raw + when mt_ch0_tx_thr_event_int_ena is set to 1.*/ +#define RMT_CH0_TX_THR_EVENT_INT_ST (BIT(24)) +#define RMT_CH0_TX_THR_EVENT_INT_ST_M (BIT(24)) +#define RMT_CH0_TX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH0_TX_THR_EVENT_INT_ST_S 24 +/* RMT_CH7_ERR_INT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 7's rmt_ch7_err_int_raw + when rmt_ch7_err_int_ena is set to 1.*/ +#define RMT_CH7_ERR_INT_ST (BIT(23)) +#define RMT_CH7_ERR_INT_ST_M (BIT(23)) +#define RMT_CH7_ERR_INT_ST_V 0x1 +#define RMT_CH7_ERR_INT_ST_S 23 +/* RMT_CH7_RX_END_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 7's rmt_ch7_rx_end_int_raw + when rmt_ch7_rx_end_int_ena is set to 1.*/ +#define RMT_CH7_RX_END_INT_ST (BIT(22)) +#define RMT_CH7_RX_END_INT_ST_M (BIT(22)) +#define RMT_CH7_RX_END_INT_ST_V 0x1 +#define RMT_CH7_RX_END_INT_ST_S 22 +/* RMT_CH7_TX_END_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 7's mt_ch7_tx_end_int_raw + when mt_ch7_tx_end_int_ena is set to 1.*/ +#define RMT_CH7_TX_END_INT_ST (BIT(21)) +#define RMT_CH7_TX_END_INT_ST_M (BIT(21)) +#define RMT_CH7_TX_END_INT_ST_V 0x1 +#define RMT_CH7_TX_END_INT_ST_S 21 +/* RMT_CH6_ERR_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 6's rmt_ch6_err_int_raw + when rmt_ch6_err_int_ena is set to 1.*/ +#define RMT_CH6_ERR_INT_ST (BIT(20)) +#define RMT_CH6_ERR_INT_ST_M (BIT(20)) +#define RMT_CH6_ERR_INT_ST_V 0x1 +#define RMT_CH6_ERR_INT_ST_S 20 +/* RMT_CH6_RX_END_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 6's rmt_ch6_rx_end_int_raw + when rmt_ch6_rx_end_int_ena is set to 1.*/ +#define RMT_CH6_RX_END_INT_ST (BIT(19)) +#define RMT_CH6_RX_END_INT_ST_M (BIT(19)) +#define RMT_CH6_RX_END_INT_ST_V 0x1 +#define RMT_CH6_RX_END_INT_ST_S 19 +/* RMT_CH6_TX_END_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 6's mt_ch6_tx_end_int_raw + when mt_ch6_tx_end_int_ena is set to 1.*/ +#define RMT_CH6_TX_END_INT_ST (BIT(18)) +#define RMT_CH6_TX_END_INT_ST_M (BIT(18)) +#define RMT_CH6_TX_END_INT_ST_V 0x1 +#define RMT_CH6_TX_END_INT_ST_S 18 +/* RMT_CH5_ERR_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 5's rmt_ch5_err_int_raw + when rmt_ch5_err_int_ena is set to 1.*/ +#define RMT_CH5_ERR_INT_ST (BIT(17)) +#define RMT_CH5_ERR_INT_ST_M (BIT(17)) +#define RMT_CH5_ERR_INT_ST_V 0x1 +#define RMT_CH5_ERR_INT_ST_S 17 +/* RMT_CH5_RX_END_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 5's rmt_ch5_rx_end_int_raw + when rmt_ch5_rx_end_int_ena is set to 1.*/ +#define RMT_CH5_RX_END_INT_ST (BIT(16)) +#define RMT_CH5_RX_END_INT_ST_M (BIT(16)) +#define RMT_CH5_RX_END_INT_ST_V 0x1 +#define RMT_CH5_RX_END_INT_ST_S 16 +/* RMT_CH5_TX_END_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 5's mt_ch5_tx_end_int_raw + when mt_ch5_tx_end_int_ena is set to 1.*/ +#define RMT_CH5_TX_END_INT_ST (BIT(15)) +#define RMT_CH5_TX_END_INT_ST_M (BIT(15)) +#define RMT_CH5_TX_END_INT_ST_V 0x1 +#define RMT_CH5_TX_END_INT_ST_S 15 +/* RMT_CH4_ERR_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 4's rmt_ch4_err_int_raw + when rmt_ch4_err_int_ena is set to 1.*/ +#define RMT_CH4_ERR_INT_ST (BIT(14)) +#define RMT_CH4_ERR_INT_ST_M (BIT(14)) +#define RMT_CH4_ERR_INT_ST_V 0x1 +#define RMT_CH4_ERR_INT_ST_S 14 +/* RMT_CH4_RX_END_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 4's rmt_ch4_rx_end_int_raw + when rmt_ch4_rx_end_int_ena is set to 1.*/ +#define RMT_CH4_RX_END_INT_ST (BIT(13)) +#define RMT_CH4_RX_END_INT_ST_M (BIT(13)) +#define RMT_CH4_RX_END_INT_ST_V 0x1 +#define RMT_CH4_RX_END_INT_ST_S 13 +/* RMT_CH4_TX_END_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 4's mt_ch4_tx_end_int_raw + when mt_ch4_tx_end_int_ena is set to 1.*/ +#define RMT_CH4_TX_END_INT_ST (BIT(12)) +#define RMT_CH4_TX_END_INT_ST_M (BIT(12)) +#define RMT_CH4_TX_END_INT_ST_V 0x1 +#define RMT_CH4_TX_END_INT_ST_S 12 +/* RMT_CH3_ERR_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 3's rmt_ch3_err_int_raw + when rmt_ch3_err_int_ena is set to 1.*/ +#define RMT_CH3_ERR_INT_ST (BIT(11)) +#define RMT_CH3_ERR_INT_ST_M (BIT(11)) +#define RMT_CH3_ERR_INT_ST_V 0x1 +#define RMT_CH3_ERR_INT_ST_S 11 +/* RMT_CH3_RX_END_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 3's rmt_ch3_rx_end_int_raw + when rmt_ch3_rx_end_int_ena is set to 1.*/ +#define RMT_CH3_RX_END_INT_ST (BIT(10)) +#define RMT_CH3_RX_END_INT_ST_M (BIT(10)) +#define RMT_CH3_RX_END_INT_ST_V 0x1 +#define RMT_CH3_RX_END_INT_ST_S 10 +/* RMT_CH3_TX_END_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 3's mt_ch3_tx_end_int_raw + when mt_ch3_tx_end_int_ena is set to 1.*/ +#define RMT_CH3_TX_END_INT_ST (BIT(9)) +#define RMT_CH3_TX_END_INT_ST_M (BIT(9)) +#define RMT_CH3_TX_END_INT_ST_V 0x1 +#define RMT_CH3_TX_END_INT_ST_S 9 +/* RMT_CH2_ERR_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 2's rmt_ch2_err_int_raw + when rmt_ch2_err_int_ena is set to 1.*/ +#define RMT_CH2_ERR_INT_ST (BIT(8)) +#define RMT_CH2_ERR_INT_ST_M (BIT(8)) +#define RMT_CH2_ERR_INT_ST_V 0x1 +#define RMT_CH2_ERR_INT_ST_S 8 +/* RMT_CH2_RX_END_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 2's rmt_ch2_rx_end_int_raw + when rmt_ch2_rx_end_int_ena is set to 1.*/ +#define RMT_CH2_RX_END_INT_ST (BIT(7)) +#define RMT_CH2_RX_END_INT_ST_M (BIT(7)) +#define RMT_CH2_RX_END_INT_ST_V 0x1 +#define RMT_CH2_RX_END_INT_ST_S 7 +/* RMT_CH2_TX_END_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 2's mt_ch2_tx_end_int_raw + when mt_ch2_tx_end_int_ena is set to 1.*/ +#define RMT_CH2_TX_END_INT_ST (BIT(6)) +#define RMT_CH2_TX_END_INT_ST_M (BIT(6)) +#define RMT_CH2_TX_END_INT_ST_V 0x1 +#define RMT_CH2_TX_END_INT_ST_S 6 +/* RMT_CH1_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 1's rmt_ch1_err_int_raw + when rmt_ch1_err_int_ena is set to 1.*/ +#define RMT_CH1_ERR_INT_ST (BIT(5)) +#define RMT_CH1_ERR_INT_ST_M (BIT(5)) +#define RMT_CH1_ERR_INT_ST_V 0x1 +#define RMT_CH1_ERR_INT_ST_S 5 +/* RMT_CH1_RX_END_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 1's rmt_ch1_rx_end_int_raw + when rmt_ch1_rx_end_int_ena is set to 1.*/ +#define RMT_CH1_RX_END_INT_ST (BIT(4)) +#define RMT_CH1_RX_END_INT_ST_M (BIT(4)) +#define RMT_CH1_RX_END_INT_ST_V 0x1 +#define RMT_CH1_RX_END_INT_ST_S 4 +/* RMT_CH1_TX_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 1's mt_ch1_tx_end_int_raw + when mt_ch1_tx_end_int_ena is set to 1.*/ +#define RMT_CH1_TX_END_INT_ST (BIT(3)) +#define RMT_CH1_TX_END_INT_ST_M (BIT(3)) +#define RMT_CH1_TX_END_INT_ST_V 0x1 +#define RMT_CH1_TX_END_INT_ST_S 3 +/* RMT_CH0_ERR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 0's rmt_ch0_err_int_raw + when rmt_ch0_err_int_ena is set to 0.*/ +#define RMT_CH0_ERR_INT_ST (BIT(2)) +#define RMT_CH0_ERR_INT_ST_M (BIT(2)) +#define RMT_CH0_ERR_INT_ST_V 0x1 +#define RMT_CH0_ERR_INT_ST_S 2 +/* RMT_CH0_RX_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 0's rmt_ch0_rx_end_int_raw + when rmt_ch0_rx_end_int_ena is set to 0.*/ +#define RMT_CH0_RX_END_INT_ST (BIT(1)) +#define RMT_CH0_RX_END_INT_ST_M (BIT(1)) +#define RMT_CH0_RX_END_INT_ST_V 0x1 +#define RMT_CH0_RX_END_INT_ST_S 1 +/* RMT_CH0_TX_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 0's mt_ch0_tx_end_int_raw + when mt_ch0_tx_end_int_ena is set to 0.*/ +#define RMT_CH0_TX_END_INT_ST (BIT(0)) +#define RMT_CH0_TX_END_INT_ST_M (BIT(0)) +#define RMT_CH0_TX_END_INT_ST_V 0x1 +#define RMT_CH0_TX_END_INT_ST_S 0 + +#define RMT_INT_ENA_REG (DR_REG_RMT_BASE + 0x00a8) +/* RMT_CH7_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch7_tx_thr_event_int_st.*/ +#define RMT_CH7_TX_THR_EVENT_INT_ENA (BIT(31)) +#define RMT_CH7_TX_THR_EVENT_INT_ENA_M (BIT(31)) +#define RMT_CH7_TX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH7_TX_THR_EVENT_INT_ENA_S 31 +/* RMT_CH6_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch6_tx_thr_event_int_st.*/ +#define RMT_CH6_TX_THR_EVENT_INT_ENA (BIT(30)) +#define RMT_CH6_TX_THR_EVENT_INT_ENA_M (BIT(30)) +#define RMT_CH6_TX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH6_TX_THR_EVENT_INT_ENA_S 30 +/* RMT_CH5_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch5_tx_thr_event_int_st.*/ +#define RMT_CH5_TX_THR_EVENT_INT_ENA (BIT(29)) +#define RMT_CH5_TX_THR_EVENT_INT_ENA_M (BIT(29)) +#define RMT_CH5_TX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH5_TX_THR_EVENT_INT_ENA_S 29 +/* RMT_CH4_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch4_tx_thr_event_int_st.*/ +#define RMT_CH4_TX_THR_EVENT_INT_ENA (BIT(28)) +#define RMT_CH4_TX_THR_EVENT_INT_ENA_M (BIT(28)) +#define RMT_CH4_TX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH4_TX_THR_EVENT_INT_ENA_S 28 +/* RMT_CH3_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch3_tx_thr_event_int_st.*/ +#define RMT_CH3_TX_THR_EVENT_INT_ENA (BIT(27)) +#define RMT_CH3_TX_THR_EVENT_INT_ENA_M (BIT(27)) +#define RMT_CH3_TX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH3_TX_THR_EVENT_INT_ENA_S 27 +/* RMT_CH2_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch2_tx_thr_event_int_st.*/ +#define RMT_CH2_TX_THR_EVENT_INT_ENA (BIT(26)) +#define RMT_CH2_TX_THR_EVENT_INT_ENA_M (BIT(26)) +#define RMT_CH2_TX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH2_TX_THR_EVENT_INT_ENA_S 26 +/* RMT_CH1_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch1_tx_thr_event_int_st.*/ +#define RMT_CH1_TX_THR_EVENT_INT_ENA (BIT(25)) +#define RMT_CH1_TX_THR_EVENT_INT_ENA_M (BIT(25)) +#define RMT_CH1_TX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH1_TX_THR_EVENT_INT_ENA_S 25 +/* RMT_CH0_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch0_tx_thr_event_int_st.*/ +#define RMT_CH0_TX_THR_EVENT_INT_ENA (BIT(24)) +#define RMT_CH0_TX_THR_EVENT_INT_ENA_M (BIT(24)) +#define RMT_CH0_TX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH0_TX_THR_EVENT_INT_ENA_S 24 +/* RMT_CH7_ERR_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch7_err_int_st.*/ +#define RMT_CH7_ERR_INT_ENA (BIT(23)) +#define RMT_CH7_ERR_INT_ENA_M (BIT(23)) +#define RMT_CH7_ERR_INT_ENA_V 0x1 +#define RMT_CH7_ERR_INT_ENA_S 23 +/* RMT_CH7_RX_END_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch7_rx_end_int_st.*/ +#define RMT_CH7_RX_END_INT_ENA (BIT(22)) +#define RMT_CH7_RX_END_INT_ENA_M (BIT(22)) +#define RMT_CH7_RX_END_INT_ENA_V 0x1 +#define RMT_CH7_RX_END_INT_ENA_S 22 +/* RMT_CH7_TX_END_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch7_tx_end_int_st.*/ +#define RMT_CH7_TX_END_INT_ENA (BIT(21)) +#define RMT_CH7_TX_END_INT_ENA_M (BIT(21)) +#define RMT_CH7_TX_END_INT_ENA_V 0x1 +#define RMT_CH7_TX_END_INT_ENA_S 21 +/* RMT_CH6_ERR_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch6_err_int_st.*/ +#define RMT_CH6_ERR_INT_ENA (BIT(20)) +#define RMT_CH6_ERR_INT_ENA_M (BIT(20)) +#define RMT_CH6_ERR_INT_ENA_V 0x1 +#define RMT_CH6_ERR_INT_ENA_S 20 +/* RMT_CH6_RX_END_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch6_rx_end_int_st.*/ +#define RMT_CH6_RX_END_INT_ENA (BIT(19)) +#define RMT_CH6_RX_END_INT_ENA_M (BIT(19)) +#define RMT_CH6_RX_END_INT_ENA_V 0x1 +#define RMT_CH6_RX_END_INT_ENA_S 19 +/* RMT_CH6_TX_END_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch6_tx_end_int_st.*/ +#define RMT_CH6_TX_END_INT_ENA (BIT(18)) +#define RMT_CH6_TX_END_INT_ENA_M (BIT(18)) +#define RMT_CH6_TX_END_INT_ENA_V 0x1 +#define RMT_CH6_TX_END_INT_ENA_S 18 +/* RMT_CH5_ERR_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch5_err_int_st.*/ +#define RMT_CH5_ERR_INT_ENA (BIT(17)) +#define RMT_CH5_ERR_INT_ENA_M (BIT(17)) +#define RMT_CH5_ERR_INT_ENA_V 0x1 +#define RMT_CH5_ERR_INT_ENA_S 17 +/* RMT_CH5_RX_END_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch5_rx_end_int_st.*/ +#define RMT_CH5_RX_END_INT_ENA (BIT(16)) +#define RMT_CH5_RX_END_INT_ENA_M (BIT(16)) +#define RMT_CH5_RX_END_INT_ENA_V 0x1 +#define RMT_CH5_RX_END_INT_ENA_S 16 +/* RMT_CH5_TX_END_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch5_tx_end_int_st.*/ +#define RMT_CH5_TX_END_INT_ENA (BIT(15)) +#define RMT_CH5_TX_END_INT_ENA_M (BIT(15)) +#define RMT_CH5_TX_END_INT_ENA_V 0x1 +#define RMT_CH5_TX_END_INT_ENA_S 15 +/* RMT_CH4_ERR_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch4_err_int_st.*/ +#define RMT_CH4_ERR_INT_ENA (BIT(14)) +#define RMT_CH4_ERR_INT_ENA_M (BIT(14)) +#define RMT_CH4_ERR_INT_ENA_V 0x1 +#define RMT_CH4_ERR_INT_ENA_S 14 +/* RMT_CH4_RX_END_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch4_rx_end_int_st.*/ +#define RMT_CH4_RX_END_INT_ENA (BIT(13)) +#define RMT_CH4_RX_END_INT_ENA_M (BIT(13)) +#define RMT_CH4_RX_END_INT_ENA_V 0x1 +#define RMT_CH4_RX_END_INT_ENA_S 13 +/* RMT_CH4_TX_END_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch4_tx_end_int_st.*/ +#define RMT_CH4_TX_END_INT_ENA (BIT(12)) +#define RMT_CH4_TX_END_INT_ENA_M (BIT(12)) +#define RMT_CH4_TX_END_INT_ENA_V 0x1 +#define RMT_CH4_TX_END_INT_ENA_S 12 +/* RMT_CH3_ERR_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch3_err_int_st.*/ +#define RMT_CH3_ERR_INT_ENA (BIT(11)) +#define RMT_CH3_ERR_INT_ENA_M (BIT(11)) +#define RMT_CH3_ERR_INT_ENA_V 0x1 +#define RMT_CH3_ERR_INT_ENA_S 11 +/* RMT_CH3_RX_END_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch3_rx_end_int_st.*/ +#define RMT_CH3_RX_END_INT_ENA (BIT(10)) +#define RMT_CH3_RX_END_INT_ENA_M (BIT(10)) +#define RMT_CH3_RX_END_INT_ENA_V 0x1 +#define RMT_CH3_RX_END_INT_ENA_S 10 +/* RMT_CH3_TX_END_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch3_tx_end_int_st.*/ +#define RMT_CH3_TX_END_INT_ENA (BIT(9)) +#define RMT_CH3_TX_END_INT_ENA_M (BIT(9)) +#define RMT_CH3_TX_END_INT_ENA_V 0x1 +#define RMT_CH3_TX_END_INT_ENA_S 9 +/* RMT_CH2_ERR_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch2_err_int_st.*/ +#define RMT_CH2_ERR_INT_ENA (BIT(8)) +#define RMT_CH2_ERR_INT_ENA_M (BIT(8)) +#define RMT_CH2_ERR_INT_ENA_V 0x1 +#define RMT_CH2_ERR_INT_ENA_S 8 +/* RMT_CH2_RX_END_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch2_rx_end_int_st.*/ +#define RMT_CH2_RX_END_INT_ENA (BIT(7)) +#define RMT_CH2_RX_END_INT_ENA_M (BIT(7)) +#define RMT_CH2_RX_END_INT_ENA_V 0x1 +#define RMT_CH2_RX_END_INT_ENA_S 7 +/* RMT_CH2_TX_END_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch2_tx_end_int_st.*/ +#define RMT_CH2_TX_END_INT_ENA (BIT(6)) +#define RMT_CH2_TX_END_INT_ENA_M (BIT(6)) +#define RMT_CH2_TX_END_INT_ENA_V 0x1 +#define RMT_CH2_TX_END_INT_ENA_S 6 +/* RMT_CH1_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch1_err_int_st.*/ +#define RMT_CH1_ERR_INT_ENA (BIT(5)) +#define RMT_CH1_ERR_INT_ENA_M (BIT(5)) +#define RMT_CH1_ERR_INT_ENA_V 0x1 +#define RMT_CH1_ERR_INT_ENA_S 5 +/* RMT_CH1_RX_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch1_rx_end_int_st.*/ +#define RMT_CH1_RX_END_INT_ENA (BIT(4)) +#define RMT_CH1_RX_END_INT_ENA_M (BIT(4)) +#define RMT_CH1_RX_END_INT_ENA_V 0x1 +#define RMT_CH1_RX_END_INT_ENA_S 4 +/* RMT_CH1_TX_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch1_tx_end_int_st.*/ +#define RMT_CH1_TX_END_INT_ENA (BIT(3)) +#define RMT_CH1_TX_END_INT_ENA_M (BIT(3)) +#define RMT_CH1_TX_END_INT_ENA_V 0x1 +#define RMT_CH1_TX_END_INT_ENA_S 3 +/* RMT_CH0_ERR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch0_err_int_st.*/ +#define RMT_CH0_ERR_INT_ENA (BIT(2)) +#define RMT_CH0_ERR_INT_ENA_M (BIT(2)) +#define RMT_CH0_ERR_INT_ENA_V 0x1 +#define RMT_CH0_ERR_INT_ENA_S 2 +/* RMT_CH0_RX_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch0_rx_end_int_st.*/ +#define RMT_CH0_RX_END_INT_ENA (BIT(1)) +#define RMT_CH0_RX_END_INT_ENA_M (BIT(1)) +#define RMT_CH0_RX_END_INT_ENA_V 0x1 +#define RMT_CH0_RX_END_INT_ENA_S 1 +/* RMT_CH0_TX_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch0_tx_end_int_st.*/ +#define RMT_CH0_TX_END_INT_ENA (BIT(0)) +#define RMT_CH0_TX_END_INT_ENA_M (BIT(0)) +#define RMT_CH0_TX_END_INT_ENA_V 0x1 +#define RMT_CH0_TX_END_INT_ENA_S 0 + +#define RMT_INT_CLR_REG (DR_REG_RMT_BASE + 0x00ac) +/* RMT_CH7_TX_THR_EVENT_INT_CLR : WO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch7_tx_thr_event_int_raw interrupt.*/ +#define RMT_CH7_TX_THR_EVENT_INT_CLR (BIT(31)) +#define RMT_CH7_TX_THR_EVENT_INT_CLR_M (BIT(31)) +#define RMT_CH7_TX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH7_TX_THR_EVENT_INT_CLR_S 31 +/* RMT_CH6_TX_THR_EVENT_INT_CLR : WO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch6_tx_thr_event_int_raw interrupt.*/ +#define RMT_CH6_TX_THR_EVENT_INT_CLR (BIT(30)) +#define RMT_CH6_TX_THR_EVENT_INT_CLR_M (BIT(30)) +#define RMT_CH6_TX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH6_TX_THR_EVENT_INT_CLR_S 30 +/* RMT_CH5_TX_THR_EVENT_INT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch5_tx_thr_event_int_raw interrupt.*/ +#define RMT_CH5_TX_THR_EVENT_INT_CLR (BIT(29)) +#define RMT_CH5_TX_THR_EVENT_INT_CLR_M (BIT(29)) +#define RMT_CH5_TX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH5_TX_THR_EVENT_INT_CLR_S 29 +/* RMT_CH4_TX_THR_EVENT_INT_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch4_tx_thr_event_int_raw interrupt.*/ +#define RMT_CH4_TX_THR_EVENT_INT_CLR (BIT(28)) +#define RMT_CH4_TX_THR_EVENT_INT_CLR_M (BIT(28)) +#define RMT_CH4_TX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH4_TX_THR_EVENT_INT_CLR_S 28 +/* RMT_CH3_TX_THR_EVENT_INT_CLR : WO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch3_tx_thr_event_int_raw interrupt.*/ +#define RMT_CH3_TX_THR_EVENT_INT_CLR (BIT(27)) +#define RMT_CH3_TX_THR_EVENT_INT_CLR_M (BIT(27)) +#define RMT_CH3_TX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH3_TX_THR_EVENT_INT_CLR_S 27 +/* RMT_CH2_TX_THR_EVENT_INT_CLR : WO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch2_tx_thr_event_int_raw interrupt.*/ +#define RMT_CH2_TX_THR_EVENT_INT_CLR (BIT(26)) +#define RMT_CH2_TX_THR_EVENT_INT_CLR_M (BIT(26)) +#define RMT_CH2_TX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH2_TX_THR_EVENT_INT_CLR_S 26 +/* RMT_CH1_TX_THR_EVENT_INT_CLR : WO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch1_tx_thr_event_int_raw interrupt.*/ +#define RMT_CH1_TX_THR_EVENT_INT_CLR (BIT(25)) +#define RMT_CH1_TX_THR_EVENT_INT_CLR_M (BIT(25)) +#define RMT_CH1_TX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH1_TX_THR_EVENT_INT_CLR_S 25 +/* RMT_CH0_TX_THR_EVENT_INT_CLR : WO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch0_tx_thr_event_int_raw interrupt.*/ +#define RMT_CH0_TX_THR_EVENT_INT_CLR (BIT(24)) +#define RMT_CH0_TX_THR_EVENT_INT_CLR_M (BIT(24)) +#define RMT_CH0_TX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH0_TX_THR_EVENT_INT_CLR_S 24 +/* RMT_CH7_ERR_INT_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch7_err_int_raw.*/ +#define RMT_CH7_ERR_INT_CLR (BIT(23)) +#define RMT_CH7_ERR_INT_CLR_M (BIT(23)) +#define RMT_CH7_ERR_INT_CLR_V 0x1 +#define RMT_CH7_ERR_INT_CLR_S 23 +/* RMT_CH7_RX_END_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch7_tx_end_int_raw.*/ +#define RMT_CH7_RX_END_INT_CLR (BIT(22)) +#define RMT_CH7_RX_END_INT_CLR_M (BIT(22)) +#define RMT_CH7_RX_END_INT_CLR_V 0x1 +#define RMT_CH7_RX_END_INT_CLR_S 22 +/* RMT_CH7_TX_END_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch7_rx_end_int_raw..*/ +#define RMT_CH7_TX_END_INT_CLR (BIT(21)) +#define RMT_CH7_TX_END_INT_CLR_M (BIT(21)) +#define RMT_CH7_TX_END_INT_CLR_V 0x1 +#define RMT_CH7_TX_END_INT_CLR_S 21 +/* RMT_CH6_ERR_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch6_err_int_raw.*/ +#define RMT_CH6_ERR_INT_CLR (BIT(20)) +#define RMT_CH6_ERR_INT_CLR_M (BIT(20)) +#define RMT_CH6_ERR_INT_CLR_V 0x1 +#define RMT_CH6_ERR_INT_CLR_S 20 +/* RMT_CH6_RX_END_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch6_tx_end_int_raw.*/ +#define RMT_CH6_RX_END_INT_CLR (BIT(19)) +#define RMT_CH6_RX_END_INT_CLR_M (BIT(19)) +#define RMT_CH6_RX_END_INT_CLR_V 0x1 +#define RMT_CH6_RX_END_INT_CLR_S 19 +/* RMT_CH6_TX_END_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch6_rx_end_int_raw..*/ +#define RMT_CH6_TX_END_INT_CLR (BIT(18)) +#define RMT_CH6_TX_END_INT_CLR_M (BIT(18)) +#define RMT_CH6_TX_END_INT_CLR_V 0x1 +#define RMT_CH6_TX_END_INT_CLR_S 18 +/* RMT_CH5_ERR_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch5_err_int_raw.*/ +#define RMT_CH5_ERR_INT_CLR (BIT(17)) +#define RMT_CH5_ERR_INT_CLR_M (BIT(17)) +#define RMT_CH5_ERR_INT_CLR_V 0x1 +#define RMT_CH5_ERR_INT_CLR_S 17 +/* RMT_CH5_RX_END_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch5_tx_end_int_raw.*/ +#define RMT_CH5_RX_END_INT_CLR (BIT(16)) +#define RMT_CH5_RX_END_INT_CLR_M (BIT(16)) +#define RMT_CH5_RX_END_INT_CLR_V 0x1 +#define RMT_CH5_RX_END_INT_CLR_S 16 +/* RMT_CH5_TX_END_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch5_rx_end_int_raw..*/ +#define RMT_CH5_TX_END_INT_CLR (BIT(15)) +#define RMT_CH5_TX_END_INT_CLR_M (BIT(15)) +#define RMT_CH5_TX_END_INT_CLR_V 0x1 +#define RMT_CH5_TX_END_INT_CLR_S 15 +/* RMT_CH4_ERR_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch4_err_int_raw.*/ +#define RMT_CH4_ERR_INT_CLR (BIT(14)) +#define RMT_CH4_ERR_INT_CLR_M (BIT(14)) +#define RMT_CH4_ERR_INT_CLR_V 0x1 +#define RMT_CH4_ERR_INT_CLR_S 14 +/* RMT_CH4_RX_END_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch4_tx_end_int_raw.*/ +#define RMT_CH4_RX_END_INT_CLR (BIT(13)) +#define RMT_CH4_RX_END_INT_CLR_M (BIT(13)) +#define RMT_CH4_RX_END_INT_CLR_V 0x1 +#define RMT_CH4_RX_END_INT_CLR_S 13 +/* RMT_CH4_TX_END_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch4_rx_end_int_raw..*/ +#define RMT_CH4_TX_END_INT_CLR (BIT(12)) +#define RMT_CH4_TX_END_INT_CLR_M (BIT(12)) +#define RMT_CH4_TX_END_INT_CLR_V 0x1 +#define RMT_CH4_TX_END_INT_CLR_S 12 +/* RMT_CH3_ERR_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch3_err_int_raw.*/ +#define RMT_CH3_ERR_INT_CLR (BIT(11)) +#define RMT_CH3_ERR_INT_CLR_M (BIT(11)) +#define RMT_CH3_ERR_INT_CLR_V 0x1 +#define RMT_CH3_ERR_INT_CLR_S 11 +/* RMT_CH3_RX_END_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch3_tx_end_int_raw.*/ +#define RMT_CH3_RX_END_INT_CLR (BIT(10)) +#define RMT_CH3_RX_END_INT_CLR_M (BIT(10)) +#define RMT_CH3_RX_END_INT_CLR_V 0x1 +#define RMT_CH3_RX_END_INT_CLR_S 10 +/* RMT_CH3_TX_END_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch3_rx_end_int_raw..*/ +#define RMT_CH3_TX_END_INT_CLR (BIT(9)) +#define RMT_CH3_TX_END_INT_CLR_M (BIT(9)) +#define RMT_CH3_TX_END_INT_CLR_V 0x1 +#define RMT_CH3_TX_END_INT_CLR_S 9 +/* RMT_CH2_ERR_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch2_err_int_raw.*/ +#define RMT_CH2_ERR_INT_CLR (BIT(8)) +#define RMT_CH2_ERR_INT_CLR_M (BIT(8)) +#define RMT_CH2_ERR_INT_CLR_V 0x1 +#define RMT_CH2_ERR_INT_CLR_S 8 +/* RMT_CH2_RX_END_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch2_tx_end_int_raw.*/ +#define RMT_CH2_RX_END_INT_CLR (BIT(7)) +#define RMT_CH2_RX_END_INT_CLR_M (BIT(7)) +#define RMT_CH2_RX_END_INT_CLR_V 0x1 +#define RMT_CH2_RX_END_INT_CLR_S 7 +/* RMT_CH2_TX_END_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch2_rx_end_int_raw..*/ +#define RMT_CH2_TX_END_INT_CLR (BIT(6)) +#define RMT_CH2_TX_END_INT_CLR_M (BIT(6)) +#define RMT_CH2_TX_END_INT_CLR_V 0x1 +#define RMT_CH2_TX_END_INT_CLR_S 6 +/* RMT_CH1_ERR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch1_err_int_raw.*/ +#define RMT_CH1_ERR_INT_CLR (BIT(5)) +#define RMT_CH1_ERR_INT_CLR_M (BIT(5)) +#define RMT_CH1_ERR_INT_CLR_V 0x1 +#define RMT_CH1_ERR_INT_CLR_S 5 +/* RMT_CH1_RX_END_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch1_tx_end_int_raw.*/ +#define RMT_CH1_RX_END_INT_CLR (BIT(4)) +#define RMT_CH1_RX_END_INT_CLR_M (BIT(4)) +#define RMT_CH1_RX_END_INT_CLR_V 0x1 +#define RMT_CH1_RX_END_INT_CLR_S 4 +/* RMT_CH1_TX_END_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch1_rx_end_int_raw..*/ +#define RMT_CH1_TX_END_INT_CLR (BIT(3)) +#define RMT_CH1_TX_END_INT_CLR_M (BIT(3)) +#define RMT_CH1_TX_END_INT_CLR_V 0x1 +#define RMT_CH1_TX_END_INT_CLR_S 3 +/* RMT_CH0_ERR_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch0_err_int_raw.*/ +#define RMT_CH0_ERR_INT_CLR (BIT(2)) +#define RMT_CH0_ERR_INT_CLR_M (BIT(2)) +#define RMT_CH0_ERR_INT_CLR_V 0x1 +#define RMT_CH0_ERR_INT_CLR_S 2 +/* RMT_CH0_RX_END_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch0_tx_end_int_raw.*/ +#define RMT_CH0_RX_END_INT_CLR (BIT(1)) +#define RMT_CH0_RX_END_INT_CLR_M (BIT(1)) +#define RMT_CH0_RX_END_INT_CLR_V 0x1 +#define RMT_CH0_RX_END_INT_CLR_S 1 +/* RMT_CH0_TX_END_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch0_rx_end_int_raw..*/ +#define RMT_CH0_TX_END_INT_CLR (BIT(0)) +#define RMT_CH0_TX_END_INT_CLR_M (BIT(0)) +#define RMT_CH0_TX_END_INT_CLR_V 0x1 +#define RMT_CH0_TX_END_INT_CLR_S 0 + +#define RMT_CH0CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00b0) +/* RMT_CARRIER_HIGH_CH0 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's high level value for channel0.*/ +#define RMT_CARRIER_HIGH_CH0 0x0000FFFF +#define RMT_CARRIER_HIGH_CH0_M ((RMT_CARRIER_HIGH_CH0_V)<<(RMT_CARRIER_HIGH_CH0_S)) +#define RMT_CARRIER_HIGH_CH0_V 0xFFFF +#define RMT_CARRIER_HIGH_CH0_S 16 +/* RMT_CARRIER_LOW_CH0 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's low level value for channel0.*/ +#define RMT_CARRIER_LOW_CH0 0x0000FFFF +#define RMT_CARRIER_LOW_CH0_M ((RMT_CARRIER_LOW_CH0_V)<<(RMT_CARRIER_LOW_CH0_S)) +#define RMT_CARRIER_LOW_CH0_V 0xFFFF +#define RMT_CARRIER_LOW_CH0_S 0 + +#define RMT_CH1CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00b4) +/* RMT_CARRIER_HIGH_CH1 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's high level value for channel1.*/ +#define RMT_CARRIER_HIGH_CH1 0x0000FFFF +#define RMT_CARRIER_HIGH_CH1_M ((RMT_CARRIER_HIGH_CH1_V)<<(RMT_CARRIER_HIGH_CH1_S)) +#define RMT_CARRIER_HIGH_CH1_V 0xFFFF +#define RMT_CARRIER_HIGH_CH1_S 16 +/* RMT_CARRIER_LOW_CH1 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's low level value for channel1.*/ +#define RMT_CARRIER_LOW_CH1 0x0000FFFF +#define RMT_CARRIER_LOW_CH1_M ((RMT_CARRIER_LOW_CH1_V)<<(RMT_CARRIER_LOW_CH1_S)) +#define RMT_CARRIER_LOW_CH1_V 0xFFFF +#define RMT_CARRIER_LOW_CH1_S 0 + +#define RMT_CH2CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00b8) +/* RMT_CARRIER_HIGH_CH2 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's high level value for channel2.*/ +#define RMT_CARRIER_HIGH_CH2 0x0000FFFF +#define RMT_CARRIER_HIGH_CH2_M ((RMT_CARRIER_HIGH_CH2_V)<<(RMT_CARRIER_HIGH_CH2_S)) +#define RMT_CARRIER_HIGH_CH2_V 0xFFFF +#define RMT_CARRIER_HIGH_CH2_S 16 +/* RMT_CARRIER_LOW_CH2 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's low level value for channel2.*/ +#define RMT_CARRIER_LOW_CH2 0x0000FFFF +#define RMT_CARRIER_LOW_CH2_M ((RMT_CARRIER_LOW_CH2_V)<<(RMT_CARRIER_LOW_CH2_S)) +#define RMT_CARRIER_LOW_CH2_V 0xFFFF +#define RMT_CARRIER_LOW_CH2_S 0 + +#define RMT_CH3CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00bc) +/* RMT_CARRIER_HIGH_CH3 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's high level value for channel3.*/ +#define RMT_CARRIER_HIGH_CH3 0x0000FFFF +#define RMT_CARRIER_HIGH_CH3_M ((RMT_CARRIER_HIGH_CH3_V)<<(RMT_CARRIER_HIGH_CH3_S)) +#define RMT_CARRIER_HIGH_CH3_V 0xFFFF +#define RMT_CARRIER_HIGH_CH3_S 16 +/* RMT_CARRIER_LOW_CH3 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's low level value for channel3.*/ +#define RMT_CARRIER_LOW_CH3 0x0000FFFF +#define RMT_CARRIER_LOW_CH3_M ((RMT_CARRIER_LOW_CH3_V)<<(RMT_CARRIER_LOW_CH3_S)) +#define RMT_CARRIER_LOW_CH3_V 0xFFFF +#define RMT_CARRIER_LOW_CH3_S 0 + +#define RMT_CH4CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00c0) +/* RMT_CARRIER_HIGH_CH4 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's high level value for channel4.*/ +#define RMT_CARRIER_HIGH_CH4 0x0000FFFF +#define RMT_CARRIER_HIGH_CH4_M ((RMT_CARRIER_HIGH_CH4_V)<<(RMT_CARRIER_HIGH_CH4_S)) +#define RMT_CARRIER_HIGH_CH4_V 0xFFFF +#define RMT_CARRIER_HIGH_CH4_S 16 +/* RMT_CARRIER_LOW_CH4 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's low level value for channel4.*/ +#define RMT_CARRIER_LOW_CH4 0x0000FFFF +#define RMT_CARRIER_LOW_CH4_M ((RMT_CARRIER_LOW_CH4_V)<<(RMT_CARRIER_LOW_CH4_S)) +#define RMT_CARRIER_LOW_CH4_V 0xFFFF +#define RMT_CARRIER_LOW_CH4_S 0 + +#define RMT_CH5CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00c4) +/* RMT_CARRIER_HIGH_CH5 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's high level value for channel5.*/ +#define RMT_CARRIER_HIGH_CH5 0x0000FFFF +#define RMT_CARRIER_HIGH_CH5_M ((RMT_CARRIER_HIGH_CH5_V)<<(RMT_CARRIER_HIGH_CH5_S)) +#define RMT_CARRIER_HIGH_CH5_V 0xFFFF +#define RMT_CARRIER_HIGH_CH5_S 16 +/* RMT_CARRIER_LOW_CH5 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's low level value for channel5.*/ +#define RMT_CARRIER_LOW_CH5 0x0000FFFF +#define RMT_CARRIER_LOW_CH5_M ((RMT_CARRIER_LOW_CH5_V)<<(RMT_CARRIER_LOW_CH5_S)) +#define RMT_CARRIER_LOW_CH5_V 0xFFFF +#define RMT_CARRIER_LOW_CH5_S 0 + +#define RMT_CH6CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00c8) +/* RMT_CARRIER_HIGH_CH6 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's high level value for channel6.*/ +#define RMT_CARRIER_HIGH_CH6 0x0000FFFF +#define RMT_CARRIER_HIGH_CH6_M ((RMT_CARRIER_HIGH_CH6_V)<<(RMT_CARRIER_HIGH_CH6_S)) +#define RMT_CARRIER_HIGH_CH6_V 0xFFFF +#define RMT_CARRIER_HIGH_CH6_S 16 +/* RMT_CARRIER_LOW_CH6 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's low level value for channel6.*/ +#define RMT_CARRIER_LOW_CH6 0x0000FFFF +#define RMT_CARRIER_LOW_CH6_M ((RMT_CARRIER_LOW_CH6_V)<<(RMT_CARRIER_LOW_CH6_S)) +#define RMT_CARRIER_LOW_CH6_V 0xFFFF +#define RMT_CARRIER_LOW_CH6_S 0 + +#define RMT_CH7CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00cc) +/* RMT_CARRIER_HIGH_CH7 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's high level value for channel7.*/ +#define RMT_CARRIER_HIGH_CH7 0x0000FFFF +#define RMT_CARRIER_HIGH_CH7_M ((RMT_CARRIER_HIGH_CH7_V)<<(RMT_CARRIER_HIGH_CH7_S)) +#define RMT_CARRIER_HIGH_CH7_V 0xFFFF +#define RMT_CARRIER_HIGH_CH7_S 16 +/* RMT_CARRIER_LOW_CH7 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's low level value for channel7.*/ +#define RMT_CARRIER_LOW_CH7 0x0000FFFF +#define RMT_CARRIER_LOW_CH7_M ((RMT_CARRIER_LOW_CH7_V)<<(RMT_CARRIER_LOW_CH7_S)) +#define RMT_CARRIER_LOW_CH7_V 0xFFFF +#define RMT_CARRIER_LOW_CH7_S 0 + +#define RMT_CH0_TX_LIM_REG (DR_REG_RMT_BASE + 0x00d0) +/* RMT_TX_LIM_CH0 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: When channel0 sends more than reg_rmt_tx_lim_ch0 datas then channel0 + produce the relative interrupt.*/ +#define RMT_TX_LIM_CH0 0x000001FF +#define RMT_TX_LIM_CH0_M ((RMT_TX_LIM_CH0_V)<<(RMT_TX_LIM_CH0_S)) +#define RMT_TX_LIM_CH0_V 0x1FF +#define RMT_TX_LIM_CH0_S 0 + +#define RMT_CH1_TX_LIM_REG (DR_REG_RMT_BASE + 0x00d4) +/* RMT_TX_LIM_CH1 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: When channel1 sends more than reg_rmt_tx_lim_ch1 datas then channel1 + produce the relative interrupt.*/ +#define RMT_TX_LIM_CH1 0x000001FF +#define RMT_TX_LIM_CH1_M ((RMT_TX_LIM_CH1_V)<<(RMT_TX_LIM_CH1_S)) +#define RMT_TX_LIM_CH1_V 0x1FF +#define RMT_TX_LIM_CH1_S 0 + +#define RMT_CH2_TX_LIM_REG (DR_REG_RMT_BASE + 0x00d8) +/* RMT_TX_LIM_CH2 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: When channel2 sends more than reg_rmt_tx_lim_ch2 datas then channel2 + produce the relative interrupt.*/ +#define RMT_TX_LIM_CH2 0x000001FF +#define RMT_TX_LIM_CH2_M ((RMT_TX_LIM_CH2_V)<<(RMT_TX_LIM_CH2_S)) +#define RMT_TX_LIM_CH2_V 0x1FF +#define RMT_TX_LIM_CH2_S 0 + +#define RMT_CH3_TX_LIM_REG (DR_REG_RMT_BASE + 0x00dc) +/* RMT_TX_LIM_CH3 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: When channel3 sends more than reg_rmt_tx_lim_ch3 datas then channel3 + produce the relative interrupt.*/ +#define RMT_TX_LIM_CH3 0x000001FF +#define RMT_TX_LIM_CH3_M ((RMT_TX_LIM_CH3_V)<<(RMT_TX_LIM_CH3_S)) +#define RMT_TX_LIM_CH3_V 0x1FF +#define RMT_TX_LIM_CH3_S 0 + +#define RMT_CH4_TX_LIM_REG (DR_REG_RMT_BASE + 0x00e0) +/* RMT_TX_LIM_CH4 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: When channel4 sends more than reg_rmt_tx_lim_ch4 datas then channel4 + produce the relative interrupt.*/ +#define RMT_TX_LIM_CH4 0x000001FF +#define RMT_TX_LIM_CH4_M ((RMT_TX_LIM_CH4_V)<<(RMT_TX_LIM_CH4_S)) +#define RMT_TX_LIM_CH4_V 0x1FF +#define RMT_TX_LIM_CH4_S 0 + +#define RMT_CH5_TX_LIM_REG (DR_REG_RMT_BASE + 0x00e4) +/* RMT_TX_LIM_CH5 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: When channel5 sends more than reg_rmt_tx_lim_ch5 datas then channel5 + produce the relative interrupt.*/ +#define RMT_TX_LIM_CH5 0x000001FF +#define RMT_TX_LIM_CH5_M ((RMT_TX_LIM_CH5_V)<<(RMT_TX_LIM_CH5_S)) +#define RMT_TX_LIM_CH5_V 0x1FF +#define RMT_TX_LIM_CH5_S 0 + +#define RMT_CH6_TX_LIM_REG (DR_REG_RMT_BASE + 0x00e8) +/* RMT_TX_LIM_CH6 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: When channel6 sends more than reg_rmt_tx_lim_ch6 datas then channel6 + produce the relative interrupt.*/ +#define RMT_TX_LIM_CH6 0x000001FF +#define RMT_TX_LIM_CH6_M ((RMT_TX_LIM_CH6_V)<<(RMT_TX_LIM_CH6_S)) +#define RMT_TX_LIM_CH6_V 0x1FF +#define RMT_TX_LIM_CH6_S 0 + +#define RMT_CH7_TX_LIM_REG (DR_REG_RMT_BASE + 0x00ec) +/* RMT_TX_LIM_CH7 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: When channel7 sends more than reg_rmt_tx_lim_ch7 datas then channel7 + produce the relative interrupt.*/ +#define RMT_TX_LIM_CH7 0x000001FF +#define RMT_TX_LIM_CH7_M ((RMT_TX_LIM_CH7_V)<<(RMT_TX_LIM_CH7_S)) +#define RMT_TX_LIM_CH7_V 0x1FF +#define RMT_TX_LIM_CH7_S 0 + +#define RMT_APB_CONF_REG (DR_REG_RMT_BASE + 0x00f0) +/* RMT_MEM_TX_WRAP_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: when datas need to be send is more than channel's mem can store + then set this bit to enable reusage of mem this bit is used together with reg_rmt_tx_lim_chn.*/ +#define RMT_MEM_TX_WRAP_EN (BIT(1)) +#define RMT_MEM_TX_WRAP_EN_M (BIT(1)) +#define RMT_MEM_TX_WRAP_EN_V 0x1 +#define RMT_MEM_TX_WRAP_EN_S 1 +/* RMT_APB_FIFO_MASK : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to disable apb fifo access*/ +#define RMT_APB_FIFO_MASK (BIT(0)) +#define RMT_APB_FIFO_MASK_M (BIT(0)) +#define RMT_APB_FIFO_MASK_V 0x1 +#define RMT_APB_FIFO_MASK_S 0 + +#define RMT_DATE_REG (DR_REG_RMT_BASE + 0x00fc) +/* RMT_DATE : R/W ;bitpos:[31:0] ;default: 32'h16022600 ; */ +/*description: This is the version register.*/ +#define RMT_DATE 0xFFFFFFFF +#define RMT_DATE_M ((RMT_DATE_V)<<(RMT_DATE_S)) +#define RMT_DATE_V 0xFFFFFFFF +#define RMT_DATE_S 0 + + + + +#endif /*_SOC_RMT_REG_H_ */ + + diff --git a/tools/sdk/include/esp32/soc/rmt_struct.h b/tools/sdk/include/esp32/soc/rmt_struct.h new file mode 100644 index 00000000..15beb8c6 --- /dev/null +++ b/tools/sdk/include/esp32/soc/rmt_struct.h @@ -0,0 +1,228 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_RMT_STRUCT_H_ +#define _SOC_RMT_STRUCT_H_ +typedef volatile struct { + uint32_t data_ch[8]; /*The R/W ram address for channel0-7 by apb fifo access.*/ + struct{ + union { + struct { + uint32_t div_cnt: 8; /*This register is used to configure the frequency divider's factor in channel0-7.*/ + uint32_t idle_thres: 16; /*In receive mode when no edge is detected on the input signal for longer than reg_idle_thres_ch0 then the receive process is done.*/ + uint32_t mem_size: 4; /*This register is used to configure the the amount of memory blocks allocated to channel0-7.*/ + uint32_t carrier_en: 1; /*This is the carrier modulation enable control bit for channel0-7.*/ + uint32_t carrier_out_lv: 1; /*This bit is used to configure the way carrier wave is modulated for channel0-7.1'b1:transmit on low output level 1'b0:transmit on high output level.*/ + uint32_t mem_pd: 1; /*This bit is used to reduce power consumed by memory. 1:memory is in low power state.*/ + uint32_t clk_en: 1; /*This bit is used to control clock.when software configure RMT internal registers it controls the register clock.*/ + }; + uint32_t val; + } conf0; + union { + struct { + uint32_t tx_start: 1; /*Set this bit to start sending data for channel0-7.*/ + uint32_t rx_en: 1; /*Set this bit to enable receiving data for channel0-7.*/ + uint32_t mem_wr_rst: 1; /*Set this bit to reset write ram address for channel0-7 by receiver access.*/ + uint32_t mem_rd_rst: 1; /*Set this bit to reset read ram address for channel0-7 by transmitter access.*/ + uint32_t apb_mem_rst: 1; /*Set this bit to reset W/R ram address for channel0-7 by apb fifo access*/ + uint32_t mem_owner: 1; /*This is the mark of channel0-7's ram usage right.1'b1：receiver uses the ram 0：transmitter uses the ram*/ + uint32_t tx_conti_mode: 1; /*Set this bit to continue sending from the first data to the last data in channel0-7 again and again.*/ + uint32_t rx_filter_en: 1; /*This is the receive filter enable bit for channel0-7.*/ + uint32_t rx_filter_thres: 8; /*in receive mode channel0-7 ignore input pulse when the pulse width is smaller then this value.*/ + uint32_t ref_cnt_rst: 1; /*This bit is used to reset divider in channel0-7.*/ + uint32_t ref_always_on: 1; /*This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ + uint32_t idle_out_lv: 1; /*This bit configures the output signal's level for channel0-7 in IDLE state.*/ + uint32_t idle_out_en: 1; /*This is the output enable control bit for channel0-7 in IDLE state.*/ + uint32_t reserved20: 12; + }; + uint32_t val; + } conf1; + } conf_ch[8]; + uint32_t status_ch[8]; /*The status for channel0-7*/ + uint32_t apb_mem_addr_ch[8]; /*The ram relative address in channel0-7 by apb fifo access*/ + union { + struct { + uint32_t ch0_tx_end: 1; /*The interrupt raw bit for channel 0 turns to high level when the transmit process is done.*/ + uint32_t ch0_rx_end: 1; /*The interrupt raw bit for channel 0 turns to high level when the receive process is done.*/ + uint32_t ch0_err: 1; /*The interrupt raw bit for channel 0 turns to high level when channel 0 detects some errors.*/ + uint32_t ch1_tx_end: 1; /*The interrupt raw bit for channel 1 turns to high level when the transmit process is done.*/ + uint32_t ch1_rx_end: 1; /*The interrupt raw bit for channel 1 turns to high level when the receive process is done.*/ + uint32_t ch1_err: 1; /*The interrupt raw bit for channel 1 turns to high level when channel 1 detects some errors.*/ + uint32_t ch2_tx_end: 1; /*The interrupt raw bit for channel 2 turns to high level when the transmit process is done.*/ + uint32_t ch2_rx_end: 1; /*The interrupt raw bit for channel 2 turns to high level when the receive process is done.*/ + uint32_t ch2_err: 1; /*The interrupt raw bit for channel 2 turns to high level when channel 2 detects some errors.*/ + uint32_t ch3_tx_end: 1; /*The interrupt raw bit for channel 3 turns to high level when the transmit process is done.*/ + uint32_t ch3_rx_end: 1; /*The interrupt raw bit for channel 3 turns to high level when the receive process is done.*/ + uint32_t ch3_err: 1; /*The interrupt raw bit for channel 3 turns to high level when channel 3 detects some errors.*/ + uint32_t ch4_tx_end: 1; /*The interrupt raw bit for channel 4 turns to high level when the transmit process is done.*/ + uint32_t ch4_rx_end: 1; /*The interrupt raw bit for channel 4 turns to high level when the receive process is done.*/ + uint32_t ch4_err: 1; /*The interrupt raw bit for channel 4 turns to high level when channel 4 detects some errors.*/ + uint32_t ch5_tx_end: 1; /*The interrupt raw bit for channel 5 turns to high level when the transmit process is done.*/ + uint32_t ch5_rx_end: 1; /*The interrupt raw bit for channel 5 turns to high level when the receive process is done.*/ + uint32_t ch5_err: 1; /*The interrupt raw bit for channel 5 turns to high level when channel 5 detects some errors.*/ + uint32_t ch6_tx_end: 1; /*The interrupt raw bit for channel 6 turns to high level when the transmit process is done.*/ + uint32_t ch6_rx_end: 1; /*The interrupt raw bit for channel 6 turns to high level when the receive process is done.*/ + uint32_t ch6_err: 1; /*The interrupt raw bit for channel 6 turns to high level when channel 6 detects some errors.*/ + uint32_t ch7_tx_end: 1; /*The interrupt raw bit for channel 7 turns to high level when the transmit process is done.*/ + uint32_t ch7_rx_end: 1; /*The interrupt raw bit for channel 7 turns to high level when the receive process is done.*/ + uint32_t ch7_err: 1; /*The interrupt raw bit for channel 7 turns to high level when channel 7 detects some errors.*/ + uint32_t ch0_tx_thr_event: 1; /*The interrupt raw bit for channel 0 turns to high level when transmitter in channel0 have send data more than reg_rmt_tx_lim_ch0 after detecting this interrupt software can updata the old data with new data.*/ + uint32_t ch1_tx_thr_event: 1; /*The interrupt raw bit for channel 1 turns to high level when transmitter in channel1 have send data more than reg_rmt_tx_lim_ch1 after detecting this interrupt software can updata the old data with new data.*/ + uint32_t ch2_tx_thr_event: 1; /*The interrupt raw bit for channel 2 turns to high level when transmitter in channel2 have send data more than reg_rmt_tx_lim_ch2 after detecting this interrupt software can updata the old data with new data.*/ + uint32_t ch3_tx_thr_event: 1; /*The interrupt raw bit for channel 3 turns to high level when transmitter in channel3 have send data more than reg_rmt_tx_lim_ch3 after detecting this interrupt software can updata the old data with new data.*/ + uint32_t ch4_tx_thr_event: 1; /*The interrupt raw bit for channel 4 turns to high level when transmitter in channel4 have send data more than reg_rmt_tx_lim_ch4 after detecting this interrupt software can updata the old data with new data.*/ + uint32_t ch5_tx_thr_event: 1; /*The interrupt raw bit for channel 5 turns to high level when transmitter in channel5 have send data more than reg_rmt_tx_lim_ch5 after detecting this interrupt software can updata the old data with new data.*/ + uint32_t ch6_tx_thr_event: 1; /*The interrupt raw bit for channel 6 turns to high level when transmitter in channel6 have send data more than reg_rmt_tx_lim_ch6 after detecting this interrupt software can updata the old data with new data.*/ + uint32_t ch7_tx_thr_event: 1; /*The interrupt raw bit for channel 7 turns to high level when transmitter in channel7 have send data more than reg_rmt_tx_lim_ch7 after detecting this interrupt software can updata the old data with new data.*/ + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t ch0_tx_end: 1; /*The interrupt state bit for channel 0's mt_ch0_tx_end_int_raw when mt_ch0_tx_end_int_ena is set to 0.*/ + uint32_t ch0_rx_end: 1; /*The interrupt state bit for channel 0's rmt_ch0_rx_end_int_raw when rmt_ch0_rx_end_int_ena is set to 0.*/ + uint32_t ch0_err: 1; /*The interrupt state bit for channel 0's rmt_ch0_err_int_raw when rmt_ch0_err_int_ena is set to 0.*/ + uint32_t ch1_tx_end: 1; /*The interrupt state bit for channel 1's mt_ch1_tx_end_int_raw when mt_ch1_tx_end_int_ena is set to 1.*/ + uint32_t ch1_rx_end: 1; /*The interrupt state bit for channel 1's rmt_ch1_rx_end_int_raw when rmt_ch1_rx_end_int_ena is set to 1.*/ + uint32_t ch1_err: 1; /*The interrupt state bit for channel 1's rmt_ch1_err_int_raw when rmt_ch1_err_int_ena is set to 1.*/ + uint32_t ch2_tx_end: 1; /*The interrupt state bit for channel 2's mt_ch2_tx_end_int_raw when mt_ch2_tx_end_int_ena is set to 1.*/ + uint32_t ch2_rx_end: 1; /*The interrupt state bit for channel 2's rmt_ch2_rx_end_int_raw when rmt_ch2_rx_end_int_ena is set to 1.*/ + uint32_t ch2_err: 1; /*The interrupt state bit for channel 2's rmt_ch2_err_int_raw when rmt_ch2_err_int_ena is set to 1.*/ + uint32_t ch3_tx_end: 1; /*The interrupt state bit for channel 3's mt_ch3_tx_end_int_raw when mt_ch3_tx_end_int_ena is set to 1.*/ + uint32_t ch3_rx_end: 1; /*The interrupt state bit for channel 3's rmt_ch3_rx_end_int_raw when rmt_ch3_rx_end_int_ena is set to 1.*/ + uint32_t ch3_err: 1; /*The interrupt state bit for channel 3's rmt_ch3_err_int_raw when rmt_ch3_err_int_ena is set to 1.*/ + uint32_t ch4_tx_end: 1; /*The interrupt state bit for channel 4's mt_ch4_tx_end_int_raw when mt_ch4_tx_end_int_ena is set to 1.*/ + uint32_t ch4_rx_end: 1; /*The interrupt state bit for channel 4's rmt_ch4_rx_end_int_raw when rmt_ch4_rx_end_int_ena is set to 1.*/ + uint32_t ch4_err: 1; /*The interrupt state bit for channel 4's rmt_ch4_err_int_raw when rmt_ch4_err_int_ena is set to 1.*/ + uint32_t ch5_tx_end: 1; /*The interrupt state bit for channel 5's mt_ch5_tx_end_int_raw when mt_ch5_tx_end_int_ena is set to 1.*/ + uint32_t ch5_rx_end: 1; /*The interrupt state bit for channel 5's rmt_ch5_rx_end_int_raw when rmt_ch5_rx_end_int_ena is set to 1.*/ + uint32_t ch5_err: 1; /*The interrupt state bit for channel 5's rmt_ch5_err_int_raw when rmt_ch5_err_int_ena is set to 1.*/ + uint32_t ch6_tx_end: 1; /*The interrupt state bit for channel 6's mt_ch6_tx_end_int_raw when mt_ch6_tx_end_int_ena is set to 1.*/ + uint32_t ch6_rx_end: 1; /*The interrupt state bit for channel 6's rmt_ch6_rx_end_int_raw when rmt_ch6_rx_end_int_ena is set to 1.*/ + uint32_t ch6_err: 1; /*The interrupt state bit for channel 6's rmt_ch6_err_int_raw when rmt_ch6_err_int_ena is set to 1.*/ + uint32_t ch7_tx_end: 1; /*The interrupt state bit for channel 7's mt_ch7_tx_end_int_raw when mt_ch7_tx_end_int_ena is set to 1.*/ + uint32_t ch7_rx_end: 1; /*The interrupt state bit for channel 7's rmt_ch7_rx_end_int_raw when rmt_ch7_rx_end_int_ena is set to 1.*/ + uint32_t ch7_err: 1; /*The interrupt state bit for channel 7's rmt_ch7_err_int_raw when rmt_ch7_err_int_ena is set to 1.*/ + uint32_t ch0_tx_thr_event: 1; /*The interrupt state bit for channel 0's rmt_ch0_tx_thr_event_int_raw when mt_ch0_tx_thr_event_int_ena is set to 1.*/ + uint32_t ch1_tx_thr_event: 1; /*The interrupt state bit for channel 1's rmt_ch1_tx_thr_event_int_raw when mt_ch1_tx_thr_event_int_ena is set to 1.*/ + uint32_t ch2_tx_thr_event: 1; /*The interrupt state bit for channel 2's rmt_ch2_tx_thr_event_int_raw when mt_ch2_tx_thr_event_int_ena is set to 1.*/ + uint32_t ch3_tx_thr_event: 1; /*The interrupt state bit for channel 3's rmt_ch3_tx_thr_event_int_raw when mt_ch3_tx_thr_event_int_ena is set to 1.*/ + uint32_t ch4_tx_thr_event: 1; /*The interrupt state bit for channel 4's rmt_ch4_tx_thr_event_int_raw when mt_ch4_tx_thr_event_int_ena is set to 1.*/ + uint32_t ch5_tx_thr_event: 1; /*The interrupt state bit for channel 5's rmt_ch5_tx_thr_event_int_raw when mt_ch5_tx_thr_event_int_ena is set to 1.*/ + uint32_t ch6_tx_thr_event: 1; /*The interrupt state bit for channel 6's rmt_ch6_tx_thr_event_int_raw when mt_ch6_tx_thr_event_int_ena is set to 1.*/ + uint32_t ch7_tx_thr_event: 1; /*The interrupt state bit for channel 7's rmt_ch7_tx_thr_event_int_raw when mt_ch7_tx_thr_event_int_ena is set to 1.*/ + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t ch0_tx_end: 1; /*Set this bit to enable rmt_ch0_tx_end_int_st.*/ + uint32_t ch0_rx_end: 1; /*Set this bit to enable rmt_ch0_rx_end_int_st.*/ + uint32_t ch0_err: 1; /*Set this bit to enable rmt_ch0_err_int_st.*/ + uint32_t ch1_tx_end: 1; /*Set this bit to enable rmt_ch1_tx_end_int_st.*/ + uint32_t ch1_rx_end: 1; /*Set this bit to enable rmt_ch1_rx_end_int_st.*/ + uint32_t ch1_err: 1; /*Set this bit to enable rmt_ch1_err_int_st.*/ + uint32_t ch2_tx_end: 1; /*Set this bit to enable rmt_ch2_tx_end_int_st.*/ + uint32_t ch2_rx_end: 1; /*Set this bit to enable rmt_ch2_rx_end_int_st.*/ + uint32_t ch2_err: 1; /*Set this bit to enable rmt_ch2_err_int_st.*/ + uint32_t ch3_tx_end: 1; /*Set this bit to enable rmt_ch3_tx_end_int_st.*/ + uint32_t ch3_rx_end: 1; /*Set this bit to enable rmt_ch3_rx_end_int_st.*/ + uint32_t ch3_err: 1; /*Set this bit to enable rmt_ch3_err_int_st.*/ + uint32_t ch4_tx_end: 1; /*Set this bit to enable rmt_ch4_tx_end_int_st.*/ + uint32_t ch4_rx_end: 1; /*Set this bit to enable rmt_ch4_rx_end_int_st.*/ + uint32_t ch4_err: 1; /*Set this bit to enable rmt_ch4_err_int_st.*/ + uint32_t ch5_tx_end: 1; /*Set this bit to enable rmt_ch5_tx_end_int_st.*/ + uint32_t ch5_rx_end: 1; /*Set this bit to enable rmt_ch5_rx_end_int_st.*/ + uint32_t ch5_err: 1; /*Set this bit to enable rmt_ch5_err_int_st.*/ + uint32_t ch6_tx_end: 1; /*Set this bit to enable rmt_ch6_tx_end_int_st.*/ + uint32_t ch6_rx_end: 1; /*Set this bit to enable rmt_ch6_rx_end_int_st.*/ + uint32_t ch6_err: 1; /*Set this bit to enable rmt_ch6_err_int_st.*/ + uint32_t ch7_tx_end: 1; /*Set this bit to enable rmt_ch7_tx_end_int_st.*/ + uint32_t ch7_rx_end: 1; /*Set this bit to enable rmt_ch7_rx_end_int_st.*/ + uint32_t ch7_err: 1; /*Set this bit to enable rmt_ch7_err_int_st.*/ + uint32_t ch0_tx_thr_event: 1; /*Set this bit to enable rmt_ch0_tx_thr_event_int_st.*/ + uint32_t ch1_tx_thr_event: 1; /*Set this bit to enable rmt_ch1_tx_thr_event_int_st.*/ + uint32_t ch2_tx_thr_event: 1; /*Set this bit to enable rmt_ch2_tx_thr_event_int_st.*/ + uint32_t ch3_tx_thr_event: 1; /*Set this bit to enable rmt_ch3_tx_thr_event_int_st.*/ + uint32_t ch4_tx_thr_event: 1; /*Set this bit to enable rmt_ch4_tx_thr_event_int_st.*/ + uint32_t ch5_tx_thr_event: 1; /*Set this bit to enable rmt_ch5_tx_thr_event_int_st.*/ + uint32_t ch6_tx_thr_event: 1; /*Set this bit to enable rmt_ch6_tx_thr_event_int_st.*/ + uint32_t ch7_tx_thr_event: 1; /*Set this bit to enable rmt_ch7_tx_thr_event_int_st.*/ + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t ch0_tx_end: 1; /*Set this bit to clear the rmt_ch0_rx_end_int_raw..*/ + uint32_t ch0_rx_end: 1; /*Set this bit to clear the rmt_ch0_tx_end_int_raw.*/ + uint32_t ch0_err: 1; /*Set this bit to clear the rmt_ch0_err_int_raw.*/ + uint32_t ch1_tx_end: 1; /*Set this bit to clear the rmt_ch1_rx_end_int_raw..*/ + uint32_t ch1_rx_end: 1; /*Set this bit to clear the rmt_ch1_tx_end_int_raw.*/ + uint32_t ch1_err: 1; /*Set this bit to clear the rmt_ch1_err_int_raw.*/ + uint32_t ch2_tx_end: 1; /*Set this bit to clear the rmt_ch2_rx_end_int_raw..*/ + uint32_t ch2_rx_end: 1; /*Set this bit to clear the rmt_ch2_tx_end_int_raw.*/ + uint32_t ch2_err: 1; /*Set this bit to clear the rmt_ch2_err_int_raw.*/ + uint32_t ch3_tx_end: 1; /*Set this bit to clear the rmt_ch3_rx_end_int_raw..*/ + uint32_t ch3_rx_end: 1; /*Set this bit to clear the rmt_ch3_tx_end_int_raw.*/ + uint32_t ch3_err: 1; /*Set this bit to clear the rmt_ch3_err_int_raw.*/ + uint32_t ch4_tx_end: 1; /*Set this bit to clear the rmt_ch4_rx_end_int_raw..*/ + uint32_t ch4_rx_end: 1; /*Set this bit to clear the rmt_ch4_tx_end_int_raw.*/ + uint32_t ch4_err: 1; /*Set this bit to clear the rmt_ch4_err_int_raw.*/ + uint32_t ch5_tx_end: 1; /*Set this bit to clear the rmt_ch5_rx_end_int_raw..*/ + uint32_t ch5_rx_end: 1; /*Set this bit to clear the rmt_ch5_tx_end_int_raw.*/ + uint32_t ch5_err: 1; /*Set this bit to clear the rmt_ch5_err_int_raw.*/ + uint32_t ch6_tx_end: 1; /*Set this bit to clear the rmt_ch6_rx_end_int_raw..*/ + uint32_t ch6_rx_end: 1; /*Set this bit to clear the rmt_ch6_tx_end_int_raw.*/ + uint32_t ch6_err: 1; /*Set this bit to clear the rmt_ch6_err_int_raw.*/ + uint32_t ch7_tx_end: 1; /*Set this bit to clear the rmt_ch7_rx_end_int_raw..*/ + uint32_t ch7_rx_end: 1; /*Set this bit to clear the rmt_ch7_tx_end_int_raw.*/ + uint32_t ch7_err: 1; /*Set this bit to clear the rmt_ch7_err_int_raw.*/ + uint32_t ch0_tx_thr_event: 1; /*Set this bit to clear the rmt_ch0_tx_thr_event_int_raw interrupt.*/ + uint32_t ch1_tx_thr_event: 1; /*Set this bit to clear the rmt_ch1_tx_thr_event_int_raw interrupt.*/ + uint32_t ch2_tx_thr_event: 1; /*Set this bit to clear the rmt_ch2_tx_thr_event_int_raw interrupt.*/ + uint32_t ch3_tx_thr_event: 1; /*Set this bit to clear the rmt_ch3_tx_thr_event_int_raw interrupt.*/ + uint32_t ch4_tx_thr_event: 1; /*Set this bit to clear the rmt_ch4_tx_thr_event_int_raw interrupt.*/ + uint32_t ch5_tx_thr_event: 1; /*Set this bit to clear the rmt_ch5_tx_thr_event_int_raw interrupt.*/ + uint32_t ch6_tx_thr_event: 1; /*Set this bit to clear the rmt_ch6_tx_thr_event_int_raw interrupt.*/ + uint32_t ch7_tx_thr_event: 1; /*Set this bit to clear the rmt_ch7_tx_thr_event_int_raw interrupt.*/ + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t low: 16; /*This register is used to configure carrier wave's low level value for channel0-7.*/ + uint32_t high:16; /*This register is used to configure carrier wave's high level value for channel0-7.*/ + }; + uint32_t val; + } carrier_duty_ch[8]; + union { + struct { + uint32_t limit: 9; /*When channel0-7 sends more than reg_rmt_tx_lim_ch0 data then channel0-7 produce the relative interrupt.*/ + uint32_t reserved9: 23; + }; + uint32_t val; + } tx_lim_ch[8]; + union { + struct { + uint32_t fifo_mask: 1; /*Set this bit to disable apb fifo access*/ + uint32_t mem_tx_wrap_en: 1; /*when data need to be send is more than channel's mem can store then set this bit to enable reuse of mem this bit is used together with reg_rmt_tx_lim_chn.*/ + uint32_t reserved2: 30; + }; + uint32_t val; + } apb_conf; + uint32_t reserved_f4; + uint32_t reserved_f8; + uint32_t date; /*This is the version register.*/ +} rmt_dev_t; +extern rmt_dev_t RMT; +#endif /* _SOC_RMT_STRUCT_H_ */ diff --git a/tools/sdk/include/esp32/soc/rtc_cntl_reg.h b/tools/sdk/include/esp32/soc/rtc_cntl_reg.h new file mode 100644 index 00000000..47328611 --- /dev/null +++ b/tools/sdk/include/esp32/soc/rtc_cntl_reg.h @@ -0,0 +1,1988 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_RTC_CNTL_REG_H_ +#define _SOC_RTC_CNTL_REG_H_ + + +#include "soc.h" +#define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0) +/* RTC_CNTL_SW_SYS_RST : WO ;bitpos:[31] ;default: 1'd0 ; */ +/*description: SW system reset*/ +#define RTC_CNTL_SW_SYS_RST (BIT(31)) +#define RTC_CNTL_SW_SYS_RST_M (BIT(31)) +#define RTC_CNTL_SW_SYS_RST_V 0x1 +#define RTC_CNTL_SW_SYS_RST_S 31 +/* RTC_CNTL_DG_WRAP_FORCE_NORST : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: digital core force no reset in deep sleep*/ +#define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_NORST_M (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_NORST_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_NORST_S 30 +/* RTC_CNTL_DG_WRAP_FORCE_RST : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: digital wrap force reset in deep sleep*/ +#define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29)) +#define RTC_CNTL_DG_WRAP_FORCE_RST_M (BIT(29)) +#define RTC_CNTL_DG_WRAP_FORCE_RST_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_RST_S 29 +/* RTC_CNTL_ANALOG_FORCE_NOISO : R/W ;bitpos:[28] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28)) +#define RTC_CNTL_ANALOG_FORCE_NOISO_M (BIT(28)) +#define RTC_CNTL_ANALOG_FORCE_NOISO_V 0x1 +#define RTC_CNTL_ANALOG_FORCE_NOISO_S 28 +/* RTC_CNTL_PLL_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_PLL_FORCE_NOISO (BIT(27)) +#define RTC_CNTL_PLL_FORCE_NOISO_M (BIT(27)) +#define RTC_CNTL_PLL_FORCE_NOISO_V 0x1 +#define RTC_CNTL_PLL_FORCE_NOISO_S 27 +/* RTC_CNTL_XTL_FORCE_NOISO : R/W ;bitpos:[26] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_XTL_FORCE_NOISO (BIT(26)) +#define RTC_CNTL_XTL_FORCE_NOISO_M (BIT(26)) +#define RTC_CNTL_XTL_FORCE_NOISO_V 0x1 +#define RTC_CNTL_XTL_FORCE_NOISO_S 26 +/* RTC_CNTL_ANALOG_FORCE_ISO : R/W ;bitpos:[25] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_ANALOG_FORCE_ISO (BIT(25)) +#define RTC_CNTL_ANALOG_FORCE_ISO_M (BIT(25)) +#define RTC_CNTL_ANALOG_FORCE_ISO_V 0x1 +#define RTC_CNTL_ANALOG_FORCE_ISO_S 25 +/* RTC_CNTL_PLL_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_PLL_FORCE_ISO (BIT(24)) +#define RTC_CNTL_PLL_FORCE_ISO_M (BIT(24)) +#define RTC_CNTL_PLL_FORCE_ISO_V 0x1 +#define RTC_CNTL_PLL_FORCE_ISO_S 24 +/* RTC_CNTL_XTL_FORCE_ISO : R/W ;bitpos:[23] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_XTL_FORCE_ISO (BIT(23)) +#define RTC_CNTL_XTL_FORCE_ISO_M (BIT(23)) +#define RTC_CNTL_XTL_FORCE_ISO_V 0x1 +#define RTC_CNTL_XTL_FORCE_ISO_S 23 +/* RTC_CNTL_BIAS_CORE_FORCE_PU : R/W ;bitpos:[22] ;default: 1'd1 ; */ +/*description: BIAS_CORE force power up*/ +#define RTC_CNTL_BIAS_CORE_FORCE_PU (BIT(22)) +#define RTC_CNTL_BIAS_CORE_FORCE_PU_M (BIT(22)) +#define RTC_CNTL_BIAS_CORE_FORCE_PU_V 0x1 +#define RTC_CNTL_BIAS_CORE_FORCE_PU_S 22 +/* RTC_CNTL_BIAS_CORE_FORCE_PD : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: BIAS_CORE force power down*/ +#define RTC_CNTL_BIAS_CORE_FORCE_PD (BIT(21)) +#define RTC_CNTL_BIAS_CORE_FORCE_PD_M (BIT(21)) +#define RTC_CNTL_BIAS_CORE_FORCE_PD_V 0x1 +#define RTC_CNTL_BIAS_CORE_FORCE_PD_S 21 +/* RTC_CNTL_BIAS_CORE_FOLW_8M : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: BIAS_CORE follow CK8M*/ +#define RTC_CNTL_BIAS_CORE_FOLW_8M (BIT(20)) +#define RTC_CNTL_BIAS_CORE_FOLW_8M_M (BIT(20)) +#define RTC_CNTL_BIAS_CORE_FOLW_8M_V 0x1 +#define RTC_CNTL_BIAS_CORE_FOLW_8M_S 20 +/* RTC_CNTL_BIAS_I2C_FORCE_PU : R/W ;bitpos:[19] ;default: 1'd1 ; */ +/*description: BIAS_I2C force power up*/ +#define RTC_CNTL_BIAS_I2C_FORCE_PU (BIT(19)) +#define RTC_CNTL_BIAS_I2C_FORCE_PU_M (BIT(19)) +#define RTC_CNTL_BIAS_I2C_FORCE_PU_V 0x1 +#define RTC_CNTL_BIAS_I2C_FORCE_PU_S 19 +/* RTC_CNTL_BIAS_I2C_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: BIAS_I2C force power down*/ +#define RTC_CNTL_BIAS_I2C_FORCE_PD (BIT(18)) +#define RTC_CNTL_BIAS_I2C_FORCE_PD_M (BIT(18)) +#define RTC_CNTL_BIAS_I2C_FORCE_PD_V 0x1 +#define RTC_CNTL_BIAS_I2C_FORCE_PD_S 18 +/* RTC_CNTL_BIAS_I2C_FOLW_8M : R/W ;bitpos:[17] ;default: 1'd0 ; */ +/*description: BIAS_I2C follow CK8M*/ +#define RTC_CNTL_BIAS_I2C_FOLW_8M (BIT(17)) +#define RTC_CNTL_BIAS_I2C_FOLW_8M_M (BIT(17)) +#define RTC_CNTL_BIAS_I2C_FOLW_8M_V 0x1 +#define RTC_CNTL_BIAS_I2C_FOLW_8M_S 17 +/* RTC_CNTL_BIAS_FORCE_NOSLEEP : R/W ;bitpos:[16] ;default: 1'd1 ; */ +/*description: BIAS_SLEEP force no sleep*/ +#define RTC_CNTL_BIAS_FORCE_NOSLEEP (BIT(16)) +#define RTC_CNTL_BIAS_FORCE_NOSLEEP_M (BIT(16)) +#define RTC_CNTL_BIAS_FORCE_NOSLEEP_V 0x1 +#define RTC_CNTL_BIAS_FORCE_NOSLEEP_S 16 +/* RTC_CNTL_BIAS_FORCE_SLEEP : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: BIAS_SLEEP force sleep*/ +#define RTC_CNTL_BIAS_FORCE_SLEEP (BIT(15)) +#define RTC_CNTL_BIAS_FORCE_SLEEP_M (BIT(15)) +#define RTC_CNTL_BIAS_FORCE_SLEEP_V 0x1 +#define RTC_CNTL_BIAS_FORCE_SLEEP_S 15 +/* RTC_CNTL_BIAS_SLEEP_FOLW_8M : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: BIAS_SLEEP follow CK8M*/ +#define RTC_CNTL_BIAS_SLEEP_FOLW_8M (BIT(14)) +#define RTC_CNTL_BIAS_SLEEP_FOLW_8M_M (BIT(14)) +#define RTC_CNTL_BIAS_SLEEP_FOLW_8M_V 0x1 +#define RTC_CNTL_BIAS_SLEEP_FOLW_8M_S 14 +/* RTC_CNTL_XTL_FORCE_PU : R/W ;bitpos:[13] ;default: 1'd1 ; */ +/*description: crystall force power up*/ +#define RTC_CNTL_XTL_FORCE_PU (BIT(13)) +#define RTC_CNTL_XTL_FORCE_PU_M (BIT(13)) +#define RTC_CNTL_XTL_FORCE_PU_V 0x1 +#define RTC_CNTL_XTL_FORCE_PU_S 13 +/* RTC_CNTL_XTL_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: crystall force power down*/ +#define RTC_CNTL_XTL_FORCE_PD (BIT(12)) +#define RTC_CNTL_XTL_FORCE_PD_M (BIT(12)) +#define RTC_CNTL_XTL_FORCE_PD_V 0x1 +#define RTC_CNTL_XTL_FORCE_PD_S 12 +/* RTC_CNTL_BBPLL_FORCE_PU : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: BB_PLL force power up*/ +#define RTC_CNTL_BBPLL_FORCE_PU (BIT(11)) +#define RTC_CNTL_BBPLL_FORCE_PU_M (BIT(11)) +#define RTC_CNTL_BBPLL_FORCE_PU_V 0x1 +#define RTC_CNTL_BBPLL_FORCE_PU_S 11 +/* RTC_CNTL_BBPLL_FORCE_PD : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: BB_PLL force power down*/ +#define RTC_CNTL_BBPLL_FORCE_PD (BIT(10)) +#define RTC_CNTL_BBPLL_FORCE_PD_M (BIT(10)) +#define RTC_CNTL_BBPLL_FORCE_PD_V 0x1 +#define RTC_CNTL_BBPLL_FORCE_PD_S 10 +/* RTC_CNTL_BBPLL_I2C_FORCE_PU : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: BB_PLL_I2C force power up*/ +#define RTC_CNTL_BBPLL_I2C_FORCE_PU (BIT(9)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_M (BIT(9)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_V 0x1 +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_S 9 +/* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: BB_PLL _I2C force power down*/ +#define RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_M (BIT(8)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_V 0x1 +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_S 8 +/* RTC_CNTL_BB_I2C_FORCE_PU : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: BB_I2C force power up*/ +#define RTC_CNTL_BB_I2C_FORCE_PU (BIT(7)) +#define RTC_CNTL_BB_I2C_FORCE_PU_M (BIT(7)) +#define RTC_CNTL_BB_I2C_FORCE_PU_V 0x1 +#define RTC_CNTL_BB_I2C_FORCE_PU_S 7 +/* RTC_CNTL_BB_I2C_FORCE_PD : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: BB_I2C force power down*/ +#define RTC_CNTL_BB_I2C_FORCE_PD (BIT(6)) +#define RTC_CNTL_BB_I2C_FORCE_PD_M (BIT(6)) +#define RTC_CNTL_BB_I2C_FORCE_PD_V 0x1 +#define RTC_CNTL_BB_I2C_FORCE_PD_S 6 +/* RTC_CNTL_SW_PROCPU_RST : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: PRO CPU SW reset*/ +#define RTC_CNTL_SW_PROCPU_RST (BIT(5)) +#define RTC_CNTL_SW_PROCPU_RST_M (BIT(5)) +#define RTC_CNTL_SW_PROCPU_RST_V 0x1 +#define RTC_CNTL_SW_PROCPU_RST_S 5 +/* RTC_CNTL_SW_APPCPU_RST : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: APP CPU SW reset*/ +#define RTC_CNTL_SW_APPCPU_RST (BIT(4)) +#define RTC_CNTL_SW_APPCPU_RST_M (BIT(4)) +#define RTC_CNTL_SW_APPCPU_RST_V 0x1 +#define RTC_CNTL_SW_APPCPU_RST_S 4 +/* RTC_CNTL_SW_STALL_PROCPU_C0 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ +/*description: {reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == + 0x86 will stall PRO CPU*/ +#define RTC_CNTL_SW_STALL_PROCPU_C0 0x00000003 +#define RTC_CNTL_SW_STALL_PROCPU_C0_M ((RTC_CNTL_SW_STALL_PROCPU_C0_V)<<(RTC_CNTL_SW_STALL_PROCPU_C0_S)) +#define RTC_CNTL_SW_STALL_PROCPU_C0_V 0x3 +#define RTC_CNTL_SW_STALL_PROCPU_C0_S 2 +/* RTC_CNTL_SW_STALL_APPCPU_C0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: {reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == + 0x86 will stall APP CPU*/ +#define RTC_CNTL_SW_STALL_APPCPU_C0 0x00000003 +#define RTC_CNTL_SW_STALL_APPCPU_C0_M ((RTC_CNTL_SW_STALL_APPCPU_C0_V)<<(RTC_CNTL_SW_STALL_APPCPU_C0_S)) +#define RTC_CNTL_SW_STALL_APPCPU_C0_V 0x3 +#define RTC_CNTL_SW_STALL_APPCPU_C0_S 0 + +#define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x4) +/* RTC_CNTL_SLP_VAL_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: RTC sleep timer low 32 bits*/ +#define RTC_CNTL_SLP_VAL_LO 0xFFFFFFFF +#define RTC_CNTL_SLP_VAL_LO_M ((RTC_CNTL_SLP_VAL_LO_V)<<(RTC_CNTL_SLP_VAL_LO_S)) +#define RTC_CNTL_SLP_VAL_LO_V 0xFFFFFFFF +#define RTC_CNTL_SLP_VAL_LO_S 0 + +#define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x8) +/* RTC_CNTL_MAIN_TIMER_ALARM_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */ +/*description: timer alarm enable bit*/ +#define RTC_CNTL_MAIN_TIMER_ALARM_EN (BIT(16)) +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_M (BIT(16)) +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_V 0x1 +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_S 16 +/* RTC_CNTL_SLP_VAL_HI : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: RTC sleep timer high 16 bits*/ +#define RTC_CNTL_SLP_VAL_HI 0x0000FFFF +#define RTC_CNTL_SLP_VAL_HI_M ((RTC_CNTL_SLP_VAL_HI_V)<<(RTC_CNTL_SLP_VAL_HI_S)) +#define RTC_CNTL_SLP_VAL_HI_V 0xFFFF +#define RTC_CNTL_SLP_VAL_HI_S 0 + +#define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0xc) +/* RTC_CNTL_TIME_UPDATE : WO ;bitpos:[31] ;default: 1'h0 ; */ +/*description: Set 1: to update register with RTC timer*/ +#define RTC_CNTL_TIME_UPDATE (BIT(31)) +#define RTC_CNTL_TIME_UPDATE_M (BIT(31)) +#define RTC_CNTL_TIME_UPDATE_V 0x1 +#define RTC_CNTL_TIME_UPDATE_S 31 +/* RTC_CNTL_TIME_VALID : RO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: To indicate the register is updated*/ +#define RTC_CNTL_TIME_VALID (BIT(30)) +#define RTC_CNTL_TIME_VALID_M (BIT(30)) +#define RTC_CNTL_TIME_VALID_V 0x1 +#define RTC_CNTL_TIME_VALID_S 30 + +#define RTC_CNTL_TIME0_REG (DR_REG_RTCCNTL_BASE + 0x10) +/* RTC_CNTL_TIME_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: RTC timer low 32 bits*/ +#define RTC_CNTL_TIME_LO 0xFFFFFFFF +#define RTC_CNTL_TIME_LO_M ((RTC_CNTL_TIME_LO_V)<<(RTC_CNTL_TIME_LO_S)) +#define RTC_CNTL_TIME_LO_V 0xFFFFFFFF +#define RTC_CNTL_TIME_LO_S 0 + +#define RTC_CNTL_TIME1_REG (DR_REG_RTCCNTL_BASE + 0x14) +/* RTC_CNTL_TIME_HI : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: RTC timer high 16 bits*/ +#define RTC_CNTL_TIME_HI 0x0000FFFF +#define RTC_CNTL_TIME_HI_M ((RTC_CNTL_TIME_HI_V)<<(RTC_CNTL_TIME_HI_S)) +#define RTC_CNTL_TIME_HI_V 0xFFFF +#define RTC_CNTL_TIME_HI_S 0 + +#define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x18) +/* RTC_CNTL_SLEEP_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: sleep enable bit*/ +#define RTC_CNTL_SLEEP_EN (BIT(31)) +#define RTC_CNTL_SLEEP_EN_M (BIT(31)) +#define RTC_CNTL_SLEEP_EN_V 0x1 +#define RTC_CNTL_SLEEP_EN_S 31 +/* RTC_CNTL_SLP_REJECT : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: sleep reject bit*/ +#define RTC_CNTL_SLP_REJECT (BIT(30)) +#define RTC_CNTL_SLP_REJECT_M (BIT(30)) +#define RTC_CNTL_SLP_REJECT_V 0x1 +#define RTC_CNTL_SLP_REJECT_S 30 +/* RTC_CNTL_SLP_WAKEUP : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: sleep wakeup bit*/ +#define RTC_CNTL_SLP_WAKEUP (BIT(29)) +#define RTC_CNTL_SLP_WAKEUP_M (BIT(29)) +#define RTC_CNTL_SLP_WAKEUP_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_S 29 +/* RTC_CNTL_SDIO_ACTIVE_IND : RO ;bitpos:[28] ;default: 1'd0 ; */ +/*description: SDIO active indication*/ +#define RTC_CNTL_SDIO_ACTIVE_IND (BIT(28)) +#define RTC_CNTL_SDIO_ACTIVE_IND_M (BIT(28)) +#define RTC_CNTL_SDIO_ACTIVE_IND_V 0x1 +#define RTC_CNTL_SDIO_ACTIVE_IND_S 28 +/* RTC_CNTL_ULP_CP_SLP_TIMER_EN : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: ULP-coprocessor timer enable bit*/ +#define RTC_CNTL_ULP_CP_SLP_TIMER_EN (BIT(24)) +#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_M (BIT(24)) +#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_V 0x1 +#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_S 24 +/* RTC_CNTL_TOUCH_SLP_TIMER_EN : R/W ;bitpos:[23] ;default: 1'd0 ; */ +/*description: touch timer enable bit*/ +#define RTC_CNTL_TOUCH_SLP_TIMER_EN (BIT(23)) +#define RTC_CNTL_TOUCH_SLP_TIMER_EN_M (BIT(23)) +#define RTC_CNTL_TOUCH_SLP_TIMER_EN_V 0x1 +#define RTC_CNTL_TOUCH_SLP_TIMER_EN_S 23 +/* RTC_CNTL_APB2RTC_BRIDGE_SEL : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: 1: APB to RTC using bridge 0: APB to RTC using sync*/ +#define RTC_CNTL_APB2RTC_BRIDGE_SEL (BIT(22)) +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_M (BIT(22)) +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_V 0x1 +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_S 22 +/* RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN : R/W ;bitpos:[21] ;default: 1'd1 ; */ +/*description: ULP-coprocessor force wake up*/ +#define RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN (BIT(21)) +#define RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN_M (BIT(21)) +#define RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN_V 0x1 +#define RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN_S 21 +/* RTC_CNTL_TOUCH_WAKEUP_FORCE_EN : R/W ;bitpos:[20] ;default: 1'd1 ; */ +/*description: touch controller force wake up*/ +#define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN (BIT(20)) +#define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN_M (BIT(20)) +#define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN_V 0x1 +#define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN_S 20 + +#define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x1c) +/* RTC_CNTL_PLL_BUF_WAIT : R/W ;bitpos:[31:24] ;default: 8'd40 ; */ +/*description: PLL wait cycles in slow_clk_rtc*/ +#define RTC_CNTL_PLL_BUF_WAIT 0x000000FF +#define RTC_CNTL_PLL_BUF_WAIT_M ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S)) +#define RTC_CNTL_PLL_BUF_WAIT_V 0xFF +#define RTC_CNTL_PLL_BUF_WAIT_S 24 +/* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; */ +/*description: XTAL wait cycles in slow_clk_rtc*/ +#define RTC_CNTL_XTL_BUF_WAIT 0x000003FF +#define RTC_CNTL_XTL_BUF_WAIT_M ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S)) +#define RTC_CNTL_XTL_BUF_WAIT_V 0x3FF +#define RTC_CNTL_XTL_BUF_WAIT_S 14 +/* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; */ +/*description: CK8M wait cycles in slow_clk_rtc*/ +#define RTC_CNTL_CK8M_WAIT 0x000000FF +#define RTC_CNTL_CK8M_WAIT_M ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S)) +#define RTC_CNTL_CK8M_WAIT_V 0xFF +#define RTC_CNTL_CK8M_WAIT_S 6 +/* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */ +/*description: CPU stall wait cycles in fast_clk_rtc*/ +#define RTC_CNTL_CPU_STALL_WAIT 0x0000001F +#define RTC_CNTL_CPU_STALL_WAIT_M ((RTC_CNTL_CPU_STALL_WAIT_V)<<(RTC_CNTL_CPU_STALL_WAIT_S)) +#define RTC_CNTL_CPU_STALL_WAIT_V 0x1F +#define RTC_CNTL_CPU_STALL_WAIT_S 1 +/* RTC_CNTL_CPU_STALL_EN : R/W ;bitpos:[0] ;default: 1'd1 ; */ +/*description: CPU stall enable bit*/ +#define RTC_CNTL_CPU_STALL_EN (BIT(0)) +#define RTC_CNTL_CPU_STALL_EN_M (BIT(0)) +#define RTC_CNTL_CPU_STALL_EN_V 0x1 +#define RTC_CNTL_CPU_STALL_EN_S 0 + +#define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x20) +/* RTC_CNTL_MIN_TIME_CK8M_OFF : R/W ;bitpos:[31:24] ;default: 8'h1 ; */ +/*description: minimal cycles in slow_clk_rtc for CK8M in power down state*/ +#define RTC_CNTL_MIN_TIME_CK8M_OFF 0x000000FF +#define RTC_CNTL_MIN_TIME_CK8M_OFF_M ((RTC_CNTL_MIN_TIME_CK8M_OFF_V)<<(RTC_CNTL_MIN_TIME_CK8M_OFF_S)) +#define RTC_CNTL_MIN_TIME_CK8M_OFF_V 0xFF +#define RTC_CNTL_MIN_TIME_CK8M_OFF_S 24 +/* RTC_CNTL_ULPCP_TOUCH_START_WAIT : R/W ;bitpos:[23:15] ;default: 9'h10 ; */ +/*description: wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller + start to work*/ +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT 0x000001FF +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_M ((RTC_CNTL_ULPCP_TOUCH_START_WAIT_V)<<(RTC_CNTL_ULPCP_TOUCH_START_WAIT_S)) +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_V 0x1FF +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_S 15 + +#define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x24) +/* RTC_CNTL_ROM_RAM_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'd10 ; */ +/*description: */ +#define RTC_CNTL_ROM_RAM_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_M ((RTC_CNTL_ROM_RAM_POWERUP_TIMER_V)<<(RTC_CNTL_ROM_RAM_POWERUP_TIMER_S)) +#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_S 25 +/* RTC_CNTL_ROM_RAM_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h16 ; */ +/*description: */ +#define RTC_CNTL_ROM_RAM_WAIT_TIMER 0x000001FF +#define RTC_CNTL_ROM_RAM_WAIT_TIMER_M ((RTC_CNTL_ROM_RAM_WAIT_TIMER_V)<<(RTC_CNTL_ROM_RAM_WAIT_TIMER_S)) +#define RTC_CNTL_ROM_RAM_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_ROM_RAM_WAIT_TIMER_S 16 +/* RTC_CNTL_WIFI_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ +/*description: */ +#define RTC_CNTL_WIFI_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_WIFI_POWERUP_TIMER_M ((RTC_CNTL_WIFI_POWERUP_TIMER_V)<<(RTC_CNTL_WIFI_POWERUP_TIMER_S)) +#define RTC_CNTL_WIFI_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_WIFI_POWERUP_TIMER_S 9 +/* RTC_CNTL_WIFI_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ +/*description: */ +#define RTC_CNTL_WIFI_WAIT_TIMER 0x000001FF +#define RTC_CNTL_WIFI_WAIT_TIMER_M ((RTC_CNTL_WIFI_WAIT_TIMER_V)<<(RTC_CNTL_WIFI_WAIT_TIMER_S)) +#define RTC_CNTL_WIFI_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_WIFI_WAIT_TIMER_S 0 + +#define RTC_CNTL_TIMER4_REG (DR_REG_RTCCNTL_BASE + 0x28) +/* RTC_CNTL_DG_WRAP_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */ +/*description: */ +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M ((RTC_CNTL_DG_WRAP_POWERUP_TIMER_V)<<(RTC_CNTL_DG_WRAP_POWERUP_TIMER_S)) +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S 25 +/* RTC_CNTL_DG_WRAP_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */ +/*description: */ +#define RTC_CNTL_DG_WRAP_WAIT_TIMER 0x000001FF +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_M ((RTC_CNTL_DG_WRAP_WAIT_TIMER_V)<<(RTC_CNTL_DG_WRAP_WAIT_TIMER_S)) +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_S 16 +/* RTC_CNTL_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ +/*description: */ +#define RTC_CNTL_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_POWERUP_TIMER_M ((RTC_CNTL_POWERUP_TIMER_V)<<(RTC_CNTL_POWERUP_TIMER_S)) +#define RTC_CNTL_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_POWERUP_TIMER_S 9 +/* RTC_CNTL_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ +/*description: */ +#define RTC_CNTL_WAIT_TIMER 0x000001FF +#define RTC_CNTL_WAIT_TIMER_M ((RTC_CNTL_WAIT_TIMER_V)<<(RTC_CNTL_WAIT_TIMER_S)) +#define RTC_CNTL_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_WAIT_TIMER_S 0 + +#define RTC_CNTL_TIMER5_REG (DR_REG_RTCCNTL_BASE + 0x2c) +/* RTC_CNTL_RTCMEM_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h9 ; */ +/*description: */ +#define RTC_CNTL_RTCMEM_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_RTCMEM_POWERUP_TIMER_M ((RTC_CNTL_RTCMEM_POWERUP_TIMER_V)<<(RTC_CNTL_RTCMEM_POWERUP_TIMER_S)) +#define RTC_CNTL_RTCMEM_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_RTCMEM_POWERUP_TIMER_S 25 +/* RTC_CNTL_RTCMEM_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h14 ; */ +/*description: */ +#define RTC_CNTL_RTCMEM_WAIT_TIMER 0x000001FF +#define RTC_CNTL_RTCMEM_WAIT_TIMER_M ((RTC_CNTL_RTCMEM_WAIT_TIMER_V)<<(RTC_CNTL_RTCMEM_WAIT_TIMER_S)) +#define RTC_CNTL_RTCMEM_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_RTCMEM_WAIT_TIMER_S 16 +/* RTC_CNTL_MIN_SLP_VAL : R/W ;bitpos:[15:8] ;default: 8'h80 ; */ +/*description: minimal sleep cycles in slow_clk_rtc*/ +#define RTC_CNTL_MIN_SLP_VAL 0x000000FF +#define RTC_CNTL_MIN_SLP_VAL_M ((RTC_CNTL_MIN_SLP_VAL_V)<<(RTC_CNTL_MIN_SLP_VAL_S)) +#define RTC_CNTL_MIN_SLP_VAL_V 0xFF +#define RTC_CNTL_MIN_SLP_VAL_S 8 +/* RTC_CNTL_ULP_CP_SUBTIMER_PREDIV : R/W ;bitpos:[7:0] ;default: 8'd1 ; */ +/*description: */ +#define RTC_CNTL_ULP_CP_SUBTIMER_PREDIV 0x000000FF +#define RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_M ((RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_V)<<(RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_S)) +#define RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_V 0xFF +#define RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_S 0 + +#define RTC_CNTL_ANA_CONF_REG (DR_REG_RTCCNTL_BASE + 0x30) +/* RTC_CNTL_PLL_I2C_PU : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: 1: PLL_I2C power up otherwise power down*/ +#define RTC_CNTL_PLL_I2C_PU (BIT(31)) +#define RTC_CNTL_PLL_I2C_PU_M (BIT(31)) +#define RTC_CNTL_PLL_I2C_PU_V 0x1 +#define RTC_CNTL_PLL_I2C_PU_S 31 +/* RTC_CNTL_CKGEN_I2C_PU : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: 1: CKGEN_I2C power up otherwise power down*/ +#define RTC_CNTL_CKGEN_I2C_PU (BIT(30)) +#define RTC_CNTL_CKGEN_I2C_PU_M (BIT(30)) +#define RTC_CNTL_CKGEN_I2C_PU_V 0x1 +#define RTC_CNTL_CKGEN_I2C_PU_S 30 +/* RTC_CNTL_RFRX_PBUS_PU : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: 1: RFRX_PBUS power up otherwise power down*/ +#define RTC_CNTL_RFRX_PBUS_PU (BIT(28)) +#define RTC_CNTL_RFRX_PBUS_PU_M (BIT(28)) +#define RTC_CNTL_RFRX_PBUS_PU_V 0x1 +#define RTC_CNTL_RFRX_PBUS_PU_S 28 +/* RTC_CNTL_TXRF_I2C_PU : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: 1: TXRF_I2C power up otherwise power down*/ +#define RTC_CNTL_TXRF_I2C_PU (BIT(27)) +#define RTC_CNTL_TXRF_I2C_PU_M (BIT(27)) +#define RTC_CNTL_TXRF_I2C_PU_V 0x1 +#define RTC_CNTL_TXRF_I2C_PU_S 27 +/* RTC_CNTL_PVTMON_PU : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: 1: PVTMON power up otherwise power down*/ +#define RTC_CNTL_PVTMON_PU (BIT(26)) +#define RTC_CNTL_PVTMON_PU_M (BIT(26)) +#define RTC_CNTL_PVTMON_PU_V 0x1 +#define RTC_CNTL_PVTMON_PU_S 26 +/* RTC_CNTL_BBPLL_CAL_SLP_START : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: start BBPLL calibration during sleep*/ +#define RTC_CNTL_BBPLL_CAL_SLP_START (BIT(25)) +#define RTC_CNTL_BBPLL_CAL_SLP_START_M (BIT(25)) +#define RTC_CNTL_BBPLL_CAL_SLP_START_V 0x1 +#define RTC_CNTL_BBPLL_CAL_SLP_START_S 25 +/* RTC_CNTL_PLLA_FORCE_PU : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: PLLA force power up*/ +#define RTC_CNTL_PLLA_FORCE_PU (BIT(24)) +#define RTC_CNTL_PLLA_FORCE_PU_M (BIT(24)) +#define RTC_CNTL_PLLA_FORCE_PU_V 0x1 +#define RTC_CNTL_PLLA_FORCE_PU_S 24 +/* RTC_CNTL_PLLA_FORCE_PD : R/W ;bitpos:[23] ;default: 1'b1 ; */ +/*description: PLLA force power down*/ +#define RTC_CNTL_PLLA_FORCE_PD (BIT(23)) +#define RTC_CNTL_PLLA_FORCE_PD_M (BIT(23)) +#define RTC_CNTL_PLLA_FORCE_PD_V 0x1 +#define RTC_CNTL_PLLA_FORCE_PD_S 23 + +#define RTC_CNTL_RESET_STATE_REG (DR_REG_RTCCNTL_BASE + 0x34) +/* RTC_CNTL_PROCPU_STAT_VECTOR_SEL : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: PRO CPU state vector sel*/ +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL (BIT(13)) +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_M (BIT(13)) +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_V 0x1 +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_S 13 +/* RTC_CNTL_APPCPU_STAT_VECTOR_SEL : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: APP CPU state vector sel*/ +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL (BIT(12)) +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_M (BIT(12)) +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_V 0x1 +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_S 12 +/* RTC_CNTL_RESET_CAUSE_APPCPU : RO ;bitpos:[11:6] ;default: 0 ; */ +/*description: reset cause of APP CPU*/ +#define RTC_CNTL_RESET_CAUSE_APPCPU 0x0000003F +#define RTC_CNTL_RESET_CAUSE_APPCPU_M ((RTC_CNTL_RESET_CAUSE_APPCPU_V)<<(RTC_CNTL_RESET_CAUSE_APPCPU_S)) +#define RTC_CNTL_RESET_CAUSE_APPCPU_V 0x3F +#define RTC_CNTL_RESET_CAUSE_APPCPU_S 6 +/* RTC_CNTL_RESET_CAUSE_PROCPU : RO ;bitpos:[5:0] ;default: 0 ; */ +/*description: reset cause of PRO CPU*/ +#define RTC_CNTL_RESET_CAUSE_PROCPU 0x0000003F +#define RTC_CNTL_RESET_CAUSE_PROCPU_M ((RTC_CNTL_RESET_CAUSE_PROCPU_V)<<(RTC_CNTL_RESET_CAUSE_PROCPU_S)) +#define RTC_CNTL_RESET_CAUSE_PROCPU_V 0x3F +#define RTC_CNTL_RESET_CAUSE_PROCPU_S 0 + +#define RTC_CNTL_WAKEUP_STATE_REG (DR_REG_RTCCNTL_BASE + 0x38) +/* RTC_CNTL_GPIO_WAKEUP_FILTER : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: enable filter for gpio wakeup event*/ +#define RTC_CNTL_GPIO_WAKEUP_FILTER (BIT(22)) +#define RTC_CNTL_GPIO_WAKEUP_FILTER_M (BIT(22)) +#define RTC_CNTL_GPIO_WAKEUP_FILTER_V 0x1 +#define RTC_CNTL_GPIO_WAKEUP_FILTER_S 22 +/* RTC_CNTL_WAKEUP_ENA : R/W ;bitpos:[21:11] ;default: 11'b1100 ; */ +/*description: wakeup enable bitmap*/ +#define RTC_CNTL_WAKEUP_ENA 0x000007FF +#define RTC_CNTL_WAKEUP_ENA_M ((RTC_CNTL_WAKEUP_ENA_V)<<(RTC_CNTL_WAKEUP_ENA_S)) +#define RTC_CNTL_WAKEUP_ENA_V 0x7FF +#define RTC_CNTL_WAKEUP_ENA_S 11 +/* RTC_CNTL_WAKEUP_CAUSE : RO ;bitpos:[10:0] ;default: 11'h0 ; */ +/*description: wakeup cause*/ +#define RTC_CNTL_WAKEUP_CAUSE 0x000007FF +#define RTC_CNTL_WAKEUP_CAUSE_M ((RTC_CNTL_WAKEUP_CAUSE_V)<<(RTC_CNTL_WAKEUP_CAUSE_S)) +#define RTC_CNTL_WAKEUP_CAUSE_V 0x7FF +#define RTC_CNTL_WAKEUP_CAUSE_S 0 + +#define RTC_CNTL_INT_ENA_REG (DR_REG_RTCCNTL_BASE + 0x3c) +/* RTC_CNTL_MAIN_TIMER_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: enable RTC main timer interrupt*/ +#define RTC_CNTL_MAIN_TIMER_INT_ENA (BIT(8)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_M (BIT(8)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_ENA_S 8 +/* RTC_CNTL_BROWN_OUT_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: enable brown out interrupt*/ +#define RTC_CNTL_BROWN_OUT_INT_ENA (BIT(7)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_M (BIT(7)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_ENA_S 7 +/* RTC_CNTL_TOUCH_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: enable touch interrupt*/ +#define RTC_CNTL_TOUCH_INT_ENA (BIT(6)) +#define RTC_CNTL_TOUCH_INT_ENA_M (BIT(6)) +#define RTC_CNTL_TOUCH_INT_ENA_V 0x1 +#define RTC_CNTL_TOUCH_INT_ENA_S 6 +/* RTC_CNTL_ULP_CP_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: enable ULP-coprocessor interrupt*/ +#define RTC_CNTL_ULP_CP_INT_ENA (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_ENA_M (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_ENA_V 0x1 +#define RTC_CNTL_ULP_CP_INT_ENA_S 5 +/* RTC_CNTL_TIME_VALID_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: enable RTC time valid interrupt*/ +#define RTC_CNTL_TIME_VALID_INT_ENA (BIT(4)) +#define RTC_CNTL_TIME_VALID_INT_ENA_M (BIT(4)) +#define RTC_CNTL_TIME_VALID_INT_ENA_V 0x1 +#define RTC_CNTL_TIME_VALID_INT_ENA_S 4 +/* RTC_CNTL_WDT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: enable RTC WDT interrupt*/ +#define RTC_CNTL_WDT_INT_ENA (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_M (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_V 0x1 +#define RTC_CNTL_WDT_INT_ENA_S 3 +/* RTC_CNTL_SDIO_IDLE_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: enable SDIO idle interrupt*/ +#define RTC_CNTL_SDIO_IDLE_INT_ENA (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ENA_M (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ENA_V 0x1 +#define RTC_CNTL_SDIO_IDLE_INT_ENA_S 2 +/* RTC_CNTL_SLP_REJECT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: enable sleep reject interrupt*/ +#define RTC_CNTL_SLP_REJECT_INT_ENA (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_ENA_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: enable sleep wakeup interrupt*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ENA (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_S 0 + +#define RTC_CNTL_INT_RAW_REG (DR_REG_RTCCNTL_BASE + 0x40) +/* RTC_CNTL_MAIN_TIMER_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: RTC main timer interrupt raw*/ +#define RTC_CNTL_MAIN_TIMER_INT_RAW (BIT(8)) +#define RTC_CNTL_MAIN_TIMER_INT_RAW_M (BIT(8)) +#define RTC_CNTL_MAIN_TIMER_INT_RAW_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_RAW_S 8 +/* RTC_CNTL_BROWN_OUT_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: brown out interrupt raw*/ +#define RTC_CNTL_BROWN_OUT_INT_RAW (BIT(7)) +#define RTC_CNTL_BROWN_OUT_INT_RAW_M (BIT(7)) +#define RTC_CNTL_BROWN_OUT_INT_RAW_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_RAW_S 7 +/* RTC_CNTL_TOUCH_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: touch interrupt raw*/ +#define RTC_CNTL_TOUCH_INT_RAW (BIT(6)) +#define RTC_CNTL_TOUCH_INT_RAW_M (BIT(6)) +#define RTC_CNTL_TOUCH_INT_RAW_V 0x1 +#define RTC_CNTL_TOUCH_INT_RAW_S 6 +/* RTC_CNTL_ULP_CP_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: ULP-coprocessor interrupt raw*/ +#define RTC_CNTL_ULP_CP_INT_RAW (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_RAW_M (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_RAW_V 0x1 +#define RTC_CNTL_ULP_CP_INT_RAW_S 5 +/* RTC_CNTL_TIME_VALID_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: RTC time valid interrupt raw*/ +#define RTC_CNTL_TIME_VALID_INT_RAW (BIT(4)) +#define RTC_CNTL_TIME_VALID_INT_RAW_M (BIT(4)) +#define RTC_CNTL_TIME_VALID_INT_RAW_V 0x1 +#define RTC_CNTL_TIME_VALID_INT_RAW_S 4 +/* RTC_CNTL_WDT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: RTC WDT interrupt raw*/ +#define RTC_CNTL_WDT_INT_RAW (BIT(3)) +#define RTC_CNTL_WDT_INT_RAW_M (BIT(3)) +#define RTC_CNTL_WDT_INT_RAW_V 0x1 +#define RTC_CNTL_WDT_INT_RAW_S 3 +/* RTC_CNTL_SDIO_IDLE_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SDIO idle interrupt raw*/ +#define RTC_CNTL_SDIO_IDLE_INT_RAW (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_RAW_M (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_RAW_V 0x1 +#define RTC_CNTL_SDIO_IDLE_INT_RAW_S 2 +/* RTC_CNTL_SLP_REJECT_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: sleep reject interrupt raw*/ +#define RTC_CNTL_SLP_REJECT_INT_RAW (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_RAW_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_RAW_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_RAW_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: sleep wakeup interrupt raw*/ +#define RTC_CNTL_SLP_WAKEUP_INT_RAW (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_S 0 + +#define RTC_CNTL_INT_ST_REG (DR_REG_RTCCNTL_BASE + 0x44) +/* RTC_CNTL_MAIN_TIMER_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: RTC main timer interrupt state*/ +#define RTC_CNTL_MAIN_TIMER_INT_ST (BIT(8)) +#define RTC_CNTL_MAIN_TIMER_INT_ST_M (BIT(8)) +#define RTC_CNTL_MAIN_TIMER_INT_ST_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_ST_S 8 +/* RTC_CNTL_BROWN_OUT_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: brown out interrupt state*/ +#define RTC_CNTL_BROWN_OUT_INT_ST (BIT(7)) +#define RTC_CNTL_BROWN_OUT_INT_ST_M (BIT(7)) +#define RTC_CNTL_BROWN_OUT_INT_ST_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_ST_S 7 +/* RTC_CNTL_TOUCH_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: touch interrupt state*/ +#define RTC_CNTL_TOUCH_INT_ST (BIT(6)) +#define RTC_CNTL_TOUCH_INT_ST_M (BIT(6)) +#define RTC_CNTL_TOUCH_INT_ST_V 0x1 +#define RTC_CNTL_TOUCH_INT_ST_S 6 +/* RTC_CNTL_SAR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: ULP-coprocessor interrupt state*/ +#define RTC_CNTL_SAR_INT_ST (BIT(5)) +#define RTC_CNTL_SAR_INT_ST_M (BIT(5)) +#define RTC_CNTL_SAR_INT_ST_V 0x1 +#define RTC_CNTL_SAR_INT_ST_S 5 +/* RTC_CNTL_TIME_VALID_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: RTC time valid interrupt state*/ +#define RTC_CNTL_TIME_VALID_INT_ST (BIT(4)) +#define RTC_CNTL_TIME_VALID_INT_ST_M (BIT(4)) +#define RTC_CNTL_TIME_VALID_INT_ST_V 0x1 +#define RTC_CNTL_TIME_VALID_INT_ST_S 4 +/* RTC_CNTL_WDT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: RTC WDT interrupt state*/ +#define RTC_CNTL_WDT_INT_ST (BIT(3)) +#define RTC_CNTL_WDT_INT_ST_M (BIT(3)) +#define RTC_CNTL_WDT_INT_ST_V 0x1 +#define RTC_CNTL_WDT_INT_ST_S 3 +/* RTC_CNTL_SDIO_IDLE_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SDIO idle interrupt state*/ +#define RTC_CNTL_SDIO_IDLE_INT_ST (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ST_M (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ST_V 0x1 +#define RTC_CNTL_SDIO_IDLE_INT_ST_S 2 +/* RTC_CNTL_SLP_REJECT_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: sleep reject interrupt state*/ +#define RTC_CNTL_SLP_REJECT_INT_ST (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ST_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ST_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_ST_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: sleep wakeup interrupt state*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ST (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ST_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ST_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_ST_S 0 + +#define RTC_CNTL_INT_CLR_REG (DR_REG_RTCCNTL_BASE + 0x48) +/* RTC_CNTL_MAIN_TIMER_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Clear RTC main timer interrupt state*/ +#define RTC_CNTL_MAIN_TIMER_INT_CLR (BIT(8)) +#define RTC_CNTL_MAIN_TIMER_INT_CLR_M (BIT(8)) +#define RTC_CNTL_MAIN_TIMER_INT_CLR_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_CLR_S 8 +/* RTC_CNTL_BROWN_OUT_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Clear brown out interrupt state*/ +#define RTC_CNTL_BROWN_OUT_INT_CLR (BIT(7)) +#define RTC_CNTL_BROWN_OUT_INT_CLR_M (BIT(7)) +#define RTC_CNTL_BROWN_OUT_INT_CLR_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_CLR_S 7 +/* RTC_CNTL_TOUCH_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Clear touch interrupt state*/ +#define RTC_CNTL_TOUCH_INT_CLR (BIT(6)) +#define RTC_CNTL_TOUCH_INT_CLR_M (BIT(6)) +#define RTC_CNTL_TOUCH_INT_CLR_V 0x1 +#define RTC_CNTL_TOUCH_INT_CLR_S 6 +/* RTC_CNTL_SAR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Clear ULP-coprocessor interrupt state*/ +#define RTC_CNTL_SAR_INT_CLR (BIT(5)) +#define RTC_CNTL_SAR_INT_CLR_M (BIT(5)) +#define RTC_CNTL_SAR_INT_CLR_V 0x1 +#define RTC_CNTL_SAR_INT_CLR_S 5 +/* RTC_CNTL_TIME_VALID_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Clear RTC time valid interrupt state*/ +#define RTC_CNTL_TIME_VALID_INT_CLR (BIT(4)) +#define RTC_CNTL_TIME_VALID_INT_CLR_M (BIT(4)) +#define RTC_CNTL_TIME_VALID_INT_CLR_V 0x1 +#define RTC_CNTL_TIME_VALID_INT_CLR_S 4 +/* RTC_CNTL_WDT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Clear RTC WDT interrupt state*/ +#define RTC_CNTL_WDT_INT_CLR (BIT(3)) +#define RTC_CNTL_WDT_INT_CLR_M (BIT(3)) +#define RTC_CNTL_WDT_INT_CLR_V 0x1 +#define RTC_CNTL_WDT_INT_CLR_S 3 +/* RTC_CNTL_SDIO_IDLE_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Clear SDIO idle interrupt state*/ +#define RTC_CNTL_SDIO_IDLE_INT_CLR (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_CLR_M (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_CLR_V 0x1 +#define RTC_CNTL_SDIO_IDLE_INT_CLR_S 2 +/* RTC_CNTL_SLP_REJECT_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Clear sleep reject interrupt state*/ +#define RTC_CNTL_SLP_REJECT_INT_CLR (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_CLR_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_CLR_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_CLR_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Clear sleep wakeup interrupt state*/ +#define RTC_CNTL_SLP_WAKEUP_INT_CLR (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_S 0 + +#define RTC_CNTL_STORE0_REG (DR_REG_RTCCNTL_BASE + 0x4c) +/* RTC_CNTL_SCRATCH0 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: 32-bit general purpose retention register*/ +#define RTC_CNTL_SCRATCH0 0xFFFFFFFF +#define RTC_CNTL_SCRATCH0_M ((RTC_CNTL_SCRATCH0_V)<<(RTC_CNTL_SCRATCH0_S)) +#define RTC_CNTL_SCRATCH0_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH0_S 0 + +#define RTC_CNTL_STORE1_REG (DR_REG_RTCCNTL_BASE + 0x50) +/* RTC_CNTL_SCRATCH1 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: 32-bit general purpose retention register*/ +#define RTC_CNTL_SCRATCH1 0xFFFFFFFF +#define RTC_CNTL_SCRATCH1_M ((RTC_CNTL_SCRATCH1_V)<<(RTC_CNTL_SCRATCH1_S)) +#define RTC_CNTL_SCRATCH1_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH1_S 0 + +#define RTC_CNTL_STORE2_REG (DR_REG_RTCCNTL_BASE + 0x54) +/* RTC_CNTL_SCRATCH2 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: 32-bit general purpose retention register*/ +#define RTC_CNTL_SCRATCH2 0xFFFFFFFF +#define RTC_CNTL_SCRATCH2_M ((RTC_CNTL_SCRATCH2_V)<<(RTC_CNTL_SCRATCH2_S)) +#define RTC_CNTL_SCRATCH2_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH2_S 0 + +#define RTC_CNTL_STORE3_REG (DR_REG_RTCCNTL_BASE + 0x58) +/* RTC_CNTL_SCRATCH3 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: 32-bit general purpose retention register*/ +#define RTC_CNTL_SCRATCH3 0xFFFFFFFF +#define RTC_CNTL_SCRATCH3_M ((RTC_CNTL_SCRATCH3_V)<<(RTC_CNTL_SCRATCH3_S)) +#define RTC_CNTL_SCRATCH3_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH3_S 0 + +#define RTC_CNTL_EXT_XTL_CONF_REG (DR_REG_RTCCNTL_BASE + 0x5c) +/* RTC_CNTL_XTL_EXT_CTR_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: enable control XTAL by external pads*/ +#define RTC_CNTL_XTL_EXT_CTR_EN (BIT(31)) +#define RTC_CNTL_XTL_EXT_CTR_EN_M (BIT(31)) +#define RTC_CNTL_XTL_EXT_CTR_EN_V 0x1 +#define RTC_CNTL_XTL_EXT_CTR_EN_S 31 +/* RTC_CNTL_XTL_EXT_CTR_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: 0: power down XTAL at high level 1: power down XTAL at low level*/ +#define RTC_CNTL_XTL_EXT_CTR_LV (BIT(30)) +#define RTC_CNTL_XTL_EXT_CTR_LV_M (BIT(30)) +#define RTC_CNTL_XTL_EXT_CTR_LV_V 0x1 +#define RTC_CNTL_XTL_EXT_CTR_LV_S 30 + +#define RTC_CNTL_EXT_WAKEUP_CONF_REG (DR_REG_RTCCNTL_BASE + 0x60) +/* RTC_CNTL_EXT_WAKEUP1_LV : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: 0: external wakeup at low level 1: external wakeup at high level*/ +#define RTC_CNTL_EXT_WAKEUP1_LV (BIT(31)) +#define RTC_CNTL_EXT_WAKEUP1_LV_M (BIT(31)) +#define RTC_CNTL_EXT_WAKEUP1_LV_V 0x1 +#define RTC_CNTL_EXT_WAKEUP1_LV_S 31 +/* RTC_CNTL_EXT_WAKEUP0_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: 0: external wakeup at low level 1: external wakeup at high level*/ +#define RTC_CNTL_EXT_WAKEUP0_LV (BIT(30)) +#define RTC_CNTL_EXT_WAKEUP0_LV_M (BIT(30)) +#define RTC_CNTL_EXT_WAKEUP0_LV_V 0x1 +#define RTC_CNTL_EXT_WAKEUP0_LV_S 30 + +#define RTC_CNTL_SLP_REJECT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x64) +/* RTC_CNTL_REJECT_CAUSE : RO ;bitpos:[31:28] ;default: 4'b0 ; */ +/*description: sleep reject cause*/ +#define RTC_CNTL_REJECT_CAUSE 0x0000000F +#define RTC_CNTL_REJECT_CAUSE_M ((RTC_CNTL_REJECT_CAUSE_V)<<(RTC_CNTL_REJECT_CAUSE_S)) +#define RTC_CNTL_REJECT_CAUSE_V 0xF +#define RTC_CNTL_REJECT_CAUSE_S 28 +/* RTC_CNTL_DEEP_SLP_REJECT_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: enable reject for deep sleep*/ +#define RTC_CNTL_DEEP_SLP_REJECT_EN (BIT(27)) +#define RTC_CNTL_DEEP_SLP_REJECT_EN_M (BIT(27)) +#define RTC_CNTL_DEEP_SLP_REJECT_EN_V 0x1 +#define RTC_CNTL_DEEP_SLP_REJECT_EN_S 27 +/* RTC_CNTL_LIGHT_SLP_REJECT_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: enable reject for light sleep*/ +#define RTC_CNTL_LIGHT_SLP_REJECT_EN (BIT(26)) +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_M (BIT(26)) +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_V 0x1 +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_S 26 +/* RTC_CNTL_SDIO_REJECT_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: enable SDIO reject*/ +#define RTC_CNTL_SDIO_REJECT_EN (BIT(25)) +#define RTC_CNTL_SDIO_REJECT_EN_M (BIT(25)) +#define RTC_CNTL_SDIO_REJECT_EN_V 0x1 +#define RTC_CNTL_SDIO_REJECT_EN_S 25 +/* RTC_CNTL_GPIO_REJECT_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: enable GPIO reject*/ +#define RTC_CNTL_GPIO_REJECT_EN (BIT(24)) +#define RTC_CNTL_GPIO_REJECT_EN_M (BIT(24)) +#define RTC_CNTL_GPIO_REJECT_EN_V 0x1 +#define RTC_CNTL_GPIO_REJECT_EN_S 24 + +#define RTC_CNTL_CPU_PERIOD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x68) +/* RTC_CNTL_CPUPERIOD_SEL : R/W ;bitpos:[31:30] ;default: 2'b00 ; */ +/*description: CPU period sel*/ +#define RTC_CNTL_CPUPERIOD_SEL 0x00000003 +#define RTC_CNTL_CPUPERIOD_SEL_M ((RTC_CNTL_CPUPERIOD_SEL_V)<<(RTC_CNTL_CPUPERIOD_SEL_S)) +#define RTC_CNTL_CPUPERIOD_SEL_V 0x3 +#define RTC_CNTL_CPUPERIOD_SEL_S 30 +/* RTC_CNTL_CPUSEL_CONF : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: CPU sel option*/ +#define RTC_CNTL_CPUSEL_CONF (BIT(29)) +#define RTC_CNTL_CPUSEL_CONF_M (BIT(29)) +#define RTC_CNTL_CPUSEL_CONF_V 0x1 +#define RTC_CNTL_CPUSEL_CONF_S 29 + +#define RTC_CNTL_SDIO_ACT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x6c) +/* RTC_CNTL_SDIO_ACT_DNUM : R/W ;bitpos:[31:22] ;default: 10'b0 ; */ +/*description: */ +#define RTC_CNTL_SDIO_ACT_DNUM 0x000003FF +#define RTC_CNTL_SDIO_ACT_DNUM_M ((RTC_CNTL_SDIO_ACT_DNUM_V)<<(RTC_CNTL_SDIO_ACT_DNUM_S)) +#define RTC_CNTL_SDIO_ACT_DNUM_V 0x3FF +#define RTC_CNTL_SDIO_ACT_DNUM_S 22 + +#define RTC_CNTL_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x70) +/* RTC_CNTL_ANA_CLK_RTC_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: slow_clk_rtc sel. 0: SLOW_CK 1: CK_XTAL_32K 2: CK8M_D256_OUT*/ +#define RTC_CNTL_ANA_CLK_RTC_SEL 0x00000003 +#define RTC_CNTL_ANA_CLK_RTC_SEL_M ((RTC_CNTL_ANA_CLK_RTC_SEL_V)<<(RTC_CNTL_ANA_CLK_RTC_SEL_S)) +#define RTC_CNTL_ANA_CLK_RTC_SEL_V 0x3 +#define RTC_CNTL_ANA_CLK_RTC_SEL_S 30 +/* RTC_CNTL_FAST_CLK_RTC_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: fast_clk_rtc sel. 0: XTAL div 4 1: CK8M*/ +#define RTC_CNTL_FAST_CLK_RTC_SEL (BIT(29)) +#define RTC_CNTL_FAST_CLK_RTC_SEL_M (BIT(29)) +#define RTC_CNTL_FAST_CLK_RTC_SEL_V 0x1 +#define RTC_CNTL_FAST_CLK_RTC_SEL_S 29 +/* RTC_CNTL_SOC_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'd0 ; */ +/*description: SOC clock sel. 0: XTAL 1: PLL 2: CK8M 3: APLL*/ +#define RTC_CNTL_SOC_CLK_SEL 0x00000003 +#define RTC_CNTL_SOC_CLK_SEL_M ((RTC_CNTL_SOC_CLK_SEL_V)<<(RTC_CNTL_SOC_CLK_SEL_S)) +#define RTC_CNTL_SOC_CLK_SEL_V 0x3 +#define RTC_CNTL_SOC_CLK_SEL_S 27 +/* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */ +/*description: CK8M force power up*/ +#define RTC_CNTL_CK8M_FORCE_PU (BIT(26)) +#define RTC_CNTL_CK8M_FORCE_PU_M (BIT(26)) +#define RTC_CNTL_CK8M_FORCE_PU_V 0x1 +#define RTC_CNTL_CK8M_FORCE_PU_S 26 +/* RTC_CNTL_CK8M_FORCE_PD : R/W ;bitpos:[25] ;default: 1'd0 ; */ +/*description: CK8M force power down*/ +#define RTC_CNTL_CK8M_FORCE_PD (BIT(25)) +#define RTC_CNTL_CK8M_FORCE_PD_M (BIT(25)) +#define RTC_CNTL_CK8M_FORCE_PD_V 0x1 +#define RTC_CNTL_CK8M_FORCE_PD_S 25 +/* RTC_CNTL_CK8M_DFREQ : R/W ;bitpos:[24:17] ;default: 8'd0 ; */ +/*description: CK8M_DFREQ*/ +#define RTC_CNTL_CK8M_DFREQ 0x000000FF +#define RTC_CNTL_CK8M_DFREQ_M ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S)) +#define RTC_CNTL_CK8M_DFREQ_V 0xFF +#define RTC_CNTL_CK8M_DFREQ_S 17 +/* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: CK8M force no gating during sleep*/ +#define RTC_CNTL_CK8M_FORCE_NOGATING (BIT(16)) +#define RTC_CNTL_CK8M_FORCE_NOGATING_M (BIT(16)) +#define RTC_CNTL_CK8M_FORCE_NOGATING_V 0x1 +#define RTC_CNTL_CK8M_FORCE_NOGATING_S 16 +/* RTC_CNTL_XTAL_FORCE_NOGATING : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: XTAL force no gating during sleep*/ +#define RTC_CNTL_XTAL_FORCE_NOGATING (BIT(15)) +#define RTC_CNTL_XTAL_FORCE_NOGATING_M (BIT(15)) +#define RTC_CNTL_XTAL_FORCE_NOGATING_V 0x1 +#define RTC_CNTL_XTAL_FORCE_NOGATING_S 15 +/* RTC_CNTL_CK8M_DIV_SEL : R/W ;bitpos:[14:12] ;default: 3'd2 ; */ +/*description: divider = reg_ck8m_div_sel + 1*/ +#define RTC_CNTL_CK8M_DIV_SEL 0x00000007 +#define RTC_CNTL_CK8M_DIV_SEL_M ((RTC_CNTL_CK8M_DIV_SEL_V)<<(RTC_CNTL_CK8M_DIV_SEL_S)) +#define RTC_CNTL_CK8M_DIV_SEL_V 0x7 +#define RTC_CNTL_CK8M_DIV_SEL_S 12 +/* RTC_CNTL_CK8M_DFREQ_FORCE : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_CK8M_DFREQ_FORCE (BIT(11)) +#define RTC_CNTL_CK8M_DFREQ_FORCE_M (BIT(11)) +#define RTC_CNTL_CK8M_DFREQ_FORCE_V 0x1 +#define RTC_CNTL_CK8M_DFREQ_FORCE_S 11 +/* RTC_CNTL_DIG_CLK8M_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: enable CK8M for digital core (no relationship with RTC core)*/ +#define RTC_CNTL_DIG_CLK8M_EN (BIT(10)) +#define RTC_CNTL_DIG_CLK8M_EN_M (BIT(10)) +#define RTC_CNTL_DIG_CLK8M_EN_V 0x1 +#define RTC_CNTL_DIG_CLK8M_EN_S 10 +/* RTC_CNTL_DIG_CLK8M_D256_EN : R/W ;bitpos:[9] ;default: 1'd1 ; */ +/*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/ +#define RTC_CNTL_DIG_CLK8M_D256_EN (BIT(9)) +#define RTC_CNTL_DIG_CLK8M_D256_EN_M (BIT(9)) +#define RTC_CNTL_DIG_CLK8M_D256_EN_V 0x1 +#define RTC_CNTL_DIG_CLK8M_D256_EN_S 9 +/* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: enable CK_XTAL_32K for digital core (no relationship with RTC core)*/ +#define RTC_CNTL_DIG_XTAL32K_EN (BIT(8)) +#define RTC_CNTL_DIG_XTAL32K_EN_M (BIT(8)) +#define RTC_CNTL_DIG_XTAL32K_EN_V 0x1 +#define RTC_CNTL_DIG_XTAL32K_EN_S 8 +/* RTC_CNTL_ENB_CK8M_DIV : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: 1: CK8M_D256_OUT is actually CK8M 0: CK8M_D256_OUT is CK8M divided by 256*/ +#define RTC_CNTL_ENB_CK8M_DIV (BIT(7)) +#define RTC_CNTL_ENB_CK8M_DIV_M (BIT(7)) +#define RTC_CNTL_ENB_CK8M_DIV_V 0x1 +#define RTC_CNTL_ENB_CK8M_DIV_S 7 +/* RTC_CNTL_ENB_CK8M : R/W ;bitpos:[6] ;default: 1'd0 ; */ +/*description: disable CK8M and CK8M_D256_OUT*/ +#define RTC_CNTL_ENB_CK8M (BIT(6)) +#define RTC_CNTL_ENB_CK8M_M (BIT(6)) +#define RTC_CNTL_ENB_CK8M_V 0x1 +#define RTC_CNTL_ENB_CK8M_S 6 +/* RTC_CNTL_CK8M_DIV : R/W ;bitpos:[5:4] ;default: 2'b01 ; */ +/*description: CK8M_D256_OUT divider. 00: div128 01: div256 10: div512 11: div1024.*/ +#define RTC_CNTL_CK8M_DIV 0x00000003 +#define RTC_CNTL_CK8M_DIV_M ((RTC_CNTL_CK8M_DIV_V)<<(RTC_CNTL_CK8M_DIV_S)) +#define RTC_CNTL_CK8M_DIV_V 0x3 +#define RTC_CNTL_CK8M_DIV_S 4 + +#define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x74) +/* RTC_CNTL_XPD_SDIO_REG : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: SW option for XPD_SDIO_REG. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_XPD_SDIO_REG (BIT(31)) +#define RTC_CNTL_XPD_SDIO_REG_M (BIT(31)) +#define RTC_CNTL_XPD_SDIO_REG_V 0x1 +#define RTC_CNTL_XPD_SDIO_REG_S 31 +/* RTC_CNTL_DREFH_SDIO : R/W ;bitpos:[30:29] ;default: 2'b00 ; */ +/*description: SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_DREFH_SDIO 0x00000003 +#define RTC_CNTL_DREFH_SDIO_M ((RTC_CNTL_DREFH_SDIO_V)<<(RTC_CNTL_DREFH_SDIO_S)) +#define RTC_CNTL_DREFH_SDIO_V 0x3 +#define RTC_CNTL_DREFH_SDIO_S 29 +/* RTC_CNTL_DREFM_SDIO : R/W ;bitpos:[28:27] ;default: 2'b00 ; */ +/*description: SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_DREFM_SDIO 0x00000003 +#define RTC_CNTL_DREFM_SDIO_M ((RTC_CNTL_DREFM_SDIO_V)<<(RTC_CNTL_DREFM_SDIO_S)) +#define RTC_CNTL_DREFM_SDIO_V 0x3 +#define RTC_CNTL_DREFM_SDIO_S 27 +/* RTC_CNTL_DREFL_SDIO : R/W ;bitpos:[26:25] ;default: 2'b01 ; */ +/*description: SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_DREFL_SDIO 0x00000003 +#define RTC_CNTL_DREFL_SDIO_M ((RTC_CNTL_DREFL_SDIO_V)<<(RTC_CNTL_DREFL_SDIO_S)) +#define RTC_CNTL_DREFL_SDIO_V 0x3 +#define RTC_CNTL_DREFL_SDIO_S 25 +/* RTC_CNTL_REG1P8_READY : RO ;bitpos:[24] ;default: 1'd0 ; */ +/*description: read only register for REG1P8_READY*/ +#define RTC_CNTL_REG1P8_READY (BIT(24)) +#define RTC_CNTL_REG1P8_READY_M (BIT(24)) +#define RTC_CNTL_REG1P8_READY_V 0x1 +#define RTC_CNTL_REG1P8_READY_S 24 +/* RTC_CNTL_SDIO_TIEH : R/W ;bitpos:[23] ;default: 1'd1 ; */ +/*description: SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_SDIO_TIEH (BIT(23)) +#define RTC_CNTL_SDIO_TIEH_M (BIT(23)) +#define RTC_CNTL_SDIO_TIEH_V 0x1 +#define RTC_CNTL_SDIO_TIEH_S 23 +/* RTC_CNTL_SDIO_FORCE : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: 1: use SW option to control SDIO_REG 0: use state machine*/ +#define RTC_CNTL_SDIO_FORCE (BIT(22)) +#define RTC_CNTL_SDIO_FORCE_M (BIT(22)) +#define RTC_CNTL_SDIO_FORCE_V 0x1 +#define RTC_CNTL_SDIO_FORCE_S 22 +/* RTC_CNTL_SDIO_PD_EN : R/W ;bitpos:[21] ;default: 1'd1 ; */ +/*description: power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/ +#define RTC_CNTL_SDIO_PD_EN (BIT(21)) +#define RTC_CNTL_SDIO_PD_EN_M (BIT(21)) +#define RTC_CNTL_SDIO_PD_EN_V 0x1 +#define RTC_CNTL_SDIO_PD_EN_S 21 + +#define RTC_CNTL_BIAS_CONF_REG (DR_REG_RTCCNTL_BASE + 0x78) +/* RTC_CNTL_RST_BIAS_I2C : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: RST_BIAS_I2C*/ +#define RTC_CNTL_RST_BIAS_I2C (BIT(31)) +#define RTC_CNTL_RST_BIAS_I2C_M (BIT(31)) +#define RTC_CNTL_RST_BIAS_I2C_V 0x1 +#define RTC_CNTL_RST_BIAS_I2C_S 31 +/* RTC_CNTL_DEC_HEARTBEAT_WIDTH : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: DEC_HEARTBEAT_WIDTH*/ +#define RTC_CNTL_DEC_HEARTBEAT_WIDTH (BIT(30)) +#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_M (BIT(30)) +#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_V 0x1 +#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_S 30 +/* RTC_CNTL_INC_HEARTBEAT_PERIOD : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: INC_HEARTBEAT_PERIOD*/ +#define RTC_CNTL_INC_HEARTBEAT_PERIOD (BIT(29)) +#define RTC_CNTL_INC_HEARTBEAT_PERIOD_M (BIT(29)) +#define RTC_CNTL_INC_HEARTBEAT_PERIOD_V 0x1 +#define RTC_CNTL_INC_HEARTBEAT_PERIOD_S 29 +/* RTC_CNTL_DEC_HEARTBEAT_PERIOD : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: DEC_HEARTBEAT_PERIOD*/ +#define RTC_CNTL_DEC_HEARTBEAT_PERIOD (BIT(28)) +#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_M (BIT(28)) +#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_V 0x1 +#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_S 28 +/* RTC_CNTL_INC_HEARTBEAT_REFRESH : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: INC_HEARTBEAT_REFRESH*/ +#define RTC_CNTL_INC_HEARTBEAT_REFRESH (BIT(27)) +#define RTC_CNTL_INC_HEARTBEAT_REFRESH_M (BIT(27)) +#define RTC_CNTL_INC_HEARTBEAT_REFRESH_V 0x1 +#define RTC_CNTL_INC_HEARTBEAT_REFRESH_S 27 +/* RTC_CNTL_ENB_SCK_XTAL : R/W ;bitpos:[26] ;default: 1'd0 ; */ +/*description: ENB_SCK_XTAL*/ +#define RTC_CNTL_ENB_SCK_XTAL (BIT(26)) +#define RTC_CNTL_ENB_SCK_XTAL_M (BIT(26)) +#define RTC_CNTL_ENB_SCK_XTAL_V 0x1 +#define RTC_CNTL_ENB_SCK_XTAL_S 26 +/* RTC_CNTL_DBG_ATTEN : R/W ;bitpos:[25:24] ;default: 2'b00 ; */ +/*description: DBG_ATTEN*/ +#define RTC_CNTL_DBG_ATTEN 0x00000003 +#define RTC_CNTL_DBG_ATTEN_M ((RTC_CNTL_DBG_ATTEN_V)<<(RTC_CNTL_DBG_ATTEN_S)) +#define RTC_CNTL_DBG_ATTEN_V 0x3 +#define RTC_CNTL_DBG_ATTEN_S 24 + +#define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x7c) +/* RTC_CNTL_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */ +/*description: RTC_REG force power up*/ +#define RTC_CNTL_FORCE_PU (BIT(31)) +#define RTC_CNTL_FORCE_PU_M (BIT(31)) +#define RTC_CNTL_FORCE_PU_V 0x1 +#define RTC_CNTL_FORCE_PU_S 31 +/* RTC_CNTL_FORCE_PD : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: RTC_REG force power down (for RTC_REG power down means decrease + the voltage to 0.8v or lower )*/ +#define RTC_CNTL_FORCE_PD (BIT(30)) +#define RTC_CNTL_FORCE_PD_M (BIT(30)) +#define RTC_CNTL_FORCE_PD_V 0x1 +#define RTC_CNTL_FORCE_PD_S 30 +/* RTC_CNTL_DBOOST_FORCE_PU : R/W ;bitpos:[29] ;default: 1'd1 ; */ +/*description: RTC_DBOOST force power up*/ +#define RTC_CNTL_DBOOST_FORCE_PU (BIT(29)) +#define RTC_CNTL_DBOOST_FORCE_PU_M (BIT(29)) +#define RTC_CNTL_DBOOST_FORCE_PU_V 0x1 +#define RTC_CNTL_DBOOST_FORCE_PU_S 29 +/* RTC_CNTL_DBOOST_FORCE_PD : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: RTC_DBOOST force power down*/ +#define RTC_CNTL_DBOOST_FORCE_PD (BIT(28)) +#define RTC_CNTL_DBOOST_FORCE_PD_M (BIT(28)) +#define RTC_CNTL_DBOOST_FORCE_PD_V 0x1 +#define RTC_CNTL_DBOOST_FORCE_PD_S 28 +/* RTC_CNTL_DBIAS_WAK : R/W ;bitpos:[27:25] ;default: 3'd4 ; */ +/*description: RTC_DBIAS during wakeup*/ +#define RTC_CNTL_DBIAS_WAK 0x00000007 +#define RTC_CNTL_DBIAS_WAK_M ((RTC_CNTL_DBIAS_WAK_V)<<(RTC_CNTL_DBIAS_WAK_S)) +#define RTC_CNTL_DBIAS_WAK_V 0x7 +#define RTC_CNTL_DBIAS_WAK_S 25 +/* RTC_CNTL_DBIAS_SLP : R/W ;bitpos:[24:22] ;default: 3'd4 ; */ +/*description: RTC_DBIAS during sleep*/ +#define RTC_CNTL_DBIAS_SLP 0x00000007 +#define RTC_CNTL_DBIAS_SLP_M ((RTC_CNTL_DBIAS_SLP_V)<<(RTC_CNTL_DBIAS_SLP_S)) +#define RTC_CNTL_DBIAS_SLP_V 0x7 +#define RTC_CNTL_DBIAS_SLP_S 22 +/* RTC_CNTL_SCK_DCAP : R/W ;bitpos:[21:14] ;default: 8'd0 ; */ +/*description: SCK_DCAP*/ +#define RTC_CNTL_SCK_DCAP 0x000000FF +#define RTC_CNTL_SCK_DCAP_M ((RTC_CNTL_SCK_DCAP_V)<<(RTC_CNTL_SCK_DCAP_S)) +#define RTC_CNTL_SCK_DCAP_V 0xFF +#define RTC_CNTL_SCK_DCAP_S 14 +/* RTC_CNTL_DIG_DBIAS_WAK : R/W ;bitpos:[13:11] ;default: 3'd4 ; */ +/*description: DIG_REG_DBIAS during wakeup*/ +#define RTC_CNTL_DIG_DBIAS_WAK 0x00000007 +#define RTC_CNTL_DIG_DBIAS_WAK_M ((RTC_CNTL_DIG_DBIAS_WAK_V)<<(RTC_CNTL_DIG_DBIAS_WAK_S)) +#define RTC_CNTL_DIG_DBIAS_WAK_V 0x7 +#define RTC_CNTL_DIG_DBIAS_WAK_S 11 +/* RTC_CNTL_DIG_DBIAS_SLP : R/W ;bitpos:[10:8] ;default: 3'd4 ; */ +/*description: DIG_REG_DBIAS during sleep*/ +#define RTC_CNTL_DIG_DBIAS_SLP 0x00000007 +#define RTC_CNTL_DIG_DBIAS_SLP_M ((RTC_CNTL_DIG_DBIAS_SLP_V)<<(RTC_CNTL_DIG_DBIAS_SLP_S)) +#define RTC_CNTL_DIG_DBIAS_SLP_V 0x7 +#define RTC_CNTL_DIG_DBIAS_SLP_S 8 +/* RTC_CNTL_SCK_DCAP_FORCE : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: N/A*/ +#define RTC_CNTL_SCK_DCAP_FORCE (BIT(7)) +#define RTC_CNTL_SCK_DCAP_FORCE_M (BIT(7)) +#define RTC_CNTL_SCK_DCAP_FORCE_V 0x1 +#define RTC_CNTL_SCK_DCAP_FORCE_S 7 + +#define RTC_CNTL_PWC_REG (DR_REG_RTCCNTL_BASE + 0x80) +/* RTC_CNTL_PD_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: enable power down rtc_peri in sleep*/ +#define RTC_CNTL_PD_EN (BIT(20)) +#define RTC_CNTL_PD_EN_M (BIT(20)) +#define RTC_CNTL_PD_EN_V 0x1 +#define RTC_CNTL_PD_EN_S 20 +/* RTC_CNTL_FORCE_PU : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: rtc_peri force power up*/ +#define RTC_CNTL_PWC_FORCE_PU (BIT(19)) +#define RTC_CNTL_PWC_FORCE_PU_M (BIT(19)) +#define RTC_CNTL_PWC_FORCE_PU_V 0x1 +#define RTC_CNTL_PWC_FORCE_PU_S 19 +/* RTC_CNTL_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: rtc_peri force power down*/ +#define RTC_CNTL_PWC_FORCE_PD (BIT(18)) +#define RTC_CNTL_PWC_FORCE_PD_M (BIT(18)) +#define RTC_CNTL_PWC_FORCE_PD_V 0x1 +#define RTC_CNTL_PWC_FORCE_PD_S 18 +/* RTC_CNTL_SLOWMEM_PD_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: enable power down RTC memory in sleep*/ +#define RTC_CNTL_SLOWMEM_PD_EN (BIT(17)) +#define RTC_CNTL_SLOWMEM_PD_EN_M (BIT(17)) +#define RTC_CNTL_SLOWMEM_PD_EN_V 0x1 +#define RTC_CNTL_SLOWMEM_PD_EN_S 17 +/* RTC_CNTL_SLOWMEM_FORCE_PU : R/W ;bitpos:[16] ;default: 1'b1 ; */ +/*description: RTC memory force power up*/ +#define RTC_CNTL_SLOWMEM_FORCE_PU (BIT(16)) +#define RTC_CNTL_SLOWMEM_FORCE_PU_M (BIT(16)) +#define RTC_CNTL_SLOWMEM_FORCE_PU_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_PU_S 16 +/* RTC_CNTL_SLOWMEM_FORCE_PD : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: RTC memory force power down*/ +#define RTC_CNTL_SLOWMEM_FORCE_PD (BIT(15)) +#define RTC_CNTL_SLOWMEM_FORCE_PD_M (BIT(15)) +#define RTC_CNTL_SLOWMEM_FORCE_PD_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_PD_S 15 +/* RTC_CNTL_FASTMEM_PD_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: enable power down fast RTC memory in sleep*/ +#define RTC_CNTL_FASTMEM_PD_EN (BIT(14)) +#define RTC_CNTL_FASTMEM_PD_EN_M (BIT(14)) +#define RTC_CNTL_FASTMEM_PD_EN_V 0x1 +#define RTC_CNTL_FASTMEM_PD_EN_S 14 +/* RTC_CNTL_FASTMEM_FORCE_PU : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: Fast RTC memory force power up*/ +#define RTC_CNTL_FASTMEM_FORCE_PU (BIT(13)) +#define RTC_CNTL_FASTMEM_FORCE_PU_M (BIT(13)) +#define RTC_CNTL_FASTMEM_FORCE_PU_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_PU_S 13 +/* RTC_CNTL_FASTMEM_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Fast RTC memory force power down*/ +#define RTC_CNTL_FASTMEM_FORCE_PD (BIT(12)) +#define RTC_CNTL_FASTMEM_FORCE_PD_M (BIT(12)) +#define RTC_CNTL_FASTMEM_FORCE_PD_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_PD_S 12 +/* RTC_CNTL_SLOWMEM_FORCE_LPU : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: RTC memory force no PD*/ +#define RTC_CNTL_SLOWMEM_FORCE_LPU (BIT(11)) +#define RTC_CNTL_SLOWMEM_FORCE_LPU_M (BIT(11)) +#define RTC_CNTL_SLOWMEM_FORCE_LPU_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_LPU_S 11 +/* RTC_CNTL_SLOWMEM_FORCE_LPD : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: RTC memory force PD*/ +#define RTC_CNTL_SLOWMEM_FORCE_LPD (BIT(10)) +#define RTC_CNTL_SLOWMEM_FORCE_LPD_M (BIT(10)) +#define RTC_CNTL_SLOWMEM_FORCE_LPD_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_LPD_S 10 +/* RTC_CNTL_SLOWMEM_FOLW_CPU : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: 1: RTC memory PD following CPU 0: RTC memory PD following RTC state machine*/ +#define RTC_CNTL_SLOWMEM_FOLW_CPU (BIT(9)) +#define RTC_CNTL_SLOWMEM_FOLW_CPU_M (BIT(9)) +#define RTC_CNTL_SLOWMEM_FOLW_CPU_V 0x1 +#define RTC_CNTL_SLOWMEM_FOLW_CPU_S 9 +/* RTC_CNTL_FASTMEM_FORCE_LPU : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: Fast RTC memory force no PD*/ +#define RTC_CNTL_FASTMEM_FORCE_LPU (BIT(8)) +#define RTC_CNTL_FASTMEM_FORCE_LPU_M (BIT(8)) +#define RTC_CNTL_FASTMEM_FORCE_LPU_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_LPU_S 8 +/* RTC_CNTL_FASTMEM_FORCE_LPD : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Fast RTC memory force PD*/ +#define RTC_CNTL_FASTMEM_FORCE_LPD (BIT(7)) +#define RTC_CNTL_FASTMEM_FORCE_LPD_M (BIT(7)) +#define RTC_CNTL_FASTMEM_FORCE_LPD_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_LPD_S 7 +/* RTC_CNTL_FASTMEM_FOLW_CPU : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: 1: Fast RTC memory PD following CPU 0: fast RTC memory PD following + RTC state machine*/ +#define RTC_CNTL_FASTMEM_FOLW_CPU (BIT(6)) +#define RTC_CNTL_FASTMEM_FOLW_CPU_M (BIT(6)) +#define RTC_CNTL_FASTMEM_FOLW_CPU_V 0x1 +#define RTC_CNTL_FASTMEM_FOLW_CPU_S 6 +/* RTC_CNTL_FORCE_NOISO : R/W ;bitpos:[5] ;default: 1'd1 ; */ +/*description: rtc_peri force no ISO*/ +#define RTC_CNTL_FORCE_NOISO (BIT(5)) +#define RTC_CNTL_FORCE_NOISO_M (BIT(5)) +#define RTC_CNTL_FORCE_NOISO_V 0x1 +#define RTC_CNTL_FORCE_NOISO_S 5 +/* RTC_CNTL_FORCE_ISO : R/W ;bitpos:[4] ;default: 1'd0 ; */ +/*description: rtc_peri force ISO*/ +#define RTC_CNTL_FORCE_ISO (BIT(4)) +#define RTC_CNTL_FORCE_ISO_M (BIT(4)) +#define RTC_CNTL_FORCE_ISO_V 0x1 +#define RTC_CNTL_FORCE_ISO_S 4 +/* RTC_CNTL_SLOWMEM_FORCE_ISO : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: RTC memory force ISO*/ +#define RTC_CNTL_SLOWMEM_FORCE_ISO (BIT(3)) +#define RTC_CNTL_SLOWMEM_FORCE_ISO_M (BIT(3)) +#define RTC_CNTL_SLOWMEM_FORCE_ISO_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_ISO_S 3 +/* RTC_CNTL_SLOWMEM_FORCE_NOISO : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: RTC memory force no ISO*/ +#define RTC_CNTL_SLOWMEM_FORCE_NOISO (BIT(2)) +#define RTC_CNTL_SLOWMEM_FORCE_NOISO_M (BIT(2)) +#define RTC_CNTL_SLOWMEM_FORCE_NOISO_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_NOISO_S 2 +/* RTC_CNTL_FASTMEM_FORCE_ISO : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Fast RTC memory force ISO*/ +#define RTC_CNTL_FASTMEM_FORCE_ISO (BIT(1)) +#define RTC_CNTL_FASTMEM_FORCE_ISO_M (BIT(1)) +#define RTC_CNTL_FASTMEM_FORCE_ISO_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_ISO_S 1 +/* RTC_CNTL_FASTMEM_FORCE_NOISO : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: Fast RTC memory force no ISO*/ +#define RTC_CNTL_FASTMEM_FORCE_NOISO (BIT(0)) +#define RTC_CNTL_FASTMEM_FORCE_NOISO_M (BIT(0)) +#define RTC_CNTL_FASTMEM_FORCE_NOISO_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_NOISO_S 0 + +#define RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0x84) +/* RTC_CNTL_DG_WRAP_PD_EN : R/W ;bitpos:[31] ;default: 0 ; */ +/*description: enable power down digital core in sleep*/ +#define RTC_CNTL_DG_WRAP_PD_EN (BIT(31)) +#define RTC_CNTL_DG_WRAP_PD_EN_M (BIT(31)) +#define RTC_CNTL_DG_WRAP_PD_EN_V 0x1 +#define RTC_CNTL_DG_WRAP_PD_EN_S 31 +/* RTC_CNTL_WIFI_PD_EN : R/W ;bitpos:[30] ;default: 0 ; */ +/*description: enable power down wifi in sleep*/ +#define RTC_CNTL_WIFI_PD_EN (BIT(30)) +#define RTC_CNTL_WIFI_PD_EN_M (BIT(30)) +#define RTC_CNTL_WIFI_PD_EN_V 0x1 +#define RTC_CNTL_WIFI_PD_EN_S 30 +/* RTC_CNTL_INTER_RAM4_PD_EN : R/W ;bitpos:[29] ;default: 0 ; */ +/*description: enable power down internal SRAM 4 in sleep*/ +#define RTC_CNTL_INTER_RAM4_PD_EN (BIT(29)) +#define RTC_CNTL_INTER_RAM4_PD_EN_M (BIT(29)) +#define RTC_CNTL_INTER_RAM4_PD_EN_V 0x1 +#define RTC_CNTL_INTER_RAM4_PD_EN_S 29 +/* RTC_CNTL_INTER_RAM3_PD_EN : R/W ;bitpos:[28] ;default: 0 ; */ +/*description: enable power down internal SRAM 3 in sleep*/ +#define RTC_CNTL_INTER_RAM3_PD_EN (BIT(28)) +#define RTC_CNTL_INTER_RAM3_PD_EN_M (BIT(28)) +#define RTC_CNTL_INTER_RAM3_PD_EN_V 0x1 +#define RTC_CNTL_INTER_RAM3_PD_EN_S 28 +/* RTC_CNTL_INTER_RAM2_PD_EN : R/W ;bitpos:[27] ;default: 0 ; */ +/*description: enable power down internal SRAM 2 in sleep*/ +#define RTC_CNTL_INTER_RAM2_PD_EN (BIT(27)) +#define RTC_CNTL_INTER_RAM2_PD_EN_M (BIT(27)) +#define RTC_CNTL_INTER_RAM2_PD_EN_V 0x1 +#define RTC_CNTL_INTER_RAM2_PD_EN_S 27 +/* RTC_CNTL_INTER_RAM1_PD_EN : R/W ;bitpos:[26] ;default: 0 ; */ +/*description: enable power down internal SRAM 1 in sleep*/ +#define RTC_CNTL_INTER_RAM1_PD_EN (BIT(26)) +#define RTC_CNTL_INTER_RAM1_PD_EN_M (BIT(26)) +#define RTC_CNTL_INTER_RAM1_PD_EN_V 0x1 +#define RTC_CNTL_INTER_RAM1_PD_EN_S 26 +/* RTC_CNTL_INTER_RAM0_PD_EN : R/W ;bitpos:[25] ;default: 0 ; */ +/*description: enable power down internal SRAM 0 in sleep*/ +#define RTC_CNTL_INTER_RAM0_PD_EN (BIT(25)) +#define RTC_CNTL_INTER_RAM0_PD_EN_M (BIT(25)) +#define RTC_CNTL_INTER_RAM0_PD_EN_V 0x1 +#define RTC_CNTL_INTER_RAM0_PD_EN_S 25 +/* RTC_CNTL_ROM0_PD_EN : R/W ;bitpos:[24] ;default: 0 ; */ +/*description: enable power down ROM in sleep*/ +#define RTC_CNTL_ROM0_PD_EN (BIT(24)) +#define RTC_CNTL_ROM0_PD_EN_M (BIT(24)) +#define RTC_CNTL_ROM0_PD_EN_V 0x1 +#define RTC_CNTL_ROM0_PD_EN_S 24 +/* RTC_CNTL_DG_WRAP_FORCE_PU : R/W ;bitpos:[20] ;default: 1'd1 ; */ +/*description: digital core force power up*/ +#define RTC_CNTL_DG_WRAP_FORCE_PU (BIT(20)) +#define RTC_CNTL_DG_WRAP_FORCE_PU_M (BIT(20)) +#define RTC_CNTL_DG_WRAP_FORCE_PU_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_PU_S 20 +/* RTC_CNTL_DG_WRAP_FORCE_PD : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: digital core force power down*/ +#define RTC_CNTL_DG_WRAP_FORCE_PD (BIT(19)) +#define RTC_CNTL_DG_WRAP_FORCE_PD_M (BIT(19)) +#define RTC_CNTL_DG_WRAP_FORCE_PD_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_PD_S 19 +/* RTC_CNTL_WIFI_FORCE_PU : R/W ;bitpos:[18] ;default: 1'd1 ; */ +/*description: wifi force power up*/ +#define RTC_CNTL_WIFI_FORCE_PU (BIT(18)) +#define RTC_CNTL_WIFI_FORCE_PU_M (BIT(18)) +#define RTC_CNTL_WIFI_FORCE_PU_V 0x1 +#define RTC_CNTL_WIFI_FORCE_PU_S 18 +/* RTC_CNTL_WIFI_FORCE_PD : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: wifi force power down*/ +#define RTC_CNTL_WIFI_FORCE_PD (BIT(17)) +#define RTC_CNTL_WIFI_FORCE_PD_M (BIT(17)) +#define RTC_CNTL_WIFI_FORCE_PD_V 0x1 +#define RTC_CNTL_WIFI_FORCE_PD_S 17 +/* RTC_CNTL_INTER_RAM4_FORCE_PU : R/W ;bitpos:[16] ;default: 1'd1 ; */ +/*description: internal SRAM 4 force power up*/ +#define RTC_CNTL_INTER_RAM4_FORCE_PU (BIT(16)) +#define RTC_CNTL_INTER_RAM4_FORCE_PU_M (BIT(16)) +#define RTC_CNTL_INTER_RAM4_FORCE_PU_V 0x1 +#define RTC_CNTL_INTER_RAM4_FORCE_PU_S 16 +/* RTC_CNTL_INTER_RAM4_FORCE_PD : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: internal SRAM 4 force power down*/ +#define RTC_CNTL_INTER_RAM4_FORCE_PD (BIT(15)) +#define RTC_CNTL_INTER_RAM4_FORCE_PD_M (BIT(15)) +#define RTC_CNTL_INTER_RAM4_FORCE_PD_V 0x1 +#define RTC_CNTL_INTER_RAM4_FORCE_PD_S 15 +/* RTC_CNTL_INTER_RAM3_FORCE_PU : R/W ;bitpos:[14] ;default: 1'd1 ; */ +/*description: internal SRAM 3 force power up*/ +#define RTC_CNTL_INTER_RAM3_FORCE_PU (BIT(14)) +#define RTC_CNTL_INTER_RAM3_FORCE_PU_M (BIT(14)) +#define RTC_CNTL_INTER_RAM3_FORCE_PU_V 0x1 +#define RTC_CNTL_INTER_RAM3_FORCE_PU_S 14 +/* RTC_CNTL_INTER_RAM3_FORCE_PD : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: internal SRAM 3 force power down*/ +#define RTC_CNTL_INTER_RAM3_FORCE_PD (BIT(13)) +#define RTC_CNTL_INTER_RAM3_FORCE_PD_M (BIT(13)) +#define RTC_CNTL_INTER_RAM3_FORCE_PD_V 0x1 +#define RTC_CNTL_INTER_RAM3_FORCE_PD_S 13 +/* RTC_CNTL_INTER_RAM2_FORCE_PU : R/W ;bitpos:[12] ;default: 1'd1 ; */ +/*description: internal SRAM 2 force power up*/ +#define RTC_CNTL_INTER_RAM2_FORCE_PU (BIT(12)) +#define RTC_CNTL_INTER_RAM2_FORCE_PU_M (BIT(12)) +#define RTC_CNTL_INTER_RAM2_FORCE_PU_V 0x1 +#define RTC_CNTL_INTER_RAM2_FORCE_PU_S 12 +/* RTC_CNTL_INTER_RAM2_FORCE_PD : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: internal SRAM 2 force power down*/ +#define RTC_CNTL_INTER_RAM2_FORCE_PD (BIT(11)) +#define RTC_CNTL_INTER_RAM2_FORCE_PD_M (BIT(11)) +#define RTC_CNTL_INTER_RAM2_FORCE_PD_V 0x1 +#define RTC_CNTL_INTER_RAM2_FORCE_PD_S 11 +/* RTC_CNTL_INTER_RAM1_FORCE_PU : R/W ;bitpos:[10] ;default: 1'd1 ; */ +/*description: internal SRAM 1 force power up*/ +#define RTC_CNTL_INTER_RAM1_FORCE_PU (BIT(10)) +#define RTC_CNTL_INTER_RAM1_FORCE_PU_M (BIT(10)) +#define RTC_CNTL_INTER_RAM1_FORCE_PU_V 0x1 +#define RTC_CNTL_INTER_RAM1_FORCE_PU_S 10 +/* RTC_CNTL_INTER_RAM1_FORCE_PD : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: internal SRAM 1 force power down*/ +#define RTC_CNTL_INTER_RAM1_FORCE_PD (BIT(9)) +#define RTC_CNTL_INTER_RAM1_FORCE_PD_M (BIT(9)) +#define RTC_CNTL_INTER_RAM1_FORCE_PD_V 0x1 +#define RTC_CNTL_INTER_RAM1_FORCE_PD_S 9 +/* RTC_CNTL_INTER_RAM0_FORCE_PU : R/W ;bitpos:[8] ;default: 1'd1 ; */ +/*description: internal SRAM 0 force power up*/ +#define RTC_CNTL_INTER_RAM0_FORCE_PU (BIT(8)) +#define RTC_CNTL_INTER_RAM0_FORCE_PU_M (BIT(8)) +#define RTC_CNTL_INTER_RAM0_FORCE_PU_V 0x1 +#define RTC_CNTL_INTER_RAM0_FORCE_PU_S 8 +/* RTC_CNTL_INTER_RAM0_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: internal SRAM 0 force power down*/ +#define RTC_CNTL_INTER_RAM0_FORCE_PD (BIT(7)) +#define RTC_CNTL_INTER_RAM0_FORCE_PD_M (BIT(7)) +#define RTC_CNTL_INTER_RAM0_FORCE_PD_V 0x1 +#define RTC_CNTL_INTER_RAM0_FORCE_PD_S 7 +/* RTC_CNTL_ROM0_FORCE_PU : R/W ;bitpos:[6] ;default: 1'd1 ; */ +/*description: ROM force power up*/ +#define RTC_CNTL_ROM0_FORCE_PU (BIT(6)) +#define RTC_CNTL_ROM0_FORCE_PU_M (BIT(6)) +#define RTC_CNTL_ROM0_FORCE_PU_V 0x1 +#define RTC_CNTL_ROM0_FORCE_PU_S 6 +/* RTC_CNTL_ROM0_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: ROM force power down*/ +#define RTC_CNTL_ROM0_FORCE_PD (BIT(5)) +#define RTC_CNTL_ROM0_FORCE_PD_M (BIT(5)) +#define RTC_CNTL_ROM0_FORCE_PD_V 0x1 +#define RTC_CNTL_ROM0_FORCE_PD_S 5 +/* RTC_CNTL_LSLP_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: memories in digital core force no PD in sleep*/ +#define RTC_CNTL_LSLP_MEM_FORCE_PU (BIT(4)) +#define RTC_CNTL_LSLP_MEM_FORCE_PU_M (BIT(4)) +#define RTC_CNTL_LSLP_MEM_FORCE_PU_V 0x1 +#define RTC_CNTL_LSLP_MEM_FORCE_PU_S 4 +/* RTC_CNTL_LSLP_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: memories in digital core force PD in sleep*/ +#define RTC_CNTL_LSLP_MEM_FORCE_PD (BIT(3)) +#define RTC_CNTL_LSLP_MEM_FORCE_PD_M (BIT(3)) +#define RTC_CNTL_LSLP_MEM_FORCE_PD_V 0x1 +#define RTC_CNTL_LSLP_MEM_FORCE_PD_S 3 + +#define RTC_CNTL_DIG_ISO_REG (DR_REG_RTCCNTL_BASE + 0x88) +/* RTC_CNTL_DG_WRAP_FORCE_NOISO : R/W ;bitpos:[31] ;default: 1'd1 ; */ +/*description: digital core force no ISO*/ +#define RTC_CNTL_DG_WRAP_FORCE_NOISO (BIT(31)) +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_M (BIT(31)) +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_S 31 +/* RTC_CNTL_DG_WRAP_FORCE_ISO : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: digital core force ISO*/ +#define RTC_CNTL_DG_WRAP_FORCE_ISO (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_ISO_M (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_ISO_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_ISO_S 30 +/* RTC_CNTL_WIFI_FORCE_NOISO : R/W ;bitpos:[29] ;default: 1'd1 ; */ +/*description: wifi force no ISO*/ +#define RTC_CNTL_WIFI_FORCE_NOISO (BIT(29)) +#define RTC_CNTL_WIFI_FORCE_NOISO_M (BIT(29)) +#define RTC_CNTL_WIFI_FORCE_NOISO_V 0x1 +#define RTC_CNTL_WIFI_FORCE_NOISO_S 29 +/* RTC_CNTL_WIFI_FORCE_ISO : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: wifi force ISO*/ +#define RTC_CNTL_WIFI_FORCE_ISO (BIT(28)) +#define RTC_CNTL_WIFI_FORCE_ISO_M (BIT(28)) +#define RTC_CNTL_WIFI_FORCE_ISO_V 0x1 +#define RTC_CNTL_WIFI_FORCE_ISO_S 28 +/* RTC_CNTL_INTER_RAM4_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ +/*description: internal SRAM 4 force no ISO*/ +#define RTC_CNTL_INTER_RAM4_FORCE_NOISO (BIT(27)) +#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_M (BIT(27)) +#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_V 0x1 +#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_S 27 +/* RTC_CNTL_INTER_RAM4_FORCE_ISO : R/W ;bitpos:[26] ;default: 1'd0 ; */ +/*description: internal SRAM 4 force ISO*/ +#define RTC_CNTL_INTER_RAM4_FORCE_ISO (BIT(26)) +#define RTC_CNTL_INTER_RAM4_FORCE_ISO_M (BIT(26)) +#define RTC_CNTL_INTER_RAM4_FORCE_ISO_V 0x1 +#define RTC_CNTL_INTER_RAM4_FORCE_ISO_S 26 +/* RTC_CNTL_INTER_RAM3_FORCE_NOISO : R/W ;bitpos:[25] ;default: 1'd1 ; */ +/*description: internal SRAM 3 force no ISO*/ +#define RTC_CNTL_INTER_RAM3_FORCE_NOISO (BIT(25)) +#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_M (BIT(25)) +#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_V 0x1 +#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_S 25 +/* RTC_CNTL_INTER_RAM3_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: internal SRAM 3 force ISO*/ +#define RTC_CNTL_INTER_RAM3_FORCE_ISO (BIT(24)) +#define RTC_CNTL_INTER_RAM3_FORCE_ISO_M (BIT(24)) +#define RTC_CNTL_INTER_RAM3_FORCE_ISO_V 0x1 +#define RTC_CNTL_INTER_RAM3_FORCE_ISO_S 24 +/* RTC_CNTL_INTER_RAM2_FORCE_NOISO : R/W ;bitpos:[23] ;default: 1'd1 ; */ +/*description: internal SRAM 2 force no ISO*/ +#define RTC_CNTL_INTER_RAM2_FORCE_NOISO (BIT(23)) +#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_M (BIT(23)) +#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_V 0x1 +#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_S 23 +/* RTC_CNTL_INTER_RAM2_FORCE_ISO : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: internal SRAM 2 force ISO*/ +#define RTC_CNTL_INTER_RAM2_FORCE_ISO (BIT(22)) +#define RTC_CNTL_INTER_RAM2_FORCE_ISO_M (BIT(22)) +#define RTC_CNTL_INTER_RAM2_FORCE_ISO_V 0x1 +#define RTC_CNTL_INTER_RAM2_FORCE_ISO_S 22 +/* RTC_CNTL_INTER_RAM1_FORCE_NOISO : R/W ;bitpos:[21] ;default: 1'd1 ; */ +/*description: internal SRAM 1 force no ISO*/ +#define RTC_CNTL_INTER_RAM1_FORCE_NOISO (BIT(21)) +#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_M (BIT(21)) +#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_V 0x1 +#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_S 21 +/* RTC_CNTL_INTER_RAM1_FORCE_ISO : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: internal SRAM 1 force ISO*/ +#define RTC_CNTL_INTER_RAM1_FORCE_ISO (BIT(20)) +#define RTC_CNTL_INTER_RAM1_FORCE_ISO_M (BIT(20)) +#define RTC_CNTL_INTER_RAM1_FORCE_ISO_V 0x1 +#define RTC_CNTL_INTER_RAM1_FORCE_ISO_S 20 +/* RTC_CNTL_INTER_RAM0_FORCE_NOISO : R/W ;bitpos:[19] ;default: 1'd1 ; */ +/*description: internal SRAM 0 force no ISO*/ +#define RTC_CNTL_INTER_RAM0_FORCE_NOISO (BIT(19)) +#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_M (BIT(19)) +#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_V 0x1 +#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_S 19 +/* RTC_CNTL_INTER_RAM0_FORCE_ISO : R/W ;bitpos:[18] ;default: 1'd0 ; */ +/*description: internal SRAM 0 force ISO*/ +#define RTC_CNTL_INTER_RAM0_FORCE_ISO (BIT(18)) +#define RTC_CNTL_INTER_RAM0_FORCE_ISO_M (BIT(18)) +#define RTC_CNTL_INTER_RAM0_FORCE_ISO_V 0x1 +#define RTC_CNTL_INTER_RAM0_FORCE_ISO_S 18 +/* RTC_CNTL_ROM0_FORCE_NOISO : R/W ;bitpos:[17] ;default: 1'd1 ; */ +/*description: ROM force no ISO*/ +#define RTC_CNTL_ROM0_FORCE_NOISO (BIT(17)) +#define RTC_CNTL_ROM0_FORCE_NOISO_M (BIT(17)) +#define RTC_CNTL_ROM0_FORCE_NOISO_V 0x1 +#define RTC_CNTL_ROM0_FORCE_NOISO_S 17 +/* RTC_CNTL_ROM0_FORCE_ISO : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: ROM force ISO*/ +#define RTC_CNTL_ROM0_FORCE_ISO (BIT(16)) +#define RTC_CNTL_ROM0_FORCE_ISO_M (BIT(16)) +#define RTC_CNTL_ROM0_FORCE_ISO_V 0x1 +#define RTC_CNTL_ROM0_FORCE_ISO_S 16 +/* RTC_CNTL_DG_PAD_FORCE_HOLD : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: digital pad force hold*/ +#define RTC_CNTL_DG_PAD_FORCE_HOLD (BIT(15)) +#define RTC_CNTL_DG_PAD_FORCE_HOLD_M (BIT(15)) +#define RTC_CNTL_DG_PAD_FORCE_HOLD_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_HOLD_S 15 +/* RTC_CNTL_DG_PAD_FORCE_UNHOLD : R/W ;bitpos:[14] ;default: 1'd1 ; */ +/*description: digital pad force un-hold*/ +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD (BIT(14)) +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M (BIT(14)) +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S 14 +/* RTC_CNTL_DG_PAD_FORCE_ISO : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: digital pad force ISO*/ +#define RTC_CNTL_DG_PAD_FORCE_ISO (BIT(13)) +#define RTC_CNTL_DG_PAD_FORCE_ISO_M (BIT(13)) +#define RTC_CNTL_DG_PAD_FORCE_ISO_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_ISO_S 13 +/* RTC_CNTL_DG_PAD_FORCE_NOISO : R/W ;bitpos:[12] ;default: 1'd1 ; */ +/*description: digital pad force no ISO*/ +#define RTC_CNTL_DG_PAD_FORCE_NOISO (BIT(12)) +#define RTC_CNTL_DG_PAD_FORCE_NOISO_M (BIT(12)) +#define RTC_CNTL_DG_PAD_FORCE_NOISO_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_NOISO_S 12 +/* RTC_CNTL_DG_PAD_AUTOHOLD_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: digital pad enable auto-hold*/ +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN (BIT(11)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M (BIT(11)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_V 0x1 +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S 11 +/* RTC_CNTL_CLR_DG_PAD_AUTOHOLD : WO ;bitpos:[10] ;default: 1'd0 ; */ +/*description: wtite only register to clear digital pad auto-hold*/ +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD (BIT(10)) +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M (BIT(10)) +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V 0x1 +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S 10 +/* RTC_CNTL_DG_PAD_AUTOHOLD : RO ;bitpos:[9] ;default: 1'd0 ; */ +/*description: read only register to indicate digital pad auto-hold status*/ +#define RTC_CNTL_DG_PAD_AUTOHOLD (BIT(9)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_M (BIT(9)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_V 0x1 +#define RTC_CNTL_DG_PAD_AUTOHOLD_S 9 +/* RTC_CNTL_DIG_ISO_FORCE_ON : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_DIG_ISO_FORCE_ON (BIT(8)) +#define RTC_CNTL_DIG_ISO_FORCE_ON_M (BIT(8)) +#define RTC_CNTL_DIG_ISO_FORCE_ON_V 0x1 +#define RTC_CNTL_DIG_ISO_FORCE_ON_S 8 +/* RTC_CNTL_DIG_ISO_FORCE_OFF : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_DIG_ISO_FORCE_OFF (BIT(7)) +#define RTC_CNTL_DIG_ISO_FORCE_OFF_M (BIT(7)) +#define RTC_CNTL_DIG_ISO_FORCE_OFF_V 0x1 +#define RTC_CNTL_DIG_ISO_FORCE_OFF_S 7 + +#define RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x8c) +/* RTC_CNTL_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: enable RTC WDT*/ +#define RTC_CNTL_WDT_EN (BIT(31)) +#define RTC_CNTL_WDT_EN_M (BIT(31)) +#define RTC_CNTL_WDT_EN_V 0x1 +#define RTC_CNTL_WDT_EN_S 31 +/* RTC_CNTL_WDT_STG0 : R/W ;bitpos:[30:28] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en 2: CPU reset stage en 3: system reset + stage en 4: RTC reset stage en*/ +#define RTC_CNTL_WDT_STG0 0x00000007 +#define RTC_CNTL_WDT_STG0_M ((RTC_CNTL_WDT_STG0_V)<<(RTC_CNTL_WDT_STG0_S)) +#define RTC_CNTL_WDT_STG0_V 0x7 +#define RTC_CNTL_WDT_STG0_S 28 +/* RTC_CNTL_WDT_STG1 : R/W ;bitpos:[27:25] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en 2: CPU reset stage en 3: system reset + stage en 4: RTC reset stage en*/ +#define RTC_CNTL_WDT_STG1 0x00000007 +#define RTC_CNTL_WDT_STG1_M ((RTC_CNTL_WDT_STG1_V)<<(RTC_CNTL_WDT_STG1_S)) +#define RTC_CNTL_WDT_STG1_V 0x7 +#define RTC_CNTL_WDT_STG1_S 25 +/* RTC_CNTL_WDT_STG2 : R/W ;bitpos:[24:22] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en 2: CPU reset stage en 3: system reset + stage en 4: RTC reset stage en*/ +#define RTC_CNTL_WDT_STG2 0x00000007 +#define RTC_CNTL_WDT_STG2_M ((RTC_CNTL_WDT_STG2_V)<<(RTC_CNTL_WDT_STG2_S)) +#define RTC_CNTL_WDT_STG2_V 0x7 +#define RTC_CNTL_WDT_STG2_S 22 +/* RTC_CNTL_WDT_STG3 : R/W ;bitpos:[21:19] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en 2: CPU reset stage en 3: system reset + stage en 4: RTC reset stage en*/ +#define RTC_CNTL_WDT_STG3 0x00000007 +#define RTC_CNTL_WDT_STG3_M ((RTC_CNTL_WDT_STG3_V)<<(RTC_CNTL_WDT_STG3_S)) +#define RTC_CNTL_WDT_STG3_V 0x7 +#define RTC_CNTL_WDT_STG3_S 19 +/* RTC_CNTL_WDT_EDGE_INT_EN : R/W ;bitpos:[18] ;default: 1'h0 ; */ +/*description: N/A*/ +#define RTC_CNTL_WDT_EDGE_INT_EN (BIT(18)) +#define RTC_CNTL_WDT_EDGE_INT_EN_M (BIT(18)) +#define RTC_CNTL_WDT_EDGE_INT_EN_V 0x1 +#define RTC_CNTL_WDT_EDGE_INT_EN_S 18 +/* RTC_CNTL_WDT_LEVEL_INT_EN : R/W ;bitpos:[17] ;default: 1'h0 ; */ +/*description: N/A*/ +#define RTC_CNTL_WDT_LEVEL_INT_EN (BIT(17)) +#define RTC_CNTL_WDT_LEVEL_INT_EN_M (BIT(17)) +#define RTC_CNTL_WDT_LEVEL_INT_EN_V 0x1 +#define RTC_CNTL_WDT_LEVEL_INT_EN_S 17 +/* RTC_CNTL_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[16:14] ;default: 3'h1 ; */ +/*description: CPU reset counter length*/ +#define RTC_CNTL_WDT_CPU_RESET_LENGTH 0x00000007 +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_M ((RTC_CNTL_WDT_CPU_RESET_LENGTH_V)<<(RTC_CNTL_WDT_CPU_RESET_LENGTH_S)) +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_V 0x7 +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_S 14 +/* RTC_CNTL_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[13:11] ;default: 3'h1 ; */ +/*description: system reset counter length*/ +#define RTC_CNTL_WDT_SYS_RESET_LENGTH 0x00000007 +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_M ((RTC_CNTL_WDT_SYS_RESET_LENGTH_V)<<(RTC_CNTL_WDT_SYS_RESET_LENGTH_S)) +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_V 0x7 +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_S 11 +/* RTC_CNTL_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[10] ;default: 1'h1 ; */ +/*description: enable WDT in flash boot*/ +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN (BIT(10)) +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M (BIT(10)) +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V 0x1 +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S 10 +/* RTC_CNTL_WDT_PROCPU_RESET_EN : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: enable WDT reset PRO CPU*/ +#define RTC_CNTL_WDT_PROCPU_RESET_EN (BIT(9)) +#define RTC_CNTL_WDT_PROCPU_RESET_EN_M (BIT(9)) +#define RTC_CNTL_WDT_PROCPU_RESET_EN_V 0x1 +#define RTC_CNTL_WDT_PROCPU_RESET_EN_S 9 +/* RTC_CNTL_WDT_APPCPU_RESET_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: enable WDT reset APP CPU*/ +#define RTC_CNTL_WDT_APPCPU_RESET_EN (BIT(8)) +#define RTC_CNTL_WDT_APPCPU_RESET_EN_M (BIT(8)) +#define RTC_CNTL_WDT_APPCPU_RESET_EN_V 0x1 +#define RTC_CNTL_WDT_APPCPU_RESET_EN_S 8 +/* RTC_CNTL_WDT_PAUSE_IN_SLP : R/W ;bitpos:[7] ;default: 1'd1 ; */ +/*description: pause WDT in sleep*/ +#define RTC_CNTL_WDT_PAUSE_IN_SLP (BIT(7)) +#define RTC_CNTL_WDT_PAUSE_IN_SLP_M (BIT(7)) +#define RTC_CNTL_WDT_PAUSE_IN_SLP_V 0x1 +#define RTC_CNTL_WDT_PAUSE_IN_SLP_S 7 + +#define RTC_CNTL_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0x90) +/* RTC_CNTL_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd128000 ; */ +/*description: */ +#define RTC_CNTL_WDT_STG0_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG0_HOLD_M ((RTC_CNTL_WDT_STG0_HOLD_V)<<(RTC_CNTL_WDT_STG0_HOLD_S)) +#define RTC_CNTL_WDT_STG0_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG0_HOLD_S 0 + +#define RTC_CNTL_WDTCONFIG2_REG (DR_REG_RTCCNTL_BASE + 0x94) +/* RTC_CNTL_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'd80000 ; */ +/*description: */ +#define RTC_CNTL_WDT_STG1_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG1_HOLD_M ((RTC_CNTL_WDT_STG1_HOLD_V)<<(RTC_CNTL_WDT_STG1_HOLD_S)) +#define RTC_CNTL_WDT_STG1_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG1_HOLD_S 0 + +#define RTC_CNTL_WDTCONFIG3_REG (DR_REG_RTCCNTL_BASE + 0x98) +/* RTC_CNTL_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ +/*description: */ +#define RTC_CNTL_WDT_STG2_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG2_HOLD_M ((RTC_CNTL_WDT_STG2_HOLD_V)<<(RTC_CNTL_WDT_STG2_HOLD_S)) +#define RTC_CNTL_WDT_STG2_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG2_HOLD_S 0 + +#define RTC_CNTL_WDTCONFIG4_REG (DR_REG_RTCCNTL_BASE + 0x9c) +/* RTC_CNTL_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ +/*description: */ +#define RTC_CNTL_WDT_STG3_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG3_HOLD_M ((RTC_CNTL_WDT_STG3_HOLD_V)<<(RTC_CNTL_WDT_STG3_HOLD_S)) +#define RTC_CNTL_WDT_STG3_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG3_HOLD_S 0 + +#define RTC_CNTL_WDTFEED_REG (DR_REG_RTCCNTL_BASE + 0xa0) +/* RTC_CNTL_WDT_FEED : WO ;bitpos:[31] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_WDT_FEED (BIT(31)) +#define RTC_CNTL_WDT_FEED_M (BIT(31)) +#define RTC_CNTL_WDT_FEED_V 0x1 +#define RTC_CNTL_WDT_FEED_S 31 + +#define RTC_CNTL_WDTWPROTECT_REG (DR_REG_RTCCNTL_BASE + 0xa4) +/* RTC_CNTL_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */ +/*description: */ +#define RTC_CNTL_WDT_WKEY 0xFFFFFFFF +#define RTC_CNTL_WDT_WKEY_M ((RTC_CNTL_WDT_WKEY_V)<<(RTC_CNTL_WDT_WKEY_S)) +#define RTC_CNTL_WDT_WKEY_V 0xFFFFFFFF +#define RTC_CNTL_WDT_WKEY_S 0 + +#define RTC_CNTL_TEST_MUX_REG (DR_REG_RTCCNTL_BASE + 0xa8) +/* RTC_CNTL_DTEST_RTC : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: DTEST_RTC*/ +#define RTC_CNTL_DTEST_RTC 0x00000003 +#define RTC_CNTL_DTEST_RTC_M ((RTC_CNTL_DTEST_RTC_V)<<(RTC_CNTL_DTEST_RTC_S)) +#define RTC_CNTL_DTEST_RTC_V 0x3 +#define RTC_CNTL_DTEST_RTC_S 30 +/* RTC_CNTL_ENT_RTC : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: ENT_RTC*/ +#define RTC_CNTL_ENT_RTC (BIT(29)) +#define RTC_CNTL_ENT_RTC_M (BIT(29)) +#define RTC_CNTL_ENT_RTC_V 0x1 +#define RTC_CNTL_ENT_RTC_S 29 + +#define RTC_CNTL_SW_CPU_STALL_REG (DR_REG_RTCCNTL_BASE + 0xac) +/* RTC_CNTL_SW_STALL_PROCPU_C1 : R/W ;bitpos:[31:26] ;default: 6'b0 ; */ +/*description: {reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == + 0x86 will stall PRO CPU*/ +#define RTC_CNTL_SW_STALL_PROCPU_C1 0x0000003F +#define RTC_CNTL_SW_STALL_PROCPU_C1_M ((RTC_CNTL_SW_STALL_PROCPU_C1_V)<<(RTC_CNTL_SW_STALL_PROCPU_C1_S)) +#define RTC_CNTL_SW_STALL_PROCPU_C1_V 0x3F +#define RTC_CNTL_SW_STALL_PROCPU_C1_S 26 +/* RTC_CNTL_SW_STALL_APPCPU_C1 : R/W ;bitpos:[25:20] ;default: 6'b0 ; */ +/*description: {reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == + 0x86 will stall APP CPU*/ +#define RTC_CNTL_SW_STALL_APPCPU_C1 0x0000003F +#define RTC_CNTL_SW_STALL_APPCPU_C1_M ((RTC_CNTL_SW_STALL_APPCPU_C1_V)<<(RTC_CNTL_SW_STALL_APPCPU_C1_S)) +#define RTC_CNTL_SW_STALL_APPCPU_C1_V 0x3F +#define RTC_CNTL_SW_STALL_APPCPU_C1_S 20 + +#define RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0xb0) +/* RTC_CNTL_SCRATCH4 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: 32-bit general purpose retention register*/ +#define RTC_CNTL_SCRATCH4 0xFFFFFFFF +#define RTC_CNTL_SCRATCH4_M ((RTC_CNTL_SCRATCH4_V)<<(RTC_CNTL_SCRATCH4_S)) +#define RTC_CNTL_SCRATCH4_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH4_S 0 + +#define RTC_CNTL_STORE5_REG (DR_REG_RTCCNTL_BASE + 0xb4) +/* RTC_CNTL_SCRATCH5 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: 32-bit general purpose retention register*/ +#define RTC_CNTL_SCRATCH5 0xFFFFFFFF +#define RTC_CNTL_SCRATCH5_M ((RTC_CNTL_SCRATCH5_V)<<(RTC_CNTL_SCRATCH5_S)) +#define RTC_CNTL_SCRATCH5_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH5_S 0 + +#define RTC_CNTL_STORE6_REG (DR_REG_RTCCNTL_BASE + 0xb8) +/* RTC_CNTL_SCRATCH6 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: 32-bit general purpose retention register*/ +#define RTC_CNTL_SCRATCH6 0xFFFFFFFF +#define RTC_CNTL_SCRATCH6_M ((RTC_CNTL_SCRATCH6_V)<<(RTC_CNTL_SCRATCH6_S)) +#define RTC_CNTL_SCRATCH6_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH6_S 0 + +#define RTC_CNTL_STORE7_REG (DR_REG_RTCCNTL_BASE + 0xbc) +/* RTC_CNTL_SCRATCH7 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: 32-bit general purpose retention register*/ +#define RTC_CNTL_SCRATCH7 0xFFFFFFFF +#define RTC_CNTL_SCRATCH7_M ((RTC_CNTL_SCRATCH7_V)<<(RTC_CNTL_SCRATCH7_S)) +#define RTC_CNTL_SCRATCH7_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH7_S 0 + +#define RTC_CNTL_DIAG0_REG (DR_REG_RTCCNTL_BASE + 0xc0) +/* RTC_CNTL_LOW_POWER_DIAG0 : RO ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_LOW_POWER_DIAG0 0xFFFFFFFF +#define RTC_CNTL_LOW_POWER_DIAG0_M ((RTC_CNTL_LOW_POWER_DIAG0_V)<<(RTC_CNTL_LOW_POWER_DIAG0_S)) +#define RTC_CNTL_LOW_POWER_DIAG0_V 0xFFFFFFFF +#define RTC_CNTL_LOW_POWER_DIAG0_S 0 + +#define RTC_CNTL_DIAG1_REG (DR_REG_RTCCNTL_BASE + 0xc4) +/* RTC_CNTL_LOW_POWER_DIAG1 : RO ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_LOW_POWER_DIAG1 0xFFFFFFFF +#define RTC_CNTL_LOW_POWER_DIAG1_M ((RTC_CNTL_LOW_POWER_DIAG1_V)<<(RTC_CNTL_LOW_POWER_DIAG1_S)) +#define RTC_CNTL_LOW_POWER_DIAG1_V 0xFFFFFFFF +#define RTC_CNTL_LOW_POWER_DIAG1_S 0 + +#define RTC_CNTL_HOLD_FORCE_REG (DR_REG_RTCCNTL_BASE + 0xc8) +/* RTC_CNTL_X32N_HOLD_FORCE : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_X32N_HOLD_FORCE (BIT(17)) +#define RTC_CNTL_X32N_HOLD_FORCE_M (BIT(17)) +#define RTC_CNTL_X32N_HOLD_FORCE_V 0x1 +#define RTC_CNTL_X32N_HOLD_FORCE_S 17 +/* RTC_CNTL_X32P_HOLD_FORCE : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_X32P_HOLD_FORCE (BIT(16)) +#define RTC_CNTL_X32P_HOLD_FORCE_M (BIT(16)) +#define RTC_CNTL_X32P_HOLD_FORCE_V 0x1 +#define RTC_CNTL_X32P_HOLD_FORCE_S 16 +/* RTC_CNTL_TOUCH_PAD7_HOLD_FORCE : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE (BIT(15)) +#define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_M (BIT(15)) +#define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_S 15 +/* RTC_CNTL_TOUCH_PAD6_HOLD_FORCE : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE (BIT(14)) +#define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_M (BIT(14)) +#define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_S 14 +/* RTC_CNTL_TOUCH_PAD5_HOLD_FORCE : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE (BIT(13)) +#define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_M (BIT(13)) +#define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_S 13 +/* RTC_CNTL_TOUCH_PAD4_HOLD_FORCE : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE (BIT(12)) +#define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_M (BIT(12)) +#define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_S 12 +/* RTC_CNTL_TOUCH_PAD3_HOLD_FORCE : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE (BIT(11)) +#define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_M (BIT(11)) +#define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_S 11 +/* RTC_CNTL_TOUCH_PAD2_HOLD_FORCE : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE (BIT(10)) +#define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_M (BIT(10)) +#define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_S 10 +/* RTC_CNTL_TOUCH_PAD1_HOLD_FORCE : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE (BIT(9)) +#define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_M (BIT(9)) +#define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_S 9 +/* RTC_CNTL_TOUCH_PAD0_HOLD_FORCE : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE (BIT(8)) +#define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_M (BIT(8)) +#define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_S 8 +/* RTC_CNTL_SENSE4_HOLD_FORCE : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_SENSE4_HOLD_FORCE (BIT(7)) +#define RTC_CNTL_SENSE4_HOLD_FORCE_M (BIT(7)) +#define RTC_CNTL_SENSE4_HOLD_FORCE_V 0x1 +#define RTC_CNTL_SENSE4_HOLD_FORCE_S 7 +/* RTC_CNTL_SENSE3_HOLD_FORCE : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_SENSE3_HOLD_FORCE (BIT(6)) +#define RTC_CNTL_SENSE3_HOLD_FORCE_M (BIT(6)) +#define RTC_CNTL_SENSE3_HOLD_FORCE_V 0x1 +#define RTC_CNTL_SENSE3_HOLD_FORCE_S 6 +/* RTC_CNTL_SENSE2_HOLD_FORCE : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_SENSE2_HOLD_FORCE (BIT(5)) +#define RTC_CNTL_SENSE2_HOLD_FORCE_M (BIT(5)) +#define RTC_CNTL_SENSE2_HOLD_FORCE_V 0x1 +#define RTC_CNTL_SENSE2_HOLD_FORCE_S 5 +/* RTC_CNTL_SENSE1_HOLD_FORCE : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_SENSE1_HOLD_FORCE (BIT(4)) +#define RTC_CNTL_SENSE1_HOLD_FORCE_M (BIT(4)) +#define RTC_CNTL_SENSE1_HOLD_FORCE_V 0x1 +#define RTC_CNTL_SENSE1_HOLD_FORCE_S 4 +/* RTC_CNTL_PDAC2_HOLD_FORCE : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_PDAC2_HOLD_FORCE (BIT(3)) +#define RTC_CNTL_PDAC2_HOLD_FORCE_M (BIT(3)) +#define RTC_CNTL_PDAC2_HOLD_FORCE_V 0x1 +#define RTC_CNTL_PDAC2_HOLD_FORCE_S 3 +/* RTC_CNTL_PDAC1_HOLD_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_PDAC1_HOLD_FORCE (BIT(2)) +#define RTC_CNTL_PDAC1_HOLD_FORCE_M (BIT(2)) +#define RTC_CNTL_PDAC1_HOLD_FORCE_V 0x1 +#define RTC_CNTL_PDAC1_HOLD_FORCE_S 2 +/* RTC_CNTL_ADC2_HOLD_FORCE : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_ADC2_HOLD_FORCE (BIT(1)) +#define RTC_CNTL_ADC2_HOLD_FORCE_M (BIT(1)) +#define RTC_CNTL_ADC2_HOLD_FORCE_V 0x1 +#define RTC_CNTL_ADC2_HOLD_FORCE_S 1 +/* RTC_CNTL_ADC1_HOLD_FORCE : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_ADC1_HOLD_FORCE (BIT(0)) +#define RTC_CNTL_ADC1_HOLD_FORCE_M (BIT(0)) +#define RTC_CNTL_ADC1_HOLD_FORCE_V 0x1 +#define RTC_CNTL_ADC1_HOLD_FORCE_S 0 + +#define RTC_CNTL_EXT_WAKEUP1_REG (DR_REG_RTCCNTL_BASE + 0xcc) +/* RTC_CNTL_EXT_WAKEUP1_STATUS_CLR : WO ;bitpos:[18] ;default: 1'd0 ; */ +/*description: clear ext wakeup1 status*/ +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR (BIT(18)) +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_M (BIT(18)) +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_V 0x1 +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_S 18 +/* RTC_CNTL_EXT_WAKEUP1_SEL : R/W ;bitpos:[17:0] ;default: 18'd0 ; */ +/*description: Bitmap to select RTC pads for ext wakeup1*/ +#define RTC_CNTL_EXT_WAKEUP1_SEL 0x0003FFFF +#define RTC_CNTL_EXT_WAKEUP1_SEL_M ((RTC_CNTL_EXT_WAKEUP1_SEL_V)<<(RTC_CNTL_EXT_WAKEUP1_SEL_S)) +#define RTC_CNTL_EXT_WAKEUP1_SEL_V 0x3FFFF +#define RTC_CNTL_EXT_WAKEUP1_SEL_S 0 + +#define RTC_CNTL_EXT_WAKEUP1_STATUS_REG (DR_REG_RTCCNTL_BASE + 0xd0) +/* RTC_CNTL_EXT_WAKEUP1_STATUS : RO ;bitpos:[17:0] ;default: 18'd0 ; */ +/*description: ext wakeup1 status*/ +#define RTC_CNTL_EXT_WAKEUP1_STATUS 0x0003FFFF +#define RTC_CNTL_EXT_WAKEUP1_STATUS_M ((RTC_CNTL_EXT_WAKEUP1_STATUS_V)<<(RTC_CNTL_EXT_WAKEUP1_STATUS_S)) +#define RTC_CNTL_EXT_WAKEUP1_STATUS_V 0x3FFFF +#define RTC_CNTL_EXT_WAKEUP1_STATUS_S 0 + +#define RTC_CNTL_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0xd4) +/* RTC_CNTL_BROWN_OUT_DET : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: brown out detect*/ +#define RTC_CNTL_BROWN_OUT_DET (BIT(31)) +#define RTC_CNTL_BROWN_OUT_DET_M (BIT(31)) +#define RTC_CNTL_BROWN_OUT_DET_V 0x1 +#define RTC_CNTL_BROWN_OUT_DET_S 31 +/* RTC_CNTL_BROWN_OUT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: enable brown out*/ +#define RTC_CNTL_BROWN_OUT_ENA (BIT(30)) +#define RTC_CNTL_BROWN_OUT_ENA_M (BIT(30)) +#define RTC_CNTL_BROWN_OUT_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_ENA_S 30 +/* RTC_CNTL_DBROWN_OUT_THRES : R/W ;bitpos:[29:27] ;default: 3'b010 ; */ +/*description: brown out threshold*/ +#define RTC_CNTL_DBROWN_OUT_THRES 0x00000007 +#define RTC_CNTL_DBROWN_OUT_THRES_M ((RTC_CNTL_DBROWN_OUT_THRES_V)<<(RTC_CNTL_DBROWN_OUT_THRES_S)) +#define RTC_CNTL_DBROWN_OUT_THRES_V 0x7 +#define RTC_CNTL_DBROWN_OUT_THRES_S 27 +/* RTC_CNTL_BROWN_OUT_RST_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: enable brown out reset*/ +#define RTC_CNTL_BROWN_OUT_RST_ENA (BIT(26)) +#define RTC_CNTL_BROWN_OUT_RST_ENA_M (BIT(26)) +#define RTC_CNTL_BROWN_OUT_RST_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_RST_ENA_S 26 +/* RTC_CNTL_BROWN_OUT_RST_WAIT : R/W ;bitpos:[25:16] ;default: 10'h3ff ; */ +/*description: brown out reset wait cycles*/ +#define RTC_CNTL_BROWN_OUT_RST_WAIT 0x000003FF +#define RTC_CNTL_BROWN_OUT_RST_WAIT_M ((RTC_CNTL_BROWN_OUT_RST_WAIT_V)<<(RTC_CNTL_BROWN_OUT_RST_WAIT_S)) +#define RTC_CNTL_BROWN_OUT_RST_WAIT_V 0x3FF +#define RTC_CNTL_BROWN_OUT_RST_WAIT_S 16 +/* RTC_CNTL_BROWN_OUT_PD_RF_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: enable power down RF when brown out happens*/ +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA (BIT(15)) +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M (BIT(15)) +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S 15 +/* RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: enable close flash when brown out happens*/ +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA (BIT(14)) +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M (BIT(14)) +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S 14 + +#define RTC_MEM_CONF (DR_REG_RTCCNTL_BASE + 0x40 * 4) +#define RTC_MEM_CRC_FINISH (BIT(31)) +#define RTC_MEM_CRC_FINISH_M (BIT(31)) +#define RTC_MEM_CRC_FINISH_V 0x1 +#define RTC_MEM_CRC_FINISH_S (31) +#define RTC_MEM_CRC_LEN (0x7ff) +#define RTC_MEM_CRC_LEN_M ((RTC_MEM_CRC_LEN_V)<<(RTC_MEM_CRC_LEN_S)) +#define RTC_MEM_CRC_LEN_V (0x7ff) +#define RTC_MEM_CRC_LEN_S (20) +#define RTC_MEM_CRC_ADDR (0x7ff) +#define RTC_MEM_CRC_ADDR_M ((RTC_MEM_CRC_ADDR_V)<<(RTC_MEM_CRC_ADDR_S)) +#define RTC_MEM_CRC_ADDR_V (0x7ff) +#define RTC_MEM_CRC_ADDR_S (9) +#define RTC_MEM_CRC_START (BIT(8)) +#define RTC_MEM_CRC_START_M (BIT(8)) +#define RTC_MEM_CRC_START_V 0x1 +#define RTC_MEM_CRC_START_S (8) +#define RTC_MEM_PID_CONF (0xff) +#define RTC_MEM_PID_CONF_M (0xff) +#define RTC_MEM_PID_CONF_V (0xff) +#define RTC_MEM_PID_CONF_S (0) + +#define RTC_MEM_CRC_RES (DR_REG_RTCCNTL_BASE + 0x41 * 4) + +#define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x13c) +/* RTC_CNTL_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h1604280 ; */ +/*description: */ +#define RTC_CNTL_CNTL_DATE 0x0FFFFFFF +#define RTC_CNTL_CNTL_DATE_M ((RTC_CNTL_CNTL_DATE_V)<<(RTC_CNTL_CNTL_DATE_S)) +#define RTC_CNTL_CNTL_DATE_V 0xFFFFFFF +#define RTC_CNTL_CNTL_DATE_S 0 +#define RTC_CNTL_RTC_CNTL_DATE_VERSION 0x1604280 + + + + +#endif /*_SOC_RTC_CNTL_REG_H_ */ + + diff --git a/tools/sdk/include/esp32/soc/rtc_io_reg.h b/tools/sdk/include/esp32/soc/rtc_io_reg.h new file mode 100644 index 00000000..086e8b76 --- /dev/null +++ b/tools/sdk/include/esp32/soc/rtc_io_reg.h @@ -0,0 +1,1951 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_RTC_IO_REG_H_ +#define _SOC_RTC_IO_REG_H_ + + +#include "soc.h" +#define RTC_GPIO_OUT_REG (DR_REG_RTCIO_BASE + 0x0) +/* RTC_GPIO_OUT_DATA : R/W ;bitpos:[31:14] ;default: 0 ; */ +/*description: GPIO0~17 output value*/ +#define RTC_GPIO_OUT_DATA 0x0003FFFF +#define RTC_GPIO_OUT_DATA_M ((RTC_GPIO_OUT_DATA_V)<<(RTC_GPIO_OUT_DATA_S)) +#define RTC_GPIO_OUT_DATA_V 0x3FFFF +#define RTC_GPIO_OUT_DATA_S 14 + +#define RTC_GPIO_OUT_W1TS_REG (DR_REG_RTCIO_BASE + 0x4) +/* RTC_GPIO_OUT_DATA_W1TS : WO ;bitpos:[31:14] ;default: 0 ; */ +/*description: GPIO0~17 output value write 1 to set*/ +#define RTC_GPIO_OUT_DATA_W1TS 0x0003FFFF +#define RTC_GPIO_OUT_DATA_W1TS_M ((RTC_GPIO_OUT_DATA_W1TS_V)<<(RTC_GPIO_OUT_DATA_W1TS_S)) +#define RTC_GPIO_OUT_DATA_W1TS_V 0x3FFFF +#define RTC_GPIO_OUT_DATA_W1TS_S 14 + +#define RTC_GPIO_OUT_W1TC_REG (DR_REG_RTCIO_BASE + 0x8) +/* RTC_GPIO_OUT_DATA_W1TC : WO ;bitpos:[31:14] ;default: 0 ; */ +/*description: GPIO0~17 output value write 1 to clear*/ +#define RTC_GPIO_OUT_DATA_W1TC 0x0003FFFF +#define RTC_GPIO_OUT_DATA_W1TC_M ((RTC_GPIO_OUT_DATA_W1TC_V)<<(RTC_GPIO_OUT_DATA_W1TC_S)) +#define RTC_GPIO_OUT_DATA_W1TC_V 0x3FFFF +#define RTC_GPIO_OUT_DATA_W1TC_S 14 + +#define RTC_GPIO_ENABLE_REG (DR_REG_RTCIO_BASE + 0xc) +/* RTC_GPIO_ENABLE : R/W ;bitpos:[31:14] ;default: 0 ; */ +/*description: GPIO0~17 output enable*/ +#define RTC_GPIO_ENABLE 0x0003FFFF +#define RTC_GPIO_ENABLE_M ((RTC_GPIO_ENABLE_V)<<(RTC_GPIO_ENABLE_S)) +#define RTC_GPIO_ENABLE_V 0x3FFFF +#define RTC_GPIO_ENABLE_S 14 + +#define RTC_GPIO_ENABLE_W1TS_REG (DR_REG_RTCIO_BASE + 0x10) +/* RTC_GPIO_ENABLE_W1TS : WO ;bitpos:[31:14] ;default: 0 ; */ +/*description: GPIO0~17 output enable write 1 to set*/ +#define RTC_GPIO_ENABLE_W1TS 0x0003FFFF +#define RTC_GPIO_ENABLE_W1TS_M ((RTC_GPIO_ENABLE_W1TS_V)<<(RTC_GPIO_ENABLE_W1TS_S)) +#define RTC_GPIO_ENABLE_W1TS_V 0x3FFFF +#define RTC_GPIO_ENABLE_W1TS_S 14 + +#define RTC_GPIO_ENABLE_W1TC_REG (DR_REG_RTCIO_BASE + 0x14) +/* RTC_GPIO_ENABLE_W1TC : WO ;bitpos:[31:14] ;default: 0 ; */ +/*description: GPIO0~17 output enable write 1 to clear*/ +#define RTC_GPIO_ENABLE_W1TC 0x0003FFFF +#define RTC_GPIO_ENABLE_W1TC_M ((RTC_GPIO_ENABLE_W1TC_V)<<(RTC_GPIO_ENABLE_W1TC_S)) +#define RTC_GPIO_ENABLE_W1TC_V 0x3FFFF +#define RTC_GPIO_ENABLE_W1TC_S 14 + +#define RTC_GPIO_STATUS_REG (DR_REG_RTCIO_BASE + 0x18) +/* RTC_GPIO_STATUS_INT : R/W ;bitpos:[31:14] ;default: 0 ; */ +/*description: GPIO0~17 interrupt status*/ +#define RTC_GPIO_STATUS_INT 0x0003FFFF +#define RTC_GPIO_STATUS_INT_M ((RTC_GPIO_STATUS_INT_V)<<(RTC_GPIO_STATUS_INT_S)) +#define RTC_GPIO_STATUS_INT_V 0x3FFFF +#define RTC_GPIO_STATUS_INT_S 14 + +#define RTC_GPIO_STATUS_W1TS_REG (DR_REG_RTCIO_BASE + 0x1c) +/* RTC_GPIO_STATUS_INT_W1TS : WO ;bitpos:[31:14] ;default: 0 ; */ +/*description: GPIO0~17 interrupt status write 1 to set*/ +#define RTC_GPIO_STATUS_INT_W1TS 0x0003FFFF +#define RTC_GPIO_STATUS_INT_W1TS_M ((RTC_GPIO_STATUS_INT_W1TS_V)<<(RTC_GPIO_STATUS_INT_W1TS_S)) +#define RTC_GPIO_STATUS_INT_W1TS_V 0x3FFFF +#define RTC_GPIO_STATUS_INT_W1TS_S 14 + +#define RTC_GPIO_STATUS_W1TC_REG (DR_REG_RTCIO_BASE + 0x20) +/* RTC_GPIO_STATUS_INT_W1TC : WO ;bitpos:[31:14] ;default: 0 ; */ +/*description: GPIO0~17 interrupt status write 1 to clear*/ +#define RTC_GPIO_STATUS_INT_W1TC 0x0003FFFF +#define RTC_GPIO_STATUS_INT_W1TC_M ((RTC_GPIO_STATUS_INT_W1TC_V)<<(RTC_GPIO_STATUS_INT_W1TC_S)) +#define RTC_GPIO_STATUS_INT_W1TC_V 0x3FFFF +#define RTC_GPIO_STATUS_INT_W1TC_S 14 + +#define RTC_GPIO_IN_REG (DR_REG_RTCIO_BASE + 0x24) +/* RTC_GPIO_IN_NEXT : RO ;bitpos:[31:14] ;default: ; */ +/*description: GPIO0~17 input value*/ +#define RTC_GPIO_IN_NEXT 0x0003FFFF +#define RTC_GPIO_IN_NEXT_M ((RTC_GPIO_IN_NEXT_V)<<(RTC_GPIO_IN_NEXT_S)) +#define RTC_GPIO_IN_NEXT_V 0x3FFFF +#define RTC_GPIO_IN_NEXT_S 14 + +#define RTC_GPIO_PIN0_REG (DR_REG_RTCIO_BASE + 0x28) +/* RTC_GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN0_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN0_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN0_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN0_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN0_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN0_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN0_INT_TYPE_M ((RTC_GPIO_PIN0_INT_TYPE_V)<<(RTC_GPIO_PIN0_INT_TYPE_S)) +#define RTC_GPIO_PIN0_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN0_INT_TYPE_S 7 +/* RTC_GPIO_PIN0_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN0_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN0_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN0_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN0_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN1_REG (DR_REG_RTCIO_BASE + 0x2c) +/* RTC_GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN1_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN1_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN1_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN1_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN1_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN1_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN1_INT_TYPE_M ((RTC_GPIO_PIN1_INT_TYPE_V)<<(RTC_GPIO_PIN1_INT_TYPE_S)) +#define RTC_GPIO_PIN1_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN1_INT_TYPE_S 7 +/* RTC_GPIO_PIN1_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN1_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN1_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN1_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN1_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN2_REG (DR_REG_RTCIO_BASE + 0x30) +/* RTC_GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN2_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN2_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN2_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN2_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN2_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN2_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN2_INT_TYPE_M ((RTC_GPIO_PIN2_INT_TYPE_V)<<(RTC_GPIO_PIN2_INT_TYPE_S)) +#define RTC_GPIO_PIN2_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN2_INT_TYPE_S 7 +/* RTC_GPIO_PIN2_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN2_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN2_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN2_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN2_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN3_REG (DR_REG_RTCIO_BASE + 0x34) +/* RTC_GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN3_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN3_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN3_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN3_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN3_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN3_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN3_INT_TYPE_M ((RTC_GPIO_PIN3_INT_TYPE_V)<<(RTC_GPIO_PIN3_INT_TYPE_S)) +#define RTC_GPIO_PIN3_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN3_INT_TYPE_S 7 +/* RTC_GPIO_PIN3_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN3_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN3_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN3_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN3_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN4_REG (DR_REG_RTCIO_BASE + 0x38) +/* RTC_GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN4_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN4_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN4_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN4_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN4_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN4_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN4_INT_TYPE_M ((RTC_GPIO_PIN4_INT_TYPE_V)<<(RTC_GPIO_PIN4_INT_TYPE_S)) +#define RTC_GPIO_PIN4_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN4_INT_TYPE_S 7 +/* RTC_GPIO_PIN4_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN4_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN4_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN4_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN4_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN5_REG (DR_REG_RTCIO_BASE + 0x3c) +/* RTC_GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN5_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN5_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN5_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN5_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN5_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN5_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN5_INT_TYPE_M ((RTC_GPIO_PIN5_INT_TYPE_V)<<(RTC_GPIO_PIN5_INT_TYPE_S)) +#define RTC_GPIO_PIN5_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN5_INT_TYPE_S 7 +/* RTC_GPIO_PIN5_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN5_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN5_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN5_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN5_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN6_REG (DR_REG_RTCIO_BASE + 0x40) +/* RTC_GPIO_PIN6_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN6_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN6_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN6_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN6_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN6_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN6_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN6_INT_TYPE_M ((RTC_GPIO_PIN6_INT_TYPE_V)<<(RTC_GPIO_PIN6_INT_TYPE_S)) +#define RTC_GPIO_PIN6_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN6_INT_TYPE_S 7 +/* RTC_GPIO_PIN6_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN6_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN6_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN6_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN6_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN7_REG (DR_REG_RTCIO_BASE + 0x44) +/* RTC_GPIO_PIN7_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN7_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN7_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN7_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN7_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN7_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN7_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN7_INT_TYPE_M ((RTC_GPIO_PIN7_INT_TYPE_V)<<(RTC_GPIO_PIN7_INT_TYPE_S)) +#define RTC_GPIO_PIN7_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN7_INT_TYPE_S 7 +/* RTC_GPIO_PIN7_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN7_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN7_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN7_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN7_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN8_REG (DR_REG_RTCIO_BASE + 0x48) +/* RTC_GPIO_PIN8_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN8_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN8_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN8_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN8_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN8_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN8_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN8_INT_TYPE_M ((RTC_GPIO_PIN8_INT_TYPE_V)<<(RTC_GPIO_PIN8_INT_TYPE_S)) +#define RTC_GPIO_PIN8_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN8_INT_TYPE_S 7 +/* RTC_GPIO_PIN8_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN8_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN8_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN8_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN8_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN9_REG (DR_REG_RTCIO_BASE + 0x4c) +/* RTC_GPIO_PIN9_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN9_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN9_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN9_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN9_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN9_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN9_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN9_INT_TYPE_M ((RTC_GPIO_PIN9_INT_TYPE_V)<<(RTC_GPIO_PIN9_INT_TYPE_S)) +#define RTC_GPIO_PIN9_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN9_INT_TYPE_S 7 +/* RTC_GPIO_PIN9_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN9_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN9_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN9_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN9_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN10_REG (DR_REG_RTCIO_BASE + 0x50) +/* RTC_GPIO_PIN10_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN10_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN10_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN10_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN10_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN10_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN10_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN10_INT_TYPE_M ((RTC_GPIO_PIN10_INT_TYPE_V)<<(RTC_GPIO_PIN10_INT_TYPE_S)) +#define RTC_GPIO_PIN10_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN10_INT_TYPE_S 7 +/* RTC_GPIO_PIN10_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN10_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN10_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN10_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN10_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN11_REG (DR_REG_RTCIO_BASE + 0x54) +/* RTC_GPIO_PIN11_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN11_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN11_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN11_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN11_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN11_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN11_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN11_INT_TYPE_M ((RTC_GPIO_PIN11_INT_TYPE_V)<<(RTC_GPIO_PIN11_INT_TYPE_S)) +#define RTC_GPIO_PIN11_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN11_INT_TYPE_S 7 +/* RTC_GPIO_PIN11_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN11_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN11_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN11_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN11_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN12_REG (DR_REG_RTCIO_BASE + 0x58) +/* RTC_GPIO_PIN12_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN12_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN12_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN12_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN12_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN12_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN12_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN12_INT_TYPE_M ((RTC_GPIO_PIN12_INT_TYPE_V)<<(RTC_GPIO_PIN12_INT_TYPE_S)) +#define RTC_GPIO_PIN12_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN12_INT_TYPE_S 7 +/* RTC_GPIO_PIN12_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN12_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN12_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN12_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN12_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN13_REG (DR_REG_RTCIO_BASE + 0x5c) +/* RTC_GPIO_PIN13_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN13_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN13_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN13_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN13_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN13_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN13_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN13_INT_TYPE_M ((RTC_GPIO_PIN13_INT_TYPE_V)<<(RTC_GPIO_PIN13_INT_TYPE_S)) +#define RTC_GPIO_PIN13_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN13_INT_TYPE_S 7 +/* RTC_GPIO_PIN13_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN13_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN13_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN13_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN13_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN14_REG (DR_REG_RTCIO_BASE + 0x60) +/* RTC_GPIO_PIN14_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN14_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN14_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN14_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN14_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN14_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN14_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN14_INT_TYPE_M ((RTC_GPIO_PIN14_INT_TYPE_V)<<(RTC_GPIO_PIN14_INT_TYPE_S)) +#define RTC_GPIO_PIN14_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN14_INT_TYPE_S 7 +/* RTC_GPIO_PIN14_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN14_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN14_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN14_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN14_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN15_REG (DR_REG_RTCIO_BASE + 0x64) +/* RTC_GPIO_PIN15_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN15_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN15_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN15_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN15_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN15_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN15_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN15_INT_TYPE_M ((RTC_GPIO_PIN15_INT_TYPE_V)<<(RTC_GPIO_PIN15_INT_TYPE_S)) +#define RTC_GPIO_PIN15_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN15_INT_TYPE_S 7 +/* RTC_GPIO_PIN15_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN15_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN15_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN15_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN15_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN16_REG (DR_REG_RTCIO_BASE + 0x68) +/* RTC_GPIO_PIN16_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN16_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN16_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN16_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN16_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN16_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN16_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN16_INT_TYPE_M ((RTC_GPIO_PIN16_INT_TYPE_V)<<(RTC_GPIO_PIN16_INT_TYPE_S)) +#define RTC_GPIO_PIN16_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN16_INT_TYPE_S 7 +/* RTC_GPIO_PIN16_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN16_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN16_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN16_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN16_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN17_REG (DR_REG_RTCIO_BASE + 0x6c) +/* RTC_GPIO_PIN17_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN17_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN17_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN17_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN17_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN17_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN17_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN17_INT_TYPE_M ((RTC_GPIO_PIN17_INT_TYPE_V)<<(RTC_GPIO_PIN17_INT_TYPE_S)) +#define RTC_GPIO_PIN17_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN17_INT_TYPE_S 7 +/* RTC_GPIO_PIN17_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN17_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN17_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN17_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN17_PAD_DRIVER_S 2 + +#define RTC_IO_RTC_DEBUG_SEL_REG (DR_REG_RTCIO_BASE + 0x70) +/* RTC_IO_DEBUG_12M_NO_GATING : R/W ;bitpos:[25] ;default: 1'd0 ; */ +/*description: */ +#define RTC_IO_DEBUG_12M_NO_GATING (BIT(25)) +#define RTC_IO_DEBUG_12M_NO_GATING_M (BIT(25)) +#define RTC_IO_DEBUG_12M_NO_GATING_V 0x1 +#define RTC_IO_DEBUG_12M_NO_GATING_S 25 +/* RTC_IO_DEBUG_SEL4 : R/W ;bitpos:[24:20] ;default: 5'd0 ; */ +/*description: */ +#define RTC_IO_DEBUG_SEL4 0x0000001F +#define RTC_IO_DEBUG_SEL4_M ((RTC_IO_DEBUG_SEL4_V)<<(RTC_IO_DEBUG_SEL4_S)) +#define RTC_IO_DEBUG_SEL4_V 0x1F +#define RTC_IO_DEBUG_SEL4_S 20 +/* RTC_IO_DEBUG_SEL3 : R/W ;bitpos:[19:15] ;default: 5'd0 ; */ +/*description: */ +#define RTC_IO_DEBUG_SEL3 0x0000001F +#define RTC_IO_DEBUG_SEL3_M ((RTC_IO_DEBUG_SEL3_V)<<(RTC_IO_DEBUG_SEL3_S)) +#define RTC_IO_DEBUG_SEL3_V 0x1F +#define RTC_IO_DEBUG_SEL3_S 15 +/* RTC_IO_DEBUG_SEL2 : R/W ;bitpos:[14:10] ;default: 5'd0 ; */ +/*description: */ +#define RTC_IO_DEBUG_SEL2 0x0000001F +#define RTC_IO_DEBUG_SEL2_M ((RTC_IO_DEBUG_SEL2_V)<<(RTC_IO_DEBUG_SEL2_S)) +#define RTC_IO_DEBUG_SEL2_V 0x1F +#define RTC_IO_DEBUG_SEL2_S 10 +/* RTC_IO_DEBUG_SEL1 : R/W ;bitpos:[9:5] ;default: 5'd0 ; */ +/*description: */ +#define RTC_IO_DEBUG_SEL1 0x0000001F +#define RTC_IO_DEBUG_SEL1_M ((RTC_IO_DEBUG_SEL1_V)<<(RTC_IO_DEBUG_SEL1_S)) +#define RTC_IO_DEBUG_SEL1_V 0x1F +#define RTC_IO_DEBUG_SEL1_S 5 +/* RTC_IO_DEBUG_SEL0 : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define RTC_IO_DEBUG_SEL0 0x0000001F +#define RTC_IO_DEBUG_SEL0_M ((RTC_IO_DEBUG_SEL0_V)<<(RTC_IO_DEBUG_SEL0_S)) +#define RTC_IO_DEBUG_SEL0_V 0x1F +#define RTC_IO_DEBUG_SEL0_S 0 + +#define RTC_IO_DIG_PAD_HOLD_REG (DR_REG_RTCIO_BASE + 0x74) +/* RTC_IO_DIG_PAD_HOLD : R/W ;bitpos:[31:0] ;default: 1'd0 ; */ +/*description: select the digital pad hold value.*/ +#define RTC_IO_DIG_PAD_HOLD 0xFFFFFFFF +#define RTC_IO_DIG_PAD_HOLD_M ((RTC_IO_DIG_PAD_HOLD_V)<<(RTC_IO_DIG_PAD_HOLD_S)) +#define RTC_IO_DIG_PAD_HOLD_V 0xFFFFFFFF +#define RTC_IO_DIG_PAD_HOLD_S 0 + +#define RTC_IO_HALL_SENS_REG (DR_REG_RTCIO_BASE + 0x78) +/* RTC_IO_XPD_HALL : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: Power on hall sensor and connect to VP and VN*/ +#define RTC_IO_XPD_HALL (BIT(31)) +#define RTC_IO_XPD_HALL_M (BIT(31)) +#define RTC_IO_XPD_HALL_V 0x1 +#define RTC_IO_XPD_HALL_S 31 +/* RTC_IO_HALL_PHASE : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: Reverse phase of hall sensor*/ +#define RTC_IO_HALL_PHASE (BIT(30)) +#define RTC_IO_HALL_PHASE_M (BIT(30)) +#define RTC_IO_HALL_PHASE_V 0x1 +#define RTC_IO_HALL_PHASE_S 30 + +#define RTC_IO_SENSOR_PADS_REG (DR_REG_RTCIO_BASE + 0x7c) +/* RTC_IO_SENSE1_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_SENSE1_HOLD (BIT(31)) +#define RTC_IO_SENSE1_HOLD_M (BIT(31)) +#define RTC_IO_SENSE1_HOLD_V 0x1 +#define RTC_IO_SENSE1_HOLD_S 31 +/* RTC_IO_SENSE2_HOLD : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_SENSE2_HOLD (BIT(30)) +#define RTC_IO_SENSE2_HOLD_M (BIT(30)) +#define RTC_IO_SENSE2_HOLD_V 0x1 +#define RTC_IO_SENSE2_HOLD_S 30 +/* RTC_IO_SENSE3_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_SENSE3_HOLD (BIT(29)) +#define RTC_IO_SENSE3_HOLD_M (BIT(29)) +#define RTC_IO_SENSE3_HOLD_V 0x1 +#define RTC_IO_SENSE3_HOLD_S 29 +/* RTC_IO_SENSE4_HOLD : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_SENSE4_HOLD (BIT(28)) +#define RTC_IO_SENSE4_HOLD_M (BIT(28)) +#define RTC_IO_SENSE4_HOLD_V 0x1 +#define RTC_IO_SENSE4_HOLD_S 28 +/* RTC_IO_SENSE1_MUX_SEL : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_SENSE1_MUX_SEL (BIT(27)) +#define RTC_IO_SENSE1_MUX_SEL_M (BIT(27)) +#define RTC_IO_SENSE1_MUX_SEL_V 0x1 +#define RTC_IO_SENSE1_MUX_SEL_S 27 +/* RTC_IO_SENSE2_MUX_SEL : R/W ;bitpos:[26] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_SENSE2_MUX_SEL (BIT(26)) +#define RTC_IO_SENSE2_MUX_SEL_M (BIT(26)) +#define RTC_IO_SENSE2_MUX_SEL_V 0x1 +#define RTC_IO_SENSE2_MUX_SEL_S 26 +/* RTC_IO_SENSE3_MUX_SEL : R/W ;bitpos:[25] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_SENSE3_MUX_SEL (BIT(25)) +#define RTC_IO_SENSE3_MUX_SEL_M (BIT(25)) +#define RTC_IO_SENSE3_MUX_SEL_V 0x1 +#define RTC_IO_SENSE3_MUX_SEL_S 25 +/* RTC_IO_SENSE4_MUX_SEL : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_SENSE4_MUX_SEL (BIT(24)) +#define RTC_IO_SENSE4_MUX_SEL_M (BIT(24)) +#define RTC_IO_SENSE4_MUX_SEL_V 0x1 +#define RTC_IO_SENSE4_MUX_SEL_S 24 +/* RTC_IO_SENSE1_FUN_SEL : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_SENSE1_FUN_SEL 0x00000003 +#define RTC_IO_SENSE1_FUN_SEL_M ((RTC_IO_SENSE1_FUN_SEL_V)<<(RTC_IO_SENSE1_FUN_SEL_S)) +#define RTC_IO_SENSE1_FUN_SEL_V 0x3 +#define RTC_IO_SENSE1_FUN_SEL_S 22 +/* RTC_IO_SENSE1_SLP_SEL : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_SENSE1_SLP_SEL (BIT(21)) +#define RTC_IO_SENSE1_SLP_SEL_M (BIT(21)) +#define RTC_IO_SENSE1_SLP_SEL_V 0x1 +#define RTC_IO_SENSE1_SLP_SEL_S 21 +/* RTC_IO_SENSE1_SLP_IE : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_SENSE1_SLP_IE (BIT(20)) +#define RTC_IO_SENSE1_SLP_IE_M (BIT(20)) +#define RTC_IO_SENSE1_SLP_IE_V 0x1 +#define RTC_IO_SENSE1_SLP_IE_S 20 +/* RTC_IO_SENSE1_FUN_IE : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_SENSE1_FUN_IE (BIT(19)) +#define RTC_IO_SENSE1_FUN_IE_M (BIT(19)) +#define RTC_IO_SENSE1_FUN_IE_V 0x1 +#define RTC_IO_SENSE1_FUN_IE_S 19 +/* RTC_IO_SENSE2_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_SENSE2_FUN_SEL 0x00000003 +#define RTC_IO_SENSE2_FUN_SEL_M ((RTC_IO_SENSE2_FUN_SEL_V)<<(RTC_IO_SENSE2_FUN_SEL_S)) +#define RTC_IO_SENSE2_FUN_SEL_V 0x3 +#define RTC_IO_SENSE2_FUN_SEL_S 17 +/* RTC_IO_SENSE2_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_SENSE2_SLP_SEL (BIT(16)) +#define RTC_IO_SENSE2_SLP_SEL_M (BIT(16)) +#define RTC_IO_SENSE2_SLP_SEL_V 0x1 +#define RTC_IO_SENSE2_SLP_SEL_S 16 +/* RTC_IO_SENSE2_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_SENSE2_SLP_IE (BIT(15)) +#define RTC_IO_SENSE2_SLP_IE_M (BIT(15)) +#define RTC_IO_SENSE2_SLP_IE_V 0x1 +#define RTC_IO_SENSE2_SLP_IE_S 15 +/* RTC_IO_SENSE2_FUN_IE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_SENSE2_FUN_IE (BIT(14)) +#define RTC_IO_SENSE2_FUN_IE_M (BIT(14)) +#define RTC_IO_SENSE2_FUN_IE_V 0x1 +#define RTC_IO_SENSE2_FUN_IE_S 14 +/* RTC_IO_SENSE3_FUN_SEL : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_SENSE3_FUN_SEL 0x00000003 +#define RTC_IO_SENSE3_FUN_SEL_M ((RTC_IO_SENSE3_FUN_SEL_V)<<(RTC_IO_SENSE3_FUN_SEL_S)) +#define RTC_IO_SENSE3_FUN_SEL_V 0x3 +#define RTC_IO_SENSE3_FUN_SEL_S 12 +/* RTC_IO_SENSE3_SLP_SEL : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_SENSE3_SLP_SEL (BIT(11)) +#define RTC_IO_SENSE3_SLP_SEL_M (BIT(11)) +#define RTC_IO_SENSE3_SLP_SEL_V 0x1 +#define RTC_IO_SENSE3_SLP_SEL_S 11 +/* RTC_IO_SENSE3_SLP_IE : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_SENSE3_SLP_IE (BIT(10)) +#define RTC_IO_SENSE3_SLP_IE_M (BIT(10)) +#define RTC_IO_SENSE3_SLP_IE_V 0x1 +#define RTC_IO_SENSE3_SLP_IE_S 10 +/* RTC_IO_SENSE3_FUN_IE : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_SENSE3_FUN_IE (BIT(9)) +#define RTC_IO_SENSE3_FUN_IE_M (BIT(9)) +#define RTC_IO_SENSE3_FUN_IE_V 0x1 +#define RTC_IO_SENSE3_FUN_IE_S 9 +/* RTC_IO_SENSE4_FUN_SEL : R/W ;bitpos:[8:7] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_SENSE4_FUN_SEL 0x00000003 +#define RTC_IO_SENSE4_FUN_SEL_M ((RTC_IO_SENSE4_FUN_SEL_V)<<(RTC_IO_SENSE4_FUN_SEL_S)) +#define RTC_IO_SENSE4_FUN_SEL_V 0x3 +#define RTC_IO_SENSE4_FUN_SEL_S 7 +/* RTC_IO_SENSE4_SLP_SEL : R/W ;bitpos:[6] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_SENSE4_SLP_SEL (BIT(6)) +#define RTC_IO_SENSE4_SLP_SEL_M (BIT(6)) +#define RTC_IO_SENSE4_SLP_SEL_V 0x1 +#define RTC_IO_SENSE4_SLP_SEL_S 6 +/* RTC_IO_SENSE4_SLP_IE : R/W ;bitpos:[5] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_SENSE4_SLP_IE (BIT(5)) +#define RTC_IO_SENSE4_SLP_IE_M (BIT(5)) +#define RTC_IO_SENSE4_SLP_IE_V 0x1 +#define RTC_IO_SENSE4_SLP_IE_S 5 +/* RTC_IO_SENSE4_FUN_IE : R/W ;bitpos:[4] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_SENSE4_FUN_IE (BIT(4)) +#define RTC_IO_SENSE4_FUN_IE_M (BIT(4)) +#define RTC_IO_SENSE4_FUN_IE_V 0x1 +#define RTC_IO_SENSE4_FUN_IE_S 4 + +#define RTC_IO_ADC_PAD_REG (DR_REG_RTCIO_BASE + 0x80) +/* RTC_IO_ADC1_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_ADC1_HOLD (BIT(31)) +#define RTC_IO_ADC1_HOLD_M (BIT(31)) +#define RTC_IO_ADC1_HOLD_V 0x1 +#define RTC_IO_ADC1_HOLD_S 31 +/* RTC_IO_ADC2_HOLD : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_ADC2_HOLD (BIT(30)) +#define RTC_IO_ADC2_HOLD_M (BIT(30)) +#define RTC_IO_ADC2_HOLD_V 0x1 +#define RTC_IO_ADC2_HOLD_S 30 +/* RTC_IO_ADC1_MUX_SEL : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_ADC1_MUX_SEL (BIT(29)) +#define RTC_IO_ADC1_MUX_SEL_M (BIT(29)) +#define RTC_IO_ADC1_MUX_SEL_V 0x1 +#define RTC_IO_ADC1_MUX_SEL_S 29 +/* RTC_IO_ADC2_MUX_SEL : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_ADC2_MUX_SEL (BIT(28)) +#define RTC_IO_ADC2_MUX_SEL_M (BIT(28)) +#define RTC_IO_ADC2_MUX_SEL_V 0x1 +#define RTC_IO_ADC2_MUX_SEL_S 28 +/* RTC_IO_ADC1_FUN_SEL : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_ADC1_FUN_SEL 0x00000003 +#define RTC_IO_ADC1_FUN_SEL_M ((RTC_IO_ADC1_FUN_SEL_V)<<(RTC_IO_ADC1_FUN_SEL_S)) +#define RTC_IO_ADC1_FUN_SEL_V 0x3 +#define RTC_IO_ADC1_FUN_SEL_S 26 +/* RTC_IO_ADC1_SLP_SEL : R/W ;bitpos:[25] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_ADC1_SLP_SEL (BIT(25)) +#define RTC_IO_ADC1_SLP_SEL_M (BIT(25)) +#define RTC_IO_ADC1_SLP_SEL_V 0x1 +#define RTC_IO_ADC1_SLP_SEL_S 25 +/* RTC_IO_ADC1_SLP_IE : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_ADC1_SLP_IE (BIT(24)) +#define RTC_IO_ADC1_SLP_IE_M (BIT(24)) +#define RTC_IO_ADC1_SLP_IE_V 0x1 +#define RTC_IO_ADC1_SLP_IE_S 24 +/* RTC_IO_ADC1_FUN_IE : R/W ;bitpos:[23] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_ADC1_FUN_IE (BIT(23)) +#define RTC_IO_ADC1_FUN_IE_M (BIT(23)) +#define RTC_IO_ADC1_FUN_IE_V 0x1 +#define RTC_IO_ADC1_FUN_IE_S 23 +/* RTC_IO_ADC2_FUN_SEL : R/W ;bitpos:[22:21] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_ADC2_FUN_SEL 0x00000003 +#define RTC_IO_ADC2_FUN_SEL_M ((RTC_IO_ADC2_FUN_SEL_V)<<(RTC_IO_ADC2_FUN_SEL_S)) +#define RTC_IO_ADC2_FUN_SEL_V 0x3 +#define RTC_IO_ADC2_FUN_SEL_S 21 +/* RTC_IO_ADC2_SLP_SEL : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_ADC2_SLP_SEL (BIT(20)) +#define RTC_IO_ADC2_SLP_SEL_M (BIT(20)) +#define RTC_IO_ADC2_SLP_SEL_V 0x1 +#define RTC_IO_ADC2_SLP_SEL_S 20 +/* RTC_IO_ADC2_SLP_IE : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_ADC2_SLP_IE (BIT(19)) +#define RTC_IO_ADC2_SLP_IE_M (BIT(19)) +#define RTC_IO_ADC2_SLP_IE_V 0x1 +#define RTC_IO_ADC2_SLP_IE_S 19 +/* RTC_IO_ADC2_FUN_IE : R/W ;bitpos:[18] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_ADC2_FUN_IE (BIT(18)) +#define RTC_IO_ADC2_FUN_IE_M (BIT(18)) +#define RTC_IO_ADC2_FUN_IE_V 0x1 +#define RTC_IO_ADC2_FUN_IE_S 18 + +#define RTC_IO_PAD_DAC1_REG (DR_REG_RTCIO_BASE + 0x84) +/* RTC_IO_PDAC1_DRV : R/W ;bitpos:[31:30] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_PDAC1_DRV 0x00000003 +#define RTC_IO_PDAC1_DRV_M ((RTC_IO_PDAC1_DRV_V)<<(RTC_IO_PDAC1_DRV_S)) +#define RTC_IO_PDAC1_DRV_V 0x3 +#define RTC_IO_PDAC1_DRV_S 30 +/* RTC_IO_PDAC1_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_PDAC1_HOLD (BIT(29)) +#define RTC_IO_PDAC1_HOLD_M (BIT(29)) +#define RTC_IO_PDAC1_HOLD_V 0x1 +#define RTC_IO_PDAC1_HOLD_S 29 +/* RTC_IO_PDAC1_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_PDAC1_RDE (BIT(28)) +#define RTC_IO_PDAC1_RDE_M (BIT(28)) +#define RTC_IO_PDAC1_RDE_V 0x1 +#define RTC_IO_PDAC1_RDE_S 28 +/* RTC_IO_PDAC1_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_PDAC1_RUE (BIT(27)) +#define RTC_IO_PDAC1_RUE_M (BIT(27)) +#define RTC_IO_PDAC1_RUE_V 0x1 +#define RTC_IO_PDAC1_RUE_S 27 +/* RTC_IO_PDAC1_DAC : R/W ;bitpos:[26:19] ;default: 8'd0 ; */ +/*description: PAD DAC1 control code.*/ +#define RTC_IO_PDAC1_DAC 0x000000FF +#define RTC_IO_PDAC1_DAC_M ((RTC_IO_PDAC1_DAC_V)<<(RTC_IO_PDAC1_DAC_S)) +#define RTC_IO_PDAC1_DAC_V 0xFF +#define RTC_IO_PDAC1_DAC_S 19 +/* RTC_IO_PDAC1_XPD_DAC : R/W ;bitpos:[18] ;default: 1'd0 ; */ +/*description: Power on DAC1. Usually we need to tristate PDAC1 if we power + on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/ +#define RTC_IO_PDAC1_XPD_DAC (BIT(18)) +#define RTC_IO_PDAC1_XPD_DAC_M (BIT(18)) +#define RTC_IO_PDAC1_XPD_DAC_V 0x1 +#define RTC_IO_PDAC1_XPD_DAC_S 18 +/* RTC_IO_PDAC1_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_PDAC1_MUX_SEL (BIT(17)) +#define RTC_IO_PDAC1_MUX_SEL_M (BIT(17)) +#define RTC_IO_PDAC1_MUX_SEL_V 0x1 +#define RTC_IO_PDAC1_MUX_SEL_S 17 +/* RTC_IO_PDAC1_FUN_SEL : R/W ;bitpos:[16:15] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_PDAC1_FUN_SEL 0x00000003 +#define RTC_IO_PDAC1_FUN_SEL_M ((RTC_IO_PDAC1_FUN_SEL_V)<<(RTC_IO_PDAC1_FUN_SEL_S)) +#define RTC_IO_PDAC1_FUN_SEL_V 0x3 +#define RTC_IO_PDAC1_FUN_SEL_S 15 +/* RTC_IO_PDAC1_SLP_SEL : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_PDAC1_SLP_SEL (BIT(14)) +#define RTC_IO_PDAC1_SLP_SEL_M (BIT(14)) +#define RTC_IO_PDAC1_SLP_SEL_V 0x1 +#define RTC_IO_PDAC1_SLP_SEL_S 14 +/* RTC_IO_PDAC1_SLP_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_PDAC1_SLP_IE (BIT(13)) +#define RTC_IO_PDAC1_SLP_IE_M (BIT(13)) +#define RTC_IO_PDAC1_SLP_IE_V 0x1 +#define RTC_IO_PDAC1_SLP_IE_S 13 +/* RTC_IO_PDAC1_SLP_OE : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_PDAC1_SLP_OE (BIT(12)) +#define RTC_IO_PDAC1_SLP_OE_M (BIT(12)) +#define RTC_IO_PDAC1_SLP_OE_V 0x1 +#define RTC_IO_PDAC1_SLP_OE_S 12 +/* RTC_IO_PDAC1_FUN_IE : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_PDAC1_FUN_IE (BIT(11)) +#define RTC_IO_PDAC1_FUN_IE_M (BIT(11)) +#define RTC_IO_PDAC1_FUN_IE_V 0x1 +#define RTC_IO_PDAC1_FUN_IE_S 11 +/* RTC_IO_PDAC1_DAC_XPD_FORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: Power on DAC1. Usually we need to tristate PDAC1 if we power + on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/ +#define RTC_IO_PDAC1_DAC_XPD_FORCE (BIT(10)) +#define RTC_IO_PDAC1_DAC_XPD_FORCE_M (BIT(10)) +#define RTC_IO_PDAC1_DAC_XPD_FORCE_V 0x1 +#define RTC_IO_PDAC1_DAC_XPD_FORCE_S 10 + +#define RTC_IO_PAD_DAC2_REG (DR_REG_RTCIO_BASE + 0x88) +/* RTC_IO_PDAC2_DRV : R/W ;bitpos:[31:30] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_PDAC2_DRV 0x00000003 +#define RTC_IO_PDAC2_DRV_M ((RTC_IO_PDAC2_DRV_V)<<(RTC_IO_PDAC2_DRV_S)) +#define RTC_IO_PDAC2_DRV_V 0x3 +#define RTC_IO_PDAC2_DRV_S 30 +/* RTC_IO_PDAC2_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_PDAC2_HOLD (BIT(29)) +#define RTC_IO_PDAC2_HOLD_M (BIT(29)) +#define RTC_IO_PDAC2_HOLD_V 0x1 +#define RTC_IO_PDAC2_HOLD_S 29 +/* RTC_IO_PDAC2_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_PDAC2_RDE (BIT(28)) +#define RTC_IO_PDAC2_RDE_M (BIT(28)) +#define RTC_IO_PDAC2_RDE_V 0x1 +#define RTC_IO_PDAC2_RDE_S 28 +/* RTC_IO_PDAC2_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_PDAC2_RUE (BIT(27)) +#define RTC_IO_PDAC2_RUE_M (BIT(27)) +#define RTC_IO_PDAC2_RUE_V 0x1 +#define RTC_IO_PDAC2_RUE_S 27 +/* RTC_IO_PDAC2_DAC : R/W ;bitpos:[26:19] ;default: 8'd0 ; */ +/*description: PAD DAC2 control code.*/ +#define RTC_IO_PDAC2_DAC 0x000000FF +#define RTC_IO_PDAC2_DAC_M ((RTC_IO_PDAC2_DAC_V)<<(RTC_IO_PDAC2_DAC_S)) +#define RTC_IO_PDAC2_DAC_V 0xFF +#define RTC_IO_PDAC2_DAC_S 19 +/* RTC_IO_PDAC2_XPD_DAC : R/W ;bitpos:[18] ;default: 1'd0 ; */ +/*description: Power on DAC2. Usually we need to tristate PDAC1 if we power + on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/ +#define RTC_IO_PDAC2_XPD_DAC (BIT(18)) +#define RTC_IO_PDAC2_XPD_DAC_M (BIT(18)) +#define RTC_IO_PDAC2_XPD_DAC_V 0x1 +#define RTC_IO_PDAC2_XPD_DAC_S 18 +/* RTC_IO_PDAC2_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_PDAC2_MUX_SEL (BIT(17)) +#define RTC_IO_PDAC2_MUX_SEL_M (BIT(17)) +#define RTC_IO_PDAC2_MUX_SEL_V 0x1 +#define RTC_IO_PDAC2_MUX_SEL_S 17 +/* RTC_IO_PDAC2_FUN_SEL : R/W ;bitpos:[16:15] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_PDAC2_FUN_SEL 0x00000003 +#define RTC_IO_PDAC2_FUN_SEL_M ((RTC_IO_PDAC2_FUN_SEL_V)<<(RTC_IO_PDAC2_FUN_SEL_S)) +#define RTC_IO_PDAC2_FUN_SEL_V 0x3 +#define RTC_IO_PDAC2_FUN_SEL_S 15 +/* RTC_IO_PDAC2_SLP_SEL : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_PDAC2_SLP_SEL (BIT(14)) +#define RTC_IO_PDAC2_SLP_SEL_M (BIT(14)) +#define RTC_IO_PDAC2_SLP_SEL_V 0x1 +#define RTC_IO_PDAC2_SLP_SEL_S 14 +/* RTC_IO_PDAC2_SLP_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_PDAC2_SLP_IE (BIT(13)) +#define RTC_IO_PDAC2_SLP_IE_M (BIT(13)) +#define RTC_IO_PDAC2_SLP_IE_V 0x1 +#define RTC_IO_PDAC2_SLP_IE_S 13 +/* RTC_IO_PDAC2_SLP_OE : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_PDAC2_SLP_OE (BIT(12)) +#define RTC_IO_PDAC2_SLP_OE_M (BIT(12)) +#define RTC_IO_PDAC2_SLP_OE_V 0x1 +#define RTC_IO_PDAC2_SLP_OE_S 12 +/* RTC_IO_PDAC2_FUN_IE : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_PDAC2_FUN_IE (BIT(11)) +#define RTC_IO_PDAC2_FUN_IE_M (BIT(11)) +#define RTC_IO_PDAC2_FUN_IE_V 0x1 +#define RTC_IO_PDAC2_FUN_IE_S 11 +/* RTC_IO_PDAC2_DAC_XPD_FORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: Power on DAC2. Usually we need to tristate PDAC2 if we power + on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/ +#define RTC_IO_PDAC2_DAC_XPD_FORCE (BIT(10)) +#define RTC_IO_PDAC2_DAC_XPD_FORCE_M (BIT(10)) +#define RTC_IO_PDAC2_DAC_XPD_FORCE_V 0x1 +#define RTC_IO_PDAC2_DAC_XPD_FORCE_S 10 + +#define RTC_IO_XTAL_32K_PAD_REG (DR_REG_RTCIO_BASE + 0x8c) +/* RTC_IO_X32N_DRV : R/W ;bitpos:[31:30] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_X32N_DRV 0x00000003 +#define RTC_IO_X32N_DRV_M ((RTC_IO_X32N_DRV_V)<<(RTC_IO_X32N_DRV_S)) +#define RTC_IO_X32N_DRV_V 0x3 +#define RTC_IO_X32N_DRV_S 30 +/* RTC_IO_X32N_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_X32N_HOLD (BIT(29)) +#define RTC_IO_X32N_HOLD_M (BIT(29)) +#define RTC_IO_X32N_HOLD_V 0x1 +#define RTC_IO_X32N_HOLD_S 29 +/* RTC_IO_X32N_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_X32N_RDE (BIT(28)) +#define RTC_IO_X32N_RDE_M (BIT(28)) +#define RTC_IO_X32N_RDE_V 0x1 +#define RTC_IO_X32N_RDE_S 28 +/* RTC_IO_X32N_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_X32N_RUE (BIT(27)) +#define RTC_IO_X32N_RUE_M (BIT(27)) +#define RTC_IO_X32N_RUE_V 0x1 +#define RTC_IO_X32N_RUE_S 27 +/* RTC_IO_X32P_DRV : R/W ;bitpos:[26:25] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_X32P_DRV 0x00000003 +#define RTC_IO_X32P_DRV_M ((RTC_IO_X32P_DRV_V)<<(RTC_IO_X32P_DRV_S)) +#define RTC_IO_X32P_DRV_V 0x3 +#define RTC_IO_X32P_DRV_S 25 +/* RTC_IO_X32P_HOLD : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_X32P_HOLD (BIT(24)) +#define RTC_IO_X32P_HOLD_M (BIT(24)) +#define RTC_IO_X32P_HOLD_V 0x1 +#define RTC_IO_X32P_HOLD_S 24 +/* RTC_IO_X32P_RDE : R/W ;bitpos:[23] ;default: 1'd0 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_X32P_RDE (BIT(23)) +#define RTC_IO_X32P_RDE_M (BIT(23)) +#define RTC_IO_X32P_RDE_V 0x1 +#define RTC_IO_X32P_RDE_S 23 +/* RTC_IO_X32P_RUE : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_X32P_RUE (BIT(22)) +#define RTC_IO_X32P_RUE_M (BIT(22)) +#define RTC_IO_X32P_RUE_V 0x1 +#define RTC_IO_X32P_RUE_S 22 +/* RTC_IO_DAC_XTAL_32K : R/W ;bitpos:[21:20] ;default: 2'b01 ; */ +/*description: 32K XTAL bias current DAC.*/ +#define RTC_IO_DAC_XTAL_32K 0x00000003 +#define RTC_IO_DAC_XTAL_32K_M ((RTC_IO_DAC_XTAL_32K_V)<<(RTC_IO_DAC_XTAL_32K_S)) +#define RTC_IO_DAC_XTAL_32K_V 0x3 +#define RTC_IO_DAC_XTAL_32K_S 20 +/* RTC_IO_XPD_XTAL_32K : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: Power up 32kHz crystal oscillator*/ +#define RTC_IO_XPD_XTAL_32K (BIT(19)) +#define RTC_IO_XPD_XTAL_32K_M (BIT(19)) +#define RTC_IO_XPD_XTAL_32K_V 0x1 +#define RTC_IO_XPD_XTAL_32K_S 19 +/* RTC_IO_X32N_MUX_SEL : R/W ;bitpos:[18] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_X32N_MUX_SEL (BIT(18)) +#define RTC_IO_X32N_MUX_SEL_M (BIT(18)) +#define RTC_IO_X32N_MUX_SEL_V 0x1 +#define RTC_IO_X32N_MUX_SEL_S 18 +/* RTC_IO_X32P_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_X32P_MUX_SEL (BIT(17)) +#define RTC_IO_X32P_MUX_SEL_M (BIT(17)) +#define RTC_IO_X32P_MUX_SEL_V 0x1 +#define RTC_IO_X32P_MUX_SEL_S 17 +/* RTC_IO_X32N_FUN_SEL : R/W ;bitpos:[16:15] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_X32N_FUN_SEL 0x00000003 +#define RTC_IO_X32N_FUN_SEL_M ((RTC_IO_X32N_FUN_SEL_V)<<(RTC_IO_X32N_FUN_SEL_S)) +#define RTC_IO_X32N_FUN_SEL_V 0x3 +#define RTC_IO_X32N_FUN_SEL_S 15 +/* RTC_IO_X32N_SLP_SEL : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_X32N_SLP_SEL (BIT(14)) +#define RTC_IO_X32N_SLP_SEL_M (BIT(14)) +#define RTC_IO_X32N_SLP_SEL_V 0x1 +#define RTC_IO_X32N_SLP_SEL_S 14 +/* RTC_IO_X32N_SLP_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_X32N_SLP_IE (BIT(13)) +#define RTC_IO_X32N_SLP_IE_M (BIT(13)) +#define RTC_IO_X32N_SLP_IE_V 0x1 +#define RTC_IO_X32N_SLP_IE_S 13 +/* RTC_IO_X32N_SLP_OE : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_X32N_SLP_OE (BIT(12)) +#define RTC_IO_X32N_SLP_OE_M (BIT(12)) +#define RTC_IO_X32N_SLP_OE_V 0x1 +#define RTC_IO_X32N_SLP_OE_S 12 +/* RTC_IO_X32N_FUN_IE : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_X32N_FUN_IE (BIT(11)) +#define RTC_IO_X32N_FUN_IE_M (BIT(11)) +#define RTC_IO_X32N_FUN_IE_V 0x1 +#define RTC_IO_X32N_FUN_IE_S 11 +/* RTC_IO_X32P_FUN_SEL : R/W ;bitpos:[10:9] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_X32P_FUN_SEL 0x00000003 +#define RTC_IO_X32P_FUN_SEL_M ((RTC_IO_X32P_FUN_SEL_V)<<(RTC_IO_X32P_FUN_SEL_S)) +#define RTC_IO_X32P_FUN_SEL_V 0x3 +#define RTC_IO_X32P_FUN_SEL_S 9 +/* RTC_IO_X32P_SLP_SEL : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_X32P_SLP_SEL (BIT(8)) +#define RTC_IO_X32P_SLP_SEL_M (BIT(8)) +#define RTC_IO_X32P_SLP_SEL_V 0x1 +#define RTC_IO_X32P_SLP_SEL_S 8 +/* RTC_IO_X32P_SLP_IE : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_X32P_SLP_IE (BIT(7)) +#define RTC_IO_X32P_SLP_IE_M (BIT(7)) +#define RTC_IO_X32P_SLP_IE_V 0x1 +#define RTC_IO_X32P_SLP_IE_S 7 +/* RTC_IO_X32P_SLP_OE : R/W ;bitpos:[6] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_X32P_SLP_OE (BIT(6)) +#define RTC_IO_X32P_SLP_OE_M (BIT(6)) +#define RTC_IO_X32P_SLP_OE_V 0x1 +#define RTC_IO_X32P_SLP_OE_S 6 +/* RTC_IO_X32P_FUN_IE : R/W ;bitpos:[5] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_X32P_FUN_IE (BIT(5)) +#define RTC_IO_X32P_FUN_IE_M (BIT(5)) +#define RTC_IO_X32P_FUN_IE_V 0x1 +#define RTC_IO_X32P_FUN_IE_S 5 +/* RTC_IO_DRES_XTAL_32K : R/W ;bitpos:[4:3] ;default: 2'b10 ; */ +/*description: 32K XTAL resistor bias control.*/ +#define RTC_IO_DRES_XTAL_32K 0x00000003 +#define RTC_IO_DRES_XTAL_32K_M ((RTC_IO_DRES_XTAL_32K_V)<<(RTC_IO_DRES_XTAL_32K_S)) +#define RTC_IO_DRES_XTAL_32K_V 0x3 +#define RTC_IO_DRES_XTAL_32K_S 3 +/* RTC_IO_DBIAS_XTAL_32K : R/W ;bitpos:[2:1] ;default: 2'b00 ; */ +/*description: 32K XTAL self-bias reference control.*/ +#define RTC_IO_DBIAS_XTAL_32K 0x00000003 +#define RTC_IO_DBIAS_XTAL_32K_M ((RTC_IO_DBIAS_XTAL_32K_V)<<(RTC_IO_DBIAS_XTAL_32K_S)) +#define RTC_IO_DBIAS_XTAL_32K_V 0x3 +#define RTC_IO_DBIAS_XTAL_32K_S 1 + +#define RTC_IO_TOUCH_CFG_REG (DR_REG_RTCIO_BASE + 0x90) +/* RTC_IO_TOUCH_XPD_BIAS : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: touch sensor bias power on.*/ +#define RTC_IO_TOUCH_XPD_BIAS (BIT(31)) +#define RTC_IO_TOUCH_XPD_BIAS_M (BIT(31)) +#define RTC_IO_TOUCH_XPD_BIAS_V 0x1 +#define RTC_IO_TOUCH_XPD_BIAS_S 31 +/* RTC_IO_TOUCH_DREFH : R/W ;bitpos:[30:29] ;default: 2'b11 ; */ +/*description: touch sensor saw wave top voltage.*/ +#define RTC_IO_TOUCH_DREFH 0x00000003 +#define RTC_IO_TOUCH_DREFH_M ((RTC_IO_TOUCH_DREFH_V)<<(RTC_IO_TOUCH_DREFH_S)) +#define RTC_IO_TOUCH_DREFH_V 0x3 +#define RTC_IO_TOUCH_DREFH_S 29 +/* RTC_IO_TOUCH_DREFL : R/W ;bitpos:[28:27] ;default: 2'b00 ; */ +/*description: touch sensor saw wave bottom voltage.*/ +#define RTC_IO_TOUCH_DREFL 0x00000003 +#define RTC_IO_TOUCH_DREFL_M ((RTC_IO_TOUCH_DREFL_V)<<(RTC_IO_TOUCH_DREFL_S)) +#define RTC_IO_TOUCH_DREFL_V 0x3 +#define RTC_IO_TOUCH_DREFL_S 27 +/* RTC_IO_TOUCH_DRANGE : R/W ;bitpos:[26:25] ;default: 2'b11 ; */ +/*description: touch sensor saw wave voltage range.*/ +#define RTC_IO_TOUCH_DRANGE 0x00000003 +#define RTC_IO_TOUCH_DRANGE_M ((RTC_IO_TOUCH_DRANGE_V)<<(RTC_IO_TOUCH_DRANGE_S)) +#define RTC_IO_TOUCH_DRANGE_V 0x3 +#define RTC_IO_TOUCH_DRANGE_S 25 +/* RTC_IO_TOUCH_DCUR : R/W ;bitpos:[24:23] ;default: 2'b00 ; */ +/*description: touch sensor bias current. Should have option to tie with BIAS_SLEEP(When + BIAS_SLEEP this setting is available*/ +#define RTC_IO_TOUCH_DCUR 0x00000003 +#define RTC_IO_TOUCH_DCUR_M ((RTC_IO_TOUCH_DCUR_V)<<(RTC_IO_TOUCH_DCUR_S)) +#define RTC_IO_TOUCH_DCUR_V 0x3 +#define RTC_IO_TOUCH_DCUR_S 23 + +#define RTC_IO_TOUCH_PAD0_REG (DR_REG_RTCIO_BASE + 0x94) +/* RTC_IO_TOUCH_PAD0_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_TOUCH_PAD0_HOLD (BIT(31)) +#define RTC_IO_TOUCH_PAD0_HOLD_M (BIT(31)) +#define RTC_IO_TOUCH_PAD0_HOLD_V 0x1 +#define RTC_IO_TOUCH_PAD0_HOLD_S 31 +/* RTC_IO_TOUCH_PAD0_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_TOUCH_PAD0_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD0_DRV_M ((RTC_IO_TOUCH_PAD0_DRV_V)<<(RTC_IO_TOUCH_PAD0_DRV_S)) +#define RTC_IO_TOUCH_PAD0_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD0_DRV_S 29 +/* RTC_IO_TOUCH_PAD0_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_TOUCH_PAD0_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD0_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD0_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD0_RDE_S 28 +/* RTC_IO_TOUCH_PAD0_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_TOUCH_PAD0_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD0_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD0_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD0_RUE_S 27 +/* RTC_IO_TOUCH_PAD0_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ +#define RTC_IO_TOUCH_PAD0_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD0_DAC_M ((RTC_IO_TOUCH_PAD0_DAC_V)<<(RTC_IO_TOUCH_PAD0_DAC_S)) +#define RTC_IO_TOUCH_PAD0_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD0_DAC_S 23 +/* RTC_IO_TOUCH_PAD0_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: start touch sensor.*/ +#define RTC_IO_TOUCH_PAD0_START (BIT(22)) +#define RTC_IO_TOUCH_PAD0_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD0_START_V 0x1 +#define RTC_IO_TOUCH_PAD0_START_S 22 +/* RTC_IO_TOUCH_PAD0_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ +#define RTC_IO_TOUCH_PAD0_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD0_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD0_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD0_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD0_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: touch sensor power on.*/ +#define RTC_IO_TOUCH_PAD0_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD0_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD0_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD0_XPD_S 20 +/* RTC_IO_TOUCH_PAD0_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_TOUCH_PAD0_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD0_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD0_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD0_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD0_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD0_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD0_FUN_SEL_M ((RTC_IO_TOUCH_PAD0_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD0_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD0_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD0_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD0_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD0_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD0_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD0_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD0_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD0_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD0_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD0_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD0_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD0_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD0_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD0_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD0_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD0_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD0_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD0_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_TOUCH_PAD0_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD0_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD0_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD0_FUN_IE_S 13 +/* RTC_IO_TOUCH_PAD0_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale GPIO4*/ +#define RTC_IO_TOUCH_PAD0_TO_GPIO (BIT(12)) +#define RTC_IO_TOUCH_PAD0_TO_GPIO_M (BIT(12)) +#define RTC_IO_TOUCH_PAD0_TO_GPIO_V 0x1 +#define RTC_IO_TOUCH_PAD0_TO_GPIO_S 12 + +#define RTC_IO_TOUCH_PAD1_REG (DR_REG_RTCIO_BASE + 0x98) +/* RTC_IO_TOUCH_PAD1_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: */ +#define RTC_IO_TOUCH_PAD1_HOLD (BIT(31)) +#define RTC_IO_TOUCH_PAD1_HOLD_M (BIT(31)) +#define RTC_IO_TOUCH_PAD1_HOLD_V 0x1 +#define RTC_IO_TOUCH_PAD1_HOLD_S 31 +/* RTC_IO_TOUCH_PAD1_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_TOUCH_PAD1_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD1_DRV_M ((RTC_IO_TOUCH_PAD1_DRV_V)<<(RTC_IO_TOUCH_PAD1_DRV_S)) +#define RTC_IO_TOUCH_PAD1_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD1_DRV_S 29 +/* RTC_IO_TOUCH_PAD1_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_TOUCH_PAD1_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD1_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD1_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD1_RDE_S 28 +/* RTC_IO_TOUCH_PAD1_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_TOUCH_PAD1_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD1_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD1_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD1_RUE_S 27 +/* RTC_IO_TOUCH_PAD1_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ +#define RTC_IO_TOUCH_PAD1_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD1_DAC_M ((RTC_IO_TOUCH_PAD1_DAC_V)<<(RTC_IO_TOUCH_PAD1_DAC_S)) +#define RTC_IO_TOUCH_PAD1_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD1_DAC_S 23 +/* RTC_IO_TOUCH_PAD1_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: start touch sensor.*/ +#define RTC_IO_TOUCH_PAD1_START (BIT(22)) +#define RTC_IO_TOUCH_PAD1_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD1_START_V 0x1 +#define RTC_IO_TOUCH_PAD1_START_S 22 +/* RTC_IO_TOUCH_PAD1_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ +#define RTC_IO_TOUCH_PAD1_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD1_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD1_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD1_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD1_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: touch sensor power on.*/ +#define RTC_IO_TOUCH_PAD1_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD1_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD1_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD1_XPD_S 20 +/* RTC_IO_TOUCH_PAD1_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_TOUCH_PAD1_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD1_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD1_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD1_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD1_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD1_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD1_FUN_SEL_M ((RTC_IO_TOUCH_PAD1_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD1_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD1_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD1_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD1_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD1_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD1_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD1_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD1_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD1_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD1_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD1_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD1_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD1_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD1_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD1_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD1_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD1_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD1_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD1_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_TOUCH_PAD1_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD1_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD1_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD1_FUN_IE_S 13 +/* RTC_IO_TOUCH_PAD1_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO0*/ +#define RTC_IO_TOUCH_PAD1_TO_GPIO (BIT(12)) +#define RTC_IO_TOUCH_PAD1_TO_GPIO_M (BIT(12)) +#define RTC_IO_TOUCH_PAD1_TO_GPIO_V 0x1 +#define RTC_IO_TOUCH_PAD1_TO_GPIO_S 12 + +#define RTC_IO_TOUCH_PAD2_REG (DR_REG_RTCIO_BASE + 0x9c) +/* RTC_IO_TOUCH_PAD2_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_TOUCH_PAD2_HOLD (BIT(31)) +#define RTC_IO_TOUCH_PAD2_HOLD_M (BIT(31)) +#define RTC_IO_TOUCH_PAD2_HOLD_V 0x1 +#define RTC_IO_TOUCH_PAD2_HOLD_S 31 +/* RTC_IO_TOUCH_PAD2_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_TOUCH_PAD2_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD2_DRV_M ((RTC_IO_TOUCH_PAD2_DRV_V)<<(RTC_IO_TOUCH_PAD2_DRV_S)) +#define RTC_IO_TOUCH_PAD2_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD2_DRV_S 29 +/* RTC_IO_TOUCH_PAD2_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_TOUCH_PAD2_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD2_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD2_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD2_RDE_S 28 +/* RTC_IO_TOUCH_PAD2_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_TOUCH_PAD2_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD2_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD2_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD2_RUE_S 27 +/* RTC_IO_TOUCH_PAD2_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ +#define RTC_IO_TOUCH_PAD2_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD2_DAC_M ((RTC_IO_TOUCH_PAD2_DAC_V)<<(RTC_IO_TOUCH_PAD2_DAC_S)) +#define RTC_IO_TOUCH_PAD2_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD2_DAC_S 23 +/* RTC_IO_TOUCH_PAD2_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: start touch sensor.*/ +#define RTC_IO_TOUCH_PAD2_START (BIT(22)) +#define RTC_IO_TOUCH_PAD2_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD2_START_V 0x1 +#define RTC_IO_TOUCH_PAD2_START_S 22 +/* RTC_IO_TOUCH_PAD2_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ +#define RTC_IO_TOUCH_PAD2_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD2_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD2_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD2_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD2_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: touch sensor power on.*/ +#define RTC_IO_TOUCH_PAD2_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD2_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD2_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD2_XPD_S 20 +/* RTC_IO_TOUCH_PAD2_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_TOUCH_PAD2_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD2_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD2_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD2_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD2_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD2_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD2_FUN_SEL_M ((RTC_IO_TOUCH_PAD2_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD2_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD2_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD2_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD2_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD2_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD2_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD2_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD2_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD2_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD2_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD2_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD2_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD2_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD2_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD2_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD2_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD2_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD2_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD2_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_TOUCH_PAD2_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD2_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD2_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD2_FUN_IE_S 13 +/* RTC_IO_TOUCH_PAD2_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO2*/ +#define RTC_IO_TOUCH_PAD2_TO_GPIO (BIT(12)) +#define RTC_IO_TOUCH_PAD2_TO_GPIO_M (BIT(12)) +#define RTC_IO_TOUCH_PAD2_TO_GPIO_V 0x1 +#define RTC_IO_TOUCH_PAD2_TO_GPIO_S 12 + +#define RTC_IO_TOUCH_PAD3_REG (DR_REG_RTCIO_BASE + 0xa0) +/* RTC_IO_TOUCH_PAD3_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_TOUCH_PAD3_HOLD (BIT(31)) +#define RTC_IO_TOUCH_PAD3_HOLD_M (BIT(31)) +#define RTC_IO_TOUCH_PAD3_HOLD_V 0x1 +#define RTC_IO_TOUCH_PAD3_HOLD_S 31 +/* RTC_IO_TOUCH_PAD3_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_TOUCH_PAD3_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD3_DRV_M ((RTC_IO_TOUCH_PAD3_DRV_V)<<(RTC_IO_TOUCH_PAD3_DRV_S)) +#define RTC_IO_TOUCH_PAD3_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD3_DRV_S 29 +/* RTC_IO_TOUCH_PAD3_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_TOUCH_PAD3_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD3_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD3_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD3_RDE_S 28 +/* RTC_IO_TOUCH_PAD3_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_TOUCH_PAD3_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD3_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD3_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD3_RUE_S 27 +/* RTC_IO_TOUCH_PAD3_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ +#define RTC_IO_TOUCH_PAD3_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD3_DAC_M ((RTC_IO_TOUCH_PAD3_DAC_V)<<(RTC_IO_TOUCH_PAD3_DAC_S)) +#define RTC_IO_TOUCH_PAD3_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD3_DAC_S 23 +/* RTC_IO_TOUCH_PAD3_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: start touch sensor.*/ +#define RTC_IO_TOUCH_PAD3_START (BIT(22)) +#define RTC_IO_TOUCH_PAD3_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD3_START_V 0x1 +#define RTC_IO_TOUCH_PAD3_START_S 22 +/* RTC_IO_TOUCH_PAD3_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ +#define RTC_IO_TOUCH_PAD3_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD3_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD3_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD3_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD3_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: touch sensor power on.*/ +#define RTC_IO_TOUCH_PAD3_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD3_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD3_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD3_XPD_S 20 +/* RTC_IO_TOUCH_PAD3_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_TOUCH_PAD3_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD3_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD3_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD3_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD3_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD3_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD3_FUN_SEL_M ((RTC_IO_TOUCH_PAD3_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD3_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD3_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD3_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD3_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD3_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD3_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD3_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD3_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD3_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD3_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD3_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD3_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD3_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD3_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD3_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD3_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD3_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD3_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD3_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_TOUCH_PAD3_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD3_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD3_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD3_FUN_IE_S 13 +/* RTC_IO_TOUCH_PAD3_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTDO*/ +#define RTC_IO_TOUCH_PAD3_TO_GPIO (BIT(12)) +#define RTC_IO_TOUCH_PAD3_TO_GPIO_M (BIT(12)) +#define RTC_IO_TOUCH_PAD3_TO_GPIO_V 0x1 +#define RTC_IO_TOUCH_PAD3_TO_GPIO_S 12 + +#define RTC_IO_TOUCH_PAD4_REG (DR_REG_RTCIO_BASE + 0xa4) +/* RTC_IO_TOUCH_PAD4_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_TOUCH_PAD4_HOLD (BIT(31)) +#define RTC_IO_TOUCH_PAD4_HOLD_M (BIT(31)) +#define RTC_IO_TOUCH_PAD4_HOLD_V 0x1 +#define RTC_IO_TOUCH_PAD4_HOLD_S 31 +/* RTC_IO_TOUCH_PAD4_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_TOUCH_PAD4_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD4_DRV_M ((RTC_IO_TOUCH_PAD4_DRV_V)<<(RTC_IO_TOUCH_PAD4_DRV_S)) +#define RTC_IO_TOUCH_PAD4_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD4_DRV_S 29 +/* RTC_IO_TOUCH_PAD4_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_TOUCH_PAD4_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD4_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD4_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD4_RDE_S 28 +/* RTC_IO_TOUCH_PAD4_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_TOUCH_PAD4_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD4_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD4_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD4_RUE_S 27 +/* RTC_IO_TOUCH_PAD4_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ +#define RTC_IO_TOUCH_PAD4_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD4_DAC_M ((RTC_IO_TOUCH_PAD4_DAC_V)<<(RTC_IO_TOUCH_PAD4_DAC_S)) +#define RTC_IO_TOUCH_PAD4_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD4_DAC_S 23 +/* RTC_IO_TOUCH_PAD4_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: start touch sensor.*/ +#define RTC_IO_TOUCH_PAD4_START (BIT(22)) +#define RTC_IO_TOUCH_PAD4_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD4_START_V 0x1 +#define RTC_IO_TOUCH_PAD4_START_S 22 +/* RTC_IO_TOUCH_PAD4_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ +#define RTC_IO_TOUCH_PAD4_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD4_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD4_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD4_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD4_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: touch sensor power on.*/ +#define RTC_IO_TOUCH_PAD4_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD4_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD4_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD4_XPD_S 20 +/* RTC_IO_TOUCH_PAD4_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_TOUCH_PAD4_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD4_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD4_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD4_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD4_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD4_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD4_FUN_SEL_M ((RTC_IO_TOUCH_PAD4_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD4_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD4_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD4_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD4_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD4_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD4_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD4_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD4_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD4_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD4_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD4_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD4_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD4_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD4_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD4_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD4_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD4_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD4_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD4_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_TOUCH_PAD4_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD4_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD4_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD4_FUN_IE_S 13 +/* RTC_IO_TOUCH_PAD4_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTCK*/ +#define RTC_IO_TOUCH_PAD4_TO_GPIO (BIT(12)) +#define RTC_IO_TOUCH_PAD4_TO_GPIO_M (BIT(12)) +#define RTC_IO_TOUCH_PAD4_TO_GPIO_V 0x1 +#define RTC_IO_TOUCH_PAD4_TO_GPIO_S 12 + +#define RTC_IO_TOUCH_PAD5_REG (DR_REG_RTCIO_BASE + 0xa8) +/* RTC_IO_TOUCH_PAD5_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_TOUCH_PAD5_HOLD (BIT(31)) +#define RTC_IO_TOUCH_PAD5_HOLD_M (BIT(31)) +#define RTC_IO_TOUCH_PAD5_HOLD_V 0x1 +#define RTC_IO_TOUCH_PAD5_HOLD_S 31 +/* RTC_IO_TOUCH_PAD5_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_TOUCH_PAD5_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD5_DRV_M ((RTC_IO_TOUCH_PAD5_DRV_V)<<(RTC_IO_TOUCH_PAD5_DRV_S)) +#define RTC_IO_TOUCH_PAD5_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD5_DRV_S 29 +/* RTC_IO_TOUCH_PAD5_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_TOUCH_PAD5_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD5_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD5_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD5_RDE_S 28 +/* RTC_IO_TOUCH_PAD5_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_TOUCH_PAD5_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD5_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD5_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD5_RUE_S 27 +/* RTC_IO_TOUCH_PAD5_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ +#define RTC_IO_TOUCH_PAD5_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD5_DAC_M ((RTC_IO_TOUCH_PAD5_DAC_V)<<(RTC_IO_TOUCH_PAD5_DAC_S)) +#define RTC_IO_TOUCH_PAD5_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD5_DAC_S 23 +/* RTC_IO_TOUCH_PAD5_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: start touch sensor.*/ +#define RTC_IO_TOUCH_PAD5_START (BIT(22)) +#define RTC_IO_TOUCH_PAD5_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD5_START_V 0x1 +#define RTC_IO_TOUCH_PAD5_START_S 22 +/* RTC_IO_TOUCH_PAD5_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ +#define RTC_IO_TOUCH_PAD5_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD5_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD5_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD5_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD5_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: touch sensor power on.*/ +#define RTC_IO_TOUCH_PAD5_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD5_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD5_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD5_XPD_S 20 +/* RTC_IO_TOUCH_PAD5_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_TOUCH_PAD5_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD5_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD5_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD5_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD5_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD5_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD5_FUN_SEL_M ((RTC_IO_TOUCH_PAD5_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD5_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD5_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD5_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD5_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD5_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD5_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD5_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD5_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD5_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD5_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD5_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD5_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD5_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD5_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD5_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD5_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD5_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD5_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD5_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_TOUCH_PAD5_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD5_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD5_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD5_FUN_IE_S 13 +/* RTC_IO_TOUCH_PAD5_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTDI*/ +#define RTC_IO_TOUCH_PAD5_TO_GPIO (BIT(12)) +#define RTC_IO_TOUCH_PAD5_TO_GPIO_M (BIT(12)) +#define RTC_IO_TOUCH_PAD5_TO_GPIO_V 0x1 +#define RTC_IO_TOUCH_PAD5_TO_GPIO_S 12 + +#define RTC_IO_TOUCH_PAD6_REG (DR_REG_RTCIO_BASE + 0xac) +/* RTC_IO_TOUCH_PAD6_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_TOUCH_PAD6_HOLD (BIT(31)) +#define RTC_IO_TOUCH_PAD6_HOLD_M (BIT(31)) +#define RTC_IO_TOUCH_PAD6_HOLD_V 0x1 +#define RTC_IO_TOUCH_PAD6_HOLD_S 31 +/* RTC_IO_TOUCH_PAD6_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_TOUCH_PAD6_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD6_DRV_M ((RTC_IO_TOUCH_PAD6_DRV_V)<<(RTC_IO_TOUCH_PAD6_DRV_S)) +#define RTC_IO_TOUCH_PAD6_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD6_DRV_S 29 +/* RTC_IO_TOUCH_PAD6_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_TOUCH_PAD6_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD6_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD6_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD6_RDE_S 28 +/* RTC_IO_TOUCH_PAD6_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_TOUCH_PAD6_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD6_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD6_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD6_RUE_S 27 +/* RTC_IO_TOUCH_PAD6_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ +#define RTC_IO_TOUCH_PAD6_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD6_DAC_M ((RTC_IO_TOUCH_PAD6_DAC_V)<<(RTC_IO_TOUCH_PAD6_DAC_S)) +#define RTC_IO_TOUCH_PAD6_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD6_DAC_S 23 +/* RTC_IO_TOUCH_PAD6_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: start touch sensor.*/ +#define RTC_IO_TOUCH_PAD6_START (BIT(22)) +#define RTC_IO_TOUCH_PAD6_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD6_START_V 0x1 +#define RTC_IO_TOUCH_PAD6_START_S 22 +/* RTC_IO_TOUCH_PAD6_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ +#define RTC_IO_TOUCH_PAD6_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD6_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD6_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD6_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD6_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: touch sensor power on.*/ +#define RTC_IO_TOUCH_PAD6_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD6_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD6_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD6_XPD_S 20 +/* RTC_IO_TOUCH_PAD6_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_TOUCH_PAD6_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD6_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD6_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD6_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD6_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD6_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD6_FUN_SEL_M ((RTC_IO_TOUCH_PAD6_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD6_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD6_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD6_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD6_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD6_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD6_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD6_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD6_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD6_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD6_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD6_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD6_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD6_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD6_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD6_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD6_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD6_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD6_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD6_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_TOUCH_PAD6_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD6_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD6_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD6_FUN_IE_S 13 +/* RTC_IO_TOUCH_PAD6_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTMS*/ +#define RTC_IO_TOUCH_PAD6_TO_GPIO (BIT(12)) +#define RTC_IO_TOUCH_PAD6_TO_GPIO_M (BIT(12)) +#define RTC_IO_TOUCH_PAD6_TO_GPIO_V 0x1 +#define RTC_IO_TOUCH_PAD6_TO_GPIO_S 12 + +#define RTC_IO_TOUCH_PAD7_REG (DR_REG_RTCIO_BASE + 0xb0) +/* RTC_IO_TOUCH_PAD7_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_TOUCH_PAD7_HOLD (BIT(31)) +#define RTC_IO_TOUCH_PAD7_HOLD_M (BIT(31)) +#define RTC_IO_TOUCH_PAD7_HOLD_V 0x1 +#define RTC_IO_TOUCH_PAD7_HOLD_S 31 +/* RTC_IO_TOUCH_PAD7_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_TOUCH_PAD7_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD7_DRV_M ((RTC_IO_TOUCH_PAD7_DRV_V)<<(RTC_IO_TOUCH_PAD7_DRV_S)) +#define RTC_IO_TOUCH_PAD7_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD7_DRV_S 29 +/* RTC_IO_TOUCH_PAD7_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_TOUCH_PAD7_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD7_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD7_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD7_RDE_S 28 +/* RTC_IO_TOUCH_PAD7_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_TOUCH_PAD7_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD7_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD7_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD7_RUE_S 27 +/* RTC_IO_TOUCH_PAD7_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ +#define RTC_IO_TOUCH_PAD7_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD7_DAC_M ((RTC_IO_TOUCH_PAD7_DAC_V)<<(RTC_IO_TOUCH_PAD7_DAC_S)) +#define RTC_IO_TOUCH_PAD7_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD7_DAC_S 23 +/* RTC_IO_TOUCH_PAD7_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: start touch sensor.*/ +#define RTC_IO_TOUCH_PAD7_START (BIT(22)) +#define RTC_IO_TOUCH_PAD7_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD7_START_V 0x1 +#define RTC_IO_TOUCH_PAD7_START_S 22 +/* RTC_IO_TOUCH_PAD7_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ +#define RTC_IO_TOUCH_PAD7_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD7_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD7_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD7_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD7_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: touch sensor power on.*/ +#define RTC_IO_TOUCH_PAD7_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD7_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD7_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD7_XPD_S 20 +/* RTC_IO_TOUCH_PAD7_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_TOUCH_PAD7_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD7_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD7_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD7_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD7_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD7_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD7_FUN_SEL_M ((RTC_IO_TOUCH_PAD7_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD7_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD7_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD7_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD7_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD7_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD7_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD7_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD7_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD7_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD7_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD7_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD7_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD7_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD7_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD7_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD7_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD7_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD7_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD7_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_TOUCH_PAD7_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD7_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD7_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD7_FUN_IE_S 13 +/* RTC_IO_TOUCH_PAD7_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO27*/ +#define RTC_IO_TOUCH_PAD7_TO_GPIO (BIT(12)) +#define RTC_IO_TOUCH_PAD7_TO_GPIO_M (BIT(12)) +#define RTC_IO_TOUCH_PAD7_TO_GPIO_V 0x1 +#define RTC_IO_TOUCH_PAD7_TO_GPIO_S 12 + +#define RTC_IO_TOUCH_PAD8_REG (DR_REG_RTCIO_BASE + 0xb4) +/* RTC_IO_TOUCH_PAD8_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ +#define RTC_IO_TOUCH_PAD8_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD8_DAC_M ((RTC_IO_TOUCH_PAD8_DAC_V)<<(RTC_IO_TOUCH_PAD8_DAC_S)) +#define RTC_IO_TOUCH_PAD8_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD8_DAC_S 23 +/* RTC_IO_TOUCH_PAD8_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: start touch sensor.*/ +#define RTC_IO_TOUCH_PAD8_START (BIT(22)) +#define RTC_IO_TOUCH_PAD8_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD8_START_V 0x1 +#define RTC_IO_TOUCH_PAD8_START_S 22 +/* RTC_IO_TOUCH_PAD8_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ +#define RTC_IO_TOUCH_PAD8_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD8_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD8_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD8_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD8_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: touch sensor power on.*/ +#define RTC_IO_TOUCH_PAD8_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD8_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD8_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD8_XPD_S 20 +/* RTC_IO_TOUCH_PAD8_TO_GPIO : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale*/ +#define RTC_IO_TOUCH_PAD8_TO_GPIO (BIT(19)) +#define RTC_IO_TOUCH_PAD8_TO_GPIO_M (BIT(19)) +#define RTC_IO_TOUCH_PAD8_TO_GPIO_V 0x1 +#define RTC_IO_TOUCH_PAD8_TO_GPIO_S 19 + +#define RTC_IO_TOUCH_PAD9_REG (DR_REG_RTCIO_BASE + 0xb8) +/* RTC_IO_TOUCH_PAD9_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ +#define RTC_IO_TOUCH_PAD9_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD9_DAC_M ((RTC_IO_TOUCH_PAD9_DAC_V)<<(RTC_IO_TOUCH_PAD9_DAC_S)) +#define RTC_IO_TOUCH_PAD9_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD9_DAC_S 23 +/* RTC_IO_TOUCH_PAD9_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: start touch sensor.*/ +#define RTC_IO_TOUCH_PAD9_START (BIT(22)) +#define RTC_IO_TOUCH_PAD9_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD9_START_V 0x1 +#define RTC_IO_TOUCH_PAD9_START_S 22 +/* RTC_IO_TOUCH_PAD9_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ +#define RTC_IO_TOUCH_PAD9_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD9_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD9_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD9_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD9_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: touch sensor power on.*/ +#define RTC_IO_TOUCH_PAD9_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD9_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD9_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD9_XPD_S 20 +/* RTC_IO_TOUCH_PAD9_TO_GPIO : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale*/ +#define RTC_IO_TOUCH_PAD9_TO_GPIO (BIT(19)) +#define RTC_IO_TOUCH_PAD9_TO_GPIO_M (BIT(19)) +#define RTC_IO_TOUCH_PAD9_TO_GPIO_V 0x1 +#define RTC_IO_TOUCH_PAD9_TO_GPIO_S 19 + +#define RTC_IO_EXT_WAKEUP0_REG (DR_REG_RTCIO_BASE + 0xbc) +/* RTC_IO_EXT_WAKEUP0_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */ +/*description: select the wakeup source Ó0Ó select GPIO0 Ó1Ó select GPIO2 ...Ò17Ó select GPIO17*/ +#define RTC_IO_EXT_WAKEUP0_SEL 0x0000001F +#define RTC_IO_EXT_WAKEUP0_SEL_M ((RTC_IO_EXT_WAKEUP0_SEL_V)<<(RTC_IO_EXT_WAKEUP0_SEL_S)) +#define RTC_IO_EXT_WAKEUP0_SEL_V 0x1F +#define RTC_IO_EXT_WAKEUP0_SEL_S 27 + +#define RTC_IO_XTL_EXT_CTR_REG (DR_REG_RTCIO_BASE + 0xc0) +/* RTC_IO_XTL_EXT_CTR_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */ +/*description: select the external xtl power source Ó0Ó select GPIO0 Ó1Ó select + GPIO2 ...Ò17Ó select GPIO17*/ +#define RTC_IO_XTL_EXT_CTR_SEL 0x0000001F +#define RTC_IO_XTL_EXT_CTR_SEL_M ((RTC_IO_XTL_EXT_CTR_SEL_V)<<(RTC_IO_XTL_EXT_CTR_SEL_S)) +#define RTC_IO_XTL_EXT_CTR_SEL_V 0x1F +#define RTC_IO_XTL_EXT_CTR_SEL_S 27 + +#define RTC_IO_SAR_I2C_IO_REG (DR_REG_RTCIO_BASE + 0xc4) +/* RTC_IO_SAR_I2C_SDA_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: Ò0Ó using TOUCH_PAD[1] as i2c sda Ò1Ó using TOUCH_PAD[3] as i2c sda*/ +#define RTC_IO_SAR_I2C_SDA_SEL 0x00000003 +#define RTC_IO_SAR_I2C_SDA_SEL_M ((RTC_IO_SAR_I2C_SDA_SEL_V)<<(RTC_IO_SAR_I2C_SDA_SEL_S)) +#define RTC_IO_SAR_I2C_SDA_SEL_V 0x3 +#define RTC_IO_SAR_I2C_SDA_SEL_S 30 +/* RTC_IO_SAR_I2C_SCL_SEL : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ +/*description: Ò0Ó using TOUCH_PAD[0] as i2c clk Ò1Ó using TOUCH_PAD[2] as i2c clk*/ +#define RTC_IO_SAR_I2C_SCL_SEL 0x00000003 +#define RTC_IO_SAR_I2C_SCL_SEL_M ((RTC_IO_SAR_I2C_SCL_SEL_V)<<(RTC_IO_SAR_I2C_SCL_SEL_S)) +#define RTC_IO_SAR_I2C_SCL_SEL_V 0x3 +#define RTC_IO_SAR_I2C_SCL_SEL_S 28 +/* RTC_IO_SAR_DEBUG_BIT_SEL : R/W ;bitpos:[27:23] ;default: 5'h0 ; */ +/*description: */ +#define RTC_IO_SAR_DEBUG_BIT_SEL 0x0000001F +#define RTC_IO_SAR_DEBUG_BIT_SEL_M ((RTC_IO_SAR_DEBUG_BIT_SEL_V)<<(RTC_IO_SAR_DEBUG_BIT_SEL_S)) +#define RTC_IO_SAR_DEBUG_BIT_SEL_V 0x1F +#define RTC_IO_SAR_DEBUG_BIT_SEL_S 23 + +#define RTC_IO_DATE_REG (DR_REG_RTCIO_BASE + 0xc8) +/* RTC_IO_IO_DATE : R/W ;bitpos:[27:0] ;default: 28'h1603160 ; */ +/*description: date*/ +#define RTC_IO_IO_DATE 0x0FFFFFFF +#define RTC_IO_IO_DATE_M ((RTC_IO_IO_DATE_V)<<(RTC_IO_IO_DATE_S)) +#define RTC_IO_IO_DATE_V 0xFFFFFFF +#define RTC_IO_IO_DATE_S 0 +#define RTC_IO_RTC_IO_DATE_VERSION 0x1703160 + + + + +#endif /*_SOC_RTC_IO_REG_H_ */ + + diff --git a/tools/sdk/include/esp32/soc/saradc_reg.h b/tools/sdk/include/esp32/soc/saradc_reg.h new file mode 100644 index 00000000..51903297 --- /dev/null +++ b/tools/sdk/include/esp32/soc/saradc_reg.h @@ -0,0 +1,1047 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_SARADC_REG_H_ +#define _SOC_SARADC_REG_H_ + + +#include "soc.h" +#define SARADC_SAR_READ_CTRL_REG (DR_REG_SARADC_BASE + 0x0000) +/* SARADC_SAR1_DATA_INV : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: Invert SAR ADC1 data*/ +#define SARADC_SAR1_DATA_INV (BIT(28)) +#define SARADC_SAR1_DATA_INV_M (BIT(28)) +#define SARADC_SAR1_DATA_INV_V 0x1 +#define SARADC_SAR1_DATA_INV_S 28 +/* SARADC_SAR1_DIG_FORCE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: 1: SAR ADC1 controlled by DIG ADC1 CTRL 0: SAR ADC1 controlled by RTC ADC1 CTRL*/ +#define SARADC_SAR1_DIG_FORCE (BIT(27)) +#define SARADC_SAR1_DIG_FORCE_M (BIT(27)) +#define SARADC_SAR1_DIG_FORCE_V 0x1 +#define SARADC_SAR1_DIG_FORCE_S 27 +/* SARADC_SAR1_SAMPLE_NUM : R/W ;bitpos:[26:19] ;default: 8'd0 ; */ +/*description: */ +#define SARADC_SAR1_SAMPLE_NUM 0x000000FF +#define SARADC_SAR1_SAMPLE_NUM_M ((SARADC_SAR1_SAMPLE_NUM_V)<<(SARADC_SAR1_SAMPLE_NUM_S)) +#define SARADC_SAR1_SAMPLE_NUM_V 0xFF +#define SARADC_SAR1_SAMPLE_NUM_S 19 +/* SARADC_SAR1_CLK_GATED : R/W ;bitpos:[18] ;default: 1'b1 ; */ +/*description: */ +#define SARADC_SAR1_CLK_GATED (BIT(18)) +#define SARADC_SAR1_CLK_GATED_M (BIT(18)) +#define SARADC_SAR1_CLK_GATED_V 0x1 +#define SARADC_SAR1_CLK_GATED_S 18 +/* SARADC_SAR1_SAMPLE_BIT : R/W ;bitpos:[17:16] ;default: 2'd3 ; */ +/*description: 00: for 9-bit width 01: for 10-bit width 10: for 11-bit width + 11: for 12-bit width*/ +#define SARADC_SAR1_SAMPLE_BIT 0x00000003 +#define SARADC_SAR1_SAMPLE_BIT_M ((SARADC_SAR1_SAMPLE_BIT_V)<<(SARADC_SAR1_SAMPLE_BIT_S)) +#define SARADC_SAR1_SAMPLE_BIT_V 0x3 +#define SARADC_SAR1_SAMPLE_BIT_S 16 +/* SARADC_SAR1_SAMPLE_CYCLE : R/W ;bitpos:[15:8] ;default: 8'd9 ; */ +/*description: sample cycles for SAR ADC1*/ +#define SARADC_SAR1_SAMPLE_CYCLE 0x000000FF +#define SARADC_SAR1_SAMPLE_CYCLE_M ((SARADC_SAR1_SAMPLE_CYCLE_V)<<(SARADC_SAR1_SAMPLE_CYCLE_S)) +#define SARADC_SAR1_SAMPLE_CYCLE_V 0xFF +#define SARADC_SAR1_SAMPLE_CYCLE_S 8 +/* SARADC_SAR1_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd2 ; */ +/*description: clock divider*/ +#define SARADC_SAR1_CLK_DIV 0x000000FF +#define SARADC_SAR1_CLK_DIV_M ((SARADC_SAR1_CLK_DIV_V)<<(SARADC_SAR1_CLK_DIV_S)) +#define SARADC_SAR1_CLK_DIV_V 0xFF +#define SARADC_SAR1_CLK_DIV_S 0 + +#define SARADC_SAR_READ_STATUS1_REG (DR_REG_SARADC_BASE + 0x0004) +/* SARADC_SAR1_READER_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SARADC_SAR1_READER_STATUS 0xFFFFFFFF +#define SARADC_SAR1_READER_STATUS_M ((SARADC_SAR1_READER_STATUS_V)<<(SARADC_SAR1_READER_STATUS_S)) +#define SARADC_SAR1_READER_STATUS_V 0xFFFFFFFF +#define SARADC_SAR1_READER_STATUS_S 0 + +#define SARADC_SAR_MEAS_WAIT1_REG (DR_REG_SARADC_BASE + 0x0008) +/* SARADC_SAR_AMP_WAIT2 : R/W ;bitpos:[31:16] ;default: 16'd10 ; */ +/*description: */ +#define SARADC_SAR_AMP_WAIT2 0x0000FFFF +#define SARADC_SAR_AMP_WAIT2_M ((SARADC_SAR_AMP_WAIT2_V)<<(SARADC_SAR_AMP_WAIT2_S)) +#define SARADC_SAR_AMP_WAIT2_V 0xFFFF +#define SARADC_SAR_AMP_WAIT2_S 16 +/* SARADC_SAR_AMP_WAIT1 : R/W ;bitpos:[15:0] ;default: 16'd10 ; */ +/*description: */ +#define SARADC_SAR_AMP_WAIT1 0x0000FFFF +#define SARADC_SAR_AMP_WAIT1_M ((SARADC_SAR_AMP_WAIT1_V)<<(SARADC_SAR_AMP_WAIT1_S)) +#define SARADC_SAR_AMP_WAIT1_V 0xFFFF +#define SARADC_SAR_AMP_WAIT1_S 0 + +#define SARADC_SAR_MEAS_WAIT2_REG (DR_REG_SARADC_BASE + 0x000c) +/* SARADC_SAR2_RSTB_WAIT : R/W ;bitpos:[27:20] ;default: 8'd2 ; */ +/*description: */ +#define SARADC_SAR2_RSTB_WAIT 0x000000FF +#define SARADC_SAR2_RSTB_WAIT_M ((SARADC_SAR2_RSTB_WAIT_V)<<(SARADC_SAR2_RSTB_WAIT_S)) +#define SARADC_SAR2_RSTB_WAIT_V 0xFF +#define SARADC_SAR2_RSTB_WAIT_S 20 +/* SARADC_FORCE_XPD_SAR : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: */ +#define SARADC_FORCE_XPD_SAR 0x00000003 +#define SARADC_FORCE_XPD_SAR_M ((SARADC_FORCE_XPD_SAR_V)<<(SARADC_FORCE_XPD_SAR_S)) +#define SARADC_FORCE_XPD_SAR_V 0x3 +#define SARADC_FORCE_XPD_SAR_S 18 +/* SARADC_FORCE_XPD_AMP : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: */ +#define SARADC_FORCE_XPD_AMP 0x00000003 +#define SARADC_FORCE_XPD_AMP_M ((SARADC_FORCE_XPD_AMP_V)<<(SARADC_FORCE_XPD_AMP_S)) +#define SARADC_FORCE_XPD_AMP_V 0x3 +#define SARADC_FORCE_XPD_AMP_S 16 +/* SARADC_SAR_AMP_WAIT3 : R/W ;bitpos:[15:0] ;default: 16'd10 ; */ +/*description: */ +#define SARADC_SAR_AMP_WAIT3 0x0000FFFF +#define SARADC_SAR_AMP_WAIT3_M ((SARADC_SAR_AMP_WAIT3_V)<<(SARADC_SAR_AMP_WAIT3_S)) +#define SARADC_SAR_AMP_WAIT3_V 0xFFFF +#define SARADC_SAR_AMP_WAIT3_S 0 + +#define SARADC_SAR_MEAS_CTRL_REG (DR_REG_SARADC_BASE + 0x0010) +/* SARADC_SAR2_XPD_WAIT : R/W ;bitpos:[31:24] ;default: 8'h7 ; */ +/*description: */ +#define SARADC_SAR2_XPD_WAIT 0x000000FF +#define SARADC_SAR2_XPD_WAIT_M ((SARADC_SAR2_XPD_WAIT_V)<<(SARADC_SAR2_XPD_WAIT_S)) +#define SARADC_SAR2_XPD_WAIT_V 0xFF +#define SARADC_SAR2_XPD_WAIT_S 24 +/* SARADC_SAR_RSTB_FSM : R/W ;bitpos:[23:20] ;default: 4'b0000 ; */ +/*description: */ +#define SARADC_SAR_RSTB_FSM 0x0000000F +#define SARADC_SAR_RSTB_FSM_M ((SARADC_SAR_RSTB_FSM_V)<<(SARADC_SAR_RSTB_FSM_S)) +#define SARADC_SAR_RSTB_FSM_V 0xF +#define SARADC_SAR_RSTB_FSM_S 20 +/* SARADC_XPD_SAR_FSM : R/W ;bitpos:[19:16] ;default: 4'b0111 ; */ +/*description: */ +#define SARADC_XPD_SAR_FSM 0x0000000F +#define SARADC_XPD_SAR_FSM_M ((SARADC_XPD_SAR_FSM_V)<<(SARADC_XPD_SAR_FSM_S)) +#define SARADC_XPD_SAR_FSM_V 0xF +#define SARADC_XPD_SAR_FSM_S 16 +/* SARADC_AMP_SHORT_REF_GND_FSM : R/W ;bitpos:[15:12] ;default: 4'b0011 ; */ +/*description: */ +#define SARADC_AMP_SHORT_REF_GND_FSM 0x0000000F +#define SARADC_AMP_SHORT_REF_GND_FSM_M ((SARADC_AMP_SHORT_REF_GND_FSM_V)<<(SARADC_AMP_SHORT_REF_GND_FSM_S)) +#define SARADC_AMP_SHORT_REF_GND_FSM_V 0xF +#define SARADC_AMP_SHORT_REF_GND_FSM_S 12 +/* SARADC_AMP_SHORT_REF_FSM : R/W ;bitpos:[11:8] ;default: 4'b0011 ; */ +/*description: */ +#define SARADC_AMP_SHORT_REF_FSM 0x0000000F +#define SARADC_AMP_SHORT_REF_FSM_M ((SARADC_AMP_SHORT_REF_FSM_V)<<(SARADC_AMP_SHORT_REF_FSM_S)) +#define SARADC_AMP_SHORT_REF_FSM_V 0xF +#define SARADC_AMP_SHORT_REF_FSM_S 8 +/* SARADC_AMP_RST_FB_FSM : R/W ;bitpos:[7:4] ;default: 4'b1000 ; */ +/*description: */ +#define SARADC_AMP_RST_FB_FSM 0x0000000F +#define SARADC_AMP_RST_FB_FSM_M ((SARADC_AMP_RST_FB_FSM_V)<<(SARADC_AMP_RST_FB_FSM_S)) +#define SARADC_AMP_RST_FB_FSM_V 0xF +#define SARADC_AMP_RST_FB_FSM_S 4 +/* SARADC_XPD_SAR_AMP_FSM : R/W ;bitpos:[3:0] ;default: 4'b1111 ; */ +/*description: */ +#define SARADC_XPD_SAR_AMP_FSM 0x0000000F +#define SARADC_XPD_SAR_AMP_FSM_M ((SARADC_XPD_SAR_AMP_FSM_V)<<(SARADC_XPD_SAR_AMP_FSM_S)) +#define SARADC_XPD_SAR_AMP_FSM_V 0xF +#define SARADC_XPD_SAR_AMP_FSM_S 0 + +#define SARADC_SAR_READ_STATUS2_REG (DR_REG_SARADC_BASE + 0x0014) +/* SARADC_SAR2_READER_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SARADC_SAR2_READER_STATUS 0xFFFFFFFF +#define SARADC_SAR2_READER_STATUS_M ((SARADC_SAR2_READER_STATUS_V)<<(SARADC_SAR2_READER_STATUS_S)) +#define SARADC_SAR2_READER_STATUS_V 0xFFFFFFFF +#define SARADC_SAR2_READER_STATUS_S 0 + +#define SARADC_ULP_CP_SLEEP_CYC0_REG (DR_REG_SARADC_BASE + 0x0018) +/* SARADC_SLEEP_CYCLES_S0 : R/W ;bitpos:[31:0] ;default: 32'd200 ; */ +/*description: sleep cycles for ULP-coprocessor timer*/ +#define SARADC_SLEEP_CYCLES_S0 0xFFFFFFFF +#define SARADC_SLEEP_CYCLES_S0_M ((SARADC_SLEEP_CYCLES_S0_V)<<(SARADC_SLEEP_CYCLES_S0_S)) +#define SARADC_SLEEP_CYCLES_S0_V 0xFFFFFFFF +#define SARADC_SLEEP_CYCLES_S0_S 0 + +#define SARADC_ULP_CP_SLEEP_CYC1_REG (DR_REG_SARADC_BASE + 0x001c) +/* SARADC_SLEEP_CYCLES_S1 : R/W ;bitpos:[31:0] ;default: 32'd100 ; */ +/*description: */ +#define SARADC_SLEEP_CYCLES_S1 0xFFFFFFFF +#define SARADC_SLEEP_CYCLES_S1_M ((SARADC_SLEEP_CYCLES_S1_V)<<(SARADC_SLEEP_CYCLES_S1_S)) +#define SARADC_SLEEP_CYCLES_S1_V 0xFFFFFFFF +#define SARADC_SLEEP_CYCLES_S1_S 0 + +#define SARADC_ULP_CP_SLEEP_CYC2_REG (DR_REG_SARADC_BASE + 0x0020) +/* SARADC_SLEEP_CYCLES_S2 : R/W ;bitpos:[31:0] ;default: 32'd50 ; */ +/*description: */ +#define SARADC_SLEEP_CYCLES_S2 0xFFFFFFFF +#define SARADC_SLEEP_CYCLES_S2_M ((SARADC_SLEEP_CYCLES_S2_V)<<(SARADC_SLEEP_CYCLES_S2_S)) +#define SARADC_SLEEP_CYCLES_S2_V 0xFFFFFFFF +#define SARADC_SLEEP_CYCLES_S2_S 0 + +#define SARADC_ULP_CP_SLEEP_CYC3_REG (DR_REG_SARADC_BASE + 0x0024) +/* SARADC_SLEEP_CYCLES_S3 : R/W ;bitpos:[31:0] ;default: 32'd40 ; */ +/*description: */ +#define SARADC_SLEEP_CYCLES_S3 0xFFFFFFFF +#define SARADC_SLEEP_CYCLES_S3_M ((SARADC_SLEEP_CYCLES_S3_V)<<(SARADC_SLEEP_CYCLES_S3_S)) +#define SARADC_SLEEP_CYCLES_S3_V 0xFFFFFFFF +#define SARADC_SLEEP_CYCLES_S3_S 0 + +#define SARADC_ULP_CP_SLEEP_CYC4_REG (DR_REG_SARADC_BASE + 0x0028) +/* SARADC_SLEEP_CYCLES_S4 : R/W ;bitpos:[31:0] ;default: 32'd20 ; */ +/*description: */ +#define SARADC_SLEEP_CYCLES_S4 0xFFFFFFFF +#define SARADC_SLEEP_CYCLES_S4_M ((SARADC_SLEEP_CYCLES_S4_V)<<(SARADC_SLEEP_CYCLES_S4_S)) +#define SARADC_SLEEP_CYCLES_S4_V 0xFFFFFFFF +#define SARADC_SLEEP_CYCLES_S4_S 0 + +#define SARADC_SAR_START_FORCE_REG (DR_REG_SARADC_BASE + 0x002c) +/* SARADC_SAR2_PWDET_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: N/A*/ +#define SARADC_SAR2_PWDET_EN (BIT(24)) +#define SARADC_SAR2_PWDET_EN_M (BIT(24)) +#define SARADC_SAR2_PWDET_EN_V 0x1 +#define SARADC_SAR2_PWDET_EN_S 24 +/* SARADC_SAR1_STOP : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: stop SAR ADC1 conversion*/ +#define SARADC_SAR1_STOP (BIT(23)) +#define SARADC_SAR1_STOP_M (BIT(23)) +#define SARADC_SAR1_STOP_V 0x1 +#define SARADC_SAR1_STOP_S 23 +/* SARADC_SAR2_STOP : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: stop SAR ADC2 conversion*/ +#define SARADC_SAR2_STOP (BIT(22)) +#define SARADC_SAR2_STOP_M (BIT(22)) +#define SARADC_SAR2_STOP_V 0x1 +#define SARADC_SAR2_STOP_S 22 +/* SARADC_PC_INIT : R/W ;bitpos:[21:11] ;default: 11'b0 ; */ +/*description: initialized PC for ULP-coprocessor*/ +#define SARADC_PC_INIT 0x000007FF +#define SARADC_PC_INIT_M ((SARADC_PC_INIT_V)<<(SARADC_PC_INIT_S)) +#define SARADC_PC_INIT_V 0x7FF +#define SARADC_PC_INIT_S 11 +/* SARADC_SARCLK_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SARADC_SARCLK_EN (BIT(10)) +#define SARADC_SARCLK_EN_M (BIT(10)) +#define SARADC_SARCLK_EN_V 0x1 +#define SARADC_SARCLK_EN_S 10 +/* SARADC_ULP_CP_START_TOP : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Write 1 to start ULP-coprocessor only active when reg_ulp_cp_force_start_top + = 1*/ +#define SARADC_ULP_CP_START_TOP (BIT(9)) +#define SARADC_ULP_CP_START_TOP_M (BIT(9)) +#define SARADC_ULP_CP_START_TOP_V 0x1 +#define SARADC_ULP_CP_START_TOP_S 9 +/* SARADC_ULP_CP_FORCE_START_TOP : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: 1: ULP-coprocessor is started by SW 0: ULP-coprocessor is started by timer*/ +#define SARADC_ULP_CP_FORCE_START_TOP (BIT(8)) +#define SARADC_ULP_CP_FORCE_START_TOP_M (BIT(8)) +#define SARADC_ULP_CP_FORCE_START_TOP_V 0x1 +#define SARADC_ULP_CP_FORCE_START_TOP_S 8 +/* SARADC_SAR2_PWDET_CCT : R/W ;bitpos:[7:5] ;default: 3'b0 ; */ +/*description: SAR2_PWDET_CCT PA power detector capacitance tuning.*/ +#define SARADC_SAR2_PWDET_CCT 0x00000007 +#define SARADC_SAR2_PWDET_CCT_M ((SARADC_SAR2_PWDET_CCT_V)<<(SARADC_SAR2_PWDET_CCT_S)) +#define SARADC_SAR2_PWDET_CCT_V 0x7 +#define SARADC_SAR2_PWDET_CCT_S 5 +/* SARADC_SAR2_EN_TEST : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: SAR2_EN_TEST only active when reg_sar2_dig_force = 0*/ +#define SARADC_SAR2_EN_TEST (BIT(4)) +#define SARADC_SAR2_EN_TEST_M (BIT(4)) +#define SARADC_SAR2_EN_TEST_V 0x1 +#define SARADC_SAR2_EN_TEST_S 4 +/* SARADC_SAR2_BIT_WIDTH : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ +/*description: 00: 9 bit 01: 10 bits 10: 11bits 11: 12bits*/ +#define SARADC_SAR2_BIT_WIDTH 0x00000003 +#define SARADC_SAR2_BIT_WIDTH_M ((SARADC_SAR2_BIT_WIDTH_V)<<(SARADC_SAR2_BIT_WIDTH_S)) +#define SARADC_SAR2_BIT_WIDTH_V 0x3 +#define SARADC_SAR2_BIT_WIDTH_S 2 +/* SARADC_SAR1_BIT_WIDTH : R/W ;bitpos:[1:0] ;default: 2'b11 ; */ +/*description: 00: 9 bit 01: 10 bits 10: 11bits 11: 12bits*/ +#define SARADC_SAR1_BIT_WIDTH 0x00000003 +#define SARADC_SAR1_BIT_WIDTH_M ((SARADC_SAR1_BIT_WIDTH_V)<<(SARADC_SAR1_BIT_WIDTH_S)) +#define SARADC_SAR1_BIT_WIDTH_V 0x3 +#define SARADC_SAR1_BIT_WIDTH_S 0 + +#define SARADC_SAR_MEM_WR_CTRL_REG (DR_REG_SARADC_BASE + 0x0030) +/* SARADC_RTC_MEM_WR_OFFST_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */ +/*description: */ +#define SARADC_RTC_MEM_WR_OFFST_CLR (BIT(22)) +#define SARADC_RTC_MEM_WR_OFFST_CLR_M (BIT(22)) +#define SARADC_RTC_MEM_WR_OFFST_CLR_V 0x1 +#define SARADC_RTC_MEM_WR_OFFST_CLR_S 22 +/* SARADC_MEM_WR_ADDR_SIZE : R/W ;bitpos:[21:11] ;default: 11'd512 ; */ +/*description: */ +#define SARADC_MEM_WR_ADDR_SIZE 0x000007FF +#define SARADC_MEM_WR_ADDR_SIZE_M ((SARADC_MEM_WR_ADDR_SIZE_V)<<(SARADC_MEM_WR_ADDR_SIZE_S)) +#define SARADC_MEM_WR_ADDR_SIZE_V 0x7FF +#define SARADC_MEM_WR_ADDR_SIZE_S 11 +/* SARADC_MEM_WR_ADDR_INIT : R/W ;bitpos:[10:0] ;default: 11'd512 ; */ +/*description: */ +#define SARADC_MEM_WR_ADDR_INIT 0x000007FF +#define SARADC_MEM_WR_ADDR_INIT_M ((SARADC_MEM_WR_ADDR_INIT_V)<<(SARADC_MEM_WR_ADDR_INIT_S)) +#define SARADC_MEM_WR_ADDR_INIT_V 0x7FF +#define SARADC_MEM_WR_ADDR_INIT_S 0 + +#define SARADC_SAR_ATTEN1_REG (DR_REG_SARADC_BASE + 0x0034) +/* SARADC_SAR1_ATTEN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/*description: 2-bit attenuation for each pad 11:1dB 10:6dB 01:3dB 00:0dB*/ +#define SARADC_SAR1_ATTEN 0xFFFFFFFF +#define SARADC_SAR1_ATTEN_M ((SARADC_SAR1_ATTEN_V)<<(SARADC_SAR1_ATTEN_S)) +#define SARADC_SAR1_ATTEN_V 0xFFFFFFFF +#define SARADC_SAR1_ATTEN_S 0 + +#define SARADC_SAR_ATTEN2_REG (DR_REG_SARADC_BASE + 0x0038) +/* SARADC_SAR2_ATTEN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/*description: 2-bit attenuation for each pad 11:1dB 10:6dB 01:3dB 00:0dB*/ +#define SARADC_SAR2_ATTEN 0xFFFFFFFF +#define SARADC_SAR2_ATTEN_M ((SARADC_SAR2_ATTEN_V)<<(SARADC_SAR2_ATTEN_S)) +#define SARADC_SAR2_ATTEN_V 0xFFFFFFFF +#define SARADC_SAR2_ATTEN_S 0 + +#define SARADC_SAR_SLAVE_ADDR1_REG (DR_REG_SARADC_BASE + 0x003c) +/* SARADC_MEAS_STATUS : RO ;bitpos:[29:22] ;default: 8'h0 ; */ +/*description: */ +#define SARADC_MEAS_STATUS 0x000000FF +#define SARADC_MEAS_STATUS_M ((SARADC_MEAS_STATUS_V)<<(SARADC_MEAS_STATUS_S)) +#define SARADC_MEAS_STATUS_V 0xFF +#define SARADC_MEAS_STATUS_S 22 +/* SARADC_I2C_SLAVE_ADDR0 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */ +/*description: */ +#define SARADC_I2C_SLAVE_ADDR0 0x000007FF +#define SARADC_I2C_SLAVE_ADDR0_M ((SARADC_I2C_SLAVE_ADDR0_V)<<(SARADC_I2C_SLAVE_ADDR0_S)) +#define SARADC_I2C_SLAVE_ADDR0_V 0x7FF +#define SARADC_I2C_SLAVE_ADDR0_S 11 +/* SARADC_I2C_SLAVE_ADDR1 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */ +/*description: */ +#define SARADC_I2C_SLAVE_ADDR1 0x000007FF +#define SARADC_I2C_SLAVE_ADDR1_M ((SARADC_I2C_SLAVE_ADDR1_V)<<(SARADC_I2C_SLAVE_ADDR1_S)) +#define SARADC_I2C_SLAVE_ADDR1_V 0x7FF +#define SARADC_I2C_SLAVE_ADDR1_S 0 + +#define SARADC_SAR_SLAVE_ADDR2_REG (DR_REG_SARADC_BASE + 0x0040) +/* SARADC_I2C_SLAVE_ADDR2 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */ +/*description: */ +#define SARADC_I2C_SLAVE_ADDR2 0x000007FF +#define SARADC_I2C_SLAVE_ADDR2_M ((SARADC_I2C_SLAVE_ADDR2_V)<<(SARADC_I2C_SLAVE_ADDR2_S)) +#define SARADC_I2C_SLAVE_ADDR2_V 0x7FF +#define SARADC_I2C_SLAVE_ADDR2_S 11 +/* SARADC_I2C_SLAVE_ADDR3 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */ +/*description: */ +#define SARADC_I2C_SLAVE_ADDR3 0x000007FF +#define SARADC_I2C_SLAVE_ADDR3_M ((SARADC_I2C_SLAVE_ADDR3_V)<<(SARADC_I2C_SLAVE_ADDR3_S)) +#define SARADC_I2C_SLAVE_ADDR3_V 0x7FF +#define SARADC_I2C_SLAVE_ADDR3_S 0 + +#define SARADC_SAR_SLAVE_ADDR3_REG (DR_REG_SARADC_BASE + 0x0044) +/* SARADC_TSENS_RDY_OUT : RO ;bitpos:[30] ;default: 1'h0 ; */ +/*description: indicate temperature sensor out ready*/ +#define SARADC_TSENS_RDY_OUT (BIT(30)) +#define SARADC_TSENS_RDY_OUT_M (BIT(30)) +#define SARADC_TSENS_RDY_OUT_V 0x1 +#define SARADC_TSENS_RDY_OUT_S 30 +/* SARADC_TSENS_OUT : RO ;bitpos:[29:22] ;default: 8'h0 ; */ +/*description: temperature sensor data out*/ +#define SARADC_TSENS_OUT 0x000000FF +#define SARADC_TSENS_OUT_M ((SARADC_TSENS_OUT_V)<<(SARADC_TSENS_OUT_S)) +#define SARADC_TSENS_OUT_V 0xFF +#define SARADC_TSENS_OUT_S 22 +/* SARADC_I2C_SLAVE_ADDR4 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */ +/*description: */ +#define SARADC_I2C_SLAVE_ADDR4 0x000007FF +#define SARADC_I2C_SLAVE_ADDR4_M ((SARADC_I2C_SLAVE_ADDR4_V)<<(SARADC_I2C_SLAVE_ADDR4_S)) +#define SARADC_I2C_SLAVE_ADDR4_V 0x7FF +#define SARADC_I2C_SLAVE_ADDR4_S 11 +/* SARADC_I2C_SLAVE_ADDR5 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */ +/*description: */ +#define SARADC_I2C_SLAVE_ADDR5 0x000007FF +#define SARADC_I2C_SLAVE_ADDR5_M ((SARADC_I2C_SLAVE_ADDR5_V)<<(SARADC_I2C_SLAVE_ADDR5_S)) +#define SARADC_I2C_SLAVE_ADDR5_V 0x7FF +#define SARADC_I2C_SLAVE_ADDR5_S 0 + +#define SARADC_SAR_SLAVE_ADDR4_REG (DR_REG_SARADC_BASE + 0x0048) +/* SARADC_I2C_DONE : RO ;bitpos:[30] ;default: 1'h0 ; */ +/*description: indicate I2C done*/ +#define SARADC_I2C_DONE (BIT(30)) +#define SARADC_I2C_DONE_M (BIT(30)) +#define SARADC_I2C_DONE_V 0x1 +#define SARADC_I2C_DONE_S 30 +/* SARADC_I2C_RDATA : RO ;bitpos:[29:22] ;default: 8'h0 ; */ +/*description: I2C read data*/ +#define SARADC_I2C_RDATA 0x000000FF +#define SARADC_I2C_RDATA_M ((SARADC_I2C_RDATA_V)<<(SARADC_I2C_RDATA_S)) +#define SARADC_I2C_RDATA_V 0xFF +#define SARADC_I2C_RDATA_S 22 +/* SARADC_I2C_SLAVE_ADDR6 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */ +/*description: */ +#define SARADC_I2C_SLAVE_ADDR6 0x000007FF +#define SARADC_I2C_SLAVE_ADDR6_M ((SARADC_I2C_SLAVE_ADDR6_V)<<(SARADC_I2C_SLAVE_ADDR6_S)) +#define SARADC_I2C_SLAVE_ADDR6_V 0x7FF +#define SARADC_I2C_SLAVE_ADDR6_S 11 +/* SARADC_I2C_SLAVE_ADDR7 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */ +/*description: */ +#define SARADC_I2C_SLAVE_ADDR7 0x000007FF +#define SARADC_I2C_SLAVE_ADDR7_M ((SARADC_I2C_SLAVE_ADDR7_V)<<(SARADC_I2C_SLAVE_ADDR7_S)) +#define SARADC_I2C_SLAVE_ADDR7_V 0x7FF +#define SARADC_I2C_SLAVE_ADDR7_S 0 + +#define SARADC_SAR_TSENS_CTRL_REG (DR_REG_SARADC_BASE + 0x004c) +/* SARADC_TSENS_DUMP_OUT : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: temperature sensor dump out only active when reg_tsens_power_up_force = 1*/ +#define SARADC_TSENS_DUMP_OUT (BIT(26)) +#define SARADC_TSENS_DUMP_OUT_M (BIT(26)) +#define SARADC_TSENS_DUMP_OUT_V 0x1 +#define SARADC_TSENS_DUMP_OUT_S 26 +/* SARADC_TSENS_POWER_UP_FORCE : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: 1: dump out & power up controlled by SW 0: by FSM*/ +#define SARADC_TSENS_POWER_UP_FORCE (BIT(25)) +#define SARADC_TSENS_POWER_UP_FORCE_M (BIT(25)) +#define SARADC_TSENS_POWER_UP_FORCE_V 0x1 +#define SARADC_TSENS_POWER_UP_FORCE_S 25 +/* SARADC_TSENS_POWER_UP : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: temperature sensor power up*/ +#define SARADC_TSENS_POWER_UP (BIT(24)) +#define SARADC_TSENS_POWER_UP_M (BIT(24)) +#define SARADC_TSENS_POWER_UP_V 0x1 +#define SARADC_TSENS_POWER_UP_S 24 +/* SARADC_TSENS_CLK_DIV : R/W ;bitpos:[23:16] ;default: 8'd6 ; */ +/*description: temperature sensor clock divider*/ +#define SARADC_TSENS_CLK_DIV 0x000000FF +#define SARADC_TSENS_CLK_DIV_M ((SARADC_TSENS_CLK_DIV_V)<<(SARADC_TSENS_CLK_DIV_S)) +#define SARADC_TSENS_CLK_DIV_V 0xFF +#define SARADC_TSENS_CLK_DIV_S 16 +/* SARADC_TSENS_IN_INV : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: invert temperature sensor data*/ +#define SARADC_TSENS_IN_INV (BIT(15)) +#define SARADC_TSENS_IN_INV_M (BIT(15)) +#define SARADC_TSENS_IN_INV_V 0x1 +#define SARADC_TSENS_IN_INV_S 15 +/* SARADC_TSENS_CLK_GATED : R/W ;bitpos:[14] ;default: 1'b1 ; */ +/*description: */ +#define SARADC_TSENS_CLK_GATED (BIT(14)) +#define SARADC_TSENS_CLK_GATED_M (BIT(14)) +#define SARADC_TSENS_CLK_GATED_V 0x1 +#define SARADC_TSENS_CLK_GATED_S 14 +/* SARADC_TSENS_CLK_INV : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: */ +#define SARADC_TSENS_CLK_INV (BIT(13)) +#define SARADC_TSENS_CLK_INV_M (BIT(13)) +#define SARADC_TSENS_CLK_INV_V 0x1 +#define SARADC_TSENS_CLK_INV_S 13 +/* SARADC_TSENS_XPD_FORCE : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define SARADC_TSENS_XPD_FORCE (BIT(12)) +#define SARADC_TSENS_XPD_FORCE_M (BIT(12)) +#define SARADC_TSENS_XPD_FORCE_V 0x1 +#define SARADC_TSENS_XPD_FORCE_S 12 +/* SARADC_TSENS_XPD_WAIT : R/W ;bitpos:[11:0] ;default: 12'h2 ; */ +/*description: */ +#define SARADC_TSENS_XPD_WAIT 0x00000FFF +#define SARADC_TSENS_XPD_WAIT_M ((SARADC_TSENS_XPD_WAIT_V)<<(SARADC_TSENS_XPD_WAIT_S)) +#define SARADC_TSENS_XPD_WAIT_V 0xFFF +#define SARADC_TSENS_XPD_WAIT_S 0 + +#define SARADC_SAR_I2C_CTRL_REG (DR_REG_SARADC_BASE + 0x0050) +/* SARADC_SAR_I2C_START_FORCE : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: 1: I2C started by SW 0: I2C started by FSM*/ +#define SARADC_SAR_I2C_START_FORCE (BIT(29)) +#define SARADC_SAR_I2C_START_FORCE_M (BIT(29)) +#define SARADC_SAR_I2C_START_FORCE_V 0x1 +#define SARADC_SAR_I2C_START_FORCE_S 29 +/* SARADC_SAR_I2C_START : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: start I2C only active when reg_sar_i2c_start_force = 1*/ +#define SARADC_SAR_I2C_START (BIT(28)) +#define SARADC_SAR_I2C_START_M (BIT(28)) +#define SARADC_SAR_I2C_START_V 0x1 +#define SARADC_SAR_I2C_START_S 28 +/* SARADC_SAR_I2C_CTRL : R/W ;bitpos:[27:0] ;default: 28'b0 ; */ +/*description: I2C control data only active when reg_sar_i2c_start_force = 1*/ +#define SARADC_SAR_I2C_CTRL 0x0FFFFFFF +#define SARADC_SAR_I2C_CTRL_M ((SARADC_SAR_I2C_CTRL_V)<<(SARADC_SAR_I2C_CTRL_S)) +#define SARADC_SAR_I2C_CTRL_V 0xFFFFFFF +#define SARADC_SAR_I2C_CTRL_S 0 + +#define SARADC_SAR_MEAS_START1_REG (DR_REG_SARADC_BASE + 0x0054) +/* SARADC_SAR1_EN_PAD_FORCE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: 1: SAR ADC1 pad enable bitmap is controlled by SW 0: SAR ADC1 + pad enable bitmap is controlled by ULP-coprocessor*/ +#define SARADC_SAR1_EN_PAD_FORCE (BIT(31)) +#define SARADC_SAR1_EN_PAD_FORCE_M (BIT(31)) +#define SARADC_SAR1_EN_PAD_FORCE_V 0x1 +#define SARADC_SAR1_EN_PAD_FORCE_S 31 +/* SARADC_SAR1_EN_PAD : R/W ;bitpos:[30:19] ;default: 12'b0 ; */ +/*description: SAR ADC1 pad enable bitmap only active when reg_sar1_en_pad_force = 1*/ +#define SARADC_SAR1_EN_PAD 0x00000FFF +#define SARADC_SAR1_EN_PAD_M ((SARADC_SAR1_EN_PAD_V)<<(SARADC_SAR1_EN_PAD_S)) +#define SARADC_SAR1_EN_PAD_V 0xFFF +#define SARADC_SAR1_EN_PAD_S 19 +/* SARADC_MEAS1_START_FORCE : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: 1: SAR ADC1 controller (in RTC) is started by SW 0: SAR ADC1 + controller is started by ULP-coprocessor*/ +#define SARADC_MEAS1_START_FORCE (BIT(18)) +#define SARADC_MEAS1_START_FORCE_M (BIT(18)) +#define SARADC_MEAS1_START_FORCE_V 0x1 +#define SARADC_MEAS1_START_FORCE_S 18 +/* SARADC_MEAS1_START_SAR : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: SAR ADC1 controller (in RTC) starts conversion only active when + reg_meas1_start_force = 1*/ +#define SARADC_MEAS1_START_SAR (BIT(17)) +#define SARADC_MEAS1_START_SAR_M (BIT(17)) +#define SARADC_MEAS1_START_SAR_V 0x1 +#define SARADC_MEAS1_START_SAR_S 17 +/* SARADC_MEAS1_DONE_SAR : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: SAR ADC1 conversion done indication*/ +#define SARADC_MEAS1_DONE_SAR (BIT(16)) +#define SARADC_MEAS1_DONE_SAR_M (BIT(16)) +#define SARADC_MEAS1_DONE_SAR_V 0x1 +#define SARADC_MEAS1_DONE_SAR_S 16 +/* SARADC_MEAS1_DATA_SAR : RO ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: SAR ADC1 data*/ +#define SARADC_MEAS1_DATA_SAR 0x0000FFFF +#define SARADC_MEAS1_DATA_SAR_M ((SARADC_MEAS1_DATA_SAR_V)<<(SARADC_MEAS1_DATA_SAR_S)) +#define SARADC_MEAS1_DATA_SAR_V 0xFFFF +#define SARADC_MEAS1_DATA_SAR_S 0 + +#define SARADC_SAR_TOUCH_CTRL1_REG (DR_REG_SARADC_BASE + 0x0058) +/* SARADC_HALL_PHASE_FORCE : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: 1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled + by FSM in ULP-coprocessor*/ +#define SARADC_HALL_PHASE_FORCE (BIT(27)) +#define SARADC_HALL_PHASE_FORCE_M (BIT(27)) +#define SARADC_HALL_PHASE_FORCE_V 0x1 +#define SARADC_HALL_PHASE_FORCE_S 27 +/* SARADC_XPD_HALL_FORCE : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: 1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by + FSM in ULP-coprocessor*/ +#define SARADC_XPD_HALL_FORCE (BIT(26)) +#define SARADC_XPD_HALL_FORCE_M (BIT(26)) +#define SARADC_XPD_HALL_FORCE_V 0x1 +#define SARADC_XPD_HALL_FORCE_S 26 +/* SARADC_TOUCH_OUT_1EN : R/W ;bitpos:[25] ;default: 1'b1 ; */ +/*description: 1: wakeup interrupt is generated if SET1 is "touched" 0: + wakeup interrupt is generated only if SET1 & SET2 is both "touched"*/ +#define SARADC_TOUCH_OUT_1EN (BIT(25)) +#define SARADC_TOUCH_OUT_1EN_M (BIT(25)) +#define SARADC_TOUCH_OUT_1EN_V 0x1 +#define SARADC_TOUCH_OUT_1EN_S 25 +/* SARADC_TOUCH_OUT_SEL : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: 1: when the counter is greater then the threshold the touch + pad is considered as "touched" 0: when the counter is less than the threshold the touch pad is considered as "touched"*/ +#define SARADC_TOUCH_OUT_SEL (BIT(24)) +#define SARADC_TOUCH_OUT_SEL_M (BIT(24)) +#define SARADC_TOUCH_OUT_SEL_V 0x1 +#define SARADC_TOUCH_OUT_SEL_S 24 +/* SARADC_TOUCH_XPD_WAIT : R/W ;bitpos:[23:16] ;default: 8'h4 ; */ +/*description: the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD*/ +#define SARADC_TOUCH_XPD_WAIT 0x000000FF +#define SARADC_TOUCH_XPD_WAIT_M ((SARADC_TOUCH_XPD_WAIT_V)<<(SARADC_TOUCH_XPD_WAIT_S)) +#define SARADC_TOUCH_XPD_WAIT_V 0xFF +#define SARADC_TOUCH_XPD_WAIT_S 16 +/* SARADC_TOUCH_MEAS_DELAY : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ +/*description: the meas length (in 8MHz)*/ +#define SARADC_TOUCH_MEAS_DELAY 0x0000FFFF +#define SARADC_TOUCH_MEAS_DELAY_M ((SARADC_TOUCH_MEAS_DELAY_V)<<(SARADC_TOUCH_MEAS_DELAY_S)) +#define SARADC_TOUCH_MEAS_DELAY_V 0xFFFF +#define SARADC_TOUCH_MEAS_DELAY_S 0 + +#define SARADC_SAR_TOUCH_THRES1_REG (DR_REG_SARADC_BASE + 0x005c) +/* SARADC_TOUCH_OUT_TH0 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: the threshold for touch pad 0*/ +#define SARADC_TOUCH_OUT_TH0 0x0000FFFF +#define SARADC_TOUCH_OUT_TH0_M ((SARADC_TOUCH_OUT_TH0_V)<<(SARADC_TOUCH_OUT_TH0_S)) +#define SARADC_TOUCH_OUT_TH0_V 0xFFFF +#define SARADC_TOUCH_OUT_TH0_S 16 +/* SARADC_TOUCH_OUT_TH1 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: the threshold for touch pad 1*/ +#define SARADC_TOUCH_OUT_TH1 0x0000FFFF +#define SARADC_TOUCH_OUT_TH1_M ((SARADC_TOUCH_OUT_TH1_V)<<(SARADC_TOUCH_OUT_TH1_S)) +#define SARADC_TOUCH_OUT_TH1_V 0xFFFF +#define SARADC_TOUCH_OUT_TH1_S 0 + +#define SARADC_SAR_TOUCH_THRES2_REG (DR_REG_SARADC_BASE + 0x0060) +/* SARADC_TOUCH_OUT_TH2 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: the threshold for touch pad 2*/ +#define SARADC_TOUCH_OUT_TH2 0x0000FFFF +#define SARADC_TOUCH_OUT_TH2_M ((SARADC_TOUCH_OUT_TH2_V)<<(SARADC_TOUCH_OUT_TH2_S)) +#define SARADC_TOUCH_OUT_TH2_V 0xFFFF +#define SARADC_TOUCH_OUT_TH2_S 16 +/* SARADC_TOUCH_OUT_TH3 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: the threshold for touch pad 3*/ +#define SARADC_TOUCH_OUT_TH3 0x0000FFFF +#define SARADC_TOUCH_OUT_TH3_M ((SARADC_TOUCH_OUT_TH3_V)<<(SARADC_TOUCH_OUT_TH3_S)) +#define SARADC_TOUCH_OUT_TH3_V 0xFFFF +#define SARADC_TOUCH_OUT_TH3_S 0 + +#define SARADC_SAR_TOUCH_THRES3_REG (DR_REG_SARADC_BASE + 0x0064) +/* SARADC_TOUCH_OUT_TH4 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: the threshold for touch pad 4*/ +#define SARADC_TOUCH_OUT_TH4 0x0000FFFF +#define SARADC_TOUCH_OUT_TH4_M ((SARADC_TOUCH_OUT_TH4_V)<<(SARADC_TOUCH_OUT_TH4_S)) +#define SARADC_TOUCH_OUT_TH4_V 0xFFFF +#define SARADC_TOUCH_OUT_TH4_S 16 +/* SARADC_TOUCH_OUT_TH5 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: the threshold for touch pad 5*/ +#define SARADC_TOUCH_OUT_TH5 0x0000FFFF +#define SARADC_TOUCH_OUT_TH5_M ((SARADC_TOUCH_OUT_TH5_V)<<(SARADC_TOUCH_OUT_TH5_S)) +#define SARADC_TOUCH_OUT_TH5_V 0xFFFF +#define SARADC_TOUCH_OUT_TH5_S 0 + +#define SARADC_SAR_TOUCH_THRES4_REG (DR_REG_SARADC_BASE + 0x0068) +/* SARADC_TOUCH_OUT_TH6 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: the threshold for touch pad 6*/ +#define SARADC_TOUCH_OUT_TH6 0x0000FFFF +#define SARADC_TOUCH_OUT_TH6_M ((SARADC_TOUCH_OUT_TH6_V)<<(SARADC_TOUCH_OUT_TH6_S)) +#define SARADC_TOUCH_OUT_TH6_V 0xFFFF +#define SARADC_TOUCH_OUT_TH6_S 16 +/* SARADC_TOUCH_OUT_TH7 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: the threshold for touch pad 7*/ +#define SARADC_TOUCH_OUT_TH7 0x0000FFFF +#define SARADC_TOUCH_OUT_TH7_M ((SARADC_TOUCH_OUT_TH7_V)<<(SARADC_TOUCH_OUT_TH7_S)) +#define SARADC_TOUCH_OUT_TH7_V 0xFFFF +#define SARADC_TOUCH_OUT_TH7_S 0 + +#define SARADC_SAR_TOUCH_THRES5_REG (DR_REG_SARADC_BASE + 0x006c) +/* SARADC_TOUCH_OUT_TH8 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: the threshold for touch pad 8*/ +#define SARADC_TOUCH_OUT_TH8 0x0000FFFF +#define SARADC_TOUCH_OUT_TH8_M ((SARADC_TOUCH_OUT_TH8_V)<<(SARADC_TOUCH_OUT_TH8_S)) +#define SARADC_TOUCH_OUT_TH8_V 0xFFFF +#define SARADC_TOUCH_OUT_TH8_S 16 +/* SARADC_TOUCH_OUT_TH9 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: the threshold for touch pad 9*/ +#define SARADC_TOUCH_OUT_TH9 0x0000FFFF +#define SARADC_TOUCH_OUT_TH9_M ((SARADC_TOUCH_OUT_TH9_V)<<(SARADC_TOUCH_OUT_TH9_S)) +#define SARADC_TOUCH_OUT_TH9_V 0xFFFF +#define SARADC_TOUCH_OUT_TH9_S 0 + +#define SARADC_SAR_TOUCH_OUT1_REG (DR_REG_SARADC_BASE + 0x0070) +/* SARADC_TOUCH_MEAS_OUT0 : RO ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: the counter for touch pad 0*/ +#define SARADC_TOUCH_MEAS_OUT0 0x0000FFFF +#define SARADC_TOUCH_MEAS_OUT0_M ((SARADC_TOUCH_MEAS_OUT0_V)<<(SARADC_TOUCH_MEAS_OUT0_S)) +#define SARADC_TOUCH_MEAS_OUT0_V 0xFFFF +#define SARADC_TOUCH_MEAS_OUT0_S 16 +/* SARADC_TOUCH_MEAS_OUT1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: the counter for touch pad 1*/ +#define SARADC_TOUCH_MEAS_OUT1 0x0000FFFF +#define SARADC_TOUCH_MEAS_OUT1_M ((SARADC_TOUCH_MEAS_OUT1_V)<<(SARADC_TOUCH_MEAS_OUT1_S)) +#define SARADC_TOUCH_MEAS_OUT1_V 0xFFFF +#define SARADC_TOUCH_MEAS_OUT1_S 0 + +#define SARADC_SAR_TOUCH_OUT2_REG (DR_REG_SARADC_BASE + 0x0074) +/* SARADC_TOUCH_MEAS_OUT2 : RO ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: the counter for touch pad 2*/ +#define SARADC_TOUCH_MEAS_OUT2 0x0000FFFF +#define SARADC_TOUCH_MEAS_OUT2_M ((SARADC_TOUCH_MEAS_OUT2_V)<<(SARADC_TOUCH_MEAS_OUT2_S)) +#define SARADC_TOUCH_MEAS_OUT2_V 0xFFFF +#define SARADC_TOUCH_MEAS_OUT2_S 16 +/* SARADC_TOUCH_MEAS_OUT3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: the counter for touch pad 3*/ +#define SARADC_TOUCH_MEAS_OUT3 0x0000FFFF +#define SARADC_TOUCH_MEAS_OUT3_M ((SARADC_TOUCH_MEAS_OUT3_V)<<(SARADC_TOUCH_MEAS_OUT3_S)) +#define SARADC_TOUCH_MEAS_OUT3_V 0xFFFF +#define SARADC_TOUCH_MEAS_OUT3_S 0 + +#define SARADC_SAR_TOUCH_OUT3_REG (DR_REG_SARADC_BASE + 0x0078) +/* SARADC_TOUCH_MEAS_OUT4 : RO ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: the counter for touch pad 4*/ +#define SARADC_TOUCH_MEAS_OUT4 0x0000FFFF +#define SARADC_TOUCH_MEAS_OUT4_M ((SARADC_TOUCH_MEAS_OUT4_V)<<(SARADC_TOUCH_MEAS_OUT4_S)) +#define SARADC_TOUCH_MEAS_OUT4_V 0xFFFF +#define SARADC_TOUCH_MEAS_OUT4_S 16 +/* SARADC_TOUCH_MEAS_OUT5 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: the counter for touch pad 5*/ +#define SARADC_TOUCH_MEAS_OUT5 0x0000FFFF +#define SARADC_TOUCH_MEAS_OUT5_M ((SARADC_TOUCH_MEAS_OUT5_V)<<(SARADC_TOUCH_MEAS_OUT5_S)) +#define SARADC_TOUCH_MEAS_OUT5_V 0xFFFF +#define SARADC_TOUCH_MEAS_OUT5_S 0 + +#define SARADC_SAR_TOUCH_OUT4_REG (DR_REG_SARADC_BASE + 0x007c) +/* SARADC_TOUCH_MEAS_OUT6 : RO ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: the counter for touch pad 6*/ +#define SARADC_TOUCH_MEAS_OUT6 0x0000FFFF +#define SARADC_TOUCH_MEAS_OUT6_M ((SARADC_TOUCH_MEAS_OUT6_V)<<(SARADC_TOUCH_MEAS_OUT6_S)) +#define SARADC_TOUCH_MEAS_OUT6_V 0xFFFF +#define SARADC_TOUCH_MEAS_OUT6_S 16 +/* SARADC_TOUCH_MEAS_OUT7 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: the counter for touch pad 7*/ +#define SARADC_TOUCH_MEAS_OUT7 0x0000FFFF +#define SARADC_TOUCH_MEAS_OUT7_M ((SARADC_TOUCH_MEAS_OUT7_V)<<(SARADC_TOUCH_MEAS_OUT7_S)) +#define SARADC_TOUCH_MEAS_OUT7_V 0xFFFF +#define SARADC_TOUCH_MEAS_OUT7_S 0 + +#define SARADC_SAR_TOUCH_OUT5_REG (DR_REG_SARADC_BASE + 0x0080) +/* SARADC_TOUCH_MEAS_OUT8 : RO ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: the counter for touch pad 8*/ +#define SARADC_TOUCH_MEAS_OUT8 0x0000FFFF +#define SARADC_TOUCH_MEAS_OUT8_M ((SARADC_TOUCH_MEAS_OUT8_V)<<(SARADC_TOUCH_MEAS_OUT8_S)) +#define SARADC_TOUCH_MEAS_OUT8_V 0xFFFF +#define SARADC_TOUCH_MEAS_OUT8_S 16 +/* SARADC_TOUCH_MEAS_OUT9 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: the counter for touch pad 9*/ +#define SARADC_TOUCH_MEAS_OUT9 0x0000FFFF +#define SARADC_TOUCH_MEAS_OUT9_M ((SARADC_TOUCH_MEAS_OUT9_V)<<(SARADC_TOUCH_MEAS_OUT9_S)) +#define SARADC_TOUCH_MEAS_OUT9_V 0xFFFF +#define SARADC_TOUCH_MEAS_OUT9_S 0 + +#define SARADC_SAR_TOUCH_CTRL2_REG (DR_REG_SARADC_BASE + 0x0084) +/* SARADC_TOUCH_MEAS_EN_CLR : WO ;bitpos:[30] ;default: 1'h0 ; */ +/*description: to clear reg_touch_meas_en*/ +#define SARADC_TOUCH_MEAS_EN_CLR (BIT(30)) +#define SARADC_TOUCH_MEAS_EN_CLR_M (BIT(30)) +#define SARADC_TOUCH_MEAS_EN_CLR_V 0x1 +#define SARADC_TOUCH_MEAS_EN_CLR_S 30 +/* SARADC_TOUCH_SLEEP_CYCLES : R/W ;bitpos:[29:14] ;default: 16'h100 ; */ +/*description: sleep cycles for timer*/ +#define SARADC_TOUCH_SLEEP_CYCLES 0x0000FFFF +#define SARADC_TOUCH_SLEEP_CYCLES_M ((SARADC_TOUCH_SLEEP_CYCLES_V)<<(SARADC_TOUCH_SLEEP_CYCLES_S)) +#define SARADC_TOUCH_SLEEP_CYCLES_V 0xFFFF +#define SARADC_TOUCH_SLEEP_CYCLES_S 14 +/* SARADC_TOUCH_START_FORCE : R/W ;bitpos:[13] ;default: 1'h0 ; */ +/*description: 1: to start touch fsm by SW 0: to start touch fsm by timer*/ +#define SARADC_TOUCH_START_FORCE (BIT(13)) +#define SARADC_TOUCH_START_FORCE_M (BIT(13)) +#define SARADC_TOUCH_START_FORCE_V 0x1 +#define SARADC_TOUCH_START_FORCE_S 13 +/* SARADC_TOUCH_START_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */ +/*description: 1: start touch fsm valid when reg_touch_start_force is set*/ +#define SARADC_TOUCH_START_EN (BIT(12)) +#define SARADC_TOUCH_START_EN_M (BIT(12)) +#define SARADC_TOUCH_START_EN_V 0x1 +#define SARADC_TOUCH_START_EN_S 12 +/* SARADC_TOUCH_START_FSM_EN : R/W ;bitpos:[11] ;default: 1'h1 ; */ +/*description: 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm 0: TOUCH_START + & TOUCH_XPD is controlled by registers*/ +#define SARADC_TOUCH_START_FSM_EN (BIT(11)) +#define SARADC_TOUCH_START_FSM_EN_M (BIT(11)) +#define SARADC_TOUCH_START_FSM_EN_V 0x1 +#define SARADC_TOUCH_START_FSM_EN_S 11 +/* SARADC_TOUCH_MEAS_DONE : RO ;bitpos:[10] ;default: 1'h0 ; */ +/*description: fsm set 1 to indicate touch touch meas is done*/ +#define SARADC_TOUCH_MEAS_DONE (BIT(10)) +#define SARADC_TOUCH_MEAS_DONE_M (BIT(10)) +#define SARADC_TOUCH_MEAS_DONE_V 0x1 +#define SARADC_TOUCH_MEAS_DONE_S 10 +/* SARADC_TOUCH_MEAS_EN : RO ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: 10-bit register to indicate which pads are "touched"*/ +#define SARADC_TOUCH_MEAS_EN 0x000003FF +#define SARADC_TOUCH_MEAS_EN_M ((SARADC_TOUCH_MEAS_EN_V)<<(SARADC_TOUCH_MEAS_EN_S)) +#define SARADC_TOUCH_MEAS_EN_V 0x3FF +#define SARADC_TOUCH_MEAS_EN_S 0 + +#define SARADC_SAR_TOUCH_ENABLE_REG (DR_REG_SARADC_BASE + 0x008c) +/* SARADC_TOUCH_PAD_OUTEN1 : R/W ;bitpos:[29:20] ;default: 10'h3ff ; */ +/*description: Bitmap defining SET1 for generating wakeup interrupt. SET1 is + "touched" only if at least one of touch pad in SET1 is "touched".*/ +#define SARADC_TOUCH_PAD_OUTEN1 0x000003FF +#define SARADC_TOUCH_PAD_OUTEN1_M ((SARADC_TOUCH_PAD_OUTEN1_V)<<(SARADC_TOUCH_PAD_OUTEN1_S)) +#define SARADC_TOUCH_PAD_OUTEN1_V 0x3FF +#define SARADC_TOUCH_PAD_OUTEN1_S 20 +/* SARADC_TOUCH_PAD_OUTEN2 : R/W ;bitpos:[19:10] ;default: 10'h3ff ; */ +/*description: Bitmap defining SET2 for generating wakeup interrupt. SET2 is + "touched" only if at least one of touch pad in SET2 is "touched".*/ +#define SARADC_TOUCH_PAD_OUTEN2 0x000003FF +#define SARADC_TOUCH_PAD_OUTEN2_M ((SARADC_TOUCH_PAD_OUTEN2_V)<<(SARADC_TOUCH_PAD_OUTEN2_S)) +#define SARADC_TOUCH_PAD_OUTEN2_V 0x3FF +#define SARADC_TOUCH_PAD_OUTEN2_S 10 +/* SARADC_TOUCH_PAD_WORKEN : R/W ;bitpos:[9:0] ;default: 10'h3ff ; */ +/*description: Bitmap defining the working set during the measurement.*/ +#define SARADC_TOUCH_PAD_WORKEN 0x000003FF +#define SARADC_TOUCH_PAD_WORKEN_M ((SARADC_TOUCH_PAD_WORKEN_V)<<(SARADC_TOUCH_PAD_WORKEN_S)) +#define SARADC_TOUCH_PAD_WORKEN_V 0x3FF +#define SARADC_TOUCH_PAD_WORKEN_S 0 + +#define SARADC_SAR_READ_CTRL2_REG (DR_REG_SARADC_BASE + 0x0090) +/* SARADC_SAR2_DATA_INV : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Invert SAR ADC2 data*/ +#define SARADC_SAR2_DATA_INV (BIT(29)) +#define SARADC_SAR2_DATA_INV_M (BIT(29)) +#define SARADC_SAR2_DATA_INV_V 0x1 +#define SARADC_SAR2_DATA_INV_S 29 +/* SARADC_SAR2_DIG_FORCE : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: 1: SAR ADC2 controlled by DIG ADC2 CTRL or PWDET CTRL 0: SAR + ADC2 controlled by RTC ADC2 CTRL*/ +#define SARADC_SAR2_DIG_FORCE (BIT(28)) +#define SARADC_SAR2_DIG_FORCE_M (BIT(28)) +#define SARADC_SAR2_DIG_FORCE_V 0x1 +#define SARADC_SAR2_DIG_FORCE_S 28 +/* SARADC_SAR2_PWDET_FORCE : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define SARADC_SAR2_PWDET_FORCE (BIT(27)) +#define SARADC_SAR2_PWDET_FORCE_M (BIT(27)) +#define SARADC_SAR2_PWDET_FORCE_V 0x1 +#define SARADC_SAR2_PWDET_FORCE_S 27 +/* SARADC_SAR2_SAMPLE_NUM : R/W ;bitpos:[26:19] ;default: 8'd0 ; */ +/*description: */ +#define SARADC_SAR2_SAMPLE_NUM 0x000000FF +#define SARADC_SAR2_SAMPLE_NUM_M ((SARADC_SAR2_SAMPLE_NUM_V)<<(SARADC_SAR2_SAMPLE_NUM_S)) +#define SARADC_SAR2_SAMPLE_NUM_V 0xFF +#define SARADC_SAR2_SAMPLE_NUM_S 19 +/* SARADC_SAR2_CLK_GATED : R/W ;bitpos:[18] ;default: 1'b1 ; */ +/*description: */ +#define SARADC_SAR2_CLK_GATED (BIT(18)) +#define SARADC_SAR2_CLK_GATED_M (BIT(18)) +#define SARADC_SAR2_CLK_GATED_V 0x1 +#define SARADC_SAR2_CLK_GATED_S 18 +/* SARADC_SAR2_SAMPLE_BIT : R/W ;bitpos:[17:16] ;default: 2'd3 ; */ +/*description: 00: for 9-bit width 01: for 10-bit width 10: for 11-bit width + 11: for 12-bit width*/ +#define SARADC_SAR2_SAMPLE_BIT 0x00000003 +#define SARADC_SAR2_SAMPLE_BIT_M ((SARADC_SAR2_SAMPLE_BIT_V)<<(SARADC_SAR2_SAMPLE_BIT_S)) +#define SARADC_SAR2_SAMPLE_BIT_V 0x3 +#define SARADC_SAR2_SAMPLE_BIT_S 16 +/* SARADC_SAR2_SAMPLE_CYCLE : R/W ;bitpos:[15:8] ;default: 8'd9 ; */ +/*description: sample cycles for SAR ADC2*/ +#define SARADC_SAR2_SAMPLE_CYCLE 0x000000FF +#define SARADC_SAR2_SAMPLE_CYCLE_M ((SARADC_SAR2_SAMPLE_CYCLE_V)<<(SARADC_SAR2_SAMPLE_CYCLE_S)) +#define SARADC_SAR2_SAMPLE_CYCLE_V 0xFF +#define SARADC_SAR2_SAMPLE_CYCLE_S 8 +/* SARADC_SAR2_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd2 ; */ +/*description: clock divider*/ +#define SARADC_SAR2_CLK_DIV 0x000000FF +#define SARADC_SAR2_CLK_DIV_M ((SARADC_SAR2_CLK_DIV_V)<<(SARADC_SAR2_CLK_DIV_S)) +#define SARADC_SAR2_CLK_DIV_V 0xFF +#define SARADC_SAR2_CLK_DIV_S 0 + +#define SARADC_SAR_MEAS_START2_REG (DR_REG_SARADC_BASE + 0x0094) +/* SARADC_SAR2_EN_PAD_FORCE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: 1: SAR ADC2 pad enable bitmap is controlled by SW 0: SAR ADC2 + pad enable bitmap is controlled by ULP-coprocessor*/ +#define SARADC_SAR2_EN_PAD_FORCE (BIT(31)) +#define SARADC_SAR2_EN_PAD_FORCE_M (BIT(31)) +#define SARADC_SAR2_EN_PAD_FORCE_V 0x1 +#define SARADC_SAR2_EN_PAD_FORCE_S 31 +/* SARADC_SAR2_EN_PAD : R/W ;bitpos:[30:19] ;default: 12'b0 ; */ +/*description: SAR ADC2 pad enable bitmap only active when reg_sar2_en_pad_force = 1*/ +#define SARADC_SAR2_EN_PAD 0x00000FFF +#define SARADC_SAR2_EN_PAD_M ((SARADC_SAR2_EN_PAD_V)<<(SARADC_SAR2_EN_PAD_S)) +#define SARADC_SAR2_EN_PAD_V 0xFFF +#define SARADC_SAR2_EN_PAD_S 19 +/* SARADC_MEAS2_START_FORCE : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: 1: SAR ADC2 controller (in RTC) is started by SW 0: SAR ADC2 + controller is started by ULP-coprocessor*/ +#define SARADC_MEAS2_START_FORCE (BIT(18)) +#define SARADC_MEAS2_START_FORCE_M (BIT(18)) +#define SARADC_MEAS2_START_FORCE_V 0x1 +#define SARADC_MEAS2_START_FORCE_S 18 +/* SARADC_MEAS2_START_SAR : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: SAR ADC2 controller (in RTC) starts conversion only active when + reg_meas2_start_force = 1*/ +#define SARADC_MEAS2_START_SAR (BIT(17)) +#define SARADC_MEAS2_START_SAR_M (BIT(17)) +#define SARADC_MEAS2_START_SAR_V 0x1 +#define SARADC_MEAS2_START_SAR_S 17 +/* SARADC_MEAS2_DONE_SAR : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: SAR ADC2 conversion done indication*/ +#define SARADC_MEAS2_DONE_SAR (BIT(16)) +#define SARADC_MEAS2_DONE_SAR_M (BIT(16)) +#define SARADC_MEAS2_DONE_SAR_V 0x1 +#define SARADC_MEAS2_DONE_SAR_S 16 +/* SARADC_MEAS2_DATA_SAR : RO ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: SAR ADC2 data*/ +#define SARADC_MEAS2_DATA_SAR 0x0000FFFF +#define SARADC_MEAS2_DATA_SAR_M ((SARADC_MEAS2_DATA_SAR_V)<<(SARADC_MEAS2_DATA_SAR_S)) +#define SARADC_MEAS2_DATA_SAR_V 0xFFFF +#define SARADC_MEAS2_DATA_SAR_S 0 + +#define SARADC_SAR_DAC_CTRL1_REG (DR_REG_SARADC_BASE + 0x0098) +/* SARADC_DAC_CLK_INV : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: 1: invert PDAC_CLK*/ +#define SARADC_DAC_CLK_INV (BIT(25)) +#define SARADC_DAC_CLK_INV_M (BIT(25)) +#define SARADC_DAC_CLK_INV_V 0x1 +#define SARADC_DAC_CLK_INV_S 25 +/* SARADC_DAC_CLK_FORCE_HIGH : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: 1: force PDAC_CLK to high*/ +#define SARADC_DAC_CLK_FORCE_HIGH (BIT(24)) +#define SARADC_DAC_CLK_FORCE_HIGH_M (BIT(24)) +#define SARADC_DAC_CLK_FORCE_HIGH_V 0x1 +#define SARADC_DAC_CLK_FORCE_HIGH_S 24 +/* SARADC_DAC_CLK_FORCE_LOW : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: 1: force PDAC_CLK to low*/ +#define SARADC_DAC_CLK_FORCE_LOW (BIT(23)) +#define SARADC_DAC_CLK_FORCE_LOW_M (BIT(23)) +#define SARADC_DAC_CLK_FORCE_LOW_V 0x1 +#define SARADC_DAC_CLK_FORCE_LOW_S 23 +/* SARADC_DAC_DIG_FORCE : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: 1: DAC1 & DAC2 use DMA 0: DAC1 & DAC2 do not use DMA*/ +#define SARADC_DAC_DIG_FORCE (BIT(22)) +#define SARADC_DAC_DIG_FORCE_M (BIT(22)) +#define SARADC_DAC_DIG_FORCE_V 0x1 +#define SARADC_DAC_DIG_FORCE_S 22 +/* SARADC_DEBUG_BIT_SEL : R/W ;bitpos:[21:17] ;default: 5'b0 ; */ +/*description: */ +#define SARADC_DEBUG_BIT_SEL 0x0000001F +#define SARADC_DEBUG_BIT_SEL_M ((SARADC_DEBUG_BIT_SEL_V)<<(SARADC_DEBUG_BIT_SEL_S)) +#define SARADC_DEBUG_BIT_SEL_V 0x1F +#define SARADC_DEBUG_BIT_SEL_S 17 +/* SARADC_SW_TONE_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: 1: enable CW generator 0: disable CW generator*/ +#define SARADC_SW_TONE_EN (BIT(16)) +#define SARADC_SW_TONE_EN_M (BIT(16)) +#define SARADC_SW_TONE_EN_V 0x1 +#define SARADC_SW_TONE_EN_S 16 +/* SARADC_SW_FSTEP : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: frequency step for CW generator can be used to adjust the frequency*/ +#define SARADC_SW_FSTEP 0x0000FFFF +#define SARADC_SW_FSTEP_M ((SARADC_SW_FSTEP_V)<<(SARADC_SW_FSTEP_S)) +#define SARADC_SW_FSTEP_V 0xFFFF +#define SARADC_SW_FSTEP_S 0 + +#define SARADC_SAR_DAC_CTRL2_REG (DR_REG_SARADC_BASE + 0x009c) +/* SARADC_DAC_CW_EN2 : R/W ;bitpos:[25] ;default: 1'b1 ; */ +/*description: 1: to select CW generator as source to PDAC2_DAC[7:0] 0: to + select register reg_pdac2_dac[7:0] as source to PDAC2_DAC[7:0]*/ +#define SARADC_DAC_CW_EN2 (BIT(25)) +#define SARADC_DAC_CW_EN2_M (BIT(25)) +#define SARADC_DAC_CW_EN2_V 0x1 +#define SARADC_DAC_CW_EN2_S 25 +/* SARADC_DAC_CW_EN1 : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: 1: to select CW generator as source to PDAC1_DAC[7:0] 0: to + select register reg_pdac1_dac[7:0] as source to PDAC1_DAC[7:0]*/ +#define SARADC_DAC_CW_EN1 (BIT(24)) +#define SARADC_DAC_CW_EN1_M (BIT(24)) +#define SARADC_DAC_CW_EN1_V 0x1 +#define SARADC_DAC_CW_EN1_S 24 +/* SARADC_DAC_INV2 : R/W ;bitpos:[23:22] ;default: 2'b0 ; */ +/*description: 00: do not invert any bits 01: invert all bits 10: invert MSB + 11: invert all bits except MSB*/ +#define SARADC_DAC_INV2 0x00000003 +#define SARADC_DAC_INV2_M ((SARADC_DAC_INV2_V)<<(SARADC_DAC_INV2_S)) +#define SARADC_DAC_INV2_V 0x3 +#define SARADC_DAC_INV2_S 22 +/* SARADC_DAC_INV1 : R/W ;bitpos:[21:20] ;default: 2'b0 ; */ +/*description: 00: do not invert any bits 01: invert all bits 10: invert MSB + 11: invert all bits except MSB*/ +#define SARADC_DAC_INV1 0x00000003 +#define SARADC_DAC_INV1_M ((SARADC_DAC_INV1_V)<<(SARADC_DAC_INV1_S)) +#define SARADC_DAC_INV1_V 0x3 +#define SARADC_DAC_INV1_S 20 +/* SARADC_DAC_SCALE2 : R/W ;bitpos:[19:18] ;default: 2'b0 ; */ +/*description: 00: no scale 01: scale to 1/2 10: scale to 1/4 scale to 1/8*/ +#define SARADC_DAC_SCALE2 0x00000003 +#define SARADC_DAC_SCALE2_M ((SARADC_DAC_SCALE2_V)<<(SARADC_DAC_SCALE2_S)) +#define SARADC_DAC_SCALE2_V 0x3 +#define SARADC_DAC_SCALE2_S 18 +/* SARADC_DAC_SCALE1 : R/W ;bitpos:[17:16] ;default: 2'b0 ; */ +/*description: 00: no scale 01: scale to 1/2 10: scale to 1/4 scale to 1/8*/ +#define SARADC_DAC_SCALE1 0x00000003 +#define SARADC_DAC_SCALE1_M ((SARADC_DAC_SCALE1_V)<<(SARADC_DAC_SCALE1_S)) +#define SARADC_DAC_SCALE1_V 0x3 +#define SARADC_DAC_SCALE1_S 16 +/* SARADC_DAC_DC2 : R/W ;bitpos:[15:8] ;default: 8'b0 ; */ +/*description: DC offset for DAC2 CW generator*/ +#define SARADC_DAC_DC2 0x000000FF +#define SARADC_DAC_DC2_M ((SARADC_DAC_DC2_V)<<(SARADC_DAC_DC2_S)) +#define SARADC_DAC_DC2_V 0xFF +#define SARADC_DAC_DC2_S 8 +/* SARADC_DAC_DC1 : R/W ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: DC offset for DAC1 CW generator*/ +#define SARADC_DAC_DC1 0x000000FF +#define SARADC_DAC_DC1_M ((SARADC_DAC_DC1_V)<<(SARADC_DAC_DC1_S)) +#define SARADC_DAC_DC1_V 0xFF +#define SARADC_DAC_DC1_S 0 + +#define SARADC_SAR_MEAS_CTRL2_REG (DR_REG_SARADC_BASE + 0x0a0) +/* SARADC_AMP_SHORT_REF_GND_FORCE : R/W ;bitpos:[18:17] ;default: 2'b0 ; */ +/*description: */ +#define SARADC_AMP_SHORT_REF_GND_FORCE 0x00000003 +#define SARADC_AMP_SHORT_REF_GND_FORCE_M ((SARADC_AMP_SHORT_REF_GND_FORCE_V)<<(SARADC_AMP_SHORT_REF_GND_FORCE_S)) +#define SARADC_AMP_SHORT_REF_GND_FORCE_V 0x3 +#define SARADC_AMP_SHORT_REF_GND_FORCE_S 17 +/* SARADC_AMP_SHORT_REF_FORCE : R/W ;bitpos:[16:15] ;default: 2'b0 ; */ +/*description: */ +#define SARADC_AMP_SHORT_REF_FORCE 0x00000003 +#define SARADC_AMP_SHORT_REF_FORCE_M ((SARADC_AMP_SHORT_REF_FORCE_V)<<(SARADC_AMP_SHORT_REF_FORCE_S)) +#define SARADC_AMP_SHORT_REF_FORCE_V 0x3 +#define SARADC_AMP_SHORT_REF_FORCE_S 15 +/* SARADC_AMP_RST_FB_FORCE : R/W ;bitpos:[14:13] ;default: 2'b0 ; */ +/*description: */ +#define SARADC_AMP_RST_FB_FORCE 0x00000003 +#define SARADC_AMP_RST_FB_FORCE_M ((SARADC_AMP_RST_FB_FORCE_V)<<(SARADC_AMP_RST_FB_FORCE_S)) +#define SARADC_AMP_RST_FB_FORCE_V 0x3 +#define SARADC_AMP_RST_FB_FORCE_S 13 +/* SARADC_SAR2_RSTB_FORCE : R/W ;bitpos:[12:11] ;default: 2'b0 ; */ +/*description: */ +#define SARADC_SAR2_RSTB_FORCE 0x00000003 +#define SARADC_SAR2_RSTB_FORCE_M ((SARADC_SAR2_RSTB_FORCE_V)<<(SARADC_SAR2_RSTB_FORCE_S)) +#define SARADC_SAR2_RSTB_FORCE_V 0x3 +#define SARADC_SAR2_RSTB_FORCE_S 11 +/* SARADC_SAR_RSTB_FSM_IDLE : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SARADC_SAR_RSTB_FSM_IDLE (BIT(10)) +#define SARADC_SAR_RSTB_FSM_IDLE_M (BIT(10)) +#define SARADC_SAR_RSTB_FSM_IDLE_V 0x1 +#define SARADC_SAR_RSTB_FSM_IDLE_S 10 +/* SARADC_XPD_SAR_FSM_IDLE : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define SARADC_XPD_SAR_FSM_IDLE (BIT(9)) +#define SARADC_XPD_SAR_FSM_IDLE_M (BIT(9)) +#define SARADC_XPD_SAR_FSM_IDLE_V 0x1 +#define SARADC_XPD_SAR_FSM_IDLE_S 9 +/* SARADC_AMP_SHORT_REF_GND_FSM_IDLE : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SARADC_AMP_SHORT_REF_GND_FSM_IDLE (BIT(8)) +#define SARADC_AMP_SHORT_REF_GND_FSM_IDLE_M (BIT(8)) +#define SARADC_AMP_SHORT_REF_GND_FSM_IDLE_V 0x1 +#define SARADC_AMP_SHORT_REF_GND_FSM_IDLE_S 8 +/* SARADC_AMP_SHORT_REF_FSM_IDLE : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define SARADC_AMP_SHORT_REF_FSM_IDLE (BIT(7)) +#define SARADC_AMP_SHORT_REF_FSM_IDLE_M (BIT(7)) +#define SARADC_AMP_SHORT_REF_FSM_IDLE_V 0x1 +#define SARADC_AMP_SHORT_REF_FSM_IDLE_S 7 +/* SARADC_AMP_RST_FB_FSM_IDLE : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SARADC_AMP_RST_FB_FSM_IDLE (BIT(6)) +#define SARADC_AMP_RST_FB_FSM_IDLE_M (BIT(6)) +#define SARADC_AMP_RST_FB_FSM_IDLE_V 0x1 +#define SARADC_AMP_RST_FB_FSM_IDLE_S 6 +/* SARADC_XPD_SAR_AMP_FSM_IDLE : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SARADC_XPD_SAR_AMP_FSM_IDLE (BIT(5)) +#define SARADC_XPD_SAR_AMP_FSM_IDLE_M (BIT(5)) +#define SARADC_XPD_SAR_AMP_FSM_IDLE_V 0x1 +#define SARADC_XPD_SAR_AMP_FSM_IDLE_S 5 +/* SARADC_SAR1_DAC_XPD_FSM_IDLE : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SARADC_SAR1_DAC_XPD_FSM_IDLE (BIT(4)) +#define SARADC_SAR1_DAC_XPD_FSM_IDLE_M (BIT(4)) +#define SARADC_SAR1_DAC_XPD_FSM_IDLE_V 0x1 +#define SARADC_SAR1_DAC_XPD_FSM_IDLE_S 4 +/* SARADC_SAR1_DAC_XPD_FSM : R/W ;bitpos:[3:0] ;default: 4'b0011 ; */ +/*description: */ +#define SARADC_SAR1_DAC_XPD_FSM 0x0000000F +#define SARADC_SAR1_DAC_XPD_FSM_M ((SARADC_SAR1_DAC_XPD_FSM_V)<<(SARADC_SAR1_DAC_XPD_FSM_S)) +#define SARADC_SAR1_DAC_XPD_FSM_V 0xF +#define SARADC_SAR1_DAC_XPD_FSM_S 0 + +#define SARADC_SAR_NOUSE_REG (DR_REG_SARADC_BASE + 0x00F8) +/* SARADC_SAR_NOUSE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SARADC_SAR_NOUSE 0xFFFFFFFF +#define SARADC_SAR_NOUSE_M ((SARADC_SAR_NOUSE_V)<<(SARADC_SAR_NOUSE_S)) +#define SARADC_SAR_NOUSE_V 0xFFFFFFFF +#define SARADC_SAR_NOUSE_S 0 + +#define SARADC_SARDATE_REG (DR_REG_SARADC_BASE + 0x00FC) +/* SARADC_SAR_DATE : R/W ;bitpos:[27:0] ;default: 28'h1605180 ; */ +/*description: */ +#define SARADC_SAR_DATE 0x0FFFFFFF +#define SARADC_SAR_DATE_M ((SARADC_SAR_DATE_V)<<(SARADC_SAR_DATE_S)) +#define SARADC_SAR_DATE_V 0xFFFFFFF +#define SARADC_SAR_DATE_S 0 + + + + +#endif /*_SOC_SARADC_REG_H_ */ + + diff --git a/tools/sdk/include/esp32/soc/soc.h b/tools/sdk/include/esp32/soc/soc.h new file mode 100755 index 00000000..4ffdfb06 --- /dev/null +++ b/tools/sdk/include/esp32/soc/soc.h @@ -0,0 +1,312 @@ +// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _ESP32_SOC_H_ +#define _ESP32_SOC_H_ + +#include + +//Register Bits{{ +#define BIT31 0x80000000 +#define BIT30 0x40000000 +#define BIT29 0x20000000 +#define BIT28 0x10000000 +#define BIT27 0x08000000 +#define BIT26 0x04000000 +#define BIT25 0x02000000 +#define BIT24 0x01000000 +#define BIT23 0x00800000 +#define BIT22 0x00400000 +#define BIT21 0x00200000 +#define BIT20 0x00100000 +#define BIT19 0x00080000 +#define BIT18 0x00040000 +#define BIT17 0x00020000 +#define BIT16 0x00010000 +#define BIT15 0x00008000 +#define BIT14 0x00004000 +#define BIT13 0x00002000 +#define BIT12 0x00001000 +#define BIT11 0x00000800 +#define BIT10 0x00000400 +#define BIT9 0x00000200 +#define BIT8 0x00000100 +#define BIT7 0x00000080 +#define BIT6 0x00000040 +#define BIT5 0x00000020 +#define BIT4 0x00000010 +#define BIT3 0x00000008 +#define BIT2 0x00000004 +#define BIT1 0x00000002 +#define BIT0 0x00000001 +//}} + +#define PRO_CPU_NUM (0) +#define APP_CPU_NUM (1) + +//Registers Operation {{ +#define ETS_UNCACHED_ADDR(addr) (addr) +#define ETS_CACHED_ADDR(addr) (addr) + +#define BIT(nr) (1UL << (nr)) + +//write value to register +#define REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v) + +//read value from register +#define REG_READ(_r) (*(volatile uint32_t *)(_r)) + +//get bit or get bits from register +#define REG_GET_BIT(_r, _b) (*(volatile uint32_t*)(_r) & (_b)) + +//set bit or set bits to register +#define REG_SET_BIT(_r, _b) (*(volatile uint32_t*)(_r) |= (_b)) + +//clear bit or clear bits of register +#define REG_CLR_BIT(_r, _b) (*(volatile uint32_t*)(_r) &= ~(_b)) + +//set bits of register controlled by mask +#define REG_SET_BITS(_r, _b, _m) (*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m))) + +//get field from register, used when _f is not left shifted by _f##_S +#define REG_GET_FIELD(_r, _f) ((REG_READ(_r) >> (_f##_S)) & (_f)) + +//set field to register, used when _f is not left shifted by _f##_S +#define REG_SET_FIELD(_r, _f, _v) (REG_WRITE((_r),((REG_READ(_r) & ~((_f) << (_f##_S)))|(((_v) & (_f))<<(_f##_S))))) + +//get field value from a variable, used when _f is not left shifted by _f##_S +#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) + +//get field value from a variable, used when _f is left shifted by _f##_S +#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S)) + +//set field value to a variable, used when _f is not left shifted by _f##_S +#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))) + +//set field value to a variable, used when _f is left shifted by _f##_S +#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))) + +//generate a value from a field value, used when _f is not left shifted by _f##_S +#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S) + +//generate a value from a field value, used when _f is left shifted by _f##_S +#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f)) + +//read value from register +#define READ_PERI_REG(addr) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) + +//write value to register +#define WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val) + +//clear bits of register controlled by mask +#define CLEAR_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))) + +//set bits of register controlled by mask +#define SET_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))) + +//get bits of register controlled by mask +#define GET_PERI_REG_MASK(reg, mask) (READ_PERI_REG(reg) & (mask)) + +//get bits of register controlled by highest bit and lowest bit +#define GET_PERI_REG_BITS(reg, hipos,lowpos) ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)) + +//set bits of register controlled by mask and shift +#define SET_PERI_REG_BITS(reg,bit_map,value,shift) (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) )) + +//get field of register +#define GET_PERI_REG_BITS2(reg, mask,shift) ((READ_PERI_REG(reg)>>(shift))&(mask)) +//}} + +//Periheral Clock {{ +#define APB_CLK_FREQ_ROM 26*1000000 +#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM +#define CPU_CLK_FREQ APB_CLK_FREQ +#define APB_CLK_FREQ 80*1000000 //unit: Hz +#define UART_CLK_FREQ APB_CLK_FREQ +#define WDT_CLK_FREQ APB_CLK_FREQ +#define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 16 +#define SPI_CLK_DIV 4 +#define TICKS_PER_US_ROM 26 // CPU is 80MHz +//}} + +#define DR_REG_DPORT_BASE 0x3ff00000 +#define DR_REG_UART_BASE 0x3ff40000 +#define DR_REG_SPI1_BASE 0x3ff42000 +#define DR_REG_SPI0_BASE 0x3ff43000 +#define DR_REG_GPIO_BASE 0x3ff44000 +#define DR_REG_GPIO_SD_BASE 0x3ff44f00 +#define DR_REG_FE2_BASE 0x3ff45000 +#define DR_REG_FE_BASE 0x3ff46000 +#define DR_REG_RTCCNTL_BASE 0x3ff48000 +#define DR_REG_RTCIO_BASE 0x3ff48400 +#define DR_REG_SARADC_BASE 0x3ff48800 +#define DR_REG_IO_MUX_BASE 0x3ff49000 +#define DR_REG_RTCMEM0_BASE 0x3ff61000 +#define DR_REG_RTCMEM1_BASE 0x3ff62000 +#define DR_REG_RTCMEM2_BASE 0x3ff63000 +#define DR_REG_HINF_BASE 0x3ff4B000 +#define DR_REG_UHCI1_BASE 0x3ff4C000 +#define DR_REG_I2S_BASE 0x3ff4F000 +#define DR_REG_UART1_BASE 0x3ff50000 +#define DR_REG_BT_BASE 0x3ff51000 +#define DR_REG_I2C_EXT_BASE 0x3ff53000 +#define DR_REG_UHCI0_BASE 0x3ff54000 +#define DR_REG_SLCHOST_BASE 0x3ff55000 +#define DR_REG_RMT_BASE 0x3ff56000 +#define DR_REG_PCNT_BASE 0x3ff57000 +#define DR_REG_SLC_BASE 0x3ff58000 +#define DR_REG_LEDC_BASE 0x3ff59000 +#define DR_REG_EFUSE_BASE 0x3ff5A000 +#define DR_REG_SPI_ENCRYPT_BASE 0x3ff5B000 +#define DR_REG_PWM_BASE 0x3ff5E000 +#define DR_REG_TIMERGROUP0_BASE 0x3ff5F000 +#define DR_REG_TIMERGROUP1_BASE 0x3ff60000 +#define DR_REG_SPI2_BASE 0x3ff64000 +#define DR_REG_SPI3_BASE 0x3ff65000 +#define DR_REG_I2C1_EXT_BASE 0x3ff67000 +#define DR_REG_SDMMC_BASE 0x3ff68000 +#define DR_REG_EMAC_BASE 0x3ff69000 +#define DR_REG_PWM1_BASE 0x3ff6C000 +#define DR_REG_I2S1_BASE 0x3ff6D000 +#define DR_REG_UART2_BASE 0x3ff6E000 +#define DR_REG_PWM2_BASE 0x3ff6F000 +#define DR_REG_PWM3_BASE 0x3ff70000 +#define PERIPHS_SPI_ENCRYPT_BASEADDR DR_REG_SPI_ENCRYPT_BASE + +//Interrupt hardware source table +//This table is decided by hardware, don't touch this. +#define ETS_WIFI_MAC_INTR_SOURCE 0/**< interrupt of WiFi MAC, level*/ +#define ETS_WIFI_MAC_NMI_SOURCE 1/**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/ +#define ETS_WIFI_BB_INTR_SOURCE 2/**< interrupt of WiFi BB, level, we can do some calibartion*/ +#define ETS_BT_MAC_INTR_SOURCE 3/**< will be cancelled*/ +#define ETS_BT_BB_INTR_SOURCE 4/**< interrupt of BT BB, level*/ +#define ETS_BT_BB_NMI_SOURCE 5/**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/ +#define ETS_RWBT_INTR_SOURCE 6/**< interrupt of RWBT, level*/ +#define ETS_RWBLE_INTR_SOURCE 7/**< interrupt of RWBLE, level*/ +#define ETS_RWBT_NMI_SOURCE 8/**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/ +#define ETS_RWBLE_NMI_SOURCE 9/**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/ +#define ETS_SLC0_INTR_SOURCE 10/**< interrupt of SLC0, level*/ +#define ETS_SLC1_INTR_SOURCE 11/**< interrupt of SLC1, level*/ +#define ETS_UHCI0_INTR_SOURCE 12/**< interrupt of UHCI0, level*/ +#define ETS_UHCI1_INTR_SOURCE 13/**< interrupt of UHCI1, level*/ +#define ETS_TG0_T0_LEVEL_INTR_SOURCE 14/**< interrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission*/ +#define ETS_TG0_T1_LEVEL_INTR_SOURCE 15/**< interrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission*/ +#define ETS_TG0_WDT_LEVEL_INTR_SOURCE 16/**< interrupt of TIMER_GROUP0, WATCHDOG, level*/ +#define ETS_TG0_LACT_LEVEL_INTR_SOURCE 17/**< interrupt of TIMER_GROUP0, LACT, level*/ +#define ETS_TG1_T0_LEVEL_INTR_SOURCE 18/**< interrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission*/ +#define ETS_TG1_T1_LEVEL_INTR_SOURCE 19/**< interrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission*/ +#define ETS_TG1_WDT_LEVEL_INTR_SOURCE 20/**< interrupt of TIMER_GROUP1, WATCHDOG, level*/ +#define ETS_TG1_LACT_LEVEL_INTR_SOURCE 21/**< interrupt of TIMER_GROUP1, LACT, level*/ +#define ETS_GPIO_INTR_SOURCE 22/**< interrupt of GPIO, level*/ +#define ETS_GPIO_NMI_SOURCE 23/**< interrupt of GPIO, NMI*/ +#define ETS_FROM_CPU_INTR0_SOURCE 24/**< interrupt0 generated from a CPU, level*/ +#define ETS_FROM_CPU_INTR1_SOURCE 25/**< interrupt1 generated from a CPU, level*/ +#define ETS_FROM_CPU_INTR2_SOURCE 26/**< interrupt2 generated from a CPU, level*/ +#define ETS_FROM_CPU_INTR3_SOURCE 27/**< interrupt3 generated from a CPU, level*/ +#define ETS_SPI0_INTR_SOURCE 28/**< interrupt of SPI0, level, SPI0 is for Cache Access, do not use this*/ +#define ETS_SPI1_INTR_SOURCE 29/**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/ +#define ETS_SPI2_INTR_SOURCE 30/**< interrupt of SPI2, level*/ +#define ETS_SPI3_INTR_SOURCE 31/**< interrupt of SPI3, level*/ +#define ETS_I2S0_INTR_SOURCE 32/**< interrupt of I2S0, level*/ +#define ETS_I2S1_INTR_SOURCE 33/**< interrupt of I2S1, level*/ +#define ETS_UART0_INTR_SOURCE 34/**< interrupt of UART0, level*/ +#define ETS_UART1_INTR_SOURCE 35/**< interrupt of UART1, level*/ +#define ETS_UART2_INTR_SOURCE 36/**< interrupt of UART2, level*/ +#define ETS_SDIO_HOST_INTR_SOURCE 37/**< interrupt of SD/SDIO/MMC HOST, level*/ +#define ETS_ETH_MAC_INTR_SOURCE 38/**< interrupt of ethernet mac, level*/ +#define ETS_PWM0_INTR_SOURCE 39/**< interrupt of PWM0, level, Reserved*/ +#define ETS_PWM1_INTR_SOURCE 40/**< interrupt of PWM1, level, Reserved*/ +#define ETS_PWM2_INTR_SOURCE 41/**< interrupt of PWM2, level*/ +#define ETS_PWM3_INTR_SOURCE 42/**< interruot of PWM3, level*/ +#define ETS_LEDC_INTR_SOURCE 43/**< interrupt of LED PWM, level*/ +#define ETS_EFUSE_INTR_SOURCE 44/**< interrupt of efuse, level, not likely to use*/ +#define ETS_CAN_INTR_SOURCE 45/**< interrupt of can, level*/ +#define ETS_RTC_CORE_INTR_SOURCE 46/**< interrupt of rtc core, level, include rtc watchdog*/ +#define ETS_RMT_INTR_SOURCE 47/**< interrupt of remote controller, level*/ +#define ETS_PCNT_INTR_SOURCE 48/**< interrupt of pluse count, level*/ +#define ETS_I2C_EXT0_INTR_SOURCE 49/**< interrupt of I2C controller1, level*/ +#define ETS_I2C_EXT1_INTR_SOURCE 50/**< interrupt of I2C controller0, level*/ +#define ETS_RSA_INTR_SOURCE 51/**< interrupt of RSA accelerator, level*/ +#define ETS_SPI1_DMA_INTR_SOURCE 52/**< interrupt of SPI1 DMA, SPI1 is for flash read/write, do not use this*/ +#define ETS_SPI2_DMA_INTR_SOURCE 53/**< interrupt of SPI2 DMA, level*/ +#define ETS_SPI3_DMA_INTR_SOURCE 54/**< interrupt of SPI3 DMA, level*/ +#define ETS_WDT_INTR_SOURCE 55/**< will be cancelled*/ +#define ETS_TIMER1_INTR_SOURCE 56/**< will be cancelled*/ +#define ETS_TIMER2_INTR_SOURCE 57/**< will be cancelled*/ +#define ETS_TG0_T0_EDGE_INTR_SOURCE 58/**< interrupt of TIMER_GROUP0, TIMER0, EDGE*/ +#define ETS_TG0_T1_EDGE_INTR_SOURCE 59/**< interrupt of TIMER_GROUP0, TIMER1, EDGE*/ +#define ETS_TG0_WDT_EDGE_INTR_SOURCE 60/**< interrupt of TIMER_GROUP0, WATCH DOG, EDGE*/ +#define ETS_TG0_LACT_EDGE_INTR_SOURCE 61/**< interrupt of TIMER_GROUP0, LACT, EDGE*/ +#define ETS_TG1_T0_EDGE_INTR_SOURCE 62/**< interrupt of TIMER_GROUP1, TIMER0, EDGE*/ +#define ETS_TG1_T1_EDGE_INTR_SOURCE 63/**< interrupt of TIMER_GROUP1, TIMER1, EDGE*/ +#define ETS_TG1_WDT_EDGE_INTR_SOURCE 64/**< interrupt of TIMER_GROUP1, WATCHDOG, EDGE*/ +#define ETS_TG1_LACT_EDGE_INTR_SOURCE 65/**< interrupt of TIMER_GROUP0, LACT, EDGE*/ +#define ETS_MMU_IA_INTR_SOURCE 66/**< interrupt of MMU Invalid Access, LEVEL*/ +#define ETS_MPU_IA_INTR_SOURCE 67/**< interrupt of MPU Invalid Access, LEVEL*/ +#define ETS_CACHE_IA_INTR_SOURCE 68/**< interrupt of Cache Invalied Access, LEVEL*/ + +//interrupt cpu using table, Please see the core-isa.h +/************************************************************************************************************* + * Intr num Level Type PRO CPU usage APP CPU uasge + * 0 1 extern level WMAC Reserved + * 1 1 extern level BT/BLE Host VHCI Reserved + * 2 1 extern level FROM_CPU FROM_CPU + * 3 1 extern level TG0_WDT Reserved + * 4 1 extern level WBB + * 5 1 extern level BT Controller + * 6 1 timer FreeRTOS Tick(L1) FreeRTOS Tick(L1) + * 7 1 software Reserved Reserved + * 8 1 extern level BLE Controller + * 9 1 extern level + * 10 1 extern edge Internal Timer + * 11 3 profiling + * 12 1 extern level + * 13 1 extern level + * 14 7 nmi Reserved Reserved + * 15 3 timer FreeRTOS Tick(L3) FreeRTOS Tick(L3) + * 16 5 timer + * 17 1 extern level + * 18 1 extern level + * 19 2 extern level + * 20 2 extern level + * 21 2 extern level + * 22 3 extern edge + * 23 3 extern level + * 24 4 extern level + * 25 4 extern level Reserved Reserved + * 26 5 extern level Reserved Reserved + * 27 3 extern level Reserved Reserved + * 28 4 extern edge + * 29 3 software Reserved Reserved + * 30 4 extern edge Reserved Reserved + * 31 5 extern level Reserved Reserved + ************************************************************************************************************* + */ + +//CPU0 Interrupt number reserved, not touch this. +#define ETS_WMAC_INUM 0 +#define ETS_BT_HOST_INUM 1 +#define ETS_FROM_CPU_INUM 2 +#define ETS_T0_WDT_INUM 3 +#define ETS_WBB_INUM 4 +#define ETS_TG0_T1_INUM 10 /**< use edge interrupt*/ + +//CPU0 Intrrupt number used in ROM, should be cancelled in SDK +#define ETS_SLC_INUM 1 +#define ETS_UART0_INUM 5 +#define ETS_UART1_INUM 5 +//Other interrupt number should be managed by the user + + +#endif /* _ESP32_SOC_H_ */ diff --git a/tools/sdk/include/esp32/soc/spi_reg.h b/tools/sdk/include/esp32/soc/spi_reg.h new file mode 100644 index 00000000..34f2f24e --- /dev/null +++ b/tools/sdk/include/esp32/soc/spi_reg.h @@ -0,0 +1,1717 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef __SPI_REG_H__ +#define __SPI_REG_H__ + + +#include "soc.h" +#define REG_SPI_BASE(i) (DR_REG_SPI1_BASE + (((i)>1) ? (((i)* 0x1000) + 0x20000) : (((~(i)) & 1)* 0x1000 ))) + +#define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0) +/* SPI_FLASH_READ : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Read flash enable. Read flash operation will be triggered when + the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ +#define SPI_FLASH_READ (BIT(31)) +#define SPI_FLASH_READ_M (BIT(31)) +#define SPI_FLASH_READ_V 0x1 +#define SPI_FLASH_READ_S 31 +/* SPI_FLASH_WREN : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Write flash enable. Write enable command will be sent when the + bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ +#define SPI_FLASH_WREN (BIT(30)) +#define SPI_FLASH_WREN_M (BIT(30)) +#define SPI_FLASH_WREN_V 0x1 +#define SPI_FLASH_WREN_S 30 +/* SPI_FLASH_WRDI : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Write flash disable. Write disable command will be sent when + the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ +#define SPI_FLASH_WRDI (BIT(29)) +#define SPI_FLASH_WRDI_M (BIT(29)) +#define SPI_FLASH_WRDI_V 0x1 +#define SPI_FLASH_WRDI_S 29 +/* SPI_FLASH_RDID : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Read JEDEC ID . Read ID command will be sent when the bit is + set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ +#define SPI_FLASH_RDID (BIT(28)) +#define SPI_FLASH_RDID_M (BIT(28)) +#define SPI_FLASH_RDID_V 0x1 +#define SPI_FLASH_RDID_S 28 +/* SPI_FLASH_RDSR : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Read status register-1. Read status operation will be triggered + when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_FLASH_RDSR (BIT(27)) +#define SPI_FLASH_RDSR_M (BIT(27)) +#define SPI_FLASH_RDSR_V 0x1 +#define SPI_FLASH_RDSR_S 27 +/* SPI_FLASH_WRSR : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: Write status register enable. Write status operation will + be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_FLASH_WRSR (BIT(26)) +#define SPI_FLASH_WRSR_M (BIT(26)) +#define SPI_FLASH_WRSR_V 0x1 +#define SPI_FLASH_WRSR_S 26 +/* SPI_FLASH_PP : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: Page program enable(1 byte ~256 bytes data to be programmed). + Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/ +#define SPI_FLASH_PP (BIT(25)) +#define SPI_FLASH_PP_M (BIT(25)) +#define SPI_FLASH_PP_V 0x1 +#define SPI_FLASH_PP_S 25 +/* SPI_FLASH_SE : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: Sector erase enable(4KB). Sector erase operation will be triggered + when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_FLASH_SE (BIT(24)) +#define SPI_FLASH_SE_M (BIT(24)) +#define SPI_FLASH_SE_V 0x1 +#define SPI_FLASH_SE_S 24 +/* SPI_FLASH_BE : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: Block erase enable(32KB) . Block erase operation will be triggered + when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_FLASH_BE (BIT(23)) +#define SPI_FLASH_BE_M (BIT(23)) +#define SPI_FLASH_BE_V 0x1 +#define SPI_FLASH_BE_S 23 +/* SPI_FLASH_CE : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Chip erase enable. Chip erase operation will be triggered when + the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_FLASH_CE (BIT(22)) +#define SPI_FLASH_CE_M (BIT(22)) +#define SPI_FLASH_CE_V 0x1 +#define SPI_FLASH_CE_S 22 +/* SPI_FLASH_DP : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Drive Flash into power down. An operation will be triggered + when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_FLASH_DP (BIT(21)) +#define SPI_FLASH_DP_M (BIT(21)) +#define SPI_FLASH_DP_V 0x1 +#define SPI_FLASH_DP_S 21 +/* SPI_FLASH_RES : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: This bit combined with reg_resandres bit releases Flash from + the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_FLASH_RES (BIT(20)) +#define SPI_FLASH_RES_M (BIT(20)) +#define SPI_FLASH_RES_V 0x1 +#define SPI_FLASH_RES_S 20 +/* SPI_FLASH_HPM : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: Drive Flash into high performance mode. The bit will be cleared + once the operation done.1: enable 0: disable.*/ +#define SPI_FLASH_HPM (BIT(19)) +#define SPI_FLASH_HPM_M (BIT(19)) +#define SPI_FLASH_HPM_V 0x1 +#define SPI_FLASH_HPM_S 19 +/* SPI_USR : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: User define command enable. An operation will be triggered when + the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_USR (BIT(18)) +#define SPI_USR_M (BIT(18)) +#define SPI_USR_V 0x1 +#define SPI_USR_S 18 +/* SPI_FLASH_PES : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: program erase suspend bit program erase suspend operation will + be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_FLASH_PES (BIT(17)) +#define SPI_FLASH_PES_M (BIT(17)) +#define SPI_FLASH_PES_V 0x1 +#define SPI_FLASH_PES_S 17 +/* SPI_FLASH_PER : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: program erase resume bit program erase suspend operation will + be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_FLASH_PER (BIT(16)) +#define SPI_FLASH_PER_M (BIT(16)) +#define SPI_FLASH_PER_V 0x1 +#define SPI_FLASH_PER_S 16 + +#define SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x4) +/* SPI_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: [31:8]:address to slave [7:0]:Reserved.*/ +#define SPI_USR_ADDR_VALUE 0xFFFFFFFF +#define SPI_USR_ADDR_VALUE_M ((SPI_USR_ADDR_VALUE_V)<<(SPI_USR_ADDR_VALUE_S)) +#define SPI_USR_ADDR_VALUE_V 0xFFFFFFFF +#define SPI_USR_ADDR_VALUE_S 0 + +#define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8) +/* SPI_WR_BIT_ORDER : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: In command address write-data (MOSI) phases 1: LSB firs 0: MSB first*/ +#define SPI_WR_BIT_ORDER (BIT(26)) +#define SPI_WR_BIT_ORDER_M (BIT(26)) +#define SPI_WR_BIT_ORDER_V 0x1 +#define SPI_WR_BIT_ORDER_S 26 +/* SPI_RD_BIT_ORDER : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: In read-data (MISO) phase 1: LSB first 0: MSB first*/ +#define SPI_RD_BIT_ORDER (BIT(25)) +#define SPI_RD_BIT_ORDER_M (BIT(25)) +#define SPI_RD_BIT_ORDER_V 0x1 +#define SPI_RD_BIT_ORDER_S 25 +/* SPI_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: In the read operations address phase and read-data phase apply + 4 signals. 1: enable 0: disable.*/ +#define SPI_FREAD_QIO (BIT(24)) +#define SPI_FREAD_QIO_M (BIT(24)) +#define SPI_FREAD_QIO_V 0x1 +#define SPI_FREAD_QIO_S 24 +/* SPI_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: In the read operations address phase and read-data phase apply + 2 signals. 1: enable 0: disable.*/ +#define SPI_FREAD_DIO (BIT(23)) +#define SPI_FREAD_DIO_M (BIT(23)) +#define SPI_FREAD_DIO_V 0x1 +#define SPI_FREAD_DIO_S 23 +/* SPI_WRSR_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: two bytes data will be written to status register when it is + set. 1: enable 0: disable.*/ +#define SPI_WRSR_2B (BIT(22)) +#define SPI_WRSR_2B_M (BIT(22)) +#define SPI_WRSR_2B_V 0x1 +#define SPI_WRSR_2B_S 22 +/* SPI_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */ +/*description: Write protect signal output when SPI is idle. 1: output high 0: output low.*/ +#define SPI_WP_REG (BIT(21)) +#define SPI_WP_REG_M (BIT(21)) +#define SPI_WP_REG_V 0x1 +#define SPI_WP_REG_S 21 +/* SPI_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/ +#define SPI_FREAD_QUAD (BIT(20)) +#define SPI_FREAD_QUAD_M (BIT(20)) +#define SPI_FREAD_QUAD_V 0x1 +#define SPI_FREAD_QUAD_S 20 +/* SPI_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */ +/*description: The Device ID is read out to SPI_RD_STATUS register, this bit + combine with spi_flash_res bit. 1: enable 0: disable.*/ +#define SPI_RESANDRES (BIT(15)) +#define SPI_RESANDRES_M (BIT(15)) +#define SPI_RESANDRES_V 0x1 +#define SPI_RESANDRES_S 15 +/* SPI_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: In the read operations read-data phase apply 2 signals. 1: enable 0: disable.*/ +#define SPI_FREAD_DUAL (BIT(14)) +#define SPI_FREAD_DUAL_M (BIT(14)) +#define SPI_FREAD_DUAL_V 0x1 +#define SPI_FREAD_DUAL_S 14 +/* SPI_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: This bit enable the bits: spi_fread_qio spi_fread_dio spi_fread_qout + and spi_fread_dout. 1: enable 0: disable.*/ +#define SPI_FASTRD_MODE (BIT(13)) +#define SPI_FASTRD_MODE_M (BIT(13)) +#define SPI_FASTRD_MODE_V 0x1 +#define SPI_FASTRD_MODE_S 13 +/* SPI_WAIT_FLASH_IDLE_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: wait flash idle when program flash or erase flash. 1: enable 0: disable.*/ +#define SPI_WAIT_FLASH_IDLE_EN (BIT(12)) +#define SPI_WAIT_FLASH_IDLE_EN_M (BIT(12)) +#define SPI_WAIT_FLASH_IDLE_EN_V 0x1 +#define SPI_WAIT_FLASH_IDLE_EN_S 12 +/* SPI_TX_CRC_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: For SPI1 enable crc32 when writing encrypted data to flash. + 1: enable 0:disable*/ +#define SPI_TX_CRC_EN (BIT(11)) +#define SPI_TX_CRC_EN_M (BIT(11)) +#define SPI_TX_CRC_EN_V 0x1 +#define SPI_TX_CRC_EN_S 11 +/* SPI_FCS_CRC_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: For SPI1 initialize crc32 module before writing encrypted data + to flash. Active low.*/ +#define SPI_FCS_CRC_EN (BIT(10)) +#define SPI_FCS_CRC_EN_M (BIT(10)) +#define SPI_FCS_CRC_EN_V 0x1 +#define SPI_FCS_CRC_EN_S 10 + +#define SPI_CTRL1_REG(i) (REG_SPI_BASE(i) + 0xC) +/* SPI_CS_HOLD_DELAY : R/W ;bitpos:[31:28] ;default: 4'h5 ; */ +/*description: SPI cs signal is delayed by spi clock cycles*/ +#define SPI_CS_HOLD_DELAY 0x0000000F +#define SPI_CS_HOLD_DELAY_M ((SPI_CS_HOLD_DELAY_V)<<(SPI_CS_HOLD_DELAY_S)) +#define SPI_CS_HOLD_DELAY_V 0xF +#define SPI_CS_HOLD_DELAY_S 28 +/* SPI_CS_HOLD_DELAY_RES : R/W ;bitpos:[27:16] ;default: 12'hfff ; */ +/*description: Delay cycles of resume Flash when resume Flash is enable by spi clock.*/ +#define SPI_CS_HOLD_DELAY_RES 0x00000FFF +#define SPI_CS_HOLD_DELAY_RES_M ((SPI_CS_HOLD_DELAY_RES_V)<<(SPI_CS_HOLD_DELAY_RES_S)) +#define SPI_CS_HOLD_DELAY_RES_V 0xFFF +#define SPI_CS_HOLD_DELAY_RES_S 16 + +#define SPI_RD_STATUS_REG(i) (REG_SPI_BASE(i) + 0x10) +/* SPI_STATUS_EXT : R/W ;bitpos:[31:24] ;default: 8'h00 ; */ +/*description: In the slave mode,it is the status for master to read out.*/ +#define SPI_STATUS_EXT 0x000000FF +#define SPI_STATUS_EXT_M ((SPI_STATUS_EXT_V)<<(SPI_STATUS_EXT_S)) +#define SPI_STATUS_EXT_V 0xFF +#define SPI_STATUS_EXT_S 24 +/* SPI_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */ +/*description: Mode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit.*/ +#define SPI_WB_MODE 0x000000FF +#define SPI_WB_MODE_M ((SPI_WB_MODE_V)<<(SPI_WB_MODE_S)) +#define SPI_WB_MODE_V 0xFF +#define SPI_WB_MODE_S 16 +/* SPI_STATUS : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: In the slave mode, it is the status for master to read out.*/ +#define SPI_STATUS 0x0000FFFF +#define SPI_STATUS_M ((SPI_STATUS_V)<<(SPI_STATUS_S)) +#define SPI_STATUS_V 0xFFFF +#define SPI_STATUS_S 0 + +#define SPI_CTRL2_REG(i) (REG_SPI_BASE(i) + 0x14) +/* SPI_CS_DELAY_NUM : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: spi_cs signal is delayed by system clock cycles*/ +#define SPI_CS_DELAY_NUM 0x0000000F +#define SPI_CS_DELAY_NUM_M ((SPI_CS_DELAY_NUM_V)<<(SPI_CS_DELAY_NUM_S)) +#define SPI_CS_DELAY_NUM_V 0xF +#define SPI_CS_DELAY_NUM_S 28 +/* SPI_CS_DELAY_MODE : R/W ;bitpos:[27:26] ;default: 2'h0 ; */ +/*description: spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge + or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ +#define SPI_CS_DELAY_MODE 0x00000003 +#define SPI_CS_DELAY_MODE_M ((SPI_CS_DELAY_MODE_V)<<(SPI_CS_DELAY_MODE_S)) +#define SPI_CS_DELAY_MODE_V 0x3 +#define SPI_CS_DELAY_MODE_S 26 +/* SPI_MOSI_DELAY_NUM : R/W ;bitpos:[25:23] ;default: 3'h0 ; */ +/*description: MOSI signals are delayed by system clock cycles*/ +#define SPI_MOSI_DELAY_NUM 0x00000007 +#define SPI_MOSI_DELAY_NUM_M ((SPI_MOSI_DELAY_NUM_V)<<(SPI_MOSI_DELAY_NUM_S)) +#define SPI_MOSI_DELAY_NUM_V 0x7 +#define SPI_MOSI_DELAY_NUM_S 23 +/* SPI_MOSI_DELAY_MODE : R/W ;bitpos:[22:21] ;default: 2'h0 ; */ +/*description: MOSI signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge + or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ +#define SPI_MOSI_DELAY_MODE 0x00000003 +#define SPI_MOSI_DELAY_MODE_M ((SPI_MOSI_DELAY_MODE_V)<<(SPI_MOSI_DELAY_MODE_S)) +#define SPI_MOSI_DELAY_MODE_V 0x3 +#define SPI_MOSI_DELAY_MODE_S 21 +/* SPI_MISO_DELAY_NUM : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ +/*description: MISO signals are delayed by system clock cycles*/ +#define SPI_MISO_DELAY_NUM 0x00000007 +#define SPI_MISO_DELAY_NUM_M ((SPI_MISO_DELAY_NUM_V)<<(SPI_MISO_DELAY_NUM_S)) +#define SPI_MISO_DELAY_NUM_V 0x7 +#define SPI_MISO_DELAY_NUM_S 18 +/* SPI_MISO_DELAY_MODE : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ +/*description: MISO signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge + or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ +#define SPI_MISO_DELAY_MODE 0x00000003 +#define SPI_MISO_DELAY_MODE_M ((SPI_MISO_DELAY_MODE_V)<<(SPI_MISO_DELAY_MODE_S)) +#define SPI_MISO_DELAY_MODE_V 0x3 +#define SPI_MISO_DELAY_MODE_S 16 +/* SPI_CK_OUT_HIGH_MODE : R/W ;bitpos:[15:12] ;default: 4'h0 ; */ +/*description: modify spi clock duty ratio when the value is lager than 8, + the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits.*/ +#define SPI_CK_OUT_HIGH_MODE 0x0000000F +#define SPI_CK_OUT_HIGH_MODE_M ((SPI_CK_OUT_HIGH_MODE_V)<<(SPI_CK_OUT_HIGH_MODE_S)) +#define SPI_CK_OUT_HIGH_MODE_V 0xF +#define SPI_CK_OUT_HIGH_MODE_S 12 +/* SPI_CK_OUT_LOW_MODE : R/W ;bitpos:[11:8] ;default: 4'h0 ; */ +/*description: modify spi clock duty ratio when the value is lager than 8, + the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits.*/ +#define SPI_CK_OUT_LOW_MODE 0x0000000F +#define SPI_CK_OUT_LOW_MODE_M ((SPI_CK_OUT_LOW_MODE_V)<<(SPI_CK_OUT_LOW_MODE_S)) +#define SPI_CK_OUT_LOW_MODE_V 0xF +#define SPI_CK_OUT_LOW_MODE_S 8 +/* SPI_HOLD_TIME : R/W ;bitpos:[7:4] ;default: 4'h1 ; */ +/*description: delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit.*/ +#define SPI_HOLD_TIME 0x0000000F +#define SPI_HOLD_TIME_M ((SPI_HOLD_TIME_V)<<(SPI_HOLD_TIME_S)) +#define SPI_HOLD_TIME_V 0xF +#define SPI_HOLD_TIME_S 4 +/* SPI_SETUP_TIME : R/W ;bitpos:[3:0] ;default: 4'h1 ; */ +/*description: (cycles-1) of ¡°prepare¡± phase by spi clock, this bits combined + with spi_cs_setup bit.*/ +#define SPI_SETUP_TIME 0x0000000F +#define SPI_SETUP_TIME_M ((SPI_SETUP_TIME_V)<<(SPI_SETUP_TIME_S)) +#define SPI_SETUP_TIME_V 0xF +#define SPI_SETUP_TIME_S 0 + +#define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0x18) +/* SPI_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: In the master mode 1: spi_clk is eqaul to system 0: spi_clk is + divided from system clock.*/ +#define SPI_CLK_EQU_SYSCLK (BIT(31)) +#define SPI_CLK_EQU_SYSCLK_M (BIT(31)) +#define SPI_CLK_EQU_SYSCLK_V 0x1 +#define SPI_CLK_EQU_SYSCLK_S 31 +/* SPI_CLKDIV_PRE : R/W ;bitpos:[30:18] ;default: 13'b0 ; */ +/*description: In the master mode it is pre-divider of spi_clk.*/ +#define SPI_CLKDIV_PRE 0x00001FFF +#define SPI_CLKDIV_PRE_M ((SPI_CLKDIV_PRE_V)<<(SPI_CLKDIV_PRE_S)) +#define SPI_CLKDIV_PRE_V 0x1FFF +#define SPI_CLKDIV_PRE_S 18 +/* SPI_CLKCNT_N : R/W ;bitpos:[17:12] ;default: 6'h3 ; */ +/*description: In the master mode it is the divider of spi_clk. So spi_clk frequency + is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)*/ +#define SPI_CLKCNT_N 0x0000003F +#define SPI_CLKCNT_N_M ((SPI_CLKCNT_N_V)<<(SPI_CLKCNT_N_S)) +#define SPI_CLKCNT_N_V 0x3F +#define SPI_CLKCNT_N_S 12 +/* SPI_CLKCNT_H : R/W ;bitpos:[11:6] ;default: 6'h1 ; */ +/*description: In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In + the slave mode it must be 0.*/ +#define SPI_CLKCNT_H 0x0000003F +#define SPI_CLKCNT_H_M ((SPI_CLKCNT_H_V)<<(SPI_CLKCNT_H_S)) +#define SPI_CLKCNT_H_V 0x3F +#define SPI_CLKCNT_H_S 6 +/* SPI_CLKCNT_L : R/W ;bitpos:[5:0] ;default: 6'h3 ; */ +/*description: In the master mode it must be equal to spi_clkcnt_N. In the slave + mode it must be 0.*/ +#define SPI_CLKCNT_L 0x0000003F +#define SPI_CLKCNT_L_M ((SPI_CLKCNT_L_V)<<(SPI_CLKCNT_L_S)) +#define SPI_CLKCNT_L_V 0x3F +#define SPI_CLKCNT_L_S 0 + +#define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x1C) +/* SPI_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: This bit enable the command phase of an operation.*/ +#define SPI_USR_COMMAND (BIT(31)) +#define SPI_USR_COMMAND_M (BIT(31)) +#define SPI_USR_COMMAND_V 0x1 +#define SPI_USR_COMMAND_S 31 +/* SPI_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: This bit enable the address phase of an operation.*/ +#define SPI_USR_ADDR (BIT(30)) +#define SPI_USR_ADDR_M (BIT(30)) +#define SPI_USR_ADDR_V 0x1 +#define SPI_USR_ADDR_S 30 +/* SPI_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: This bit enable the dummy phase of an operation.*/ +#define SPI_USR_DUMMY (BIT(29)) +#define SPI_USR_DUMMY_M (BIT(29)) +#define SPI_USR_DUMMY_V 0x1 +#define SPI_USR_DUMMY_S 29 +/* SPI_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: This bit enable the read-data phase of an operation.*/ +#define SPI_USR_MISO (BIT(28)) +#define SPI_USR_MISO_M (BIT(28)) +#define SPI_USR_MISO_V 0x1 +#define SPI_USR_MISO_S 28 +/* SPI_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: This bit enable the write-data phase of an operation.*/ +#define SPI_USR_MOSI (BIT(27)) +#define SPI_USR_MOSI_M (BIT(27)) +#define SPI_USR_MOSI_V 0x1 +#define SPI_USR_MOSI_S 27 +/* SPI_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: spi clock is disable in dummy phase when the bit is enable.*/ +#define SPI_USR_DUMMY_IDLE (BIT(26)) +#define SPI_USR_DUMMY_IDLE_M (BIT(26)) +#define SPI_USR_DUMMY_IDLE_V 0x1 +#define SPI_USR_DUMMY_IDLE_S 26 +/* SPI_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: write-data phase only access to high-part of the buffer spi_w8~spi_w15. + 1: enable 0: disable.*/ +#define SPI_USR_MOSI_HIGHPART (BIT(25)) +#define SPI_USR_MOSI_HIGHPART_M (BIT(25)) +#define SPI_USR_MOSI_HIGHPART_V 0x1 +#define SPI_USR_MOSI_HIGHPART_S 25 +/* SPI_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: read-data phase only access to high-part of the buffer spi_w8~spi_w15. + 1: enable 0: disable.*/ +#define SPI_USR_MISO_HIGHPART (BIT(24)) +#define SPI_USR_MISO_HIGHPART_M (BIT(24)) +#define SPI_USR_MISO_HIGHPART_V 0x1 +#define SPI_USR_MISO_HIGHPART_S 24 +/* SPI_USR_PREP_HOLD : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: spi is hold at prepare state the bit combined with spi_usr_hold_pol bit.*/ +#define SPI_USR_PREP_HOLD (BIT(23)) +#define SPI_USR_PREP_HOLD_M (BIT(23)) +#define SPI_USR_PREP_HOLD_V 0x1 +#define SPI_USR_PREP_HOLD_S 23 +/* SPI_USR_CMD_HOLD : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: spi is hold at command state the bit combined with spi_usr_hold_pol bit.*/ +#define SPI_USR_CMD_HOLD (BIT(22)) +#define SPI_USR_CMD_HOLD_M (BIT(22)) +#define SPI_USR_CMD_HOLD_V 0x1 +#define SPI_USR_CMD_HOLD_S 22 +/* SPI_USR_ADDR_HOLD : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: spi is hold at address state the bit combined with spi_usr_hold_pol bit.*/ +#define SPI_USR_ADDR_HOLD (BIT(21)) +#define SPI_USR_ADDR_HOLD_M (BIT(21)) +#define SPI_USR_ADDR_HOLD_V 0x1 +#define SPI_USR_ADDR_HOLD_S 21 +/* SPI_USR_DUMMY_HOLD : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: spi is hold at dummy state the bit combined with spi_usr_hold_pol bit.*/ +#define SPI_USR_DUMMY_HOLD (BIT(20)) +#define SPI_USR_DUMMY_HOLD_M (BIT(20)) +#define SPI_USR_DUMMY_HOLD_V 0x1 +#define SPI_USR_DUMMY_HOLD_S 20 +/* SPI_USR_DIN_HOLD : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: spi is hold at data in state the bit combined with spi_usr_hold_pol bit.*/ +#define SPI_USR_DIN_HOLD (BIT(19)) +#define SPI_USR_DIN_HOLD_M (BIT(19)) +#define SPI_USR_DIN_HOLD_V 0x1 +#define SPI_USR_DIN_HOLD_S 19 +/* SPI_USR_DOUT_HOLD : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: spi is hold at data out state the bit combined with spi_usr_hold_pol bit.*/ +#define SPI_USR_DOUT_HOLD (BIT(18)) +#define SPI_USR_DOUT_HOLD_M (BIT(18)) +#define SPI_USR_DOUT_HOLD_V 0x1 +#define SPI_USR_DOUT_HOLD_S 18 +/* SPI_USR_HOLD_POL : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: It is combined with hold bits to set the polarity of spi hold + line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low*/ +#define SPI_USR_HOLD_POL (BIT(17)) +#define SPI_USR_HOLD_POL_M (BIT(17)) +#define SPI_USR_HOLD_POL_V 0x1 +#define SPI_USR_HOLD_POL_S 17 +/* SPI_SIO : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: Set the bit to enable 3-line half duplex communication mosi + and miso signals share the same pin. 1: enable 0: disable.*/ +#define SPI_SIO (BIT(16)) +#define SPI_SIO_M (BIT(16)) +#define SPI_SIO_V 0x1 +#define SPI_SIO_S 16 +/* SPI_FWRITE_QIO : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: In the write operations address phase and read-data phase apply 4 signals.*/ +#define SPI_FWRITE_QIO (BIT(15)) +#define SPI_FWRITE_QIO_M (BIT(15)) +#define SPI_FWRITE_QIO_V 0x1 +#define SPI_FWRITE_QIO_S 15 +/* SPI_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: In the write operations address phase and read-data phase apply 2 signals.*/ +#define SPI_FWRITE_DIO (BIT(14)) +#define SPI_FWRITE_DIO_M (BIT(14)) +#define SPI_FWRITE_DIO_V 0x1 +#define SPI_FWRITE_DIO_S 14 +/* SPI_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: In the write operations read-data phase apply 4 signals*/ +#define SPI_FWRITE_QUAD (BIT(13)) +#define SPI_FWRITE_QUAD_M (BIT(13)) +#define SPI_FWRITE_QUAD_V 0x1 +#define SPI_FWRITE_QUAD_S 13 +/* SPI_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: In the write operations read-data phase apply 2 signals*/ +#define SPI_FWRITE_DUAL (BIT(12)) +#define SPI_FWRITE_DUAL_M (BIT(12)) +#define SPI_FWRITE_DUAL_V 0x1 +#define SPI_FWRITE_DUAL_S 12 +/* SPI_WR_BYTE_ORDER : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: In command address write-data (MOSI) phases 1: big-endian 0: litte_endian*/ +#define SPI_WR_BYTE_ORDER (BIT(11)) +#define SPI_WR_BYTE_ORDER_M (BIT(11)) +#define SPI_WR_BYTE_ORDER_V 0x1 +#define SPI_WR_BYTE_ORDER_S 11 +/* SPI_RD_BYTE_ORDER : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: In read-data (MISO) phase 1: big-endian 0: little_endian*/ +#define SPI_RD_BYTE_ORDER (BIT(10)) +#define SPI_RD_BYTE_ORDER_M (BIT(10)) +#define SPI_RD_BYTE_ORDER_V 0x1 +#define SPI_RD_BYTE_ORDER_S 10 +/* SPI_CK_OUT_EDGE : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode.*/ +#define SPI_CK_OUT_EDGE (BIT(7)) +#define SPI_CK_OUT_EDGE_M (BIT(7)) +#define SPI_CK_OUT_EDGE_V 0x1 +#define SPI_CK_OUT_EDGE_S 7 +/* SPI_CK_I_EDGE : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: In the slave mode the bit is same as spi_ck_out_edge in master + mode. It is combined with spi_miso_delay_mode bits.*/ +#define SPI_CK_I_EDGE (BIT(6)) +#define SPI_CK_I_EDGE_M (BIT(6)) +#define SPI_CK_I_EDGE_V 0x1 +#define SPI_CK_I_EDGE_S 6 +/* SPI_CS_SETUP : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: spi cs is enable when spi is in ¡°prepare¡± phase. 1: enable 0: disable.*/ +#define SPI_CS_SETUP (BIT(5)) +#define SPI_CS_SETUP_M (BIT(5)) +#define SPI_CS_SETUP_V 0x1 +#define SPI_CS_SETUP_S 5 +/* SPI_CS_HOLD : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: spi cs keep low when spi is in ¡°done¡± phase. 1: enable 0: disable.*/ +#define SPI_CS_HOLD (BIT(4)) +#define SPI_CS_HOLD_M (BIT(4)) +#define SPI_CS_HOLD_V 0x1 +#define SPI_CS_HOLD_S 4 +/* SPI_DOUTDIN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set the bit to enable full duplex communication. 1: enable 0: disable.*/ +#define SPI_DOUTDIN (BIT(0)) +#define SPI_DOUTDIN_M (BIT(0)) +#define SPI_DOUTDIN_V 0x1 +#define SPI_DOUTDIN_S 0 + +#define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x20) +/* SPI_USR_ADDR_BITLEN : RO ;bitpos:[31:26] ;default: 6'd23 ; */ +/*description: The length in bits of address phase. The register value shall be (bit_num-1).*/ +#define SPI_USR_ADDR_BITLEN 0x0000003F +#define SPI_USR_ADDR_BITLEN_M ((SPI_USR_ADDR_BITLEN_V)<<(SPI_USR_ADDR_BITLEN_S)) +#define SPI_USR_ADDR_BITLEN_V 0x3F +#define SPI_USR_ADDR_BITLEN_S 26 +/* SPI_USR_DUMMY_CYCLELEN : R/W ;bitpos:[7:0] ;default: 8'd7 ; */ +/*description: The length in spi_clk cycles of dummy phase. The register value + shall be (cycle_num-1).*/ +#define SPI_USR_DUMMY_CYCLELEN 0x000000FF +#define SPI_USR_DUMMY_CYCLELEN_M ((SPI_USR_DUMMY_CYCLELEN_V)<<(SPI_USR_DUMMY_CYCLELEN_S)) +#define SPI_USR_DUMMY_CYCLELEN_V 0xFF +#define SPI_USR_DUMMY_CYCLELEN_S 0 + +#define SPI_USER2_REG(i) (REG_SPI_BASE(i) + 0x24) +/* SPI_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */ +/*description: The length in bits of command phase. The register value shall be (bit_num-1)*/ +#define SPI_USR_COMMAND_BITLEN 0x0000000F +#define SPI_USR_COMMAND_BITLEN_M ((SPI_USR_COMMAND_BITLEN_V)<<(SPI_USR_COMMAND_BITLEN_S)) +#define SPI_USR_COMMAND_BITLEN_V 0xF +#define SPI_USR_COMMAND_BITLEN_S 28 +/* SPI_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: The value of command.*/ +#define SPI_USR_COMMAND_VALUE 0x0000FFFF +#define SPI_USR_COMMAND_VALUE_M ((SPI_USR_COMMAND_VALUE_V)<<(SPI_USR_COMMAND_VALUE_S)) +#define SPI_USR_COMMAND_VALUE_V 0xFFFF +#define SPI_USR_COMMAND_VALUE_S 0 + +#define SPI_MOSI_DLEN_REG(i) (REG_SPI_BASE(i) + 0x28) +/* SPI_USR_MOSI_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: The length in bits of write-data. The register value shall be (bit_num-1).*/ +#define SPI_USR_MOSI_DBITLEN 0x00FFFFFF +#define SPI_USR_MOSI_DBITLEN_M ((SPI_USR_MOSI_DBITLEN_V)<<(SPI_USR_MOSI_DBITLEN_S)) +#define SPI_USR_MOSI_DBITLEN_V 0xFFFFFF +#define SPI_USR_MOSI_DBITLEN_S 0 + +#define SPI_MISO_DLEN_REG(i) (REG_SPI_BASE(i) + 0x2C) +/* SPI_USR_MISO_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: The length in bits of read-data. The register value shall be (bit_num-1).*/ +#define SPI_USR_MISO_DBITLEN 0x00FFFFFF +#define SPI_USR_MISO_DBITLEN_M ((SPI_USR_MISO_DBITLEN_V)<<(SPI_USR_MISO_DBITLEN_S)) +#define SPI_USR_MISO_DBITLEN_V 0xFFFFFF +#define SPI_USR_MISO_DBITLEN_S 0 + +#define SPI_SLV_WR_STATUS_REG(i) (REG_SPI_BASE(i) + 0x30) +/* SPI_SLV_WR_ST : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: In the slave mode this register are the status register for the + master to write into. In the master mode this register are the higher 32bits in the 64 bits address condition.*/ +#define SPI_SLV_WR_ST 0xFFFFFFFF +#define SPI_SLV_WR_ST_M ((SPI_SLV_WR_ST_V)<<(SPI_SLV_WR_ST_S)) +#define SPI_SLV_WR_ST_V 0xFFFFFFFF +#define SPI_SLV_WR_ST_S 0 + +#define SPI_PIN_REG(i) (REG_SPI_BASE(i) + 0x34) +/* SPI_CS_KEEP_ACTIVE : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: spi cs line keep low when the bit is set.*/ +#define SPI_CS_KEEP_ACTIVE (BIT(30)) +#define SPI_CS_KEEP_ACTIVE_M (BIT(30)) +#define SPI_CS_KEEP_ACTIVE_V 0x1 +#define SPI_CS_KEEP_ACTIVE_S 30 +/* SPI_CK_IDLE_EDGE : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: 1: spi clk line is high when idle 0: spi clk line is low when idle*/ +#define SPI_CK_IDLE_EDGE (BIT(29)) +#define SPI_CK_IDLE_EDGE_M (BIT(29)) +#define SPI_CK_IDLE_EDGE_V 0x1 +#define SPI_CK_IDLE_EDGE_S 29 +/* SPI_MASTER_CK_SEL : R/W ;bitpos:[15:11] ;default: 5'b0 ; */ +/*description: In the master mode spi cs line is enable as spi clk it is combined + with spi_cs0_dis spi_cs1_dis spi_cs2_dis.*/ +#define SPI_MASTER_CK_SEL 0x0000001F +#define SPI_MASTER_CK_SEL_M ((SPI_MASTER_CK_SEL_V)<<(SPI_MASTER_CK_SEL_S)) +#define SPI_MASTER_CK_SEL_V 0x1F +#define SPI_MASTER_CK_SEL_S 11 +/* SPI_MASTER_CS_POL : R/W ;bitpos:[10:6] ;default: 5'b0 ; */ +/*description: In the master mode the bits are the polarity of spi cs line + the value is equivalent to spi_cs ^ spi_master_cs_pol.*/ +#define SPI_MASTER_CS_POL 0x0000001F +#define SPI_MASTER_CS_POL_M ((SPI_MASTER_CS_POL_V)<<(SPI_MASTER_CS_POL_S)) +#define SPI_MASTER_CS_POL_V 0x1F +#define SPI_MASTER_CS_POL_S 6 +/* SPI_CK_DIS : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: 1: spi clk out disable 0: spi clk out enable*/ +#define SPI_CK_DIS (BIT(5)) +#define SPI_CK_DIS_M (BIT(5)) +#define SPI_CK_DIS_V 0x1 +#define SPI_CK_DIS_S 5 +/* SPI_CS2_DIS : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin*/ +#define SPI_CS2_DIS (BIT(2)) +#define SPI_CS2_DIS_M (BIT(2)) +#define SPI_CS2_DIS_V 0x1 +#define SPI_CS2_DIS_S 2 +/* SPI_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin*/ +#define SPI_CS1_DIS (BIT(1)) +#define SPI_CS1_DIS_M (BIT(1)) +#define SPI_CS1_DIS_V 0x1 +#define SPI_CS1_DIS_S 1 +/* SPI_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin*/ +#define SPI_CS0_DIS (BIT(0)) +#define SPI_CS0_DIS_M (BIT(0)) +#define SPI_CS0_DIS_V 0x1 +#define SPI_CS0_DIS_S 0 + +#define SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0x38) +/* SPI_SYNC_RESET : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Software reset enable, reset the spi clock line cs line and data lines.*/ +#define SPI_SYNC_RESET (BIT(31)) +#define SPI_SYNC_RESET_M (BIT(31)) +#define SPI_SYNC_RESET_V 0x1 +#define SPI_SYNC_RESET_S 31 +/* SPI_SLAVE_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: 1: slave mode 0: master mode.*/ +#define SPI_SLAVE_MODE (BIT(30)) +#define SPI_SLAVE_MODE_M (BIT(30)) +#define SPI_SLAVE_MODE_V 0x1 +#define SPI_SLAVE_MODE_S 30 +/* SPI_SLV_WR_RD_BUF_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: write and read buffer enable in the slave mode*/ +#define SPI_SLV_WR_RD_BUF_EN (BIT(29)) +#define SPI_SLV_WR_RD_BUF_EN_M (BIT(29)) +#define SPI_SLV_WR_RD_BUF_EN_V 0x1 +#define SPI_SLV_WR_RD_BUF_EN_S 29 +/* SPI_SLV_WR_RD_STA_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: write and read status enable in the slave mode*/ +#define SPI_SLV_WR_RD_STA_EN (BIT(28)) +#define SPI_SLV_WR_RD_STA_EN_M (BIT(28)) +#define SPI_SLV_WR_RD_STA_EN_V 0x1 +#define SPI_SLV_WR_RD_STA_EN_S 28 +/* SPI_SLV_CMD_DEFINE : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: 1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode + commands are fixed as: 1: write-status 2: write-buffer and 3: read-buffer.*/ +#define SPI_SLV_CMD_DEFINE (BIT(27)) +#define SPI_SLV_CMD_DEFINE_M (BIT(27)) +#define SPI_SLV_CMD_DEFINE_V 0x1 +#define SPI_SLV_CMD_DEFINE_S 27 +/* SPI_TRANS_CNT : RO ;bitpos:[26:23] ;default: 4'b0 ; */ +/*description: The operations counter in both the master mode and the slave + mode. 4: read-status*/ +#define SPI_TRANS_CNT 0x0000000F +#define SPI_TRANS_CNT_M ((SPI_TRANS_CNT_V)<<(SPI_TRANS_CNT_S)) +#define SPI_TRANS_CNT_V 0xF +#define SPI_TRANS_CNT_S 23 +/* SPI_SLV_LAST_STATE : RO ;bitpos:[22:20] ;default: 3'b0 ; */ +/*description: In the slave mode it is the state of spi state machine.*/ +#define SPI_SLV_LAST_STATE 0x00000007 +#define SPI_SLV_LAST_STATE_M ((SPI_SLV_LAST_STATE_V)<<(SPI_SLV_LAST_STATE_S)) +#define SPI_SLV_LAST_STATE_V 0x7 +#define SPI_SLV_LAST_STATE_S 20 +/* SPI_SLV_LAST_COMMAND : RO ;bitpos:[19:17] ;default: 3'b0 ; */ +/*description: In the slave mode it is the value of command.*/ +#define SPI_SLV_LAST_COMMAND 0x00000007 +#define SPI_SLV_LAST_COMMAND_M ((SPI_SLV_LAST_COMMAND_V)<<(SPI_SLV_LAST_COMMAND_S)) +#define SPI_SLV_LAST_COMMAND_V 0x7 +#define SPI_SLV_LAST_COMMAND_S 17 +/* SPI_CS_I_MODE : R/W ;bitpos:[11:10] ;default: 2'b0 ; */ +/*description: In the slave mode this bits used to synchronize the input spi + cs signal and eliminate spi cs jitter.*/ +#define SPI_CS_I_MODE 0x00000003 +#define SPI_CS_I_MODE_M ((SPI_CS_I_MODE_V)<<(SPI_CS_I_MODE_S)) +#define SPI_CS_I_MODE_V 0x3 +#define SPI_CS_I_MODE_S 10 +/* SPI_INT_EN : R/W ;bitpos:[9:5] ;default: 5'b1_0000 ; */ +/*description: Interrupt enable bits for the below 5 sources*/ +#define SPI_INT_EN 0x0000001F +#define SPI_INT_EN_M ((SPI_INT_EN_V)<<(SPI_INT_EN_S)) +#define SPI_INT_EN_V 0x1F +#define SPI_INT_EN_S 5 +/* SPI_TRANS_DONE : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for the completion of any operation in + both the master mode and the slave mode.*/ +#define SPI_TRANS_DONE (BIT(4)) +#define SPI_TRANS_DONE_M (BIT(4)) +#define SPI_TRANS_DONE_V 0x1 +#define SPI_TRANS_DONE_S 4 +/* SPI_SLV_WR_STA_DONE : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for the completion of write-status operation + in the slave mode.*/ +#define SPI_SLV_WR_STA_DONE (BIT(3)) +#define SPI_SLV_WR_STA_DONE_M (BIT(3)) +#define SPI_SLV_WR_STA_DONE_V 0x1 +#define SPI_SLV_WR_STA_DONE_S 3 +/* SPI_SLV_RD_STA_DONE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for the completion of read-status operation + in the slave mode.*/ +#define SPI_SLV_RD_STA_DONE (BIT(2)) +#define SPI_SLV_RD_STA_DONE_M (BIT(2)) +#define SPI_SLV_RD_STA_DONE_V 0x1 +#define SPI_SLV_RD_STA_DONE_S 2 +/* SPI_SLV_WR_BUF_DONE : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for the completion of write-buffer operation + in the slave mode.*/ +#define SPI_SLV_WR_BUF_DONE (BIT(1)) +#define SPI_SLV_WR_BUF_DONE_M (BIT(1)) +#define SPI_SLV_WR_BUF_DONE_V 0x1 +#define SPI_SLV_WR_BUF_DONE_S 1 +/* SPI_SLV_RD_BUF_DONE : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for the completion of read-buffer operation + in the slave mode.*/ +#define SPI_SLV_RD_BUF_DONE (BIT(0)) +#define SPI_SLV_RD_BUF_DONE_M (BIT(0)) +#define SPI_SLV_RD_BUF_DONE_V 0x1 +#define SPI_SLV_RD_BUF_DONE_S 0 + +#define SPI_SLAVE1_REG(i) (REG_SPI_BASE(i) + 0x3C) +/* SPI_SLV_STATUS_BITLEN : R/W ;bitpos:[31:27] ;default: 5'b0 ; */ +/*description: In the slave mode it is the length of status bit.*/ +#define SPI_SLV_STATUS_BITLEN 0x0000001F +#define SPI_SLV_STATUS_BITLEN_M ((SPI_SLV_STATUS_BITLEN_V)<<(SPI_SLV_STATUS_BITLEN_S)) +#define SPI_SLV_STATUS_BITLEN_V 0x1F +#define SPI_SLV_STATUS_BITLEN_S 27 +/* SPI_SLV_STATUS_FAST_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: In the slave mode enable fast read status.*/ +#define SPI_SLV_STATUS_FAST_EN (BIT(26)) +#define SPI_SLV_STATUS_FAST_EN_M (BIT(26)) +#define SPI_SLV_STATUS_FAST_EN_V 0x1 +#define SPI_SLV_STATUS_FAST_EN_S 26 +/* SPI_SLV_STATUS_READBACK : R/W ;bitpos:[25] ;default: 1'b1 ; */ +/*description: In the slave mode 1:read register of SPI_SLV_WR_STATUS 0: read + register of SPI_RD_STATUS.*/ +#define SPI_SLV_STATUS_READBACK (BIT(25)) +#define SPI_SLV_STATUS_READBACK_M (BIT(25)) +#define SPI_SLV_STATUS_READBACK_V 0x1 +#define SPI_SLV_STATUS_READBACK_S 25 +/* SPI_SLV_RD_ADDR_BITLEN : R/W ;bitpos:[15:10] ;default: 6'h0 ; */ +/*description: In the slave mode it is the address length in bits for read-buffer + operation. The register value shall be (bit_num-1).*/ +#define SPI_SLV_RD_ADDR_BITLEN 0x0000003F +#define SPI_SLV_RD_ADDR_BITLEN_M ((SPI_SLV_RD_ADDR_BITLEN_V)<<(SPI_SLV_RD_ADDR_BITLEN_S)) +#define SPI_SLV_RD_ADDR_BITLEN_V 0x3F +#define SPI_SLV_RD_ADDR_BITLEN_S 10 +/* SPI_SLV_WR_ADDR_BITLEN : R/W ;bitpos:[9:4] ;default: 6'h0 ; */ +/*description: In the slave mode it is the address length in bits for write-buffer + operation. The register value shall be (bit_num-1).*/ +#define SPI_SLV_WR_ADDR_BITLEN 0x0000003F +#define SPI_SLV_WR_ADDR_BITLEN_M ((SPI_SLV_WR_ADDR_BITLEN_V)<<(SPI_SLV_WR_ADDR_BITLEN_S)) +#define SPI_SLV_WR_ADDR_BITLEN_V 0x3F +#define SPI_SLV_WR_ADDR_BITLEN_S 4 +/* SPI_SLV_WRSTA_DUMMY_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: In the slave mode it is the enable bit of dummy phase for write-status + operations.*/ +#define SPI_SLV_WRSTA_DUMMY_EN (BIT(3)) +#define SPI_SLV_WRSTA_DUMMY_EN_M (BIT(3)) +#define SPI_SLV_WRSTA_DUMMY_EN_V 0x1 +#define SPI_SLV_WRSTA_DUMMY_EN_S 3 +/* SPI_SLV_RDSTA_DUMMY_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: In the slave mode it is the enable bit of dummy phase for read-status + operations.*/ +#define SPI_SLV_RDSTA_DUMMY_EN (BIT(2)) +#define SPI_SLV_RDSTA_DUMMY_EN_M (BIT(2)) +#define SPI_SLV_RDSTA_DUMMY_EN_V 0x1 +#define SPI_SLV_RDSTA_DUMMY_EN_S 2 +/* SPI_SLV_WRBUF_DUMMY_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: In the slave mode it is the enable bit of dummy phase for write-buffer + operations.*/ +#define SPI_SLV_WRBUF_DUMMY_EN (BIT(1)) +#define SPI_SLV_WRBUF_DUMMY_EN_M (BIT(1)) +#define SPI_SLV_WRBUF_DUMMY_EN_V 0x1 +#define SPI_SLV_WRBUF_DUMMY_EN_S 1 +/* SPI_SLV_RDBUF_DUMMY_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: In the slave mode it is the enable bit of dummy phase for read-buffer + operations.*/ +#define SPI_SLV_RDBUF_DUMMY_EN (BIT(0)) +#define SPI_SLV_RDBUF_DUMMY_EN_M (BIT(0)) +#define SPI_SLV_RDBUF_DUMMY_EN_V 0x1 +#define SPI_SLV_RDBUF_DUMMY_EN_S 0 + +#define SPI_SLAVE2_REG(i) (REG_SPI_BASE(i) + 0x40) +/* SPI_SLV_WRBUF_DUMMY_CYCLELEN : R/W ;bitpos:[31:24] ;default: 8'b0 ; */ +/*description: In the slave mode it is the length in spi_clk cycles of dummy + phase for write-buffer operations. The register value shall be (cycle_num-1).*/ +#define SPI_SLV_WRBUF_DUMMY_CYCLELEN 0x000000FF +#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_M ((SPI_SLV_WRBUF_DUMMY_CYCLELEN_V)<<(SPI_SLV_WRBUF_DUMMY_CYCLELEN_S)) +#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_V 0xFF +#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_S 24 +/* SPI_SLV_RDBUF_DUMMY_CYCLELEN : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: In the slave mode it is the length in spi_clk cycles of dummy + phase for read-buffer operations. The register value shall be (cycle_num-1).*/ +#define SPI_SLV_RDBUF_DUMMY_CYCLELEN 0x000000FF +#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_M ((SPI_SLV_RDBUF_DUMMY_CYCLELEN_V)<<(SPI_SLV_RDBUF_DUMMY_CYCLELEN_S)) +#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_V 0xFF +#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_S 16 +/* SPI_SLV_WRSTA_DUMMY_CYCLELEN : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: In the slave mode it is the length in spi_clk cycles of dummy + phase for write-status operations. The register value shall be (cycle_num-1).*/ +#define SPI_SLV_WRSTA_DUMMY_CYCLELEN 0x000000FF +#define SPI_SLV_WRSTA_DUMMY_CYCLELEN_M ((SPI_SLV_WRSTA_DUMMY_CYCLELEN_V)<<(SPI_SLV_WRSTA_DUMMY_CYCLELEN_S)) +#define SPI_SLV_WRSTA_DUMMY_CYCLELEN_V 0xFF +#define SPI_SLV_WRSTA_DUMMY_CYCLELEN_S 8 +/* SPI_SLV_RDSTA_DUMMY_CYCLELEN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: In the slave mode it is the length in spi_clk cycles of dummy + phase for read-status operations. The register value shall be (cycle_num-1).*/ +#define SPI_SLV_RDSTA_DUMMY_CYCLELEN 0x000000FF +#define SPI_SLV_RDSTA_DUMMY_CYCLELEN_M ((SPI_SLV_RDSTA_DUMMY_CYCLELEN_V)<<(SPI_SLV_RDSTA_DUMMY_CYCLELEN_S)) +#define SPI_SLV_RDSTA_DUMMY_CYCLELEN_V 0xFF +#define SPI_SLV_RDSTA_DUMMY_CYCLELEN_S 0 + +#define SPI_SLAVE3_REG(i) (REG_SPI_BASE(i) + 0x44) +/* SPI_SLV_WRSTA_CMD_VALUE : R/W ;bitpos:[31:24] ;default: 8'b0 ; */ +/*description: In the slave mode it is the value of write-status command.*/ +#define SPI_SLV_WRSTA_CMD_VALUE 0x000000FF +#define SPI_SLV_WRSTA_CMD_VALUE_M ((SPI_SLV_WRSTA_CMD_VALUE_V)<<(SPI_SLV_WRSTA_CMD_VALUE_S)) +#define SPI_SLV_WRSTA_CMD_VALUE_V 0xFF +#define SPI_SLV_WRSTA_CMD_VALUE_S 24 +/* SPI_SLV_RDSTA_CMD_VALUE : R/W ;bitpos:[23:16] ;default: 8'b0 ; */ +/*description: In the slave mode it is the value of read-status command.*/ +#define SPI_SLV_RDSTA_CMD_VALUE 0x000000FF +#define SPI_SLV_RDSTA_CMD_VALUE_M ((SPI_SLV_RDSTA_CMD_VALUE_V)<<(SPI_SLV_RDSTA_CMD_VALUE_S)) +#define SPI_SLV_RDSTA_CMD_VALUE_V 0xFF +#define SPI_SLV_RDSTA_CMD_VALUE_S 16 +/* SPI_SLV_WRBUF_CMD_VALUE : R/W ;bitpos:[15:8] ;default: 8'b0 ; */ +/*description: In the slave mode it is the value of write-buffer command.*/ +#define SPI_SLV_WRBUF_CMD_VALUE 0x000000FF +#define SPI_SLV_WRBUF_CMD_VALUE_M ((SPI_SLV_WRBUF_CMD_VALUE_V)<<(SPI_SLV_WRBUF_CMD_VALUE_S)) +#define SPI_SLV_WRBUF_CMD_VALUE_V 0xFF +#define SPI_SLV_WRBUF_CMD_VALUE_S 8 +/* SPI_SLV_RDBUF_CMD_VALUE : R/W ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: In the slave mode it is the value of read-buffer command.*/ +#define SPI_SLV_RDBUF_CMD_VALUE 0x000000FF +#define SPI_SLV_RDBUF_CMD_VALUE_M ((SPI_SLV_RDBUF_CMD_VALUE_V)<<(SPI_SLV_RDBUF_CMD_VALUE_S)) +#define SPI_SLV_RDBUF_CMD_VALUE_V 0xFF +#define SPI_SLV_RDBUF_CMD_VALUE_S 0 + +#define SPI_SLV_WRBUF_DLEN_REG(i) (REG_SPI_BASE(i) + 0x48) +/* SPI_SLV_WRBUF_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: In the slave mode it is the length in bits for write-buffer operations. + The register value shall be (bit_num-1).*/ +#define SPI_SLV_WRBUF_DBITLEN 0x00FFFFFF +#define SPI_SLV_WRBUF_DBITLEN_M ((SPI_SLV_WRBUF_DBITLEN_V)<<(SPI_SLV_WRBUF_DBITLEN_S)) +#define SPI_SLV_WRBUF_DBITLEN_V 0xFFFFFF +#define SPI_SLV_WRBUF_DBITLEN_S 0 + +#define SPI_SLV_RDBUF_DLEN_REG(i) (REG_SPI_BASE(i) + 0x4C) +/* SPI_SLV_RDBUF_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: In the slave mode it is the length in bits for read-buffer operations. + The register value shall be (bit_num-1).*/ +#define SPI_SLV_RDBUF_DBITLEN 0x00FFFFFF +#define SPI_SLV_RDBUF_DBITLEN_M ((SPI_SLV_RDBUF_DBITLEN_V)<<(SPI_SLV_RDBUF_DBITLEN_S)) +#define SPI_SLV_RDBUF_DBITLEN_V 0xFFFFFF +#define SPI_SLV_RDBUF_DBITLEN_S 0 + +#define SPI_CACHE_FCTRL_REG(i) (REG_SPI_BASE(i) + 0x50) +/* SPI_CACHE_FLASH_PES_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: For SPI0 spi1 send suspend command before cache read flash + 1: enable 0:disable.*/ +#define SPI_CACHE_FLASH_PES_EN (BIT(3)) +#define SPI_CACHE_FLASH_PES_EN_M (BIT(3)) +#define SPI_CACHE_FLASH_PES_EN_V 0x1 +#define SPI_CACHE_FLASH_PES_EN_S 3 +/* SPI_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: For SPI0 cache read flash for user define command 1: enable 0:disable.*/ +#define SPI_CACHE_FLASH_USR_CMD (BIT(2)) +#define SPI_CACHE_FLASH_USR_CMD_M (BIT(2)) +#define SPI_CACHE_FLASH_USR_CMD_V 0x1 +#define SPI_CACHE_FLASH_USR_CMD_S 2 +/* SPI_CACHE_USR_CMD_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: For SPI0 cache read flash with 4 bytes command 1: enable 0:disable.*/ +#define SPI_CACHE_USR_CMD_4BYTE (BIT(1)) +#define SPI_CACHE_USR_CMD_4BYTE_M (BIT(1)) +#define SPI_CACHE_USR_CMD_4BYTE_V 0x1 +#define SPI_CACHE_USR_CMD_4BYTE_S 1 +/* SPI_CACHE_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: For SPI0 Cache access enable 1: enable 0:disable.*/ +#define SPI_CACHE_REQ_EN (BIT(0)) +#define SPI_CACHE_REQ_EN_M (BIT(0)) +#define SPI_CACHE_REQ_EN_V 0x1 +#define SPI_CACHE_REQ_EN_S 0 + +#define SPI_CACHE_SCTRL_REG(i) (REG_SPI_BASE(i) + 0x54) +/* SPI_CACHE_SRAM_USR_WCMD : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: For SPI0 In the spi sram mode cache write sram for user define command*/ +#define SPI_CACHE_SRAM_USR_WCMD (BIT(28)) +#define SPI_CACHE_SRAM_USR_WCMD_M (BIT(28)) +#define SPI_CACHE_SRAM_USR_WCMD_V 0x1 +#define SPI_CACHE_SRAM_USR_WCMD_S 28 +/* SPI_SRAM_ADDR_BITLEN : R/W ;bitpos:[27:22] ;default: 6'd23 ; */ +/*description: For SPI0 In the sram mode it is the length in bits of address + phase. The register value shall be (bit_num-1).*/ +#define SPI_SRAM_ADDR_BITLEN 0x0000003F +#define SPI_SRAM_ADDR_BITLEN_M ((SPI_SRAM_ADDR_BITLEN_V)<<(SPI_SRAM_ADDR_BITLEN_S)) +#define SPI_SRAM_ADDR_BITLEN_V 0x3F +#define SPI_SRAM_ADDR_BITLEN_S 22 +/* SPI_SRAM_DUMMY_CYCLELEN : R/W ;bitpos:[21:14] ;default: 8'b1 ; */ +/*description: For SPI0 In the sram mode it is the length in bits of address + phase. The register value shall be (bit_num-1).*/ +#define SPI_SRAM_DUMMY_CYCLELEN 0x000000FF +#define SPI_SRAM_DUMMY_CYCLELEN_M ((SPI_SRAM_DUMMY_CYCLELEN_V)<<(SPI_SRAM_DUMMY_CYCLELEN_S)) +#define SPI_SRAM_DUMMY_CYCLELEN_V 0xFF +#define SPI_SRAM_DUMMY_CYCLELEN_S 14 +/* SPI_SRAM_BYTES_LEN : R/W ;bitpos:[13:6] ;default: 8'b32 ; */ +/*description: For SPI0 In the sram mode it is the byte length of spi read sram data.*/ +#define SPI_SRAM_BYTES_LEN 0x000000FF +#define SPI_SRAM_BYTES_LEN_M ((SPI_SRAM_BYTES_LEN_V)<<(SPI_SRAM_BYTES_LEN_S)) +#define SPI_SRAM_BYTES_LEN_V 0xFF +#define SPI_SRAM_BYTES_LEN_S 6 +/* SPI_CACHE_SRAM_USR_RCMD : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: For SPI0 In the spi sram mode cache read sram for user define command.*/ +#define SPI_CACHE_SRAM_USR_RCMD (BIT(5)) +#define SPI_CACHE_SRAM_USR_RCMD_M (BIT(5)) +#define SPI_CACHE_SRAM_USR_RCMD_V 0x1 +#define SPI_CACHE_SRAM_USR_RCMD_S 5 +/* SPI_USR_RD_SRAM_DUMMY : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: For SPI0 In the spi sram mode it is the enable bit of dummy + phase for read operations.*/ +#define SPI_USR_RD_SRAM_DUMMY (BIT(4)) +#define SPI_USR_RD_SRAM_DUMMY_M (BIT(4)) +#define SPI_USR_RD_SRAM_DUMMY_V 0x1 +#define SPI_USR_RD_SRAM_DUMMY_S 4 +/* SPI_USR_WR_SRAM_DUMMY : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: For SPI0 In the spi sram mode it is the enable bit of dummy + phase for write operations.*/ +#define SPI_USR_WR_SRAM_DUMMY (BIT(3)) +#define SPI_USR_WR_SRAM_DUMMY_M (BIT(3)) +#define SPI_USR_WR_SRAM_DUMMY_V 0x1 +#define SPI_USR_WR_SRAM_DUMMY_S 3 +/* SPI_USR_SRAM_QIO : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: For SPI0 In the spi sram mode spi quad I/O mode enable 1: enable 0:disable*/ +#define SPI_USR_SRAM_QIO (BIT(2)) +#define SPI_USR_SRAM_QIO_M (BIT(2)) +#define SPI_USR_SRAM_QIO_V 0x1 +#define SPI_USR_SRAM_QIO_S 2 +/* SPI_USR_SRAM_DIO : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: For SPI0 In the spi sram mode spi dual I/O mode enable 1: enable 0:disable*/ +#define SPI_USR_SRAM_DIO (BIT(1)) +#define SPI_USR_SRAM_DIO_M (BIT(1)) +#define SPI_USR_SRAM_DIO_V 0x1 +#define SPI_USR_SRAM_DIO_S 1 + +#define SPI_SRAM_CMD_REG(i) (REG_SPI_BASE(i) + 0x58) +/* SPI_SRAM_RSTIO : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: For SPI0 SRAM IO mode reset enable. SRAM IO mode reset operation + will be triggered when the bit is set. The bit will be cleared once the operation done*/ +#define SPI_SRAM_RSTIO (BIT(4)) +#define SPI_SRAM_RSTIO_M (BIT(4)) +#define SPI_SRAM_RSTIO_V 0x1 +#define SPI_SRAM_RSTIO_S 4 +/* SPI_SRAM_QIO : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: For SPI0 SRAM QIO mode enable . SRAM QIO enable command will + be send when the bit is set. The bit will be cleared once the operation done.*/ +#define SPI_SRAM_QIO (BIT(1)) +#define SPI_SRAM_QIO_M (BIT(1)) +#define SPI_SRAM_QIO_V 0x1 +#define SPI_SRAM_QIO_S 1 +/* SPI_SRAM_DIO : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: For SPI0 SRAM DIO mode enable . SRAM DIO enable command will + be send when the bit is set. The bit will be cleared once the operation done.*/ +#define SPI_SRAM_DIO (BIT(0)) +#define SPI_SRAM_DIO_M (BIT(0)) +#define SPI_SRAM_DIO_V 0x1 +#define SPI_SRAM_DIO_S 0 + +#define SPI_SRAM_DRD_CMD_REG(i) (REG_SPI_BASE(i) + 0x5C) +/* SPI_CACHE_SRAM_USR_RD_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: For SPI0 When cache mode is enable it is the length in bits of + command phase for SRAM. The register value shall be (bit_num-1).*/ +#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000F +#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_M ((SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V)<<(SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S)) +#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V 0xF +#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S 28 +/* SPI_CACHE_SRAM_USR_RD_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: For SPI0 When cache mode is enable it is the read command value + of command phase for SRAM.*/ +#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE 0x0000FFFF +#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE_M ((SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V)<<(SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S)) +#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V 0xFFFF +#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S 0 + +#define SPI_SRAM_DWR_CMD_REG(i) (REG_SPI_BASE(i) + 0x60) +/* SPI_CACHE_SRAM_USR_WR_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: For SPI0 When cache mode is enable it is the in bits of command + phase for SRAM. The register value shall be (bit_num-1).*/ +#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN 0x0000000F +#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_M ((SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_V)<<(SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S)) +#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_V 0xF +#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S 28 +/* SPI_CACHE_SRAM_USR_WR_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: For SPI0 When cache mode is enable it is the write command value + of command phase for SRAM.*/ +#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE 0x0000FFFF +#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE_M ((SPI_CACHE_SRAM_USR_WR_CMD_VALUE_V)<<(SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S)) +#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE_V 0xFFFF +#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S 0 + +#define SPI_SLV_RD_BIT_REG(i) (REG_SPI_BASE(i) + 0x64) +/* SPI_SLV_RDATA_BIT : RW ;bitpos:[23:0] ;default: 24'b0 ; */ +/*description: In the slave mode it is the bit length of read data. The value + is the length - 1.*/ +#define SPI_SLV_RDATA_BIT 0x00FFFFFF +#define SPI_SLV_RDATA_BIT_M ((SPI_SLV_RDATA_BIT_V)<<(SPI_SLV_RDATA_BIT_S)) +#define SPI_SLV_RDATA_BIT_V 0xFFFFFF +#define SPI_SLV_RDATA_BIT_S 0 + +#define SPI_W0_REG(i) (REG_SPI_BASE(i) + 0x80) +/* SPI_BUF0 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF0 0xFFFFFFFF +#define SPI_BUF0_M ((SPI_BUF0_V)<<(SPI_BUF0_S)) +#define SPI_BUF0_V 0xFFFFFFFF +#define SPI_BUF0_S 0 + +#define SPI_W1_REG(i) (REG_SPI_BASE(i) + 0x84) +/* SPI_BUF1 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF1 0xFFFFFFFF +#define SPI_BUF1_M ((SPI_BUF1_V)<<(SPI_BUF1_S)) +#define SPI_BUF1_V 0xFFFFFFFF +#define SPI_BUF1_S 0 + +#define SPI_W2_REG(i) (REG_SPI_BASE(i) + 0x88) +/* SPI_BUF2 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF2 0xFFFFFFFF +#define SPI_BUF2_M ((SPI_BUF2_V)<<(SPI_BUF2_S)) +#define SPI_BUF2_V 0xFFFFFFFF +#define SPI_BUF2_S 0 + +#define SPI_W3_REG(i) (REG_SPI_BASE(i) + 0x8C) +/* SPI_BUF3 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF3 0xFFFFFFFF +#define SPI_BUF3_M ((SPI_BUF3_V)<<(SPI_BUF3_S)) +#define SPI_BUF3_V 0xFFFFFFFF +#define SPI_BUF3_S 0 + +#define SPI_W4_REG(i) (REG_SPI_BASE(i) + 0x90) +/* SPI_BUF4 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF4 0xFFFFFFFF +#define SPI_BUF4_M ((SPI_BUF4_V)<<(SPI_BUF4_S)) +#define SPI_BUF4_V 0xFFFFFFFF +#define SPI_BUF4_S 0 + +#define SPI_W5_REG(i) (REG_SPI_BASE(i) + 0x94) +/* SPI_BUF5 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF5 0xFFFFFFFF +#define SPI_BUF5_M ((SPI_BUF5_V)<<(SPI_BUF5_S)) +#define SPI_BUF5_V 0xFFFFFFFF +#define SPI_BUF5_S 0 + +#define SPI_W6_REG(i) (REG_SPI_BASE(i) + 0x98) +/* SPI_BUF6 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF6 0xFFFFFFFF +#define SPI_BUF6_M ((SPI_BUF6_V)<<(SPI_BUF6_S)) +#define SPI_BUF6_V 0xFFFFFFFF +#define SPI_BUF6_S 0 + +#define SPI_W7_REG(i) (REG_SPI_BASE(i) + 0x9C) +/* SPI_BUF7 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF7 0xFFFFFFFF +#define SPI_BUF7_M ((SPI_BUF7_V)<<(SPI_BUF7_S)) +#define SPI_BUF7_V 0xFFFFFFFF +#define SPI_BUF7_S 0 + +#define SPI_W8_REG(i) (REG_SPI_BASE(i) + 0xA0) +/* SPI_BUF8 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF8 0xFFFFFFFF +#define SPI_BUF8_M ((SPI_BUF8_V)<<(SPI_BUF8_S)) +#define SPI_BUF8_V 0xFFFFFFFF +#define SPI_BUF8_S 0 + +#define SPI_W9_REG(i) (REG_SPI_BASE(i) + 0xA4) +/* SPI_BUF9 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF9 0xFFFFFFFF +#define SPI_BUF9_M ((SPI_BUF9_V)<<(SPI_BUF9_S)) +#define SPI_BUF9_V 0xFFFFFFFF +#define SPI_BUF9_S 0 + +#define SPI_W10_REG(i) (REG_SPI_BASE(i) + 0xA8) +/* SPI_BUF10 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF10 0xFFFFFFFF +#define SPI_BUF10_M ((SPI_BUF10_V)<<(SPI_BUF10_S)) +#define SPI_BUF10_V 0xFFFFFFFF +#define SPI_BUF10_S 0 + +#define SPI_W11_REG(i) (REG_SPI_BASE(i) + 0xAC) +/* SPI_BUF11 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF11 0xFFFFFFFF +#define SPI_BUF11_M ((SPI_BUF11_V)<<(SPI_BUF11_S)) +#define SPI_BUF11_V 0xFFFFFFFF +#define SPI_BUF11_S 0 + +#define SPI_W12_REG(i) (REG_SPI_BASE(i) + 0xB0) +/* SPI_BUF12 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF12 0xFFFFFFFF +#define SPI_BUF12_M ((SPI_BUF12_V)<<(SPI_BUF12_S)) +#define SPI_BUF12_V 0xFFFFFFFF +#define SPI_BUF12_S 0 + +#define SPI_W13_REG(i) (REG_SPI_BASE(i) + 0xB4) +/* SPI_BUF13 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF13 0xFFFFFFFF +#define SPI_BUF13_M ((SPI_BUF13_V)<<(SPI_BUF13_S)) +#define SPI_BUF13_V 0xFFFFFFFF +#define SPI_BUF13_S 0 + +#define SPI_W14_REG(i) (REG_SPI_BASE(i) + 0xB8) +/* SPI_BUF14 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF14 0xFFFFFFFF +#define SPI_BUF14_M ((SPI_BUF14_V)<<(SPI_BUF14_S)) +#define SPI_BUF14_V 0xFFFFFFFF +#define SPI_BUF14_S 0 + +#define SPI_W15_REG(i) (REG_SPI_BASE(i) + 0xBC) +/* SPI_BUF15 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF15 0xFFFFFFFF +#define SPI_BUF15_M ((SPI_BUF15_V)<<(SPI_BUF15_S)) +#define SPI_BUF15_V 0xFFFFFFFF +#define SPI_BUF15_S 0 + +#define SPI_TX_CRC_REG(i) (REG_SPI_BASE(i) + 0xC0) +/* SPI_TX_CRC_DATA : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: For SPI1 the value of crc32 for 256 bits data.*/ +#define SPI_TX_CRC_DATA 0xFFFFFFFF +#define SPI_TX_CRC_DATA_M ((SPI_TX_CRC_DATA_V)<<(SPI_TX_CRC_DATA_S)) +#define SPI_TX_CRC_DATA_V 0xFFFFFFFF +#define SPI_TX_CRC_DATA_S 0 + +#define SPI_EXT0_REG(i) (REG_SPI_BASE(i) + 0xF0) +/* SPI_T_PP_ENA : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: page program delay enable.*/ +#define SPI_T_PP_ENA (BIT(31)) +#define SPI_T_PP_ENA_M (BIT(31)) +#define SPI_T_PP_ENA_V 0x1 +#define SPI_T_PP_ENA_S 31 +/* SPI_T_PP_SHIFT : R/W ;bitpos:[19:16] ;default: 4'd10 ; */ +/*description: page program delay time shift .*/ +#define SPI_T_PP_SHIFT 0x0000000F +#define SPI_T_PP_SHIFT_M ((SPI_T_PP_SHIFT_V)<<(SPI_T_PP_SHIFT_S)) +#define SPI_T_PP_SHIFT_V 0xF +#define SPI_T_PP_SHIFT_S 16 +/* SPI_T_PP_TIME : R/W ;bitpos:[11:0] ;default: 12'd80 ; */ +/*description: page program delay time by system clock.*/ +#define SPI_T_PP_TIME 0x00000FFF +#define SPI_T_PP_TIME_M ((SPI_T_PP_TIME_V)<<(SPI_T_PP_TIME_S)) +#define SPI_T_PP_TIME_V 0xFFF +#define SPI_T_PP_TIME_S 0 + +#define SPI_EXT1_REG(i) (REG_SPI_BASE(i) + 0xF4) +/* SPI_T_ERASE_ENA : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: erase flash delay enable.*/ +#define SPI_T_ERASE_ENA (BIT(31)) +#define SPI_T_ERASE_ENA_M (BIT(31)) +#define SPI_T_ERASE_ENA_V 0x1 +#define SPI_T_ERASE_ENA_S 31 +/* SPI_T_ERASE_SHIFT : R/W ;bitpos:[19:16] ;default: 4'd15 ; */ +/*description: erase flash delay time shift.*/ +#define SPI_T_ERASE_SHIFT 0x0000000F +#define SPI_T_ERASE_SHIFT_M ((SPI_T_ERASE_SHIFT_V)<<(SPI_T_ERASE_SHIFT_S)) +#define SPI_T_ERASE_SHIFT_V 0xF +#define SPI_T_ERASE_SHIFT_S 16 +/* SPI_T_ERASE_TIME : R/W ;bitpos:[11:0] ;default: 12'd0 ; */ +/*description: erase flash delay time by system clock.*/ +#define SPI_T_ERASE_TIME 0x00000FFF +#define SPI_T_ERASE_TIME_M ((SPI_T_ERASE_TIME_V)<<(SPI_T_ERASE_TIME_S)) +#define SPI_T_ERASE_TIME_V 0xFFF +#define SPI_T_ERASE_TIME_S 0 + +#define SPI_EXT2_REG(i) (REG_SPI_BASE(i) + 0xF8) +/* SPI_ST : RO ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: The status of spi state machine .*/ +#define SPI_ST 0x00000007 +#define SPI_ST_M ((SPI_ST_V)<<(SPI_ST_S)) +#define SPI_ST_V 0x7 +#define SPI_ST_S 0 + +#define SPI_EXT3_REG(i) (REG_SPI_BASE(i) + 0xFC) +/* SPI_INT_HOLD_ENA : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: This register is for two SPI masters to share the same cs clock + and data signals. The bits of one SPI are set if the other SPI is busy the SPI will be hold. 1(3): hold at ¡°idle¡± phase 2: hold at ¡°prepare¡± phase.*/ +#define SPI_INT_HOLD_ENA 0x00000003 +#define SPI_INT_HOLD_ENA_M ((SPI_INT_HOLD_ENA_V)<<(SPI_INT_HOLD_ENA_S)) +#define SPI_INT_HOLD_ENA_V 0x3 +#define SPI_INT_HOLD_ENA_S 0 + +#define SPI_DMA_CONF_REG(i) (REG_SPI_BASE(i) + 0x100) +/* SPI_DMA_CONTINUE : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: spi dma continue tx/rx data.*/ +#define SPI_DMA_CONTINUE (BIT(16)) +#define SPI_DMA_CONTINUE_M (BIT(16)) +#define SPI_DMA_CONTINUE_V 0x1 +#define SPI_DMA_CONTINUE_S 16 +/* SPI_DMA_TX_STOP : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: spi dma write data stop when in continue tx/rx mode.*/ +#define SPI_DMA_TX_STOP (BIT(15)) +#define SPI_DMA_TX_STOP_M (BIT(15)) +#define SPI_DMA_TX_STOP_V 0x1 +#define SPI_DMA_TX_STOP_S 15 +/* SPI_DMA_RX_STOP : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: spi dma read data stop when in continue tx/rx mode.*/ +#define SPI_DMA_RX_STOP (BIT(14)) +#define SPI_DMA_RX_STOP_M (BIT(14)) +#define SPI_DMA_RX_STOP_V 0x1 +#define SPI_DMA_RX_STOP_S 14 +/* SPI_OUT_DATA_BURST_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: spi dma read data from memory in burst mode.*/ +#define SPI_OUT_DATA_BURST_EN (BIT(12)) +#define SPI_OUT_DATA_BURST_EN_M (BIT(12)) +#define SPI_OUT_DATA_BURST_EN_V 0x1 +#define SPI_OUT_DATA_BURST_EN_S 12 +/* SPI_INDSCR_BURST_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: read descriptor use burst mode when write data to memory.*/ +#define SPI_INDSCR_BURST_EN (BIT(11)) +#define SPI_INDSCR_BURST_EN_M (BIT(11)) +#define SPI_INDSCR_BURST_EN_V 0x1 +#define SPI_INDSCR_BURST_EN_S 11 +/* SPI_OUTDSCR_BURST_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: read descriptor use burst mode when read data for memory.*/ +#define SPI_OUTDSCR_BURST_EN (BIT(10)) +#define SPI_OUTDSCR_BURST_EN_M (BIT(10)) +#define SPI_OUTDSCR_BURST_EN_V 0x1 +#define SPI_OUTDSCR_BURST_EN_S 10 +/* SPI_OUT_EOF_MODE : R/W ;bitpos:[9] ;default: 1'b1 ; */ +/*description: out eof flag generation mode . 1: when dma pop all data from + fifo 0:when ahb push all data to fifo.*/ +#define SPI_OUT_EOF_MODE (BIT(9)) +#define SPI_OUT_EOF_MODE_M (BIT(9)) +#define SPI_OUT_EOF_MODE_V 0x1 +#define SPI_OUT_EOF_MODE_S 9 +/* SPI_OUT_AUTO_WRBACK : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: when the link is empty jump to next automatically.*/ +#define SPI_OUT_AUTO_WRBACK (BIT(8)) +#define SPI_OUT_AUTO_WRBACK_M (BIT(8)) +#define SPI_OUT_AUTO_WRBACK_V 0x1 +#define SPI_OUT_AUTO_WRBACK_S 8 +/* SPI_OUT_LOOP_TEST : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set bit to test out link.*/ +#define SPI_OUT_LOOP_TEST (BIT(7)) +#define SPI_OUT_LOOP_TEST_M (BIT(7)) +#define SPI_OUT_LOOP_TEST_V 0x1 +#define SPI_OUT_LOOP_TEST_S 7 +/* SPI_IN_LOOP_TEST : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set bit to test in link.*/ +#define SPI_IN_LOOP_TEST (BIT(6)) +#define SPI_IN_LOOP_TEST_M (BIT(6)) +#define SPI_IN_LOOP_TEST_V 0x1 +#define SPI_IN_LOOP_TEST_S 6 +/* SPI_AHBM_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: reset spi dma ahb master.*/ +#define SPI_AHBM_RST (BIT(5)) +#define SPI_AHBM_RST_M (BIT(5)) +#define SPI_AHBM_RST_V 0x1 +#define SPI_AHBM_RST_S 5 +/* SPI_AHBM_FIFO_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: reset spi dma ahb master fifo pointer.*/ +#define SPI_AHBM_FIFO_RST (BIT(4)) +#define SPI_AHBM_FIFO_RST_M (BIT(4)) +#define SPI_AHBM_FIFO_RST_V 0x1 +#define SPI_AHBM_FIFO_RST_S 4 +/* SPI_OUT_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The bit is used to reset out dma fsm and out data fifo pointer.*/ +#define SPI_OUT_RST (BIT(3)) +#define SPI_OUT_RST_M (BIT(3)) +#define SPI_OUT_RST_V 0x1 +#define SPI_OUT_RST_S 3 +/* SPI_IN_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to reset in dma fsm and in data fifo pointer.*/ +#define SPI_IN_RST (BIT(2)) +#define SPI_IN_RST_M (BIT(2)) +#define SPI_IN_RST_V 0x1 +#define SPI_IN_RST_S 2 + +#define SPI_DMA_OUT_LINK_REG(i) (REG_SPI_BASE(i) + 0x104) +/* SPI_OUTLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Set the bit to mount on new outlink descriptors.*/ +#define SPI_OUTLINK_RESTART (BIT(30)) +#define SPI_OUTLINK_RESTART_M (BIT(30)) +#define SPI_OUTLINK_RESTART_V 0x1 +#define SPI_OUTLINK_RESTART_S 30 +/* SPI_OUTLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Set the bit to start to use outlink descriptor.*/ +#define SPI_OUTLINK_START (BIT(29)) +#define SPI_OUTLINK_START_M (BIT(29)) +#define SPI_OUTLINK_START_V 0x1 +#define SPI_OUTLINK_START_S 29 +/* SPI_OUTLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Set the bit to stop to use outlink descriptor.*/ +#define SPI_OUTLINK_STOP (BIT(28)) +#define SPI_OUTLINK_STOP_M (BIT(28)) +#define SPI_OUTLINK_STOP_V 0x1 +#define SPI_OUTLINK_STOP_S 28 +/* SPI_OUTLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The address of the first outlink descriptor.*/ +#define SPI_OUTLINK_ADDR 0x000FFFFF +#define SPI_OUTLINK_ADDR_M ((SPI_OUTLINK_ADDR_V)<<(SPI_OUTLINK_ADDR_S)) +#define SPI_OUTLINK_ADDR_V 0xFFFFF +#define SPI_OUTLINK_ADDR_S 0 + +#define SPI_DMA_IN_LINK_REG(i) (REG_SPI_BASE(i) + 0x108) +/* SPI_INLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Set the bit to mount on new inlink descriptors.*/ +#define SPI_INLINK_RESTART (BIT(30)) +#define SPI_INLINK_RESTART_M (BIT(30)) +#define SPI_INLINK_RESTART_V 0x1 +#define SPI_INLINK_RESTART_S 30 +/* SPI_INLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Set the bit to start to use inlink descriptor.*/ +#define SPI_INLINK_START (BIT(29)) +#define SPI_INLINK_START_M (BIT(29)) +#define SPI_INLINK_START_V 0x1 +#define SPI_INLINK_START_S 29 +/* SPI_INLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Set the bit to stop to use inlink descriptor.*/ +#define SPI_INLINK_STOP (BIT(28)) +#define SPI_INLINK_STOP_M (BIT(28)) +#define SPI_INLINK_STOP_V 0x1 +#define SPI_INLINK_STOP_S 28 +/* SPI_INLINK_AUTO_RET : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: when the bit is set inlink descriptor returns to the next descriptor + while a packet is wrong*/ +#define SPI_INLINK_AUTO_RET (BIT(20)) +#define SPI_INLINK_AUTO_RET_M (BIT(20)) +#define SPI_INLINK_AUTO_RET_V 0x1 +#define SPI_INLINK_AUTO_RET_S 20 +/* SPI_INLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The address of the first inlink descriptor.*/ +#define SPI_INLINK_ADDR 0x000FFFFF +#define SPI_INLINK_ADDR_M ((SPI_INLINK_ADDR_V)<<(SPI_INLINK_ADDR_S)) +#define SPI_INLINK_ADDR_V 0xFFFFF +#define SPI_INLINK_ADDR_S 0 + +#define SPI_DMA_STATUS_REG(i) (REG_SPI_BASE(i) + 0x10C) +/* SPI_DMA_TX_EN : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: spi dma write data status bit.*/ +#define SPI_DMA_TX_EN (BIT(1)) +#define SPI_DMA_TX_EN_M (BIT(1)) +#define SPI_DMA_TX_EN_V 0x1 +#define SPI_DMA_TX_EN_S 1 +/* SPI_DMA_RX_EN : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: spi dma read data status bit.*/ +#define SPI_DMA_RX_EN (BIT(0)) +#define SPI_DMA_RX_EN_M (BIT(0)) +#define SPI_DMA_RX_EN_V 0x1 +#define SPI_DMA_RX_EN_S 0 + +#define SPI_DMA_INT_ENA_REG(i) (REG_SPI_BASE(i) + 0x110) +/* SPI_OUT_TOTAL_EOF_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The enable bit for sending all the packets to host done.*/ +#define SPI_OUT_TOTAL_EOF_INT_ENA (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_ENA_M (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_ENA_V 0x1 +#define SPI_OUT_TOTAL_EOF_INT_ENA_S 8 +/* SPI_OUT_EOF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The enable bit for sending a packet to host done.*/ +#define SPI_OUT_EOF_INT_ENA (BIT(7)) +#define SPI_OUT_EOF_INT_ENA_M (BIT(7)) +#define SPI_OUT_EOF_INT_ENA_V 0x1 +#define SPI_OUT_EOF_INT_ENA_S 7 +/* SPI_OUT_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The enable bit for completing usage of a outlink descriptor .*/ +#define SPI_OUT_DONE_INT_ENA (BIT(6)) +#define SPI_OUT_DONE_INT_ENA_M (BIT(6)) +#define SPI_OUT_DONE_INT_ENA_V 0x1 +#define SPI_OUT_DONE_INT_ENA_S 6 +/* SPI_IN_SUC_EOF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The enable bit for completing receiving all the packets from host.*/ +#define SPI_IN_SUC_EOF_INT_ENA (BIT(5)) +#define SPI_IN_SUC_EOF_INT_ENA_M (BIT(5)) +#define SPI_IN_SUC_EOF_INT_ENA_V 0x1 +#define SPI_IN_SUC_EOF_INT_ENA_S 5 +/* SPI_IN_ERR_EOF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The enable bit for receiving error.*/ +#define SPI_IN_ERR_EOF_INT_ENA (BIT(4)) +#define SPI_IN_ERR_EOF_INT_ENA_M (BIT(4)) +#define SPI_IN_ERR_EOF_INT_ENA_V 0x1 +#define SPI_IN_ERR_EOF_INT_ENA_S 4 +/* SPI_IN_DONE_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The enable bit for completing usage of a inlink descriptor.*/ +#define SPI_IN_DONE_INT_ENA (BIT(3)) +#define SPI_IN_DONE_INT_ENA_M (BIT(3)) +#define SPI_IN_DONE_INT_ENA_V 0x1 +#define SPI_IN_DONE_INT_ENA_S 3 +/* SPI_INLINK_DSCR_ERROR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The enable bit for inlink descriptor error.*/ +#define SPI_INLINK_DSCR_ERROR_INT_ENA (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_ENA_M (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_ENA_V 0x1 +#define SPI_INLINK_DSCR_ERROR_INT_ENA_S 2 +/* SPI_OUTLINK_DSCR_ERROR_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The enable bit for outlink descriptor error.*/ +#define SPI_OUTLINK_DSCR_ERROR_INT_ENA (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_M (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_V 0x1 +#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_S 1 +/* SPI_INLINK_DSCR_EMPTY_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The enable bit for lack of enough inlink descriptors.*/ +#define SPI_INLINK_DSCR_EMPTY_INT_ENA (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_ENA_M (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_ENA_V 0x1 +#define SPI_INLINK_DSCR_EMPTY_INT_ENA_S 0 + +#define SPI_DMA_INT_RAW_REG(i) (REG_SPI_BASE(i) + 0x114) +/* SPI_OUT_TOTAL_EOF_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The raw bit for sending all the packets to host done.*/ +#define SPI_OUT_TOTAL_EOF_INT_RAW (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_RAW_M (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_RAW_V 0x1 +#define SPI_OUT_TOTAL_EOF_INT_RAW_S 8 +/* SPI_OUT_EOF_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw bit for sending a packet to host done.*/ +#define SPI_OUT_EOF_INT_RAW (BIT(7)) +#define SPI_OUT_EOF_INT_RAW_M (BIT(7)) +#define SPI_OUT_EOF_INT_RAW_V 0x1 +#define SPI_OUT_EOF_INT_RAW_S 7 +/* SPI_OUT_DONE_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw bit for completing usage of a outlink descriptor.*/ +#define SPI_OUT_DONE_INT_RAW (BIT(6)) +#define SPI_OUT_DONE_INT_RAW_M (BIT(6)) +#define SPI_OUT_DONE_INT_RAW_V 0x1 +#define SPI_OUT_DONE_INT_RAW_S 6 +/* SPI_IN_SUC_EOF_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw bit for completing receiving all the packets from host.*/ +#define SPI_IN_SUC_EOF_INT_RAW (BIT(5)) +#define SPI_IN_SUC_EOF_INT_RAW_M (BIT(5)) +#define SPI_IN_SUC_EOF_INT_RAW_V 0x1 +#define SPI_IN_SUC_EOF_INT_RAW_S 5 +/* SPI_IN_ERR_EOF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw bit for receiving error.*/ +#define SPI_IN_ERR_EOF_INT_RAW (BIT(4)) +#define SPI_IN_ERR_EOF_INT_RAW_M (BIT(4)) +#define SPI_IN_ERR_EOF_INT_RAW_V 0x1 +#define SPI_IN_ERR_EOF_INT_RAW_S 4 +/* SPI_IN_DONE_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw bit for completing usage of a inlink descriptor.*/ +#define SPI_IN_DONE_INT_RAW (BIT(3)) +#define SPI_IN_DONE_INT_RAW_M (BIT(3)) +#define SPI_IN_DONE_INT_RAW_V 0x1 +#define SPI_IN_DONE_INT_RAW_S 3 +/* SPI_INLINK_DSCR_ERROR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw bit for inlink descriptor error.*/ +#define SPI_INLINK_DSCR_ERROR_INT_RAW (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_RAW_M (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_RAW_V 0x1 +#define SPI_INLINK_DSCR_ERROR_INT_RAW_S 2 +/* SPI_OUTLINK_DSCR_ERROR_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw bit for outlink descriptor error.*/ +#define SPI_OUTLINK_DSCR_ERROR_INT_RAW (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_M (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_V 0x1 +#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_S 1 +/* SPI_INLINK_DSCR_EMPTY_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw bit for lack of enough inlink descriptors.*/ +#define SPI_INLINK_DSCR_EMPTY_INT_RAW (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_RAW_M (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_RAW_V 0x1 +#define SPI_INLINK_DSCR_EMPTY_INT_RAW_S 0 + +#define SPI_DMA_INT_ST_REG(i) (REG_SPI_BASE(i) + 0x118) +/* SPI_OUT_TOTAL_EOF_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The status bit for sending all the packets to host done.*/ +#define SPI_OUT_TOTAL_EOF_INT_ST (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_ST_M (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_ST_V 0x1 +#define SPI_OUT_TOTAL_EOF_INT_ST_S 8 +/* SPI_OUT_EOF_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The status bit for sending a packet to host done.*/ +#define SPI_OUT_EOF_INT_ST (BIT(7)) +#define SPI_OUT_EOF_INT_ST_M (BIT(7)) +#define SPI_OUT_EOF_INT_ST_V 0x1 +#define SPI_OUT_EOF_INT_ST_S 7 +/* SPI_OUT_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The status bit for completing usage of a outlink descriptor.*/ +#define SPI_OUT_DONE_INT_ST (BIT(6)) +#define SPI_OUT_DONE_INT_ST_M (BIT(6)) +#define SPI_OUT_DONE_INT_ST_V 0x1 +#define SPI_OUT_DONE_INT_ST_S 6 +/* SPI_IN_SUC_EOF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The status bit for completing receiving all the packets from host.*/ +#define SPI_IN_SUC_EOF_INT_ST (BIT(5)) +#define SPI_IN_SUC_EOF_INT_ST_M (BIT(5)) +#define SPI_IN_SUC_EOF_INT_ST_V 0x1 +#define SPI_IN_SUC_EOF_INT_ST_S 5 +/* SPI_IN_ERR_EOF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The status bit for receiving error.*/ +#define SPI_IN_ERR_EOF_INT_ST (BIT(4)) +#define SPI_IN_ERR_EOF_INT_ST_M (BIT(4)) +#define SPI_IN_ERR_EOF_INT_ST_V 0x1 +#define SPI_IN_ERR_EOF_INT_ST_S 4 +/* SPI_IN_DONE_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The status bit for completing usage of a inlink descriptor.*/ +#define SPI_IN_DONE_INT_ST (BIT(3)) +#define SPI_IN_DONE_INT_ST_M (BIT(3)) +#define SPI_IN_DONE_INT_ST_V 0x1 +#define SPI_IN_DONE_INT_ST_S 3 +/* SPI_INLINK_DSCR_ERROR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The status bit for inlink descriptor error.*/ +#define SPI_INLINK_DSCR_ERROR_INT_ST (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_ST_M (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_ST_V 0x1 +#define SPI_INLINK_DSCR_ERROR_INT_ST_S 2 +/* SPI_OUTLINK_DSCR_ERROR_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The status bit for outlink descriptor error.*/ +#define SPI_OUTLINK_DSCR_ERROR_INT_ST (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_ST_M (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_ST_V 0x1 +#define SPI_OUTLINK_DSCR_ERROR_INT_ST_S 1 +/* SPI_INLINK_DSCR_EMPTY_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The status bit for lack of enough inlink descriptors.*/ +#define SPI_INLINK_DSCR_EMPTY_INT_ST (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_ST_M (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_ST_V 0x1 +#define SPI_INLINK_DSCR_EMPTY_INT_ST_S 0 + +#define SPI_DMA_INT_CLR_REG(i) (REG_SPI_BASE(i) + 0x11C) +/* SPI_OUT_TOTAL_EOF_INT_CLR : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The clear bit for sending all the packets to host done.*/ +#define SPI_OUT_TOTAL_EOF_INT_CLR (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_CLR_M (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_CLR_V 0x1 +#define SPI_OUT_TOTAL_EOF_INT_CLR_S 8 +/* SPI_OUT_EOF_INT_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The clear bit for sending a packet to host done.*/ +#define SPI_OUT_EOF_INT_CLR (BIT(7)) +#define SPI_OUT_EOF_INT_CLR_M (BIT(7)) +#define SPI_OUT_EOF_INT_CLR_V 0x1 +#define SPI_OUT_EOF_INT_CLR_S 7 +/* SPI_OUT_DONE_INT_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The clear bit for completing usage of a outlink descriptor.*/ +#define SPI_OUT_DONE_INT_CLR (BIT(6)) +#define SPI_OUT_DONE_INT_CLR_M (BIT(6)) +#define SPI_OUT_DONE_INT_CLR_V 0x1 +#define SPI_OUT_DONE_INT_CLR_S 6 +/* SPI_IN_SUC_EOF_INT_CLR : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The clear bit for completing receiving all the packets from host.*/ +#define SPI_IN_SUC_EOF_INT_CLR (BIT(5)) +#define SPI_IN_SUC_EOF_INT_CLR_M (BIT(5)) +#define SPI_IN_SUC_EOF_INT_CLR_V 0x1 +#define SPI_IN_SUC_EOF_INT_CLR_S 5 +/* SPI_IN_ERR_EOF_INT_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The clear bit for receiving error.*/ +#define SPI_IN_ERR_EOF_INT_CLR (BIT(4)) +#define SPI_IN_ERR_EOF_INT_CLR_M (BIT(4)) +#define SPI_IN_ERR_EOF_INT_CLR_V 0x1 +#define SPI_IN_ERR_EOF_INT_CLR_S 4 +/* SPI_IN_DONE_INT_CLR : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The clear bit for completing usage of a inlink descriptor.*/ +#define SPI_IN_DONE_INT_CLR (BIT(3)) +#define SPI_IN_DONE_INT_CLR_M (BIT(3)) +#define SPI_IN_DONE_INT_CLR_V 0x1 +#define SPI_IN_DONE_INT_CLR_S 3 +/* SPI_INLINK_DSCR_ERROR_INT_CLR : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The clear bit for inlink descriptor error.*/ +#define SPI_INLINK_DSCR_ERROR_INT_CLR (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_CLR_M (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_CLR_V 0x1 +#define SPI_INLINK_DSCR_ERROR_INT_CLR_S 2 +/* SPI_OUTLINK_DSCR_ERROR_INT_CLR : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The clear bit for outlink descriptor error.*/ +#define SPI_OUTLINK_DSCR_ERROR_INT_CLR (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_M (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_V 0x1 +#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_S 1 +/* SPI_INLINK_DSCR_EMPTY_INT_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The clear bit for lack of enough inlink descriptors.*/ +#define SPI_INLINK_DSCR_EMPTY_INT_CLR (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_CLR_M (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_CLR_V 0x1 +#define SPI_INLINK_DSCR_EMPTY_INT_CLR_S 0 + +#define SPI_IN_ERR_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x120) +/* SPI_DMA_IN_ERR_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The inlink descriptor address when spi dma produce receiving error.*/ +#define SPI_DMA_IN_ERR_EOF_DES_ADDR 0xFFFFFFFF +#define SPI_DMA_IN_ERR_EOF_DES_ADDR_M ((SPI_DMA_IN_ERR_EOF_DES_ADDR_V)<<(SPI_DMA_IN_ERR_EOF_DES_ADDR_S)) +#define SPI_DMA_IN_ERR_EOF_DES_ADDR_V 0xFFFFFFFF +#define SPI_DMA_IN_ERR_EOF_DES_ADDR_S 0 + +#define SPI_IN_SUC_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x124) +/* SPI_DMA_IN_SUC_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The last inlink descriptor address when spi dma produce from_suc_eof.*/ +#define SPI_DMA_IN_SUC_EOF_DES_ADDR 0xFFFFFFFF +#define SPI_DMA_IN_SUC_EOF_DES_ADDR_M ((SPI_DMA_IN_SUC_EOF_DES_ADDR_V)<<(SPI_DMA_IN_SUC_EOF_DES_ADDR_S)) +#define SPI_DMA_IN_SUC_EOF_DES_ADDR_V 0xFFFFFFFF +#define SPI_DMA_IN_SUC_EOF_DES_ADDR_S 0 + +#define SPI_INLINK_DSCR_REG(i) (REG_SPI_BASE(i) + 0x128) +/* SPI_DMA_INLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The content of current in descriptor pointer.*/ +#define SPI_DMA_INLINK_DSCR 0xFFFFFFFF +#define SPI_DMA_INLINK_DSCR_M ((SPI_DMA_INLINK_DSCR_V)<<(SPI_DMA_INLINK_DSCR_S)) +#define SPI_DMA_INLINK_DSCR_V 0xFFFFFFFF +#define SPI_DMA_INLINK_DSCR_S 0 + +#define SPI_INLINK_DSCR_BF0_REG(i) (REG_SPI_BASE(i) + 0x12C) +/* SPI_DMA_INLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The content of next in descriptor pointer.*/ +#define SPI_DMA_INLINK_DSCR_BF0 0xFFFFFFFF +#define SPI_DMA_INLINK_DSCR_BF0_M ((SPI_DMA_INLINK_DSCR_BF0_V)<<(SPI_DMA_INLINK_DSCR_BF0_S)) +#define SPI_DMA_INLINK_DSCR_BF0_V 0xFFFFFFFF +#define SPI_DMA_INLINK_DSCR_BF0_S 0 + +#define SPI_INLINK_DSCR_BF1_REG(i) (REG_SPI_BASE(i) + 0x130) +/* SPI_DMA_INLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The content of current in descriptor data buffer pointer.*/ +#define SPI_DMA_INLINK_DSCR_BF1 0xFFFFFFFF +#define SPI_DMA_INLINK_DSCR_BF1_M ((SPI_DMA_INLINK_DSCR_BF1_V)<<(SPI_DMA_INLINK_DSCR_BF1_S)) +#define SPI_DMA_INLINK_DSCR_BF1_V 0xFFFFFFFF +#define SPI_DMA_INLINK_DSCR_BF1_S 0 + +#define SPI_OUT_EOF_BFR_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x134) +/* SPI_DMA_OUT_EOF_BFR_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of buffer relative to the outlink descriptor that produce eof.*/ +#define SPI_DMA_OUT_EOF_BFR_DES_ADDR 0xFFFFFFFF +#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_M ((SPI_DMA_OUT_EOF_BFR_DES_ADDR_V)<<(SPI_DMA_OUT_EOF_BFR_DES_ADDR_S)) +#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_V 0xFFFFFFFF +#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_S 0 + +#define SPI_OUT_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x138) +/* SPI_DMA_OUT_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The last outlink descriptor address when spi dma produce to_eof.*/ +#define SPI_DMA_OUT_EOF_DES_ADDR 0xFFFFFFFF +#define SPI_DMA_OUT_EOF_DES_ADDR_M ((SPI_DMA_OUT_EOF_DES_ADDR_V)<<(SPI_DMA_OUT_EOF_DES_ADDR_S)) +#define SPI_DMA_OUT_EOF_DES_ADDR_V 0xFFFFFFFF +#define SPI_DMA_OUT_EOF_DES_ADDR_S 0 + +#define SPI_OUTLINK_DSCR_REG(i) (REG_SPI_BASE(i) + 0x13C) +/* SPI_DMA_OUTLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The content of current out descriptor pointer.*/ +#define SPI_DMA_OUTLINK_DSCR 0xFFFFFFFF +#define SPI_DMA_OUTLINK_DSCR_M ((SPI_DMA_OUTLINK_DSCR_V)<<(SPI_DMA_OUTLINK_DSCR_S)) +#define SPI_DMA_OUTLINK_DSCR_V 0xFFFFFFFF +#define SPI_DMA_OUTLINK_DSCR_S 0 + +#define SPI_OUTLINK_DSCR_BF0_REG(i) (REG_SPI_BASE(i) + 0x140) +/* SPI_DMA_OUTLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The content of next out descriptor pointer.*/ +#define SPI_DMA_OUTLINK_DSCR_BF0 0xFFFFFFFF +#define SPI_DMA_OUTLINK_DSCR_BF0_M ((SPI_DMA_OUTLINK_DSCR_BF0_V)<<(SPI_DMA_OUTLINK_DSCR_BF0_S)) +#define SPI_DMA_OUTLINK_DSCR_BF0_V 0xFFFFFFFF +#define SPI_DMA_OUTLINK_DSCR_BF0_S 0 + +#define SPI_OUTLINK_DSCR_BF1_REG(i) (REG_SPI_BASE(i) + 0x144) +/* SPI_DMA_OUTLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The content of current out descriptor data buffer pointer.*/ +#define SPI_DMA_OUTLINK_DSCR_BF1 0xFFFFFFFF +#define SPI_DMA_OUTLINK_DSCR_BF1_M ((SPI_DMA_OUTLINK_DSCR_BF1_V)<<(SPI_DMA_OUTLINK_DSCR_BF1_S)) +#define SPI_DMA_OUTLINK_DSCR_BF1_V 0xFFFFFFFF +#define SPI_DMA_OUTLINK_DSCR_BF1_S 0 + +#define SPI_DMA_RSTATUS_REG(i) (REG_SPI_BASE(i) + 0x148) +/* SPI_DMA_OUT_STATUS : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: spi dma read data from memory status.*/ +#define SPI_DMA_OUT_STATUS 0xFFFFFFFF +#define SPI_DMA_OUT_STATUS_M ((SPI_DMA_OUT_STATUS_V)<<(SPI_DMA_OUT_STATUS_S)) +#define SPI_DMA_OUT_STATUS_V 0xFFFFFFFF +#define SPI_DMA_OUT_STATUS_S 0 + +#define SPI_DMA_TSTATUS_REG(i) (REG_SPI_BASE(i) + 0x14C) +/* SPI_DMA_IN_STATUS : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: spi dma write data to memory status.*/ +#define SPI_DMA_IN_STATUS 0xFFFFFFFF +#define SPI_DMA_IN_STATUS_M ((SPI_DMA_IN_STATUS_V)<<(SPI_DMA_IN_STATUS_S)) +#define SPI_DMA_IN_STATUS_V 0xFFFFFFFF +#define SPI_DMA_IN_STATUS_S 0 + +#define SPI_DATE_REG(i) (REG_SPI_BASE(i) + 0x3FC) +/* SPI_DATE : RO ;bitpos:[27:0] ;default: 32'h1604270 ; */ +/*description: SPI register version.*/ +#define SPI_DATE 0x0FFFFFFF +#define SPI_DATE_M ((SPI_DATE_V)<<(SPI_DATE_S)) +#define SPI_DATE_V 0xFFFFFFF +#define SPI_DATE_S 0 + + + + +#endif /*__SPI_REG_H__ */ + + diff --git a/tools/sdk/include/esp32/soc/spi_struct.h b/tools/sdk/include/esp32/soc/spi_struct.h new file mode 100644 index 00000000..c7aa29a7 --- /dev/null +++ b/tools/sdk/include/esp32/soc/spi_struct.h @@ -0,0 +1,677 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_SPI_STRUCT_H_ +#define _SOC_SPI_STRUCT_H_ +typedef volatile struct { + union { + struct { + uint32_t reserved0: 16; /*reserved*/ + uint32_t flash_per: 1; /*program erase resume bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t flash_pes: 1; /*program erase suspend bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t usr: 1; /*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t flash_hpm: 1; /*Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t flash_res: 1; /*This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t flash_dp: 1; /*Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t flash_ce: 1; /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t flash_be: 1; /*Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t flash_se: 1; /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t flash_pp: 1; /*Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/ + uint32_t flash_wrsr: 1; /*Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t flash_rdsr: 1; /*Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t flash_rdid: 1; /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ + uint32_t flash_wrdi: 1; /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ + uint32_t flash_wren: 1; /*Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ + uint32_t flash_read: 1; /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ + }; + uint32_t val; + } cmd; + union { + struct { + uint32_t reserved : 8; + uint32_t usr_addr_value:24; /*[31:8]:address to slave [7:0]:Reserved.*/ + }; + uint32_t val; + } addr; + union { + struct { + uint32_t reserved0: 10; /*reserved*/ + uint32_t fcs_crc_en: 1; /*For SPI1 initialize crc32 module before writing encrypted data to flash. Active low.*/ + uint32_t tx_crc_en: 1; /*For SPI1 enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/ + uint32_t wait_flash_idle_en: 1; /*wait flash idle when program flash or erase flash. 1: enable 0: disable.*/ + uint32_t fastrd_mode: 1; /*This bit enable the bits: spi_fread_qio spi_fread_dio spi_fread_qout and spi_fread_dout. 1: enable 0: disable.*/ + uint32_t fread_dual: 1; /*In the read operations read-data phase apply 2 signals. 1: enable 0: disable.*/ + uint32_t resandres: 1; /*The Device ID is read out to SPI_RD_STATUS register, this bit combine with spi_flash_res bit. 1: enable 0: disable.*/ + uint32_t reserved16: 4; /*reserved*/ + uint32_t fread_quad: 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/ + uint32_t wp: 1; /*Write protect signal output when SPI is idle. 1: output high 0: output low.*/ + uint32_t wrsr_2b: 1; /*two bytes data will be written to status register when it is set. 1: enable 0: disable.*/ + uint32_t fread_dio: 1; /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.*/ + uint32_t fread_qio: 1; /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.*/ + uint32_t rd_bit_order: 1; /*In read-data (MISO) phase 1: LSB first 0: MSB first*/ + uint32_t wr_bit_order: 1; /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first*/ + uint32_t reserved27: 5; /*reserved*/ + }; + uint32_t val; + } ctrl; + union { + struct { + uint32_t reserved0: 16; /*reserved*/ + uint32_t cs_hold_delay_res:12; /*Delay cycles of resume Flash when resume Flash is enable by spi clock.*/ + uint32_t cs_hold_delay: 4; /*SPI cs signal is delayed by spi clock cycles*/ + }; + uint32_t val; + } ctrl1; + union { + struct { + uint32_t status: 16; /*In the slave mode, it is the status for master to read out.*/ + uint32_t wb_mode: 8; /*Mode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit.*/ + uint32_t status_ext: 8; /*In the slave mode,it is the status for master to read out.*/ + }; + uint32_t val; + } rd_status; + union { + struct { + uint32_t setup_time: 4; /*(cycles-1) of ,prepare, phase by spi clock, this bits combined with spi_cs_setup bit.*/ + uint32_t hold_time: 4; /*delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit.*/ + uint32_t ck_out_low_mode: 4; /*modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits.*/ + uint32_t ck_out_high_mode: 4; /*modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits.*/ + uint32_t miso_delay_mode: 2; /*MISO signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ + uint32_t miso_delay_num: 3; /*MISO signals are delayed by system clock cycles*/ + uint32_t mosi_delay_mode: 2; /*MOSI signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ + uint32_t mosi_delay_num: 3; /*MOSI signals are delayed by system clock cycles*/ + uint32_t cs_delay_mode: 2; /*spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ + uint32_t cs_delay_num: 4; /*spi_cs signal is delayed by system clock cycles*/ + }; + uint32_t val; + } ctrl2; + union { + struct { + uint32_t clkcnt_l: 6; /*In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0.*/ + uint32_t clkcnt_h: 6; /*In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0.*/ + uint32_t clkcnt_n: 6; /*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)*/ + uint32_t clkdiv_pre: 13; /*In the master mode it is pre-divider of spi_clk.*/ + uint32_t clk_equ_sysclk: 1; /*In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock.*/ + }; + uint32_t val; + } clock; + union { + struct { + uint32_t doutdin: 1; /*Set the bit to enable full duplex communication. 1: enable 0: disable.*/ + uint32_t reserved1: 3; /*reserved*/ + uint32_t cs_hold: 1; /*spi cs keep low when spi is in ,done, phase. 1: enable 0: disable.*/ + uint32_t cs_setup: 1; /*spi cs is enable when spi is in ,prepare, phase. 1: enable 0: disable.*/ + uint32_t ck_i_edge: 1; /*In the slave mode the bit is same as spi_ck_out_edge in master mode. It is combined with spi_miso_delay_mode bits.*/ + uint32_t ck_out_edge: 1; /*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode.*/ + uint32_t reserved8: 2; /*reserved*/ + uint32_t rd_byte_order: 1; /*In read-data (MISO) phase 1: big-endian 0: little_endian*/ + uint32_t wr_byte_order: 1; /*In command address write-data (MOSI) phases 1: big-endian 0: litte_endian*/ + uint32_t fwrite_dual: 1; /*In the write operations read-data phase apply 2 signals*/ + uint32_t fwrite_quad: 1; /*In the write operations read-data phase apply 4 signals*/ + uint32_t fwrite_dio: 1; /*In the write operations address phase and read-data phase apply 2 signals.*/ + uint32_t fwrite_qio: 1; /*In the write operations address phase and read-data phase apply 4 signals.*/ + uint32_t sio: 1; /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable.*/ + uint32_t usr_hold_pol: 1; /*It is combined with hold bits to set the polarity of spi hold line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low*/ + uint32_t usr_dout_hold: 1; /*spi is hold at data out state the bit combined with spi_usr_hold_pol bit.*/ + uint32_t usr_din_hold: 1; /*spi is hold at data in state the bit combined with spi_usr_hold_pol bit.*/ + uint32_t usr_dummy_hold: 1; /*spi is hold at dummy state the bit combined with spi_usr_hold_pol bit.*/ + uint32_t usr_addr_hold: 1; /*spi is hold at address state the bit combined with spi_usr_hold_pol bit.*/ + uint32_t usr_cmd_hold: 1; /*spi is hold at command state the bit combined with spi_usr_hold_pol bit.*/ + uint32_t usr_prep_hold: 1; /*spi is hold at prepare state the bit combined with spi_usr_hold_pol bit.*/ + uint32_t usr_miso_highpart: 1; /*read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.*/ + uint32_t usr_mosi_highpart: 1; /*write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.*/ + uint32_t usr_dummy_idle: 1; /*spi clock is disable in dummy phase when the bit is enable.*/ + uint32_t usr_mosi: 1; /*This bit enable the write-data phase of an operation.*/ + uint32_t usr_miso: 1; /*This bit enable the read-data phase of an operation.*/ + uint32_t usr_dummy: 1; /*This bit enable the dummy phase of an operation.*/ + uint32_t usr_addr: 1; /*This bit enable the address phase of an operation.*/ + uint32_t usr_command: 1; /*This bit enable the command phase of an operation.*/ + }; + uint32_t val; + } user; + union { + struct { + uint32_t usr_dummy_cyclelen: 8; /*The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/ + uint32_t reserved8: 18; /*reserved*/ + uint32_t usr_addr_bitlen: 6; /*The length in bits of address phase. The register value shall be (bit_num-1).*/ + }; + uint32_t val; + } user1; + union { + struct { + uint32_t usr_command_value: 16; /*The value of command.*/ + uint32_t reserved16: 12; /*reserved*/ + uint32_t usr_command_bitlen: 4; /*The length in bits of command phase. The register value shall be (bit_num-1)*/ + }; + uint32_t val; + } user2; + union { + struct { + uint32_t usr_mosi_dbitlen:24; /*The length in bits of write-data. The register value shall be (bit_num-1).*/ + uint32_t reserved24: 8; /*reserved*/ + }; + uint32_t val; + } mosi_dlen; + union { + struct { + uint32_t usr_miso_dbitlen:24; /*The length in bits of read-data. The register value shall be (bit_num-1).*/ + uint32_t reserved24: 8; /*reserved*/ + }; + uint32_t val; + } miso_dlen; + uint32_t slv_wr_status; /*In the slave mode this register are the status register for the master to write into. In the master mode this register are the higher 32bits in the 64 bits address condition.*/ + union { + struct { + uint32_t cs0_dis: 1; /*SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin*/ + uint32_t cs1_dis: 1; /*SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin*/ + uint32_t cs2_dis: 1; /*SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin*/ + uint32_t reserved3: 2; /*reserved*/ + uint32_t ck_dis: 1; /*1: spi clk out disable 0: spi clk out enable*/ + uint32_t master_cs_pol: 5; /*In the master mode the bits are the polarity of spi cs line the value is equivalent to spi_cs ^ spi_master_cs_pol.*/ + uint32_t master_ck_sel: 5; /*In the master mode spi cs line is enable as spi clk it is combined with spi_cs0_dis spi_cs1_dis spi_cs2_dis.*/ + uint32_t reserved16: 13; /*reserved*/ + uint32_t ck_idle_edge: 1; /*1: spi clk line is high when idle 0: spi clk line is low when idle*/ + uint32_t cs_keep_active: 1; /*spi cs line keep low when the bit is set.*/ + uint32_t reserved31: 1; /*reserved*/ + }; + uint32_t val; + } pin; + union { + struct { + uint32_t rd_buf_done: 1; /*The interrupt raw bit for the completion of read-buffer operation in the slave mode.*/ + uint32_t wr_buf_done: 1; /*The interrupt raw bit for the completion of write-buffer operation in the slave mode.*/ + uint32_t rd_sta_done: 1; /*The interrupt raw bit for the completion of read-status operation in the slave mode.*/ + uint32_t wr_sta_done: 1; /*The interrupt raw bit for the completion of write-status operation in the slave mode.*/ + uint32_t trans_done: 1; /*The interrupt raw bit for the completion of any operation in both the master mode and the slave mode.*/ + uint32_t int_en: 5; /*Interrupt enable bits for the below 5 sources*/ + uint32_t cs_i_mode: 2; /*In the slave mode this bits used to synchronize the input spi cs signal and eliminate spi cs jitter.*/ + uint32_t reserved12: 5; /*reserved*/ + uint32_t last_command: 3; /*In the slave mode it is the value of command.*/ + uint32_t last_state: 3; /*In the slave mode it is the state of spi state machine.*/ + uint32_t trans_cnt: 4; /*The operations counter in both the master mode and the slave mode. 4: read-status*/ + uint32_t cmd_define: 1; /*1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as: 1: write-status 2: write-buffer and 3: read-buffer.*/ + uint32_t wr_rd_sta_en: 1; /*write and read status enable in the slave mode*/ + uint32_t wr_rd_buf_en: 1; /*write and read buffer enable in the slave mode*/ + uint32_t slave_mode: 1; /*1: slave mode 0: master mode.*/ + uint32_t sync_reset: 1; /*Software reset enable, reset the spi clock line cs line and data lines.*/ + }; + uint32_t val; + } slave; + union { + struct { + uint32_t rdbuf_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for read-buffer operations.*/ + uint32_t wrbuf_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for write-buffer operations.*/ + uint32_t rdsta_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for read-status operations.*/ + uint32_t wrsta_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for write-status operations.*/ + uint32_t wr_addr_bitlen: 6; /*In the slave mode it is the address length in bits for write-buffer operation. The register value shall be (bit_num-1).*/ + uint32_t rd_addr_bitlen: 6; /*In the slave mode it is the address length in bits for read-buffer operation. The register value shall be (bit_num-1).*/ + uint32_t reserved16: 9; /*reserved*/ + uint32_t status_readback: 1; /*In the slave mode 1:read register of SPI_SLV_WR_STATUS 0: read register of SPI_RD_STATUS.*/ + uint32_t status_fast_en: 1; /*In the slave mode enable fast read status.*/ + uint32_t status_bitlen: 5; /*In the slave mode it is the length of status bit.*/ + }; + uint32_t val; + } slave1; + union { + struct { + uint32_t rdsta_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for read-status operations. The register value shall be (cycle_num-1).*/ + uint32_t wrsta_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for write-status operations. The register value shall be (cycle_num-1).*/ + uint32_t rdbuf_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for read-buffer operations. The register value shall be (cycle_num-1).*/ + uint32_t wrbuf_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for write-buffer operations. The register value shall be (cycle_num-1).*/ + }; + uint32_t val; + } slave2; + union { + struct { + uint32_t rdbuf_cmd_value: 8; /*In the slave mode it is the value of read-buffer command.*/ + uint32_t wrbuf_cmd_value: 8; /*In the slave mode it is the value of write-buffer command.*/ + uint32_t rdsta_cmd_value: 8; /*In the slave mode it is the value of read-status command.*/ + uint32_t wrsta_cmd_value: 8; /*In the slave mode it is the value of write-status command.*/ + }; + uint32_t val; + } slave3; + union { + struct { + uint32_t bit_len: 24; /*In the slave mode it is the length in bits for write-buffer operations. The register value shall be (bit_num-1).*/ + uint32_t reserved24: 8; /*reserved*/ + }; + uint32_t val; + } slv_wrbuf_dlen; + union { + struct { + uint32_t bit_len: 24; /*In the slave mode it is the length in bits for read-buffer operations. The register value shall be (bit_num-1).*/ + uint32_t reserved24: 8; /*reserved*/ + }; + uint32_t val; + } slv_rdbuf_dlen; + union { + struct { + uint32_t req_en: 1; /*For SPI0 Cache access enable 1: enable 0:disable.*/ + uint32_t usr_cmd_4byte: 1; /*For SPI0 cache read flash with 4 bytes command 1: enable 0:disable.*/ + uint32_t flash_usr_cmd: 1; /*For SPI0 cache read flash for user define command 1: enable 0:disable.*/ + uint32_t flash_pes_en: 1; /*For SPI0 spi1 send suspend command before cache read flash 1: enable 0:disable.*/ + uint32_t reserved4: 28; /*reserved*/ + }; + uint32_t val; + } cache_fctrl; + union { + struct { + uint32_t reserved0: 1; /*reserved*/ + uint32_t usr_sram_dio: 1; /*For SPI0 In the spi sram mode spi dual I/O mode enable 1: enable 0:disable*/ + uint32_t usr_sram_qio: 1; /*For SPI0 In the spi sram mode spi quad I/O mode enable 1: enable 0:disable*/ + uint32_t usr_wr_sram_dummy: 1; /*For SPI0 In the spi sram mode it is the enable bit of dummy phase for write operations.*/ + uint32_t usr_rd_sram_dummy: 1; /*For SPI0 In the spi sram mode it is the enable bit of dummy phase for read operations.*/ + uint32_t cache_sram_usr_rcmd: 1; /*For SPI0 In the spi sram mode cache read sram for user define command.*/ + uint32_t sram_bytes_len: 8; /*For SPI0 In the sram mode it is the byte length of spi read sram data.*/ + uint32_t sram_dummy_cyclelen: 8; /*For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).*/ + uint32_t sram_addr_bitlen: 6; /*For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).*/ + uint32_t cache_sram_usr_wcmd: 1; /*For SPI0 In the spi sram mode cache write sram for user define command*/ + uint32_t reserved29: 3; /*reserved*/ + }; + uint32_t val; + } cache_sctrl; + union { + struct { + uint32_t dio: 1; /*For SPI0 SRAM DIO mode enable . SRAM DIO enable command will be send when the bit is set. The bit will be cleared once the operation done.*/ + uint32_t qio: 1; /*For SPI0 SRAM QIO mode enable . SRAM QIO enable command will be send when the bit is set. The bit will be cleared once the operation done.*/ + uint32_t reserved2: 2; /*For SPI0 SRAM write enable . SRAM write operation will be triggered when the bit is set. The bit will be cleared once the operation done.*/ + uint32_t rst_io: 1; /*For SPI0 SRAM IO mode reset enable. SRAM IO mode reset operation will be triggered when the bit is set. The bit will be cleared once the operation done*/ + uint32_t reserved5:27; /*reserved*/ + }; + uint32_t val; + } sram_cmd; + union { + struct { + uint32_t usr_rd_cmd_value: 16; /*For SPI0 When cache mode is enable it is the read command value of command phase for SRAM.*/ + uint32_t reserved16: 12; /*reserved*/ + uint32_t usr_rd_cmd_bitlen: 4; /*For SPI0 When cache mode is enable it is the length in bits of command phase for SRAM. The register value shall be (bit_num-1).*/ + }; + uint32_t val; + } sram_drd_cmd; + union { + struct { + uint32_t usr_wr_cmd_value: 16; /*For SPI0 When cache mode is enable it is the write command value of command phase for SRAM.*/ + uint32_t reserved16: 12; /*reserved*/ + uint32_t usr_wr_cmd_bitlen: 4; /*For SPI0 When cache mode is enable it is the in bits of command phase for SRAM. The register value shall be (bit_num-1).*/ + }; + uint32_t val; + } sram_dwr_cmd; + union { + struct { + uint32_t slv_rdata_bit:24; /*In the slave mode it is the bit length of read data. The value is the length - 1.*/ + uint32_t reserved24: 8; /*reserved*/ + }; + uint32_t val; + } slv_rd_bit; + uint32_t reserved_68; + uint32_t reserved_6c; + uint32_t reserved_70; + uint32_t reserved_74; + uint32_t reserved_78; + uint32_t reserved_7c; + uint32_t data_buf[16]; /*data buffer*/ + uint32_t tx_crc; /*For SPI1 the value of crc32 for 256 bits data.*/ + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t reserved_cc; + uint32_t reserved_d0; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + union { + struct { + uint32_t t_pp_time: 12; /*page program delay time by system clock.*/ + uint32_t reserved12: 4; /*reserved*/ + uint32_t t_pp_shift: 4; /*page program delay time shift .*/ + uint32_t reserved20:11; /*reserved*/ + uint32_t t_pp_ena: 1; /*page program delay enable.*/ + }; + uint32_t val; + } ext0; + union { + struct { + uint32_t t_erase_time: 12; /*erase flash delay time by system clock.*/ + uint32_t reserved12: 4; /*reserved*/ + uint32_t t_erase_shift: 4; /*erase flash delay time shift.*/ + uint32_t reserved20: 11; /*reserved*/ + uint32_t t_erase_ena: 1; /*erase flash delay enable.*/ + }; + uint32_t val; + } ext1; + union { + struct { + uint32_t st: 3; /*The status of spi state machine .*/ + uint32_t reserved3: 29; /*reserved*/ + }; + uint32_t val; + } ext2; + union { + struct { + uint32_t int_hold_ena: 2; /*This register is for two SPI masters to share the same cs clock and data signals. The bits of one SPI are set if the other SPI is busy the SPI will be hold. 1(3): hold at ,idle, phase 2: hold at ,prepare, phase.*/ + uint32_t reserved2: 30; /*reserved*/ + }; + uint32_t val; + } ext3; + union { + struct { + uint32_t reserved0: 2; /*reserved*/ + uint32_t in_rst: 1; /*The bit is used to reset in dma fsm and in data fifo pointer.*/ + uint32_t out_rst: 1; /*The bit is used to reset out dma fsm and out data fifo pointer.*/ + uint32_t ahbm_fifo_rst: 1; /*reset spi dma ahb master fifo pointer.*/ + uint32_t ahbm_rst: 1; /*reset spi dma ahb master.*/ + uint32_t in_loop_test: 1; /*Set bit to test in link.*/ + uint32_t out_loop_test: 1; /*Set bit to test out link.*/ + uint32_t out_auto_wrback: 1; /*when the link is empty jump to next automatically.*/ + uint32_t out_eof_mode: 1; /*out eof flag generation mode . 1: when dma pop all data from fifo 0:when ahb push all data to fifo.*/ + uint32_t outdscr_burst_en: 1; /*read descriptor use burst mode when read data for memory.*/ + uint32_t indscr_burst_en: 1; /*read descriptor use burst mode when write data to memory.*/ + uint32_t out_data_burst_en: 1; /*spi dma read data from memory in burst mode.*/ + uint32_t reserved13: 1; /*reserved*/ + uint32_t dma_rx_stop: 1; /*spi dma read data stop when in continue tx/rx mode.*/ + uint32_t dma_tx_stop: 1; /*spi dma write data stop when in continue tx/rx mode.*/ + uint32_t dma_continue: 1; /*spi dma continue tx/rx data.*/ + uint32_t reserved17: 15; /*reserved*/ + }; + uint32_t val; + } dma_conf; + union { + struct { + uint32_t addr: 20; /*The address of the first outlink descriptor.*/ + uint32_t reserved20: 8; /*reserved*/ + uint32_t stop: 1; /*Set the bit to stop to use outlink descriptor.*/ + uint32_t start: 1; /*Set the bit to start to use outlink descriptor.*/ + uint32_t restart: 1; /*Set the bit to mount on new outlink descriptors.*/ + uint32_t reserved31: 1; /*reserved*/ + }; + uint32_t val; + } dma_out_link; + union { + struct { + uint32_t addr: 20; /*The address of the first inlink descriptor.*/ + uint32_t auto_ret: 1; /*when the bit is set inlink descriptor returns to the next descriptor while a packet is wrong*/ + uint32_t reserved21: 7; /*reserved*/ + uint32_t stop: 1; /*Set the bit to stop to use inlink descriptor.*/ + uint32_t start: 1; /*Set the bit to start to use inlink descriptor.*/ + uint32_t restart: 1; /*Set the bit to mount on new inlink descriptors.*/ + uint32_t reserved31: 1; /*reserved*/ + }; + uint32_t val; + } dma_in_link; + union { + struct { + uint32_t rx_en: 1; /*spi dma read data status bit.*/ + uint32_t tx_en: 1; /*spi dma write data status bit.*/ + uint32_t reserved2: 30; /*spi dma read data from memory count.*/ + }; + uint32_t val; + } dma_status; + union { + struct { + uint32_t inlink_dscr_empty: 1; /*The enable bit for lack of enough inlink descriptors.*/ + uint32_t outlink_dscr_error: 1; /*The enable bit for outlink descriptor error.*/ + uint32_t inlink_dscr_error: 1; /*The enable bit for inlink descriptor error.*/ + uint32_t in_done: 1; /*The enable bit for completing usage of a inlink descriptor.*/ + uint32_t in_err_eof: 1; /*The enable bit for receiving error.*/ + uint32_t in_suc_eof: 1; /*The enable bit for completing receiving all the packets from host.*/ + uint32_t out_done: 1; /*The enable bit for completing usage of a outlink descriptor .*/ + uint32_t out_eof: 1; /*The enable bit for sending a packet to host done.*/ + uint32_t out_total_eof: 1; /*The enable bit for sending all the packets to host done.*/ + uint32_t reserved9: 23; /*reserved*/ + }; + uint32_t val; + } dma_int_ena; + union { + struct { + uint32_t inlink_dscr_empty: 1; /*The raw bit for lack of enough inlink descriptors.*/ + uint32_t outlink_dscr_error: 1; /*The raw bit for outlink descriptor error.*/ + uint32_t inlink_dscr_error: 1; /*The raw bit for inlink descriptor error.*/ + uint32_t in_done: 1; /*The raw bit for completing usage of a inlink descriptor.*/ + uint32_t in_err_eof: 1; /*The raw bit for receiving error.*/ + uint32_t in_suc_eof: 1; /*The raw bit for completing receiving all the packets from host.*/ + uint32_t out_done: 1; /*The raw bit for completing usage of a outlink descriptor.*/ + uint32_t out_eof: 1; /*The raw bit for sending a packet to host done.*/ + uint32_t out_total_eof: 1; /*The raw bit for sending all the packets to host done.*/ + uint32_t reserved9: 23; /*reserved*/ + }; + uint32_t val; + } dma_int_raw; + union { + struct { + uint32_t inlink_dscr_empty: 1; /*The status bit for lack of enough inlink descriptors.*/ + uint32_t outlink_dscr_error: 1; /*The status bit for outlink descriptor error.*/ + uint32_t inlink_dscr_error: 1; /*The status bit for inlink descriptor error.*/ + uint32_t in_done: 1; /*The status bit for completing usage of a inlink descriptor.*/ + uint32_t in_err_eof: 1; /*The status bit for receiving error.*/ + uint32_t in_suc_eof: 1; /*The status bit for completing receiving all the packets from host.*/ + uint32_t out_done: 1; /*The status bit for completing usage of a outlink descriptor.*/ + uint32_t out_eof: 1; /*The status bit for sending a packet to host done.*/ + uint32_t out_total_eof: 1; /*The status bit for sending all the packets to host done.*/ + uint32_t reserved9: 23; /*reserved*/ + }; + uint32_t val; + } dma_int_st; + union { + struct { + uint32_t inlink_dscr_empty: 1; /*The clear bit for lack of enough inlink descriptors.*/ + uint32_t outlink_dscr_error: 1; /*The clear bit for outlink descriptor error.*/ + uint32_t inlink_dscr_error: 1; /*The clear bit for inlink descriptor error.*/ + uint32_t in_done: 1; /*The clear bit for completing usage of a inlink descriptor.*/ + uint32_t in_err_eof: 1; /*The clear bit for receiving error.*/ + uint32_t in_suc_eof: 1; /*The clear bit for completing receiving all the packets from host.*/ + uint32_t out_done: 1; /*The clear bit for completing usage of a outlink descriptor.*/ + uint32_t out_eof: 1; /*The clear bit for sending a packet to host done.*/ + uint32_t out_total_eof: 1; /*The clear bit for sending all the packets to host done.*/ + uint32_t reserved9: 23; /*reserved*/ + }; + uint32_t val; + } dma_int_clr; + uint32_t dma_in_err_eof_des_addr; /*The inlink descriptor address when spi dma produce receiving error.*/ + uint32_t dma_in_suc_eof_des_addr; /*The last inlink descriptor address when spi dma produce from_suc_eof.*/ + uint32_t dma_inlink_dscr; /*The content of current in descriptor pointer.*/ + uint32_t dma_inlink_dscr_bf0; /*The content of next in descriptor pointer.*/ + uint32_t dma_inlink_dscr_bf1; /*The content of current in descriptor data buffer pointer.*/ + uint32_t dma_out_eof_bfr_des_addr; /*The address of buffer relative to the outlink descriptor that produce eof.*/ + uint32_t dma_out_eof_des_addr; /*The last outlink descriptor address when spi dma produce to_eof.*/ + uint32_t dma_outlink_dscr; /*The content of current out descriptor pointer.*/ + uint32_t dma_outlink_dscr_bf0; /*The content of next out descriptor pointer.*/ + uint32_t dma_outlink_dscr_bf1; /*The content of current out descriptor data buffer pointer.*/ + uint32_t dma_rx_status; /*spi dma read data from memory status.*/ + uint32_t dma_tx_status; /*spi dma write data to memory status.*/ + uint32_t reserved_150; + uint32_t reserved_154; + uint32_t reserved_158; + uint32_t reserved_15c; + uint32_t reserved_160; + uint32_t reserved_164; + uint32_t reserved_168; + uint32_t reserved_16c; + uint32_t reserved_170; + uint32_t reserved_174; + uint32_t reserved_178; + uint32_t reserved_17c; + uint32_t reserved_180; + uint32_t reserved_184; + uint32_t reserved_188; + uint32_t reserved_18c; + uint32_t reserved_190; + uint32_t reserved_194; + uint32_t reserved_198; + uint32_t reserved_19c; + uint32_t reserved_1a0; + uint32_t reserved_1a4; + uint32_t reserved_1a8; + uint32_t reserved_1ac; + uint32_t reserved_1b0; + uint32_t reserved_1b4; + uint32_t reserved_1b8; + uint32_t reserved_1bc; + uint32_t reserved_1c0; + uint32_t reserved_1c4; + uint32_t reserved_1c8; + uint32_t reserved_1cc; + uint32_t reserved_1d0; + uint32_t reserved_1d4; + uint32_t reserved_1d8; + uint32_t reserved_1dc; + uint32_t reserved_1e0; + uint32_t reserved_1e4; + uint32_t reserved_1e8; + uint32_t reserved_1ec; + uint32_t reserved_1f0; + uint32_t reserved_1f4; + uint32_t reserved_1f8; + uint32_t reserved_1fc; + uint32_t reserved_200; + uint32_t reserved_204; + uint32_t reserved_208; + uint32_t reserved_20c; + uint32_t reserved_210; + uint32_t reserved_214; + uint32_t reserved_218; + uint32_t reserved_21c; + uint32_t reserved_220; + uint32_t reserved_224; + uint32_t reserved_228; + uint32_t reserved_22c; + uint32_t reserved_230; + uint32_t reserved_234; + uint32_t reserved_238; + uint32_t reserved_23c; + uint32_t reserved_240; + uint32_t reserved_244; + uint32_t reserved_248; + uint32_t reserved_24c; + uint32_t reserved_250; + uint32_t reserved_254; + uint32_t reserved_258; + uint32_t reserved_25c; + uint32_t reserved_260; + uint32_t reserved_264; + uint32_t reserved_268; + uint32_t reserved_26c; + uint32_t reserved_270; + uint32_t reserved_274; + uint32_t reserved_278; + uint32_t reserved_27c; + uint32_t reserved_280; + uint32_t reserved_284; + uint32_t reserved_288; + uint32_t reserved_28c; + uint32_t reserved_290; + uint32_t reserved_294; + uint32_t reserved_298; + uint32_t reserved_29c; + uint32_t reserved_2a0; + uint32_t reserved_2a4; + uint32_t reserved_2a8; + uint32_t reserved_2ac; + uint32_t reserved_2b0; + uint32_t reserved_2b4; + uint32_t reserved_2b8; + uint32_t reserved_2bc; + uint32_t reserved_2c0; + uint32_t reserved_2c4; + uint32_t reserved_2c8; + uint32_t reserved_2cc; + uint32_t reserved_2d0; + uint32_t reserved_2d4; + uint32_t reserved_2d8; + uint32_t reserved_2dc; + uint32_t reserved_2e0; + uint32_t reserved_2e4; + uint32_t reserved_2e8; + uint32_t reserved_2ec; + uint32_t reserved_2f0; + uint32_t reserved_2f4; + uint32_t reserved_2f8; + uint32_t reserved_2fc; + uint32_t reserved_300; + uint32_t reserved_304; + uint32_t reserved_308; + uint32_t reserved_30c; + uint32_t reserved_310; + uint32_t reserved_314; + uint32_t reserved_318; + uint32_t reserved_31c; + uint32_t reserved_320; + uint32_t reserved_324; + uint32_t reserved_328; + uint32_t reserved_32c; + uint32_t reserved_330; + uint32_t reserved_334; + uint32_t reserved_338; + uint32_t reserved_33c; + uint32_t reserved_340; + uint32_t reserved_344; + uint32_t reserved_348; + uint32_t reserved_34c; + uint32_t reserved_350; + uint32_t reserved_354; + uint32_t reserved_358; + uint32_t reserved_35c; + uint32_t reserved_360; + uint32_t reserved_364; + uint32_t reserved_368; + uint32_t reserved_36c; + uint32_t reserved_370; + uint32_t reserved_374; + uint32_t reserved_378; + uint32_t reserved_37c; + uint32_t reserved_380; + uint32_t reserved_384; + uint32_t reserved_388; + uint32_t reserved_38c; + uint32_t reserved_390; + uint32_t reserved_394; + uint32_t reserved_398; + uint32_t reserved_39c; + uint32_t reserved_3a0; + uint32_t reserved_3a4; + uint32_t reserved_3a8; + uint32_t reserved_3ac; + uint32_t reserved_3b0; + uint32_t reserved_3b4; + uint32_t reserved_3b8; + uint32_t reserved_3bc; + uint32_t reserved_3c0; + uint32_t reserved_3c4; + uint32_t reserved_3c8; + uint32_t reserved_3cc; + uint32_t reserved_3d0; + uint32_t reserved_3d4; + uint32_t reserved_3d8; + uint32_t reserved_3dc; + uint32_t reserved_3e0; + uint32_t reserved_3e4; + uint32_t reserved_3e8; + uint32_t reserved_3ec; + uint32_t reserved_3f0; + uint32_t reserved_3f4; + uint32_t reserved_3f8; + union { + struct { + uint32_t date: 28; /*SPI register version.*/ + uint32_t reserved28: 4; /*reserved*/ + }; + uint32_t val; + } date; +} spi_dev_t; +extern spi_dev_t SPI0; /* SPI0 IS FOR INTERNAL USE*/ +extern spi_dev_t SPI1; +extern spi_dev_t SPI2; +extern spi_dev_t SPI3; +#endif /* _SOC_SPI_STRUCT_H_ */ diff --git a/tools/sdk/include/esp32/soc/timer_group_reg.h b/tools/sdk/include/esp32/soc/timer_group_reg.h new file mode 100644 index 00000000..96a5eb79 --- /dev/null +++ b/tools/sdk/include/esp32/soc/timer_group_reg.h @@ -0,0 +1,658 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef __TIMG_REG_H__ +#define __TIMG_REG_H__ +#include "soc.h" + +#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + i*0x1000) +#define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0000) +/* TIMG_T0_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: When set timer 0 time-base counter is enabled*/ +#define TIMG_T0_EN (BIT(31)) +#define TIMG_T0_EN_M (BIT(31)) +#define TIMG_T0_EN_V 0x1 +#define TIMG_T0_EN_S 31 +/* TIMG_T0_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */ +/*description: When set timer 0 time-base counter increment. When cleared timer + 0 time-base counter decrement.*/ +#define TIMG_T0_INCREASE (BIT(30)) +#define TIMG_T0_INCREASE_M (BIT(30)) +#define TIMG_T0_INCREASE_V 0x1 +#define TIMG_T0_INCREASE_S 30 +/* TIMG_T0_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */ +/*description: When set timer 0 auto-reload at alarming is enabled*/ +#define TIMG_T0_AUTORELOAD (BIT(29)) +#define TIMG_T0_AUTORELOAD_M (BIT(29)) +#define TIMG_T0_AUTORELOAD_V 0x1 +#define TIMG_T0_AUTORELOAD_S 29 +/* TIMG_T0_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */ +/*description: Timer 0 clock (T0_clk) prescale value.*/ +#define TIMG_T0_DIVIDER 0x0000FFFF +#define TIMG_T0_DIVIDER_M ((TIMG_T0_DIVIDER_V)<<(TIMG_T0_DIVIDER_S)) +#define TIMG_T0_DIVIDER_V 0xFFFF +#define TIMG_T0_DIVIDER_S 13 +/* TIMG_T0_EDGE_INT_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */ +/*description: When set edge type interrupt will be generated during alarm*/ +#define TIMG_T0_EDGE_INT_EN (BIT(12)) +#define TIMG_T0_EDGE_INT_EN_M (BIT(12)) +#define TIMG_T0_EDGE_INT_EN_V 0x1 +#define TIMG_T0_EDGE_INT_EN_S 12 +/* TIMG_T0_LEVEL_INT_EN : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: When set level type interrupt will be generated during alarm*/ +#define TIMG_T0_LEVEL_INT_EN (BIT(11)) +#define TIMG_T0_LEVEL_INT_EN_M (BIT(11)) +#define TIMG_T0_LEVEL_INT_EN_V 0x1 +#define TIMG_T0_LEVEL_INT_EN_S 11 +/* TIMG_T0_ALARM_EN : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: When set alarm is enabled*/ +#define TIMG_T0_ALARM_EN (BIT(10)) +#define TIMG_T0_ALARM_EN_M (BIT(10)) +#define TIMG_T0_ALARM_EN_V 0x1 +#define TIMG_T0_ALARM_EN_S 10 + +#define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x0004) +/* TIMG_T0_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Register to store timer 0 time-base counter current value lower 32 bits.*/ +#define TIMG_T0_LO 0xFFFFFFFF +#define TIMG_T0_LO_M ((TIMG_T0_LO_V)<<(TIMG_T0_LO_S)) +#define TIMG_T0_LO_V 0xFFFFFFFF +#define TIMG_T0_LO_S 0 + +#define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x0008) +/* TIMG_T0_HI : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Register to store timer 0 time-base counter current value higher 32 bits.*/ +#define TIMG_T0_HI 0xFFFFFFFF +#define TIMG_T0_HI_M ((TIMG_T0_HI_V)<<(TIMG_T0_HI_S)) +#define TIMG_T0_HI_V 0xFFFFFFFF +#define TIMG_T0_HI_S 0 + +#define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x000c) +/* TIMG_T0_UPDATE : WO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Write any value will trigger a timer 0 time-base counter value + update (timer 0 current value will be stored in registers above)*/ +#define TIMG_T0_UPDATE 0xFFFFFFFF +#define TIMG_T0_UPDATE_M ((TIMG_T0_UPDATE_V)<<(TIMG_T0_UPDATE_S)) +#define TIMG_T0_UPDATE_V 0xFFFFFFFF +#define TIMG_T0_UPDATE_S 0 + +#define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0010) +/* TIMG_T0_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Timer 0 time-base counter value lower 32 bits that will trigger the alarm*/ +#define TIMG_T0_ALARM_LO 0xFFFFFFFF +#define TIMG_T0_ALARM_LO_M ((TIMG_T0_ALARM_LO_V)<<(TIMG_T0_ALARM_LO_S)) +#define TIMG_T0_ALARM_LO_V 0xFFFFFFFF +#define TIMG_T0_ALARM_LO_S 0 + +#define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0014) +/* TIMG_T0_ALARM_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Timer 0 time-base counter value higher 32 bits that will trigger the alarm*/ +#define TIMG_T0_ALARM_HI 0xFFFFFFFF +#define TIMG_T0_ALARM_HI_M ((TIMG_T0_ALARM_HI_V)<<(TIMG_T0_ALARM_HI_S)) +#define TIMG_T0_ALARM_HI_V 0xFFFFFFFF +#define TIMG_T0_ALARM_HI_S 0 + +#define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x0018) +/* TIMG_T0_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Lower 32 bits of the value that will load into timer 0 time-base counter*/ +#define TIMG_T0_LOAD_LO 0xFFFFFFFF +#define TIMG_T0_LOAD_LO_M ((TIMG_T0_LOAD_LO_V)<<(TIMG_T0_LOAD_LO_S)) +#define TIMG_T0_LOAD_LO_V 0xFFFFFFFF +#define TIMG_T0_LOAD_LO_S 0 + +#define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x001c) +/* TIMG_T0_LOAD_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: higher 32 bits of the value that will load into timer 0 time-base counter*/ +#define TIMG_T0_LOAD_HI 0xFFFFFFFF +#define TIMG_T0_LOAD_HI_M ((TIMG_T0_LOAD_HI_V)<<(TIMG_T0_LOAD_HI_S)) +#define TIMG_T0_LOAD_HI_V 0xFFFFFFFF +#define TIMG_T0_LOAD_HI_S 0 + +#define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x0020) +/* TIMG_T0_LOAD : WO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Write any value will trigger timer 0 time-base counter reload*/ +#define TIMG_T0_LOAD 0xFFFFFFFF +#define TIMG_T0_LOAD_M ((TIMG_T0_LOAD_V)<<(TIMG_T0_LOAD_S)) +#define TIMG_T0_LOAD_V 0xFFFFFFFF +#define TIMG_T0_LOAD_S 0 + +#define TIMG_T1CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0024) +/* TIMG_T1_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: When set timer 1 time-base counter is enabled*/ +#define TIMG_T1_EN (BIT(31)) +#define TIMG_T1_EN_M (BIT(31)) +#define TIMG_T1_EN_V 0x1 +#define TIMG_T1_EN_S 31 +/* TIMG_T1_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */ +/*description: When set timer 1 time-base counter increment. When cleared timer + 1 time-base counter decrement.*/ +#define TIMG_T1_INCREASE (BIT(30)) +#define TIMG_T1_INCREASE_M (BIT(30)) +#define TIMG_T1_INCREASE_V 0x1 +#define TIMG_T1_INCREASE_S 30 +/* TIMG_T1_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */ +/*description: When set timer 1 auto-reload at alarming is enabled*/ +#define TIMG_T1_AUTORELOAD (BIT(29)) +#define TIMG_T1_AUTORELOAD_M (BIT(29)) +#define TIMG_T1_AUTORELOAD_V 0x1 +#define TIMG_T1_AUTORELOAD_S 29 +/* TIMG_T1_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */ +/*description: Timer 1 clock (T1_clk) prescale value.*/ +#define TIMG_T1_DIVIDER 0x0000FFFF +#define TIMG_T1_DIVIDER_M ((TIMG_T1_DIVIDER_V)<<(TIMG_T1_DIVIDER_S)) +#define TIMG_T1_DIVIDER_V 0xFFFF +#define TIMG_T1_DIVIDER_S 13 +/* TIMG_T1_EDGE_INT_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */ +/*description: When set edge type interrupt will be generated during alarm*/ +#define TIMG_T1_EDGE_INT_EN (BIT(12)) +#define TIMG_T1_EDGE_INT_EN_M (BIT(12)) +#define TIMG_T1_EDGE_INT_EN_V 0x1 +#define TIMG_T1_EDGE_INT_EN_S 12 +/* TIMG_T1_LEVEL_INT_EN : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: When set level type interrupt will be generated during alarm*/ +#define TIMG_T1_LEVEL_INT_EN (BIT(11)) +#define TIMG_T1_LEVEL_INT_EN_M (BIT(11)) +#define TIMG_T1_LEVEL_INT_EN_V 0x1 +#define TIMG_T1_LEVEL_INT_EN_S 11 +/* TIMG_T1_ALARM_EN : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: When set alarm is enabled*/ +#define TIMG_T1_ALARM_EN (BIT(10)) +#define TIMG_T1_ALARM_EN_M (BIT(10)) +#define TIMG_T1_ALARM_EN_V 0x1 +#define TIMG_T1_ALARM_EN_S 10 + +#define TIMG_T1LO_REG(i) (REG_TIMG_BASE(i) + 0x0028) +/* TIMG_T1_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Register to store timer 1 time-base counter current value lower 32 bits.*/ +#define TIMG_T1_LO 0xFFFFFFFF +#define TIMG_T1_LO_M ((TIMG_T1_LO_V)<<(TIMG_T1_LO_S)) +#define TIMG_T1_LO_V 0xFFFFFFFF +#define TIMG_T1_LO_S 0 + +#define TIMG_T1HI_REG(i) (REG_TIMG_BASE(i) + 0x002c) +/* TIMG_T1_HI : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Register to store timer 1 time-base counter current value higher 32 bits.*/ +#define TIMG_T1_HI 0xFFFFFFFF +#define TIMG_T1_HI_M ((TIMG_T1_HI_V)<<(TIMG_T1_HI_S)) +#define TIMG_T1_HI_V 0xFFFFFFFF +#define TIMG_T1_HI_S 0 + +#define TIMG_T1UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x0030) +/* TIMG_T1_UPDATE : WO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Write any value will trigger a timer 1 time-base counter value + update (timer 1 current value will be stored in registers above)*/ +#define TIMG_T1_UPDATE 0xFFFFFFFF +#define TIMG_T1_UPDATE_M ((TIMG_T1_UPDATE_V)<<(TIMG_T1_UPDATE_S)) +#define TIMG_T1_UPDATE_V 0xFFFFFFFF +#define TIMG_T1_UPDATE_S 0 + +#define TIMG_T1ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0034) +/* TIMG_T1_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Timer 1 time-base counter value lower 32 bits that will trigger the alarm*/ +#define TIMG_T1_ALARM_LO 0xFFFFFFFF +#define TIMG_T1_ALARM_LO_M ((TIMG_T1_ALARM_LO_V)<<(TIMG_T1_ALARM_LO_S)) +#define TIMG_T1_ALARM_LO_V 0xFFFFFFFF +#define TIMG_T1_ALARM_LO_S 0 + +#define TIMG_T1ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0038) +/* TIMG_T1_ALARM_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Timer 1 time-base counter value higher 32 bits that will trigger the alarm*/ +#define TIMG_T1_ALARM_HI 0xFFFFFFFF +#define TIMG_T1_ALARM_HI_M ((TIMG_T1_ALARM_HI_V)<<(TIMG_T1_ALARM_HI_S)) +#define TIMG_T1_ALARM_HI_V 0xFFFFFFFF +#define TIMG_T1_ALARM_HI_S 0 + +#define TIMG_T1LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x003c) +/* TIMG_T1_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Lower 32 bits of the value that will load into timer 1 time-base counter*/ +#define TIMG_T1_LOAD_LO 0xFFFFFFFF +#define TIMG_T1_LOAD_LO_M ((TIMG_T1_LOAD_LO_V)<<(TIMG_T1_LOAD_LO_S)) +#define TIMG_T1_LOAD_LO_V 0xFFFFFFFF +#define TIMG_T1_LOAD_LO_S 0 + +#define TIMG_T1LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x0040) +/* TIMG_T1_LOAD_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: higher 32 bits of the value that will load into timer 1 time-base counter*/ +#define TIMG_T1_LOAD_HI 0xFFFFFFFF +#define TIMG_T1_LOAD_HI_M ((TIMG_T1_LOAD_HI_V)<<(TIMG_T1_LOAD_HI_S)) +#define TIMG_T1_LOAD_HI_V 0xFFFFFFFF +#define TIMG_T1_LOAD_HI_S 0 + +#define TIMG_T1LOAD_REG(i) (REG_TIMG_BASE(i) + 0x0044) +/* TIMG_T1_LOAD : WO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Write any value will trigger timer 1 time-base counter reload*/ +#define TIMG_T1_LOAD 0xFFFFFFFF +#define TIMG_T1_LOAD_M ((TIMG_T1_LOAD_V)<<(TIMG_T1_LOAD_S)) +#define TIMG_T1_LOAD_V 0xFFFFFFFF +#define TIMG_T1_LOAD_S 0 + +#define TIMG_WDTCONFIG0_REG(i) (REG_TIMG_BASE(i) + 0x0048) +/* TIMG_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: When set SWDT is enabled*/ +#define TIMG_WDT_EN (BIT(31)) +#define TIMG_WDT_EN_M (BIT(31)) +#define TIMG_WDT_EN_V 0x1 +#define TIMG_WDT_EN_S 31 +/* TIMG_WDT_STG0 : R/W ;bitpos:[30:29] ;default: 1'd0 ; */ +/*description: Stage 0 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ +#define TIMG_WDT_STG0 0x00000003 +#define TIMG_WDT_STG0_M ((TIMG_WDT_STG0_V)<<(TIMG_WDT_STG0_S)) +#define TIMG_WDT_STG0_V 0x3 +#define TIMG_WDT_STG0_S 29 +/* TIMG_WDT_STG1 : R/W ;bitpos:[28:27] ;default: 1'd0 ; */ +/*description: Stage 1 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ +#define TIMG_WDT_STG1 0x00000003 +#define TIMG_WDT_STG1_M ((TIMG_WDT_STG1_V)<<(TIMG_WDT_STG1_S)) +#define TIMG_WDT_STG1_V 0x3 +#define TIMG_WDT_STG1_S 27 +/* TIMG_WDT_STG2 : R/W ;bitpos:[26:25] ;default: 1'd0 ; */ +/*description: Stage 2 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ +#define TIMG_WDT_STG2 0x00000003 +#define TIMG_WDT_STG2_M ((TIMG_WDT_STG2_V)<<(TIMG_WDT_STG2_S)) +#define TIMG_WDT_STG2_V 0x3 +#define TIMG_WDT_STG2_S 25 +/* TIMG_WDT_STG3 : R/W ;bitpos:[24:23] ;default: 1'd0 ; */ +/*description: Stage 3 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ +#define TIMG_WDT_STG3 0x00000003 +#define TIMG_WDT_STG3_M ((TIMG_WDT_STG3_V)<<(TIMG_WDT_STG3_S)) +#define TIMG_WDT_STG3_V 0x3 +#define TIMG_WDT_STG3_S 23 +/* TIMG_WDT_EDGE_INT_EN : R/W ;bitpos:[22] ;default: 1'h0 ; */ +/*description: When set edge type interrupt generation is enabled*/ +#define TIMG_WDT_EDGE_INT_EN (BIT(22)) +#define TIMG_WDT_EDGE_INT_EN_M (BIT(22)) +#define TIMG_WDT_EDGE_INT_EN_V 0x1 +#define TIMG_WDT_EDGE_INT_EN_S 22 +/* TIMG_WDT_LEVEL_INT_EN : R/W ;bitpos:[21] ;default: 1'h0 ; */ +/*description: When set level type interrupt generation is enabled*/ +#define TIMG_WDT_LEVEL_INT_EN (BIT(21)) +#define TIMG_WDT_LEVEL_INT_EN_M (BIT(21)) +#define TIMG_WDT_LEVEL_INT_EN_V 0x1 +#define TIMG_WDT_LEVEL_INT_EN_S 21 +/* TIMG_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[20:18] ;default: 3'h1 ; */ +/*description: length of CPU reset selection. 0: 100ns 1: 200ns 2: 300ns + 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us*/ +#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007 +#define TIMG_WDT_CPU_RESET_LENGTH_M ((TIMG_WDT_CPU_RESET_LENGTH_V)<<(TIMG_WDT_CPU_RESET_LENGTH_S)) +#define TIMG_WDT_CPU_RESET_LENGTH_V 0x7 +#define TIMG_WDT_CPU_RESET_LENGTH_S 18 +/* TIMG_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[17:15] ;default: 3'h1 ; */ +/*description: length of system reset selection. 0: 100ns 1: 200ns 2: 300ns + 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us*/ +#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007 +#define TIMG_WDT_SYS_RESET_LENGTH_M ((TIMG_WDT_SYS_RESET_LENGTH_V)<<(TIMG_WDT_SYS_RESET_LENGTH_S)) +#define TIMG_WDT_SYS_RESET_LENGTH_V 0x7 +#define TIMG_WDT_SYS_RESET_LENGTH_S 15 +/* TIMG_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */ +/*description: When set flash boot protection is enabled*/ +#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14)) +#define TIMG_WDT_FLASHBOOT_MOD_EN_M (BIT(14)) +#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x1 +#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14 + +#define TIMG_WDTCONFIG1_REG(i) (REG_TIMG_BASE(i) + 0x004c) +/* TIMG_WDT_CLK_PRESCALE : R/W ;bitpos:[31:16] ;default: 16'h1 ; */ +/*description: SWDT clock prescale value. Period = 12.5ns * value stored in this register*/ +#define TIMG_WDT_CLK_PRESCALE 0x0000FFFF +#define TIMG_WDT_CLK_PRESCALE_M ((TIMG_WDT_CLK_PRESCALE_V)<<(TIMG_WDT_CLK_PRESCALE_S)) +#define TIMG_WDT_CLK_PRESCALE_V 0xFFFF +#define TIMG_WDT_CLK_PRESCALE_S 16 + +#define TIMG_WDTCONFIG2_REG(i) (REG_TIMG_BASE(i) + 0x0050) +/* TIMG_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd26000000 ; */ +/*description: Stage 0 timeout value in SWDT clock cycles*/ +#define TIMG_WDT_STG0_HOLD 0xFFFFFFFF +#define TIMG_WDT_STG0_HOLD_M ((TIMG_WDT_STG0_HOLD_V)<<(TIMG_WDT_STG0_HOLD_S)) +#define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFF +#define TIMG_WDT_STG0_HOLD_S 0 + +#define TIMG_WDTCONFIG3_REG(i) (REG_TIMG_BASE(i) + 0x0054) +/* TIMG_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'h7ffffff ; */ +/*description: Stage 1 timeout value in SWDT clock cycles*/ +#define TIMG_WDT_STG1_HOLD 0xFFFFFFFF +#define TIMG_WDT_STG1_HOLD_M ((TIMG_WDT_STG1_HOLD_V)<<(TIMG_WDT_STG1_HOLD_S)) +#define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFF +#define TIMG_WDT_STG1_HOLD_S 0 + +#define TIMG_WDTCONFIG4_REG(i) (REG_TIMG_BASE(i) + 0x0058) +/* TIMG_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; */ +/*description: Stage 2 timeout value in SWDT clock cycles*/ +#define TIMG_WDT_STG2_HOLD 0xFFFFFFFF +#define TIMG_WDT_STG2_HOLD_M ((TIMG_WDT_STG2_HOLD_V)<<(TIMG_WDT_STG2_HOLD_S)) +#define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFF +#define TIMG_WDT_STG2_HOLD_S 0 + +#define TIMG_WDTCONFIG5_REG(i) (REG_TIMG_BASE(i) + 0x005c) +/* TIMG_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; */ +/*description: Stage 3 timeout value in SWDT clock cycles*/ +#define TIMG_WDT_STG3_HOLD 0xFFFFFFFF +#define TIMG_WDT_STG3_HOLD_M ((TIMG_WDT_STG3_HOLD_V)<<(TIMG_WDT_STG3_HOLD_S)) +#define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFF +#define TIMG_WDT_STG3_HOLD_S 0 + +#define TIMG_WDTFEED_REG(i) (REG_TIMG_BASE(i) + 0x0060) +/* TIMG_WDT_FEED : WO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Write any value will feed SWDT*/ +#define TIMG_WDT_FEED 0xFFFFFFFF +#define TIMG_WDT_FEED_M ((TIMG_WDT_FEED_V)<<(TIMG_WDT_FEED_S)) +#define TIMG_WDT_FEED_V 0xFFFFFFFF +#define TIMG_WDT_FEED_S 0 + +#define TIMG_WDTWPROTECT_REG(i) (REG_TIMG_BASE(i) + 0x0064) +/* TIMG_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */ +/*description: If change its value from default then write protection is on.*/ +#define TIMG_WDT_WKEY 0xFFFFFFFF +#define TIMG_WDT_WKEY_M ((TIMG_WDT_WKEY_V)<<(TIMG_WDT_WKEY_S)) +#define TIMG_WDT_WKEY_V 0xFFFFFFFF +#define TIMG_WDT_WKEY_S 0 + +#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x0068) +/* TIMG_RTC_CALI_START : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_RTC_CALI_START (BIT(31)) +#define TIMG_RTC_CALI_START_M (BIT(31)) +#define TIMG_RTC_CALI_START_V 0x1 +#define TIMG_RTC_CALI_START_S 31 +/* TIMG_RTC_CALI_MAX : R/W ;bitpos:[30:16] ;default: 15'h1 ; */ +/*description: */ +#define TIMG_RTC_CALI_MAX 0x00007FFF +#define TIMG_RTC_CALI_MAX_M ((TIMG_RTC_CALI_MAX_V)<<(TIMG_RTC_CALI_MAX_S)) +#define TIMG_RTC_CALI_MAX_V 0x7FFF +#define TIMG_RTC_CALI_MAX_S 16 +/* TIMG_RTC_CALI_RDY : RO ;bitpos:[15] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_RTC_CALI_RDY (BIT(15)) +#define TIMG_RTC_CALI_RDY_M (BIT(15)) +#define TIMG_RTC_CALI_RDY_V 0x1 +#define TIMG_RTC_CALI_RDY_S 15 +/* TIMG_RTC_CALI_CLK_SEL : R/W ;bitpos:[14:13] ;default: 2'h1 ; */ +/*description: */ +#define TIMG_RTC_CALI_CLK_SEL 0x00000003 +#define TIMG_RTC_CALI_CLK_SEL_M ((TIMG_RTC_CALI_CLK_SEL_V)<<(TIMG_RTC_CALI_CLK_SEL_S)) +#define TIMG_RTC_CALI_CLK_SEL_V 0x3 +#define TIMG_RTC_CALI_CLK_SEL_S 13 +/* TIMG_RTC_CALI_START_CYCLING : R/W ;bitpos:[12] ;default: 1'd1 ; */ +/*description: */ +#define TIMG_RTC_CALI_START_CYCLING (BIT(12)) +#define TIMG_RTC_CALI_START_CYCLING_M (BIT(12)) +#define TIMG_RTC_CALI_START_CYCLING_V 0x1 +#define TIMG_RTC_CALI_START_CYCLING_S 12 + +#define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x006c) +/* TIMG_RTC_CALI_VALUE : RO ;bitpos:[31:7] ;default: 25'h0 ; */ +/*description: */ +#define TIMG_RTC_CALI_VALUE 0x01FFFFFF +#define TIMG_RTC_CALI_VALUE_M ((TIMG_RTC_CALI_VALUE_V)<<(TIMG_RTC_CALI_VALUE_S)) +#define TIMG_RTC_CALI_VALUE_V 0x1FFFFFF +#define TIMG_RTC_CALI_VALUE_S 7 + +#define TIMG_LACTCONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0070) +/* TIMG_LACT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_LACT_EN (BIT(31)) +#define TIMG_LACT_EN_M (BIT(31)) +#define TIMG_LACT_EN_V 0x1 +#define TIMG_LACT_EN_S 31 +/* TIMG_LACT_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */ +/*description: */ +#define TIMG_LACT_INCREASE (BIT(30)) +#define TIMG_LACT_INCREASE_M (BIT(30)) +#define TIMG_LACT_INCREASE_V 0x1 +#define TIMG_LACT_INCREASE_S 30 +/* TIMG_LACT_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */ +/*description: */ +#define TIMG_LACT_AUTORELOAD (BIT(29)) +#define TIMG_LACT_AUTORELOAD_M (BIT(29)) +#define TIMG_LACT_AUTORELOAD_V 0x1 +#define TIMG_LACT_AUTORELOAD_S 29 +/* TIMG_LACT_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */ +/*description: */ +#define TIMG_LACT_DIVIDER 0x0000FFFF +#define TIMG_LACT_DIVIDER_M ((TIMG_LACT_DIVIDER_V)<<(TIMG_LACT_DIVIDER_S)) +#define TIMG_LACT_DIVIDER_V 0xFFFF +#define TIMG_LACT_DIVIDER_S 13 +/* TIMG_LACT_EDGE_INT_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_LACT_EDGE_INT_EN (BIT(12)) +#define TIMG_LACT_EDGE_INT_EN_M (BIT(12)) +#define TIMG_LACT_EDGE_INT_EN_V 0x1 +#define TIMG_LACT_EDGE_INT_EN_S 12 +/* TIMG_LACT_LEVEL_INT_EN : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_LACT_LEVEL_INT_EN (BIT(11)) +#define TIMG_LACT_LEVEL_INT_EN_M (BIT(11)) +#define TIMG_LACT_LEVEL_INT_EN_V 0x1 +#define TIMG_LACT_LEVEL_INT_EN_S 11 +/* TIMG_LACT_ALARM_EN : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_LACT_ALARM_EN (BIT(10)) +#define TIMG_LACT_ALARM_EN_M (BIT(10)) +#define TIMG_LACT_ALARM_EN_V 0x1 +#define TIMG_LACT_ALARM_EN_S 10 +/* TIMG_LACT_LAC_EN : R/W ;bitpos:[9] ;default: 1'h1 ; */ +/*description: */ +#define TIMG_LACT_LAC_EN (BIT(9)) +#define TIMG_LACT_LAC_EN_M (BIT(9)) +#define TIMG_LACT_LAC_EN_V 0x1 +#define TIMG_LACT_LAC_EN_S 9 +/* TIMG_LACT_CPST_EN : R/W ;bitpos:[8] ;default: 1'h1 ; */ +/*description: */ +#define TIMG_LACT_CPST_EN (BIT(8)) +#define TIMG_LACT_CPST_EN_M (BIT(8)) +#define TIMG_LACT_CPST_EN_V 0x1 +#define TIMG_LACT_CPST_EN_S 8 +/* TIMG_LACT_RTC_ONLY : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_LACT_RTC_ONLY (BIT(7)) +#define TIMG_LACT_RTC_ONLY_M (BIT(7)) +#define TIMG_LACT_RTC_ONLY_V 0x1 +#define TIMG_LACT_RTC_ONLY_S 7 + +#define TIMG_LACTRTC_REG(i) (REG_TIMG_BASE(i) + 0x0074) +/* TIMG_LACT_RTC_STEP_LEN : R/W ;bitpos:[31:6] ;default: 26'h0 ; */ +/*description: */ +#define TIMG_LACT_RTC_STEP_LEN 0x03FFFFFF +#define TIMG_LACT_RTC_STEP_LEN_M ((TIMG_LACT_RTC_STEP_LEN_V)<<(TIMG_LACT_RTC_STEP_LEN_S)) +#define TIMG_LACT_RTC_STEP_LEN_V 0x3FFFFFF +#define TIMG_LACT_RTC_STEP_LEN_S 6 + +#define TIMG_LACTLO_REG(i) (REG_TIMG_BASE(i) + 0x0078) +/* TIMG_LACT_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define TIMG_LACT_LO 0xFFFFFFFF +#define TIMG_LACT_LO_M ((TIMG_LACT_LO_V)<<(TIMG_LACT_LO_S)) +#define TIMG_LACT_LO_V 0xFFFFFFFF +#define TIMG_LACT_LO_S 0 + +#define TIMG_LACTHI_REG(i) (REG_TIMG_BASE(i) + 0x007c) +/* TIMG_LACT_HI : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define TIMG_LACT_HI 0xFFFFFFFF +#define TIMG_LACT_HI_M ((TIMG_LACT_HI_V)<<(TIMG_LACT_HI_S)) +#define TIMG_LACT_HI_V 0xFFFFFFFF +#define TIMG_LACT_HI_S 0 + +#define TIMG_LACTUPDATE_REG(i) (REG_TIMG_BASE(i) + 0x0080) +/* TIMG_LACT_UPDATE : WO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define TIMG_LACT_UPDATE 0xFFFFFFFF +#define TIMG_LACT_UPDATE_M ((TIMG_LACT_UPDATE_V)<<(TIMG_LACT_UPDATE_S)) +#define TIMG_LACT_UPDATE_V 0xFFFFFFFF +#define TIMG_LACT_UPDATE_S 0 + +#define TIMG_LACTALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0084) +/* TIMG_LACT_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define TIMG_LACT_ALARM_LO 0xFFFFFFFF +#define TIMG_LACT_ALARM_LO_M ((TIMG_LACT_ALARM_LO_V)<<(TIMG_LACT_ALARM_LO_S)) +#define TIMG_LACT_ALARM_LO_V 0xFFFFFFFF +#define TIMG_LACT_ALARM_LO_S 0 + +#define TIMG_LACTALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0088) +/* TIMG_LACT_ALARM_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define TIMG_LACT_ALARM_HI 0xFFFFFFFF +#define TIMG_LACT_ALARM_HI_M ((TIMG_LACT_ALARM_HI_V)<<(TIMG_LACT_ALARM_HI_S)) +#define TIMG_LACT_ALARM_HI_V 0xFFFFFFFF +#define TIMG_LACT_ALARM_HI_S 0 + +#define TIMG_LACTLOADLO_REG(i) (REG_TIMG_BASE(i) + 0x008c) +/* TIMG_LACT_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define TIMG_LACT_LOAD_LO 0xFFFFFFFF +#define TIMG_LACT_LOAD_LO_M ((TIMG_LACT_LOAD_LO_V)<<(TIMG_LACT_LOAD_LO_S)) +#define TIMG_LACT_LOAD_LO_V 0xFFFFFFFF +#define TIMG_LACT_LOAD_LO_S 0 + +#define TIMG_LACTLOADHI_REG(i) (REG_TIMG_BASE(i) + 0x0090) +/* TIMG_LACT_LOAD_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define TIMG_LACT_LOAD_HI 0xFFFFFFFF +#define TIMG_LACT_LOAD_HI_M ((TIMG_LACT_LOAD_HI_V)<<(TIMG_LACT_LOAD_HI_S)) +#define TIMG_LACT_LOAD_HI_V 0xFFFFFFFF +#define TIMG_LACT_LOAD_HI_S 0 + +#define TIMG_LACTLOAD_REG(i) (REG_TIMG_BASE(i) + 0x0094) +/* TIMG_LACT_LOAD : WO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define TIMG_LACT_LOAD 0xFFFFFFFF +#define TIMG_LACT_LOAD_M ((TIMG_LACT_LOAD_V)<<(TIMG_LACT_LOAD_S)) +#define TIMG_LACT_LOAD_V 0xFFFFFFFF +#define TIMG_LACT_LOAD_S 0 + +#define TIMG_INT_ENA_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x0098) +/* TIMG_LACT_INT_ENA : R/W ;bitpos:[3] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_LACT_INT_ENA (BIT(3)) +#define TIMG_LACT_INT_ENA_M (BIT(3)) +#define TIMG_LACT_INT_ENA_V 0x1 +#define TIMG_LACT_INT_ENA_S 3 +/* TIMG_WDT_INT_ENA : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Interrupt when an interrupt stage timeout*/ +#define TIMG_WDT_INT_ENA (BIT(2)) +#define TIMG_WDT_INT_ENA_M (BIT(2)) +#define TIMG_WDT_INT_ENA_V 0x1 +#define TIMG_WDT_INT_ENA_S 2 +/* TIMG_T1_INT_ENA : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: interrupt when timer1 alarm*/ +#define TIMG_T1_INT_ENA (BIT(1)) +#define TIMG_T1_INT_ENA_M (BIT(1)) +#define TIMG_T1_INT_ENA_V 0x1 +#define TIMG_T1_INT_ENA_S 1 +/* TIMG_T0_INT_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: interrupt when timer0 alarm*/ +#define TIMG_T0_INT_ENA (BIT(0)) +#define TIMG_T0_INT_ENA_M (BIT(0)) +#define TIMG_T0_INT_ENA_V 0x1 +#define TIMG_T0_INT_ENA_S 0 + +#define TIMG_INT_RAW_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x009c) +/* TIMG_LACT_INT_RAW : RO ;bitpos:[3] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_LACT_INT_RAW (BIT(3)) +#define TIMG_LACT_INT_RAW_M (BIT(3)) +#define TIMG_LACT_INT_RAW_V 0x1 +#define TIMG_LACT_INT_RAW_S 3 +/* TIMG_WDT_INT_RAW : RO ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Interrupt when an interrupt stage timeout*/ +#define TIMG_WDT_INT_RAW (BIT(2)) +#define TIMG_WDT_INT_RAW_M (BIT(2)) +#define TIMG_WDT_INT_RAW_V 0x1 +#define TIMG_WDT_INT_RAW_S 2 +/* TIMG_T1_INT_RAW : RO ;bitpos:[1] ;default: 1'h0 ; */ +/*description: interrupt when timer1 alarm*/ +#define TIMG_T1_INT_RAW (BIT(1)) +#define TIMG_T1_INT_RAW_M (BIT(1)) +#define TIMG_T1_INT_RAW_V 0x1 +#define TIMG_T1_INT_RAW_S 1 +/* TIMG_T0_INT_RAW : RO ;bitpos:[0] ;default: 1'h0 ; */ +/*description: interrupt when timer0 alarm*/ +#define TIMG_T0_INT_RAW (BIT(0)) +#define TIMG_T0_INT_RAW_M (BIT(0)) +#define TIMG_T0_INT_RAW_V 0x1 +#define TIMG_T0_INT_RAW_S 0 + +#define TIMG_INT_ST_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x00a0) +/* TIMG_LACT_INT_ST : RO ;bitpos:[3] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_LACT_INT_ST (BIT(3)) +#define TIMG_LACT_INT_ST_M (BIT(3)) +#define TIMG_LACT_INT_ST_V 0x1 +#define TIMG_LACT_INT_ST_S 3 +/* TIMG_WDT_INT_ST : RO ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Interrupt when an interrupt stage timeout*/ +#define TIMG_WDT_INT_ST (BIT(2)) +#define TIMG_WDT_INT_ST_M (BIT(2)) +#define TIMG_WDT_INT_ST_V 0x1 +#define TIMG_WDT_INT_ST_S 2 +/* TIMG_T1_INT_ST : RO ;bitpos:[1] ;default: 1'h0 ; */ +/*description: interrupt when timer1 alarm*/ +#define TIMG_T1_INT_ST (BIT(1)) +#define TIMG_T1_INT_ST_M (BIT(1)) +#define TIMG_T1_INT_ST_V 0x1 +#define TIMG_T1_INT_ST_S 1 +/* TIMG_T0_INT_ST : RO ;bitpos:[0] ;default: 1'h0 ; */ +/*description: interrupt when timer0 alarm*/ +#define TIMG_T0_INT_ST (BIT(0)) +#define TIMG_T0_INT_ST_M (BIT(0)) +#define TIMG_T0_INT_ST_V 0x1 +#define TIMG_T0_INT_ST_S 0 + +#define TIMG_INT_CLR_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x00a4) +/* TIMG_LACT_INT_CLR : WO ;bitpos:[3] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_LACT_INT_CLR (BIT(3)) +#define TIMG_LACT_INT_CLR_M (BIT(3)) +#define TIMG_LACT_INT_CLR_V 0x1 +#define TIMG_LACT_INT_CLR_S 3 +/* TIMG_WDT_INT_CLR : WO ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Interrupt when an interrupt stage timeout*/ +#define TIMG_WDT_INT_CLR (BIT(2)) +#define TIMG_WDT_INT_CLR_M (BIT(2)) +#define TIMG_WDT_INT_CLR_V 0x1 +#define TIMG_WDT_INT_CLR_S 2 +/* TIMG_T1_INT_CLR : WO ;bitpos:[1] ;default: 1'h0 ; */ +/*description: interrupt when timer1 alarm*/ +#define TIMG_T1_INT_CLR (BIT(1)) +#define TIMG_T1_INT_CLR_M (BIT(1)) +#define TIMG_T1_INT_CLR_V 0x1 +#define TIMG_T1_INT_CLR_S 1 +/* TIMG_T0_INT_CLR : WO ;bitpos:[0] ;default: 1'h0 ; */ +/*description: interrupt when timer0 alarm*/ +#define TIMG_T0_INT_CLR (BIT(0)) +#define TIMG_T0_INT_CLR_M (BIT(0)) +#define TIMG_T0_INT_CLR_V 0x1 +#define TIMG_T0_INT_CLR_S 0 + +#define TIMG_NTIMERS_DATE_REG(i) (REG_TIMG_BASE(i) + 0x00f8) +/* TIMG_NTIMERS_DATE : R/W ;bitpos:[27:0] ;default: 28'h1604290 ; */ +/*description: Version of this regfile*/ +#define TIMG_NTIMERS_DATE 0x0FFFFFFF +#define TIMG_NTIMERS_DATE_M ((TIMG_NTIMERS_DATE_V)<<(TIMG_NTIMERS_DATE_S)) +#define TIMG_NTIMERS_DATE_V 0xFFFFFFF +#define TIMG_NTIMERS_DATE_S 0 + +#define TIMGCLK_REG(i) (REG_TIMG_BASE(i) + 0x00fc) +/* TIMG_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: Force clock enable for this regfile*/ +#define TIMG_CLK_EN (BIT(31)) +#define TIMG_CLK_EN_M (BIT(31)) +#define TIMG_CLK_EN_V 0x1 +#define TIMG_CLK_EN_S 31 + + + + +#endif /*__TIMG_REG_H__ */ + + diff --git a/tools/sdk/include/esp32/soc/timer_group_struct.h b/tools/sdk/include/esp32/soc/timer_group_struct.h new file mode 100644 index 00000000..696b439d --- /dev/null +++ b/tools/sdk/include/esp32/soc/timer_group_struct.h @@ -0,0 +1,195 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_TIMG_STRUCT_H_ +#define _SOC_TIMG_STRUCT_H_ +typedef volatile struct { + struct{ + union { + struct { + uint32_t reserved0: 10; + uint32_t alarm_en: 1; /*When set alarm is enabled*/ + uint32_t level_int_en: 1; /*When set level type interrupt will be generated during alarm*/ + uint32_t edge_int_en: 1; /*When set edge type interrupt will be generated during alarm*/ + uint32_t divider: 16; /*Timer clock (T0/1_clk) pre-scale value.*/ + uint32_t autoreload: 1; /*When set timer 0/1 auto-reload at alarming is enabled*/ + uint32_t increase: 1; /*When set timer 0/1 time-base counter increment. When cleared timer 0 time-base counter decrement.*/ + uint32_t enable: 1; /*When set timer 0/1 time-base counter is enabled*/ + }; + uint32_t val; + } config; + uint32_t cnt_low; /*Register to store timer 0/1 time-base counter current value lower 32 bits.*/ + uint32_t cnt_high; /*Register to store timer 0 time-base counter current value higher 32 bits.*/ + uint32_t update; /*Write any value will trigger a timer 0 time-base counter value update (timer 0 current value will be stored in registers above)*/ + uint32_t alarm_low; /*Timer 0 time-base counter value lower 32 bits that will trigger the alarm*/ + uint32_t alarm_high; /*Timer 0 time-base counter value higher 32 bits that will trigger the alarm*/ + uint32_t load_low; /*Lower 32 bits of the value that will load into timer 0 time-base counter*/ + uint32_t load_high; /*higher 32 bits of the value that will load into timer 0 time-base counter*/ + uint32_t reload; /*Write any value will trigger timer 0 time-base counter reload*/ + } hw_timer[2]; + union { + struct { + uint32_t reserved0: 14; + uint32_t flashboot_mod_en: 1; /*When set flash boot protection is enabled*/ + uint32_t sys_reset_length: 3; /*length of system reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us*/ + uint32_t cpu_reset_length: 3; /*length of CPU reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us*/ + uint32_t level_int_en: 1; /*When set level type interrupt generation is enabled*/ + uint32_t edge_int_en: 1; /*When set edge type interrupt generation is enabled*/ + uint32_t stg3: 2; /*Stage 3 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ + uint32_t stg2: 2; /*Stage 2 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ + uint32_t stg1: 2; /*Stage 1 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ + uint32_t stg0: 2; /*Stage 0 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ + uint32_t en: 1; /*When set SWDT is enabled*/ + }; + uint32_t val; + } wdt_config0; + union { + struct { + uint32_t reserved0: 16; + uint32_t clk_prescale:16; /*SWDT clock prescale value. Period = 12.5ns * value stored in this register*/ + }; + uint32_t val; + } wdt_config1; + uint32_t wdt_config2; /*Stage 0 timeout value in SWDT clock cycles*/ + uint32_t wdt_config3; /*Stage 1 timeout value in SWDT clock cycles*/ + uint32_t wdt_config4; /*Stage 2 timeout value in SWDT clock cycles*/ + uint32_t wdt_config5; /*Stage 3 timeout value in SWDT clock cycles*/ + uint32_t wdt_feed; /*Write any value will feed SWDT*/ + uint32_t wdt_wprotect; /*If change its value from default then write protection is on.*/ + union { + struct { + uint32_t reserved0: 12; + uint32_t start_cycling: 1; + uint32_t clk_sel: 2; + uint32_t rdy: 1; + uint32_t max: 15; + uint32_t start: 1; + }; + uint32_t val; + } rtc_cali_cfg; + union { + struct { + uint32_t reserved0: 7; + uint32_t value:25; + }; + uint32_t val; + } rtc_cali_cfg1; + union { + struct { + uint32_t reserved0: 7; + uint32_t rtc_only: 1; + uint32_t cpst_en: 1; + uint32_t lac_en: 1; + uint32_t alarm_en: 1; + uint32_t level_int_en: 1; + uint32_t edge_int_en: 1; + uint32_t divider: 16; + uint32_t autoreload: 1; + uint32_t increase: 1; + uint32_t en: 1; + }; + uint32_t val; + } lactconfig; + union { + struct { + uint32_t reserved0: 6; + uint32_t step_len:26; + }; + uint32_t val; + } lactrtc; + uint32_t lactlo; /**/ + uint32_t lacthi; /**/ + uint32_t lactupdate; /**/ + uint32_t lactalarmlo; /**/ + uint32_t lactalarmhi; /**/ + uint32_t lactloadlo; /**/ + uint32_t lactloadhi; /**/ + uint32_t lactload; /**/ + union { + struct { + uint32_t t0: 1; /*interrupt when timer0 alarm*/ + uint32_t t1: 1; /*interrupt when timer1 alarm*/ + uint32_t wdt: 1; /*Interrupt when an interrupt stage timeout*/ + uint32_t lact: 1; + uint32_t reserved4: 28; + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t t0: 1; /*interrupt when timer0 alarm*/ + uint32_t t1: 1; /*interrupt when timer1 alarm*/ + uint32_t wdt: 1; /*Interrupt when an interrupt stage timeout*/ + uint32_t lact: 1; + uint32_t reserved4:28; + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t t0: 1; /*interrupt when timer0 alarm*/ + uint32_t t1: 1; /*interrupt when timer1 alarm*/ + uint32_t wdt: 1; /*Interrupt when an interrupt stage timeout*/ + uint32_t lact: 1; + uint32_t reserved4: 28; + }; + uint32_t val; + } int_st_timers; + union { + struct { + uint32_t t0: 1; /*interrupt when timer0 alarm*/ + uint32_t t1: 1; /*interrupt when timer1 alarm*/ + uint32_t wdt: 1; /*Interrupt when an interrupt stage timeout*/ + uint32_t lact: 1; + uint32_t reserved4: 28; + }; + uint32_t val; + } int_clr_timers; + uint32_t reserved_a8; + uint32_t reserved_ac; + uint32_t reserved_b0; + uint32_t reserved_b4; + uint32_t reserved_b8; + uint32_t reserved_bc; + uint32_t reserved_c0; + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t reserved_cc; + uint32_t reserved_d0; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + union { + struct { + uint32_t date:28; /*Version of this regfile*/ + uint32_t reserved28: 4; + }; + uint32_t val; + } timg_date; + union { + struct { + uint32_t reserved0: 31; + uint32_t en: 1; /*Force clock enable for this regfile*/ + }; + uint32_t val; + } clk; +} timg_dev_t; +extern timg_dev_t TIMERG0; +extern timg_dev_t TIMERG1; +#endif /* _SOC_TIMG_STRUCT_H_ */ diff --git a/tools/sdk/include/esp32/soc/uart_reg.h b/tools/sdk/include/esp32/soc/uart_reg.h new file mode 100644 index 00000000..155700b2 --- /dev/null +++ b/tools/sdk/include/esp32/soc/uart_reg.h @@ -0,0 +1,1165 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef __UART_REG_H__ +#define __UART_REG_H__ + + +#include "soc.h" + +#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ( i > 1 ? 0xe000 : 0 ) ) + +#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0) +/* UART_RXFIFO_RD_BYTE : RO ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: This register stores one byte data read by rx fifo.*/ +#define UART_RXFIFO_RD_BYTE 0x000000FF +#define UART_RXFIFO_RD_BYTE_M ((UART_RXFIFO_RD_BYTE_V)<<(UART_RXFIFO_RD_BYTE_S)) +#define UART_RXFIFO_RD_BYTE_V 0xFF +#define UART_RXFIFO_RD_BYTE_S 0 + +#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4) +/* UART_AT_CMD_CHAR_DET_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects + the configured at_cmd chars.*/ +#define UART_AT_CMD_CHAR_DET_INT_RAW (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_RAW_M (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_RAW_V 0x1 +#define UART_AT_CMD_CHAR_DET_INT_RAW_S 18 +/* UART_RS485_CLASH_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when rs485 detects + the clash between transmitter and receiver.*/ +#define UART_RS485_CLASH_INT_RAW (BIT(17)) +#define UART_RS485_CLASH_INT_RAW_M (BIT(17)) +#define UART_RS485_CLASH_INT_RAW_V 0x1 +#define UART_RS485_CLASH_INT_RAW_S 17 +/* UART_RS485_FRM_ERR_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when rs485 detects + the data frame error.*/ +#define UART_RS485_FRM_ERR_INT_RAW (BIT(16)) +#define UART_RS485_FRM_ERR_INT_RAW_M (BIT(16)) +#define UART_RS485_FRM_ERR_INT_RAW_V 0x1 +#define UART_RS485_FRM_ERR_INT_RAW_S 16 +/* UART_RS485_PARITY_ERR_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when rs485 detects the parity error.*/ +#define UART_RS485_PARITY_ERR_INT_RAW (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_RAW_M (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_RAW_V 0x1 +#define UART_RS485_PARITY_ERR_INT_RAW_S 15 +/* UART_TX_DONE_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when transmitter has + send all the data in fifo.*/ +#define UART_TX_DONE_INT_RAW (BIT(14)) +#define UART_TX_DONE_INT_RAW_M (BIT(14)) +#define UART_TX_DONE_INT_RAW_V 0x1 +#define UART_TX_DONE_INT_RAW_S 14 +/* UART_TX_BRK_IDLE_DONE_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when transmitter has + kept the shortest duration after the last data has been send.*/ +#define UART_TX_BRK_IDLE_DONE_INT_RAW (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_RAW_M (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_RAW_V 0x1 +#define UART_TX_BRK_IDLE_DONE_INT_RAW_S 13 +/* UART_TX_BRK_DONE_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when transmitter completes + sendding 0 after all the datas in transmitter's fifo are send.*/ +#define UART_TX_BRK_DONE_INT_RAW (BIT(12)) +#define UART_TX_BRK_DONE_INT_RAW_M (BIT(12)) +#define UART_TX_BRK_DONE_INT_RAW_V 0x1 +#define UART_TX_BRK_DONE_INT_RAW_S 12 +/* UART_GLITCH_DET_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects the start bit.*/ +#define UART_GLITCH_DET_INT_RAW (BIT(11)) +#define UART_GLITCH_DET_INT_RAW_M (BIT(11)) +#define UART_GLITCH_DET_INT_RAW_V 0x1 +#define UART_GLITCH_DET_INT_RAW_S 11 +/* UART_SW_XOFF_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver receives + xon char with uart_sw_flow_con_en is set to 1.*/ +#define UART_SW_XOFF_INT_RAW (BIT(10)) +#define UART_SW_XOFF_INT_RAW_M (BIT(10)) +#define UART_SW_XOFF_INT_RAW_V 0x1 +#define UART_SW_XOFF_INT_RAW_S 10 +/* UART_SW_XON_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver receives + xoff char with uart_sw_flow_con_en is set to 1.*/ +#define UART_SW_XON_INT_RAW (BIT(9)) +#define UART_SW_XON_INT_RAW_M (BIT(9)) +#define UART_SW_XON_INT_RAW_V 0x1 +#define UART_SW_XON_INT_RAW_S 9 +/* UART_RXFIFO_TOUT_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver takes + more time than rx_tout_thrhd to receive a byte.*/ +#define UART_RXFIFO_TOUT_INT_RAW (BIT(8)) +#define UART_RXFIFO_TOUT_INT_RAW_M (BIT(8)) +#define UART_RXFIFO_TOUT_INT_RAW_V 0x1 +#define UART_RXFIFO_TOUT_INT_RAW_S 8 +/* UART_BRK_DET_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects + the 0 after the stop bit.*/ +#define UART_BRK_DET_INT_RAW (BIT(7)) +#define UART_BRK_DET_INT_RAW_M (BIT(7)) +#define UART_BRK_DET_INT_RAW_V 0x1 +#define UART_BRK_DET_INT_RAW_S 7 +/* UART_CTS_CHG_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects + the edge change of ctsn signal.*/ +#define UART_CTS_CHG_INT_RAW (BIT(6)) +#define UART_CTS_CHG_INT_RAW_M (BIT(6)) +#define UART_CTS_CHG_INT_RAW_V 0x1 +#define UART_CTS_CHG_INT_RAW_S 6 +/* UART_DSR_CHG_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects + the edge change of dsrn signal.*/ +#define UART_DSR_CHG_INT_RAW (BIT(5)) +#define UART_DSR_CHG_INT_RAW_M (BIT(5)) +#define UART_DSR_CHG_INT_RAW_V 0x1 +#define UART_DSR_CHG_INT_RAW_S 5 +/* UART_RXFIFO_OVF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver receives + more data than the fifo can store.*/ +#define UART_RXFIFO_OVF_INT_RAW (BIT(4)) +#define UART_RXFIFO_OVF_INT_RAW_M (BIT(4)) +#define UART_RXFIFO_OVF_INT_RAW_V 0x1 +#define UART_RXFIFO_OVF_INT_RAW_S 4 +/* UART_FRM_ERR_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects + data's frame error .*/ +#define UART_FRM_ERR_INT_RAW (BIT(3)) +#define UART_FRM_ERR_INT_RAW_M (BIT(3)) +#define UART_FRM_ERR_INT_RAW_V 0x1 +#define UART_FRM_ERR_INT_RAW_S 3 +/* UART_PARITY_ERR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects + the parity error of data.*/ +#define UART_PARITY_ERR_INT_RAW (BIT(2)) +#define UART_PARITY_ERR_INT_RAW_M (BIT(2)) +#define UART_PARITY_ERR_INT_RAW_V 0x1 +#define UART_PARITY_ERR_INT_RAW_S 2 +/* UART_TXFIFO_EMPTY_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when the amount of + data in transmitter's fifo is less than ((tx_mem_cnttxfifo_cnt) .*/ +#define UART_TXFIFO_EMPTY_INT_RAW (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_RAW_M (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_RAW_V 0x1 +#define UART_TXFIFO_EMPTY_INT_RAW_S 1 +/* UART_RXFIFO_FULL_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver receives + more data than (rx_flow_thrhd_h3 rx_flow_thrhd).*/ +#define UART_RXFIFO_FULL_INT_RAW (BIT(0)) +#define UART_RXFIFO_FULL_INT_RAW_M (BIT(0)) +#define UART_RXFIFO_FULL_INT_RAW_V 0x1 +#define UART_RXFIFO_FULL_INT_RAW_S 0 + +#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8) +/* UART_AT_CMD_CHAR_DET_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena + is set to 1.*/ +#define UART_AT_CMD_CHAR_DET_INT_ST (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ST_M (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ST_V 0x1 +#define UART_AT_CMD_CHAR_DET_INT_ST_S 18 +/* UART_RS485_CLASH_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena + is set to 1.*/ +#define UART_RS485_CLASH_INT_ST (BIT(17)) +#define UART_RS485_CLASH_INT_ST_M (BIT(17)) +#define UART_RS485_CLASH_INT_ST_V 0x1 +#define UART_RS485_CLASH_INT_ST_S 17 +/* UART_RS485_FRM_ERR_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This is the status bit for rs485_fm_err_int_raw when rs485_fm_err_int_ena + is set to 1.*/ +#define UART_RS485_FRM_ERR_INT_ST (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ST_M (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ST_V 0x1 +#define UART_RS485_FRM_ERR_INT_ST_S 16 +/* UART_RS485_PARITY_ERR_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena + is set to 1.*/ +#define UART_RS485_PARITY_ERR_INT_ST (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ST_M (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ST_V 0x1 +#define UART_RS485_PARITY_ERR_INT_ST_S 15 +/* UART_TX_DONE_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/ +#define UART_TX_DONE_INT_ST (BIT(14)) +#define UART_TX_DONE_INT_ST_M (BIT(14)) +#define UART_TX_DONE_INT_ST_V 0x1 +#define UART_TX_DONE_INT_ST_S 14 +/* UART_TX_BRK_IDLE_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena + is set to 1.*/ +#define UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ST_M (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ST_V 0x1 +#define UART_TX_BRK_IDLE_DONE_INT_ST_S 13 +/* UART_TX_BRK_DONE_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena + is set to 1.*/ +#define UART_TX_BRK_DONE_INT_ST (BIT(12)) +#define UART_TX_BRK_DONE_INT_ST_M (BIT(12)) +#define UART_TX_BRK_DONE_INT_ST_V 0x1 +#define UART_TX_BRK_DONE_INT_ST_S 12 +/* UART_GLITCH_DET_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: This is the status bit for glitch_det_int_raw when glitch_det_int_ena + is set to 1.*/ +#define UART_GLITCH_DET_INT_ST (BIT(11)) +#define UART_GLITCH_DET_INT_ST_M (BIT(11)) +#define UART_GLITCH_DET_INT_ST_V 0x1 +#define UART_GLITCH_DET_INT_ST_S 11 +/* UART_SW_XOFF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/ +#define UART_SW_XOFF_INT_ST (BIT(10)) +#define UART_SW_XOFF_INT_ST_M (BIT(10)) +#define UART_SW_XOFF_INT_ST_V 0x1 +#define UART_SW_XOFF_INT_ST_S 10 +/* UART_SW_XON_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/ +#define UART_SW_XON_INT_ST (BIT(9)) +#define UART_SW_XON_INT_ST_M (BIT(9)) +#define UART_SW_XON_INT_ST_V 0x1 +#define UART_SW_XON_INT_ST_S 9 +/* UART_RXFIFO_TOUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena + is set to 1.*/ +#define UART_RXFIFO_TOUT_INT_ST (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ST_M (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ST_V 0x1 +#define UART_RXFIFO_TOUT_INT_ST_S 8 +/* UART_BRK_DET_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/ +#define UART_BRK_DET_INT_ST (BIT(7)) +#define UART_BRK_DET_INT_ST_M (BIT(7)) +#define UART_BRK_DET_INT_ST_V 0x1 +#define UART_BRK_DET_INT_ST_S 7 +/* UART_CTS_CHG_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/ +#define UART_CTS_CHG_INT_ST (BIT(6)) +#define UART_CTS_CHG_INT_ST_M (BIT(6)) +#define UART_CTS_CHG_INT_ST_V 0x1 +#define UART_CTS_CHG_INT_ST_S 6 +/* UART_DSR_CHG_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/ +#define UART_DSR_CHG_INT_ST (BIT(5)) +#define UART_DSR_CHG_INT_ST_M (BIT(5)) +#define UART_DSR_CHG_INT_ST_V 0x1 +#define UART_DSR_CHG_INT_ST_S 5 +/* UART_RXFIFO_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena + is set to 1.*/ +#define UART_RXFIFO_OVF_INT_ST (BIT(4)) +#define UART_RXFIFO_OVF_INT_ST_M (BIT(4)) +#define UART_RXFIFO_OVF_INT_ST_V 0x1 +#define UART_RXFIFO_OVF_INT_ST_S 4 +/* UART_FRM_ERR_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This is the status bit for frm_err_int_raw when fm_err_int_ena is set to 1.*/ +#define UART_FRM_ERR_INT_ST (BIT(3)) +#define UART_FRM_ERR_INT_ST_M (BIT(3)) +#define UART_FRM_ERR_INT_ST_V 0x1 +#define UART_FRM_ERR_INT_ST_S 3 +/* UART_PARITY_ERR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the status bit for parity_err_int_raw when parity_err_int_ena + is set to 1.*/ +#define UART_PARITY_ERR_INT_ST (BIT(2)) +#define UART_PARITY_ERR_INT_ST_M (BIT(2)) +#define UART_PARITY_ERR_INT_ST_V 0x1 +#define UART_PARITY_ERR_INT_ST_S 2 +/* UART_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena + is set to 1.*/ +#define UART_TXFIFO_EMPTY_INT_ST (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ST_M (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ST_V 0x1 +#define UART_TXFIFO_EMPTY_INT_ST_S 1 +/* UART_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena + is set to 1.*/ +#define UART_RXFIFO_FULL_INT_ST (BIT(0)) +#define UART_RXFIFO_FULL_INT_ST_M (BIT(0)) +#define UART_RXFIFO_FULL_INT_ST_V 0x1 +#define UART_RXFIFO_FULL_INT_ST_S 0 + +#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xC) +/* UART_AT_CMD_CHAR_DET_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This is the enable bit for at_cmd_char_det_int_st register.*/ +#define UART_AT_CMD_CHAR_DET_INT_ENA (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ENA_M (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ENA_V 0x1 +#define UART_AT_CMD_CHAR_DET_INT_ENA_S 18 +/* UART_RS485_CLASH_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This is the enable bit for rs485_clash_int_st register.*/ +#define UART_RS485_CLASH_INT_ENA (BIT(17)) +#define UART_RS485_CLASH_INT_ENA_M (BIT(17)) +#define UART_RS485_CLASH_INT_ENA_V 0x1 +#define UART_RS485_CLASH_INT_ENA_S 17 +/* UART_RS485_FRM_ERR_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This is the enable bit for rs485_parity_err_int_st register.*/ +#define UART_RS485_FRM_ERR_INT_ENA (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ENA_M (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ENA_V 0x1 +#define UART_RS485_FRM_ERR_INT_ENA_S 16 +/* UART_RS485_PARITY_ERR_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This is the enable bit for rs485_parity_err_int_st register.*/ +#define UART_RS485_PARITY_ERR_INT_ENA (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ENA_M (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ENA_V 0x1 +#define UART_RS485_PARITY_ERR_INT_ENA_S 15 +/* UART_TX_DONE_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This is the enable bit for tx_done_int_st register.*/ +#define UART_TX_DONE_INT_ENA (BIT(14)) +#define UART_TX_DONE_INT_ENA_M (BIT(14)) +#define UART_TX_DONE_INT_ENA_V 0x1 +#define UART_TX_DONE_INT_ENA_S 14 +/* UART_TX_BRK_IDLE_DONE_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: This is the enable bit for tx_brk_idle_done_int_st register.*/ +#define UART_TX_BRK_IDLE_DONE_INT_ENA (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ENA_M (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ENA_V 0x1 +#define UART_TX_BRK_IDLE_DONE_INT_ENA_S 13 +/* UART_TX_BRK_DONE_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: This is the enable bit for tx_brk_done_int_st register.*/ +#define UART_TX_BRK_DONE_INT_ENA (BIT(12)) +#define UART_TX_BRK_DONE_INT_ENA_M (BIT(12)) +#define UART_TX_BRK_DONE_INT_ENA_V 0x1 +#define UART_TX_BRK_DONE_INT_ENA_S 12 +/* UART_GLITCH_DET_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: This is the enable bit for glitch_det_int_st register.*/ +#define UART_GLITCH_DET_INT_ENA (BIT(11)) +#define UART_GLITCH_DET_INT_ENA_M (BIT(11)) +#define UART_GLITCH_DET_INT_ENA_V 0x1 +#define UART_GLITCH_DET_INT_ENA_S 11 +/* UART_SW_XOFF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: This is the enable bit for sw_xoff_int_st register.*/ +#define UART_SW_XOFF_INT_ENA (BIT(10)) +#define UART_SW_XOFF_INT_ENA_M (BIT(10)) +#define UART_SW_XOFF_INT_ENA_V 0x1 +#define UART_SW_XOFF_INT_ENA_S 10 +/* UART_SW_XON_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: This is the enable bit for sw_xon_int_st register.*/ +#define UART_SW_XON_INT_ENA (BIT(9)) +#define UART_SW_XON_INT_ENA_M (BIT(9)) +#define UART_SW_XON_INT_ENA_V 0x1 +#define UART_SW_XON_INT_ENA_S 9 +/* UART_RXFIFO_TOUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: This is the enable bit for rxfifo_tout_int_st register.*/ +#define UART_RXFIFO_TOUT_INT_ENA (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ENA_M (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ENA_V 0x1 +#define UART_RXFIFO_TOUT_INT_ENA_S 8 +/* UART_BRK_DET_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the enable bit for brk_det_int_st register.*/ +#define UART_BRK_DET_INT_ENA (BIT(7)) +#define UART_BRK_DET_INT_ENA_M (BIT(7)) +#define UART_BRK_DET_INT_ENA_V 0x1 +#define UART_BRK_DET_INT_ENA_S 7 +/* UART_CTS_CHG_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This is the enable bit for cts_chg_int_st register.*/ +#define UART_CTS_CHG_INT_ENA (BIT(6)) +#define UART_CTS_CHG_INT_ENA_M (BIT(6)) +#define UART_CTS_CHG_INT_ENA_V 0x1 +#define UART_CTS_CHG_INT_ENA_S 6 +/* UART_DSR_CHG_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This is the enable bit for dsr_chg_int_st register.*/ +#define UART_DSR_CHG_INT_ENA (BIT(5)) +#define UART_DSR_CHG_INT_ENA_M (BIT(5)) +#define UART_DSR_CHG_INT_ENA_V 0x1 +#define UART_DSR_CHG_INT_ENA_S 5 +/* UART_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This is the enable bit for rxfifo_ovf_int_st register.*/ +#define UART_RXFIFO_OVF_INT_ENA (BIT(4)) +#define UART_RXFIFO_OVF_INT_ENA_M (BIT(4)) +#define UART_RXFIFO_OVF_INT_ENA_V 0x1 +#define UART_RXFIFO_OVF_INT_ENA_S 4 +/* UART_FRM_ERR_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This is the enable bit for frm_err_int_st register.*/ +#define UART_FRM_ERR_INT_ENA (BIT(3)) +#define UART_FRM_ERR_INT_ENA_M (BIT(3)) +#define UART_FRM_ERR_INT_ENA_V 0x1 +#define UART_FRM_ERR_INT_ENA_S 3 +/* UART_PARITY_ERR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the enable bit for parity_err_int_st register.*/ +#define UART_PARITY_ERR_INT_ENA (BIT(2)) +#define UART_PARITY_ERR_INT_ENA_M (BIT(2)) +#define UART_PARITY_ERR_INT_ENA_V 0x1 +#define UART_PARITY_ERR_INT_ENA_S 2 +/* UART_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: This is the enable bit for rxfifo_full_int_st register.*/ +#define UART_TXFIFO_EMPTY_INT_ENA (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ENA_M (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ENA_V 0x1 +#define UART_TXFIFO_EMPTY_INT_ENA_S 1 +/* UART_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This is the enable bit for rxfifo_full_int_st register.*/ +#define UART_RXFIFO_FULL_INT_ENA (BIT(0)) +#define UART_RXFIFO_FULL_INT_ENA_M (BIT(0)) +#define UART_RXFIFO_FULL_INT_ENA_V 0x1 +#define UART_RXFIFO_FULL_INT_ENA_S 0 + +#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10) +/* UART_AT_CMD_CHAR_DET_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/ +#define UART_AT_CMD_CHAR_DET_INT_CLR (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_CLR_M (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_CLR_V 0x1 +#define UART_AT_CMD_CHAR_DET_INT_CLR_S 18 +/* UART_RS485_CLASH_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rs485_clash_int_raw interrupt.*/ +#define UART_RS485_CLASH_INT_CLR (BIT(17)) +#define UART_RS485_CLASH_INT_CLR_M (BIT(17)) +#define UART_RS485_CLASH_INT_CLR_V 0x1 +#define UART_RS485_CLASH_INT_CLR_S 17 +/* UART_RS485_FRM_ERR_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rs485_frm_err_int_raw interrupt.*/ +#define UART_RS485_FRM_ERR_INT_CLR (BIT(16)) +#define UART_RS485_FRM_ERR_INT_CLR_M (BIT(16)) +#define UART_RS485_FRM_ERR_INT_CLR_V 0x1 +#define UART_RS485_FRM_ERR_INT_CLR_S 16 +/* UART_RS485_PARITY_ERR_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rs485_parity_err_int_raw interrupt.*/ +#define UART_RS485_PARITY_ERR_INT_CLR (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_CLR_M (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_CLR_V 0x1 +#define UART_RS485_PARITY_ERR_INT_CLR_S 15 +/* UART_TX_DONE_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: Set this bit to clear the tx_done_int_raw interrupt.*/ +#define UART_TX_DONE_INT_CLR (BIT(14)) +#define UART_TX_DONE_INT_CLR_M (BIT(14)) +#define UART_TX_DONE_INT_CLR_V 0x1 +#define UART_TX_DONE_INT_CLR_S 14 +/* UART_TX_BRK_IDLE_DONE_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/ +#define UART_TX_BRK_IDLE_DONE_INT_CLR (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_CLR_M (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_CLR_V 0x1 +#define UART_TX_BRK_IDLE_DONE_INT_CLR_S 13 +/* UART_TX_BRK_DONE_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to clear the tx_brk_done_int_raw interrupt..*/ +#define UART_TX_BRK_DONE_INT_CLR (BIT(12)) +#define UART_TX_BRK_DONE_INT_CLR_M (BIT(12)) +#define UART_TX_BRK_DONE_INT_CLR_V 0x1 +#define UART_TX_BRK_DONE_INT_CLR_S 12 +/* UART_GLITCH_DET_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Set this bit to clear the glitch_det_int_raw interrupt.*/ +#define UART_GLITCH_DET_INT_CLR (BIT(11)) +#define UART_GLITCH_DET_INT_CLR_M (BIT(11)) +#define UART_GLITCH_DET_INT_CLR_V 0x1 +#define UART_GLITCH_DET_INT_CLR_S 11 +/* UART_SW_XOFF_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to clear the sw_xon_int_raw interrupt.*/ +#define UART_SW_XOFF_INT_CLR (BIT(10)) +#define UART_SW_XOFF_INT_CLR_M (BIT(10)) +#define UART_SW_XOFF_INT_CLR_V 0x1 +#define UART_SW_XOFF_INT_CLR_S 10 +/* UART_SW_XON_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to clear the sw_xon_int_raw interrupt.*/ +#define UART_SW_XON_INT_CLR (BIT(9)) +#define UART_SW_XON_INT_CLR_M (BIT(9)) +#define UART_SW_XON_INT_CLR_V 0x1 +#define UART_SW_XON_INT_CLR_S 9 +/* UART_RXFIFO_TOUT_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rxfifo_tout_int_raw interrupt.*/ +#define UART_RXFIFO_TOUT_INT_CLR (BIT(8)) +#define UART_RXFIFO_TOUT_INT_CLR_M (BIT(8)) +#define UART_RXFIFO_TOUT_INT_CLR_V 0x1 +#define UART_RXFIFO_TOUT_INT_CLR_S 8 +/* UART_BRK_DET_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to clear the brk_det_int_raw interrupt.*/ +#define UART_BRK_DET_INT_CLR (BIT(7)) +#define UART_BRK_DET_INT_CLR_M (BIT(7)) +#define UART_BRK_DET_INT_CLR_V 0x1 +#define UART_BRK_DET_INT_CLR_S 7 +/* UART_CTS_CHG_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to clear the cts_chg_int_raw interrupt.*/ +#define UART_CTS_CHG_INT_CLR (BIT(6)) +#define UART_CTS_CHG_INT_CLR_M (BIT(6)) +#define UART_CTS_CHG_INT_CLR_V 0x1 +#define UART_CTS_CHG_INT_CLR_S 6 +/* UART_DSR_CHG_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to clear the dsr_chg_int_raw interrupt.*/ +#define UART_DSR_CHG_INT_CLR (BIT(5)) +#define UART_DSR_CHG_INT_CLR_M (BIT(5)) +#define UART_DSR_CHG_INT_CLR_V 0x1 +#define UART_DSR_CHG_INT_CLR_S 5 +/* UART_RXFIFO_OVF_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to clear rxfifo_ovf_int_raw interrupt.*/ +#define UART_RXFIFO_OVF_INT_CLR (BIT(4)) +#define UART_RXFIFO_OVF_INT_CLR_M (BIT(4)) +#define UART_RXFIFO_OVF_INT_CLR_V 0x1 +#define UART_RXFIFO_OVF_INT_CLR_S 4 +/* UART_FRM_ERR_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear frm_err_int_raw interrupt.*/ +#define UART_FRM_ERR_INT_CLR (BIT(3)) +#define UART_FRM_ERR_INT_CLR_M (BIT(3)) +#define UART_FRM_ERR_INT_CLR_V 0x1 +#define UART_FRM_ERR_INT_CLR_S 3 +/* UART_PARITY_ERR_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear parity_err_int_raw interrupt.*/ +#define UART_PARITY_ERR_INT_CLR (BIT(2)) +#define UART_PARITY_ERR_INT_CLR_M (BIT(2)) +#define UART_PARITY_ERR_INT_CLR_V 0x1 +#define UART_PARITY_ERR_INT_CLR_S 2 +/* UART_TXFIFO_EMPTY_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear txfifo_empty_int_raw interrupt.*/ +#define UART_TXFIFO_EMPTY_INT_CLR (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_CLR_M (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_CLR_V 0x1 +#define UART_TXFIFO_EMPTY_INT_CLR_S 1 +/* UART_RXFIFO_FULL_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rxfifo_full_int_raw interrupt.*/ +#define UART_RXFIFO_FULL_INT_CLR (BIT(0)) +#define UART_RXFIFO_FULL_INT_CLR_M (BIT(0)) +#define UART_RXFIFO_FULL_INT_CLR_V 0x1 +#define UART_RXFIFO_FULL_INT_CLR_S 0 + +#define UART_CLKDIV_REG(i) (REG_UART_BASE(i) + 0x14) +/* UART_CLKDIV_FRAG : R/W ;bitpos:[23:20] ;default: 4'h0 ; */ +/*description: The register value is the decimal part of the frequency divider's factor.*/ +#define UART_CLKDIV_FRAG 0x0000000F +#define UART_CLKDIV_FRAG_M ((UART_CLKDIV_FRAG_V)<<(UART_CLKDIV_FRAG_S)) +#define UART_CLKDIV_FRAG_V 0xF +#define UART_CLKDIV_FRAG_S 20 +/* UART_CLKDIV : R/W ;bitpos:[19:0] ;default: 20'h2B6 ; */ +/*description: The register value is the integer part of the frequency divider's factor.*/ +#define UART_CLKDIV 0x000FFFFF +#define UART_CLKDIV_M ((UART_CLKDIV_V)<<(UART_CLKDIV_S)) +#define UART_CLKDIV_V 0xFFFFF +#define UART_CLKDIV_S 0 + +#define UART_AUTOBAUD_REG(i) (REG_UART_BASE(i) + 0x18) +/* UART_GLITCH_FILT : R/W ;bitpos:[15:8] ;default: 8'h10 ; */ +/*description: when input pulse width is lower then this value igore this pulse.this + register is used in autobaud detect process.*/ +#define UART_GLITCH_FILT 0x000000FF +#define UART_GLITCH_FILT_M ((UART_GLITCH_FILT_V)<<(UART_GLITCH_FILT_S)) +#define UART_GLITCH_FILT_V 0xFF +#define UART_GLITCH_FILT_S 8 +/* UART_AUTOBAUD_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This is the enable bit for detecting baudrate.*/ +#define UART_AUTOBAUD_EN (BIT(0)) +#define UART_AUTOBAUD_EN_M (BIT(0)) +#define UART_AUTOBAUD_EN_V 0x1 +#define UART_AUTOBAUD_EN_S 0 + +#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1C) +/* UART_TXD : RO ;bitpos:[31] ;default: 8'h0 ; */ +/*description: This register represent the level value of the internal uart rxd signal.*/ +#define UART_TXD (BIT(31)) +#define UART_TXD_M (BIT(31)) +#define UART_TXD_V 0x1 +#define UART_TXD_S 31 +/* UART_RTSN : RO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: This register represent the level value of the internal uart cts signal.*/ +#define UART_RTSN (BIT(30)) +#define UART_RTSN_M (BIT(30)) +#define UART_RTSN_V 0x1 +#define UART_RTSN_S 30 +/* UART_DTRN : RO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: The register represent the level value of the internal uart dsr signal.*/ +#define UART_DTRN (BIT(29)) +#define UART_DTRN_M (BIT(29)) +#define UART_DTRN_V 0x1 +#define UART_DTRN_S 29 +/* UART_ST_UTX_OUT : RO ;bitpos:[27:24] ;default: 4'b0 ; */ +/*description: This register stores the value of transmitter's finite state + machine. 0:TX_IDLE 1:TX_STRT 2:TX_DAT0 3:TX_DAT1 4:TX_DAT2 5:TX_DAT3 6:TX_DAT4 7:TX_DAT5 8:TX_DAT6 9:TX_DAT7 10:TX_PRTY 11:TX_STP1 12:TX_STP2 13:TX_DL0 14:TX_DL1*/ +#define UART_ST_UTX_OUT 0x0000000F +#define UART_ST_UTX_OUT_M ((UART_ST_UTX_OUT_V)<<(UART_ST_UTX_OUT_S)) +#define UART_ST_UTX_OUT_V 0xF +#define UART_ST_UTX_OUT_S 24 +/* UART_TXFIFO_CNT : RO ;bitpos:[23:16] ;default: 8'b0 ; */ +/*description: (tx_mem_cnt txfifo_cnt) stores the byte num of valid datas in + transmitter's fifo.tx_mem_cnt stores the 3 most significant bits txfifo_cnt stores the 8 least significant bits.*/ +#define UART_TXFIFO_CNT 0x000000FF +#define UART_TXFIFO_CNT_M ((UART_TXFIFO_CNT_V)<<(UART_TXFIFO_CNT_S)) +#define UART_TXFIFO_CNT_V 0xFF +#define UART_TXFIFO_CNT_S 16 +/* UART_RXD : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This register stores the level value of the internal uart rxd signal.*/ +#define UART_RXD (BIT(15)) +#define UART_RXD_M (BIT(15)) +#define UART_RXD_V 0x1 +#define UART_RXD_S 15 +/* UART_CTSN : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This register stores the level value of the internal uart cts signal.*/ +#define UART_CTSN (BIT(14)) +#define UART_CTSN_M (BIT(14)) +#define UART_CTSN_V 0x1 +#define UART_CTSN_S 14 +/* UART_DSRN : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: This register stores the level value of the internal uart dsr signal.*/ +#define UART_DSRN (BIT(13)) +#define UART_DSRN_M (BIT(13)) +#define UART_DSRN_V 0x1 +#define UART_DSRN_S 13 +/* UART_ST_URX_OUT : RO ;bitpos:[11:8] ;default: 4'b0 ; */ +/*description: This register stores the value of receiver's finite state machine. + 0:RX_IDLE 1:RX_STRT 2:RX_DAT0 3:RX_DAT1 4:RX_DAT2 5:RX_DAT3 6:RX_DAT4 7:RX_DAT5 8:RX_DAT6 9:RX_DAT7 10:RX_PRTY 11:RX_STP1 12:RX_STP2 13:RX_DL1*/ +#define UART_ST_URX_OUT 0x0000000F +#define UART_ST_URX_OUT_M ((UART_ST_URX_OUT_V)<<(UART_ST_URX_OUT_S)) +#define UART_ST_URX_OUT_V 0xF +#define UART_ST_URX_OUT_S 8 +/* UART_RXFIFO_CNT : RO ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: (rx_mem_cnt rxfifo_cnt) stores the byte num of valid datas in + receiver's fifo. rx_mem_cnt register stores the 3 most significant bits rxfifo_cnt stores the 8 least significant bits.*/ +#define UART_RXFIFO_CNT 0x000000FF +#define UART_RXFIFO_CNT_M ((UART_RXFIFO_CNT_V)<<(UART_RXFIFO_CNT_S)) +#define UART_RXFIFO_CNT_V 0xFF +#define UART_RXFIFO_CNT_S 0 + +#define UART_CONF0_REG(i) (REG_UART_BASE(i) + 0x20) +/* UART_TICK_REF_ALWAYS_ON : R/W ;bitpos:[27] ;default: 1'b1 ; */ +/*description: This register is used to select the clock.1.apb clock 0:ref_tick*/ +#define UART_TICK_REF_ALWAYS_ON (BIT(27)) +#define UART_TICK_REF_ALWAYS_ON_M (BIT(27)) +#define UART_TICK_REF_ALWAYS_ON_V 0x1 +#define UART_TICK_REF_ALWAYS_ON_S 27 +/* UART_ERR_WR_MASK : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: 1.receiver stops storing data int fifo when data is wrong. + 0.receiver stores the data even if the received data is wrong.*/ +#define UART_ERR_WR_MASK (BIT(26)) +#define UART_ERR_WR_MASK_M (BIT(26)) +#define UART_ERR_WR_MASK_V 0x1 +#define UART_ERR_WR_MASK_S 26 +/* UART_CLK_EN : R/W ;bitpos:[25] ;default: 1'h0 ; */ +/*description: 1.force clock on for registers.support clock only when write registers*/ +#define UART_CLK_EN (BIT(25)) +#define UART_CLK_EN_M (BIT(25)) +#define UART_CLK_EN_V 0x1 +#define UART_CLK_EN_S 25 +/* UART_DTR_INV : R/W ;bitpos:[24] ;default: 1'h0 ; */ +/*description: Set this bit to inverse the level value of uart dtr signal.*/ +#define UART_DTR_INV (BIT(24)) +#define UART_DTR_INV_M (BIT(24)) +#define UART_DTR_INV_V 0x1 +#define UART_DTR_INV_S 24 +/* UART_RTS_INV : R/W ;bitpos:[23] ;default: 1'h0 ; */ +/*description: Set this bit to inverse the level value of uart rts signal.*/ +#define UART_RTS_INV (BIT(23)) +#define UART_RTS_INV_M (BIT(23)) +#define UART_RTS_INV_V 0x1 +#define UART_RTS_INV_S 23 +/* UART_TXD_INV : R/W ;bitpos:[22] ;default: 1'h0 ; */ +/*description: Set this bit to inverse the level value of uart txd signal.*/ +#define UART_TXD_INV (BIT(22)) +#define UART_TXD_INV_M (BIT(22)) +#define UART_TXD_INV_V 0x1 +#define UART_TXD_INV_S 22 +/* UART_DSR_INV : R/W ;bitpos:[21] ;default: 1'h0 ; */ +/*description: Set this bit to inverse the level value of uart dsr signal.*/ +#define UART_DSR_INV (BIT(21)) +#define UART_DSR_INV_M (BIT(21)) +#define UART_DSR_INV_V 0x1 +#define UART_DSR_INV_S 21 +/* UART_CTS_INV : R/W ;bitpos:[20] ;default: 1'h0 ; */ +/*description: Set this bit to inverse the level value of uart cts signal.*/ +#define UART_CTS_INV (BIT(20)) +#define UART_CTS_INV_M (BIT(20)) +#define UART_CTS_INV_V 0x1 +#define UART_CTS_INV_S 20 +/* UART_RXD_INV : R/W ;bitpos:[19] ;default: 1'h0 ; */ +/*description: Set this bit to inverse the level value of uart rxd signal.*/ +#define UART_RXD_INV (BIT(19)) +#define UART_RXD_INV_M (BIT(19)) +#define UART_RXD_INV_V 0x1 +#define UART_RXD_INV_S 19 +/* UART_TXFIFO_RST : R/W ;bitpos:[18] ;default: 1'h0 ; */ +/*description: Set this bit to reset uart transmitter's fifo.*/ +#define UART_TXFIFO_RST (BIT(18)) +#define UART_TXFIFO_RST_M (BIT(18)) +#define UART_TXFIFO_RST_V 0x1 +#define UART_TXFIFO_RST_S 18 +/* UART_RXFIFO_RST : R/W ;bitpos:[17] ;default: 1'h0 ; */ +/*description: Set this bit to reset uart receiver's fifo.*/ +#define UART_RXFIFO_RST (BIT(17)) +#define UART_RXFIFO_RST_M (BIT(17)) +#define UART_RXFIFO_RST_V 0x1 +#define UART_RXFIFO_RST_S 17 +/* UART_IRDA_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */ +/*description: Set this bit to enable irda protocol.*/ +#define UART_IRDA_EN (BIT(16)) +#define UART_IRDA_EN_M (BIT(16)) +#define UART_IRDA_EN_V 0x1 +#define UART_IRDA_EN_S 16 +/* UART_TX_FLOW_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: Set this bit to enable transmitter's flow control function.*/ +#define UART_TX_FLOW_EN (BIT(15)) +#define UART_TX_FLOW_EN_M (BIT(15)) +#define UART_TX_FLOW_EN_V 0x1 +#define UART_TX_FLOW_EN_S 15 +/* UART_LOOPBACK : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: Set this bit to enable uart loopback test mode.*/ +#define UART_LOOPBACK (BIT(14)) +#define UART_LOOPBACK_M (BIT(14)) +#define UART_LOOPBACK_V 0x1 +#define UART_LOOPBACK_S 14 +/* UART_IRDA_RX_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Set this bit to inverse the level value of irda receiver's level.*/ +#define UART_IRDA_RX_INV (BIT(13)) +#define UART_IRDA_RX_INV_M (BIT(13)) +#define UART_IRDA_RX_INV_V 0x1 +#define UART_IRDA_RX_INV_S 13 +/* UART_IRDA_TX_INV : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to inverse the level value of irda transmitter's level.*/ +#define UART_IRDA_TX_INV (BIT(12)) +#define UART_IRDA_TX_INV_M (BIT(12)) +#define UART_IRDA_TX_INV_V 0x1 +#define UART_IRDA_TX_INV_S 12 +/* UART_IRDA_WCTL : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: 1.the irda transmitter's 11th bit is the same to the 10th bit. + 0.set irda transmitter's 11th bit to 0.*/ +#define UART_IRDA_WCTL (BIT(11)) +#define UART_IRDA_WCTL_M (BIT(11)) +#define UART_IRDA_WCTL_V 0x1 +#define UART_IRDA_WCTL_S 11 +/* UART_IRDA_TX_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: This is the start enable bit for irda transmitter.*/ +#define UART_IRDA_TX_EN (BIT(10)) +#define UART_IRDA_TX_EN_M (BIT(10)) +#define UART_IRDA_TX_EN_V 0x1 +#define UART_IRDA_TX_EN_S 10 +/* UART_IRDA_DPLX : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to enable irda loopback mode.*/ +#define UART_IRDA_DPLX (BIT(9)) +#define UART_IRDA_DPLX_M (BIT(9)) +#define UART_IRDA_DPLX_V 0x1 +#define UART_IRDA_DPLX_S 9 +/* UART_TXD_BRK : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to enbale transmitter to send 0 when the process + of sending data is done.*/ +#define UART_TXD_BRK (BIT(8)) +#define UART_TXD_BRK_M (BIT(8)) +#define UART_TXD_BRK_V 0x1 +#define UART_TXD_BRK_S 8 +/* UART_SW_DTR : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This register is used to configure the software dtr signal which + is used in software flow control..*/ +#define UART_SW_DTR (BIT(7)) +#define UART_SW_DTR_M (BIT(7)) +#define UART_SW_DTR_V 0x1 +#define UART_SW_DTR_S 7 +/* UART_SW_RTS : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This register is used to configure the software rts signal which + is used in software flow control.*/ +#define UART_SW_RTS (BIT(6)) +#define UART_SW_RTS_M (BIT(6)) +#define UART_SW_RTS_V 0x1 +#define UART_SW_RTS_S 6 +/* UART_STOP_BIT_NUM : R/W ;bitpos:[5:4] ;default: 2'd1 ; */ +/*description: This register is used to set the length of stop bit. 1:1bit 2:1.5bits 3:2bits*/ +#define UART_STOP_BIT_NUM 0x00000003 +#define UART_STOP_BIT_NUM_M ((UART_STOP_BIT_NUM_V)<<(UART_STOP_BIT_NUM_S)) +#define UART_STOP_BIT_NUM_V 0x3 +#define UART_STOP_BIT_NUM_S 4 +/* UART_BIT_NUM : R/W ;bitpos:[3:2] ;default: 2'd3 ; */ +/*description: This registe is used to set the length of data: 0:5bits 1:6bits 2:7bits 3:8bits*/ +#define UART_BIT_NUM 0x00000003 +#define UART_BIT_NUM_M ((UART_BIT_NUM_V)<<(UART_BIT_NUM_S)) +#define UART_BIT_NUM_V 0x3 +#define UART_BIT_NUM_S 2 +/* UART_PARITY_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to enable uart parity check.*/ +#define UART_PARITY_EN (BIT(1)) +#define UART_PARITY_EN_M (BIT(1)) +#define UART_PARITY_EN_V 0x1 +#define UART_PARITY_EN_S 1 +/* UART_PARITY : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This register is used to configure the parity check mode. 0:even 1:odd*/ +#define UART_PARITY (BIT(0)) +#define UART_PARITY_M (BIT(0)) +#define UART_PARITY_V 0x1 +#define UART_PARITY_S 0 + +#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24) +/* UART_RX_TOUT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: This is the enble bit for uart receiver's timeout function.*/ +#define UART_RX_TOUT_EN (BIT(31)) +#define UART_RX_TOUT_EN_M (BIT(31)) +#define UART_RX_TOUT_EN_V 0x1 +#define UART_RX_TOUT_EN_S 31 +/* UART_RX_TOUT_THRHD : R/W ;bitpos:[30:24] ;default: 7'b0 ; */ +/*description: This register is used to configure the timeout value for uart + receiver receiving a byte.*/ +#define UART_RX_TOUT_THRHD 0x0000007F +#define UART_RX_TOUT_THRHD_M ((UART_RX_TOUT_THRHD_V)<<(UART_RX_TOUT_THRHD_S)) +#define UART_RX_TOUT_THRHD_V 0x7F +#define UART_RX_TOUT_THRHD_S 24 +/* UART_RX_FLOW_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: This is the flow enable bit for uart receiver. 1:choose software + flow control with configuring sw_rts signal*/ +#define UART_RX_FLOW_EN (BIT(23)) +#define UART_RX_FLOW_EN_M (BIT(23)) +#define UART_RX_FLOW_EN_V 0x1 +#define UART_RX_FLOW_EN_S 23 +/* UART_RX_FLOW_THRHD : R/W ;bitpos:[22:16] ;default: 7'h0 ; */ +/*description: when receiver receives more data than its threshold value. + receiver produce signal to tell the transmitter stop transferring data. the threshold value is (rx_flow_thrhd_h3 rx_flow_thrhd).*/ +#define UART_RX_FLOW_THRHD 0x0000007F +#define UART_RX_FLOW_THRHD_M ((UART_RX_FLOW_THRHD_V)<<(UART_RX_FLOW_THRHD_S)) +#define UART_RX_FLOW_THRHD_V 0x7F +#define UART_RX_FLOW_THRHD_S 16 +/* UART_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[14:8] ;default: 7'h60 ; */ +/*description: when the data amount in transmitter fifo is less than its threshold + value. it will produce txfifo_empty_int_raw interrupt. the threshold value is (tx_mem_empty_thrhd txfifo_empty_thrhd)*/ +#define UART_TXFIFO_EMPTY_THRHD 0x0000007F +#define UART_TXFIFO_EMPTY_THRHD_M ((UART_TXFIFO_EMPTY_THRHD_V)<<(UART_TXFIFO_EMPTY_THRHD_S)) +#define UART_TXFIFO_EMPTY_THRHD_V 0x7F +#define UART_TXFIFO_EMPTY_THRHD_S 8 +/* UART_RXFIFO_FULL_THRHD : R/W ;bitpos:[6:0] ;default: 7'h60 ; */ +/*description: When receiver receives more data than its threshold value.receiver + will produce rxfifo_full_int_raw interrupt.the threshold value is (rx_flow_thrhd_h3 rxfifo_full_thrhd).*/ +#define UART_RXFIFO_FULL_THRHD 0x0000007F +#define UART_RXFIFO_FULL_THRHD_M ((UART_RXFIFO_FULL_THRHD_V)<<(UART_RXFIFO_FULL_THRHD_S)) +#define UART_RXFIFO_FULL_THRHD_V 0x7F +#define UART_RXFIFO_FULL_THRHD_S 0 + +#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x28) +/* UART_LOWPULSE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */ +/*description: This register stores the value of the minimum duration time for + the low level pulse. it is used in baudrate-detect process.*/ +#define UART_LOWPULSE_MIN_CNT 0x000FFFFF +#define UART_LOWPULSE_MIN_CNT_M ((UART_LOWPULSE_MIN_CNT_V)<<(UART_LOWPULSE_MIN_CNT_S)) +#define UART_LOWPULSE_MIN_CNT_V 0xFFFFF +#define UART_LOWPULSE_MIN_CNT_S 0 + +#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x2C) +/* UART_HIGHPULSE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */ +/*description: This register stores the value of the maxinum duration time + for the high level pulse. it is used in baudrate-detect process.*/ +#define UART_HIGHPULSE_MIN_CNT 0x000FFFFF +#define UART_HIGHPULSE_MIN_CNT_M ((UART_HIGHPULSE_MIN_CNT_V)<<(UART_HIGHPULSE_MIN_CNT_S)) +#define UART_HIGHPULSE_MIN_CNT_V 0xFFFFF +#define UART_HIGHPULSE_MIN_CNT_S 0 + +#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x30) +/* UART_RXD_EDGE_CNT : RO ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register stores the count of rxd edge change. it is used + in baudrate-detect process.*/ +#define UART_RXD_EDGE_CNT 0x000003FF +#define UART_RXD_EDGE_CNT_M ((UART_RXD_EDGE_CNT_V)<<(UART_RXD_EDGE_CNT_S)) +#define UART_RXD_EDGE_CNT_V 0x3FF +#define UART_RXD_EDGE_CNT_S 0 + +#define UART_FLOW_CONF_REG(i) (REG_UART_BASE(i) + 0x34) +/* UART_SEND_XOFF : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to send xoff char. it is cleared by hardware automatically.*/ +#define UART_SEND_XOFF (BIT(5)) +#define UART_SEND_XOFF_M (BIT(5)) +#define UART_SEND_XOFF_V 0x1 +#define UART_SEND_XOFF_S 5 +/* UART_SEND_XON : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to send xon char. it is cleared by hardware automatically.*/ +#define UART_SEND_XON (BIT(4)) +#define UART_SEND_XON_M (BIT(4)) +#define UART_SEND_XON_V 0x1 +#define UART_SEND_XON_S 4 +/* UART_FORCE_XOFF : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to set ctsn to enable the transmitter to go on sending data.*/ +#define UART_FORCE_XOFF (BIT(3)) +#define UART_FORCE_XOFF_M (BIT(3)) +#define UART_FORCE_XOFF_V 0x1 +#define UART_FORCE_XOFF_S 3 +/* UART_FORCE_XON : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear ctsn to stop the transmitter from sending data.*/ +#define UART_FORCE_XON (BIT(2)) +#define UART_FORCE_XON_M (BIT(2)) +#define UART_FORCE_XON_V 0x1 +#define UART_FORCE_XON_S 2 +/* UART_XONOFF_DEL : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to remove flow control char from the received data.*/ +#define UART_XONOFF_DEL (BIT(1)) +#define UART_XONOFF_DEL_M (BIT(1)) +#define UART_XONOFF_DEL_V 0x1 +#define UART_XONOFF_DEL_S 1 +/* UART_SW_FLOW_CON_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to enable software flow control. it is used with + register sw_xon or sw_xoff .*/ +#define UART_SW_FLOW_CON_EN (BIT(0)) +#define UART_SW_FLOW_CON_EN_M (BIT(0)) +#define UART_SW_FLOW_CON_EN_V 0x1 +#define UART_SW_FLOW_CON_EN_S 0 + +#define UART_SLEEP_CONF_REG(i) (REG_UART_BASE(i) + 0x38) +/* UART_ACTIVE_THRESHOLD : R/W ;bitpos:[9:0] ;default: 10'hf0 ; */ +/*description: When the input rxd edge changes more than this register value. + the uart is active from light sleeping mode.*/ +#define UART_ACTIVE_THRESHOLD 0x000003FF +#define UART_ACTIVE_THRESHOLD_M ((UART_ACTIVE_THRESHOLD_V)<<(UART_ACTIVE_THRESHOLD_S)) +#define UART_ACTIVE_THRESHOLD_V 0x3FF +#define UART_ACTIVE_THRESHOLD_S 0 + +#define UART_SWFC_CONF_REG(i) (REG_UART_BASE(i) + 0x3C) +/* UART_XOFF_CHAR : R/W ;bitpos:[31:24] ;default: 8'h13 ; */ +/*description: This register stores the xoff flow control char.*/ +#define UART_XOFF_CHAR 0x000000FF +#define UART_XOFF_CHAR_M ((UART_XOFF_CHAR_V)<<(UART_XOFF_CHAR_S)) +#define UART_XOFF_CHAR_V 0xFF +#define UART_XOFF_CHAR_S 24 +/* UART_XON_CHAR : R/W ;bitpos:[23:16] ;default: 8'h11 ; */ +/*description: This register stores the xon flow control char.*/ +#define UART_XON_CHAR 0x000000FF +#define UART_XON_CHAR_M ((UART_XON_CHAR_V)<<(UART_XON_CHAR_S)) +#define UART_XON_CHAR_V 0xFF +#define UART_XON_CHAR_S 16 +/* UART_XOFF_THRESHOLD : R/W ;bitpos:[15:8] ;default: 8'he0 ; */ +/*description: When the data amount in receiver's fifo is less than this register + value. it will send a xon char with uart_sw_flow_con_en set to 1.*/ +#define UART_XOFF_THRESHOLD 0x000000FF +#define UART_XOFF_THRESHOLD_M ((UART_XOFF_THRESHOLD_V)<<(UART_XOFF_THRESHOLD_S)) +#define UART_XOFF_THRESHOLD_V 0xFF +#define UART_XOFF_THRESHOLD_S 8 +/* UART_XON_THRESHOLD : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: when the data amount in receiver's fifo is more than this register + value. it will send a xoff char with uart_sw_flow_con_en set to 1.*/ +#define UART_XON_THRESHOLD 0x000000FF +#define UART_XON_THRESHOLD_M ((UART_XON_THRESHOLD_V)<<(UART_XON_THRESHOLD_S)) +#define UART_XON_THRESHOLD_V 0xFF +#define UART_XON_THRESHOLD_S 0 + +#define UART_IDLE_CONF_REG(i) (REG_UART_BASE(i) + 0x40) +/* UART_TX_BRK_NUM : R/W ;bitpos:[27:20] ;default: 8'ha ; */ +/*description: This register is used to configure the num of 0 send after the + process of sending data is done. it is active when txd_brk is set to 1.*/ +#define UART_TX_BRK_NUM 0x000000FF +#define UART_TX_BRK_NUM_M ((UART_TX_BRK_NUM_V)<<(UART_TX_BRK_NUM_S)) +#define UART_TX_BRK_NUM_V 0xFF +#define UART_TX_BRK_NUM_S 20 +/* UART_TX_IDLE_NUM : R/W ;bitpos:[19:10] ;default: 10'h100 ; */ +/*description: This register is used to configure the duration time between transfers.*/ +#define UART_TX_IDLE_NUM 0x000003FF +#define UART_TX_IDLE_NUM_M ((UART_TX_IDLE_NUM_V)<<(UART_TX_IDLE_NUM_S)) +#define UART_TX_IDLE_NUM_V 0x3FF +#define UART_TX_IDLE_NUM_S 10 +/* UART_RX_IDLE_THRHD : R/W ;bitpos:[9:0] ;default: 10'h100 ; */ +/*description: when receiver takes more time than this register value to receive + a byte data. it will produce frame end signal for uhci to stop receiving data.*/ +#define UART_RX_IDLE_THRHD 0x000003FF +#define UART_RX_IDLE_THRHD_M ((UART_RX_IDLE_THRHD_V)<<(UART_RX_IDLE_THRHD_S)) +#define UART_RX_IDLE_THRHD_V 0x3FF +#define UART_RX_IDLE_THRHD_S 0 + +#define UART_RS485_CONF_REG(i) (REG_UART_BASE(i) + 0x44) +/* UART_RS485_TX_DLY_NUM : R/W ;bitpos:[9:6] ;default: 4'b0 ; */ +/*description: This register is used to delay the transmitter's internal data signal.*/ +#define UART_RS485_TX_DLY_NUM 0x0000000F +#define UART_RS485_TX_DLY_NUM_M ((UART_RS485_TX_DLY_NUM_V)<<(UART_RS485_TX_DLY_NUM_S)) +#define UART_RS485_TX_DLY_NUM_V 0xF +#define UART_RS485_TX_DLY_NUM_S 6 +/* UART_RS485_RX_DLY_NUM : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This register is used to delay the receiver's internal data signal.*/ +#define UART_RS485_RX_DLY_NUM (BIT(5)) +#define UART_RS485_RX_DLY_NUM_M (BIT(5)) +#define UART_RS485_RX_DLY_NUM_V 0x1 +#define UART_RS485_RX_DLY_NUM_S 5 +/* UART_RS485RXBY_TX_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: 1: enable rs485's transmitter to send data when rs485's receiver + is busy. 0:rs485's transmitter should not send data when its receiver is busy.*/ +#define UART_RS485RXBY_TX_EN (BIT(4)) +#define UART_RS485RXBY_TX_EN_M (BIT(4)) +#define UART_RS485RXBY_TX_EN_V 0x1 +#define UART_RS485RXBY_TX_EN_S 4 +/* UART_RS485TX_RX_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to enable loopback transmitter's output data signal + to receiver's input data signal.*/ +#define UART_RS485TX_RX_EN (BIT(3)) +#define UART_RS485TX_RX_EN_M (BIT(3)) +#define UART_RS485TX_RX_EN_V 0x1 +#define UART_RS485TX_RX_EN_S 3 +/* UART_DL1_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to delay the stop bit by 1 bit.*/ +#define UART_DL1_EN (BIT(2)) +#define UART_DL1_EN_M (BIT(2)) +#define UART_DL1_EN_V 0x1 +#define UART_DL1_EN_S 2 +/* UART_DL0_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to delay the stop bit by 1 bit.*/ +#define UART_DL0_EN (BIT(1)) +#define UART_DL0_EN_M (BIT(1)) +#define UART_DL0_EN_V 0x1 +#define UART_DL0_EN_S 1 +/* UART_RS485_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to choose rs485 mode.*/ +#define UART_RS485_EN (BIT(0)) +#define UART_RS485_EN_M (BIT(0)) +#define UART_RS485_EN_V 0x1 +#define UART_RS485_EN_S 0 + +#define UART_AT_CMD_PRECNT_REG(i) (REG_UART_BASE(i) + 0x48) +/* UART_PRE_IDLE_NUM : R/W ;bitpos:[23:0] ;default: 24'h186a00 ; */ +/*description: This register is used to configure the idle duration time before + the first at_cmd is received by receiver. when the the duration is less than this register value it will not take the next data received as at_cmd char.*/ +#define UART_PRE_IDLE_NUM 0x00FFFFFF +#define UART_PRE_IDLE_NUM_M ((UART_PRE_IDLE_NUM_V)<<(UART_PRE_IDLE_NUM_S)) +#define UART_PRE_IDLE_NUM_V 0xFFFFFF +#define UART_PRE_IDLE_NUM_S 0 + +#define UART_AT_CMD_POSTCNT_REG(i) (REG_UART_BASE(i) + 0x4c) +/* UART_POST_IDLE_NUM : R/W ;bitpos:[23:0] ;default: 24'h186a00 ; */ +/*description: This register is used to configure the duration time between + the last at_cmd and the next data. when the duration is less than this register value it will not take the previous data as at_cmd char.*/ +#define UART_POST_IDLE_NUM 0x00FFFFFF +#define UART_POST_IDLE_NUM_M ((UART_POST_IDLE_NUM_V)<<(UART_POST_IDLE_NUM_S)) +#define UART_POST_IDLE_NUM_V 0xFFFFFF +#define UART_POST_IDLE_NUM_S 0 + +#define UART_AT_CMD_GAPTOUT_REG(i) (REG_UART_BASE(i) + 0x50) +/* UART_RX_GAP_TOUT : R/W ;bitpos:[23:0] ;default: 24'h1e00 ; */ +/*description: This register is used to configure the duration time between + the at_cmd chars. when the duration time is less than this register value it will not take the datas as continous at_cmd chars.*/ +#define UART_RX_GAP_TOUT 0x00FFFFFF +#define UART_RX_GAP_TOUT_M ((UART_RX_GAP_TOUT_V)<<(UART_RX_GAP_TOUT_S)) +#define UART_RX_GAP_TOUT_V 0xFFFFFF +#define UART_RX_GAP_TOUT_S 0 + +#define UART_AT_CMD_CHAR_REG(i) (REG_UART_BASE(i) + 0x54) +/* UART_CHAR_NUM : R/W ;bitpos:[15:8] ;default: 8'h3 ; */ +/*description: This register is used to configure the num of continous at_cmd + chars received by receiver.*/ +#define UART_CHAR_NUM 0x000000FF +#define UART_CHAR_NUM_M ((UART_CHAR_NUM_V)<<(UART_CHAR_NUM_S)) +#define UART_CHAR_NUM_V 0xFF +#define UART_CHAR_NUM_S 8 +/* UART_AT_CMD_CHAR : R/W ;bitpos:[7:0] ;default: 8'h2b ; */ +/*description: This register is used to configure the content of at_cmd char.*/ +#define UART_AT_CMD_CHAR 0x000000FF +#define UART_AT_CMD_CHAR_M ((UART_AT_CMD_CHAR_V)<<(UART_AT_CMD_CHAR_S)) +#define UART_AT_CMD_CHAR_V 0xFF +#define UART_AT_CMD_CHAR_S 0 + +#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x58) +/* UART_TX_MEM_EMPTY_THRHD : R/W ;bitpos:[30:28] ;default: 3'h0 ; */ +/*description: refer to txfifo_empty_thrhd 's describtion.*/ +#define UART_TX_MEM_EMPTY_THRHD 0x00000007 +#define UART_TX_MEM_EMPTY_THRHD_M ((UART_TX_MEM_EMPTY_THRHD_V)<<(UART_TX_MEM_EMPTY_THRHD_S)) +#define UART_TX_MEM_EMPTY_THRHD_V 0x7 +#define UART_TX_MEM_EMPTY_THRHD_S 28 +/* UART_RX_MEM_FULL_THRHD : R/W ;bitpos:[27:25] ;default: 3'h0 ; */ +/*description: refer to the rxfifo_full_thrhd's describtion.*/ +#define UART_RX_MEM_FULL_THRHD 0x00000007 +#define UART_RX_MEM_FULL_THRHD_M ((UART_RX_MEM_FULL_THRHD_V)<<(UART_RX_MEM_FULL_THRHD_S)) +#define UART_RX_MEM_FULL_THRHD_V 0x7 +#define UART_RX_MEM_FULL_THRHD_S 25 +/* UART_XOFF_THRESHOLD_H2 : R/W ;bitpos:[24:23] ;default: 2'h0 ; */ +/*description: refer to the uart_xoff_threshold's describtion.*/ +#define UART_XOFF_THRESHOLD_H2 0x00000003 +#define UART_XOFF_THRESHOLD_H2_M ((UART_XOFF_THRESHOLD_H2_V)<<(UART_XOFF_THRESHOLD_H2_S)) +#define UART_XOFF_THRESHOLD_H2_V 0x3 +#define UART_XOFF_THRESHOLD_H2_S 23 +/* UART_XON_THRESHOLD_H2 : R/W ;bitpos:[22:21] ;default: 2'h0 ; */ +/*description: refer to the uart_xon_threshold's describtion.*/ +#define UART_XON_THRESHOLD_H2 0x00000003 +#define UART_XON_THRESHOLD_H2_M ((UART_XON_THRESHOLD_H2_V)<<(UART_XON_THRESHOLD_H2_S)) +#define UART_XON_THRESHOLD_H2_V 0x3 +#define UART_XON_THRESHOLD_H2_S 21 +/* UART_RX_TOUT_THRHD_H3 : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ +/*description: refer to the rx_tout_thrhd's describtion.*/ +#define UART_RX_TOUT_THRHD_H3 0x00000007 +#define UART_RX_TOUT_THRHD_H3_M ((UART_RX_TOUT_THRHD_H3_V)<<(UART_RX_TOUT_THRHD_H3_S)) +#define UART_RX_TOUT_THRHD_H3_V 0x7 +#define UART_RX_TOUT_THRHD_H3_S 18 +/* UART_RX_FLOW_THRHD_H3 : R/W ;bitpos:[17:15] ;default: 3'h0 ; */ +/*description: refer to the rx_flow_thrhd's describtion.*/ +#define UART_RX_FLOW_THRHD_H3 0x00000007 +#define UART_RX_FLOW_THRHD_H3_M ((UART_RX_FLOW_THRHD_H3_V)<<(UART_RX_FLOW_THRHD_H3_S)) +#define UART_RX_FLOW_THRHD_H3_V 0x7 +#define UART_RX_FLOW_THRHD_H3_S 15 +/* UART_TX_SIZE : R/W ;bitpos:[10:7] ;default: 4'h1 ; */ +/*description: This register is used to configure the amount of mem allocated + to transmitter's fifo.the default byte num is 128.*/ +#define UART_TX_SIZE 0x0000000F +#define UART_TX_SIZE_M ((UART_TX_SIZE_V)<<(UART_TX_SIZE_S)) +#define UART_TX_SIZE_V 0xF +#define UART_TX_SIZE_S 7 +/* UART_RX_SIZE : R/W ;bitpos:[6:3] ;default: 4'h1 ; */ +/*description: This register is used to configure the amount of mem allocated + to receiver's fifo. the default byte num is 128.*/ +#define UART_RX_SIZE 0x0000000F +#define UART_RX_SIZE_M ((UART_RX_SIZE_V)<<(UART_RX_SIZE_S)) +#define UART_RX_SIZE_V 0xF +#define UART_RX_SIZE_S 3 +/* UART_MEM_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to power down mem.when reg_mem_pd registers in + the 3 uarts are all set to 1 mem will enter low power mode.*/ +#define UART_MEM_PD (BIT(0)) +#define UART_MEM_PD_M (BIT(0)) +#define UART_MEM_PD_V 0x1 +#define UART_MEM_PD_S 0 + +#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x5c) +/* UART_MEM_TX_STATUS : RO ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: */ +#define UART_MEM_TX_STATUS 0x00FFFFFF +#define UART_MEM_TX_STATUS_M ((UART_MEM_TX_STATUS_V)<<(UART_MEM_TX_STATUS_S)) +#define UART_MEM_TX_STATUS_V 0xFFFFFF +#define UART_MEM_TX_STATUS_S 0 + +#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x60) +/* UART_MEM_RX_STATUS : RO ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: */ +#define UART_MEM_RX_STATUS 0x00FFFFFF +#define UART_MEM_RX_STATUS_M ((UART_MEM_RX_STATUS_V)<<(UART_MEM_RX_STATUS_S)) +#define UART_MEM_RX_STATUS_V 0xFFFFFF +#define UART_MEM_RX_STATUS_S 0 + +#define UART_MEM_CNT_STATUS_REG(i) (REG_UART_BASE(i) + 0x64) +/* UART_TX_MEM_CNT : RO ;bitpos:[5:3] ;default: 3'b0 ; */ +/*description: refer to the txfifo_cnt's describtion.*/ +#define UART_TX_MEM_CNT 0x00000007 +#define UART_TX_MEM_CNT_M ((UART_TX_MEM_CNT_V)<<(UART_TX_MEM_CNT_S)) +#define UART_TX_MEM_CNT_V 0x7 +#define UART_TX_MEM_CNT_S 3 +/* UART_RX_MEM_CNT : RO ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: refer to the rxfifo_cnt's describtion.*/ +#define UART_RX_MEM_CNT 0x00000007 +#define UART_RX_MEM_CNT_M ((UART_RX_MEM_CNT_V)<<(UART_RX_MEM_CNT_S)) +#define UART_RX_MEM_CNT_V 0x7 +#define UART_RX_MEM_CNT_S 0 + +#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x68) +/* UART_POSEDGE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */ +/*description: This register stores the count of rxd posedge edge. it is used + in boudrate-detect process.*/ +#define UART_POSEDGE_MIN_CNT 0x000FFFFF +#define UART_POSEDGE_MIN_CNT_M ((UART_POSEDGE_MIN_CNT_V)<<(UART_POSEDGE_MIN_CNT_S)) +#define UART_POSEDGE_MIN_CNT_V 0xFFFFF +#define UART_POSEDGE_MIN_CNT_S 0 + +#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x6c) +/* UART_NEGEDGE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */ +/*description: This register stores the count of rxd negedge edge. it is used + in boudrate-detect process.*/ +#define UART_NEGEDGE_MIN_CNT 0x000FFFFF +#define UART_NEGEDGE_MIN_CNT_M ((UART_NEGEDGE_MIN_CNT_V)<<(UART_NEGEDGE_MIN_CNT_S)) +#define UART_NEGEDGE_MIN_CNT_V 0xFFFFF +#define UART_NEGEDGE_MIN_CNT_S 0 + +#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x78) +/* UART_DATE : R/W ;bitpos:[31:0] ;default: 32'h15122500 ; */ +/*description: */ +#define UART_DATE 0xFFFFFFFF +#define UART_DATE_M ((UART_DATE_V)<<(UART_DATE_S)) +#define UART_DATE_V 0xFFFFFFFF +#define UART_DATE_S 0 + +#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x7C) +/* UART_ID : R/W ;bitpos:[31:0] ;default: 32'h0500 ; */ +/*description: */ +#define UART_ID 0xFFFFFFFF +#define UART_ID_M ((UART_ID_V)<<(UART_ID_S)) +#define UART_ID_V 0xFFFFFFFF +#define UART_ID_S 0 + + + + +#endif /*__UART_REG_H__ */ + + diff --git a/tools/sdk/include/esp32/soc/uart_struct.h b/tools/sdk/include/esp32/soc/uart_struct.h new file mode 100644 index 00000000..05b54867 --- /dev/null +++ b/tools/sdk/include/esp32/soc/uart_struct.h @@ -0,0 +1,365 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_UART_STRUCT_H_ +#define _SOC_UART_STRUCT_H_ +typedef volatile struct { + union { + struct { + uint8_t rw_byte; /*This register stores one byte data read by rx fifo.*/ + uint8_t reserved[3]; + }; + uint32_t val; + } fifo; + union { + struct { + uint32_t rxfifo_full: 1; /*This interrupt raw bit turns to high level when receiver receives more data than (rx_flow_thrhd_h3 rx_flow_thrhd).*/ + uint32_t txfifo_empty: 1; /*This interrupt raw bit turns to high level when the amount of data in transmitter's fifo is less than ((tx_mem_cnttxfifo_cnt) .*/ + uint32_t parity_err: 1; /*This interrupt raw bit turns to high level when receiver detects the parity error of data.*/ + uint32_t frm_err: 1; /*This interrupt raw bit turns to high level when receiver detects data's frame error .*/ + uint32_t rxfifo_ovf: 1; /*This interrupt raw bit turns to high level when receiver receives more data than the fifo can store.*/ + uint32_t dsr_chg: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of dsrn signal.*/ + uint32_t cts_chg: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of ctsn signal.*/ + uint32_t brk_det: 1; /*This interrupt raw bit turns to high level when receiver detects the 0 after the stop bit.*/ + uint32_t rxfifo_tout: 1; /*This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.*/ + uint32_t sw_xon: 1; /*This interrupt raw bit turns to high level when receiver receives xoff char with uart_sw_flow_con_en is set to 1.*/ + uint32_t sw_xoff: 1; /*This interrupt raw bit turns to high level when receiver receives xon char with uart_sw_flow_con_en is set to 1.*/ + uint32_t glitch_det: 1; /*This interrupt raw bit turns to high level when receiver detects the start bit.*/ + uint32_t tx_brk_done: 1; /*This interrupt raw bit turns to high level when transmitter completes sending 0 after all the data in transmitter's fifo are send.*/ + uint32_t tx_brk_idle_done: 1; /*This interrupt raw bit turns to high level when transmitter has kept the shortest duration after the last data has been send.*/ + uint32_t tx_done: 1; /*This interrupt raw bit turns to high level when transmitter has send all the data in fifo.*/ + uint32_t rs485_parity_err: 1; /*This interrupt raw bit turns to high level when rs485 detects the parity error.*/ + uint32_t rs485_frm_err: 1; /*This interrupt raw bit turns to high level when rs485 detects the data frame error.*/ + uint32_t rs485_clash: 1; /*This interrupt raw bit turns to high level when rs485 detects the clash between transmitter and receiver.*/ + uint32_t at_cmd_char_det: 1; /*This interrupt raw bit turns to high level when receiver detects the configured at_cmd chars.*/ + uint32_t reserved19: 13; + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t rxfifo_full: 1; /*This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.*/ + uint32_t txfifo_empty: 1; /*This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1.*/ + uint32_t parity_err: 1; /*This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.*/ + uint32_t frm_err: 1; /*This is the status bit for frm_err_int_raw when fm_err_int_ena is set to 1.*/ + uint32_t rxfifo_ovf: 1; /*This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.*/ + uint32_t dsr_chg: 1; /*This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/ + uint32_t cts_chg: 1; /*This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/ + uint32_t brk_det: 1; /*This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/ + uint32_t rxfifo_tout: 1; /*This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.*/ + uint32_t sw_xon: 1; /*This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/ + uint32_t sw_xoff: 1; /*This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/ + uint32_t glitch_det: 1; /*This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.*/ + uint32_t tx_brk_done: 1; /*This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.*/ + uint32_t tx_brk_idle_done: 1; /*This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/ + uint32_t tx_done: 1; /*This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/ + uint32_t rs485_parity_err: 1; /*This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.*/ + uint32_t rs485_frm_err: 1; /*This is the status bit for rs485_fm_err_int_raw when rs485_fm_err_int_ena is set to 1.*/ + uint32_t rs485_clash: 1; /*This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.*/ + uint32_t at_cmd_char_det: 1; /*This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.*/ + uint32_t reserved19: 13; + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t rxfifo_full: 1; /*This is the enable bit for rxfifo_full_int_st register.*/ + uint32_t txfifo_empty: 1; /*This is the enable bit for rxfifo_full_int_st register.*/ + uint32_t parity_err: 1; /*This is the enable bit for parity_err_int_st register.*/ + uint32_t frm_err: 1; /*This is the enable bit for frm_err_int_st register.*/ + uint32_t rxfifo_ovf: 1; /*This is the enable bit for rxfifo_ovf_int_st register.*/ + uint32_t dsr_chg: 1; /*This is the enable bit for dsr_chg_int_st register.*/ + uint32_t cts_chg: 1; /*This is the enable bit for cts_chg_int_st register.*/ + uint32_t brk_det: 1; /*This is the enable bit for brk_det_int_st register.*/ + uint32_t rxfifo_tout: 1; /*This is the enable bit for rxfifo_tout_int_st register.*/ + uint32_t sw_xon: 1; /*This is the enable bit for sw_xon_int_st register.*/ + uint32_t sw_xoff: 1; /*This is the enable bit for sw_xoff_int_st register.*/ + uint32_t glitch_det: 1; /*This is the enable bit for glitch_det_int_st register.*/ + uint32_t tx_brk_done: 1; /*This is the enable bit for tx_brk_done_int_st register.*/ + uint32_t tx_brk_idle_done: 1; /*This is the enable bit for tx_brk_idle_done_int_st register.*/ + uint32_t tx_done: 1; /*This is the enable bit for tx_done_int_st register.*/ + uint32_t rs485_parity_err: 1; /*This is the enable bit for rs485_parity_err_int_st register.*/ + uint32_t rs485_frm_err: 1; /*This is the enable bit for rs485_parity_err_int_st register.*/ + uint32_t rs485_clash: 1; /*This is the enable bit for rs485_clash_int_st register.*/ + uint32_t at_cmd_char_det: 1; /*This is the enable bit for at_cmd_char_det_int_st register.*/ + uint32_t reserved19: 13; + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t rxfifo_full: 1; /*Set this bit to clear the rxfifo_full_int_raw interrupt.*/ + uint32_t txfifo_empty: 1; /*Set this bit to clear txfifo_empty_int_raw interrupt.*/ + uint32_t parity_err: 1; /*Set this bit to clear parity_err_int_raw interrupt.*/ + uint32_t frm_err: 1; /*Set this bit to clear frm_err_int_raw interrupt.*/ + uint32_t rxfifo_ovf: 1; /*Set this bit to clear rxfifo_ovf_int_raw interrupt.*/ + uint32_t dsr_chg: 1; /*Set this bit to clear the dsr_chg_int_raw interrupt.*/ + uint32_t cts_chg: 1; /*Set this bit to clear the cts_chg_int_raw interrupt.*/ + uint32_t brk_det: 1; /*Set this bit to clear the brk_det_int_raw interrupt.*/ + uint32_t rxfifo_tout: 1; /*Set this bit to clear the rxfifo_tout_int_raw interrupt.*/ + uint32_t sw_xon: 1; /*Set this bit to clear the sw_xon_int_raw interrupt.*/ + uint32_t sw_xoff: 1; /*Set this bit to clear the sw_xon_int_raw interrupt.*/ + uint32_t glitch_det: 1; /*Set this bit to clear the glitch_det_int_raw interrupt.*/ + uint32_t tx_brk_done: 1; /*Set this bit to clear the tx_brk_done_int_raw interrupt..*/ + uint32_t tx_brk_idle_done: 1; /*Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/ + uint32_t tx_done: 1; /*Set this bit to clear the tx_done_int_raw interrupt.*/ + uint32_t rs485_parity_err: 1; /*Set this bit to clear the rs485_parity_err_int_raw interrupt.*/ + uint32_t rs485_frm_err: 1; /*Set this bit to clear the rs485_frm_err_int_raw interrupt.*/ + uint32_t rs485_clash: 1; /*Set this bit to clear the rs485_clash_int_raw interrupt.*/ + uint32_t at_cmd_char_det: 1; /*Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/ + uint32_t reserved19: 13; + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t div_int: 20; /*The register value is the integer part of the frequency divider's factor.*/ + uint32_t div_frag: 4; /*The register value is the decimal part of the frequency divider's factor.*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } clk_div; + union { + struct { + uint32_t en: 1; /*This is the enable bit for detecting baudrate.*/ + uint32_t reserved1: 7; + uint32_t glitch_filt: 8; /*when input pulse width is lower then this value ignore this pulse.this register is used in auto-baud detect process.*/ + uint32_t reserved16: 16; + }; + uint32_t val; + } auto_baud; + union { + struct { + uint32_t rxfifo_cnt: 8; /*(rx_mem_cnt rxfifo_cnt) stores the byte number of valid data in receiver's fifo. rx_mem_cnt register stores the 3 most significant bits rxfifo_cnt stores the 8 least significant bits.*/ + uint32_t st_urx_out: 4; /*This register stores the value of receiver's finite state machine. 0:RX_IDLE 1:RX_STRT 2:RX_DAT0 3:RX_DAT1 4:RX_DAT2 5:RX_DAT3 6:RX_DAT4 7:RX_DAT5 8:RX_DAT6 9:RX_DAT7 10:RX_PRTY 11:RX_STP1 12:RX_STP2 13:RX_DL1*/ + uint32_t reserved12: 1; + uint32_t dsrn: 1; /*This register stores the level value of the internal uart dsr signal.*/ + uint32_t ctsn: 1; /*This register stores the level value of the internal uart cts signal.*/ + uint32_t rxd: 1; /*This register stores the level value of the internal uart rxd signal.*/ + uint32_t txfifo_cnt: 8; /*(tx_mem_cnt txfifo_cnt) stores the byte number of valid data in transmitter's fifo.tx_mem_cnt stores the 3 most significant bits txfifo_cnt stores the 8 least significant bits.*/ + uint32_t st_utx_out: 4; /*This register stores the value of transmitter's finite state machine. 0:TX_IDLE 1:TX_STRT 2:TX_DAT0 3:TX_DAT1 4:TX_DAT2 5:TX_DAT3 6:TX_DAT4 7:TX_DAT5 8:TX_DAT6 9:TX_DAT7 10:TX_PRTY 11:TX_STP1 12:TX_STP2 13:TX_DL0 14:TX_DL1*/ + uint32_t reserved28: 1; + uint32_t dtrn: 1; /*The register represent the level value of the internal uart dsr signal.*/ + uint32_t rtsn: 1; /*This register represent the level value of the internal uart cts signal.*/ + uint32_t txd: 1; /*This register represent the level value of the internal uart rxd signal.*/ + }; + uint32_t val; + } status; + union { + struct { + uint32_t parity: 1; /*This register is used to configure the parity check mode. 0:even 1:odd*/ + uint32_t parity_en: 1; /*Set this bit to enable uart parity check.*/ + uint32_t bit_num: 2; /*This register is used to set the length of data: 0:5bits 1:6bits 2:7bits 3:8bits*/ + uint32_t stop_bit_num: 2; /*This register is used to set the length of stop bit. 1:1bit 2:1.5bits 3:2bits*/ + uint32_t sw_rts: 1; /*This register is used to configure the software rts signal which is used in software flow control.*/ + uint32_t sw_dtr: 1; /*This register is used to configure the software dtr signal which is used in software flow control..*/ + uint32_t txd_brk: 1; /*Set this bit to enable transmitter to send 0 when the process of sending data is done.*/ + uint32_t irda_dplx: 1; /*Set this bit to enable irda loop-back mode.*/ + uint32_t irda_tx_en: 1; /*This is the start enable bit for irda transmitter.*/ + uint32_t irda_wctl: 1; /*1：the irda transmitter's 11th bit is the same to the 10th bit. 0：set irda transmitter's 11th bit to 0.*/ + uint32_t irda_tx_inv: 1; /*Set this bit to inverse the level value of irda transmitter's level.*/ + uint32_t irda_rx_inv: 1; /*Set this bit to inverse the level value of irda receiver's level.*/ + uint32_t loopback: 1; /*Set this bit to enable uart loop-back test mode.*/ + uint32_t tx_flow_en: 1; /*Set this bit to enable transmitter's flow control function.*/ + uint32_t irda_en: 1; /*Set this bit to enable irda protocol.*/ + uint32_t rxfifo_rst: 1; /*Set this bit to reset uart receiver's fifo.*/ + uint32_t txfifo_rst: 1; /*Set this bit to reset uart transmitter's fifo.*/ + uint32_t rxd_inv: 1; /*Set this bit to inverse the level value of uart rxd signal.*/ + uint32_t cts_inv: 1; /*Set this bit to inverse the level value of uart cts signal.*/ + uint32_t dsr_inv: 1; /*Set this bit to inverse the level value of uart dsr signal.*/ + uint32_t txd_inv: 1; /*Set this bit to inverse the level value of uart txd signal.*/ + uint32_t rts_inv: 1; /*Set this bit to inverse the level value of uart rts signal.*/ + uint32_t dtr_inv: 1; /*Set this bit to inverse the level value of uart dtr signal.*/ + uint32_t clk_en: 1; /*1：force clock on for registers：support clock only when write registers*/ + uint32_t err_wr_mask: 1; /*1：receiver stops storing data int fifo when data is wrong. 0：receiver stores the data even if the received data is wrong.*/ + uint32_t tick_ref_always_on: 1; /*This register is used to select the clock.1：apb clock：ref_tick*/ + uint32_t reserved28: 4; + }; + uint32_t val; + } conf0; + union { + struct { + uint32_t rxfifo_full_thrhd: 7; /*When receiver receives more data than its threshold value，receiver will produce rxfifo_full_int_raw interrupt.the threshold value is (rx_flow_thrhd_h3 rxfifo_full_thrhd).*/ + uint32_t reserved7: 1; + uint32_t txfifo_empty_thrhd: 7; /*when the data amount in transmitter fifo is less than its threshold value， it will produce txfifo_empty_int_raw interrupt. the threshold value is (tx_mem_empty_thrhd txfifo_empty_thrhd)*/ + uint32_t reserved15: 1; + uint32_t rx_flow_thrhd: 7; /*when receiver receives more data than its threshold value， receiver produce signal to tell the transmitter stop transferring data. the threshold value is (rx_flow_thrhd_h3 rx_flow_thrhd).*/ + uint32_t rx_flow_en: 1; /*This is the flow enable bit for uart receiver. 1:choose software flow control with configuring sw_rts signal*/ + uint32_t rx_tout_thrhd: 7; /*This register is used to configure the timeout value for uart receiver receiving a byte.*/ + uint32_t rx_tout_en: 1; /*This is the enable bit for uart receiver's timeout function.*/ + }; + uint32_t val; + } conf1; + union { + struct { + uint32_t min_cnt: 20; /*This register stores the value of the minimum duration time for the low level pulse， it is used in baudrate-detect process.*/ + uint32_t reserved20: 12; + }; + uint32_t val; + } lowpulse; + union { + struct { + uint32_t min_cnt: 20; /*This register stores the value of the maximum duration time for the high level pulse， it is used in baudrate-detect process.*/ + uint32_t reserved20: 12; + }; + uint32_t val; + } highpulse; + union { + struct { + uint32_t edge_cnt: 10; /*This register stores the count of rxd edge change， it is used in baudrate-detect process.*/ + uint32_t reserved10: 22; + }; + uint32_t val; + } rxd_cnt; + union { + struct { + uint32_t sw_flow_con_en: 1; /*Set this bit to enable software flow control. it is used with register sw_xon or sw_xoff .*/ + uint32_t xonoff_del: 1; /*Set this bit to remove flow control char from the received data.*/ + uint32_t force_xon: 1; /*Set this bit to clear ctsn to stop the transmitter from sending data.*/ + uint32_t force_xoff: 1; /*Set this bit to set ctsn to enable the transmitter to go on sending data.*/ + uint32_t send_xon: 1; /*Set this bit to send xon char， it is cleared by hardware automatically.*/ + uint32_t send_xoff: 1; /*Set this bit to send xoff char， it is cleared by hardware automatically.*/ + uint32_t reserved6: 26; + }; + uint32_t val; + } flow_conf; + union { + struct { + uint32_t active_threshold:10; /*When the input rxd edge changes more than this register value， the uart is active from light sleeping mode.*/ + uint32_t reserved10: 22; + }; + uint32_t val; + } sleep_conf; + union { + struct { + uint32_t xon_threshold: 8; /*when the data amount in receiver's fifo is more than this register value， it will send a xoff char with uart_sw_flow_con_en set to 1.*/ + uint32_t xoff_threshold: 8; /*When the data amount in receiver's fifo is less than this register value， it will send a xon char with uart_sw_flow_con_en set to 1.*/ + uint32_t xon_char: 8; /*This register stores the xon flow control char.*/ + uint32_t xoff_char: 8; /*This register stores the xoff flow control char.*/ + }; + uint32_t val; + } swfc_conf; + union { + struct { + uint32_t rx_idle_thrhd:10; /*when receiver takes more time than this register value to receive a byte data， it will produce frame end signal for uhci to stop receiving data.*/ + uint32_t tx_idle_num: 10; /*This register is used to configure the duration time between transfers.*/ + uint32_t tx_brk_num: 8; /*This register is used to configure the number of 0 send after the process of sending data is done. it is active when txd_brk is set to 1.*/ + uint32_t reserved28: 4; + }; + uint32_t val; + } idle_conf; + union { + struct { + uint32_t en: 1; /*Set this bit to choose rs485 mode.*/ + uint32_t dl0_en: 1; /*Set this bit to delay the stop bit by 1 bit.*/ + uint32_t dl1_en: 1; /*Set this bit to delay the stop bit by 1 bit.*/ + uint32_t tx_rx_en: 1; /*Set this bit to enable loop-back transmitter's output data signal to receiver's input data signal.*/ + uint32_t rx_busy_tx_en: 1; /*1: enable rs485's transmitter to send data when rs485's receiver is busy. 0:rs485's transmitter should not send data when its receiver is busy.*/ + uint32_t rx_dly_num: 1; /*This register is used to delay the receiver's internal data signal.*/ + uint32_t tx_dly_num: 4; /*This register is used to delay the transmitter's internal data signal.*/ + uint32_t reserved10: 22; + }; + uint32_t val; + } rs485_conf; + union { + struct { + uint32_t pre_idle_num:24; /*This register is used to configure the idle duration time before the first at_cmd is received by receiver， when the the duration is less than this register value it will not take the next data received as at_cmd char.*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } at_cmd_precnt; + union { + struct { + uint32_t post_idle_num:24; /*This register is used to configure the duration time between the last at_cmd and the next data， when the duration is less than this register value it will not take the previous data as at_cmd char.*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } at_cmd_postcnt; + union { + struct { + uint32_t rx_gap_tout:24; /*This register is used to configure the duration time between the at_cmd chars， when the duration time is less than this register value it will not take the data as continous at_cmd chars.*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } at_cmd_gaptout; + union { + struct { + uint32_t data: 8; /*This register is used to configure the content of at_cmd char.*/ + uint32_t char_num: 8; /*This register is used to configure the number of continuous at_cmd chars received by receiver.*/ + uint32_t reserved16: 16; + }; + uint32_t val; + } at_cmd_char; + union { + struct { + uint32_t mem_pd: 1; /*Set this bit to power down memory，when reg_mem_pd registers in the 3 uarts are all set to 1 memory will enter low power mode.*/ + uint32_t reserved1: 1; + uint32_t reserved2: 1; + uint32_t rx_size: 4; /*This register is used to configure the amount of mem allocated to receiver's fifo. the default byte num is 128.*/ + uint32_t tx_size: 4; /*This register is used to configure the amount of mem allocated to transmitter's fifo.the default byte num is 128.*/ + uint32_t reserved11: 4; + uint32_t rx_flow_thrhd_h3: 3; /*refer to the rx_flow_thrhd's description.*/ + uint32_t rx_tout_thrhd_h3: 3; /*refer to the rx_tout_thrhd's description.*/ + uint32_t xon_threshold_h2: 2; /*refer to the uart_xon_threshold's description.*/ + uint32_t xoff_threshold_h2: 2; /*refer to the uart_xoff_threshold's description.*/ + uint32_t rx_mem_full_thrhd: 3; /*refer to the rxfifo_full_thrhd's description.*/ + uint32_t tx_mem_empty_thrhd: 3; /*refer to txfifo_empty_thrhd 's description.*/ + uint32_t reserved31: 1; + }; + uint32_t val; + } mem_conf; + union { + struct { + uint32_t status:24; + uint32_t reserved24: 8; + }; + uint32_t val; + } mem_tx_status; + union { + struct { + uint32_t status:24; + uint32_t reserved24: 8; + }; + uint32_t val; + } mem_rx_status; + union { + struct { + uint32_t rx_cnt: 3; /*refer to the rxfifo_cnt's description.*/ + uint32_t tx_cnt: 3; /*refer to the txfifo_cnt's description.*/ + uint32_t reserved6: 26; + }; + uint32_t val; + } mem_cnt_status; + union { + struct { + uint32_t min_cnt: 20; /*This register stores the count of rxd pos-edge edge， it is used in baudrate-detect process.*/ + uint32_t reserved20: 12; + }; + uint32_t val; + } pospulse; + union { + struct { + uint32_t min_cnt: 20; /*This register stores the count of rxd neg-edge edge， it is used in baudrate-detect process.*/ + uint32_t reserved20: 12; + }; + uint32_t val; + } negpulse; + uint32_t reserved_70; + uint32_t reserved_74; + uint32_t date; /**/ + uint32_t id; /**/ +} uart_dev_t; +extern uart_dev_t UART0; +extern uart_dev_t UART1; +extern uart_dev_t UART2; +#endif /* _SOC_UART_STRUCT_H_ */ diff --git a/tools/sdk/include/esp32/soc/uhci_reg.h b/tools/sdk/include/esp32/soc/uhci_reg.h new file mode 100644 index 00000000..973c6b58 --- /dev/null +++ b/tools/sdk/include/esp32/soc/uhci_reg.h @@ -0,0 +1,1260 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_UHCI_REG_H_ +#define _SOC_UHCI_REG_H_ + + +#include "soc.h" +#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000) +#define UHCI_CONF0_REG(i) (REG_UHCI_BASE(i) + 0x0) +/* UHCI_UART_RX_BRK_EOF_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: Set this bit to enable to use brk char as the end of a data frame.*/ +#define UHCI_UART_RX_BRK_EOF_EN (BIT(23)) +#define UHCI_UART_RX_BRK_EOF_EN_M (BIT(23)) +#define UHCI_UART_RX_BRK_EOF_EN_V 0x1 +#define UHCI_UART_RX_BRK_EOF_EN_S 23 +/* UHCI_CLK_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Set this bit to enable clock-gating for read or write registers.*/ +#define UHCI_CLK_EN (BIT(22)) +#define UHCI_CLK_EN_M (BIT(22)) +#define UHCI_CLK_EN_V 0x1 +#define UHCI_CLK_EN_S 22 +/* UHCI_ENCODE_CRC_EN : R/W ;bitpos:[21] ;default: 1'b1 ; */ +/*description: Set this bit to enable crc calculation for data frame when bit6 + in the head packet is 1.*/ +#define UHCI_ENCODE_CRC_EN (BIT(21)) +#define UHCI_ENCODE_CRC_EN_M (BIT(21)) +#define UHCI_ENCODE_CRC_EN_V 0x1 +#define UHCI_ENCODE_CRC_EN_S 21 +/* UHCI_LEN_EOF_EN : R/W ;bitpos:[20] ;default: 1'b1 ; */ +/*description: Set this bit to enable to use packet_len in packet head when + the received data is equal to packet_len this means the end of a data frame.*/ +#define UHCI_LEN_EOF_EN (BIT(20)) +#define UHCI_LEN_EOF_EN_M (BIT(20)) +#define UHCI_LEN_EOF_EN_V 0x1 +#define UHCI_LEN_EOF_EN_S 20 +/* UHCI_UART_IDLE_EOF_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: Set this bit to enable to use idle time when the idle time after + data frame is satisfied this means the end of a data frame.*/ +#define UHCI_UART_IDLE_EOF_EN (BIT(19)) +#define UHCI_UART_IDLE_EOF_EN_M (BIT(19)) +#define UHCI_UART_IDLE_EOF_EN_V 0x1 +#define UHCI_UART_IDLE_EOF_EN_S 19 +/* UHCI_CRC_REC_EN : R/W ;bitpos:[18] ;default: 1'b1 ; */ +/*description: Set this bit to enable receiver''s ability of crc calculation + when crc_en bit in head packet is 1 then there will be crc bytes after data_frame*/ +#define UHCI_CRC_REC_EN (BIT(18)) +#define UHCI_CRC_REC_EN_M (BIT(18)) +#define UHCI_CRC_REC_EN_V 0x1 +#define UHCI_CRC_REC_EN_S 18 +/* UHCI_HEAD_EN : R/W ;bitpos:[17] ;default: 1'b1 ; */ +/*description: Set this bit to enable to use head packet before the data frame.*/ +#define UHCI_HEAD_EN (BIT(17)) +#define UHCI_HEAD_EN_M (BIT(17)) +#define UHCI_HEAD_EN_V 0x1 +#define UHCI_HEAD_EN_S 17 +/* UHCI_SEPER_EN : R/W ;bitpos:[16] ;default: 1'b1 ; */ +/*description: Set this bit to use special char to separate the data frame.*/ +#define UHCI_SEPER_EN (BIT(16)) +#define UHCI_SEPER_EN_M (BIT(16)) +#define UHCI_SEPER_EN_V 0x1 +#define UHCI_SEPER_EN_S 16 +/* UHCI_MEM_TRANS_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_MEM_TRANS_EN (BIT(15)) +#define UHCI_MEM_TRANS_EN_M (BIT(15)) +#define UHCI_MEM_TRANS_EN_V 0x1 +#define UHCI_MEM_TRANS_EN_S 15 +/* UHCI_OUT_DATA_BURST_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: Set this bit to enable DMA burst MODE*/ +#define UHCI_OUT_DATA_BURST_EN (BIT(14)) +#define UHCI_OUT_DATA_BURST_EN_M (BIT(14)) +#define UHCI_OUT_DATA_BURST_EN_V 0x1 +#define UHCI_OUT_DATA_BURST_EN_S 14 +/* UHCI_INDSCR_BURST_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Set this bit to enable DMA out links to use burst mode.*/ +#define UHCI_INDSCR_BURST_EN (BIT(13)) +#define UHCI_INDSCR_BURST_EN_M (BIT(13)) +#define UHCI_INDSCR_BURST_EN_V 0x1 +#define UHCI_INDSCR_BURST_EN_S 13 +/* UHCI_OUTDSCR_BURST_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to enable DMA in links to use burst mode.*/ +#define UHCI_OUTDSCR_BURST_EN (BIT(12)) +#define UHCI_OUTDSCR_BURST_EN_M (BIT(12)) +#define UHCI_OUTDSCR_BURST_EN_V 0x1 +#define UHCI_OUTDSCR_BURST_EN_S 12 +/* UHCI_UART2_CE : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Set this bit to use UART2 to transmit or receive data.*/ +#define UHCI_UART2_CE (BIT(11)) +#define UHCI_UART2_CE_M (BIT(11)) +#define UHCI_UART2_CE_V 0x1 +#define UHCI_UART2_CE_S 11 +/* UHCI_UART1_CE : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to use UART1 to transmit or receive data.*/ +#define UHCI_UART1_CE (BIT(10)) +#define UHCI_UART1_CE_M (BIT(10)) +#define UHCI_UART1_CE_V 0x1 +#define UHCI_UART1_CE_S 10 +/* UHCI_UART0_CE : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to use UART to transmit or receive data.*/ +#define UHCI_UART0_CE (BIT(9)) +#define UHCI_UART0_CE_M (BIT(9)) +#define UHCI_UART0_CE_V 0x1 +#define UHCI_UART0_CE_S 9 +/* UHCI_OUT_EOF_MODE : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: Set this bit to produce eof after DMA pops all data clear this + bit to produce eof after DMA pushes all data*/ +#define UHCI_OUT_EOF_MODE (BIT(8)) +#define UHCI_OUT_EOF_MODE_M (BIT(8)) +#define UHCI_OUT_EOF_MODE_V 0x1 +#define UHCI_OUT_EOF_MODE_S 8 +/* UHCI_OUT_NO_RESTART_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: don't use*/ +#define UHCI_OUT_NO_RESTART_CLR (BIT(7)) +#define UHCI_OUT_NO_RESTART_CLR_M (BIT(7)) +#define UHCI_OUT_NO_RESTART_CLR_V 0x1 +#define UHCI_OUT_NO_RESTART_CLR_S 7 +/* UHCI_OUT_AUTO_WRBACK : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: when in link's length is 0 go on to use the next in link automatically.*/ +#define UHCI_OUT_AUTO_WRBACK (BIT(6)) +#define UHCI_OUT_AUTO_WRBACK_M (BIT(6)) +#define UHCI_OUT_AUTO_WRBACK_V 0x1 +#define UHCI_OUT_AUTO_WRBACK_S 6 +/* UHCI_OUT_LOOP_TEST : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to enable loop test for out links.*/ +#define UHCI_OUT_LOOP_TEST (BIT(5)) +#define UHCI_OUT_LOOP_TEST_M (BIT(5)) +#define UHCI_OUT_LOOP_TEST_V 0x1 +#define UHCI_OUT_LOOP_TEST_S 5 +/* UHCI_IN_LOOP_TEST : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to enable loop test for in links.*/ +#define UHCI_IN_LOOP_TEST (BIT(4)) +#define UHCI_IN_LOOP_TEST_M (BIT(4)) +#define UHCI_IN_LOOP_TEST_V 0x1 +#define UHCI_IN_LOOP_TEST_S 4 +/* UHCI_AHBM_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to reset dma ahb interface.*/ +#define UHCI_AHBM_RST (BIT(3)) +#define UHCI_AHBM_RST_M (BIT(3)) +#define UHCI_AHBM_RST_V 0x1 +#define UHCI_AHBM_RST_S 3 +/* UHCI_AHBM_FIFO_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to reset dma ahb fifo.*/ +#define UHCI_AHBM_FIFO_RST (BIT(2)) +#define UHCI_AHBM_FIFO_RST_M (BIT(2)) +#define UHCI_AHBM_FIFO_RST_V 0x1 +#define UHCI_AHBM_FIFO_RST_S 2 +/* UHCI_OUT_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to reset out link operations.*/ +#define UHCI_OUT_RST (BIT(1)) +#define UHCI_OUT_RST_M (BIT(1)) +#define UHCI_OUT_RST_V 0x1 +#define UHCI_OUT_RST_S 1 +/* UHCI_IN_RST : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to reset in link operations.*/ +#define UHCI_IN_RST (BIT(0)) +#define UHCI_IN_RST_M (BIT(0)) +#define UHCI_IN_RST_V 0x1 +#define UHCI_IN_RST_S 0 + +#define UHCI_INT_RAW_REG(i) (REG_UHCI_BASE(i) + 0x4) +/* UHCI_DMA_INFIFO_FULL_WM_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_DMA_INFIFO_FULL_WM_INT_RAW (BIT(16)) +#define UHCI_DMA_INFIFO_FULL_WM_INT_RAW_M (BIT(16)) +#define UHCI_DMA_INFIFO_FULL_WM_INT_RAW_V 0x1 +#define UHCI_DMA_INFIFO_FULL_WM_INT_RAW_S 16 +/* UHCI_SEND_A_Q_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: When use always_send registers to send a series of short packets + it will produce this interrupt when dma has send the short packet.*/ +#define UHCI_SEND_A_Q_INT_RAW (BIT(15)) +#define UHCI_SEND_A_Q_INT_RAW_M (BIT(15)) +#define UHCI_SEND_A_Q_INT_RAW_V 0x1 +#define UHCI_SEND_A_Q_INT_RAW_S 15 +/* UHCI_SEND_S_Q_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: When use single send registers to send a short packets it will + produce this interrupt when dma has send the short packet.*/ +#define UHCI_SEND_S_Q_INT_RAW (BIT(14)) +#define UHCI_SEND_S_Q_INT_RAW_M (BIT(14)) +#define UHCI_SEND_S_Q_INT_RAW_V 0x1 +#define UHCI_SEND_S_Q_INT_RAW_S 14 +/* UHCI_OUT_TOTAL_EOF_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: When all data have been send it will produce uhci_out_total_eof_int interrupt.*/ +#define UHCI_OUT_TOTAL_EOF_INT_RAW (BIT(13)) +#define UHCI_OUT_TOTAL_EOF_INT_RAW_M (BIT(13)) +#define UHCI_OUT_TOTAL_EOF_INT_RAW_V 0x1 +#define UHCI_OUT_TOTAL_EOF_INT_RAW_S 13 +/* UHCI_OUTLINK_EOF_ERR_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: when there are some errors about eof in outlink descriptor it + will produce uhci_outlink_eof_err_int interrupt.*/ +#define UHCI_OUTLINK_EOF_ERR_INT_RAW (BIT(12)) +#define UHCI_OUTLINK_EOF_ERR_INT_RAW_M (BIT(12)) +#define UHCI_OUTLINK_EOF_ERR_INT_RAW_V 0x1 +#define UHCI_OUTLINK_EOF_ERR_INT_RAW_S 12 +/* UHCI_IN_DSCR_EMPTY_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: when there are not enough in links for DMA it will produce uhci_in_dscr_err_int + interrupt.*/ +#define UHCI_IN_DSCR_EMPTY_INT_RAW (BIT(11)) +#define UHCI_IN_DSCR_EMPTY_INT_RAW_M (BIT(11)) +#define UHCI_IN_DSCR_EMPTY_INT_RAW_V 0x1 +#define UHCI_IN_DSCR_EMPTY_INT_RAW_S 11 +/* UHCI_OUT_DSCR_ERR_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: when there are some errors about the in link descriptor it will + produce uhci_out_dscr_err_int interrupt.*/ +#define UHCI_OUT_DSCR_ERR_INT_RAW (BIT(10)) +#define UHCI_OUT_DSCR_ERR_INT_RAW_M (BIT(10)) +#define UHCI_OUT_DSCR_ERR_INT_RAW_V 0x1 +#define UHCI_OUT_DSCR_ERR_INT_RAW_S 10 +/* UHCI_IN_DSCR_ERR_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: when there are some errors about the out link descriptor it + will produce uhci_in_dscr_err_int interrupt.*/ +#define UHCI_IN_DSCR_ERR_INT_RAW (BIT(9)) +#define UHCI_IN_DSCR_ERR_INT_RAW_M (BIT(9)) +#define UHCI_IN_DSCR_ERR_INT_RAW_V 0x1 +#define UHCI_IN_DSCR_ERR_INT_RAW_S 9 +/* UHCI_OUT_EOF_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: when the current descriptor's eof bit is 1 it will produce uhci_out_eof_int + interrupt.*/ +#define UHCI_OUT_EOF_INT_RAW (BIT(8)) +#define UHCI_OUT_EOF_INT_RAW_M (BIT(8)) +#define UHCI_OUT_EOF_INT_RAW_V 0x1 +#define UHCI_OUT_EOF_INT_RAW_S 8 +/* UHCI_OUT_DONE_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: when a out link descriptor is completed it will produce uhci_out_done_int + interrupt.*/ +#define UHCI_OUT_DONE_INT_RAW (BIT(7)) +#define UHCI_OUT_DONE_INT_RAW_M (BIT(7)) +#define UHCI_OUT_DONE_INT_RAW_V 0x1 +#define UHCI_OUT_DONE_INT_RAW_S 7 +/* UHCI_IN_ERR_EOF_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: when there are some errors about eof in in link descriptor it + will produce uhci_in_err_eof_int interrupt.*/ +#define UHCI_IN_ERR_EOF_INT_RAW (BIT(6)) +#define UHCI_IN_ERR_EOF_INT_RAW_M (BIT(6)) +#define UHCI_IN_ERR_EOF_INT_RAW_V 0x1 +#define UHCI_IN_ERR_EOF_INT_RAW_S 6 +/* UHCI_IN_SUC_EOF_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: when a data packet has been received it will produce uhci_in_suc_eof_int + interrupt.*/ +#define UHCI_IN_SUC_EOF_INT_RAW (BIT(5)) +#define UHCI_IN_SUC_EOF_INT_RAW_M (BIT(5)) +#define UHCI_IN_SUC_EOF_INT_RAW_V 0x1 +#define UHCI_IN_SUC_EOF_INT_RAW_S 5 +/* UHCI_IN_DONE_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: when a in link descriptor has been completed it will produce + uhci_in_done_int interrupt.*/ +#define UHCI_IN_DONE_INT_RAW (BIT(4)) +#define UHCI_IN_DONE_INT_RAW_M (BIT(4)) +#define UHCI_IN_DONE_INT_RAW_V 0x1 +#define UHCI_IN_DONE_INT_RAW_S 4 +/* UHCI_TX_HUNG_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: when DMA takes a lot of time to read a data from RAM it will + produce uhci_tx_hung_int interrupt.*/ +#define UHCI_TX_HUNG_INT_RAW (BIT(3)) +#define UHCI_TX_HUNG_INT_RAW_M (BIT(3)) +#define UHCI_TX_HUNG_INT_RAW_V 0x1 +#define UHCI_TX_HUNG_INT_RAW_S 3 +/* UHCI_RX_HUNG_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: when DMA takes a lot of time to receive a data it will produce + uhci_rx_hung_int interrupt.*/ +#define UHCI_RX_HUNG_INT_RAW (BIT(2)) +#define UHCI_RX_HUNG_INT_RAW_M (BIT(2)) +#define UHCI_RX_HUNG_INT_RAW_V 0x1 +#define UHCI_RX_HUNG_INT_RAW_S 2 +/* UHCI_TX_START_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: when DMA detects a separator char it will produce uhci_tx_start_int interrupt.*/ +#define UHCI_TX_START_INT_RAW (BIT(1)) +#define UHCI_TX_START_INT_RAW_M (BIT(1)) +#define UHCI_TX_START_INT_RAW_V 0x1 +#define UHCI_TX_START_INT_RAW_S 1 +/* UHCI_RX_START_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: when a separator char has been send it will produce uhci_rx_start_int + interrupt.*/ +#define UHCI_RX_START_INT_RAW (BIT(0)) +#define UHCI_RX_START_INT_RAW_M (BIT(0)) +#define UHCI_RX_START_INT_RAW_V 0x1 +#define UHCI_RX_START_INT_RAW_S 0 + +#define UHCI_INT_ST_REG(i) (REG_UHCI_BASE(i) + 0x8) +/* UHCI_DMA_INFIFO_FULL_WM_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_DMA_INFIFO_FULL_WM_INT_ST (BIT(16)) +#define UHCI_DMA_INFIFO_FULL_WM_INT_ST_M (BIT(16)) +#define UHCI_DMA_INFIFO_FULL_WM_INT_ST_V 0x1 +#define UHCI_DMA_INFIFO_FULL_WM_INT_ST_S 16 +/* UHCI_SEND_A_Q_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_SEND_A_Q_INT_ST (BIT(15)) +#define UHCI_SEND_A_Q_INT_ST_M (BIT(15)) +#define UHCI_SEND_A_Q_INT_ST_V 0x1 +#define UHCI_SEND_A_Q_INT_ST_S 15 +/* UHCI_SEND_S_Q_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_SEND_S_Q_INT_ST (BIT(14)) +#define UHCI_SEND_S_Q_INT_ST_M (BIT(14)) +#define UHCI_SEND_S_Q_INT_ST_V 0x1 +#define UHCI_SEND_S_Q_INT_ST_S 14 +/* UHCI_OUT_TOTAL_EOF_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_OUT_TOTAL_EOF_INT_ST (BIT(13)) +#define UHCI_OUT_TOTAL_EOF_INT_ST_M (BIT(13)) +#define UHCI_OUT_TOTAL_EOF_INT_ST_V 0x1 +#define UHCI_OUT_TOTAL_EOF_INT_ST_S 13 +/* UHCI_OUTLINK_EOF_ERR_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_OUTLINK_EOF_ERR_INT_ST (BIT(12)) +#define UHCI_OUTLINK_EOF_ERR_INT_ST_M (BIT(12)) +#define UHCI_OUTLINK_EOF_ERR_INT_ST_V 0x1 +#define UHCI_OUTLINK_EOF_ERR_INT_ST_S 12 +/* UHCI_IN_DSCR_EMPTY_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_IN_DSCR_EMPTY_INT_ST (BIT(11)) +#define UHCI_IN_DSCR_EMPTY_INT_ST_M (BIT(11)) +#define UHCI_IN_DSCR_EMPTY_INT_ST_V 0x1 +#define UHCI_IN_DSCR_EMPTY_INT_ST_S 11 +/* UHCI_OUT_DSCR_ERR_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_OUT_DSCR_ERR_INT_ST (BIT(10)) +#define UHCI_OUT_DSCR_ERR_INT_ST_M (BIT(10)) +#define UHCI_OUT_DSCR_ERR_INT_ST_V 0x1 +#define UHCI_OUT_DSCR_ERR_INT_ST_S 10 +/* UHCI_IN_DSCR_ERR_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_IN_DSCR_ERR_INT_ST (BIT(9)) +#define UHCI_IN_DSCR_ERR_INT_ST_M (BIT(9)) +#define UHCI_IN_DSCR_ERR_INT_ST_V 0x1 +#define UHCI_IN_DSCR_ERR_INT_ST_S 9 +/* UHCI_OUT_EOF_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_OUT_EOF_INT_ST (BIT(8)) +#define UHCI_OUT_EOF_INT_ST_M (BIT(8)) +#define UHCI_OUT_EOF_INT_ST_V 0x1 +#define UHCI_OUT_EOF_INT_ST_S 8 +/* UHCI_OUT_DONE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_OUT_DONE_INT_ST (BIT(7)) +#define UHCI_OUT_DONE_INT_ST_M (BIT(7)) +#define UHCI_OUT_DONE_INT_ST_V 0x1 +#define UHCI_OUT_DONE_INT_ST_S 7 +/* UHCI_IN_ERR_EOF_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_IN_ERR_EOF_INT_ST (BIT(6)) +#define UHCI_IN_ERR_EOF_INT_ST_M (BIT(6)) +#define UHCI_IN_ERR_EOF_INT_ST_V 0x1 +#define UHCI_IN_ERR_EOF_INT_ST_S 6 +/* UHCI_IN_SUC_EOF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_IN_SUC_EOF_INT_ST (BIT(5)) +#define UHCI_IN_SUC_EOF_INT_ST_M (BIT(5)) +#define UHCI_IN_SUC_EOF_INT_ST_V 0x1 +#define UHCI_IN_SUC_EOF_INT_ST_S 5 +/* UHCI_IN_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_IN_DONE_INT_ST (BIT(4)) +#define UHCI_IN_DONE_INT_ST_M (BIT(4)) +#define UHCI_IN_DONE_INT_ST_V 0x1 +#define UHCI_IN_DONE_INT_ST_S 4 +/* UHCI_TX_HUNG_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_TX_HUNG_INT_ST (BIT(3)) +#define UHCI_TX_HUNG_INT_ST_M (BIT(3)) +#define UHCI_TX_HUNG_INT_ST_V 0x1 +#define UHCI_TX_HUNG_INT_ST_S 3 +/* UHCI_RX_HUNG_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_RX_HUNG_INT_ST (BIT(2)) +#define UHCI_RX_HUNG_INT_ST_M (BIT(2)) +#define UHCI_RX_HUNG_INT_ST_V 0x1 +#define UHCI_RX_HUNG_INT_ST_S 2 +/* UHCI_TX_START_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_TX_START_INT_ST (BIT(1)) +#define UHCI_TX_START_INT_ST_M (BIT(1)) +#define UHCI_TX_START_INT_ST_V 0x1 +#define UHCI_TX_START_INT_ST_S 1 +/* UHCI_RX_START_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_RX_START_INT_ST (BIT(0)) +#define UHCI_RX_START_INT_ST_M (BIT(0)) +#define UHCI_RX_START_INT_ST_V 0x1 +#define UHCI_RX_START_INT_ST_S 0 + +#define UHCI_INT_ENA_REG(i) (REG_UHCI_BASE(i) + 0xC) +/* UHCI_DMA_INFIFO_FULL_WM_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_DMA_INFIFO_FULL_WM_INT_ENA (BIT(16)) +#define UHCI_DMA_INFIFO_FULL_WM_INT_ENA_M (BIT(16)) +#define UHCI_DMA_INFIFO_FULL_WM_INT_ENA_V 0x1 +#define UHCI_DMA_INFIFO_FULL_WM_INT_ENA_S 16 +/* UHCI_SEND_A_Q_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_SEND_A_Q_INT_ENA (BIT(15)) +#define UHCI_SEND_A_Q_INT_ENA_M (BIT(15)) +#define UHCI_SEND_A_Q_INT_ENA_V 0x1 +#define UHCI_SEND_A_Q_INT_ENA_S 15 +/* UHCI_SEND_S_Q_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_SEND_S_Q_INT_ENA (BIT(14)) +#define UHCI_SEND_S_Q_INT_ENA_M (BIT(14)) +#define UHCI_SEND_S_Q_INT_ENA_V 0x1 +#define UHCI_SEND_S_Q_INT_ENA_S 14 +/* UHCI_OUT_TOTAL_EOF_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_OUT_TOTAL_EOF_INT_ENA (BIT(13)) +#define UHCI_OUT_TOTAL_EOF_INT_ENA_M (BIT(13)) +#define UHCI_OUT_TOTAL_EOF_INT_ENA_V 0x1 +#define UHCI_OUT_TOTAL_EOF_INT_ENA_S 13 +/* UHCI_OUTLINK_EOF_ERR_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_OUTLINK_EOF_ERR_INT_ENA (BIT(12)) +#define UHCI_OUTLINK_EOF_ERR_INT_ENA_M (BIT(12)) +#define UHCI_OUTLINK_EOF_ERR_INT_ENA_V 0x1 +#define UHCI_OUTLINK_EOF_ERR_INT_ENA_S 12 +/* UHCI_IN_DSCR_EMPTY_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_IN_DSCR_EMPTY_INT_ENA (BIT(11)) +#define UHCI_IN_DSCR_EMPTY_INT_ENA_M (BIT(11)) +#define UHCI_IN_DSCR_EMPTY_INT_ENA_V 0x1 +#define UHCI_IN_DSCR_EMPTY_INT_ENA_S 11 +/* UHCI_OUT_DSCR_ERR_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_OUT_DSCR_ERR_INT_ENA (BIT(10)) +#define UHCI_OUT_DSCR_ERR_INT_ENA_M (BIT(10)) +#define UHCI_OUT_DSCR_ERR_INT_ENA_V 0x1 +#define UHCI_OUT_DSCR_ERR_INT_ENA_S 10 +/* UHCI_IN_DSCR_ERR_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_IN_DSCR_ERR_INT_ENA (BIT(9)) +#define UHCI_IN_DSCR_ERR_INT_ENA_M (BIT(9)) +#define UHCI_IN_DSCR_ERR_INT_ENA_V 0x1 +#define UHCI_IN_DSCR_ERR_INT_ENA_S 9 +/* UHCI_OUT_EOF_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_OUT_EOF_INT_ENA (BIT(8)) +#define UHCI_OUT_EOF_INT_ENA_M (BIT(8)) +#define UHCI_OUT_EOF_INT_ENA_V 0x1 +#define UHCI_OUT_EOF_INT_ENA_S 8 +/* UHCI_OUT_DONE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_OUT_DONE_INT_ENA (BIT(7)) +#define UHCI_OUT_DONE_INT_ENA_M (BIT(7)) +#define UHCI_OUT_DONE_INT_ENA_V 0x1 +#define UHCI_OUT_DONE_INT_ENA_S 7 +/* UHCI_IN_ERR_EOF_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_IN_ERR_EOF_INT_ENA (BIT(6)) +#define UHCI_IN_ERR_EOF_INT_ENA_M (BIT(6)) +#define UHCI_IN_ERR_EOF_INT_ENA_V 0x1 +#define UHCI_IN_ERR_EOF_INT_ENA_S 6 +/* UHCI_IN_SUC_EOF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_IN_SUC_EOF_INT_ENA (BIT(5)) +#define UHCI_IN_SUC_EOF_INT_ENA_M (BIT(5)) +#define UHCI_IN_SUC_EOF_INT_ENA_V 0x1 +#define UHCI_IN_SUC_EOF_INT_ENA_S 5 +/* UHCI_IN_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_IN_DONE_INT_ENA (BIT(4)) +#define UHCI_IN_DONE_INT_ENA_M (BIT(4)) +#define UHCI_IN_DONE_INT_ENA_V 0x1 +#define UHCI_IN_DONE_INT_ENA_S 4 +/* UHCI_TX_HUNG_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_TX_HUNG_INT_ENA (BIT(3)) +#define UHCI_TX_HUNG_INT_ENA_M (BIT(3)) +#define UHCI_TX_HUNG_INT_ENA_V 0x1 +#define UHCI_TX_HUNG_INT_ENA_S 3 +/* UHCI_RX_HUNG_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_RX_HUNG_INT_ENA (BIT(2)) +#define UHCI_RX_HUNG_INT_ENA_M (BIT(2)) +#define UHCI_RX_HUNG_INT_ENA_V 0x1 +#define UHCI_RX_HUNG_INT_ENA_S 2 +/* UHCI_TX_START_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_TX_START_INT_ENA (BIT(1)) +#define UHCI_TX_START_INT_ENA_M (BIT(1)) +#define UHCI_TX_START_INT_ENA_V 0x1 +#define UHCI_TX_START_INT_ENA_S 1 +/* UHCI_RX_START_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_RX_START_INT_ENA (BIT(0)) +#define UHCI_RX_START_INT_ENA_M (BIT(0)) +#define UHCI_RX_START_INT_ENA_V 0x1 +#define UHCI_RX_START_INT_ENA_S 0 + +#define UHCI_INT_CLR_REG(i) (REG_UHCI_BASE(i) + 0x10) +/* UHCI_DMA_INFIFO_FULL_WM_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_DMA_INFIFO_FULL_WM_INT_CLR (BIT(16)) +#define UHCI_DMA_INFIFO_FULL_WM_INT_CLR_M (BIT(16)) +#define UHCI_DMA_INFIFO_FULL_WM_INT_CLR_V 0x1 +#define UHCI_DMA_INFIFO_FULL_WM_INT_CLR_S 16 +/* UHCI_SEND_A_Q_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_SEND_A_Q_INT_CLR (BIT(15)) +#define UHCI_SEND_A_Q_INT_CLR_M (BIT(15)) +#define UHCI_SEND_A_Q_INT_CLR_V 0x1 +#define UHCI_SEND_A_Q_INT_CLR_S 15 +/* UHCI_SEND_S_Q_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_SEND_S_Q_INT_CLR (BIT(14)) +#define UHCI_SEND_S_Q_INT_CLR_M (BIT(14)) +#define UHCI_SEND_S_Q_INT_CLR_V 0x1 +#define UHCI_SEND_S_Q_INT_CLR_S 14 +/* UHCI_OUT_TOTAL_EOF_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_OUT_TOTAL_EOF_INT_CLR (BIT(13)) +#define UHCI_OUT_TOTAL_EOF_INT_CLR_M (BIT(13)) +#define UHCI_OUT_TOTAL_EOF_INT_CLR_V 0x1 +#define UHCI_OUT_TOTAL_EOF_INT_CLR_S 13 +/* UHCI_OUTLINK_EOF_ERR_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_OUTLINK_EOF_ERR_INT_CLR (BIT(12)) +#define UHCI_OUTLINK_EOF_ERR_INT_CLR_M (BIT(12)) +#define UHCI_OUTLINK_EOF_ERR_INT_CLR_V 0x1 +#define UHCI_OUTLINK_EOF_ERR_INT_CLR_S 12 +/* UHCI_IN_DSCR_EMPTY_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_IN_DSCR_EMPTY_INT_CLR (BIT(11)) +#define UHCI_IN_DSCR_EMPTY_INT_CLR_M (BIT(11)) +#define UHCI_IN_DSCR_EMPTY_INT_CLR_V 0x1 +#define UHCI_IN_DSCR_EMPTY_INT_CLR_S 11 +/* UHCI_OUT_DSCR_ERR_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_OUT_DSCR_ERR_INT_CLR (BIT(10)) +#define UHCI_OUT_DSCR_ERR_INT_CLR_M (BIT(10)) +#define UHCI_OUT_DSCR_ERR_INT_CLR_V 0x1 +#define UHCI_OUT_DSCR_ERR_INT_CLR_S 10 +/* UHCI_IN_DSCR_ERR_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_IN_DSCR_ERR_INT_CLR (BIT(9)) +#define UHCI_IN_DSCR_ERR_INT_CLR_M (BIT(9)) +#define UHCI_IN_DSCR_ERR_INT_CLR_V 0x1 +#define UHCI_IN_DSCR_ERR_INT_CLR_S 9 +/* UHCI_OUT_EOF_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_OUT_EOF_INT_CLR (BIT(8)) +#define UHCI_OUT_EOF_INT_CLR_M (BIT(8)) +#define UHCI_OUT_EOF_INT_CLR_V 0x1 +#define UHCI_OUT_EOF_INT_CLR_S 8 +/* UHCI_OUT_DONE_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_OUT_DONE_INT_CLR (BIT(7)) +#define UHCI_OUT_DONE_INT_CLR_M (BIT(7)) +#define UHCI_OUT_DONE_INT_CLR_V 0x1 +#define UHCI_OUT_DONE_INT_CLR_S 7 +/* UHCI_IN_ERR_EOF_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_IN_ERR_EOF_INT_CLR (BIT(6)) +#define UHCI_IN_ERR_EOF_INT_CLR_M (BIT(6)) +#define UHCI_IN_ERR_EOF_INT_CLR_V 0x1 +#define UHCI_IN_ERR_EOF_INT_CLR_S 6 +/* UHCI_IN_SUC_EOF_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_IN_SUC_EOF_INT_CLR (BIT(5)) +#define UHCI_IN_SUC_EOF_INT_CLR_M (BIT(5)) +#define UHCI_IN_SUC_EOF_INT_CLR_V 0x1 +#define UHCI_IN_SUC_EOF_INT_CLR_S 5 +/* UHCI_IN_DONE_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_IN_DONE_INT_CLR (BIT(4)) +#define UHCI_IN_DONE_INT_CLR_M (BIT(4)) +#define UHCI_IN_DONE_INT_CLR_V 0x1 +#define UHCI_IN_DONE_INT_CLR_S 4 +/* UHCI_TX_HUNG_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_TX_HUNG_INT_CLR (BIT(3)) +#define UHCI_TX_HUNG_INT_CLR_M (BIT(3)) +#define UHCI_TX_HUNG_INT_CLR_V 0x1 +#define UHCI_TX_HUNG_INT_CLR_S 3 +/* UHCI_RX_HUNG_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_RX_HUNG_INT_CLR (BIT(2)) +#define UHCI_RX_HUNG_INT_CLR_M (BIT(2)) +#define UHCI_RX_HUNG_INT_CLR_V 0x1 +#define UHCI_RX_HUNG_INT_CLR_S 2 +/* UHCI_TX_START_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_TX_START_INT_CLR (BIT(1)) +#define UHCI_TX_START_INT_CLR_M (BIT(1)) +#define UHCI_TX_START_INT_CLR_V 0x1 +#define UHCI_TX_START_INT_CLR_S 1 +/* UHCI_RX_START_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_RX_START_INT_CLR (BIT(0)) +#define UHCI_RX_START_INT_CLR_M (BIT(0)) +#define UHCI_RX_START_INT_CLR_V 0x1 +#define UHCI_RX_START_INT_CLR_S 0 + +#define UHCI_DMA_OUT_STATUS_REG(i) (REG_UHCI_BASE(i) + 0x14) +/* UHCI_OUT_EMPTY : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: 1:DMA in link descriptor's fifo is empty.*/ +#define UHCI_OUT_EMPTY (BIT(1)) +#define UHCI_OUT_EMPTY_M (BIT(1)) +#define UHCI_OUT_EMPTY_V 0x1 +#define UHCI_OUT_EMPTY_S 1 +/* UHCI_OUT_FULL : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: 1:DMA out link descriptor's fifo is full.*/ +#define UHCI_OUT_FULL (BIT(0)) +#define UHCI_OUT_FULL_M (BIT(0)) +#define UHCI_OUT_FULL_V 0x1 +#define UHCI_OUT_FULL_S 0 + +#define UHCI_DMA_OUT_PUSH_REG(i) (REG_UHCI_BASE(i) + 0x18) +/* UHCI_OUTFIFO_PUSH : R/W ;bitpos:[16] ;default: 1'h0 ; */ +/*description: Set this bit to push data in out link descriptor's fifo.*/ +#define UHCI_OUTFIFO_PUSH (BIT(16)) +#define UHCI_OUTFIFO_PUSH_M (BIT(16)) +#define UHCI_OUTFIFO_PUSH_V 0x1 +#define UHCI_OUTFIFO_PUSH_S 16 +/* UHCI_OUTFIFO_WDATA : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ +/*description: This is the data need to be pushed into out link descriptor's fifo.*/ +#define UHCI_OUTFIFO_WDATA 0x000001FF +#define UHCI_OUTFIFO_WDATA_M ((UHCI_OUTFIFO_WDATA_V)<<(UHCI_OUTFIFO_WDATA_S)) +#define UHCI_OUTFIFO_WDATA_V 0x1FF +#define UHCI_OUTFIFO_WDATA_S 0 + +#define UHCI_DMA_IN_STATUS_REG(i) (REG_UHCI_BASE(i) + 0x1C) +/* UHCI_RX_ERR_CAUSE : RO ;bitpos:[6:4] ;default: 3'h0 ; */ +/*description: This register stores the errors caused in out link descriptor's data packet.*/ +#define UHCI_RX_ERR_CAUSE 0x00000007 +#define UHCI_RX_ERR_CAUSE_M ((UHCI_RX_ERR_CAUSE_V)<<(UHCI_RX_ERR_CAUSE_S)) +#define UHCI_RX_ERR_CAUSE_V 0x7 +#define UHCI_RX_ERR_CAUSE_S 4 +/* UHCI_IN_EMPTY : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: */ +#define UHCI_IN_EMPTY (BIT(1)) +#define UHCI_IN_EMPTY_M (BIT(1)) +#define UHCI_IN_EMPTY_V 0x1 +#define UHCI_IN_EMPTY_S 1 +/* UHCI_IN_FULL : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_IN_FULL (BIT(0)) +#define UHCI_IN_FULL_M (BIT(0)) +#define UHCI_IN_FULL_V 0x1 +#define UHCI_IN_FULL_S 0 + +#define UHCI_DMA_IN_POP_REG(i) (REG_UHCI_BASE(i) + 0x20) +/* UHCI_INFIFO_POP : R/W ;bitpos:[16] ;default: 1'h0 ; */ +/*description: Set this bit to pop data in in link descriptor's fifo.*/ +#define UHCI_INFIFO_POP (BIT(16)) +#define UHCI_INFIFO_POP_M (BIT(16)) +#define UHCI_INFIFO_POP_V 0x1 +#define UHCI_INFIFO_POP_S 16 +/* UHCI_INFIFO_RDATA : RO ;bitpos:[11:0] ;default: 12'h0 ; */ +/*description: This register stores the data pop from in link descriptor's fifo.*/ +#define UHCI_INFIFO_RDATA 0x00000FFF +#define UHCI_INFIFO_RDATA_M ((UHCI_INFIFO_RDATA_V)<<(UHCI_INFIFO_RDATA_S)) +#define UHCI_INFIFO_RDATA_V 0xFFF +#define UHCI_INFIFO_RDATA_S 0 + +#define UHCI_DMA_OUT_LINK_REG(i) (REG_UHCI_BASE(i) + 0x24) +/* UHCI_OUTLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */ +/*description: 1£º the out link descriptor's fsm is in idle state. 0:the out + link descriptor's fsm is working.*/ +#define UHCI_OUTLINK_PARK (BIT(31)) +#define UHCI_OUTLINK_PARK_M (BIT(31)) +#define UHCI_OUTLINK_PARK_V 0x1 +#define UHCI_OUTLINK_PARK_S 31 +/* UHCI_OUTLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Set this bit to mount on new out link descriptors*/ +#define UHCI_OUTLINK_RESTART (BIT(30)) +#define UHCI_OUTLINK_RESTART_M (BIT(30)) +#define UHCI_OUTLINK_RESTART_V 0x1 +#define UHCI_OUTLINK_RESTART_S 30 +/* UHCI_OUTLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Set this bit to start dealing with the out link descriptors.*/ +#define UHCI_OUTLINK_START (BIT(29)) +#define UHCI_OUTLINK_START_M (BIT(29)) +#define UHCI_OUTLINK_START_V 0x1 +#define UHCI_OUTLINK_START_S 29 +/* UHCI_OUTLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Set this bit to stop dealing with the out link descriptors.*/ +#define UHCI_OUTLINK_STOP (BIT(28)) +#define UHCI_OUTLINK_STOP_M (BIT(28)) +#define UHCI_OUTLINK_STOP_V 0x1 +#define UHCI_OUTLINK_STOP_S 28 +/* UHCI_OUTLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: This register stores the least 20 bits of the first out link + descriptor's address.*/ +#define UHCI_OUTLINK_ADDR 0x000FFFFF +#define UHCI_OUTLINK_ADDR_M ((UHCI_OUTLINK_ADDR_V)<<(UHCI_OUTLINK_ADDR_S)) +#define UHCI_OUTLINK_ADDR_V 0xFFFFF +#define UHCI_OUTLINK_ADDR_S 0 + +#define UHCI_DMA_IN_LINK_REG(i) (REG_UHCI_BASE(i) + 0x28) +/* UHCI_INLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */ +/*description: 1:the in link descriptor's fsm is in idle state. 0:the in link + descriptor's fsm is working*/ +#define UHCI_INLINK_PARK (BIT(31)) +#define UHCI_INLINK_PARK_M (BIT(31)) +#define UHCI_INLINK_PARK_V 0x1 +#define UHCI_INLINK_PARK_S 31 +/* UHCI_INLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Set this bit to mount on new in link descriptors*/ +#define UHCI_INLINK_RESTART (BIT(30)) +#define UHCI_INLINK_RESTART_M (BIT(30)) +#define UHCI_INLINK_RESTART_V 0x1 +#define UHCI_INLINK_RESTART_S 30 +/* UHCI_INLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Set this bit to start dealing with the in link descriptors.*/ +#define UHCI_INLINK_START (BIT(29)) +#define UHCI_INLINK_START_M (BIT(29)) +#define UHCI_INLINK_START_V 0x1 +#define UHCI_INLINK_START_S 29 +/* UHCI_INLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Set this bit to stop dealing with the in link descriptors.*/ +#define UHCI_INLINK_STOP (BIT(28)) +#define UHCI_INLINK_STOP_M (BIT(28)) +#define UHCI_INLINK_STOP_V 0x1 +#define UHCI_INLINK_STOP_S 28 +/* UHCI_INLINK_AUTO_RET : R/W ;bitpos:[20] ;default: 1'b1 ; */ +/*description: 1:when a packet is wrong in link descriptor returns to the descriptor + which is lately used.*/ +#define UHCI_INLINK_AUTO_RET (BIT(20)) +#define UHCI_INLINK_AUTO_RET_M (BIT(20)) +#define UHCI_INLINK_AUTO_RET_V 0x1 +#define UHCI_INLINK_AUTO_RET_S 20 +/* UHCI_INLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: This register stores the least 20 bits of the first in link descriptor's + address.*/ +#define UHCI_INLINK_ADDR 0x000FFFFF +#define UHCI_INLINK_ADDR_M ((UHCI_INLINK_ADDR_V)<<(UHCI_INLINK_ADDR_S)) +#define UHCI_INLINK_ADDR_V 0xFFFFF +#define UHCI_INLINK_ADDR_S 0 + +#define UHCI_CONF1_REG(i) (REG_UHCI_BASE(i) + 0x2C) +/* UHCI_DMA_INFIFO_FULL_THRS : R/W ;bitpos:[20:9] ;default: 12'b0 ; */ +/*description: when data amount in link descriptor's fifo is more than this + register value it will produce uhci_dma_infifo_full_wm_int interrupt.*/ +#define UHCI_DMA_INFIFO_FULL_THRS 0x00000FFF +#define UHCI_DMA_INFIFO_FULL_THRS_M ((UHCI_DMA_INFIFO_FULL_THRS_V)<<(UHCI_DMA_INFIFO_FULL_THRS_S)) +#define UHCI_DMA_INFIFO_FULL_THRS_V 0xFFF +#define UHCI_DMA_INFIFO_FULL_THRS_S 9 +/* UHCI_SW_START : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to start inserting the packet header.*/ +#define UHCI_SW_START (BIT(8)) +#define UHCI_SW_START_M (BIT(8)) +#define UHCI_SW_START_V 0x1 +#define UHCI_SW_START_S 8 +/* UHCI_WAIT_SW_START : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to enable software way to add packet header.*/ +#define UHCI_WAIT_SW_START (BIT(7)) +#define UHCI_WAIT_SW_START_M (BIT(7)) +#define UHCI_WAIT_SW_START_V 0x1 +#define UHCI_WAIT_SW_START_S 7 +/* UHCI_CHECK_OWNER : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to check the owner bit in link descriptor.*/ +#define UHCI_CHECK_OWNER (BIT(6)) +#define UHCI_CHECK_OWNER_M (BIT(6)) +#define UHCI_CHECK_OWNER_V 0x1 +#define UHCI_CHECK_OWNER_S 6 +/* UHCI_TX_ACK_NUM_RE : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: Set this bit to enable hardware replace ack num in packet header automatically.*/ +#define UHCI_TX_ACK_NUM_RE (BIT(5)) +#define UHCI_TX_ACK_NUM_RE_M (BIT(5)) +#define UHCI_TX_ACK_NUM_RE_V 0x1 +#define UHCI_TX_ACK_NUM_RE_S 5 +/* UHCI_TX_CHECK_SUM_RE : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: Set this bit to enable hardware replace check_sum in packet header + automatically.*/ +#define UHCI_TX_CHECK_SUM_RE (BIT(4)) +#define UHCI_TX_CHECK_SUM_RE_M (BIT(4)) +#define UHCI_TX_CHECK_SUM_RE_V 0x1 +#define UHCI_TX_CHECK_SUM_RE_S 4 +/* UHCI_SAVE_HEAD : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to save packet header .*/ +#define UHCI_SAVE_HEAD (BIT(3)) +#define UHCI_SAVE_HEAD_M (BIT(3)) +#define UHCI_SAVE_HEAD_V 0x1 +#define UHCI_SAVE_HEAD_S 3 +/* UHCI_CRC_DISABLE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to disable crc calculation.*/ +#define UHCI_CRC_DISABLE (BIT(2)) +#define UHCI_CRC_DISABLE_M (BIT(2)) +#define UHCI_CRC_DISABLE_V 0x1 +#define UHCI_CRC_DISABLE_S 2 +/* UHCI_CHECK_SEQ_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: Set this bit to enable decoder to check seq num in packet header.*/ +#define UHCI_CHECK_SEQ_EN (BIT(1)) +#define UHCI_CHECK_SEQ_EN_M (BIT(1)) +#define UHCI_CHECK_SEQ_EN_V 0x1 +#define UHCI_CHECK_SEQ_EN_S 1 +/* UHCI_CHECK_SUM_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: Set this bit to enable decoder to check check_sum in packet header.*/ +#define UHCI_CHECK_SUM_EN (BIT(0)) +#define UHCI_CHECK_SUM_EN_M (BIT(0)) +#define UHCI_CHECK_SUM_EN_V 0x1 +#define UHCI_CHECK_SUM_EN_S 0 + +#define UHCI_STATE0_REG(i) (REG_UHCI_BASE(i) + 0x30) +/* UHCI_STATE0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define UHCI_STATE0 0xFFFFFFFF +#define UHCI_STATE0_M ((UHCI_STATE0_V)<<(UHCI_STATE0_S)) +#define UHCI_STATE0_V 0xFFFFFFFF +#define UHCI_STATE0_S 0 + +#define UHCI_STATE1_REG(i) (REG_UHCI_BASE(i) + 0x34) +/* UHCI_STATE1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define UHCI_STATE1 0xFFFFFFFF +#define UHCI_STATE1_M ((UHCI_STATE1_V)<<(UHCI_STATE1_S)) +#define UHCI_STATE1_V 0xFFFFFFFF +#define UHCI_STATE1_S 0 + +#define UHCI_DMA_OUT_EOF_DES_ADDR_REG(i) (REG_UHCI_BASE(i) + 0x38) +/* UHCI_OUT_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of out link descriptoir when + eof bit in this descriptor is 1.*/ +#define UHCI_OUT_EOF_DES_ADDR 0xFFFFFFFF +#define UHCI_OUT_EOF_DES_ADDR_M ((UHCI_OUT_EOF_DES_ADDR_V)<<(UHCI_OUT_EOF_DES_ADDR_S)) +#define UHCI_OUT_EOF_DES_ADDR_V 0xFFFFFFFF +#define UHCI_OUT_EOF_DES_ADDR_S 0 + +#define UHCI_DMA_IN_SUC_EOF_DES_ADDR_REG(i) (REG_UHCI_BASE(i) + 0x3C) +/* UHCI_IN_SUC_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of in link descriptor when eof + bit in this descriptor is 1.*/ +#define UHCI_IN_SUC_EOF_DES_ADDR 0xFFFFFFFF +#define UHCI_IN_SUC_EOF_DES_ADDR_M ((UHCI_IN_SUC_EOF_DES_ADDR_V)<<(UHCI_IN_SUC_EOF_DES_ADDR_S)) +#define UHCI_IN_SUC_EOF_DES_ADDR_V 0xFFFFFFFF +#define UHCI_IN_SUC_EOF_DES_ADDR_S 0 + +#define UHCI_DMA_IN_ERR_EOF_DES_ADDR_REG(i) (REG_UHCI_BASE(i) + 0x40) +/* UHCI_IN_ERR_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of in link descriptor when there + are some errors in this descriptor.*/ +#define UHCI_IN_ERR_EOF_DES_ADDR 0xFFFFFFFF +#define UHCI_IN_ERR_EOF_DES_ADDR_M ((UHCI_IN_ERR_EOF_DES_ADDR_V)<<(UHCI_IN_ERR_EOF_DES_ADDR_S)) +#define UHCI_IN_ERR_EOF_DES_ADDR_V 0xFFFFFFFF +#define UHCI_IN_ERR_EOF_DES_ADDR_S 0 + +#define UHCI_DMA_OUT_EOF_BFR_DES_ADDR_REG(i) (REG_UHCI_BASE(i) + 0x44) +/* UHCI_OUT_EOF_BFR_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of out link descriptor when + there are some errors in this descriptor.*/ +#define UHCI_OUT_EOF_BFR_DES_ADDR 0xFFFFFFFF +#define UHCI_OUT_EOF_BFR_DES_ADDR_M ((UHCI_OUT_EOF_BFR_DES_ADDR_V)<<(UHCI_OUT_EOF_BFR_DES_ADDR_S)) +#define UHCI_OUT_EOF_BFR_DES_ADDR_V 0xFFFFFFFF +#define UHCI_OUT_EOF_BFR_DES_ADDR_S 0 + +#define UHCI_AHB_TEST_REG(i) (REG_UHCI_BASE(i) + 0x48) +/* UHCI_AHB_TESTADDR : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ +/*description: The two bits represent ahb bus address bit[20:19]*/ +#define UHCI_AHB_TESTADDR 0x00000003 +#define UHCI_AHB_TESTADDR_M ((UHCI_AHB_TESTADDR_V)<<(UHCI_AHB_TESTADDR_S)) +#define UHCI_AHB_TESTADDR_V 0x3 +#define UHCI_AHB_TESTADDR_S 4 +/* UHCI_AHB_TESTMODE : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: bit2 is ahb bus test enable ,bit1 is used to choose wrtie(1) + or read(0) mode. bit0 is used to choose test only once(1) or continue(0)*/ +#define UHCI_AHB_TESTMODE 0x00000007 +#define UHCI_AHB_TESTMODE_M ((UHCI_AHB_TESTMODE_V)<<(UHCI_AHB_TESTMODE_S)) +#define UHCI_AHB_TESTMODE_V 0x7 +#define UHCI_AHB_TESTMODE_S 0 + +#define UHCI_DMA_IN_DSCR_REG(i) (REG_UHCI_BASE(i) + 0x4C) +/* UHCI_INLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The content of current in link descriptor's third dword*/ +#define UHCI_INLINK_DSCR 0xFFFFFFFF +#define UHCI_INLINK_DSCR_M ((UHCI_INLINK_DSCR_V)<<(UHCI_INLINK_DSCR_S)) +#define UHCI_INLINK_DSCR_V 0xFFFFFFFF +#define UHCI_INLINK_DSCR_S 0 + +#define UHCI_DMA_IN_DSCR_BF0_REG(i) (REG_UHCI_BASE(i) + 0x50) +/* UHCI_INLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The content of current in link descriptor's first dword*/ +#define UHCI_INLINK_DSCR_BF0 0xFFFFFFFF +#define UHCI_INLINK_DSCR_BF0_M ((UHCI_INLINK_DSCR_BF0_V)<<(UHCI_INLINK_DSCR_BF0_S)) +#define UHCI_INLINK_DSCR_BF0_V 0xFFFFFFFF +#define UHCI_INLINK_DSCR_BF0_S 0 + +#define UHCI_DMA_IN_DSCR_BF1_REG(i) (REG_UHCI_BASE(i) + 0x54) +/* UHCI_INLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The content of current in link descriptor's second dword*/ +#define UHCI_INLINK_DSCR_BF1 0xFFFFFFFF +#define UHCI_INLINK_DSCR_BF1_M ((UHCI_INLINK_DSCR_BF1_V)<<(UHCI_INLINK_DSCR_BF1_S)) +#define UHCI_INLINK_DSCR_BF1_V 0xFFFFFFFF +#define UHCI_INLINK_DSCR_BF1_S 0 + +#define UHCI_DMA_OUT_DSCR_REG(i) (REG_UHCI_BASE(i) + 0x58) +/* UHCI_OUTLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The content of current out link descriptor's third dword*/ +#define UHCI_OUTLINK_DSCR 0xFFFFFFFF +#define UHCI_OUTLINK_DSCR_M ((UHCI_OUTLINK_DSCR_V)<<(UHCI_OUTLINK_DSCR_S)) +#define UHCI_OUTLINK_DSCR_V 0xFFFFFFFF +#define UHCI_OUTLINK_DSCR_S 0 + +#define UHCI_DMA_OUT_DSCR_BF0_REG(i) (REG_UHCI_BASE(i) + 0x5C) +/* UHCI_OUTLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The content of current out link descriptor's first dword*/ +#define UHCI_OUTLINK_DSCR_BF0 0xFFFFFFFF +#define UHCI_OUTLINK_DSCR_BF0_M ((UHCI_OUTLINK_DSCR_BF0_V)<<(UHCI_OUTLINK_DSCR_BF0_S)) +#define UHCI_OUTLINK_DSCR_BF0_V 0xFFFFFFFF +#define UHCI_OUTLINK_DSCR_BF0_S 0 + +#define UHCI_DMA_OUT_DSCR_BF1_REG(i) (REG_UHCI_BASE(i) + 0x60) +/* UHCI_OUTLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The content of current out link descriptor's second dword*/ +#define UHCI_OUTLINK_DSCR_BF1 0xFFFFFFFF +#define UHCI_OUTLINK_DSCR_BF1_M ((UHCI_OUTLINK_DSCR_BF1_V)<<(UHCI_OUTLINK_DSCR_BF1_S)) +#define UHCI_OUTLINK_DSCR_BF1_V 0xFFFFFFFF +#define UHCI_OUTLINK_DSCR_BF1_S 0 + +#define UHCI_ESCAPE_CONF_REG(i) (REG_UHCI_BASE(i) + 0x64) +/* UHCI_RX_13_ESC_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to enable flow control char 0x13 replace when DMA sends data.*/ +#define UHCI_RX_13_ESC_EN (BIT(7)) +#define UHCI_RX_13_ESC_EN_M (BIT(7)) +#define UHCI_RX_13_ESC_EN_V 0x1 +#define UHCI_RX_13_ESC_EN_S 7 +/* UHCI_RX_11_ESC_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to enable flow control char 0x11 replace when DMA sends data.*/ +#define UHCI_RX_11_ESC_EN (BIT(6)) +#define UHCI_RX_11_ESC_EN_M (BIT(6)) +#define UHCI_RX_11_ESC_EN_V 0x1 +#define UHCI_RX_11_ESC_EN_S 6 +/* UHCI_RX_DB_ESC_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: Set this bit to enable 0xdb char replace when DMA sends data.*/ +#define UHCI_RX_DB_ESC_EN (BIT(5)) +#define UHCI_RX_DB_ESC_EN_M (BIT(5)) +#define UHCI_RX_DB_ESC_EN_V 0x1 +#define UHCI_RX_DB_ESC_EN_S 5 +/* UHCI_RX_C0_ESC_EN : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: Set this bit to enable 0xc0 char replace when DMA sends data.*/ +#define UHCI_RX_C0_ESC_EN (BIT(4)) +#define UHCI_RX_C0_ESC_EN_M (BIT(4)) +#define UHCI_RX_C0_ESC_EN_V 0x1 +#define UHCI_RX_C0_ESC_EN_S 4 +/* UHCI_TX_13_ESC_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to enable flow control char 0x13 decode when DMA receives data.*/ +#define UHCI_TX_13_ESC_EN (BIT(3)) +#define UHCI_TX_13_ESC_EN_M (BIT(3)) +#define UHCI_TX_13_ESC_EN_V 0x1 +#define UHCI_TX_13_ESC_EN_S 3 +/* UHCI_TX_11_ESC_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to enable flow control char 0x11 decode when DMA receives data.*/ +#define UHCI_TX_11_ESC_EN (BIT(2)) +#define UHCI_TX_11_ESC_EN_M (BIT(2)) +#define UHCI_TX_11_ESC_EN_V 0x1 +#define UHCI_TX_11_ESC_EN_S 2 +/* UHCI_TX_DB_ESC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: Set this bit to enable 0xdb char decode when DMA receives data.*/ +#define UHCI_TX_DB_ESC_EN (BIT(1)) +#define UHCI_TX_DB_ESC_EN_M (BIT(1)) +#define UHCI_TX_DB_ESC_EN_V 0x1 +#define UHCI_TX_DB_ESC_EN_S 1 +/* UHCI_TX_C0_ESC_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: Set this bit to enable 0xc0 char decode when DMA receives data.*/ +#define UHCI_TX_C0_ESC_EN (BIT(0)) +#define UHCI_TX_C0_ESC_EN_M (BIT(0)) +#define UHCI_TX_C0_ESC_EN_V 0x1 +#define UHCI_TX_C0_ESC_EN_S 0 + +#define UHCI_HUNG_CONF_REG(i) (REG_UHCI_BASE(i) + 0x68) +/* UHCI_RXFIFO_TIMEOUT_ENA : R/W ;bitpos:[23] ;default: 1'b1 ; */ +/*description: This is the enable bit for DMA send data timeout*/ +#define UHCI_RXFIFO_TIMEOUT_ENA (BIT(23)) +#define UHCI_RXFIFO_TIMEOUT_ENA_M (BIT(23)) +#define UHCI_RXFIFO_TIMEOUT_ENA_V 0x1 +#define UHCI_RXFIFO_TIMEOUT_ENA_S 23 +/* UHCI_RXFIFO_TIMEOUT_SHIFT : R/W ;bitpos:[22:20] ;default: 3'b0 ; */ +/*description: The tick count is cleared when its value >=(17'd8000>>reg_rxfifo_timeout_shift)*/ +#define UHCI_RXFIFO_TIMEOUT_SHIFT 0x00000007 +#define UHCI_RXFIFO_TIMEOUT_SHIFT_M ((UHCI_RXFIFO_TIMEOUT_SHIFT_V)<<(UHCI_RXFIFO_TIMEOUT_SHIFT_S)) +#define UHCI_RXFIFO_TIMEOUT_SHIFT_V 0x7 +#define UHCI_RXFIFO_TIMEOUT_SHIFT_S 20 +/* UHCI_RXFIFO_TIMEOUT : R/W ;bitpos:[19:12] ;default: 8'h10 ; */ +/*description: This register stores the timeout value.when DMA takes more time + than this register value to read a data from RAM it will produce uhci_rx_hung_int interrupt.*/ +#define UHCI_RXFIFO_TIMEOUT 0x000000FF +#define UHCI_RXFIFO_TIMEOUT_M ((UHCI_RXFIFO_TIMEOUT_V)<<(UHCI_RXFIFO_TIMEOUT_S)) +#define UHCI_RXFIFO_TIMEOUT_V 0xFF +#define UHCI_RXFIFO_TIMEOUT_S 12 +/* UHCI_TXFIFO_TIMEOUT_ENA : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: The enable bit for txfifo receive data timeout*/ +#define UHCI_TXFIFO_TIMEOUT_ENA (BIT(11)) +#define UHCI_TXFIFO_TIMEOUT_ENA_M (BIT(11)) +#define UHCI_TXFIFO_TIMEOUT_ENA_V 0x1 +#define UHCI_TXFIFO_TIMEOUT_ENA_S 11 +/* UHCI_TXFIFO_TIMEOUT_SHIFT : R/W ;bitpos:[10:8] ;default: 3'b0 ; */ +/*description: The tick count is cleared when its value >=(17'd8000>>reg_txfifo_timeout_shift)*/ +#define UHCI_TXFIFO_TIMEOUT_SHIFT 0x00000007 +#define UHCI_TXFIFO_TIMEOUT_SHIFT_M ((UHCI_TXFIFO_TIMEOUT_SHIFT_V)<<(UHCI_TXFIFO_TIMEOUT_SHIFT_S)) +#define UHCI_TXFIFO_TIMEOUT_SHIFT_V 0x7 +#define UHCI_TXFIFO_TIMEOUT_SHIFT_S 8 +/* UHCI_TXFIFO_TIMEOUT : R/W ;bitpos:[7:0] ;default: 8'h10 ; */ +/*description: This register stores the timeout value.when DMA takes more time + than this register value to receive a data it will produce uhci_tx_hung_int interrupt.*/ +#define UHCI_TXFIFO_TIMEOUT 0x000000FF +#define UHCI_TXFIFO_TIMEOUT_M ((UHCI_TXFIFO_TIMEOUT_V)<<(UHCI_TXFIFO_TIMEOUT_S)) +#define UHCI_TXFIFO_TIMEOUT_V 0xFF +#define UHCI_TXFIFO_TIMEOUT_S 0 + +#define UHCI_ACK_NUM_REG(i) (REG_UHCI_BASE(i) + 0x6C) + +#define UHCI_RX_HEAD_REG(i) (REG_UHCI_BASE(i) + 0x70) +/* UHCI_RX_HEAD : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the packet header received by DMA*/ +#define UHCI_RX_HEAD 0xFFFFFFFF +#define UHCI_RX_HEAD_M ((UHCI_RX_HEAD_V)<<(UHCI_RX_HEAD_S)) +#define UHCI_RX_HEAD_V 0xFFFFFFFF +#define UHCI_RX_HEAD_S 0 + +#define UHCI_QUICK_SENT_REG(i) (REG_UHCI_BASE(i) + 0x74) +/* UHCI_ALWAYS_SEND_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to enable continuously send the same short packet*/ +#define UHCI_ALWAYS_SEND_EN (BIT(7)) +#define UHCI_ALWAYS_SEND_EN_M (BIT(7)) +#define UHCI_ALWAYS_SEND_EN_V 0x1 +#define UHCI_ALWAYS_SEND_EN_S 7 +/* UHCI_ALWAYS_SEND_NUM : R/W ;bitpos:[6:4] ;default: 3'h0 ; */ +/*description: The bits are used to choose which short packet*/ +#define UHCI_ALWAYS_SEND_NUM 0x00000007 +#define UHCI_ALWAYS_SEND_NUM_M ((UHCI_ALWAYS_SEND_NUM_V)<<(UHCI_ALWAYS_SEND_NUM_S)) +#define UHCI_ALWAYS_SEND_NUM_V 0x7 +#define UHCI_ALWAYS_SEND_NUM_S 4 +/* UHCI_SINGLE_SEND_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to enable send a short packet*/ +#define UHCI_SINGLE_SEND_EN (BIT(3)) +#define UHCI_SINGLE_SEND_EN_M (BIT(3)) +#define UHCI_SINGLE_SEND_EN_V 0x1 +#define UHCI_SINGLE_SEND_EN_S 3 +/* UHCI_SINGLE_SEND_NUM : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ +/*description: The bits are used to choose which short packet*/ +#define UHCI_SINGLE_SEND_NUM 0x00000007 +#define UHCI_SINGLE_SEND_NUM_M ((UHCI_SINGLE_SEND_NUM_V)<<(UHCI_SINGLE_SEND_NUM_S)) +#define UHCI_SINGLE_SEND_NUM_V 0x7 +#define UHCI_SINGLE_SEND_NUM_S 0 + +#define UHCI_Q0_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x78) +/* UHCI_SEND_Q0_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the content of short packet's first dword*/ +#define UHCI_SEND_Q0_WORD0 0xFFFFFFFF +#define UHCI_SEND_Q0_WORD0_M ((UHCI_SEND_Q0_WORD0_V)<<(UHCI_SEND_Q0_WORD0_S)) +#define UHCI_SEND_Q0_WORD0_V 0xFFFFFFFF +#define UHCI_SEND_Q0_WORD0_S 0 + +#define UHCI_Q0_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x7C) +/* UHCI_SEND_Q0_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the content of short packet's second dword*/ +#define UHCI_SEND_Q0_WORD1 0xFFFFFFFF +#define UHCI_SEND_Q0_WORD1_M ((UHCI_SEND_Q0_WORD1_V)<<(UHCI_SEND_Q0_WORD1_S)) +#define UHCI_SEND_Q0_WORD1_V 0xFFFFFFFF +#define UHCI_SEND_Q0_WORD1_S 0 + +#define UHCI_Q1_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x80) +/* UHCI_SEND_Q1_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the content of short packet's first dword*/ +#define UHCI_SEND_Q1_WORD0 0xFFFFFFFF +#define UHCI_SEND_Q1_WORD0_M ((UHCI_SEND_Q1_WORD0_V)<<(UHCI_SEND_Q1_WORD0_S)) +#define UHCI_SEND_Q1_WORD0_V 0xFFFFFFFF +#define UHCI_SEND_Q1_WORD0_S 0 + +#define UHCI_Q1_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x84) +/* UHCI_SEND_Q1_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the content of short packet's second dword*/ +#define UHCI_SEND_Q1_WORD1 0xFFFFFFFF +#define UHCI_SEND_Q1_WORD1_M ((UHCI_SEND_Q1_WORD1_V)<<(UHCI_SEND_Q1_WORD1_S)) +#define UHCI_SEND_Q1_WORD1_V 0xFFFFFFFF +#define UHCI_SEND_Q1_WORD1_S 0 + +#define UHCI_Q2_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x88) +/* UHCI_SEND_Q2_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the content of short packet's first dword*/ +#define UHCI_SEND_Q2_WORD0 0xFFFFFFFF +#define UHCI_SEND_Q2_WORD0_M ((UHCI_SEND_Q2_WORD0_V)<<(UHCI_SEND_Q2_WORD0_S)) +#define UHCI_SEND_Q2_WORD0_V 0xFFFFFFFF +#define UHCI_SEND_Q2_WORD0_S 0 + +#define UHCI_Q2_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x8C) +/* UHCI_SEND_Q2_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the content of short packet's second dword*/ +#define UHCI_SEND_Q2_WORD1 0xFFFFFFFF +#define UHCI_SEND_Q2_WORD1_M ((UHCI_SEND_Q2_WORD1_V)<<(UHCI_SEND_Q2_WORD1_S)) +#define UHCI_SEND_Q2_WORD1_V 0xFFFFFFFF +#define UHCI_SEND_Q2_WORD1_S 0 + +#define UHCI_Q3_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x90) +/* UHCI_SEND_Q3_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the content of short packet's first dword*/ +#define UHCI_SEND_Q3_WORD0 0xFFFFFFFF +#define UHCI_SEND_Q3_WORD0_M ((UHCI_SEND_Q3_WORD0_V)<<(UHCI_SEND_Q3_WORD0_S)) +#define UHCI_SEND_Q3_WORD0_V 0xFFFFFFFF +#define UHCI_SEND_Q3_WORD0_S 0 + +#define UHCI_Q3_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x94) +/* UHCI_SEND_Q3_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the content of short packet's second dword*/ +#define UHCI_SEND_Q3_WORD1 0xFFFFFFFF +#define UHCI_SEND_Q3_WORD1_M ((UHCI_SEND_Q3_WORD1_V)<<(UHCI_SEND_Q3_WORD1_S)) +#define UHCI_SEND_Q3_WORD1_V 0xFFFFFFFF +#define UHCI_SEND_Q3_WORD1_S 0 + +#define UHCI_Q4_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x98) +/* UHCI_SEND_Q4_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the content of short packet's first dword*/ +#define UHCI_SEND_Q4_WORD0 0xFFFFFFFF +#define UHCI_SEND_Q4_WORD0_M ((UHCI_SEND_Q4_WORD0_V)<<(UHCI_SEND_Q4_WORD0_S)) +#define UHCI_SEND_Q4_WORD0_V 0xFFFFFFFF +#define UHCI_SEND_Q4_WORD0_S 0 + +#define UHCI_Q4_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x9C) +/* UHCI_SEND_Q4_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the content of short packet's second dword*/ +#define UHCI_SEND_Q4_WORD1 0xFFFFFFFF +#define UHCI_SEND_Q4_WORD1_M ((UHCI_SEND_Q4_WORD1_V)<<(UHCI_SEND_Q4_WORD1_S)) +#define UHCI_SEND_Q4_WORD1_V 0xFFFFFFFF +#define UHCI_SEND_Q4_WORD1_S 0 + +#define UHCI_Q5_WORD0_REG(i) (REG_UHCI_BASE(i) + 0xA0) +/* UHCI_SEND_Q5_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the content of short packet's first dword*/ +#define UHCI_SEND_Q5_WORD0 0xFFFFFFFF +#define UHCI_SEND_Q5_WORD0_M ((UHCI_SEND_Q5_WORD0_V)<<(UHCI_SEND_Q5_WORD0_S)) +#define UHCI_SEND_Q5_WORD0_V 0xFFFFFFFF +#define UHCI_SEND_Q5_WORD0_S 0 + +#define UHCI_Q5_WORD1_REG(i) (REG_UHCI_BASE(i) + 0xA4) +/* UHCI_SEND_Q5_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the content of short packet's second dword*/ +#define UHCI_SEND_Q5_WORD1 0xFFFFFFFF +#define UHCI_SEND_Q5_WORD1_M ((UHCI_SEND_Q5_WORD1_V)<<(UHCI_SEND_Q5_WORD1_S)) +#define UHCI_SEND_Q5_WORD1_V 0xFFFFFFFF +#define UHCI_SEND_Q5_WORD1_S 0 + +#define UHCI_Q6_WORD0_REG(i) (REG_UHCI_BASE(i) + 0xA8) +/* UHCI_SEND_Q6_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the content of short packet's first dword*/ +#define UHCI_SEND_Q6_WORD0 0xFFFFFFFF +#define UHCI_SEND_Q6_WORD0_M ((UHCI_SEND_Q6_WORD0_V)<<(UHCI_SEND_Q6_WORD0_S)) +#define UHCI_SEND_Q6_WORD0_V 0xFFFFFFFF +#define UHCI_SEND_Q6_WORD0_S 0 + +#define UHCI_Q6_WORD1_REG(i) (REG_UHCI_BASE(i) + 0xAC) +/* UHCI_SEND_Q6_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the content of short packet's second dword*/ +#define UHCI_SEND_Q6_WORD1 0xFFFFFFFF +#define UHCI_SEND_Q6_WORD1_M ((UHCI_SEND_Q6_WORD1_V)<<(UHCI_SEND_Q6_WORD1_S)) +#define UHCI_SEND_Q6_WORD1_V 0xFFFFFFFF +#define UHCI_SEND_Q6_WORD1_S 0 + +#define UHCI_ESC_CONF0_REG(i) (REG_UHCI_BASE(i) + 0xB0) +/* UHCI_SEPER_ESC_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdc ; */ +/*description: This register stores the second char used to replace seperator + char in data . 0xdc 0xdb replace 0xc0 by default.*/ +#define UHCI_SEPER_ESC_CHAR1 0x000000FF +#define UHCI_SEPER_ESC_CHAR1_M ((UHCI_SEPER_ESC_CHAR1_V)<<(UHCI_SEPER_ESC_CHAR1_S)) +#define UHCI_SEPER_ESC_CHAR1_V 0xFF +#define UHCI_SEPER_ESC_CHAR1_S 16 +/* UHCI_SEPER_ESC_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */ +/*description: This register stores thee first char used to replace seperator char in data.*/ +#define UHCI_SEPER_ESC_CHAR0 0x000000FF +#define UHCI_SEPER_ESC_CHAR0_M ((UHCI_SEPER_ESC_CHAR0_V)<<(UHCI_SEPER_ESC_CHAR0_S)) +#define UHCI_SEPER_ESC_CHAR0_V 0xFF +#define UHCI_SEPER_ESC_CHAR0_S 8 +/* UHCI_SEPER_CHAR : R/W ;bitpos:[7:0] ;default: 8'hc0 ; */ +/*description: This register stores the seperator char seperator char is used + to seperate the data frame.*/ +#define UHCI_SEPER_CHAR 0x000000FF +#define UHCI_SEPER_CHAR_M ((UHCI_SEPER_CHAR_V)<<(UHCI_SEPER_CHAR_S)) +#define UHCI_SEPER_CHAR_V 0xFF +#define UHCI_SEPER_CHAR_S 0 + +#define UHCI_ESC_CONF1_REG(i) (REG_UHCI_BASE(i) + 0xB4) +/* UHCI_ESC_SEQ0_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdd ; */ +/*description: This register stores the second char used to replace the reg_esc_seq0 in data*/ +#define UHCI_ESC_SEQ0_CHAR1 0x000000FF +#define UHCI_ESC_SEQ0_CHAR1_M ((UHCI_ESC_SEQ0_CHAR1_V)<<(UHCI_ESC_SEQ0_CHAR1_S)) +#define UHCI_ESC_SEQ0_CHAR1_V 0xFF +#define UHCI_ESC_SEQ0_CHAR1_S 16 +/* UHCI_ESC_SEQ0_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */ +/*description: This register stores the first char used to replace reg_esc_seq0 in data.*/ +#define UHCI_ESC_SEQ0_CHAR0 0x000000FF +#define UHCI_ESC_SEQ0_CHAR0_M ((UHCI_ESC_SEQ0_CHAR0_V)<<(UHCI_ESC_SEQ0_CHAR0_S)) +#define UHCI_ESC_SEQ0_CHAR0_V 0xFF +#define UHCI_ESC_SEQ0_CHAR0_S 8 +/* UHCI_ESC_SEQ0 : R/W ;bitpos:[7:0] ;default: 8'hdb ; */ +/*description: This register stores the first substitute char used to replace + the seperator char.*/ +#define UHCI_ESC_SEQ0 0x000000FF +#define UHCI_ESC_SEQ0_M ((UHCI_ESC_SEQ0_V)<<(UHCI_ESC_SEQ0_S)) +#define UHCI_ESC_SEQ0_V 0xFF +#define UHCI_ESC_SEQ0_S 0 + +#define UHCI_ESC_CONF2_REG(i) (REG_UHCI_BASE(i) + 0xB8) +/* UHCI_ESC_SEQ1_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hde ; */ +/*description: This register stores the second char used to replace the reg_esc_seq1 in data.*/ +#define UHCI_ESC_SEQ1_CHAR1 0x000000FF +#define UHCI_ESC_SEQ1_CHAR1_M ((UHCI_ESC_SEQ1_CHAR1_V)<<(UHCI_ESC_SEQ1_CHAR1_S)) +#define UHCI_ESC_SEQ1_CHAR1_V 0xFF +#define UHCI_ESC_SEQ1_CHAR1_S 16 +/* UHCI_ESC_SEQ1_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */ +/*description: This register stores the first char used to replace the reg_esc_seq1 in data.*/ +#define UHCI_ESC_SEQ1_CHAR0 0x000000FF +#define UHCI_ESC_SEQ1_CHAR0_M ((UHCI_ESC_SEQ1_CHAR0_V)<<(UHCI_ESC_SEQ1_CHAR0_S)) +#define UHCI_ESC_SEQ1_CHAR0_V 0xFF +#define UHCI_ESC_SEQ1_CHAR0_S 8 +/* UHCI_ESC_SEQ1 : R/W ;bitpos:[7:0] ;default: 8'h11 ; */ +/*description: This register stores the flow control char to turn on the flow_control*/ +#define UHCI_ESC_SEQ1 0x000000FF +#define UHCI_ESC_SEQ1_M ((UHCI_ESC_SEQ1_V)<<(UHCI_ESC_SEQ1_S)) +#define UHCI_ESC_SEQ1_V 0xFF +#define UHCI_ESC_SEQ1_S 0 + +#define UHCI_ESC_CONF3_REG(i) (REG_UHCI_BASE(i) + 0xBC) +/* UHCI_ESC_SEQ2_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdf ; */ +/*description: This register stores the second char used to replace the reg_esc_seq2 in data.*/ +#define UHCI_ESC_SEQ2_CHAR1 0x000000FF +#define UHCI_ESC_SEQ2_CHAR1_M ((UHCI_ESC_SEQ2_CHAR1_V)<<(UHCI_ESC_SEQ2_CHAR1_S)) +#define UHCI_ESC_SEQ2_CHAR1_V 0xFF +#define UHCI_ESC_SEQ2_CHAR1_S 16 +/* UHCI_ESC_SEQ2_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */ +/*description: This register stores the first char used to replace the reg_esc_seq2 in data.*/ +#define UHCI_ESC_SEQ2_CHAR0 0x000000FF +#define UHCI_ESC_SEQ2_CHAR0_M ((UHCI_ESC_SEQ2_CHAR0_V)<<(UHCI_ESC_SEQ2_CHAR0_S)) +#define UHCI_ESC_SEQ2_CHAR0_V 0xFF +#define UHCI_ESC_SEQ2_CHAR0_S 8 +/* UHCI_ESC_SEQ2 : R/W ;bitpos:[7:0] ;default: 8'h13 ; */ +/*description: This register stores the flow_control char to turn off the flow_control*/ +#define UHCI_ESC_SEQ2 0x000000FF +#define UHCI_ESC_SEQ2_M ((UHCI_ESC_SEQ2_V)<<(UHCI_ESC_SEQ2_S)) +#define UHCI_ESC_SEQ2_V 0xFF +#define UHCI_ESC_SEQ2_S 0 + +#define UHCI_PKT_THRES_REG(i) (REG_UHCI_BASE(i) + 0xC0) +/* UHCI_PKT_THRS : R/W ;bitpos:[12:0] ;default: 13'h80 ; */ +/*description: when the amount of packet payload is greater than this value + the process of receiving data is done.*/ +#define UHCI_PKT_THRS 0x00001FFF +#define UHCI_PKT_THRS_M ((UHCI_PKT_THRS_V)<<(UHCI_PKT_THRS_S)) +#define UHCI_PKT_THRS_V 0x1FFF +#define UHCI_PKT_THRS_S 0 + +#define UHCI_DATE_REG(i) (REG_UHCI_BASE(i) + 0xFC) +/* UHCI_DATE : R/W ;bitpos:[31:0] ;default: 32'h16041001 ; */ +/*description: version information*/ +#define UHCI_DATE 0xFFFFFFFF +#define UHCI_DATE_M ((UHCI_DATE_V)<<(UHCI_DATE_S)) +#define UHCI_DATE_V 0xFFFFFFFF +#define UHCI_DATE_S 0 + + + + +#endif /*_SOC_UHCI_REG_H_ */ + + diff --git a/tools/sdk/include/esp32/soc/uhci_struct.h b/tools/sdk/include/esp32/soc/uhci_struct.h new file mode 100644 index 00000000..0c939796 --- /dev/null +++ b/tools/sdk/include/esp32/soc/uhci_struct.h @@ -0,0 +1,337 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_UHCI_STRUCT_H_ +#define _SOC_UHCI_STRUCT_H_ +typedef volatile struct { + union { + struct { + uint32_t in_rst: 1; /*Set this bit to reset in link operations.*/ + uint32_t out_rst: 1; /*Set this bit to reset out link operations.*/ + uint32_t ahbm_fifo_rst: 1; /*Set this bit to reset dma ahb fifo.*/ + uint32_t ahbm_rst: 1; /*Set this bit to reset dma ahb interface.*/ + uint32_t in_loop_test: 1; /*Set this bit to enable loop test for in links.*/ + uint32_t out_loop_test: 1; /*Set this bit to enable loop test for out links.*/ + uint32_t out_auto_wrback: 1; /*when in link's length is 0 go on to use the next in link automatically.*/ + uint32_t out_no_restart_clr: 1; /*don't use*/ + uint32_t out_eof_mode: 1; /*Set this bit to produce eof after DMA pops all data clear this bit to produce eof after DMA pushes all data*/ + uint32_t uart0_ce: 1; /*Set this bit to use UART to transmit or receive data.*/ + uint32_t uart1_ce: 1; /*Set this bit to use UART1 to transmit or receive data.*/ + uint32_t uart2_ce: 1; /*Set this bit to use UART2 to transmit or receive data.*/ + uint32_t outdscr_burst_en: 1; /*Set this bit to enable DMA in links to use burst mode.*/ + uint32_t indscr_burst_en: 1; /*Set this bit to enable DMA out links to use burst mode.*/ + uint32_t out_data_burst_en: 1; /*Set this bit to enable DMA burst MODE*/ + uint32_t mem_trans_en: 1; + uint32_t seper_en: 1; /*Set this bit to use special char to separate the data frame.*/ + uint32_t head_en: 1; /*Set this bit to enable to use head packet before the data frame.*/ + uint32_t crc_rec_en: 1; /*Set this bit to enable receiver''s ability of crc calculation when crc_en bit in head packet is 1 then there will be crc bytes after data_frame*/ + uint32_t uart_idle_eof_en: 1; /*Set this bit to enable to use idle time when the idle time after data frame is satisfied this means the end of a data frame.*/ + uint32_t len_eof_en: 1; /*Set this bit to enable to use packet_len in packet head when the received data is equal to packet_len this means the end of a data frame.*/ + uint32_t encode_crc_en: 1; /*Set this bit to enable crc calculation for data frame when bit6 in the head packet is 1.*/ + uint32_t clk_en: 1; /*Set this bit to enable clock-gating for read or write registers.*/ + uint32_t uart_rx_brk_eof_en: 1; /*Set this bit to enable to use brk char as the end of a data frame.*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } conf0; + union { + struct { + uint32_t rx_start: 1; /*when a separator char has been send it will produce uhci_rx_start_int interrupt.*/ + uint32_t tx_start: 1; /*when DMA detects a separator char it will produce uhci_tx_start_int interrupt.*/ + uint32_t rx_hung: 1; /*when DMA takes a lot of time to receive a data it will produce uhci_rx_hung_int interrupt.*/ + uint32_t tx_hung: 1; /*when DMA takes a lot of time to read a data from RAM it will produce uhci_tx_hung_int interrupt.*/ + uint32_t in_done: 1; /*when a in link descriptor has been completed it will produce uhci_in_done_int interrupt.*/ + uint32_t in_suc_eof: 1; /*when a data packet has been received it will produce uhci_in_suc_eof_int interrupt.*/ + uint32_t in_err_eof: 1; /*when there are some errors about eof in in link descriptor it will produce uhci_in_err_eof_int interrupt.*/ + uint32_t out_done: 1; /*when a out link descriptor is completed it will produce uhci_out_done_int interrupt.*/ + uint32_t out_eof: 1; /*when the current descriptor's eof bit is 1 it will produce uhci_out_eof_int interrupt.*/ + uint32_t in_dscr_err: 1; /*when there are some errors about the out link descriptor it will produce uhci_in_dscr_err_int interrupt.*/ + uint32_t out_dscr_err: 1; /*when there are some errors about the in link descriptor it will produce uhci_out_dscr_err_int interrupt.*/ + uint32_t in_dscr_empty: 1; /*when there are not enough in links for DMA it will produce uhci_in_dscr_err_int interrupt.*/ + uint32_t outlink_eof_err: 1; /*when there are some errors about eof in outlink descriptor it will produce uhci_outlink_eof_err_int interrupt.*/ + uint32_t out_total_eof: 1; /*When all data have been send it will produce uhci_out_total_eof_int interrupt.*/ + uint32_t send_s_q: 1; /*When use single send registers to send a short packets it will produce this interrupt when dma has send the short packet.*/ + uint32_t send_a_q: 1; /*When use always_send registers to send a series of short packets it will produce this interrupt when dma has send the short packet.*/ + uint32_t dma_in_fifo_full_wm: 1; + uint32_t reserved17: 15; + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_hung: 1; + uint32_t tx_hung: 1; + uint32_t in_done: 1; + uint32_t in_suc_eof: 1; + uint32_t in_err_eof: 1; + uint32_t out_done: 1; + uint32_t out_eof: 1; + uint32_t in_dscr_err: 1; + uint32_t out_dscr_err: 1; + uint32_t in_dscr_empty: 1; + uint32_t outlink_eof_err: 1; + uint32_t out_total_eof: 1; + uint32_t send_s_q: 1; + uint32_t send_a_q: 1; + uint32_t dma_in_fifo_full_wm: 1; + uint32_t reserved17: 15; + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_hung: 1; + uint32_t tx_hung: 1; + uint32_t in_done: 1; + uint32_t in_suc_eof: 1; + uint32_t in_err_eof: 1; + uint32_t out_done: 1; + uint32_t out_eof: 1; + uint32_t in_dscr_err: 1; + uint32_t out_dscr_err: 1; + uint32_t in_dscr_empty: 1; + uint32_t outlink_eof_err: 1; + uint32_t out_total_eof: 1; + uint32_t send_s_q: 1; + uint32_t send_a_q: 1; + uint32_t dma_in_fifo_full_wm: 1; + uint32_t reserved17: 15; + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_hung: 1; + uint32_t tx_hung: 1; + uint32_t in_done: 1; + uint32_t in_suc_eof: 1; + uint32_t in_err_eof: 1; + uint32_t out_done: 1; + uint32_t out_eof: 1; + uint32_t in_dscr_err: 1; + uint32_t out_dscr_err: 1; + uint32_t in_dscr_empty: 1; + uint32_t outlink_eof_err: 1; + uint32_t out_total_eof: 1; + uint32_t send_s_q: 1; + uint32_t send_a_q: 1; + uint32_t dma_in_fifo_full_wm: 1; + uint32_t reserved17: 15; + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t full: 1; /*1:DMA out link descriptor's fifo is full.*/ + uint32_t empty: 1; /*1:DMA in link descriptor's fifo is empty.*/ + uint32_t reserved2: 30; + }; + uint32_t val; + } dma_out_status; + union { + struct { + uint32_t fifo_wdata: 9; /*This is the data need to be pushed into out link descriptor's fifo.*/ + uint32_t reserved9: 7; + uint32_t fifo_push: 1; /*Set this bit to push data in out link descriptor's fifo.*/ + uint32_t reserved17:15; + }; + uint32_t val; + } dma_out_push; + union { + struct { + uint32_t full: 1; + uint32_t empty: 1; + uint32_t reserved2: 2; + uint32_t rx_err_cause: 3; /*This register stores the errors caused in out link descriptor's data packet.*/ + uint32_t reserved7: 25; + }; + uint32_t val; + } dma_in_status; + union { + struct { + uint32_t fifo_rdata: 12; /*This register stores the data pop from in link descriptor's fifo.*/ + uint32_t reserved12: 4; + uint32_t fifo_pop: 1; /*Set this bit to pop data in in link descriptor's fifo.*/ + uint32_t reserved17: 15; + }; + uint32_t val; + } dma_in_pop; + union { + struct { + uint32_t addr: 20; /*This register stores the least 20 bits of the first out link descriptor's address.*/ + uint32_t reserved20: 8; + uint32_t stop: 1; /*Set this bit to stop dealing with the out link descriptors.*/ + uint32_t start: 1; /*Set this bit to start dealing with the out link descriptors.*/ + uint32_t restart: 1; /*Set this bit to mount on new out link descriptors*/ + uint32_t park: 1; /*1： the out link descriptor's fsm is in idle state. 0:the out link descriptor's fsm is working.*/ + }; + uint32_t val; + } dma_out_link; + union { + struct { + uint32_t addr: 20; /*This register stores the least 20 bits of the first in link descriptor's address.*/ + uint32_t auto_ret: 1; /*1:when a packet is wrong in link descriptor returns to the descriptor which is lately used.*/ + uint32_t reserved21: 7; + uint32_t stop: 1; /*Set this bit to stop dealing with the in link descriptors.*/ + uint32_t start: 1; /*Set this bit to start dealing with the in link descriptors.*/ + uint32_t restart: 1; /*Set this bit to mount on new in link descriptors*/ + uint32_t park: 1; /*1:the in link descriptor's fsm is in idle state. 0:the in link descriptor's fsm is working*/ + }; + uint32_t val; + } dma_in_link; + union { + struct { + uint32_t check_sum_en: 1; /*Set this bit to enable decoder to check check_sum in packet header.*/ + uint32_t check_seq_en: 1; /*Set this bit to enable decoder to check seq num in packet header.*/ + uint32_t crc_disable: 1; /*Set this bit to disable crc calculation.*/ + uint32_t save_head: 1; /*Set this bit to save packet header .*/ + uint32_t tx_check_sum_re: 1; /*Set this bit to enable hardware replace check_sum in packet header automatically.*/ + uint32_t tx_ack_num_re: 1; /*Set this bit to enable hardware replace ack num in packet header automatically.*/ + uint32_t check_owner: 1; /*Set this bit to check the owner bit in link descriptor.*/ + uint32_t wait_sw_start: 1; /*Set this bit to enable software way to add packet header.*/ + uint32_t sw_start: 1; /*Set this bit to start inserting the packet header.*/ + uint32_t dma_in_fifo_full_thrs:12; /*when data amount in link descriptor's fifo is more than this register value it will produce uhci_dma_in_fifo_full_wm_int interrupt.*/ + uint32_t reserved21: 11; + }; + uint32_t val; + } conf1; + uint32_t state0; /**/ + uint32_t state1; /**/ + uint32_t dma_out_eof_des_addr; /*This register stores the address of out link description when eof bit in this descriptor is 1.*/ + uint32_t dma_in_suc_eof_des_addr; /*This register stores the address of in link descriptor when eof bit in this descriptor is 1.*/ + uint32_t dma_in_err_eof_des_addr; /*This register stores the address of in link descriptor when there are some errors in this descriptor.*/ + uint32_t dma_out_eof_bfr_des_addr; /*This register stores the address of out link descriptor when there are some errors in this descriptor.*/ + union { + struct { + uint32_t test_mode: 3; /*bit2 is ahb bus test enable ，bit1 is used to choose write(1) or read(0) mode. bit0 is used to choose test only once(1) or continue(0)*/ + uint32_t reserved3: 1; + uint32_t test_addr: 2; /*The two bits represent ahb bus address bit[20:19]*/ + uint32_t reserved6: 26; + }; + uint32_t val; + } ahb_test; + uint32_t dma_in_dscr; /*The content of current in link descriptor's third dword*/ + uint32_t dma_in_dscr_bf0; /*The content of current in link descriptor's first dword*/ + uint32_t dma_in_dscr_bf1; /*The content of current in link descriptor's second dword*/ + uint32_t dma_out_dscr; /*The content of current out link descriptor's third dword*/ + uint32_t dma_out_dscr_bf0; /*The content of current out link descriptor's first dword*/ + uint32_t dma_out_dscr_bf1; /*The content of current out link descriptor's second dword*/ + union { + struct { + uint32_t tx_c0_esc_en: 1; /*Set this bit to enable 0xc0 char decode when DMA receives data.*/ + uint32_t tx_db_esc_en: 1; /*Set this bit to enable 0xdb char decode when DMA receives data.*/ + uint32_t tx_11_esc_en: 1; /*Set this bit to enable flow control char 0x11 decode when DMA receives data.*/ + uint32_t tx_13_esc_en: 1; /*Set this bit to enable flow control char 0x13 decode when DMA receives data.*/ + uint32_t rx_c0_esc_en: 1; /*Set this bit to enable 0xc0 char replace when DMA sends data.*/ + uint32_t rx_db_esc_en: 1; /*Set this bit to enable 0xdb char replace when DMA sends data.*/ + uint32_t rx_11_esc_en: 1; /*Set this bit to enable flow control char 0x11 replace when DMA sends data.*/ + uint32_t rx_13_esc_en: 1; /*Set this bit to enable flow control char 0x13 replace when DMA sends data.*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } escape_conf; + union { + struct { + uint32_t txfifo_timeout: 8; /*This register stores the timeout value.when DMA takes more time than this register value to receive a data it will produce uhci_tx_hung_int interrupt.*/ + uint32_t txfifo_timeout_shift: 3; /*The tick count is cleared when its value >=(17'd8000>>reg_txfifo_timeout_shift)*/ + uint32_t txfifo_timeout_ena: 1; /*The enable bit for tx fifo receive data timeout*/ + uint32_t rxfifo_timeout: 8; /*This register stores the timeout value.when DMA takes more time than this register value to read a data from RAM it will produce uhci_rx_hung_int interrupt.*/ + uint32_t rxfifo_timeout_shift: 3; /*The tick count is cleared when its value >=(17'd8000>>reg_rxfifo_timeout_shift)*/ + uint32_t rxfifo_timeout_ena: 1; /*This is the enable bit for DMA send data timeout*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } hung_conf; + uint32_t ack_num; /**/ + uint32_t rx_head; /*This register stores the packet header received by DMA*/ + union { + struct { + uint32_t single_send_num: 3; /*The bits are used to choose which short packet*/ + uint32_t single_send_en: 1; /*Set this bit to enable send a short packet*/ + uint32_t always_send_num: 3; /*The bits are used to choose which short packet*/ + uint32_t always_send_en: 1; /*Set this bit to enable continuously send the same short packet*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } quick_sent; + struct{ + uint32_t w_data[2]; /*This register stores the content of short packet's dword*/ + } q_data[7]; + union { + struct { + uint32_t seper_char: 8; /*This register stores the separator char separator char is used to separate the data frame.*/ + uint32_t seper_esc_char0: 8; /*This register stores the first char used to replace separator char in data.*/ + uint32_t seper_esc_char1: 8; /*This register stores the second char used to replace separator char in data . 0xdc 0xdb replace 0xc0 by default.*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } esc_conf0; + union { + struct { + uint32_t seq0: 8; /*This register stores the first substitute char used to replace the separate char.*/ + uint32_t seq0_char0: 8; /*This register stores the first char used to replace reg_esc_seq0 in data.*/ + uint32_t seq0_char1: 8; /*This register stores the second char used to replace the reg_esc_seq0 in data*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } esc_conf1; + union { + struct { + uint32_t seq1: 8; /*This register stores the flow control char to turn on the flow_control*/ + uint32_t seq1_char0: 8; /*This register stores the first char used to replace the reg_esc_seq1 in data.*/ + uint32_t seq1_char1: 8; /*This register stores the second char used to replace the reg_esc_seq1 in data.*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } esc_conf2; + union { + struct { + uint32_t seq2: 8; /*This register stores the flow_control char to turn off the flow_control*/ + uint32_t seq2_char0: 8; /*This register stores the first char used to replace the reg_esc_seq2 in data.*/ + uint32_t seq2_char1: 8; /*This register stores the second char used to replace the reg_esc_seq2 in data.*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } esc_conf3; + union { + struct { + uint32_t thrs: 13; /*when the amount of packet payload is larger than this value the process of receiving data is done.*/ + uint32_t reserved13:19; + }; + uint32_t val; + } pkt_thres; + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t reserved_cc; + uint32_t reserved_d0; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t reserved_f8; + uint32_t date; /*version information*/ +} uhci_dev_t; +extern uhci_dev_t UHCI0; +extern uhci_dev_t UHCI1; +#endif /* _SOC_UHCI_STRUCT_H_ */ diff --git a/tools/sdk/include/esp32/xtensa/board.h b/tools/sdk/include/esp32/xtensa/board.h new file mode 100755 index 00000000..c6b04a25 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/board.h @@ -0,0 +1,28 @@ +/* This header is supposed to be obtained from /xtensa/board.h + using a -I directive passed to the compiler. */ + +#error "Unspecified board. Missing -I directive to select supported Xtensa board, usually -I XTENSA_TOOLS_ROOT/xtensa-elf/include/xtensa/ (XTENSA_TOOLS_ROOT is root of Xtensa Tools install, see xt-run --show-config=xttools)" + +/* + * Copyright (c) 2013 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + diff --git a/tools/sdk/include/esp32/xtensa/c6x-compat.h b/tools/sdk/include/esp32/xtensa/c6x-compat.h new file mode 100755 index 00000000..4b17987e --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/c6x-compat.h @@ -0,0 +1,1758 @@ +/* + * Copyright (c) 2006-2010 Tensilica Inc. ALL RIGHTS RESERVED. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef __C6X_COMPAT__H +#define __C6X_COMPAT__H + +/* Unimplemented functions _gmpy, _gmpy4, _xormpy, _lssub, _cmpy, _cmpyr, + _cmpyr1, _ddotpl2r, _ddotph2r */ + + +typedef long long C6X_COMPAT_LONG40; + + +#define _memd8(a) (*((double*)(a))) +#define _memd8_const(a) (*((const double*)(a))) + +#define _amemd8(a) (*((double*)(a))) +#define _amemd8_const(a) (*((const double*)(a))) + +#define _mem8(a) (*((unsigned long long*)(a))) +#define _mem8_const(a) (*((const unsigned long long*)(a))) + +#define _mem4(a) (*((unsigned*)(a))) +#define _mem4_const(a) (*((const unsigned*)(a))) +#define _amem4_const(a) (*((const unsigned*)(a))) + +/* NOTE: To emulate a C6X properly you should define global variables + for your Xtensa with these names. Some of the emulation routines + will set these values. */ + +extern int _carry; +extern int _overflow; + +// Utility routines + + +#define TESTBIT(x,n) (((x) >> (n)) & 1) + +#define NSA_BITS 32 + +static inline unsigned int norm_shift_amt_U_and_non_U(int is_signed, int inp) { +int j=0, k=0; +int x=inp; +if (is_signed) { + /* Invert signed val if negative */ + x= TESTBIT(x,(NSA_BITS-1))? ~x: x; + x= (x&1)|(x<<1); /* Shift up to return count-1 */ + if (x ==0) + return NSA_BITS-1; + } + if (x ==0) + return NSA_BITS; + /* Now count leading zeros */ + for (j=0, k=NSA_BITS-1; k>=0; j++, k--) { + if (TESTBIT(x,k)) + return j; + } + return NSA_BITS; +} + + + +static inline long long +orig_L40_set( long long L40_var1) { + long long L40_var_out; + + L40_var_out = L40_var1 & 0x000000ffffffffffLL; + + if( L40_var1 & 0x8000000000LL) + L40_var_out = L40_var_out | 0xffffff0000000000LL; + + return( L40_var_out); +} + + + +static inline signed long long +util_saturate_n_no_state(signed long long t, int n) +{ + signed long long maxv, minv; + maxv = (1LL << (n-1)) - 1; + minv = (-1LL << (n-1)); + if (t > maxv) { + t = maxv; + } else if (t < minv) { + t = minv; + } + return t; +} + + +static inline signed long long +util_saturate_n_sgn(signed long long t, int n) +{ + signed long long result; + signed long long maxv, minv; + maxv = (1LL << (n-1)) - 1; + minv = (-1LL << (n-1)); + if (t > 0) { + result = maxv; + _overflow = 1; + } else if (t < 0) { + result = minv; + _overflow = 1; + } else { + result = 0; + } + return result; +} + + + + +/* well-behaved signed shift right (left on negative) with + saturation */ +static inline signed long long +util_shift_right_saturate_n(signed long long t, int shval, int n) +{ + /* n should be <= 62 */ + long long result; + + signed long long mask; + int actual_shift = shval; + long long shft = actual_shift > 0 ? actual_shift : -actual_shift; + + if (t == 0 || actual_shift == 0) + return t; + + if (actual_shift >= n) { + return (t < 0) ? -1 : 0; + } + if (actual_shift <= -n) { + return util_saturate_n_sgn(t, n); + } + if (actual_shift > 0) { + return t >> actual_shift; + } + /* actual_shift < 0. Check for saturation after shift. */ + mask = (-1LL << (n-shft-1)); + if (t > 0 && ((mask & t) != 0)) { + return util_saturate_n_sgn(t, n); + } + if (t < 0 && ((mask & t) != mask)) { + return util_saturate_n_sgn(t, n); + } + result = t << shft; + + return result; +} + + +/* Implemented c6x standard C compatibility functions (alphabetical + order) */ + + +static inline int _abs(int src1) { + if ((unsigned) src1 == (unsigned) 0x80000000) { + return 0x7fffffff; + } + return abs(src1); +} + + +static inline int _abs2(int src1) { + short s1[2],r[2]; + int result; + *((int*)s1) = src1; + if ((unsigned short) s1[1] == (unsigned short) 0x8000) r[1] = 0x7fff; + else r[1] = abs(s1[1]); + if ((unsigned short) s1[0] == (unsigned short) 0x8000) r[0] = 0x7fff; + else r[0] = abs(s1[0]); + result = *(int*)r; + return result; + } + + + + +static inline int _add2(int src1, int src2) { + short s1[2], s2[2], r[2]; + int result; + *((int*)s1) = src1; + *((int*)s2) = src2; + r[0] = s1[0] + s2[0]; + r[1] = s1[1] + s2[1]; + result = *(int*)r; + return result; +} + +static inline int _add4(int src1, int src2) { + char c1[4], c2[4], r[4]; + int result; + *((int*)c1) = src1; + *((int*)c2) = src2; + r[0] = c1[0] + c2[0]; + r[1] = c1[1] + c2[1]; + r[2] = c1[2] + c2[2]; + r[3] = c1[3] + c2[3]; + result = *(int*)r; + return result; +} + + + +static inline long long _addsub(unsigned int src1, unsigned int src2) +{ + + int res_lo; + int res_hi; + + res_hi = src1+src2; + res_lo = src1-src2; + return (((unsigned long long) res_hi) << 32) | ((unsigned int) res_lo) ; +} + + +static inline long long _addsub2(unsigned int src1, unsigned int src2) +{ + short s1[2], s2[2], ra[2], rs[2]; + int res_lo; + int res_hi; + + *((int*)s1) = src1; + *((int*)s2) = src2; + ra[0] = s1[0] + s2[0]; + ra[1] = s1[1] + s2[1]; + rs[0] = s1[0] - s2[0]; + rs[1] = s1[1] - s2[1]; + + res_hi = *(int*)ra; + res_lo = *(int*)rs; + return (((unsigned long long) res_hi) << 32) | ((unsigned int) res_lo) ; +} + + +static inline int _avg2(int src1, int src2) { + int low = (((int)1 + (short) src1 + (short) src2) >> 1) & 0XFFFF; + int high1 = src1 >> 16; + int high2 = src2 >> 16; + int high = ((high1 + high2 + 1) >> 1)<< 16; + return high | low; +} + + + +static inline unsigned int _avgu4(unsigned int src1, unsigned int src2) { +unsigned int res0 = ((src1 & 0xFF) + (src2 & 0xFF) + 1) >> 1; + unsigned int res1 = (((src1 & 0xFF00) >> 8) + ((src2 & 0xFF00) >> 8) + 1) >> 1; + unsigned int res2 = (((src1 & 0xFF0000) >> 16) + ((src2 & 0xFF0000) >> 16) + 1) >> 1; + unsigned int res3 = (((src1 & 0xFF000000) >> 24) + ((src2 & 0xFF000000) >> 24) + 1) >> 1; + return (res3 << 24) | (res2 << 16) | (res1 << 8) | res0; +} + + +static inline int TEN_popc (unsigned char b) +{ + int i, result = 0; + for (i = 0; i < 8; i++){ + if (b & 0x1) + result++; + b >>= 1; + } + return result; +} + +static inline unsigned int _bitc4(unsigned int src1) +{ + unsigned int res0 = TEN_popc(src1 & 0xFF); + unsigned int res1 = TEN_popc((src1 & 0xFF00) >> 8); + unsigned int res2 = TEN_popc((src1 & 0xFF0000) >> 16); + unsigned int res3 = TEN_popc((src1 & 0xFF000000) >> 24); + return (res3 << 24) | (res2 << 16) | (res1 << 8) | res0; +} + +static inline unsigned int _bitr(unsigned int src) { + int i; + unsigned r = 0; + for (i = 0; i< 32; ++i) { + r = r | (((src >> i) & 1)<<(31-i)); + } + return r; +} + + +static inline unsigned int _clr(unsigned int src2, int csta, int cstb) +{ + csta &= 0x1f; + cstb &= 0x1f; + if (csta > cstb) + return src2; + else { + unsigned int mask = (((1 << (cstb - csta)) << 1) - 1) << csta; + return src2 & (~mask); + } +} + +static inline unsigned int _clrr(unsigned int src2, int src1) +{ + unsigned int csta = (src1 >> 5) & 0x1f; + unsigned int cstb = src1 & 0x1f; + if (csta > cstb) + return src2; + else { + unsigned int mask = (((1 << (cstb - csta)) << 1) - 1) << csta; + return src2 & (~mask); + } +} + + + + +static inline int _cmpeq2(int src1, int src2) { + short s1[2], s2[2]; + int r0, r1; + int result; + *((int*)s1) = src1; + *((int*)s2) = src2; + r0 = s1[0] == s2[0] ? 1 : 0; + r1 = s1[1] == s2[1] ? 1 : 0; + result = (r1 << 1) | r0; + return result; +} + +static inline int _cmpeq4(int src1, int src2) { + char s1[4], s2[4]; + int r0, r1, r2, r3; + int result; + *((int*)s1) = src1; + *((int*)s2) = src2; + r0 = s1[0] == s2[0] ? 1 : 0; + r1 = s1[1] == s2[1] ? 1 : 0; + r2 = s1[2] == s2[2] ? 1 : 0; + r3 = s1[3] == s2[3] ? 1 : 0; + result = (r3 << 3) | (r2 << 2) | (r1 << 1) | r0; + return result; +} + + +static inline int _cmpgt2(int src1, int src2) { + short s1[2], s2[2]; + int r1, r0; + int result; + *((int*)s1) = src1; + *((int*)s2) = src2; + r0 = s1[0] > s2[0] ? 1 : 0; + r1 = s1[1] > s2[1] ? 1 : 0; + result = (r1<<1) | r0; + return result; +} + + +static inline unsigned int _cmpgtu4(unsigned int src1, unsigned int src2) { + unsigned int s1_0 = (src1 & 0xFF); + unsigned int s1_1 = (src1 & 0xFF00) >> 8; + unsigned int s1_2 = (src1 & 0xFF0000) >> 16; + unsigned int s1_3 = (src1 & 0xFF000000) >> 24; + + unsigned int s2_0 = (src2 & 0xFF); + unsigned int s2_1 = (src2 & 0xFF00) >> 8; + unsigned int s2_2 = (src2 & 0xFF0000) >> 16; + unsigned int s2_3 = (src2 & 0xFF000000) >> 24; + + unsigned int result = 0; + + if (s1_0 > s2_0) + result |= 0x1; + + if (s1_1 > s2_1) + result |= 0x2; + + if (s1_2 > s2_2) + result |= 0x4; + + if (s1_3 > s2_3) + result |= 0x8; + + return result; +} + + + + +static inline long long _ddotp4(unsigned int src1, unsigned int src2) { + unsigned int res0, res1; + short s1_0 = (src1 & 0xffff); + short s1_1 = (src1 & 0xfff0000) >> 16; + + unsigned short s2_0 = (src2 & 0xff); + unsigned short s2_1 = (src2 & 0xff00) >> 8; + unsigned short s2_2 = (src2 & 0xff0000) >> 16; + unsigned short s2_3 = (src2 & 0xff000000) >> 24; + + res0 = ((int)s1_0) * s2_0 + ((int)s1_1) * s2_1; + res1 = ((int)s1_0) * s2_2 + ((int)s1_1) * s2_3; + + return (res1 << 16) | res0; +} + + +static inline long long _ddotph2(long long src1_o_src1_e, unsigned int src2) +{ + + unsigned int src1_o = src1_o_src1_e >> 32; + unsigned int src1_e = src1_o_src1_e & 0xFFFFFFFF; + short ls1_o = src1_o & 0XFFFF; + short hs1_o = src1_o >> 16; +// short ls1_e = src1_e & 0XFFFF; + short hs1_e = src1_e >> 16; + short ls2 = src2 & 0XFFFF; + short hs2 = src2 >> 16; + + unsigned long long res_hi = ls2 * ls1_o + hs2 * hs1_o; + unsigned int res_lo = ls1_o * hs2 + hs1_e * ls2; + return (res_hi << 32) | res_lo; +} + + +static inline long long _ddotpl2(long long src1_o_src1_e, unsigned int src2) +{ + unsigned int src1_o = src1_o_src1_e >> 32; + unsigned int src1_e = src1_o_src1_e & 0xFFFFFFFF; + short ls1_o = src1_o & 0XFFFF; +// short hs1_o = src1_o >> 16; + short ls1_e = src1_e & 0XFFFF; + short hs1_e = src1_e >> 16; + short ls2 = src2 & 0XFFFF; + short hs2 = src2 >> 16; + + unsigned long long res_hi = ls2 * hs1_e + hs2 * ls1_o; + unsigned res_lo = hs1_e * hs2 + ls1_e * ls2; + return (res_hi << 32) | res_lo; +} + + +static inline unsigned int _deal(unsigned int src) +{ + int i; + unsigned short lo = 0, hi = 0; + for (i = 0; i < 32; i+= 2) { + lo >>= 1; + lo |= (src & 0x1) << 15; + src >>= 1; + hi >>= 1; + hi |= (src & 0x1) << 15; + src >>= 1; + } + return (hi << 16) | lo; +} + + +static inline long long _dmv(unsigned int src1, unsigned int src2) +{ + return (((long long) src1) << 32) | src2; +} + + +static inline int _dotpn2(int src1, int src2) { +short int s1_h = src1>>16; + short int s1_l = src1; + short int s2_h = src2>>16; + short int s2_l = src2; + return s1_h * s2_h - s1_l * s2_l; +} + + +static inline int _dotp2(int src1, int src2) { + short int s1_h = src1>>16; + short int s1_l = src1; + short int s2_h = src2>>16; + short int s2_l = src2; + return s1_h * s2_h + s1_l * s2_l; +} + + + +static inline int _dotpnrsu2(int src1, unsigned int src2) +{ + short ls1 = src1 & 0XFFFF; + unsigned short ls2 = src2 & 0XFFFF; + short hs1 = src1 >> 16; + unsigned short hs2 = src2 >> 16; + + int result = (((long long) (int)(hs1 * hs2)) - ((long long) (int)(ls1 * ls2)) + (1 << 15)) >> 16; + return result; +} + + + +static inline int _dotprsu2(int src1, unsigned int src2) { + short ls1 = src1 & 0XFFFF; + unsigned short ls2 = (src2 & 0XFFFF); + short hs1 = src1 >> 16; + unsigned short hs2 = (src2 >> 16); + + int result = (((long long) (int) (ls1 * ls2)) + ((long long) (int) (hs1 * hs2)) + (1LL << 15)) >> 16; + return result; +} + + + + + + + +static inline int _dotpsu4(int src1, unsigned int src2) { + int result; + signed char s1_0 = (src1 & 0xff); + signed char s1_1 = (src1 & 0xff00) >> 8; + signed char s1_2 = (src1 & 0xff0000) >> 16; + signed char s1_3 = (src1 & 0xff000000) >> 24; + + unsigned int s2_0 = (src2 & 0xff); + unsigned int s2_1 = (src2 & 0xff00) >> 8; + unsigned int s2_2 = (src2 & 0xff0000) >> 16; + unsigned int s2_3 = (src2 & 0xff000000) >> 24; + + result = s1_0 * s2_0 + s1_1 * s2_1 + s1_2 * s2_2 + s1_3 * s2_3; + return result; +} + + +static inline unsigned int _dotpu4(unsigned int src1, unsigned int src2) { + unsigned char v1_0 = src1 & 0xff; + unsigned char v1_1 = (src1>>8) & 0xff; + unsigned char v1_2 = (src1>>16) & 0xff; + unsigned char v1_3 = (src1>>24) & 0xff; + + unsigned char v2_0 = src2 & 0xff; + unsigned char v2_1 = (src2>>8) & 0xff; + unsigned char v2_2 = (src2>>16) & 0xff; + unsigned char v2_3 = (src2>>24) & 0xff; + + unsigned v = v1_0 * v2_0 + v1_1 * v2_1 + v1_2 * v2_2 + v1_3 * v2_3; + return v; +} + + +static inline long long _dpack2(unsigned int src1, unsigned int src2){ +unsigned short s1[2], s2[2]; +*((int*)s1) = src1; +*((int*)s2) = src2; +return ((unsigned long long) s1[1] << 48) | ((unsigned long long) s2[1] << 32) | ((unsigned long long) s1[0] << 16) | ((unsigned long long) s2[0]); +} + + +static inline long long _dpackx2(unsigned int src1, unsigned int src2){ +unsigned short s1[2], s2[2]; +*((int*)s1) = src1; +*((int*)s2) = src2; +return ((unsigned long long) s2[0] << 48) | ((unsigned long long) s1[1] << 32) | ((unsigned long long) s1[0] << 16) | ((unsigned long long) s2[1]); +} + +static inline int _ext(int src2, unsigned int csta, unsigned int cstb) +{ + return (src2 << csta) >> cstb; +} + +static inline int _extr(int src2, int src1) +{ + unsigned int csta = (src1 >> 5) & 0x1f; + unsigned int cstb = src1 & 0x1f; + return (src2 << csta) >> cstb; +} + +static inline unsigned int _extu(unsigned int src2, unsigned int csta, unsigned int cstb) +{ + return (src2 << csta) >> cstb; +} + +static inline unsigned int _extur(unsigned int src2, int src1) +{ + unsigned int csta = (src1 >> 5) & 0x1f; + unsigned int cstb = src1 & 0x1f; + return (src2 << csta) >> cstb; +} + + +static inline unsigned long long _hi(double src) { + unsigned long long v; + *(double*)&v = src; + return v>>32; +} + +static inline unsigned int _hill (long long src) +{ + return (unsigned int) (src >> 32); +} + + + +static inline double _itod(unsigned hi, unsigned lo) { + double v; + unsigned long long ll = ((((unsigned long long)(hi))<<32) | (unsigned long long)((unsigned)lo)); + *((unsigned long long *)&v) = ll; + return v; +} + + +static inline long long _itoll(unsigned int src2, unsigned int src1) +{ + return (((long long) src2) << 32) | src1; +} + + +static inline C6X_COMPAT_LONG40 _labs(C6X_COMPAT_LONG40 src2) +{ + long long maxv = (1LL << (40 -1)) - 1; + long long minv = (-1LL << (40 - 1)); + C6X_COMPAT_LONG40 lres = orig_L40_set(src2); + + lres = lres < 0 ? -lres : lres; + if (lres > maxv) lres = maxv; + else if (lres < minv) lres = minv; + + return lres; +} + + +static inline C6X_COMPAT_LONG40 _ldotp2(int src1, int src2) { +return (C6X_COMPAT_LONG40) _dotp2(src1, src2); +} + + +static inline unsigned int _lmbd(unsigned int src1, unsigned int src2) +{ + return norm_shift_amt_U_and_non_U(0,(((int) (src1 << 31)) >> 31) ^ (~src2)); +} + + +static inline unsigned int _lnorm(C6X_COMPAT_LONG40 src2) { +if (src2 == 0) + return 39; + else { + int hi = (int)(src2 >> 32); + int lo = (int)src2; + + + long long temp = (unsigned long long)(unsigned)lo | (unsigned long long)hi << 32; + temp = orig_L40_set(temp); + + if (temp == 0) return 0; + int cnt = 0; + while (((temp >> 39) & 1) == ((temp >> 38) & 1)) { + temp <<= 1; + cnt++; + } + return cnt; + } +} + + +static inline unsigned long long _lo(double src) { + unsigned long long v; + *(double*)&v = src; + return v; +} + + +static inline unsigned int _loll (long long src) +{ + return (unsigned int) src; +} + + +static inline C6X_COMPAT_LONG40 _lsadd(int src1, C6X_COMPAT_LONG40 src2) +{ + long long maxv = (1LL << (40 -1)) - 1; + long long minv = (-1LL << (40 - 1)); + int hi = (int)(src2 >> 32); + int lo = (int)src2; + long long src2_int = (unsigned long long)(unsigned)lo | (unsigned long long)hi << 32; + + + long long src2_int2 = orig_L40_set(src2_int); + + long long res = src1 + src2_int2; + + if (res > maxv) { + res = maxv; + _overflow = 1; + } + else if (res < minv) { + res = minv; + _overflow = 1; + } + + long long res2 = orig_L40_set(res); + + res2 = (signed char)(res2 >> 32); + + C6X_COMPAT_LONG40 lres = (((C6X_COMPAT_LONG40) res2) << 32) | ((unsigned int)res); + return lres; +} + + + +static inline int _max2 (int src1, int src2) { + short s1[2], s2[2], r[2]; + int result; + *((int*)s1) = src1; + *((int*)s2) = src2; + r[0] = s1[0] > s2[0] ? s1[0] : s2[0]; + r[1] = s1[1] > s2[1] ? s1[1] : s2[1]; + result = *(int*)r; + return result; +} + + + + + + +static inline unsigned int _maxu4(unsigned int src1, unsigned int src2) { + unsigned int res0, res1, res2, res3; + unsigned int s1_0 = res0 = (src1 & 0xFF); + unsigned int s1_1 = res1 = (src1 & 0xFF00) >> 8; + unsigned int s1_2 = res2 = (src1 & 0xFF0000) >> 16; + unsigned int s1_3 = res3 = (src1 & 0xFF000000) >> 24; + + unsigned int s2_0 = (src2 & 0xFF); + unsigned int s2_1 = (src2 & 0xFF00) >> 8; + unsigned int s2_2 = (src2 & 0xFF0000) >> 16; + unsigned int s2_3 = (src2 & 0xFF000000) >> 24; + +// unsigned int res = 0; + + if (s1_0 < s2_0) + res0 = s2_0; + + if (s1_1 < s2_1) + res1 = s2_1; + + if (s1_2 < s2_2) + res2 = s2_2; + + if (s1_3 < s2_3) + res3 = s2_3; + + return (res3 << 24) | (res2 << 16) | (res1 << 8) | res0; + + +} + +static inline int _min2(int src1, int src2) { + short s1[2], s2[2], r[2]; + int result; + *((int*)s1) = src1; + *((int*)s2) = src2; + r[0] = s1[0] < s2[0] ? s1[0] : s2[0]; + r[1] = s1[1] < s2[1] ? s1[1] : s2[1]; + result = *(int*)r; + return result; +} + + +static inline unsigned int _minu4(unsigned int src1, unsigned int src2) { +unsigned int res0, res1, res2, res3; + unsigned int s1_0 = res0 = (src1 & 0xFF); + unsigned int s1_1 = res1 = (src1 & 0xFF00) >> 8; + unsigned int s1_2 = res2 = (src1 & 0xFF0000) >> 16; + unsigned int s1_3 = res3 = (src1 & 0xFF000000) >> 24; + + unsigned int s2_0 = (src2 & 0xFF); + unsigned int s2_1 = (src2 & 0xFF00) >> 8; + unsigned int s2_2 = (src2 & 0xFF0000) >> 16; + unsigned int s2_3 = (src2 & 0xFF000000) >> 24; + +// unsigned int res = 0; + + if (s1_0 > s2_0) + res0 = s2_0; + + if (s1_1 > s2_1) + res1 = s2_1; + + if (s1_2 > s2_2) + res2 = s2_2; + + if (s1_3 > s2_3) + res3 = s2_3; + + return (res3 << 24) | (res2 << 16) | (res1 << 8) | res0; +} + + +static inline int _mpy(int src1, int src2) { +return (short) src1 * (short) src2; +} + + +static inline int _mpyh(int src1, int src2) { +return (short) (src1 >> 16) * (short) (src2 >> 16); +} + + +static inline long long _mpyhill (int src1, int src2) +{ + short s1 = src1 >> 16; + return ((long long) src2) * s1; +} + +static inline int _mpyhir(int src1, int src2) +{ + short s1 = src1 >> 16; + long long result = ((long long) src2) * s1 + (1 << 14); + result >>= 15; + return result; +} + + +static inline int _mpyhl(int src1, int src2) { +return (short) (src1 >> 16) * (short) (src2); +} + +static inline unsigned int _mpyhlu(unsigned int src1, unsigned int src2) { +return (unsigned short) (src1 >> 16) * (unsigned short) (src2); +} + +static inline int _mpyhslu(int src1, unsigned int src2) { +return (short) (src1 >> 16) * (unsigned short) src2; +} + + +static inline int _mpyhsu(int src1, unsigned int src2) { +return (short) (src1 >>16) * (unsigned short) (src2 >>16); +} + + +static inline unsigned int _mpyhu(unsigned int src1, unsigned int src2) { +return (unsigned short) (src1 >>16) * (unsigned short) (src2 >> 16); +} + + +static inline int _mpyhuls(unsigned int src1, int src2) { +return (unsigned short) (src1 >>16) * (signed short) (src2); +} + + +static inline int _mpyhus(unsigned int src1, int src2) { +return (unsigned short) (src1 >> 16) * (short) (src2 >>16); +} + + + +static inline long long _mpyidll (int src1, int src2) +{ + return (long long) src1 * src2; +} + + +static inline int _mpylh(int src1, int src2) { +return (signed short) (src1 & 0xffff) * (signed short) (src2 >> 16); +} + +static inline unsigned int _mpylhu(unsigned int src1, unsigned int src2) { +return (unsigned short) src1 * (unsigned short) (src2 >> 16); +} + + +static inline long long _mpylill (int src1, int src2) +{ + return ((long long) src2) * ((short)src1); +} + + + +static inline int _mpylir(int src1, int src2) +{ + short s1 = src1; + long long result = ((long long) src2) * s1 + (1 << 14); + result >>= 15; + return result; +} + + +static inline int _mpylshu(int src1, unsigned int src2) { +return (short) src1 * (unsigned short) (src2 >> 16); +} + + +static inline int _mpyluhs(unsigned int src1, int src2) { +return (unsigned short) src1 * (short) (src2 >> 16); +} + + + +static inline int _mpysu(int src1, unsigned int src2) { +return (short) src1 * (unsigned short) src2; +} + + + +static inline long long _mpysu4ll (int src1, unsigned int src2) { + unsigned short res0, res1, res2, res3; + signed char s1_0 = (src1 & 0xff); + signed char s1_1 = (src1 & 0xff00) >> 8; + signed char s1_2 = (src1 & 0xff0000) >> 16; + signed char s1_3 = (src1 & 0xff000000) >> 24; + + unsigned short s2_0 = (src2 & 0xff); + unsigned short s2_1 = (src2 & 0xff00) >> 8; + unsigned short s2_2 = (src2 & 0xff0000) >> 16; + unsigned short s2_3 = (src2 & 0xff000000) >> 24; + + res0 = s1_0 * s2_0; + res1 = s1_1 * s2_1; + res2 = s1_2 * s2_2; + res3 = s1_3 * s2_3; + + return (((unsigned long long) res3) << 48) + | (((unsigned long long) res2) << 32) + | (((unsigned long long) res1) << 16) + | res0; +} + +static inline unsigned int _mpyu(unsigned int src1, unsigned int src2) { + unsigned v = (unsigned short)src1 * (unsigned short)src2; + return v; +} + +static inline int _mpyus(unsigned int src1, int src2) { +return (unsigned short) src1 * (short) src2; +} + +static inline long long _mpyu4ll (unsigned int src1, unsigned int src2) { + unsigned short res0, res1, res2, res3; + unsigned char s1_0 = (src1 & 0xff); + unsigned char s1_1 = (src1 & 0xff00) >> 8; + unsigned char s1_2 = (src1 & 0xff0000) >> 16; + unsigned char s1_3 = (src1 & 0xff000000) >> 24; + + unsigned short s2_0 = (src2 & 0xff); + unsigned short s2_1 = (src2 & 0xff00) >> 8; + unsigned short s2_2 = (src2 & 0xff0000) >> 16; + unsigned short s2_3 = (src2 & 0xff000000) >> 24; + + res0 = s1_0 * s2_0; + res1 = s1_1 * s2_1; + res2 = s1_2 * s2_2; + res3 = s1_3 * s2_3; + + return (((unsigned long long) res3) << 48) + | (((unsigned long long) res2) << 32) + | (((unsigned long long) res1) << 16) + | res0; +} + + +static inline long long _mpy2ir(unsigned int src1, unsigned int src2) +{ + if ((src1 == 0x8000) && (src2 == 0x80000000)) { + _overflow = 1; + return 0; + } + else { + short ls1 = src1 & 0xffff; + short hs1 = src1 >> 16; + unsigned long long hi = (((long long) hs1) * (int) src2 + (1 << 14)) >> 15; + unsigned long long lo = ((((long long) ls1) * (int) src2 + (1 << 14)) >> 15) & 0xFFFFFFFF; + return (hi << 32) | lo; + } +} + + +static inline long long _mpy2ll (int src1, int src2) { + short ls1 = src1 & 0xffff; + short hs1 = src1 >> 16; + short ls2 = src2 & 0xffff; + short hs2 = src2 >> 16; + + unsigned long long hi = hs1 * hs2; + unsigned long long lo = (ls1 * ls2) & 0xFFFFFFFF; + + return (hi << 32) | lo; + +} + + +static inline int _mpy32(int src1, int src2) +{ + return src1 * src2; +} + + +static inline long long _mpy32ll(int src1, int src2) +{ + return ((long long) src1) * src2; +} + +static inline long long _mpy32su(int src1, unsigned int src2) +{ + return ((long long) src1) * ((int) src2); +} + +static inline long long _mpy32u(unsigned int src1, unsigned int src2) +{ + return ((long long) ((int) src1)) * ((long long) ((int) src2)); +} + +static inline long long _mpy32us(unsigned int src1, int src2) +{ + return ((int) src1) * ((long long) src2); +} + +static inline int _mvd (int src2) +{ + return src2; +} + + +static inline unsigned int _norm(int src2) +{ + return norm_shift_amt_U_and_non_U(1,src2); +} + + +static inline unsigned int _pack2 (unsigned int src1, unsigned int src2) { + short s1[2], s2[2], r[2]; + int result; + *((int*)s1) = src1; + *((int*)s2) = src2; + r[0] = s2[0]; + r[1] = s1[0]; + result = *(int*)r; + return result; +} + + +static inline int _packh2 (unsigned int src1, unsigned int src2) { + unsigned v0 = src1 & 0xffff0000; + unsigned v1 = src2 >> 16; + unsigned v = v0|v1; + return v; + +} + +static inline unsigned int _packh4 (unsigned int src1, unsigned int src2) { + unsigned v3 = (src1 >> 24) & 0xff; + unsigned v2 = (src1 >> 8) & 0xff; + unsigned v1 = (src2 >> 24) & 0xff; + unsigned v0 = (src2 >> 8) & 0xff; + unsigned v = (v3<<24) | (v2<<16) | (v1 << 8) | v0; + return v; +} + +static inline unsigned int _packhl2 (unsigned int src1, unsigned int src2) { + unsigned v0 = src1 & 0xffff0000; + unsigned v1 = src2 & 0x0000ffff; + unsigned v = v0|v1; + return v; +} + +static inline unsigned int _packlh2 (unsigned int src1, unsigned int src2) { + unsigned v0 = src1 << 16; + unsigned v1 = (src2 >> 16) & 0xffff; + unsigned v = v0|v1; + return v; +} + + + + +static inline unsigned int _packl4 (unsigned int src1, unsigned int src2) { + unsigned v3 = (src1 >> 16) & 0xff; + unsigned v2 = (src1) & 0xff; + unsigned v1 = (src2 >> 16) & 0xff; + unsigned v0 = (src2) & 0xff; + unsigned v = (v3<<24) | (v2<<16) | (v1 << 8) | v0; + return v; +} + + + + +static inline unsigned int _rpack2 (unsigned int src1, unsigned int src2) { +int s1 = (int) src1; +int s2 = (int) src2; +s1 = util_shift_right_saturate_n (s1, -1, 32); +s2 = util_shift_right_saturate_n (s2, -1, 32); +return (unsigned int) (s1 & 0xffff0000) | (unsigned int) ((s2 & 0xffff0000) >>16); +} + + +static inline unsigned int _rotl (unsigned int src1, unsigned int src2) +{ + src2 &= 0x1f; + return (src1 << src2) | (src1 >> (32 - src2)); +} + + +static inline int _sadd(int src1, int src2) { +signed long long res; +signed long long maxv, minv; +maxv = (1LL << (32-1)) - 1; +minv = (-1LL << (32-1)); +res = (long long) src1 + (long long) src2; +if (res > maxv) { + res = maxv; + _overflow = 1; + } +else if (res < minv ) { + res = minv; + _overflow = 1; + } +return (int) res; +} + +static inline long long _saddsub(unsigned int src1, unsigned int src2) { +int radd; +signed long long rsub; + +signed long long maxv, minv; +maxv = (1LL << (32-1)) - 1; +minv = (-1LL << (32-1)); + +radd = (int) src1 + (int) src2; + +// saturate on subtract, not add + + +rsub = (long long) ((int) src1) - (long long) ((int) src2); +if (rsub > maxv) { + rsub = maxv; + /* NOTE: TI c6x does NOT set the overflow register even if results saturate */ + /* _overflow = 1; */ + } +else if (rsub < minv ) { + rsub = minv; + /* NOTE: TI c6x does NOT set the overflow register even if results saturate */ + /* _overflow = 1; */ + } + +return (((unsigned long long) radd) << 32) | ( rsub & 0x00000000ffffffff ) ; +} + + + +static inline long long _saddsub2(unsigned int src1, unsigned int src2) { +signed int radd[2]; +signed int rsub[2]; +signed short s1[2], s2[2]; + +signed int maxv, minv; +maxv = (1L << (16-1)) - 1; +minv = (-1L << (16-1)); + +*((int*)s1) = src1; +*((int*)s2) = src2; + +radd[0] = (int) s1[0] + (int) s2[0]; +radd[1] = (int) s1[1] + (int) s2[1]; + +rsub[0] = (int) s1[0] - (int) s2[0]; +rsub[1] = (int) s1[1] - (int) s2[1]; + +if (radd[0] > maxv) { + radd[0] = maxv; + /* NOTE: TI c6x does NOT set the overflow register even if results saturate */ + /* _overflow = 1; */ + } +else if (radd[0] < minv ) { + radd[0] = minv; + /* NOTE: TI c6x does NOT set the overflow register even if results saturate */ + /* _overflow = 1; */ + } + +if (radd[1] > maxv) { + radd[1] = maxv; + /* NOTE: TI c6x does NOT set the overflow register even if results saturate */ + /* _overflow = 1; */ + } +else if (radd[1] < minv ) { + radd[1] = minv; + /* NOTE: TI c6x does NOT set the overflow register even if results saturate */ + /* _overflow = 1; */ + } + + +if (rsub[0] > maxv) { + rsub[0] = maxv; + /* NOTE: TI c6x does NOT set the overflow register even if results saturate */ + /* _overflow = 1; */ + } +else if (rsub[0] < minv ) { + rsub[0] = minv; + /* NOTE: TI c6x does NOT set the overflow register even if results saturate */ + /* _overflow = 1; */ + } + +if (rsub[1] > maxv) { + rsub[1] = maxv; + /* NOTE: TI c6x does NOT set the overflow register even if results saturate */ + /* _overflow = 1; */ + } +else if (rsub[1] < minv ) { + rsub[1] = minv; + /* NOTE: TI c6x does NOT set the overflow register even if results saturate */ + /* _overflow = 1; */ + } + + +return ((((unsigned long long) radd[1]) & 0x000000000000ffff) << 48) | + ((((unsigned long long) radd[0]) & 0x000000000000ffff) << 32) | + ((((unsigned long long) rsub[1]) & 0x000000000000ffff) << 16) | + ((((unsigned long long) rsub[0]) & 0x000000000000ffff)); +} + + + +static inline int _sadd2(int src1, int src2) { +signed short s1[2], s2[2]; +signed int r[2], maxv, minv; + +maxv = (1L << (16-1)) - 1; +minv = (-1L << (16-1)); + + +*((int*)s1) = src1; +*((int*)s2) = src2; + +r[0] = (int) s1[0] + (int) s2[0]; +r[1] = (int) s1[1] + (int) s2[1]; + +if (r[0] > maxv) { + r[0] = maxv; + /* NOTE: TI c6x does NOT set the overflow register even if results saturate */ + /* _overflow = 1; */ + } +else if (r[0] < minv ) { + r[0] = minv; + /* NOTE: TI c6x does NOT set the overflow register even if results saturate */ + /* _overflow = 1; */ + } +if (r[1] > maxv) { + r[1] = maxv; + /* NOTE: TI c6x does NOT set the overflow register even if results saturate */ + /* _overflow = 1; */ + } +else if (r[1] < minv ) { + r[1] = minv; + /* NOTE: TI c6x does NOT set the overflow register even if results saturate */ + /* _overflow = 1; */ + } + +return ((r[1] & 0xffff) << 16 ) | (r[0] & 0xffff) ; +} + + +static inline int _saddus2(unsigned int src1, int src2) { +int res0, res1; + unsigned int s1_0 = (src1 & 0xffff); + unsigned int s1_1 = (src1 & 0xffff0000) >> 16; + + short s2_0 = (src2 & 0xffff); + short s2_1 = (src2 & 0xffff0000) >> 16; + + res0 = s1_0 + s2_0; + res1 = s1_1 + s2_1; + + if (res0 >= 0x10000) + res0 = 0xffff; + else if (res0 < 0) + res0 = 0; + + if (res1 >= 0x10000) + res1 = 0xffff; + else if (res1 < 0) + res1 = 0; + + return (res1 << 16) | res0; +} + + +static inline unsigned int _saddu4(unsigned int src1, unsigned int src2) { +unsigned int res0, res1, res2, res3; + unsigned int s1_0 = (src1 & 0xff); + unsigned int s1_1 = (src1 & 0xff00) >> 8; + unsigned int s1_2 = (src1 & 0xff0000) >> 16; + unsigned int s1_3 = (src1 & 0xff000000) >> 24; + + unsigned int s2_0 = (src2 & 0xff); + unsigned int s2_1 = (src2 & 0xff00) >> 8; + unsigned int s2_2 = (src2 & 0xff0000) >> 16; + unsigned int s2_3 = (src2 & 0xff000000) >> 24; + + res0 = s1_0 + s2_0; + res1 = s1_1 + s2_1; + res2 = s1_2 + s2_2; + res3 = s1_3 + s2_3; + + if (res0 >= 0x100) + res0 = 0xff; + + if (res1 >= 0x100) + res1 = 0xff; + + if (res2 >= 0x100) + res2 = 0xff; + + if (res3 >= 0x100) + res3 = 0xff; + + return (res3 << 24) | (res2 << 16) | (res1 << 8) | res0; + +} + + + +static inline int _sat(C6X_COMPAT_LONG40 src2) +{ + long long maxv = (1LL << (32-1)) - 1; + long long minv = (-1LL << (32-1)); + + int hi = (int)(src2 >> 32); + int lo = (int)src2; + long long temp = (unsigned long long)(unsigned)lo | (unsigned long long)hi << 32; + temp = orig_L40_set(temp); + + if (temp > maxv) { + temp = maxv; + _overflow = 1; + } + else if (temp < minv) { + temp = minv; + _overflow = 1; + } + return (int) temp; +} + +static inline unsigned int _set(unsigned int src2, unsigned int csta, unsigned int cstb) +{ + csta &= 0x1f; + cstb &= 0x1f; + if (csta > cstb) + return src2; + else { + unsigned int mask = (((1 << (cstb - csta)) << 1) - 1) << csta; + return src2 | mask; + } +} + +static inline unsigned int _setr(unsigned int src2, int src1) +{ + unsigned int csta = (src1 >> 5) & 0x1f; + unsigned int cstb = src1 & 0x1f; + if (csta > cstb) + return src2; + else { + unsigned int mask = (((1 << (cstb - csta)) << 1) - 1) << csta; + return src2 | mask; + } +} + + +static inline unsigned int _shfl (unsigned int src2) +{ + unsigned short lo = src2; + unsigned short hi = src2 >> 16; + unsigned int result = 0; + int i; + for (i = 0; i < 32; i+= 2) { + result >>= 1; + result |= (lo & 0x1) << 31; + lo >>= 1; + result >>= 1; + result |= (hi & 0x1) << 31; + hi >>= 1; + } + return result; +} + +static inline long long _shfl3 (unsigned int src1, unsigned int src2) +{ + unsigned short lo = src2; + unsigned short hi = src1 >> 16; + unsigned short mid = src1; + unsigned long long result = 0; + int i; + for (i = 0; i < 32; i+= 2) { + result >>= 1; + result |= ((unsigned long long) (lo & 0x1)) << 47; + lo >>= 1; + result >>= 1; + result |= ((unsigned long long) (mid & 0x1)) << 47; + mid >>= 1; + result >>= 1; + result |= ((unsigned long long) (hi & 0x1)) << 47; + hi >>= 1; + } + return result; +} + + + +static inline unsigned int _shlmb (unsigned int src1, unsigned int src2) +{ + return (src2 << 8) | (src1 >> 24); +} + +static inline unsigned int _shrmb (unsigned int src1, unsigned int src2) +{ + return (src2 >> 8) | (src1 << 24); +} + + +static inline unsigned int _shru2 (unsigned int src1, unsigned int src2) { +unsigned short hs1 = src1 >> 16; + unsigned short ls1 = src1 & 0xFFFF; + hs1 >>= src2; + ls1 >>= src2; + return (hs1 << 16) | ls1; +} + + +static inline int _shr2 (int src1, unsigned int src2) { + short s1[2], result[2]; + *((int*)s1) = src1; + src2 = src2 & 31; + result[0] = (int)s1[0] >> src2; + result[1] = (int)s1[1] >> src2; + + return *(int*)result; +} + + +static inline int _smpy (int src1, int src2) { +unsigned long long result; +result = (((short) src1 * (short) src2) << 1); + +if ((result & 0xffffffff) == 0x80000000){ + result = 0x7fffffff; + _overflow = 1; + } +return (int) (result); +} + +static inline int _smpyh (int src1, int src2) { +unsigned long long result; +result = ((short) (src1 >> 16) * (short) (src2 >> 16)) << 1; +if ((result & 0xffffffff) == 0x80000000){ + result = 0x7fffffff; + _overflow = 1; + } +return (int) (result); +} + +static inline int _smpyhl (int src1, int src2) { +unsigned long long result; +result = ((short) (src1 >> 16) * (short) (src2)) << 1; +if ((result & 0xffffffff) == 0x80000000){ + result = 0x7fffffff; + _overflow = 1; + } +return (int) (result); +} + +static inline int _smpylh (int src1, int src2) { +unsigned long long result; +result = ((short) (src1) * (short) (src2 >> 16)) << 1; +if ((result & 0xffffffff) == 0x80000000){ + result = 0x7fffffff; + _overflow = 1; + } +return (int) (result); +} + +static inline long long _smpy2ll (int src1, int src2) { + short ls1 = src1 & 0XFFFF; + short hs1 = src1 >> 16; + short ls2 = src2 & 0XFFFF; + short hs2 = src2 >> 16; + + unsigned long long hi = (hs1 * hs2) << 1; + unsigned long long lo = ((ls1 * ls2) << 1) & 0xFFFFFFFF; + if ((hi & 0xffffffff) == 0x80000000){ + hi = 0x7fffffff; + _overflow = 1; + } + + if ((lo & 0xffffffff) == 0x80000000){ + lo = 0x7fffffff; + _overflow = 1; + } + + return (hi << 32) | lo; +} + + + + +static inline int _smpy32(int src1, int src2) +{ + long long res = (long long) src1 * src2; + res <<= 1; + res >>= 32; + return res; +} + +static inline unsigned char TEN_satu8 (short src) +{ + if (src > 0xff) + return 0xff; + else if (src < 0) + return 0; + else + return src; +} + +static inline int _spack2 (int src1, int src2) { +short s1 = (short) util_saturate_n_no_state(src1,16); +short s2 = (short) util_saturate_n_no_state(src2,16); +return ( (unsigned int) s1 << 16) | (((int) s2) & 0xFFFF); +} + + +static inline unsigned int _spacku4 (int src1, int src2) { + short lolo = src2; + short lohi = src2 >> 16; + short hilo = src1; + short hihi = src1 >> 16; + + lolo = TEN_satu8(lolo); + lohi = TEN_satu8(lohi); + hilo = TEN_satu8(hilo); + hihi = TEN_satu8(hihi); + + return (((unsigned int) hihi) << 24) | (((unsigned int) hilo) << 16) | (lohi << 8) | lolo; +} + + + +static inline int _sshl (int src1, unsigned int src2) { +short local2 = (short)(src2 & 0x7FFF); +return (int) util_shift_right_saturate_n(src1, -local2, 32); +} + + + + +static inline int _sshvl (int src2, int src1) { + short s1; + if (src1 > 31) + s1 = 31; + else if (src1 < -31) + s1 = -31; + else + s1 = src1; + + return (int) util_shift_right_saturate_n(src2, -s1, 32); +} + + + + + +static inline int _sshvr (int src2, int src1) { +short s1; + if (src1 > 31) + s1 = 31; + else if (src1 < -31) + s1 = -31; + else + s1 = src1; + return (int) util_shift_right_saturate_n(src2, s1, 32); +} + + + + +static inline int _ssub(int src1, int src2) { +signed long long res; +signed long long maxv, minv; +maxv = (1LL << (32-1)) - 1; +minv = (-1LL << (32-1)); +res = (long long) src1 - (long long) src2; +if (res > maxv) { + res = maxv; + _overflow = 1; + } +else if (res < minv ) { + res = minv; + _overflow = 1; + } +return (int) res; +} + +static inline int _ssub2(int src1, int src2) { +signed short s1[2], s2[2]; +signed int r[2], maxv, minv; + +maxv = (1L << (16-1)) - 1; +minv = (-1L << (16-1)); + + +*((int*)s1) = src1; +*((int*)s2) = src2; + +r[0] = (int) s1[0] - (int) s2[0]; +r[1] = (int) s1[1] - (int) s2[1]; + +if (r[0] > maxv) { + r[0] = maxv; + /* NOTE: TI c6x does NOT set the overflow register even if results saturate */ + /* _overflow = 1; */ + } +else if (r[0] < minv ) { + r[0] = minv; + /* NOTE: TI c6x does NOT set the overflow register even if results saturate */ + /* _overflow = 1; */ + } +if (r[1] > maxv) { + r[1] = maxv; + /* NOTE: TI c6x does NOT set the overflow register even if results saturate */ + /* _overflow = 1; */ + } +else if (r[1] < minv ) { + r[1] = minv; + /* NOTE: TI c6x does NOT set the overflow register even if results saturate */ + /* _overflow = 1; */ + } + +return ((r[1] & 0xffff) << 16 ) | (r[0] & 0xffff) ; +} + + +static inline int _subabs4 (int src1, int src2) { + int res0, res1, res2, res3; + unsigned int s1_0 = (src1 & 0xff); + unsigned int s1_1 = (src1 & 0xff00) >> 8; + unsigned int s1_2 = (src1 & 0xff0000) >> 16; + unsigned int s1_3 = (src1 & 0xff000000) >> 24; + + unsigned int s2_0 = (src2 & 0xff); + unsigned int s2_1 = (src2 & 0xff00) >> 8; + unsigned int s2_2 = (src2 & 0xff0000) >> 16; + unsigned int s2_3 = (src2 & 0xff000000) >> 24; + + res0 = s1_0 - s2_0; + res1 = s1_1 - s2_1; + res2 = s1_2 - s2_2; + res3 = s1_3 - s2_3; + + if (res0 < 0) + res0 = -res0; + + if (res1 < 0) + res1 = -res1; + + if (res2 < 0) + res2 = -res2; + + if (res3 < 0) + res3 = -res3; + + return (res3 << 24) | (res2 << 16) | (res1 << 8) | res0; +} + + +static inline unsigned int _subc (unsigned int src1, unsigned int src2) +{ + if ( src1 >= src2) + return ((src1 - src2) << 1) + 1; + else + return src1 << 1; +} + + + +static inline int _sub2(int src1, int src2) { + short s1[2], s2[2], r[2]; + int result; + *((int*)s1) = src1; + *((int*)s2) = src2; + r[0] = s1[0] - s2[0]; + r[1] = s1[1] - s2[1]; + result = *(int*)r; + return result; +} + + +static inline int _sub4(int src1, int src2) { + char c1[4], c2[4], r[4]; + int result; + *((int*)c1) = src1; + *((int*)c2) = src2; + r[0] = c1[0] - c2[0]; + r[1] = c1[1] - c2[1]; + r[2] = c1[2] - c2[2]; + r[3] = c1[3] - c2[3]; + result = *(int*)r; + return result; +} + + +static inline int _swap4 (unsigned int src1) { + unsigned char v0 = src1; + unsigned char v1 = src1 >> 8; + unsigned char v2 = src1 >> 16; + unsigned char v3 = src1 >> 24; + unsigned v = v0<<8 | v1 | v2<<24 | v3<<16; + return v; +} + +static inline unsigned int _unpkhu4 (unsigned int src1) { + unsigned v0 = src1>>24; + unsigned v1 = (src1>>16) & 0xff; + return (v0<<16) | v1; +} + +static inline unsigned int _unpklu4 (unsigned int src1) { + unsigned v1 = (src1>>8) & 0xff; + unsigned v0 = (src1) & 0xff; + return (v1<<16) | v0; +} + + + + +static inline unsigned int _xpnd2 (unsigned int src1) { + int v0 = (src1 & 0x1) ? 0x0000ffff : 0x00000000; + int v1 = (src1 & 0x2) ? 0xffff0000 : 0x00000000; + return v0|v1; +} + +static inline unsigned int _xpnd4 (unsigned int src1) { + int v0 = (src1 & 0x1) ? 0x000000ff : 0x00000000; + int v1 = (src1 & 0x2) ? 0x0000ff00 : 0x00000000; + int v2 = (src1 & 0x4) ? 0x00ff0000 : 0x00000000; + int v3 = (src1 & 0x8) ? 0xff000000 : 0x00000000; + int r = v0|v1|v2|v3; + return r; +} + + + +// end of Implemented in alphabetical order + + +#endif /* __C6X_COMPAT__H */ diff --git a/tools/sdk/include/esp32/xtensa/cacheasm.h b/tools/sdk/include/esp32/xtensa/cacheasm.h new file mode 100755 index 00000000..225e01b3 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/cacheasm.h @@ -0,0 +1,962 @@ +/* + * xtensa/cacheasm.h -- assembler-specific cache related definitions + * that depend on CORE configuration + * + * This file is logically part of xtensa/coreasm.h , + * but is kept separate for modularity / compilation-performance. + */ + +/* + * Copyright (c) 2001-2014 Cadence Design Systems, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef XTENSA_CACHEASM_H +#define XTENSA_CACHEASM_H + +#include +#include +#include +#include + +/* + * This header file defines assembler macros of the form: + * cache_ + * where is 'i' or 'd' for instruction and data caches, + * and indicates the function of the macro. + * + * The following functions are defined, + * and apply only to the specified cache (I or D): + * + * reset + * Resets the cache. + * + * sync + * Makes sure any previous cache instructions have been completed; + * ie. makes sure any previous cache control operations + * have had full effect and been synchronized to memory. + * Eg. any invalidate completed [so as not to generate a hit], + * any writebacks or other pipelined writes written to memory, etc. + * + * invalidate_line (single cache line) + * invalidate_region (specified memory range) + * invalidate_all (entire cache) + * Invalidates all cache entries that cache + * data from the specified memory range. + * NOTE: locked entries are not invalidated. + * + * writeback_line (single cache line) + * writeback_region (specified memory range) + * writeback_all (entire cache) + * Writes back to memory all dirty cache entries + * that cache data from the specified memory range, + * and marks these entries as clean. + * NOTE: on some future implementations, this might + * also invalidate. + * NOTE: locked entries are written back, but never invalidated. + * NOTE: instruction caches never implement writeback. + * + * writeback_inv_line (single cache line) + * writeback_inv_region (specified memory range) + * writeback_inv_all (entire cache) + * Writes back to memory all dirty cache entries + * that cache data from the specified memory range, + * and invalidates these entries (including all clean + * cache entries that cache data from that range). + * NOTE: locked entries are written back but not invalidated. + * NOTE: instruction caches never implement writeback. + * + * lock_line (single cache line) + * lock_region (specified memory range) + * Prefetch and lock the specified memory range into cache. + * NOTE: if any part of the specified memory range cannot + * be locked, a Load/Store Error (for dcache) or Instruction + * Fetch Error (for icache) exception occurs. These macros don't + * do anything special (yet anyway) to handle this situation. + * + * unlock_line (single cache line) + * unlock_region (specified memory range) + * unlock_all (entire cache) + * Unlock cache entries that cache the specified memory range. + * Entries not already locked are unaffected. + * + * coherence_on + * coherence_off + * Turn off and on cache coherence + * + */ + + + +/*************************** GENERIC -- ALL CACHES ***************************/ + + +/* + * The following macros assume the following cache size/parameter limits + * in the current Xtensa core implementation: + * cache size: 1024 bytes minimum + * line size: 16 - 64 bytes + * way count: 1 - 4 + * + * Minimum entries per way (ie. per associativity) = 1024 / 64 / 4 = 4 + * Hence the assumption that each loop can execute four cache instructions. + * + * Correspondingly, the offset range of instructions is assumed able to cover + * four lines, ie. offsets {0,1,2,3} * line_size are assumed valid for + * both hit and indexed cache instructions. Ie. these offsets are all + * valid: 0, 16, 32, 48, 64, 96, 128, 192 (for line sizes 16, 32, 64). + * This is true of all original cache instructions + * (dhi, ihi, dhwb, dhwbi, dii, iii) which have offsets + * of 0 to 1020 in multiples of 4 (ie. 8 bits shifted by 2). + * This is also true of subsequent cache instructions + * (dhu, ihu, diu, iiu, diwb, diwbi, dpfl, ipfl) which have offsets + * of 0 to 240 in multiples of 16 (ie. 4 bits shifted by 4). + * + * (Maximum cache size, currently 32k, doesn't affect the following macros. + * Cache ways > MMU min page size cause aliasing but that's another matter.) + */ + + + +/* + * Macro to apply an 'indexed' cache instruction to the entire cache. + * + * Parameters: + * cainst instruction/ that takes an address register parameter + * and an offset parameter (in range 0 .. 3*linesize). + * size size of cache in bytes + * linesize size of cache line in bytes (always power-of-2) + * assoc_or1 number of associativities (ways/sets) in cache + * if all sets affected by cainst, + * or 1 if only one set (or not all sets) of the cache + * is affected by cainst (eg. DIWB or DIWBI [not yet ISA defined]). + * aa, ab unique address registers (temporaries). + * awb set to other than a0 if wb type of instruction + * loopokay 1 allows use of zero-overhead loops, 0 does not + * immrange range (max value) of cainst's immediate offset parameter, in bytes + * (NOTE: macro assumes immrange allows power-of-2 number of lines) + */ + + .macro cache_index_all cainst, size, linesize, assoc_or1, aa, ab, loopokay, maxofs, awb=a0 + + // Number of indices in cache (lines per way): + .set .Lindices, (\size / (\linesize * \assoc_or1)) + // Number of indices processed per loop iteration (max 4): + .set .Lperloop, .Lindices + .ifgt .Lperloop - 4 + .set .Lperloop, 4 + .endif + // Also limit instructions per loop if cache line size exceeds immediate range: + .set .Lmaxperloop, (\maxofs / \linesize) + 1 + .ifgt .Lperloop - .Lmaxperloop + .set .Lperloop, .Lmaxperloop + .endif + // Avoid addi of 128 which takes two instructions (addmi,addi): + .ifeq .Lperloop*\linesize - 128 + .ifgt .Lperloop - 1 + .set .Lperloop, .Lperloop / 2 + .endif + .endif + + // \size byte cache, \linesize byte lines, \assoc_or1 way(s) affected by each \cainst. + // XCHAL_ERRATUM_497 - don't execute using loop, to reduce the amount of added code + .ifne (\loopokay & XCHAL_HAVE_LOOPS && !XCHAL_ERRATUM_497) + + movi \aa, .Lindices / .Lperloop // number of loop iterations + // Possible improvement: need only loop if \aa > 1 ; + // however \aa == 1 is highly unlikely. + movi \ab, 0 // to iterate over cache + loop \aa, .Lend_cachex\@ + .set .Li, 0 ; .rept .Lperloop + \cainst \ab, .Li*\linesize + .set .Li, .Li+1 ; .endr + addi \ab, \ab, .Lperloop*\linesize // move to next line +.Lend_cachex\@: + + .else + + movi \aa, (\size / \assoc_or1) + // Possible improvement: need only loop if \aa > 1 ; + // however \aa == 1 is highly unlikely. + movi \ab, 0 // to iterate over cache + .ifne ((\awb !=a0) & XCHAL_ERRATUM_497) // don't use awb if set to a0 + movi \awb, 0 + .endif +.Lstart_cachex\@: + .set .Li, 0 ; .rept .Lperloop + \cainst \ab, .Li*\linesize + .set .Li, .Li+1 ; .endr + .ifne ((\awb !=a0) & XCHAL_ERRATUM_497) // do memw after 8 cainst wb instructions + addi \awb, \awb, .Lperloop + blti \awb, 8, .Lstart_memw\@ + memw + movi \awb, 0 +.Lstart_memw\@: + .endif + addi \ab, \ab, .Lperloop*\linesize // move to next line + bltu \ab, \aa, .Lstart_cachex\@ + .endif + + .endm + + +/* + * Macro to apply a 'hit' cache instruction to a memory region, + * ie. to any cache entries that cache a specified portion (region) of memory. + * Takes care of the unaligned cases, ie. may apply to one + * more cache line than $asize / lineSize if $aaddr is not aligned. + * + * + * Parameters are: + * cainst instruction/macro that takes an address register parameter + * and an offset parameter (currently always zero) + * and generates a cache instruction (eg. "dhi", "dhwb", "ihi", etc.) + * linesize_log2 log2(size of cache line in bytes) + * addr register containing start address of region (clobbered) + * asize register containing size of the region in bytes (clobbered) + * askew unique register used as temporary + * awb unique register used as temporary for erratum 497. + * + * Note: A possible optimization to this macro is to apply the operation + * to the entire cache if the region exceeds the size of the cache + * by some empirically determined amount or factor. Some experimentation + * is required to determine the appropriate factors, which also need + * to be tunable if required. + */ + + .macro cache_hit_region cainst, linesize_log2, addr, asize, askew, awb=a0 + + // Make \asize the number of iterations: + extui \askew, \addr, 0, \linesize_log2 // get unalignment amount of \addr + add \asize, \asize, \askew // ... and add it to \asize + addi \asize, \asize, (1 << \linesize_log2) - 1 // round up! + srli \asize, \asize, \linesize_log2 + + // Iterate over region: + .ifne ((\awb !=a0) & XCHAL_ERRATUM_497) // don't use awb if set to a0 + movi \awb, 0 + .endif + floopnez \asize, cacheh\@ + \cainst \addr, 0 + .ifne ((\awb !=a0) & XCHAL_ERRATUM_497) // do memw after 8 cainst wb instructions + addi \awb, \awb, 1 + blti \awb, 8, .Lstart_memw\@ + memw + movi \awb, 0 +.Lstart_memw\@: + .endif + addi \addr, \addr, (1 << \linesize_log2) // move to next line + floopend \asize, cacheh\@ + .endm + + + + + +/*************************** INSTRUCTION CACHE ***************************/ + + +/* + * Reset/initialize the instruction cache by simply invalidating it: + * (need to unlock first also, if cache locking implemented): + * + * Parameters: + * aa, ab unique address registers (temporaries) + */ + .macro icache_reset aa, ab, loopokay=0 + icache_unlock_all \aa, \ab, \loopokay + icache_invalidate_all \aa, \ab, \loopokay + .endm + + +/* + * Synchronize after an instruction cache operation, + * to be sure everything is in sync with memory as to be + * expected following any previous instruction cache control operations. + * + * Even if a config doesn't have caches, an isync is still needed + * when instructions in any memory are modified, whether by a loader + * or self-modifying code. Therefore, this macro always produces + * an isync, whether or not an icache is present. + * + * Parameters are: + * ar an address register (temporary) (currently unused, but may be used in future) + */ + .macro icache_sync ar + isync + .endm + + + +/* + * Invalidate a single line of the instruction cache. + * Parameters are: + * ar address register that contains (virtual) address to invalidate + * (may get clobbered in a future implementation, but not currently) + * offset (optional) offset to add to \ar to compute effective address to invalidate + * (note: some number of lsbits are ignored) + */ + .macro icache_invalidate_line ar, offset +#if XCHAL_ICACHE_SIZE > 0 + ihi \ar, \offset // invalidate icache line + icache_sync \ar +#endif + .endm + + + + +/* + * Invalidate instruction cache entries that cache a specified portion of memory. + * Parameters are: + * astart start address (register gets clobbered) + * asize size of the region in bytes (register gets clobbered) + * ac unique register used as temporary + */ + .macro icache_invalidate_region astart, asize, ac +#if XCHAL_ICACHE_SIZE > 0 + // Instruction cache region invalidation: + cache_hit_region ihi, XCHAL_ICACHE_LINEWIDTH, \astart, \asize, \ac + icache_sync \ac + // End of instruction cache region invalidation +#endif + .endm + + + +/* + * Invalidate entire instruction cache. + * + * Parameters: + * aa, ab unique address registers (temporaries) + */ + .macro icache_invalidate_all aa, ab, loopokay=1 +#if XCHAL_ICACHE_SIZE > 0 + // Instruction cache invalidation: + cache_index_all iii, XCHAL_ICACHE_SIZE, XCHAL_ICACHE_LINESIZE, XCHAL_ICACHE_WAYS, \aa, \ab, \loopokay, 1020 + icache_sync \aa + // End of instruction cache invalidation +#endif + .endm + + + +/* + * Lock (prefetch & lock) a single line of the instruction cache. + * + * Parameters are: + * ar address register that contains (virtual) address to lock + * (may get clobbered in a future implementation, but not currently) + * offset offset to add to \ar to compute effective address to lock + * (note: some number of lsbits are ignored) + */ + .macro icache_lock_line ar, offset +#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE + ipfl \ar, \offset /* prefetch and lock icache line */ + icache_sync \ar +#endif + .endm + + + +/* + * Lock (prefetch & lock) a specified portion of memory into the instruction cache. + * Parameters are: + * astart start address (register gets clobbered) + * asize size of the region in bytes (register gets clobbered) + * ac unique register used as temporary + */ + .macro icache_lock_region astart, asize, ac +#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE + // Instruction cache region lock: + cache_hit_region ipfl, XCHAL_ICACHE_LINEWIDTH, \astart, \asize, \ac + icache_sync \ac + // End of instruction cache region lock +#endif + .endm + + + +/* + * Unlock a single line of the instruction cache. + * + * Parameters are: + * ar address register that contains (virtual) address to unlock + * (may get clobbered in a future implementation, but not currently) + * offset offset to add to \ar to compute effective address to unlock + * (note: some number of lsbits are ignored) + */ + .macro icache_unlock_line ar, offset +#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE + ihu \ar, \offset /* unlock icache line */ + icache_sync \ar +#endif + .endm + + + +/* + * Unlock a specified portion of memory from the instruction cache. + * Parameters are: + * astart start address (register gets clobbered) + * asize size of the region in bytes (register gets clobbered) + * ac unique register used as temporary + */ + .macro icache_unlock_region astart, asize, ac +#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE + // Instruction cache region unlock: + cache_hit_region ihu, XCHAL_ICACHE_LINEWIDTH, \astart, \asize, \ac + icache_sync \ac + // End of instruction cache region unlock +#endif + .endm + + + +/* + * Unlock entire instruction cache. + * + * Parameters: + * aa, ab unique address registers (temporaries) + */ + .macro icache_unlock_all aa, ab, loopokay=1 +#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE + // Instruction cache unlock: + cache_index_all iiu, XCHAL_ICACHE_SIZE, XCHAL_ICACHE_LINESIZE, 1, \aa, \ab, \loopokay, 240 + icache_sync \aa + // End of instruction cache unlock +#endif + .endm + + + + + +/*************************** DATA CACHE ***************************/ + + + +/* + * Reset/initialize the data cache by simply invalidating it + * (need to unlock first also, if cache locking implemented): + * + * Parameters: + * aa, ab unique address registers (temporaries) + */ + .macro dcache_reset aa, ab, loopokay=0 + dcache_unlock_all \aa, \ab, \loopokay + dcache_invalidate_all \aa, \ab, \loopokay + .endm + + + + +/* + * Synchronize after a data cache operation, + * to be sure everything is in sync with memory as to be + * expected following any previous data cache control operations. + * + * Parameters are: + * ar an address register (temporary) (currently unused, but may be used in future) + */ + .macro dcache_sync ar, wbtype=0 +#if XCHAL_DCACHE_SIZE > 0 + // No synchronization is needed. + // (memw may be desired e.g. after writeback operation to help ensure subsequent + // external accesses are seen to follow that writeback, however that's outside + // the scope of this macro) + + //dsync + .ifne (\wbtype & XCHAL_ERRATUM_497) + memw + .endif +#endif + .endm + + + +/* + * Turn on cache coherence. + * + * WARNING: for RE-201x.x and later hardware, any interrupt that tries + * to change MEMCTL will see its changes dropped if the interrupt comes + * in the middle of this routine. If this might be an issue, call this + * routine with interrupts disabled. + * + * Parameters are: + * ar,at two scratch address registers (both clobbered) + */ + .macro cache_coherence_on ar at +#if XCHAL_DCACHE_IS_COHERENT +# if XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0 + /* Have MEMCTL. Enable snoop responses. */ + rsr.memctl \ar + movi \at, MEMCTL_SNOOP_EN + or \ar, \ar, \at + wsr.memctl \ar +# elif XCHAL_HAVE_EXTERN_REGS && XCHAL_HAVE_MX + /* Opt into coherence for MX (for backward compatibility / testing). */ + movi \ar, 1 + movi \at, XER_CCON + wer \ar, \at + extw +# endif +#endif + .endm + + + +/* + * Turn off cache coherence. + * + * NOTE: this is generally preceded by emptying the cache; + * see xthal_cache_coherence_optout() in hal/coherence.c for details. + * + * WARNING: for RE-201x.x and later hardware, any interrupt that tries + * to change MEMCTL will see its changes dropped if the interrupt comes + * in the middle of this routine. If this might be an issue, call this + * routine with interrupts disabled. + * + * Parameters are: + * ar,at two scratch address registers (both clobbered) + */ + .macro cache_coherence_off ar at +#if XCHAL_DCACHE_IS_COHERENT +# if XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0 + /* Have MEMCTL. Disable snoop responses. */ + rsr.memctl \ar + movi \at, ~MEMCTL_SNOOP_EN + and \ar, \ar, \at + wsr.memctl \ar +# elif XCHAL_HAVE_EXTERN_REGS && XCHAL_HAVE_MX + /* Opt out of coherence, for MX (for backward compatibility / testing). */ + extw + movi \at, 0 + movi \ar, XER_CCON + wer \at, \ar + extw +# endif +#endif + .endm + + + +/* + * Synchronize after a data store operation, + * to be sure the stored data is completely off the processor + * (and assuming there is no buffering outside the processor, + * that the data is in memory). This may be required to + * ensure that the processor's write buffers are emptied. + * A MEMW followed by a read guarantees this, by definition. + * We also try to make sure the read itself completes. + * + * Parameters are: + * ar an address register (temporary) + */ + .macro write_sync ar + memw // ensure previous memory accesses are complete prior to subsequent memory accesses + l32i \ar, sp, 0 // completing this read ensures any previous write has completed, because of MEMW + //slot + add \ar, \ar, \ar // use the result of the read to help ensure the read completes (in future architectures) + .endm + + +/* + * Invalidate a single line of the data cache. + * Parameters are: + * ar address register that contains (virtual) address to invalidate + * (may get clobbered in a future implementation, but not currently) + * offset (optional) offset to add to \ar to compute effective address to invalidate + * (note: some number of lsbits are ignored) + */ + .macro dcache_invalidate_line ar, offset +#if XCHAL_DCACHE_SIZE > 0 + dhi \ar, \offset + dcache_sync \ar +#endif + .endm + + + + + +/* + * Invalidate data cache entries that cache a specified portion of memory. + * Parameters are: + * astart start address (register gets clobbered) + * asize size of the region in bytes (register gets clobbered) + * ac unique register used as temporary + */ + .macro dcache_invalidate_region astart, asize, ac +#if XCHAL_DCACHE_SIZE > 0 + // Data cache region invalidation: + cache_hit_region dhi, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac + dcache_sync \ac + // End of data cache region invalidation +#endif + .endm + + + +/* + * Invalidate entire data cache. + * + * Parameters: + * aa, ab unique address registers (temporaries) + */ + .macro dcache_invalidate_all aa, ab, loopokay=1 +#if XCHAL_DCACHE_SIZE > 0 + // Data cache invalidation: + cache_index_all dii, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, XCHAL_DCACHE_WAYS, \aa, \ab, \loopokay, 1020 + dcache_sync \aa + // End of data cache invalidation +#endif + .endm + + + +/* + * Writeback a single line of the data cache. + * Parameters are: + * ar address register that contains (virtual) address to writeback + * (may get clobbered in a future implementation, but not currently) + * offset offset to add to \ar to compute effective address to writeback + * (note: some number of lsbits are ignored) + */ + .macro dcache_writeback_line ar, offset +#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK + dhwb \ar, \offset + dcache_sync \ar, wbtype=1 +#endif + .endm + + + +/* + * Writeback dirty data cache entries that cache a specified portion of memory. + * Parameters are: + * astart start address (register gets clobbered) + * asize size of the region in bytes (register gets clobbered) + * ac unique register used as temporary + */ + .macro dcache_writeback_region astart, asize, ac, awb +#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK + // Data cache region writeback: + cache_hit_region dhwb, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac, \awb + dcache_sync \ac, wbtype=1 + // End of data cache region writeback +#endif + .endm + + + +/* + * Writeback entire data cache. + * Parameters: + * aa, ab unique address registers (temporaries) + */ + .macro dcache_writeback_all aa, ab, awb, loopokay=1 +#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK + // Data cache writeback: + cache_index_all diwb, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab, \loopokay, 240, \awb, + dcache_sync \aa, wbtype=1 + // End of data cache writeback +#endif + .endm + + + +/* + * Writeback and invalidate a single line of the data cache. + * Parameters are: + * ar address register that contains (virtual) address to writeback and invalidate + * (may get clobbered in a future implementation, but not currently) + * offset offset to add to \ar to compute effective address to writeback and invalidate + * (note: some number of lsbits are ignored) + */ + .macro dcache_writeback_inv_line ar, offset +#if XCHAL_DCACHE_SIZE > 0 + dhwbi \ar, \offset /* writeback and invalidate dcache line */ + dcache_sync \ar, wbtype=1 +#endif + .endm + + + +/* + * Writeback and invalidate data cache entries that cache a specified portion of memory. + * Parameters are: + * astart start address (register gets clobbered) + * asize size of the region in bytes (register gets clobbered) + * ac unique register used as temporary + */ + .macro dcache_writeback_inv_region astart, asize, ac, awb +#if XCHAL_DCACHE_SIZE > 0 + // Data cache region writeback and invalidate: + cache_hit_region dhwbi, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac, \awb + dcache_sync \ac, wbtype=1 + // End of data cache region writeback and invalidate +#endif + .endm + + + +/* + * Writeback and invalidate entire data cache. + * Parameters: + * aa, ab unique address registers (temporaries) + */ + .macro dcache_writeback_inv_all aa, ab, awb, loopokay=1 +#if XCHAL_DCACHE_SIZE > 0 + // Data cache writeback and invalidate: +#if XCHAL_DCACHE_IS_WRITEBACK + cache_index_all diwbi, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab, \loopokay, 240, \awb + dcache_sync \aa, wbtype=1 +#else /*writeback*/ + // Data cache does not support writeback, so just invalidate: */ + dcache_invalidate_all \aa, \ab, \loopokay +#endif /*writeback*/ + // End of data cache writeback and invalidate +#endif + .endm + + + + +/* + * Lock (prefetch & lock) a single line of the data cache. + * + * Parameters are: + * ar address register that contains (virtual) address to lock + * (may get clobbered in a future implementation, but not currently) + * offset offset to add to \ar to compute effective address to lock + * (note: some number of lsbits are ignored) + */ + .macro dcache_lock_line ar, offset +#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE + dpfl \ar, \offset /* prefetch and lock dcache line */ + dcache_sync \ar +#endif + .endm + + + +/* + * Lock (prefetch & lock) a specified portion of memory into the data cache. + * Parameters are: + * astart start address (register gets clobbered) + * asize size of the region in bytes (register gets clobbered) + * ac unique register used as temporary + */ + .macro dcache_lock_region astart, asize, ac +#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE + // Data cache region lock: + cache_hit_region dpfl, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac + dcache_sync \ac + // End of data cache region lock +#endif + .endm + + + +/* + * Unlock a single line of the data cache. + * + * Parameters are: + * ar address register that contains (virtual) address to unlock + * (may get clobbered in a future implementation, but not currently) + * offset offset to add to \ar to compute effective address to unlock + * (note: some number of lsbits are ignored) + */ + .macro dcache_unlock_line ar, offset +#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE + dhu \ar, \offset /* unlock dcache line */ + dcache_sync \ar +#endif + .endm + + + +/* + * Unlock a specified portion of memory from the data cache. + * Parameters are: + * astart start address (register gets clobbered) + * asize size of the region in bytes (register gets clobbered) + * ac unique register used as temporary + */ + .macro dcache_unlock_region astart, asize, ac +#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE + // Data cache region unlock: + cache_hit_region dhu, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac + dcache_sync \ac + // End of data cache region unlock +#endif + .endm + + + +/* + * Unlock entire data cache. + * + * Parameters: + * aa, ab unique address registers (temporaries) + */ + .macro dcache_unlock_all aa, ab, loopokay=1 +#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE + // Data cache unlock: + cache_index_all diu, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab, \loopokay, 240 + dcache_sync \aa + // End of data cache unlock +#endif + .endm + + + +/* + * Get the number of enabled icache ways. Note that this may + * be different from the value read from the MEMCTL register. + * + * Parameters: + * aa address register where value is returned + */ + .macro icache_get_ways aa +#if XCHAL_ICACHE_SIZE > 0 +#if XCHAL_HAVE_ICACHE_DYN_WAYS + // Read from MEMCTL and shift/mask + rsr \aa, MEMCTL + extui \aa, \aa, MEMCTL_ICWU_SHIFT, MEMCTL_ICWU_BITS + blti \aa, XCHAL_ICACHE_WAYS, .Licgw + movi \aa, XCHAL_ICACHE_WAYS +.Licgw: +#else + // All ways are always enabled + movi \aa, XCHAL_ICACHE_WAYS +#endif +#else + // No icache + movi \aa, 0 +#endif + .endm + + + +/* + * Set the number of enabled icache ways. + * + * Parameters: + * aa address register specifying number of ways (trashed) + * ab,ac address register for scratch use (trashed) + */ + .macro icache_set_ways aa, ab, ac +#if XCHAL_ICACHE_SIZE > 0 +#if XCHAL_HAVE_ICACHE_DYN_WAYS + movi \ac, MEMCTL_ICWU_CLR_MASK // set up to clear bits 18-22 + rsr \ab, MEMCTL + and \ab, \ab, \ac + movi \ac, MEMCTL_INV_EN // set bit 23 + slli \aa, \aa, MEMCTL_ICWU_SHIFT // move to right spot + or \ab, \ab, \aa + or \ab, \ab, \ac + wsr \ab, MEMCTL + isync +#else + // All ways are always enabled +#endif +#else + // No icache +#endif + .endm + + + +/* + * Get the number of enabled dcache ways. Note that this may + * be different from the value read from the MEMCTL register. + * + * Parameters: + * aa address register where value is returned + */ + .macro dcache_get_ways aa +#if XCHAL_DCACHE_SIZE > 0 +#if XCHAL_HAVE_DCACHE_DYN_WAYS + // Read from MEMCTL and shift/mask + rsr \aa, MEMCTL + extui \aa, \aa, MEMCTL_DCWU_SHIFT, MEMCTL_DCWU_BITS + blti \aa, XCHAL_DCACHE_WAYS, .Ldcgw + movi \aa, XCHAL_DCACHE_WAYS +.Ldcgw: +#else + // All ways are always enabled + movi \aa, XCHAL_DCACHE_WAYS +#endif +#else + // No dcache + movi \aa, 0 +#endif + .endm + + + +/* + * Set the number of enabled dcache ways. + * + * Parameters: + * aa address register specifying number of ways (trashed) + * ab,ac address register for scratch use (trashed) + */ + .macro dcache_set_ways aa, ab, ac +#if (XCHAL_DCACHE_SIZE > 0) && XCHAL_HAVE_DCACHE_DYN_WAYS + movi \ac, MEMCTL_DCWA_CLR_MASK // set up to clear bits 13-17 + rsr \ab, MEMCTL + and \ab, \ab, \ac // clear ways allocatable + slli \ac, \aa, MEMCTL_DCWA_SHIFT + or \ab, \ab, \ac // set ways allocatable + wsr \ab, MEMCTL +#if XCHAL_DCACHE_IS_WRITEBACK + // Check if the way count is increasing or decreasing + extui \ac, \ab, MEMCTL_DCWU_SHIFT, MEMCTL_DCWU_BITS // bits 8-12 - ways in use + bge \aa, \ac, .Ldsw3 // equal or increasing + slli \ab, \aa, XCHAL_DCACHE_LINEWIDTH + XCHAL_DCACHE_SETWIDTH // start way number + slli \ac, \ac, XCHAL_DCACHE_LINEWIDTH + XCHAL_DCACHE_SETWIDTH // end way number +.Ldsw1: + diwbui.p \ab // auto-increments ab + bge \ab, \ac, .Ldsw2 + beqz \ab, .Ldsw2 + j .Ldsw1 +.Ldsw2: + rsr \ab, MEMCTL +#endif +.Ldsw3: + // No dirty data to write back, just set the new number of ways + movi \ac, MEMCTL_DCWU_CLR_MASK // set up to clear bits 8-12 + and \ab, \ab, \ac // clear ways in use + movi \ac, MEMCTL_INV_EN + or \ab, \ab, \ac // set bit 23 + slli \aa, \aa, MEMCTL_DCWU_SHIFT + or \ab, \ab, \aa // set ways in use + wsr \ab, MEMCTL +#else + // No dcache or no way disable support +#endif + .endm + +#endif /*XTENSA_CACHEASM_H*/ + diff --git a/tools/sdk/include/esp32/xtensa/cacheattrasm.h b/tools/sdk/include/esp32/xtensa/cacheattrasm.h new file mode 100755 index 00000000..20c4cfd5 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/cacheattrasm.h @@ -0,0 +1,436 @@ +/* + * xtensa/cacheattrasm.h -- assembler-specific CACHEATTR register related definitions + * that depend on CORE configuration + * + * This file is logically part of xtensa/coreasm.h (or perhaps xtensa/cacheasm.h), + * but is kept separate for modularity / compilation-performance. + */ + +/* + * Copyright (c) 2001-2009 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef XTENSA_CACHEATTRASM_H +#define XTENSA_CACHEATTRASM_H + +#include + +/* Determine whether cache attributes are controlled using eight 512MB entries: */ +#define XCHAL_CA_8X512 (XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR \ + || (XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY)) + + +/* + * This header file defines assembler macros of the form: + * cacheattr_ + * where: + * is 'i', 'd' or absent for instruction, data + * or both caches; and + * indicates the function of the macro. + * + * The following functions are defined: + * + * icacheattr_get + * Reads I-cache CACHEATTR into a2 (clobbers a3-a5). + * + * dcacheattr_get + * Reads D-cache CACHEATTR into a2 (clobbers a3-a5). + * (Note: for configs with a real CACHEATTR register, the + * above two macros are identical.) + * + * cacheattr_set + * Writes both I-cache and D-cache CACHEATTRs from a2 (a3-a8 clobbered). + * Works even when changing one's own code's attributes. + * + * icacheattr_is_enabled label + * Branches to \label if I-cache appears to have been enabled + * (eg. if CACHEATTR contains a cache-enabled attribute). + * (clobbers a2-a5,SAR) + * + * dcacheattr_is_enabled label + * Branches to \label if D-cache appears to have been enabled + * (eg. if CACHEATTR contains a cache-enabled attribute). + * (clobbers a2-a5,SAR) + * + * cacheattr_is_enabled label + * Branches to \label if either I-cache or D-cache appears to have been enabled + * (eg. if CACHEATTR contains a cache-enabled attribute). + * (clobbers a2-a5,SAR) + * + * The following macros are only defined under certain conditions: + * + * icacheattr_set (if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR) + * Writes I-cache CACHEATTR from a2 (a3-a8 clobbered). + * + * dcacheattr_set (if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR) + * Writes D-cache CACHEATTR from a2 (a3-a8 clobbered). + */ + + + +/*************************** GENERIC -- ALL CACHES ***************************/ + +/* + * _cacheattr_get + * + * (Internal macro.) + * Returns value of CACHEATTR register (or closest equivalent) in a2. + * + * Entry: + * (none) + * Exit: + * a2 value read from CACHEATTR + * a3-a5 clobbered (temporaries) + */ + .macro _cacheattr_get tlb +#if XCHAL_HAVE_CACHEATTR + rsr a2, CACHEATTR +#elif XCHAL_CA_8X512 + // We have a config that "mimics" CACHEATTR using a simplified + // "MMU" composed of a single statically-mapped way. + // DTLB and ITLB are independent, so there's no single + // cache attribute that can describe both. So for now + // just return the DTLB state. + movi a5, 0xE0000000 + movi a2, 0 + movi a3, XCHAL_SPANNING_WAY +1: add a3, a3, a5 // next segment + r&tlb&1 a4, a3 // get PPN+CA of segment at 0xE0000000, 0xC0000000, ..., 0 + dsync // interlock??? + slli a2, a2, 4 + extui a4, a4, 0, 4 // extract CA + or a2, a2, a4 + bgeui a3, 16, 1b +#else + // This macro isn't applicable to arbitrary MMU configurations. + // Just return zero. + movi a2, 0 +#endif + .endm + + .macro icacheattr_get + _cacheattr_get itlb + .endm + + .macro dcacheattr_get + _cacheattr_get dtlb + .endm + + +/* Default (powerup/reset) value of CACHEATTR, + all BYPASS mode (ie. disabled/bypassed caches): */ +#if XCHAL_HAVE_PTP_MMU +# define XCHAL_CACHEATTR_ALL_BYPASS 0x33333333 +#else +# define XCHAL_CACHEATTR_ALL_BYPASS 0x22222222 +#endif + +#if XCHAL_CA_8X512 + +#if XCHAL_HAVE_PTP_MMU +# define XCHAL_FCA_ENAMASK 0x0AA0 /* bitmap of fetch attributes that require enabled icache */ +# define XCHAL_LCA_ENAMASK 0x0FF0 /* bitmap of load attributes that require enabled dcache */ +# define XCHAL_SCA_ENAMASK 0x0CC0 /* bitmap of store attributes that require enabled dcache */ +#else +# define XCHAL_FCA_ENAMASK 0x003A /* bitmap of fetch attributes that require enabled icache */ +# define XCHAL_LCA_ENAMASK 0x0033 /* bitmap of load attributes that require enabled dcache */ +# define XCHAL_SCA_ENAMASK 0x0033 /* bitmap of store attributes that require enabled dcache */ +#endif +#define XCHAL_LSCA_ENAMASK (XCHAL_LCA_ENAMASK|XCHAL_SCA_ENAMASK) /* l/s attrs requiring enabled dcache */ +#define XCHAL_ALLCA_ENAMASK (XCHAL_FCA_ENAMASK|XCHAL_LSCA_ENAMASK) /* all attrs requiring enabled caches */ + +/* + * _cacheattr_is_enabled + * + * (Internal macro.) + * Branches to \label if CACHEATTR in a2 indicates an enabled + * cache, using mask in a3. + * + * Parameters: + * label where to branch to if cache is enabled + * Entry: + * a2 contains CACHEATTR value used to determine whether + * caches are enabled + * a3 16-bit constant where each bit correspond to + * one of the 16 possible CA values (in a CACHEATTR mask); + * CA values that indicate the cache is enabled + * have their corresponding bit set in this mask + * (eg. use XCHAL_xCA_ENAMASK , above) + * Exit: + * a2,a4,a5 clobbered + * SAR clobbered + */ + .macro _cacheattr_is_enabled label + movi a4, 8 // loop 8 times +.Lcaife\@: + extui a5, a2, 0, 4 // get CA nibble + ssr a5 // index into mask according to CA... + srl a5, a3 // ...and get CA's mask bit in a5 bit 0 + bbsi.l a5, 0, \label // if CA indicates cache enabled, jump to label + srli a2, a2, 4 // next nibble + addi a4, a4, -1 + bnez a4, .Lcaife\@ // loop for each nibble + .endm + +#else /* XCHAL_CA_8X512 */ + .macro _cacheattr_is_enabled label + j \label // macro not applicable, assume caches always enabled + .endm +#endif /* XCHAL_CA_8X512 */ + + + +/* + * icacheattr_is_enabled + * + * Branches to \label if I-cache is enabled. + * + * Parameters: + * label where to branch to if icache is enabled + * Entry: + * (none) + * Exit: + * a2-a5, SAR clobbered (temporaries) + */ + .macro icacheattr_is_enabled label +#if XCHAL_CA_8X512 + icacheattr_get + movi a3, XCHAL_FCA_ENAMASK +#endif + _cacheattr_is_enabled \label + .endm + +/* + * dcacheattr_is_enabled + * + * Branches to \label if D-cache is enabled. + * + * Parameters: + * label where to branch to if dcache is enabled + * Entry: + * (none) + * Exit: + * a2-a5, SAR clobbered (temporaries) + */ + .macro dcacheattr_is_enabled label +#if XCHAL_CA_8X512 + dcacheattr_get + movi a3, XCHAL_LSCA_ENAMASK +#endif + _cacheattr_is_enabled \label + .endm + +/* + * cacheattr_is_enabled + * + * Branches to \label if either I-cache or D-cache is enabled. + * + * Parameters: + * label where to branch to if a cache is enabled + * Entry: + * (none) + * Exit: + * a2-a5, SAR clobbered (temporaries) + */ + .macro cacheattr_is_enabled label +#if XCHAL_HAVE_CACHEATTR + rsr a2, CACHEATTR + movi a3, XCHAL_ALLCA_ENAMASK +#elif XCHAL_CA_8X512 + icacheattr_get + movi a3, XCHAL_FCA_ENAMASK + _cacheattr_is_enabled \label + dcacheattr_get + movi a3, XCHAL_LSCA_ENAMASK +#endif + _cacheattr_is_enabled \label + .endm + + + +/* + * The ISA does not have a defined way to change the + * instruction cache attributes of the running code, + * ie. of the memory area that encloses the current PC. + * However, each micro-architecture (or class of + * configurations within a micro-architecture) + * provides a way to deal with this issue. + * + * Here are a few macros used to implement the relevant + * approach taken. + */ + +#if XCHAL_CA_8X512 && !XCHAL_HAVE_CACHEATTR + // We have a config that "mimics" CACHEATTR using a simplified + // "MMU" composed of a single statically-mapped way. + +/* + * icacheattr_set + * + * Entry: + * a2 cacheattr value to set + * Exit: + * a2 unchanged + * a3-a8 clobbered (temporaries) + */ + .macro icacheattr_set + + movi a5, 0xE0000000 // mask of upper 3 bits + movi a6, 3f // PC where ITLB is set + movi a3, XCHAL_SPANNING_WAY // start at region 0 (0 .. 7) + mov a7, a2 // copy a2 so it doesn't get clobbered + and a6, a6, a5 // upper 3 bits of local PC area + j 3f + + // Use micro-architecture specific method. + // The following 4-instruction sequence is aligned such that + // it all fits within a single I-cache line. Sixteen byte + // alignment is sufficient for this (using XCHAL_ICACHE_LINESIZE + // actually causes problems because that can be greater than + // the alignment of the reset vector, where this macro is often + // invoked, which would cause the linker to align the reset + // vector code away from the reset vector!!). + .begin no-transform + .align 16 /*XCHAL_ICACHE_LINESIZE*/ +1: witlb a4, a3 // write wired PTE (CA, no PPN) of 512MB segment to ITLB + isync + .end no-transform + nop + nop + + sub a3, a3, a5 // next segment (add 0x20000000) + bltui a3, 16, 4f // done? + + // Note that in the WITLB loop, we don't do any load/stores + // (may not be an issue here, but it is important in the DTLB case). +2: srli a7, a7, 4 // next CA +3: +# if XCHAL_HAVE_MIMIC_CACHEATTR + extui a4, a7, 0, 4 // extract CA to set +# else /* have translation, preserve it: */ + ritlb1 a8, a3 // get current PPN+CA of segment + //dsync // interlock??? + extui a4, a7, 0, 4 // extract CA to set + srli a8, a8, 4 // clear CA but keep PPN ... + slli a8, a8, 4 // ... + add a4, a4, a8 // combine new CA with PPN to preserve +# endif + beq a3, a6, 1b // current PC's region? if so, do it in a safe way + witlb a4, a3 // write wired PTE (CA [+PPN]) of 512MB segment to ITLB + sub a3, a3, a5 // next segment (add 0x20000000) + bgeui a3, 16, 2b + isync // make sure all ifetch changes take effect +4: + .endm // icacheattr_set + + +/* + * dcacheattr_set + * + * Entry: + * a2 cacheattr value to set + * Exit: + * a2 unchanged + * a3-a8 clobbered (temporaries) + */ + + .macro dcacheattr_set + + movi a5, 0xE0000000 // mask of upper 3 bits + movi a3, XCHAL_SPANNING_WAY // start at region 0 (0 .. 7) + mov a7, a2 // copy a2 so it doesn't get clobbered + // Note that in the WDTLB loop, we don't do any load/stores +2: // (including implicit l32r via movi) because it isn't safe. +# if XCHAL_HAVE_MIMIC_CACHEATTR + extui a4, a7, 0, 4 // extract CA to set +# else /* have translation, preserve it: */ + rdtlb1 a8, a3 // get current PPN+CA of segment + //dsync // interlock??? + extui a4, a7, 0, 4 // extract CA to set + srli a8, a8, 4 // clear CA but keep PPN ... + slli a8, a8, 4 // ... + add a4, a4, a8 // combine new CA with PPN to preserve +# endif + wdtlb a4, a3 // write wired PTE (CA [+PPN]) of 512MB segment to DTLB + sub a3, a3, a5 // next segment (add 0x20000000) + srli a7, a7, 4 // next CA + bgeui a3, 16, 2b + dsync // make sure all data path changes take effect + .endm // dcacheattr_set + +#endif /* XCHAL_CA_8X512 && !XCHAL_HAVE_CACHEATTR */ + + + +/* + * cacheattr_set + * + * Macro that sets the current CACHEATTR safely + * (both i and d) according to the current contents of a2. + * It works even when changing the cache attributes of + * the currently running code. + * + * Entry: + * a2 cacheattr value to set + * Exit: + * a2 unchanged + * a3-a8 clobbered (temporaries) + */ + .macro cacheattr_set + +#if XCHAL_HAVE_CACHEATTR +# if XCHAL_ICACHE_LINESIZE < 4 + // No i-cache, so can always safely write to CACHEATTR: + wsr a2, CACHEATTR +# else + // The Athens micro-architecture, when using the old + // exception architecture option (ie. with the CACHEATTR register) + // allows changing the cache attributes of the running code + // using the following exact sequence aligned to be within + // an instruction cache line. (NOTE: using XCHAL_ICACHE_LINESIZE + // alignment actually causes problems because that can be greater + // than the alignment of the reset vector, where this macro is often + // invoked, which would cause the linker to align the reset + // vector code away from the reset vector!!). + j 1f + .begin no-transform + .align 16 /*XCHAL_ICACHE_LINESIZE*/ // align to within an I-cache line +1: wsr a2, CACHEATTR + isync + .end no-transform + nop + nop +# endif +#elif XCHAL_CA_8X512 + // DTLB and ITLB are independent, but to keep semantics + // of this macro we simply write to both. + icacheattr_set + dcacheattr_set +#else + // This macro isn't applicable to arbitrary MMU configurations. + // Do nothing in this case. +#endif + .endm + + +#endif /*XTENSA_CACHEATTRASM_H*/ + diff --git a/tools/sdk/include/esp32/xtensa/config/core-isa.h b/tools/sdk/include/esp32/xtensa/config/core-isa.h new file mode 100644 index 00000000..18456472 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/config/core-isa.h @@ -0,0 +1,655 @@ +/* + * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa + * processor CORE configuration + * + * See , which includes this file, for more details. + */ + +/* Xtensa processor core configuration information. + + Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef _XTENSA_CORE_CONFIGURATION_H +#define _XTENSA_CORE_CONFIGURATION_H + + +/**************************************************************************** + Parameters Useful for Any Code, USER or PRIVILEGED + ****************************************************************************/ + +/* + * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is + * configured, and a value of 0 otherwise. These macros are always defined. + */ + + +/*---------------------------------------------------------------------- + ISA + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ +#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ +#define XCHAL_NUM_AREGS 64 /* num of physical addr regs */ +#define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */ +#define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */ +#define XCHAL_HAVE_DEBUG 1 /* debug option */ +#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ +#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ +#define XCHAL_LOOP_BUFFER_SIZE 256 /* zero-ov. loop instr buffer size */ +#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ +#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ +#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ +#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */ +#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ +#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ +#define XCHAL_HAVE_MUL32 1 /* MULL instruction */ +#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */ +#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */ +#define XCHAL_HAVE_L32R 1 /* L32R instruction */ +#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ +#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ +#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ +#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ +#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ +#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ +#define XCHAL_HAVE_ABS 1 /* ABS instruction */ +/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */ +/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */ +#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ +#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ +#define XCHAL_HAVE_SPECULATION 0 /* speculation */ +#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ +#define XCHAL_NUM_CONTEXTS 1 /* */ +#define XCHAL_NUM_MISC_REGS 4 /* num of scratch regs (0..4) */ +#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ +#define XCHAL_HAVE_PRID 1 /* processor ID register */ +#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ +#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */ +#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ +#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ +#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */ +#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */ +#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */ +#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ +#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */ +#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ +#define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */ +#define XCHAL_HAVE_MAC16 1 /* MAC16 package */ + +#define XCHAL_HAVE_FUSION 0 /* Fusion*/ +#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */ +#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */ +#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */ +#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */ +#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */ +#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */ +#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */ +#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */ +#define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */ +#define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */ +#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ +#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ +#define XCHAL_HAVE_HIFI_MINI 0 + + +#define XCHAL_HAVE_VECTORFPU2005 0 /* vector or user floating-point pkg */ +#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */ +#define XCHAL_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */ +#define XCHAL_HAVE_FP 1 /* single prec floating point */ +#define XCHAL_HAVE_FP_DIV 1 /* FP with DIV instructions */ +#define XCHAL_HAVE_FP_RECIP 1 /* FP with RECIP instructions */ +#define XCHAL_HAVE_FP_SQRT 1 /* FP with SQRT instructions */ +#define XCHAL_HAVE_FP_RSQRT 1 /* FP with RSQRT instructions */ +#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ +#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */ +#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/ +#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */ +#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/ +#define XCHAL_HAVE_DFP_ACCEL 1 /* double precision FP acceleration pkg */ +#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */ + +#define XCHAL_HAVE_DFPU_SINGLE_ONLY 1 /* DFPU Coprocessor, single precision only */ +#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */ +#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ +#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ +#define XCHAL_HAVE_PDX4 0 /* PDX4 */ +#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ +#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */ +#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ +#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ +#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ +#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ +#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */ +#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ +#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */ +#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ +#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ +#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ +#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ +#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */ +#define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */ +#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ + + +/*---------------------------------------------------------------------- + MISC + ----------------------------------------------------------------------*/ + +#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */ +#define XCHAL_NUM_WRITEBUFFER_ENTRIES 4 /* size of write buffer */ +#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */ +#define XCHAL_DATA_WIDTH 4 /* data width in bytes */ +#define XCHAL_DATA_PIPE_DELAY 2 /* d-side pipeline delay + (1 = 5-stage, 2 = 7-stage) */ +#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */ +#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */ +/* In T1050, applies to selected core load and store instructions (see ISA): */ +#define XCHAL_UNALIGNED_LOAD_EXCEPTION 0 /* unaligned loads cause exc. */ +#define XCHAL_UNALIGNED_STORE_EXCEPTION 0 /* unaligned stores cause exc.*/ +#define XCHAL_UNALIGNED_LOAD_HW 1 /* unaligned loads work in hw */ +#define XCHAL_UNALIGNED_STORE_HW 1 /* unaligned stores work in hw*/ + +#define XCHAL_SW_VERSION 1100003 /* sw version of this header */ + +#define XCHAL_CORE_ID "esp32_v3_49_prod" /* alphanum core name + (CoreID) set in the Xtensa + Processor Generator */ + +#define XCHAL_BUILD_UNIQUE_ID 0x0005FE96 /* 22-bit sw build ID */ + +/* + * These definitions describe the hardware targeted by this software. + */ +#define XCHAL_HW_CONFIGID0 0xC2BCFFFE /* ConfigID hi 32 bits*/ +#define XCHAL_HW_CONFIGID1 0x1CC5FE96 /* ConfigID lo 32 bits*/ +#define XCHAL_HW_VERSION_NAME "LX6.0.3" /* full version name */ +#define XCHAL_HW_VERSION_MAJOR 2600 /* major ver# of targeted hw */ +#define XCHAL_HW_VERSION_MINOR 3 /* minor ver# of targeted hw */ +#define XCHAL_HW_VERSION 260003 /* major*100+minor */ +#define XCHAL_HW_REL_LX6 1 +#define XCHAL_HW_REL_LX6_0 1 +#define XCHAL_HW_REL_LX6_0_3 1 +#define XCHAL_HW_CONFIGID_RELIABLE 1 +/* If software targets a *range* of hardware versions, these are the bounds: */ +#define XCHAL_HW_MIN_VERSION_MAJOR 2600 /* major v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION_MINOR 3 /* minor v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION 260003 /* earliest targeted hw */ +#define XCHAL_HW_MAX_VERSION_MAJOR 2600 /* major v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION_MINOR 3 /* minor v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION 260003 /* latest targeted hw */ + + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_ICACHE_LINESIZE 4 /* I-cache line size in bytes */ +#define XCHAL_DCACHE_LINESIZE 4 /* D-cache line size in bytes */ +#define XCHAL_ICACHE_LINEWIDTH 2 /* log2(I line size in bytes) */ +#define XCHAL_DCACHE_LINEWIDTH 2 /* log2(D line size in bytes) */ + +#define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */ +#define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */ + +#define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */ +#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ + +#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */ +#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */ +#define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */ +#define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */ +#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */ +#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */ +#define XCHAL_HAVE_ICACHE_TEST 0 /* Icache test instructions */ +#define XCHAL_HAVE_DCACHE_TEST 0 /* Dcache test instructions */ +#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */ +#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */ + + + + +/**************************************************************************** + Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code + ****************************************************************************/ + + +#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */ +#define XCHAL_HAVE_AXI 0 /* AXI bus */ + +#define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */ +#define XCHAL_HAVE_PIF_REQ_ATTR 0 /* pif attribute */ + +/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ + +/* Number of cache sets in log2(lines per way): */ +#define XCHAL_ICACHE_SETWIDTH 0 +#define XCHAL_DCACHE_SETWIDTH 0 + +/* Cache set associativity (number of ways): */ +#define XCHAL_ICACHE_WAYS 1 +#define XCHAL_DCACHE_WAYS 1 + +/* Cache features: */ +#define XCHAL_ICACHE_LINE_LOCKABLE 0 +#define XCHAL_DCACHE_LINE_LOCKABLE 0 +#define XCHAL_ICACHE_ECC_PARITY 0 +#define XCHAL_DCACHE_ECC_PARITY 0 + +/* Cache access size in bytes (affects operation of SICW instruction): */ +#define XCHAL_ICACHE_ACCESS_SIZE 1 +#define XCHAL_DCACHE_ACCESS_SIZE 1 + +#define XCHAL_DCACHE_BANKS 0 /* number of banks */ + +/* Number of encoded cache attr bits (see for decoded bits): */ +#define XCHAL_CA_BITS 4 + + +/*---------------------------------------------------------------------- + INTERNAL I/D RAM/ROMs and XLMI + ----------------------------------------------------------------------*/ + +#define XCHAL_NUM_INSTROM 1 /* number of core instr. ROMs */ +#define XCHAL_NUM_INSTRAM 2 /* number of core instr. RAMs */ +#define XCHAL_NUM_DATAROM 1 /* number of core data ROMs */ +#define XCHAL_NUM_DATARAM 2 /* number of core data RAMs */ +#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ +#define XCHAL_NUM_XLMI 1 /* number of core XLMI ports */ + +/* Instruction ROM 0: */ +#define XCHAL_INSTROM0_VADDR 0x40800000 /* virtual address */ +#define XCHAL_INSTROM0_PADDR 0x40800000 /* physical address */ +#define XCHAL_INSTROM0_SIZE 4194304 /* size in bytes */ +#define XCHAL_INSTROM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ + +/* Instruction RAM 0: */ +#define XCHAL_INSTRAM0_VADDR 0x40000000 /* virtual address */ +#define XCHAL_INSTRAM0_PADDR 0x40000000 /* physical address */ +#define XCHAL_INSTRAM0_SIZE 4194304 /* size in bytes */ +#define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ + +/* Instruction RAM 1: */ +#define XCHAL_INSTRAM1_VADDR 0x40400000 /* virtual address */ +#define XCHAL_INSTRAM1_PADDR 0x40400000 /* physical address */ +#define XCHAL_INSTRAM1_SIZE 4194304 /* size in bytes */ +#define XCHAL_INSTRAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */ + +/* Data ROM 0: */ +#define XCHAL_DATAROM0_VADDR 0x3F400000 /* virtual address */ +#define XCHAL_DATAROM0_PADDR 0x3F400000 /* physical address */ +#define XCHAL_DATAROM0_SIZE 4194304 /* size in bytes */ +#define XCHAL_DATAROM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_DATAROM0_BANKS 1 /* number of banks */ + +/* Data RAM 0: */ +#define XCHAL_DATARAM0_VADDR 0x3FF80000 /* virtual address */ +#define XCHAL_DATARAM0_PADDR 0x3FF80000 /* physical address */ +#define XCHAL_DATARAM0_SIZE 524288 /* size in bytes */ +#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_DATARAM0_BANKS 1 /* number of banks */ + +/* Data RAM 1: */ +#define XCHAL_DATARAM1_VADDR 0x3F800000 /* virtual address */ +#define XCHAL_DATARAM1_PADDR 0x3F800000 /* physical address */ +#define XCHAL_DATARAM1_SIZE 4194304 /* size in bytes */ +#define XCHAL_DATARAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_DATARAM1_BANKS 1 /* number of banks */ + +/* XLMI Port 0: */ +#define XCHAL_XLMI0_VADDR 0x3FF00000 /* virtual address */ +#define XCHAL_XLMI0_PADDR 0x3FF00000 /* physical address */ +#define XCHAL_XLMI0_SIZE 524288 /* size in bytes */ +#define XCHAL_XLMI0_ECC_PARITY 0 /* ECC/parity type, 0=none */ + +#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ + + +/*---------------------------------------------------------------------- + INTERRUPTS and TIMERS + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ +#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ +#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ +#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ +#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ +#define XCHAL_NUM_INTERRUPTS 32 /* number of interrupts */ +#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ +#define XCHAL_NUM_EXTINTERRUPTS 26 /* num of external interrupts */ +#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels + (not including level zero) */ +#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */ + /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ + +/* Masks of interrupts at each interrupt level: */ +#define XCHAL_INTLEVEL1_MASK 0x000637FF +#define XCHAL_INTLEVEL2_MASK 0x00380000 +#define XCHAL_INTLEVEL3_MASK 0x28C08800 +#define XCHAL_INTLEVEL4_MASK 0x53000000 +#define XCHAL_INTLEVEL5_MASK 0x84010000 +#define XCHAL_INTLEVEL6_MASK 0x00000000 +#define XCHAL_INTLEVEL7_MASK 0x00004000 + +/* Masks of interrupts at each range 1..n of interrupt levels: */ +#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x000637FF +#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x003E37FF +#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x28FEBFFF +#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x7BFEBFFF +#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0xFFFFBFFF +#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0xFFFFBFFF +#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0xFFFFFFFF + +/* Level of each interrupt: */ +#define XCHAL_INT0_LEVEL 1 +#define XCHAL_INT1_LEVEL 1 +#define XCHAL_INT2_LEVEL 1 +#define XCHAL_INT3_LEVEL 1 +#define XCHAL_INT4_LEVEL 1 +#define XCHAL_INT5_LEVEL 1 +#define XCHAL_INT6_LEVEL 1 +#define XCHAL_INT7_LEVEL 1 +#define XCHAL_INT8_LEVEL 1 +#define XCHAL_INT9_LEVEL 1 +#define XCHAL_INT10_LEVEL 1 +#define XCHAL_INT11_LEVEL 3 +#define XCHAL_INT12_LEVEL 1 +#define XCHAL_INT13_LEVEL 1 +#define XCHAL_INT14_LEVEL 7 +#define XCHAL_INT15_LEVEL 3 +#define XCHAL_INT16_LEVEL 5 +#define XCHAL_INT17_LEVEL 1 +#define XCHAL_INT18_LEVEL 1 +#define XCHAL_INT19_LEVEL 2 +#define XCHAL_INT20_LEVEL 2 +#define XCHAL_INT21_LEVEL 2 +#define XCHAL_INT22_LEVEL 3 +#define XCHAL_INT23_LEVEL 3 +#define XCHAL_INT24_LEVEL 4 +#define XCHAL_INT25_LEVEL 4 +#define XCHAL_INT26_LEVEL 5 +#define XCHAL_INT27_LEVEL 3 +#define XCHAL_INT28_LEVEL 4 +#define XCHAL_INT29_LEVEL 3 +#define XCHAL_INT30_LEVEL 4 +#define XCHAL_INT31_LEVEL 5 +#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ +#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ +#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with + EXCSAVE/EPS/EPC_n, RFI n) */ + +/* Type of each interrupt: */ +#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT11_TYPE XTHAL_INTTYPE_PROFILING +#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI +#define XCHAL_INT15_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT16_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT22_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT23_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT24_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT25_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT26_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT27_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT28_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT29_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT30_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT31_TYPE XTHAL_INTTYPE_EXTERN_LEVEL + +/* Masks of interrupts for each type of interrupt: */ +#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0x00000000 +#define XCHAL_INTTYPE_MASK_SOFTWARE 0x20000080 +#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x50400400 +#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x8FBE333F +#define XCHAL_INTTYPE_MASK_TIMER 0x00018040 +#define XCHAL_INTTYPE_MASK_NMI 0x00004000 +#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 +#define XCHAL_INTTYPE_MASK_PROFILING 0x00000800 + +/* Interrupt numbers assigned to specific interrupt sources: */ +#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */ +#define XCHAL_TIMER1_INTERRUPT 15 /* CCOMPARE1 */ +#define XCHAL_TIMER2_INTERRUPT 16 /* CCOMPARE2 */ +#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED +#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */ +#define XCHAL_PROFILING_INTERRUPT 11 /* profiling interrupt */ + +/* Interrupt numbers for levels at which only one interrupt is configured: */ +#define XCHAL_INTLEVEL7_NUM 14 +/* (There are many interrupts each at level(s) 1, 2, 3, 4, 5.) */ + + +/* + * External interrupt mapping. + * These macros describe how Xtensa processor interrupt numbers + * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) + * map to external BInterrupt pins, for those interrupts + * configured as external (level-triggered, edge-triggered, or NMI). + * See the Xtensa processor databook for more details. + */ + +/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */ +#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */ +#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */ +#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */ +#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */ +#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */ +#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */ +#define XCHAL_EXTINT6_NUM 8 /* (intlevel 1) */ +#define XCHAL_EXTINT7_NUM 9 /* (intlevel 1) */ +#define XCHAL_EXTINT8_NUM 10 /* (intlevel 1) */ +#define XCHAL_EXTINT9_NUM 12 /* (intlevel 1) */ +#define XCHAL_EXTINT10_NUM 13 /* (intlevel 1) */ +#define XCHAL_EXTINT11_NUM 14 /* (intlevel 7) */ +#define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */ +#define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */ +#define XCHAL_EXTINT14_NUM 19 /* (intlevel 2) */ +#define XCHAL_EXTINT15_NUM 20 /* (intlevel 2) */ +#define XCHAL_EXTINT16_NUM 21 /* (intlevel 2) */ +#define XCHAL_EXTINT17_NUM 22 /* (intlevel 3) */ +#define XCHAL_EXTINT18_NUM 23 /* (intlevel 3) */ +#define XCHAL_EXTINT19_NUM 24 /* (intlevel 4) */ +#define XCHAL_EXTINT20_NUM 25 /* (intlevel 4) */ +#define XCHAL_EXTINT21_NUM 26 /* (intlevel 5) */ +#define XCHAL_EXTINT22_NUM 27 /* (intlevel 3) */ +#define XCHAL_EXTINT23_NUM 28 /* (intlevel 4) */ +#define XCHAL_EXTINT24_NUM 30 /* (intlevel 4) */ +#define XCHAL_EXTINT25_NUM 31 /* (intlevel 5) */ +/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */ +#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */ +#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */ +#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */ +#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */ +#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */ +#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */ +#define XCHAL_INT8_EXTNUM 6 /* (intlevel 1) */ +#define XCHAL_INT9_EXTNUM 7 /* (intlevel 1) */ +#define XCHAL_INT10_EXTNUM 8 /* (intlevel 1) */ +#define XCHAL_INT12_EXTNUM 9 /* (intlevel 1) */ +#define XCHAL_INT13_EXTNUM 10 /* (intlevel 1) */ +#define XCHAL_INT14_EXTNUM 11 /* (intlevel 7) */ +#define XCHAL_INT17_EXTNUM 12 /* (intlevel 1) */ +#define XCHAL_INT18_EXTNUM 13 /* (intlevel 1) */ +#define XCHAL_INT19_EXTNUM 14 /* (intlevel 2) */ +#define XCHAL_INT20_EXTNUM 15 /* (intlevel 2) */ +#define XCHAL_INT21_EXTNUM 16 /* (intlevel 2) */ +#define XCHAL_INT22_EXTNUM 17 /* (intlevel 3) */ +#define XCHAL_INT23_EXTNUM 18 /* (intlevel 3) */ +#define XCHAL_INT24_EXTNUM 19 /* (intlevel 4) */ +#define XCHAL_INT25_EXTNUM 20 /* (intlevel 4) */ +#define XCHAL_INT26_EXTNUM 21 /* (intlevel 5) */ +#define XCHAL_INT27_EXTNUM 22 /* (intlevel 3) */ +#define XCHAL_INT28_EXTNUM 23 /* (intlevel 4) */ +#define XCHAL_INT30_EXTNUM 24 /* (intlevel 4) */ +#define XCHAL_INT31_EXTNUM 25 /* (intlevel 5) */ + + +/*---------------------------------------------------------------------- + EXCEPTIONS and VECTORS + ----------------------------------------------------------------------*/ + +#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture + number: 1 == XEA1 (old) + 2 == XEA2 (new) + 0 == XEAX (extern) or TX */ +#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ +#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ +#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ +#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ +#define XCHAL_HAVE_HALT 0 /* halt architecture option */ +#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ +#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ +#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ +#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ +#define XCHAL_VECBASE_RESET_VADDR 0x40000000 /* VECBASE reset value */ +#define XCHAL_VECBASE_RESET_PADDR 0x40000000 +#define XCHAL_RESET_VECBASE_OVERLAP 0 + +#define XCHAL_RESET_VECTOR0_VADDR 0x50000000 +#define XCHAL_RESET_VECTOR0_PADDR 0x50000000 +#define XCHAL_RESET_VECTOR1_VADDR 0x40000400 +#define XCHAL_RESET_VECTOR1_PADDR 0x40000400 +#define XCHAL_RESET_VECTOR_VADDR 0x40000400 +#define XCHAL_RESET_VECTOR_PADDR 0x40000400 +#define XCHAL_USER_VECOFS 0x00000340 +#define XCHAL_USER_VECTOR_VADDR 0x40000340 +#define XCHAL_USER_VECTOR_PADDR 0x40000340 +#define XCHAL_KERNEL_VECOFS 0x00000300 +#define XCHAL_KERNEL_VECTOR_VADDR 0x40000300 +#define XCHAL_KERNEL_VECTOR_PADDR 0x40000300 +#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0 +#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x400003C0 +#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x400003C0 +#define XCHAL_WINDOW_OF4_VECOFS 0x00000000 +#define XCHAL_WINDOW_UF4_VECOFS 0x00000040 +#define XCHAL_WINDOW_OF8_VECOFS 0x00000080 +#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 +#define XCHAL_WINDOW_OF12_VECOFS 0x00000100 +#define XCHAL_WINDOW_UF12_VECOFS 0x00000140 +#define XCHAL_WINDOW_VECTORS_VADDR 0x40000000 +#define XCHAL_WINDOW_VECTORS_PADDR 0x40000000 +#define XCHAL_INTLEVEL2_VECOFS 0x00000180 +#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x40000180 +#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x40000180 +#define XCHAL_INTLEVEL3_VECOFS 0x000001C0 +#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x400001C0 +#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x400001C0 +#define XCHAL_INTLEVEL4_VECOFS 0x00000200 +#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x40000200 +#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x40000200 +#define XCHAL_INTLEVEL5_VECOFS 0x00000240 +#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x40000240 +#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x40000240 +#define XCHAL_INTLEVEL6_VECOFS 0x00000280 +#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x40000280 +#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x40000280 +#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS +#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR +#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR +#define XCHAL_NMI_VECOFS 0x000002C0 +#define XCHAL_NMI_VECTOR_VADDR 0x400002C0 +#define XCHAL_NMI_VECTOR_PADDR 0x400002C0 +#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS +#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR +#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR + + +/*---------------------------------------------------------------------- + DEBUG MODULE + ----------------------------------------------------------------------*/ + +/* Misc */ +#define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */ +#define XCHAL_HAVE_DEBUG_APB 1 /* APB to debug module */ +#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */ + +/* On-Chip Debug (OCD) */ +#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ +#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ +#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ +#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */ +#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */ + +/* TRAX (in core) */ +#define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */ +#define XCHAL_TRAX_MEM_SIZE 16384 /* TRAX memory size in bytes */ +#define XCHAL_TRAX_MEM_SHAREABLE 1 /* start/end regs; ready sig. */ +#define XCHAL_TRAX_ATB_WIDTH 32 /* ATB width (bits), 0=no ATB */ +#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ + +/* Perf counters */ +#define XCHAL_NUM_PERF_COUNTERS 2 /* performance counters */ + + +/*---------------------------------------------------------------------- + MMU + ----------------------------------------------------------------------*/ + +/* See core-matmap.h header file for more details. */ + +#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ +#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ +#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */ +#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */ +#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ +#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */ +#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ +#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table + [autorefill] and protection) + usable for an MMU-based OS */ +/* If none of the above last 4 are set, it's a custom TLB configuration. */ + +#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ +#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ +#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */ + +#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ + + +#endif /* _XTENSA_CORE_CONFIGURATION_H */ + diff --git a/tools/sdk/include/esp32/xtensa/config/core-matmap.h b/tools/sdk/include/esp32/xtensa/config/core-matmap.h new file mode 100644 index 00000000..b101f1e6 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/config/core-matmap.h @@ -0,0 +1,318 @@ +/* + * xtensa/config/core-matmap.h -- Memory access and translation mapping + * parameters (CHAL) of the Xtensa processor core configuration. + * + * If you are using Xtensa Tools, see (which includes + * this file) for more details. + * + * In the Xtensa processor products released to date, all parameters + * defined in this file are derivable (at least in theory) from + * information contained in the core-isa.h header file. + * In particular, the following core configuration parameters are relevant: + * XCHAL_HAVE_CACHEATTR + * XCHAL_HAVE_MIMIC_CACHEATTR + * XCHAL_HAVE_XLT_CACHEATTR + * XCHAL_HAVE_PTP_MMU + * XCHAL_ITLB_ARF_ENTRIES_LOG2 + * XCHAL_DTLB_ARF_ENTRIES_LOG2 + * XCHAL_DCACHE_IS_WRITEBACK + * XCHAL_ICACHE_SIZE (presence of I-cache) + * XCHAL_DCACHE_SIZE (presence of D-cache) + * XCHAL_HW_VERSION_MAJOR + * XCHAL_HW_VERSION_MINOR + */ + +/* Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + + +#ifndef XTENSA_CONFIG_CORE_MATMAP_H +#define XTENSA_CONFIG_CORE_MATMAP_H + + +/*---------------------------------------------------------------------- + CACHE (MEMORY ACCESS) ATTRIBUTES + ----------------------------------------------------------------------*/ + + +/* Cache Attribute encodings -- lists of access modes for each cache attribute: */ +#define XCHAL_FCA_LIST XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_BYPASS XCHAL_SEP \ + XTHAL_FAM_BYPASS XCHAL_SEP \ + XTHAL_FAM_BYPASS XCHAL_SEP \ + XTHAL_FAM_BYPASS XCHAL_SEP \ + XTHAL_FAM_BYPASS XCHAL_SEP \ + XTHAL_FAM_BYPASS XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION +#define XCHAL_LCA_LIST XTHAL_LAM_BYPASSG XCHAL_SEP \ + XTHAL_LAM_BYPASSG XCHAL_SEP \ + XTHAL_LAM_BYPASSG XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_BYPASSG XCHAL_SEP \ + XTHAL_LAM_BYPASSG XCHAL_SEP \ + XTHAL_LAM_BYPASSG XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_BYPASSG XCHAL_SEP \ + XTHAL_LAM_EXCEPTION +#define XCHAL_SCA_LIST XTHAL_SAM_BYPASS XCHAL_SEP \ + XTHAL_SAM_BYPASS XCHAL_SEP \ + XTHAL_SAM_BYPASS XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_BYPASS XCHAL_SEP \ + XTHAL_SAM_BYPASS XCHAL_SEP \ + XTHAL_SAM_BYPASS XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_BYPASS XCHAL_SEP \ + XTHAL_SAM_EXCEPTION + + +/* + * Specific encoded cache attribute values of general interest. + * If a specific cache mode is not available, the closest available + * one is returned instead (eg. writethru instead of writeback, + * bypass instead of writethru). + */ +#define XCHAL_CA_BYPASS 2 /* cache disabled (bypassed) mode */ +#define XCHAL_CA_BYPASSBUF 6 /* cache disabled (bypassed) bufferable mode */ +#define XCHAL_CA_WRITETHRU 2 /* cache enabled (write-through) mode */ +#define XCHAL_CA_WRITEBACK 2 /* cache enabled (write-back) mode */ +#define XCHAL_HAVE_CA_WRITEBACK_NOALLOC 0 /* write-back no-allocate availability */ +#define XCHAL_CA_WRITEBACK_NOALLOC 2 /* cache enabled (write-back no-allocate) mode */ +#define XCHAL_CA_BYPASS_RW 0 /* cache disabled (bypassed) mode (no exec) */ +#define XCHAL_CA_WRITETHRU_RW 0 /* cache enabled (write-through) mode (no exec) */ +#define XCHAL_CA_WRITEBACK_RW 0 /* cache enabled (write-back) mode (no exec) */ +#define XCHAL_CA_WRITEBACK_NOALLOC_RW 0 /* cache enabled (write-back no-allocate) mode (no exec) */ +#define XCHAL_CA_ILLEGAL 15 /* no access allowed (all cause exceptions) mode */ +#define XCHAL_CA_ISOLATE 0 /* cache isolate (accesses go to cache not memory) mode */ + + +/*---------------------------------------------------------------------- + MMU + ----------------------------------------------------------------------*/ + +/* + * General notes on MMU parameters. + * + * Terminology: + * ASID = address-space ID (acts as an "extension" of virtual addresses) + * VPN = virtual page number + * PPN = physical page number + * CA = encoded cache attribute (access modes) + * TLB = translation look-aside buffer (term is stretched somewhat here) + * I = instruction (fetch accesses) + * D = data (load and store accesses) + * way = each TLB (ITLB and DTLB) consists of a number of "ways" + * that simultaneously match the virtual address of an access; + * a TLB successfully translates a virtual address if exactly + * one way matches the vaddr; if none match, it is a miss; + * if multiple match, one gets a "multihit" exception; + * each way can be independently configured in terms of number of + * entries, page sizes, which fields are writable or constant, etc. + * set = group of contiguous ways with exactly identical parameters + * ARF = auto-refill; hardware services a 1st-level miss by loading a PTE + * from the page table and storing it in one of the auto-refill ways; + * if this PTE load also misses, a miss exception is posted for s/w. + * min-wired = a "min-wired" way can be used to map a single (minimum-sized) + * page arbitrarily under program control; it has a single entry, + * is non-auto-refill (some other way(s) must be auto-refill), + * all its fields (VPN, PPN, ASID, CA) are all writable, and it + * supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current + * restriction is that this be the only page size it supports). + * + * TLB way entries are virtually indexed. + * TLB ways that support multiple page sizes: + * - must have all writable VPN and PPN fields; + * - can only use one page size at any given time (eg. setup at startup), + * selected by the respective ITLBCFG or DTLBCFG special register, + * whose bits n*4+3 .. n*4 index the list of page sizes for way n + * (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n); + * this list may be sparse for auto-refill ways because auto-refill + * ways have independent lists of supported page sizes sharing a + * common encoding with PTE entries; the encoding is the index into + * this list; unsupported sizes for a given way are zero in the list; + * selecting unsupported sizes results in undefined hardware behaviour; + * - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition). + */ + +#define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */ +#define XCHAL_MMU_ASID_KERNEL 0 /* ASID value indicating kernel (ring 0) address space */ +#define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */ +#define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */ +#define XCHAL_MMU_MAX_PTE_PAGE_SIZE 29 /* max page size in a PTE structure (log2) */ +#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 29 /* min page size in a PTE structure (log2) */ + + +/*** Instruction TLB: ***/ + +#define XCHAL_ITLB_WAY_BITS 0 /* number of bits holding the ways */ +#define XCHAL_ITLB_WAYS 1 /* number of ways (n-way set-associative TLB) */ +#define XCHAL_ITLB_ARF_WAYS 0 /* number of auto-refill ways */ +#define XCHAL_ITLB_SETS 1 /* number of sets (groups of ways with identical settings) */ + +/* Way set to which each way belongs: */ +#define XCHAL_ITLB_WAY0_SET 0 + +/* Ways sets that are used by hardware auto-refill (ARF): */ +#define XCHAL_ITLB_ARF_SETS 0 /* number of auto-refill sets */ + +/* Way sets that are "min-wired" (see terminology comment above): */ +#define XCHAL_ITLB_MINWIRED_SETS 0 /* number of "min-wired" sets */ + + +/* ITLB way set 0 (group of ways 0 thru 0): */ +#define XCHAL_ITLB_SET0_WAY 0 /* index of first way in this way set */ +#define XCHAL_ITLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */ +#define XCHAL_ITLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */ +#define XCHAL_ITLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */ +#define XCHAL_ITLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ +#define XCHAL_ITLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */ +#define XCHAL_ITLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */ +#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */ +#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */ +#define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP; + 2^PAGESZ_BITS entries in list, unsupported entries are zero */ +#define XCHAL_ITLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ +#define XCHAL_ITLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */ +#define XCHAL_ITLB_SET0_PPN_CONSTMASK 0xE0000000 /* constant PPN bits, including entry index bits; 0 if all writable */ +#define XCHAL_ITLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ +#define XCHAL_ITLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ +#define XCHAL_ITLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_ITLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_ITLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */ +/* Constant VPN values for each entry of ITLB way set 0 (because VPN_CONSTMASK is non-zero): */ +#define XCHAL_ITLB_SET0_E0_VPN_CONST 0x00000000 +#define XCHAL_ITLB_SET0_E1_VPN_CONST 0x20000000 +#define XCHAL_ITLB_SET0_E2_VPN_CONST 0x40000000 +#define XCHAL_ITLB_SET0_E3_VPN_CONST 0x60000000 +#define XCHAL_ITLB_SET0_E4_VPN_CONST 0x80000000 +#define XCHAL_ITLB_SET0_E5_VPN_CONST 0xA0000000 +#define XCHAL_ITLB_SET0_E6_VPN_CONST 0xC0000000 +#define XCHAL_ITLB_SET0_E7_VPN_CONST 0xE0000000 +/* Constant PPN values for each entry of ITLB way set 0 (because PPN_CONSTMASK is non-zero): */ +#define XCHAL_ITLB_SET0_E0_PPN_CONST 0x00000000 +#define XCHAL_ITLB_SET0_E1_PPN_CONST 0x20000000 +#define XCHAL_ITLB_SET0_E2_PPN_CONST 0x40000000 +#define XCHAL_ITLB_SET0_E3_PPN_CONST 0x60000000 +#define XCHAL_ITLB_SET0_E4_PPN_CONST 0x80000000 +#define XCHAL_ITLB_SET0_E5_PPN_CONST 0xA0000000 +#define XCHAL_ITLB_SET0_E6_PPN_CONST 0xC0000000 +#define XCHAL_ITLB_SET0_E7_PPN_CONST 0xE0000000 +/* Reset CA values for each entry of ITLB way set 0 (because SET0_CA_RESET is non-zero): */ +#define XCHAL_ITLB_SET0_E0_CA_RESET 0x02 +#define XCHAL_ITLB_SET0_E1_CA_RESET 0x02 +#define XCHAL_ITLB_SET0_E2_CA_RESET 0x02 +#define XCHAL_ITLB_SET0_E3_CA_RESET 0x02 +#define XCHAL_ITLB_SET0_E4_CA_RESET 0x02 +#define XCHAL_ITLB_SET0_E5_CA_RESET 0x02 +#define XCHAL_ITLB_SET0_E6_CA_RESET 0x02 +#define XCHAL_ITLB_SET0_E7_CA_RESET 0x02 + + +/*** Data TLB: ***/ + +#define XCHAL_DTLB_WAY_BITS 0 /* number of bits holding the ways */ +#define XCHAL_DTLB_WAYS 1 /* number of ways (n-way set-associative TLB) */ +#define XCHAL_DTLB_ARF_WAYS 0 /* number of auto-refill ways */ +#define XCHAL_DTLB_SETS 1 /* number of sets (groups of ways with identical settings) */ + +/* Way set to which each way belongs: */ +#define XCHAL_DTLB_WAY0_SET 0 + +/* Ways sets that are used by hardware auto-refill (ARF): */ +#define XCHAL_DTLB_ARF_SETS 0 /* number of auto-refill sets */ + +/* Way sets that are "min-wired" (see terminology comment above): */ +#define XCHAL_DTLB_MINWIRED_SETS 0 /* number of "min-wired" sets */ + + +/* DTLB way set 0 (group of ways 0 thru 0): */ +#define XCHAL_DTLB_SET0_WAY 0 /* index of first way in this way set */ +#define XCHAL_DTLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */ +#define XCHAL_DTLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */ +#define XCHAL_DTLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */ +#define XCHAL_DTLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ +#define XCHAL_DTLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */ +#define XCHAL_DTLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */ +#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */ +#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */ +#define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP; + 2^PAGESZ_BITS entries in list, unsupported entries are zero */ +#define XCHAL_DTLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ +#define XCHAL_DTLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */ +#define XCHAL_DTLB_SET0_PPN_CONSTMASK 0xE0000000 /* constant PPN bits, including entry index bits; 0 if all writable */ +#define XCHAL_DTLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ +#define XCHAL_DTLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */ +/* Constant VPN values for each entry of DTLB way set 0 (because VPN_CONSTMASK is non-zero): */ +#define XCHAL_DTLB_SET0_E0_VPN_CONST 0x00000000 +#define XCHAL_DTLB_SET0_E1_VPN_CONST 0x20000000 +#define XCHAL_DTLB_SET0_E2_VPN_CONST 0x40000000 +#define XCHAL_DTLB_SET0_E3_VPN_CONST 0x60000000 +#define XCHAL_DTLB_SET0_E4_VPN_CONST 0x80000000 +#define XCHAL_DTLB_SET0_E5_VPN_CONST 0xA0000000 +#define XCHAL_DTLB_SET0_E6_VPN_CONST 0xC0000000 +#define XCHAL_DTLB_SET0_E7_VPN_CONST 0xE0000000 +/* Constant PPN values for each entry of DTLB way set 0 (because PPN_CONSTMASK is non-zero): */ +#define XCHAL_DTLB_SET0_E0_PPN_CONST 0x00000000 +#define XCHAL_DTLB_SET0_E1_PPN_CONST 0x20000000 +#define XCHAL_DTLB_SET0_E2_PPN_CONST 0x40000000 +#define XCHAL_DTLB_SET0_E3_PPN_CONST 0x60000000 +#define XCHAL_DTLB_SET0_E4_PPN_CONST 0x80000000 +#define XCHAL_DTLB_SET0_E5_PPN_CONST 0xA0000000 +#define XCHAL_DTLB_SET0_E6_PPN_CONST 0xC0000000 +#define XCHAL_DTLB_SET0_E7_PPN_CONST 0xE0000000 +/* Reset CA values for each entry of DTLB way set 0 (because SET0_CA_RESET is non-zero): */ +#define XCHAL_DTLB_SET0_E0_CA_RESET 0x02 +#define XCHAL_DTLB_SET0_E1_CA_RESET 0x02 +#define XCHAL_DTLB_SET0_E2_CA_RESET 0x02 +#define XCHAL_DTLB_SET0_E3_CA_RESET 0x02 +#define XCHAL_DTLB_SET0_E4_CA_RESET 0x02 +#define XCHAL_DTLB_SET0_E5_CA_RESET 0x02 +#define XCHAL_DTLB_SET0_E6_CA_RESET 0x02 +#define XCHAL_DTLB_SET0_E7_CA_RESET 0x02 + + + + +#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/ + diff --git a/tools/sdk/include/esp32/xtensa/config/core.h b/tools/sdk/include/esp32/xtensa/config/core.h new file mode 100644 index 00000000..98f1b196 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/config/core.h @@ -0,0 +1,1405 @@ +/* + * xtensa/config/core.h -- HAL definitions dependent on CORE configuration + * + * This header file is sometimes referred to as the "compile-time HAL" or CHAL. + * It pulls definitions tailored for a specific Xtensa processor configuration. + * + * Sources for binaries meant to be configuration-independent generally avoid + * including this file (they may use the configuration-specific HAL library). + * It is normal for the HAL library source itself to include this file. + */ + +/* + * Copyright (c) 2005-2014 Cadence Design Systems, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + + +#ifndef XTENSA_CONFIG_CORE_H +#define XTENSA_CONFIG_CORE_H + +/* CONFIGURATION INDEPENDENT DEFINITIONS: */ +#ifdef __XTENSA__ +#include +#include +#else +#include "../hal.h" +#include "../xtensa-versions.h" +#endif + +/* CONFIGURATION SPECIFIC DEFINITIONS: */ +#ifdef __XTENSA__ +#include +#include +#include +#else +#include "core-isa.h" +#include "core-matmap.h" +#include "tie.h" +#endif + +#if defined (_ASMLANGUAGE) || defined (__ASSEMBLER__) +#ifdef __XTENSA__ +#include +#else +#include "tie-asm.h" +#endif +#endif /*_ASMLANGUAGE or __ASSEMBLER__*/ + + +/*---------------------------------------------------------------------- + GENERAL + ----------------------------------------------------------------------*/ + +/* + * Separators for macros that expand into arrays. + * These can be predefined by files that #include this one, + * when different separators are required. + */ +/* Element separator for macros that expand into 1-dimensional arrays: */ +#ifndef XCHAL_SEP +#define XCHAL_SEP , +#endif +/* Array separator for macros that expand into 2-dimensional arrays: */ +#ifndef XCHAL_SEP2 +#define XCHAL_SEP2 },{ +#endif + + + +/*---------------------------------------------------------------------- + ISA + ----------------------------------------------------------------------*/ + +#if XCHAL_HAVE_BE +# define XCHAL_HAVE_LE 0 +# define XCHAL_MEMORY_ORDER XTHAL_BIGENDIAN +#else +# define XCHAL_HAVE_LE 1 +# define XCHAL_MEMORY_ORDER XTHAL_LITTLEENDIAN +#endif + + + +/*---------------------------------------------------------------------- + INTERRUPTS + ----------------------------------------------------------------------*/ + +/* Indexing macros: */ +#define _XCHAL_INTLEVEL_MASK(n) XCHAL_INTLEVEL ## n ## _MASK +#define XCHAL_INTLEVEL_MASK(n) _XCHAL_INTLEVEL_MASK(n) /* n = 0 .. 15 */ +#define _XCHAL_INTLEVEL_ANDBELOWMASK(n) XCHAL_INTLEVEL ## n ## _ANDBELOW_MASK +#define XCHAL_INTLEVEL_ANDBELOW_MASK(n) _XCHAL_INTLEVEL_ANDBELOWMASK(n) /* n = 0 .. 15 */ +#define _XCHAL_INTLEVEL_NUM(n) XCHAL_INTLEVEL ## n ## _NUM +#define XCHAL_INTLEVEL_NUM(n) _XCHAL_INTLEVEL_NUM(n) /* n = 0 .. 15 */ +#define _XCHAL_INT_LEVEL(n) XCHAL_INT ## n ## _LEVEL +#define XCHAL_INT_LEVEL(n) _XCHAL_INT_LEVEL(n) /* n = 0 .. 31 */ +#define _XCHAL_INT_TYPE(n) XCHAL_INT ## n ## _TYPE +#define XCHAL_INT_TYPE(n) _XCHAL_INT_TYPE(n) /* n = 0 .. 31 */ +#define _XCHAL_TIMER_INTERRUPT(n) XCHAL_TIMER ## n ## _INTERRUPT +#define XCHAL_TIMER_INTERRUPT(n) _XCHAL_TIMER_INTERRUPT(n) /* n = 0 .. 3 */ + + +#define XCHAL_HAVE_HIGHLEVEL_INTERRUPTS XCHAL_HAVE_HIGHPRI_INTERRUPTS +#define XCHAL_NUM_LOWPRI_LEVELS 1 /* number of low-priority interrupt levels (always 1) */ +#define XCHAL_FIRST_HIGHPRI_LEVEL (XCHAL_NUM_LOWPRI_LEVELS+1) /* level of first high-priority interrupt (always 2) */ +/* Note: 1 <= LOWPRI_LEVELS <= EXCM_LEVEL < DEBUGLEVEL <= NUM_INTLEVELS < NMILEVEL <= 15 */ + +/* These values are constant for existing Xtensa processor implementations: */ +#define XCHAL_INTLEVEL0_MASK 0x00000000 +#define XCHAL_INTLEVEL8_MASK 0x00000000 +#define XCHAL_INTLEVEL9_MASK 0x00000000 +#define XCHAL_INTLEVEL10_MASK 0x00000000 +#define XCHAL_INTLEVEL11_MASK 0x00000000 +#define XCHAL_INTLEVEL12_MASK 0x00000000 +#define XCHAL_INTLEVEL13_MASK 0x00000000 +#define XCHAL_INTLEVEL14_MASK 0x00000000 +#define XCHAL_INTLEVEL15_MASK 0x00000000 + +/* Array of masks of interrupts at each interrupt level: */ +#define XCHAL_INTLEVEL_MASKS XCHAL_INTLEVEL0_MASK \ + XCHAL_SEP XCHAL_INTLEVEL1_MASK \ + XCHAL_SEP XCHAL_INTLEVEL2_MASK \ + XCHAL_SEP XCHAL_INTLEVEL3_MASK \ + XCHAL_SEP XCHAL_INTLEVEL4_MASK \ + XCHAL_SEP XCHAL_INTLEVEL5_MASK \ + XCHAL_SEP XCHAL_INTLEVEL6_MASK \ + XCHAL_SEP XCHAL_INTLEVEL7_MASK \ + XCHAL_SEP XCHAL_INTLEVEL8_MASK \ + XCHAL_SEP XCHAL_INTLEVEL9_MASK \ + XCHAL_SEP XCHAL_INTLEVEL10_MASK \ + XCHAL_SEP XCHAL_INTLEVEL11_MASK \ + XCHAL_SEP XCHAL_INTLEVEL12_MASK \ + XCHAL_SEP XCHAL_INTLEVEL13_MASK \ + XCHAL_SEP XCHAL_INTLEVEL14_MASK \ + XCHAL_SEP XCHAL_INTLEVEL15_MASK + +/* These values are constant for existing Xtensa processor implementations: */ +#define XCHAL_INTLEVEL0_ANDBELOW_MASK 0x00000000 +#define XCHAL_INTLEVEL8_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK +#define XCHAL_INTLEVEL9_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK +#define XCHAL_INTLEVEL10_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK +#define XCHAL_INTLEVEL11_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK +#define XCHAL_INTLEVEL12_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK +#define XCHAL_INTLEVEL13_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK +#define XCHAL_INTLEVEL14_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK +#define XCHAL_INTLEVEL15_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK + +/* Mask of all low-priority interrupts: */ +#define XCHAL_LOWPRI_MASK XCHAL_INTLEVEL1_ANDBELOW_MASK + +/* Mask of all interrupts masked by PS.EXCM (or CEXCM): */ +#define XCHAL_EXCM_MASK XCHAL_INTLEVEL_ANDBELOW_MASK(XCHAL_EXCM_LEVEL) + +/* Array of masks of interrupts at each range 1..n of interrupt levels: */ +#define XCHAL_INTLEVEL_ANDBELOW_MASKS XCHAL_INTLEVEL0_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL1_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL2_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL3_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL4_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL5_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL6_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL7_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL8_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL9_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL10_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL11_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL12_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL13_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL14_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL15_ANDBELOW_MASK + +#if 0 /*XCHAL_HAVE_NMI*/ +/* NMI "interrupt level" (for use with EXCSAVE_n, EPS_n, EPC_n, RFI n): */ +# define XCHAL_NMILEVEL (XCHAL_NUM_INTLEVELS+1) +#endif + +/* Array of levels of each possible interrupt: */ +#define XCHAL_INT_LEVELS XCHAL_INT0_LEVEL \ + XCHAL_SEP XCHAL_INT1_LEVEL \ + XCHAL_SEP XCHAL_INT2_LEVEL \ + XCHAL_SEP XCHAL_INT3_LEVEL \ + XCHAL_SEP XCHAL_INT4_LEVEL \ + XCHAL_SEP XCHAL_INT5_LEVEL \ + XCHAL_SEP XCHAL_INT6_LEVEL \ + XCHAL_SEP XCHAL_INT7_LEVEL \ + XCHAL_SEP XCHAL_INT8_LEVEL \ + XCHAL_SEP XCHAL_INT9_LEVEL \ + XCHAL_SEP XCHAL_INT10_LEVEL \ + XCHAL_SEP XCHAL_INT11_LEVEL \ + XCHAL_SEP XCHAL_INT12_LEVEL \ + XCHAL_SEP XCHAL_INT13_LEVEL \ + XCHAL_SEP XCHAL_INT14_LEVEL \ + XCHAL_SEP XCHAL_INT15_LEVEL \ + XCHAL_SEP XCHAL_INT16_LEVEL \ + XCHAL_SEP XCHAL_INT17_LEVEL \ + XCHAL_SEP XCHAL_INT18_LEVEL \ + XCHAL_SEP XCHAL_INT19_LEVEL \ + XCHAL_SEP XCHAL_INT20_LEVEL \ + XCHAL_SEP XCHAL_INT21_LEVEL \ + XCHAL_SEP XCHAL_INT22_LEVEL \ + XCHAL_SEP XCHAL_INT23_LEVEL \ + XCHAL_SEP XCHAL_INT24_LEVEL \ + XCHAL_SEP XCHAL_INT25_LEVEL \ + XCHAL_SEP XCHAL_INT26_LEVEL \ + XCHAL_SEP XCHAL_INT27_LEVEL \ + XCHAL_SEP XCHAL_INT28_LEVEL \ + XCHAL_SEP XCHAL_INT29_LEVEL \ + XCHAL_SEP XCHAL_INT30_LEVEL \ + XCHAL_SEP XCHAL_INT31_LEVEL + +/* Array of types of each possible interrupt: */ +#define XCHAL_INT_TYPES XCHAL_INT0_TYPE \ + XCHAL_SEP XCHAL_INT1_TYPE \ + XCHAL_SEP XCHAL_INT2_TYPE \ + XCHAL_SEP XCHAL_INT3_TYPE \ + XCHAL_SEP XCHAL_INT4_TYPE \ + XCHAL_SEP XCHAL_INT5_TYPE \ + XCHAL_SEP XCHAL_INT6_TYPE \ + XCHAL_SEP XCHAL_INT7_TYPE \ + XCHAL_SEP XCHAL_INT8_TYPE \ + XCHAL_SEP XCHAL_INT9_TYPE \ + XCHAL_SEP XCHAL_INT10_TYPE \ + XCHAL_SEP XCHAL_INT11_TYPE \ + XCHAL_SEP XCHAL_INT12_TYPE \ + XCHAL_SEP XCHAL_INT13_TYPE \ + XCHAL_SEP XCHAL_INT14_TYPE \ + XCHAL_SEP XCHAL_INT15_TYPE \ + XCHAL_SEP XCHAL_INT16_TYPE \ + XCHAL_SEP XCHAL_INT17_TYPE \ + XCHAL_SEP XCHAL_INT18_TYPE \ + XCHAL_SEP XCHAL_INT19_TYPE \ + XCHAL_SEP XCHAL_INT20_TYPE \ + XCHAL_SEP XCHAL_INT21_TYPE \ + XCHAL_SEP XCHAL_INT22_TYPE \ + XCHAL_SEP XCHAL_INT23_TYPE \ + XCHAL_SEP XCHAL_INT24_TYPE \ + XCHAL_SEP XCHAL_INT25_TYPE \ + XCHAL_SEP XCHAL_INT26_TYPE \ + XCHAL_SEP XCHAL_INT27_TYPE \ + XCHAL_SEP XCHAL_INT28_TYPE \ + XCHAL_SEP XCHAL_INT29_TYPE \ + XCHAL_SEP XCHAL_INT30_TYPE \ + XCHAL_SEP XCHAL_INT31_TYPE + +/* Array of masks of interrupts for each type of interrupt: */ +#define XCHAL_INTTYPE_MASKS XCHAL_INTTYPE_MASK_UNCONFIGURED \ + XCHAL_SEP XCHAL_INTTYPE_MASK_SOFTWARE \ + XCHAL_SEP XCHAL_INTTYPE_MASK_EXTERN_EDGE \ + XCHAL_SEP XCHAL_INTTYPE_MASK_EXTERN_LEVEL \ + XCHAL_SEP XCHAL_INTTYPE_MASK_TIMER \ + XCHAL_SEP XCHAL_INTTYPE_MASK_NMI \ + XCHAL_SEP XCHAL_INTTYPE_MASK_WRITE_ERROR + +/* Interrupts that can be cleared using the INTCLEAR special register: */ +#define XCHAL_INTCLEARABLE_MASK (XCHAL_INTTYPE_MASK_SOFTWARE+XCHAL_INTTYPE_MASK_EXTERN_EDGE+XCHAL_INTTYPE_MASK_WRITE_ERROR) +/* Interrupts that can be triggered using the INTSET special register: */ +#define XCHAL_INTSETTABLE_MASK XCHAL_INTTYPE_MASK_SOFTWARE + +/* Array of interrupts assigned to each timer (CCOMPARE0 to CCOMPARE3): */ +#define XCHAL_TIMER_INTERRUPTS XCHAL_TIMER0_INTERRUPT \ + XCHAL_SEP XCHAL_TIMER1_INTERRUPT \ + XCHAL_SEP XCHAL_TIMER2_INTERRUPT \ + XCHAL_SEP XCHAL_TIMER3_INTERRUPT + + + +/* For backward compatibility and for the array macros, define macros for + * each unconfigured interrupt number (unfortunately, the value of + * XTHAL_INTTYPE_UNCONFIGURED is not zero): */ +#if XCHAL_NUM_INTERRUPTS == 0 +# define XCHAL_INT0_LEVEL 0 +# define XCHAL_INT0_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 1 +# define XCHAL_INT1_LEVEL 0 +# define XCHAL_INT1_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 2 +# define XCHAL_INT2_LEVEL 0 +# define XCHAL_INT2_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 3 +# define XCHAL_INT3_LEVEL 0 +# define XCHAL_INT3_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 4 +# define XCHAL_INT4_LEVEL 0 +# define XCHAL_INT4_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 5 +# define XCHAL_INT5_LEVEL 0 +# define XCHAL_INT5_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 6 +# define XCHAL_INT6_LEVEL 0 +# define XCHAL_INT6_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 7 +# define XCHAL_INT7_LEVEL 0 +# define XCHAL_INT7_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 8 +# define XCHAL_INT8_LEVEL 0 +# define XCHAL_INT8_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 9 +# define XCHAL_INT9_LEVEL 0 +# define XCHAL_INT9_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 10 +# define XCHAL_INT10_LEVEL 0 +# define XCHAL_INT10_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 11 +# define XCHAL_INT11_LEVEL 0 +# define XCHAL_INT11_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 12 +# define XCHAL_INT12_LEVEL 0 +# define XCHAL_INT12_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 13 +# define XCHAL_INT13_LEVEL 0 +# define XCHAL_INT13_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 14 +# define XCHAL_INT14_LEVEL 0 +# define XCHAL_INT14_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 15 +# define XCHAL_INT15_LEVEL 0 +# define XCHAL_INT15_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 16 +# define XCHAL_INT16_LEVEL 0 +# define XCHAL_INT16_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 17 +# define XCHAL_INT17_LEVEL 0 +# define XCHAL_INT17_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 18 +# define XCHAL_INT18_LEVEL 0 +# define XCHAL_INT18_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 19 +# define XCHAL_INT19_LEVEL 0 +# define XCHAL_INT19_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 20 +# define XCHAL_INT20_LEVEL 0 +# define XCHAL_INT20_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 21 +# define XCHAL_INT21_LEVEL 0 +# define XCHAL_INT21_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 22 +# define XCHAL_INT22_LEVEL 0 +# define XCHAL_INT22_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 23 +# define XCHAL_INT23_LEVEL 0 +# define XCHAL_INT23_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 24 +# define XCHAL_INT24_LEVEL 0 +# define XCHAL_INT24_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 25 +# define XCHAL_INT25_LEVEL 0 +# define XCHAL_INT25_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 26 +# define XCHAL_INT26_LEVEL 0 +# define XCHAL_INT26_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 27 +# define XCHAL_INT27_LEVEL 0 +# define XCHAL_INT27_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 28 +# define XCHAL_INT28_LEVEL 0 +# define XCHAL_INT28_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 29 +# define XCHAL_INT29_LEVEL 0 +# define XCHAL_INT29_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 30 +# define XCHAL_INT30_LEVEL 0 +# define XCHAL_INT30_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 31 +# define XCHAL_INT31_LEVEL 0 +# define XCHAL_INT31_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif + + +/* + * Masks and levels corresponding to each *external* interrupt. + */ + +#define XCHAL_EXTINT0_MASK (1 << XCHAL_EXTINT0_NUM) +#define XCHAL_EXTINT0_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT0_NUM) +#define XCHAL_EXTINT1_MASK (1 << XCHAL_EXTINT1_NUM) +#define XCHAL_EXTINT1_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT1_NUM) +#define XCHAL_EXTINT2_MASK (1 << XCHAL_EXTINT2_NUM) +#define XCHAL_EXTINT2_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT2_NUM) +#define XCHAL_EXTINT3_MASK (1 << XCHAL_EXTINT3_NUM) +#define XCHAL_EXTINT3_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT3_NUM) +#define XCHAL_EXTINT4_MASK (1 << XCHAL_EXTINT4_NUM) +#define XCHAL_EXTINT4_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT4_NUM) +#define XCHAL_EXTINT5_MASK (1 << XCHAL_EXTINT5_NUM) +#define XCHAL_EXTINT5_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT5_NUM) +#define XCHAL_EXTINT6_MASK (1 << XCHAL_EXTINT6_NUM) +#define XCHAL_EXTINT6_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT6_NUM) +#define XCHAL_EXTINT7_MASK (1 << XCHAL_EXTINT7_NUM) +#define XCHAL_EXTINT7_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT7_NUM) +#define XCHAL_EXTINT8_MASK (1 << XCHAL_EXTINT8_NUM) +#define XCHAL_EXTINT8_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT8_NUM) +#define XCHAL_EXTINT9_MASK (1 << XCHAL_EXTINT9_NUM) +#define XCHAL_EXTINT9_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT9_NUM) +#define XCHAL_EXTINT10_MASK (1 << XCHAL_EXTINT10_NUM) +#define XCHAL_EXTINT10_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT10_NUM) +#define XCHAL_EXTINT11_MASK (1 << XCHAL_EXTINT11_NUM) +#define XCHAL_EXTINT11_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT11_NUM) +#define XCHAL_EXTINT12_MASK (1 << XCHAL_EXTINT12_NUM) +#define XCHAL_EXTINT12_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT12_NUM) +#define XCHAL_EXTINT13_MASK (1 << XCHAL_EXTINT13_NUM) +#define XCHAL_EXTINT13_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT13_NUM) +#define XCHAL_EXTINT14_MASK (1 << XCHAL_EXTINT14_NUM) +#define XCHAL_EXTINT14_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT14_NUM) +#define XCHAL_EXTINT15_MASK (1 << XCHAL_EXTINT15_NUM) +#define XCHAL_EXTINT15_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT15_NUM) +#define XCHAL_EXTINT16_MASK (1 << XCHAL_EXTINT16_NUM) +#define XCHAL_EXTINT16_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT16_NUM) +#define XCHAL_EXTINT17_MASK (1 << XCHAL_EXTINT17_NUM) +#define XCHAL_EXTINT17_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT17_NUM) +#define XCHAL_EXTINT18_MASK (1 << XCHAL_EXTINT18_NUM) +#define XCHAL_EXTINT18_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT18_NUM) +#define XCHAL_EXTINT19_MASK (1 << XCHAL_EXTINT19_NUM) +#define XCHAL_EXTINT19_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT19_NUM) +#define XCHAL_EXTINT20_MASK (1 << XCHAL_EXTINT20_NUM) +#define XCHAL_EXTINT20_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT20_NUM) +#define XCHAL_EXTINT21_MASK (1 << XCHAL_EXTINT21_NUM) +#define XCHAL_EXTINT21_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT21_NUM) +#define XCHAL_EXTINT22_MASK (1 << XCHAL_EXTINT22_NUM) +#define XCHAL_EXTINT22_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT22_NUM) +#define XCHAL_EXTINT23_MASK (1 << XCHAL_EXTINT23_NUM) +#define XCHAL_EXTINT23_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT23_NUM) +#define XCHAL_EXTINT24_MASK (1 << XCHAL_EXTINT24_NUM) +#define XCHAL_EXTINT24_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT24_NUM) +#define XCHAL_EXTINT25_MASK (1 << XCHAL_EXTINT25_NUM) +#define XCHAL_EXTINT25_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT25_NUM) +#define XCHAL_EXTINT26_MASK (1 << XCHAL_EXTINT26_NUM) +#define XCHAL_EXTINT26_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT26_NUM) +#define XCHAL_EXTINT27_MASK (1 << XCHAL_EXTINT27_NUM) +#define XCHAL_EXTINT27_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT27_NUM) +#define XCHAL_EXTINT28_MASK (1 << XCHAL_EXTINT28_NUM) +#define XCHAL_EXTINT28_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT28_NUM) +#define XCHAL_EXTINT29_MASK (1 << XCHAL_EXTINT29_NUM) +#define XCHAL_EXTINT29_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT29_NUM) +#define XCHAL_EXTINT30_MASK (1 << XCHAL_EXTINT30_NUM) +#define XCHAL_EXTINT30_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT30_NUM) +#define XCHAL_EXTINT31_MASK (1 << XCHAL_EXTINT31_NUM) +#define XCHAL_EXTINT31_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT31_NUM) + + +/*---------------------------------------------------------------------- + EXCEPTIONS and VECTORS + ----------------------------------------------------------------------*/ + +/* For backward compatibility ONLY -- DO NOT USE (will be removed in future release): */ +#define XCHAL_HAVE_OLD_EXC_ARCH XCHAL_HAVE_XEA1 /* (DEPRECATED) 1 if old exception architecture (XEA1), 0 otherwise (eg. XEA2) */ +#define XCHAL_HAVE_EXCM XCHAL_HAVE_XEA2 /* (DEPRECATED) 1 if PS.EXCM bit exists (currently equals XCHAL_HAVE_TLBS) */ +#ifdef XCHAL_USER_VECTOR_VADDR +#define XCHAL_PROGRAMEXC_VECTOR_VADDR XCHAL_USER_VECTOR_VADDR +#define XCHAL_USEREXC_VECTOR_VADDR XCHAL_USER_VECTOR_VADDR +#endif +#ifdef XCHAL_USER_VECTOR_PADDR +# define XCHAL_PROGRAMEXC_VECTOR_PADDR XCHAL_USER_VECTOR_PADDR +# define XCHAL_USEREXC_VECTOR_PADDR XCHAL_USER_VECTOR_PADDR +#endif +#ifdef XCHAL_KERNEL_VECTOR_VADDR +# define XCHAL_STACKEDEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR +# define XCHAL_KERNELEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR +#endif +#ifdef XCHAL_KERNEL_VECTOR_PADDR +# define XCHAL_STACKEDEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR +# define XCHAL_KERNELEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR +#endif + +#if 0 +#if XCHAL_HAVE_DEBUG +# define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL_VECTOR_VADDR(XCHAL_DEBUGLEVEL) +/* This one should only get defined if the corresponding intlevel paddr macro exists: */ +# define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL_VECTOR_PADDR(XCHAL_DEBUGLEVEL) +#endif +#endif + +/* Indexing macros: */ +#define _XCHAL_INTLEVEL_VECTOR_VADDR(n) XCHAL_INTLEVEL ## n ## _VECTOR_VADDR +#define XCHAL_INTLEVEL_VECTOR_VADDR(n) _XCHAL_INTLEVEL_VECTOR_VADDR(n) /* n = 0 .. 15 */ + +/* + * General Exception Causes + * (values of EXCCAUSE special register set by general exceptions, + * which vector to the user, kernel, or double-exception vectors). + * + * DEPRECATED. Please use the equivalent EXCCAUSE_xxx macros + * defined in . (Note that these have slightly + * different names, they don't just have the XCHAL_ prefix removed.) + */ +#define XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION 0 /* Illegal Instruction */ +#define XCHAL_EXCCAUSE_SYSTEM_CALL 1 /* System Call */ +#define XCHAL_EXCCAUSE_INSTRUCTION_FETCH_ERROR 2 /* Instruction Fetch Error */ +#define XCHAL_EXCCAUSE_LOAD_STORE_ERROR 3 /* Load Store Error */ +#define XCHAL_EXCCAUSE_LEVEL1_INTERRUPT 4 /* Level 1 Interrupt */ +#define XCHAL_EXCCAUSE_ALLOCA 5 /* Stack Extension Assist */ +#define XCHAL_EXCCAUSE_INTEGER_DIVIDE_BY_ZERO 6 /* Integer Divide by Zero */ +#define XCHAL_EXCCAUSE_SPECULATION 7 /* Speculation */ +#define XCHAL_EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction */ +#define XCHAL_EXCCAUSE_UNALIGNED 9 /* Unaligned Load Store */ +/*10..15 reserved*/ +#define XCHAL_EXCCAUSE_ITLB_MISS 16 /* ITlb Miss Exception */ +#define XCHAL_EXCCAUSE_ITLB_MULTIHIT 17 /* ITlb Mutltihit Exception */ +#define XCHAL_EXCCAUSE_ITLB_PRIVILEGE 18 /* ITlb Privilege Exception */ +#define XCHAL_EXCCAUSE_ITLB_SIZE_RESTRICTION 19 /* ITlb Size Restriction Exception */ +#define XCHAL_EXCCAUSE_FETCH_CACHE_ATTRIBUTE 20 /* Fetch Cache Attribute Exception */ +/*21..23 reserved*/ +#define XCHAL_EXCCAUSE_DTLB_MISS 24 /* DTlb Miss Exception */ +#define XCHAL_EXCCAUSE_DTLB_MULTIHIT 25 /* DTlb Multihit Exception */ +#define XCHAL_EXCCAUSE_DTLB_PRIVILEGE 26 /* DTlb Privilege Exception */ +#define XCHAL_EXCCAUSE_DTLB_SIZE_RESTRICTION 27 /* DTlb Size Restriction Exception */ +#define XCHAL_EXCCAUSE_LOAD_CACHE_ATTRIBUTE 28 /* Load Cache Attribute Exception */ +#define XCHAL_EXCCAUSE_STORE_CACHE_ATTRIBUTE 29 /* Store Cache Attribute Exception */ +/*30..31 reserved*/ +#define XCHAL_EXCCAUSE_COPROCESSOR0_DISABLED 32 /* Coprocessor 0 disabled */ +#define XCHAL_EXCCAUSE_COPROCESSOR1_DISABLED 33 /* Coprocessor 1 disabled */ +#define XCHAL_EXCCAUSE_COPROCESSOR2_DISABLED 34 /* Coprocessor 2 disabled */ +#define XCHAL_EXCCAUSE_COPROCESSOR3_DISABLED 35 /* Coprocessor 3 disabled */ +#define XCHAL_EXCCAUSE_COPROCESSOR4_DISABLED 36 /* Coprocessor 4 disabled */ +#define XCHAL_EXCCAUSE_COPROCESSOR5_DISABLED 37 /* Coprocessor 5 disabled */ +#define XCHAL_EXCCAUSE_COPROCESSOR6_DISABLED 38 /* Coprocessor 6 disabled */ +#define XCHAL_EXCCAUSE_COPROCESSOR7_DISABLED 39 /* Coprocessor 7 disabled */ +/*40..63 reserved*/ + + +/* + * Miscellaneous special register fields. + * + * For each special register, and each field within each register: + * XCHAL__VALIDMASK is the set of bits defined in the register. + * XCHAL___BITS is the number of bits in the field. + * XCHAL___NUM is 2^bits, the number of possible values + * of the field. + * XCHAL___SHIFT is the position of the field within + * the register, starting from the least significant bit. + * + * DEPRECATED. Please use the equivalent macros defined in + * . (Note that these have different names.) + */ + +/* DBREAKC (special register number 160): */ +#define XCHAL_DBREAKC_VALIDMASK 0xC000003F +#define XCHAL_DBREAKC_MASK_BITS 6 +#define XCHAL_DBREAKC_MASK_NUM 64 +#define XCHAL_DBREAKC_MASK_SHIFT 0 +#define XCHAL_DBREAKC_MASK_MASK 0x0000003F +#define XCHAL_DBREAKC_LOADBREAK_BITS 1 +#define XCHAL_DBREAKC_LOADBREAK_NUM 2 +#define XCHAL_DBREAKC_LOADBREAK_SHIFT 30 +#define XCHAL_DBREAKC_LOADBREAK_MASK 0x40000000 +#define XCHAL_DBREAKC_STOREBREAK_BITS 1 +#define XCHAL_DBREAKC_STOREBREAK_NUM 2 +#define XCHAL_DBREAKC_STOREBREAK_SHIFT 31 +#define XCHAL_DBREAKC_STOREBREAK_MASK 0x80000000 +/* PS (special register number 230): */ +#define XCHAL_PS_VALIDMASK 0x00070F3F +#define XCHAL_PS_INTLEVEL_BITS 4 +#define XCHAL_PS_INTLEVEL_NUM 16 +#define XCHAL_PS_INTLEVEL_SHIFT 0 +#define XCHAL_PS_INTLEVEL_MASK 0x0000000F +#define XCHAL_PS_EXCM_BITS 1 +#define XCHAL_PS_EXCM_NUM 2 +#define XCHAL_PS_EXCM_SHIFT 4 +#define XCHAL_PS_EXCM_MASK 0x00000010 +#define XCHAL_PS_UM_BITS 1 +#define XCHAL_PS_UM_NUM 2 +#define XCHAL_PS_UM_SHIFT 5 +#define XCHAL_PS_UM_MASK 0x00000020 +#define XCHAL_PS_RING_BITS 2 +#define XCHAL_PS_RING_NUM 4 +#define XCHAL_PS_RING_SHIFT 6 +#define XCHAL_PS_RING_MASK 0x000000C0 +#define XCHAL_PS_OWB_BITS 4 +#define XCHAL_PS_OWB_NUM 16 +#define XCHAL_PS_OWB_SHIFT 8 +#define XCHAL_PS_OWB_MASK 0x00000F00 +#define XCHAL_PS_CALLINC_BITS 2 +#define XCHAL_PS_CALLINC_NUM 4 +#define XCHAL_PS_CALLINC_SHIFT 16 +#define XCHAL_PS_CALLINC_MASK 0x00030000 +#define XCHAL_PS_WOE_BITS 1 +#define XCHAL_PS_WOE_NUM 2 +#define XCHAL_PS_WOE_SHIFT 18 +#define XCHAL_PS_WOE_MASK 0x00040000 +/* EXCCAUSE (special register number 232): */ +#define XCHAL_EXCCAUSE_VALIDMASK 0x0000003F +#define XCHAL_EXCCAUSE_BITS 6 +#define XCHAL_EXCCAUSE_NUM 64 +#define XCHAL_EXCCAUSE_SHIFT 0 +#define XCHAL_EXCCAUSE_MASK 0x0000003F +/* DEBUGCAUSE (special register number 233): */ +#define XCHAL_DEBUGCAUSE_VALIDMASK 0x0000003F +#define XCHAL_DEBUGCAUSE_ICOUNT_BITS 1 +#define XCHAL_DEBUGCAUSE_ICOUNT_NUM 2 +#define XCHAL_DEBUGCAUSE_ICOUNT_SHIFT 0 +#define XCHAL_DEBUGCAUSE_ICOUNT_MASK 0x00000001 +#define XCHAL_DEBUGCAUSE_IBREAK_BITS 1 +#define XCHAL_DEBUGCAUSE_IBREAK_NUM 2 +#define XCHAL_DEBUGCAUSE_IBREAK_SHIFT 1 +#define XCHAL_DEBUGCAUSE_IBREAK_MASK 0x00000002 +#define XCHAL_DEBUGCAUSE_DBREAK_BITS 1 +#define XCHAL_DEBUGCAUSE_DBREAK_NUM 2 +#define XCHAL_DEBUGCAUSE_DBREAK_SHIFT 2 +#define XCHAL_DEBUGCAUSE_DBREAK_MASK 0x00000004 +#define XCHAL_DEBUGCAUSE_BREAK_BITS 1 +#define XCHAL_DEBUGCAUSE_BREAK_NUM 2 +#define XCHAL_DEBUGCAUSE_BREAK_SHIFT 3 +#define XCHAL_DEBUGCAUSE_BREAK_MASK 0x00000008 +#define XCHAL_DEBUGCAUSE_BREAKN_BITS 1 +#define XCHAL_DEBUGCAUSE_BREAKN_NUM 2 +#define XCHAL_DEBUGCAUSE_BREAKN_SHIFT 4 +#define XCHAL_DEBUGCAUSE_BREAKN_MASK 0x00000010 +#define XCHAL_DEBUGCAUSE_DEBUGINT_BITS 1 +#define XCHAL_DEBUGCAUSE_DEBUGINT_NUM 2 +#define XCHAL_DEBUGCAUSE_DEBUGINT_SHIFT 5 +#define XCHAL_DEBUGCAUSE_DEBUGINT_MASK 0x00000020 + + + + +/*---------------------------------------------------------------------- + TIMERS + ----------------------------------------------------------------------*/ + +/*#define XCHAL_HAVE_TIMERS XCHAL_HAVE_CCOUNT*/ + + + +/*---------------------------------------------------------------------- + INTERNAL I/D RAM/ROMs and XLMI + ----------------------------------------------------------------------*/ + +#define XCHAL_NUM_IROM XCHAL_NUM_INSTROM /* (DEPRECATED) */ +#define XCHAL_NUM_IRAM XCHAL_NUM_INSTRAM /* (DEPRECATED) */ +#define XCHAL_NUM_DROM XCHAL_NUM_DATAROM /* (DEPRECATED) */ +#define XCHAL_NUM_DRAM XCHAL_NUM_DATARAM /* (DEPRECATED) */ + +#define XCHAL_IROM0_VADDR XCHAL_INSTROM0_VADDR /* (DEPRECATED) */ +#define XCHAL_IROM0_PADDR XCHAL_INSTROM0_PADDR /* (DEPRECATED) */ +#define XCHAL_IROM0_SIZE XCHAL_INSTROM0_SIZE /* (DEPRECATED) */ +#define XCHAL_IROM1_VADDR XCHAL_INSTROM1_VADDR /* (DEPRECATED) */ +#define XCHAL_IROM1_PADDR XCHAL_INSTROM1_PADDR /* (DEPRECATED) */ +#define XCHAL_IROM1_SIZE XCHAL_INSTROM1_SIZE /* (DEPRECATED) */ +#define XCHAL_IRAM0_VADDR XCHAL_INSTRAM0_VADDR /* (DEPRECATED) */ +#define XCHAL_IRAM0_PADDR XCHAL_INSTRAM0_PADDR /* (DEPRECATED) */ +#define XCHAL_IRAM0_SIZE XCHAL_INSTRAM0_SIZE /* (DEPRECATED) */ +#define XCHAL_IRAM1_VADDR XCHAL_INSTRAM1_VADDR /* (DEPRECATED) */ +#define XCHAL_IRAM1_PADDR XCHAL_INSTRAM1_PADDR /* (DEPRECATED) */ +#define XCHAL_IRAM1_SIZE XCHAL_INSTRAM1_SIZE /* (DEPRECATED) */ +#define XCHAL_DROM0_VADDR XCHAL_DATAROM0_VADDR /* (DEPRECATED) */ +#define XCHAL_DROM0_PADDR XCHAL_DATAROM0_PADDR /* (DEPRECATED) */ +#define XCHAL_DROM0_SIZE XCHAL_DATAROM0_SIZE /* (DEPRECATED) */ +#define XCHAL_DROM1_VADDR XCHAL_DATAROM1_VADDR /* (DEPRECATED) */ +#define XCHAL_DROM1_PADDR XCHAL_DATAROM1_PADDR /* (DEPRECATED) */ +#define XCHAL_DROM1_SIZE XCHAL_DATAROM1_SIZE /* (DEPRECATED) */ +#define XCHAL_DRAM0_VADDR XCHAL_DATARAM0_VADDR /* (DEPRECATED) */ +#define XCHAL_DRAM0_PADDR XCHAL_DATARAM0_PADDR /* (DEPRECATED) */ +#define XCHAL_DRAM0_SIZE XCHAL_DATARAM0_SIZE /* (DEPRECATED) */ +#define XCHAL_DRAM1_VADDR XCHAL_DATARAM1_VADDR /* (DEPRECATED) */ +#define XCHAL_DRAM1_PADDR XCHAL_DATARAM1_PADDR /* (DEPRECATED) */ +#define XCHAL_DRAM1_SIZE XCHAL_DATARAM1_SIZE /* (DEPRECATED) */ + + + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + + +/* Default PREFCTL value to enable prefetch. */ +#if XCHAL_HW_MIN_VERSION < XTENSA_HWVERSION_RE_2012_0 +#define XCHAL_CACHE_PREFCTL_DEFAULT 0x00044 /* enabled, not aggressive */ +#elif XCHAL_HW_MIN_VERSION < XTENSA_HWVERSION_RF_2014_0 +#define XCHAL_CACHE_PREFCTL_DEFAULT 0x01044 /* + enable prefetch to L1 */ +#elif XCHAL_PREFETCH_ENTRIES >= 16 +#define XCHAL_CACHE_PREFCTL_DEFAULT 0x81044 /* 12 entries for block ops */ +#elif XCHAL_PREFETCH_ENTRIES >= 8 +#define XCHAL_CACHE_PREFCTL_DEFAULT 0x51044 /* 5 entries for block ops */ +#else +#define XCHAL_CACHE_PREFCTL_DEFAULT 0x01044 /* 0 entries for block ops */ +#endif + + +/* Max for both I-cache and D-cache (used for general alignment): */ +#if XCHAL_ICACHE_LINESIZE > XCHAL_DCACHE_LINESIZE +# define XCHAL_CACHE_LINEWIDTH_MAX XCHAL_ICACHE_LINEWIDTH +# define XCHAL_CACHE_LINESIZE_MAX XCHAL_ICACHE_LINESIZE +#else +# define XCHAL_CACHE_LINEWIDTH_MAX XCHAL_DCACHE_LINEWIDTH +# define XCHAL_CACHE_LINESIZE_MAX XCHAL_DCACHE_LINESIZE +#endif + +#define XCHAL_ICACHE_SETSIZE (1< XCHAL_DCACHE_SETWIDTH +# define XCHAL_CACHE_SETWIDTH_MAX XCHAL_ICACHE_SETWIDTH +# define XCHAL_CACHE_SETSIZE_MAX XCHAL_ICACHE_SETSIZE +#else +# define XCHAL_CACHE_SETWIDTH_MAX XCHAL_DCACHE_SETWIDTH +# define XCHAL_CACHE_SETSIZE_MAX XCHAL_DCACHE_SETSIZE +#endif + +/* Instruction cache tag bits: */ +#define XCHAL_ICACHE_TAG_V_SHIFT 0 +#define XCHAL_ICACHE_TAG_V 0x1 /* valid bit */ +#if XCHAL_ICACHE_WAYS > 1 +# define XCHAL_ICACHE_TAG_F_SHIFT 1 +# define XCHAL_ICACHE_TAG_F 0x2 /* fill (LRU) bit */ +#else +# define XCHAL_ICACHE_TAG_F_SHIFT 0 +# define XCHAL_ICACHE_TAG_F 0 /* no fill (LRU) bit */ +#endif +#if XCHAL_ICACHE_LINE_LOCKABLE +# define XCHAL_ICACHE_TAG_L_SHIFT (XCHAL_ICACHE_TAG_F_SHIFT+1) +# define XCHAL_ICACHE_TAG_L (1 << XCHAL_ICACHE_TAG_L_SHIFT) /* lock bit */ +#else +# define XCHAL_ICACHE_TAG_L_SHIFT XCHAL_ICACHE_TAG_F_SHIFT +# define XCHAL_ICACHE_TAG_L 0 /* no lock bit */ +#endif +/* Data cache tag bits: */ +#define XCHAL_DCACHE_TAG_V_SHIFT 0 +#define XCHAL_DCACHE_TAG_V 0x1 /* valid bit */ +#if XCHAL_DCACHE_WAYS > 1 +# define XCHAL_DCACHE_TAG_F_SHIFT 1 +# define XCHAL_DCACHE_TAG_F 0x2 /* fill (LRU) bit */ +#else +# define XCHAL_DCACHE_TAG_F_SHIFT 0 +# define XCHAL_DCACHE_TAG_F 0 /* no fill (LRU) bit */ +#endif +#if XCHAL_DCACHE_IS_WRITEBACK +# define XCHAL_DCACHE_TAG_D_SHIFT (XCHAL_DCACHE_TAG_F_SHIFT+1) +# define XCHAL_DCACHE_TAG_D (1 << XCHAL_DCACHE_TAG_D_SHIFT) /* dirty bit */ +#else +# define XCHAL_DCACHE_TAG_D_SHIFT XCHAL_DCACHE_TAG_F_SHIFT +# define XCHAL_DCACHE_TAG_D 0 /* no dirty bit */ +#endif +#if XCHAL_DCACHE_LINE_LOCKABLE +# define XCHAL_DCACHE_TAG_L_SHIFT (XCHAL_DCACHE_TAG_D_SHIFT+1) +# define XCHAL_DCACHE_TAG_L (1 << XCHAL_DCACHE_TAG_L_SHIFT) /* lock bit */ +#else +# define XCHAL_DCACHE_TAG_L_SHIFT XCHAL_DCACHE_TAG_D_SHIFT +# define XCHAL_DCACHE_TAG_L 0 /* no lock bit */ +#endif + +/* Whether MEMCTL register has anything useful */ +#define XCHAL_USE_MEMCTL (((XCHAL_LOOP_BUFFER_SIZE > 0) || \ + XCHAL_DCACHE_IS_COHERENT || \ + XCHAL_HAVE_ICACHE_DYN_WAYS || \ + XCHAL_HAVE_DCACHE_DYN_WAYS) && \ + (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0)) + +/* Default MEMCTL values: */ +#if XCHAL_HAVE_ICACHE_DYN_WAYS || XCHAL_HAVE_DCACHE_DYN_WAYS +/* NOTE: constant defined this way to allow movi instead of l32r in reset code. */ +#define XCHAL_CACHE_MEMCTL_DEFAULT 0xFFFFFF00 /* Init all possible ways */ +#else +#define XCHAL_CACHE_MEMCTL_DEFAULT 0x00000000 /* Nothing to do */ +#endif + +#if XCHAL_DCACHE_IS_COHERENT +#define _MEMCTL_SNOOP_EN 0x02 /* Enable snoop */ +#else +#define _MEMCTL_SNOOP_EN 0x00 /* Don't enable snoop */ +#endif + +#if (XCHAL_LOOP_BUFFER_SIZE == 0) || XCHAL_ERRATUM_453 +#define _MEMCTL_L0IBUF_EN 0x00 /* No loop buffer or don't enable */ +#else +#define _MEMCTL_L0IBUF_EN 0x01 /* Enable loop buffer */ +#endif + +#define XCHAL_SNOOP_LB_MEMCTL_DEFAULT (_MEMCTL_SNOOP_EN | _MEMCTL_L0IBUF_EN) + + +/*---------------------------------------------------------------------- + MMU + ----------------------------------------------------------------------*/ + +/* See for more details. */ + +/* Has different semantic in open source headers (where it means HAVE_PTP_MMU), + so comment out starting with RB-2008.3 release; later, might get + get reintroduced as a synonym for XCHAL_HAVE_PTP_MMU instead: */ +/*#define XCHAL_HAVE_MMU XCHAL_HAVE_TLBS*/ /* (DEPRECATED; use XCHAL_HAVE_TLBS instead) */ + +/* Indexing macros: */ +#define _XCHAL_ITLB_SET(n,_what) XCHAL_ITLB_SET ## n ## _what +#define XCHAL_ITLB_SET(n,what) _XCHAL_ITLB_SET(n, _ ## what ) +#define _XCHAL_ITLB_SET_E(n,i,_what) XCHAL_ITLB_SET ## n ## _E ## i ## _what +#define XCHAL_ITLB_SET_E(n,i,what) _XCHAL_ITLB_SET_E(n,i, _ ## what ) +#define _XCHAL_DTLB_SET(n,_what) XCHAL_DTLB_SET ## n ## _what +#define XCHAL_DTLB_SET(n,what) _XCHAL_DTLB_SET(n, _ ## what ) +#define _XCHAL_DTLB_SET_E(n,i,_what) XCHAL_DTLB_SET ## n ## _E ## i ## _what +#define XCHAL_DTLB_SET_E(n,i,what) _XCHAL_DTLB_SET_E(n,i, _ ## what ) +/* + * Example use: XCHAL_ITLB_SET(XCHAL_ITLB_ARF_SET0,ENTRIES) + * to get the value of XCHAL_ITLB_SET_ENTRIES where is the first auto-refill set. + */ + +/* Number of entries per autorefill way: */ +#define XCHAL_ITLB_ARF_ENTRIES (1< 0 && XCHAL_DTLB_ARF_WAYS > 0 && XCHAL_MMU_RINGS >= 2 +# define XCHAL_HAVE_PTP_MMU 1 /* have full MMU (with page table [autorefill] and protection) */ +#else +# define XCHAL_HAVE_PTP_MMU 0 /* don't have full MMU */ +#endif +#endif + +/* + * For full MMUs, report kernel RAM segment and kernel I/O segment static page mappings: + */ +#if XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY +#define XCHAL_KSEG_CACHED_VADDR 0xD0000000 /* virt.addr of kernel RAM cached static map */ +#define XCHAL_KSEG_CACHED_PADDR 0x00000000 /* phys.addr of kseg_cached */ +#define XCHAL_KSEG_CACHED_SIZE 0x08000000 /* size in bytes of kseg_cached (assumed power of 2!!!) */ +#define XCHAL_KSEG_BYPASS_VADDR 0xD8000000 /* virt.addr of kernel RAM bypass (uncached) static map */ +#define XCHAL_KSEG_BYPASS_PADDR 0x00000000 /* phys.addr of kseg_bypass */ +#define XCHAL_KSEG_BYPASS_SIZE 0x08000000 /* size in bytes of kseg_bypass (assumed power of 2!!!) */ + +#define XCHAL_KIO_CACHED_VADDR 0xE0000000 /* virt.addr of kernel I/O cached static map */ +#define XCHAL_KIO_CACHED_PADDR 0xF0000000 /* phys.addr of kio_cached */ +#define XCHAL_KIO_CACHED_SIZE 0x10000000 /* size in bytes of kio_cached (assumed power of 2!!!) */ +#define XCHAL_KIO_BYPASS_VADDR 0xF0000000 /* virt.addr of kernel I/O bypass (uncached) static map */ +#define XCHAL_KIO_BYPASS_PADDR 0xF0000000 /* phys.addr of kio_bypass */ +#define XCHAL_KIO_BYPASS_SIZE 0x10000000 /* size in bytes of kio_bypass (assumed power of 2!!!) */ + +#define XCHAL_SEG_MAPPABLE_VADDR 0x00000000 /* start of largest non-static-mapped virtual addr area */ +#define XCHAL_SEG_MAPPABLE_SIZE 0xD0000000 /* size in bytes of " */ +/* define XCHAL_SEG_MAPPABLE2_xxx if more areas present, sorted in order of descending size. */ +#endif + + +/*---------------------------------------------------------------------- + MISC + ----------------------------------------------------------------------*/ + +/* Data alignment required if used for instructions: */ +#if XCHAL_INST_FETCH_WIDTH > XCHAL_DATA_WIDTH +# define XCHAL_ALIGN_MAX XCHAL_INST_FETCH_WIDTH +#else +# define XCHAL_ALIGN_MAX XCHAL_DATA_WIDTH +#endif + +/* + * Names kept for backward compatibility. + * (Here "RELEASE" is now a misnomer; these are product *versions*, not the releases + * under which they are released. In the T10##.# era there was no distinction.) + */ +#define XCHAL_HW_RELEASE_MAJOR XCHAL_HW_VERSION_MAJOR +#define XCHAL_HW_RELEASE_MINOR XCHAL_HW_VERSION_MINOR +#define XCHAL_HW_RELEASE_NAME XCHAL_HW_VERSION_NAME + + + + +/*---------------------------------------------------------------------- + COPROCESSORS and EXTRA STATE + ----------------------------------------------------------------------*/ + +#define XCHAL_EXTRA_SA_SIZE XCHAL_NCP_SA_SIZE +#define XCHAL_EXTRA_SA_ALIGN XCHAL_NCP_SA_ALIGN +#define XCHAL_CPEXTRA_SA_SIZE XCHAL_TOTAL_SA_SIZE +#define XCHAL_CPEXTRA_SA_ALIGN XCHAL_TOTAL_SA_ALIGN + +#if defined (_ASMLANGUAGE) || defined (__ASSEMBLER__) + + /* Invoked at start of save area load/store sequence macro to setup macro + * internal offsets. Not usually invoked directly. + * continue 0 for 1st sequence, 1 for subsequent consecutive ones. + * totofs offset from original ptr to next load/store location. + */ + .macro xchal_sa_start continue totofs + .ifeq \continue + .set .Lxchal_pofs_, 0 /* offset from original ptr to current \ptr */ + .set .Lxchal_ofs_, 0 /* offset from current \ptr to next load/store location */ + .endif + .if \totofs + 1 /* if totofs specified (not -1) */ + .set .Lxchal_ofs_, \totofs - .Lxchal_pofs_ /* specific offset from original ptr */ + .endif + .endm + + /* Align portion of save area and bring ptr in range if necessary. + * Used by save area load/store sequences. Not usually invoked directly. + * Allows combining multiple (sub-)sequences arbitrarily. + * ptr pointer to save area (may be off, see .Lxchal_pofs_) + * minofs,maxofs range of offset from cur ptr to next load/store loc; + * minofs <= 0 <= maxofs (0 must always be valid offset) + * range must be within +/- 30kB or so. + * ofsalign alignment granularity of minofs .. maxofs (pow of 2) + * (restriction on offset from ptr to next load/store loc) + * totalign align from orig ptr to next load/store loc (pow of 2) + */ + .macro xchal_sa_align ptr minofs maxofs ofsalign totalign + /* First align where we start accessing the next register + * per \totalign relative to original ptr (i.e. start of the save area): + */ + .set .Lxchal_ofs_, ((.Lxchal_pofs_ + .Lxchal_ofs_ + \totalign - 1) & -\totalign) - .Lxchal_pofs_ + /* If necessary, adjust \ptr to bring .Lxchal_ofs_ in acceptable range: */ + .if (((\maxofs) - .Lxchal_ofs_) & 0xC0000000) | ((.Lxchal_ofs_ - (\minofs)) & 0xC0000000) | (.Lxchal_ofs_ & (\ofsalign-1)) + .set .Ligmask, 0xFFFFFFFF /* TODO: optimize to addmi, per aligns and .Lxchal_ofs_ */ + addi \ptr, \ptr, (.Lxchal_ofs_ & .Ligmask) + .set .Lxchal_pofs_, .Lxchal_pofs_ + (.Lxchal_ofs_ & .Ligmask) + .set .Lxchal_ofs_, (.Lxchal_ofs_ & ~.Ligmask) + .endif + .endm + /* + * We could optimize for addi to expand to only addmi instead of + * "addmi;addi", where possible. Here's a partial example how: + * .set .Lmaxmask, -(\ofsalign) & -(\totalign) + * .if (((\maxofs) + ~.Lmaxmask + 1) & 0xFFFFFF00) && ((.Lxchal_ofs_ & ~.Lmaxmask) == 0) + * .set .Ligmask, 0xFFFFFF00 + * .elif ... ditto for negative ofs range ... + * .set .Ligmask, 0xFFFFFF00 + * .set ... adjust per offset ... + * .else + * .set .Ligmask, 0xFFFFFFFF + * .endif + */ + + /* Invoke this after xchal_XXX_{load,store} macros to restore \ptr. */ + .macro xchal_sa_ptr_restore ptr + .if .Lxchal_pofs_ + addi \ptr, \ptr, - .Lxchal_pofs_ + .set .Lxchal_ofs_, .Lxchal_ofs_ + .Lxchal_pofs_ + .set .Lxchal_pofs_, 0 + .endif + .endm + + /* + * Use as eg: + * xchal_atmps_store a1, SOMEOFS, XCHAL_SA_NUM_ATMPS, a4, a5 + * xchal_ncp_load a2, a0,a3,a4,a5 + * xchal_atmps_load a1, SOMEOFS, XCHAL_SA_NUM_ATMPS, a4, a5 + * + * Specify only the ARs you *haven't* saved/restored already, up to 4. + * They *must* be the *last* ARs (in same order) specified to save area + * load/store sequences. In the example above, a0 and a3 were already + * saved/restored and unused (thus available) but a4 and a5 were not. + */ +#define xchal_atmps_store xchal_atmps_loadstore s32i, +#define xchal_atmps_load xchal_atmps_loadstore l32i, + .macro xchal_atmps_loadstore inst ptr offset nreq aa=0 ab=0 ac=0 ad=0 + .set .Lnsaved_, 0 + .irp reg,\aa,\ab,\ac,\ad + .ifeq 0x\reg ; .set .Lnsaved_,.Lnsaved_+1 ; .endif + .endr + .set .Laofs_, 0 + .irp reg,\aa,\ab,\ac,\ad + .ifgt (\nreq)-.Lnsaved_ + \inst \reg, \ptr, .Laofs_+\offset + .set .Laofs_,.Laofs_+4 + .set .Lnsaved_,.Lnsaved_+1 + .endif + .endr + .endm + +/*#define xchal_ncp_load_a2 xchal_ncp_load a2,a3,a4,a5,a6*/ +/*#define xchal_ncp_store_a2 xchal_ncp_store a2,a3,a4,a5,a6*/ +#define xchal_extratie_load xchal_ncptie_load +#define xchal_extratie_store xchal_ncptie_store +#define xchal_extratie_load_a2 xchal_ncptie_load a2,a3,a4,a5,a6 +#define xchal_extratie_store_a2 xchal_ncptie_store a2,a3,a4,a5,a6 +#define xchal_extra_load xchal_ncp_load +#define xchal_extra_store xchal_ncp_store +#define xchal_extra_load_a2 xchal_ncp_load a2,a3,a4,a5,a6 +#define xchal_extra_store_a2 xchal_ncp_store a2,a3,a4,a5,a6 +#define xchal_extra_load_funcbody xchal_ncp_load a2,a3,a4,a5,a6 +#define xchal_extra_store_funcbody xchal_ncp_store a2,a3,a4,a5,a6 +#define xchal_cp0_store_a2 xchal_cp0_store a2,a3,a4,a5,a6 +#define xchal_cp0_load_a2 xchal_cp0_load a2,a3,a4,a5,a6 +#define xchal_cp1_store_a2 xchal_cp1_store a2,a3,a4,a5,a6 +#define xchal_cp1_load_a2 xchal_cp1_load a2,a3,a4,a5,a6 +#define xchal_cp2_store_a2 xchal_cp2_store a2,a3,a4,a5,a6 +#define xchal_cp2_load_a2 xchal_cp2_load a2,a3,a4,a5,a6 +#define xchal_cp3_store_a2 xchal_cp3_store a2,a3,a4,a5,a6 +#define xchal_cp3_load_a2 xchal_cp3_load a2,a3,a4,a5,a6 +#define xchal_cp4_store_a2 xchal_cp4_store a2,a3,a4,a5,a6 +#define xchal_cp4_load_a2 xchal_cp4_load a2,a3,a4,a5,a6 +#define xchal_cp5_store_a2 xchal_cp5_store a2,a3,a4,a5,a6 +#define xchal_cp5_load_a2 xchal_cp5_load a2,a3,a4,a5,a6 +#define xchal_cp6_store_a2 xchal_cp6_store a2,a3,a4,a5,a6 +#define xchal_cp6_load_a2 xchal_cp6_load a2,a3,a4,a5,a6 +#define xchal_cp7_store_a2 xchal_cp7_store a2,a3,a4,a5,a6 +#define xchal_cp7_load_a2 xchal_cp7_load a2,a3,a4,a5,a6 + +/* Empty placeholder macros for undefined coprocessors: */ +#if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK) == 0 +# if XCHAL_CP0_SA_SIZE == 0 + .macro xchal_cp0_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp0_load p a b c d continue=0 ofs=-1 select=-1 ; .endm +# endif +# if XCHAL_CP1_SA_SIZE == 0 + .macro xchal_cp1_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp1_load p a b c d continue=0 ofs=-1 select=-1 ; .endm +# endif +# if XCHAL_CP2_SA_SIZE == 0 + .macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm +# endif +# if XCHAL_CP3_SA_SIZE == 0 + .macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm +# endif +# if XCHAL_CP4_SA_SIZE == 0 + .macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm +# endif +# if XCHAL_CP5_SA_SIZE == 0 + .macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm +# endif +# if XCHAL_CP6_SA_SIZE == 0 + .macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm +# endif +# if XCHAL_CP7_SA_SIZE == 0 + .macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm +# endif +#endif + + /******************** + * Macros to create functions that save and restore the state of *any* TIE + * coprocessor (by dynamic index). + */ + + /* + * Macro that expands to the body of a function + * that stores the selected coprocessor's state (registers etc). + * Entry: a2 = ptr to save area in which to save cp state + * a3 = coprocessor number + * Exit: any register a2-a15 (?) may have been clobbered. + */ + .macro xchal_cpi_store_funcbody +#if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK) +# if XCHAL_CP0_SA_SIZE + bnez a3, 99f + xchal_cp0_store_a2 + j 90f +99: +# endif +# if XCHAL_CP1_SA_SIZE + bnei a3, 1, 99f + xchal_cp1_store_a2 + j 90f +99: +# endif +# if XCHAL_CP2_SA_SIZE + bnei a3, 2, 99f + xchal_cp2_store_a2 + j 90f +99: +# endif +# if XCHAL_CP3_SA_SIZE + bnei a3, 3, 99f + xchal_cp3_store_a2 + j 90f +99: +# endif +# if XCHAL_CP4_SA_SIZE + bnei a3, 4, 99f + xchal_cp4_store_a2 + j 90f +99: +# endif +# if XCHAL_CP5_SA_SIZE + bnei a3, 5, 99f + xchal_cp5_store_a2 + j 90f +99: +# endif +# if XCHAL_CP6_SA_SIZE + bnei a3, 6, 99f + xchal_cp6_store_a2 + j 90f +99: +# endif +# if XCHAL_CP7_SA_SIZE + bnei a3, 7, 99f + xchal_cp7_store_a2 + j 90f +99: +# endif +90: +#endif + .endm + + /* + * Macro that expands to the body of a function + * that loads the selected coprocessor's state (registers etc). + * Entry: a2 = ptr to save area from which to restore cp state + * a3 = coprocessor number + * Exit: any register a2-a15 (?) may have been clobbered. + */ + .macro xchal_cpi_load_funcbody +#if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK) +# if XCHAL_CP0_SA_SIZE + bnez a3, 99f + xchal_cp0_load_a2 + j 90f +99: +# endif +# if XCHAL_CP1_SA_SIZE + bnei a3, 1, 99f + xchal_cp1_load_a2 + j 90f +99: +# endif +# if XCHAL_CP2_SA_SIZE + bnei a3, 2, 99f + xchal_cp2_load_a2 + j 90f +99: +# endif +# if XCHAL_CP3_SA_SIZE + bnei a3, 3, 99f + xchal_cp3_load_a2 + j 90f +99: +# endif +# if XCHAL_CP4_SA_SIZE + bnei a3, 4, 99f + xchal_cp4_load_a2 + j 90f +99: +# endif +# if XCHAL_CP5_SA_SIZE + bnei a3, 5, 99f + xchal_cp5_load_a2 + j 90f +99: +# endif +# if XCHAL_CP6_SA_SIZE + bnei a3, 6, 99f + xchal_cp6_load_a2 + j 90f +99: +# endif +# if XCHAL_CP7_SA_SIZE + bnei a3, 7, 99f + xchal_cp7_load_a2 + j 90f +99: +# endif +90: +#endif + .endm + +#endif /*_ASMLANGUAGE or __ASSEMBLER__*/ + + +/* Other default macros for undefined coprocessors: */ +#ifndef XCHAL_CP0_NAME +# define XCHAL_CP0_NAME 0 +# define XCHAL_CP0_SA_CONTENTS_LIBDB_NUM 0 +# define XCHAL_CP0_SA_CONTENTS_LIBDB /* empty */ +#endif +#ifndef XCHAL_CP1_NAME +# define XCHAL_CP1_NAME 0 +# define XCHAL_CP1_SA_CONTENTS_LIBDB_NUM 0 +# define XCHAL_CP1_SA_CONTENTS_LIBDB /* empty */ +#endif +#ifndef XCHAL_CP2_NAME +# define XCHAL_CP2_NAME 0 +# define XCHAL_CP2_SA_CONTENTS_LIBDB_NUM 0 +# define XCHAL_CP2_SA_CONTENTS_LIBDB /* empty */ +#endif +#ifndef XCHAL_CP3_NAME +# define XCHAL_CP3_NAME 0 +# define XCHAL_CP3_SA_CONTENTS_LIBDB_NUM 0 +# define XCHAL_CP3_SA_CONTENTS_LIBDB /* empty */ +#endif +#ifndef XCHAL_CP4_NAME +# define XCHAL_CP4_NAME 0 +# define XCHAL_CP4_SA_CONTENTS_LIBDB_NUM 0 +# define XCHAL_CP4_SA_CONTENTS_LIBDB /* empty */ +#endif +#ifndef XCHAL_CP5_NAME +# define XCHAL_CP5_NAME 0 +# define XCHAL_CP5_SA_CONTENTS_LIBDB_NUM 0 +# define XCHAL_CP5_SA_CONTENTS_LIBDB /* empty */ +#endif +#ifndef XCHAL_CP6_NAME +# define XCHAL_CP6_NAME 0 +# define XCHAL_CP6_SA_CONTENTS_LIBDB_NUM 0 +# define XCHAL_CP6_SA_CONTENTS_LIBDB /* empty */ +#endif +#ifndef XCHAL_CP7_NAME +# define XCHAL_CP7_NAME 0 +# define XCHAL_CP7_SA_CONTENTS_LIBDB_NUM 0 +# define XCHAL_CP7_SA_CONTENTS_LIBDB /* empty */ +#endif + +#if XCHAL_CP_MASK == 0 +/* Filler info for unassigned coprocessors, to simplify arrays etc: */ +#define XCHAL_CP0_SA_SIZE 0 +#define XCHAL_CP0_SA_ALIGN 1 +#define XCHAL_CP1_SA_SIZE 0 +#define XCHAL_CP1_SA_ALIGN 1 +#define XCHAL_CP2_SA_SIZE 0 +#define XCHAL_CP2_SA_ALIGN 1 +#define XCHAL_CP3_SA_SIZE 0 +#define XCHAL_CP3_SA_ALIGN 1 +#define XCHAL_CP4_SA_SIZE 0 +#define XCHAL_CP4_SA_ALIGN 1 +#define XCHAL_CP5_SA_SIZE 0 +#define XCHAL_CP5_SA_ALIGN 1 +#define XCHAL_CP6_SA_SIZE 0 +#define XCHAL_CP6_SA_ALIGN 1 +#define XCHAL_CP7_SA_SIZE 0 +#define XCHAL_CP7_SA_ALIGN 1 +#endif + + +/* Indexing macros: */ +#define _XCHAL_CP_SA_SIZE(n) XCHAL_CP ## n ## _SA_SIZE +#define XCHAL_CP_SA_SIZE(n) _XCHAL_CP_SA_SIZE(n) /* n = 0 .. 7 */ +#define _XCHAL_CP_SA_ALIGN(n) XCHAL_CP ## n ## _SA_ALIGN +#define XCHAL_CP_SA_ALIGN(n) _XCHAL_CP_SA_ALIGN(n) /* n = 0 .. 7 */ + +#define XCHAL_CPEXTRA_SA_SIZE_TOR2 XCHAL_CPEXTRA_SA_SIZE /* Tor2Beta only - do not use */ + +/* Link-time HAL global variables that report coprocessor numbers by name + (names are case-preserved from the original TIE): */ +#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__) +# define _XCJOIN(a,b) a ## b +# define XCJOIN(a,b) _XCJOIN(a,b) +# ifdef XCHAL_CP0_NAME +extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP0_IDENT); +extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP0_IDENT); +# endif +# ifdef XCHAL_CP1_NAME +extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP1_IDENT); +extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP1_IDENT); +# endif +# ifdef XCHAL_CP2_NAME +extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP2_IDENT); +extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP2_IDENT); +# endif +# ifdef XCHAL_CP3_NAME +extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP3_IDENT); +extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP3_IDENT); +# endif +# ifdef XCHAL_CP4_NAME +extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP4_IDENT); +extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP4_IDENT); +# endif +# ifdef XCHAL_CP5_NAME +extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP5_IDENT); +extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP5_IDENT); +# endif +# ifdef XCHAL_CP6_NAME +extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP6_IDENT); +extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP6_IDENT); +# endif +# ifdef XCHAL_CP7_NAME +extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP7_IDENT); +extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP7_IDENT); +# endif +#endif + + + + +/*---------------------------------------------------------------------- + DERIVED + ----------------------------------------------------------------------*/ + +#if XCHAL_HAVE_BE +#define XCHAL_INST_ILLN 0xD60F /* 2-byte illegal instruction, msb-first */ +#define XCHAL_INST_ILLN_BYTE0 0xD6 /* 2-byte illegal instruction, 1st byte */ +#define XCHAL_INST_ILLN_BYTE1 0x0F /* 2-byte illegal instruction, 2nd byte */ +#else +#define XCHAL_INST_ILLN 0xF06D /* 2-byte illegal instruction, lsb-first */ +#define XCHAL_INST_ILLN_BYTE0 0x6D /* 2-byte illegal instruction, 1st byte */ +#define XCHAL_INST_ILLN_BYTE1 0xF0 /* 2-byte illegal instruction, 2nd byte */ +#endif +/* Belongs in xtensa/hal.h: */ +#define XTHAL_INST_ILL 0x000000 /* 3-byte illegal instruction */ + + +/* + * Because information as to exactly which hardware version is targeted + * by a given software build is not always available, compile-time HAL + * Hardware-Release "_AT" macros are fuzzy (return 0, 1, or XCHAL_MAYBE): + * (Here "RELEASE" is now a misnomer; these are product *versions*, not the releases + * under which they are released. In the T10##.# era there was no distinction.) + */ +#if XCHAL_HW_CONFIGID_RELIABLE +# define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor) (XTHAL_REL_LE( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0) +# define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) (XTHAL_REL_GE( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0) +# define XCHAL_HW_RELEASE_AT(major,minor) (XTHAL_REL_EQ( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0) +# define XCHAL_HW_RELEASE_MAJOR_AT(major) ((XCHAL_HW_VERSION_MAJOR == (major)) ? 1 : 0) +#else +# define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor) ( ((major) < 1040 && XCHAL_HAVE_XEA2) ? 0 \ + : ((major) > 1050 && XCHAL_HAVE_XEA1) ? 1 \ + : XTHAL_MAYBE ) +# define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) ( ((major) >= 2000 && XCHAL_HAVE_XEA1) ? 0 \ + : (XTHAL_REL_LE(major,minor, 1040,0) && XCHAL_HAVE_XEA2) ? 1 \ + : XTHAL_MAYBE ) +# define XCHAL_HW_RELEASE_AT(major,minor) ( (((major) < 1040 && XCHAL_HAVE_XEA2) || \ + ((major) >= 2000 && XCHAL_HAVE_XEA1)) ? 0 : XTHAL_MAYBE) +# define XCHAL_HW_RELEASE_MAJOR_AT(major) XCHAL_HW_RELEASE_AT(major,0) +#endif + +/* + * Specific errata: + */ + +/* + * Erratum T1020.H13, T1030.H7, T1040.H10, T1050.H4 (fixed in T1040.3 and T1050.1; + * relevant only in XEA1, kernel-vector mode, level-one interrupts and overflows enabled): + */ +#define XCHAL_MAYHAVE_ERRATUM_XEA1KWIN (XCHAL_HAVE_XEA1 && \ + (XCHAL_HW_RELEASE_AT_OR_BELOW(1040,2) != 0 \ + || XCHAL_HW_RELEASE_AT(1050,0))) +/* + * Erratum 453 present in RE-2013.2 up to RF-2014.0, fixed in RF-2014.1. + * Applies to specific set of configuration options. + * Part of the workaround is to add ISYNC at certain points in the code. + * The workaround gated by this macro can be disabled if not needed, e.g. if + * zero-overhead loop buffer will be disabled, by defining _NO_ERRATUM_453. + */ +#if ( XCHAL_HW_MAX_VERSION >= XTENSA_HWVERSION_RE_2013_2 && \ + XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RF_2014_0 && \ + XCHAL_ICACHE_SIZE != 0 && XCHAL_HAVE_PIF /*covers also AXI/AHB*/ && \ + XCHAL_HAVE_LOOPS && XCHAL_LOOP_BUFFER_SIZE != 0 && \ + XCHAL_CLOCK_GATING_GLOBAL && !defined(_NO_ERRATUM_453) ) +#define XCHAL_ERRATUM_453 1 +#else +#define XCHAL_ERRATUM_453 0 +#endif + +/* + * Erratum 497 present in RE-2012.2 up to RG/RF-2015.2 + * Applies to specific set of configuration options. + * Workaround is to add MEMWs after at most 8 cache WB instructions + */ +#if ( ((XCHAL_HW_MAX_VERSION >= XTENSA_HWVERSION_RE_2012_0 && \ + XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RF_2015_2) || \ + (XCHAL_HW_MAX_VERSION >= XTENSA_HWVERSION_RG_2015_0 && \ + XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RG_2015_2) \ + ) && \ + XCHAL_DCACHE_IS_WRITEBACK && \ + XCHAL_HAVE_AXI && \ + XCHAL_HAVE_PIF_WR_RESP && \ + XCHAL_HAVE_PIF_REQ_ATTR && !defined(_NO_ERRATUM_497) \ + ) +#define XCHAL_ERRATUM_497 1 +#else +#define XCHAL_ERRATUM_497 0 +#endif + +#endif /*XTENSA_CONFIG_CORE_H*/ + diff --git a/tools/sdk/include/esp32/xtensa/config/defs.h b/tools/sdk/include/esp32/xtensa/config/defs.h new file mode 100644 index 00000000..d7c48ea8 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/config/defs.h @@ -0,0 +1,38 @@ +/* Definitions for Xtensa instructions, types, and protos. */ + +/* Customer ID=11657; Build=0x5fe96; Copyright (c) 2003-2004 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +/* NOTE: This file exists only for backward compatibility with T1050 + and earlier Xtensa releases. It includes only a subset of the + available header files. */ + +#ifndef _XTENSA_BASE_HEADER +#define _XTENSA_BASE_HEADER + +#ifdef __XTENSA__ + +#include +#include +#include + +#endif /* __XTENSA__ */ +#endif /* !_XTENSA_BASE_HEADER */ diff --git a/tools/sdk/include/esp32/xtensa/config/specreg.h b/tools/sdk/include/esp32/xtensa/config/specreg.h new file mode 100644 index 00000000..0135d4c7 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/config/specreg.h @@ -0,0 +1,117 @@ +/* + * Xtensa Special Register symbolic names + */ + +/* $Id: //depot/rel/Eaglenest/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */ + +/* Customer ID=11657; Build=0x5fe96; Copyright (c) 1998-2002 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef XTENSA_SPECREG_H +#define XTENSA_SPECREG_H + +/* Include these special register bitfield definitions, for historical reasons: */ +#include + + +/* Special registers: */ +#define LBEG 0 +#define LEND 1 +#define LCOUNT 2 +#define SAR 3 +#define BR 4 +#define SCOMPARE1 12 +#define ACCLO 16 +#define ACCHI 17 +#define MR_0 32 +#define MR_1 33 +#define MR_2 34 +#define MR_3 35 +#define WINDOWBASE 72 +#define WINDOWSTART 73 +#define IBREAKENABLE 96 +#define MEMCTL 97 +#define ATOMCTL 99 +#define DDR 104 +#define IBREAKA_0 128 +#define IBREAKA_1 129 +#define DBREAKA_0 144 +#define DBREAKA_1 145 +#define DBREAKC_0 160 +#define DBREAKC_1 161 +#define EPC_1 177 +#define EPC_2 178 +#define EPC_3 179 +#define EPC_4 180 +#define EPC_5 181 +#define EPC_6 182 +#define EPC_7 183 +#define DEPC 192 +#define EPS_2 194 +#define EPS_3 195 +#define EPS_4 196 +#define EPS_5 197 +#define EPS_6 198 +#define EPS_7 199 +#define EXCSAVE_1 209 +#define EXCSAVE_2 210 +#define EXCSAVE_3 211 +#define EXCSAVE_4 212 +#define EXCSAVE_5 213 +#define EXCSAVE_6 214 +#define EXCSAVE_7 215 +#define CPENABLE 224 +#define INTERRUPT 226 +#define INTENABLE 228 +#define PS 230 +#define VECBASE 231 +#define EXCCAUSE 232 +#define DEBUGCAUSE 233 +#define CCOUNT 234 +#define PRID 235 +#define ICOUNT 236 +#define ICOUNTLEVEL 237 +#define EXCVADDR 238 +#define CCOMPARE_0 240 +#define CCOMPARE_1 241 +#define CCOMPARE_2 242 +#define MISC_REG_0 244 +#define MISC_REG_1 245 +#define MISC_REG_2 246 +#define MISC_REG_3 247 + +/* Special cases (bases of special register series): */ +#define MR 32 +#define IBREAKA 128 +#define DBREAKA 144 +#define DBREAKC 160 +#define EPC 176 +#define EPS 192 +#define EXCSAVE 208 +#define CCOMPARE 240 + +/* Special names for read-only and write-only interrupt registers: */ +#define INTREAD 226 +#define INTSET 226 +#define INTCLEAR 227 + +#endif /* XTENSA_SPECREG_H */ + diff --git a/tools/sdk/include/esp32/xtensa/config/system.h b/tools/sdk/include/esp32/xtensa/config/system.h new file mode 100644 index 00000000..0d56eef7 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/config/system.h @@ -0,0 +1,274 @@ +/* + * xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration + * + * NOTE: The location and contents of this file are highly subject to change. + * + * Source for configuration-independent binaries (which link in a + * configuration-specific HAL library) must NEVER include this file. + * The HAL itself has historically included this file in some instances, + * but this is not appropriate either, because the HAL is meant to be + * core-specific but system independent. + */ + +/* Customer ID=11657; Build=0x5fe96; Copyright (c) 2000-2010 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + + +#ifndef XTENSA_CONFIG_SYSTEM_H +#define XTENSA_CONFIG_SYSTEM_H + +/*#include */ + + + +/*---------------------------------------------------------------------- + CONFIGURED SOFTWARE OPTIONS + ----------------------------------------------------------------------*/ + +#define XSHAL_USE_ABSOLUTE_LITERALS 0 /* (sw-only option, whether software uses absolute literals) */ +#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */ + +#define XSHAL_ABI XTHAL_ABI_WINDOWED /* (sw-only option, selected ABI) */ +/* The above maps to one of the following constants: */ +#define XTHAL_ABI_WINDOWED 0 +#define XTHAL_ABI_CALL0 1 +/* Alternatives: */ +/*#define XSHAL_WINDOWED_ABI 1*/ /* set if windowed ABI selected */ +/*#define XSHAL_CALL0_ABI 0*/ /* set if call0 ABI selected */ + +#define XSHAL_CLIB XTHAL_CLIB_NEWLIB /* (sw-only option, selected C library) */ +/* The above maps to one of the following constants: */ +#define XTHAL_CLIB_NEWLIB 0 +#define XTHAL_CLIB_UCLIBC 1 +#define XTHAL_CLIB_XCLIB 2 +/* Alternatives: */ +/*#define XSHAL_NEWLIB 1*/ /* set if newlib C library selected */ +/*#define XSHAL_UCLIBC 0*/ /* set if uCLibC C library selected */ +/*#define XSHAL_XCLIB 0*/ /* set if Xtensa C library selected */ + +#define XSHAL_USE_FLOATING_POINT 1 + +#define XSHAL_FLOATING_POINT_ABI 0 + +/* SW workarounds enabled for HW errata: */ + +/*---------------------------------------------------------------------- + DEVICE ADDRESSES + ----------------------------------------------------------------------*/ + +/* + * Strange place to find these, but the configuration GUI + * allows moving these around to account for various core + * configurations. Specific boards (and their BSP software) + * will have specific meanings for these components. + */ + +/* I/O Block areas: */ +#define XSHAL_IOBLOCK_CACHED_VADDR 0x70000000 +#define XSHAL_IOBLOCK_CACHED_PADDR 0x70000000 +#define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000 + +#define XSHAL_IOBLOCK_BYPASS_VADDR 0x90000000 +#define XSHAL_IOBLOCK_BYPASS_PADDR 0x90000000 +#define XSHAL_IOBLOCK_BYPASS_SIZE 0x0E000000 + +/* System ROM: */ +#define XSHAL_ROM_VADDR 0x50000000 +#define XSHAL_ROM_PADDR 0x50000000 +#define XSHAL_ROM_SIZE 0x01000000 +/* Largest available area (free of vectors): */ +#define XSHAL_ROM_AVAIL_VADDR 0x50000000 +#define XSHAL_ROM_AVAIL_VSIZE 0x01000000 + +/* System RAM: */ +#define XSHAL_RAM_VADDR 0x60000000 +#define XSHAL_RAM_PADDR 0x60000000 +#define XSHAL_RAM_VSIZE 0x20000000 +#define XSHAL_RAM_PSIZE 0x20000000 +#define XSHAL_RAM_SIZE XSHAL_RAM_PSIZE +/* Largest available area (free of vectors): */ +#define XSHAL_RAM_AVAIL_VADDR 0x60000000 +#define XSHAL_RAM_AVAIL_VSIZE 0x20000000 + +/* + * Shadow system RAM (same device as system RAM, at different address). + * (Emulation boards need this for the SONIC Ethernet driver + * when data caches are configured for writeback mode.) + * NOTE: on full MMU configs, this points to the BYPASS virtual address + * of system RAM, ie. is the same as XSHAL_RAM_* except that virtual + * addresses are viewed through the BYPASS static map rather than + * the CACHED static map. + */ +#define XSHAL_RAM_BYPASS_VADDR 0xA0000000 +#define XSHAL_RAM_BYPASS_PADDR 0xA0000000 +#define XSHAL_RAM_BYPASS_PSIZE 0x20000000 + +/* Alternate system RAM (different device than system RAM): */ +/*#define XSHAL_ALTRAM_[VP]ADDR ...not configured...*/ +/*#define XSHAL_ALTRAM_SIZE ...not configured...*/ + +/* Some available location in which to place devices in a simulation (eg. XTMP): */ +#define XSHAL_SIMIO_CACHED_VADDR 0xC0000000 +#define XSHAL_SIMIO_BYPASS_VADDR 0xC0000000 +#define XSHAL_SIMIO_PADDR 0xC0000000 +#define XSHAL_SIMIO_SIZE 0x20000000 + + +/*---------------------------------------------------------------------- + * For use by reference testbench exit and diagnostic routines. + */ +#define XSHAL_MAGIC_EXIT 0x0 + +/*---------------------------------------------------------------------- + * DEVICE-ADDRESS DEPENDENT... + * + * Values written to CACHEATTR special register (or its equivalent) + * to enable and disable caches in various modes. + *----------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------- + BACKWARD COMPATIBILITY ... + ----------------------------------------------------------------------*/ + +/* + * NOTE: the following two macros are DEPRECATED. Use the latter + * board-specific macros instead, which are specially tuned for the + * particular target environments' memory maps. + */ +#define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */ +#define XSHAL_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT /* default setting to enable caches (no writeback!) */ + +/*---------------------------------------------------------------------- + GENERIC + ----------------------------------------------------------------------*/ + +/* For the following, a 512MB region is used if it contains a system (PIF) RAM, + * system (PIF) ROM, local memory, or XLMI. */ + +/* These set any unused 512MB region to cache-BYPASS attribute: */ +#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK 0x22221112 /* enable caches in write-back mode */ +#define XSHAL_ALLVALID_CACHEATTR_WRITEALLOC 0x22221112 /* enable caches in write-allocate mode */ +#define XSHAL_ALLVALID_CACHEATTR_WRITETHRU 0x22221112 /* enable caches in write-through mode */ +#define XSHAL_ALLVALID_CACHEATTR_BYPASS 0x22222222 /* disable caches in bypass mode */ +#define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting to enable caches */ + +/* These set any unused 512MB region to ILLEGAL attribute: */ +#define XSHAL_STRICT_CACHEATTR_WRITEBACK 0xFFFF111F /* enable caches in write-back mode */ +#define XSHAL_STRICT_CACHEATTR_WRITEALLOC 0xFFFF111F /* enable caches in write-allocate mode */ +#define XSHAL_STRICT_CACHEATTR_WRITETHRU 0xFFFF111F /* enable caches in write-through mode */ +#define XSHAL_STRICT_CACHEATTR_BYPASS 0xFFFF222F /* disable caches in bypass mode */ +#define XSHAL_STRICT_CACHEATTR_DEFAULT XSHAL_STRICT_CACHEATTR_WRITEBACK /* default setting to enable caches */ + +/* These set the first 512MB, if unused, to ILLEGAL attribute to help catch + * NULL-pointer dereference bugs; all other unused 512MB regions are set + * to cache-BYPASS attribute: */ +#define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x2222111F /* enable caches in write-back mode */ +#define XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC 0x2222111F /* enable caches in write-allocate mode */ +#define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU 0x2222111F /* enable caches in write-through mode */ +#define XSHAL_TRAPNULL_CACHEATTR_BYPASS 0x2222222F /* disable caches in bypass mode */ +#define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to enable caches */ + +/*---------------------------------------------------------------------- + ISS (Instruction Set Simulator) SPECIFIC ... + ----------------------------------------------------------------------*/ + +/* For now, ISS defaults to the TRAPNULL settings: */ +#define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK +#define XSHAL_ISS_CACHEATTR_WRITEALLOC XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC +#define XSHAL_ISS_CACHEATTR_WRITETHRU XSHAL_TRAPNULL_CACHEATTR_WRITETHRU +#define XSHAL_ISS_CACHEATTR_BYPASS XSHAL_TRAPNULL_CACHEATTR_BYPASS +#define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK + +#define XSHAL_ISS_PIPE_REGIONS 0 +#define XSHAL_ISS_SDRAM_REGIONS 0 + + +/*---------------------------------------------------------------------- + XT2000 BOARD SPECIFIC ... + ----------------------------------------------------------------------*/ + +/* For the following, a 512MB region is used if it contains any system RAM, + * system ROM, local memory, XLMI, or other XT2000 board device or memory. + * Regions containing devices are forced to cache-BYPASS mode regardless + * of whether the macro is _WRITEBACK vs. _BYPASS etc. */ + +/* These set any 512MB region unused on the XT2000 to ILLEGAL attribute: */ +#define XSHAL_XT2000_CACHEATTR_WRITEBACK 0xFF22111F /* enable caches in write-back mode */ +#define XSHAL_XT2000_CACHEATTR_WRITEALLOC 0xFF22111F /* enable caches in write-allocate mode */ +#define XSHAL_XT2000_CACHEATTR_WRITETHRU 0xFF22111F /* enable caches in write-through mode */ +#define XSHAL_XT2000_CACHEATTR_BYPASS 0xFF22222F /* disable caches in bypass mode */ +#define XSHAL_XT2000_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_WRITEBACK /* default setting to enable caches */ + +#define XSHAL_XT2000_PIPE_REGIONS 0x00000000 /* BusInt pipeline regions */ +#define XSHAL_XT2000_SDRAM_REGIONS 0x00000440 /* BusInt SDRAM regions */ + + +/*---------------------------------------------------------------------- + VECTOR INFO AND SIZES + ----------------------------------------------------------------------*/ + +#define XSHAL_VECTORS_PACKED 0 +#define XSHAL_STATIC_VECTOR_SELECT 1 +#define XSHAL_RESET_VECTOR_VADDR 0x40000400 +#define XSHAL_RESET_VECTOR_PADDR 0x40000400 + +/* + * Sizes allocated to vectors by the system (memory map) configuration. + * These sizes are constrained by core configuration (eg. one vector's + * code cannot overflow into another vector) but are dependent on the + * system or board (or LSP) memory map configuration. + * + * Whether or not each vector happens to be in a system ROM is also + * a system configuration matter, sometimes useful, included here also: + */ +#define XSHAL_RESET_VECTOR_SIZE 0x00000300 +#define XSHAL_RESET_VECTOR_ISROM 0 +#define XSHAL_USER_VECTOR_SIZE 0x00000038 +#define XSHAL_USER_VECTOR_ISROM 0 +#define XSHAL_PROGRAMEXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */ +#define XSHAL_USEREXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */ +#define XSHAL_KERNEL_VECTOR_SIZE 0x00000038 +#define XSHAL_KERNEL_VECTOR_ISROM 0 +#define XSHAL_STACKEDEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */ +#define XSHAL_KERNELEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */ +#define XSHAL_DOUBLEEXC_VECTOR_SIZE 0x00000040 +#define XSHAL_DOUBLEEXC_VECTOR_ISROM 0 +#define XSHAL_WINDOW_VECTORS_SIZE 0x00000178 +#define XSHAL_WINDOW_VECTORS_ISROM 0 +#define XSHAL_INTLEVEL2_VECTOR_SIZE 0x00000038 +#define XSHAL_INTLEVEL2_VECTOR_ISROM 0 +#define XSHAL_INTLEVEL3_VECTOR_SIZE 0x00000038 +#define XSHAL_INTLEVEL3_VECTOR_ISROM 0 +#define XSHAL_INTLEVEL4_VECTOR_SIZE 0x00000038 +#define XSHAL_INTLEVEL4_VECTOR_ISROM 0 +#define XSHAL_INTLEVEL5_VECTOR_SIZE 0x00000038 +#define XSHAL_INTLEVEL5_VECTOR_ISROM 0 +#define XSHAL_INTLEVEL6_VECTOR_SIZE 0x00000038 +#define XSHAL_INTLEVEL6_VECTOR_ISROM 0 +#define XSHAL_DEBUG_VECTOR_SIZE XSHAL_INTLEVEL6_VECTOR_SIZE +#define XSHAL_DEBUG_VECTOR_ISROM XSHAL_INTLEVEL6_VECTOR_ISROM +#define XSHAL_NMI_VECTOR_SIZE 0x00000038 +#define XSHAL_NMI_VECTOR_ISROM 0 +#define XSHAL_INTLEVEL7_VECTOR_SIZE XSHAL_NMI_VECTOR_SIZE + + +#endif /*XTENSA_CONFIG_SYSTEM_H*/ + diff --git a/tools/sdk/include/esp32/xtensa/config/tie-asm.h b/tools/sdk/include/esp32/xtensa/config/tie-asm.h new file mode 100644 index 00000000..831d8676 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/config/tie-asm.h @@ -0,0 +1,323 @@ +/* + * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE + * + * NOTE: This header file is not meant to be included directly. + */ + +/* This header file contains assembly-language definitions (assembly + macros, etc.) for this specific Xtensa processor's TIE extensions + and options. It is customized to this Xtensa processor configuration. + + Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Cadence Design Systems Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef _XTENSA_CORE_TIE_ASM_H +#define _XTENSA_CORE_TIE_ASM_H + +/* Selection parameter values for save-area save/restore macros: */ +/* Option vs. TIE: */ +#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */ +#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */ +#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */ +/* Whether used automatically by compiler: */ +#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */ +#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */ +#define XTHAL_SAS_ANYCC 0x000C /* both of the above */ +/* ABI handling across function calls: */ +#define XTHAL_SAS_CALR 0x0010 /* caller-saved */ +#define XTHAL_SAS_CALE 0x0020 /* callee-saved */ +#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */ +#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */ +/* Misc */ +#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ +#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \ + | ((ccuse) & XTHAL_SAS_ANYCC) \ + | ((abi) & XTHAL_SAS_ANYABI) ) + + + /* + * Macro to store all non-coprocessor (extra) custom TIE and optional state + * (not including zero-overhead loop registers). + * Required parameters: + * ptr Save area pointer address register (clobbered) + * (register must contain a 4 byte aligned address). + * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS + * registers are clobbered, the remaining are unused). + * Optional parameters: + * continue If macro invoked as part of a larger store sequence, set to 1 + * if this is not the first in the sequence. Defaults to 0. + * ofs Offset from start of larger sequence (from value of first ptr + * in sequence) at which to store. Defaults to next available space + * (or 0 if is 0). + * select Select what category(ies) of registers to store, as a bitmask + * (see XTHAL_SAS_xxx constants). Defaults to all registers. + * alloc Select what category(ies) of registers to allocate; if any + * category is selected here that is not in , space for + * the corresponding registers is skipped without doing any load. + */ + .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 + xchal_sa_start \continue, \ofs + // Optional global registers used by default by the compiler: + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select) + xchal_sa_align \ptr, 0, 1016, 4, 4 + l32i \at1, \ptr, .Lxchal_ofs_+0 + wur.THREADPTR \at1 // threadptr option + .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 + .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0 + xchal_sa_align \ptr, 0, 1016, 4, 4 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 + .endif + // Optional caller-saved registers used by default by the compiler: + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select) + xchal_sa_align \ptr, 0, 1012, 4, 4 + l32i \at1, \ptr, .Lxchal_ofs_+0 + wsr.ACCLO \at1 // MAC16 option + l32i \at1, \ptr, .Lxchal_ofs_+4 + wsr.ACCHI \at1 // MAC16 option + .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 + .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 + xchal_sa_align \ptr, 0, 1012, 4, 4 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 + .endif + // Optional caller-saved registers not used by default by the compiler: + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) + xchal_sa_align \ptr, 0, 996, 4, 4 + l32i \at1, \ptr, .Lxchal_ofs_+0 + wsr.BR \at1 // boolean option + l32i \at1, \ptr, .Lxchal_ofs_+4 + wsr.SCOMPARE1 \at1 // conditional store option + l32i \at1, \ptr, .Lxchal_ofs_+8 + wsr.M0 \at1 // MAC16 option + l32i \at1, \ptr, .Lxchal_ofs_+12 + wsr.M1 \at1 // MAC16 option + l32i \at1, \ptr, .Lxchal_ofs_+16 + wsr.M2 \at1 // MAC16 option + l32i \at1, \ptr, .Lxchal_ofs_+20 + wsr.M3 \at1 // MAC16 option + .set .Lxchal_ofs_, .Lxchal_ofs_ + 24 + .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 + xchal_sa_align \ptr, 0, 996, 4, 4 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 24 + .endif + // Custom caller-saved registers not used by default by the compiler: + .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) + xchal_sa_align \ptr, 0, 1008, 4, 4 + l32i \at1, \ptr, .Lxchal_ofs_+0 + wur.F64R_LO \at1 // ureg 234 + l32i \at1, \ptr, .Lxchal_ofs_+4 + wur.F64R_HI \at1 // ureg 235 + l32i \at1, \ptr, .Lxchal_ofs_+8 + wur.F64S \at1 // ureg 236 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 12 + .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 + xchal_sa_align \ptr, 0, 1008, 4, 4 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 12 + .endif + .endm // xchal_ncp_load + + +#define XCHAL_NCP_NUM_ATMPS 1 + + /* + * Macro to store the state of TIE coprocessor FPU. + * Required parameters: + * ptr Save area pointer address register (clobbered) + * (register must contain a 4 byte aligned address). + * at1..at4 Four temporary address registers (first XCHAL_CP0_NUM_ATMPS + * registers are clobbered, the remaining are unused). + * Optional parameters are the same as for xchal_ncp_store. + */ +#define xchal_cp_FPU_store xchal_cp0_store + .macro xchal_cp0_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 + xchal_sa_start \continue, \ofs + // Custom caller-saved registers not used by default by the compiler: + .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) + xchal_sa_align \ptr, 0, 948, 4, 4 + rur.FCR \at1 // ureg 232 + s32i \at1, \ptr, .Lxchal_ofs_+0 + rur.FSR \at1 // ureg 233 + s32i \at1, \ptr, .Lxchal_ofs_+4 + ssi f0, \ptr, .Lxchal_ofs_+8 + ssi f1, \ptr, .Lxchal_ofs_+12 + ssi f2, \ptr, .Lxchal_ofs_+16 + ssi f3, \ptr, .Lxchal_ofs_+20 + ssi f4, \ptr, .Lxchal_ofs_+24 + ssi f5, \ptr, .Lxchal_ofs_+28 + ssi f6, \ptr, .Lxchal_ofs_+32 + ssi f7, \ptr, .Lxchal_ofs_+36 + ssi f8, \ptr, .Lxchal_ofs_+40 + ssi f9, \ptr, .Lxchal_ofs_+44 + ssi f10, \ptr, .Lxchal_ofs_+48 + ssi f11, \ptr, .Lxchal_ofs_+52 + ssi f12, \ptr, .Lxchal_ofs_+56 + ssi f13, \ptr, .Lxchal_ofs_+60 + ssi f14, \ptr, .Lxchal_ofs_+64 + ssi f15, \ptr, .Lxchal_ofs_+68 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 72 + .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 + xchal_sa_align \ptr, 0, 948, 4, 4 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 72 + .endif + .endm // xchal_cp0_store + + /* + * Macro to load the state of TIE coprocessor FPU. + * Required parameters: + * ptr Save area pointer address register (clobbered) + * (register must contain a 4 byte aligned address). + * at1..at4 Four temporary address registers (first XCHAL_CP0_NUM_ATMPS + * registers are clobbered, the remaining are unused). + * Optional parameters are the same as for xchal_ncp_load. + */ +#define xchal_cp_FPU_load xchal_cp0_load + .macro xchal_cp0_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 + xchal_sa_start \continue, \ofs + // Custom caller-saved registers not used by default by the compiler: + .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) + xchal_sa_align \ptr, 0, 948, 4, 4 + l32i \at1, \ptr, .Lxchal_ofs_+0 + wur.FCR \at1 // ureg 232 + l32i \at1, \ptr, .Lxchal_ofs_+4 + wur.FSR \at1 // ureg 233 + lsi f0, \ptr, .Lxchal_ofs_+8 + lsi f1, \ptr, .Lxchal_ofs_+12 + lsi f2, \ptr, .Lxchal_ofs_+16 + lsi f3, \ptr, .Lxchal_ofs_+20 + lsi f4, \ptr, .Lxchal_ofs_+24 + lsi f5, \ptr, .Lxchal_ofs_+28 + lsi f6, \ptr, .Lxchal_ofs_+32 + lsi f7, \ptr, .Lxchal_ofs_+36 + lsi f8, \ptr, .Lxchal_ofs_+40 + lsi f9, \ptr, .Lxchal_ofs_+44 + lsi f10, \ptr, .Lxchal_ofs_+48 + lsi f11, \ptr, .Lxchal_ofs_+52 + lsi f12, \ptr, .Lxchal_ofs_+56 + lsi f13, \ptr, .Lxchal_ofs_+60 + lsi f14, \ptr, .Lxchal_ofs_+64 + lsi f15, \ptr, .Lxchal_ofs_+68 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 72 + .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 + xchal_sa_align \ptr, 0, 948, 4, 4 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 72 + .endif + .endm // xchal_cp0_load + +#define XCHAL_CP0_NUM_ATMPS 1 +#define XCHAL_SA_NUM_ATMPS 1 + + /* Empty macros for unconfigured coprocessors: */ + .macro xchal_cp1_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp1_load p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm + +#endif /*_XTENSA_CORE_TIE_ASM_H*/ + diff --git a/tools/sdk/include/esp32/xtensa/config/tie.h b/tools/sdk/include/esp32/xtensa/config/tie.h new file mode 100644 index 00000000..e1787997 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/config/tie.h @@ -0,0 +1,182 @@ +/* + * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration + * + * NOTE: This header file is not meant to be included directly. + */ + +/* This header file describes this specific Xtensa processor's TIE extensions + that extend basic Xtensa core functionality. It is customized to this + Xtensa processor configuration. + + Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Cadence Design Systems Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef _XTENSA_CORE_TIE_H +#define _XTENSA_CORE_TIE_H + +#define XCHAL_CP_NUM 1 /* number of coprocessors */ +#define XCHAL_CP_MAX 1 /* max CP ID + 1 (0 if none) */ +#define XCHAL_CP_MASK 0x01 /* bitmask of all CPs by ID */ +#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */ + +/* Basic parameters of each coprocessor: */ +#define XCHAL_CP0_NAME "FPU" +#define XCHAL_CP0_IDENT FPU +#define XCHAL_CP0_SA_SIZE 72 /* size of state save area */ +#define XCHAL_CP0_SA_ALIGN 4 /* min alignment of save area */ +#define XCHAL_CP_ID_FPU 0 /* coprocessor ID (0..7) */ + +/* Filler info for unassigned coprocessors, to simplify arrays etc: */ +#define XCHAL_CP1_SA_SIZE 0 +#define XCHAL_CP1_SA_ALIGN 1 +#define XCHAL_CP2_SA_SIZE 0 +#define XCHAL_CP2_SA_ALIGN 1 +#define XCHAL_CP3_SA_SIZE 0 +#define XCHAL_CP3_SA_ALIGN 1 +#define XCHAL_CP4_SA_SIZE 0 +#define XCHAL_CP4_SA_ALIGN 1 +#define XCHAL_CP5_SA_SIZE 0 +#define XCHAL_CP5_SA_ALIGN 1 +#define XCHAL_CP6_SA_SIZE 0 +#define XCHAL_CP6_SA_ALIGN 1 +#define XCHAL_CP7_SA_SIZE 0 +#define XCHAL_CP7_SA_ALIGN 1 + +/* Save area for non-coprocessor optional and custom (TIE) state: */ +#define XCHAL_NCP_SA_SIZE 48 +#define XCHAL_NCP_SA_ALIGN 4 + +/* Total save area for optional and custom state (NCP + CPn): */ +#define XCHAL_TOTAL_SA_SIZE 128 /* with 16-byte align padding */ +#define XCHAL_TOTAL_SA_ALIGN 4 /* actual minimum alignment */ + +/* + * Detailed contents of save areas. + * NOTE: caller must define the XCHAL_SA_REG macro (not defined here) + * before expanding the XCHAL_xxx_SA_LIST() macros. + * + * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize, + * dbnum,base,regnum,bitsz,gapsz,reset,x...) + * + * s = passed from XCHAL_*_LIST(s), eg. to select how to expand + * ccused = set if used by compiler without special options or code + * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global) + * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg) + * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg) + * name = lowercase reg name (no quotes) + * galign = group byte alignment (power of 2) (galign >= align) + * align = register byte alignment (power of 2) + * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz) + * (not including any pad bytes required to galign this or next reg) + * dbnum = unique target number f/debug (see ) + * base = reg shortname w/o index (or sr=special, ur=TIE user reg) + * regnum = reg index in regfile, or special/TIE-user reg number + * bitsz = number of significant bits (regfile width, or ur/sr mask bits) + * gapsz = intervening bits, if bitsz bits not stored contiguously + * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize) + * reset = register reset value (or 0 if undefined at reset) + * x = reserved for future use (0 until then) + * + * To filter out certain registers, e.g. to expand only the non-global + * registers used by the compiler, you can do something like this: + * + * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p) + * #define SELCC0(p...) + * #define SELCC1(abikind,p...) SELAK##abikind(p) + * #define SELAK0(p...) REG(p) + * #define SELAK1(p...) REG(p) + * #define SELAK2(p...) + * #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \ + * ...what you want to expand... + */ + +#define XCHAL_NCP_SA_NUM 12 +#define XCHAL_NCP_SA_LIST(s) \ + XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \ + XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \ + XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0, f64r_lo, 4, 4, 4,0x03EA, ur,234, 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0, f64r_hi, 4, 4, 4,0x03EB, ur,235, 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0, f64s, 4, 4, 4,0x03EC, ur,236, 32,0,0,0) + +#define XCHAL_CP0_SA_NUM 18 +#define XCHAL_CP0_SA_LIST(s) \ + XCHAL_SA_REG(s,0,0,1,0, fcr, 4, 4, 4,0x03E8, ur,232, 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0, fsr, 4, 4, 4,0x03E9, ur,233, 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f0, 4, 4, 4,0x0030, f,0 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f1, 4, 4, 4,0x0031, f,1 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f2, 4, 4, 4,0x0032, f,2 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f3, 4, 4, 4,0x0033, f,3 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f4, 4, 4, 4,0x0034, f,4 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f5, 4, 4, 4,0x0035, f,5 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f6, 4, 4, 4,0x0036, f,6 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f7, 4, 4, 4,0x0037, f,7 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f8, 4, 4, 4,0x0038, f,8 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f9, 4, 4, 4,0x0039, f,9 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f10, 4, 4, 4,0x003A, f,10 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f11, 4, 4, 4,0x003B, f,11 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f12, 4, 4, 4,0x003C, f,12 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f13, 4, 4, 4,0x003D, f,13 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f14, 4, 4, 4,0x003E, f,14 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f15, 4, 4, 4,0x003F, f,15 , 32,0,0,0) + +#define XCHAL_CP1_SA_NUM 0 +#define XCHAL_CP1_SA_LIST(s) /* empty */ + +#define XCHAL_CP2_SA_NUM 0 +#define XCHAL_CP2_SA_LIST(s) /* empty */ + +#define XCHAL_CP3_SA_NUM 0 +#define XCHAL_CP3_SA_LIST(s) /* empty */ + +#define XCHAL_CP4_SA_NUM 0 +#define XCHAL_CP4_SA_LIST(s) /* empty */ + +#define XCHAL_CP5_SA_NUM 0 +#define XCHAL_CP5_SA_LIST(s) /* empty */ + +#define XCHAL_CP6_SA_NUM 0 +#define XCHAL_CP6_SA_LIST(s) /* empty */ + +#define XCHAL_CP7_SA_NUM 0 +#define XCHAL_CP7_SA_LIST(s) /* empty */ + +/* Byte length of instruction from its first nibble (op0 field), per FLIX. */ +#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3 +/* Byte length of instruction from its first byte, per FLIX. */ +#define XCHAL_BYTE0_FORMAT_LENGTHS \ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3 + +#endif /*_XTENSA_CORE_TIE_H*/ + diff --git a/tools/sdk/include/esp32/xtensa/core-macros.h b/tools/sdk/include/esp32/xtensa/core-macros.h new file mode 100755 index 00000000..663d2947 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/core-macros.h @@ -0,0 +1,456 @@ +/* + * xtensa/core-macros.h -- C specific definitions + * that depend on CORE configuration + */ + +/* + * Copyright (c) 2012 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef XTENSA_CACHE_H +#define XTENSA_CACHE_H + +#include + +/* Only define things for C code. */ +#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__) + + + +/*************************** CACHE ***************************/ + +/* All the macros are in the lower case now and some of them + * share the name with the existing functions from hal.h. + * Including this header file will define XTHAL_USE_CACHE_MACROS + * which directs hal.h not to use the functions. + * + +/* + * Single-cache-line operations in C-callable inline assembly. + * Essentially macro versions (uppercase) of: + * + * xthal_icache_line_invalidate(void *addr); + * xthal_icache_line_lock(void *addr); + * xthal_icache_line_unlock(void *addr); + * xthal_icache_sync(void); + * + * NOTE: unlike the above functions, the following macros do NOT + * execute the xthal_icache_sync() as part of each line operation. + * This sync must be called explicitly by the caller. This is to + * allow better optimization when operating on more than one line. + * + * xthal_dcache_line_invalidate(void *addr); + * xthal_dcache_line_writeback(void *addr); + * xthal_dcache_line_writeback_inv(void *addr); + * xthal_dcache_line_lock(void *addr); + * xthal_dcache_line_unlock(void *addr); + * xthal_dcache_sync(void); + * xthal_dcache_line_prefetch_for_write(void *addr); + * xthal_dcache_line_prefetch_for_read(void *addr); + * + * All are made memory-barriers, given that's how they're typically used + * (ops operate on a whole line, so clobbers all memory not just *addr). + * + * NOTE: All the block block cache ops and line prefetches are implemented + * using intrinsics so they are better optimized regarding memory barriers etc. + * + * All block downgrade functions exist in two forms: with and without + * the 'max' parameter: This parameter allows compiler to optimize + * the functions whenever the parameter is smaller than the cache size. + * + * xthal_dcache_block_invalidate(void *addr, unsigned size); + * xthal_dcache_block_writeback(void *addr, unsigned size); + * xthal_dcache_block_writeback_inv(void *addr, unsigned size); + * xthal_dcache_block_invalidate_max(void *addr, unsigned size, unsigned max); + * xthal_dcache_block_writeback_max(void *addr, unsigned size, unsigned max); + * xthal_dcache_block_writeback_inv_max(void *addr, unsigned size, unsigned max); + * + * xthal_dcache_block_prefetch_for_read(void *addr, unsigned size); + * xthal_dcache_block_prefetch_for_write(void *addr, unsigned size); + * xthal_dcache_block_prefetch_modify(void *addr, unsigned size); + * xthal_dcache_block_prefetch_read_write(void *addr, unsigned size); + * xthal_dcache_block_prefetch_for_read_grp(void *addr, unsigned size); + * xthal_dcache_block_prefetch_for_write_grp(void *addr, unsigned size); + * xthal_dcache_block_prefetch_modify_grp(void *addr, unsigned size); + * xthal_dcache_block_prefetch_read_write_grp(void *addr, unsigned size) + * + * xthal_dcache_block_wait(); + * xthal_dcache_block_required_wait(); + * xthal_dcache_block_abort(); + * xthal_dcache_block_prefetch_end(); + * xthal_dcache_block_newgrp(); + */ + +/*** INSTRUCTION CACHE ***/ + +#define XTHAL_USE_CACHE_MACROS + +#if XCHAL_ICACHE_SIZE > 0 +# define xthal_icache_line_invalidate(addr) do { void *__a = (void*)(addr); \ + __asm__ __volatile__("ihi %0, 0" :: "a"(__a) : "memory"); \ + } while(0) +#else +# define xthal_icache_line_invalidate(addr) do {/*nothing*/} while(0) +#endif + +#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE +# define xthal_icache_line_lock(addr) do { void *__a = (void*)(addr); \ + __asm__ __volatile__("ipfl %0, 0" :: "a"(__a) : "memory"); \ + } while(0) +# define xthal_icache_line_unlock(addr) do { void *__a = (void*)(addr); \ + __asm__ __volatile__("ihu %0, 0" :: "a"(__a) : "memory"); \ + } while(0) +#else +# define xthal_icache_line_lock(addr) do {/*nothing*/} while(0) +# define xthal_icache_line_unlock(addr) do {/*nothing*/} while(0) +#endif + +/* + * Even if a config doesn't have caches, an isync is still needed + * when instructions in any memory are modified, whether by a loader + * or self-modifying code. Therefore, this macro always produces + * an isync, whether or not an icache is present. + */ +#define xthal_icache_sync() \ + __asm__ __volatile__("isync":::"memory") + + +/*** DATA CACHE ***/ + +#if XCHAL_DCACHE_SIZE > 0 + +# include + +# define xthal_dcache_line_invalidate(addr) do { void *__a = (void*)(addr); \ + __asm__ __volatile__("dhi %0, 0" :: "a"(__a) : "memory"); \ + } while(0) +# define xthal_dcache_line_writeback(addr) do { void *__a = (void*)(addr); \ + __asm__ __volatile__("dhwb %0, 0" :: "a"(__a) : "memory"); \ + } while(0) +# define xthal_dcache_line_writeback_inv(addr) do { void *__a = (void*)(addr); \ + __asm__ __volatile__("dhwbi %0, 0" :: "a"(__a) : "memory"); \ + } while(0) +# define xthal_dcache_sync() \ + __asm__ __volatile__("" /*"dsync"?*/:::"memory") +# define xthal_dcache_line_prefetch_for_read(addr) do { \ + XT_DPFR((const int*)addr, 0); \ + } while(0) +#else +# define xthal_dcache_line_invalidate(addr) do {/*nothing*/} while(0) +# define xthal_dcache_line_writeback(addr) do {/*nothing*/} while(0) +# define xthal_dcache_line_writeback_inv(addr) do {/*nothing*/} while(0) +# define xthal_dcache_sync() __asm__ __volatile__("":::"memory") +# define xthal_dcache_line_prefetch_for_read(addr) do {/*nothing*/} while(0) +#endif + +#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE +# define xthal_dcache_line_lock(addr) do { void *__a = (void*)(addr); \ + __asm__ __volatile__("dpfl %0, 0" :: "a"(__a) : "memory"); \ + } while(0) +# define xthal_dcache_line_unlock(addr) do { void *__a = (void*)(addr); \ + __asm__ __volatile__("dhu %0, 0" :: "a"(__a) : "memory"); \ + } while(0) +#else +# define xthal_dcache_line_lock(addr) do {/*nothing*/} while(0) +# define xthal_dcache_line_unlock(addr) do {/*nothing*/} while(0) +#endif + +#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK + +# define xthal_dcache_line_prefetch_for_write(addr) do { \ + XT_DPFW((const int*)addr, 0); \ + } while(0) +#else +# define xthal_dcache_line_prefetch_for_write(addr) do {/*nothing*/} while(0) +#endif + + +/***** Block Operations *****/ + +#if XCHAL_DCACHE_SIZE > 0 && XCHAL_HAVE_CACHE_BLOCKOPS + +/* upgrades */ + +# define _XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, type) \ + { \ + type((const int*)addr, size); \ + } + +/*downgrades */ + +# define _XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, type) \ + unsigned _s = size; \ + unsigned _a = addr; \ + do { \ + unsigned __s = (_s > XCHAL_DCACHE_SIZE) ? \ + XCHAL_DCACHE_SIZE : _s; \ + type((const int*)_a, __s); \ + _s -= __s; \ + _a += __s; \ + } while(_s > 0); + +# define _XTHAL_DCACHE_BLOCK_DOWNGRADE_MAX(addr, size, type, max) \ + if (max <= XCHAL_DCACHE_SIZE) { \ + unsigned _s = size; \ + unsigned _a = addr; \ + type((const int*)_a, _s); \ + } \ + else { \ + _XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, type); \ + } + +# define xthal_dcache_block_invalidate(addr, size) do { \ + _XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, XT_DHI_B); \ + } while(0) +# define xthal_dcache_block_writeback(addr, size) do { \ + _XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, XT_DHWB_B); \ + } while(0) +# define xthal_dcache_block_writeback_inv(addr, size) do { \ + _XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, XT_DHWBI_B); \ + } while(0) + +# define xthal_dcache_block_invalidate_max(addr, size, max) do { \ + _XTHAL_DCACHE_BLOCK_DOWNGRADE_MAX(addr, size, XT_DHI_B, max); \ + } while(0) +# define xthal_dcache_block_writeback_max(addr, size, max) do { \ + _XTHAL_DCACHE_BLOCK_DOWNGRADE_MAX(addr, size, XT_DHWB_B, max); \ + } while(0) +# define xthal_dcache_block_writeback_inv_max(addr, size, max) do { \ + _XTHAL_DCACHE_BLOCK_DOWNGRADE_MAX(addr, size, XT_DHWBI_B, max); \ + } while(0) + +/* upgrades that are performed even with write-thru caches */ + +# define xthal_dcache_block_prefetch_read_write(addr, size) do { \ + _XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFW_B); \ + } while(0) +# define xthal_dcache_block_prefetch_read_write_grp(addr, size) do { \ + _XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFW_BF); \ + } while(0) +# define xthal_dcache_block_prefetch_for_read(addr, size) do { \ + _XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFR_B); \ + } while(0) +# define xthal_dcache_block_prefetch_for_read_grp(addr, size) do { \ + _XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFR_BF); \ + } while(0) + +/* abort all or end optional block cache operations */ +# define xthal_dcache_block_abort() do { \ + XT_PFEND_A(); \ + } while(0) +# define xthal_dcache_block_end() do { \ + XT_PFEND_O(); \ + } while(0) + +/* wait for all/required block cache operations to finish */ +# define xthal_dcache_block_wait() do { \ + XT_PFWAIT_A(); \ + } while(0) +# define xthal_dcache_block_required_wait() do { \ + XT_PFWAIT_R(); \ + } while(0) +/* Start a new group */ +# define xthal_dcache_block_newgrp() do { \ + XT_PFNXT_F(); \ + } while(0) +#else +# define xthal_dcache_block_invalidate(addr, size) do {/*nothing*/} while(0) +# define xthal_dcache_block_writeback(addr, size) do {/*nothing*/} while(0) +# define xthal_dcache_block_writeback_inv(addr, size) do {/*nothing*/} while(0) +# define xthal_dcache_block_invalidate_max(addr, size, max) do {/*nothing*/} while(0) +# define xthal_dcache_block_writeback_max(addr, size, max) do {/*nothing*/} while(0) +# define xthal_dcache_block_writeback_inv_max(addr, size, max) do {/*nothing*/} while(0) +# define xthal_dcache_block_prefetch_read_write(addr, size) do {/*nothing*/} while(0) +# define xthal_dcache_block_prefetch_read_write_grp(addr, size) do {/*nothing*/} while(0) +# define xthal_dcache_block_prefetch_for_read(addr, size) do {/*nothing*/} while(0) +# define xthal_dcache_block_prefetch_for_read_grp(addr, size) do {/*nothing*/} while(0) +# define xthal_dcache_block_end() do {/*nothing*/} while(0) +# define xthal_dcache_block_abort() do {/*nothing*/} while(0) +# define xthal_dcache_block_wait() do {/*nothing*/} while(0) +# define xthal_dcache_block_required_wait() do {/*nothing*/} while(0) +# define xthal_dcache_block_newgrp() do {/*nothing*/} while(0) +#endif + +#if XCHAL_DCACHE_SIZE > 0 && XCHAL_HAVE_CACHE_BLOCKOPS && XCHAL_DCACHE_IS_WRITEBACK + +# define xthal_dcache_block_prefetch_for_write(addr, size) do { \ + _XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFW_B); \ + } while(0) +# define xthal_dcache_block_prefetch_modify(addr, size) do { \ + _XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFM_B); \ + } while(0) +# define xthal_dcache_block_prefetch_for_write_grp(addr, size) do { \ + _XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFW_BF); \ + } while(0) +# define xthal_dcache_block_prefetch_modify_grp(addr, size) do { \ + _XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFM_BF); \ + } while(0) +#else +# define xthal_dcache_block_prefetch_for_write(addr, size) do {/*nothing*/} while(0) +# define xthal_dcache_block_prefetch_modify(addr, size) do {/*nothing*/} while(0) +# define xthal_dcache_block_prefetch_for_write_grp(addr, size) do {/*nothing*/} while(0) +# define xthal_dcache_block_prefetch_modify_grp(addr, size) do {/*nothing*/} while(0) +#endif + +/*************************** INTERRUPTS ***************************/ + +/* + * Macro versions of: + * unsigned xthal_get_intenable( void ); + * void xthal_set_intenable( unsigned ); + * unsigned xthal_get_interrupt( void ); + * void xthal_set_intset( unsigned ); + * void xthal_set_intclear( unsigned ); + * unsigned xthal_get_ccount(void); + * void xthal_set_ccompare(int, unsigned); + * unsigned xthal_get_ccompare(int); + * + * NOTE: for {set,get}_ccompare, the first argument MUST be a decimal constant. + */ + +#if XCHAL_HAVE_INTERRUPTS +# define XTHAL_GET_INTENABLE() ({ int __intenable; \ + __asm__("rsr.intenable %0" : "=a"(__intenable)); \ + __intenable; }) +# define XTHAL_SET_INTENABLE(v) do { int __intenable = (int)(v); \ + __asm__ __volatile__("wsr.intenable %0" :: "a"(__intenable):"memory"); \ + } while(0) +# define XTHAL_GET_INTERRUPT() ({ int __interrupt; \ + __asm__("rsr.interrupt %0" : "=a"(__interrupt)); \ + __interrupt; }) +# define XTHAL_SET_INTSET(v) do { int __interrupt = (int)(v); \ + __asm__ __volatile__("wsr.intset %0" :: "a"(__interrupt):"memory"); \ + } while(0) +# define XTHAL_SET_INTCLEAR(v) do { int __interrupt = (int)(v); \ + __asm__ __volatile__("wsr.intclear %0" :: "a"(__interrupt):"memory"); \ + } while(0) +# define XTHAL_GET_CCOUNT() ({ int __ccount; \ + __asm__("rsr.ccount %0" : "=a"(__ccount)); \ + __ccount; }) +# define XTHAL_SET_CCOUNT(v) do { int __ccount = (int)(v); \ + __asm__ __volatile__("wsr.ccount %0" :: "a"(__ccount):"memory"); \ + } while(0) +# define _XTHAL_GET_CCOMPARE(n) ({ int __ccompare; \ + __asm__("rsr.ccompare" #n " %0" : "=a"(__ccompare)); \ + __ccompare; }) +# define XTHAL_GET_CCOMPARE(n) _XTHAL_GET_CCOMPARE(n) +# define _XTHAL_SET_CCOMPARE(n,v) do { int __ccompare = (int)(v); \ + __asm__ __volatile__("wsr.ccompare" #n " %0 ; esync" :: "a"(__ccompare):"memory"); \ + } while(0) +# define XTHAL_SET_CCOMPARE(n,v) _XTHAL_SET_CCOMPARE(n,v) +#else +# define XTHAL_GET_INTENABLE() 0 +# define XTHAL_SET_INTENABLE(v) do {/*nothing*/} while(0) +# define XTHAL_GET_INTERRUPT() 0 +# define XTHAL_SET_INTSET(v) do {/*nothing*/} while(0) +# define XTHAL_SET_INTCLEAR(v) do {/*nothing*/} while(0) +# define XTHAL_GET_CCOUNT() 0 +# define XTHAL_SET_CCOUNT(v) do {/*nothing*/} while(0) +# define XTHAL_GET_CCOMPARE(n) 0 +# define XTHAL_SET_CCOMPARE(n,v) do {/*nothing*/} while(0) +#endif + + +/*************************** MISC ***************************/ + +/* + * Macro or inline versions of: + * void xthal_clear_regcached_code( void ); + * unsigned xthal_get_prid( void ); + * unsigned xthal_compare_and_set( int *addr, int testval, int setval ); + */ + +#if XCHAL_HAVE_LOOPS +# define XTHAL_CLEAR_REGCACHED_CODE() \ + __asm__ __volatile__("wsr.lcount %0" :: "a"(0) : "memory") +#else +# define XTHAL_CLEAR_REGCACHED_CODE() do {/*nothing*/} while(0) +#endif + +#if XCHAL_HAVE_PRID +# define XTHAL_GET_PRID() ({ int __prid; \ + __asm__("rsr.prid %0" : "=a"(__prid)); \ + __prid; }) +#else +# define XTHAL_GET_PRID() 0 +#endif + + +static inline unsigned XTHAL_COMPARE_AND_SET( int *addr, int testval, int setval ) +{ + int result; + +#if XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION_MAJOR >= 2200 + __asm__ __volatile__ ( + " wsr.scompare1 %2 \n" + " s32c1i %0, %3, 0 \n" + : "=a"(result) : "0" (setval), "a" (testval), "a" (addr) + : "memory"); +#elif XCHAL_HAVE_INTERRUPTS + int tmp; + __asm__ __volatile__ ( + " rsil %4, 15 \n" // %4 == saved ps + " l32i %0, %3, 0 \n" // %0 == value to test, return val + " bne %2, %0, 9f \n" // test + " s32i %1, %3, 0 \n" // write the new value + "9: wsr.ps %4 ; rsync \n" // restore the PS + : "=a"(result) + : "0" (setval), "a" (testval), "a" (addr), "a" (tmp) + : "memory"); +#else + __asm__ __volatile__ ( + " l32i %0, %3, 0 \n" // %0 == value to test, return val + " bne %2, %0, 9f \n" // test + " s32i %1, %3, 0 \n" // write the new value + "9: \n" + : "=a"(result) : "0" (setval), "a" (testval), "a" (addr) + : "memory"); +#endif + return result; +} + +#if XCHAL_HAVE_EXTERN_REGS + +static inline unsigned XTHAL_RER (unsigned int reg) +{ + unsigned result; + + __asm__ __volatile__ ( + " rer %0, %1" + : "=a" (result) : "a" (reg) : "memory"); + + return result; +} + +static inline void XTHAL_WER (unsigned reg, unsigned value) +{ + __asm__ __volatile__ ( + " wer %0, %1" + : : "a" (value), "a" (reg) : "memory"); +} + +#endif /* XCHAL_HAVE_EXTERN_REGS */ + +#endif /* C code */ + +#endif /*XTENSA_CACHE_H*/ + diff --git a/tools/sdk/include/esp32/xtensa/coreasm.h b/tools/sdk/include/esp32/xtensa/coreasm.h new file mode 100755 index 00000000..e41e04d1 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/coreasm.h @@ -0,0 +1,939 @@ +/* + * xtensa/coreasm.h -- assembler-specific definitions that depend on CORE configuration + * + * Source for configuration-independent binaries (which link in a + * configuration-specific HAL library) must NEVER include this file. + * It is perfectly normal, however, for the HAL itself to include this file. + * + * This file must NOT include xtensa/config/system.h. Any assembler + * header file that depends on system information should likely go + * in a new systemasm.h (or sysasm.h) header file. + * + * NOTE: macro beqi32 is NOT configuration-dependent, and is placed + * here until we have a proper configuration-independent header file. + */ + +/* $Id: //depot/rel/Eaglenest/Xtensa/OS/include/xtensa/coreasm.h#3 $ */ + +/* + * Copyright (c) 2000-2014 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef XTENSA_COREASM_H +#define XTENSA_COREASM_H + +/* + * Tell header files this is assembly source, so they can avoid non-assembler + * definitions (eg. C types etc): + */ +#ifndef _ASMLANGUAGE /* conditionalize to avoid cpp warnings (3rd parties might use same macro) */ +#define _ASMLANGUAGE +#endif + +#include +#include +#include + +/* + * Assembly-language specific definitions (assembly macros, etc.). + */ + +/*---------------------------------------------------------------------- + * find_ms_setbit + * + * This macro finds the most significant bit that is set in + * and return its index + in , or - 1 if is zero. + * The index counts starting at zero for the lsbit, so the return + * value ranges from -1 (no bit set) to +31 (msbit set). + * + * Parameters: + * destination address register (any register) + * source address register + * temporary address register (must be different than ) + * constant value added to result (usually 0 or 1) + * On entry: + * = undefined if different than + * = value whose most significant set bit is to be found + * = undefined + * no other registers are used by this macro. + * On exit: + * = + index of msbit set in original , + * = - 1 if original was zero. + * clobbered (if not ) + * clobbered (if not ) + * Example: + * find_ms_setbit a0, a4, a0, 0 -- return in a0 index of msbit set in a4 + */ + + .macro find_ms_setbit ad, as, at, base +#if XCHAL_HAVE_NSA + movi \at, 31+\base + nsau \as, \as // get index of \as, numbered from msbit (32 if absent) + sub \ad, \at, \as // get numbering from lsbit (0..31, -1 if absent) +#else /* XCHAL_HAVE_NSA */ + movi \at, \base // start with result of 0 (point to lsbit of 32) + + beqz \as, 2f // special case for zero argument: return -1 + bltui \as, 0x10000, 1f // is it one of the 16 lsbits? (if so, check lower 16 bits) + addi \at, \at, 16 // no, increment result to upper 16 bits (of 32) + //srli \as, \as, 16 // check upper half (shift right 16 bits) + extui \as, \as, 16, 16 // check upper half (shift right 16 bits) +1: bltui \as, 0x100, 1f // is it one of the 8 lsbits? (if so, check lower 8 bits) + addi \at, \at, 8 // no, increment result to upper 8 bits (of 16) + srli \as, \as, 8 // shift right to check upper 8 bits +1: bltui \as, 0x10, 1f // is it one of the 4 lsbits? (if so, check lower 4 bits) + addi \at, \at, 4 // no, increment result to upper 4 bits (of 8) + srli \as, \as, 4 // shift right 4 bits to check upper half +1: bltui \as, 0x4, 1f // is it one of the 2 lsbits? (if so, check lower 2 bits) + addi \at, \at, 2 // no, increment result to upper 2 bits (of 4) + srli \as, \as, 2 // shift right 2 bits to check upper half +1: bltui \as, 0x2, 1f // is it the lsbit? + addi \at, \at, 2 // no, increment result to upper bit (of 2) +2: addi \at, \at, -1 // (from just above: add 1; from beqz: return -1) + //srli \as, \as, 1 +1: // done! \at contains index of msbit set (or -1 if none set) + .if 0x\ad - 0x\at // destination different than \at ? (works because regs are a0-a15) + mov \ad, \at // then move result to \ad + .endif +#endif /* XCHAL_HAVE_NSA */ + .endm // find_ms_setbit + +/*---------------------------------------------------------------------- + * find_ls_setbit + * + * This macro finds the least significant bit that is set in , + * and return its index in . + * Usage is the same as for the find_ms_setbit macro. + * Example: + * find_ls_setbit a0, a4, a0, 0 -- return in a0 index of lsbit set in a4 + */ + + .macro find_ls_setbit ad, as, at, base + neg \at, \as // keep only the least-significant bit that is set... + and \as, \at, \as // ... in \as + find_ms_setbit \ad, \as, \at, \base + .endm // find_ls_setbit + +/*---------------------------------------------------------------------- + * find_ls_one + * + * Same as find_ls_setbit with base zero. + * Source (as) and destination (ad) registers must be different. + * Provided for backward compatibility. + */ + + .macro find_ls_one ad, as + find_ls_setbit \ad, \as, \ad, 0 + .endm // find_ls_one + +/*---------------------------------------------------------------------- + * floop, floopnez, floopgtz, floopend + * + * These macros are used for fast inner loops that + * work whether or not the Loops options is configured. + * If the Loops option is configured, they simply use + * the zero-overhead LOOP instructions; otherwise + * they use explicit decrement and branch instructions. + * + * They are used in pairs, with floop, floopnez or floopgtz + * at the beginning of the loop, and floopend at the end. + * + * Each pair of loop macro calls must be given the loop count + * address register and a unique label for that loop. + * + * Example: + * + * movi a3, 16 // loop 16 times + * floop a3, myloop1 + * : + * bnez a7, end1 // exit loop if a7 != 0 + * : + * floopend a3, myloop1 + * end1: + * + * Like the LOOP instructions, these macros cannot be + * nested, must include at least one instruction, + * cannot call functions inside the loop, etc. + * The loop can be exited by jumping to the instruction + * following floopend (or elsewhere outside the loop), + * or continued by jumping to a NOP instruction placed + * immediately before floopend. + * + * Unlike LOOP instructions, the register passed to floop* + * cannot be used inside the loop, because it is used as + * the loop counter if the Loops option is not configured. + * And its value is undefined after exiting the loop. + * And because the loop counter register is active inside + * the loop, you can't easily use this construct to loop + * across a register file using ROTW as you might with LOOP + * instructions, unless you copy the loop register along. + */ + + /* Named label version of the macros: */ + + .macro floop ar, endlabel + floop_ \ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel + .endm + + .macro floopnez ar, endlabel + floopnez_ \ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel + .endm + + .macro floopgtz ar, endlabel + floopgtz_ \ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel + .endm + + .macro floopend ar, endlabel + floopend_ \ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel + .endm + + /* Numbered local label version of the macros: */ +#if 0 /*UNTESTED*/ + .macro floop89 ar + floop_ \ar, 8, 9f + .endm + + .macro floopnez89 ar + floopnez_ \ar, 8, 9f + .endm + + .macro floopgtz89 ar + floopgtz_ \ar, 8, 9f + .endm + + .macro floopend89 ar + floopend_ \ar, 8b, 9 + .endm +#endif /*0*/ + + /* Underlying version of the macros: */ + + .macro floop_ ar, startlabel, endlabelref + .ifdef _infloop_ + .if _infloop_ + .err // Error: floop cannot be nested + .endif + .endif + .set _infloop_, 1 +#if XCHAL_HAVE_LOOPS + loop \ar, \endlabelref +#else /* XCHAL_HAVE_LOOPS */ +\startlabel: + addi \ar, \ar, -1 +#endif /* XCHAL_HAVE_LOOPS */ + .endm // floop_ + + .macro floopnez_ ar, startlabel, endlabelref + .ifdef _infloop_ + .if _infloop_ + .err // Error: floopnez cannot be nested + .endif + .endif + .set _infloop_, 1 +#if XCHAL_HAVE_LOOPS + loopnez \ar, \endlabelref +#else /* XCHAL_HAVE_LOOPS */ + beqz \ar, \endlabelref +\startlabel: + addi \ar, \ar, -1 +#endif /* XCHAL_HAVE_LOOPS */ + .endm // floopnez_ + + .macro floopgtz_ ar, startlabel, endlabelref + .ifdef _infloop_ + .if _infloop_ + .err // Error: floopgtz cannot be nested + .endif + .endif + .set _infloop_, 1 +#if XCHAL_HAVE_LOOPS + loopgtz \ar, \endlabelref +#else /* XCHAL_HAVE_LOOPS */ + bltz \ar, \endlabelref + beqz \ar, \endlabelref +\startlabel: + addi \ar, \ar, -1 +#endif /* XCHAL_HAVE_LOOPS */ + .endm // floopgtz_ + + + .macro floopend_ ar, startlabelref, endlabel + .ifndef _infloop_ + .err // Error: floopend without matching floopXXX + .endif + .ifeq _infloop_ + .err // Error: floopend without matching floopXXX + .endif + .set _infloop_, 0 +#if ! XCHAL_HAVE_LOOPS + bnez \ar, \startlabelref +#endif /* XCHAL_HAVE_LOOPS */ +\endlabel: + .endm // floopend_ + +/*---------------------------------------------------------------------- + * crsil -- conditional RSIL (read/set interrupt level) + * + * Executes the RSIL instruction if it exists, else just reads PS. + * The RSIL instruction does not exist in the new exception architecture + * if the interrupt option is not selected. + */ + + .macro crsil ar, newlevel +#if XCHAL_HAVE_OLD_EXC_ARCH || XCHAL_HAVE_INTERRUPTS + rsil \ar, \newlevel +#else + rsr \ar, PS +#endif + .endm // crsil + +/*---------------------------------------------------------------------- + * safe_movi_a0 -- move constant into a0 when L32R is not safe + * + * This macro is typically used by interrupt/exception handlers. + * Loads a 32-bit constant in a0, without using any other register, + * and without corrupting the LITBASE register, even when the + * value of the LITBASE register is unknown (eg. when application + * code and interrupt/exception handling code are built independently, + * and thus with independent values of the LITBASE register; + * debug monitors are one example of this). + * + * Worst-case size of resulting code: 17 bytes. + */ + + .macro safe_movi_a0 constant +#if XCHAL_HAVE_ABSOLUTE_LITERALS + /* Contort a PC-relative literal load even though we may be in litbase-relative mode: */ + j 1f + .begin no-transform // ensure what follows is assembled exactly as-is + .align 4 // ensure constant and call0 target ... + .byte 0 // ... are 4-byte aligned (call0 instruction is 3 bytes long) +1: call0 2f // read PC (that follows call0) in a0 + .long \constant // 32-bit constant to load into a0 +2: + .end no-transform + l32i a0, a0, 0 // load constant +#else + movi a0, \constant // no LITBASE, can assume PC-relative L32R +#endif + .endm + + + + +/*---------------------------------------------------------------------- + * window_spill{4,8,12} + * + * These macros spill callers' register windows to the stack. + * They work for both privileged and non-privileged tasks. + * Must be called from a windowed ABI context, eg. within + * a windowed ABI function (ie. valid stack frame, window + * exceptions enabled, not in exception mode, etc). + * + * This macro requires a single invocation of the window_spill_common + * macro in the same assembly unit and section. + * + * Note that using window_spill{4,8,12} macros is more efficient + * than calling a function implemented using window_spill_function, + * because the latter needs extra code to figure out the size of + * the call to the spilling function. + * + * Example usage: + * + * .text + * .align 4 + * .global some_function + * .type some_function,@function + * some_function: + * entry a1, 16 + * : + * : + * + * window_spill4 // Spill windows of some_function's callers; preserves a0..a3 only; + * // to use window_spill{8,12} in this example function we'd have + * // to increase space allocated by the entry instruction, because + * // 16 bytes only allows call4; 32 or 48 bytes (+locals) are needed + * // for call8/window_spill8 or call12/window_spill12 respectively. + * + * : + * + * retw + * + * window_spill_common // instantiates code used by window_spill4 + * + * + * On entry: + * none (if window_spill4) + * stack frame has enough space allocated for call8 (if window_spill8) + * stack frame has enough space allocated for call12 (if window_spill12) + * On exit: + * a4..a15 clobbered (if window_spill4) + * a8..a15 clobbered (if window_spill8) + * a12..a15 clobbered (if window_spill12) + * no caller windows are in live registers + */ + + .macro window_spill4 +#if XCHAL_HAVE_WINDOWED +# if XCHAL_NUM_AREGS == 16 + movi a15, 0 // for 16-register files, no need to call to reach the end +# elif XCHAL_NUM_AREGS == 32 + call4 .L__wdwspill_assist28 // call deep enough to clear out any live callers +# elif XCHAL_NUM_AREGS == 64 + call4 .L__wdwspill_assist60 // call deep enough to clear out any live callers +# endif +#endif + .endm // window_spill4 + + .macro window_spill8 +#if XCHAL_HAVE_WINDOWED +# if XCHAL_NUM_AREGS == 16 + movi a15, 0 // for 16-register files, no need to call to reach the end +# elif XCHAL_NUM_AREGS == 32 + call8 .L__wdwspill_assist24 // call deep enough to clear out any live callers +# elif XCHAL_NUM_AREGS == 64 + call8 .L__wdwspill_assist56 // call deep enough to clear out any live callers +# endif +#endif + .endm // window_spill8 + + .macro window_spill12 +#if XCHAL_HAVE_WINDOWED +# if XCHAL_NUM_AREGS == 16 + movi a15, 0 // for 16-register files, no need to call to reach the end +# elif XCHAL_NUM_AREGS == 32 + call12 .L__wdwspill_assist20 // call deep enough to clear out any live callers +# elif XCHAL_NUM_AREGS == 64 + call12 .L__wdwspill_assist52 // call deep enough to clear out any live callers +# endif +#endif + .endm // window_spill12 + + +/*---------------------------------------------------------------------- + * window_spill_function + * + * This macro outputs a function that will spill its caller's callers' + * register windows to the stack. Eg. it could be used to implement + * a version of xthal_window_spill() that works in non-privileged tasks. + * This works for both privileged and non-privileged tasks. + * + * Typical usage: + * + * .text + * .align 4 + * .global my_spill_function + * .type my_spill_function,@function + * my_spill_function: + * window_spill_function + * + * On entry to resulting function: + * none + * On exit from resulting function: + * none (no caller windows are in live registers) + */ + + .macro window_spill_function +#if XCHAL_HAVE_WINDOWED +# if XCHAL_NUM_AREGS == 32 + entry sp, 48 + bbci.l a0, 31, 1f // branch if called with call4 + bbsi.l a0, 30, 2f // branch if called with call12 + call8 .L__wdwspill_assist16 // called with call8, only need another 8 + retw +1: call12 .L__wdwspill_assist16 // called with call4, only need another 12 + retw +2: call4 .L__wdwspill_assist16 // called with call12, only need another 4 + retw +# elif XCHAL_NUM_AREGS == 64 + entry sp, 48 + bbci.l a0, 31, 1f // branch if called with call4 + bbsi.l a0, 30, 2f // branch if called with call12 + call4 .L__wdwspill_assist52 // called with call8, only need a call4 + retw +1: call8 .L__wdwspill_assist52 // called with call4, only need a call8 + retw +2: call12 .L__wdwspill_assist40 // called with call12, can skip a call12 + retw +# elif XCHAL_NUM_AREGS == 16 + entry sp, 16 + bbci.l a0, 31, 1f // branch if called with call4 + bbsi.l a0, 30, 2f // branch if called with call12 + movi a7, 0 // called with call8 + retw +1: movi a11, 0 // called with call4 +2: retw // if called with call12, everything already spilled + +// movi a15, 0 // trick to spill all but the direct caller +// j 1f +// // The entry instruction is magical in the assembler (gets auto-aligned) +// // so we have to jump to it to avoid falling through the padding. +// // We need entry/retw to know where to return. +//1: entry sp, 16 +// retw +# else +# error "unrecognized address register file size" +# endif + +#endif /* XCHAL_HAVE_WINDOWED */ + window_spill_common + .endm // window_spill_function + +/*---------------------------------------------------------------------- + * window_spill_common + * + * Common code used by any number of invocations of the window_spill## + * and window_spill_function macros. + * + * Must be instantiated exactly once within a given assembly unit, + * within call/j range of and same section as window_spill## + * macro invocations for that assembly unit. + * (Is automatically instantiated by the window_spill_function macro.) + */ + + .macro window_spill_common +#if XCHAL_HAVE_WINDOWED && (XCHAL_NUM_AREGS == 32 || XCHAL_NUM_AREGS == 64) + .ifndef .L__wdwspill_defined +# if XCHAL_NUM_AREGS >= 64 +.L__wdwspill_assist60: + entry sp, 32 + call8 .L__wdwspill_assist52 + retw +.L__wdwspill_assist56: + entry sp, 16 + call4 .L__wdwspill_assist52 + retw +.L__wdwspill_assist52: + entry sp, 48 + call12 .L__wdwspill_assist40 + retw +.L__wdwspill_assist40: + entry sp, 48 + call12 .L__wdwspill_assist28 + retw +# endif +.L__wdwspill_assist28: + entry sp, 48 + call12 .L__wdwspill_assist16 + retw +.L__wdwspill_assist24: + entry sp, 32 + call8 .L__wdwspill_assist16 + retw +.L__wdwspill_assist20: + entry sp, 16 + call4 .L__wdwspill_assist16 + retw +.L__wdwspill_assist16: + entry sp, 16 + movi a15, 0 + retw + .set .L__wdwspill_defined, 1 + .endif +#endif /* XCHAL_HAVE_WINDOWED with 32 or 64 aregs */ + .endm // window_spill_common + +/*---------------------------------------------------------------------- + * beqi32 + * + * macro implements version of beqi for arbitrary 32-bit immediate value + * + * beqi32 ax, ay, imm32, label + * + * Compares value in register ax with imm32 value and jumps to label if + * equal. Clobbers register ay if needed + * + */ + .macro beqi32 ax, ay, imm, label + .ifeq ((\imm-1) & ~7) // 1..8 ? + beqi \ax, \imm, \label + .else + .ifeq (\imm+1) // -1 ? + beqi \ax, \imm, \label + .else + .ifeq (\imm) // 0 ? + beqz \ax, \label + .else + // We could also handle immediates 10,12,16,32,64,128,256 + // but it would be a long macro... + movi \ay, \imm + beq \ax, \ay, \label + .endif + .endif + .endif + .endm // beqi32 + +/*---------------------------------------------------------------------- + * isync_retw_nop + * + * This macro must be invoked immediately after ISYNC if ISYNC + * would otherwise be immediately followed by RETW (or other instruction + * modifying WindowBase or WindowStart), in a context where + * kernel vector mode may be selected, and level-one interrupts + * and window overflows may be enabled, on an XEA1 configuration. + * + * On hardware with erratum "XEA1KWIN" (see for details), + * XEA1 code must have at least one instruction between ISYNC and RETW if + * run in kernel vector mode with interrupts and window overflows enabled. + */ + .macro isync_retw_nop +#if XCHAL_MAYHAVE_ERRATUM_XEA1KWIN + nop +#endif + .endm + +/*---------------------------------------------------------------------- + * isync_erratum453 + * + * This macro must be invoked at certain points in the code, + * such as in exception and interrupt vectors in particular, + * to work around erratum 453. + */ + .macro isync_erratum453 +#if XCHAL_ERRATUM_453 + isync +#endif + .endm + + + +/*---------------------------------------------------------------------- + * abs + * + * implements abs on machines that do not have it configured + */ + +#if !XCHAL_HAVE_ABS + .macro abs arr, ars + .ifc \arr, \ars + //src equal dest is less efficient + bgez \arr, 1f + neg \arr, \arr +1: + .else + neg \arr, \ars + movgez \arr, \ars, \ars + .endif + .endm +#endif /* !XCHAL_HAVE_ABS */ + + +/*---------------------------------------------------------------------- + * addx2 + * + * implements addx2 on machines that do not have it configured + * + */ + +#if !XCHAL_HAVE_ADDX + .macro addx2 arr, ars, art + .ifc \arr, \art + .ifc \arr, \ars + // addx2 a, a, a (not common) + .err + .else + add \arr, \ars, \art + add \arr, \ars, \art + .endif + .else + //addx2 a, b, c + //addx2 a, a, b + //addx2 a, b, b + slli \arr, \ars, 1 + add \arr, \arr, \art + .endif + .endm +#endif /* !XCHAL_HAVE_ADDX */ + +/*---------------------------------------------------------------------- + * addx4 + * + * implements addx4 on machines that do not have it configured + * + */ + +#if !XCHAL_HAVE_ADDX + .macro addx4 arr, ars, art + .ifc \arr, \art + .ifc \arr, \ars + // addx4 a, a, a (not common) + .err + .else + //# addx4 a, b, a + add \arr, \ars, \art + add \arr, \ars, \art + add \arr, \ars, \art + add \arr, \ars, \art + .endif + .else + //addx4 a, b, c + //addx4 a, a, b + //addx4 a, b, b + slli \arr, \ars, 2 + add \arr, \arr, \art + .endif + .endm +#endif /* !XCHAL_HAVE_ADDX */ + +/*---------------------------------------------------------------------- + * addx8 + * + * implements addx8 on machines that do not have it configured + * + */ + +#if !XCHAL_HAVE_ADDX + .macro addx8 arr, ars, art + .ifc \arr, \art + .ifc \arr, \ars + //addx8 a, a, a (not common) + .err + .else + //addx8 a, b, a + add \arr, \ars, \art + add \arr, \ars, \art + add \arr, \ars, \art + add \arr, \ars, \art + add \arr, \ars, \art + add \arr, \ars, \art + add \arr, \ars, \art + add \arr, \ars, \art + .endif + .else + //addx8 a, b, c + //addx8 a, a, b + //addx8 a, b, b + slli \arr, \ars, 3 + add \arr, \arr, \art + .endif + .endm +#endif /* !XCHAL_HAVE_ADDX */ + + +/*---------------------------------------------------------------------- + * rfe_rfue + * + * Maps to RFUE on XEA1, and RFE on XEA2. No mapping on XEAX. + */ + +#if XCHAL_HAVE_XEA1 + .macro rfe_rfue + rfue + .endm +#elif XCHAL_HAVE_XEA2 + .macro rfe_rfue + rfe + .endm +#endif + + +/*---------------------------------------------------------------------- + * abi_entry + * + * Generate proper function entry sequence for the current ABI + * (windowed or call0). Takes care of allocating stack space (up to 1kB) + * and saving the return PC, if necessary. The corresponding abi_return + * macro does the corresponding stack deallocation and restoring return PC. + * + * Parameters are: + * + * locsize Number of bytes to allocate on the stack + * for local variables (and for args to pass to + * callees, if any calls are made). Defaults to zero. + * The macro rounds this up to a multiple of 16. + * NOTE: large values are allowed (e.g. up to 1 GB). + * + * callsize Maximum call size made by this function. + * Leave zero (default) for leaf functions, i.e. if + * this function makes no calls to other functions. + * Otherwise must be set to 4, 8, or 12 according + * to whether the "largest" call made is a call[x]4, + * call[x]8, or call[x]12 (for call0 ABI, it makes + * no difference whether this is set to 4, 8 or 12, + * but it must be set to one of these values). + * + * NOTE: It is up to the caller to align the entry point, declare the + * function symbol, make it global, etc. + * + * NOTE: This macro relies on assembler relaxation for large values + * of locsize. It might not work with the no-transform directive. + * NOTE: For the call0 ABI, this macro ensures SP is allocated or + * de-allocated cleanly, i.e. without temporarily allocating too much + * (or allocating negatively!) due to addi relaxation. + * + * NOTE: Generating the proper sequence and register allocation for + * making calls in an ABI independent manner is a separate topic not + * covered by this macro. + * + * NOTE: To access arguments, you can't use a fixed offset from SP. + * The offset depends on the ABI, whether the function is leaf, etc. + * The simplest method is probably to use the .locsz symbol, which + * is set by this macro to the actual number of bytes allocated on + * the stack, in other words, to the offset from SP to the arguments. + * E.g. for a function whose arguments are all 32-bit integers, you + * can get the 7th and 8th arguments (1st and 2nd args stored on stack) + * using: + * l32i a2, sp, .locsz + * l32i a3, sp, .locsz+4 + * (this example works as long as locsize is under L32I's offset limit + * of 1020 minus up to 48 bytes of ABI-specific stack usage; + * otherwise you might first need to do "addi a?, sp, .locsz" + * or similar sequence). + * + * NOTE: For call0 ABI, this macro (and abi_return) may clobber a9 + * (a caller-saved register). + * + * Examples: + * abi_entry + * abi_entry 5 + * abi_entry 22, 8 + * abi_entry 0, 4 + */ + + /* + * Compute .locsz and .callsz without emitting any instructions. + * Used by both abi_entry and abi_return. + * Assumes locsize >= 0. + */ + .macro abi_entry_size locsize=0, callsize=0 +#if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__ + .ifeq \callsize + .set .callsz, 16 + .else + .ifeq \callsize-4 + .set .callsz, 16 + .else + .ifeq \callsize-8 + .set .callsz, 32 + .else + .ifeq \callsize-12 + .set .callsz, 48 + .else + .error "abi_entry: invalid call size \callsize" + .endif + .endif + .endif + .endif + .set .locsz, .callsz + ((\locsize + 15) & -16) +#else + .set .callsz, \callsize + .if .callsz /* if calls, need space for return PC */ + .set .locsz, (\locsize + 4 + 15) & -16 + .else + .set .locsz, (\locsize + 15) & -16 + .endif +#endif + .endm + + .macro abi_entry locsize=0, callsize=0 + .iflt \locsize + .error "abi_entry: invalid negative size of locals (\locsize)" + .endif + abi_entry_size \locsize, \callsize +#if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__ + .ifgt .locsz - 32760 /* .locsz > 32760 (ENTRY's max range)? */ + /* Funky computation to try to have assembler use addmi efficiently if possible: */ + entry sp, 0x7F00 + (.locsz & 0xF0) + addi a12, sp, - ((.locsz & -0x100) - 0x7F00) + movsp sp, a12 + .else + entry sp, .locsz + .endif +#else + .if .locsz + .ifle .locsz - 128 /* if locsz <= 128 */ + addi sp, sp, -.locsz + .if .callsz + s32i a0, sp, .locsz - 4 + .endif + .elseif .callsz /* locsz > 128, with calls: */ + movi a9, .locsz - 16 /* note: a9 is caller-saved */ + addi sp, sp, -16 + s32i a0, sp, 12 + sub sp, sp, a9 + .else /* locsz > 128, no calls: */ + movi a9, .locsz + sub sp, sp, a9 + .endif /* end */ + .endif +#endif + .endm + + + +/*---------------------------------------------------------------------- + * abi_return + * + * Generate proper function exit sequence for the current ABI + * (windowed or call0). Takes care of freeing stack space and + * restoring the return PC, if necessary. + * NOTE: This macro MUST be invoked following a corresponding + * abi_entry macro invocation. For call0 ABI in particular, + * all stack and PC restoration are done according to the last + * abi_entry macro invoked before this macro in the assembly file. + * + * Normally this macro takes no arguments. However to allow + * for placing abi_return *before* abi_entry (as must be done + * for some highly optimized assembly), it optionally takes + * exactly the same arguments as abi_entry. + */ + + .macro abi_return locsize=-1, callsize=0 + .ifge \locsize + abi_entry_size \locsize, \callsize + .endif +#if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__ + retw +#else + .if .locsz + .iflt .locsz - 128 /* if locsz < 128 */ + .if .callsz + l32i a0, sp, .locsz - 4 + .endif + addi sp, sp, .locsz + .elseif .callsz /* locsz >= 128, with calls: */ + addi a9, sp, .locsz - 16 + l32i a0, a9, 12 + addi sp, a9, 16 + .else /* locsz >= 128, no calls: */ + movi a9, .locsz + add sp, sp, a9 + .endif /* end */ + .endif + ret +#endif + .endm + + +/* + * HW erratum fixes. + */ + + .macro hw_erratum_487_fix +#if defined XSHAL_ERRATUM_487_FIX + isync +#endif + .endm + + +#endif /*XTENSA_COREASM_H*/ + diff --git a/tools/sdk/include/esp32/xtensa/corebits.h b/tools/sdk/include/esp32/xtensa/corebits.h new file mode 100755 index 00000000..0ac0c801 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/corebits.h @@ -0,0 +1,185 @@ +/* + * xtensa/corebits.h - Xtensa Special Register field positions, masks, values. + * + * (In previous releases, these were defined in specreg.h, a generated file. + * This file is not generated, ie. it is processor configuration independent.) + */ + +/* $Id: //depot/rel/Eaglenest/Xtensa/OS/include/xtensa/corebits.h#2 $ */ + +/* + * Copyright (c) 2005-2011 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef XTENSA_COREBITS_H +#define XTENSA_COREBITS_H + +/* EXCCAUSE register fields: */ +#define EXCCAUSE_EXCCAUSE_SHIFT 0 +#define EXCCAUSE_EXCCAUSE_MASK 0x3F +/* EXCCAUSE register values: */ +/* + * General Exception Causes + * (values of EXCCAUSE special register set by general exceptions, + * which vector to the user, kernel, or double-exception vectors). + */ +#define EXCCAUSE_ILLEGAL 0 /* Illegal Instruction */ +#define EXCCAUSE_SYSCALL 1 /* System Call (SYSCALL instruction) */ +#define EXCCAUSE_INSTR_ERROR 2 /* Instruction Fetch Error */ +# define EXCCAUSE_IFETCHERROR 2 /* (backward compatibility macro, deprecated, avoid) */ +#define EXCCAUSE_LOAD_STORE_ERROR 3 /* Load Store Error */ +# define EXCCAUSE_LOADSTOREERROR 3 /* (backward compatibility macro, deprecated, avoid) */ +#define EXCCAUSE_LEVEL1_INTERRUPT 4 /* Level 1 Interrupt */ +# define EXCCAUSE_LEVEL1INTERRUPT 4 /* (backward compatibility macro, deprecated, avoid) */ +#define EXCCAUSE_ALLOCA 5 /* Stack Extension Assist (MOVSP instruction) for alloca */ +#define EXCCAUSE_DIVIDE_BY_ZERO 6 /* Integer Divide by Zero */ +#define EXCCAUSE_SPECULATION 7 /* Use of Failed Speculative Access (not implemented) */ +#define EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction */ +#define EXCCAUSE_UNALIGNED 9 /* Unaligned Load or Store */ +/* Reserved 10..11 */ +#define EXCCAUSE_INSTR_DATA_ERROR 12 /* PIF Data Error on Instruction Fetch (RB-200x and later) */ +#define EXCCAUSE_LOAD_STORE_DATA_ERROR 13 /* PIF Data Error on Load or Store (RB-200x and later) */ +#define EXCCAUSE_INSTR_ADDR_ERROR 14 /* PIF Address Error on Instruction Fetch (RB-200x and later) */ +#define EXCCAUSE_LOAD_STORE_ADDR_ERROR 15 /* PIF Address Error on Load or Store (RB-200x and later) */ +#define EXCCAUSE_ITLB_MISS 16 /* ITLB Miss (no ITLB entry matches, hw refill also missed) */ +#define EXCCAUSE_ITLB_MULTIHIT 17 /* ITLB Multihit (multiple ITLB entries match) */ +#define EXCCAUSE_INSTR_RING 18 /* Ring Privilege Violation on Instruction Fetch */ +/* Reserved 19 */ /* Size Restriction on IFetch (not implemented) */ +#define EXCCAUSE_INSTR_PROHIBITED 20 /* Cache Attribute does not allow Instruction Fetch */ +/* Reserved 21..23 */ +#define EXCCAUSE_DTLB_MISS 24 /* DTLB Miss (no DTLB entry matches, hw refill also missed) */ +#define EXCCAUSE_DTLB_MULTIHIT 25 /* DTLB Multihit (multiple DTLB entries match) */ +#define EXCCAUSE_LOAD_STORE_RING 26 /* Ring Privilege Violation on Load or Store */ +/* Reserved 27 */ /* Size Restriction on Load/Store (not implemented) */ +#define EXCCAUSE_LOAD_PROHIBITED 28 /* Cache Attribute does not allow Load */ +#define EXCCAUSE_STORE_PROHIBITED 29 /* Cache Attribute does not allow Store */ +/* Reserved 30..31 */ +#define EXCCAUSE_CP_DISABLED(n) (32+(n)) /* Access to Coprocessor 'n' when disabled */ +#define EXCCAUSE_CP0_DISABLED 32 /* Access to Coprocessor 0 when disabled */ +#define EXCCAUSE_CP1_DISABLED 33 /* Access to Coprocessor 1 when disabled */ +#define EXCCAUSE_CP2_DISABLED 34 /* Access to Coprocessor 2 when disabled */ +#define EXCCAUSE_CP3_DISABLED 35 /* Access to Coprocessor 3 when disabled */ +#define EXCCAUSE_CP4_DISABLED 36 /* Access to Coprocessor 4 when disabled */ +#define EXCCAUSE_CP5_DISABLED 37 /* Access to Coprocessor 5 when disabled */ +#define EXCCAUSE_CP6_DISABLED 38 /* Access to Coprocessor 6 when disabled */ +#define EXCCAUSE_CP7_DISABLED 39 /* Access to Coprocessor 7 when disabled */ +/* Reserved 40..63 */ + +/* PS register fields: */ +#define PS_WOE_SHIFT 18 +#define PS_WOE_MASK 0x00040000 +#define PS_WOE PS_WOE_MASK +#define PS_CALLINC_SHIFT 16 +#define PS_CALLINC_MASK 0x00030000 +#define PS_CALLINC(n) (((n)&3)< +#include +#include + +int xt_dbfs_open(const char *pathname, int flags, mode_t mode); +int xt_dbfs_ftruncate(int fd, off_t length); +int xt_dbfs_truncate(const char * filename, off_t length); +int xt_dbfs_creat(const char *pathname, mode_t mode); +int xt_dbfs_errno(void); +int xt_dbfs_lseek(int fd, off_t offset, int whence); +ssize_t xt_dbfs_write(int fd, const void * buf, size_t bytes); + ssize_t xt_dbfs_open_append_close(const char * filename, int align, + const void * buf, size_t bytes); +ssize_t xt_dbfs_read(int fd, void * buf, size_t bytes); +int xt_dbfs_close(int fd); +int xt_dbfs_unlink(const char *pathname); + +/* By default, this function is a wrapper around sbrk, and follows + sbrk semantics: + + On success, it returns increment bytes of memory allocated from + system memory. + + On failure, it returns 0xFFFFFFFF + + + If you want to use a method of allocating memory other than sbrk, + implement xt_dbfs_sbrk in your own sources, and the linker will + automatically use that copy. +*/ +void * xt_dbfs_sbrk(int increment); + + + +#ifdef REPLACE_FS_WITH_DBFS +#define open xt_dbfs_open +#define close xt_dbfs_close +#define creat xt_dbfs_creat +#define lseek xt_dbfs_lseek +#define write xt_dbfs_write +#define read xt_dbfs_read +#define close xt_dbfs_close +#define unlink xt_dbfs_unlink + +#define rmdir NOT_IMPLEMENTED_IN_DBFS +#define opendir NOT_IMPLEMENTED_IN_DBFS +#define closedir NOT_IMPLEMENTED_IN_DBFS +#define dirfs NOT_IMPLEMENTED_IN_DBFS +#define readdir NOT_IMPLEMENTED_IN_DBFS +#define scandir NOT_IMPLEMENTED_IN_DBFS +#define seekdir NOT_IMPLEMENTED_IN_DBFS +#define telldir NOT_IMPLEMENTED_IN_DBFS + +#define fcntl NOT_IMPLEMENTED_IN_DBFS +#define dup2 NOT_IMPLEMENTED_IN_DBFS +#define dup NOT_IMPLEMENTED_IN_DBFS +#define flock NOT_IMPLEMENTED_IN_DBFS +#define lockf NOT_IMPLEMENTED_IN_DBFS +#define link NOT_IMPLEMENTED_IN_DBFS +#define stat NOT_IMPLEMENTED_IN_DBFS +#define fstat NOT_IMPLEMENTED_IN_DBFS +#define lstat NOT_IMPLEMENTED_IN_DBFS +#define chmod NOT_IMPLEMENTED_IN_DBFS +#define fchmod NOT_IMPLEMENTED_IN_DBFS +#define chmown NOT_IMPLEMENTED_IN_DBFS +#define lchown NOT_IMPLEMENTED_IN_DBFS +#define fchown NOT_IMPLEMENTED_IN_DBFS + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/tools/sdk/include/esp32/xtensa/feedback.h b/tools/sdk/include/esp32/xtensa/feedback.h new file mode 100755 index 00000000..aecb7453 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/feedback.h @@ -0,0 +1,45 @@ + +/* + * Copyright (c) 2013 by Tensilica Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of Tensilica Inc. + * They may not be modified, copied, reproduced, distributed, or disclosed to + * third parties in any manner, medium, or form, in whole or in part, without + * the prior written consent of Tensilica Inc. + */ + +#ifndef __XT_FEEDBACK_INCLUDED__ +#define __XT_FEEDBACK_INCLUDED__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* xt_feedback_save_and_reset + + Save and reset the accumulated feedback data. +*/ +extern void xt_feedback_save_and_reset(void); + +/* xt_feedback_enable + + Turn on feedback accumulation. Ordinarily, feedback accumulation is on + by default. If you turn it off using xt_feedback_disable, You can turn + it on again via this function. +*/ +extern void xt_feedback_enable (void); + +/* xt_feedback_disable + + Turn off feedback accumulation. If you don't want to gather feedback for a + portion of your code, use this function and then xt_feedback_enable when + you want to start again. +*/ +extern void xt_feedback_disable (void); + +#ifdef __cplusplus +} +#endif + +#endif /* __XT_FEEDBACK_INCLUDED__ */ + diff --git a/tools/sdk/include/esp32/xtensa/gdbio.h b/tools/sdk/include/esp32/xtensa/gdbio.h new file mode 100755 index 00000000..784a8629 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/gdbio.h @@ -0,0 +1,80 @@ +/* Xtensa Debug-FileSystem definitions + * + * Copyright (c) 2006-2009 by Tensilica Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of Tensilica Inc. + * They may not be modified, copied, reproduced, distributed, or disclosed to + * third parties in any manner, medium, or form, in whole or in part, without + * the prior written consent of Tensilica Inc. + */ + +#ifndef __DEBUGFS_H__ +#define __DEBUGFS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include + + int _gdbio_open_r(void * ptr, const char *pathname, int flags, mode_t mode); + int _gdbio_creat_r(void * ptr, const char *pathname, mode_t mode); + int _gdbio_lseek_r(void * ptr, int fd, off_t offset, int whence); + ssize_t _gdbio_write_r(void * ptr, int fd, const void * buf, size_t bytes); + ssize_t _gdbio_read_r(void * ptr, int fd, void * buf, size_t bytes); + int _gdbio_close_r(void * ptr, int fd); + int _gdbio_unlink_r(void * ptr, const char * pathname); + + static inline + int gdbio_open(const char *pathname, int flags, mode_t mode) { + return _gdbio_open_r(&errno, pathname, flags, mode); + } + static inline int + gdbio_creat(const char *pathname, mode_t mode) { + return _gdbio_open_r(&errno, pathname, O_CREAT|O_WRONLY|O_TRUNC, mode); + } + static inline int + gdbio_errno(void) { + return errno; + } + static inline int + gdbio_lseek(int fd, off_t offset, int whence) { + return _gdbio_lseek_r(&errno, fd, offset, whence); + } + static inline + ssize_t gdbio_write(int fd, const void * buf, size_t bytes) { + return _gdbio_write_r(&errno, fd, buf, bytes); + } + static inline + ssize_t gdbio_read(int fd, void * buf, size_t bytes) { + return _gdbio_read_r(&errno, fd, buf, bytes); + } + static inline int + gdbio_close(int fd) { + return _gdbio_close_r(&errno, fd); + } + static inline int + gdbio_unlink(const char * pathname) { + return _gdbio_unlink_r(&errno, pathname); + } + +#ifdef REPLACE_FS_WITH_GDBIO +#define open gdbio_open +#define close gdbio_close +#define creat gdbio_creat +#define lseek gdbio_lseek +#define write gdbio_write +#define read gdbio_read +#define close gdbio_close +#define unlink gdbio_unlink + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/tools/sdk/include/esp32/xtensa/hal.h b/tools/sdk/include/esp32/xtensa/hal.h new file mode 100755 index 00000000..d4d95d9f --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/hal.h @@ -0,0 +1,1024 @@ +/* + xtensa/hal.h -- contains a definition of the Core HAL interface + + All definitions in this header file are independent of any specific + Xtensa processor configuration. Thus software (eg. OS, application, + etc) can include this header file and be compiled into configuration- + independent objects that can be distributed and eventually linked + to the HAL library (libhal.a) to create a configuration-specific + final executable. + + Certain definitions, however, are release/version-specific -- such as + the XTHAL_RELEASE_xxx macros (or additions made in later versions). + + + $Id: //depot/rel/Eaglenest/Xtensa/OS/target-os-src/hal.h.tpp#4 $ + + Copyright (c) 1999-2014 Cadence Design Systems, Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + +#ifndef XTENSA_HAL_H +#define XTENSA_HAL_H + + +/**************************************************************************** + Definitions Useful for Any Code, USER or PRIVILEGED + ****************************************************************************/ + + +/*---------------------------------------------------------------------- + Constant Definitions (shared with assembly) + ----------------------------------------------------------------------*/ + +/* + * Software (Xtensa Tools) version information. Not configuration-specific! + * + * NOTE: "release" is a misnomer here, these are really product "version" + * numbers. A "release" is a collection of product versions + * made available at once (together) to customers. + * In the past, release and version names all matched in T####.# form, + * making the distinction irrelevant. This is no longer the case. + */ +#define XTHAL_RELEASE_MAJOR 11000 +#define XTHAL_RELEASE_MINOR 3 +#define XTHAL_RELEASE_NAME "11.0.3" +#define XTHAL_REL_11 1 +#define XTHAL_REL_11_0 1 +#define XTHAL_REL_11_0_3 1 + +/* HAL version numbers (these names are for backward compatibility): */ +#define XTHAL_MAJOR_REV XTHAL_RELEASE_MAJOR +#define XTHAL_MINOR_REV XTHAL_RELEASE_MINOR +/* + * A bit of software release/version history on values of XTHAL_{MAJOR,MINOR}_REV: + * + * SW Version MAJOR MINOR Comment + * ======= ===== ===== ======= + * T1015.n n/a n/a (HAL not yet available) + * T1020.{0,1,2} 0 1 (HAL beta) + * T1020.{3,4} 0 2 First release. + * T1020.n (n>4) 0 2 or >3 (TBD) + * T1030.0 0 1 (HAL beta) + * T1030.{1,2} 0 3 Equivalent to first release. + * T1030.n (n>=3) 0 >= 3 (TBD) + * T1040.n 1040 n Full CHAL available from T1040.2 + * T1050.n 1050 n . + * 6.0.n 6000 n Xtensa Tools v6 (RA-200x.n) + * 7.0.n 7000 n Xtensa Tools v7 (RB-200x.n) + * 7.1.n 7010 n Xtensa Tools v7.1 (RB-200x.(n+2)) + * 8.0.n 8000 n Xtensa Tools v8 (RC-20xx.n) + * 9.0.n 9000 n Xtensa Tools v9 (RD-201x.n) + * 10.0.n 10000 n Xtensa Tools v10 (RE-201x.n) + * + * + * Note: there is a distinction between the software version with + * which something is compiled (accessible using XTHAL_RELEASE_* macros) + * and the software version with which the HAL library was compiled + * (accessible using Xthal_release_* global variables). This + * distinction is particularly relevant for vendors that distribute + * configuration-independent binaries (eg. an OS), where their customer + * might link it with a HAL of a different Xtensa software version. + * In this case, it may be appropriate for the OS to verify at run-time + * whether XTHAL_RELEASE_* and Xthal_release_* are compatible. + * [Guidelines as to which version is compatible with which are not + * currently provided explicitly, but might be inferred from reading + * OSKit documentation for all releases -- compatibility is also highly + * dependent on which HAL features are used. Each version is usually + * backward compatible, with very few exceptions if any.] + */ + +/* Version comparison operators (among major/minor pairs): */ +#define XTHAL_REL_GE(maja,mina, majb,minb) ((maja) > (majb) || \ + ((maja) == (majb) && (mina) >= (minb))) +#define XTHAL_REL_GT(maja,mina, majb,minb) ((maja) > (majb) || \ + ((maja) == (majb) && (mina) > (minb))) +#define XTHAL_REL_LE(maja,mina, majb,minb) ((maja) < (majb) || \ + ((maja) == (majb) && (mina) <= (minb))) +#define XTHAL_REL_LT(maja,mina, majb,minb) ((maja) < (majb) || \ + ((maja) == (majb) && (mina) < (minb))) +#define XTHAL_REL_EQ(maja,mina, majb,minb) ((maja) == (majb) && (mina) == (minb)) + +/* Fuzzy (3-way) logic operators: */ +#define XTHAL_MAYBE -1 /* 0=NO, 1=YES, -1=MAYBE */ +#define XTHAL_FUZZY_AND(a,b) (((a)==0 || (b)==0) ? 0 : ((a)==1 && (b)==1) ? 1 : XTHAL_MAYBE) +#define XTHAL_FUZZY_OR(a,b) (((a)==1 || (b)==1) ? 1 : ((a)==0 && (b)==0) ? 0 : XTHAL_MAYBE) +#define XTHAL_FUZZY_NOT(a) (((a)==0 || (a)==1) ? (1-(a)) : XTHAL_MAYBE) + + +/* + * Architectural limit, independent of configuration: + */ +#define XTHAL_MAX_CPS 8 /* max number of coprocessors (0..7) */ + +/* Misc: */ +#define XTHAL_LITTLEENDIAN 0 +#define XTHAL_BIGENDIAN 1 + + + +#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__) +#ifdef __cplusplus +extern "C" { +#endif + +/*---------------------------------------------------------------------- + HAL + ----------------------------------------------------------------------*/ + +/* Constant to be checked in build = (XTHAL_MAJOR_REV<<16)|XTHAL_MINOR_REV */ +extern const unsigned int Xthal_rev_no; + + +/*---------------------------------------------------------------------- + Optional/Custom Processor State + ----------------------------------------------------------------------*/ + +/* save & restore the extra processor state */ +extern void xthal_save_extra(void *base); +extern void xthal_restore_extra(void *base); + +extern void xthal_save_cpregs(void *base, int); +extern void xthal_restore_cpregs(void *base, int); +/* versions specific to each coprocessor id */ +extern void xthal_save_cp0(void *base); +extern void xthal_save_cp1(void *base); +extern void xthal_save_cp2(void *base); +extern void xthal_save_cp3(void *base); +extern void xthal_save_cp4(void *base); +extern void xthal_save_cp5(void *base); +extern void xthal_save_cp6(void *base); +extern void xthal_save_cp7(void *base); +extern void xthal_restore_cp0(void *base); +extern void xthal_restore_cp1(void *base); +extern void xthal_restore_cp2(void *base); +extern void xthal_restore_cp3(void *base); +extern void xthal_restore_cp4(void *base); +extern void xthal_restore_cp5(void *base); +extern void xthal_restore_cp6(void *base); +extern void xthal_restore_cp7(void *base); +/* pointers to each of the functions above */ +extern void* Xthal_cpregs_save_fn[XTHAL_MAX_CPS]; +extern void* Xthal_cpregs_restore_fn[XTHAL_MAX_CPS]; +/* similarly for non-windowed ABI (may be same or different) */ +extern void* Xthal_cpregs_save_nw_fn[XTHAL_MAX_CPS]; +extern void* Xthal_cpregs_restore_nw_fn[XTHAL_MAX_CPS]; + +/*extern void xthal_save_all_extra(void *base);*/ +/*extern void xthal_restore_all_extra(void *base);*/ + +/* space for processor state */ +extern const unsigned int Xthal_extra_size; +extern const unsigned int Xthal_extra_align; +extern const unsigned int Xthal_cpregs_size[XTHAL_MAX_CPS]; +extern const unsigned int Xthal_cpregs_align[XTHAL_MAX_CPS]; +extern const unsigned int Xthal_all_extra_size; +extern const unsigned int Xthal_all_extra_align; +/* coprocessor names */ +extern const char * const Xthal_cp_names[XTHAL_MAX_CPS]; + +/* initialize the extra processor */ +/*extern void xthal_init_extra(void);*/ +/* initialize the TIE coprocessor */ +/*extern void xthal_init_cp(int);*/ + +/* initialize the extra processor */ +extern void xthal_init_mem_extra(void *); +/* initialize the TIE coprocessor */ +extern void xthal_init_mem_cp(void *, int); + +/* the number of TIE coprocessors contiguous from zero (for Tor2) */ +extern const unsigned int Xthal_num_coprocessors; + +/* actual number of coprocessors */ +extern const unsigned char Xthal_cp_num; +/* index of highest numbered coprocessor, plus one */ +extern const unsigned char Xthal_cp_max; +/* index of highest allowed coprocessor number, per cfg, plus one */ +/*extern const unsigned char Xthal_cp_maxcfg;*/ +/* bitmask of which coprocessors are present */ +extern const unsigned int Xthal_cp_mask; + +/* read & write extra state register */ +/*extern int xthal_read_extra(void *base, unsigned reg, unsigned *value);*/ +/*extern int xthal_write_extra(void *base, unsigned reg, unsigned value);*/ + +/* read & write a TIE coprocessor register */ +/*extern int xthal_read_cpreg(void *base, int cp, unsigned reg, unsigned *value);*/ +/*extern int xthal_write_cpreg(void *base, int cp, unsigned reg, unsigned value);*/ + +/* return coprocessor number based on register */ +/*extern int xthal_which_cp(unsigned reg);*/ + + +/*---------------------------------------------------------------------- + Register Windows + ----------------------------------------------------------------------*/ + +/* number of registers in register window */ +extern const unsigned int Xthal_num_aregs; +extern const unsigned char Xthal_num_aregs_log2; + + +/*---------------------------------------------------------------------- + Cache + ----------------------------------------------------------------------*/ + +/* size of the cache lines in log2(bytes) */ +extern const unsigned char Xthal_icache_linewidth; +extern const unsigned char Xthal_dcache_linewidth; +/* size of the cache lines in bytes (2^linewidth) */ +extern const unsigned short Xthal_icache_linesize; +extern const unsigned short Xthal_dcache_linesize; + +/* size of the caches in bytes (ways * 2^(linewidth + setwidth)) */ +extern const unsigned int Xthal_icache_size; +extern const unsigned int Xthal_dcache_size; +/* cache features */ +extern const unsigned char Xthal_dcache_is_writeback; + +/* invalidate the caches */ + +extern void xthal_icache_region_invalidate( void *addr, unsigned size ); +extern void xthal_dcache_region_invalidate( void *addr, unsigned size ); +# ifndef XTHAL_USE_CACHE_MACROS +extern void xthal_icache_line_invalidate(void *addr); +extern void xthal_dcache_line_invalidate(void *addr); +# endif +/* write dirty data back */ +extern void xthal_dcache_region_writeback( void *addr, unsigned size ); +# ifndef XTHAL_USE_CACHE_MACROS +extern void xthal_dcache_line_writeback(void *addr); +# endif +/* write dirty data back and invalidate */ +extern void xthal_dcache_region_writeback_inv( void *addr, unsigned size ); +# ifndef XTHAL_USE_CACHE_MACROS +extern void xthal_dcache_line_writeback_inv(void *addr); +/* sync icache and memory */ +extern void xthal_icache_sync( void ); +/* sync dcache and memory */ +extern void xthal_dcache_sync( void ); +#endif + +/* get number of icache ways enabled */ +extern unsigned int xthal_icache_get_ways(void); +/* set number of icache ways enabled */ +extern void xthal_icache_set_ways(unsigned int ways); +/* get number of dcache ways enabled */ +extern unsigned int xthal_dcache_get_ways(void); +/* set number of dcache ways enabled */ +extern void xthal_dcache_set_ways(unsigned int ways); + +/* coherency (low-level -- not normally called directly) */ +extern void xthal_cache_coherence_on( void ); +extern void xthal_cache_coherence_off( void ); +/* coherency (high-level) */ +extern void xthal_cache_coherence_optin( void ); +extern void xthal_cache_coherence_optout( void ); + +/* + * Cache prefetch control. + * The parameter to xthal_set_cache_prefetch() contains both + * a PREFCTL register value and a mask of which bits to actually modify. + * This allows easily combining field macros (below) by ORing, + * leaving unspecified fields unmodified. + * + * For backward compatibility with the older version of this routine + * (that took 15-bit value and mask in a 32-bit parameter, for pre-RF + * cores with only the lower 15 bits of PREFCTL defined), the 32-bit + * value and mask are staggered as follows in a 64-bit parameter: + * param[63:48] are PREFCTL[31:16] if param[31] is set + * param[47:32] are mask[31:16] if param[31] is set + * param[31] is set if mask is used, 0 if not + * param[31:16] are mask[15:0] if param[31] is set + * param[31:16] are PREFCTL[31:16] if param[31] is clear + * param[15:0] are PREFCTL[15:0] + * + * Limitation: PREFCTL register bit 31 cannot be set without masking, + * and bit 15 must always be set when using masking, so it is hoped that + * these two bits will remain reserved, read-as-zero in PREFCTL. + */ +#define XTHAL_PREFETCH_ENABLE -1 /* enable inst+data prefetch */ +#define XTHAL_PREFETCH_DISABLE 0xFFFF0000 /* disab inst+data prefetch*/ +#define XTHAL_DCACHE_PREFETCH(n) (0x800F0000+((n)&0xF)) /* data-side */ +#define XTHAL_DCACHE_PREFETCH_OFF XTHAL_DCACHE_PREFETCH(0) /* disable */ +#define XTHAL_DCACHE_PREFETCH_LOW XTHAL_DCACHE_PREFETCH(4) /* less aggr.*/ +#define XTHAL_DCACHE_PREFETCH_MEDIUM XTHAL_DCACHE_PREFETCH(5) /* mid aggr. */ +#define XTHAL_DCACHE_PREFETCH_HIGH XTHAL_DCACHE_PREFETCH(8) /* more aggr.*/ +#define XTHAL_DCACHE_PREFETCH_L1_OFF 0x90000000 /* to prefetch buffers*/ +#define XTHAL_DCACHE_PREFETCH_L1 0x90001000 /* direct to L1 dcache*/ +#define XTHAL_ICACHE_PREFETCH(n) (0x80F00000+(((n)&0xF)<<4)) /* i-side */ +#define XTHAL_ICACHE_PREFETCH_OFF XTHAL_ICACHE_PREFETCH(0) /* disable */ +#define XTHAL_ICACHE_PREFETCH_LOW XTHAL_ICACHE_PREFETCH(4) /* less aggr.*/ +#define XTHAL_ICACHE_PREFETCH_MEDIUM XTHAL_ICACHE_PREFETCH(5) /* mid aggr. */ +#define XTHAL_ICACHE_PREFETCH_HIGH XTHAL_ICACHE_PREFETCH(8) /* more aggr.*/ +#define XTHAL_ICACHE_PREFETCH_L1_OFF 0xA0000000 /* (not implemented) */ +#define XTHAL_ICACHE_PREFETCH_L1 0xA0002000 /* (not implemented) */ +#define _XTHAL_PREFETCH_BLOCKS(n) ((n)<0?0:(n)<5?(n):(n)<15?((n)>>1)+2:9) +#define XTHAL_PREFETCH_BLOCKS(n) (0x0000000F80000000ULL + \ + (((unsigned long long)_XTHAL_PREFETCH_BLOCKS(n))<<48)) + +extern int xthal_get_cache_prefetch( void ); +extern int xthal_set_cache_prefetch( int ); +extern int xthal_set_cache_prefetch_long( unsigned long long ); +/* Only use the new extended function from now on: */ +#define xthal_set_cache_prefetch xthal_set_cache_prefetch_long +#define xthal_set_cache_prefetch_nw xthal_set_cache_prefetch_long_nw + + +/*---------------------------------------------------------------------- + Debug + ----------------------------------------------------------------------*/ + +/* 1 if debug option configured, 0 if not: */ +extern const int Xthal_debug_configured; + +/* Set (plant) and remove software breakpoint, both synchronizing cache: */ +extern unsigned int xthal_set_soft_break(void *addr); +extern void xthal_remove_soft_break(void *addr, unsigned int); + + +/*---------------------------------------------------------------------- + Disassembler + ----------------------------------------------------------------------*/ + +/* Max expected size of the return buffer for a disassembled instruction (hint only): */ +#define XTHAL_DISASM_BUFSIZE 80 + +/* Disassembly option bits for selecting what to return: */ +#define XTHAL_DISASM_OPT_ADDR 0x0001 /* display address */ +#define XTHAL_DISASM_OPT_OPHEX 0x0002 /* display opcode bytes in hex */ +#define XTHAL_DISASM_OPT_OPCODE 0x0004 /* display opcode name (mnemonic) */ +#define XTHAL_DISASM_OPT_PARMS 0x0008 /* display parameters */ +#define XTHAL_DISASM_OPT_ALL 0x0FFF /* display everything */ + +/* routine to get a string for the disassembled instruction */ +extern int xthal_disassemble( unsigned char *instr_buf, void *tgt_addr, + char *buffer, unsigned buflen, unsigned options ); + +/* routine to get the size of the next instruction. Returns 0 for + illegal instruction */ +extern int xthal_disassemble_size( unsigned char *instr_buf ); + + +/*---------------------------------------------------------------------- + Instruction/Data RAM/ROM Access + ----------------------------------------------------------------------*/ + +extern void* xthal_memcpy(void *dst, const void *src, unsigned len); +extern void* xthal_bcopy(const void *src, void *dst, unsigned len); + + +/*---------------------------------------------------------------------- + MP Synchronization + ----------------------------------------------------------------------*/ + +extern int xthal_compare_and_set( int *addr, int test_val, int compare_val ); + +/*extern const char Xthal_have_s32c1i;*/ + + +/*---------------------------------------------------------------------- + Miscellaneous + ----------------------------------------------------------------------*/ + +extern const unsigned int Xthal_release_major; +extern const unsigned int Xthal_release_minor; +extern const char * const Xthal_release_name; +extern const char * const Xthal_release_internal; + +extern const unsigned char Xthal_memory_order; +extern const unsigned char Xthal_have_windowed; +extern const unsigned char Xthal_have_density; +extern const unsigned char Xthal_have_booleans; +extern const unsigned char Xthal_have_loops; +extern const unsigned char Xthal_have_nsa; +extern const unsigned char Xthal_have_minmax; +extern const unsigned char Xthal_have_sext; +extern const unsigned char Xthal_have_clamps; +extern const unsigned char Xthal_have_mac16; +extern const unsigned char Xthal_have_mul16; +extern const unsigned char Xthal_have_fp; +extern const unsigned char Xthal_have_speculation; +extern const unsigned char Xthal_have_threadptr; + +extern const unsigned char Xthal_have_pif; +extern const unsigned short Xthal_num_writebuffer_entries; + +extern const unsigned int Xthal_build_unique_id; +/* Version info for hardware targeted by software upgrades: */ +extern const unsigned int Xthal_hw_configid0; +extern const unsigned int Xthal_hw_configid1; +extern const unsigned int Xthal_hw_release_major; +extern const unsigned int Xthal_hw_release_minor; +extern const char * const Xthal_hw_release_name; +extern const char * const Xthal_hw_release_internal; + +/* Clear any remnant code-dependent state (i.e. clear loop count regs). */ +extern void xthal_clear_regcached_code( void ); + +#ifdef __cplusplus +} +#endif +#endif /*!_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */ + + + + + +/**************************************************************************** + Definitions Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code + ****************************************************************************/ + + +#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY + +/*---------------------------------------------------------------------- + Constant Definitions (shared with assembly) + ----------------------------------------------------------------------*/ + +/* + * Architectural limits, independent of configuration. + * Note that these are ISA-defined limits, not micro-architecture implementation + * limits enforced by the Xtensa Processor Generator (which may be stricter than + * these below). + */ +#define XTHAL_MAX_INTERRUPTS 32 /* max number of interrupts (0..31) */ +#define XTHAL_MAX_INTLEVELS 16 /* max number of interrupt levels (0..15) */ + /* (as of T1040, implementation limit is 7: 0..6) */ +#define XTHAL_MAX_TIMERS 4 /* max number of timers (CCOMPARE0..CCOMPARE3) */ + /* (as of T1040, implementation limit is 3: 0..2) */ + +/* Interrupt types: */ +#define XTHAL_INTTYPE_UNCONFIGURED 0 +#define XTHAL_INTTYPE_SOFTWARE 1 +#define XTHAL_INTTYPE_EXTERN_EDGE 2 +#define XTHAL_INTTYPE_EXTERN_LEVEL 3 +#define XTHAL_INTTYPE_TIMER 4 +#define XTHAL_INTTYPE_NMI 5 +#define XTHAL_INTTYPE_WRITE_ERROR 6 +#define XTHAL_INTTYPE_PROFILING 7 +#define XTHAL_MAX_INTTYPES 8 /* number of interrupt types */ + +/* Timer related: */ +#define XTHAL_TIMER_UNCONFIGURED -1 /* Xthal_timer_interrupt[] value for non-existent timers */ +#define XTHAL_TIMER_UNASSIGNED XTHAL_TIMER_UNCONFIGURED /* (for backwards compatibility only) */ + +/* Local Memory ECC/Parity: */ +#define XTHAL_MEMEP_PARITY 1 +#define XTHAL_MEMEP_ECC 2 +/* Flags parameter to xthal_memep_inject_error(): */ +#define XTHAL_MEMEP_F_LOCAL 0 /* local memory (default) */ +#define XTHAL_MEMEP_F_DCACHE_DATA 4 /* data cache data */ +#define XTHAL_MEMEP_F_DCACHE_TAG 5 /* data cache tag */ +#define XTHAL_MEMEP_F_ICACHE_DATA 6 /* instruction cache data */ +#define XTHAL_MEMEP_F_ICACHE_TAG 7 /* instruction cache tag */ +#define XTHAL_MEMEP_F_CORRECTABLE 16 /* inject correctable error + (default is non-corr.) */ + + +/* Access Mode bits (tentative): */ /* bit abbr unit short_name PPC equ - Description */ +#define XTHAL_AMB_EXCEPTION 0 /* 001 E EX fls: EXception none + exception on any access (aka "illegal") */ +#define XTHAL_AMB_HITCACHE 1 /* 002 C CH fls: use Cache on Hit ~(I CI) + [or H HC] way from tag match; + [or U UC] (ISA: same except Isolate case) */ +#define XTHAL_AMB_ALLOCATE 2 /* 004 A AL fl?: ALlocate none + [or F FI fill] refill cache on miss, way from LRU + (ISA: Read/Write Miss Refill) */ +#define XTHAL_AMB_WRITETHRU 3 /* 008 W WT --s: WriteThrough W WT + store immediately to memory (ISA: same) */ +#define XTHAL_AMB_ISOLATE 4 /* 010 I IS fls: ISolate none + use cache regardless of hit-vs-miss, + way from vaddr (ISA: use-cache-on-miss+hit) */ +#define XTHAL_AMB_GUARD 5 /* 020 G GU ?l?: GUard G * + non-speculative; spec/replay refs not permitted */ +#define XTHAL_AMB_COHERENT 6 /* 040 M MC ?ls: Mem/MP Coherent M + on read, other CPU/bus-master may need to supply data; + on write, maybe redirect to or flush other CPU dirty line; etc */ +#if 0 +#define XTHAL_AMB_BUFFERABLE x /* 000 B BU --s: BUfferable ? + write response may return earlier than from final destination */ +#define XTHAL_AMB_ORDERED x /* 000 O OR fls: ORdered G * + mem accesses cannot be out of order */ +#define XTHAL_AMB_FUSEWRITES x /* 000 F FW --s: FuseWrites none + allow combining/merging/coalescing multiple writes + (to same datapath data unit) into one + (implied by writeback) */ +#define XTHAL_AMB_TRUSTED x /* 000 T TR ?l?: TRusted none + memory will not bus error (if it does, + handle as fatal imprecise interrupt) */ +#define XTHAL_AMB_PREFETCH x /* 000 P PR fl?: PRefetch none + on refill, read line+1 into prefetch buffers */ +#define XTHAL_AMB_STREAM x /* 000 S ST ???: STreaming none + access one of N stream buffers */ +#endif /*0*/ + +#define XTHAL_AM_EXCEPTION (1< = bit is set + * '-' = bit is clear + * '.' = bit is irrelevant / don't care, as follows: + * E=1 makes all others irrelevant + * W,F relevant only for stores + * "2345" + * Indicates which Xtensa releases support the corresponding + * access mode. Releases for each character column are: + * 2 = prior to T1020.2: T1015 (V1.5), T1020.0, T1020.1 + * 3 = T1020.2 and later: T1020.2+, T1030 + * 4 = T1040 + * 5 = T1050 (maybe), LX1, LX2, LX2.1 + * 7 = LX2.2 + * 8 = LX3, LX4 + * 9 = LX5 + * And the character column contents are: + * = supported by release(s) + * "." = unsupported by release(s) + * "?" = support unknown + */ + /* foMGIWACE 2345789 */ +/* For instruction fetch: */ +#define XTHAL_FAM_EXCEPTION 0x001 /* ........E 2345789 exception */ +/*efine XTHAL_FAM_ISOLATE*/ /*0x012*/ /* .---I.-C- ....... isolate */ +#define XTHAL_FAM_BYPASS 0x000 /* .----.--- 2345789 bypass */ +/*efine XTHAL_FAM_NACACHED*/ /*0x002*/ /* .----.-C- ....... cached no-allocate (frozen) */ +#define XTHAL_FAM_CACHED 0x006 /* .----.AC- 2345789 cached */ +/* For data load: */ +#define XTHAL_LAM_EXCEPTION 0x001 /* ........E 2345789 exception */ +#define XTHAL_LAM_ISOLATE 0x012 /* .---I.-C- 2345789 isolate */ +#define XTHAL_LAM_BYPASS 0x000 /* .O---.--- 2...... bypass speculative */ +#define XTHAL_LAM_BYPASSG 0x020 /* .O-G-.--- .345789 bypass guarded */ +#define XTHAL_LAM_CACHED_NOALLOC 0x002 /* .O---.-C- 2345789 cached no-allocate speculative */ +#define XTHAL_LAM_NACACHED XTHAL_LAM_CACHED_NOALLOC +#define XTHAL_LAM_NACACHEDG 0x022 /* .O-G-.-C- .?..... cached no-allocate guarded */ +#define XTHAL_LAM_CACHED 0x006 /* .----.AC- 2345789 cached speculative */ +#define XTHAL_LAM_COHCACHED 0x046 /* .-M--.AC- ....*89 cached speculative MP-coherent */ +/* For data store: */ +#define XTHAL_SAM_EXCEPTION 0x001 /* ........E 2345789 exception */ +#define XTHAL_SAM_ISOLATE 0x032 /* .--GI--C- 2345789 isolate */ +#define XTHAL_SAM_BYPASS 0x028 /* -O-G-W--- 2345789 bypass */ +#define XTHAL_SAM_WRITETHRU 0x02A /* -O-G-W-C- 2345789 writethrough */ +/*efine XTHAL_SAM_WRITETHRU_ALLOC*/ /*0x02E*/ /* -O-G-WAC- ....... writethrough allocate */ +#define XTHAL_SAM_WRITEBACK 0x026 /* F--G--AC- ...5789 writeback */ +#define XTHAL_SAM_WRITEBACK_NOALLOC 0x022 /* ?--G---C- .....89 writeback no-allocate */ +#define XTHAL_SAM_COHWRITEBACK 0x066 /* F-MG--AC- ....*89 writeback MP-coherent */ +/* For PIF attributes: */ /* -PIwrWCBUUUU ...9 */ +#define XTHAL_PAM_BYPASS 0x000 /* xxx00000xxxx ...9 bypass non-bufferable */ +#define XTHAL_PAM_BYPASS_BUF 0x010 /* xxx0000bxxxx ...9 bypass */ +#define XTHAL_PAM_CACHED_NOALLOC 0x030 /* xxx0001bxxxx ...9 cached no-allocate */ +#define XTHAL_PAM_WRITETHRU 0x0B0 /* xxx0101bxxxx ...9 writethrough (WT) */ +#define XTHAL_PAM_WRITEBACK_NOALLOC 0x0F0 /* xxx0111bxxxx ...9 writeback no-alloc (WBNA) */ +#define XTHAL_PAM_WRITEBACK 0x1F0 /* xxx1111bxxxx ...9 writeback (WB) */ +/*efine XTHAL_PAM_NORMAL*/ /*0x050*/ /* xxx0010bxxxx .... (unimplemented) */ +/*efine XTHAL_PAM_WRITETHRU_WA*/ /*0x130*/ /* xxx1001bxxxx .... (unimplemented, less likely) */ +/*efine XTHAL_PAM_WRITETHRU_RWA*/ /*0x1B0*/ /* xxx1101bxxxx .... (unimplemented, less likely) */ +/*efine XTHAL_PAM_WRITEBACK_WA*/ /*0x170*/ /* xxx1011bxxxx .... (unimplemented, less likely) */ + + +#if 0 +/* + Cache attribute encoding for CACHEATTR (per ISA): + (Note: if this differs from ISA Ref Manual, ISA has precedence) + + Inst-fetches Loads Stores + ------------- ------------ ------------- +0x0 FCA_EXCEPTION LCA_NACACHED SCA_WRITETHRU cached no-allocate (previously misnamed "uncached") +0x1 FCA_CACHED LCA_CACHED SCA_WRITETHRU cached +0x2 FCA_BYPASS LCA_BYPASS_G* SCA_BYPASS bypass cache (what most people call uncached) +0x3 FCA_CACHED LCA_CACHED SCA_WRITEALLOCF write-allocate + or LCA_EXCEPTION SCA_EXCEPTION (if unimplemented) +0x4 FCA_CACHED LCA_CACHED SCA_WRITEBACK[M] write-back [MP-coherent] + or LCA_EXCEPTION SCA_EXCEPTION (if unimplemented) +0x5 FCA_CACHED LCA_CACHED SCA_WRITEBACK_NOALLOC write-back no-allocate + or FCA_EXCEPTION LCA_EXCEPTION SCA_EXCEPTION (if unimplemented) +0x6..D FCA_EXCEPTION LCA_EXCEPTION SCA_EXCEPTION (reserved) +0xE FCA_EXCEPTION LCA_ISOLATE SCA_ISOLATE isolate +0xF FCA_EXCEPTION LCA_EXCEPTION SCA_EXCEPTION illegal + * Prior to T1020.2?, guard feature not supported, this defaulted to speculative (no _G) +*/ +#endif /*0*/ + + +#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__) +#ifdef __cplusplus +extern "C" { +#endif + + +/*---------------------------------------------------------------------- + Register Windows + ----------------------------------------------------------------------*/ + +/* This spill any live register windows (other than the caller's): + * (NOTE: current implementation require privileged code, but + * a user-callable implementation is possible.) */ +extern void xthal_window_spill( void ); + + +/*---------------------------------------------------------------------- + Optional/Custom Processor State + ----------------------------------------------------------------------*/ + +/* validate & invalidate the TIE register file */ +extern void xthal_validate_cp(int); +extern void xthal_invalidate_cp(int); + +/* read and write cpenable register */ +extern void xthal_set_cpenable(unsigned); +extern unsigned xthal_get_cpenable(void); + + +/*---------------------------------------------------------------------- + Interrupts + ----------------------------------------------------------------------*/ + +/* the number of interrupt levels */ +extern const unsigned char Xthal_num_intlevels; +/* the number of interrupts */ +extern const unsigned char Xthal_num_interrupts; +/* the highest level of interrupts masked by PS.EXCM */ +extern const unsigned char Xthal_excm_level; + +/* mask for level of interrupts */ +extern const unsigned int Xthal_intlevel_mask[XTHAL_MAX_INTLEVELS]; +/* mask for level 0 to N interrupts */ +extern const unsigned int Xthal_intlevel_andbelow_mask[XTHAL_MAX_INTLEVELS]; + +/* level of each interrupt */ +extern const unsigned char Xthal_intlevel[XTHAL_MAX_INTERRUPTS]; + +/* type per interrupt */ +extern const unsigned char Xthal_inttype[XTHAL_MAX_INTERRUPTS]; + +/* masks of each type of interrupt */ +extern const unsigned int Xthal_inttype_mask[XTHAL_MAX_INTTYPES]; + +/* interrupt numbers assigned to each timer interrupt */ +extern const int Xthal_timer_interrupt[XTHAL_MAX_TIMERS]; + +/* INTENABLE,INTERRUPT,INTSET,INTCLEAR register access functions: */ +extern unsigned xthal_get_intenable( void ); +extern void xthal_set_intenable( unsigned ); +extern unsigned xthal_get_interrupt( void ); +#define xthal_get_intread xthal_get_interrupt /* backward compatibility */ +extern void xthal_set_intset( unsigned ); +extern void xthal_set_intclear( unsigned ); + + +/*---------------------------------------------------------------------- + Debug + ----------------------------------------------------------------------*/ + +/* Number of instruction and data break registers: */ +extern const int Xthal_num_ibreak; +extern const int Xthal_num_dbreak; + + +/*---------------------------------------------------------------------- + Core Counter + ----------------------------------------------------------------------*/ + +/* counter info */ +extern const unsigned char Xthal_have_ccount; /* set if CCOUNT register present */ +extern const unsigned char Xthal_num_ccompare; /* number of CCOMPAREn registers */ + +/* get CCOUNT register (if not present return 0) */ +extern unsigned xthal_get_ccount(void); + +/* set and get CCOMPAREn registers (if not present, get returns 0) */ +extern void xthal_set_ccompare(int, unsigned); +extern unsigned xthal_get_ccompare(int); + + +/*---------------------------------------------------------------------- + Miscellaneous + ----------------------------------------------------------------------*/ + +extern const unsigned char Xthal_have_prid; +extern const unsigned char Xthal_have_exceptions; +extern const unsigned char Xthal_xea_version; +extern const unsigned char Xthal_have_interrupts; +extern const unsigned char Xthal_have_highlevel_interrupts; +extern const unsigned char Xthal_have_nmi; + +extern unsigned xthal_get_prid( void ); + + +/*---------------------------------------------------------------------- + Virtual interrupt prioritization (DEPRECATED) + ----------------------------------------------------------------------*/ + +/* Convert between interrupt levels (as per PS.INTLEVEL) and virtual interrupt priorities: */ +extern unsigned xthal_vpri_to_intlevel(unsigned vpri); +extern unsigned xthal_intlevel_to_vpri(unsigned intlevel); + +/* Enables/disables given set (mask) of interrupts; returns previous enabled-mask of all ints: */ +extern unsigned xthal_int_enable(unsigned); +extern unsigned xthal_int_disable(unsigned); + +/* Set/get virtual priority of an interrupt: */ +extern int xthal_set_int_vpri(int intnum, int vpri); +extern int xthal_get_int_vpri(int intnum); + +/* Set/get interrupt lockout level for exclusive access to virtual priority data structures: */ +extern void xthal_set_vpri_locklevel(unsigned intlevel); +extern unsigned xthal_get_vpri_locklevel(void); + +/* Set/get current virtual interrupt priority: */ +extern unsigned xthal_set_vpri(unsigned vpri); +extern unsigned xthal_get_vpri(void); +extern unsigned xthal_set_vpri_intlevel(unsigned intlevel); +extern unsigned xthal_set_vpri_lock(void); + + +/*---------------------------------------------------------------------- + Generic Interrupt Trampolining Support (DEPRECATED) + ----------------------------------------------------------------------*/ + +typedef void (XtHalVoidFunc)(void); + +/* Bitmask of interrupts currently trampolining down: */ +extern unsigned Xthal_tram_pending; + +/* + * Bitmask of which interrupts currently trampolining down synchronously are + * actually enabled; this bitmask is necessary because INTENABLE cannot hold + * that state (sync-trampolining interrupts must be kept disabled while + * trampolining); in the current implementation, any bit set here is not set + * in INTENABLE, and vice-versa; once a sync-trampoline is handled (at level + * one), its enable bit must be moved from here to INTENABLE: + */ +extern unsigned Xthal_tram_enabled; + +/* Bitmask of interrupts configured for sync trampolining: */ +extern unsigned Xthal_tram_sync; + +/* Trampoline support functions: */ +extern unsigned xthal_tram_pending_to_service( void ); +extern void xthal_tram_done( unsigned serviced_mask ); +extern int xthal_tram_set_sync( int intnum, int sync ); +extern XtHalVoidFunc* xthal_set_tram_trigger_func( XtHalVoidFunc *trigger_fn ); + + +/*---------------------------------------------------------------------- + Internal Memories + ----------------------------------------------------------------------*/ + +extern const unsigned char Xthal_num_instrom; +extern const unsigned char Xthal_num_instram; +extern const unsigned char Xthal_num_datarom; +extern const unsigned char Xthal_num_dataram; +extern const unsigned char Xthal_num_xlmi; + +/* Each of the following arrays contains at least one entry, + * or as many entries as needed if more than one: */ +extern const unsigned int Xthal_instrom_vaddr[]; +extern const unsigned int Xthal_instrom_paddr[]; +extern const unsigned int Xthal_instrom_size []; +extern const unsigned int Xthal_instram_vaddr[]; +extern const unsigned int Xthal_instram_paddr[]; +extern const unsigned int Xthal_instram_size []; +extern const unsigned int Xthal_datarom_vaddr[]; +extern const unsigned int Xthal_datarom_paddr[]; +extern const unsigned int Xthal_datarom_size []; +extern const unsigned int Xthal_dataram_vaddr[]; +extern const unsigned int Xthal_dataram_paddr[]; +extern const unsigned int Xthal_dataram_size []; +extern const unsigned int Xthal_xlmi_vaddr[]; +extern const unsigned int Xthal_xlmi_paddr[]; +extern const unsigned int Xthal_xlmi_size []; + + +/*---------------------------------------------------------------------- + Cache + ----------------------------------------------------------------------*/ + +/* number of cache sets in log2(lines per way) */ +extern const unsigned char Xthal_icache_setwidth; +extern const unsigned char Xthal_dcache_setwidth; +/* cache set associativity (number of ways) */ +extern const unsigned int Xthal_icache_ways; +extern const unsigned int Xthal_dcache_ways; +/* cache features */ +extern const unsigned char Xthal_icache_line_lockable; +extern const unsigned char Xthal_dcache_line_lockable; + +/* cache attribute register control (used by other HAL routines) */ +extern unsigned xthal_get_cacheattr( void ); +extern unsigned xthal_get_icacheattr( void ); +extern unsigned xthal_get_dcacheattr( void ); +extern void xthal_set_cacheattr( unsigned ); +extern void xthal_set_icacheattr( unsigned ); +extern void xthal_set_dcacheattr( unsigned ); +/* set cache attribute (access modes) for a range of memory */ +extern int xthal_set_region_attribute( void *addr, unsigned size, + unsigned cattr, unsigned flags ); +/* Bits of flags parameter to xthal_set_region_attribute(): */ +#define XTHAL_CAFLAG_EXPAND 0x000100 /* only expand allowed access to range, don't reduce it */ +#define XTHAL_CAFLAG_EXACT 0x000200 /* return error if can't apply change to exact range specified */ +#define XTHAL_CAFLAG_NO_PARTIAL 0x000400 /* don't apply change to regions partially covered by range */ +#define XTHAL_CAFLAG_NO_AUTO_WB 0x000800 /* don't writeback data after leaving writeback attribute */ +#define XTHAL_CAFLAG_NO_AUTO_INV 0x001000 /* don't invalidate after disabling cache (entering bypass) */ + +/* enable caches */ +extern void xthal_icache_enable( void ); /* DEPRECATED */ +extern void xthal_dcache_enable( void ); /* DEPRECATED */ +/* disable caches */ +extern void xthal_icache_disable( void ); /* DEPRECATED */ +extern void xthal_dcache_disable( void ); /* DEPRECATED */ + +/* invalidate the caches */ +extern void xthal_icache_all_invalidate( void ); +extern void xthal_dcache_all_invalidate( void ); +/* write dirty data back */ +extern void xthal_dcache_all_writeback( void ); +/* write dirty data back and invalidate */ +extern void xthal_dcache_all_writeback_inv( void ); +/* prefetch and lock specified memory range into cache */ +extern void xthal_icache_region_lock( void *addr, unsigned size ); +extern void xthal_dcache_region_lock( void *addr, unsigned size ); +# ifndef XTHAL_USE_CACHE_MACROS +extern void xthal_icache_line_lock(void *addr); +extern void xthal_dcache_line_lock(void *addr); +# endif +/* unlock from cache */ +extern void xthal_icache_all_unlock( void ); +extern void xthal_dcache_all_unlock( void ); +extern void xthal_icache_region_unlock( void *addr, unsigned size ); +extern void xthal_dcache_region_unlock( void *addr, unsigned size ); +# ifndef XTHAL_USE_CACHE_MACROS +extern void xthal_icache_line_unlock(void *addr); +extern void xthal_dcache_line_unlock(void *addr); +# endif + + + +/*---------------------------------------------------------------------- + Local Memory ECC/Parity + ----------------------------------------------------------------------*/ + +/* Inject memory errors; flags is bit combination of XTHAL_MEMEP_F_xxx: */ +extern void xthal_memep_inject_error(void *addr, int size, int flags); + + + +/*---------------------------------------------------------------------- + Memory Management Unit + ----------------------------------------------------------------------*/ + +extern const unsigned char Xthal_have_spanning_way; +extern const unsigned char Xthal_have_identity_map; +extern const unsigned char Xthal_have_mimic_cacheattr; +extern const unsigned char Xthal_have_xlt_cacheattr; +extern const unsigned char Xthal_have_cacheattr; +extern const unsigned char Xthal_have_tlbs; + +extern const unsigned char Xthal_mmu_asid_bits; /* 0 .. 8 */ +extern const unsigned char Xthal_mmu_asid_kernel; +extern const unsigned char Xthal_mmu_rings; /* 1 .. 4 (perhaps 0 if no MMU and/or no protection?) */ +extern const unsigned char Xthal_mmu_ring_bits; +extern const unsigned char Xthal_mmu_sr_bits; +extern const unsigned char Xthal_mmu_ca_bits; +extern const unsigned int Xthal_mmu_max_pte_page_size; +extern const unsigned int Xthal_mmu_min_pte_page_size; + +extern const unsigned char Xthal_itlb_way_bits; +extern const unsigned char Xthal_itlb_ways; +extern const unsigned char Xthal_itlb_arf_ways; +extern const unsigned char Xthal_dtlb_way_bits; +extern const unsigned char Xthal_dtlb_ways; +extern const unsigned char Xthal_dtlb_arf_ways; + +/* Convert between virtual and physical addresses (through static maps only): */ +/*** WARNING: these two functions may go away in a future release; don't depend on them! ***/ +extern int xthal_static_v2p( unsigned vaddr, unsigned *paddrp ); +extern int xthal_static_p2v( unsigned paddr, unsigned *vaddrp, unsigned cached ); + +#define XCHAL_SUCCESS 0 +#define XCHAL_ADDRESS_MISALIGNED -1 +#define XCHAL_INEXACT -2 +#define XCHAL_INVALID_ADDRESS -3 +#define XCHAL_UNSUPPORTED_ON_THIS_ARCH -4 +#define XCHAL_NO_PAGES_MAPPED -5 +#define XTHAL_NO_MAPPING -6 + +#define XCHAL_CA_R (0xC0 | 0x40000000) +#define XCHAL_CA_RX (0xD0 | 0x40000000) +#define XCHAL_CA_RW (0xE0 | 0x40000000) +#define XCHAL_CA_RWX (0xF0 | 0x40000000) + +extern int xthal_set_region_translation(void* vaddr, void* paddr, unsigned size, unsigned cache_atr, unsigned flags); +extern int xthal_v2p(void*, void**, unsigned*, unsigned*); +extern int xthal_invalidate_region(void* addr); +extern int xthal_set_region_translation_raw(void *vaddr, void *paddr, unsigned cattr); + +#ifdef __cplusplus +} +#endif +#endif /*!_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */ + +#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ + + + + +/**************************************************************************** + EXPERIMENTAL and DEPRECATED Definitions + ****************************************************************************/ + + +#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__) +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef INCLUDE_DEPRECATED_HAL_CODE +extern const unsigned char Xthal_have_old_exc_arch; +extern const unsigned char Xthal_have_mmu; +extern const unsigned int Xthal_num_regs; +extern const unsigned char Xthal_num_iroms; +extern const unsigned char Xthal_num_irams; +extern const unsigned char Xthal_num_droms; +extern const unsigned char Xthal_num_drams; +extern const unsigned int Xthal_configid0; +extern const unsigned int Xthal_configid1; +#endif + +#ifdef INCLUDE_DEPRECATED_HAL_DEBUG_CODE +#define XTHAL_24_BIT_BREAK 0x80000000 +#define XTHAL_16_BIT_BREAK 0x40000000 +extern const unsigned short Xthal_ill_inst_16[16]; +#define XTHAL_DEST_REG 0xf0000000 /* Mask for destination register */ +#define XTHAL_DEST_REG_INST 0x08000000 /* Branch address is in register */ +#define XTHAL_DEST_REL_INST 0x04000000 /* Branch address is relative */ +#define XTHAL_RFW_INST 0x00000800 +#define XTHAL_RFUE_INST 0x00000400 +#define XTHAL_RFI_INST 0x00000200 +#define XTHAL_RFE_INST 0x00000100 +#define XTHAL_RET_INST 0x00000080 +#define XTHAL_BREAK_INST 0x00000040 +#define XTHAL_SYSCALL_INST 0x00000020 +#define XTHAL_LOOP_END 0x00000010 /* Not set by xthal_inst_type */ +#define XTHAL_JUMP_INST 0x00000008 /* Call or jump instruction */ +#define XTHAL_BRANCH_INST 0x00000004 /* Branch instruction */ +#define XTHAL_24_BIT_INST 0x00000002 +#define XTHAL_16_BIT_INST 0x00000001 +typedef struct xthal_state { + unsigned pc; + unsigned ar[16]; + unsigned lbeg; + unsigned lend; + unsigned lcount; + unsigned extra_ptr; + unsigned cpregs_ptr[XTHAL_MAX_CPS]; +} XTHAL_STATE; +extern unsigned int xthal_inst_type(void *addr); +extern unsigned int xthal_branch_addr(void *addr); +extern unsigned int xthal_get_npc(XTHAL_STATE *user_state); +#endif /* INCLUDE_DEPRECATED_HAL_DEBUG_CODE */ + +#ifdef __cplusplus +} +#endif +#endif /*!_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */ + +#endif /*XTENSA_HAL_H*/ + diff --git a/tools/sdk/include/esp32/xtensa/jtag-xtensa.h b/tools/sdk/include/esp32/xtensa/jtag-xtensa.h new file mode 100755 index 00000000..45ac1caa --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/jtag-xtensa.h @@ -0,0 +1,99 @@ +/* Copyright (c) 2011-2012 Tensilica Inc. ALL RIGHTS RESERVED. +// These coded instructions, statements, and computer programs are the +// copyrighted works and confidential proprietary information of Tensilica Inc. +// They may not be modified, copied, reproduced, distributed, or disclosed to +// third parties in any manner, medium, or form, in whole or in part, without +// the prior written consent of Tensilica Inc. +*/ + +#ifndef _JTAG_XTENSA_H_ +#define _JTAG_XTENSA_H_ + + +/* ---------------- JTAG registers ------------------ */ + +/* -- ER and later JTAG registers */ +typedef enum { + regIR, + regBypass, + regNAR, + regNDR, + regIdcode, + regPWRCTL, + regPWRSTAT, + regJtagMAX, +} xtensaJtagReg; + +/* -- pre-ER JTAG registers */ +typedef enum { + regOldIR, + regOldBypass, + regOldDIRW, + regOldDIR, + regOldDDR, + regOldDOSR, + regOldESR, + regOldDCR, + regOldTraxNDR, + regOldTraxNAR, + regOldMAX +} xtensaOldJtagReg; + + +/* ---------------- JTAG Instructions ------------------ */ + +/* -- pre-ER JTAG instructions */ +typedef enum { + ji_EnableOCD = 0x11, + ji_DebugInt, + ji_RetDebugInt, // TBD: remove + ji_DisRetOCD, // TBD: remove + ji_ExecuteDI, + ji_LoadDI, + ji_ScanDDR, + ji_ReadDOSR, + ji_ScanDCR, + ji_LoadWDI, + ji_TRAX = 0x1c, + ji_BYPASS = 0x1f, +} xtensaJtagInstruction; + +typedef enum { + OCDNormalMode, + OCDRunMode, + OCDHaltMode, + OCDStepMode +} xtensaMode; + +typedef struct { + xtensaMode mode; + int DRsel; + XTMP_core core; + XTMP_tap tap; + int core_num; + jtagReg_t *jtagRegs; + void *dap; // used for ARM DAP only + bool isBig; + int dir_array_option; // used by pre-ER devices only + // for testing, below - FIXME - delete later + int ocdReg; + unsigned int wr_data; + XTMP_event start_OCD_trans; + bool data_cycle; + bool data_pending; +} coreSlaveData_t; + + +enum OCD_ACCESS_TYPE{ + NEXUS_ACCESS, + CS_ACCESS, +}; + +// pre-ER Xtensa initializiation +EXTERN XTMP_deviceStatus +XTMP_jtagCoreSlaveEX(XTMP_component component, XTMP_jtagSlave slave, void* mydata); + +extern char *OCDrd; +extern char *OCDwr; + +#endif diff --git a/tools/sdk/include/esp32/xtensa/lcd-splc780d-4bitmode-board.h b/tools/sdk/include/esp32/xtensa/lcd-splc780d-4bitmode-board.h new file mode 100755 index 00000000..f4db5885 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/lcd-splc780d-4bitmode-board.h @@ -0,0 +1,62 @@ +/******************************************************************************* +Copyright (c) 2009-2013 by Tensilica Inc. ALL RIGHTS RESERVED. +These coded instructions, statements, and computer programs are the +copyrighted works and confidential proprietary information of Tensilica Inc. +They may not be modified, copied, reproduced, distributed, or disclosed to +third parties in any manner, medium, or form, in whole or in part, without +the prior written consent of Tensilica Inc. +-------------------------------------------------------------------------------- + +lcd-splc780d-4bitmode-board.h Board-specific LCD info for these boards: + Avnet AV110 (XT-AV110) + Xilinx ML605 (XT-ML605) + Xilinx KC705 (XT-KC705) + +Interface between board-independent driver and board-specific header. + +This is used by a board-independent SPLC780D LCD controller (4 bit mode) +driver to obtain board-specific information about LCD displays on the board, +such as the controller register base address and spacing (a function of how +the address lines are connected on the board) and length of the visible window +of the display (a function of the LCD panel the controller drives). +The driver doesnot refer directly to the board-specific header, which therefore is not +constrained to use macro names consistent with other boards. + +!! Must not contain any board-specific macro names (only controller specific) !! + +Included at compile-time via an include path specific to the board. + +The listed boards contain a single MYTech MOC-16216B-B display driven by +a Sunplus SPLC870D controller. + +*******************************************************************************/ + +#ifndef _LCD_SPLC780D_4BIT_BOARD_H +#define _LCD_SPLC780D_4BIT_BOARD_H + +#include /* Board info */ + + +/* Base address of the controller's registers. */ +#ifdef SPLC780D_4BIT_VADDR +#define SPLC780D_4BIT_REGBASE SPLC780D_4BIT_VADDR +#endif + +/* +The controller's registers are connected at word addresses on these boards. +Each byte-wide register appears as the least-significant-byte (LSB) of the +word regardless of the endianness of the processor (so if using word accesses +then endianness doesn't matter). +*/ +#define SPLC780D_4BIT_REGSPACING 4 +typedef unsigned splc780d_4bit_reg_t; + +/* Include generic information shared by all boards that use this device. */ +#include + + +/* Display limits of the LCD panel. */ +#define DISPLAY_VISIBLE_LEN 16 /* length (chars) of visible window */ + +#endif /* _LCD_SPLC780D_4BIT_BOARD_H */ + diff --git a/tools/sdk/include/esp32/xtensa/lcd-splc780d-4bitmode.h b/tools/sdk/include/esp32/xtensa/lcd-splc780d-4bitmode.h new file mode 100755 index 00000000..0a214bb4 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/lcd-splc780d-4bitmode.h @@ -0,0 +1,105 @@ +/******************************************************************************* + +Copyright (c) 2009-2010 by Tensilica Inc. ALL RIGHTS RESERVED. +These coded instructions, statements, and computer programs are the +copyrighted works and confidential proprietary information of Tensilica Inc. +They may not be modified, copied, reproduced, distributed, or disclosed to +third parties in any manner, medium, or form, in whole or in part, without +the prior written consent of Tensilica Inc. +-------------------------------------------------------------------------------- + +lcd-SPLC780D-4bitmode.h Generic definitions for Sunplus SPLC780D LCD Controller +operating in 4 bit mode. + +This is used by board-support-packages with one or more LCD displays that use +a SPLC780D controller in 4 bit mode. A BSP provides a base address for each +instance of an SPLC780D LCD controller on the board. + +Note that LCD display operation is almost totally independent of the LCD +display, depending almost entirely on the controller. However the display +may limit the number of characters of the controller's RAM buffer that are +actually visible at one time. The length of the display's visible window +is not specifified in this controller-specific header, but comes to the +driver from the board-specific "display.h" header. + +*******************************************************************************/ + +#ifndef _LCD_SPLC780D_4BIT_H_ +#define _LCD_SPLC780D_4BIT_H_ + + +/* Offsets to controller registers from base. */ +#define SPLC780D_4BIT_INST 0 +#define SPLC780D_4BIT_DATA (SPLC780D_4BIT_INST + SPLC780D_4BIT_REGSPACING) + + +#define SPLC780D_4BIT_INST_INIT1 0xFF /* First command in + init sequence */ +#define SPLC780D_4BIT_INST_INIT2 0x30 /* Second command in + init sequence, + issued 3 times */ +#define SPLC780D_4BIT_INST_INIT3 0x20 /* Third and last command + in init sequence */ +#define SPLC780D_4BIT_INST_CLEAR 0x01 /* clear (blank) display) */ +#define SPLC780D_4BIT_INST_SET_MODE 0x28 /* Set LCD mode. Supported + setting is 4 bit data + length, 2 lines, 5*8 */ +#define SPLC780D_4BIT_INST_DSPLY_ON 0x0C /* Set Display ON */ +#define SPLC780D_4BIT_INST_CRSR_INC 0x06 /* Set cursor moving direction + as increment */ + +#define SPLC780D_4BIT_LINET_ADDR 0x80 /* clear (blank) display) */ +#define SPLC780D_4BIT_LINEB_ADDR 0xC0 /* clear (blank) display) */ + +#ifndef __ASSEMBLER__ + +/* C interface to controller registers. */ +struct splc780d_4bit_s { + splc780d_4bit_reg_t inst; /* instruction register */ + splc780d_4bit_reg_t data; /* data register */ +}; + +typedef volatile struct splc780d_4bit_s splc780d_4bit_t; + +/* +Prototypes of high level driver functions. +*/ + +/* Write an instruction byte to LCD, result in two back to back writes since the + * LCD is hooked up in 4 bit mode*/ +extern void lcd_write_inst_byte(splc780d_4bit_t *lcd, unsigned char inst); + +/* Write a data byte to LCD, result in two back to back writes since the + * LCD is hooked up in 4 bit mode*/ +extern void lcd_write_data_byte(splc780d_4bit_t *lcd, unsigned char data); + +/* +Initialize the display with default settings. +*/ +extern void splc780d_4bit_init_default(splc780d_4bit_t *lcd); + +/* +Write a single character at a given position (chars from left, starting at 0). +Wait long enough afterward for the controller to be ready for more input. +Positions beyond the end of the display are ignored. +*/ +extern void splc780d_4bit_write_char(splc780d_4bit_t *lcd, unsigned pos, const char c); + +/* +Write a string to the display starting at the left (position 0). +Blank-pad to or truncate at the end of the display (overwrites any previous +string so don't need to blank the display first). +Wait long enough after each char for the controller to be ready for more input. +*/ +extern void splc780d_4bit_write_string(splc780d_4bit_t *lcd, const char *s); + +/* +Blank (clear) the entire display. +Wait long enough afterward for the controller to be ready for more input. +*/ +extern void splc780d_4bit_blank(splc780d_4bit_t *lcd); + +#endif /* __ASSEMBLER__ */ + +#endif /* _LCD_SPLC780D_4BIT_H_ */ + diff --git a/tools/sdk/include/esp32/xtensa/lcd-splc780d.h b/tools/sdk/include/esp32/xtensa/lcd-splc780d.h new file mode 100755 index 00000000..4e878e90 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/lcd-splc780d.h @@ -0,0 +1,151 @@ +/******************************************************************************* + +Copyright (c) 2006-2007 by Tensilica Inc. ALL RIGHTS RESERVED. +These coded instructions, statements, and computer programs are the +copyrighted works and confidential proprietary information of Tensilica Inc. +They may not be modified, copied, reproduced, distributed, or disclosed to +third parties in any manner, medium, or form, in whole or in part, without +the prior written consent of Tensilica Inc. +-------------------------------------------------------------------------------- + +lcd-SPLC780D.h Generic definitions for Sunplus SPLC780D LCD Controller + +This is used by board-support-packages with one or more LCD displays that use +a SPLC780D controller. A BSP provides a base address for each instance of an +SPLC780D LCD controller on the board. + +Note that LCD display operation is almost totally independent of the LCD +display, depending almost entirely on the controller. However the display +may limit the number of characters of the controller's RAM buffer that are +actually visible at one time. The length of the display's visible window +is not specifified in this controller-specific header, but comes to the +driver from the board-specific "display.h" header. + +*******************************************************************************/ + +#ifndef _LCD_SPLC780D_H_ +#define _LCD_SPLC780D_H_ + + +/* Offsets to controller registers from base. */ +#define SPLC780D_INST 0 +#define SPLC780D_DATA (SPLC780D_INST + SPLC780D_REGSPACING) + +/* +Bit fields and their values in the instruction register. +These fields are NOT orthogonal - they overlap! +Thus only one field may be written at a time, determined by the +most-significant 1 bit in the pattern (the field selector). +All less significant bits are part of the value of the selected field. +The fields and their values are grouped together to emphasize this format. +Field selector macro names end in '_' (implying something more needs +to be ORed) and the value macros are indented. The pattern written to a +bitfield is a bitwise OR of a field selector and one or more values, eg. + (SPLC780D_INST_ON_ | SPLC780D_INST_ON_DISPLAY | SPLC780D_INST_ON_CURSOR) +A single bit field (eg. SPCL780D_INST_HOME) need not have a value. + +NOTE: Controller requires a software delay after writing to the control +or data registers. For the data register it is 38us. For the control +register it is 38us for most bit fields, with the following exceptions: + SPLC780D_FUNC_ 100us. + SPLC780D_INST_CLEAR, SPLC780D_INST_HOME 1520us. +For more details and reset timing, see the SUNPLUS SPLC780D data sheet. +*/ + +#define SPLC780D_INST_CLEAR_ 0x1 /* clear (blank) display) */ + +#define SPLC780D_INST_HOME_ 0x2 /* home cursor and shift pos */ + +#define SPLC780D_INST_ENTRY_ 0x4 /* combine *ENTRY_* flags below */ +#define SPLC780D_INST_ENTRY_SHIFT 0x1 /* display shift on entry / not */ +#define SPLC780D_INST_ENTRY_INCR 0x2 /* cursor incr / decr */ +#define SPLC780D_INST_ENTRY_DECR 0 /* cursor incr / decr */ + +#define SPLC780D_INST_ON_ 0x8 /* combine *ON_* flags below */ +#define SPLC780D_INST_ON_DISPLAY 0x4 /* display on / off */ +#define SPLC780D_INST_ON_CURSOR 0x2 /* cursor on / off */ +#define SPLC780D_INST_ON_BLINK 0x1 /* blink on / off */ + +#define SPLC780D_INST_SHIFT_ 0x10 /* combine *SHIFT_* flags below */ +#define SPLC780D_INST_SHIFT_DISP 0x8 /* shift display / move cursor */ +#define SPLC780D_INST_SHIFT_CURS 0 /* shift display / move cursor */ +#define SPLC780D_INST_SHIFT_RIGHT 0x4 /* shift right / left */ +#define SPLC780D_INST_SHIFT_LEFT 0 /* shift right / left */ + +#define SPLC780D_INST_FUNC_ 0x20 /* combine *FUNC_* flags below */ +#define SPLC780D_INST_FUNC_8BIT 0x10 /* data length 8 bit / 4 bit */ +#define SPLC780D_INST_FUNC_4BIT 0 /* data length 8 bit / 4 bit */ +#define SPLC780D_INST_FUNC_2LINE 0x08 /* display lines 2 / 1 */ +#define SPLC780D_INST_FUNC_1LINE 0 /* display lines 2 / 1 */ +#define SPLC780D_INST_FUNC_F5x10 0x04 /* character font 5x10 / 5x8 */ +#define SPLC780D_INST_FUNC_F5x8 0 /* character font 5x10 / 5x8 */ + /* font must be 5x8 for 2 lines */ +#define SPLC780D_INST_CGEN_ 0x40 /* set char generator address */ +#define SPLC780D_INST_CGEN_ADDR 0x3F /* to address in this field */ +#define SPLC780D_INST_DRAM_ 0x80 /* set display data RAM address */ +#define SPLC780D_INST_DRAM_ADDR 0x7F /* to address in this field */ +#define SPLC780D_INST_DRAM_LINE2 0x40 /* address offset to line 2 */ +/* Controller limits */ +#define SPLC780D_RAMLEN_1LINE 0x50 /* length of line in RAM (1 line) */ +#define SPLC780D_RAMLEN_2LINE 0x28 /* length of line in RAM (2 line) */ + + +#ifndef __ASSEMBLER__ + +/* C interface to controller registers. */ +struct splc780d_s { + splc780d_reg_t inst; /* instruction register */ + splc780d_reg_t data; /* data register */ +}; + +typedef volatile struct splc780d_s splc780d_t; + +/* +Prototypes of high level driver functions. +*/ + +/* +Initialize the display with the FUNC_, ENTRY_ and ON_ fields as specified in +terms of the values above. The splc780d_init_default() macro is an example. +*/ +extern void splc780d_init(splc780d_t *lcd, + unsigned func, unsigned entry, unsigned on); + +/* +Initialize the display to default mode: 8-bit interface, 2 line, 5x8 font, +increment cursor on entry, display on (cursor and blinking off). +*/ +#define splc780d_init_default(lcd) \ + splc780d_init( lcd, \ + SPLC780D_INST_FUNC_8BIT \ + | SPLC780D_INST_FUNC_2LINE \ + | SPLC780D_INST_FUNC_F5x8, \ + SPLC780D_INST_ENTRY_INCR, \ + SPLC780D_INST_ON_DISPLAY \ + ) + +/* +Write a single character at a given position (chars from left, starting at 0). +Wait long enough afterward for the controller to be ready for more input. +Positions beyond the end of the display are ignored. +*/ +extern void splc780d_write_char(splc780d_t *lcd, unsigned pos, const char c); + +/* +Write a string to the display starting at the left (position 0). +Blank-pad to or truncate at the end of the display (overwrites any previous +string so don't need to blank the display first). +Wait long enough after each char for the controller to be ready for more input. +*/ +extern void splc780d_write_string(splc780d_t *lcd, const char *s); + +/* +Blank (clear) the entire display. +Wait long enough afterward for the controller to be ready for more input. +*/ +extern void splc780d_blank(splc780d_t *lcd); + +#endif /* __ASSEMBLER__ */ + +#endif /* _LCD_SPLC780D_H_ */ + diff --git a/tools/sdk/include/esp32/xtensa/overlay.h b/tools/sdk/include/esp32/xtensa/overlay.h new file mode 100755 index 00000000..e959cf51 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/overlay.h @@ -0,0 +1,184 @@ +// overlay.h -- Overlay manager header file +// $Id$ + +// Copyright (c) 2013 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + +#ifndef OVERLAY_H +#define OVERLAY_H + + +#include + + +#ifdef __cplusplus +extern "C" { +#endif + +// Define this to turn off overlay support +#ifdef XT_DISABLE_OVERLAYS + +#define OVERLAY(n) +#define DECLARE_OVERLAY(n) + +#define xt_overlay_map(ov_id) +#define xt_overlay_map_async(ov_id) 0 +#define xt_overlay_map_in_progress() 0 +#define xt_overlay_get_id() 0 +#define xt_overlay_get_state(pc) 0 +#define xt_overlay_check_map(pc,ps,ovstate,sp) 0 + +#else + +// Shorthand for convenience and portability. +#define OVERLAY(n) __attribute__((overlay(n))) + +// Structure of the overlay table required by gdb and the overlay +// manager. Should not be accessed by user code unless overriding +// the load process. +struct ovly_table { + void * vma; // The overlay's mapped address. + unsigned int size; // The size of the overlay, in bytes. + void * lma; // The overlay's load address. + unsigned int mapped; // Non-zero if overlay is currently mapped; zero otherwise. +}; + +// Constructed by the linker. Required for gdb and for the overlay +// manager. Should not be accessed by user code unless overriding +// the load process. +extern struct ovly_table _ovly_table[]; + +// Functions. +void xt_overlay_map(int ov_id); +int xt_overlay_map_async(int ov_id); +int xt_overlay_map_in_progress(void); +unsigned int xt_overlay_get_state(unsigned int pc); +unsigned int xt_overlay_check_map(unsigned int * pc, unsigned int * ps, + unsigned int ovstate, unsigned int sp); +int xt_overlay_start_map(void * dst, void * src, unsigned int len, int ov_id); +int xt_overlay_is_mapping(int ov_id); +void xt_overlay_fatal_error(int ov_id); + + +// Returns the current overlay ID. If no overlay is mapped or an overlay +// is in the middle of being mapped, returns -1. Inlined to avoid calling +// out of overlay (wastes cycles, can end up reading wrong ID on interrupt +// activity). +// +static inline int xt_overlay_get_id(void) +{ +#pragma always_inline +extern short _mapping_id; +extern short _ovly_id; + + int ret; + unsigned int flags = XTOS_SET_INTLEVEL(15); + + if (_mapping_id >= 0) { + ret = -1; + } + else { + ret = _ovly_id; + } + + XTOS_RESTORE_INTLEVEL(flags); + return ret; +} + + +// The following macros are used to declare numbered overlays and generate +// the corresponding call stubs. Use as follows: +// +// DECLARE_OVERLAY(n) +// +// See documentation for more details. + +//#include + +// At this time overlays are not supported without windowing. +#if defined(__XTENSA_WINDOWED_ABI__) + +#define xstr(x) str(x) +#define str(x) #x + +// At entry, register a8 holds the return address and a9 holds the target +// function address. This stub saves a8 on the stack at (SP - 20) which +// is the only location that is safe for us to use. Then it allocates 32 +// bytes on the stack for working storage, loads the overlay number into +// a8, and jumps to the common handler. The common handler will make sure +// that the called function is loaded into memory before calling it. +// NOTE: we are using the stack area normally reserved for nested functions. +// This means nested functions cannot be used when overlays are in use. + +#define CALL_IN(num) \ + asm(".section .gnu.linkonce.t.overlay.call." xstr(num) ".text, \"ax\"\n" \ + ".global _overlay_call_in_" xstr(num) "_\n" \ + ".align 4\n" \ + "_overlay_call_in_" xstr(num) "_:\n" \ + "s32e a8, a1, -20\n" \ + "addi a8, a1, -32\n" \ + "movsp a1, a8\n" \ + "movi a8, " xstr(num) "\n" \ + "j _overlay_call_in_common\n" \ + ".size _overlay_call_in_" xstr(num) "_, . - _overlay_call_in_" xstr(num) "_\n"); + +// The call-out stub first calls the target function, then loads the overlay +// number into register a14 and jumps to the common handler. The handler will +// make sure that the caller function is present in memory before returning. +// Note that registers a10-a13 may contain return values so must be preserved. +// +// Because we came here via a call4, the return address is in a4, and the top +// 2 bits are set to the window increment. We'll restore the top 2 bits of +// the return address from the called function's address, assuming that both +// are in the same 1 GB segment. For now this is always true. + +#define CALL_OUT(num) \ + asm(".section .gnu.linkonce.t.overlay.call." xstr(num) ".text, \"ax\"\n" \ + ".global _overlay_call_out_" xstr(num) "_\n" \ + ".align 4\n" \ + "_overlay_call_out_" xstr(num) "_:\n" \ + "slli a4, a4, 2\n" \ + "srli a4, a4, 2\n" \ + "extui a8, a9, 30, 2\n" \ + "slli a8, a8, 30\n" \ + "or a4, a4, a8\n" \ + "callx8 a9\n" \ + "movi a14, " xstr(num) "\n" \ + "j _overlay_call_out_common\n" \ + ".size _overlay_call_out_" xstr(num) "_, . - _overlay_call_out_" xstr(num) "_\n"); + +// Generate a call-in and a call-out stub for each overlay. + +#define DECLARE_OVERLAY(num) \ + CALL_IN(num) \ + CALL_OUT(num) + +#endif // defined(__XTENSA_WINDOWED_ABI__) + +#endif // XT_DISABLE_OVERLAYS + +#ifdef __cplusplus +} +#endif + +#endif // OVERLAY_H + diff --git a/tools/sdk/include/esp32/xtensa/overlay_os_asm.h b/tools/sdk/include/esp32/xtensa/overlay_os_asm.h new file mode 100755 index 00000000..4adc044e --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/overlay_os_asm.h @@ -0,0 +1,140 @@ +// overlay_os_asm.h -- Overlay manager assembly macros for OS use. +// $Id$ + +// Copyright (c) 2013 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + +#ifndef OVERLAY_OS_ASM_H +#define OVERLAY_OS_ASM_H + +// The macros in here are intended to be used by RTOS task switch code +// to check overlay status. Such code is usually in assembly and cannot +// call C code without penalty. For C code usage, it is best to use the +// corresponding C functions from the library. + + +// Inline assembly version of xt_overlay_get_state(). The arguments are +// three AR registers (a0-a15): +// +// "pcreg" - should contain the outgoing task's PC, i.e. the point at +// which the task got interrupted. The return value is also +// returned in this register. +// "sr1/2" - Scratch registers. These must be distinct from "pcreg". +// +// The return value is a 32-bit result that should be saved with the +// task context and passed as-is to xt_overlay_check_map. + + .macro _xt_overlay_get_state pcreg sr1 sr2 + + movi \sr1, _mapping_id + movi \sr2, _ovly_id + l16si \sr1, \sr1, 0 + l16ui \sr2, \sr2, 0 + slli \sr1, \sr1, 16 + or \pcreg, \sr1, \sr2 + + .endm + + +// Inline assembly version of xt_overlay_check_map(). It requires 5 AR +// registers (a0-a15) as arguments. +// +// "pcreg" - should contain the interrupted task's PC, i.e. the point +// at which the task got interrupted. This will be adjusted +// if required. +// "psreg" - should contain the interrupted task's PS. This will be +// adjusted if required. +// "ovreg" - should contain the overlay state on entry. Contents may +// be clobbered. +// "spreg" - should contain the tasks stack pointer on entry. +// "sr1" - Scratch register. Must be distinct from any of the above. +// +// The return values are "pcreg" and "psreg" and these must be used +// to update the task's PC and PS. +// Note that this macro may store data below the "spreg" pointer. If +// it does, then it will also disable interrupts via the PS, so that +// the task resumes with all interrupts disabled (to avoid corrupting +// this data). +// +// (SP - 24) Overlay ID to restore +// (SP - 28) Task PC +// (SP - 32) Task PS + + .macro _xt_overlay_check_map pcreg psreg ovreg spreg sr1 + +// There are four cases to deal with: +// +// _ovly_id = -1, _mapping_id = -1 +// No overlay is mapped or mapping, nothing to do. +// +// _ovly_id >= 0, _mapping_id = -1 +// An overlay was mapped, check PC to see if we need a restore. +// +// _ovly_id = -1, _mapping_id >= 0 +// An overlay is being mapped. Either it belongs to this task, which +// implies that the PC is in the mapping function, or it does not +// belong to this task. Either way there is nothing to do. +// +// _ovly_id >= 0, _mapping_id >= 0 +// Illegal, cannot happen by design. Don't need to handle this. +// +// So, the logic is to check _ovly_id first. If this is >= 0, then +// we check the task PC. If the PC is in the regions of interest then +// we'll patch the return PC to invoke xt_overlay_restore. + +.L1: + extui \sr1, \ovreg, 0, 16 // Extract _ovly_id + bbsi.l \sr1, 15, .Lno // If -1 then we're done + mov \ovreg, \sr1 // Restore this one + +// Next check the PC to see if it falls within the ranges of interest. + +.L2: + movi \sr1, _overlay_vma // Is PC < VMA range ? + bltu \pcreg, \sr1, .L3 + movi \sr1, _overlay_vma_end // Is PC > VMA range ? + bgeu \pcreg, \sr1, .L3 + j .L4 // PC is in VMA range +.L3: + movi \sr1, _overlay_call_stubs_start // Is PC < call stubs range ? + bltu \pcreg, \sr1, .Lno + movi \sr1, _overlay_call_stubs_end // Is PC > call stubs range ? + bgeu \pcreg, \sr1, .Lno + +// If we get here then a restore is needed. Save the overlay ID, PC and PS. +// Return modified PC and PS so that xt_overlay_restore() will execute in +// the context of the task when resumed. Note that the OS resumption code +// may expect PS.EXCM to be set so we leave it as is in the return value. + +.L4: + s32e \ovreg, \spreg, -24 // Save overlay ID + s32e \pcreg, \spreg, -28 // Save task PC + s32e \psreg, \spreg, -32 // Save task PS + movi \pcreg, xt_overlay_restore // Adjust resumption PC + movi \sr1, 15 + or \psreg, \psreg, \sr1 // Set intlevel to highest +.Lno: + + .endm + +#endif // OVERLAY_OS_ASM_H + diff --git a/tools/sdk/include/esp32/xtensa/sim.h b/tools/sdk/include/esp32/xtensa/sim.h new file mode 100755 index 00000000..e02087c5 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/sim.h @@ -0,0 +1,60 @@ +/* Copyright (c) 2004-2006 by Tensilica Inc. ALL RIGHTS RESERVED. +/ These coded instructions, statements, and computer programs are the +/ copyrighted works and confidential proprietary information of Tensilica Inc. +/ They may not be modified, copied, reproduced, distributed, or disclosed to +/ third parties in any manner, medium, or form, in whole or in part, without +/ the prior written consent of Tensilica Inc. +*/ + +/* sim.h + * + * Definitions and prototypes for specific ISS SIMCALLs + * (ie. outside the standard C library). + */ + +#ifndef _INC_SIM_H_ +#define _INC_SIM_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Shortcuts for enabling/disabling profiling in the Xtensa ISS */ +extern void xt_iss_profile_enable(void); +extern void xt_iss_profile_disable(void); + +/* Shortcut for setting the trace level in the Xtensa ISS */ +extern void xt_iss_trace_level(unsigned level); + +/* Generic interface for passing client commands in the Xtensa ISS: + * returns 0 on success, -1 on failure. + */ +extern int xt_iss_client_command(const char *client, const char *command); + +/* Interface for switching simulation modes in the Xtensa ISS: + * returns 0 on success, -1 on failure. + */ +#define XT_ISS_CYCLE_ACCURATE 0 +#define XT_ISS_FUNCTIONAL 1 +extern int xt_iss_switch_mode(int mode); + + +/* Interface for waiting on a system synchronization event */ +extern void xt_iss_event_wait(unsigned event_id); + +/* Interface for firing a system synchronization event */ +extern void xt_iss_event_fire(unsigned event_id); + +/* Interface for invoking a user simcall action, + * which can be registered in XTMP or XTSC. + */ +extern int xt_iss_simcall(int arg1, int arg2, int arg3, + int arg4, int arg5, int arg6); + + +#ifdef __cplusplus +} +#endif + +#endif /*_INC_SIM_H_*/ + diff --git a/tools/sdk/include/esp32/xtensa/simboard.h b/tools/sdk/include/esp32/xtensa/simboard.h new file mode 100755 index 00000000..980b0b75 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/simboard.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2001 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* simboard.h - Xtensa ISS "Board" specific definitions */ + +#ifndef _INC_SIMBOARD_H_ +#define _INC_SIMBOARD_H_ + +#include +#include + + +/* + * Device addresses. + */ + +/* System ROM: */ +#define XTBOARD_ROM_SIZE XSHAL_ROM_SIZE +#ifdef XSHAL_ROM_VADDR +#define XTBOARD_ROM_VADDR XSHAL_ROM_VADDR +#endif +#ifdef XSHAL_ROM_PADDR +#define XTBOARD_ROM_PADDR XSHAL_ROM_PADDR +#endif + +/* System RAM: */ +#define XTBOARD_RAM_SIZE XSHAL_RAM_SIZE +#ifdef XSHAL_RAM_VADDR +#define XTBOARD_RAM_VADDR XSHAL_RAM_VADDR +#endif +#ifdef XSHAL_RAM_PADDR +#define XTBOARD_RAM_PADDR XSHAL_RAM_PADDR +#endif + + +/* + * Things that depend on device addresses. + */ + +#define XTBOARD_CACHEATTR_WRITEBACK XSHAL_ISS_CACHEATTR_WRITEBACK +#define XTBOARD_CACHEATTR_WRITEALLOC XSHAL_ISS_CACHEATTR_WRITEALLOC +#define XTBOARD_CACHEATTR_WRITETHRU XSHAL_ISS_CACHEATTR_WRITETHRU +#define XTBOARD_CACHEATTR_BYPASS XSHAL_ISS_CACHEATTR_BYPASS +#define XTBOARD_CACHEATTR_DEFAULT XSHAL_ISS_CACHEATTR_DEFAULT + +#define XTBOARD_BUSINT_PIPE_REGIONS 0 +#define XTBOARD_BUSINT_SDRAM_REGIONS 0 + + +#endif /*_INC_SIMBOARD_H_*/ + diff --git a/tools/sdk/include/esp32/xtensa/simcall-errno.h b/tools/sdk/include/esp32/xtensa/simcall-errno.h new file mode 100755 index 00000000..445ec901 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/simcall-errno.h @@ -0,0 +1,139 @@ +/* Error numbers for Xtensa ISS semihosting. */ + +/* Copyright (c) 2003 by Tensilica Inc. ALL RIGHTS RESERVED. + These coded instructions, statements, and computer programs are the + copyrighted works and confidential proprietary information of Tensilica Inc. + They may not be modified, copied, reproduced, distributed, or disclosed to + third parties in any manner, medium, or form, in whole or in part, without + the prior written consent of Tensilica Inc. */ + +#ifndef _SIMCALL_ERRNO_H +#define _SIMCALL_ERRNO_H + +/* Define the error numbers (using the default newlib values) with prefixes + so they can be used in ISS without conflicting with the host values. */ + +#define _SIMC_EPERM 1 +#define _SIMC_ENOENT 2 +#define _SIMC_ESRCH 3 +#define _SIMC_EINTR 4 +#define _SIMC_EIO 5 +#define _SIMC_ENXIO 6 +#define _SIMC_E2BIG 7 +#define _SIMC_ENOEXEC 8 +#define _SIMC_EBADF 9 +#define _SIMC_ECHILD 10 +#define _SIMC_EAGAIN 11 +#define _SIMC_ENOMEM 12 +#define _SIMC_EACCES 13 +#define _SIMC_EFAULT 14 +#define _SIMC_ENOTBLK 15 +#define _SIMC_EBUSY 16 +#define _SIMC_EEXIST 17 +#define _SIMC_EXDEV 18 +#define _SIMC_ENODEV 19 +#define _SIMC_ENOTDIR 20 +#define _SIMC_EISDIR 21 +#define _SIMC_EINVAL 22 +#define _SIMC_ENFILE 23 +#define _SIMC_EMFILE 24 +#define _SIMC_ENOTTY 25 +#define _SIMC_ETXTBSY 26 +#define _SIMC_EFBIG 27 +#define _SIMC_ENOSPC 28 +#define _SIMC_ESPIPE 29 +#define _SIMC_EROFS 30 +#define _SIMC_EMLINK 31 +#define _SIMC_EPIPE 32 +#define _SIMC_EDOM 33 +#define _SIMC_ERANGE 34 +#define _SIMC_ENOMSG 35 +#define _SIMC_EIDRM 36 +#define _SIMC_ECHRNG 37 +#define _SIMC_EL2NSYNC 38 +#define _SIMC_EL3HLT 39 +#define _SIMC_EL3RST 40 +#define _SIMC_ELNRNG 41 +#define _SIMC_EUNATCH 42 +#define _SIMC_ENOCSI 43 +#define _SIMC_EL2HLT 44 +#define _SIMC_EDEADLK 45 +#define _SIMC_ENOLCK 46 +#define _SIMC_EBADE 50 +#define _SIMC_EBADR 51 +#define _SIMC_EXFULL 52 +#define _SIMC_ENOANO 53 +#define _SIMC_EBADRQC 54 +#define _SIMC_EBADSLT 55 +#define _SIMC_EDEADLOCK 56 +#define _SIMC_EBFONT 57 +#define _SIMC_ENOSTR 60 +#define _SIMC_ENODATA 61 +#define _SIMC_ETIME 62 +#define _SIMC_ENOSR 63 +#define _SIMC_ENONET 64 +#define _SIMC_ENOPKG 65 +#define _SIMC_EREMOTE 66 +#define _SIMC_ENOLINK 67 +#define _SIMC_EADV 68 +#define _SIMC_ESRMNT 69 +#define _SIMC_ECOMM 70 +#define _SIMC_EPROTO 71 +#define _SIMC_EMULTIHOP 74 +#define _SIMC_ELBIN 75 +#define _SIMC_EDOTDOT 76 +#define _SIMC_EBADMSG 77 +#define _SIMC_EFTYPE 79 +#define _SIMC_ENOTUNIQ 80 +#define _SIMC_EBADFD 81 +#define _SIMC_EREMCHG 82 +#define _SIMC_ELIBACC 83 +#define _SIMC_ELIBBAD 84 +#define _SIMC_ELIBSCN 85 +#define _SIMC_ELIBMAX 86 +#define _SIMC_ELIBEXEC 87 +#define _SIMC_ENOSYS 88 +#define _SIMC_ENMFILE 89 +#define _SIMC_ENOTEMPTY 90 +#define _SIMC_ENAMETOOLONG 91 +#define _SIMC_ELOOP 92 +#define _SIMC_EOPNOTSUPP 95 +#define _SIMC_EPFNOSUPPORT 96 +#define _SIMC_ECONNRESET 104 +#define _SIMC_ENOBUFS 105 +#define _SIMC_EAFNOSUPPORT 106 +#define _SIMC_EPROTOTYPE 107 +#define _SIMC_ENOTSOCK 108 +#define _SIMC_ENOPROTOOPT 109 +#define _SIMC_ESHUTDOWN 110 +#define _SIMC_ECONNREFUSED 111 +#define _SIMC_EADDRINUSE 112 +#define _SIMC_ECONNABORTED 113 +#define _SIMC_ENETUNREACH 114 +#define _SIMC_ENETDOWN 115 +#define _SIMC_ETIMEDOUT 116 +#define _SIMC_EHOSTDOWN 117 +#define _SIMC_EHOSTUNREACH 118 +#define _SIMC_EINPROGRESS 119 +#define _SIMC_EALREADY 120 +#define _SIMC_EDESTADDRREQ 121 +#define _SIMC_EMSGSIZE 122 +#define _SIMC_EPROTONOSUPPORT 123 +#define _SIMC_ESOCKTNOSUPPORT 124 +#define _SIMC_EADDRNOTAVAIL 125 +#define _SIMC_ENETRESET 126 +#define _SIMC_EISCONN 127 +#define _SIMC_ENOTCONN 128 +#define _SIMC_ETOOMANYREFS 129 +#define _SIMC_EPROCLIM 130 +#define _SIMC_EUSERS 131 +#define _SIMC_EDQUOT 132 +#define _SIMC_ESTALE 133 +#define _SIMC_ENOTSUP 134 +#define _SIMC_ENOMEDIUM 135 +#define _SIMC_ENOSHARE 136 +#define _SIMC_ECASECLASH 137 +#define _SIMC_EILSEQ 138 +#define _SIMC_EOVERFLOW 139 + +#endif /* ! _SIMCALL_ERRNO_H */ diff --git a/tools/sdk/include/esp32/xtensa/simcall-fcntl.h b/tools/sdk/include/esp32/xtensa/simcall-fcntl.h new file mode 100755 index 00000000..1c03f559 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/simcall-fcntl.h @@ -0,0 +1,21 @@ +/* File control operations for Xtensa ISS semihosting. */ + +/* Copyright (c) 2003 by Tensilica Inc. ALL RIGHTS RESERVED. + These coded instructions, statements, and computer programs are the + copyrighted works and confidential proprietary information of Tensilica Inc. + They may not be modified, copied, reproduced, distributed, or disclosed to + third parties in any manner, medium, or form, in whole or in part, without + the prior written consent of Tensilica Inc. */ + +#ifndef _SIMCALL_FCNTL_H +#define _SIMCALL_FCNTL_H + +#define _SIMC_O_APPEND 0x0008 +#define _SIMC_O_NONBLOCK 0x0080 +#define _SIMC_O_CREAT 0x0100 +#define _SIMC_O_TRUNC 0x0200 +#define _SIMC_O_EXCL 0x0400 +#define _SIMC_O_TEXT 0x4000 +#define _SIMC_O_BINARY 0x8000 + +#endif /* ! _SIMCALL_FCNTL_H */ diff --git a/tools/sdk/include/esp32/xtensa/simcall.h b/tools/sdk/include/esp32/xtensa/simcall.h new file mode 100755 index 00000000..d71959ee --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/simcall.h @@ -0,0 +1,189 @@ +/* + * simcall.h - Simulator call numbers + * + * Software that runs on a simulated Xtensa processor using + * the instruction set simulator (ISS) can invoke simulator + * services using the SIMCALL instruction. The a2 register + * is set prior to executing SIMCALL to a "simcall number", + * indicating which service to invoke. This file defines the + * simcall numbers defined and/or supported by the Xtensa ISS. + * + * IMPORTANT NOTE: These numbers are highly subject to change! + * + * Copyright (c) 2002-2007 by Tensilica Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of Tensilica Inc. + * They may not be modified, copied, reproduced, distributed, or disclosed to + * third parties in any manner, medium, or form, in whole or in part, without + * the prior written consent of Tensilica Inc. + */ + +#ifndef SIMCALL_INCLUDED +#define SIMCALL_INCLUDED + +/* + * System call like services offered by the simulator host. + * These are modeled after the Linux 2.4 kernel system calls + * for Xtensa processors. However not all system calls and + * not all functionality of a given system call are implemented, + * or necessarily have well defined or equivalent semantics in + * the context of a simulation (as opposed to a Unix kernel). + * + * These services behave largely as if they had been invoked + * as a task in the simulator host's operating system + * (eg. files accessed are those of the simulator host). + * However, these SIMCALLs model a virtual operating system + * so that various definitions, bit assignments etc + * (eg. open mode bits, errno values, etc) are independent + * of the host operating system used to run the simulation. + * Rather these definitions are specific to the Xtensa ISS. + * This way Xtensa ISA code written to use these SIMCALLs + * can (in principle) be simulated on any host. + * + * Up to 6 parameters are passed in registers a3 to a8 + * (note the 6th parameter isn't passed on the stack, + * unlike windowed function calling conventions). + * The return value is in a2. A negative value in the + * range -4096 to -1 indicates a negated error code to be + * reported in errno with a return value of -1, otherwise + * the value in a2 is returned as is. + */ + +/* These #defines need to match what's in Xtensa/OS/vxworks/xtiss/simcalls.c */ + +#define SYS_nop 0 /* n/a - setup; used to flush register windows */ +#define SYS_exit 1 /*x*/ +#define SYS_fork 2 +#define SYS_read 3 /*x*/ +#define SYS_write 4 /*x*/ +#define SYS_open 5 /*x*/ +#define SYS_close 6 /*x*/ +#define SYS_rename 7 /*x 38 - waitpid */ +#define SYS_creat 8 /*x*/ +#define SYS_link 9 /*x (not implemented on WIN32) */ +#define SYS_unlink 10 /*x*/ +#define SYS_execv 11 /* n/a - execve */ +#define SYS_execve 12 /* 11 - chdir */ +#define SYS_pipe 13 /* 42 - time */ +#define SYS_stat 14 /* 106 - mknod */ +#define SYS_chmod 15 +#define SYS_chown 16 /* 202 - lchown */ +#define SYS_utime 17 /* 30 - break */ +#define SYS_wait 18 /* n/a - oldstat */ +#define SYS_lseek 19 /*x*/ +#define SYS_getpid 20 +#define SYS_isatty 21 /* n/a - mount */ +#define SYS_fstat 22 /* 108 - oldumount */ +#define SYS_time 23 /* 13 - setuid */ +#define SYS_gettimeofday 24 /*x 78 - getuid (not implemented on WIN32) */ +#define SYS_times 25 /*X 43 - stime (Xtensa-specific implementation) */ +#define SYS_socket 26 +#define SYS_sendto 27 +#define SYS_recvfrom 28 +#define SYS_select_one 29 /* not compitible select, one file descriptor at the time */ +#define SYS_bind 30 +#define SYS_ioctl 31 + +/* + * Other... + */ +#define SYS_iss_argc 1000 /* returns value of argc */ +#define SYS_iss_argv_size 1001 /* bytes needed for argv & arg strings */ +#define SYS_iss_set_argv 1002 /* saves argv & arg strings at given addr */ + +#define SYS_memset 1004 /* fill a range of memory (fast) */ + +/* + * SIMCALLs for the ferret memory debugger. All are invoked by + * libferret.a ... ( Xtensa/Target-Libs/ferret ) + */ +#define SYS_ferret 1010 +#define SYS_malloc 1011 +#define SYS_free 1012 +#define SYS_more_heap 1013 +#define SYS_no_heap 1014 +#define SYS_enter_ferret 1015 +#define SYS_leave_ferret 1016 + +/* + * SIMCALLs for ISS client commands + */ +#define SYS_profile_enable 1020 +#define SYS_profile_disable 1021 +#define SYS_trace_level 1022 +#define SYS_client_command 1023 + +/* + * SIMCALL for simulation mode switching + */ +#define SYS_sim_mode_switch 1030 + +/* + * SIMCALLs for XTMP/XTSC event notify and core stall + */ +#define SYS_event_fire 1040 +#define SYS_event_stall 1041 + +/* + * SIMCALLs for callbacks registered in XTMP/XTSC + */ +#define SYS_callback_first 100 +#define SYS_callback_last 999 + +/* + * User defined simcall + */ +#define SYS_user_simcall 100 + +#define SYS_xmpa_errinfo 200 +#define SYS_xmpa_proc_status 201 +#define SYS_xmpa_proc_start 202 +#define SYS_xmpa_proc_stop 203 +#define SYS_xmpa_proc_mem_read 204 +#define SYS_xmpa_proc_mem_write 205 +#define SYS_xmpa_proc_mem_fill 206 +#define SYS_xmpa_proc_reg_read 207 +#define SYS_xmpa_proc_reg_write 208 + + +/* + * Extra SIMCALLs for GDB: + */ +#define SYS_gdb_break -1 /* invoked by XTOS on user exceptions if EPC points + to a break.n/break, regardless of cause! */ +#define SYS_xmon_out -2 /* invoked by XMON: ... */ +#define SYS_xmon_in -3 /* invoked by XMON: ... */ +#define SYS_xmon_flush -4 /* invoked by XMON: ... */ +#define SYS_gdb_abort -5 /* invoked by XTOS in _xtos_panic() */ +#define SYS_gdb_illegal_inst -6 /* invoked by XTOS for illegal instructions (too deeply) */ +#define SYS_xmon_init -7 /* invoked by XMON: ... */ +#define SYS_gdb_enter_sktloop -8 /* invoked by XTOS on debug exceptions */ +#define SYS_unhandled_kernel_exc -9 /* invoked by XTOS for unhandled kernel exceptions */ +#define SYS_unhandled_user_exc -10 /* invoked by XTOS for unhandled user exceptions */ +#define SYS_unhandled_double_exc -11 /* invoked by XTOS for unhandled double exceptions */ +#define SYS_unhandled_highpri_interrupt -12 /* invoked by XTOS for unhandled high-priority interrupts */ +#define SYS_xmon_close -13 /* invoked by XMON: ... */ + +/* + * SIMCALLs for vxWorks xtiss BSP: + */ +#define SYS_setup_ppp_pipes -83 +#define SYS_log_msg -84 + +/* + * SYS_select_one specifiers + */ +#define XTISS_SELECT_ONE_READ 1 +#define XTISS_SELECT_ONE_WRITE 2 +#define XTISS_SELECT_ONE_EXCEPT 3 + +/* + * SIMCALL for client calling arbitrary code in a client plug in. + * see clients/xcc_instr to see how this works. + */ + +#define SYS_client 0xC0DECAFE + + + +#endif /* !SIMCALL_INCLUDED */ diff --git a/tools/sdk/include/esp32/xtensa/specreg.h b/tools/sdk/include/esp32/xtensa/specreg.h new file mode 100755 index 00000000..0b2edee0 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/specreg.h @@ -0,0 +1,143 @@ +/* + * Xtensa Special Register symbolic names + */ + +/* $Id: //depot/rel/Eaglenest/Xtensa/OS/include/xtensa/specreg.h#2 $ */ + +/* + * Copyright (c) 2005-2011 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef XTENSA_SPECREG_H +#define XTENSA_SPECREG_H + +/* Special registers: */ +#define LBEG 0 +#define LEND 1 +#define LCOUNT 2 +#define SAR 3 +#define BR 4 +#define LITBASE 5 +#define SCOMPARE1 12 +#define ACCLO 16 +#define ACCHI 17 +#define MR_0 32 +#define MR_1 33 +#define MR_2 34 +#define MR_3 35 +#define PREFCTL 40 +#define WINDOWBASE 72 +#define WINDOWSTART 73 +#define PTEVADDR 83 +#define RASID 90 +#define ITLBCFG 91 +#define DTLBCFG 92 +#define IBREAKENABLE 96 +#define MEMCTL 97 +#define CACHEATTR 98 +#define ATOMCTL 99 +#define DDR 104 +#define MECR 110 +#define IBREAKA_0 128 +#define IBREAKA_1 129 +#define DBREAKA_0 144 +#define DBREAKA_1 145 +#define DBREAKC_0 160 +#define DBREAKC_1 161 +#define CONFIGID0 176 +#define EPC_1 177 +#define EPC_2 178 +#define EPC_3 179 +#define EPC_4 180 +#define EPC_5 181 +#define EPC_6 182 +#define EPC_7 183 +#define DEPC 192 +#define EPS_2 194 +#define EPS_3 195 +#define EPS_4 196 +#define EPS_5 197 +#define EPS_6 198 +#define EPS_7 199 +#define CONFIGID1 208 +#define EXCSAVE_1 209 +#define EXCSAVE_2 210 +#define EXCSAVE_3 211 +#define EXCSAVE_4 212 +#define EXCSAVE_5 213 +#define EXCSAVE_6 214 +#define EXCSAVE_7 215 +#define CPENABLE 224 +#define INTERRUPT 226 +#define INTREAD INTERRUPT /* alternate name for backward compatibility */ +#define INTSET INTERRUPT /* alternate name for backward compatibility */ +#define INTCLEAR 227 +#define INTENABLE 228 +#define PS 230 +#define VECBASE 231 +#define EXCCAUSE 232 +#define DEBUGCAUSE 233 +#define CCOUNT 234 +#define PRID 235 +#define ICOUNT 236 +#define ICOUNTLEVEL 237 +#define EXCVADDR 238 +#define CCOMPARE_0 240 +#define CCOMPARE_1 241 +#define CCOMPARE_2 242 +#define MISC_REG_0 244 +#define MISC_REG_1 245 +#define MISC_REG_2 246 +#define MISC_REG_3 247 + +/* Special cases (bases of special register series): */ +#define MR 32 +#define IBREAKA 128 +#define DBREAKA 144 +#define DBREAKC 160 +#define EPC 176 +#define EPS 192 +#define EXCSAVE 208 +#define CCOMPARE 240 +#define MISC_REG 244 + +/* Tensilica-defined user registers: */ +#if 0 +/*#define ... 21..24 */ /* (545CK) */ +/*#define ... 140..143 */ /* (545CK) */ +#define EXPSTATE 230 /* Diamond */ +#define THREADPTR 231 /* threadptr option */ +#define FCR 232 /* FPU */ +#define FSR 233 /* FPU */ +#define AE_OVF_SAR 240 /* HiFi2 */ +#define AE_BITHEAD 241 /* HiFi2 */ +#define AE_TS_FTS_BU_BP 242 /* HiFi2 */ +#define AE_SD_NO 243 /* HiFi2 */ +#define VSAR 240 /* VectraLX */ +#define ROUND_LO 242 /* VectraLX */ +#define ROUND_HI 243 /* VectraLX */ +#define CBEGIN 246 /* VectraLX */ +#define CEND 247 /* VectraLX */ +#endif + +#endif /* XTENSA_SPECREG_H */ + diff --git a/tools/sdk/include/esp32/xtensa/tie/xt_DFP_assist.h b/tools/sdk/include/esp32/xtensa/tie/xt_DFP_assist.h new file mode 100644 index 00000000..4d529ebd --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/tie/xt_DFP_assist.h @@ -0,0 +1,96 @@ +/* Definitions for the xt_DFP_assist TIE package */ + +/* + * Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of Tensilica Inc. + * They may not be modified, copied, reproduced, distributed, or disclosed to + * third parties in any manner, medium, or form, in whole or in part, without + * the prior written consent of Tensilica Inc. + */ + +/* Do not modify. This is automatically generated.*/ + +#ifndef _XTENSA_xt_DFP_assist_HEADER +#define _XTENSA_xt_DFP_assist_HEADER + +#ifdef __XTENSA__ +#ifdef __XCC__ + +#include + +/* + * The following prototypes describe intrinsic functions + * corresponding to TIE instructions. Some TIE instructions + * may produce multiple results (designated as "out" operands + * in the iclass section) or may have operands used as both + * inputs and outputs (designated as "inout"). However, the C + * and C++ languages do not provide syntax that can express + * the in/out/inout constraints of TIE intrinsics. + * Nevertheless, the compiler understands these constraints + * and will check that the intrinsic functions are used + * correctly. To improve the readability of these prototypes, + * the "out" and "inout" parameters are marked accordingly + * with comments. + */ + +extern void _TIE_xt_DFP_assist_F64ITER(unsigned arr /*inout*/, unsigned ars, unsigned art, immediate oper, immediate noshift); +extern unsigned _TIE_xt_DFP_assist_F64RND(unsigned ars, unsigned art, immediate mode); +extern void _TIE_xt_DFP_assist_F64ADDC(unsigned art /*inout*/, unsigned ars, immediate immZ, immediate immC); +extern void _TIE_xt_DFP_assist_F64SUBC(unsigned art /*inout*/, unsigned ars, immediate immZ, immediate immC); +extern unsigned _TIE_xt_DFP_assist_F64SIG(unsigned ars); +extern unsigned _TIE_xt_DFP_assist_F64CMPL(unsigned ars, unsigned art); +extern unsigned _TIE_xt_DFP_assist_F64CMPH(unsigned ars, unsigned art, immediate oper); +extern unsigned _TIE_xt_DFP_assist_F64NORM(unsigned ars, unsigned art, immediate mode); +extern unsigned _TIE_xt_DFP_assist_F64SEXP(unsigned ars, unsigned art); +extern unsigned _TIE_xt_DFP_assist_RF64R(immediate hilo); +extern void _TIE_xt_DFP_assist_WF64R(unsigned ars, unsigned art, immediate hilo); +extern unsigned _TIE_xt_DFP_assist_RUR_F64R_LO(void); +extern unsigned _TIE_xt_DFP_assist_RUR_F64R_HI(void); +extern void _TIE_xt_DFP_assist_WUR_F64R_LO(unsigned art); +extern void _TIE_xt_DFP_assist_WUR_F64R_HI(unsigned art); +extern unsigned _TIE_xt_DFP_assist_RUR_F64S(void); +extern void _TIE_xt_DFP_assist_WUR_F64S(unsigned art); +#define F64ITER _TIE_xt_DFP_assist_F64ITER +#define F64RND _TIE_xt_DFP_assist_F64RND +#define F64ADDC _TIE_xt_DFP_assist_F64ADDC +#define F64SUBC _TIE_xt_DFP_assist_F64SUBC +#define F64SIG _TIE_xt_DFP_assist_F64SIG +#define F64CMPL _TIE_xt_DFP_assist_F64CMPL +#define F64CMPH _TIE_xt_DFP_assist_F64CMPH +#define F64NORM _TIE_xt_DFP_assist_F64NORM +#define F64SEXP _TIE_xt_DFP_assist_F64SEXP +#define RF64R _TIE_xt_DFP_assist_RF64R +#define WF64R _TIE_xt_DFP_assist_WF64R +#define RUR_F64R_LO _TIE_xt_DFP_assist_RUR_F64R_LO +#define RF64R_LO _TIE_xt_DFP_assist_RUR_F64R_LO +#define RUR234 _TIE_xt_DFP_assist_RUR_F64R_LO +#define RUR_F64R_HI _TIE_xt_DFP_assist_RUR_F64R_HI +#define RF64R_HI _TIE_xt_DFP_assist_RUR_F64R_HI +#define RUR235 _TIE_xt_DFP_assist_RUR_F64R_HI +#define WUR_F64R_LO _TIE_xt_DFP_assist_WUR_F64R_LO +#define WF64R_LO _TIE_xt_DFP_assist_WUR_F64R_LO +#define WUR234 _TIE_xt_DFP_assist_WUR_F64R_LO +#define WUR_F64R_HI _TIE_xt_DFP_assist_WUR_F64R_HI +#define WF64R_HI _TIE_xt_DFP_assist_WUR_F64R_HI +#define WUR235 _TIE_xt_DFP_assist_WUR_F64R_HI +#define RUR_F64S _TIE_xt_DFP_assist_RUR_F64S +#define RF64S _TIE_xt_DFP_assist_RUR_F64S +#define RUR236 _TIE_xt_DFP_assist_RUR_F64S +#define WUR_F64S _TIE_xt_DFP_assist_WUR_F64S +#define WF64S _TIE_xt_DFP_assist_WUR_F64S +#define WUR236 _TIE_xt_DFP_assist_WUR_F64S + +#ifndef RUR +#define RUR(NUM) RUR##NUM() +#endif + +#ifndef WUR +#define WUR(VAL, NUM) WUR##NUM(VAL) +#endif + +#endif /* __XCC__ */ + +#endif /* __XTENSA__ */ + +#endif /* !_XTENSA_xt_DFP_assist_HEADER */ diff --git a/tools/sdk/include/esp32/xtensa/tie/xt_FP.h b/tools/sdk/include/esp32/xtensa/tie/xt_FP.h new file mode 100644 index 00000000..229a108a --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/tie/xt_FP.h @@ -0,0 +1,197 @@ +/* Definitions for the xt_FP TIE package */ + +/* + * Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of Tensilica Inc. + * They may not be modified, copied, reproduced, distributed, or disclosed to + * third parties in any manner, medium, or form, in whole or in part, without + * the prior written consent of Tensilica Inc. + */ + +/* Do not modify. This is automatically generated.*/ + +#ifndef _XTENSA_xt_FP_HEADER +#define _XTENSA_xt_FP_HEADER + +#ifdef __XTENSA__ +#ifdef __XCC__ + +#include +#include +typedef float _TIE_xt_FP_xtfloat; +typedef _TIE_xt_FP_xtfloat xtfloat; + +/* + * The following prototypes describe intrinsic functions + * corresponding to TIE instructions. Some TIE instructions + * may produce multiple results (designated as "out" operands + * in the iclass section) or may have operands used as both + * inputs and outputs (designated as "inout"). However, the C + * and C++ languages do not provide syntax that can express + * the in/out/inout constraints of TIE intrinsics. + * Nevertheless, the compiler understands these constraints + * and will check that the intrinsic functions are used + * correctly. To improve the readability of these prototypes, + * the "out" and "inout" parameters are marked accordingly + * with comments. + */ + +extern unsigned _TIE_xt_FP_RUR_FCR(void); +extern void _TIE_xt_FP_WUR_FCR(unsigned v); +extern unsigned _TIE_xt_FP_RUR_FSR(void); +extern void _TIE_xt_FP_WUR_FSR(unsigned v); +extern xtfloat _TIE_xt_FP_xtfloat_loadi(const xtfloat * p, immediate imm8x4); +extern void _TIE_xt_FP_xtfloat_storei(xtfloat t, xtfloat * p, immediate imm8x4); +extern void _TIE_xt_FP_xtfloat_loadip(xtfloat t /*out*/, const xtfloat * p /*inout*/, immediate imm8x4); +extern void _TIE_xt_FP_xtfloat_storeip(xtfloat t, xtfloat * p /*inout*/, immediate imm8x4); +extern xtfloat _TIE_xt_FP_xtfloat_loadx(const xtfloat * p, int imm8x4); +extern void _TIE_xt_FP_xtfloat_storex(xtfloat t, xtfloat * p, int imm8x4); +extern void _TIE_xt_FP_xtfloat_loadxp(xtfloat t /*out*/, const xtfloat * p /*inout*/, int imm8x4); +extern void _TIE_xt_FP_xtfloat_storexp(xtfloat t, xtfloat * p /*inout*/, int imm8x4); +extern xtfloat _TIE_xt_FP_xtfloat_move(xtfloat r); +extern int _TIE_xt_FP_ROUND_S(xtfloat s, immediate t); +extern int _TIE_xt_FP_TRUNC_S(xtfloat s, immediate t); +extern unsigned _TIE_xt_FP_UTRUNC_S(xtfloat s, immediate t); +extern int _TIE_xt_FP_FLOOR_S(xtfloat s, immediate t); +extern int _TIE_xt_FP_CEIL_S(xtfloat s, immediate t); +extern xtfloat _TIE_xt_FP_LSI(const xtfloat * p, immediate imm8x4); +extern void _TIE_xt_FP_SSI(xtfloat t, xtfloat * p, immediate imm8x4); +extern void _TIE_xt_FP_LSIP(xtfloat t /*out*/, const xtfloat * p /*inout*/, immediate imm8x4); +extern void _TIE_xt_FP_SSIP(xtfloat t, xtfloat * p /*inout*/, immediate imm8x4); +extern xtfloat _TIE_xt_FP_LSX(const xtfloat * p, int imm8x4); +extern void _TIE_xt_FP_SSX(xtfloat t, xtfloat * p, int imm8x4); +extern void _TIE_xt_FP_LSXP(xtfloat t /*out*/, const xtfloat * p /*inout*/, int imm8x4); +extern void _TIE_xt_FP_SSXP(xtfloat t, xtfloat * p /*inout*/, int imm8x4); +extern xtfloat _TIE_xt_FP_ABS_S(xtfloat s); +extern xtfloat _TIE_xt_FP_NEG_S(xtfloat s); +extern xtfloat _TIE_xt_FP_MOV_S(xtfloat s); +extern void _TIE_xt_FP_MOVEQZ_S(xtfloat r /*inout*/, xtfloat s, int t); +extern void _TIE_xt_FP_MOVNEZ_S(xtfloat r /*inout*/, xtfloat s, int t); +extern void _TIE_xt_FP_MOVLTZ_S(xtfloat r /*inout*/, xtfloat s, int t); +extern void _TIE_xt_FP_MOVGEZ_S(xtfloat r /*inout*/, xtfloat s, int t); +extern void _TIE_xt_FP_MOVF_S(xtfloat r /*inout*/, xtfloat s, xtbool t); +extern void _TIE_xt_FP_MOVT_S(xtfloat r /*inout*/, xtfloat s, xtbool t); +extern unsigned _TIE_xt_FP_RFR(xtfloat s); +extern xtfloat _TIE_xt_FP_WFR(unsigned s); +extern xtfloat _TIE_xt_FP_FLOAT_S(int s, immediate t); +extern xtfloat _TIE_xt_FP_UFLOAT_S(unsigned s, immediate t); +extern xtbool _TIE_xt_FP_OEQ_S(xtfloat s, xtfloat t); +extern xtbool _TIE_xt_FP_OLE_S(xtfloat s, xtfloat t); +extern xtbool _TIE_xt_FP_OLT_S(xtfloat s, xtfloat t); +extern xtbool _TIE_xt_FP_UEQ_S(xtfloat s, xtfloat t); +extern xtbool _TIE_xt_FP_ULE_S(xtfloat s, xtfloat t); +extern xtbool _TIE_xt_FP_ULT_S(xtfloat s, xtfloat t); +extern xtbool _TIE_xt_FP_UN_S(xtfloat s, xtfloat t); +extern xtfloat _TIE_xt_FP_ADD_S(xtfloat s, xtfloat t); +extern xtfloat _TIE_xt_FP_SUB_S(xtfloat s, xtfloat t); +extern xtfloat _TIE_xt_FP_MUL_S(xtfloat s, xtfloat t); +extern void _TIE_xt_FP_MADD_S(xtfloat r /*inout*/, xtfloat s, xtfloat t); +extern void _TIE_xt_FP_MSUB_S(xtfloat r /*inout*/, xtfloat s, xtfloat t); +extern xtfloat _TIE_xt_FP_RECIP0_S(xtfloat s); +extern xtfloat _TIE_xt_FP_DIV0_S(xtfloat s); +extern xtfloat _TIE_xt_FP_NEXP01_S(xtfloat s); +extern xtfloat _TIE_xt_FP_CONST_S(immediate s); +extern void _TIE_xt_FP_MKDADJ_S(xtfloat r /*inout*/, xtfloat s); +extern xtfloat _TIE_xt_FP_MKSADJ_S(xtfloat s); +extern void _TIE_xt_FP_ADDEXPM_S(xtfloat r /*inout*/, xtfloat s); +extern void _TIE_xt_FP_ADDEXP_S(xtfloat r /*inout*/, xtfloat s); +extern void _TIE_xt_FP_DIVN_S(xtfloat r /*inout*/, xtfloat s, xtfloat t); +extern xtfloat _TIE_xt_FP_RSQRT0_S(xtfloat s); +extern xtfloat _TIE_xt_FP_SQRT0_S(xtfloat s); +extern void _TIE_xt_FP_MADDN_S(xtfloat r /*inout*/, xtfloat s, xtfloat t); +extern xtfloat _TIE_xt_FP_DIV_S(xtfloat s, xtfloat t); +extern xtfloat _TIE_xt_FP_SQRT_S(xtfloat s); +extern xtfloat _TIE_xt_FP_RECIP_S(xtfloat s); +extern xtfloat _TIE_xt_FP_RSQRT_S(xtfloat s); +extern xtfloat _TIE_xt_FP_FSQRT_S(xtfloat s); +#define XT_RUR_FCR _TIE_xt_FP_RUR_FCR +#define RFCR _TIE_xt_FP_RUR_FCR +#define RUR232 _TIE_xt_FP_RUR_FCR +#define XT_WUR_FCR _TIE_xt_FP_WUR_FCR +#define WFCR _TIE_xt_FP_WUR_FCR +#define WUR232 _TIE_xt_FP_WUR_FCR +#define XT_RUR_FSR _TIE_xt_FP_RUR_FSR +#define RFSR _TIE_xt_FP_RUR_FSR +#define RUR233 _TIE_xt_FP_RUR_FSR +#define XT_WUR_FSR _TIE_xt_FP_WUR_FSR +#define WFSR _TIE_xt_FP_WUR_FSR +#define WUR233 _TIE_xt_FP_WUR_FSR +#define XT_xtfloat_loadi _TIE_xt_FP_xtfloat_loadi +#define XT_xtfloat_storei _TIE_xt_FP_xtfloat_storei +#define XT_xtfloat_loadip _TIE_xt_FP_xtfloat_loadip +#define XT_xtfloat_storeip _TIE_xt_FP_xtfloat_storeip +#define XT_xtfloat_loadx _TIE_xt_FP_xtfloat_loadx +#define XT_xtfloat_storex _TIE_xt_FP_xtfloat_storex +#define XT_xtfloat_loadxp _TIE_xt_FP_xtfloat_loadxp +#define XT_xtfloat_storexp _TIE_xt_FP_xtfloat_storexp +#define XT_xtfloat_move _TIE_xt_FP_xtfloat_move +#define XT_ROUND_S _TIE_xt_FP_ROUND_S +#define XT_TRUNC_S _TIE_xt_FP_TRUNC_S +#define XT_UTRUNC_S _TIE_xt_FP_UTRUNC_S +#define XT_FLOOR_S _TIE_xt_FP_FLOOR_S +#define XT_CEIL_S _TIE_xt_FP_CEIL_S +#define XT_LSI _TIE_xt_FP_LSI +#define XT_SSI _TIE_xt_FP_SSI +#define XT_LSIP _TIE_xt_FP_LSIP +#define XT_SSIP _TIE_xt_FP_SSIP +#define XT_LSX _TIE_xt_FP_LSX +#define XT_SSX _TIE_xt_FP_SSX +#define XT_LSXP _TIE_xt_FP_LSXP +#define XT_SSXP _TIE_xt_FP_SSXP +#define XT_ABS_S _TIE_xt_FP_ABS_S +#define XT_NEG_S _TIE_xt_FP_NEG_S +#define XT_MOV_S _TIE_xt_FP_MOV_S +#define XT_MOVEQZ_S _TIE_xt_FP_MOVEQZ_S +#define XT_MOVNEZ_S _TIE_xt_FP_MOVNEZ_S +#define XT_MOVLTZ_S _TIE_xt_FP_MOVLTZ_S +#define XT_MOVGEZ_S _TIE_xt_FP_MOVGEZ_S +#define XT_MOVF_S _TIE_xt_FP_MOVF_S +#define XT_MOVT_S _TIE_xt_FP_MOVT_S +#define XT_RFR _TIE_xt_FP_RFR +#define XT_WFR _TIE_xt_FP_WFR +#define XT_FLOAT_S _TIE_xt_FP_FLOAT_S +#define XT_UFLOAT_S _TIE_xt_FP_UFLOAT_S +#define XT_OEQ_S _TIE_xt_FP_OEQ_S +#define XT_OLE_S _TIE_xt_FP_OLE_S +#define XT_OLT_S _TIE_xt_FP_OLT_S +#define XT_UEQ_S _TIE_xt_FP_UEQ_S +#define XT_ULE_S _TIE_xt_FP_ULE_S +#define XT_ULT_S _TIE_xt_FP_ULT_S +#define XT_UN_S _TIE_xt_FP_UN_S +#define XT_ADD_S _TIE_xt_FP_ADD_S +#define XT_SUB_S _TIE_xt_FP_SUB_S +#define XT_MUL_S _TIE_xt_FP_MUL_S +#define XT_MADD_S _TIE_xt_FP_MADD_S +#define XT_MSUB_S _TIE_xt_FP_MSUB_S +#define XT_RECIP0_S _TIE_xt_FP_RECIP0_S +#define XT_DIV0_S _TIE_xt_FP_DIV0_S +#define XT_NEXP01_S _TIE_xt_FP_NEXP01_S +#define XT_CONST_S _TIE_xt_FP_CONST_S +#define XT_MKDADJ_S _TIE_xt_FP_MKDADJ_S +#define XT_MKSADJ_S _TIE_xt_FP_MKSADJ_S +#define XT_ADDEXPM_S _TIE_xt_FP_ADDEXPM_S +#define XT_ADDEXP_S _TIE_xt_FP_ADDEXP_S +#define XT_DIVN_S _TIE_xt_FP_DIVN_S +#define XT_RSQRT0_S _TIE_xt_FP_RSQRT0_S +#define XT_SQRT0_S _TIE_xt_FP_SQRT0_S +#define XT_MADDN_S _TIE_xt_FP_MADDN_S +#define XT_DIV_S _TIE_xt_FP_DIV_S +#define XT_SQRT_S _TIE_xt_FP_SQRT_S +#define XT_RECIP_S _TIE_xt_FP_RECIP_S +#define XT_RSQRT_S _TIE_xt_FP_RSQRT_S +#define XT_FSQRT_S _TIE_xt_FP_FSQRT_S + +#ifndef RUR +#define RUR(NUM) RUR##NUM() +#endif + +#ifndef WUR +#define WUR(VAL, NUM) WUR##NUM(VAL) +#endif + +#endif /* __XCC__ */ + +#endif /* __XTENSA__ */ + +#endif /* !_XTENSA_xt_FP_HEADER */ diff --git a/tools/sdk/include/esp32/xtensa/tie/xt_MAC16.h b/tools/sdk/include/esp32/xtensa/tie/xt_MAC16.h new file mode 100644 index 00000000..b46a1db7 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/tie/xt_MAC16.h @@ -0,0 +1,239 @@ +/* Definitions for the xt_MAC16 TIE package */ + +/* + * Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of Tensilica Inc. + * They may not be modified, copied, reproduced, distributed, or disclosed to + * third parties in any manner, medium, or form, in whole or in part, without + * the prior written consent of Tensilica Inc. + */ + +/* Do not modify. This is automatically generated.*/ + +#ifndef _XTENSA_xt_MAC16_HEADER +#define _XTENSA_xt_MAC16_HEADER + +#ifdef __XTENSA__ +#ifdef __XCC__ + +#include +#include + +/* + * The following prototypes describe intrinsic functions + * corresponding to TIE instructions. Some TIE instructions + * may produce multiple results (designated as "out" operands + * in the iclass section) or may have operands used as both + * inputs and outputs (designated as "inout"). However, the C + * and C++ languages do not provide syntax that can express + * the in/out/inout constraints of TIE intrinsics. + * Nevertheless, the compiler understands these constraints + * and will check that the intrinsic functions are used + * correctly. To improve the readability of these prototypes, + * the "out" and "inout" parameters are marked accordingly + * with comments. + */ + +extern void _TIE_xt_MAC16_UMUL_AA_HH(unsigned ars, unsigned art); +extern void _TIE_xt_MAC16_UMUL_AA_LH(unsigned ars, unsigned art); +extern void _TIE_xt_MAC16_UMUL_AA_HL(unsigned ars, unsigned art); +extern void _TIE_xt_MAC16_UMUL_AA_LL(unsigned ars, unsigned art); +extern void _TIE_xt_MAC16_MUL_AA_HH(unsigned ars, unsigned art); +extern void _TIE_xt_MAC16_MUL_AA_LH(unsigned ars, unsigned art); +extern void _TIE_xt_MAC16_MUL_AA_HL(unsigned ars, unsigned art); +extern void _TIE_xt_MAC16_MUL_AA_LL(unsigned ars, unsigned art); +extern void _TIE_xt_MAC16_MUL_AD_HH(unsigned ars, immediate my); +extern void _TIE_xt_MAC16_MUL_AD_LH(unsigned ars, immediate my); +extern void _TIE_xt_MAC16_MUL_AD_HL(unsigned ars, immediate my); +extern void _TIE_xt_MAC16_MUL_AD_LL(unsigned ars, immediate my); +extern void _TIE_xt_MAC16_MUL_DA_HH(immediate mx, unsigned art); +extern void _TIE_xt_MAC16_MUL_DA_LH(immediate mx, unsigned art); +extern void _TIE_xt_MAC16_MUL_DA_HL(immediate mx, unsigned art); +extern void _TIE_xt_MAC16_MUL_DA_LL(immediate mx, unsigned art); +extern void _TIE_xt_MAC16_MUL_DD_HH(immediate mx, immediate my); +extern void _TIE_xt_MAC16_MUL_DD_LH(immediate mx, immediate my); +extern void _TIE_xt_MAC16_MUL_DD_HL(immediate mx, immediate my); +extern void _TIE_xt_MAC16_MUL_DD_LL(immediate mx, immediate my); +extern void _TIE_xt_MAC16_MULS_AA_HH(unsigned ars, unsigned art); +extern void _TIE_xt_MAC16_MULS_AA_LH(unsigned ars, unsigned art); +extern void _TIE_xt_MAC16_MULS_AA_HL(unsigned ars, unsigned art); +extern void _TIE_xt_MAC16_MULS_AA_LL(unsigned ars, unsigned art); +extern void _TIE_xt_MAC16_MULA_AA_HH(unsigned ars, unsigned art); +extern void _TIE_xt_MAC16_MULA_AA_LH(unsigned ars, unsigned art); +extern void _TIE_xt_MAC16_MULA_AA_HL(unsigned ars, unsigned art); +extern void _TIE_xt_MAC16_MULA_AA_LL(unsigned ars, unsigned art); +extern void _TIE_xt_MAC16_MULS_AD_HH(unsigned ars, immediate my); +extern void _TIE_xt_MAC16_MULS_AD_LH(unsigned ars, immediate my); +extern void _TIE_xt_MAC16_MULS_AD_HL(unsigned ars, immediate my); +extern void _TIE_xt_MAC16_MULS_AD_LL(unsigned ars, immediate my); +extern void _TIE_xt_MAC16_MULA_AD_HH(unsigned ars, immediate my); +extern void _TIE_xt_MAC16_MULA_AD_LH(unsigned ars, immediate my); +extern void _TIE_xt_MAC16_MULA_AD_HL(unsigned ars, immediate my); +extern void _TIE_xt_MAC16_MULA_AD_LL(unsigned ars, immediate my); +extern void _TIE_xt_MAC16_MULS_DA_HH(immediate mx, unsigned art); +extern void _TIE_xt_MAC16_MULS_DA_LH(immediate mx, unsigned art); +extern void _TIE_xt_MAC16_MULS_DA_HL(immediate mx, unsigned art); +extern void _TIE_xt_MAC16_MULS_DA_LL(immediate mx, unsigned art); +extern void _TIE_xt_MAC16_MULA_DA_HH(immediate mx, unsigned art); +extern void _TIE_xt_MAC16_MULA_DA_LH(immediate mx, unsigned art); +extern void _TIE_xt_MAC16_MULA_DA_HL(immediate mx, unsigned art); +extern void _TIE_xt_MAC16_MULA_DA_LL(immediate mx, unsigned art); +extern void _TIE_xt_MAC16_MULS_DD_HH(immediate mx, immediate my); +extern void _TIE_xt_MAC16_MULS_DD_LH(immediate mx, immediate my); +extern void _TIE_xt_MAC16_MULS_DD_HL(immediate mx, immediate my); +extern void _TIE_xt_MAC16_MULS_DD_LL(immediate mx, immediate my); +extern void _TIE_xt_MAC16_MULA_DD_HH(immediate mx, immediate my); +extern void _TIE_xt_MAC16_MULA_DD_LH(immediate mx, immediate my); +extern void _TIE_xt_MAC16_MULA_DD_HL(immediate mx, immediate my); +extern void _TIE_xt_MAC16_MULA_DD_LL(immediate mx, immediate my); +extern unsigned _TIE_xt_MAC16_RSR_M0(void); +extern void _TIE_xt_MAC16_WSR_M0(unsigned art); +extern void _TIE_xt_MAC16_XSR_M0(unsigned art /*inout*/); +extern unsigned _TIE_xt_MAC16_RSR_M1(void); +extern void _TIE_xt_MAC16_WSR_M1(unsigned art); +extern void _TIE_xt_MAC16_XSR_M1(unsigned art /*inout*/); +extern unsigned _TIE_xt_MAC16_RSR_M2(void); +extern void _TIE_xt_MAC16_WSR_M2(unsigned art); +extern void _TIE_xt_MAC16_XSR_M2(unsigned art /*inout*/); +extern unsigned _TIE_xt_MAC16_RSR_M3(void); +extern void _TIE_xt_MAC16_WSR_M3(unsigned art); +extern void _TIE_xt_MAC16_XSR_M3(unsigned art /*inout*/); +extern unsigned _TIE_xt_MAC16_RSR_ACCLO(void); +extern void _TIE_xt_MAC16_WSR_ACCLO(unsigned art); +extern void _TIE_xt_MAC16_XSR_ACCLO(unsigned art /*inout*/); +extern unsigned _TIE_xt_MAC16_RSR_ACCHI(void); +extern void _TIE_xt_MAC16_WSR_ACCHI(unsigned art); +extern void _TIE_xt_MAC16_XSR_ACCHI(unsigned art /*inout*/); +extern void _TIE_xt_MAC16_MULA_DA_LL_LDDEC(immediate w, const short * s /*inout*/, immediate x, int t); +extern void _TIE_xt_MAC16_MULA_DA_LL_LDINC(immediate w, const short * s /*inout*/, immediate x, int t); +extern void _TIE_xt_MAC16_MULA_DA_HL_LDDEC(immediate w, const short * s /*inout*/, immediate x, int t); +extern void _TIE_xt_MAC16_MULA_DA_HL_LDINC(immediate w, const short * s /*inout*/, immediate x, int t); +extern void _TIE_xt_MAC16_MULA_DA_LH_LDDEC(immediate w, const short * s /*inout*/, immediate x, int t); +extern void _TIE_xt_MAC16_MULA_DA_LH_LDINC(immediate w, const short * s /*inout*/, immediate x, int t); +extern void _TIE_xt_MAC16_MULA_DA_HH_LDDEC(immediate w, const short * s /*inout*/, immediate x, int t); +extern void _TIE_xt_MAC16_MULA_DA_HH_LDINC(immediate w, const short * s /*inout*/, immediate x, int t); +extern void _TIE_xt_MAC16_MULA_DD_LL_LDDEC(immediate w, const short * s /*inout*/, immediate x, immediate y); +extern void _TIE_xt_MAC16_MULA_DD_LL_LDINC(immediate w, const short * s /*inout*/, immediate x, immediate y); +extern void _TIE_xt_MAC16_MULA_DD_HL_LDDEC(immediate w, const short * s /*inout*/, immediate x, immediate y); +extern void _TIE_xt_MAC16_MULA_DD_HL_LDINC(immediate w, const short * s /*inout*/, immediate x, immediate y); +extern void _TIE_xt_MAC16_MULA_DD_LH_LDDEC(immediate w, const short * s /*inout*/, immediate x, immediate y); +extern void _TIE_xt_MAC16_MULA_DD_LH_LDINC(immediate w, const short * s /*inout*/, immediate x, immediate y); +extern void _TIE_xt_MAC16_MULA_DD_HH_LDDEC(immediate w, const short * s /*inout*/, immediate x, immediate y); +extern void _TIE_xt_MAC16_MULA_DD_HH_LDINC(immediate w, const short * s /*inout*/, immediate x, immediate y); +extern void _TIE_xt_MAC16_LDDEC(immediate w, const short * p /*inout*/); +extern void _TIE_xt_MAC16_ULDDEC(immediate w, const unsigned short * p /*inout*/); +extern void _TIE_xt_MAC16_SLDDEC(immediate w, const short * p /*inout*/); +extern void _TIE_xt_MAC16_LDINC(immediate w, const short * p /*inout*/); +extern void _TIE_xt_MAC16_ULDINC(immediate w, const unsigned short * p /*inout*/); +extern void _TIE_xt_MAC16_SLDINC(immediate w, const short * p /*inout*/); +extern int _TIE_xt_MAC16_RSR16(void); +extern void _TIE_xt_MAC16_WSR16(int t); +extern void _TIE_xt_MAC16_XSR16(int t /*inout*/); +extern int _TIE_xt_MAC16_RSR17(void); +extern void _TIE_xt_MAC16_WSR17(int t); +extern void _TIE_xt_MAC16_XSR17(int t /*inout*/); +#define XT_UMUL_AA_HH _TIE_xt_MAC16_UMUL_AA_HH +#define XT_UMUL_AA_LH _TIE_xt_MAC16_UMUL_AA_LH +#define XT_UMUL_AA_HL _TIE_xt_MAC16_UMUL_AA_HL +#define XT_UMUL_AA_LL _TIE_xt_MAC16_UMUL_AA_LL +#define XT_MUL_AA_HH _TIE_xt_MAC16_MUL_AA_HH +#define XT_MUL_AA_LH _TIE_xt_MAC16_MUL_AA_LH +#define XT_MUL_AA_HL _TIE_xt_MAC16_MUL_AA_HL +#define XT_MUL_AA_LL _TIE_xt_MAC16_MUL_AA_LL +#define XT_MUL_AD_HH _TIE_xt_MAC16_MUL_AD_HH +#define XT_MUL_AD_LH _TIE_xt_MAC16_MUL_AD_LH +#define XT_MUL_AD_HL _TIE_xt_MAC16_MUL_AD_HL +#define XT_MUL_AD_LL _TIE_xt_MAC16_MUL_AD_LL +#define XT_MUL_DA_HH _TIE_xt_MAC16_MUL_DA_HH +#define XT_MUL_DA_LH _TIE_xt_MAC16_MUL_DA_LH +#define XT_MUL_DA_HL _TIE_xt_MAC16_MUL_DA_HL +#define XT_MUL_DA_LL _TIE_xt_MAC16_MUL_DA_LL +#define XT_MUL_DD_HH _TIE_xt_MAC16_MUL_DD_HH +#define XT_MUL_DD_LH _TIE_xt_MAC16_MUL_DD_LH +#define XT_MUL_DD_HL _TIE_xt_MAC16_MUL_DD_HL +#define XT_MUL_DD_LL _TIE_xt_MAC16_MUL_DD_LL +#define XT_MULS_AA_HH _TIE_xt_MAC16_MULS_AA_HH +#define XT_MULS_AA_LH _TIE_xt_MAC16_MULS_AA_LH +#define XT_MULS_AA_HL _TIE_xt_MAC16_MULS_AA_HL +#define XT_MULS_AA_LL _TIE_xt_MAC16_MULS_AA_LL +#define XT_MULA_AA_HH _TIE_xt_MAC16_MULA_AA_HH +#define XT_MULA_AA_LH _TIE_xt_MAC16_MULA_AA_LH +#define XT_MULA_AA_HL _TIE_xt_MAC16_MULA_AA_HL +#define XT_MULA_AA_LL _TIE_xt_MAC16_MULA_AA_LL +#define XT_MULS_AD_HH _TIE_xt_MAC16_MULS_AD_HH +#define XT_MULS_AD_LH _TIE_xt_MAC16_MULS_AD_LH +#define XT_MULS_AD_HL _TIE_xt_MAC16_MULS_AD_HL +#define XT_MULS_AD_LL _TIE_xt_MAC16_MULS_AD_LL +#define XT_MULA_AD_HH _TIE_xt_MAC16_MULA_AD_HH +#define XT_MULA_AD_LH _TIE_xt_MAC16_MULA_AD_LH +#define XT_MULA_AD_HL _TIE_xt_MAC16_MULA_AD_HL +#define XT_MULA_AD_LL _TIE_xt_MAC16_MULA_AD_LL +#define XT_MULS_DA_HH _TIE_xt_MAC16_MULS_DA_HH +#define XT_MULS_DA_LH _TIE_xt_MAC16_MULS_DA_LH +#define XT_MULS_DA_HL _TIE_xt_MAC16_MULS_DA_HL +#define XT_MULS_DA_LL _TIE_xt_MAC16_MULS_DA_LL +#define XT_MULA_DA_HH _TIE_xt_MAC16_MULA_DA_HH +#define XT_MULA_DA_LH _TIE_xt_MAC16_MULA_DA_LH +#define XT_MULA_DA_HL _TIE_xt_MAC16_MULA_DA_HL +#define XT_MULA_DA_LL _TIE_xt_MAC16_MULA_DA_LL +#define XT_MULS_DD_HH _TIE_xt_MAC16_MULS_DD_HH +#define XT_MULS_DD_LH _TIE_xt_MAC16_MULS_DD_LH +#define XT_MULS_DD_HL _TIE_xt_MAC16_MULS_DD_HL +#define XT_MULS_DD_LL _TIE_xt_MAC16_MULS_DD_LL +#define XT_MULA_DD_HH _TIE_xt_MAC16_MULA_DD_HH +#define XT_MULA_DD_LH _TIE_xt_MAC16_MULA_DD_LH +#define XT_MULA_DD_HL _TIE_xt_MAC16_MULA_DD_HL +#define XT_MULA_DD_LL _TIE_xt_MAC16_MULA_DD_LL +#define XT_RSR_M0 _TIE_xt_MAC16_RSR_M0 +#define XT_WSR_M0 _TIE_xt_MAC16_WSR_M0 +#define XT_XSR_M0 _TIE_xt_MAC16_XSR_M0 +#define XT_RSR_M1 _TIE_xt_MAC16_RSR_M1 +#define XT_WSR_M1 _TIE_xt_MAC16_WSR_M1 +#define XT_XSR_M1 _TIE_xt_MAC16_XSR_M1 +#define XT_RSR_M2 _TIE_xt_MAC16_RSR_M2 +#define XT_WSR_M2 _TIE_xt_MAC16_WSR_M2 +#define XT_XSR_M2 _TIE_xt_MAC16_XSR_M2 +#define XT_RSR_M3 _TIE_xt_MAC16_RSR_M3 +#define XT_WSR_M3 _TIE_xt_MAC16_WSR_M3 +#define XT_XSR_M3 _TIE_xt_MAC16_XSR_M3 +#define XT_RSR_ACCLO _TIE_xt_MAC16_RSR_ACCLO +#define XT_WSR_ACCLO _TIE_xt_MAC16_WSR_ACCLO +#define XT_XSR_ACCLO _TIE_xt_MAC16_XSR_ACCLO +#define XT_RSR_ACCHI _TIE_xt_MAC16_RSR_ACCHI +#define XT_WSR_ACCHI _TIE_xt_MAC16_WSR_ACCHI +#define XT_XSR_ACCHI _TIE_xt_MAC16_XSR_ACCHI +#define XT_MULA_DA_LL_LDDEC _TIE_xt_MAC16_MULA_DA_LL_LDDEC +#define XT_MULA_DA_LL_LDINC _TIE_xt_MAC16_MULA_DA_LL_LDINC +#define XT_MULA_DA_HL_LDDEC _TIE_xt_MAC16_MULA_DA_HL_LDDEC +#define XT_MULA_DA_HL_LDINC _TIE_xt_MAC16_MULA_DA_HL_LDINC +#define XT_MULA_DA_LH_LDDEC _TIE_xt_MAC16_MULA_DA_LH_LDDEC +#define XT_MULA_DA_LH_LDINC _TIE_xt_MAC16_MULA_DA_LH_LDINC +#define XT_MULA_DA_HH_LDDEC _TIE_xt_MAC16_MULA_DA_HH_LDDEC +#define XT_MULA_DA_HH_LDINC _TIE_xt_MAC16_MULA_DA_HH_LDINC +#define XT_MULA_DD_LL_LDDEC _TIE_xt_MAC16_MULA_DD_LL_LDDEC +#define XT_MULA_DD_LL_LDINC _TIE_xt_MAC16_MULA_DD_LL_LDINC +#define XT_MULA_DD_HL_LDDEC _TIE_xt_MAC16_MULA_DD_HL_LDDEC +#define XT_MULA_DD_HL_LDINC _TIE_xt_MAC16_MULA_DD_HL_LDINC +#define XT_MULA_DD_LH_LDDEC _TIE_xt_MAC16_MULA_DD_LH_LDDEC +#define XT_MULA_DD_LH_LDINC _TIE_xt_MAC16_MULA_DD_LH_LDINC +#define XT_MULA_DD_HH_LDDEC _TIE_xt_MAC16_MULA_DD_HH_LDDEC +#define XT_MULA_DD_HH_LDINC _TIE_xt_MAC16_MULA_DD_HH_LDINC +#define XT_LDDEC _TIE_xt_MAC16_LDDEC +#define XT_ULDDEC _TIE_xt_MAC16_ULDDEC +#define XT_SLDDEC _TIE_xt_MAC16_SLDDEC +#define XT_LDINC _TIE_xt_MAC16_LDINC +#define XT_ULDINC _TIE_xt_MAC16_ULDINC +#define XT_SLDINC _TIE_xt_MAC16_SLDINC +#define XT_RSR16 _TIE_xt_MAC16_RSR16 +#define XT_WSR16 _TIE_xt_MAC16_WSR16 +#define XT_XSR16 _TIE_xt_MAC16_XSR16 +#define XT_RSR17 _TIE_xt_MAC16_RSR17 +#define XT_WSR17 _TIE_xt_MAC16_WSR17 +#define XT_XSR17 _TIE_xt_MAC16_XSR17 + +#endif /* __XCC__ */ + +#endif /* __XTENSA__ */ + +#endif /* !_XTENSA_xt_MAC16_HEADER */ diff --git a/tools/sdk/include/esp32/xtensa/tie/xt_MUL32.h b/tools/sdk/include/esp32/xtensa/tie/xt_MUL32.h new file mode 100644 index 00000000..91b3c329 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/tie/xt_MUL32.h @@ -0,0 +1,24 @@ +/* Definitions for the 32-bit Integer Multiply Option. */ + +/* + * Customer ID=11657; Build=0x5fe96; Copyright (c) 2009 by Tensilica Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of Tensilica Inc. + * They may not be modified, copied, reproduced, distributed, or disclosed to + * third parties in any manner, medium, or form, in whole or in part, without + * the prior written consent of Tensilica Inc. + */ + +/* NOTE: This file exists only for backward compatibility with RB-200X.x + and earlier Xtensa releases. Starting with RC-2009.0 you should use + . */ + +#ifndef _XTENSA_xt_MUL32_HEADER +#define _XTENSA_xt_MUL32_HEADER + +#ifdef __XTENSA__ + +#include + +#endif /* __XTENSA__ */ +#endif /* !_XTENSA_xt_MUL32_HEADER */ diff --git a/tools/sdk/include/esp32/xtensa/tie/xt_booleans.h b/tools/sdk/include/esp32/xtensa/tie/xt_booleans.h new file mode 100644 index 00000000..94b5b468 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/tie/xt_booleans.h @@ -0,0 +1,69 @@ +/* Definitions for the xt_booleans TIE package */ + +/* + * Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of Tensilica Inc. + * They may not be modified, copied, reproduced, distributed, or disclosed to + * third parties in any manner, medium, or form, in whole or in part, without + * the prior written consent of Tensilica Inc. + */ + +/* Do not modify. This is automatically generated.*/ + +#ifndef _XTENSA_xt_booleans_HEADER +#define _XTENSA_xt_booleans_HEADER + +#ifdef __XTENSA__ +#ifdef __XCC__ + +#include +typedef _TIE_xtbool xtbool; +typedef _TIE_xtbool2 xtbool2; +typedef _TIE_xtbool4 xtbool4; +typedef _TIE_xtbool8 xtbool8; +typedef _TIE_xtbool16 xtbool16; + +/* + * The following prototypes describe intrinsic functions + * corresponding to TIE instructions. Some TIE instructions + * may produce multiple results (designated as "out" operands + * in the iclass section) or may have operands used as both + * inputs and outputs (designated as "inout"). However, the C + * and C++ languages do not provide syntax that can express + * the in/out/inout constraints of TIE intrinsics. + * Nevertheless, the compiler understands these constraints + * and will check that the intrinsic functions are used + * correctly. To improve the readability of these prototypes, + * the "out" and "inout" parameters are marked accordingly + * with comments. + */ + +extern xtbool _TIE_xt_booleans_XORB(xtbool bs, xtbool bt); +extern xtbool _TIE_xt_booleans_ORBC(xtbool bs, xtbool bt); +extern xtbool _TIE_xt_booleans_ORB(xtbool bs, xtbool bt); +extern xtbool _TIE_xt_booleans_ANDBC(xtbool bs, xtbool bt); +extern xtbool _TIE_xt_booleans_ANDB(xtbool bs, xtbool bt); +extern xtbool _TIE_xt_booleans_ALL4(xtbool4 bs4); +extern xtbool _TIE_xt_booleans_ANY4(xtbool4 bs4); +extern xtbool _TIE_xt_booleans_ALL8(xtbool8 bs8); +extern xtbool _TIE_xt_booleans_ANY8(xtbool8 bs8); +extern void _TIE_xt_booleans_MOVT(unsigned arr /*inout*/, unsigned ars, xtbool bt); +extern void _TIE_xt_booleans_MOVF(unsigned arr /*inout*/, unsigned ars, xtbool bt); +#define XT_XORB _TIE_xt_booleans_XORB +#define XT_ORBC _TIE_xt_booleans_ORBC +#define XT_ORB _TIE_xt_booleans_ORB +#define XT_ANDBC _TIE_xt_booleans_ANDBC +#define XT_ANDB _TIE_xt_booleans_ANDB +#define XT_ALL4 _TIE_xt_booleans_ALL4 +#define XT_ANY4 _TIE_xt_booleans_ANY4 +#define XT_ALL8 _TIE_xt_booleans_ALL8 +#define XT_ANY8 _TIE_xt_booleans_ANY8 +#define XT_MOVT _TIE_xt_booleans_MOVT +#define XT_MOVF _TIE_xt_booleans_MOVF + +#endif /* __XCC__ */ + +#endif /* __XTENSA__ */ + +#endif /* !_XTENSA_xt_booleans_HEADER */ diff --git a/tools/sdk/include/esp32/xtensa/tie/xt_coprocessors.h b/tools/sdk/include/esp32/xtensa/tie/xt_coprocessors.h new file mode 100644 index 00000000..27215cf1 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/tie/xt_coprocessors.h @@ -0,0 +1,48 @@ +/* Definitions for the xt_coprocessors TIE package */ + +/* + * Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of Tensilica Inc. + * They may not be modified, copied, reproduced, distributed, or disclosed to + * third parties in any manner, medium, or form, in whole or in part, without + * the prior written consent of Tensilica Inc. + */ + +/* Do not modify. This is automatically generated.*/ + +#ifndef _XTENSA_xt_coprocessors_HEADER +#define _XTENSA_xt_coprocessors_HEADER + +#ifdef __XTENSA__ +#ifdef __XCC__ + +#include + +/* + * The following prototypes describe intrinsic functions + * corresponding to TIE instructions. Some TIE instructions + * may produce multiple results (designated as "out" operands + * in the iclass section) or may have operands used as both + * inputs and outputs (designated as "inout"). However, the C + * and C++ languages do not provide syntax that can express + * the in/out/inout constraints of TIE intrinsics. + * Nevertheless, the compiler understands these constraints + * and will check that the intrinsic functions are used + * correctly. To improve the readability of these prototypes, + * the "out" and "inout" parameters are marked accordingly + * with comments. + */ + +extern unsigned _TIE_xt_coprocessors_RSR_CPENABLE(void); +extern void _TIE_xt_coprocessors_WSR_CPENABLE(unsigned art); +extern void _TIE_xt_coprocessors_XSR_CPENABLE(unsigned art /*inout*/); +#define XT_RSR_CPENABLE _TIE_xt_coprocessors_RSR_CPENABLE +#define XT_WSR_CPENABLE _TIE_xt_coprocessors_WSR_CPENABLE +#define XT_XSR_CPENABLE _TIE_xt_coprocessors_XSR_CPENABLE + +#endif /* __XCC__ */ + +#endif /* __XTENSA__ */ + +#endif /* !_XTENSA_xt_coprocessors_HEADER */ diff --git a/tools/sdk/include/esp32/xtensa/tie/xt_core.h b/tools/sdk/include/esp32/xtensa/tie/xt_core.h new file mode 100644 index 00000000..469b199e --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/tie/xt_core.h @@ -0,0 +1,395 @@ +/* Definitions for the xt_core TIE package */ + +/* + * Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of Tensilica Inc. + * They may not be modified, copied, reproduced, distributed, or disclosed to + * third parties in any manner, medium, or form, in whole or in part, without + * the prior written consent of Tensilica Inc. + */ + +/* Do not modify. This is automatically generated.*/ + +#ifndef _XTENSA_xt_core_HEADER +#define _XTENSA_xt_core_HEADER + +#ifdef __XTENSA__ +#ifdef __XCC__ + + +/* + * The following prototypes describe intrinsic functions + * corresponding to TIE instructions. Some TIE instructions + * may produce multiple results (designated as "out" operands + * in the iclass section) or may have operands used as both + * inputs and outputs (designated as "inout"). However, the C + * and C++ languages do not provide syntax that can express + * the in/out/inout constraints of TIE intrinsics. + * Nevertheless, the compiler understands these constraints + * and will check that the intrinsic functions are used + * correctly. To improve the readability of these prototypes, + * the "out" and "inout" parameters are marked accordingly + * with comments. + */ + +extern void _TIE_xt_core_ILL(void); +extern void _TIE_xt_core_NOP(void); +extern void _TIE_xt_core_SIMCALL(void); +extern void _TIE_xt_core_MEMW(void); +extern void _TIE_xt_core_EXTW(void); +extern void _TIE_xt_core_ISYNC(void); +extern void _TIE_xt_core_DSYNC(void); +extern void _TIE_xt_core_ESYNC(void); +extern void _TIE_xt_core_RSYNC(void); +extern unsigned _TIE_xt_core_RSR_LBEG(void); +extern void _TIE_xt_core_WSR_LBEG(unsigned art); +extern void _TIE_xt_core_XSR_LBEG(unsigned art /*inout*/); +extern unsigned _TIE_xt_core_RSR_CONFIGID0(void); +extern void _TIE_xt_core_WSR_CONFIGID0(unsigned art); +extern unsigned _TIE_xt_core_RSR_CONFIGID1(void); +extern unsigned _TIE_xt_core_RUR_THREADPTR(void); +extern void _TIE_xt_core_WUR_THREADPTR(unsigned v); +extern unsigned _TIE_xt_core_uint32_loadi(const unsigned * p, immediate o); +extern void _TIE_xt_core_uint32_storei(unsigned c, unsigned * p, immediate o); +extern unsigned _TIE_xt_core_uint32_move(unsigned b); +extern int _TIE_xt_core_ADDI(int s, immediate i); +extern int _TIE_xt_core_OR(int s, int t); +extern int _TIE_xt_core_L32I(const int * p, immediate i); +extern void _TIE_xt_core_S32I(int r, int * p, immediate i); +extern void _TIE_xt_core_S32NB(int r, int * p, immediate i); +extern unsigned char _TIE_xt_core_L8UI(const unsigned char * p, immediate i); +extern void _TIE_xt_core_S8I(signed char r, signed char * p, immediate i); +extern unsigned short _TIE_xt_core_L16UI(const unsigned short * p, immediate i); +extern short _TIE_xt_core_L16SI(const short * p, immediate i); +extern void _TIE_xt_core_S16I(short r, short * p, immediate i); +extern int _TIE_xt_core_ADDMI(int s, immediate i); +extern int _TIE_xt_core_ADD(int s, int t); +extern int _TIE_xt_core_ADDX2(int s, int t); +extern int _TIE_xt_core_ADDX4(int s, int t); +extern int _TIE_xt_core_ADDX8(int s, int t); +extern int _TIE_xt_core_SUB(int s, int t); +extern int _TIE_xt_core_SUBX2(int s, int t); +extern int _TIE_xt_core_SUBX4(int s, int t); +extern int _TIE_xt_core_SUBX8(int s, int t); +extern int _TIE_xt_core_AND(int s, int t); +extern int _TIE_xt_core_XOR(int s, int t); +extern unsigned _TIE_xt_core_EXTUI(unsigned t, immediate i, immediate o); +extern int _TIE_xt_core_MOVI(immediate i); +extern void _TIE_xt_core_MOVEQZ(int r /*inout*/, int s, int t); +extern void _TIE_xt_core_MOVNEZ(int r /*inout*/, int s, int t); +extern void _TIE_xt_core_MOVLTZ(int r /*inout*/, int s, int t); +extern void _TIE_xt_core_MOVGEZ(int r /*inout*/, int s, int t); +extern int _TIE_xt_core_NEG(int t); +extern int _TIE_xt_core_ABS(int t); +extern void _TIE_xt_core_SSR(int s); +extern void _TIE_xt_core_SSL(int s); +extern void _TIE_xt_core_SSA8L(int s); +extern void _TIE_xt_core_SSA8B(int s); +extern void _TIE_xt_core_SSAI(immediate i); +extern int _TIE_xt_core_SLL(int s); +extern int _TIE_xt_core_SRC(int s, int t); +extern unsigned _TIE_xt_core_SRL(unsigned t); +extern int _TIE_xt_core_SRA(int t); +extern int _TIE_xt_core_SLLI(int s, immediate i); +extern int _TIE_xt_core_SRAI(int t, immediate i); +extern unsigned _TIE_xt_core_SRLI(unsigned t, immediate i); +extern int _TIE_xt_core_SSAI_SRC(int src1, int src2, immediate amount); +extern int _TIE_xt_core_SSR_SRC(int src1, int src2, int amount); +extern int _TIE_xt_core_WSR_SAR_SRC(int src1, int src2, int amount); +extern int _TIE_xt_core_SSR_SRA(int src, int amount); +extern unsigned _TIE_xt_core_SSR_SRL(unsigned src, int amount); +extern int _TIE_xt_core_SSL_SLL(int src, int amount); +extern int _TIE_xt_core_RSIL(immediate t); +extern int _TIE_xt_core_RSR_LEND(void); +extern void _TIE_xt_core_WSR_LEND(int t); +extern void _TIE_xt_core_XSR_LEND(int t /*inout*/); +extern int _TIE_xt_core_RSR_LCOUNT(void); +extern void _TIE_xt_core_WSR_LCOUNT(int t); +extern void _TIE_xt_core_XSR_LCOUNT(int t /*inout*/); +extern unsigned _TIE_xt_core_RSR_SAR(void); +extern void _TIE_xt_core_WSR_SAR(unsigned t); +extern void _TIE_xt_core_XSR_SAR(unsigned t /*inout*/); +extern unsigned _TIE_xt_core_RSR_MEMCTL(void); +extern void _TIE_xt_core_WSR_MEMCTL(unsigned t); +extern void _TIE_xt_core_XSR_MEMCTL(unsigned t /*inout*/); +extern unsigned _TIE_xt_core_RSR_LITBASE(void); +extern void _TIE_xt_core_WSR_LITBASE(unsigned t); +extern void _TIE_xt_core_XSR_LITBASE(unsigned t /*inout*/); +extern unsigned _TIE_xt_core_RSR_PS(void); +extern void _TIE_xt_core_WSR_PS(unsigned t); +extern void _TIE_xt_core_XSR_PS(unsigned t /*inout*/); +extern unsigned _TIE_xt_core_RSR_EPC1(void); +extern void _TIE_xt_core_WSR_EPC1(unsigned t); +extern void _TIE_xt_core_XSR_EPC1(unsigned t /*inout*/); +extern unsigned _TIE_xt_core_RSR_EXCSAVE1(void); +extern void _TIE_xt_core_WSR_EXCSAVE1(unsigned t); +extern void _TIE_xt_core_XSR_EXCSAVE1(unsigned t /*inout*/); +extern unsigned _TIE_xt_core_RSR_EPC2(void); +extern void _TIE_xt_core_WSR_EPC2(unsigned t); +extern void _TIE_xt_core_XSR_EPC2(unsigned t /*inout*/); +extern unsigned _TIE_xt_core_RSR_EXCSAVE2(void); +extern void _TIE_xt_core_WSR_EXCSAVE2(unsigned t); +extern void _TIE_xt_core_XSR_EXCSAVE2(unsigned t /*inout*/); +extern unsigned _TIE_xt_core_RSR_EPC3(void); +extern void _TIE_xt_core_WSR_EPC3(unsigned t); +extern void _TIE_xt_core_XSR_EPC3(unsigned t /*inout*/); +extern unsigned _TIE_xt_core_RSR_EXCSAVE3(void); +extern void _TIE_xt_core_WSR_EXCSAVE3(unsigned t); +extern void _TIE_xt_core_XSR_EXCSAVE3(unsigned t /*inout*/); +extern unsigned _TIE_xt_core_RSR_EPC4(void); +extern void _TIE_xt_core_WSR_EPC4(unsigned t); +extern void _TIE_xt_core_XSR_EPC4(unsigned t /*inout*/); +extern unsigned _TIE_xt_core_RSR_EXCSAVE4(void); +extern void _TIE_xt_core_WSR_EXCSAVE4(unsigned t); +extern void _TIE_xt_core_XSR_EXCSAVE4(unsigned t /*inout*/); +extern unsigned _TIE_xt_core_RSR_EPC5(void); +extern void _TIE_xt_core_WSR_EPC5(unsigned t); +extern void _TIE_xt_core_XSR_EPC5(unsigned t /*inout*/); +extern unsigned _TIE_xt_core_RSR_EXCSAVE5(void); +extern void _TIE_xt_core_WSR_EXCSAVE5(unsigned t); +extern void _TIE_xt_core_XSR_EXCSAVE5(unsigned t /*inout*/); +extern unsigned _TIE_xt_core_RSR_EPC6(void); +extern void _TIE_xt_core_WSR_EPC6(unsigned t); +extern void _TIE_xt_core_XSR_EPC6(unsigned t /*inout*/); +extern unsigned _TIE_xt_core_RSR_EXCSAVE6(void); +extern void _TIE_xt_core_WSR_EXCSAVE6(unsigned t); +extern void _TIE_xt_core_XSR_EXCSAVE6(unsigned t /*inout*/); +extern unsigned _TIE_xt_core_RSR_EPC7(void); +extern void _TIE_xt_core_WSR_EPC7(unsigned t); +extern void _TIE_xt_core_XSR_EPC7(unsigned t /*inout*/); +extern unsigned _TIE_xt_core_RSR_EXCSAVE7(void); +extern void _TIE_xt_core_WSR_EXCSAVE7(unsigned t); +extern void _TIE_xt_core_XSR_EXCSAVE7(unsigned t /*inout*/); +extern unsigned _TIE_xt_core_RSR_VECBASE(void); +extern void _TIE_xt_core_WSR_VECBASE(unsigned t); +extern void _TIE_xt_core_XSR_VECBASE(unsigned t /*inout*/); +extern unsigned _TIE_xt_core_RSR_EPS2(void); +extern void _TIE_xt_core_WSR_EPS2(unsigned t); +extern void _TIE_xt_core_XSR_EPS2(unsigned t /*inout*/); +extern unsigned _TIE_xt_core_RSR_EPS3(void); +extern void _TIE_xt_core_WSR_EPS3(unsigned t); +extern void _TIE_xt_core_XSR_EPS3(unsigned t /*inout*/); +extern unsigned _TIE_xt_core_RSR_EPS4(void); +extern void _TIE_xt_core_WSR_EPS4(unsigned t); +extern void _TIE_xt_core_XSR_EPS4(unsigned t /*inout*/); +extern unsigned _TIE_xt_core_RSR_EPS5(void); +extern void _TIE_xt_core_WSR_EPS5(unsigned t); +extern void _TIE_xt_core_XSR_EPS5(unsigned t /*inout*/); +extern unsigned _TIE_xt_core_RSR_EPS6(void); +extern void _TIE_xt_core_WSR_EPS6(unsigned t); +extern void _TIE_xt_core_XSR_EPS6(unsigned t /*inout*/); +extern unsigned _TIE_xt_core_RSR_EPS7(void); +extern void _TIE_xt_core_WSR_EPS7(unsigned t); +extern void _TIE_xt_core_XSR_EPS7(unsigned t /*inout*/); +extern unsigned _TIE_xt_core_RSR_EXCCAUSE(void); +extern void _TIE_xt_core_WSR_EXCCAUSE(unsigned t); +extern void _TIE_xt_core_XSR_EXCCAUSE(unsigned t /*inout*/); +extern unsigned _TIE_xt_core_RSR_EXCVADDR(void); +extern void _TIE_xt_core_WSR_EXCVADDR(unsigned t); +extern void _TIE_xt_core_XSR_EXCVADDR(unsigned t /*inout*/); +extern unsigned _TIE_xt_core_RSR_DEPC(void); +extern void _TIE_xt_core_WSR_DEPC(unsigned t); +extern void _TIE_xt_core_XSR_DEPC(unsigned t /*inout*/); +extern unsigned _TIE_xt_core_RSR_MISC0(void); +extern void _TIE_xt_core_WSR_MISC0(unsigned t); +extern void _TIE_xt_core_XSR_MISC0(unsigned t /*inout*/); +extern unsigned _TIE_xt_core_RSR_MISC1(void); +extern void _TIE_xt_core_WSR_MISC1(unsigned t); +extern void _TIE_xt_core_XSR_MISC1(unsigned t /*inout*/); +extern unsigned _TIE_xt_core_RSR_MISC2(void); +extern void _TIE_xt_core_WSR_MISC2(unsigned t); +extern void _TIE_xt_core_XSR_MISC2(unsigned t /*inout*/); +extern unsigned _TIE_xt_core_RSR_MISC3(void); +extern void _TIE_xt_core_WSR_MISC3(unsigned t); +extern void _TIE_xt_core_XSR_MISC3(unsigned t /*inout*/); +extern int _TIE_xt_core_RSR_PRID(void); +#define XT_ILL _TIE_xt_core_ILL +#define XT_NOP _TIE_xt_core_NOP +#define XT_SIMCALL _TIE_xt_core_SIMCALL +#define XT_MEMW _TIE_xt_core_MEMW +#define XT_EXTW _TIE_xt_core_EXTW +#define XT_ISYNC _TIE_xt_core_ISYNC +#define XT_DSYNC _TIE_xt_core_DSYNC +#define XT_ESYNC _TIE_xt_core_ESYNC +#define XT_RSYNC _TIE_xt_core_RSYNC +#define XT_RSR_LBEG _TIE_xt_core_RSR_LBEG +#define XT_WSR_LBEG _TIE_xt_core_WSR_LBEG +#define XT_XSR_LBEG _TIE_xt_core_XSR_LBEG +#define XT_RSR_CONFIGID0 _TIE_xt_core_RSR_CONFIGID0 +#define XT_WSR_CONFIGID0 _TIE_xt_core_WSR_CONFIGID0 +#define XT_RSR_CONFIGID1 _TIE_xt_core_RSR_CONFIGID1 +#define XT_RUR_THREADPTR _TIE_xt_core_RUR_THREADPTR +#define RTHREADPTR _TIE_xt_core_RUR_THREADPTR +#define RUR231 _TIE_xt_core_RUR_THREADPTR +#define XT_WUR_THREADPTR _TIE_xt_core_WUR_THREADPTR +#define WTHREADPTR _TIE_xt_core_WUR_THREADPTR +#define WUR231 _TIE_xt_core_WUR_THREADPTR +#define XT_uint32_loadi _TIE_xt_core_uint32_loadi +#define XT_uint32_storei _TIE_xt_core_uint32_storei +#define XT_uint32_move _TIE_xt_core_uint32_move +#define XT_ADDI _TIE_xt_core_ADDI +#define XT_OR _TIE_xt_core_OR +#define XT_L32I _TIE_xt_core_L32I +#define XT_S32I _TIE_xt_core_S32I +#define XT_S32NB _TIE_xt_core_S32NB +#define XT_L8UI _TIE_xt_core_L8UI +#define XT_S8I _TIE_xt_core_S8I +#define XT_L16UI _TIE_xt_core_L16UI +#define XT_L16SI _TIE_xt_core_L16SI +#define XT_S16I _TIE_xt_core_S16I +#define XT_ADDMI _TIE_xt_core_ADDMI +#define XT_ADD _TIE_xt_core_ADD +#define XT_ADDX2 _TIE_xt_core_ADDX2 +#define XT_ADDX4 _TIE_xt_core_ADDX4 +#define XT_ADDX8 _TIE_xt_core_ADDX8 +#define XT_SUB _TIE_xt_core_SUB +#define XT_SUBX2 _TIE_xt_core_SUBX2 +#define XT_SUBX4 _TIE_xt_core_SUBX4 +#define XT_SUBX8 _TIE_xt_core_SUBX8 +#define XT_AND _TIE_xt_core_AND +#define XT_XOR _TIE_xt_core_XOR +#define XT_EXTUI _TIE_xt_core_EXTUI +#define XT_MOVI _TIE_xt_core_MOVI +#define XT_MOVEQZ _TIE_xt_core_MOVEQZ +#define XT_MOVNEZ _TIE_xt_core_MOVNEZ +#define XT_MOVLTZ _TIE_xt_core_MOVLTZ +#define XT_MOVGEZ _TIE_xt_core_MOVGEZ +#define XT_NEG _TIE_xt_core_NEG +#define XT_ABS _TIE_xt_core_ABS +#define XT_SSR _TIE_xt_core_SSR +#define XT_SSL _TIE_xt_core_SSL +#define XT_SSA8L _TIE_xt_core_SSA8L +#define XT_SSA8B _TIE_xt_core_SSA8B +#define XT_SSAI _TIE_xt_core_SSAI +#define XT_SLL _TIE_xt_core_SLL +#define XT_SRC _TIE_xt_core_SRC +#define XT_SRL _TIE_xt_core_SRL +#define XT_SRA _TIE_xt_core_SRA +#define XT_SLLI _TIE_xt_core_SLLI +#define XT_SRAI _TIE_xt_core_SRAI +#define XT_SRLI _TIE_xt_core_SRLI +#define XT_SSAI_SRC _TIE_xt_core_SSAI_SRC +#define XT_SSR_SRC _TIE_xt_core_SSR_SRC +#define XT_WSR_SAR_SRC _TIE_xt_core_WSR_SAR_SRC +#define XT_SSR_SRA _TIE_xt_core_SSR_SRA +#define XT_SSR_SRL _TIE_xt_core_SSR_SRL +#define XT_SSL_SLL _TIE_xt_core_SSL_SLL +#define XT_RSIL _TIE_xt_core_RSIL +#define XT_RSR_LEND _TIE_xt_core_RSR_LEND +#define XT_WSR_LEND _TIE_xt_core_WSR_LEND +#define XT_XSR_LEND _TIE_xt_core_XSR_LEND +#define XT_RSR_LCOUNT _TIE_xt_core_RSR_LCOUNT +#define XT_WSR_LCOUNT _TIE_xt_core_WSR_LCOUNT +#define XT_XSR_LCOUNT _TIE_xt_core_XSR_LCOUNT +#define XT_RSR_SAR _TIE_xt_core_RSR_SAR +#define XT_WSR_SAR _TIE_xt_core_WSR_SAR +#define XT_XSR_SAR _TIE_xt_core_XSR_SAR +#define XT_RSR_MEMCTL _TIE_xt_core_RSR_MEMCTL +#define XT_WSR_MEMCTL _TIE_xt_core_WSR_MEMCTL +#define XT_XSR_MEMCTL _TIE_xt_core_XSR_MEMCTL +#define XT_RSR_LITBASE _TIE_xt_core_RSR_LITBASE +#define XT_WSR_LITBASE _TIE_xt_core_WSR_LITBASE +#define XT_XSR_LITBASE _TIE_xt_core_XSR_LITBASE +#define XT_RSR_PS _TIE_xt_core_RSR_PS +#define XT_WSR_PS _TIE_xt_core_WSR_PS +#define XT_XSR_PS _TIE_xt_core_XSR_PS +#define XT_RSR_EPC1 _TIE_xt_core_RSR_EPC1 +#define XT_WSR_EPC1 _TIE_xt_core_WSR_EPC1 +#define XT_XSR_EPC1 _TIE_xt_core_XSR_EPC1 +#define XT_RSR_EXCSAVE1 _TIE_xt_core_RSR_EXCSAVE1 +#define XT_WSR_EXCSAVE1 _TIE_xt_core_WSR_EXCSAVE1 +#define XT_XSR_EXCSAVE1 _TIE_xt_core_XSR_EXCSAVE1 +#define XT_RSR_EPC2 _TIE_xt_core_RSR_EPC2 +#define XT_WSR_EPC2 _TIE_xt_core_WSR_EPC2 +#define XT_XSR_EPC2 _TIE_xt_core_XSR_EPC2 +#define XT_RSR_EXCSAVE2 _TIE_xt_core_RSR_EXCSAVE2 +#define XT_WSR_EXCSAVE2 _TIE_xt_core_WSR_EXCSAVE2 +#define XT_XSR_EXCSAVE2 _TIE_xt_core_XSR_EXCSAVE2 +#define XT_RSR_EPC3 _TIE_xt_core_RSR_EPC3 +#define XT_WSR_EPC3 _TIE_xt_core_WSR_EPC3 +#define XT_XSR_EPC3 _TIE_xt_core_XSR_EPC3 +#define XT_RSR_EXCSAVE3 _TIE_xt_core_RSR_EXCSAVE3 +#define XT_WSR_EXCSAVE3 _TIE_xt_core_WSR_EXCSAVE3 +#define XT_XSR_EXCSAVE3 _TIE_xt_core_XSR_EXCSAVE3 +#define XT_RSR_EPC4 _TIE_xt_core_RSR_EPC4 +#define XT_WSR_EPC4 _TIE_xt_core_WSR_EPC4 +#define XT_XSR_EPC4 _TIE_xt_core_XSR_EPC4 +#define XT_RSR_EXCSAVE4 _TIE_xt_core_RSR_EXCSAVE4 +#define XT_WSR_EXCSAVE4 _TIE_xt_core_WSR_EXCSAVE4 +#define XT_XSR_EXCSAVE4 _TIE_xt_core_XSR_EXCSAVE4 +#define XT_RSR_EPC5 _TIE_xt_core_RSR_EPC5 +#define XT_WSR_EPC5 _TIE_xt_core_WSR_EPC5 +#define XT_XSR_EPC5 _TIE_xt_core_XSR_EPC5 +#define XT_RSR_EXCSAVE5 _TIE_xt_core_RSR_EXCSAVE5 +#define XT_WSR_EXCSAVE5 _TIE_xt_core_WSR_EXCSAVE5 +#define XT_XSR_EXCSAVE5 _TIE_xt_core_XSR_EXCSAVE5 +#define XT_RSR_EPC6 _TIE_xt_core_RSR_EPC6 +#define XT_WSR_EPC6 _TIE_xt_core_WSR_EPC6 +#define XT_XSR_EPC6 _TIE_xt_core_XSR_EPC6 +#define XT_RSR_EXCSAVE6 _TIE_xt_core_RSR_EXCSAVE6 +#define XT_WSR_EXCSAVE6 _TIE_xt_core_WSR_EXCSAVE6 +#define XT_XSR_EXCSAVE6 _TIE_xt_core_XSR_EXCSAVE6 +#define XT_RSR_EPC7 _TIE_xt_core_RSR_EPC7 +#define XT_WSR_EPC7 _TIE_xt_core_WSR_EPC7 +#define XT_XSR_EPC7 _TIE_xt_core_XSR_EPC7 +#define XT_RSR_EXCSAVE7 _TIE_xt_core_RSR_EXCSAVE7 +#define XT_WSR_EXCSAVE7 _TIE_xt_core_WSR_EXCSAVE7 +#define XT_XSR_EXCSAVE7 _TIE_xt_core_XSR_EXCSAVE7 +#define XT_RSR_VECBASE _TIE_xt_core_RSR_VECBASE +#define XT_WSR_VECBASE _TIE_xt_core_WSR_VECBASE +#define XT_XSR_VECBASE _TIE_xt_core_XSR_VECBASE +#define XT_RSR_EPS2 _TIE_xt_core_RSR_EPS2 +#define XT_WSR_EPS2 _TIE_xt_core_WSR_EPS2 +#define XT_XSR_EPS2 _TIE_xt_core_XSR_EPS2 +#define XT_RSR_EPS3 _TIE_xt_core_RSR_EPS3 +#define XT_WSR_EPS3 _TIE_xt_core_WSR_EPS3 +#define XT_XSR_EPS3 _TIE_xt_core_XSR_EPS3 +#define XT_RSR_EPS4 _TIE_xt_core_RSR_EPS4 +#define XT_WSR_EPS4 _TIE_xt_core_WSR_EPS4 +#define XT_XSR_EPS4 _TIE_xt_core_XSR_EPS4 +#define XT_RSR_EPS5 _TIE_xt_core_RSR_EPS5 +#define XT_WSR_EPS5 _TIE_xt_core_WSR_EPS5 +#define XT_XSR_EPS5 _TIE_xt_core_XSR_EPS5 +#define XT_RSR_EPS6 _TIE_xt_core_RSR_EPS6 +#define XT_WSR_EPS6 _TIE_xt_core_WSR_EPS6 +#define XT_XSR_EPS6 _TIE_xt_core_XSR_EPS6 +#define XT_RSR_EPS7 _TIE_xt_core_RSR_EPS7 +#define XT_WSR_EPS7 _TIE_xt_core_WSR_EPS7 +#define XT_XSR_EPS7 _TIE_xt_core_XSR_EPS7 +#define XT_RSR_EXCCAUSE _TIE_xt_core_RSR_EXCCAUSE +#define XT_WSR_EXCCAUSE _TIE_xt_core_WSR_EXCCAUSE +#define XT_XSR_EXCCAUSE _TIE_xt_core_XSR_EXCCAUSE +#define XT_RSR_EXCVADDR _TIE_xt_core_RSR_EXCVADDR +#define XT_WSR_EXCVADDR _TIE_xt_core_WSR_EXCVADDR +#define XT_XSR_EXCVADDR _TIE_xt_core_XSR_EXCVADDR +#define XT_RSR_DEPC _TIE_xt_core_RSR_DEPC +#define XT_WSR_DEPC _TIE_xt_core_WSR_DEPC +#define XT_XSR_DEPC _TIE_xt_core_XSR_DEPC +#define XT_RSR_MISC0 _TIE_xt_core_RSR_MISC0 +#define XT_WSR_MISC0 _TIE_xt_core_WSR_MISC0 +#define XT_XSR_MISC0 _TIE_xt_core_XSR_MISC0 +#define XT_RSR_MISC1 _TIE_xt_core_RSR_MISC1 +#define XT_WSR_MISC1 _TIE_xt_core_WSR_MISC1 +#define XT_XSR_MISC1 _TIE_xt_core_XSR_MISC1 +#define XT_RSR_MISC2 _TIE_xt_core_RSR_MISC2 +#define XT_WSR_MISC2 _TIE_xt_core_WSR_MISC2 +#define XT_XSR_MISC2 _TIE_xt_core_XSR_MISC2 +#define XT_RSR_MISC3 _TIE_xt_core_RSR_MISC3 +#define XT_WSR_MISC3 _TIE_xt_core_WSR_MISC3 +#define XT_XSR_MISC3 _TIE_xt_core_XSR_MISC3 +#define XT_RSR_PRID _TIE_xt_core_RSR_PRID + +#ifndef RUR +#define RUR(NUM) RUR##NUM() +#endif + +#ifndef WUR +#define WUR(VAL, NUM) WUR##NUM(VAL) +#endif + +#endif /* __XCC__ */ + +#endif /* __XTENSA__ */ + +#endif /* !_XTENSA_xt_core_HEADER */ diff --git a/tools/sdk/include/esp32/xtensa/tie/xt_debug.h b/tools/sdk/include/esp32/xtensa/tie/xt_debug.h new file mode 100644 index 00000000..676fd33c --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/tie/xt_debug.h @@ -0,0 +1,116 @@ +/* Definitions for the xt_debug TIE package */ + +/* + * Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of Tensilica Inc. + * They may not be modified, copied, reproduced, distributed, or disclosed to + * third parties in any manner, medium, or form, in whole or in part, without + * the prior written consent of Tensilica Inc. + */ + +/* Do not modify. This is automatically generated.*/ + +#ifndef _XTENSA_xt_debug_HEADER +#define _XTENSA_xt_debug_HEADER + +#ifdef __XTENSA__ +#ifdef __XCC__ + +#include + +/* + * The following prototypes describe intrinsic functions + * corresponding to TIE instructions. Some TIE instructions + * may produce multiple results (designated as "out" operands + * in the iclass section) or may have operands used as both + * inputs and outputs (designated as "inout"). However, the C + * and C++ languages do not provide syntax that can express + * the in/out/inout constraints of TIE intrinsics. + * Nevertheless, the compiler understands these constraints + * and will check that the intrinsic functions are used + * correctly. To improve the readability of these prototypes, + * the "out" and "inout" parameters are marked accordingly + * with comments. + */ + +extern void _TIE_xt_debug_BREAK(immediate imms, immediate immt); +extern void _TIE_xt_debug_BREAK_N(immediate imms); +extern unsigned _TIE_xt_debug_RSR_DBREAKA0(void); +extern void _TIE_xt_debug_WSR_DBREAKA0(unsigned art); +extern void _TIE_xt_debug_XSR_DBREAKA0(unsigned art /*inout*/); +extern unsigned _TIE_xt_debug_RSR_DBREAKC0(void); +extern void _TIE_xt_debug_WSR_DBREAKC0(unsigned art); +extern void _TIE_xt_debug_XSR_DBREAKC0(unsigned art /*inout*/); +extern unsigned _TIE_xt_debug_RSR_DBREAKA1(void); +extern void _TIE_xt_debug_WSR_DBREAKA1(unsigned art); +extern void _TIE_xt_debug_XSR_DBREAKA1(unsigned art /*inout*/); +extern unsigned _TIE_xt_debug_RSR_DBREAKC1(void); +extern void _TIE_xt_debug_WSR_DBREAKC1(unsigned art); +extern void _TIE_xt_debug_XSR_DBREAKC1(unsigned art /*inout*/); +extern unsigned _TIE_xt_debug_RSR_IBREAKA0(void); +extern void _TIE_xt_debug_WSR_IBREAKA0(unsigned art); +extern void _TIE_xt_debug_XSR_IBREAKA0(unsigned art /*inout*/); +extern unsigned _TIE_xt_debug_RSR_IBREAKA1(void); +extern void _TIE_xt_debug_WSR_IBREAKA1(unsigned art); +extern void _TIE_xt_debug_XSR_IBREAKA1(unsigned art /*inout*/); +extern unsigned _TIE_xt_debug_RSR_IBREAKENABLE(void); +extern void _TIE_xt_debug_WSR_IBREAKENABLE(unsigned art); +extern void _TIE_xt_debug_XSR_IBREAKENABLE(unsigned art /*inout*/); +extern unsigned _TIE_xt_debug_RSR_DEBUGCAUSE(void); +extern void _TIE_xt_debug_WSR_DEBUGCAUSE(unsigned art); +extern void _TIE_xt_debug_XSR_DEBUGCAUSE(unsigned art /*inout*/); +extern unsigned _TIE_xt_debug_RSR_ICOUNT(void); +extern void _TIE_xt_debug_WSR_ICOUNT(unsigned art); +extern void _TIE_xt_debug_XSR_ICOUNT(unsigned art /*inout*/); +extern unsigned _TIE_xt_debug_RSR_ICOUNTLEVEL(void); +extern void _TIE_xt_debug_WSR_ICOUNTLEVEL(unsigned art); +extern void _TIE_xt_debug_XSR_ICOUNTLEVEL(unsigned art /*inout*/); +extern unsigned _TIE_xt_debug_RSR_DDR(void); +extern void _TIE_xt_debug_WSR_DDR(unsigned art); +extern void _TIE_xt_debug_XSR_DDR(unsigned art /*inout*/); +extern void _TIE_xt_debug_LDDR32_P(const void * ars /*inout*/); +extern void _TIE_xt_debug_SDDR32_P(void * ars /*inout*/); +#define XT_BREAK _TIE_xt_debug_BREAK +#define XT_BREAK_N _TIE_xt_debug_BREAK_N +#define XT_RSR_DBREAKA0 _TIE_xt_debug_RSR_DBREAKA0 +#define XT_WSR_DBREAKA0 _TIE_xt_debug_WSR_DBREAKA0 +#define XT_XSR_DBREAKA0 _TIE_xt_debug_XSR_DBREAKA0 +#define XT_RSR_DBREAKC0 _TIE_xt_debug_RSR_DBREAKC0 +#define XT_WSR_DBREAKC0 _TIE_xt_debug_WSR_DBREAKC0 +#define XT_XSR_DBREAKC0 _TIE_xt_debug_XSR_DBREAKC0 +#define XT_RSR_DBREAKA1 _TIE_xt_debug_RSR_DBREAKA1 +#define XT_WSR_DBREAKA1 _TIE_xt_debug_WSR_DBREAKA1 +#define XT_XSR_DBREAKA1 _TIE_xt_debug_XSR_DBREAKA1 +#define XT_RSR_DBREAKC1 _TIE_xt_debug_RSR_DBREAKC1 +#define XT_WSR_DBREAKC1 _TIE_xt_debug_WSR_DBREAKC1 +#define XT_XSR_DBREAKC1 _TIE_xt_debug_XSR_DBREAKC1 +#define XT_RSR_IBREAKA0 _TIE_xt_debug_RSR_IBREAKA0 +#define XT_WSR_IBREAKA0 _TIE_xt_debug_WSR_IBREAKA0 +#define XT_XSR_IBREAKA0 _TIE_xt_debug_XSR_IBREAKA0 +#define XT_RSR_IBREAKA1 _TIE_xt_debug_RSR_IBREAKA1 +#define XT_WSR_IBREAKA1 _TIE_xt_debug_WSR_IBREAKA1 +#define XT_XSR_IBREAKA1 _TIE_xt_debug_XSR_IBREAKA1 +#define XT_RSR_IBREAKENABLE _TIE_xt_debug_RSR_IBREAKENABLE +#define XT_WSR_IBREAKENABLE _TIE_xt_debug_WSR_IBREAKENABLE +#define XT_XSR_IBREAKENABLE _TIE_xt_debug_XSR_IBREAKENABLE +#define XT_RSR_DEBUGCAUSE _TIE_xt_debug_RSR_DEBUGCAUSE +#define XT_WSR_DEBUGCAUSE _TIE_xt_debug_WSR_DEBUGCAUSE +#define XT_XSR_DEBUGCAUSE _TIE_xt_debug_XSR_DEBUGCAUSE +#define XT_RSR_ICOUNT _TIE_xt_debug_RSR_ICOUNT +#define XT_WSR_ICOUNT _TIE_xt_debug_WSR_ICOUNT +#define XT_XSR_ICOUNT _TIE_xt_debug_XSR_ICOUNT +#define XT_RSR_ICOUNTLEVEL _TIE_xt_debug_RSR_ICOUNTLEVEL +#define XT_WSR_ICOUNTLEVEL _TIE_xt_debug_WSR_ICOUNTLEVEL +#define XT_XSR_ICOUNTLEVEL _TIE_xt_debug_XSR_ICOUNTLEVEL +#define XT_RSR_DDR _TIE_xt_debug_RSR_DDR +#define XT_WSR_DDR _TIE_xt_debug_WSR_DDR +#define XT_XSR_DDR _TIE_xt_debug_XSR_DDR +#define XT_LDDR32_P _TIE_xt_debug_LDDR32_P +#define XT_SDDR32_P _TIE_xt_debug_SDDR32_P + +#endif /* __XCC__ */ + +#endif /* __XTENSA__ */ + +#endif /* !_XTENSA_xt_debug_HEADER */ diff --git a/tools/sdk/include/esp32/xtensa/tie/xt_density.h b/tools/sdk/include/esp32/xtensa/tie/xt_density.h new file mode 100644 index 00000000..da5c51cc --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/tie/xt_density.h @@ -0,0 +1,58 @@ +/* Definitions for the xt_density TIE package */ + +/* + * Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of Tensilica Inc. + * They may not be modified, copied, reproduced, distributed, or disclosed to + * third parties in any manner, medium, or form, in whole or in part, without + * the prior written consent of Tensilica Inc. + */ + +/* Do not modify. This is automatically generated.*/ + +#ifndef _XTENSA_xt_density_HEADER +#define _XTENSA_xt_density_HEADER + +#ifdef __XTENSA__ +#ifdef __XCC__ + +#include + +/* + * The following prototypes describe intrinsic functions + * corresponding to TIE instructions. Some TIE instructions + * may produce multiple results (designated as "out" operands + * in the iclass section) or may have operands used as both + * inputs and outputs (designated as "inout"). However, the C + * and C++ languages do not provide syntax that can express + * the in/out/inout constraints of TIE intrinsics. + * Nevertheless, the compiler understands these constraints + * and will check that the intrinsic functions are used + * correctly. To improve the readability of these prototypes, + * the "out" and "inout" parameters are marked accordingly + * with comments. + */ + +extern void _TIE_xt_density_ILL_N(void); +extern void _TIE_xt_density_NOP_N(void); +extern int _TIE_xt_density_L32I_N(const int * p, immediate i); +extern void _TIE_xt_density_S32I_N(int t, int * p, immediate i); +extern int _TIE_xt_density_ADD_N(int s, int t); +extern int _TIE_xt_density_ADDI_N(int s, immediate i); +extern int _TIE_xt_density_MOV_N(int s); +extern int _TIE_xt_density_MOVI_N(immediate i); +#define XT_ILL_N _TIE_xt_density_ILL_N +#define XT_NOP_N _TIE_xt_density_NOP_N +#define XT_L32I_N _TIE_xt_density_L32I_N +#define XT_S32I_N _TIE_xt_density_S32I_N +#define XT_ADD_N _TIE_xt_density_ADD_N +#define XT_ADDI_N _TIE_xt_density_ADDI_N +#define XT_MOV_N _TIE_xt_density_MOV_N +#define XT_MOVI_N _TIE_xt_density_MOVI_N + +#endif /* __XCC__ */ + +#endif /* __XTENSA__ */ + +#endif /* !_XTENSA_xt_density_HEADER */ diff --git a/tools/sdk/include/esp32/xtensa/tie/xt_exceptions.h b/tools/sdk/include/esp32/xtensa/tie/xt_exceptions.h new file mode 100644 index 00000000..64fb3930 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/tie/xt_exceptions.h @@ -0,0 +1,45 @@ +/* Definitions for the xt_exceptions TIE package */ + +/* + * Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of Tensilica Inc. + * They may not be modified, copied, reproduced, distributed, or disclosed to + * third parties in any manner, medium, or form, in whole or in part, without + * the prior written consent of Tensilica Inc. + */ + +/* Do not modify. This is automatically generated.*/ + +#ifndef _XTENSA_xt_exceptions_HEADER +#define _XTENSA_xt_exceptions_HEADER + +#ifdef __XTENSA__ +#ifdef __XCC__ + + +/* + * The following prototypes describe intrinsic functions + * corresponding to TIE instructions. Some TIE instructions + * may produce multiple results (designated as "out" operands + * in the iclass section) or may have operands used as both + * inputs and outputs (designated as "inout"). However, the C + * and C++ languages do not provide syntax that can express + * the in/out/inout constraints of TIE intrinsics. + * Nevertheless, the compiler understands these constraints + * and will check that the intrinsic functions are used + * correctly. To improve the readability of these prototypes, + * the "out" and "inout" parameters are marked accordingly + * with comments. + */ + +extern void _TIE_xt_exceptions_EXCW(void); +extern void _TIE_xt_exceptions_SYSCALL(void); +#define XT_EXCW _TIE_xt_exceptions_EXCW +#define XT_SYSCALL _TIE_xt_exceptions_SYSCALL + +#endif /* __XCC__ */ + +#endif /* __XTENSA__ */ + +#endif /* !_XTENSA_xt_exceptions_HEADER */ diff --git a/tools/sdk/include/esp32/xtensa/tie/xt_externalregisters.h b/tools/sdk/include/esp32/xtensa/tie/xt_externalregisters.h new file mode 100644 index 00000000..3196527c --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/tie/xt_externalregisters.h @@ -0,0 +1,46 @@ +/* Definitions for the xt_externalregisters TIE package */ + +/* + * Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of Tensilica Inc. + * They may not be modified, copied, reproduced, distributed, or disclosed to + * third parties in any manner, medium, or form, in whole or in part, without + * the prior written consent of Tensilica Inc. + */ + +/* Do not modify. This is automatically generated.*/ + +#ifndef _XTENSA_xt_externalregisters_HEADER +#define _XTENSA_xt_externalregisters_HEADER + +#ifdef __XTENSA__ +#ifdef __XCC__ + +#include + +/* + * The following prototypes describe intrinsic functions + * corresponding to TIE instructions. Some TIE instructions + * may produce multiple results (designated as "out" operands + * in the iclass section) or may have operands used as both + * inputs and outputs (designated as "inout"). However, the C + * and C++ languages do not provide syntax that can express + * the in/out/inout constraints of TIE intrinsics. + * Nevertheless, the compiler understands these constraints + * and will check that the intrinsic functions are used + * correctly. To improve the readability of these prototypes, + * the "out" and "inout" parameters are marked accordingly + * with comments. + */ + +extern unsigned _TIE_xt_externalregisters_RER(unsigned ars); +extern void _TIE_xt_externalregisters_WER(unsigned art, unsigned ars); +#define XT_RER _TIE_xt_externalregisters_RER +#define XT_WER _TIE_xt_externalregisters_WER + +#endif /* __XCC__ */ + +#endif /* __XTENSA__ */ + +#endif /* !_XTENSA_xt_externalregisters_HEADER */ diff --git a/tools/sdk/include/esp32/xtensa/tie/xt_integerdivide.h b/tools/sdk/include/esp32/xtensa/tie/xt_integerdivide.h new file mode 100644 index 00000000..9fbe9615 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/tie/xt_integerdivide.h @@ -0,0 +1,50 @@ +/* Definitions for the xt_integerdivide TIE package */ + +/* + * Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of Tensilica Inc. + * They may not be modified, copied, reproduced, distributed, or disclosed to + * third parties in any manner, medium, or form, in whole or in part, without + * the prior written consent of Tensilica Inc. + */ + +/* Do not modify. This is automatically generated.*/ + +#ifndef _XTENSA_xt_integerdivide_HEADER +#define _XTENSA_xt_integerdivide_HEADER + +#ifdef __XTENSA__ +#ifdef __XCC__ + +#include + +/* + * The following prototypes describe intrinsic functions + * corresponding to TIE instructions. Some TIE instructions + * may produce multiple results (designated as "out" operands + * in the iclass section) or may have operands used as both + * inputs and outputs (designated as "inout"). However, the C + * and C++ languages do not provide syntax that can express + * the in/out/inout constraints of TIE intrinsics. + * Nevertheless, the compiler understands these constraints + * and will check that the intrinsic functions are used + * correctly. To improve the readability of these prototypes, + * the "out" and "inout" parameters are marked accordingly + * with comments. + */ + +extern unsigned _TIE_xt_integerdivide_REMS(unsigned ars, unsigned art); +extern unsigned _TIE_xt_integerdivide_REMU(unsigned ars, unsigned art); +extern unsigned _TIE_xt_integerdivide_QUOS(unsigned ars, unsigned art); +extern unsigned _TIE_xt_integerdivide_QUOU(unsigned ars, unsigned art); +#define XT_REMS _TIE_xt_integerdivide_REMS +#define XT_REMU _TIE_xt_integerdivide_REMU +#define XT_QUOS _TIE_xt_integerdivide_QUOS +#define XT_QUOU _TIE_xt_integerdivide_QUOU + +#endif /* __XCC__ */ + +#endif /* __XTENSA__ */ + +#endif /* !_XTENSA_xt_integerdivide_HEADER */ diff --git a/tools/sdk/include/esp32/xtensa/tie/xt_interrupt.h b/tools/sdk/include/esp32/xtensa/tie/xt_interrupt.h new file mode 100644 index 00000000..b20c94f4 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/tie/xt_interrupt.h @@ -0,0 +1,56 @@ +/* Definitions for the xt_interrupt TIE package */ + +/* + * Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of Tensilica Inc. + * They may not be modified, copied, reproduced, distributed, or disclosed to + * third parties in any manner, medium, or form, in whole or in part, without + * the prior written consent of Tensilica Inc. + */ + +/* Do not modify. This is automatically generated.*/ + +#ifndef _XTENSA_xt_interrupt_HEADER +#define _XTENSA_xt_interrupt_HEADER + +#ifdef __XTENSA__ +#ifdef __XCC__ + +#include + +/* + * The following prototypes describe intrinsic functions + * corresponding to TIE instructions. Some TIE instructions + * may produce multiple results (designated as "out" operands + * in the iclass section) or may have operands used as both + * inputs and outputs (designated as "inout"). However, the C + * and C++ languages do not provide syntax that can express + * the in/out/inout constraints of TIE intrinsics. + * Nevertheless, the compiler understands these constraints + * and will check that the intrinsic functions are used + * correctly. To improve the readability of these prototypes, + * the "out" and "inout" parameters are marked accordingly + * with comments. + */ + +extern void _TIE_xt_interrupt_WAITI(immediate s); +extern unsigned _TIE_xt_interrupt_RSR_INTERRUPT(void); +extern void _TIE_xt_interrupt_WSR_INTSET(unsigned art); +extern void _TIE_xt_interrupt_WSR_INTCLEAR(unsigned art); +extern unsigned _TIE_xt_interrupt_RSR_INTENABLE(void); +extern void _TIE_xt_interrupt_WSR_INTENABLE(unsigned art); +extern void _TIE_xt_interrupt_XSR_INTENABLE(unsigned art /*inout*/); +#define XT_WAITI _TIE_xt_interrupt_WAITI +#define XT_RSR_INTERRUPT _TIE_xt_interrupt_RSR_INTERRUPT +#define XT_WSR_INTSET _TIE_xt_interrupt_WSR_INTSET +#define XT_WSR_INTCLEAR _TIE_xt_interrupt_WSR_INTCLEAR +#define XT_RSR_INTENABLE _TIE_xt_interrupt_RSR_INTENABLE +#define XT_WSR_INTENABLE _TIE_xt_interrupt_WSR_INTENABLE +#define XT_XSR_INTENABLE _TIE_xt_interrupt_XSR_INTENABLE + +#endif /* __XCC__ */ + +#endif /* __XTENSA__ */ + +#endif /* !_XTENSA_xt_interrupt_HEADER */ diff --git a/tools/sdk/include/esp32/xtensa/tie/xt_ioports.h b/tools/sdk/include/esp32/xtensa/tie/xt_ioports.h new file mode 100644 index 00000000..0253bea4 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/tie/xt_ioports.h @@ -0,0 +1,66 @@ +/* Definitions for the xt_ioports TIE package */ + +/* + * Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of Tensilica Inc. + * They may not be modified, copied, reproduced, distributed, or disclosed to + * third parties in any manner, medium, or form, in whole or in part, without + * the prior written consent of Tensilica Inc. + */ + +/* Do not modify. This is automatically generated.*/ + +#ifndef _XTENSA_xt_ioports_HEADER +#define _XTENSA_xt_ioports_HEADER + +#ifdef __XTENSA__ +#ifdef __XCC__ + +#include + +/* + * The following prototypes describe intrinsic functions + * corresponding to TIE instructions. Some TIE instructions + * may produce multiple results (designated as "out" operands + * in the iclass section) or may have operands used as both + * inputs and outputs (designated as "inout"). However, the C + * and C++ languages do not provide syntax that can express + * the in/out/inout constraints of TIE intrinsics. + * Nevertheless, the compiler understands these constraints + * and will check that the intrinsic functions are used + * correctly. To improve the readability of these prototypes, + * the "out" and "inout" parameters are marked accordingly + * with comments. + */ + +extern unsigned _TIE_xt_ioports_READ_IMPWIRE(void); +extern void _TIE_xt_ioports_SETB_EXPSTATE(immediate bitindex); +extern void _TIE_xt_ioports_CLRB_EXPSTATE(immediate bitindex); +extern void _TIE_xt_ioports_WRMSK_EXPSTATE(unsigned art, unsigned ars); +extern unsigned _TIE_xt_ioports_RUR_EXPSTATE(void); +extern void _TIE_xt_ioports_WUR_EXPSTATE(unsigned v); +#define READ_IMPWIRE _TIE_xt_ioports_READ_IMPWIRE +#define SETB_EXPSTATE _TIE_xt_ioports_SETB_EXPSTATE +#define CLRB_EXPSTATE _TIE_xt_ioports_CLRB_EXPSTATE +#define WRMSK_EXPSTATE _TIE_xt_ioports_WRMSK_EXPSTATE +#define RUR_EXPSTATE _TIE_xt_ioports_RUR_EXPSTATE +#define REXPSTATE _TIE_xt_ioports_RUR_EXPSTATE +#define RUR230 _TIE_xt_ioports_RUR_EXPSTATE +#define WUR_EXPSTATE _TIE_xt_ioports_WUR_EXPSTATE +#define WEXPSTATE _TIE_xt_ioports_WUR_EXPSTATE +#define WUR230 _TIE_xt_ioports_WUR_EXPSTATE + +#ifndef RUR +#define RUR(NUM) RUR##NUM() +#endif + +#ifndef WUR +#define WUR(VAL, NUM) WUR##NUM(VAL) +#endif + +#endif /* __XCC__ */ + +#endif /* __XTENSA__ */ + +#endif /* !_XTENSA_xt_ioports_HEADER */ diff --git a/tools/sdk/include/esp32/xtensa/tie/xt_misc.h b/tools/sdk/include/esp32/xtensa/tie/xt_misc.h new file mode 100644 index 00000000..a0b36f4e --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/tie/xt_misc.h @@ -0,0 +1,58 @@ +/* Definitions for the xt_misc TIE package */ + +/* + * Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of Tensilica Inc. + * They may not be modified, copied, reproduced, distributed, or disclosed to + * third parties in any manner, medium, or form, in whole or in part, without + * the prior written consent of Tensilica Inc. + */ + +/* Do not modify. This is automatically generated.*/ + +#ifndef _XTENSA_xt_misc_HEADER +#define _XTENSA_xt_misc_HEADER + +#ifdef __XTENSA__ +#ifdef __XCC__ + +#include + +/* + * The following prototypes describe intrinsic functions + * corresponding to TIE instructions. Some TIE instructions + * may produce multiple results (designated as "out" operands + * in the iclass section) or may have operands used as both + * inputs and outputs (designated as "inout"). However, the C + * and C++ languages do not provide syntax that can express + * the in/out/inout constraints of TIE intrinsics. + * Nevertheless, the compiler understands these constraints + * and will check that the intrinsic functions are used + * correctly. To improve the readability of these prototypes, + * the "out" and "inout" parameters are marked accordingly + * with comments. + */ + +extern int _TIE_xt_misc_CLAMPS(int s, immediate i); +extern int _TIE_xt_misc_MIN(int s, int t); +extern int _TIE_xt_misc_MAX(int s, int t); +extern unsigned _TIE_xt_misc_MINU(unsigned s, unsigned t); +extern unsigned _TIE_xt_misc_MAXU(unsigned s, unsigned t); +extern int _TIE_xt_misc_NSA(int s); +extern unsigned _TIE_xt_misc_NSAU(unsigned s); +extern int _TIE_xt_misc_SEXT(int s, immediate i); +#define XT_CLAMPS _TIE_xt_misc_CLAMPS +#define XT_MIN _TIE_xt_misc_MIN +#define XT_MAX _TIE_xt_misc_MAX +#define XT_MINU _TIE_xt_misc_MINU +#define XT_MAXU _TIE_xt_misc_MAXU +#define XT_NSA _TIE_xt_misc_NSA +#define XT_NSAU _TIE_xt_misc_NSAU +#define XT_SEXT _TIE_xt_misc_SEXT + +#endif /* __XCC__ */ + +#endif /* __XTENSA__ */ + +#endif /* !_XTENSA_xt_misc_HEADER */ diff --git a/tools/sdk/include/esp32/xtensa/tie/xt_mmu.h b/tools/sdk/include/esp32/xtensa/tie/xt_mmu.h new file mode 100644 index 00000000..ce786c0f --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/tie/xt_mmu.h @@ -0,0 +1,62 @@ +/* Definitions for the xt_mmu TIE package */ + +/* + * Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of Tensilica Inc. + * They may not be modified, copied, reproduced, distributed, or disclosed to + * third parties in any manner, medium, or form, in whole or in part, without + * the prior written consent of Tensilica Inc. + */ + +/* Do not modify. This is automatically generated.*/ + +#ifndef _XTENSA_xt_mmu_HEADER +#define _XTENSA_xt_mmu_HEADER + +#ifdef __XTENSA__ +#ifdef __XCC__ + +#include + +/* + * The following prototypes describe intrinsic functions + * corresponding to TIE instructions. Some TIE instructions + * may produce multiple results (designated as "out" operands + * in the iclass section) or may have operands used as both + * inputs and outputs (designated as "inout"). However, the C + * and C++ languages do not provide syntax that can express + * the in/out/inout constraints of TIE intrinsics. + * Nevertheless, the compiler understands these constraints + * and will check that the intrinsic functions are used + * correctly. To improve the readability of these prototypes, + * the "out" and "inout" parameters are marked accordingly + * with comments. + */ + +extern void _TIE_xt_mmu_IDTLB(unsigned ars); +extern unsigned _TIE_xt_mmu_RDTLB1(unsigned ars); +extern unsigned _TIE_xt_mmu_RDTLB0(unsigned ars); +extern unsigned _TIE_xt_mmu_PDTLB(unsigned ars); +extern void _TIE_xt_mmu_WDTLB(unsigned art, unsigned ars); +extern void _TIE_xt_mmu_IITLB(unsigned ars); +extern unsigned _TIE_xt_mmu_RITLB1(unsigned ars); +extern unsigned _TIE_xt_mmu_RITLB0(unsigned ars); +extern unsigned _TIE_xt_mmu_PITLB(unsigned ars); +extern void _TIE_xt_mmu_WITLB(unsigned art, unsigned ars); +#define XT_IDTLB _TIE_xt_mmu_IDTLB +#define XT_RDTLB1 _TIE_xt_mmu_RDTLB1 +#define XT_RDTLB0 _TIE_xt_mmu_RDTLB0 +#define XT_PDTLB _TIE_xt_mmu_PDTLB +#define XT_WDTLB _TIE_xt_mmu_WDTLB +#define XT_IITLB _TIE_xt_mmu_IITLB +#define XT_RITLB1 _TIE_xt_mmu_RITLB1 +#define XT_RITLB0 _TIE_xt_mmu_RITLB0 +#define XT_PITLB _TIE_xt_mmu_PITLB +#define XT_WITLB _TIE_xt_mmu_WITLB + +#endif /* __XCC__ */ + +#endif /* __XTENSA__ */ + +#endif /* !_XTENSA_xt_mmu_HEADER */ diff --git a/tools/sdk/include/esp32/xtensa/tie/xt_mul.h b/tools/sdk/include/esp32/xtensa/tie/xt_mul.h new file mode 100644 index 00000000..e2086206 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/tie/xt_mul.h @@ -0,0 +1,52 @@ +/* Definitions for the xt_mul TIE package */ + +/* + * Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of Tensilica Inc. + * They may not be modified, copied, reproduced, distributed, or disclosed to + * third parties in any manner, medium, or form, in whole or in part, without + * the prior written consent of Tensilica Inc. + */ + +/* Do not modify. This is automatically generated.*/ + +#ifndef _XTENSA_xt_mul_HEADER +#define _XTENSA_xt_mul_HEADER + +#ifdef __XTENSA__ +#ifdef __XCC__ + +#include + +/* + * The following prototypes describe intrinsic functions + * corresponding to TIE instructions. Some TIE instructions + * may produce multiple results (designated as "out" operands + * in the iclass section) or may have operands used as both + * inputs and outputs (designated as "inout"). However, the C + * and C++ languages do not provide syntax that can express + * the in/out/inout constraints of TIE intrinsics. + * Nevertheless, the compiler understands these constraints + * and will check that the intrinsic functions are used + * correctly. To improve the readability of these prototypes, + * the "out" and "inout" parameters are marked accordingly + * with comments. + */ + +extern int _TIE_xt_mul_MUL16S(short s, short t); +extern unsigned _TIE_xt_mul_MUL16U(unsigned short s, unsigned short t); +extern int _TIE_xt_mul_MULL(int s, int t); +extern unsigned _TIE_xt_mul_MULUH(unsigned s, unsigned t); +extern int _TIE_xt_mul_MULSH(int s, int t); +#define XT_MUL16S _TIE_xt_mul_MUL16S +#define XT_MUL16U _TIE_xt_mul_MUL16U +#define XT_MULL _TIE_xt_mul_MULL +#define XT_MULUH _TIE_xt_mul_MULUH +#define XT_MULSH _TIE_xt_mul_MULSH + +#endif /* __XCC__ */ + +#endif /* __XTENSA__ */ + +#endif /* !_XTENSA_xt_mul_HEADER */ diff --git a/tools/sdk/include/esp32/xtensa/tie/xt_regwin.h b/tools/sdk/include/esp32/xtensa/tie/xt_regwin.h new file mode 100644 index 00000000..7bce471a --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/tie/xt_regwin.h @@ -0,0 +1,64 @@ +/* Definitions for the xt_regwin TIE package */ + +/* + * Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of Tensilica Inc. + * They may not be modified, copied, reproduced, distributed, or disclosed to + * third parties in any manner, medium, or form, in whole or in part, without + * the prior written consent of Tensilica Inc. + */ + +/* Do not modify. This is automatically generated.*/ + +#ifndef _XTENSA_xt_regwin_HEADER +#define _XTENSA_xt_regwin_HEADER + +#ifdef __XTENSA__ +#ifdef __XCC__ + +#include + +/* + * The following prototypes describe intrinsic functions + * corresponding to TIE instructions. Some TIE instructions + * may produce multiple results (designated as "out" operands + * in the iclass section) or may have operands used as both + * inputs and outputs (designated as "inout"). However, the C + * and C++ languages do not provide syntax that can express + * the in/out/inout constraints of TIE intrinsics. + * Nevertheless, the compiler understands these constraints + * and will check that the intrinsic functions are used + * correctly. To improve the readability of these prototypes, + * the "out" and "inout" parameters are marked accordingly + * with comments. + */ + +extern void _TIE_xt_regwin_ENTRY(unsigned ars /*inout*/, immediate uimm12x8); +extern void _TIE_xt_regwin_ROTW(immediate simm4); +extern int _TIE_xt_regwin_MOVSP(int s); +extern int _TIE_xt_regwin_L32E(const int * s, immediate o); +extern void _TIE_xt_regwin_S32E(int t, int * s, immediate o); +extern unsigned _TIE_xt_regwin_RSR_WINDOWBASE(void); +extern void _TIE_xt_regwin_WSR_WINDOWBASE(unsigned t); +extern void _TIE_xt_regwin_XSR_WINDOWBASE(unsigned t /*inout*/); +extern unsigned _TIE_xt_regwin_RSR_WINDOWSTART(void); +extern void _TIE_xt_regwin_WSR_WINDOWSTART(unsigned t); +extern void _TIE_xt_regwin_XSR_WINDOWSTART(unsigned t /*inout*/); +#define XT_ENTRY _TIE_xt_regwin_ENTRY +#define XT_ROTW _TIE_xt_regwin_ROTW +#define XT_MOVSP _TIE_xt_regwin_MOVSP +#define XT_L32E _TIE_xt_regwin_L32E +#define XT_S32E _TIE_xt_regwin_S32E +#define XT_RSR_WINDOWBASE _TIE_xt_regwin_RSR_WINDOWBASE +#define XT_WSR_WINDOWBASE _TIE_xt_regwin_WSR_WINDOWBASE +#define XT_XSR_WINDOWBASE _TIE_xt_regwin_XSR_WINDOWBASE +#define XT_RSR_WINDOWSTART _TIE_xt_regwin_RSR_WINDOWSTART +#define XT_WSR_WINDOWSTART _TIE_xt_regwin_WSR_WINDOWSTART +#define XT_XSR_WINDOWSTART _TIE_xt_regwin_XSR_WINDOWSTART + +#endif /* __XCC__ */ + +#endif /* __XTENSA__ */ + +#endif /* !_XTENSA_xt_regwin_HEADER */ diff --git a/tools/sdk/include/esp32/xtensa/tie/xt_scmpr.h b/tools/sdk/include/esp32/xtensa/tie/xt_scmpr.h new file mode 100644 index 00000000..337c7762 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/tie/xt_scmpr.h @@ -0,0 +1,22 @@ + +/* + * Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of Tensilica Inc. + * They may not be modified, copied, reproduced, distributed, or disclosed to + * third parties in any manner, medium, or form, in whole or in part, without + * the prior written consent of Tensilica Inc. + */ + +/* Do not modify. This is automatically generated.*/ + +#ifndef _XTENSA_xt_scmpr_h_HEADER +#define _XTENSA_xt_scmpr_h_HEADER + + +/* Header includes start */ + + +/* Header includes end */ + +#endif /* !_XTENSA_xt_scmpr_h_HEADER */ diff --git a/tools/sdk/include/esp32/xtensa/tie/xt_sync.h b/tools/sdk/include/esp32/xtensa/tie/xt_sync.h new file mode 100644 index 00000000..9323dfe4 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/tie/xt_sync.h @@ -0,0 +1,60 @@ +/* Definitions for the xt_sync TIE package */ + +/* + * Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of Tensilica Inc. + * They may not be modified, copied, reproduced, distributed, or disclosed to + * third parties in any manner, medium, or form, in whole or in part, without + * the prior written consent of Tensilica Inc. + */ + +/* Do not modify. This is automatically generated.*/ + +#ifndef _XTENSA_xt_sync_HEADER +#define _XTENSA_xt_sync_HEADER + +#ifdef __XTENSA__ +#ifdef __XCC__ + +#include + +/* + * The following prototypes describe intrinsic functions + * corresponding to TIE instructions. Some TIE instructions + * may produce multiple results (designated as "out" operands + * in the iclass section) or may have operands used as both + * inputs and outputs (designated as "inout"). However, the C + * and C++ languages do not provide syntax that can express + * the in/out/inout constraints of TIE intrinsics. + * Nevertheless, the compiler understands these constraints + * and will check that the intrinsic functions are used + * correctly. To improve the readability of these prototypes, + * the "out" and "inout" parameters are marked accordingly + * with comments. + */ + +extern unsigned _TIE_xt_sync_RSR_SCOMPARE1(void); +extern void _TIE_xt_sync_WSR_SCOMPARE1(unsigned art); +extern void _TIE_xt_sync_XSR_SCOMPARE1(unsigned art /*inout*/); +extern unsigned _TIE_xt_sync_RSR_ATOMCTL(void); +extern void _TIE_xt_sync_WSR_ATOMCTL(unsigned art); +extern void _TIE_xt_sync_XSR_ATOMCTL(unsigned art /*inout*/); +extern unsigned _TIE_xt_sync_L32AI(const unsigned * p, immediate o); +extern void _TIE_xt_sync_S32RI(unsigned c, unsigned * p, immediate o); +extern void _TIE_xt_sync_S32C1I(unsigned c /*inout*/, const unsigned * p, immediate o); +#define XT_RSR_SCOMPARE1 _TIE_xt_sync_RSR_SCOMPARE1 +#define XT_WSR_SCOMPARE1 _TIE_xt_sync_WSR_SCOMPARE1 +#define XT_XSR_SCOMPARE1 _TIE_xt_sync_XSR_SCOMPARE1 +#define XT_RSR_ATOMCTL _TIE_xt_sync_RSR_ATOMCTL +#define XT_WSR_ATOMCTL _TIE_xt_sync_WSR_ATOMCTL +#define XT_XSR_ATOMCTL _TIE_xt_sync_XSR_ATOMCTL +#define XT_L32AI _TIE_xt_sync_L32AI +#define XT_S32RI _TIE_xt_sync_S32RI +#define XT_S32C1I _TIE_xt_sync_S32C1I + +#endif /* __XCC__ */ + +#endif /* __XTENSA__ */ + +#endif /* !_XTENSA_xt_sync_HEADER */ diff --git a/tools/sdk/include/esp32/xtensa/tie/xt_timer.h b/tools/sdk/include/esp32/xtensa/tie/xt_timer.h new file mode 100644 index 00000000..64db45c1 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/tie/xt_timer.h @@ -0,0 +1,66 @@ +/* Definitions for the xt_timer TIE package */ + +/* + * Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of Tensilica Inc. + * They may not be modified, copied, reproduced, distributed, or disclosed to + * third parties in any manner, medium, or form, in whole or in part, without + * the prior written consent of Tensilica Inc. + */ + +/* Do not modify. This is automatically generated.*/ + +#ifndef _XTENSA_xt_timer_HEADER +#define _XTENSA_xt_timer_HEADER + +#ifdef __XTENSA__ +#ifdef __XCC__ + +#include + +/* + * The following prototypes describe intrinsic functions + * corresponding to TIE instructions. Some TIE instructions + * may produce multiple results (designated as "out" operands + * in the iclass section) or may have operands used as both + * inputs and outputs (designated as "inout"). However, the C + * and C++ languages do not provide syntax that can express + * the in/out/inout constraints of TIE intrinsics. + * Nevertheless, the compiler understands these constraints + * and will check that the intrinsic functions are used + * correctly. To improve the readability of these prototypes, + * the "out" and "inout" parameters are marked accordingly + * with comments. + */ + +extern unsigned _TIE_xt_timer_RSR_CCOUNT(void); +extern void _TIE_xt_timer_WSR_CCOUNT(unsigned art); +extern void _TIE_xt_timer_XSR_CCOUNT(unsigned art /*inout*/); +extern unsigned _TIE_xt_timer_RSR_CCOMPARE0(void); +extern void _TIE_xt_timer_WSR_CCOMPARE0(unsigned art); +extern void _TIE_xt_timer_XSR_CCOMPARE0(unsigned art /*inout*/); +extern unsigned _TIE_xt_timer_RSR_CCOMPARE1(void); +extern void _TIE_xt_timer_WSR_CCOMPARE1(unsigned art); +extern void _TIE_xt_timer_XSR_CCOMPARE1(unsigned art /*inout*/); +extern unsigned _TIE_xt_timer_RSR_CCOMPARE2(void); +extern void _TIE_xt_timer_WSR_CCOMPARE2(unsigned art); +extern void _TIE_xt_timer_XSR_CCOMPARE2(unsigned art /*inout*/); +#define XT_RSR_CCOUNT _TIE_xt_timer_RSR_CCOUNT +#define XT_WSR_CCOUNT _TIE_xt_timer_WSR_CCOUNT +#define XT_XSR_CCOUNT _TIE_xt_timer_XSR_CCOUNT +#define XT_RSR_CCOMPARE0 _TIE_xt_timer_RSR_CCOMPARE0 +#define XT_WSR_CCOMPARE0 _TIE_xt_timer_WSR_CCOMPARE0 +#define XT_XSR_CCOMPARE0 _TIE_xt_timer_XSR_CCOMPARE0 +#define XT_RSR_CCOMPARE1 _TIE_xt_timer_RSR_CCOMPARE1 +#define XT_WSR_CCOMPARE1 _TIE_xt_timer_WSR_CCOMPARE1 +#define XT_XSR_CCOMPARE1 _TIE_xt_timer_XSR_CCOMPARE1 +#define XT_RSR_CCOMPARE2 _TIE_xt_timer_RSR_CCOMPARE2 +#define XT_WSR_CCOMPARE2 _TIE_xt_timer_WSR_CCOMPARE2 +#define XT_XSR_CCOMPARE2 _TIE_xt_timer_XSR_CCOMPARE2 + +#endif /* __XCC__ */ + +#endif /* __XTENSA__ */ + +#endif /* !_XTENSA_xt_timer_HEADER */ diff --git a/tools/sdk/include/esp32/xtensa/tie/xt_trace.h b/tools/sdk/include/esp32/xtensa/tie/xt_trace.h new file mode 100644 index 00000000..8d8d07fa --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/tie/xt_trace.h @@ -0,0 +1,44 @@ +/* Definitions for the xt_trace TIE package */ + +/* + * Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of Tensilica Inc. + * They may not be modified, copied, reproduced, distributed, or disclosed to + * third parties in any manner, medium, or form, in whole or in part, without + * the prior written consent of Tensilica Inc. + */ + +/* Do not modify. This is automatically generated.*/ + +#ifndef _XTENSA_xt_trace_HEADER +#define _XTENSA_xt_trace_HEADER + +#ifdef __XTENSA__ +#ifdef __XCC__ + +#include + +/* + * The following prototypes describe intrinsic functions + * corresponding to TIE instructions. Some TIE instructions + * may produce multiple results (designated as "out" operands + * in the iclass section) or may have operands used as both + * inputs and outputs (designated as "inout"). However, the C + * and C++ languages do not provide syntax that can express + * the in/out/inout constraints of TIE intrinsics. + * Nevertheless, the compiler understands these constraints + * and will check that the intrinsic functions are used + * correctly. To improve the readability of these prototypes, + * the "out" and "inout" parameters are marked accordingly + * with comments. + */ + +extern void _TIE_xt_trace_WSR_MMID(unsigned art); +#define XT_WSR_MMID _TIE_xt_trace_WSR_MMID + +#endif /* __XCC__ */ + +#endif /* __XTENSA__ */ + +#endif /* !_XTENSA_xt_trace_HEADER */ diff --git a/tools/sdk/include/esp32/xtensa/trax-api.h b/tools/sdk/include/esp32/xtensa/trax-api.h new file mode 100755 index 00000000..aa158435 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/trax-api.h @@ -0,0 +1,93 @@ +/* Misc TRAX API function definitions. + + Copyright (c) 2007-2012 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef _TRAX_API_H_ +#define _TRAX_API_H_ + +#include +#include +#include "tpack.h" +#include "traxreg.h" + +#include "xdm-regs.h" + +/* Flags for trax_stop(): */ +#define TRAX_STOP_HALT 0x0001 /* halt immediately, don't wait for post-stop-trigger capture */ +#define TRAX_STOP_QUIET 0x0002 /* don't display informative messages */ + + +/* + * Describes a TRAX channel (based on tpack). + */ +typedef struct { + tpack_channel chan; /* channel structure header */ + /* Per TRAX unit information: */ + int trax_version; /* TRAX_ID_VER(id), one of TRAX_VER_xxx macros */ + unsigned long trax_tram_size; /* size of trace RAM in bytes */ + int trax_erratum10; /* set if TRAX 1.0 erratum workarounds needed */ + int trax_erratum20; /* set if TRAX 2.0 erratum workaround needed (PR 22161)*/ + int trax_erratum20_size; + int trax_has_busy; /* has trace-busy feature */ + int trax_has_atb; /* has ATB feature */ + /*FIXME: add various features: coresight regs (don't call it that), APB, ATB, TRAM, ... */ +} trax_channel; + + +/* Prototypes: */ + +/* TRAX Protocol API: */ +extern int trax_read_register(tpack_channel *tchan, int regno, unsigned *value); +extern int trax_write_register(tpack_channel *tchan, int regno, unsigned value); +extern int trax_read_memory(tpack_channel *tchan, int address, int size, unsigned char *pdata); +extern int trax_fill_memory(tpack_channel *tchan, int address, int size, tpack_u32 pattern); +extern int trax_enumerate_devices(tpack_channel *tchan, int * buf, int * size); + +/* TRAX Network API: */ +extern unsigned long trax_ram_size(tpack_channel *traxchan); +extern unsigned long trax_ram_size_addr(tpack_channel *traxchan); +extern int trax_create_tracefile(tpack_channel *traxchan, int size, unsigned char * data, + char *filename, int hflags, const char *toolver); +extern int trax_memaccess_safe(tpack_channel *traxchan, const char *what); +extern int trax_start(tpack_channel *traxchan, int flags); +extern int trax_stop(tpack_channel *traxchan, int flags); +extern int trax_halt(tpack_channel *traxchan, int flags); +extern int trax_save(tpack_channel *traxchan, char *filename, int flags, const char *toolver, int erratum); + +/* TRAX Misc API (no network dependencies): */ +int trax_fixed_hw(unsigned * regs); +extern int trax_display_id(unsigned id, const char *prefix); +extern int trax_display_summary(unsigned id, + unsigned status, + unsigned control, + unsigned address, + unsigned delay, + unsigned trigger, + unsigned match, + unsigned startaddr, + unsigned endaddr, + const char *prefix); + +/* Other: */ + +#endif /* _TRAX_API_H_ */ + diff --git a/tools/sdk/include/esp32/xtensa/trax-core-config.h b/tools/sdk/include/esp32/xtensa/trax-core-config.h new file mode 100755 index 00000000..42a03334 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/trax-core-config.h @@ -0,0 +1,144 @@ +/* Definitions for Xtensa processor config info needed for TRAX. + + Copyright (c) 2005-2011 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef TRAX_CORE_CONFIG_H +#define TRAX_CORE_CONFIG_H + +#include "xtensa-params.h" + +/* + * Vector Enumerations. + */ + +/* These must match the LX2.0 and later traceport spec: */ +#define VEC_NO_VECTOR 0 +#define VEC_FIRST VEC_RESET /* first valid vector */ +#define VEC_RESET 1 +#define VEC_DEBUG 2 +#define VEC_NMI 3 +#define VEC_USER 4 +#define VEC_KERNEL 5 +#define VEC_DOUBLE 6 +#define VEC_MEMERR 7 +#define VEC_RESERVED8 8 +#define VEC_RESERVED9 9 +#define VEC_WINO4 10 +#define VEC_WINU4 11 +#define VEC_WINO8 12 +#define VEC_WINU8 13 +#define VEC_WINO12 14 +#define VEC_WINU12 15 +#define VEC_INTLEVEL2 16 +#define VEC_INTLEVEL3 17 +#define VEC_INTLEVEL4 18 +#define VEC_INTLEVEL5 19 +#define VEC_INTLEVEL6 20 +/* These are internal, i.e. don't appear like this on traceport: */ +#define VEC_DEBUG_OCD 21 +#define VEC_UNKNOWN 22 +/* Enumerations 23 through 31 are also reserved, but putting */ +/* placeholders here seems wasteful and unnecessary. */ +#define VEC_COUNT 23 + +/* Other branch (change-of-PC-flow) type encodings; + * if PC changes due to an exception or interrupt vector, + * one of the VEC_* values above is used, otherwise + * (or if it's unknown whether it's due to an exception/interrupt) + * one of the following is used: */ + +#define BRANCH_IS_VEC(n) ((n) < VEC_COUNT) /* is known to be except/interrupt? */ +#define BRANCH_OR_VEC 24 /* unknown type of branch (branch/exception/interrupt/etc) */ +#define BRANCH_UNKNOWN 25 /* unknown type of branch (anything but except/interrupt) */ +#define BRANCH_UNKNOWN_ERR 26 /* like BRANCH_UNKNOWN with known error (non-branch instr) */ +#define BRANCH_LOOPBACK 28 /* zero-overhead loopback (from LEND to LBEG) */ +#define BRANCH_CONDTAKEN 29 /* conditional branch taken (or LOOP{NEZ,GTZ} loop skip) */ +#define BRANCH_JUMP 30 /* jump (unconditional branch, i.e. J or JX) */ +#define BRANCH_IS_CALL(n) (((n) & ~3) == 32) /* is a function call? */ +#define BRANCH_CALL0 32 /* non-windowed function call (CALL0, CALLX0) */ +#define BRANCH_CALL4 33 /* windowed function call (CALL4, CALLX4) */ +#define BRANCH_CALL8 34 /* windowed function call (CALL8, CALLX8) */ +#define BRANCH_CALL12 35 /* windowed function call (CALL12, CALLX12) */ +#define BRANCH_IS_RETURN(n) ((n) >= 36) /* is any kind of return? */ +#define BRANCH_IS_CALLRETURN(n) (((n) & ~1) == 36) /* is a function return? */ +#define BRANCH_RET 36 /* non-windowed function return (RET or RET.N) */ +#define BRANCH_RETW 37 /* windowed function return (RETW or RETW.N) */ +#define BRANCH_IS_EIRETURN(n) ((n) >= 38) /* is an except/inter. return? */ +#define BRANCH_RFE 38 /* RFE or RFUE */ +#define BRANCH_RFDE 39 /* RFDE */ +#define BRANCH_RFWO 40 /* RFWO */ +#define BRANCH_RFWU 41 /* RFWU */ +#define BRANCH_RFI_2 42 /* RFI 2 */ +#define BRANCH_RFI_3 43 /* RFI 3 */ +#define BRANCH_RFI_4 44 /* RFI 4 */ +#define BRANCH_RFI_5 45 /* RFI 5 */ +#define BRANCH_RFI_6 46 /* RFI 6 */ +#define BRANCH_RFI_NMI 47 /* RFI NMILEVEL */ +#define BRANCH_RFI_DEBUG 48 /* RFI DEBUGLEVEL */ +#define BRANCH_RFME 49 /* RFME */ +#define BRANCH_COUNT 50 /* (number of defined BRANCH_xxx values) */ + + + +typedef struct { + unsigned vaddr; + unsigned vaddr2; /* for static vectors only (reloc vectors option) */ + int is_configured; +} trax_vector_t; + + +/* + * This structure describes those portion of a Tensilica processor's + * configuration that are useful for trace. + */ +typedef struct { + char ** isa_dlls; + char * core_name; /* (XPG core name, not necessarily same as XTENSA_CORE) */ + int big_endian; /* 0 = little-endian, 1 = big-endian */ + int has_loops; /* 1 = zero overhead loops configured */ + int has_autorefill; /* 1 = TLB autorefill (MMU) configured */ + unsigned max_instr_size; /* in bytes (eg. 3, 4, 8, ...) */ + unsigned int_level_max; /* number of interrupt levels configured (without NMI) */ + int debug_level; /* debug intlevel, 0 if debug not configured */ + int nmi_level; /* NMI intlevel, 0 if NMI not configured */ + unsigned targethw_min; /* min. targeted hardware version (XTENSA_HWVERSION_) */ + unsigned targethw_max; /* max. targeted hardware version (XTENSA_HWVERSION_) */ + int reloc_vectors; /* 0 = fixed vectors, 1 = relocatable vectors */ + int statvec_select; /* 0 = stat vec base 0, 1 = stat vec base 1 (SW default) */ + int vecbase_align; /* number of bits to align VECBASE (32 - bits in VECBASE) */ + unsigned statvec_base0; /* static vector base 0 */ + unsigned statvec_base1; /* static vector base 1 */ + unsigned vecbase_reset; /* reset value of VECBASE */ + trax_vector_t vectors[VEC_COUNT]; /* all vectors... */ +} trax_core_config_t; + + +/* Globals: */ +//extern const char * const trax_vector_short_names[/*VEC_COUNT*/]; // nobody uses this one +extern const char * const trax_vector_names[/*VEC_COUNT*/]; + +/* Prototypes: */ +extern int trax_read_params (trax_core_config_t *c, xtensa_params p); +extern int trax_vector_from_address(trax_core_config_t *config, unsigned long vaddr, unsigned long *vecbases); + +#endif /* TRAX_CORE_CONFIG_H */ + diff --git a/tools/sdk/include/esp32/xtensa/trax-proto.h b/tools/sdk/include/esp32/xtensa/trax-proto.h new file mode 100755 index 00000000..41d5c9fd --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/trax-proto.h @@ -0,0 +1,91 @@ +/* This file contains functions that are hidden from the user. These are + * protocol specific functions used to read and write TRAX registers + * and the trace memory + */ + +/* + * Copyright (c) 2012-2013 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _TRAX_PROTO_H +#define _TRAX_PROTO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Function to read register + * + * regno : The register number to be read (not ERI addressed) + * data : Location where the read value is kept + * + * returns : 0 if successful, -1 if unsuccessful + */ +int trax_read_register_eri (int regno, unsigned *data); + +/* Function to write a value into a register + * + * regno : The register number to be written (not ERI addressed) + * value : The value to be written at that register location + * + * returns : 0 if successful, -1 if unsuccessful + */ +int trax_write_register_eri (int regno, unsigned value); + +/* Function to read memory + * + * address : Address of the TraceRAM memory, each location has a word + * len : Amount of memory in bytes, to be read + * data : buffer in which the read memory is stored + * final_address: Next address to be read in the following call to this + * function (trace save mechanism) + * + * returns : 0 if successful, -1 if unsuccessful + */ +int trax_read_memory_eri (unsigned address, int len, int *data, + unsigned *final_address); + +/* Function to write a value to the memory address + * + * address : Address of the TraceRAM memory + * value : The value to be written inside that location + * + * returns : 0 if successful, -1 if unsuccessful + */ +int trax_write_memory_eri (int address, unsigned value); + +/* Function to write to a subfield of the register. + * Called by set and show parameter functions. + * + * regno : Register number + * regmask : Mask in order to toggle appropriate bits + * value : Value to be written in the masked location + * + * returns : 0 if successful, -1 if unsuccessful + */ +int trax_write_register_field_eri (int regno, unsigned regmask, + unsigned value); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/tools/sdk/include/esp32/xtensa/trax-util.h b/tools/sdk/include/esp32/xtensa/trax-util.h new file mode 100755 index 00000000..123ac366 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/trax-util.h @@ -0,0 +1,63 @@ +/* This file contains utility functions that can be used for polling TRAX + * or executing higher level save functionality + * It assumes that print subroutines and file I/O routines are available + * on the system + */ + +/* + * Copyright (c) 2012-2013 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _TRAX_UTIL_H +#define _TRAX_UTIL_H + + +#ifdef __cplusplus +extern "C" { +#endif + +/* User can use this function if he wants to generate a tracefile output. + * Internally it calls trax_get_trace in a loop until it realizes that + * the entire trace has been read. + * + * context : pointer to structure which contains information about the + * current TRAX session + * filename : user specified output trace file name. If the file does not + * exist, it would create the new file, else would append to it + * + * returns : 0 if successful, -1 if unsuccessful + */ +int trax_save (trax_context *context, char *filename); + +/* Displays a brief machine readable status. + * + * context : pointer to structure which contains information about the + * current TRAX session + * returns : 0 if successful, -1 if unsuccessful + */ +int trax_poll (trax_context *context); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/tools/sdk/include/esp32/xtensa/trax.h b/tools/sdk/include/esp32/xtensa/trax.h new file mode 100755 index 00000000..47049c51 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/trax.h @@ -0,0 +1,409 @@ +/* Header file for TRAX control Library */ + +/* + * Copyright (c) 2012-2013 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _TRAX_H +#define _TRAX_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define TRAX_STOP_HALT 0x0001 +#define TRAX_STOP_QUIET 0x0002 + +/* Flag values to indicate if the user wanted to reverse the pcstop + * parameters */ +#define TRAX_PCSTOP_REVERSE 0x0001 +#define TRAX_PCSTOP_NO_REVERSE 0x0000 + +/* Indicating whether postsize should be in terms of bytes, instructions + * or percentage of trace size captured */ +#define TRAX_POSTSIZE_BYTES 0x0000 +#define TRAX_POSTSIZE_INSTR 0x0001 +#define TRAX_POSTSIZE_PERCENT 0x0002 + +/* Size of the header inside the trace file */ +#define TRAX_HEADER_SIZE 256 + +/* Minimum size between start and end addresses */ +#define TRAX_MIN_TRACEMEM 64 + +/* For basic debugging */ +#define DEBUG 0 + +#include + +#define ffs(i) __builtin_ffs(i) + +/* Data structures */ + +/* Represents the context of the TRAX unit and the current TRAX session. + * To be used by set and show function calls to set and show appropriate + * parameters of appropriate TRAX unit. + */ + +typedef struct { + int trax_version; /* TRAX PC version information */ + unsigned long trax_tram_size; /* If trace RAM is present,size of it */ + int hflags; /* Flags that can be used to debug, + print info, etc. */ + int address_read_last; /* During saving of the trace, this + indicates the address from which + the current trace reading must + resume */ + unsigned long bytes_read; /* bytes read uptil now */ + unsigned long total_memlen; /* Total bytes to be read based on the + trace collected in the trace RAM */ + bool get_trace_started; /* indicates that the first chunk of + bytes (which include the header) has + been read */ +} trax_context; + + +/* -----------------------TRAX Initialization ------------------------------*/ + +/* Initializing the trax context. Reads registers and sets values for version, + * trace RAM size, total memory length, etc. Most of the other values are + * initialized to their default case. + * + * context : pointer to structure which contains information about the + * current TRAX session + * + * returns : 0 if successful, -1 if unsuccessful, -2 if ram_size if + * incorrect + */ +int trax_context_init_eri (trax_context *context); + +/* -----------------Starting/Stopping TRAX session -------------------------*/ + +/* Start tracing with current parameter setting. If tracing is already in + * progress, an error is reported. Otherwise, tracing starts and any unsaved + * contents of the TraceRAM is discarded + * + * context : pointer to structure which contains information about the + * current TRAX session + * returns : 0 if successful, 1 if trace is already active, + * -1 if unsuccessful + */ +int trax_start (trax_context *context); + +/* This command initiates a stop trigger or halts a trace session based of the + * value of the flag parameter passed. In case stop trigger is initiated, any + * selected post-stop-trigger capture proceeds normally. + * If trace capture was not in progress, or a stop was already triggered, the + * return value indicates appropriately. + * + * context : pointer to structure which contains information about the + * current TRAX session + * flags : To differentiate between stopping trace without any + * post-size-trigger capture (trax_halt) or with that. + * A zero value would stop the trace based on trigger and a + * value of one would halt it + * + * returns : 0 if successful, 1 if already stopped, -1 if unsuccessful + */ +int trax_stop_halt (trax_context *context, int flags); + +/* Resets the TRAX parameters to their default values which would internally + * involve resetting the TRAX registers. To invoke another trace session or + * reset the current tracing mechanism, this function needs to be called as + * it resets parameters of the context that deal with tracing information + * + * context : pointer to structure which contains information about the + * current TRAX session + * + * returns : 0 if successful, -1 if unsuccessful + */ +int trax_reset (trax_context *context); + +/* ---------------Set/Get several TRAX parameters --------------------------*/ + +/* Sets the start address and end address (word aligned) of the trace in the + * TraceRAM. Care must be taken to ensure that the difference between the + * start and the end addresses is atleast TRAX_MIN_TRACEMEM bytes. If not, + * the values are reset to default, which is 0 for startaddr and + * traceRAM_words -1 for endaddr + * + * context : pointer to structure which contains information about the + * current TRAX session + * startaddr : value to which the start address must be set. Can be + * any value between 0 - (traceRAM_words - 1) + * endaddr : value to which the end address must be set. Can be any value + * between 0 - (traceRAM_words - 1) + * + * returns : 0 if successful, -1 if unsuccessful, -2 if the difference + * between the start and end addresses is less than + * TRAX_MIN_TRACEMEM bytes or if they are passed incorrect + * values, -3 if memory shared option is not configured, in + * which case, start and end addresses are set to default + * values instead of those passed by the user + */ +int trax_set_ram_boundaries (trax_context *context, unsigned startaddr, + unsigned endaddr); + +/* Shows the start address and end address(word aligned) of the trace in the + * TraceRAM. If incorrect, the startaddress and the endaddress values are + * set to default, i.e. 0 for startaddr and traceRAM_words - 1 for endaddr + * + * context : pointer to structure which contains information about the + * current TRAX session + * startaddr : pointer to value which will contain the start address + * endaddr : pointer to value which will contain the end address + * + * returns : 0 if successful, -1 if unsuccessful + * + */ +int trax_get_ram_boundaries (trax_context *context, unsigned *startaddr, + unsigned *endaddr); + +/* Selects stop trigger via cross-trigger input + * + * context : pointer to structure which contains information about the + * current TRAX session + * value : 0 = off (reset value), 1 = on + * + * returns : 0 if successful, -1 if unsuccessful + */ +int trax_set_ctistop (trax_context *context, unsigned value); + +/* Shows if stop-trigger via cross-trigger input is off or on + * + * context : pointer to structure which contains information about the + * current TRAX session + * returns : 0 if off, 1 if on, -1 if unsuccessful + */ +int trax_get_ctistop (trax_context *context); + +/* Selects stop trigger via processor-trigger input + * + * context : pointer to structure which contains information about the + * current TRAX session + * value : 0 = off (reset value), 1 = on + * + * returns : 0 if successful, -1 if unsuccessful + */ +int trax_set_ptistop (trax_context *context, unsigned value); + +/* Shows if stop trigger visa processor-trigger input is off or on + * + * context : pointer to structure which contains information about the + * current TRAX session + * returns : 0 if off, 1 if on, -1 if unsuccessful + */ +int trax_get_ptistop (trax_context *context); + +/* Reports cross trigger output state + * + * context : pointer to structure which contains information about the + * current TRAX session + * returns : 0 if CTO bit is reset, 1 if CTO bit is set + */ +int trax_get_cto (trax_context *context); + +/* Reports processor trigger output state + * + * context : pointer to structure which contains information about the + * current TRAX session + * returns : 0 if PTO bit is reset, 1 if PTO bit is set + */ +int trax_get_pto (trax_context *context); + +/* Selects condition that asserts cross trigger output + * + * context : pointer to structure which contains information about the + * current TRAX session + * option : 0 = off(reset value)/1 = ontrig/2 = onhalt + * + * returns : 0 if successful, -1 if unsuccessful + */ +int trax_set_ctowhen (trax_context *context, int option); + +/* Shows condition that asserted cross trigger output. It can be + * any of: ontrig or onhalt or even off + * + * context : pointer to structure which contains information about the + * current TRAX session + * + * returns : 0 if off, 1 if ontrig, 2 if onhalt, -1 if unsuccessful + */ +int trax_get_ctowhen (trax_context *context); + +/* Selects condition that asserts processor trigger output + * + * context : pointer to structure which contains information about the + * current TRAX session + * option : 0 = off(reset value)/1 = ontrig/2 = onhalt + * + * returns : 0 if successful, -1 if unsuccessful + */ +int trax_set_ptowhen (trax_context *context, int option); + + +/* Shows condition that asserted processor trigger output. It can be + * any of: ontrig or onhalt or even off + * + * context : pointer to structure which contains information about the + * current TRAX session + * returns : 0 if off, 1 if ontrig, 2 if onhalt, -1 if unsuccessful + */ +int trax_get_ptowhen (trax_context *context); + +/* Selects the trace synchronization message period. + * If ATEN enabled, we cannot allow syncper to be off, set it to reset value. + * Also, if no trace RAM, and ATEN enabled, set syncper to be reset value + * i.e. 256. A value of 1 i.e. on indicates that internally the message + * frequency is set to an optimal value. This option should be preferred + * if the user is not sure what message frequency option to set for the + * trace session. + * + * context : pointer to structure which contains information about the + * current TRAX session + * option : 0 = off, 1 = on, -1 = auto, 8, 16, 32, 64, 128, + * 256 (reset value) + * + * returns : 0 if successful, -1 if unsuccessful, -2 if incorrect + * arguments + */ +int trax_set_syncper (trax_context *context, int option); + +/* Shows trace synchronization message period. Can be one of: + * off, on, auto, 8, 16, 32, 64, 128, 256 (reset value) + * + * context : pointer to structure which contains information about the + * current TRAX session + * returns : value of sync period, 0 if off, -1 if unsuccessful + */ +int trax_get_syncper (trax_context *context); + +/* Selects stop trigger via PC match. Specifies the address or + * address range to match against program counter. Trace stops when the + * processor executes an instruction matching the specified address + * or range. + * + * context : pointer to structure which contains information about the + * current TRAX session + * index : indicates the number of stop trigger (currently there is + * only one i.e. index = 0) + * startaddress : start range of the address at which the stop trigger + * should be activated + * enaddress : end range of the address at which the stop trigger should + * be activated + * flags : If non-zero, this inverts the range. i.e. trace stops + * when the processor executes an instruction that does not + * match the specified address or range + * + * returns : 0 if successful, -1 if unsuccessful, -2 if incorrect + * arguments (unaligned) + * + * Note : For the current version of TRAX library, the endaddress and + * startaddress can differ by at most 31 bytes and the total + * range i.e. (endaddress - startaddress + 1) has to be a power + * of two + */ +int trax_set_pcstop (trax_context *context, int index, unsigned long startaddress, + unsigned long endaddress, int flags); + +/* Shows the stop trigger via PC match + * + * context : pointer to structure which contains information about the + * current TRAX session + * index : container of information about the number of stop triggers + * startaddress : container of start range of stop trigger + * endaddress : container of end range of stop trigger + * flags : container of information whcih indicates whether the + * pc stop range is inverted or not. + * + * returns : 0 if successful, -1 if unsuccessful + */ +int trax_get_pcstop (trax_context *context, int *index, + unsigned long *startaddress, + unsigned long *endaddress, int *flags); + +/* This function is used to set the amount of trace to be captured past + * the stop trigger. + * + * context : pointer to structure which contains information about the + * current TRAX session + * count_unit : contains the count of units (instructions or bytes) to be + * captured post trigger. If 0, it implies that this is off + * unit : unit of measuring the count. 0 is bytes, 1 is instructions + * 2 is percentage of trace + * + * returns : 0 if successful, -1 if unsuccessful, -2 if incorrect + * arguments + * + */ +int trax_set_postsize (trax_context *context, int count_unit, int unit); + +/* This function shows the amount of TraceRAM in terms of the number of + * instructions or bytes, captured post the stop trigger + * + * context : pointer to structure which contains information about the + * current TRAX session + * count_unit : will contain the count of units(instructions or bytes) post + * trigger + * unit : will contain information about the events that are counted + * 0 implies that the traceRAM words consumed are counted and + * 1 implies that the target processor instructions executed and + * excpetions/interrupts taken are counted + * + * returns : 0 if postsize was got successfully, -1 if unsuccessful + */ +int trax_get_postsize (trax_context *context, int *count_unit, int *unit); + +/* -------------------------- TRAX save routines ---------------------------*/ + +/* This function should be called by the user to return a chunk of + * bytes in buf. It can be a lower layer function of save, or can be + * called by the user explicitly. If bytes_actually_read contains a 0 + * after a call to this function has been made, it implies that the entire + * trace has been read successfully. + * + * context : pointer to structure which contains information about + * the current TRAX session + * buf : Buffer that is allocated by the user, all the trace + * data read would be put in this buffer, which can then + * be used to generate a tracefile. + * The first TRAX_HEADER_SIZE of the buffer will always + * contain the header information. + * bytes_to_be_read : Indicates the bytes the user wants to read. The first + * invocation would need this parameter to be + * TRAX_HEADER_SIZE at least. + * + * returns : bytes actually read during the call to this function. + * 0 implies that all the bytes in the trace have been + * read, -1 if unsuccessful read/write of + * registers or memory, -2 if trace was active while + * this function was called, -3 if user enters + * bytes_to_be_read < TRAX_HEADER_SIZE in the first + * pass + */ +int trax_get_trace (trax_context *context, void *buf, + int bytes_to_be_read); +#ifdef __cplusplus +} +#endif + +#endif /* _TRAX_H */ diff --git a/tools/sdk/include/esp32/xtensa/traxfile.h b/tools/sdk/include/esp32/xtensa/traxfile.h new file mode 100755 index 00000000..4afc926a --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/traxfile.h @@ -0,0 +1,62 @@ +/* TRAX file header definition. + + Copyright (c) 2007-2012 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + + +#define TRAX_FHEAD_MAGIC "TRAXdmp" +#define TRAX_FHEAD_VERSION 1 + +/* Header flags: */ +#define TRAX_FHEADF_OCD_ENABLED 0x00000001 /* set if OCD was enabled while capturing trace */ +#define TRAX_FHEADF_TESTDUMP 0x00000002 /* set if is a test file + (from 'memsave' instead of 'save') */ +#define TRAX_FHEADF_OCD_ENABLED_WHILE_EXIT 0x00000004 /* set if OCD was enabled while capturing trace and + we were exiting the OCD mode */ + +/* Header at the start of a TRAX dump file. */ +typedef struct { + char magic[8]; /* 00: "TRAXdmp\0" (TRAX_FHEAD_MAGIC) */ + char endianness; /* 08: 0=little-endian, 1=big-endian */ + char version; /* 09: TRAX_FHEAD_VERSION */ + char reserved0[2]; /* 0A: ... */ + unsigned filesize; /* 0C: size of the trace file, including this header */ + unsigned trace_ofs; /* 10: start of trace output, byte offset from start of header */ + unsigned trace_size; /* 14: size of trace output in bytes */ + unsigned dumptime; /* 18: date/time of capture save (secs since 1970-01-01), 0 if unknown */ + unsigned flags; /* 1C: misc flags (TRAX_FHEAD_F_xxx) */ + char username[16]; /* 20: user doing the capture/save (up to 15 chars) */ + char toolver[24]; /* 30: tool + version used for capture/save (up to 23 chars) */ + char reserved2[40]; /* 48: (reserved - could be hostname used for dump (up to 39 chars)) */ + unsigned configid[2]; /* 70: processor ConfigID values, 0 if unknown */ + unsigned ts_freq; /* 78: timestamp frequency, 0 if not specified */ + unsigned reserved3; /* 7C: (reserved) */ + unsigned id; /* 80: TRAX registers at time of save (0 if not read) */ + unsigned control; + unsigned status; + unsigned reserved4; /* Data register (should not be read) */ + unsigned address; + unsigned trigger; + unsigned match; + unsigned delay; + unsigned trax_regs[24]; /*100: (total size) -- dummy allocation (FIXME) */ +} trax_file_header; + diff --git a/tools/sdk/include/esp32/xtensa/traxreg.h b/tools/sdk/include/esp32/xtensa/traxreg.h new file mode 100755 index 00000000..282ba1fe --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/traxreg.h @@ -0,0 +1,199 @@ +/* TRAX register definitions + + Copyright (c) 2006-2012 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef _TRAX_REGISTERS_H_ +#define _TRAX_REGISTERS_H_ + +#define SHOW 1 +#define HIDE 0 + +#define RO 0 +#define RW 1 + +/* TRAX Register Numbers (from possible range of 0..127) */ +#if 0 +#define TRAXREG_ID 0 +#define TRAXREG_CONTROL 1 +#define TRAXREG_STATUS 2 +#define TRAXREG_DATA 3 +#define TRAXREG_ADDRESS 4 +#define TRAXREG_TRIGGER 5 +#define TRAXREG_MATCH 6 +#define TRAXREG_DELAY 7 +#define TRAXREG_STARTADDR 8 +#define TRAXREG_ENDADDR 9 +/* Internal use only (unpublished): */ +#define TRAXREG_P4CHANGE 16 +#define TRAXREG_P4REV 17 +#define TRAXREG_P4DATE 18 +#define TRAXREG_P4TIME 19 +#define TRAXREG_PDSTATUS 20 +#define TRAXREG_PDDATA 21 +#define TRAXREG_STOP_PC 22 +#define TRAXREG_STOP_ICNT 23 +#define TRAXREG_MSG_STATUS 24 +#define TRAXREG_FSM_STATUS 25 +#define TRAXREG_IB_STATUS 26 +#define TRAXREG_MAX 27 +#define TRAXREG_ITCTRL 96 +#endif +/* The registers above match the NAR addresses. So, their values are used for NAR access */ + +/* TRAX Register Fields */ + +/* TRAX ID register fields: */ +#define TRAX_ID_PRODNO 0xf0000000 /* product number (0=TRAX) */ +#define TRAX_ID_PRODOPT 0x0f000000 /* product options */ +#define TRAX_ID_MIW64 0x08000000 /* opt: instruction width */ +#define TRAX_ID_AMTRAX 0x04000000 /* opt: collection of options, + internal (VER_2_0 or later)*/ +#define TRAX_ID_MAJVER(id) (((id) >> 20) & 0x0f) +#define TRAX_ID_MINVER(id) (((id) >> 17) & 0x07) +#define TRAX_ID_VER(id) ((TRAX_ID_MAJVER(id)<<4)|TRAX_ID_MINVER(id)) +#define TRAX_ID_STDCFG 0x00010000 /* standard config */ +#define TRAX_ID_CFGID 0x0000ffff /* TRAX configuration ID */ +#define TRAX_ID_MEMSHARED 0x00001000 /* Memshared option in TRAX */ +#define TRAX_ID_FROM_VER(ver) ((((ver) & 0xf0) << 16) | (((ver) & 0x7) << 17)) +/* Other TRAX ID register macros: */ +/* TRAX versions of interest (TRAX_ID_VER(), ie. MAJVER*16 + MINVER): */ +#define TRAX_VER_1_0 0x10 /* RA */ +#define TRAX_VER_1_1 0x11 /* RB thru RC-2010.1 */ +#define TRAX_VER_2_0 0x20 /* RC-2010.2, RD-2010.0, + RD-2011.1 */ +#define TRAX_VER_2_1 0x21 /* RC-2011.3 / RD-2011.2 and + later */ +#define TRAX_VER_3_0 0x30 /* RE-2012.0 */ +#define TRAX_VER_3_1 0x31 /* RE-2012.1 */ +#define TRAX_VER_HUAWEI_3 TRAX_VER_3_0 /* For Huawei, PRs: 25223, 25224 + , 24880 */ + + +/* TRAX version 1.0 requires a couple software workarounds: */ +#define TRAX_ID_1_0_ERRATUM(id) (TRAX_ID_VER(id) == TRAX_VER_1_0) +/* TRAX version 2.0 requires software workaround for PR 22161: */ +#define TRAX_ID_MEMSZ_ERRATUM(id) (TRAX_ID_VER(id) == TRAX_VER_2_0) + +/* TRAX Control register fields: */ +#define TRAX_CONTROL_TREN 0x00000001 +#define TRAX_CONTROL_TRSTP 0x00000002 +#define TRAX_CONTROL_PCMEN 0x00000004 +#define TRAX_CONTROL_PTIEN 0x00000010 +#define TRAX_CONTROL_CTIEN 0x00000020 +#define TRAX_CONTROL_TMEN 0x00000080 /* 2.0+ */ +#define TRAX_CONTROL_CNTU 0x00000200 +#define TRAX_CONTROL_BIEN 0x00000400 +#define TRAX_CONTROL_BOEN 0x00000800 +#define TRAX_CONTROL_TSEN 0x00000800 +#define TRAX_CONTROL_SMPER 0x00007000 +#define TRAX_CONTROL_SMPER_SHIFT 12 +#define TRAX_CONTROL_PTOWT 0x00010000 +#define TRAX_CONTROL_CTOWT 0x00020000 +#define TRAX_CONTROL_PTOWS 0x00100000 +#define TRAX_CONTROL_CTOWS 0x00200000 +#define TRAX_CONTROL_ATID 0x7F000000 /* 2.0+, amtrax */ +#define TRAX_CONTROL_ATID_SHIFT 24 +#define TRAX_CONTROL_ATEN 0x80000000 /* 2.0+, amtrax */ + +#define TRAX_CONTROL_PTOWS_ER 0x00020000 /* For 3.0 */ +#define TRAX_CONTROL_CTOWT_ER 0x00100000 /* For 3.0 */ + +#define TRAX_CONTROL_ITCTO 0x00400000 /* For 3.0 */ +#define TRAX_CONTROL_ITCTIA 0x00800000 /* For 3.0 */ +#define TRAX_CONTROL_ITATV 0x01000000 /* For 3.0 */ + + +/* TRAX Status register fields: */ +#define TRAX_STATUS_TRACT 0x00000001 +#define TRAX_STATUS_TRIG 0x00000002 +#define TRAX_STATUS_PCMTG 0x00000004 +#define TRAX_STATUS_BUSY 0x00000008 /* ER ??? */ +#define TRAX_STATUS_PTITG 0x00000010 +#define TRAX_STATUS_CTITG 0x00000020 +#define TRAX_STATUS_MEMSZ 0x00001F00 +#define TRAX_STATUS_MEMSZ_SHIFT 8 +#define TRAX_STATUS_PTO 0x00010000 +#define TRAX_STATUS_CTO 0x00020000 + +#define TRAX_STATUS_ITCTOA 0x00400000 /* For 3.0 */ +#define TRAX_STATUS_ITCTI 0x00800000 /* For 3.0 */ +#define TRAX_STATUS_ITATR 0x01000000 /* For 3.0 */ + + +/* TRAX Address register fields: */ +#define TRAX_ADDRESS_TWSAT 0x80000000 +#define TRAX_ADDRESS_TWSAT_SHIFT 31 +#define TRAX_ADDRESS_TOTALMASK 0x00FFFFFF +// !!! VUakiVU. added for new TRAX: +#define TRAX_ADDRESS_WRAPCNT 0x7FE00000 /* version ???... */ +#define TRAX_ADDRESS_WRAP_SHIFT 21 + +/* TRAX PCMatch register fields: */ +#define TRAX_PCMATCH_PCML 0x0000001F +#define TRAX_PCMATCH_PCML_SHIFT 0 +#define TRAX_PCMATCH_PCMS 0x80000000 + +/* Compute trace ram buffer size (in bytes) from status register: */ +#define TRAX_MEM_SIZE(status) (1L << (((status) & TRAX_STATUS_MEMSZ) >> TRAX_STATUS_MEMSZ_SHIFT)) + +#if 0 +/* Describes a field within a register: */ +typedef struct { + const char* name; +// unsigned width; +// unsigned shift; + char width; + char shift; + char visible; /* 0 = internal use only, 1 = shown */ + char reserved; +} trax_regfield_t; +#endif + +/* Describes a TRAX register: */ +typedef struct { + const char* name; + unsigned id; + char width; + char visible; + char writable; + char reserved; + //const trax_regfield_t * fieldset; +} trax_regdef_t; + + +extern const trax_regdef_t trax_reglist[]; +extern const signed char trax_readable_regs[]; + +#ifdef __cplusplus +extern "C" { +#endif + +/* Prototypes: */ +extern int trax_find_reg(char * regname, char **errmsg); +extern const char * trax_regname(int regno); + +#ifdef __cplusplus +} +#endif + +#endif /* _TRAX_REGISTERS_H_ */ + diff --git a/tools/sdk/include/esp32/xtensa/uart-16550-board.h b/tools/sdk/include/esp32/xtensa/uart-16550-board.h new file mode 100755 index 00000000..8ef8af16 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/uart-16550-board.h @@ -0,0 +1,69 @@ +/******************************************************************************* +Copyright (c) 2006-2013 by Tensilica Inc. ALL RIGHTS RESERVED. +These coded instructions, statements, and computer programs are the +copyrighted works and confidential proprietary information of Tensilica Inc. +They may not be modified, copied, reproduced, distributed, or disclosed to +third parties in any manner, medium, or form, in whole or in part, without +the prior written consent of Tensilica Inc. +-------------------------------------------------------------------------------- + +uart-16550-board.h Board-specific UART info on these boards: + Avnet AV60 (XT-AV60) + Avnet AV110 (XT-AV110) + Avnet AV200 (XT-AV200) + Xilinx ML605 (XT-ML605) + Xilinx KC705 (XT-KC705) + +Interface between board-independent driver and board-specific header. + +This is used by a board-independent 16550 UART driver to obtain board-specific +information about 1 instance of the 16550 UART on the board, such as the device +register base address and spacing (a function of how the address lines are +connected on the board) and the frequency of the UART clock. The driver does +not refer directly to the board-specific header, which therefore is not +constrained to use macro names consistent with other boards. + +!! Must not contain any board-specific macro names (only UART specific). !! + +Included at compile-time via an include path specific to the board. + +These boards contain a single 16550 UART implemented on the FPGA. +Their clock frequency comes from the board's core clock (not its own crystal) +which depends on the core config so is not a constant. Obtained via the BSP. + +*******************************************************************************/ + +#ifndef _UART_16550_BOARD_H +#define _UART_16550_BOARD_H + +#include /* BSP API */ +#include /* Board info */ + + +/* Base address of UART's registers. */ +#ifdef UART16550_VADDR +#define UART_16550_REGBASE UART16550_VADDR +#endif + +/* +The UART's registers are connected at word addresses on these boards. +Each byte-wide register appears as the least-significant-byte (LSB) of the +word regardless of the endianness of the processor. +*/ +#define UART_16550_REGSPACING 4 +typedef unsigned uart16550_reg_t; + +/* UART Clock Frequency in Hz */ +#define UART_16550_XTAL_FREQ xtbsp_clock_freq_hz() + +/* UART Interrupt Number */ +#ifdef UART16550_INTNUM +#define UART_16550_INTNUM UART16550_INTNUM +#endif + + +/* Include generic information shared by all boards that use this device. */ +#include + +#endif /* _UART_16550_BOARD_H */ + diff --git a/tools/sdk/include/esp32/xtensa/uart-16550.h b/tools/sdk/include/esp32/xtensa/uart-16550.h new file mode 100755 index 00000000..c551c64c --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/uart-16550.h @@ -0,0 +1,152 @@ +/******************************************************************************* + + Copyright (c) 2006-2007 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +-------------------------------------------------------------------------------- + +uart-16550.h Generic definitions for National Semiconductor 16550 UART + +This is used by board-support-packages with one or more 16550 compatible UARTs. +A BSP provides a base address for each instance of a 16550 UART on the board. + +Note that a 16552 DUART (Dual UART) is simply two instances of a 16550 UART. + +*******************************************************************************/ + +#ifndef _UART_16550_H_ +#define _UART_16550_H_ + +/* C interface to UART registers. */ +struct uart_dev_s { + union { + uart16550_reg_t rxb; /* DLAB=0: receive buffer, read-only */ + uart16550_reg_t txb; /* DLAB=0: transmit buffer, write-only */ + uart16550_reg_t dll; /* DLAB=1: divisor, LS byte latch */ + } w0; + union { + uart16550_reg_t ier; /* DLAB=0: interrupt-enable register */ + uart16550_reg_t dlm; /* DLAB=1: divisor, MS byte latch */ + } w1; + + union { + uart16550_reg_t isr; /* DLAB=0: interrupt status register, read-only */ + uart16550_reg_t fcr; /* DLAB=0: FIFO control register, write-only */ + uart16550_reg_t afr; /* DLAB=1: alternate function register */ + } w2; + + uart16550_reg_t lcr; /* line control-register, write-only */ + uart16550_reg_t mcr; /* modem control-regsiter, write-only */ + uart16550_reg_t lsr; /* line status register, read-only */ + uart16550_reg_t msr; /* modem status register, read-only */ + uart16550_reg_t scr; /* scratch regsiter, read/write */ +}; + + +#define _RXB(u) ((u)->w0.rxb) +#define _TXB(u) ((u)->w0.txb) +#define _DLL(u) ((u)->w0.dll) +#define _IER(u) ((u)->w1.ier) +#define _DLM(u) ((u)->w1.dlm) +#define _ISR(u) ((u)->w2.isr) +#define _FCR(u) ((u)->w2.fcr) +#define _AFR(u) ((u)->w2.afr) +#define _LCR(u) ((u)->lcr) +#define _MCR(u) ((u)->mcr) +#define _LSR(u) ((u)->lsr) +#define _MSR(u) ((u)->msr) +#define _SCR(u) ((u)->scr) + +typedef volatile struct uart_dev_s uart_dev_t; + +/* IER bits */ +#define RCVR_DATA_REG_INTENABLE 0x01 +#define XMIT_HOLD_REG_INTENABLE 0x02 +#define RCVR_STATUS_INTENABLE 0x04 +#define MODEM_STATUS_INTENABLE 0x08 + +/* FCR bits */ +#define _FIFO_ENABLE 0x01 +#define RCVR_FIFO_RESET 0x02 +#define XMIT_FIFO_RESET 0x04 +#define DMA_MODE_SELECT 0x08 +#define RCVR_TRIGGER_LSB 0x40 +#define RCVR_TRIGGER_MSB 0x80 + +/* AFR bits */ +#define AFR_CONC_WRITE 0x01 +#define AFR_BAUDOUT_SEL 0x02 +#define AFR_RXRDY_SEL 0x04 + +/* ISR bits */ +#define INT_STATUS(r) ((r)&1) +#define INT_PRIORITY(r) (((r)>>1)&0x7) + +/* LCR bits */ +#define WORD_LENGTH(n) (((n)-5)&0x3) +#define STOP_BIT_ENABLE 0x04 +#define PARITY_ENABLE 0x08 +#define EVEN_PARITY 0x10 +#define FORCE_PARITY 0x20 +#define XMIT_BREAK 0x40 +#define DLAB_ENABLE 0x80 + +/* MCR bits */ +#define _DTR 0x01 +#define _RTS 0x02 +#define _OP1 0x04 +#define _OP2 0x08 +#define LOOP_BACK 0x10 + +/* LSR Bits */ +#define RCVR_DATA_READY 0x01 +#define OVERRUN_ERROR 0x02 +#define PARITY_ERROR 0x04 +#define FRAMING_ERROR 0x08 +#define BREAK_INTERRUPT 0x10 +#define XMIT_HOLD_EMPTY 0x20 +#define XMIT_EMPTY 0x40 +#define FIFO_ERROR 0x80 +#define RCVR_READY(u) (_LSR(u)&RCVR_DATA_READY) +#define XMIT_READY(u) (_LSR(u)&XMIT_HOLD_EMPTY) + +/* MSR bits */ +#define _RDR 0x01 +#define DELTA_DSR 0x02 +#define DELTA_RI 0x04 +#define DELTA_CD 0x08 +#define _CTS 0x10 +#define _DSR 0x20 +#define _RI 0x40 +#define _CD 0x80 + + +/* Compute 16-bit divisor for baudrate generator, with rounding: */ +#define UART_DIVISOR(clock,baud) (((clock)/16 + (baud)/2)/(baud)) + +/* Prototypes of driver functions */ +extern void uart16550_init( uart_dev_t *u, unsigned baud, unsigned ndata, + unsigned parity, unsigned nstop ); +extern void uart16550_out( uart_dev_t *u, char c ); +extern char uart16550_in( uart_dev_t *u ); +extern unsigned uart16550_measure_sys_clk( uart_dev_t *u ); + +#endif /* _UART_16550_H_ */ diff --git a/tools/sdk/include/esp32/xtensa/udma.h b/tools/sdk/include/esp32/xtensa/udma.h new file mode 100755 index 00000000..a5feb777 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/udma.h @@ -0,0 +1,276 @@ +/* Customer ID=11656; Build=0x5f626; Copyright (c) 2005-2014 by Cadence Design Systems, Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of + * Cadence Design Systems, Inc. They may not be modified, copied, reproduced, + * distributed, or disclosed to third parties in any manner, medium, or form, + * in whole or in part, without the prior written consent of Cadence Design + * Systems Inc. + */ +#ifndef __UDMA_H__ +#define __UDMA_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Size of the uDMA descriptor */ +#define UDMA_DESC_STRUCT_SIZE 32 + +/* Request attribute is a bit vector passed to the udma functions - udma_copy, + * udma_2d_copy, udma_add_descs. + * Bit 0 : 1 - trigger an interrupt when done, else do nothing + * Bit 1 : 0 - retry the failed request; abort after programmer specified + * number of retries. Defaults to abort with no retries. + * 1 - abort the failed request (after retries) and all pending requests + */ +#define UDMA_DONE_INTERRUPT 0x1 +#define UDMA_ERROR_ABORT 0x0 +#define UDMA_ERROR_ABORT_ALL 0x2 + +/* Enum representing various udma error conditions, udma status, and + * return values + */ +typedef enum { + UDMA_OK = 0, + UDMA_ERROR_QUEUE_FULL = 1, + UDMA_ERROR_BAD_DESC = 2, + UDMA_ERROR_DRAM_CROSSING = 3, + UDMA_ERROR_PIF_ADDR_BUS = 4, + UDMA_ERROR_PIF_DATA_BUS = 5, + UDMA_REQ_PENDING = 6, + UDMA_REQ_DONE = 7, + UDMA_ERROR_BAD_REQUEST = 8, + UDMA_ERROR_INVALID_ARG = 11, + UDMA_ERROR_INIT = 12, + UDMA_ERROR_INTERNAL = -1 +} udma_status_t; + +#ifndef __UDMA_INTERNAL_H__ +/* Opaque structure describing a uDMA descriptor */ +struct udma_desc_struct { + char _[UDMA_DESC_STRUCT_SIZE]; +} __attribute__ ((aligned (UDMA_DESC_STRUCT_SIZE))); +#endif + +typedef struct udma_desc_struct udma_desc_t; + +/* Initialize the udma control structure, the uDMA registers with + * the descriptor queue addresses, and the uDMA sync and error interrupt + * handler. This function needs to be invoked prior to using the uDMA. + * + * xmp_udma_sync_intr : Processor interrupt number to flag udma done + * xmp_udma_error_intr : Processor interrupt number to flag udma error + * + * Returns UDMA_ERROR_INIT if there was an error during initialization else + * returns UDMA_OK. + */ +extern udma_status_t +udma_init(uint32_t xmp_udma_sync_intr, uint32_t xmp_udma_error_intr); + +/* Performs a copy of a linear block of size bytes from the src + * to the dest address. If the call returns UDMA_OK, status is set to + * UDMA_REQ_PENDING or UDMA_REQ_DONE. If there is a dma error, the error code, + * which could be one of UDMA_ERROR_BAD_DESC, UDMA_ERROR_DRAM_CROSSING, + * UDMA_ERROR_PIF_ADDR_BUS, UDMA_ERROR_PIF_DATA_BUS is returned in the status. + * Status is set to UDMA_REQ_DONE if the dma completes normally. + * On completion, the callback function is invoked with the callback_data + * and status as parameters. Note, the callback is always invoked even if + * there is a dma error. + * + * src : src address of the copy + * dest : dest address of the copy + * size : number of bytes to copy + * callback_data : optional data to be passed to callback_func + * callback_func : optional callback after copy is done + * request_attr : attribute defining how to process this request + * (see description of the request attribute in top of udma.h) + * status : track status of the copy; this gets also passed + * as the second argument to the callback_func + * + * Returns UDMA_ERROR_QUEUE_FULL if no more requests can be added, else + * returns UDMA_OK. + */ +extern udma_status_t +udma_copy(void *dest, + void *src, + size_t size, + void *callback_data, + void (*callback_func)(void *, udma_status_t *status), + uint32_t request_attr, + udma_status_t *status); + +/* Performs a copy of a 2D block of data from the src to the dest + * address. If the call returns UDMA_OK, status is set to UDMA_REQ_PENDING or + * UDMA_REQ_DONE. If there is a dma error, the error code, + * which could be one of UDMA_ERROR_BAD_DESC, UDMA_ERROR_DRAM_CROSSING, + * UDMA_ERROR_PIF_ADDR_BUS, UDMA_ERROR_PIF_DATA_BUS is returned in the status. + * Status is set to UDMA_REQ_DONE if the dma completes normally. + * On completion, the callback function is invoked with the callback_data + * and status as parameters. Note, the callback is always invoked even if + * there is a dma error. + * + * src : src address of the copy + * dest : dest address of the copy + * row_size : number of bytes per row to copy + * num_rows : number of rows to copy + * src_pitch : src pitch + * dest_pitch : dest pitch + * callback_data : optional data to be passed to callback_func + * callback_func : optional callback after copy is done + * request_attr : attribute defining how to process this request + * (see description of the request attribute in top of udma.h) + * status : track status of the copy; this gets also passed + * as the second argument to the callback_func + * + * Returns UDMA_ERROR_QUEUE_FULL if no more requests can be added, else + * returns UDMA_OK. + */ +extern udma_status_t +udma_2d_copy(void *dest, + void *src, + size_t row_size, + uint32_t num_rows, + uint32_t src_pitch, + uint32_t dest_pitch, + void *callback_data, + void (*callback_func)(void *, udma_status_t *status), + uint32_t request_attr, + udma_status_t *status); + +/* Process requests that are done. Any callbacks associated + * with the completed requests gets invoked. If there are any errors, + * the error request is (and any pending request based on the request attribute) + * cancelled and the error code is returned in the status associated with + * all such cancelled requests. Callbacks associated with the cancelled + * requests are also invoked. If all requests terminate normally, the status + * of the completed requests are set to UDMA_REQ_DONE. + * + * Returns void + */ +extern void +udma_process_requests(); + +/* Sets the udma max PIF block size + * + * max_block_size : max block size to be set + * + * Returns UDMA_ERROR_INVALID_ARG if block_size is > 3, else returns UDMA_OK + */ +udma_status_t +udma_set_max_block_size(uint32_t block_size); + +/* Sets the udma max outstanding PIF requests + * + * max_outstanding : max outstanding PIF requests + * + * Returns UDMA_ERROR_INVALID_ARG if max_outstanding is not between 1 and 16 + * else returns UDMA_OK + */ +udma_status_t +udma_set_max_outstanding(uint32_t max_outstanding); + +/* Initialize a uDMA descriptor using the copy parameters. The descriptor + * is then queued separately using udma_add_desc + * + * src : src address of the copy + * dest : dest address of the copy + * row_size : number of bytes per row to copy + * num_rows : number of rows to copy + * src_pitch : src pitch + * dest_pitch : dest pitch + * notify_with_interrupt : If 1, interrupt when dma is done with this descriptor + * if 0, do nothing, else undefined + * + * Returns void + */ +extern void +udma_set_desc(void *src, + void *dest, + size_t row_size, + uint32_t num_rows, + uint32_t src_pitch, + uint32_t dest_pitch, + uint32_t notify_with_interrupt, + udma_desc_t *desc); + +/* Add multiple uDMA descriptors to the descriptor queue. If the call returns + * UDMA_OK, the status is set to UDMA_REQ_PENDING or UDMA_REQ_DONE. + * If there is a dma error, the error code, which could be one of + * UDMA_ERROR_BAD_DESC, UDMA_ERROR_DRAM_CROSSING, UDMA_ERROR_PIF_ADDR_BUS, + * UDMA_ERROR_PIF_DATA_BUS is returned in the status. Status is set + * to UDMA_REQ_DONE, if the dma completes normally. + * On completion, the callback function is invoked with the callback_data + * and status as parameters. Note, the callback is always invoked even if + * there is a dma error. + * + * desc : descriptors to be added + * num_desc : number of descriptors to be added + * callback_data : optional data to be passed to callback_func + * callback_func : optional callback after copy is done + * request_attr : attribute defining how to process this request + * (see description of the request attribute in top of udma.h) + * Note, bit 0 (for enabling interrupt) is ignored in this call. + * To interrupt on dma completion, set the + * notify_with_interrupt parameter when creating descriptors + * using udma_set_desc. + * status : track status of the copy; this gets also passed + * as the second argument to the callback_func + * + * Returns UDMA_ERROR_QUEUE_FULL if no more descriptors can be added, + * UDMA_ERROR_INVALID_ARG if num_descs == 0, else return UDMA_OK + */ +udma_status_t +udma_add_descs(udma_desc_t *descs, + uint32_t num_descs, + void *callback_data, + void (*callback_func)(void *, udma_status_t *status), + uint32_t request_attr, + udma_status_t *status); + +/* Wait for udma copy request to complete. Could spin wait or goto waiti + * based on the sleep_wait parameter. Once the request is done, the callback + * associated with this request and any prior completed requests are handled. + * Error code, if any, is returned in the status s, else s is set to + * UDMA_REQ_DONE. + * + * s : status to wait for + * sleep_wait : sleep wait if true, else spin waits + * + * Returns void + */ +extern void +udma_wait_request(volatile udma_status_t *s, uint32_t sleep_wait); + +/* Inlined function to set the src, dest address of the descriptor + * + * src : src address of the uDMA + * dest : dest address of the uDMA + * desc : descriptor to be modified + * + * Returns void + */ +void static inline +udma_set_desc_addrs(void *src, void *dest, udma_desc_t *desc) { + uint32_t *d = (uint32_t *)desc; + *d = (uintptr_t)src; + *(d+1) = (uintptr_t)dest; +} + +/* Sets the number of retries for a failed dma request + * + * max_retries : max number of retries + * + * Sets the max number of retries for a failed dma request. The default is 0, + * i.e, no retries + */ +void +udma_set_max_retries(uint32_t max_retries); + +#ifdef __cplusplus +} +#endif + +#endif /* __UDMA_H__ */ diff --git a/tools/sdk/include/esp32/xtensa/xdm-regs.h b/tools/sdk/include/esp32/xtensa/xdm-regs.h new file mode 100755 index 00000000..50ee0293 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/xdm-regs.h @@ -0,0 +1,530 @@ +/* xdm-regs.h - Common register and related definitions for the XDM + (Xtensa Debug Module) */ + +/* Copyright (c) 2011-2012 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + + +#ifndef _XDM_REGS_H_ +#define _XDM_REGS_H_ + +/* NOTE: This header file is included by C, assembler, and other sources. + So any C-specific or asm-specific content must be appropriately #ifdef'd. */ + + +/* + * XDM registers can be accessed using APB, ERI, or JTAG (via NAR). + * Address offsets for APB and ERI are the same, and for JTAG + * is different (due to the limited 7-bit NAR addressing). + * + * Here, we first provide the constants as APB / ERI address offsets. + * This is necessary for assembler code (which accesses XDM via ERI), + * because complex conversion macros between the two address maps + * don't work in the assembler. + * Conversion macros are used to convert these to/from JTAG (NAR), + * addresses, for software using JTAG. + */ +/* FIXME: maybe provide only MISC+CS registers here, and leave specific + subsystem registers in separate headers? eg. for TRAX, PERF, OCD */ + +/* XDM_.... ERI addr [NAR addr] Description...... */ + +/* TRAX */ +#define XDM_TRAX_ID 0x0000 /*[0x00] ID */ +#define XDM_TRAX_CONTROL 0x0004 /*[0x01] Control */ +#define XDM_TRAX_STATUS 0x0008 /*[0x02] Status */ +#define XDM_TRAX_DATA 0x000C /*[0x03] Data */ +#define XDM_TRAX_ADDRESS 0x0010 /*[0x04] Address */ +#define XDM_TRAX_TRIGGER 0x0014 /*[0x05] Stop PC */ +#define XDM_TRAX_MATCH 0x0018 /*[0x06] Stop PC Range */ +#define XDM_TRAX_DELAY 0x001C /*[0x07] Post Stop Trigger Capture Size */ +#define XDM_TRAX_STARTADDR 0x0020 /*[0x08] Trace Memory Start */ +#define XDM_TRAX_ENDADDR 0x0024 /*[0x09] Trace Memory End */ +#define XDM_TRAX_DEBUGPC 0x003C /*[0x0F] Debug PC */ +#define XDM_TRAX_P4CHANGE 0x0040 /*[0x10] X */ +#define XDM_TRAX_TIME0 0x0040 /*[0x10] First Time Register */ +#define XDM_TRAX_P4REV 0x0044 /*[0x11] X */ +#define XDM_TRAX_TIME1 0x0044 /*[0x11] Second Time Register */ +#define XDM_TRAX_P4DATE 0x0048 /*[0x12] X */ +#define XDM_TRAX_INTTIME_MAX 0x0048 /*[0x12] maximal Value of Timestamp IntTime */ +#define XDM_TRAX_P4TIME 0x004C /*[0x13] X */ +#define XDM_TRAX_PDSTATUS 0x0050 /*[0x14] Sample of PDebugStatus */ +#define XDM_TRAX_PDDATA 0x0054 /*[0x15] Sample of PDebugData */ +#define XDM_TRAX_STOP_PC 0x0058 /*[0x16] X */ +#define XDM_TRAX_STOP_ICNT 0x005C /*[0x16] X */ +#define XDM_TRAX_MSG_STATUS 0x0060 /*[0x17] X */ +#define XDM_TRAX_FSM_STATUS 0x0064 /*[0x18] X */ +#define XDM_TRAX_IB_STATUS 0x0068 /*[0x19] X */ +#define XDM_TRAX_STOPCNT 0x006C /*[0x1A] X */ + +/* Performance Monitoring Counters */ +#define XDM_PERF_PMG 0x1000 /*[0x20] perf. mon. global control register */ +#define XDM_PERF_INTPC 0x1010 /*[0x24] perf. mon. interrupt PC */ +#define XDM_PERF_PM0 0x1080 /*[0x28] perf. mon. counter 0 value */ +#define XDM_PERF_PM1 0x1084 /*[0x29] perf. mon. counter 1 value */ +#define XDM_PERF_PM2 0x1088 /*[0x2A] perf. mon. counter 2 value */ +#define XDM_PERF_PM3 0x108C /*[0x2B] perf. mon. counter 3 value */ +#define XDM_PERF_PM4 0x1090 /*[0x2C] perf. mon. counter 4 value */ +#define XDM_PERF_PM5 0x1094 /*[0x2D] perf. mon. counter 5 value */ +#define XDM_PERF_PM6 0x1098 /*[0x2E] perf. mon. counter 6 value */ +#define XDM_PERF_PM7 0x109C /*[0x2F] perf. mon. counter 7 value */ +#define XDM_PERF_PM(n) (0x1080+((n)<<2)) /* perfmon cnt n=0..7 value */ +#define XDM_PERF_PMCTRL0 0x1100 /*[0x30] perf. mon. counter 0 control */ +#define XDM_PERF_PMCTRL1 0x1104 /*[0x31] perf. mon. counter 1 control */ +#define XDM_PERF_PMCTRL2 0x1108 /*[0x32] perf. mon. counter 2 control */ +#define XDM_PERF_PMCTRL3 0x110C /*[0x33] perf. mon. counter 3 control */ +#define XDM_PERF_PMCTRL4 0x1110 /*[0x34] perf. mon. counter 4 control */ +#define XDM_PERF_PMCTRL5 0x1114 /*[0x35] perf. mon. counter 5 control */ +#define XDM_PERF_PMCTRL6 0x1118 /*[0x36] perf. mon. counter 6 control */ +#define XDM_PERF_PMCTRL7 0x111C /*[0x37] perf. mon. counter 7 control */ +#define XDM_PERF_PMCTRL(n) (0x1100+((n)<<2)) /* perfmon cnt n=0..7 control */ +#define XDM_PERF_PMSTAT0 0x1180 /*[0x38] perf. mon. counter 0 status */ +#define XDM_PERF_PMSTAT1 0x1184 /*[0x39] perf. mon. counter 1 status */ +#define XDM_PERF_PMSTAT2 0x1188 /*[0x3A] perf. mon. counter 2 status */ +#define XDM_PERF_PMSTAT3 0x118C /*[0x3B] perf. mon. counter 3 status */ +#define XDM_PERF_PMSTAT4 0x1190 /*[0x3C] perf. mon. counter 4 status */ +#define XDM_PERF_PMSTAT5 0x1194 /*[0x3D] perf. mon. counter 5 status */ +#define XDM_PERF_PMSTAT6 0x1198 /*[0x3E] perf. mon. counter 6 status */ +#define XDM_PERF_PMSTAT7 0x119C /*[0x3F] perf. mon. counter 7 status */ +#define XDM_PERF_PMSTAT(n) (0x1180+((n)<<2)) /* perfmon cnt n=0..7 status */ + +/* On-Chip-Debug (OCD) */ +#define XDM_OCD_ID 0x2000 /*[0x40] ID register */ +#define XDM_OCD_DCR_CLR 0x2008 /*[0x42] Debug Control reg clear */ +#define XDM_OCD_DCR_SET 0x200C /*[0x43] Debug Control reg set */ +#define XDM_OCD_DSR 0x2010 /*[0x44] Debug Status reg */ +#define XDM_OCD_DDR 0x2014 /*[0x45] Debug Data reg */ +#define XDM_OCD_DDREXEC 0x2018 /*[0x46] Debug Data reg + execute-DIR */ +#define XDM_OCD_DIR0EXEC 0x201C /*[0x47] Debug Instruction reg, word 0 + execute-DIR */ +#define XDM_OCD_DIR0 0x2020 /*[0x48] Debug Instruction reg, word 1 */ +#define XDM_OCD_DIR1 0x2024 /*[0x49] Debug Instruction reg, word 2 */ +#define XDM_OCD_DIR2 0x2028 /*[0x4A] Debug Instruction reg, word 3 */ +#define XDM_OCD_DIR3 0x202C /*[0x49] Debug Instruction reg, word 4 */ +#define XDM_OCD_DIR4 0x2030 /*[0x4C] Debug Instruction reg, word 5 */ +#define XDM_OCD_DIR5 0x2034 /*[0x4D] Debug Instruction reg, word 5 */ +#define XDM_OCD_DIR6 0x2038 /*[0x4E] Debug Instruction reg, word 6 */ +#define XDM_OCD_DIR7 0x203C /*[0x4F] Debug Instruction reg, word 7 */ + +/* Miscellaneous Registers */ +#define XDM_MISC_PWRCTL 0x3020 /*[0x58] Power and Reset Control */ +#define XDM_MISC_PWRSTAT 0x3024 /*[0x59] Power and Reset Status */ +#define XDM_MISC_ERISTAT 0x3028 /*[0x5A] ERI Transaction Status */ +#define XDM_MISC_DATETIME 0x3034 /*[0x5D] [INTERNAL] Timestamps of build */ +#define XDM_MISC_UBID 0x3038 /*[0x5E] [INTERNAL] Build Unique ID */ +#define XDM_MISC_CID 0x303C /*[0x5F] [INTERNAL] Customer ID */ + +/* CoreSight compatibility */ +#define XDM_CS_ITCTRL 0x3F00 /*[0x60] InTegration Mode control reg */ +#define XDM_CS_CLAIMSET 0x3FA0 /*[0x68] Claim Tag Set reg */ +#define XDM_CS_CLAIMCLR 0x3FA4 /*[0x69] Claim Tag Clear reg */ +#define XDM_CS_LOCK_ACCESS 0x3FB0 /*[0x6B] Lock Access (writing 0xC5ACCE55 unlocks) */ +#define XDM_CS_LOCK_STATUS 0x3FB4 /*[0x6D] Lock Status */ +#define XDM_CS_AUTH_STATUS 0x3FB8 /*[0x6E] Authentication Status */ +#define XDM_CS_DEV_ID 0x3FC8 /*[0x72] Device ID */ +#define XDM_CS_DEV_TYPE 0x3FCC /*[0x73] Device Type */ +#define XDM_CS_PER_ID4 0x3FD0 /*[0x74] Peripheral ID reg byte 4 */ +#define XDM_CS_PER_ID5 0x3FD4 /*[0x75] Peripheral ID reg byte 5 */ +#define XDM_CS_PER_ID6 0x3FD8 /*[0x76] Peripheral ID reg byte 6 */ +#define XDM_CS_PER_ID7 0x3FDC /*[0x77] Peripheral ID reg byte 7 */ +#define XDM_CS_PER_ID0 0x3FE0 /*[0x78] Peripheral ID reg byte 0 */ +#define XDM_CS_PER_ID1 0x3FE4 /*[0x79] Peripheral ID reg byte 1 */ +#define XDM_CS_PER_ID2 0x3FE8 /*[0x7A] Peripheral ID reg byte 2 */ +#define XDM_CS_PER_ID3 0x3FEC /*[0x7B] Peripheral ID reg byte 3 */ +#define XDM_CS_COMP_ID0 0x3FF0 /*[0x7C] Component ID reg byte 0 */ +#define XDM_CS_COMP_ID1 0x3FF4 /*[0x7D] Component ID reg byte 1 */ +#define XDM_CS_COMP_ID2 0x3FF8 /*[0x7E] Component ID reg byte 2 */ +#define XDM_CS_COMP_ID3 0x3FFC /*[0x7F] Component ID reg byte 3 */ + +#define CS_PER_ID0 0x00000003 +#define CS_PER_ID1 0x00000021 +#define CS_PER_ID2 0x0000000f +#define CS_PER_ID3 0x00000000 +#define CS_PER_ID4 0x00000024 + +#define CS_COMP_ID0 0x0000000d +#define CS_COMP_ID1 0x00000090 +#define CS_COMP_ID2 0x00000005 +#define CS_COMP_ID3 0x000000b1 + +#define CS_DEV_TYPE 0x00000015 + +#define XTENSA_IDCODE 0x120034e5 // FIXME (upper bits not spec. out but BE is !) +#define XTENSA_MFC_ID (XTENSA_IDCODE & 0xFFF) +#define CS_DEV_ID XTENSA_IDCODE + +#define NXS_OCD_REG(val) ((val >= 0x40) && (val <= 0x5F)) +#define NXS_TRAX_REG(val) val <= 0x3F + +#define ERI_TRAX_REG(val) ((val & 0xFFFF) < 0x1000) +#define ERI_OCD_REG(val) ((val & 0xFFFF) >= 0x2000) && ((val & 0xFFFF) < 0x4000)) + +/* Convert above 14-bit ERI/APB address/offset to 7-bit NAR address: */ +#define _XDM_ERI_TO_NAR(a) ( ((a)&0x3F80)==0x0000 ? (((a)>>2) & 0x1F) \ + : ((a)&0x3E00)==0x1000 ? (0x20 | (((a)>>2) & 7) | (((a)>>4) & 0x18)) \ + : ((a)&0x3FC0)==0x2000 ? (0x40 | (((a)>>2) & 0xF)) \ + : ((a)&0x3FE0)==0x3020 ? (0x50 | (((a)>>2) & 0xF)) \ + : ((a)&0x3FFC)==0x3F00 ? 0x60 \ + : ((a)&0x3F80)==0x3F80 ? (0x60 | (((a)>>2) & 0x1F)) \ + : -1 ) + +#define XDM_ERI_TO_NAR(a) _XDM_ERI_TO_NAR(a & 0xFFFF) + +/* Convert 7-bit NAR address back to ERI/APB address/offset: */ +#define _XDM_NAR_TO_APB(a) ((a) <= 0x1f ? ((a) << 2) \ + :(a) >= 0x20 && (a) <= 0x3F ? (0x1000 | (((a)& 7) << 2) | (((a)&0x18)<<4)) \ + :(a) >= 0x40 && (a) <= 0x4F ? (0x2000 | (((a)&0xF) << 2)) \ + :(a) >= 0x58 && (a) <= 0x5F ? (0x3000 | (((a)&0xF) << 2)) \ + :(a) == 0x60 ? (0x3F00) \ + :(a) >= 0x68 && (a) <= 0x7F ? (0x3F80 | (((a)&0x1F) << 2)) \ + : -1) + +#define XDM_NAR_TO_APB(a) _XDM_NAR_TO_APB((a & 0xFFFF)) +#define XDM_NAR_TO_ERI(a) _XDM_NAR_TO_APB((a & 0xFFFF)) | 0x000000 + +/* Convert APB to ERI address */ +#define XDM_APB_TO_ERI(a) ((a) | (0x100000)) +#define XDM_ERI_TO_APB(a) ((a) & (0x0FFFFF)) + +/*********** Bit definitions within some of the above registers ***********/ +#define OCD_ID_LSDDRP 0x01000000 +#define OCD_ID_LSDDRP_SHIFT 24 +#define OCD_ID_ENDIANESS 0x00000001 +#define OCD_ID_ENDIANESS_SHIFT 0 +#define OCD_ID_PSO 0x0000000C +#define OCD_ID_PSO_SHIFT 2 +#define OCD_ID_TRACEPORT 0x00000080 +#define OCD_ID_TRACEPORT_SHIFT 7 + +/* Power Status register. NOTE: different bit positions in JTAG vs. ERI/APB !! */ +/* ERI/APB: */ +#define PWRSTAT_CORE_DOMAIN_ON 0x00000001 /* set if core is powered on */ +#define PWRSTAT_CORE_DOMAIN_ON_SHIFT 0 +#define PWRSTAT_WAKEUP_RESET 0x00000002 /* [ERI only] 0=cold start, 1=PSO wakeup */ +#define PWRSTAT_WAKEUP_RESET_SHIFT 1 +#define PWRSTAT_CACHES_LOST_POWER 0x00000004 /* [ERI only] set if caches (/localmems?) lost power */ + /* FIXME: does this include local memories? */ +#define PWRSTAT_CACHES_LOST_POWER_SHIFT 2 +#define PWRSTAT_CORE_STILL_NEEDED 0x00000010 /* set if others keeping core awake */ +#define PWRSTAT_CORE_STILL_NEEDED_SHIFT 4 +#define PWRSTAT_MEM_DOMAIN_ON 0x00000100 /* set if memory domain is powered on */ +#define PWRSTAT_MEM_DOMAIN_ON_SHIFT 8 +#define PWRSTAT_DEBUG_DOMAIN_ON 0x00001000 /* set if debug domain is powered on */ +#define PWRSTAT_DEBUG_DOMAIN_ON_SHIFT 12 +#define PWRSTAT_ALL_ON PWRSTAT_CORE_DOMAIN_ON | PWRSTAT_MEM_DOMAIN_ON | PWRSTAT_DEBUG_DOMAIN_ON +#define PWRSTAT_CORE_WAS_RESET 0x00010000 /* [APB only] set if core got reset */ +#define PWRSTAT_CORE_WAS_RESET_SHIFT 16 +#define PWRSTAT_DEBUG_WAS_RESET 0x10000000 /* set if debug module got reset */ +#define PWRSTAT_DEBUG_WAS_RESET_SHIFT 28 +/* JTAG: */ +#define J_PWRSTAT_CORE_DOMAIN_ON 0x01 /* set if core is powered on */ +#define J_PWRSTAT_MEM_DOMAIN_ON 0x02 /* set if memory domain is powered on */ +#define J_PWRSTAT_DEBUG_DOMAIN_ON 0x04 /* set if debug domain is powered on */ +#define J_PWRSTAT_ALL_ON J_PWRSTAT_CORE_DOMAIN_ON | J_PWRSTAT_MEM_DOMAIN_ON | J_PWRSTAT_DEBUG_DOMAIN_ON +#define J_PWRSTAT_CORE_STILL_NEEDED 0x08 /* set if others keeping core awake */ +#define J_PWRSTAT_CORE_WAS_RESET 0x10 /* set if core got reset */ +#define J_PWRSTAT_DEBUG_WAS_RESET 0x40 /* set if debug module got reset */ + +/* Power Control register. NOTE: different bit positions in JTAG vs. ERI/APB !! */ +/* ERI/APB: */ +#define PWRCTL_CORE_SHUTOFF 0x00000001 /* [ERI only] core wants to shut off on WAITI */ +#define PWRCTL_CORE_SHUTOFF_SHIFT 0 +#define PWRCTL_CORE_WAKEUP 0x00000001 /* [APB only] set to force core to stay powered on */ +#define PWRCTL_CORE_WAKEUP_SHIFT 0 +#define PWRCTL_MEM_WAKEUP 0x00000100 /* set to force memory domain to stay powered on */ +#define PWRCTL_MEM_WAKEUP_SHIFT 8 +#define PWRCTL_DEBUG_WAKEUP 0x00001000 /* set to force debug domain to stay powered on */ +#define PWRCTL_DEBUG_WAKEUP_SHIFT 12 +#define PWRCTL_ALL_ON PWRCTL_CORE_WAKEUP | PWRCTL_MEM_WAKEUP | PWRCTL_DEBUG_WAKEUP +#define PWRCTL_CORE_RESET 0x00010000 /* [APB only] set to assert core reset */ +#define PWRCTL_CORE_RESET_SHIFT 16 +#define PWRCTL_DEBUG_RESET 0x10000000 /* set to assert debug module reset */ +#define PWRCTL_DEBUG_RESET_SHIFT 28 +/* JTAG: */ +#define J_PWRCTL_CORE_WAKEUP 0x01 /* set to force core to stay powered on */ +#define J_PWRCTL_MEM_WAKEUP 0x02 /* set to force memory domain to stay powered on */ +#define J_PWRCTL_DEBUG_WAKEUP 0x04 /* set to force debug domain to stay powered on */ +#define J_DEBUG_USE 0x80 /* */ +#define J_PWRCTL_ALL_ON J_DEBUG_USE | J_PWRCTL_CORE_WAKEUP | J_PWRCTL_MEM_WAKEUP | J_PWRCTL_DEBUG_WAKEUP +#define J_PWRCTL_DEBUG_ON J_DEBUG_USE | J_PWRCTL_DEBUG_WAKEUP +#define J_PWRCTL_CORE_RESET 0x10 /* set to assert core reset */ +#define J_PWRCTL_DEBUG_RESET 0x40 /* set to assert debug module reset */ + +#define J_PWRCTL_WRITE_MASK 0xFF +#define J_PWRSTAT_WRITE_MASK 0xFF + +#define PWRCTL_WRITE_MASK ~0 +#define PWRSTAT_WRITE_MASK ~0 + +/************ The following are only relevant for JTAG, so perhaps belong in OCD only **************/ + +/* XDM 5-bit JTAG Instruction Register (IR) values: */ +#define XDM_IR_PWRCTL 0x08 /* select 8-bit Power/Reset Control (PRC) */ +#define XDM_IR_PWRSTAT 0x09 /* select 8-bit Power/Reset Status (PRS) */ +#define XDM_IR_NAR_SEL 0x1c /* select altern. 8-bit NAR / 32-bit NDR (Nexus-style) */ +#define XDM_IR_NDR_SEL 0x1d /* select altern. 32-bit NDR / 8-bit NAR + (FIXME - functionality not yet in HW) */ +#define XDM_IR_IDCODE 0x1e /* select 32-bit JTAG IDCODE */ +#define XDM_IR_BYPASS 0x1f /* select 1-bit bypass */ + +#define XDM_IR_WIDTH 5 /* width of IR for Xtensa TAP */ + +/* NAR register bits: */ +#define XDM_NAR_WRITE 0x01 +#define XDM_NAR_ADDR_MASK 0xFE +#define XDM_NAR_ADDR_SHIFT 1 + +#define XDM_NAR_BUSY 0x02 +#define XDM_NAR_ERROR 0x01 + +#define NEXUS_DIR_READ 0x00 +#define NEXUS_DIR_WRITE 0x01 + +/************ Define DCR register bits **************/ + +#define DCR_ENABLEOCD 0x0000001 +#define DCR_ENABLEOCD_SHIFT 0 +#define DCR_DEBUG_INT 0x0000002 +#define DCR_DEBUG_INT_SHIFT 1 +#define DCR_DEBUG_OVERRIDE 0x0000004 +#define DCR_DEBUG_OVERRIDE_SHIFT 2 +#define DCR_DEBUG_INTERCEPT 0x0000008 +#define DCR_DEBUG_INTERCEPT_SHIFT 3 +#define DCR_MASK_NMI 0x0000020 +#define DCR_MASK_NMI_SHIFT 5 +#define DCR_STEP_ENABLE 0x0000040 +#define DCR_STEP_ENABLE_SHIFT 6 +#define DCR_BREAK_IN_EN 0x0010000 +#define DCR_BREAK_IN_EN_SHIFT 16 +#define DCR_BREAK_OUT_EN 0x0020000 +#define DCR_BREAK_OUT_EN_SHIFT 17 +#define DCR_DEBUG_INT_EN 0x0040000 +#define DCR_DEBUG_INT_EN_SHIFT 18 +#define DCR_DBG_SW_ACTIVE 0x0100000 +#define DCR_DBG_SW_ACTIVE_SHIFT 20 +#define DCR_STALL_IN_EN 0x0200000 +#define DCR_STALL_IN_EN_SHIFT 21 +#define DCR_DEBUG_OUT_EN 0x0400000 +#define DCR_DEBUG_OUT_EN_SHIFT 22 +#define DCR_BREAK_OUT_ITO 0x1000000 +#define DCR_STALL_OUT_ITO 0x2000000 +#define DCR_STALL_OUT_ITO_SHIFT 25 + +/************ Define DSR register bits **************/ + +#define DOSR_EXECDONE_ER 0x01 +#define DOSR_EXECDONE_SHIFT 0 +#define DOSR_EXCEPTION_ER 0x02 +#define DOSR_EXCEPTION_SHIFT 1 +#define DOSR_BUSY 0x04 +#define DOSR_BUSY_SHIFT 2 +#define DOSR_OVERRUN 0x08 +#define DOSR_OVERRUN_SHIFT 3 +#define DOSR_INOCDMODE_ER 0x10 +#define DOSR_INOCDMODE_SHIFT 4 +#define DOSR_CORE_WROTE_DDR_ER 0x400 +#define DOSR_CORE_WROTE_DDR_SHIFT 10 +#define DOSR_CORE_READ_DDR_ER 0x800 +#define DOSR_CORE_READ_DDR_SHIFT 11 +#define DOSR_HOST_WROTE_DDR_ER 0x4000 +#define DOSR_HOST_WROTE_DDR_SHIFT 14 +#define DOSR_HOST_READ_DDR_ER 0x8000 +#define DOSR_HOST_READ_DDR_SHIFT 15 + +#define DOSR_DEBUG_PEND_BIN 0x10000 +#define DOSR_DEBUG_PEND_HOST 0x20000 +#define DOSR_DEBUG_PEND_TRAX 0x40000 +#define DOSR_DEBUG_BIN 0x100000 +#define DOSR_DEBUG_HOST 0x200000 +#define DOSR_DEBUG_TRAX 0x400000 +#define DOSR_DEBUG_PEND_BIN_SHIFT 16 +#define DOSR_DEBUG_PEND_HOST_SHIFT 17 +#define DOSR_DEBUG_PEND_TRAX_SHIFT 18 +#define DOSR_DEBUG_BREAKIN 0x0100000 +#define DOSR_DEBUG_BREAKIN_SHIFT 20 +#define DOSR_DEBUG_HOST_SHIFT 21 +#define DOSR_DEBUG_TRAX_SHIFT 22 + +#define DOSR_DEBUG_STALL 0x1000000 +#define DOSR_DEBUG_STALL_SHIFT 24 + +#define DOSR_CORE_ON 0x40000000 +#define DOSR_CORE_ON_SHIFT 30 +#define DOSR_DEBUG_ON 0x80000000 +#define DOSR_DEBUG_ON_SHIFT 31 + +/********** Performance monitor registers bits **********/ + +#define PERF_PMG_ENABLE 0x00000001 /* global enable bit */ +#define PERF_PMG_ENABLE_SHIFT 0 + +#define PERF_PMCTRL_INT_ENABLE 0x00000001 /* assert interrupt on overflow */ +#define PERF_PMCTRL_INT_ENABLE_SHIFT 0 +#define PERF_PMCTRL_KRNLCNT 0x00000008 /* ignore TRACELEVEL */ +#define PERF_PMCTRL_KRNLCNT_SHIFT 3 +#define PERF_PMCTRL_TRACELEVEL 0x000000F0 /* count when CINTLEVEL <= TRACELEVEL */ +#define PERF_PMCTRL_TRACELEVEL_SHIFT 4 +#define PERF_PMCTRL_SELECT 0x00001F00 /* events group selector */ +#define PERF_PMCTRL_SELECT_SHIFT 8 +#define PERF_PMCTRL_MASK 0xFFFF0000 /* events mask */ +#define PERF_PMCTRL_MASK_SHIFT 16 + +#define PERF_PMSTAT_OVERFLOW 0x00000001 /* counter overflowed */ +#define PERF_PMSTAT_OVERFLOW_SHIFT 0 +#define PERF_PMSTAT_INT 0x00000010 /* interrupt asserted */ +#define PERF_PMSTAT_INT_SHIFT 4 + +#if defined (USE_XDM_REGNAME) || defined (USE_DAP_REGNAME) +/* Describes XDM register: */ +typedef struct { + int reg; + char* name; +} regdef_t; + +/*char* regname(regdef_t* list, int regno) +{ + unsigned i; + for(i = 0 ; i < (sizeof(list) / sizeof(regdef_t)); i++){ + if(list[i].reg == regno) + return list[i].name; + } + return "???"; +}*/ + +/* + * Returns the name of the specified XDM register number, + * or simply "???" if the register number is not recognized. + * FIXME - requires -1 as the last entry - change to compare the name to ??? + * or even better, make the code above to work. + */ +static char * regname(regdef_t* list, int reg) +{ + int i = 0; + while (list[i].reg != -1){ + if (list[i].reg == reg) + break; + i++; + } + return list[i].name; +} + +#if defined (USE_XDM_REGNAME) +regdef_t xdm_reglist[] = +{ + {XDM_TRAX_ID ,"TRAX_ID" }, + {XDM_TRAX_CONTROL ,"CONTROL" }, + {XDM_TRAX_STATUS ,"STATUS" }, + {XDM_TRAX_DATA ,"DATA" }, + {XDM_TRAX_ADDRESS ,"ADDRESS" }, + {XDM_TRAX_TRIGGER ,"TRIGGER PC" }, + {XDM_TRAX_MATCH ,"PC MATCH" }, + {XDM_TRAX_DELAY ,"DELAY CNT." }, + {XDM_TRAX_STARTADDR ,"START ADDRESS"}, + {XDM_TRAX_ENDADDR ,"END ADDRESS" }, + {XDM_TRAX_DEBUGPC ,"DEBUG PC" }, + {XDM_TRAX_P4CHANGE ,"P4 CHANGE" }, + {XDM_TRAX_P4REV ,"P4 REV." }, + {XDM_TRAX_P4DATE ,"P4 DATE" }, + {XDM_TRAX_P4TIME ,"P4 TIME" }, + {XDM_TRAX_PDSTATUS ,"PD STATUS" }, + {XDM_TRAX_PDDATA ,"PD DATA" }, + {XDM_TRAX_STOP_PC ,"STOP PC" }, + {XDM_TRAX_STOP_ICNT ,"STOP ICNT" }, + {XDM_TRAX_MSG_STATUS ,"MSG STAT." }, + {XDM_TRAX_FSM_STATUS ,"FSM STAT." }, + {XDM_TRAX_IB_STATUS ,"IB STAT." }, + + {XDM_OCD_ID ,"OCD_ID" }, + {XDM_OCD_DCR_CLR ,"DCR_CLR" }, + {XDM_OCD_DCR_SET ,"DCR_SET" }, + {XDM_OCD_DSR ,"DOSR" }, + {XDM_OCD_DDR ,"DDR" }, + {XDM_OCD_DDREXEC ,"DDREXEC" }, + {XDM_OCD_DIR0EXEC ,"DIR0EXEC"}, + {XDM_OCD_DIR0 ,"DIR0" }, + {XDM_OCD_DIR1 ,"DIR1" }, + {XDM_OCD_DIR2 ,"DIR2" }, + {XDM_OCD_DIR3 ,"DIR3" }, + {XDM_OCD_DIR4 ,"DIR4" }, + {XDM_OCD_DIR5 ,"DIR5" }, + {XDM_OCD_DIR6 ,"DIR6" }, + {XDM_OCD_DIR7 ,"DIR7" }, + + {XDM_PERF_PMG ,"PMG" }, + {XDM_PERF_INTPC ,"INTPC" }, + {XDM_PERF_PM0 ,"PM0 " }, + {XDM_PERF_PM1 ,"PM1 " }, + {XDM_PERF_PM2 ,"PM2 " }, + {XDM_PERF_PM3 ,"PM3 " }, + {XDM_PERF_PM4 ,"PM4 " }, + {XDM_PERF_PM5 ,"PM5 " }, + {XDM_PERF_PM6 ,"PM6 " }, + {XDM_PERF_PM7 ,"PM7 " }, + {XDM_PERF_PMCTRL0 ,"PMCTRL0"}, + {XDM_PERF_PMCTRL1 ,"PMCTRL1"}, + {XDM_PERF_PMCTRL2 ,"PMCTRL2"}, + {XDM_PERF_PMCTRL3 ,"PMCTRL3"}, + {XDM_PERF_PMCTRL4 ,"PMCTRL4"}, + {XDM_PERF_PMCTRL5 ,"PMCTRL5"}, + {XDM_PERF_PMCTRL6 ,"PMCTRL6"}, + {XDM_PERF_PMCTRL7 ,"PMCTRL7"}, + {XDM_PERF_PMSTAT0 ,"PMSTAT0"}, + {XDM_PERF_PMSTAT1 ,"PMSTAT1"}, + {XDM_PERF_PMSTAT2 ,"PMSTAT2"}, + {XDM_PERF_PMSTAT3 ,"PMSTAT3"}, + {XDM_PERF_PMSTAT4 ,"PMSTAT4"}, + {XDM_PERF_PMSTAT5 ,"PMSTAT5"}, + {XDM_PERF_PMSTAT6 ,"PMSTAT6"}, + {XDM_PERF_PMSTAT7 ,"PMSTAT7"}, + + {XDM_MISC_PWRCTL ,"PWRCTL" }, + {XDM_MISC_PWRSTAT ,"PWRSTAT" }, + {XDM_MISC_ERISTAT ,"ERISTAT" }, + {XDM_MISC_DATETIME ,"DATETIME"}, + {XDM_MISC_UBID ,"UBID" }, + {XDM_MISC_CID ,"CID" }, + + {XDM_CS_ITCTRL ,"ITCTRL" }, + {XDM_CS_CLAIMSET ,"CLAIMSET" }, + {XDM_CS_CLAIMCLR ,"CLAIMCLR" }, + {XDM_CS_LOCK_ACCESS ,"LOCK_ACCESS"}, + {XDM_CS_LOCK_STATUS ,"LOCK_STATUS"}, + {XDM_CS_AUTH_STATUS ,"AUTH_STATUS"}, + {XDM_CS_DEV_ID ,"DEV_ID" }, + {XDM_CS_DEV_TYPE ,"DEV_TYPE" }, + {XDM_CS_PER_ID4 ,"PER_ID4" }, + {XDM_CS_PER_ID5 ,"PER_ID5" }, + {XDM_CS_PER_ID6 ,"PER_ID6" }, + {XDM_CS_PER_ID7 ,"PER_ID7" }, + {XDM_CS_PER_ID0 ,"PER_ID0" }, + {XDM_CS_PER_ID1 ,"PER_ID1" }, + {XDM_CS_PER_ID2 ,"PER_ID2" }, + {XDM_CS_PER_ID3 ,"PER_ID3" }, + {XDM_CS_COMP_ID0 ,"COMP_ID0" }, + {XDM_CS_COMP_ID1 ,"COMP_ID1" }, + {XDM_CS_COMP_ID2 ,"COMP_ID2" }, + {XDM_CS_COMP_ID3 ,"COMP_ID3" }, + {-1 ,"???" }, +}; +#endif + +#endif + +#endif /* _XDM_REGS_H_ */ diff --git a/tools/sdk/include/esp32/xtensa/xmon.h b/tools/sdk/include/esp32/xtensa/xmon.h new file mode 100755 index 00000000..12a757a2 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/xmon.h @@ -0,0 +1,97 @@ +/* xmon.h - XMON definitions + * + * $Id: //depot/rel/Eaglenest/Xtensa/OS/xmon/xmon.h#3 $ + * + * Copyright (c) 2001-2013 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef __H_XMON +#define __H_XMON + +/* Default GDB packet size */ +#define GDB_PKT_SIZE 4096 + +/*XMON signals */ +#define XMON_SIGINT 2 /*target was interrupted */ +#define XMON_SIGILL 4 /*illegal instruction */ +#define XMON_SIGTRAP 5 /*general exception */ +#define XMON_SIGSEGV 11 /*page faults */ + + +/* Type of log message from XMON to the application */ +typedef enum { + XMON_LOG, + XMON_TRACE, + XMON_ERR, + XMON_APP, + XMON_GDB +} xmon_log_t; + +/* Return value type for xmon_proc() (see below) */ +typedef enum { + XMON_GDB_PEND, + XMON_GDB_PKT, + XMON_NOT_GDB +} xmon_gdb_pkt_t; + +#ifdef _cplusplus +extern "C" { +#endif + +/* + * THE FOLLOWING ROUTINES ARE USED BY USER + */ +extern int _xmon_init(char* gdbBuf, int gdbPktSize, + void(*xlog)(xmon_log_t type, const char* str)); +//Initialize GDB communication and logging to the main app. +//For the logging to work, xlog function needs to be provided. +//gdbBuf - pointer to a buffer XMON can use to comm. with GDB +//gdbPktSize - Size of the allocated buffer for GDB communication. +//xlog - logger handle. + + +extern void _xmon_close(void); +//Main application can detach from xmon at any time + + +extern xmon_gdb_pkt_t _xmon_proc(char); +// Give character to XMON to check if GDB message +// Application is supposed to accumulate all the +// character in case the recognition fails and chars +// have to be sent to the original handler +// Return: XMON_GDB_PEND - send me more chars +// XMON_GDB_PKT - GDB message confirmed, C) not +// XMON_NOT_GDB - not GDB message + + +/* + * THE FOLLOWING ROUTINES NEED TO BE PROVIDED BY USER + */ +extern int _xmon_in(); // wait for character from GDB +extern void _xmon_out(char); // output a character to GDB +extern int _xmon_flush(void); // flush output characters + +#ifdef _cplusplus +} +#endif + +#endif diff --git a/tools/sdk/include/esp32/xtensa/xmp-library.h b/tools/sdk/include/esp32/xtensa/xmp-library.h new file mode 100755 index 00000000..62427207 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/xmp-library.h @@ -0,0 +1,789 @@ +/* Customer ID=11656; Build=0x5f626; Copyright (c) 2008-2009 by Tensilica Inc. ALL RIGHTS RESERVED. + These coded instructions, statements, and computer programs are the + copyrighted works and confidential proprietary information of Tensilica Inc. + They may not be modified, copied, reproduced, distributed, or disclosed to + third parties in any manner, medium, or form, in whole or in part, without + the prior written consent of Tensilica Inc. */ + +#ifndef _XMP_LIBRARY_H +#define _XMP_LIBRARY_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#if XCHAL_HAVE_RELEASE_SYNC +#include +#endif +#if XCHAL_HAVE_EXTERN_REGS +#include +#endif +#include +#include + +#include "xtensa/system/mpsystem.h" + +/* + W A R N I N G: + + xmp library clients should treat all data structures in this file + as opaque. They are only public to enable users to declare them + statically. +*/ + + +/* ------------------------------------------------------------------------- + When using XMP on cache-incoherent systems, these macros are helpful + to ensure that you are not reading stale data, and to ensure that + the data you write makes it all the way back to main memory. + */ + +#if !XCHAL_DCACHE_IS_COHERENT +#define XMP_WRITE_BACK_ELEMENT(x) xthal_dcache_region_writeback((void *)x, sizeof(*x)) +#define XMP_INVALIDATE_ELEMENT(x) xthal_dcache_region_invalidate((void *)x, sizeof(*x)) +#define XMP_WRITE_BACK_INVALIDATE_ELEMENT(x) xthal_dcache_region_writeback_inv((void *)x, sizeof(*x)) +#define XMP_WRITE_BACK_ARRAY(x) xthal_dcache_region_writeback((void *)x, sizeof(x)) +#define XMP_INVALIDATE_ARRAY(x) xthal_dcache_region_invalidate((void *)x, sizeof(x)) +#define XMP_WRITE_BACK_INVALIDATE_ARRAY(x) xthal_dcache_region_writeback_inv((void *)x, sizeof(x)) +#define XMP_WRITE_BACK_ARRAY_ELEMENTS(x, num_elements) xthal_dcache_region_writeback((void *)x, sizeof(*x) * num_elements) +#define XMP_INVALIDATE_ARRAY_ELEMENTS(x, num_elements) xthal_dcache_region_invalidate((void *)x, sizeof(*x) * num_elements) +#define XMP_WRITE_BACK_INVALIDATE_ARRAY_ELEMENTS(x, num_elements) xthal_dcache_region_writeback_inv((void *)x, sizeof(*x) * num_elements) +#else +#define XMP_WRITE_BACK_ELEMENT(x) +#define XMP_INVALIDATE_ELEMENT(x) +#define XMP_WRITE_BACK_INVALIDATE_ELEMENT(x) +#define XMP_WRITE_BACK_ARRAY(x) +#define XMP_INVALIDATE_ARRAY(x) +#define XMP_WRITE_BACK_INVALIDATE_ARRAY(x) +#define XMP_WRITE_BACK_ARRAY_ELEMENTS(x, num_elements) +#define XMP_INVALIDATE_ARRAY_ELEMENTS(x, num_elements) +#define XMP_WRITE_BACK_INVALIDATE_ARRAY_ELEMENTS(x, num_elements) +#endif + +/* ------------------------------------------------------------------------- + Initialization, error codes, constants and house-keeping + + Every core should call xmp_init with the number of cores in the + system. + + xmp_init should be called before you use any global synchronization + primitive or shared data. + + Further, before you use a dynamically allocated synchronization + primitives, you need to both initialize it by calling the + xmp_*_init function, and you need to have called xmp_init, which + sets up interrupt handlers and interrupt routing. + + The second parameter sets the interprocessor interrupt + routing. Passing zero instructs the library to use the default + routing, which will be suitable for most users. + +*/ + +extern void xmp_init (int num_cores, unsigned int interrupt_routing); + + +/* If you want finer-grained control than that provided by xmp_init, + you can the functions below individually--however, this is more + inconvenient and requires greater understanding of the library's + internals. Don't use them directly unless you have a good reason. +*/ + +extern void xmp_unpack_shared (void); +extern void xmp_route_interrupts (unsigned int routing); + +#if XCHAL_HAVE_MP_INTERRUPTS +extern void xmp_enable_ipi_interrupts (void); + +/* Turn off certain things enabled by xmp_init */ +extern void xmp_disable_ipi_interrupts (void); +#endif + +extern void xmp_end (void); + +/* Only valid after xmp_init. */ +extern int xmp_num_cores (void); + +/* How many cycles should a core wait before rechecking a + synchronization variable? Higher values will reduce memory + transactions, but will also result in higher latency in returning + from synchronization. +*/ +extern void xmp_spin_wait_set_cycles (unsigned int limit); + +/* If you would prefer to provide your own spin wait function, + to go to sleep, etc. Declare a function of this type, then call + this function. */ +typedef void (*xmp_spin_wait_function_t)(void); +extern void xmp_spin_wait_set_function (xmp_spin_wait_function_t func); +extern void xmp_spin(void); + +#define XMP_NO_OWNER 0x07 +#define XMP_MUTEX_DESTROYED 0xFE +#define XMP_ERROR_FATAL 0xFD + +#define XMP_MAX_CORES 0x4 + + +static inline unsigned int xmp_prid (void) +{ +#if XCHAL_HAVE_PRID + return XT_RSR_PRID() & 0xFF; +#else + return 0; +#endif +} + + +/* ------------------------------------------------------------------------- + Tracing + + A core must set a trace_file if it wants any synchronization + tracing to occur. Sharing file descriptors among cores is very + messy, so don't do it. This, unfortunately, means that two cores + contending for a mutex are not able to trace to the same file. + + Any object (except the atomic integer) can have tracing off or on. +*/ + +extern void xmp_set_trace_file (FILE * file); +extern void xmp_trace (const char * fmt, ...); + + +/* ------------------------------------------------------------------------- + Memory Allocation Functions. + + These do what you would expect, only from shared memory instead of + private memory. +*/ + +#if XCHAL_DCACHE_IS_COHERENT +extern void * xmp_malloc (size_t size); +extern void * xmp_calloc (size_t nmemb, size_t size); +extern void xmp_free (void * ptr); +#endif +extern void * xmp_sbrk(int size); + +/* ------------------------------------------------------------------------- + xmp_atomic_int_t + + The most basic synchronization primitive in the xmp library. + Atomic ints are sharable among processors, and even interrupt + levels on the same processor. However, their semantics are fairly + rudimentary. All other primitives are based on these, therefore, + changing this implementation affects all other primitives. + +*/ + +typedef unsigned int xmp_atomic_int_t; + +static inline xmp_atomic_int_t +xmp_coherent_l32ai(xmp_atomic_int_t * address) +{ + XMP_INVALIDATE_ELEMENT (address); + return XT_L32AI(address, 0); +} + +static inline void +xmp_coherent_s32ri(xmp_atomic_int_t value, xmp_atomic_int_t * address) +{ + XT_S32RI (value, address, 0); + XMP_WRITE_BACK_ELEMENT (address); +} + +#define XMP_ATOMIC_INT_INITIALIZER(value) (value) + +/* xmp_atomic_int_init - Initialize an int prior to use + + Nonsynchronizing, Nonblocking + + Usage: + value - initial value + integer - points to an uninitialized integer + + On exit: + initialized to given value + + Errors: none +*/ + +static inline void +xmp_atomic_int_init (xmp_atomic_int_t * integer, int value) +{ + xmp_coherent_s32ri (value, integer); +} + + +/* xmp_atomic_int_value - Read the value + + Nonsynchronizing, Nonblocking + + Usage: + integer - points to an int + + Returns: + the value +*/ + +static inline int +xmp_atomic_int_value (xmp_atomic_int_t * integer) +{ + return xmp_coherent_l32ai (integer); +} + + +/* xmp_atomic_int_conditional_increment - Conditionally increment integer + + Synchronizing, nonblocking + + Usage: + integer - points to an initialized integer + amount - how much to increment + prev - believed value of the integer + eg: prev = xmp_atomic_int_value (integer); + success = xmp_atomic_int_increment (integer, 1, prev); + + Returns: current value of integer - user should check if it matches + the previous value of the integer. If it does, then the update + was successful. + +*/ + +#define USE_ASSEMBLY_IMPLEMENTATION 0 + +static inline int +xmp_atomic_int_conditional_increment (xmp_atomic_int_t * integer, int amount, int prev) +{ + int val; + int saved; + +#if USE_ASSEMBLY_IMPLEMENTATION + /* %0 = prev + %1 = saved + %2 = atomic integer pointer + %3 = amount + */ + + asm volatile ("wsr.scompare1 %0\n" + "mov %1, %0\n" + "add %0, %0, %3\n" + "s32c1i %0, %2, 0\n" + : "+&a" (prev), "+&a"(saved) : "a" (integer), "a" (amount)); + + return prev; + +#else + + XT_WSR_SCOMPARE1 (prev); + val = prev + amount; + saved = val; + XT_S32C1I (val, integer, 0); + + return val; +#endif +} + + +/* xmp_atomic_int_increment - Increment integer + + Synchronizing, blocking + + Usage: + integer - points to an initialized integer + amount - how much to increment + + Returns: new value of integer + +*/ + +static inline int +xmp_atomic_int_increment (xmp_atomic_int_t * integer, int amount) +{ + int val; + int saved; +#if USE_ASSEMBLY_IMPLEMENTATION + /* %0 = val + %1 = saved + %2 = atomic integer pointer + %3 = amount + */ + + asm volatile ("l32ai %0, %2, 0\n" + "1:\n" + "wsr.scompare1 %0\n" + "mov %1, %0\n" + "add %0, %0, %3\n" + "s32c1i %0, %2, 0\n" + "bne %0, %1, 1b\n" + : "+&a" (val), "+&a"(saved) : "a" (integer), "a" (amount)); +#else + /* Accurately naming "val" is tricky. Sometimes it will be what we + want to be the new value, but sometimes it contains the value + that is currently at the location. */ + + /* Load location's current value */ + val = xmp_coherent_l32ai (integer); + + do { + XT_WSR_SCOMPARE1 (val); + saved = val; + /* Change it to what we would like to store there--"new_val" */ + val = val + amount; + /* Possibly store new_val, but reload location's current value no + matter what. */ + XT_S32C1I (val, integer, 0); + if (val != saved) + xmp_spin(); + } while (val != saved); + +#endif + return val + amount; +} + + +/* xmp_atomic_int_conditional_set - Set the value of an atomic integer + + Synchronizing, nonblocking + + Usage: + integer - points to an initialized integer + from - believed value of the integer + eg: prev = xmp_atomic_int_value (integer); + success = xmp_atomic_int_conditional_set (integer, 1, prev); + to - new value + + Returns: current value of integer - user should check if it matches + the previous value of the integer. If it does, then the update + was successful. + +*/ + +static inline int +xmp_atomic_int_conditional_set (xmp_atomic_int_t * integer, int from, int to) +{ + int val; + + /* Don't even try to update if the integer's value isn't what we + think it should be. This prevents acquiring this cache-line for + writing and therefore prevents bus transactions when various + cores contend. */ + val = xmp_coherent_l32ai(integer); + if (val == from) { + XT_WSR_SCOMPARE1 (from); + val = to; + /* Possibly store to, but reload location's current value no + matter what. */ + XT_S32C1I (val, integer, 0); + } + return val; +} + + +/* Macros to implement trivial spin locks. These are very primitive, but + can be useful when you don't need the higher-overhead synchronization. + + To use an xmp_atomic_int_t as a trivial spin lock, you should + initialize it to zero first. +*/ + +#define XMP_SIMPLE_SPINLOCK_ACQUIRE(atomic_int_ptr) \ + { while (xmp_atomic_int_conditional_set (atomic_int_ptr, 0, xmp_prid() + 1) != 0) \ + xmp_spin(); } +#define XMP_SIMPLE_SPINLOCK_RELEASE(atomic_int_ptr) \ + { while (xmp_atomic_int_conditional_set (atomic_int_ptr, xmp_prid() + 1, 0) != xmp_prid() + 1) \ + xmp_spin(); } + +#define XMP_SIMPLE_SPINLOCK_OWNER(atomic_int_ptr) (xmp_atomic_int_value(atomic_int_ptr) - 1) + + +/* ------------------------------------------------------------------------- + xmp_mutex_t - An even higher-level data structure to enforce + mutual exclusion between cores. A core which waits on a mutex might + sleep with a waiti and be interrupted by an interrupt. + + Mutexes can be normal or recursive. For a normal mutex, a core + attempting to acquire a mutex it already holds will result in + deadlock. For a recursive mutex, a core will succeed in acquiring a + mutex it already holds, and must release it as many times as it + acquired it. + + Mutexes are not sharable between interrupt levels--because + ownership is tracked by core, not thread. + + Like all xmp data structures, an object of type xmp_mutex_t + should be treated by the programmer as opaque. They are only + public in this header file to allow them to be declared statically. + + For configurations with 16-byte cache lines, this has the most + frequently used and changed data in the first line. + +*/ + +#if XCHAL_DCACHE_IS_COHERENT +typedef struct xmp_mutex_t { + xmp_atomic_int_t qlock; + unsigned int qhead; + unsigned int qtail; + unsigned char queue[XMP_MAX_CORES]; + unsigned short held; + + unsigned char owner; + unsigned char recursive : 1; + unsigned char trace : 1; + unsigned char system : 1; + unsigned char unused : 5; + const char * name; +} xmp_mutex_t __attribute__ ((aligned (XMP_MAX_DCACHE_LINESIZE))); + + +#define XMP_MUTEX_INITIALIZER(name) \ + { 0, 0, -1, {XMP_NO_OWNER, XMP_NO_OWNER, XMP_NO_OWNER, XMP_NO_OWNER}, \ + 0, XMP_NO_OWNER, XMP_MUTEX_FLAG_NORMAL, 0, 0, 0, name } + +#define XMP_RECURSIVE_MUTEX_INITIALIZER(name) \ + { 0, 0, -1, {XMP_NO_OWNER, XMP_NO_OWNER, XMP_NO_OWNER, XMP_NO_OWNER}, \ + 0, XMP_NO_OWNER, XMP_MUTEX_FLAG_RECURSIVE, 0, 0, 0, name } + +#define XMP_MUTEX_FLAG_NORMAL 0 +#define XMP_MUTEX_FLAG_RECURSIVE 1 + +#define XMP_MUTEX_ACQUIRE_FAILED -1 +#define XMP_MUTEX_ERROR_DESTROY_OWNED -2 +#define XMP_MUTEX_ERROR_NOT_OWNED -3 +#define XMP_MUTEX_ERROR_ALREADY_OWNED -4 + +/* + xmp_mutex_init + + Nonsynchronizing + Nonblocking + + Usage: + mutex - points to an uninitialized mutex + name - name if you want one, NULL if not. + recursive - use recursive semantices + + Returns + zero on success (always succeeds) + +*/ + +extern int xmp_mutex_init (xmp_mutex_t * mutex, + const char * name, + unsigned int recursive); + +/* + int xmp_mutex_destroy (xmp_mutex_t * mutex); + + Synchronizing - will fail if mutex is held by anyone -- including + current processor + Nonblocking + + Usage: + mutex - points to a mutex + + Returns + zero on success + non-zero if mutex is held +*/ + +extern int xmp_mutex_destroy (xmp_mutex_t * mutex); + + +/* + xmp_mutex_lock -- Synchronizing + xmp_mutex_trylock + + Usage: + mutex - points to a mutex + + Returns + zero on success +*/ + +extern int xmp_mutex_lock (xmp_mutex_t * mutex); +extern int xmp_mutex_trylock (xmp_mutex_t * mutex); + + +/* + xmp_mutex_unlock + + Synchronizing + Nonblocking + + Usage: + mutex - points to a mutex + + Returns + zero on success - mutex is released + non-zero on failure - mutex is owned by another core + - prid of processor that does own it + note that by the time this function + returns, the owner of the core may + have changed. +*/ + +extern int xmp_mutex_unlock (xmp_mutex_t * mutex); + + +/* + xmp_mutex_name + + Nonsynchronizing + Nonblocking + + Usage: + mutex - points to a mutex + + Returns the name of the given mutex, which may be NULL. + +*/ + +const char * xmp_mutex_name (const xmp_mutex_t * mutex); + + +/* + xmp_mutex_trace_on + xmp_mutex_trace_off + + Nonsynchronizing + Nonblocking + + Turn off and on tracing for the mutex. + + These functions are only present in the debug version of the library. +*/ + +extern void xmp_mutex_trace_on (xmp_mutex_t * mutex); +extern void xmp_mutex_trace_off (xmp_mutex_t * mutex); + + +/* ------------------------------------------------------------------------- + xmp_condition_t + + Condition Variables following Mesa semantics. + + Condition variables are not sharable among interrupt levels. + +*/ + + +typedef struct xmp_condition_t { + unsigned int qhead; + unsigned int qtail; + unsigned char queue[XMP_MAX_CORES]; + unsigned int waiting[XMP_MAX_CORES]; + + unsigned char trace : 1; + unsigned char unused : 7; + const char * name; +} xmp_condition_t __attribute__ ((aligned (XMP_MAX_DCACHE_LINESIZE))); + + +#define XMP_CONDITION_INITIALIZER(name) \ + { 0, -1, {XMP_NO_OWNER, XMP_NO_OWNER, XMP_NO_OWNER, XMP_NO_OWNER}, \ + {0, 0, 0, 0}, 0, 0, name} + + +/* xmp_condition_init - Initialize a condition variable + + Nonsynchronizing, Nonblocking + + Usage: + condition - pointer to an xmp_condition_t + + On exit: + condition initialized + + Errors: none +*/ + +extern int xmp_condition_init (xmp_condition_t * condition, + const char * name); +extern int xmp_condition_destroy (xmp_condition_t * condition); + + +/* xmp_condition_wait - Wait for a condition variable + + Synchronizing, blocking + + Usage: + condition - pointer to an xmp_condition_t + mutex - pointer to an xmp_mutex_t already acquired by the calling + process + + Errors: if the mutex isn't held by this core +*/ + +extern int xmp_condition_wait (xmp_condition_t * condition, + xmp_mutex_t * mutex); + +/* xmp_condition_signal + + - Signal the first (if any) core waiting on a condition variable + + You must hold the mutex you passed to xmp_condition_wait before + calling this function. + + Synchronizing, nonblocking + + Usage: + condition - pointer to an xmp_condition_t + + Errors: none +*/ + +extern int xmp_condition_signal (xmp_condition_t * condition); + + +/* xmp_condition_broadcast + + - Signal all cores waiting on a condition variable + + Synchronizing, nonblocking + + You must hold the mutex you passed to xmp_condition_wait before + calling this function. + + Usage: + condition - pointer to an xmp_condition_t + + Errors: none +*/ + +extern int xmp_condition_broadcast (xmp_condition_t * condition); + + +static inline const char * xmp_condition_name (const xmp_condition_t * condition) +{ + return condition->name; +} + +/* + xmp_condition_trace_on + xmp_condition_trace_off + + Nonsynchronizing + Nonblocking + + Turn off and on statistics and tracing for the condition. For + tracing you must also set a trace file for the core. + + These functions are only present in the debug-version of the library. +*/ + +extern void xmp_condition_trace_on (xmp_condition_t * condition); +extern void xmp_condition_trace_off (xmp_condition_t * condition); + +#endif /* XCHAL_DCACHE_IS_COHERENT */ + +/* ------------------------------------------------------------------------- + xmp_barrier_t + + Classic barriers that stop any core from continuing until a + specified number of cores reach that point. Once the barrier allows + cores through, the barrier is reset and will stop cores from + progressing again. + + Barriers are not sharable among interrupt levels. + +*/ + + +typedef struct xmp_barrier_t +{ + xmp_atomic_int_t count; + xmp_atomic_int_t state; + xmp_atomic_int_t sleeping; + unsigned short num_cores; + unsigned short trace : 1; + unsigned short system : 1; + const char * name; +} xmp_barrier_t __attribute__ ((aligned (XMP_MAX_DCACHE_LINESIZE))); + +#define XMP_BARRIER_INITIALIZER(number, name) \ + { 0, 0, 0, number, 0, 0, name } + + +/* xmp_barrier_init - Initialize a barrier + + Nonsynchronizing, Nonblocking + + Usage: + barrier - pointer to an xmp_barrier_t + num_cores - number of cores needed to arrive at the + barrier before any are allowed through + On exit: + barrier initialized + + Always returns zero. + + Errors: none +*/ + +extern int xmp_barrier_init (xmp_barrier_t * barrier, int num_cores, + const char * name); + + +/* xmp_barrier_wait - Wait on a barrier + + Nonsynchronizing, Nonblocking + + Usage: + barrier - pointer to an xmp_barrier_t + On exit: + Enough cores (as determined at the barrier's initialization) + have reached the barrier. + + Errors: none +*/ + +extern int xmp_barrier_wait (xmp_barrier_t * barrier); + + +static inline const char * xmp_barrier_name (const xmp_barrier_t * barrier) +{ + return barrier->name; +} + + +/* + xmp_barrier_trace_on + xmp_barrier_trace_off + + Nonsynchronizing + Nonblocking + + Turn on and off tracing for the barrier. For + tracing you must also set a trace file for the core. + + These functions are only present in the debug-version of the library. +*/ + +extern void xmp_barrier_trace_on (xmp_barrier_t * barrier); +extern void xmp_barrier_trace_off (xmp_barrier_t * barrier); + + +/* ------------------------------------------------------------------------- + Portions of the library that are internal, but belong here for + convenience. +*/ + +extern xmp_atomic_int_t _ResetSync; + +static inline void +xmp_initial_sync (int num_cores) +{ + xmp_atomic_int_increment (&_ResetSync, 1); + while (xmp_coherent_l32ai (&_ResetSync) != num_cores) + xmp_spin (); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _XMP_LIBRARY_H */ diff --git a/tools/sdk/include/esp32/xtensa/xos.h b/tools/sdk/include/esp32/xtensa/xos.h new file mode 100755 index 00000000..883a9c97 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/xos.h @@ -0,0 +1,524 @@ +/** @file */ + +// xos.h - XOS API interface and data structures visible to user code. + +// Copyright (c) 2003-2015 Cadence Design Systems, Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + +#ifndef __XOS_H__ +#define __XOS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +#include "xos_types.h" + +#include +#if XCHAL_HAVE_INTERRUPTS +#include +#include +#endif + +#include "xos_common.h" +#include "xos_errors.h" +#include "xos_regaccess.h" + + +//----------------------------------------------------------------------------- +// Convert x into a literal string. +//----------------------------------------------------------------------------- +#define _XOS_STR(x) __XOS_STR(x) +#define __XOS_STR(x) #x + + +//----------------------------------------------------------------------------- +// XOS version. +//----------------------------------------------------------------------------- +#define XOS_VERSION_MAJOR 1 +#define XOS_VERSION_MINOR 10 +#define XOS_VERSION_STRING "1.10" ///< XOS version string. + + +//----------------------------------------------------------------------------- +// Runtime error handling. +//----------------------------------------------------------------------------- + + +//----------------------------------------------------------------------------- +/// +/// Reports a fatal error and halts XOS operation, i.e. halts the system. This +/// function will call a user-registered error handler (if one has been set) +/// and then halt the system. The user handler may do system-specific things +/// such as record the error reason in nonvolatile memory etc. +/// +/// \param errcode Error code. May be any user defined value < 0. +/// Values >=0 are reserved for use by the system. +/// +/// \param errmsg Optional text string describing the error. +/// +/// \return This function does not return. +/// +//----------------------------------------------------------------------------- +void +xos_fatal_error(int32_t errcode, const char * errmsg); + + +#if XOS_DEBUG + +// Do not call directly. +void +xos_assert(const char * file, int32_t line); + +//----------------------------------------------------------------------------- +/// +/// Check condition and fail if condition expression is false. +/// In debug builds, an assertion failure will cause a fatal error to be +/// reported. In non-debug builds, assertions are compiled out. +/// +/// NOTE: Remember that any code in XOS_ASSERT() statements gets compiled out +/// for non-debug builds. +/// +//----------------------------------------------------------------------------- + +#define XOS_ASSERT(expr) if ((expr) == 0) xos_assert(__FILE__, __LINE__) + +#else + +#define XOS_ASSERT(expr) + +#endif + + +//----------------------------------------------------------------------------- +/// +/// Interrupt handler function pointer type. +/// +//----------------------------------------------------------------------------- +typedef void (XosIntFunc)(void * arg); + +//----------------------------------------------------------------------------- +/// +/// Print handler function pointer type. +/// +//----------------------------------------------------------------------------- +typedef int32_t (XosPrintFunc)(void * arg, const char * fmt, ...); + +//----------------------------------------------------------------------------- +/// +/// Fatal error handler function pointer type. +/// +//----------------------------------------------------------------------------- +typedef void (XosFatalErrFunc)(int32_t errcode, const char * errmsg); + +//----------------------------------------------------------------------------- +/// +/// Exception handler function pointer type. +/// +//----------------------------------------------------------------------------- +typedef void (XosExcHandlerFunc)(XosExcFrame * frame); + + +//----------------------------------------------------------------------------- +/// +/// Install a user defined exception handler for the specified exception type. +/// This will override the default XOS exception handler. The handler is a C +/// function that is passed one parameter -- a pointer to the exception frame. +/// The exception frame is allocated on the stack of the thread that caused the +/// exception, and contains saved state and exception information. For details +/// of the exception frame see the structure XosExcFrame. +/// +/// \param exc Exception type (number) to override. The exception +/// numbers are enumerated in . +/// +/// \param handler Pointer to handler function to be installed. +/// To revert to the default handler, pass NULL. +/// +/// \return Returns a pointer to previous handler installed, if any. +/// +//----------------------------------------------------------------------------- +XosExcHandlerFunc * +xos_register_exception_handler(int32_t exc, XosExcHandlerFunc * handler); + + +//----------------------------------------------------------------------------- +/// +/// Install a user defined fatal error handler. This function will be called if +/// a fatal error is reported either by user code or by XOS itself. It will be +/// passed the same arguments that are passed to xos_fatal_error(). +/// +/// The handler need not return. It should make minimal assumptions about the +/// state of the system. In particular, it should not assume that further XOS +/// system calls will succeed. +/// +/// \param handler Pointer to handler function to be installed. +/// +/// \return Returns a pointer to previous handler installed, if any. +/// +//----------------------------------------------------------------------------- +XosFatalErrFunc * +xos_register_fatal_error_handler(XosFatalErrFunc * handler); + + +#ifdef _XOS_INCLUDE_INTERNAL_ +# include "xos_internal.h" +#endif + + +#include "xos_thread.h" +#include "xos_timer.h" +#include "xos_cond.h" +#include "xos_event.h" +#include "xos_mutex.h" +#include "xos_msgq.h" +#include "xos_semaphore.h" +#include "xos_stopwatch.h" + + +//----------------------------------------------------------------------------- +/// +/// Register a handler function to call when interrupt "num" occurs. +/// +/// For level-triggered and timer interrupts, the handler function will have +/// to clear the source of the interrupt before returning, to avoid infinitely +/// retaking the interrupt. Edge-triggered and software interrupts are +/// automatically cleared by the OS interrupt dispatcher (see xos_handlers.S). +/// +/// \param num Xtensa internal interrupt number (0..31). To +/// refer to a specific external interrupt number +/// (BInterrupt pin), use HAL macro XCHAL_EXTINTx_NUM +/// where 'x' is the external number. +/// +/// \param handler Pointer to handler function. +/// +/// \param arg Argument passed to handler. +/// +/// \return Returns XOS_OK if successful, else error code. +/// +//----------------------------------------------------------------------------- +int32_t +xos_register_interrupt_handler(int32_t num, XosIntFunc * handler, void * arg); + + +//----------------------------------------------------------------------------- +/// +/// Unregister a handler function for interrupt "num". If no handler was +/// installed, this function will have no effect. +/// +/// \param num Xtensa internal interrupt number (0..31). To +/// refer to a specific external interrupt number +/// (BInterrupt pin), use HAL macro XCHAL_EXTINTx_NUM +/// where 'x' is the external number. +/// +/// \return Returns XOS_OK if successful, else error code. +/// +//----------------------------------------------------------------------------- +int32_t +xos_unregister_interrupt_handler(int32_t num); + + +//----------------------------------------------------------------------------- +/// +/// Register a high priority interrupt handler for interrupt level "level". +/// +/// Unlike low and medium priority interrupt handlers, high priority handlers +/// are not installed for a specific interrupt number, but for an interrupt +/// level. The level must be above XCHAL_EXCM_LEVEL. The handler function must +/// be written in assembly since C handlers are not supported for levels above +/// XCHAL_EXCM_LEVEL. The handler function must preserve all registers except +/// a0, and must return to the dispatcher via a "ret" instruction, not "rfi". +/// +/// NOTE: This method of dispatch takes a few cycles of overhead. If you wish +/// to save even these cycles, then you can define your own dispatch function +/// to override the built-in dispatcher. See xos_handlers.S for more details. +/// +/// \param level The interrupt level to be handled. +/// +/// \param handler Pointer to handler function. +/// +/// \return Returns XOS_OK if successful, else error code. +/// +//----------------------------------------------------------------------------- +int32_t +xos_register_hp_interrupt_handler(int32_t level, void * handler); + + +//----------------------------------------------------------------------------- +/// +/// Enable a specific interrupt, by interrupt number. +/// The state (enabled vs. disabled) of individual interrupts is global, i.e. +/// not associated with any specific thread. Depending on system options and +/// implementation, this state may be stored in one of two ways: +/// - directly in the INTENABLE register, or +/// - in a global variable (this is generally the case when INTENABLE is used +/// not just to control what interrupts are enabled globally, but also for +/// software interrupt prioritization within an interrupt level, effectively +/// providing finer grained levels; in this case XOS takes care to update +/// INTENABLE whenever either the global enabled-state variable or the +/// per-thread fine-grained-level variable change). +/// Thus it is best to never access the INTENABLE register directly. +/// +/// To modify thread-specific interrupt priority level, use one of: +/// - xos_set_int_pri_level() +/// - xos_restore_int_pri_level() +/// - xos_disable_interrupts() +/// - xos_restore_interrupts() +/// +/// NOTE: To refer to a specific external interrupt number (BInterrupt pin), +/// use HAL macro XCHAL_EXTINTx_NUM where 'x' is the external interrupt +/// number. For example, to enable external interrupt 3 (BInterrupt[3]), +/// you can use: +/// +/// xos_interrupt_enable( XCHAL_EXTINT3_NUM ); +/// +/// \param intnum Interrupt number to enable. Must range between 0-31. +/// +/// \return Returns nothing. +/// +//----------------------------------------------------------------------------- +void +xos_interrupt_enable(uint32_t intnum); + + +//----------------------------------------------------------------------------- +/// +/// Disable a specific individual interrupt, by interrupt number. +/// +/// This is the counterpart to xos_interrupt_enable(). See the description +/// of xos_interrupt_enable() for further comments and notes. +/// +/// \param intnum Interrupt number to disable. Must range between 0-31. +/// +/// \return Returns nothing. +/// +//----------------------------------------------------------------------------- +void +xos_interrupt_disable(uint32_t intnum); + + +//----------------------------------------------------------------------------- +/// +/// Get the CPU's current interrupt priority level. Interrupts at or below this +/// priority level are blocked. +/// +/// \return Returns the current IPL, ranging from 0 to XCHAL_NUM_INTLEVELS. +/// +//----------------------------------------------------------------------------- +static inline uint32_t +xos_get_int_pri_level(void) +{ +#if XCHAL_HAVE_INTERRUPTS + return XT_RSR_PS() & 0xF; +#else + return 0; +#endif +} + + +//----------------------------------------------------------------------------- +/// +/// Set the CPU's interrupt priority level to the specified level, but only if +/// the current IPL is below the one requested. This function will never cause +/// the interrupt priority level to be lowered from the current level. +/// Call this function to block interrupts at or below the specified priority +/// level. +/// +/// When setting the IPL temporarily (such as in a critical section), call +/// xos_set_int_pri_level(), execute the critical code section, and then call +/// xos_restore_int_pri_level(). +/// +/// The interrupt priority level is part of the thread context, so it is saved +/// and restored across context switches. To enable and disable individual +/// interrupts globally, use the functions xos_interrupt_enable() and +/// xos_interrupt_disable() instead. +/// +/// NOTE: It is usually not required to disable interrupts at a level higher +/// than that of the highest priority interrupt that interacts with the OS +/// (i.e. calls into XOS such that threads may be woken / blocked / +/// reprioritized / switched, or otherwise access XOS data structures). +/// In XOS, that maximum level is XOS_MAX_OS_INTLEVEL, which defaults to +/// XCHAL_EXCM_LEVEL. This may be modified by editing xos_params.h and +/// rebuilding XOS. +/// +/// \param level The new interrupt priority level (IPL). +/// +/// \return Returns a value that can be used to restore the previous +/// priority level by calling xos_restore_int_pri_level(). This +/// value should be treated as opaque by application code, and +/// should be passed unchanged to the restore function. +/// +//----------------------------------------------------------------------------- +__attribute__((always_inline)) +static inline uint32_t +xos_set_int_pri_level(uint32_t level) +{ +#if XCHAL_HAVE_INTERRUPTS +#pragma no_reorder + uint32_t ps = XT_RSR_PS(); + + if (level > (ps & 0xF)) { + level = (ps & ~0xF) | level; + XT_WSR_PS(level); + XT_RSYNC(); + } + + return ps; +#else + return 0; +#endif +} + + +//----------------------------------------------------------------------------- +/// +/// Restores the CPU to a previously saved interrupt priority level. This level +/// must have been obtained by calling xos_set_int_pri_level(). +/// +/// \param oldval Return value from xos_set_int_pri_level(). +/// +/// \return Returns nothing. +/// +//----------------------------------------------------------------------------- +__attribute__((always_inline)) +static inline void +xos_restore_int_pri_level(const uint32_t oldval) +{ +#if XCHAL_HAVE_INTERRUPTS +#pragma no_reorder + XT_WSR_PS(oldval); + XT_RSYNC(); +#else + // Nothing +#endif +} + + +//----------------------------------------------------------------------------- +/// +/// Disable all interrupts that can interact directly with the OS. This is a +/// convenience function, shorthand for setting the IPL to XOS_MAX_OS_INTLEVEL. +/// +/// Returns: A value that can be used to restore the previous priority level +/// by calling xos_restore_interrupts(). This value should be treated as +/// opaque by application code, and should be passed unchanged to the restore +/// function. +/// +//----------------------------------------------------------------------------- +static inline uint32_t +xos_disable_interrupts(void) +{ + return xos_set_int_pri_level(XOS_MAX_OS_INTLEVEL); +} + + +//----------------------------------------------------------------------------- +/// +/// Restore the CPU's previously saved interrupt status. This is a convenience +/// function, the counterpart to xos_disable_interrupts(). +/// +/// \return rval Return value from xos_disable_interrupts(). +/// +/// \return Returns nothing. +/// +//----------------------------------------------------------------------------- +static inline void +xos_restore_interrupts(uint32_t rval) +{ + xos_restore_int_pri_level(rval); +} + + +#ifdef _XOS_INCLUDE_INTERNAL_ + +//----------------------------------------------------------------------------- +// Enter an OS critical section, i.e. get exclusive access to OS critical +// state and data structures. Code that manipulates the state of OS objects +// or modifies internal OS state must call this function first, to ensure +// that it has exclusive access. On a single-core system, this is equivalent +// to blocking all interrupts that can interact directly with the OS, i.e. +// all interrupts at or below XOS_MAX_OS_INTLEVEL. In a multi-core system +// this is likely to be implemented differently to achieve the same effect. +// +// Returns: A value that is to be used to restore the state of the CPU when +// exiting the critical section. This must be treated as opaque and passed +// unmodified to xos_critical_exit(). +// +// NOTE: This function is meant for use in OS code, not in applications. +//----------------------------------------------------------------------------- +__attribute__((always_inline)) +static inline uint32_t +xos_critical_enter(void) +{ +#if XCHAL_HAVE_INTERRUPTS + // This function cannot be called by high-level interrupt handlers, + // i.e. it can never be called with intlevel > XOS_MAX_OS_INTLEVEL. + // So, we do not need to check current intlevel because we will not + // ever be lowering it by setting it to XOS_MAX_OS_INTLEVEL. + // NOTE: sync after RSIL not needed. + return XT_RSIL(XOS_MAX_OS_INTLEVEL); +#else + return 0; +#endif +} + + +//----------------------------------------------------------------------------- +// Exit an OS critical section and restore CPU state. See the documentation +// for xos_critical_enter(). +// +// cflags Return value from xos_critical_enter(). +// Must be treated as an opaque value. +// +// Returns: Nothing. +// +// NOTE: This function is meant for use in OS code, not in applications. +//----------------------------------------------------------------------------- +__attribute__((always_inline)) +static inline void +xos_critical_exit(uint32_t cflags) +{ + xos_restore_int_pri_level(cflags); +} + +#endif // _XOS_INCLUDE_INTERNAL_ + + +// This file uses things defined above +#include "xos_syslog.h" + + +// Misc + +//----------------------------------------------------------------------------- +// Helper function to list all threads in system. Useful for debug. +//----------------------------------------------------------------------------- +void +xos_display_threads(void * arg, XosPrintFunc * print_fn); + + +#ifdef __cplusplus +} +#endif + +#endif // __XOS_H__ + diff --git a/tools/sdk/include/esp32/xtensa/xos_common.h b/tools/sdk/include/esp32/xtensa/xos_common.h new file mode 100755 index 00000000..647cb7f4 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/xos_common.h @@ -0,0 +1,362 @@ + +// xos_common.h - Macros and definitions common to C and assembly code. + +// Copyright (c) 2003-2015 Cadence Design Systems, Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + +#ifndef __XOS_COMMON_H__ +#define __XOS_COMMON_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +#include +#include +#include + +#include "xos_params.h" + + +//----------------------------------------------------------------------------- +// Macros that help define structures for both C and assembler. +// These are somewhat different from the XTOS version in xtruntime-frames.h. +//----------------------------------------------------------------------------- +#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__) + +#define STRUCT_BEGIN .pushsection .text; .struct 0 +#define STRUCT_FIELD(ctype,size,asname,name) asname: .space size +#define STRUCT_AFIELD(ctype,size,asname,name,n) asname: .space (size)*(n) +#define STRUCT_END(sname) sname##Size:; .popsection + +#else + +#define STRUCT_BEGIN typedef struct { +#define STRUCT_FIELD(ctype,size,asname,name) ctype name; +#define STRUCT_AFIELD(ctype,size,asname,name,n) ctype name[n]; +#define STRUCT_END(sname) } sname; + +#endif //_ASMLANGUAGE || __ASSEMBLER__ + + +//----------------------------------------------------------------------------- +// Offsets relative to xos_globals. +//----------------------------------------------------------------------------- +#define XOS_INTLEVEL_MASK 0 // offset to the level mask +#define XOS_INTENABLE_MASK 4 // offset to the enable mask +#define XOS_CURR_THREADPTR 8 // offset to the current thread ptr +#define XOS_NEXT_THREADPTR 12 // offset to the next thread ptr +#define XOS_INTERRUPT_TABLE 16 // offset to the interrupt table + + +//----------------------------------------------------------------------------- +// Offsets for xos_interrupt_table[] entries. +//----------------------------------------------------------------------------- +#define XOS_INTTAB_HANDLER (XOS_INTERRUPT_TABLE+0) // ofs to interrupt handler +#define XOS_INTTAB_ARG (XOS_INTERRUPT_TABLE+4) // ofs to interrupt handler arg +#define XOS_INTTAB_PS (XOS_INTERRUPT_TABLE+8) // (hwpri) PS for interrupt level +#define XOS_INTTAB_LEVEL (XOS_INTERRUPT_TABLE+8) // (swpri) interrupt level (1..7) +#define XOS_INTTAB_PRI (XOS_INTERRUPT_TABLE+9) // (swpri) interrupt priority (0..255) +#define XOS_INTTAB_PRIMASK (XOS_INTERRUPT_TABLE+12) // (swpri) mask of higher pri. interrupts + + +//----------------------------------------------------------------------------- +// Exception/interrupt stack frame layout for a pre-empted thread +// tcb->resume_fn == &xos_resume_preempted_thread). +// Pointed to by thread->esf. Located just below thread's current stack ptr. +// Thread's a1 == thread->esf + XosExcFrameSize. +// NOTE: exception frame size is a multiple of 16. +//----------------------------------------------------------------------------- +STRUCT_BEGIN +STRUCT_AFIELD(long,4,FRAME_AREG,areg, 12) // a4-a15 (offsets 0 thru 44) + // (a1 is computed, a0,a2-a3 are in s32e range of a1) +//#if XCHAL_HAVE_LOOPS +STRUCT_FIELD (long,4,FRAME_LBEG,lbeg) +STRUCT_FIELD (long,4,FRAME_LEND,lend) +STRUCT_FIELD (long,4,FRAME_LCOUNT,lcount) +//#endif +//#if XCHAL_HAVE_MAC16 +STRUCT_FIELD (long,4,FRAME_ACCLO,acclo) +STRUCT_FIELD (char,1,FRAME_ACCHI,acchi) +//#endif +STRUCT_FIELD (char,1,FRAME_SAR,sar) +STRUCT_FIELD (short,2,FRAME_PAD0,pad0) // unused +STRUCT_FIELD (long,4,FRAME_EXCCAUSE,exccause) +STRUCT_FIELD (long,4,FRAME_EXCVADDR,excvaddr) +STRUCT_FIELD (long,4,FRAME_PAD1,pad1) // unused -- pad to make multiple of 16 bytes +STRUCT_FIELD (long,4,FRAME_PAD2,pad2) +STRUCT_FIELD (long,4,FRAME_PS,ps) // (XOS_FRAME_SIZE-44) in S32E range of end +STRUCT_FIELD (long,4,FRAME_PC,pc) // (XOS_FRAME_SIZE-40) in S32E range of end +STRUCT_FIELD (long,4,FRAME_A0,a0) +STRUCT_FIELD (long,4,FRAME_A2,a2) // (XOS_FRAME_SIZE-32) in S32E range of end +STRUCT_FIELD (long,4,FRAME_A3,a3) // (XOS_FRAME_SIZE-28) in S32E range of end +STRUCT_FIELD (long,4,FRAME_LEVELMASK,levelmask) // +STRUCT_FIELD (long,4,FRAME_NESTCHAIN,nestchain) // nested C function call chain ptr +// Caller's a0-a3 save area below SP. These fields MUST be the last ones in the +// struct so that they are guaranteed to be just under the original SP (before +// we allocate the exception frame). +STRUCT_AFIELD (long,4,FRAME_CWINSAVE,cwinsave, 4) // (XOS_FRAME_SIZE-16) +STRUCT_END(XosExcFrame) // NOTE: exception frame size is 128 + +#define FRAME_AR(x) (FRAME_AREG + x*4 - 16) + +#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__) +#define XOS_FRAME_SIZE XosExcFrameSize +#else +#define XOS_FRAME_SIZE sizeof(XosExcFrame) +#endif + + +//----------------------------------------------------------------------------- +// Stack frame layout for a cooperatively switched out thread +// (tcb->resume_fn == &xos_resume_cooperative_thread). +// Pointed to by thread->esf. This is a function frame. +// Thread's a1 == thread->esf. +//----------------------------------------------------------------------------- +STRUCT_BEGIN +STRUCT_FIELD (long,4,CFRAME_A0,a0) // return PC +STRUCT_FIELD (long,4,CFRAME_LEVELMASK,levelmask) +STRUCT_FIELD (long,4,CFRAME_PS,ps) +#ifdef __XTENSA_CALL0_ABI__ +STRUCT_FIELD (long,4,CFRAME_PAD0,pad0) +STRUCT_AFIELD(long,4,CFRAME_AREG,areg,4) // callee-saved regs a12-a15 +#endif +STRUCT_END(XosCoopFrame) + + +//----------------------------------------------------------------------------- +// Offsets into thread control block (must match xos_thread.h !!) +//----------------------------------------------------------------------------- +#define TCB_RESUME_FN 12 // ptr to thread resume asm sequence +#define TCB_STACK_ESF 16 // saved stack ptr (actually, ptr to ESF) +#define TCB_TIE_SAVE 20 // ptr to TIE save area +#define TCB_RETVALUE 24 // ptr to xos_block return value +#define TCB_STACK_END 36 // ptr to end of stack (thread's initial stack ptr) +#define TCB_STARTUP_ENTRY 40 // ptr to thread entry function +#define TCB_STARTUP_ARG 44 // ptr to thread entry function's arg +#define TCB_READY 48 // thread ready state (1 byte) +#define TCB_CLIB_PTR 108 // thread C lib context pointer + +#define TCB_RESUME_CCOUNT 116 // cycle count at last resume +#define TCB_CYCLE_COUNT 120 // number of cycles consumed +#define TCB_NORMAL_RESUMES 128 // number of cooperative/restart thread resumes +#define TCB_PREEMPT_RESUMES 132 // number of pre-emptive thread resumes + + +//----------------------------------------------------------------------------- +// Coprocessor state handling: +// The coprocessor state save area is allocated on the thread stack. The stack +// must be sized appropriately. Threads that do not use coprocessors need not +// allocate the storage area. +// +// Along with the save area for each coprocessor, two bitmasks with flags per +// coprocessor (laid out as in the CPENABLE reg) help manage context switching +// coprocessors as efficiently as possible: +// +// XT_CPENABLE +// The contents of a non-running thread's CPENABLE register. +// It represents the coprocessors owned (and whose state is still needed) +// by the thread. When a thread is preempted, its CPENABLE is saved here. +// When a thread solicits a context switch, its CPENABLE is cleared - the +// compiler has saved the (caller-saved) coprocessor state if needed. +// When a non-running thread loses ownership of a CP, its bit is cleared. +// When a thread runs, it's XT_CPENABLE is loaded into the CPENABLE reg. +// Avoids coprocessor exceptions when no change of ownership is needed. +// +// XT_CPSTORED +// A bitmask with the same layout as CPENABLE, a bit per coprocessor. +// Indicates whether the state of each coprocessor is saved in the state +// save area. When a thread enters the kernel, only the state of coprocs +// still enabled in CPENABLE is saved. When the coprocessor exception +// handler assigns ownership of a coprocessor to a thread, it restores +// the saved state only if this bit is set, and clears this bit. +// +// XT_CP_CS_ST +// A bitmask with the same layout as CPENABLE, a bit per co-processor. +// Indicates whether callee-saved state is saved in the state save area. +// Callee-saved state is saved by itself on a solicited context switch, +// and restored when needed by the coprocessor exception handler. +// Unsolicited switches will cause the entire coprocessor to be saved +// when necessary. +// +// XT_NCP_ASA +// Pointer to aligned save area for non-CP state. This is always filled +// in, even if there is no non-CP state to be saved. If there is no state +// to be saved then no space is actually allocated and this pointer is +// not used. +// +// XT_CP_ASA +// Pointer to aligned save area for coprocessor state. This is filled in +// only if coprocessor state is to be saved for the thread. Allows it to be +// aligned more than the overall save area (which might be stack-aligned +// or TCB-aligned). Especially relevant for Xtensa cores configured with a +// very large data path that requires alignment greater than 16 bytes (ABI +// stack alignment). +//----------------------------------------------------------------------------- + +#define ALIGNUP(n, val) (((val) + (n)-1) & -(n)) + +// Offsets of each coprocessor save area within the 'aligned save area'. +// The non-CP TIE state save area is at offset 0, so that it does not +// move around if some or all coprocessors are not to be saved. + +#define XT_NCP_SA 0 +#define XT_CP0_SA ALIGNUP(XCHAL_CP0_SA_ALIGN, XT_NCP_SA + XCHAL_NCP_SA_SIZE) +#define XT_CP1_SA ALIGNUP(XCHAL_CP1_SA_ALIGN, XT_CP0_SA + XCHAL_CP0_SA_SIZE) +#define XT_CP2_SA ALIGNUP(XCHAL_CP2_SA_ALIGN, XT_CP1_SA + XCHAL_CP1_SA_SIZE) +#define XT_CP3_SA ALIGNUP(XCHAL_CP3_SA_ALIGN, XT_CP2_SA + XCHAL_CP2_SA_SIZE) +#define XT_CP4_SA ALIGNUP(XCHAL_CP4_SA_ALIGN, XT_CP3_SA + XCHAL_CP3_SA_SIZE) +#define XT_CP5_SA ALIGNUP(XCHAL_CP5_SA_ALIGN, XT_CP4_SA + XCHAL_CP4_SA_SIZE) +#define XT_CP6_SA ALIGNUP(XCHAL_CP6_SA_ALIGN, XT_CP5_SA + XCHAL_CP5_SA_SIZE) +#define XT_CP7_SA ALIGNUP(XCHAL_CP7_SA_ALIGN, XT_CP6_SA + XCHAL_CP6_SA_SIZE) + +#define XT_TOT_SA_SIZE ALIGNUP(16, XT_CP7_SA + XCHAL_CP7_SA_SIZE) +#define XT_NCP_SA_SIZE XCHAL_NCP_SA_SIZE + +// Offsets within the overall save area + +#define XT_CPENABLE 0 // (2 bytes) coprocessors active for this thread +#define XT_CPSTORED 2 // (2 bytes) coprocessors saved for this thread +#define XT_CP_CS_ST 4 // (2 bytes) coprocessor callee-saved regs for this thread +#define XT_NCP_ASA 8 // (4 bytes) ptr to aligned save area for nonCP state +#define XT_CP_ASA 12 // (4 bytes) ptr to aligned save area for CP state + +// Overall size allows for dynamic alignment, make sure multiple of 4 bytes. +// XT_CP_SIZE - total space needed for all coprocessors + nonCP state + hdr +// XT_NCP_SIZE - total space needed for nonCP state + hdr + +#define XT_CP_SIZE ALIGNUP(4, (16 + XT_TOT_SA_SIZE + XCHAL_TOTAL_SA_ALIGN)) +#define XT_NCP_SIZE ALIGNUP(4, (16 + XT_NCP_SA_SIZE + XCHAL_TOTAL_SA_ALIGN)) + + +//----------------------------------------------------------------------------- +// Stack size computation. +// +// XOS_STACK_MIN_SIZE +// The minimum recommended stack size for any XOS thread. If you want to +// use a stack size smaller than this, you will have to verify that the +// smaller size will work under all operating conditions. +// +// XOS_STACK_MIN_SIZE_NO_CP +// The minimum recommended atack size for threads that will not use any +// coprocessor resources. No coprocessor state will be saved/restored +// for these threads. Non-CP TIE state will still be saved/restored. +// These threads must be created with the flag XOS_THREAD_NO_CP. +// +// XOS_STACK_EXTRA +// The amount of stack space used by the system to: +// - save coprocessor state +// - save non-coprocessor TIE state +// - allocate an interrupt/exception frame +// +// XOS_STACK_EXTRA_NO_CP +// The amount of stack space used by the system to: +// - save non-coprocessor TIE state +// - allocate an interrupt/exception frame +//----------------------------------------------------------------------------- + +#define XOS_STACK_EXTRA (XOS_FRAME_SIZE + XT_CP_SIZE) +#define XOS_STACK_EXTRA_NO_CP (XOS_FRAME_SIZE + XT_NCP_SIZE) + +#ifdef __XTENSA_CALL0_ABI__ +#define XOS_STACK_MIN_SIZE (XOS_STACK_EXTRA + 0x180) +#define XOS_STACK_MIN_SIZE_NO_CP (XOS_STACK_EXTRA_NO_CP + 0x180) +#else +#define XOS_STACK_MIN_SIZE (XOS_STACK_EXTRA + 0x200) +#define XOS_STACK_MIN_SIZE_NO_CP (XOS_STACK_EXTRA_NO_CP + 0x200) +#endif + + +//----------------------------------------------------------------------------- +// Items related to C library thread safety. +//----------------------------------------------------------------------------- +#if XOS_OPT_THREAD_SAFE_CLIB + +#if XSHAL_CLIB == XTHAL_CLIB_XCLIB + #if !defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__) + #include + #endif + #define CLIB_THREAD_STRUCT struct _reent xclib_reent + #define GLOBAL_CLIB_PTR _reent_ptr +#elif XSHAL_CLIB == XTHAL_CLIB_NEWLIB + #if !defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__) + #include + #endif + #define CLIB_THREAD_STRUCT struct _reent newlib_reent + #define GLOBAL_CLIB_PTR _impure_ptr +#else + #error The selected C runtime library is not thread safe. +#endif + +#endif // XOS_OPT_THREAD_SAFE_CLIB + + +//----------------------------------------------------------------------------- +// Check (MAX_OS_INTLEVEL,EXCM_LEVEL) +//----------------------------------------------------------------------------- +#if XOS_MAX_OS_INTLEVEL >= XCHAL_EXCM_LEVEL +# define XOS_MAX_OSEXCM_LEVEL XOS_MAX_OS_INTLEVEL +#else +# warning "XOS_MAX_OS_INTLEVEL was set below XCHAL_EXCM_LEVEL: this was never tested" +# define XOS_MAX_OSEXCM_LEVEL XCHAL_EXCM_LEVEL +#endif + + +//----------------------------------------------------------------------------- +// Detect if in interrupt context. +//----------------------------------------------------------------------------- +#if XCHAL_HAVE_INTERRUPTS +#define INTERRUPT_CONTEXT ((XT_RSR_PS() & PS_UM) == 0) +#else +#define INTERRUPT_CONTEXT 0 +#endif + + +//----------------------------------------------------------------------------- +// Xtensa tools version. +//----------------------------------------------------------------------------- +#if defined __XCC__ +#define XTTOOLS_VERSION (__XCC__ + __XCC_MINOR__) +#else +#define XTTOOLS_VERSION (0) +#endif + + +//----------------------------------------------------------------------------- +// Erratum workarounds. +//----------------------------------------------------------------------------- + +// Erratum 487 fix is available in version RF.3 onwards and RG.2 onwards. +#if ((__XCC__ == 11000) && (__XCC_MINOR__ >= 3)) || (XTTOOLS_VERSION >= 12002) +#define HWERR_487_FIX hw_erratum_487_fix +#else +#define HWERR_487_FIX +#endif + + +#ifdef __cplusplus +} +#endif + +#endif // __XOS_COMMON_H__ + diff --git a/tools/sdk/include/esp32/xtensa/xos_cond.h b/tools/sdk/include/esp32/xtensa/xos_cond.h new file mode 100755 index 00000000..8116947d --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/xos_cond.h @@ -0,0 +1,145 @@ +/** @file */ + +// xos_cond.h - XOS condition variables API interface and data structures. + +// Copyright (c) 2003-2015 Cadence Design Systems, Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +// NOTE: Do not include this file directly in your application. Including +// xos.h will automatically include this file. + +#ifndef __XOS_COND_H__ +#define __XOS_COND_H__ + +#include "xos_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +//----------------------------------------------------------------------------- +// +// Function pointer type for condition callbacks (defined in xos_thread.h) +// +// typedef int32_t (XosCondFunc)(void * arg, int32_t sig_value, XosThread * thread); +// +//----------------------------------------------------------------------------- + + +//----------------------------------------------------------------------------- +/// +/// Condition object. +/// +//----------------------------------------------------------------------------- +typedef struct XosCond { + XosThreadQueue queue; ///< Queue of waiters. +#if XOS_COND_DEBUG + uint32_t sig; // Signature indicates valid object. +#endif +} XosCond; + + +//----------------------------------------------------------------------------- +/// +/// Initialize a condition object before first use. The object must be +/// allocated by the caller. +/// +/// \param cond Pointer to condition object. +/// +/// \return Returns nothing. +/// +//----------------------------------------------------------------------------- +void +xos_cond_create(XosCond * cond); + + +//----------------------------------------------------------------------------- +/// +/// Destroy a condition object. Must have been previously created by calling +/// xos_cond_create(). +/// +/// \param cond Pointer to condition object. +/// +/// \return Returns nothing. +/// +//----------------------------------------------------------------------------- +void +xos_cond_delete(XosCond * cond); + + +//----------------------------------------------------------------------------- +/// +/// Wait on a condition: block until the condition is satisfied. The condition +/// is satisfied when xos_cond_signal() is called on this condition *and* the +/// condition callback function returns non-zero. If there is no callback +/// function, then the condition is automatically satisfied. +/// +/// The condition structure must have been initialized before first use by +/// calling xos_cond_create(). +/// +/// \param cond Pointer to condition object. +/// +/// \param cond_fn Pointer to a function, called by xos_cond_signal(), +/// that should return non-zero if this thread is to +/// be resumed. The function is invoked as: +/// `(*cond_fn)(cond_arg, sig_value)`. +/// +/// \param cond_arg Argument passed to cond_fn. +/// +/// \return Returns the value passed to xos_cond_signal(). +/// +//----------------------------------------------------------------------------- +int32_t +xos_cond_wait(XosCond * cond, XosCondFunc * cond_fn, void * cond_arg); + + +//----------------------------------------------------------------------------- +/// +/// Trigger the condition: wake all threads waiting on the condition, if their +/// condition function evaluates to true (non-zero). If there is no condition +/// function for a thread then it is automatically awakened. +/// +/// The condition structure must have been initialized before first use by +/// calling xos_cond_create(). +/// +/// \param cond Pointer to condition object. +/// +/// \param sig_value Value passed to all waiters, returned by +/// xos_cond_wait(). +/// +/// \return Returns the number of waiting threads that were resumed. +/// +/// NOTE: Signaling a condition that has no waiters has no effect on it, and +/// the signal is not remembered. Any thread that waits on it later must be +/// woken by another call to xos_cond_signal(). +/// +//----------------------------------------------------------------------------- +int32_t +xos_cond_signal(XosCond * cond, int32_t sig_value); + + +#ifdef __cplusplus +} +#endif + +#endif // __XOS_COND_H__ + diff --git a/tools/sdk/include/esp32/xtensa/xos_errors.h b/tools/sdk/include/esp32/xtensa/xos_errors.h new file mode 100755 index 00000000..790cdde3 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/xos_errors.h @@ -0,0 +1,107 @@ +/** @file */ + +// xos_errors.h - XOS error codes. + +// Copyright (c) 2003-2015 Cadence Design Systems, Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +// NOTE: Do not include this file directly in your application. Including +// xos.h will automatically include this file. + + +#ifndef __XOS_ERRORS_H__ +#define __XOS_ERRORS_H__ + +#include "xos_types.h" + + +#define _XOS_ERR_FIRST (-65536) +#define _XOS_ERR_LAST (-1) + + +//----------------------------------------------------------------------------- +/// +/// List of XOS error codes. All error codes are negative integers, except for +/// XOS_OK which is zero. +/// XOS error codes occupy the range from -65536 up to -1. +/// The function IS_XOS_ERRCODE() can be used to check if a value lies within +/// the error code range. +/// +//----------------------------------------------------------------------------- +typedef enum xos_err_t { + XOS_OK = 0, + + XOS_ERR_NOT_FOUND = _XOS_ERR_FIRST, ///< Object not found + XOS_ERR_INVALID_PARAMETER, ///< Function parameter is invalid + XOS_ERR_LIMIT, ///< Limit exceeded + XOS_ERR_NOT_OWNED, ///< Object not owned by caller + XOS_ERR_MUTEX_LOCKED, ///< Mutex is already locked + XOS_ERR_MUTEX_NOT_OWNED, ///< Mutex not owned by caller + XOS_ERR_MUTEX_ALREADY_OWNED, ///< Mutex already owned by caller + XOS_ERR_MUTEX_DELETE, ///< Mutex being waited on has been deleted + XOS_ERR_COND_DELETE, ///< Condition being waited on has been deleted + XOS_ERR_SEM_DELETE, ///< Semaphore being waited on has been deleted + XOS_ERR_SEM_BUSY, ///< Semaphore is not available + XOS_ERR_EVENT_DELETE, ///< Event being waited on has been deleted + XOS_ERR_MSGQ_FULL, ///< Message queue is full + XOS_ERR_MSGQ_EMPTY, ///< Message queue is empty + XOS_ERR_MSGQ_DELETE, ///< Message queue being waited on has been deleted + XOS_ERR_TIMER_DELETE, ///< Timer being waited on has been deleted + XOS_ERR_CONTAINER_NOT_RTC, ///< Containing thread not of RTC type + XOS_ERR_CONTAINER_NOT_SAME_PRI, ///< Containing thread not at same priority + XOS_ERR_STACK_TOO_SMALL, ///< Thread stack is too small + XOS_ERR_CONTAINER_ILLEGAL, ///< Illegal container thread + XOS_ERR_ILLEGAL_OPERATION, ///< This operation is not allowed + XOS_ERR_THREAD_EXITED, ///< The thread has already exited + XOS_ERR_NO_TIMER, ///< No suitable timer found + XOS_ERR_FEATURE_NOT_PRESENT, ///< This feature is disabled or not implemented + XOS_ERR_TIMEOUT, ///< Wait timed out + + XOS_ERR_UNHANDLED_INTERRUPT, ///< No handler for interrupt + XOS_ERR_UNHANDLED_EXCEPTION, ///< No handler for exception + XOS_ERR_INTERRUPT_CONTEXT, ///< Operation is illegal in interrupt context + XOS_ERR_THREAD_BLOCKED, ///< Thread already blocked + XOS_ERR_ASSERT_FAILED, ///< Runtime assertion failure + XOS_ERR_CLIB_ERR, ///< Error in C library thread safety module + XOS_ERR_INTERNAL_ERROR, ///< XOS internal error + + XOS_ERR_LAST = _XOS_ERR_LAST, +} xos_err_t; + + +//----------------------------------------------------------------------------- +/// +/// Check if a value is a valid XOS error code. +/// +/// \param val Value to check +/// +/// \return Returns nonzero if 'val' is in the XOS error code range. +/// +//----------------------------------------------------------------------------- +static inline int32_t +IS_XOS_ERRCODE(xos_err_t val) +{ + return ((val >= _XOS_ERR_FIRST) && (val <= _XOS_ERR_LAST)); +} + + +#endif // __XOS_ERRORS_H__ + diff --git a/tools/sdk/include/esp32/xtensa/xos_event.h b/tools/sdk/include/esp32/xtensa/xos_event.h new file mode 100755 index 00000000..43219a24 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/xos_event.h @@ -0,0 +1,281 @@ +/** @file */ + +// xos_event.h - XOS Event API interface and data structures. + +// Copyright (c) 2003-2015 Cadence Design Systems, Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +// NOTE: Do not include this file directly in your application. Including +// xos.h will automatically include this file. + +#ifndef __XOS_EVENT_H__ +#define __XOS_EVENT_H__ + +#include "xos_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +//----------------------------------------------------------------------------- +// Defines. +//----------------------------------------------------------------------------- +#define XOS_EVENT_BITS_ALL 0xFFFFFFFF +#define XOS_EVENT_BITS_NONE 0 + + +//----------------------------------------------------------------------------- +// Event flags. +//----------------------------------------------------------------------------- + + +//----------------------------------------------------------------------------- +/// +/// Event object. +/// +//----------------------------------------------------------------------------- +typedef struct XosEvent { + XosThreadQueue waitq; ///< Queue of waiters. + uint32_t bits; ///< Event bits + uint32_t mask; ///< Specifies which bits are valid + uint16_t flags; ///< Properties. + uint16_t pad; ///< Padding +#if XOS_EVENT_DEBUG + uint32_t sig; // Valid signature indicates inited. +#endif +} XosEvent; + + +//----------------------------------------------------------------------------- +/// +/// Initialize an event object before first use. +/// +/// \param event Pointer to event object. +/// +/// \param mask Mask of active bits. Only these bits can be signaled. +/// +/// \param flags Creation flags (currently ignored, should be zero). +/// +/// \return Returns nothing. +/// +//----------------------------------------------------------------------------- +void +xos_event_create(XosEvent * event, uint32_t mask, uint32_t flags); + + +//----------------------------------------------------------------------------- +/// +/// Destroy an event object. Must have been previously created by calling +/// xos_event_create(). +/// +/// \param event Pointer to event object. +/// +/// \return Returns nothing. +/// +//----------------------------------------------------------------------------- +void +xos_event_delete(XosEvent * event); + + +//----------------------------------------------------------------------------- +/// +/// Set the specified bits in the specified event. Propagates the bit states +/// to all waiting threads and wakes them if needed. +/// +/// \param event Pointer to event object. +/// +/// \param bits Mask of bits to set. Bits not set in the mask +/// will not be modified by this call. To set all +/// the bits in the event, use the constant +/// XOS_EVENT_BITS_ALL. +/// +/// \return Returns XOS_OK on success, else error code. +/// +//----------------------------------------------------------------------------- +int32_t +xos_event_set(XosEvent * event, uint32_t bits); + + +//----------------------------------------------------------------------------- +/// +/// Clear the specified bits in the specified event. Propagates the bit states +/// to all waiting threads and wakes them if needed. +/// +/// \param event Pointer to event object. +/// +/// \param bits Mask of bits to clear. Every bit that is set in +/// the mask will be cleared from the event. Bits +/// not set in the mask will not be modified by this +/// call. To clear all the bits in an event use the +/// constant XOS_EVENT_BITS_ALL. +/// +/// \return Returns XOS_OK on success, else error code. +/// +//----------------------------------------------------------------------------- +int32_t +xos_event_clear(XosEvent * event, uint32_t bits); + + +//----------------------------------------------------------------------------- +/// +/// Clear and set the specified bits in the specified event. The two steps are +/// combined into one update, so this is faster than calling xos_event_clear() +/// and xos_event_set() separately. Only one update is sent out to waiting +/// threads. +/// +/// \param event Pointer to event object. +/// +/// \param clr_bits Mask of bits to clear. The clear operation +/// happens before the set operation. +/// +/// \param set_bits Mask of bits to set. +/// +/// \return Returns XOS_OK on success, else error code. +/// +//----------------------------------------------------------------------------- +int32_t +xos_event_clear_and_set(XosEvent * event, uint32_t clr_bits, uint32_t set_bits); + + +//----------------------------------------------------------------------------- +/// +/// Get the current state of the event object. This is a snapshot of the state +/// of the event at this time. +/// +/// \param event Pointer to event object. +/// +/// \param pstate Pointer to a uint32_t variable where the state +/// will be returned. +/// +/// \return Returns XOS_OK on success, else error code. +/// +//----------------------------------------------------------------------------- +int32_t +xos_event_get(XosEvent * event, uint32_t * pstate); + + +//----------------------------------------------------------------------------- +/// +/// Wait until all the specified bits in the wait mask become set in the given +/// event object. +/// +/// \param event Pointer to event object. +/// +/// \param bits Mask of bits to test. +/// +/// \return Returns XOS_OK on success, else error code. +/// +//----------------------------------------------------------------------------- +int32_t +xos_event_wait_all(XosEvent * event, uint32_t bits); + + +//----------------------------------------------------------------------------- +/// +/// Wait until all the specified bits in the wait mask become set in the given +/// event object, or the timeout expires. +/// +/// \param event Pointer to event object. +/// +/// \param bits Mask of bits to test. +/// +/// \param to_cycles Timeout in cycles. Convert from time to cycles +/// using the helper functions provided in xos_timer. +/// A value of zero indicates no timeout. +/// +/// \return Returns XOS_OK on success, XOS_ERR_TIMEOUT on timeout, else +/// error code. +/// +/// NOTE: If XOS_OPT_WAIT_TIMEOUT is not enabled, then the timeout value is +/// ignored, and no timeout will occur. +/// +//----------------------------------------------------------------------------- +int32_t +xos_event_wait_all_timeout(XosEvent * event, uint32_t bits, uint64_t to_cycles); + + +//----------------------------------------------------------------------------- +/// +/// Wait until any of the specified bits in the wait mask become set in the +/// given event object. +/// +/// \param event Pointer to event object. +/// +/// \param bits Mask of bits to test. +/// +/// \return Returns XOS_OK on success, else error code. +/// +//----------------------------------------------------------------------------- +int32_t +xos_event_wait_any(XosEvent * event, uint32_t bits); + + +//----------------------------------------------------------------------------- +/// +/// Wait until any of the specified bits in the wait mask become set in the +/// event object, or the timeout expires. +/// +/// \param event Pointer to event object. +/// +/// \param bits Mask of bits to test. +/// +/// \param to_cycles Timeout in cycles. Convert from time to cycles +/// using the helper functions provided in xos_timer. +/// A value of zero indicates no timeout. +/// +/// \return Returns XOS_OK on success, XOS_ERR_TIMEOUT on timeout, else +/// error code. +/// +/// NOTE: If XOS_OPT_WAIT_TIMEOUT is not enabled, then the timeout value is +/// ignored, and no timeout will occur. +/// +//----------------------------------------------------------------------------- +int32_t +xos_event_wait_any_timeout(XosEvent * event, uint32_t bits, uint64_t to_cycles); + + +//----------------------------------------------------------------------------- +/// +/// Atomically set a specified group of bits, then wait for another specified +/// group of bits to become set. +/// +/// \param event Pointer to event object. +/// +/// \param set_bits Group of bits to set. +/// +/// \param wait_bits Group of bits to wait on. All the bits in the +/// group will have to get set before the wait is +/// satisfied. +/// +/// \return Returns XOS_OK on success, else error code. +/// +//----------------------------------------------------------------------------- +int32_t +xos_event_set_and_wait(XosEvent * event, uint32_t set_bits, uint32_t wait_bits); + + +#ifdef __cplusplus +} +#endif + +#endif // __XOS_EVENT_H__ + diff --git a/tools/sdk/include/esp32/xtensa/xos_internal.h b/tools/sdk/include/esp32/xtensa/xos_internal.h new file mode 100755 index 00000000..5b8c8b46 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/xos_internal.h @@ -0,0 +1,120 @@ + +// Copyright (c) 2003-2015 Cadence Design Systems, Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + +#ifndef __XOS_INTERNAL_H__ +#define __XOS_INTERNAL_H__ + +#if !defined(__XOS_H__) || !defined(_XOS_INCLUDE_INTERNAL_) + #error "xos_internal.h must be included by defining _XOS_INCLUDE_INTERNAL_ before including xos.h" +#endif + +#include +#include "xos_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +// Use this macro to suppress compiler warnings for unused variables. + +#define UNUSED(x) (void)(x) + + +#if XOS_DEBUG + +#include +#include +# define DPRINTF printf + +#else + +# define DPRINTF(x...) do {} while(0) + +#endif + + +//----------------------------------------------------------------------------- +// Internal flags for thread creation. +//----------------------------------------------------------------------------- +#define XOS_THREAD_FAKE 0x8000 // Don't allocate stack (init and idle threads). + + +//----------------------------------------------------------------------------- +// Interrupt handler table entry. This structure defines one entry in the XOS +// interrupt handler table. +//----------------------------------------------------------------------------- +typedef struct XosIntEntry { + XosIntFunc * handler; // Pointer to handler function. + void * arg; // Argument passed to handler function. +#if XOS_OPT_INTERRUPT_SWPRI + unsigned char level; // Interrupt level. + unsigned char priority; // Interrupt priority. + short reserved; // Reserved. + unsigned int primask; // Mask of interrupts at higher priority. +#else + unsigned int ps; // Value of PS when running the handler. +#endif +} XosIntEntry; + + +//----------------------------------------------------------------------------- +// Extern variables. +//----------------------------------------------------------------------------- +extern unsigned xos_intlevel_mask; +extern unsigned xos_intenable_mask; +extern XosIntEntry xos_interrupt_table[XCHAL_NUM_INTERRUPTS]; + +extern uint32_t xos_clock_freq; +extern uint32_t xos_tick_period; +extern uint64_t xos_system_ticks; +extern uint64_t xos_system_cycles; +extern uint32_t xos_num_ctx_switches; + + +/* + +One thing I noticed is different between my initial idea of stack +assignments to RTC threads, when comparing to interrupts, is that I +expected each RTC thread priority to have its own stack, whereas +interrupts of different priorities share an interrupt stack. + +It's not really a difference in memory usage, because when assigning +multiple priorities to a stack, you have to add-up worst-case for +all priorities. One possible functional difference is that with +separate stacks per priority, it's possible to dynamically change +the priority of an RTC thread (while it's running). Not sure how +valuable that might be -- changing priority is useful with priority +inheritance, to avoid priority inversion, but I don't know how often +an RTC thread might acquire a lock (it couldn't block on acquiring a +lock in the usual sense -- it could get queued waiting and be restarted +when it becomes available, or use try_lock instead of lock). + +*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __XOS_INTERNAL_H__ */ + diff --git a/tools/sdk/include/esp32/xtensa/xos_msgq.h b/tools/sdk/include/esp32/xtensa/xos_msgq.h new file mode 100755 index 00000000..30b9aa90 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/xos_msgq.h @@ -0,0 +1,278 @@ +/** @file */ + +// xos_msgq.h - XOS Message Queue API and data structures. + +// Copyright (c) 2003-2015 Cadence Design Systems, Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +// NOTE: Do not include this file directly in your application. Including +// xos.h will automatically include this file. + + +#ifndef __XOS_MSGQ_H__ +#define __XOS_MSGQ_H__ + +#include "xos_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +//----------------------------------------------------------------------------- +// XosMsgQueue is a multi-writer multi-reader message queue implementation. +// It is completely thread-safe and can be used by interrupt handlers. +// Interrupt handlers are guaranteed not to block when trying to send or +// receive a message. Messages are copied into the queue. The queue contains +// storage for a fixed number of messages defined at queue creation time. +// Messages must be a multiple of 4 bytes long (padded if necessary) and the +// message buffers must be 4-byte aligned. +//----------------------------------------------------------------------------- + + +//----------------------------------------------------------------------------- +// Message Queue flags. +//----------------------------------------------------------------------------- +#define XOS_MSGQ_WAIT_PRIORITY 0x0000 ///< Wake waiters in priority order (default) +#define XOS_MSGQ_WAIT_FIFO 0x0001 ///< Wake waiters in FIFO order +#define XOS_MSGQ_FULL 0x0002 // Queue is full +#define XOS_MSGQ_DELETED 0x8000 // Queue is deleted + + +//----------------------------------------------------------------------------- +/// +/// XosMsgQueue object. +/// +//----------------------------------------------------------------------------- +typedef struct XosMsgQueue { + uint16_t flags; ///< queue flags + uint16_t count; ///< # of messages queue can hold + uint32_t msize; ///< message size in bytes + uint16_t head; ///< write pointer + uint16_t tail; ///< read pointer + XosThreadQueue readq; ///< reader wait queue + XosThreadQueue writeq; ///< writer wait queue +#if XOS_MSGQ_DEBUG + uint32_t sig; // debug signature +#endif +#if XOS_OPT_MSGQ_STATS + uint32_t num_send; ///< # of messages put to queue + uint32_t num_recv; ///< # of messages taken from queue + uint32_t num_send_blks; ///< # of times thread blocked on send + uint32_t num_recv_blks; ///< # of times thread blocked on recv +#endif + uint32_t msg[1]; ///< first word of message buffer +} XosMsgQueue; + + +//----------------------------------------------------------------------------- +/// +/// Use these macros to statically or dynamically allocate a message queue. +/// XOS_MSGQ_ALLOC allocates a static queue, while XOS_MSGQ_SIZE can be used +/// to allocate memory via malloc() etc. +/// +/// Static: this allocates a queue named "testq", containing 10 messages, +/// each 16 bytes long. +/// +/// XOS_MSGQ_ALLOC(testq, 10, 16); +/// +/// Dynamic: this allocates a queue named "testq", containing 10 messages, +/// each 16 bytes long. +/// +/// XosMsgQueue * testq = malloc( XOS_MSGQ_SIZE(10, 16) ); +/// +/// \param name The queue name, i.e. the name of the pointer +/// to the queue. Used as the queue handle in +/// queue API calls. +/// +/// \param num Number of messages to allocate in queue. Must be > 0. +/// +/// \param size Message size in bytes. Must be > 0 and multiple of 4. +/// +//----------------------------------------------------------------------------- + +#define XOS_MSGQ_ALLOC(name, num, size) \ + static uint8_t name ## _buf[ sizeof(XosMsgQueue) + ((num) * (size)) ]; \ + XosMsgQueue * name = (XosMsgQueue *) name ## _buf; + +#define XOS_MSGQ_SIZE(num, size) \ + (sizeof(XosMsgQueue) + ((num) * (size))) + + +//----------------------------------------------------------------------------- +/// +/// Create the message queue object. Memory for the queue must be allocated by +/// the caller, either statically or via dynamic allocation. See the macros +/// XOS_MSGQ_ALLOC and XOS_MSGQ_SIZE for examples. +/// +/// \param msgq Handle (pointer) to message queue. +/// +/// \param num Number of messages allocated in queue. Must be > 0. +/// +/// \param size Message size in bytes. Must be > 0 and multiple of 4. +/// +/// \param flags Queue flags: +/// - XOS_MSGQ_WAIT_FIFO - blocked threads will be +/// woken in FIFO order. +/// - XOS_MSGQ_WAIT_PRIORITY - blocked threads will +/// be woken in priority order (default). +/// +/// \return Returns XOS_OK on success, else error code. +/// +//----------------------------------------------------------------------------- +int32_t +xos_msgq_create(XosMsgQueue * msgq, uint16_t num, uint32_t size, uint16_t flags); + + +//----------------------------------------------------------------------------- +/// +/// Destroys the specified queue. Any waiting threads are unblocked with an +/// error return. Any messages in the queue will be lost. +/// +/// \param msgq Pointer to message queue. +/// +/// \return Returns XOS_OK on success, else error code. +/// +//----------------------------------------------------------------------------- +int32_t +xos_msgq_delete(XosMsgQueue * msgq); + + +//----------------------------------------------------------------------------- +/// +/// Put a message into the queue. The message contents are copied into the next +/// available message slot. If no space is available, this function will block +/// if called from a thread, but will return immediately if called from an +/// interrupt handler. +/// +/// \param msgq Pointer to message queue. +/// +/// \param msg Pointer to message buffer. +/// +/// \return Returns XOS_OK on success, else error code. +/// +//----------------------------------------------------------------------------- +int32_t +xos_msgq_put(XosMsgQueue * msgq, const uint32_t * msg); + + +//----------------------------------------------------------------------------- +/// +/// Put a message into the queue. The message contents are copied into the next +/// available message slot. If no space is available, this function will block +/// if called from a thread, but will return immediately if called from an +/// interrupt handler. The thread will be unblocked when space frees up in the +/// queue or the timeout expires. +/// +/// \param msgq Pointer to message queue. +/// +/// \param msg Pointer to message buffer. +/// +/// \param to_cycles Timeout in cycles. Convert from time to cycles +/// using the helper functions provided in xos_timer. +/// A value of zero indicates no timeout. +/// +/// \return Returns XOS_OK on success, XOS_ERR_TIMEOUT on timeout, else error code. +/// +/// NOTE: If XOS_OPT_WAIT_TIMEOUT is not enabled, then the timeout value is +/// ignored, and no timeout will occur. +/// +//----------------------------------------------------------------------------- +int32_t +xos_msgq_put_timeout(XosMsgQueue * msgq, const uint32_t * msg, uint64_t to_cycles); + + +//----------------------------------------------------------------------------- +/// +/// Get a message from the queue. The message contents are copied into the +/// buffer that must be provided. If no message is available, this function +/// will block if called from a thread, but will return immediately if called +/// from an interrupt handler. +/// +/// \param msgq Pointer to message queue. +/// +/// \param msg Pointer to message buffer. +/// +/// \return Returns XOS_OK on success, else error code. +/// +//----------------------------------------------------------------------------- +int32_t +xos_msgq_get(XosMsgQueue * msgq, uint32_t * msg); + + +//----------------------------------------------------------------------------- +/// +/// Get a message from the queue. The message contents are copied into the +/// buffer that must be provided. If no message is available, this function +/// will block if called from a thread, but will return immediately if called +/// from an interrupt handler. The thread will be unblocked when a message +/// arrives in the queue or the timeout expires. +/// +/// \param msgq Pointer to message queue. +/// +/// \param msg Pointer to message buffer. +/// +/// \param to_cycles Timeout in cycles. Convert from time to cycles +/// using the helper functions provided in xos_timer. +/// A value of zero indicates no timeout. +/// +/// \return Returns XOS_OK on success, XOS_ERR_TIMEOUT on timeout, else error code. +/// +/// NOTE: If XOS_OPT_WAIT_TIMEOUT is not enabled, then the timeout value is +/// ignored, and no timeout will occur. +/// +//----------------------------------------------------------------------------- +int32_t +xos_msgq_get_timeout(XosMsgQueue * msgq, uint32_t * msg, uint64_t to_cycles); + + +//----------------------------------------------------------------------------- +/// +/// Check if the queue is empty. +/// +/// \param msgq Pointer to message queue. +/// +/// \return Returns nonzero if queue is empty, zero if queue is not empty. +/// +//----------------------------------------------------------------------------- +int32_t +xos_msgq_empty(XosMsgQueue * msgq); + + +//----------------------------------------------------------------------------- +/// +/// Check if the queue is full. +/// +/// \param msgq Pointer to message queue. +/// +/// \return Returns nonzero if queue is full, zero if queue is not full. +/// +//----------------------------------------------------------------------------- +int32_t +xos_msgq_full(XosMsgQueue * msgq); + + +#ifdef __cplusplus +} +#endif + +#endif // __XOS_MSGQ_H__ + diff --git a/tools/sdk/include/esp32/xtensa/xos_mutex.h b/tools/sdk/include/esp32/xtensa/xos_mutex.h new file mode 100755 index 00000000..9df5f975 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/xos_mutex.h @@ -0,0 +1,205 @@ +/** @file */ + +// xos_mutex.h - XOS Mutex API interface and data structures. + +// Copyright (c) 2003-2015 Cadence Design Systems, Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +// NOTE: Do not include this file directly in your application. Including +// xos.h will automatically include this file. + +#ifndef __XOS_MUTEX_H__ +#define __XOS_MUTEX_H__ + +#include "xos_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +//----------------------------------------------------------------------------- +// Mutex flags. +//----------------------------------------------------------------------------- +#define XOS_MUTEX_WAIT_PRIORITY 0x0000 ///< Wake waiters in priority order (default) +#define XOS_MUTEX_WAIT_FIFO 0x0001 ///< Wake waiters in FIFO order +#define XOS_MUTEX_PRIORITY_CLG 0x0004 // Use priority ceiling +#define XOS_MUTEX_PRIORITY_INV 0x0008 // Protect against priority inversion + + +//----------------------------------------------------------------------------- +/// +/// XosMutex object. +/// +//----------------------------------------------------------------------------- +typedef struct XosMutex { + XosThread * owner; ///< Owning thread (null if unlocked). + XosThreadQueue waitq; ///< Queue of waiters. + uint32_t flags; ///< Properties. + uint32_t priority; + int32_t lock_count; ///< For recursive locking. +#if XOS_MUTEX_DEBUG + uint32_t sig; // Valid signature indicates inited. +#endif +} XosMutex; + + +//----------------------------------------------------------------------------- +/// +/// Initialize a mutex object before first use. +/// +/// \param mutex Pointer to mutex object. +/// +/// \param flags Creation flags: +/// - XOS_MUTEX_WAIT_FIFO -- Queue waiting threads +/// in fifo order. +/// - XOS_MUTEX_WAIT_PRIORITY -- Queue waiting threads +/// by priority. This is the default. +/// - XOS_MUTEX_PRIORITY_CLG -- Use specified priority +/// value as the mutex's priority ceiling. If the +/// owning thread has a priority lower than the mutex's +/// priority, then the thread will have its priority +/// raised to the higher value as long as it owns the +/// mutex. +/// - XOS_MUTEX_PRIORITY_INV -- Protect against priority +/// inversion. If there is a waiting thread with a +/// higher priority than the current owner thread, +/// then the owner thread's priority is raised to the +/// higher value for as long as it owns the mutex. +/// +/// \param priority Mutex's priority ceiling. This is used only if the +/// XOS_MUTEX_PRIORITY_CLG flag is set. +/// +/// \return Returns XOS_OK on success, else error code. +/// +/// NOTE: XOS_MUTEX_PRIORITY_CLG and XOS_MUTEX_PRIORITY_INV are NOT supported +/// in the current release. They will be supported in a future release. +/// +//----------------------------------------------------------------------------- +int32_t +xos_mutex_create(XosMutex * mutex, uint32_t flags, uint8_t priority); + + +//----------------------------------------------------------------------------- +/// +/// Destroy a mutex object. Must have been previously initialized by calling +/// xos_mutex_create(). +/// +/// \param mutex Pointer to mutex object. +/// +/// \return Returns XOS_OK on success, else error code. +/// +//----------------------------------------------------------------------------- +int32_t +xos_mutex_delete(XosMutex * mutex); + + +//----------------------------------------------------------------------------- +/// +/// Take ownership of the mutex: block until the mutex is owned. +/// The mutex must have been initialized. +/// +/// \param mutex Pointer to mutex object. +/// +/// \return Returns XOS_OK on success, else error code. +/// +//----------------------------------------------------------------------------- +int32_t +xos_mutex_lock(XosMutex * mutex); + + +//----------------------------------------------------------------------------- +/// +/// Take ownership of the mutex: block until the mutex is owned or the timeout +/// expires. The mutex must have been initialized. +/// +/// \param mutex Pointer to mutex object. +/// +/// \param to_cycles Timeout in cycles. Convert from time to cycles +/// using the helper functions provided in xos_timer. +/// A value of zero indicates no timeout. +/// +/// \return Returns XOS_OK on success, XOS_ERR_TIMEOUT on timeout, else error code. +/// +/// NOTE: If XOS_OPT_WAIT_TIMEOUT is not enabled, then the timeout value is +/// ignored, and no timeout will occur. +/// +//----------------------------------------------------------------------------- +int32_t +xos_mutex_lock_timeout(XosMutex * mutex, uint64_t to_cycles); + + +//----------------------------------------------------------------------------- +/// +/// Release ownership of the mutex. The mutex must have been initialized and +/// must be owned by the calling thread. +/// +/// \param mutex Pointer to mutex object. +/// +/// \return Returns XOS_OK on success, else error code. +/// +//----------------------------------------------------------------------------- +int32_t +xos_mutex_unlock(XosMutex * mutex); + + +//----------------------------------------------------------------------------- +/// +/// Try to take ownership of the mutex, but do not block if the mutex is taken. +/// Return immediately. The mutex must have been initialized. +/// +/// \param mutex Pointer to mutex object. +/// +/// \return Returns XOS_OK on success (mutex owned), else error code. +/// +//----------------------------------------------------------------------------- +int32_t +xos_mutex_trylock(XosMutex * mutex); + + +//----------------------------------------------------------------------------- +/// +/// Return the state of the mutex (locked or unlocked) but do not attempt to +/// take ownership. The mutex must have been initialized. +/// +/// \param mutex Pointer to mutex object. +/// +/// \return Returns 0 if the mutex is unlocked, 1 if it is locked, -1 on error. +/// +//----------------------------------------------------------------------------- +static inline int32_t +xos_mutex_test(XosMutex * mutex) +{ + XOS_ASSERT(mutex); + + if (mutex != XOS_NULL) { + return (mutex->owner != XOS_NULL) ? 1 : 0; + } + return -1; +} + + +#ifdef __cplusplus +} +#endif + +#endif // __XOS_MUTEX_H__ + diff --git a/tools/sdk/include/esp32/xtensa/xos_params.h b/tools/sdk/include/esp32/xtensa/xos_params.h new file mode 100755 index 00000000..3fca11f2 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/xos_params.h @@ -0,0 +1,276 @@ +/** @file */ + +// xos_params.h - user-settable compile time parameters for XOS. + +// Copyright (c) 2003-2015 Cadence Design Systems, Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + +#ifndef __XOS_PARAMS_H__ +#define __XOS_PARAMS_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +//----------------------------------------------------------------------------- +/// +/// Number of thread priority levels. At this time XOS supports a maximum of +/// 32 priority levels (0 - 31). +/// +//----------------------------------------------------------------------------- +#ifndef XOS_NUM_PRIORITY +#define XOS_NUM_PRIORITY 16 // Default is 16 +#endif + + +//----------------------------------------------------------------------------- +/// +/// Debug flags - Set to 1 to enable debug mode (and more verbose operation). +/// Can be set individually, or define XOS_DEBUG_ALL to enable all of them. +/// +/// - XOS_DEBUG -- Generic OS debug +/// - XOS_COND_DEBUG -- Condition objects debug +/// - XOS_EVENT_DEBUG -- Event objects debug +/// - XOS_MSGQ_DEBUG -- Message queue debug +/// - XOS_MUTEX_DEBUG -- Mutex objects debug +/// - XOS_SEM_DEBUG -- Semaphore objects debug +/// - XOS_THREAD_DEBUG -- Thread module debug +/// - XOS_TIMER_DEBUG -- Timer module debug +/// +/// WARNING: Enabling one or more of these flags will affect system performance +/// and timing. +/// +/// NOTE: Not all of these have been fully implemented. +/// +//----------------------------------------------------------------------------- +#if defined XOS_DEBUG_ALL + +#define XOS_DEBUG 1 +#define XOS_THREAD_DEBUG 1 +#define XOS_TIMER_DEBUG 1 +#define XOS_COND_DEBUG 1 +#define XOS_MUTEX_DEBUG 1 +#define XOS_SEM_DEBUG 1 +#define XOS_EVENT_DEBUG 1 +#define XOS_MSGQ_DEBUG 1 + +#else + +#ifndef XOS_DEBUG +#define XOS_DEBUG 0 +#endif +#ifndef XOS_THREAD_DEBUG +#define XOS_THREAD_DEBUG 0 +#endif +#ifndef XOS_TIMER_DEBUG +#define XOS_TIMER_DEBUG 0 +#endif +#ifndef XOS_COND_DEBUG +#define XOS_COND_DEBUG 0 +#endif +#ifndef XOS_MUTEX_DEBUG +#define XOS_MUTEX_DEBUG 0 +#endif +#ifndef XOS_SEM_DEBUG +#define XOS_SEM_DEBUG 0 +#endif +#ifndef XOS_EVENT_DEBUG +#define XOS_EVENT_DEBUG 0 +#endif +#ifndef XOS_MSGQ_DEBUG +#define XOS_MSGQ_DEBUG 0 +#endif + +#endif + + +//----------------------------------------------------------------------------- +/// +/// Set this option to 1 to enable runtime statistics collection for XOS. +/// NOTE: Enabling this option does have some impact on runtime performance +/// and OS footprint. +/// +//----------------------------------------------------------------------------- +#ifndef XOS_OPT_STATS +#define XOS_OPT_STATS 1 +#endif + + +//----------------------------------------------------------------------------- +/// +/// Set this option to 1 to enable statistics tracking for message queues. +/// enabling this will cause message queue objects to increase in size, and add +/// some overhead to message queue processing. +/// +//----------------------------------------------------------------------------- +#ifndef XOS_OPT_MSGQ_STATS +#define XOS_OPT_MSGQ_STATS 0 +#endif + + +//----------------------------------------------------------------------------- +/// +/// Size of interrupt stack in bytes. Shared by all interrupt handlers. Must be +/// sized to handle worst case nested interrupts. This is also used by the idle +/// thread so must exist even if interrupts are not configured. +/// +//----------------------------------------------------------------------------- +#ifndef XOS_INT_STACK_SIZE +#if XCHAL_HAVE_INTERRUPTS +#define XOS_INT_STACK_SIZE 8192 +#else +#define XOS_INT_STACK_SIZE 32 +#endif +#endif + + +//----------------------------------------------------------------------------- +/// +/// Default maximum interrupt level at which XOS primitives may be called. +/// It is the level at which interrupts are disabled by default. +/// See also description of xos_set_int_pri_level(). +/// +//----------------------------------------------------------------------------- +#ifndef XOS_MAX_OS_INTLEVEL +#define XOS_MAX_OS_INTLEVEL XCHAL_EXCM_LEVEL +#endif + + +//----------------------------------------------------------------------------- +/// +/// Set this to 1 to enable stack checking. The stack is filled with a pattern +/// on thread creation, and the stack is checked at certain times during system +/// operation. +/// WARNING: Enabling this option can have some impact on runtime performance. +/// +//----------------------------------------------------------------------------- +#ifndef XOS_OPT_STACK_CHECK +#if XOS_DEBUG +#define XOS_OPT_STACK_CHECK 1 +#else +#define XOS_OPT_STACK_CHECK 0 +#endif +#endif + + +//----------------------------------------------------------------------------- +/// +/// Set XOS_CLOCK_FREQ to the system clock frequency if this is known ahead of +/// time. Otherwise, call xos_set_clock_freq() to set it at run time. +/// +//----------------------------------------------------------------------------- +#ifndef XOS_CLOCK_FREQ +#define XOS_CLOCK_FREQ 1000000 +#endif +#define XOS_DEFAULT_CLOCK_FREQ XOS_CLOCK_FREQ + + +//----------------------------------------------------------------------------- +/// +/// Set this option to 1 to enable software prioritization of interrupts. The +/// priority scheme applied is that a higher interrupt number at the same level +/// will have higher priority. +/// +//----------------------------------------------------------------------------- +#ifndef XOS_OPT_INTERRUPT_SWPRI +#define XOS_OPT_INTERRUPT_SWPRI 1 +#endif + + +//----------------------------------------------------------------------------- +/// +/// Set this option to 1 to use the thread-safe version of the C runtime library. +/// You may need to enable this if you call C library functions from multiple +/// threads -- see the documentation for the relevant C library to determine if +/// this is necessary. This option increases the size of the TCB. +/// NOTE: At this time only the newlib and xclib libraries are supported for +/// thread safety. +/// +//----------------------------------------------------------------------------- +#include + +#ifndef XOS_OPT_THREAD_SAFE_CLIB + +#if XSHAL_CLIB == XTHAL_CLIB_XCLIB +#define XOS_OPT_THREAD_SAFE_CLIB 1 +#elif XSHAL_CLIB == XTHAL_CLIB_NEWLIB +#define XOS_OPT_THREAD_SAFE_CLIB 1 +#else +#define XOS_OPT_THREAD_SAFE_CLIB 0 +#endif + +#endif + + +//----------------------------------------------------------------------------- +/// +/// Set this option to 1 to enable the wait timeout feature. This allows waits +/// on waitable objects to expire after a specified timeout. +/// +//----------------------------------------------------------------------------- +#ifndef XOS_OPT_WAIT_TIMEOUT +#define XOS_OPT_WAIT_TIMEOUT 1 +#endif + + +//----------------------------------------------------------------------------- +/// +/// Set this option to 1 to enable threads waiting on timer objects. If this +/// feature is not used, turning it off will make timer objects smaller, and +/// reduce the time taken by timer expiry processing (by a small amount). +/// +//----------------------------------------------------------------------------- +#ifndef XOS_OPT_TIMER_WAIT +#define XOS_OPT_TIMER_WAIT 1 +#endif + + +//----------------------------------------------------------------------------- +/// +/// Set this option to 1 to enable time-slicing between multiple threads at the +/// same priority. If this option is enabled then on every timer tick the timer +/// handler will switch out the current thread if there is another ready thread +/// at the same priority, and allow the latter thread to run. Execution will be +/// round robin switched among all the threads at the same priority. +/// +/// Currently the time slice interval is fixed to be one timer tick. +/// +/// This feature is most useful if fixed duration timer ticks are used. +/// If dynamic ticking is enabled, then time slicing will work unpredictably +/// because the interval between ticks will vary. In some cases it may be +/// better to turn time slicing off. +/// +//----------------------------------------------------------------------------- +#ifndef XOS_OPT_TIME_SLICE +#define XOS_OPT_TIME_SLICE 1 +#endif + + +#ifdef __cplusplus +} +#endif + +#endif // __XOS_PARAMS_H__ + diff --git a/tools/sdk/include/esp32/xtensa/xos_regaccess.h b/tools/sdk/include/esp32/xtensa/xos_regaccess.h new file mode 100755 index 00000000..1fea5ddc --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/xos_regaccess.h @@ -0,0 +1,201 @@ + +// xos_regaccess.h - Access routines for various processor special registers. + +// Copyright (c) 2003-2015 Cadence Design Systems, Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +#ifndef __REGACCESS_H__ +#define __REGACCESS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "xos_types.h" + +#include + +#if defined (__XCC__) +#if XCHAL_HAVE_CCOUNT +#include +#endif +#endif + + +//----------------------------------------------------------------------------- +// Read CCOUNT register. +//----------------------------------------------------------------------------- +static __inline__ uint32_t xos_get_ccount(void) +{ +#if XCHAL_HAVE_CCOUNT + +#if defined (__XCC__) + return XT_RSR_CCOUNT(); +#else + uint32_t ccount; + + __asm__ __volatile__ ( "rsr %0, ccount" : "=a" (ccount) ); + return ccount; +#endif + +#else + + return 0; + +#endif +} + + +//----------------------------------------------------------------------------- +// Read CCOMPARE0 +//----------------------------------------------------------------------------- +static __inline__ uint32_t xos_get_ccompare0(void) +{ +#if XCHAL_HAVE_CCOUNT + +#if defined (__XCC__) + return XT_RSR_CCOMPARE0(); +#else + uint32_t ccompare0; + + __asm__ __volatile__ ( "rsr %0, ccompare0" : "=a" (ccompare0)); + return ccompare0; +#endif + +#else + + return 0; + +#endif +} + + +//----------------------------------------------------------------------------- +// Read CCOMPARE1 +//----------------------------------------------------------------------------- +#if (XCHAL_NUM_TIMERS > 1) +static __inline__ uint32_t xos_get_ccompare1(void) +{ +#if defined (__XCC__) + return XT_RSR_CCOMPARE1(); +#else + uint32_t ccompare1; + + __asm__ __volatile__ ( "rsr %0, ccompare1" : "=a" (ccompare1)); + return ccompare1; +#endif +} +#endif + + +//----------------------------------------------------------------------------- +// Read CCOMPARE2 +//----------------------------------------------------------------------------- +#if (XCHAL_NUM_TIMERS > 2) +static __inline__ uint32_t xos_get_ccompare2(void) +{ +#if defined (__XCC__) + return XT_RSR_CCOMPARE2(); +#else + uint32_t ccompare2; + + __asm__ __volatile__ ( "rsr %0, ccompare2" : "=a" (ccompare2)); + return ccompare2; +#endif +} +#endif + + +//----------------------------------------------------------------------------- +// Write CCOMPARE0 +//----------------------------------------------------------------------------- +static __inline__ void xos_set_ccompare0(uint32_t val) +{ +#if XCHAL_HAVE_CCOUNT + +#if defined (__XCC__) + XT_WSR_CCOMPARE0(val); + XT_ISYNC(); +#else + __asm__ __volatile__ ( + "wsr %0, ccompare0\n" + "isync" + : + : "a" (val) + ); +#endif + +#else + + // Empty + +#endif +} + + +//----------------------------------------------------------------------------- +// Write CCOMPARE1 +//----------------------------------------------------------------------------- +#if (XCHAL_NUM_TIMERS > 1) +static __inline__ void xos_set_ccompare1(uint32_t val) +{ +#if defined (__XCC__) + XT_WSR_CCOMPARE1(val); + XT_ISYNC(); +#else + __asm__ __volatile__ ( + "wsr %0, ccompare1\n" + "isync" + : + : "a" (val) + ); +#endif +} +#endif + + +//----------------------------------------------------------------------------- +// Write CCOMPARE2 +//----------------------------------------------------------------------------- +#if (XCHAL_NUM_TIMERS > 2) +static __inline__ void xos_set_ccompare2(uint32_t val) +{ +#if defined (__XCC__) + XT_WSR_CCOMPARE2(val); + XT_ISYNC(); +#else + __asm__ __volatile__ ( + "wsr %0, ccompare2\n" + "isync" + : + : "a" (val) + ); +#endif +} +#endif + + +#ifdef __cplusplus +} +#endif + +#endif // __REGACCESS_H__ + diff --git a/tools/sdk/include/esp32/xtensa/xos_semaphore.h b/tools/sdk/include/esp32/xtensa/xos_semaphore.h new file mode 100755 index 00000000..42b7914e --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/xos_semaphore.h @@ -0,0 +1,190 @@ +/** @file */ + +// xos_semaphore.h - XOS Semaphore API interface and data structures. + +// Copyright (c) 2003-2015 Cadence Design Systems, Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +// NOTE: Do not include this file directly in your application. Including +// xos.h will automatically include this file. + +#ifndef __XOS_SEMAPHORE_H__ +#define __XOS_SEMAPHORE_H__ + +#include "xos_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +//----------------------------------------------------------------------------- +// Semaphore flags. +//----------------------------------------------------------------------------- +#define XOS_SEM_WAIT_PRIORITY 0x0000 ///< Wake waiters in priority order (default) +#define XOS_SEM_WAIT_FIFO 0x0001 ///< Wake waiters in FIFO order +#define XOS_SEM_PRIORITY_INV 0x0004 // Protect against priority inversion + + +//----------------------------------------------------------------------------- +/// +/// XosSem object. +/// +//----------------------------------------------------------------------------- +typedef struct XosSem { + uint32_t count; ///< Current count + XosThreadQueue waitq; ///< Queue of waiters. + uint32_t flags; ///< Properties. +#if XOS_SEM_DEBUG + uint32_t sig; // Valid signature indicates inited. +#endif +} XosSem; + + +//----------------------------------------------------------------------------- +/// +/// Initialize a semaphore object before first use. +/// +/// \param sem Pointer to semaphore object. +/// +/// \param flags Creation flags: +/// - XOS_SEM_WAIT_FIFO -- queue waiting threads in +/// fifo order. +/// - XOS_SEM_WAIT_PRIORITY -- queue waiting threads +/// by priority. This is the default. +/// - XOS_SEM_PRIORITY_INV -- protect against priority +/// inversion. +/// +/// \param initial_count Initial count for semaphore on creation. +/// +/// \return Returns XOS_OK on success, else error code. +/// +/// NOTE: XOS_SEM_PRIORITY_INV is NOT supported in the current release. It will +/// be supported in a future release. +/// +//----------------------------------------------------------------------------- +int32_t +xos_sem_create(XosSem * sem, uint32_t flags, uint32_t initial_count); + + +//----------------------------------------------------------------------------- +/// +/// Destroy a semaphore object. Must have been previously created by calling +/// xos_sem_create(). +/// +/// \param sem Pointer to semaphore object. +/// +/// \return Returns XOS_OK on success, else error code. +/// +//----------------------------------------------------------------------------- +int32_t +xos_sem_delete(XosSem * sem); + + +//----------------------------------------------------------------------------- +/// +/// Decrement the semaphore count: block until the decrement is possible. +/// The semaphore must have been initialized. +/// +/// \param sem Pointer to semaphore object. +/// +/// \return Returns XOS_OK on success, else error code. +/// +//----------------------------------------------------------------------------- +int32_t +xos_sem_get(XosSem * sem); + + +//----------------------------------------------------------------------------- +/// +/// Decrement the semaphore count: block until the decrement is possible or +/// the timeout expires. The semaphore must have been initialized. +/// +/// \param sem Pointer to semaphore object. +/// +/// \param to_cycles Timeout in cycles. Convert from time to cycles +/// using the helper functions provided in xos_timer. +/// A value of zero indicates no timeout. +/// +/// \return Returns XOS_OK on success, XOS_ERR_TIMEOUT on timeout, else error code. +/// +/// NOTE: If XOS_OPT_WAIT_TIMEOUT is not enabled, then the timeout value is +/// ignored, and no timeout will occur. +/// +//----------------------------------------------------------------------------- +int32_t +xos_sem_get_timeout(XosSem * sem, uint64_t to_cycles); + + +//----------------------------------------------------------------------------- +/// +/// Increment the semaphore count. The semaphore must have been initialized. +/// Remember that this action may wake up a waiting thread, and if that thread +/// is higher priority then there will be an immediate context switch. +/// +/// \param sem Pointer to semaphore object. +/// +/// \return Returns XOS_OK on success, else error code. +/// +//----------------------------------------------------------------------------- +int32_t +xos_sem_put(XosSem * sem); + + +//----------------------------------------------------------------------------- +/// +/// Try to decrement the semaphore, but do not block if the semaphore count is +/// zero. Return immediately. The semaphore must have been initialized. +/// +/// \param sem Pointer to semaphore object. +/// +/// \return Returns XOS_OK on success (semaphore decremented), else error code. +/// +//----------------------------------------------------------------------------- +int32_t +xos_sem_tryget(XosSem * sem); + + +//----------------------------------------------------------------------------- +/// +/// Return the count of the semaphore but do not attempt to decrement it. +/// The semaphore must have been initialized. +/// +/// \param sem Pointer to semaphore object. +/// +/// \return Returns semaphore count, -1 on error. +/// +//----------------------------------------------------------------------------- +static inline int32_t +xos_sem_test(XosSem * sem) +{ + XOS_ASSERT(sem); + + return sem ? sem->count : -1; +} + + +#ifdef __cplusplus +} +#endif + +#endif // __XOS_SEMAPHORE_H__ + diff --git a/tools/sdk/include/esp32/xtensa/xos_stopwatch.h b/tools/sdk/include/esp32/xtensa/xos_stopwatch.h new file mode 100755 index 00000000..bf71cc38 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/xos_stopwatch.h @@ -0,0 +1,175 @@ +/** @file */ + +// xos_stopwatch.h - XOS Stopwatch objects and related API. + +// Copyright (c) 2003-2015 Cadence Design Systems, Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +// NOTE: Do not include this file directly in your application. Including +// xos.h will automatically include this file. + + +#ifndef __XOS_STOPWATCH_H__ +#define __XOS_STOPWATCH_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "xos_types.h" +#include "xos_params.h" + + +//----------------------------------------------------------------------------- +// A stopwatch object can be used to track elapsed time and accumulate total +// elapsed time over multiple execution periods. The stopwatch records the +// time whenever its start function is called, and stops recording the time +// when the stop function is called and updates its cumulative time counter. +// The stopwatch keeps time in cycles. This can be converted to seconds etc. +// by using the XOS conversion calls such as xos_cycles_to_secs(). +//----------------------------------------------------------------------------- + + +//----------------------------------------------------------------------------- +/// +/// XosStopwatch object. +/// +//----------------------------------------------------------------------------- +typedef struct XosStopwatch { + uint64_t total; ///< Total accumulated cycle count + uint64_t start; ///< Starting system cycle count + uint16_t active; ///< Active flag (nonzero when active) +} XosStopwatch; + + +//----------------------------------------------------------------------------- +/// +/// Initialize a stopwatch object. +/// +/// \param sw Pointer to a stopwatch object. +/// +/// \return Returns nothing. +/// +//----------------------------------------------------------------------------- +static inline void +xos_stopwatch_init(XosStopwatch * sw) +{ + sw->total = 0; + sw->start = 0; + sw->active = 0; +} + + +//----------------------------------------------------------------------------- +/// +/// Start a stopwatch. Starts cycle counting. +/// Note that this does not necessarily start counting from zero. The current +/// run (start-to-stop interval) will just get added to the accumulated count +/// in the stopwatch if any. +/// To reset the accumulated count, use xos_stopwatch_clear(). +/// +/// \param sw Pointer to a stopwatch object. +/// +/// \return Returns nothing. +/// +//----------------------------------------------------------------------------- +static inline void +xos_stopwatch_start(XosStopwatch * sw) +{ + XOS_ASSERT(!sw->active); + sw->active = 1; + sw->start = xos_get_system_cycles(); +} + + +//----------------------------------------------------------------------------- +/// +/// Stop a stopwatch. Stops cycle counting and updates total. +/// +/// \param sw Pointer to a stopwatch object. +/// +/// \return Returns nothing. +/// +//----------------------------------------------------------------------------- +static inline void +xos_stopwatch_stop(XosStopwatch * sw) +{ + XOS_ASSERT(sw->active); + sw->active = 0; + sw->total += xos_get_system_cycles() - sw->start; +} + + +//----------------------------------------------------------------------------- +/// +/// Get stopwatch accumulated count. +/// +/// \param sw Pointer to a stopwatch object. +/// +/// \return Returns the accumulated count. +/// +//----------------------------------------------------------------------------- +static inline uint64_t +xos_stopwatch_count(XosStopwatch * sw) +{ + return sw->total; +} + + +//----------------------------------------------------------------------------- +/// +/// Get elapsed time since stopwatch was started. If not started, returns zero. +/// +/// \param sw Pointer to a stopwatch object. +/// +/// \return Returns elapsed time in cycles. +/// +//----------------------------------------------------------------------------- +static inline uint64_t +xos_stopwatch_elapsed(XosStopwatch * sw) +{ + return sw->active ? xos_get_system_cycles() - sw->start : 0; +} + + +//----------------------------------------------------------------------------- +/// +/// Clears a stopwatch. Resets the accumulated count to zero, and deactivates +/// it if active. +/// +/// \param sw Pointer to a stopwatch object. +/// +/// \return Returns nothing. +/// +//----------------------------------------------------------------------------- +static inline void +xos_stopwatch_clear(XosStopwatch * sw) +{ + xos_stopwatch_init(sw); +} + + +#ifdef __cplusplus +} +#endif + +#endif // __XOS_STOPWATCH_H__ + diff --git a/tools/sdk/include/esp32/xtensa/xos_syslog.h b/tools/sdk/include/esp32/xtensa/xos_syslog.h new file mode 100755 index 00000000..be56968f --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/xos_syslog.h @@ -0,0 +1,330 @@ +/** @file */ + +// xos_syslog.h - XOS Event logging module. + +// Copyright (c) 2003-2015 Cadence Design Systems, Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +// NOTE: Do not include this file directly in your application. Including +// xos.h will automatically include this file. + + +#ifndef __XOS_SYSLOG_H__ +#define __XOS_SYSLOG_H__ + +#include "xos_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +//----------------------------------------------------------------------------- +// The XOS system log is an array of fixed size entries. The size of the log +// is determined by the application, and memory for the log must be provided +// at init time. Every time the log function is called, an entry is made in +// the log and the next pointer advanced. When the log is full, it will wrap +// around and start overwriting the oldest entries. +// Logging can be done from C/C++ code as well as assembly code, and at any +// interrupt level, even from high level interrupt handlers. +//----------------------------------------------------------------------------- + + +//----------------------------------------------------------------------------- +// Defines. +//----------------------------------------------------------------------------- +#define XOS_SYSLOG_ENABLED 0x0001 + + +///---------------------------------------------------------------------------- +/// +/// Use this macro to compute how much memory to allocate for the syslog. +/// +///---------------------------------------------------------------------------- +#define XOS_SYSLOG_SIZE(num_entries) \ + ( sizeof(XosSysLog) + ((num_entries - 1) * sizeof(XosSysLogEntry)) ) + + +///---------------------------------------------------------------------------- +/// +/// System log entry structure. +/// +///---------------------------------------------------------------------------- +typedef struct XosSysLogEntry { + uint32_t timestamp; ///< Timestamp in clock cycles + uint32_t param1; ///< User defined value + uint32_t param2; ///< User defined value + struct XosSysLogEntry * next; ///< Link to next entry +} XosSysLogEntry; + + +///---------------------------------------------------------------------------- +/// +/// System log structure. +/// +///---------------------------------------------------------------------------- +typedef struct XosSysLog { + uint16_t flags; ///< Flags + uint16_t size; ///< Number of entries + XosSysLogEntry * next; ///< Next write position + XosSysLogEntry entries[1]; ///< First entry +} XosSysLog; + + +//----------------------------------------------------------------------------- +// Pointer to syslog area. +//----------------------------------------------------------------------------- +extern XosSysLog * xos_syslog; + + +//---------------------------------------------------------------------------- +/// +/// Initialize the syslog. Initializing the log also enables it. The system +/// log always wraps around when full and overwrites the oldest entries. +/// +/// \param log_mem Pointer to allocated memory for the log. +/// +/// \param num_entries The number of entries that the log can contain. +/// +/// \return Returns nothing. +/// +//---------------------------------------------------------------------------- +static inline void +xos_syslog_init(void * log_mem, uint16_t num_entries) +{ + uint16_t i; + + xos_syslog = (XosSysLog *) log_mem; + xos_syslog->size = num_entries; + xos_syslog->next = xos_syslog->entries; + + for (i = 0; i < num_entries - 1; i++) { + xos_syslog->entries[i].next = &(xos_syslog->entries[i+1]); + xos_syslog->entries[i].timestamp = 0; + } + xos_syslog->entries[i].next = xos_syslog->entries; + xos_syslog->entries[i].timestamp = 0; + + xos_syslog->flags = XOS_SYSLOG_ENABLED; +} + + +///---------------------------------------------------------------------------- +/// +/// Reset the syslog. All entries made up to now are abandoned and the write +/// pointer is set to the first entry location. +/// +/// No parameters. +/// +/// \return Returns nothing. +/// +///---------------------------------------------------------------------------- +static inline void +xos_syslog_clear() +{ +#if XCHAL_HAVE_INTERRUPTS + uint32_t ps = XT_RSIL(XCHAL_NUM_INTLEVELS); +#endif + + xos_syslog_init(xos_syslog, xos_syslog->size); +#if XCHAL_HAVE_INTERRUPTS + xos_restore_int_pri_level(ps); +#endif +} + + +///---------------------------------------------------------------------------- +/// +/// Enable logging to the syslog. This function needs to be called only if +/// logging had been previously disabled via xos_syslog_disable(), since +/// initializing the syslog automatically enables it. +/// +/// No parameters. +/// +/// \return Returns nothing. +/// +///---------------------------------------------------------------------------- +static inline void +xos_syslog_enable() +{ +#if XCHAL_HAVE_INTERRUPTS + uint32_t ps = XT_RSIL(XCHAL_NUM_INTLEVELS); +#endif + + xos_syslog->flags |= XOS_SYSLOG_ENABLED; +#if XCHAL_HAVE_INTERRUPTS + xos_restore_int_pri_level(ps); +#endif +} + + +///---------------------------------------------------------------------------- +/// +/// Disable logging to the syslog. It is sometimes useful to disable logging +/// while the log is being examined or dumped. +/// +/// No parameters. +/// +/// \return Returns nothing. +/// +///---------------------------------------------------------------------------- +static inline void +xos_syslog_disable() +{ +#if XCHAL_HAVE_INTERRUPTS + uint32_t ps = XT_RSIL(XCHAL_NUM_INTLEVELS); +#endif + xos_syslog->flags &= ~XOS_SYSLOG_ENABLED; +#if XCHAL_HAVE_INTERRUPTS + xos_restore_int_pri_level(ps); +#endif +} + + +///---------------------------------------------------------------------------- +/// +/// Write an entry into the syslog. This function does disable all interrupts +/// since logging can be done from interrupt handlers as well. It will write +/// into the log only if the log exists and is enabled. +/// +/// \param param1 User defined value. +/// +/// \param param2 User defined value. +/// +/// \return Returns nothing. +/// +///---------------------------------------------------------------------------- +static inline void +xos_syslog_write(uint32_t param1, uint32_t param2) +{ + if (xos_syslog != XOS_NULL) { +#if XCHAL_HAVE_INTERRUPTS + uint32_t ps = XT_RSIL(XCHAL_NUM_INTLEVELS); +#endif + + if ((xos_syslog->flags & XOS_SYSLOG_ENABLED) != 0) { + XosSysLogEntry * next = xos_syslog->next; + + next->timestamp = xos_get_ccount(); + next->param1 = param1; + next->param2 = param2; + + xos_syslog->next = next->next; + } + +#if XCHAL_HAVE_INTERRUPTS + xos_restore_int_pri_level(ps); +#endif + } +} + + +///---------------------------------------------------------------------------- +/// +/// Read the first (oldest) entry in the syslog. Will return an error if the +/// log has not been created or is empty. Storage to copy the entry must be +/// provided by the caller. +/// +/// \param entry Pointer to storage where the entry data will be +/// copied. This pointer must be passed to +/// xos_syslog_get_next(). +/// +/// \return Returns XOS_OK on success, else error code. +/// +///---------------------------------------------------------------------------- +static inline int32_t +xos_syslog_get_first(XosSysLogEntry * entry) +{ + if (xos_syslog == XOS_NULL) { + return XOS_ERR_NOT_FOUND; + } + + if (entry != XOS_NULL) { +#if XCHAL_HAVE_INTERRUPTS + uint32_t ps = XT_RSIL(XCHAL_NUM_INTLEVELS); +#endif + XosSysLogEntry * next = xos_syslog->next; + + // 'next' should be pointing to the next entry to be overwritten, if we + // have wrapped. This means it is the oldest entry. However if this entry + // has a zero timestamp then we have not wrapped, in which case we must + // look at the first entry in the list. + if (next->timestamp == 0) { + next = xos_syslog->entries; + } + + *entry = *next; +#if XCHAL_HAVE_INTERRUPTS + xos_restore_int_pri_level(ps); +#endif + return entry->timestamp ? XOS_OK : XOS_ERR_NOT_FOUND; + } + + return XOS_ERR_INVALID_PARAMETER; +} + + +///---------------------------------------------------------------------------- +/// +/// Get the next sequential entry from the syslog. This function must be called +/// only after xos_syslog_get_first() has been called. +/// +/// \param entry Pointer to storage where entry data will be copied. +/// Must be the same pointer that was passed in the call +/// to xos_syslog_get_first(), as it is used to keep track +/// of the current position. +/// +/// \return Returns XOS_OK on success, else error code. +/// +///---------------------------------------------------------------------------- +static inline int32_t +xos_syslog_get_next(XosSysLogEntry * entry) +{ + if (entry != XOS_NULL) { +#if XCHAL_HAVE_INTERRUPTS + uint32_t ps = XT_RSIL(XCHAL_NUM_INTLEVELS); +#endif + XosSysLogEntry * next = entry->next; + int32_t ret = XOS_OK; + + // Make sure we're not pointing past the last entry. + if ((next != XOS_NULL) && (next != xos_syslog->next) && (next->timestamp != 0)) { + *entry = *next; + } + else { + ret = XOS_ERR_NOT_FOUND; + } +#if XCHAL_HAVE_INTERRUPTS + xos_restore_int_pri_level(ps); +#endif + return ret; + } + + return XOS_ERR_INVALID_PARAMETER; +} + + +#ifdef __cplusplus +} +#endif + +#endif // __XOS_SYSLOG_H__ + diff --git a/tools/sdk/include/esp32/xtensa/xos_thread.h b/tools/sdk/include/esp32/xtensa/xos_thread.h new file mode 100755 index 00000000..8bc5077e --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/xos_thread.h @@ -0,0 +1,1086 @@ +/** @file */ + +// xos_thread.h - XOS Thread API interface and data structures. + +// Copyright (c) 2003-2015 Cadence Design Systems, Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +// NOTE: Do not include this file directly in your application. Including +// xos.h will automatically include this file. + + +#ifndef __XOS_THREAD_H__ +#define __XOS_THREAD_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "xos_types.h" +#include "xos_params.h" + + +//----------------------------------------------------------------------------- +// Number of thread priority levels. +//----------------------------------------------------------------------------- +#ifndef XOS_NUM_PRIORITY +#error "XOS_NUM_PRIORITY must be defined (in xos_params.h)." +#endif +#if XOS_NUM_PRIORITY > 32 +#error "The number of thread priority levels (XOS_NUM_PRIORITY) must be <= 32." +#endif +#define XOS_MAX_PRIORITY (XOS_NUM_PRIORITY) + + +//----------------------------------------------------------------------------- +// Macro for thread self pointer. +//----------------------------------------------------------------------------- +#define XOS_THREAD_SELF (xos_thread_id()) + + +//----------------------------------------------------------------------------- +/// +/// Thread entry function pointer type. +/// +//----------------------------------------------------------------------------- +typedef int32_t (XosThreadFunc)(void * arg, int32_t wake_value); + + +//----------------------------------------------------------------------------- +// Thread switcher function signature. +//----------------------------------------------------------------------------- +typedef struct XosThread XosThread; +typedef int32_t (XosSwitchFunc)(XosThread *); + + +//----------------------------------------------------------------------------- +/// +/// Condition evaluation callback function pointer type. +/// +//----------------------------------------------------------------------------- +typedef int32_t (XosCondFunc)(void * arg, int32_t sig_value, XosThread * thread); + + +//----------------------------------------------------------------------------- +/// +/// Thread exit handler function pointer type. +/// +//----------------------------------------------------------------------------- +typedef int32_t (XosThdExitFunc)(int32_t exitcode); + + +//----------------------------------------------------------------------------- +// Thread queue structure. Used to implement the ready queues as well +// as the wait queues. +//----------------------------------------------------------------------------- +typedef struct XosThreadQueue { + XosThread * head; // Pointer to first thread in queue, or 0 if none. + XosThread ** tail; // Pointer to last thread's r_next pointer, or + // to "head" if none. +} XosThreadQueue; + + +//----------------------------------------------------------------------------- +// Stack frame for a thread that is not running. That is, it has either +// been preempted or has yielded. +//----------------------------------------------------------------------------- +typedef union XosFrame { + XosExcFrame e; // resume_fn == &xos_resume_preempted_thread + XosCoopFrame c; // resume_fn == &xos_resume_cooperative_thread + // nothing for resume_fn == &xos_resume_idle_thread + // nothing for resume_fn == &xos_resume_by_restart +} XosFrame; + + +//----------------------------------------------------------------------------- +// Thread Control Block. Tracks the state and control information associated +// with a thread. +// +// IMPORTANT: keep this in sync with TCB_*** offsets in xos_common.h . +//----------------------------------------------------------------------------- +struct XosThread { + XosThread * r_next; // 00 Next thread in queue (eg. ready queue of + // its priority, or some queue of blocked threads) + // Should be NULL if not in any queue. + + XosThread ** r_pprev; // 04 Points to previous queue entry's r_next + // pointer (i.e. to itself), or to queue head + // if first in queue. NULL if not in any queue. + + XosThread * all_next; // 08 Next in list of all threads. + + void * resume_fn; // 12 Pointer to the routine to be called to + // resume this thread. On entry to such code: + // a2 == xos_curr_threadptr (thread being resumed) + // a3 == &xos_globals + + XosFrame * esf; // 16 Pointer to saved exception stack frame, + // just below thread's current stack pointer. + // For RTC threads, this is valid only while the + // thread is preempted, not when it is blocked. + + void * tie_save; // 20 TIE state save area. May be NULL if there + // is not TIE state saved for this thread. + + int32_t wake_value; // 24 Value returned from block call (by wake call) + // (for RTC: pass this to start function??) + + XosSwitchFunc * switch_fn; // 28 Pointer to a function that + // can be called from within this thread, to save + // this thread's state and switch to a specified + // other thread. Returns wake value. + + void * stack_base; // 32 Base of stack as specified by thread creator. + + void * stack_end; // 36 End of stack (adjusted for TIE state save area + // if any). + + XosThreadFunc * entry; // 40 Pointer to thread entry function. Used for + // RTC thread restart. + + void * arg; // 44 Argument value passed to entry function. + + bool ready; // 48 Set when thread is ready to run, and is in + // its priority queue (i.e. r_pprev is set when + // this flag is set). + + bool in_exit; // Exit flag, nonzero when in exit processing. + + int8_t priority; // Thread priority, 0 .. (XOS_MAX_PRI - 1). Higher + // numbers have higher priority. This must only be + // changed when thread is not ready, or by calling + // xos_thread_set_priority(). + + int8_t preempt_pri; // This thread's preemption blocking priority. + // (preempt_pri >= priority). A thread's priority + // must be higher than another's preempt_pri to be + // able to preempt it. Note that preempt_pri can + // change during runtime e.g. due to priority + // inheritance. + + uint32_t flags; // 52 Thread creation flags. + + const char * name; // 56 Thread name (mainly for debug). + + const char * block_cause; // 60 Reason for blocking. Valid only when thread + // not ready (r_pprev == 0). + + XosThread * container; // 64 Thread whose stack will be used to run + // this thread. Valid for RTC threads only, else NULL. + + XosThdExitFunc * exit_func; // 68 Thread exit handler function pointer. + + XosThreadQueue exit_waiters; // 72 Queue of threads waiting for this one to exit. + + XosThreadQueue * wq_ptr; // 80 If this thread is in a wait queue, this + // points to the queue. Must be NULL when + // thread not in a queue. + + XosCondFunc * cond_fn; // 84 Condition function. Valid only while thread + // is blocked on condition. + + void * cond_arg; // 88 Argument to be passed to condition function. + + uint16_t cp_mask; // 92 Mask of coprocessors used. + uint16_t cp_saved; // 94 Mask of coprocessors saved. + + uint32_t event_bits; // 96 event bits + uint32_t event_mask; // 100 event bit mask + uint32_t event_flags; // 104 event flags + + void * clib_ptr; // 108 Pointer to C lib context struct. + + uint32_t sig; // 112 Signature of valid TCB + + uint32_t resume_ccount; // 116 cycle count at resume + uint64_t cycle_count; // 120 number of cycles consumed (approx). + // NOTE: must be 8-byte aligned + uint32_t normal_resumes; // 128 Number of non-preemptive resumptions. + uint32_t preempt_resumes;// 132 Number of preemptive resumptions. + +#if XOS_OPT_THREAD_SAFE_CLIB + CLIB_THREAD_STRUCT; // C library context area. +#endif +}; + + +//----------------------------------------------------------------------------- +// User-visible flags for xos_thread_create(). +//----------------------------------------------------------------------------- +#define XOS_THREAD_SUSPEND 0x0001 ///< Create suspended instead of ready +#define XOS_THREAD_RTC 0x0002 ///< Run-to-completion thread +#define XOS_THREAD_NO_CP 0x0004 ///< Thread does not use coprocessors + + +//----------------------------------------------------------------------------- +// Flags used by thread creation extra parameters. +//----------------------------------------------------------------------------- +#define XOS_TP_COPROC_MASK 0x0001 +#define XOS_TP_PREEMPT_PRI 0x0002 +#define XOS_TP_EXIT_HANDLER 0x0004 + + +//----------------------------------------------------------------------------- +// Thread creation extra parameters. +//----------------------------------------------------------------------------- +typedef struct XosThreadParm { + uint32_t parms_mask; // Combination of XOS_TP_xxx flags indicating + // which parameters are valid. + + uint16_t cp_mask; // Mask of coprocessors the thread can access. + + uint32_t preempt_pri; // Initial preemption blocking priority. Can be + // changed later via xos_thread_set_priority(). + + XosThdExitFunc * handler; // Exit handler function. + +} XosThreadParm; + + +//----------------------------------------------------------------------------- +// Wrapper struct for RTC (run to completion) thread. +//----------------------------------------------------------------------------- +typedef struct XosRtcThread { + struct XosThread thread; +} XosRtcThread; + + +//----------------------------------------------------------------------------- +// External variables. +//----------------------------------------------------------------------------- +extern XosThread * xos_curr_threadptr; // Current active thread +extern XosThread * xos_next_threadptr; // Next ready thread +extern XosThread * xos_all_threads; // List of all threads + + +//----------------------------------------------------------------------------- +/// +/// Set thread creation parameter: the group of coprocessors that this thread +/// will use. This must be set during thread creation, and cannot be changed +/// after the thread has been created. Defining this allows reduction of +/// memory usage (for CP state saving) in some circumstances, and can also +/// speed up the context switch time. +/// +/// NOTE: Support for this is not currently implemented. If a thread uses +/// any coprocessor, space for all coprocessors must be reserved. +/// +/// \param parms Thread creation parameter structure. Must be +/// allocated by the caller. +/// +/// \param cp_mask Bitmask of coprocessors thread is allowed to +/// use. Bit 0 for coprocessor 0, etc. +/// +/// \return Returns nothing. +/// +//----------------------------------------------------------------------------- +static inline void +xos_threadp_set_cp_mask(XosThreadParm * parms, uint16_t cp_mask) +{ + if (parms != XOS_NULL) { + parms->parms_mask |= XOS_TP_COPROC_MASK; + parms->cp_mask = cp_mask; + } +} + + +//----------------------------------------------------------------------------- +/// +/// Set thread creation parameter: thread pre-emption priority. +/// +/// \param parms Thread creation parameter structure. Must be +/// allocated by caller. +/// +/// \param preempt_pri Thread pre-emption blocking priority. +/// From 0 .. XOS_NUM_PRIORITY - 1. +/// Must be greater or equal to the thread priority +/// (if not, is automatically set to thread priority). +/// +/// \return Returns nothing. +/// +//----------------------------------------------------------------------------- +static inline void +xos_threadp_set_preemption_priority(XosThreadParm * parms, int8_t preempt_pri) +{ + if (parms != XOS_NULL) { + parms->parms_mask |= XOS_TP_PREEMPT_PRI; + parms->preempt_pri = preempt_pri; + } +} + + +//----------------------------------------------------------------------------- +/// +/// Set thread creation parameter: thread exit handler. +/// +/// \param parms Thread creation parameter structure. Must be +/// allocated by caller. +/// +/// \param handler Exit handler function. +/// +/// \return Returns nothing. +//----------------------------------------------------------------------------- +static inline void +xos_threadp_set_exit_handler(XosThreadParm * parms, XosThdExitFunc * handler) +{ + if (parms != XOS_NULL) { + parms->parms_mask |= XOS_TP_EXIT_HANDLER; + parms->handler = handler; + } +} + + +//----------------------------------------------------------------------------- +/// +/// Create a new thread. If the thread is not created suspended, then it will +/// be made ready as soon as it is created, and will immediately run if it is +/// the highest priority non-blocked thread in the system. +/// +/// \param thread Pointer to the thread descriptor (an otherwise +/// unused XosThread structure, usually allocated +/// by the caller for the lifetime of the thread, +/// for example as a global variable). +/// +/// \param container Pointer to separate thread acting as "container" +/// for this one. At the moment, this is only meaningful +/// for run-to-completion (RTC) threads (identified with +/// the XOS_THREAD_RTC flag), in which case the container +/// must have the same priority and also be an RTC thread. +/// (The priority restriction may be lifted in a future +/// implementation, with appropriate constraints on dynamic +/// reprioritization of the created thread). +/// +/// \param entry Thread entry function, takes one argument. +/// +/// \param arg Argument "void*" that is passed to the thread function. +/// +/// \param name Unique name of the thread, for debug/display purposes. +/// This string must be valid for the lifetime of the thread +/// (only a pointer to it is stored in the thread control block). +/// Typically consists of identifier chars with no spaces. +/// +/// \param stack Base of initial stack for the thread, allocated by the +/// caller. Need not be aligned (initial stack pointer will be +/// computed and aligned from given stack base and size). +/// Required argument, except for run-to-completion threads +/// when container is non-NULL, in which case the container's +/// stack is used and this argument must be NULL. +/// +/// \param stack_size Size of the stack, in bytes. +/// NOTE: stack should be at least XOS_STACK_EXTRA bytes plus +/// whatever the thread actually needs if the thread will use +/// coprocessors/TIE state. If the thread will not touch the +/// coprocessors, then it should be XOS_STACK_EXTRA_NO_CP +/// plus whatever the thread actually needs. +/// Recommended minimum stack sizes are defined by the constants +/// XOS_STACK_MIN_SIZE and XOS_STACK_MIN_SIZE_NO_CP. +/// +/// For run-to-completion threads where container is non-NULL, +/// stack_size specifies the minimum stack size required for +/// the thread; it should be smaller or equal to the container's +/// stack. +/// +/// \param priority Initial thread priority. From 0 .. XOS_MAX_PRI - 1. +/// Higher numbers are higher priority. +/// +/// \param parms Pointer to extra parameters structure, or 0 if none given. +/// Use xos_thread_p_***() functions to set parameters in the +/// structure. +/// +/// \param flags Option flags: +/// - XOS_THREAD_SUSPEND -- Leave thread suspended instead of +/// making it ready. The thread can be made ready to run later +/// by calling xos_thread_resume(). +/// - XOS_THREAD_RTC -- Run-to-completion thread. +/// - XOS_THREAD_NO_CP -- Thread does not use coprocessors. +/// No coprocessor state will be saved for this thread. +/// Threads that have this flag set will not allocate any +/// storage for saving coprocessor state and so can have +/// smaller stacks. +/// +/// NOTE: xos_start_main() calls xos_thread_create() to convert main() into the 'main' +/// thread. +/// +/// \return Returns XOS_OK if successful, error code otherwise. +/// +//----------------------------------------------------------------------------- +int32_t +xos_thread_create(XosThread * thread, + XosThread * container, + XosThreadFunc * entry, + void * arg, + const char * name, + void * stack, + uint32_t stack_size, + int32_t priority, + XosThreadParm * parms, + uint32_t flags ); + + +//----------------------------------------------------------------------------- +/// +/// Remove thread and free up all resources. Thread must have exited already. +/// After this call returns, all resources allocated to the thread (e.g. TCB, +/// stack space, etc.) can be reused. +/// +/// \param thread Handle of thread to be deleted. +/// +/// \return Returns XOS_OK on success, else error code. +/// +/// NOTE: A thread cannot call this on itself. +/// +//----------------------------------------------------------------------------- +int32_t +xos_thread_delete(XosThread * thread); + + +//----------------------------------------------------------------------------- +/// +/// Force the thread to terminate. The thread execution is aborted, but exit +/// processing will still happen, i.e. the exit handler (if any) will be run. +/// After termination, any other threads waiting on this thread are notified. +/// This function cannot be called on the current thread. +/// +/// \param thread Handle of thread to be aborted. +/// +/// \param exitcode Exit code returned to any waiting threads. +/// +/// \return Returns XOS_OK on success, else error code. +/// +/// NOTE: If the thread is blocked waiting for something, the wait is aborted +/// and the thread is made ready. +/// NOTE: The thread is not guaranteed to have exited when this call returns. +/// It will be made ready and set up for exit processing, but when the exit +/// processing will actually happen depends on the state of the system and +/// the priority of the thread being aborted. +/// +//----------------------------------------------------------------------------- +int32_t +xos_thread_abort(XosThread * thread, int32_t exitcode); + + +//----------------------------------------------------------------------------- +/// +/// Exit the current thread. The exit handler (if any) will be run before the +/// thread terminates. +/// +/// \param exitcode Exit code to be returned to any waiting threads. +/// +/// \return This function does not return. +/// +/// NOTE: This is automatically called if the thread returns from its entry +/// function. The entry function's return value will be passed as the exit +/// code. +/// +//----------------------------------------------------------------------------- +void +xos_thread_exit(int32_t exitcode); + + +//----------------------------------------------------------------------------- +/// +/// Wait until the specified thread exits and get its exit code. If the thread +/// has exited already, an error will be returned. +/// +/// \param thread The thread to wait for. Cannot be "self", i.e. +/// one cannot wait on one's own exit. +/// +/// \param p_exitcode If not null, the exit code will be returned here. +/// +/// \return Returns XOS_OK on sucess, else error code. +/// +//----------------------------------------------------------------------------- +int32_t +xos_thread_join(XosThread * thread, int32_t * p_exitcode); + + +//----------------------------------------------------------------------------- +/// +/// Yield the CPU to the next thread in line. The calling thread remains ready +/// and is placed at the tail of the ready queue at its current priority level. +/// If there are no threads at the same priority level that are ready to run, +/// then this call will return immediately. +/// +/// \return Returns nothing. +/// +//----------------------------------------------------------------------------- +void +xos_thread_yield(); + + +//----------------------------------------------------------------------------- +/// +/// Suspend the specified thread. The thread will remain suspended until +/// xos_thread_resume() has been called on it. If the thread is already blocked +/// on some other condition, then this function will return an error. +/// +/// \param thread Handle of thread being suspended. A thread can +/// use the special handle XOS_THREAD_SELF to suspend +/// itself. +/// +/// \return Returns XOS_OK on success, else error code. +/// +//----------------------------------------------------------------------------- +int32_t +xos_thread_suspend(XosThread * thread); + + +//----------------------------------------------------------------------------- +/// +/// Resume a suspended thread. If the thread is not suspended or is blocked on +/// some other condition then this function will do nothing. Otherwise, it will +/// be made ready, and this can cause an immediate context switch if the thread +/// is at a higher priority than the calling thread. +/// +/// \param thread Handle of thread being resumed. +/// +/// \return Returns XOS_OK on success, else error code. +/// +//----------------------------------------------------------------------------- +int32_t +xos_thread_resume(XosThread * thread); + + +//----------------------------------------------------------------------------- +/// +/// Get the priority of the specified thread. This returns the priority of the +/// queried thread at this instant, however this can change at any time due to +/// other activity in the system. +/// +/// \param thread Handle of thread being queried. A thread can use +/// the special handle XOS_THREAD_SELF to query itself. +/// +/// \return Returns the thread's current priority, or -1 if the thread handle +/// is not valid. +/// +//----------------------------------------------------------------------------- +static inline int32_t +xos_thread_get_priority(XosThread * thread) +{ + XOS_ASSERT(thread); + return thread ? thread->priority : -1; +} + + +//----------------------------------------------------------------------------- +/// +/// Set the priority of the specified thread. The thread must exist. +/// +/// \param thread Handle of thread being affected. A thread can +/// use the special handle XOS_THREAD_SELF to specify +/// itself. +/// +/// \param priority The new priority level to be set. +/// +/// \return Returns XOS_OK on success, else error code. +/// +/// NOTE: Calling this function can result in a scheduler activation, and the +/// caller may be suspended as a result. +/// +//----------------------------------------------------------------------------- +int32_t +xos_thread_set_priority(XosThread * thread, int32_t priority); + + +//----------------------------------------------------------------------------- +/// +/// Return the name of the specified thread. +/// +/// \param thread Handle of thread being queried. A thread can use +/// the special handle XOS_THREAD_SELF to specify +/// itself. +/// +/// \return Returns a pointer to the name string if available, else NULL. +/// +//----------------------------------------------------------------------------- +static inline const char * +xos_thread_get_name(XosThread * thread) +{ + XOS_ASSERT(thread); + return thread ? thread->name : 0; +} + + +//----------------------------------------------------------------------------- +/// +/// Set the name of the specified thread. +/// +/// \param thread Handle of thread whose name is to be set. A thread +/// can use the special handle XOS_THREAD_SELF to specify +/// itself. +/// +/// \param name Pointer to the new name string. The string is not +/// copied, only the pointer is saved. So the string +/// must be persistent for the life of the thread. +/// +/// \return Returns XOS_OK on success, else error code. +/// +//----------------------------------------------------------------------------- +static inline int32_t +xos_thread_set_name(XosThread * thread, const char * name) +{ + XOS_ASSERT(thread); + if (thread != XOS_NULL) { + thread->name = name; + return XOS_OK; + } + + return XOS_ERR_INVALID_PARAMETER; +} + + +//----------------------------------------------------------------------------- +/// +/// Set an exit handler for the specified thread. The exit handler is run when +/// the thread terminates, either by calling xos_thread_exit() or by returning +/// from its entry function. It will also be called if the thread is being +/// terminated due to e.g. an unhandled exception. +/// +/// The handler must be a function defined as e.g.: +/// +/// int32_t exit_handler(int32_t exitcode); +/// +/// The exit handler runs in the context of the exiting thread, and can call +/// system services. It is provided with a single parameter which is the +/// thread's exit code (the exit code may be set to an error code if the +/// thread is being terminated due to an error or exception). The handler +/// must return a value which will be set as the thread's exit code. +/// +/// \param thread Handle of the thread for which the handler is +/// to be installed. A thread can use the special +/// handle XOS_THREAD_SELF to specify itself. +/// +/// \param func Pointer to exit handler function. To clear an +/// existing handler, pass NULL as the pointer. +/// +/// \return Returns XOS_OK on success, else error code. +/// +//----------------------------------------------------------------------------- +int32_t +xos_thread_set_exit_handler(XosThread * thread, XosThdExitFunc * func); + + +//----------------------------------------------------------------------------- +/// +/// Return the ID (handle) of the current thread. +/// +/// \return Returns the handle of the current thread. This handle can be +/// used in all XOS system calls. +/// +/// NOTE: If called from interrupt context, returns the handle of the thread +/// that was preempted. +/// +//----------------------------------------------------------------------------- +static inline XosThread * +xos_thread_id() +{ + return xos_curr_threadptr; +} + + +//----------------------------------------------------------------------------- +/// +/// Return the coprocessor mask for the specified thread. +/// +/// \param thread Handle of thread being queried. +/// +/// \return Returns the mask for the specified thread if available, else 0. +/// +//----------------------------------------------------------------------------- +static inline uint16_t +xos_thread_cp_mask(XosThread * thread) +{ + XOS_ASSERT(thread); + return thread ? thread->cp_mask : 0; +} + + +//----------------------------------------------------------------------------- +/// +/// Return the wake value for the specified thread. +/// +/// \return thread Handle of thread being queried. +/// +/// \return Returns The last set wake value. There is no way to detect what +/// action set the wake value and when. +/// +//----------------------------------------------------------------------------- +static inline int32_t +xos_thread_get_wake_value(XosThread * thread) +{ + XOS_ASSERT(thread); + return thread ? thread->wake_value : 0; +} + + +//----------------------------------------------------------------------------- +/// +/// Return the current value of the event bits for the current thread. +/// This function takes no parameters. +/// +/// \return Returns the current value of the event bits. The event bits +/// are set when the thread is woken from an event wait. They will +/// not change while the thread is running. There is no way to +/// determine when the event bits were last updated. +/// +//----------------------------------------------------------------------------- +static inline uint32_t +xos_thread_get_event_bits(void) +{ + XosThread * thread = xos_thread_id(); + return thread ? thread->event_bits : 0; +} + + +//----------------------------------------------------------------------------- +/// +/// Enum values for thread state. +/// +//----------------------------------------------------------------------------- +typedef enum xos_thread_state_t { + XOS_THREAD_STATE_INVALID = 0, ///< Invalid thread + XOS_THREAD_STATE_BLOCKED, ///< Thread is blocked + XOS_THREAD_STATE_READY, ///< Thread is ready to run + XOS_THREAD_STATE_RUNNING, ///< Thread is running + XOS_THREAD_STATE_EXITED, ///< Thread has exited +} xos_thread_state_t; + + +//----------------------------------------------------------------------------- +/// +/// Return the state of the specified thread. +/// +/// \param thread Handle of thread being queried. +/// +/// \return Returns one of the following values: +/// - XOS_THREAD_STATE_RUNNING -- The thread is currently running. +/// - XOS_THREAD_STATE_READY -- The thread is ready to run. +/// - XOS_THREAD_STATE_BLOCKED -- The thread is blocked on something. +/// - XOS_THREAD_STATE_INVALID -- The thread handle is invalid. +/// - XOS_THREAD_STATE_EXITED -- The thread has exited. +/// +//----------------------------------------------------------------------------- +xos_thread_state_t +xos_thread_get_state(XosThread * thread); + + +//----------------------------------------------------------------------------- +/// +/// Disable thread preemption. Prevents context switching to another thread. +/// However, interrupt handlers will still continue to be run. Multiple calls +/// will nest, and the same number of calls to xos_preemption_enable() will be +/// required to re-enable preemption. If the calling thread yields the CPU or +/// exits without enabling preemption, it will cause a system halt. +/// If the calling thread encounters a fatal error, preemption will be enabled +/// during fatal error handling. +/// +/// \return Returns the new value of preemption disable flag after this call. +/// +/// NOTE: Cannot be called from interrupt context. +/// +//----------------------------------------------------------------------------- +uint32_t +xos_preemption_disable(void); + + +//----------------------------------------------------------------------------- +/// +/// Enable thread preemption. Has no effect if preemption was already enabled. +/// Otherwise, it decrements the value of the preemption disable flag and if +/// the value goes to zero, enables preemption. +/// +/// \return Returns the new value of preemption disable flag after this call. +/// +/// NOTE: If scheduling gets enabled, it may cause an immediate context switch +/// if higher priority threads are ready. +/// +//----------------------------------------------------------------------------- +uint32_t +xos_preemption_enable(void); + + +//----------------------------------------------------------------------------- +/// +/// Initialize XOS thread support and start scheduler. +/// +/// Must be called from main() before calling any other thread function. +/// This function initializes thread support, creates the idle thread, and +/// starts the scheduler. It does not return to its caller. This means that +/// at least one user thread must be created before calling xos_start(). +/// Otherwise, the scheduler will run the idle thread since it will be the +/// only thread in the system, and no other thread can be created. +/// +/// NOTE: This function does not initialize timer/tick support. For timer +/// services to be available xos_start_system_timer() must be called. +/// +/// NOTE: xos_start() and xos_start_main() are exclusive, both cannot be +/// called within the same application. +/// +/// \param flags Currently unused (pass 0). +/// +/// \return Does not return. +/// +//----------------------------------------------------------------------------- +void +xos_start(uint32_t flags); + + +//----------------------------------------------------------------------------- +/// +/// Initialize XOS thread support and create init (main) thread. +/// +/// Must be called from main() before calling any other thread function. +/// This function converts the caller into the 'main' or 'init' thread, and +/// returns to the caller after completing initialization. +/// +/// NOTE: This function does not initialize timer/tick support. For timer +/// services to be available xos_start_system_timer() must be called. +/// +/// NOTE: xos_start_main() and xos_start() are exclusive, both cannot be +/// called within the same application. +/// +/// \param name Name of main thread (see xos_thread_create()). +/// +/// \param priority Initial priority of main thread. +/// +/// \param flags Currently unused (pass 0). +/// +/// \return Returns nothing. +/// +//----------------------------------------------------------------------------- +void +xos_start_main(const char * name, int8_t priority, uint32_t flags); + + +//----------------------------------------------------------------------------- +/// +/// Per-thread stats structure. +/// Note that the CPU use % is approximate, both because of cycle counting +/// and because of integer division. So all the threads' CPU % will not add +/// up to exactly 100%. +/// +//----------------------------------------------------------------------------- +typedef struct XosThreadStats { + XosThread * thread; ///< Thread handle (or pseudo-handle) + uint32_t cpu_pct; ///< CPU use % for this thread + uint32_t normal_switches; ///< Number of non-preemptive switches. + uint32_t preempt_switches; ///< Number of preemptive switches. + uint64_t cycle_count; ///< Number of cycles consumed. +} XosThreadStats; + + +//----------------------------------------------------------------------------- +// Thread pseudo-handles. +//----------------------------------------------------------------------------- +#define XOS_THD_STATS_IDLE ((XosThread *) 1) +#define XOS_THD_STATS_INTR ((XosThread *) 2) + + +//----------------------------------------------------------------------------- +/// +/// Get the thread statistics for the specified thread. Statistics are only +/// available if XOS_OPT_STATS has been enabled. Otherwise, the function +/// will return XOS_OK, but the structure contents will be undefined. +/// +/// \param thread Handle of thread being queried. The following +/// special pseudo-handles can be used: +/// - XOS_THD_STATS_IDLE -- stats for idle thread +/// - XOS_THD_STATS_INTR -- stats for interrupt processing +/// +/// \param stats Pointer to XosThreadStats struct to be filled in. +/// +/// \return Returns XOS_OK on success, else error code. +/// +/// NOTE: Can be called from interrupt context. +/// NOTE: This call will not fill in the "thread" and "cpu_pct" fields in the +/// "stats" structure. The thread handle is already known, and calculating the +/// CPU loading can take quite a bit of time so is not done here. +/// +//----------------------------------------------------------------------------- +int32_t +xos_thread_get_stats(XosThread * thread, XosThreadStats * stats); + + +//----------------------------------------------------------------------------- +/// +/// Get CPU loading statistics for the system. This function computes the CPU +/// percentage use for all threads in the system (including the idle thread and +/// the 'interrupt thread' (interrupt context). It also returns the cycle count +/// and number of context switches for each thread. +/// Statistics are only available if XOS_OPT_STATS has been enabled. +/// Otherwise, the function will return XOS_OK, but the structure contents will +/// be undefined. +/// +/// IMPORTANT: The entry for interrupt context does not contain a real thread +/// handle. It uses the pseudo-handle XOS_THD_STATS_INTR to indicate that this +/// entry reports interrupt statistics. This pseudo-handle cannot be used for +/// any other thread operations or queries. +/// +/// NOTE: This function disables interrupts while traversing the thread list. +/// It does not leave interrupts disabled during the computations, as that can +/// take a fair amount of time. +/// +/// \param stats Pointer to an array of XosThreadStats structures. +/// The array must be large enough to accommodate all +/// threads in the system. +/// +/// \param size The number of elements available in the array. If +/// this is smaller than the number of threads plus one +/// (for the interrupt context) then XOS_ERR_INVALID_PARAMETER +/// will be returned and '*size' will be set to the +/// minimum number of elements required. On a successful +/// return, '*size' is set to the number of elements +/// actually filled in. +/// +/// \param reset If nonzero, then thread stats counters are reset +/// after reading. This is useful if you want to track +/// the stats so as to get a better idea of current +/// system loading. E.g. calling this function once a +/// second with 'reset' nonzero will provide CPU load +/// information for the last second on each call. +/// +/// \return Returns XOS_OK on success, else error code. In particular, +/// XOS_ERR_INVALID_PARAMETER will be returned if the output buffer +/// is too small. +/// +//----------------------------------------------------------------------------- +int32_t +xos_get_cpu_load(XosThreadStats * stats, int32_t * size, int32_t reset); + + +#ifdef _XOS_INCLUDE_INTERNAL_ + +// Signature of valid thread object +#define XOS_THREAD_SIG 0x54485244 + + +// Extern functions +void +xos_init(void); + +bool +xos_init_done(void); + +bool +xos_started(void); + +int32_t +xos_schedule(XosThread * curr_thread); + +void +xos_q_remove(XosThreadQueue * queue, XosThread * thread); + +XosThread * +xos_q_pop(XosThreadQueue * queue); + +int32_t +xos_wake_queue(XosThreadQueue * queue, const char * expected_cause, int32_t wake_value); + +// Well known block causes +extern const char * const xos_blkon_idle; // (for idle thread only) +extern const char * const xos_blkon_suspend; +extern const char * const xos_blkon_delay; +extern const char * const xos_blkon_exited; +extern const char * const xos_blkon_join; +extern const char * const xos_blkon_event; +extern const char * const xos_blkon_condition; +extern const char * const xos_blkon_mutex; +extern const char * const xos_blkon_sem; +extern const char * const xos_blkon_msgq; + + +//----------------------------------------------------------------------------- +// Blocks the current active thread. +// +// Currently, this can be called from an interrupt handler to block the thread +// that was interrupted. Note that in interrupt context the current thread can +// already be in the blocked state, due to a previous call to this function. +// Can be called with interrupts enabled. +// +// block_cause Reason for blocking. +// +// block_queue Queue on to which this thread should be pushed once it +// is blocked. Can be NULL. +// +// must_schedule If nonzero, then forces a scheduling operation to pick +// the next thread to run, even if there are ready threads +// at the same priority level as the blocked thread. +// +// use_priority If nonzero, then the blocked thread will be queued in +// priority order in the specified block queue. If zero, +// the thread is queued in FIFO order. If no queue has +// been specified, this parameter is ignored. +// +// Returns: The value passed by xos_thread_wake(). +//----------------------------------------------------------------------------- +int32_t +xos_block(const char * block_cause, + XosThreadQueue * block_queue, + int32_t must_schedule, + int32_t use_priority); + + +//----------------------------------------------------------------------------- +// Unblocks the specified blocked thread and puts it at the tail end of its +// ready queue. Schedules it if it is higher priority than the current thread. +// No effect if the thread is not blocked with the specified cause. +// +// thread The thread to wake up (make ready). +// +// expected_cause The expected block cause of the thread. Thread will be +// woken only if its block cause matches this cause, or if +// expected_cause is zero. +// +// wake_value The value to be passed to the woken thread as a return +// value from xos_thread_block(). +// +// Returns: nothing. +// +// The target thread can be woken at a different priority by changing its +// priority while the thread is blocked. +// Can be called with interrupts enabled. Can be called in interrupt context. +//----------------------------------------------------------------------------- +void +xos_thread_wake(XosThread * thread, const char * expected_cause, int32_t wakevalue); + + +//----------------------------------------------------------------------------- +// Function to init C library per-thread and reentrancy support. +//----------------------------------------------------------------------------- +#if XOS_OPT_THREAD_SAFE_CLIB +void +xos_clib_init(void); + +void +xos_clib_thread_init(XosThread * thread); + +void +xos_clib_thread_cleanup(XosThread * thread); +#endif + +#endif + + +#ifdef __cplusplus +} +#endif + +#endif // __XOS_THREAD_H__ + diff --git a/tools/sdk/include/esp32/xtensa/xos_timer.h b/tools/sdk/include/esp32/xtensa/xos_timer.h new file mode 100755 index 00000000..0d89a219 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/xos_timer.h @@ -0,0 +1,592 @@ +/** @file */ + +// xos_timer.h - XOS Timer API interface and data structures. + +// Copyright (c) 2003-2015 Cadence Design Systems, Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +// NOTE: Do not include this file directly in your application. Including +// xos.h will automatically include this file. + + +#ifndef __XOS_TIMER_H__ +#define __XOS_TIMER_H__ + +#include "xos_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +//----------------------------------------------------------------------------- +/// +/// Function pointer type for timer callbacks. +/// +//----------------------------------------------------------------------------- +typedef void (XosTimerFunc)(void * arg); + + +//----------------------------------------------------------------------------- +/// +/// Timer event structure. Used to track pending timer events. +/// +//----------------------------------------------------------------------------- +typedef struct XosTimer { + struct XosTimer * next; ///< Pointer to next event in list. + uint64_t when; ///< Time (clock cycles) at which to trigger. + uint64_t delta; ///< Delta for next re-trigger, 0 if none. + XosTimerFunc * fn; ///< Function to call when timer expires. + void * arg; ///< Argument to pass to called function. + bool active; ///< Set if active (in some list of events). +#if XOS_OPT_TIMER_WAIT + XosThreadQueue waitq; ///< Queue of threads waiting on this timer. +#endif +#if XOS_TIMER_DEBUG + uint32_t signature; +#endif +} XosTimer; + + +//----------------------------------------------------------------------------- +// Extern declarations. +//----------------------------------------------------------------------------- + +// System clock frequency in cycles per second. +extern uint32_t xos_clock_freq; + + +///@{ +//----------------------------------------------------------------------------- +// Functions to convert from clock cycles to time units and vice versa. +// +// Note that these are integer conversions so for example a cycle count of less +// than one second will convert to zero seconds. +//----------------------------------------------------------------------------- + +/// Converts CPU cycles to time in seconds. +/// +/// \param cycles Number of CPU cycles. +/// +/// \return Equivalent number of seconds (truncated to integer). +static inline uint64_t +xos_cycles_to_secs(uint64_t cycles) +{ + return cycles / xos_clock_freq; +} + +/// Converts CPU cycles to time in milliseconds. +/// +/// \param cycles Number of CPU cycles. +/// +/// \return Equivalent number of milliseconds (truncated to integer). +static inline uint64_t +xos_cycles_to_msecs(uint64_t cycles) +{ + return (cycles * 1000) / xos_clock_freq; +} + +/// Converts CPU cycles to time in microseconds. +/// +/// \param cycles Number of CPU cycles. +/// +/// \return Equivalent number of microseconds (truncated to integer). +static inline uint64_t +xos_cycles_to_usecs(uint64_t cycles) +{ + return (cycles * 1000000) / xos_clock_freq; +} + +/// Converts time in seconds to CPU cycle count. +/// +/// \param secs Number of seconds. +/// +/// \return Equivalent number of CPU cycles. +static inline uint64_t +xos_secs_to_cycles(uint64_t secs) +{ + return secs * xos_clock_freq; +} + +/// Converts time in milliseconds to CPU cycle count. +/// +/// \param msecs Number of milliseconds. +/// +/// \return Equivalent number of CPU cycles. +static inline uint64_t +xos_msecs_to_cycles(uint64_t msecs) +{ + return (msecs * xos_clock_freq) / 1000; +} + +/// Converts time in microseconds to CPU cycle count. +/// +/// \param usecs Number of microseconds. +/// +/// \return Equivalent number of CPU cycles. +static inline uint64_t +xos_usecs_to_cycles(uint64_t usecs) +{ + return (usecs * xos_clock_freq) / 1000000; +} +///@} + + +//----------------------------------------------------------------------------- +/// +/// Set system clock frequency. This is expected to be set only once, and only +/// if the clock frequency is not known at compile time. +/// +/// \param freq Frequency in cycles per second. +/// +/// \return Returns nothing. +/// +//----------------------------------------------------------------------------- +static inline void +xos_set_clock_freq(uint32_t freq) +{ + xos_clock_freq = freq; +} + + +//----------------------------------------------------------------------------- +/// +/// Get current system clock frequency. +/// +/// \return Returns current system clock frequency in cycles per second. +/// +//----------------------------------------------------------------------------- +static inline uint32_t +xos_get_clock_freq() +{ + return xos_clock_freq; +} + + +//----------------------------------------------------------------------------- +/// +/// Initialize timer support and start the system timer. +/// This function must be called before calling any other timer function. +/// +/// NOTE: The smaller the tick period, the more precisely delays can be +/// specified using timers. However, we also need to make the tick period +/// large enough to allow time both to execute the tick timer interrupt handler +/// and for the application to make reasonable forward progress. If tick_period +/// is too small, the timer interrupt may re-trigger before the timer interrupt +/// handler has returned to the application, thus keeping the processor busy in +/// constantly executing the timer interrupt handler without leaving any cycles +/// for the application. Or, the application might get some cycles but only a +/// fraction of what is spent in the timer interrupt handler, thus severely +/// impacting application performance. +/// +/// The exact number of cycles needed to execute the timer interrupt handler +/// is not specified here. It depends on many factors (e.g. use of caches, +/// various processor configuration options, etc) and can vary by orders of +/// magnitude. Also note that the time to execute this handler is variable: +/// when timers expire upon a given tick timer interrupt, their respective +/// timer handler functions are called from within the interrupt handler. +/// +/// \param timer_num Which Xtensa timer to use (0..2). This timer +/// must exist and be configured at level 1 or at a +/// medium-priority interrupt level (<=EXCM_LEVEL). +/// If 'timer_num' is -1, then this function will +/// automatically choose the highest priority timer +/// that is suitable for use. This value will be +/// passed to xos_system_timer_select(). +/// +/// \param tick_period Number of clock (CCOUNT) cycles between ticks. +/// Must range between 0 and UINT32_MAX. +/// Zero is used to specify dynamic tick (tickless) +/// mode. +/// +/// \return Returns XOS_OK on success, else error code. +/// +//----------------------------------------------------------------------------- +int32_t +xos_start_system_timer(int32_t timer_num, uint32_t tick_period); + + +//----------------------------------------------------------------------------- +/// +/// Get the timer number of the system timer. Useful mainly when XOS has been +/// allowed to choose its own timer via xos_start_system_timer(). Not valid if +/// called before the system timer has been started. +/// +/// \return Returns one of XOS_SYS_TIMER_0, XOS_SYS_TIMER_1, XOS_SYS_TIMER_2 +/// or XOS_SYS_TIMER_EXTERNAL, or XOS_SYS_TIMER_NONE. +/// +//----------------------------------------------------------------------------- +int32_t +xos_get_system_timer_num(void); + + +//----------------------------------------------------------------------------- +/// +/// Initialize timer object. +/// +/// \param timer Pointer to timer event structure. +/// +/// \return Returns nothing. +/// +/// NOTE: This function should not be called on a timer object once it has +/// been activated. +/// +//----------------------------------------------------------------------------- +void xos_timer_init(XosTimer * timer); + + +//----------------------------------------------------------------------------- +// Flags for xos_timer_start(). +//----------------------------------------------------------------------------- +#define XOS_TIMER_DELTA 0x0000 +#define XOS_TIMER_PERIODIC 0x0001 +#define XOS_TIMER_ABSOLUTE 0x0002 +#define XOS_TIMER_FROM_NOW 0x0000 +#define XOS_TIMER_FROM_LAST 0x0010 + + +//----------------------------------------------------------------------------- +/// +/// Start the timer, and when the timer expires, call the specified function +/// (invoke (*fn)(arg)). If the timer is periodic, it will be automatically +/// restarted when it expires. +/// +/// The specified timer event structure must have been initialized before +/// first use by calling xos_timer_init(). +/// +/// The callback function will be called in an interrupt context. Hence it is +/// NOT safe to use any coprocessors in the function, including the FPU. If a +/// coprocessor must be used, then its state must be saved and restored across +/// its use. +/// +/// NOTE: If you are using the timer only to wait on (via xos_timer_wait()) +/// then it is not necessary to specify a callback function. You should pass +/// NULL for the callback function and zero for the callback argument. +/// +/// \param timer Pointer to timer event structure. Must have been +/// initialized. May be active or not. +/// +/// \param when When to call the function (see flags). +/// +/// \param flags Set of option flags XOS_TIMER_* \n +/// The following flags are mutually exclusive: +/// - XOS_TIMER_DELTA -- when is number of cycles from +/// [see below] (default) +/// - XOS_TIMER_PERIODIC -- when is number of cycles +/// from [see below], and timer continually +/// re-triggers at that interval +/// - XOS_TIMER_ABSOLUTE -- when is absolute value of +/// cycle count \n +/// \n +/// The following flags are mutually exclusive: +/// - XOS_TIMER_FROM_NOW -- *DELTA and *PERIODIC are +/// relative to now (default) +/// - XOS_TIMER_FROM_LAST -- *DELTA and *PERIODIC are +/// relative to the timer event's last specified expiry +/// time (usually in the future if active, in the past +/// if not, absolute 0 if was never activated). +/// +/// \param func Function to call (called in timer interrupt context). +/// This argument is optional. Specify NULL if no function +/// is to be called. +/// +/// \param arg Argument passed to callback function. Only relevant if +/// 'func' is not NULL. +/// +/// \return Returns XOS_OK on success, else error code. +/// +//----------------------------------------------------------------------------- +int32_t +xos_timer_start(XosTimer * timer, + uint64_t when, + uint32_t flags, + XosTimerFunc * func, + void * arg); + + +//----------------------------------------------------------------------------- +/// +/// Stop the timer and remove it from the list of active timers. Has no effect +/// if the timer is not active. Any waiting threads are woken up. +/// +/// The timer structure must have been initialized at least once, else its +/// contents are undefined and can lead to unpredictable results. +/// +/// \param timer Pointer to timer object. +/// +/// \return Returns XOS_OK on success, else error code. +/// +//----------------------------------------------------------------------------- +int32_t +xos_timer_stop(XosTimer * timer); + + +//----------------------------------------------------------------------------- +/// +/// Reset and restart the timer. +/// +/// The timer is reset to go off at time "when" from now. If the timer was not +/// active, it will be activated. If the timer was active, it will be restarted. +/// If the timer is periodic, the period will be set to "when". +/// The timer object must have been initialized at some point before this call. +/// +/// \param timer Pointer to timer object. +/// +/// \param when Number of cycles from now that the timer will expire. +/// +/// \return Returns XOS_OK on success, else error code. +/// +//----------------------------------------------------------------------------- +int32_t +xos_timer_restart(XosTimer * timer, uint64_t when); + + +//----------------------------------------------------------------------------- +/// +/// Check if the timer is active. The timer is active if it has been started +/// and not yet expired or canceled. +/// +/// \param timer Pointer to timer object. +/// +/// \return Returns non-zero if the timer is active, else zero. +/// +//----------------------------------------------------------------------------- +static inline int32_t +xos_timer_is_active(XosTimer * timer) +{ + return timer ? timer->active : 0; +} + + +//----------------------------------------------------------------------------- +/// +/// Get the repeat period for a periodic timer. For a one-shot timer this will +/// return zero. The period is reported in system clock cycles. +/// +/// \param timer Pointer to timer object. +/// +/// \return Returns period in cycles, or zero for non-periodic timers. +/// +//----------------------------------------------------------------------------- +static inline uint64_t +xos_timer_get_period(XosTimer * timer) +{ + return timer ? timer->delta : 0; +} + + +//----------------------------------------------------------------------------- +/// +/// Set the repeat period for a periodic timer. The period must be specified +/// in system clock cycles. +/// +/// If the timer is active, the change in period does not take effect until +/// the timer expires at least once after this call. +/// Note that setting a period of zero will effectively turn a periodic timer +/// into a one-shot timer. Similarly, a one-shot timer can be turned into a +/// periodic timer. +/// +/// \param timer Pointer to timer object. +/// +/// \param period Repeat period in system clock cycles. +/// +/// \return Returns XOS_OK on success, else error code. +/// +//----------------------------------------------------------------------------- +int32_t +xos_timer_set_period(XosTimer * timer, uint64_t period); + + +//----------------------------------------------------------------------------- +/// +/// Get the current system cycle count. This accounts for the periodic rollover +/// of the 32-bit CCOUNT cycle counter and returns a 64-bit value. +/// +/// \return Returns the current system cycle count. +/// +//----------------------------------------------------------------------------- +static inline uint64_t +xos_get_system_cycles(void) +{ + extern uint64_t xos_system_cycles; + extern uint32_t xos_last_ccount; + + // xos_last_ccount was updated when xos_system_cycles was last updated. + // We need to add in the number of cycles elapsed since then. + return xos_system_cycles + (xos_get_ccount() - xos_last_ccount); +} + + +//----------------------------------------------------------------------------- +/// +/// Put calling thread to sleep for at least the specified number of cycles. +/// The actual number of cycles spent sleeping may be larger depending upon +/// the granularity of the system timer. Once the specified time has elapsed +/// the thread will be woken and made ready. +/// +/// \param cycles Number of system clock cycles to sleep. +/// +/// \return Returns XOS_OK on success, else error code. +/// +//----------------------------------------------------------------------------- +int32_t +xos_thread_sleep(uint64_t cycles); + + +//----------------------------------------------------------------------------- +/// +/// Put calling thread to sleep for at least the specified number of msec. +/// The actual amount of time spent sleeping may be larger depending upon +/// the granularity of the system timer. Once the specified time has elapsed +/// the thread will be woken and made ready. +/// +/// \return msecs The number of milliseconds to sleep. +/// +/// \return Returns XOS_OK on success, else error code. +/// +//----------------------------------------------------------------------------- +static inline int32_t +xos_thread_sleep_msec(uint64_t msecs) +{ + return xos_thread_sleep(xos_msecs_to_cycles(msecs)); +} + + +//----------------------------------------------------------------------------- +/// +/// Put calling thread to sleep for at least the specified number of usec. +/// The actual amount of time spent sleeping may be larger depending upon +/// the granularity of the system timer. Once the specified time has elapsed +/// the thread will be woken and made ready. +/// +/// \return usecs The number of microseconds to sleep. +/// +/// \return Returns XOS_OK on success, else error code. +/// +//----------------------------------------------------------------------------- +static inline int32_t +xos_thread_sleep_usec(uint64_t usecs) +{ + return xos_thread_sleep(xos_usecs_to_cycles(usecs)); +} + + +//----------------------------------------------------------------------------- +/// +/// Wait on a timer until it expires or is cancelled. The calling thread will +/// be blocked. The timer must be active. +/// NOTE: This operation is only available if XOS_OPT_TIMER_WAIT is set +/// to 1 in the configuration options. +/// +/// \param timer Pointer to timer object. +/// +/// \return Returns XOS_OK on normal timeout, else an error code. +/// +//----------------------------------------------------------------------------- +int32_t +xos_timer_wait(XosTimer * timer); + + +//----------------------------------------------------------------------------- +// System timer control interface. +//----------------------------------------------------------------------------- + + +//----------------------------------------------------------------------------- +// Defines for system timer ID. +//----------------------------------------------------------------------------- +#define XOS_SYS_TIMER_0 0 ///< Internal timer 0 +#define XOS_SYS_TIMER_1 1 ///< Internal timer 1 +#define XOS_SYS_TIMER_2 2 ///< Internal timer 2 +#define XOS_SYS_TIMER_EXTERNAL -2 ///< External timer +#define XOS_SYS_TIMER_NONE -1 ///< No system timer selected + + +//----------------------------------------------------------------------------- +/// +/// This function handles XOS timer tick processing. It must be called by the +/// timer interrupt handler on every timer interrupt. This function computes +/// the time to the next tick and sets it up by calling xos_system_timer_set(). +/// +//----------------------------------------------------------------------------- +void +xos_tick_handler(void); + + +//----------------------------------------------------------------------------- +/// +/// Selects the timer to use. The selection may be one of the internal timers +/// or an external timer. The default implementation selects an internal timer. +/// This function can be overridden to provide custom timer processing or to +/// support an external timer. +/// +/// \param timer_num The internal timer number to select (0-2) or +/// -1 to auto-select a timer. This parameter can +/// be ignored by custom implementations that use +/// an external timer. +/// +/// \param psel Pointer to a location where the selected timer +/// ID must be returned. The timer ID must be one +/// of XOS_SYS_TIMER_0, XOS_SYS_TIMER_1, XOS_SYS_TIMER_2 +/// or XOS_SYS_TIMER_EXTERNAL. +/// +/// \return Returns XOS_OK on success, else error code. +/// +//----------------------------------------------------------------------------- +int32_t +xos_system_timer_select(int32_t timer_num, int32_t *psel); + + +//----------------------------------------------------------------------------- +/// +/// Starts the system timer and sets up the first interrupt. This function can +/// be overridden to provide custom timer processing or to support an external +/// timer. +/// +/// \param cycles The number of CPU cycles from now when the +/// first interrupt must occur. +/// +//----------------------------------------------------------------------------- +void +xos_system_timer_init(uint32_t cycles); + + +//----------------------------------------------------------------------------- +/// +/// Sets the next trigger value of the system timer. The parameter 'cycles' is +/// the number of CPU cycles from now when the interrupt must occur. +/// This function can be overridden to provide custom timer processing or to +/// support an external timer. +/// +/// \param cycles The number of CPU cycles from now when the +/// next interrupt must occur. +/// +//----------------------------------------------------------------------------- +void +xos_system_timer_set(uint32_t cycles); + + +#ifdef __cplusplus +} +#endif + +#endif // __XOS_TIMER_H__ + diff --git a/tools/sdk/include/esp32/xtensa/xos_types.h b/tools/sdk/include/esp32/xtensa/xos_types.h new file mode 100755 index 00000000..a913b94a --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/xos_types.h @@ -0,0 +1,75 @@ +/** @file */ +// xos_types.h - XOS type definitions. + +// Copyright (c) 2003-2015 Cadence Design Systems, Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +// NOTE: Do not include this file directly in your application. Including +// xos.h will automatically include this file. + + +#ifndef __XOS_TYPES_H__ +#define __XOS_TYPES_H__ + +#if !defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__) + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +//----------------------------------------------------------------------------- +// The following are defined here because of the variations in the C libraries +// that we need to work with. +// - Not all of them have stdbool.h +// - Not all of them define NULL as (void *)0 +//----------------------------------------------------------------------------- + + +//----------------------------------------------------------------------------- +/// +/// XOS define for NULL value. This makes the NULL value independent of the +/// C library (not all of them define NULL the same way). +/// +//----------------------------------------------------------------------------- +#define XOS_NULL ((void *)0) + + +//----------------------------------------------------------------------------- +/// +/// XOS definition of 'bool' type. Some C libraries do not support stdbool.h. +/// +//----------------------------------------------------------------------------- +#ifndef bool +#define bool int8_t +#define false 0 ///< XOS definition of 'false' +#define true 1 ///< XOS definition of 'true' +#endif + +#ifdef __cplusplus +} +#endif + +#endif // !defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__) + +#endif // __XOS_TYPES_H__ + diff --git a/tools/sdk/include/esp32/xtensa/xt_perf_consts.h b/tools/sdk/include/esp32/xtensa/xt_perf_consts.h new file mode 100755 index 00000000..f063a31f --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/xt_perf_consts.h @@ -0,0 +1,283 @@ +/* + * Customer ID=11656; Build=0x5f626; Copyright (c) 2012 by Tensilica Inc. ALL RIGHTS RESERVED. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef __XT_PERF_CONSTS_H__ +#define __XT_PERF_CONSTS_H__ + +/* + * Performance monitor counter selectors + */ + +#define XTPERF_CNT_COMMITTED_INSN 0x8002 /* Instructions committed */ +#define XTPERF_CNT_BRANCH_PENALTY 0x8003 /* Branch penalty cycles */ +#define XTPERF_CNT_PIPELINE_INTERLOCKS 0x8004 /* Pipeline interlocks cycles */ +#define XTPERF_CNT_ICACHE_MISSES 0x8005 /* ICache misses penalty in cycles */ +#define XTPERF_CNT_DCACHE_MISSES 0x8006 /* DCache misses penalty in cycles */ + +#define XTPERF_CNT_CYCLES 0 /* Count cycles */ +#define XTPERF_CNT_OVERFLOW 1 /* Overflow of counter n-1 (assuming this is counter n) */ +#define XTPERF_CNT_INSN 2 /* Successfully completed instructions */ +#define XTPERF_CNT_D_STALL 3 /* Data-related GlobalStall cycles */ +#define XTPERF_CNT_I_STALL 4 /* Instruction-related and other GlobalStall cycles */ +#define XTPERF_CNT_EXR 5 /* Exceptions and pipeline replays */ +#define XTPERF_CNT_BUBBLES 6 /* Hold and other bubble cycles */ +#define XTPERF_CNT_I_TLB 7 /* Instruction TLB Accesses (per instruction retiring) */ +#define XTPERF_CNT_I_MEM 8 /* Instruction memory accesses (per instruction retiring) */ +#define XTPERF_CNT_D_TLB 9 /* Data TLB accesses */ +#define XTPERF_CNT_D_LOAD_U1 10 /* Data memory load instruction (load-store unit 1) */ +#define XTPERF_CNT_D_STORE_U1 11 /* Data memory store instruction (load-store unit 1) */ +#define XTPERF_CNT_D_ACCESS_U1 12 /* Data memory accesses (load, store, S32C1I, etc; load-store unit 1) */ +#define XTPERF_CNT_D_LOAD_U2 13 /* Data memory load instruction (load-store unit 2) */ +#define XTPERF_CNT_D_STORE_U2 14 /* Data memory store instruction (load-store unit 2) */ +#define XTPERF_CNT_D_ACCESS_U2 15 /* Data memory accesses (load, store, S32C1I, etc; load-store unit 2) */ +#define XTPERF_CNT_D_LOAD_U3 16 /* Data memory load instruction (load-store unit 3) */ +#define XTPERF_CNT_D_STORE_U3 17 /* Data memory store instruction (load-store unit 3) */ +#define XTPERF_CNT_D_ACCESS_U3 18 /* Data memory accesses (load, store, S32C1I, etc; load-store unit 3) */ +#define XTPERF_CNT_MULTIPLE_LS 22 /* Multiple Load/Store */ +#define XTPERF_CNT_OUTBOUND_PIF 23 /* Outbound PIF transactions */ +#define XTPERF_CNT_INBOUND_PIF 24 /* Inbound PIF transactions */ +#define XTPERF_CNT_PREFETCH 26 /* Prefetch events */ + + +/* + * Masks for each of the selector listed above + */ + +/* XTPERF_CNT_COMMITTED_INSN selector mask */ + +#define XTPERF_MASK_COMMITTED_INSN 0x0001 + +/* XTPERF_CNT_BRANCH_PENALTY selector mask */ + +#define XTPERF_MASK_BRANCH_PENALTY 0x0001 + +/* XTPERF_CNT_PIPELINE_INTERLOCKS selector mask */ + +#define XTPERF_MASK_PIPELINE_INTERLOCKS 0x0001 + +/* XTPERF_CNT_ICACHE_MISSES selector mask */ + +#define XTPERF_MASK_ICACHE_MISSES 0x0001 + +/* XTPERF_CNT_DCACHE_MISSES selector mask */ + +#define XTPERF_MASK_DCACHE_MISSES 0x0001 + +/* XTPERF_CNT_CYCLES selector mask */ + +#define XTPERF_MASK_CYCLES 0x0001 + +/* XTPERF_CNT_OVERFLOW selector mask */ + +#define XTPERF_MASK_OVERFLOW 0x0001 + +/* + * XTPERF_CNT_INSN selector mask + */ + +#define XTPERF_MASK_INSN_ALL 0x8DFF + +#define XTPERF_MASK_INSN_JX 0x0001 /* JX */ +#define XTPERF_MASK_INSN_CALLX 0x0002 /* CALLXn */ +#define XTPERF_MASK_INSN_RET 0x0004 /* call return i.e. RET, RETW */ +#define XTPERF_MASK_INSN_RF 0x0008 /* supervisor return i.e. RFDE, RFE, RFI, RFWO, RFWU */ +#define XTPERF_MASK_INSN_BRANCH_TAKEN 0x0010 /* Conditional branch taken, or loopgtz/loopnez skips loop */ +#define XTPERF_MASK_INSN_J 0x0020 /* J */ +#define XTPERF_MASK_INSN_CALL 0x0040 /* CALLn */ +#define XTPERF_MASK_INSN_BRANCH_NOT_TAKEN 0x0080 /* Conditional branch fall through (aka. not-taken branch) */ +#define XTPERF_MASK_INSN_LOOP_TAKEN 0x0100 /* Loop instr falls into loop (aka. taken loop) */ +#define XTPERF_MASK_INSN_LOOP_BEG 0x0400 /* Loopback taken to LBEG */ +#define XTPERF_MASK_INSN_LOOP_END 0x0800 /* Loopback falls through to LEND */ +#define XTPERF_MASK_INSN_NON_BRANCH 0x8000 /* Non-branch instruction (aka. non-CTI) */ + +/* + * XTPERF_CNT_D_STALL selector mask + */ + +#define XTPERF_MASK_D_STALL_ALL 0x01FE + +#define XTPERF_MASK_D_STALL_STORE_BUF_FULL 0x0002 /* Store buffer full stall */ +#define XTPERF_MASK_D_STALL_STORE_BUF_CONFLICT 0x0004 /* Store buffer conflict stall */ +#define XTPERF_MASK_D_STALL_CACHE_MISS 0x0008 /* DCache-miss stall */ +#define XTPERF_MASK_D_STALL_BUSY 0x0010 /* Data RAM/ROM/XLMI busy stall */ +#define XTPERF_MASK_D_STALL_IN_PIF 0x0020 /* Data inbound-PIF request stall (incl s32c1i) */ +#define XTPERF_MASK_D_STALL_MHT_LOOKUP 0x0040 /* MHT lookup stall */ +#define XTPERF_MASK_D_STALL_UNCACHED_LOAD 0x0080 /* Uncached load stall (included in MHT lookup stall) */ +#define XTPERF_MASK_D_STALL_BANK_CONFLICT 0x0100 /* Bank-conflict stall */ + +/* + * XTPERF_CNT_I_STALL selector mask + */ + +#define XTPERF_MASK_I_STALL_ALL 0x01FF + +#define XTPERF_MASK_I_STALL_CACHE_MISS 0x0001 /* ICache-miss stall */ +#define XTPERF_MASK_I_STALL_BUSY 0x0002 /* Instruction RAM/ROM busy stall */ +#define XTPERF_MASK_I_STALL_IN_PIF 0x0004 /* Instruction RAM inbound-PIF request stall */ +#define XTPERF_MASK_I_STALL_TIE_PORT 0x0008 /* TIE port stall */ +#define XTPERF_MASK_I_STALL_EXTERNAL_SIGNAL 0x0010 /* External RunStall signal status */ +#define XTPERF_MASK_I_STALL_UNCACHED_FETCH 0x0020 /* Uncached fetch stall */ +#define XTPERF_MASK_I_STALL_FAST_L32R 0x0040 /* FastL32R stall */ +#define XTPERF_MASK_I_STALL_ITERATIVE_MUL 0x0080 /* Iterative multiply stall */ +#define XTPERF_MASK_I_STALL_ITERATIVE_DIV 0x0100 /* Iterative divide stall */ + +/* + * XTPERF_CNT_EXR selector mask + */ + +#define XTPERF_MASK_EXR_ALL 0x01FF + +#define XTPERF_MASK_EXR_REPLAYS 0x0001 /* Other Pipeline Replay (i.e. excludes $ miss etc.) */ +#define XTPERF_MASK_EXR_LEVEL1_INT 0x0002 /* Level-1 interrupt */ +#define XTPERF_MASK_EXR_LEVELH_INT 0x0004 /* Greater-than-level-1 interrupt */ +#define XTPERF_MASK_EXR_DEBUG 0x0008 /* Debug exception */ +#define XTPERF_MASK_EXR_NMI 0x0010 /* NMI */ +#define XTPERF_MASK_EXR_WINDOW 0x0020 /* Window exception */ +#define XTPERF_MASK_EXR_ALLOCA 0x0040 /* Alloca exception */ +#define XTPERF_MASK_EXR_OTHER 0x0080 /* Other exceptions */ +#define XTPERF_MASK_EXR_MEM_ERR 0x0100 /* HW-corrected memory error */ + +/* + * XTPERF_CNT_BUBBLES selector mask + */ + +#define XTPERF_MASK_BUBBLES_ALL 0x01FD + +#define XTPERF_MASK_BUBBLES_PSO 0x0001 /* Processor domain PSO bubble */ +#define XTPERF_MASK_BUBBLES_R_HOLD_D_CACHE_MISS 0x0004 /* R hold caused by DCache miss */ +#define XTPERF_MASK_BUBBLES_R_HOLD_STORE_RELEASE 0x0008 /* R hold caused by Store release */ +#define XTPERF_MASK_BUBBLES_R_HOLD_REG_DEP 0x0010 /* R hold caused by register dependency */ +#define XTPERF_MASK_BUBBLES_R_HOLD_WAIT 0x0020 /* R hold caused by MEMW, EXTW or EXCW */ +#define XTPERF_MASK_BUBBLES_R_HOLD_HALT 0x0040 /* R hold caused by Halt instruction (TX only) */ +#define XTPERF_MASK_BUBBLES_CTI 0x0080 /* CTI bubble (e.g. branch delay slot) */ +#define XTPERF_MASK_BUBBLES_WAITI 0x0100 /* WAITI bubble */ + +/* + * XTPERF_CNT_I_TLB selector mask + */ + +#define XTPERF_MASK_I_TLB_ALL 0x000F + +#define XTPERF_MASK_I_TLB_HITS 0x0001 /* Hit */ +#define XTPERF_MASK_I_TLB_REPLAYS 0x0002 /* Replay of instruction due to ITLB miss */ +#define XTPERF_MASK_I_TLB_REFILLS 0x0004 /* HW-assisted TLB Refill completes */ +#define XTPERF_MASK_I_TLB_MISSES 0x0008 /* ITLB Miss Exception */ + +/* + * XTPERF_CNT_I_MEM selector mask + */ + +#define XTPERF_MASK_I_MEM_ALL 0x000F + +#define XTPERF_MASK_I_MEM_CACHE_HITS 0x0001 /* ICache Hit */ +#define XTPERF_MASK_I_MEM_CACHE_MISSES 0x0002 /* ICache Miss (includes uncached) */ +#define XTPERF_MASK_I_MEM_IRAM 0x0004 /* InstRAM or InstROM */ +#define XTPERF_MASK_I_MEM_BYPASS 0x0008 /* Bypass (i.e. uncached) fetch */ + +/* + * XTPERF_CNT_D_TLB selector mask + */ + +#define XTPERF_MASK_D_TLB_ALL 0x000F + +#define XTPERF_MASK_D_TLB_HITS 0x0001 /* Hit */ +#define XTPERF_MASK_D_TLB_REPLAYS 0x0002 /* Replay of instruction due to DTLB miss */ +#define XTPERF_MASK_D_TLB_REFILLS 0x0004 /* HW-assisted TLB Refill completes */ +#define XTPERF_MASK_D_TLB_MISSES 0x0008 /* DTLB Miss Exception */ + +/* + * XTPERF_CNT_D_LOAD_U* selector mask + */ + +#define XTPERF_MASK_D_LOAD_ALL 0x000F + +#define XTPERF_MASK_D_LOAD_CACHE_HITS 0x0001 /* Cache Hit */ +#define XTPERF_MASK_D_LOAD_CACHE_MISSES 0x0002 /* Cache Miss */ +#define XTPERF_MASK_D_LOAD_LOCAL_MEM 0x0004 /* Local memory hit */ +#define XTPERF_MASK_D_LOAD_BYPASS 0x0008 /* Bypass (i.e. uncached) load */ + +/* + * XTPERF_CNT_D_STORE_U* selector mask + */ + +#define XTPERF_MASK_D_STORE_ALL 0x000F + +#define XTPERF_MASK_D_STORE_CACHE_HITS 0x0001 /* DCache Hit */ +#define XTPERF_MASK_D_STORE_CACHE_MISSES 0x0002 /* DCache Miss */ +#define XTPERF_MASK_D_STORE_LOCAL_MEM 0x0004 /* Local memory hit */ +#define XTPERF_MASK_D_STORE_PIF 0x0008 /* PIF Store */ + +/* + * XTPERF_CNT_D_ACCESS_U* selector mask + */ + +#define XTPERF_MASK_D_ACCESS_ALL 0x000F + +#define XTPERF_MASK_D_ACCESS_CACHE_MISSES 0x0001 /* DCache Miss */ +#define XTPERF_MASK_D_ACCESS_HITS_SHARED 0x0002 /* Hit Shared */ +#define XTPERF_MASK_D_ACCESS_HITS_EXCLUSIVE 0x0004 /* Hit Exclusive */ +#define XTPERF_MASK_D_ACCESS_HITS_MODIFIED 0x0008 /* Hit Modified */ + +/* + * XTPERF_CNT_MULTIPLE_LS selector mask + */ + +#define XTPERF_MASK_MULTIPLE_LS_ALL 0x003F + +#define XTPERF_MASK_MULTIPLE_LS_0S_0L 0x0001 /* 0 stores and 0 loads */ +#define XTPERF_MASK_MULTIPLE_LS_0S_1L 0x0002 /* 0 stores and 1 loads */ +#define XTPERF_MASK_MULTIPLE_LS_1S_0L 0x0004 /* 1 stores and 0 loads */ +#define XTPERF_MASK_MULTIPLE_LS_1S_1L 0x0008 /* 1 stores and 1 loads */ +#define XTPERF_MASK_MULTIPLE_LS_0S_2L 0x0010 /* 0 stores and 2 loads */ +#define XTPERF_MASK_MULTIPLE_LS_2S_0L 0x0020 /* 2 stores and 0 loads */ + +/* + * XTPERF_CNT_OUTBOUND_PIF selector mask + */ + +#define XTPERF_MASK_OUTBOUND_PIF_ALL 0x0003 + +#define XTPERF_MASK_OUTBOUND_PIF_CASTOUT 0x0001 /* Castout */ +#define XTPERF_MASK_OUTBOUND_PIF_PREFETCH 0x0002 /* Prefetch */ + +/* + * XTPERF_CNT_INBOUND_PIF selector mask + */ + +#define XTPERF_MASK_INBOUND_PIF_ALL 0x0003 + +#define XTPERF_MASK_INBOUND_PIF_I_DMA 0x0001 /* Instruction DMA */ +#define XTPERF_MASK_INBOUND_PIF_D_DMA 0x0002 /* Data DMA */ + +/* + * XTPERF_CNT_PREFETCH selector mask + */ + +#define XTPERF_MASK_PREFETCH_ALL 0x002F + +#define XTPERF_MASK_PREFETCH_I_HIT 0x0001 /* I prefetch-buffer-lookup hit */ +#define XTPERF_MASK_PREFETCH_D_HIT 0x0002 /* D prefetch-buffer-lookup hit */ +#define XTPERF_MASK_PREFETCH_I_MISS 0x0004 /* I prefetch-buffer-lookup miss */ +#define XTPERF_MASK_PREFETCH_D_MISS 0x0008 /* D prefetch-buffer-lookup miss */ +#define XTPERF_MASK_PREFETCH_D_L1_FILL 0x0020 /* Fill directly to DCache L1 */ + +#endif /* __XT_PERF_CONSTS_H__ */ diff --git a/tools/sdk/include/esp32/xtensa/xt_perfmon.h b/tools/sdk/include/esp32/xtensa/xt_perfmon.h new file mode 100755 index 00000000..959052b1 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/xt_perfmon.h @@ -0,0 +1,183 @@ +/* + * Customer ID=11656; Build=0x5f626; Copyright (c) 2012 by Tensilica Inc. ALL RIGHTS RESERVED. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef __XT_PERFMON_H__ +#define __XT_PERFMON_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef int counter_id_t; + +/* xt_perf_init + + Initialize the performance monitor library. Ordinarily, this + function is called automatically via the .init section. If your + environment does not support the .init section, you will need to + call this function from your code. +*/ + +extern void xt_perf_init(void); + +/* xt_perf_enable + + Turn on the performance monitor. Ordinarily, counting is off by + default. If you turn off performance monitor using xt_perf_disable or + by call to a function that disables performance monitor, you can turn + it on again via this function. +*/ + +extern void xt_perf_enable(void); + +/* xt_perf_disable + + Turn off the performance monitor. If you want to suspend counting + events for a portion of your code, use this function and then call + xt_perf_enable when you want to start again. +*/ + +extern void xt_perf_disable(void); + +/* xt_perf_clear + + Disable performance monitor and clear all initialized hardware counters. + All counter ids are invalid after call to this function and all hardware + counters available for initialization. +*/ + +extern void xt_perf_clear (void); + +/* xt_perf_counters_num + + Returns number of free hardware performance counters. After call to xt_perf_clear + all counters are free and available for initialization. With each successful + xt_perf_init_counter/xt_perf_init_event call this number is decreasing until + no free counters available. +*/ + +extern int xt_perf_counters_num (void); + +/* xt_perf_init_counter32 + + Setup 32 bit performance counter. This function disables performance monitor + if it was enabled. + + Returns zero based counter id on success or negative value if failed. + This function may fail if there is insufficient number of free hardware + counters or function arguments are invalid. + + The counter id returned on success can be used with xt_perf_reset_counter + and xt_perf_counter32 functions. + + - events group, one of XTPERF_CNT constants defined in + xt_perf_consts.h; + - events mask for selected group. Mask bit fields for each + selector defined with XTPERF_MASK prefix in xt_perf_consts.h; + - specifies interrupt levels at which to count events; + if trace_level is greater or equal to zero events are + counted only at interrupt levels below or equal to + trace_level; if trace_level is negative events are + counted only at (-trace_level) interrupt level or higher. +*/ + + +extern counter_id_t xt_perf_init_counter32 ( unsigned int selector, + unsigned int mask, + int trace_level); + +/* xt_perf_init_counter64 + + Setup 64 bit performance counter. Library emulates 64 bit counters by handling + profiling interrupt and recording overflows of 32 bit hardware counters. + This function disables performance monitor if it was enabled. + + Returns zero based counter id on success or negative value if failed. + This function may fail if there is insufficient number of free hardware + counters or function arguments are invalid. + + The counter id returned on success can be used with xt_perf_reset_counter + and xt_perf_counter64 functions. + + - events group, one of XTPERF_CNT constants defined in + xt_perf_consts.h; + - events mask for selected group. Mask bit fields for each + selector defined with XTPERF_MASK prefix in xt_perf_consts.h; + - specifies interrupt levels at which to count events; + if trace_level is greater or equal to zero events are + counted only at interrupt levels below or equal to + trace_level; if trace_level is negative events are + counted only at (-trace_level) interrupt level or higher. +*/ + +extern counter_id_t xt_perf_init_counter64 ( unsigned int selector, + unsigned int mask, + int trace_level); + +/* xt_perf_reset_counter + + Reset counter value to 0. + Returns zero on success or non zero if failed. +*/ + +extern int xt_perf_reset_counter (counter_id_t counter_id); + +/* xt_perf_counter32 + + Read 32 bit counter value. + + Returns zero if counter id is not valid. +*/ + +extern unsigned int xt_perf_counter32 (counter_id_t counter_id); + +/* xt_perf_counter64 + + Read 64 bit counter value. + + Counter must be initialized using xt_perf_init_counter64 function. + + Returns zero if counter id is not valid. +*/ + +extern unsigned long long xt_perf_counter64 (counter_id_t counter_id); + + /* xt_perf_overflow32 + + Read overflow flag of 32 bit counter. This flag is dropped when + counter initialized or reset. Once counter overflows and wraps + around the flag is set and stays set until counter reset. + + Returns negative value if counter id is invalid, zero if counter + not overflowed, positive if in overflowed state. + */ + +extern int xt_perf_overflow32 (counter_id_t counter_id); + +#ifdef __cplusplus +} +#endif + +#endif /* __XT_PERFMON_H__ */ diff --git a/tools/sdk/include/esp32/xtensa/xt_profiling.h b/tools/sdk/include/esp32/xtensa/xt_profiling.h new file mode 100755 index 00000000..650713a4 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/xt_profiling.h @@ -0,0 +1,233 @@ +/* + * Customer ID=11656; Build=0x5f626; Copyright (c) 2005-2012 by Tensilica Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of Tensilica Inc. + * They may not be modified, copied, reproduced, distributed, or disclosed to + * third parties in any manner, medium, or form, in whole or in part, without + * the prior written consent of Tensilica Inc. + */ + +#ifndef __XT_PROFILER_H__ +#define __XT_PROFILER_H__ + +#include + +#if XCHAL_NUM_PERF_COUNTERS +/* Performance monitor counters constants */ +#include + +#endif /* XCHAL_NUM_PERF_COUNTERS */ + + +#ifdef __cplusplus +extern "C" { +#endif + +/* This file defines an interface that allows a program being profiled + to control when and how it is profiled, whether it is running under + the instruction set simulator or under the hardware profiler. + + Both ISS and HWP implement this interface, although in different + ways. Both also do the right thing if you don't call any of these + functions. +*/ + + +/* +xt_profile_init + + ISS: a no op. + + HWP: Initialize the profiler. Ordinarily, this function is called + automatically via the .init section. If your environment does not + support the .init section, you will need to call this function + by hand. +*/ +extern void xt_profile_init(void); + +/* +xt_profile_add_memory + + ISS: a no op. + + HWP: + Makes "buf_size" bytes at "buf" available to the hardware profiler. + This buffer should be initialized to zeros prior to this call. + + The hardware profiler has already estimated the amount of memory it needs, + but under certain circumstances may still run out of memory. If so, you can + provide more memory with this routine. + +*/ +extern void xt_profile_add_memory(void * buf, unsigned int buf_size); + + +/* xt_profile_enable + + Turn on the profiler. Ordinarily, profiling is on by default. + If you turn off profiling using xt_profile_disable, You can turn + it on again via this function. +*/ +extern void xt_profile_enable(void); + +/* xt_profile_disable + + Turn off the profiler. If you don't want to profile a portion of your code, + use this function and then xt_profile_enable when you want to start again. +*/ +extern void xt_profile_disable(void); + +/* xt_profile_save_and_reset + + Save and reset the profiler's data. + If there were errors, either during profiling or while attempting to + write the data, no data will be written and this function will + return non-zero. + +*/ +extern int xt_profile_save_and_reset(void); + +/* xt_profile_get_frequency + + ISS: always returns 1. + + HWP: + Returns the number of cycles between samples for timer based profiler. + In performance counters based profiler always returns 1. +*/ +extern unsigned int xt_profile_get_frequency(void); + +/* xt_profile_set_frequency + + ISS: a no op. + + HWP: + Set the number of cycles between samples for timer based profiler. + Ignored in performance counters based profiler. + + sample frequency is the number of cycles to wait between samples. It should + be a multiple of 1024. + + If you set the sample frequency to a different value than was passed in xt_profile_init, + then the labels in the output will reflect the later frequency, even though some samples may + have been taken at the earlier frequency. Typically this does not make a significant difference + in the results if this function is called early enough. +*/ +extern void xt_profile_set_frequency(unsigned int sample_frequency); + +/* xt_profile_num_errors + + ISS: always returns 0 + + HWP: + Returns the number of errors that occured while taking samples. Typically these + are out of memory errors and you need to pass a bigger buffer to + xt_profile_add_memory +*/ +extern int xt_profile_num_errors(void); + + +#if XCHAL_NUM_PERF_COUNTERS + + +/* xt_profile_randomize + + ISS: not available + + HWP: Available in performance monitor based profiler. + + Turns on or off sampling period randomization mode. Period randomization + helps to avoid aliasing problems when code being profiled is highly periodic. + Profiler maintains same average sampling period but individual sampling + steps may vary. + Period randomization is turned off by default. + + - non zero turns randomization on, + zero turns randomization off. +*/ + +extern void xt_profile_randomization(int value); + +/* xt_profile_config_clear + + ISS: not available + + HWP: Available in performance monitor based profiler. + + Stops profiling if it was enabled and clears performance counters + parameters. Accumulated profile data stays in memory and will be + saved when xt_profile_save_and_reset is called or at program exit. + Number of configured performance counters is zero after this + function call. +*/ + +extern void xt_profile_config_clear(void); + + +/* xt_profile_config_num + + ISS: not available + + HWP: Available in performance monitor based profiler. + + Returns number of free performance counters. +*/ + +extern int xt_profile_config_num(void); + + +/* xt_profile_config_counter error codes +*/ + +#define XTPROF_ERR_OUT_OF_MEM -1 +#define XTPROF_ERR_INVALID_ARGS -2 +#define XTPROF_ERR_NOT_ENOUGH_COUNTERS -3 +#define XTPROF_ERR_DEFUNCT -4 + +/* xt_profile_config_counter + + ISS: not available + + HWP: Available in performance monitor based profiler. + + Allocating and initializing one or more performance counter for sampling. + Even though event may require multiple performance counters allocated the + profile data for event is merged and dumped into single gmon file. + This function disables profiling if it was enabled. + + Returns 0 on success, non zero if failed: + XTPROF_ERR_OUT_OF_MEM - memory allocation failed; + XTPROF_ERR_INVALID_ARGS - invalid function parameters; + XTPROF_ERR_NOT_ENOUGH_COUNTERS - not enough free performance counters available; + XTPROF_ERR_DEFUNCT - profiling is disabled because of previous errors + (xt_profile_num_errors() is non zero) + + - events group, one of XTPERF_CNT constants defined in xt_perf_consts.h + - events mask for selected group. Mask bit fields for each + selector defined with XTPERF_MASK prefix in xt_perf_consts.h + - specifies interrupt levels at which to take samples; + if trace_level is greater or equal to zero samples are + taken only at interrupt levels below or equal to + trace_level; if trace_level is negative samples are taken + only at (-trace_level) interrupt level or higher. + - sampling period; 1 - record every event, 2 - record every + other event and so on; + Please note - there is overhead associated with events recording, + high frequency events may produce incorrect profile when period + is too small. +*/ + +extern int xt_profile_config_counter ( unsigned int selector, + unsigned int mask, + int trace_level, + unsigned int period); + + + +#endif /* XCHAL_NUM_PERF_COUNTERS */ + +#ifdef __cplusplus +} +#endif + +#endif /* __XT_PROFILER_H__ */ diff --git a/tools/sdk/include/esp32/xtensa/xt_reftb.h b/tools/sdk/include/esp32/xtensa/xt_reftb.h new file mode 100755 index 00000000..358c39f7 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/xt_reftb.h @@ -0,0 +1,86 @@ +/* + * Customer ID=11656; Build=0x5f626; Copyright (c) 2009-2013 by Tensilica Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of + * Tensilica Inc. They may be adapted and modified by bona fide + * purchasers for internal use, but neither the original nor any + * adapted or modified version may be disclosed or distributed to + * third parties in any manner, medium, or form, in whole or in part, + * without the prior written consent of Tensilica Inc. + * + * This software and its derivatives are to be executed solely on + * products incorporating a Tensilica processor. + */ + +// Utility routines for returning pass/fail status in HW simulations + +#ifndef XT_REF_TESTBENCH_H +#define XT_REF_TESTBENCH_H 1 + +#ifdef __cplusplus +extern "C" { +#endif + +// Exit routines for HW simulation +extern int diag_pass(); +extern int diag_fail(); + +// Set exit status for HW simulation +int set_diag_status(int stat); + +// Setup for user power toggling +extern int setup_power_toggle(); + +// Return exit status location +extern unsigned int* testbench_exit_location(); +// Return power toggle location +extern unsigned int* testbench_power_toggle_location(); + + +// Change exit status location +// You must also change the plusarg "+DVMagicExit" sent to the HW simulator +// or change the argument "--exit_location" sent to the ISS +extern unsigned int* set_testbench_exit_location(unsigned int*); +// Change power toggle location +// You must also change the plusarg "+DVPowerLoc" sent to the HW simulator +extern unsigned int* set_testbench_power_toggle_location(unsigned int*); + +// Exit routines with status message +// +static inline +int pass(const char *msg) +{ + return diag_pass(); +} + +static inline +int fail(const char *msg) +{ + return diag_fail(); +} + +#define POWER_TOGGLE_ON 1 +#define POWER_TOGGLE_OFF 0 + +// Routine to turn on and off power toggle +// Does a magic write that Monitors.v intercepts and appropriately turns +// SAIF dumping on and offf +// +extern volatile unsigned int *_reftb_power_toggle; + +__attribute__ ((always_inline)) +static inline +int set_power_toggle(int val) +{ +#ifdef __XTENSA__ + *_reftb_power_toggle = val; +#endif + return val; +} + +#ifdef __cplusplus +} +#endif + +#endif // XT_REF_TESTBENCH_H + diff --git a/tools/sdk/include/esp32/xtensa/xtav110.h b/tools/sdk/include/esp32/xtensa/xtav110.h new file mode 100755 index 00000000..23421f0b --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/xtav110.h @@ -0,0 +1,313 @@ +/* Copyright (c) 2007-2013 by Tensilica Inc. ALL RIGHTS RESERVED. +/ These coded instructions, statements, and computer programs are the +/ copyrighted works and confidential proprietary information of Tensilica Inc. +/ They may not be modified, copied, reproduced, distributed, or disclosed to +/ third parties in any manner, medium, or form, in whole or in part, without +/ the prior written consent of Tensilica Inc. +*/ + +/* xtav110.h - Xtensa Avnet LX110 (XT-AV110) board specific definitions */ + +#ifndef _INC_XTAV110_H_ +#define _INC_XTAV110_H_ + +#include +#include + +#define XTBOARD_NAME "XT-AV110" + + +/* + * Default assignment of XTAV110 devices to external interrupts. + */ + +/* Ethernet interrupt: */ +#ifdef XCHAL_EXTINT1_NUM +#define ETHERNET_INTNUM XCHAL_EXTINT1_NUM +#define ETHERNET_INTLEVEL XCHAL_EXTINT1_LEVEL +#define ETHERNET_INTMASK XCHAL_EXTINT1_MASK +#else +#define ETHERNET_INTMASK 0 +#endif + +/* UART interrupt: */ +#ifdef XCHAL_EXTINT0_NUM +#define UART16550_INTNUM XCHAL_EXTINT0_NUM +#define UART16550_INTLEVEL XCHAL_EXTINT0_LEVEL +#define UART16550_INTMASK XCHAL_EXTINT0_MASK +#else +#define UART16550_INTMASK 0 +#endif + +/* Audio output interrupt (I2S transmitter FIFO): */ +#ifdef XCHAL_EXTINT2_NUM +#define AUDIO_I2S_OUT_INTNUM XCHAL_EXTINT2_NUM +#define AUDIO_I2S_OUT_INTLEVEL XCHAL_EXTINT2_LEVEL +#define AUDIO_I2S_OUT_INTMASK XCHAL_EXTINT2_MASK +#else +#define AUDIO_I2S_OUT_INTMASK 0 +#endif + +/* Audio input interrupt (I2S receiver FIFO): */ +#ifdef XCHAL_EXTINT3_NUM +#define AUDIO_I2S_IN_INTNUM XCHAL_EXTINT3_NUM +#define AUDIO_I2S_IN_INTLEVEL XCHAL_EXTINT3_LEVEL +#define AUDIO_I2S_IN_INTMASK XCHAL_EXTINT3_MASK +#else +#define AUDIO_I2S_IN_INTMASK 0 +#endif + +/* I2C interrupt */ +#ifdef XCHAL_EXTINT4_NUM +#define I2C_INTNUM XCHAL_EXTINT4_NUM +#define I2C_INTLEVEL XCHAL_EXTINT4_LEVEL +#define I2C_INTMASK XCHAL_EXTINT4_MASK +#else +#define I2C_INTMASK 0 +#endif + +/* USB interrupt */ +#ifdef XCHAL_EXTINT5_NUM +#define USB_INTNUM XCHAL_EXTINT5_NUM +#define USB_INTLEVEL XCHAL_EXTINT5_LEVEL +#define USB_INTMASK XCHAL_EXTINT5_MASK +#else +#define USB_INTMASK 0 +#endif + +/* + * Device addresses. + * + * Note: for endianness-independence, use 32-bit loads and stores for all + * register accesses to Ethernet, UART and LED devices. Undefined bits + * may need to be masked out if needed when reading if the actual register + * size is smaller than 32 bits. + * + * Note: XTAV110 bus byte lanes are defined in terms of msbyte and lsbyte + * relative to the processor. So 32-bit registers are accessed consistently + * from both big and little endian processors. However, this means byte + * sequences are not consistent between big and little endian processors. + * This is fine for RAM, and for ROM if ROM is created for a specific + * processor (and thus has correct byte sequences). However this may be + * unexpected for Flash, which might contain a file-system that one wants + * to use for multiple processor configurations (eg. the Flash might contain + * the Ethernet card's address, endianness-independent application data, etc). + * That is, byte sequences written in Flash by a core of a given endianness + * will be byte-swapped when seen by a core of the other endianness. + * Someone implementing an endianness-independent Flash file system will + * likely handle this byte-swapping issue in the Flash driver software. + */ + +#define XTBOARD_FLASH_MAXSIZE 0x1000000 /* 16 MB */ + +#ifdef XSHAL_IOBLOCK_BYPASS_PADDR + +/* Flash Memory: */ +# define XTBOARD_FLASH_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x08000000) + +/* FPGA registers: */ +# define XTBOARD_FPGAREGS_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D020000) + +/* Ethernet controller/transceiver SONIC SN83934: */ +# define ETHERNET_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D030000) + + +/* UART National-Semi PC16550D: */ +# define UART16550_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D050000) + +/* I2S transmitter */ +# define AUDIO_I2S_OUT_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D080000) + +/* I2S receiver */ +# define AUDIO_I2S_IN_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D088000) + +/* I2C master */ +# define I2C_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D090000) + +/* SPI controller */ +# define SPI_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D0A0000) + +/* Display controller Sunplus SPLC780D, 4bit mode, + * LCD Display MYTech MOC-16216B-B: */ +# define SPLC780D_4BIT_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D0C0000) + +/* USB Controller */ +# define USB_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D0D0000) + +/* Ethernet buffer: */ +# define ETHERNET_BUFFER_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D800000) + +#endif /* XSHAL_IOBLOCK_BYPASS_PADDR */ + +/* These devices might be accessed cached: */ +#ifdef XSHAL_IOBLOCK_CACHED_PADDR +# define XTBOARD_FLASH_CACHED_PADDR (XSHAL_IOBLOCK_CACHED_PADDR+0x08000000) +# define ETHERNET_BUFFER_CACHED_PADDR (XSHAL_IOBLOCK_CACHED_PADDR+0x0D800000) +#endif /* XSHAL_IOBLOCK_CACHED_PADDR */ + + +/*** Same thing over again, this time with virtual addresses: ***/ + +#ifdef XSHAL_IOBLOCK_BYPASS_VADDR + +/* Flash Memory: */ +# define XTBOARD_FLASH_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x08000000) + +/* FPGA registers: */ +# define XTBOARD_FPGAREGS_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D020000) + +/* Ethernet controller/transceiver SONIC SN83934: */ +# define ETHERNET_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D030000) + + +/* UART National-Semi PC16550D: */ +# define UART16550_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D050000) + +/* I2S transmitter */ +# define AUDIO_I2S_OUT_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D080000) + +/* I2S receiver */ +# define AUDIO_I2S_IN_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D088000) + +/* I2C master */ +# define I2C_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D090000) + +/* SPI controller */ +# define SPI_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D0A0000) + +/* Display controller Sunplus SPLC780D, 4bit mode, + * LCD Display MYTech MOC-16216B-B: */ +# define SPLC780D_4BIT_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D0C0000) + +/* USB Controller */ +# define USB_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D0D0000) + +/* Ethernet buffer: */ +# define ETHERNET_BUFFER_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D800000) + +#endif /* XSHAL_IOBLOCK_BYPASS_VADDR */ + +/* These devices might be accessed cached: */ +#ifdef XSHAL_IOBLOCK_CACHED_VADDR +# define XTBOARD_FLASH_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+0x08000000) +# define ETHERNET_BUFFER_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+0x0D800000) +#endif /* XSHAL_IOBLOCK_CACHED_VADDR */ + + +/* System ROM: */ +#define XTBOARD_ROM_SIZE XSHAL_ROM_SIZE +#ifdef XSHAL_ROM_VADDR +#define XTBOARD_ROM_VADDR XSHAL_ROM_VADDR +#endif +#ifdef XSHAL_ROM_PADDR +#define XTBOARD_ROM_PADDR XSHAL_ROM_PADDR +#endif + +/* System RAM: */ +#define XTBOARD_RAM_SIZE XSHAL_RAM_SIZE +#ifdef XSHAL_RAM_VADDR +#define XTBOARD_RAM_VADDR XSHAL_RAM_VADDR +#endif +#ifdef XSHAL_RAM_PADDR +#define XTBOARD_RAM_PADDR XSHAL_RAM_PADDR +#endif +#define XTBOARD_RAM_BYPASS_VADDR XSHAL_RAM_BYPASS_VADDR +#define XTBOARD_RAM_BYPASS_PADDR XSHAL_RAM_BYPASS_PADDR + + + +/* + * Things that depend on device addresses. + */ + + +#define XTBOARD_CACHEATTR_WRITEBACK XSHAL_XT2000_CACHEATTR_WRITEBACK +#define XTBOARD_CACHEATTR_WRITEALLOC XSHAL_XT2000_CACHEATTR_WRITEALLOC +#define XTBOARD_CACHEATTR_WRITETHRU XSHAL_XT2000_CACHEATTR_WRITETHRU +#define XTBOARD_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS +#define XTBOARD_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT + +#define XTBOARD_BUSINT_PIPE_REGIONS XSHAL_XT2000_PIPE_REGIONS +#define XTBOARD_BUSINT_SDRAM_REGIONS XSHAL_XT2000_SDRAM_REGIONS + + +/* + * FPGA registers. + * All these registers are normally accessed using 32-bit loads/stores. + */ + +/* Register offsets: */ +#define XTBOARD_DATECD_OFS 0x00 /* date code (read-only) */ +#define XTBOARD_CLKFRQ_OFS 0x04 /* clock frequency Hz (read-only) */ +#define XTBOARD_SYSLED_OFS 0x08 /* LEDs */ +#define XTBOARD_DIPSW_OFS 0x0C /* DIP switch bits (read-only) */ +#define XTBOARD_SWRST_OFS 0x10 /* software reset */ + +/* Physical register addresses: */ +#ifdef XTBOARD_FPGAREGS_PADDR +#define XTBOARD_DATECD_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_DATECD_OFS) +#define XTBOARD_CLKFRQ_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_CLKFRQ_OFS) +#define XTBOARD_SYSLED_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_SYSLED_OFS) +#define XTBOARD_DIPSW_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_DIPSW_OFS) +#define XTBOARD_SWRST_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_SWRST_OFS) +#endif + +/* Virtual register addresses: */ +#ifdef XTBOARD_FPGAREGS_VADDR +#define XTBOARD_DATECD_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_DATECD_OFS) +#define XTBOARD_CLKFRQ_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_CLKFRQ_OFS) +#define XTBOARD_SYSLED_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_SYSLED_OFS) +#define XTBOARD_DIPSW_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_DIPSW_OFS) +#define XTBOARD_SWRST_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_SWRST_OFS) +/* Register access (for C code): */ +#define XTBOARD_DATECD_REG (*(volatile unsigned*) XTBOARD_DATECD_VADDR) +#define XTBOARD_CLKFRQ_REG (*(volatile unsigned*) XTBOARD_CLKFRQ_VADDR) +#define XTBOARD_SYSLED_REG (*(volatile unsigned*) XTBOARD_SYSLED_VADDR) +#define XTBOARD_DIPSW_REG (*(volatile unsigned*) XTBOARD_DIPSW_VADDR) +#define XTBOARD_SWRST_REG (*(volatile unsigned*) XTBOARD_SWRST_VADDR) +#endif + +/* DATECD (date code; when core was built) bit fields: */ +/* BCD-coded month (01..12): */ +#define XTBOARD_DATECD_MONTH_SHIFT 24 +#define XTBOARD_DATECD_MONTH_BITS 8 +#define XTBOARD_DATECD_MONTH_MASK 0xFF000000 +/* BCD-coded day (01..31): */ +#define XTBOARD_DATECD_DAY_SHIFT 16 +#define XTBOARD_DATECD_DAY_BITS 8 +#define XTBOARD_DATECD_DAY_MASK 0x00FF0000 +/* BCD-coded year (2001..9999): */ +#define XTBOARD_DATECD_YEAR_SHIFT 0 +#define XTBOARD_DATECD_YEAR_BITS 16 +#define XTBOARD_DATECD_YEAR_MASK 0x0000FFFF + +/* SYSLED (system LED) bit fields: */ + +/* LED control bits (off=0, on=1): */ +#define XTBOARD_SYSLED_USER_SHIFT 0 +#define XTBOARD_SYSLED_USER_BITS 2 +#define XTBOARD_SYSLED_USER_MASK 0x00000003 + +/* DIP Switch SW5 (left=sw1=lsb=bit0, right=sw4=msb=bit3; off=0, on=1): */ +/* DIP switch bit fields (bit2/sw3 is reserved and presently unused): */ +#define XTBOARD_DIPSW_USER_SHIFT 0 /* labeled 1-2 (1=lsb) */ +#define XTBOARD_DIPSW_USER_BITS 2 +#define XTBOARD_DIPSW_USER_MASK 0x00000003 +#define XTBOARD_DIPSW_BOOT_SHIFT 3 /* labeled 8 (msb) */ +#define XTBOARD_DIPSW_BOOT_BITS 1 +#define XTBOARD_DIPSW_BOOT_MASK 0x00000008 +/* Boot settings: bit3/sw4, off=0, on=1 (this switch controls hardware): */ +#define XTBOARD_DIPSW_BOOT_RAM (0< + diff --git a/tools/sdk/include/esp32/xtensa/xtav200.h b/tools/sdk/include/esp32/xtensa/xtav200.h new file mode 100755 index 00000000..f3d837ef --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/xtav200.h @@ -0,0 +1,280 @@ +/* Copyright (c) 2007-2013 by Tensilica Inc. ALL RIGHTS RESERVED. +/ These coded instructions, statements, and computer programs are the +/ copyrighted works and confidential proprietary information of Tensilica Inc. +/ They may not be modified, copied, reproduced, distributed, or disclosed to +/ third parties in any manner, medium, or form, in whole or in part, without +/ the prior written consent of Tensilica Inc. +*/ + +/* xtav200.h - Xtensa Avnet LX200 (XT-AV200) board specific definitions */ + +#ifndef _INC_XTAV200_H_ +#define _INC_XTAV200_H_ + +#include +#include + +#define XTBOARD_NAME "XT-AV200" + + +/* + * Default assignment of XTAV200 devices to external interrupts. + */ + +/* Ethernet interrupt: */ +#ifdef XCHAL_EXTINT1_NUM +#define ETHERNET_INTNUM XCHAL_EXTINT1_NUM +#define ETHERNET_INTLEVEL XCHAL_EXTINT1_LEVEL +#define ETHERNET_INTMASK XCHAL_EXTINT1_MASK +#else +#define ETHERNET_INTMASK 0 +#endif + +/* UART interrupt: */ +#ifdef XCHAL_EXTINT0_NUM +#define UART16550_INTNUM XCHAL_EXTINT0_NUM +#define UART16550_INTLEVEL XCHAL_EXTINT0_LEVEL +#define UART16550_INTMASK XCHAL_EXTINT0_MASK +#else +#define UART16550_INTMASK 0 +#endif + +/* Audio output interrupt (I2S FIFO underrun): */ +#ifdef XCHAL_EXTINT2_NUM +#define AUDIO_INTNUM XCHAL_EXTINT2_NUM +#define AUDIO_INTLEVEL XCHAL_EXTINT2_LEVEL +#define AUDIO_INTMASK XCHAL_EXTINT2_MASK +#else +#define AUDIO_INTMASK 0 +#endif + +/* Audio output (I2S FIFO level) interrupt: */ +#ifdef XCHAL_EXTINT3_NUM +#define AUDIO_I2SLVL_INTNUM XCHAL_EXTINT3_NUM +#define AUDIO_I2SLVL_INTLEVEL XCHAL_EXTINT3_LEVEL +#define AUDIO_I2SLVL_INTMASK XCHAL_EXTINT3_MASK +#else +#define AUDIO_I2SLVL_INTMASK 0 +#endif + +/* Audio input (ADC FIFO level) interrupt: */ +#ifdef XCHAL_EXTINT4_NUM +#define AUDIO_ADCLVL_INTNUM XCHAL_EXTINT4_NUM +#define AUDIO_ADCLVL_INTLEVEL XCHAL_EXTINT4_LEVEL +#define AUDIO_ADCLVL_INTMASK XCHAL_EXTINT4_MASK +#else +#define AUDIO_ADCLVL_INTMASK 0 +#endif + + +/* + * Device addresses. + * + * Note: for endianness-independence, use 32-bit loads and stores for all + * register accesses to Ethernet, UART and LED devices. Undefined bits + * may need to be masked out if needed when reading if the actual register + * size is smaller than 32 bits. + * + * Note: XTAV200 bus byte lanes are defined in terms of msbyte and lsbyte + * relative to the processor. So 32-bit registers are accessed consistently + * from both big and little endian processors. However, this means byte + * sequences are not consistent between big and little endian processors. + * This is fine for RAM, and for ROM if ROM is created for a specific + * processor (and thus has correct byte sequences). However this may be + * unexpected for Flash, which might contain a file-system that one wants + * to use for multiple processor configurations (eg. the Flash might contain + * the Ethernet card's address, endianness-independent application data, etc). + * That is, byte sequences written in Flash by a core of a given endianness + * will be byte-swapped when seen by a core of the other endianness. + * Someone implementing an endianness-independent Flash file system will + * likely handle this byte-swapping issue in the Flash driver software. + */ + +#define XTBOARD_FLASH_MAXSIZE 0x1000000 /* 16 MB */ + +#ifdef XSHAL_IOBLOCK_BYPASS_PADDR + +/* Flash Memory: */ +# define XTBOARD_FLASH_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x08000000) + +/* FPGA registers: */ +# define XTBOARD_FPGAREGS_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D020000) + +/* Ethernet controller/transceiver SONIC SN83934: */ +# define ETHERNET_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D030000) + +/* UART National-Semi PC16550D: */ +# define UART16550_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D050000) + +/* TI 320AIC23/28-TSSOP Stereo Audio Codec: */ +# define AUDIO_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D070000) + +/* Boot 128K Sram address: */ +# define BOOT_SRAM_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D400000) + +/* Ethernet buffer: */ +# define ETHERNET_BUFFER_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D800000) + +#endif /* XSHAL_IOBLOCK_BYPASS_PADDR */ + +/* These devices might be accessed cached: */ +#ifdef XSHAL_IOBLOCK_CACHED_PADDR +# define XTBOARD_FLASH_CACHED_PADDR (XSHAL_IOBLOCK_CACHED_PADDR+0x08000000) +# define ETHERNET_BUFFER_CACHED_PADDR (XSHAL_IOBLOCK_CACHED_PADDR+0x0D800000) +# define BOOT_SRAM_CACHED_PADDR (XSHAL_IOBLOCK_CACHED_PADDR+0x0D400000) +#endif /* XSHAL_IOBLOCK_CACHED_PADDR */ + + +/*** Same thing over again, this time with virtual addresses: ***/ + +#ifdef XSHAL_IOBLOCK_BYPASS_VADDR + +/* Flash Memory: */ +# define XTBOARD_FLASH_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x08000000) + +/* FPGA registers: */ +# define XTBOARD_FPGAREGS_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D020000) + +/* Ethernet controller/transceiver SONIC SN83934: */ +# define ETHERNET_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D030000) + +/* UART National-Semi PC16550D: */ +# define UART16550_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D050000) + +/* TI 320AIC23/28-TSSOP Stereo Audio Codec: */ +# define AUDIO_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D070000) + +/* 128K Sram address: */ +# define BOOT_SRAM_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D400000) + +/* Ethernet buffer: */ +# define ETHERNET_BUFFER_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D800000) + +#endif /* XSHAL_IOBLOCK_BYPASS_VADDR */ + +/* These devices might be accessed cached: */ +#ifdef XSHAL_IOBLOCK_CACHED_VADDR +# define XTBOARD_FLASH_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+0x08000000) +# define AUDIO_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+0x0D070000) +# define ETHERNET_BUFFER_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+0x0D800000) +# define BOOT_SRAM_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+0x0D400000) +#endif /* XSHAL_IOBLOCK_CACHED_VADDR */ + + +/* System ROM: */ +#define XTBOARD_ROM_SIZE XSHAL_ROM_SIZE +#ifdef XSHAL_ROM_VADDR +#define XTBOARD_ROM_VADDR XSHAL_ROM_VADDR +#endif +#ifdef XSHAL_ROM_PADDR +#define XTBOARD_ROM_PADDR XSHAL_ROM_PADDR +#endif + +/* System RAM: */ +#define XTBOARD_RAM_SIZE XSHAL_RAM_SIZE +#ifdef XSHAL_RAM_VADDR +#define XTBOARD_RAM_VADDR XSHAL_RAM_VADDR +#endif +#ifdef XSHAL_RAM_PADDR +#define XTBOARD_RAM_PADDR XSHAL_RAM_PADDR +#endif +#define XTBOARD_RAM_BYPASS_VADDR XSHAL_RAM_BYPASS_VADDR +#define XTBOARD_RAM_BYPASS_PADDR XSHAL_RAM_BYPASS_PADDR + + + +/* + * Things that depend on device addresses. + */ + + +#define XTBOARD_CACHEATTR_WRITEBACK XSHAL_XT2000_CACHEATTR_WRITEBACK +#define XTBOARD_CACHEATTR_WRITEALLOC XSHAL_XT2000_CACHEATTR_WRITEALLOC +#define XTBOARD_CACHEATTR_WRITETHRU XSHAL_XT2000_CACHEATTR_WRITETHRU +#define XTBOARD_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS +#define XTBOARD_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT + +#define XTBOARD_BUSINT_PIPE_REGIONS XSHAL_XT2000_PIPE_REGIONS +#define XTBOARD_BUSINT_SDRAM_REGIONS XSHAL_XT2000_SDRAM_REGIONS + + +/* + * FPGA registers. + * All these registers are normally accessed using 32-bit loads/stores. + */ + +/* Register offsets: */ +#define XTBOARD_DATECD_OFS 0x00 /* date code (read-only) */ +#define XTBOARD_CLKFRQ_OFS 0x04 /* clock frequency Hz (read-only) */ +#define XTBOARD_SYSLED_OFS 0x08 /* LEDs */ +#define XTBOARD_DIPSW_OFS 0x0C /* DIP switch bits (read-only) */ +#define XTBOARD_SWRST_OFS 0x10 /* software reset */ + +/* Physical register addresses: */ +#ifdef XTBOARD_FPGAREGS_PADDR +#define XTBOARD_DATECD_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_DATECD_OFS) +#define XTBOARD_CLKFRQ_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_CLKFRQ_OFS) +#define XTBOARD_SYSLED_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_SYSLED_OFS) +#define XTBOARD_DIPSW_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_DIPSW_OFS) +#define XTBOARD_SWRST_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_SWRST_OFS) +#endif + +/* Virtual register addresses: */ +#ifdef XTBOARD_FPGAREGS_VADDR +#define XTBOARD_DATECD_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_DATECD_OFS) +#define XTBOARD_CLKFRQ_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_CLKFRQ_OFS) +#define XTBOARD_SYSLED_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_SYSLED_OFS) +#define XTBOARD_DIPSW_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_DIPSW_OFS) +#define XTBOARD_SWRST_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_SWRST_OFS) +/* Register access (for C code): */ +#define XTBOARD_DATECD_REG (*(volatile unsigned*) XTBOARD_DATECD_VADDR) +#define XTBOARD_CLKFRQ_REG (*(volatile unsigned*) XTBOARD_CLKFRQ_VADDR) +#define XTBOARD_SYSLED_REG (*(volatile unsigned*) XTBOARD_SYSLED_VADDR) +#define XTBOARD_DIPSW_REG (*(volatile unsigned*) XTBOARD_DIPSW_VADDR) +#define XTBOARD_SWRST_REG (*(volatile unsigned*) XTBOARD_SWRST_VADDR) +#endif + +/* DATECD (date code; when core was built) bit fields: */ +/* BCD-coded month (01..12): */ +#define XTBOARD_DATECD_MONTH_SHIFT 24 +#define XTBOARD_DATECD_MONTH_BITS 8 +#define XTBOARD_DATECD_MONTH_MASK 0xFF000000 +/* BCD-coded day (01..31): */ +#define XTBOARD_DATECD_DAY_SHIFT 16 +#define XTBOARD_DATECD_DAY_BITS 8 +#define XTBOARD_DATECD_DAY_MASK 0x00FF0000 +/* BCD-coded year (2001..9999): */ +#define XTBOARD_DATECD_YEAR_SHIFT 0 +#define XTBOARD_DATECD_YEAR_BITS 16 +#define XTBOARD_DATECD_YEAR_MASK 0x0000FFFF + +/* SYSLED (system LED) bit fields: */ + +/* LED control bits (off=0, on=1): */ +#define XTBOARD_SYSLED_USER_SHIFT 0 +#define XTBOARD_SYSLED_USER_BITS 4 +#define XTBOARD_SYSLED_USER_MASK 0x0000000F + +/* DIP Switch (left=sw1=lsb=bit0, right=sw8=msb=bit7; off=0, on=1): */ +/* DIP switch bit fields (bit6/sw7 is reserved and presently unused): */ +#define XTBOARD_DIPSW_USER_SHIFT 0 /* labeled 1-6 (1=lsb) */ +#define XTBOARD_DIPSW_USER_BITS 6 +#define XTBOARD_DIPSW_USER_MASK 0x0000003F +#define XTBOARD_DIPSW_BOOT_SHIFT 7 /* labeled 8 (msb) */ +#define XTBOARD_DIPSW_BOOT_BITS 1 +#define XTBOARD_DIPSW_BOOT_MASK 0x00000080 +/* Boot settings: bit7/sw8, off=0, on=1 (this switch controls hardware): */ +#define XTBOARD_DIPSW_BOOT_RAM (0< + diff --git a/tools/sdk/include/esp32/xtensa/xtav60.h b/tools/sdk/include/esp32/xtensa/xtav60.h new file mode 100755 index 00000000..d7c8e3ae --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/xtav60.h @@ -0,0 +1,241 @@ +/* Copyright (c) 2002-2013 by Tensilica Inc. ALL RIGHTS RESERVED. +/ These coded instructions, statements, and computer programs are the +/ copyrighted works and confidential proprietary information of Tensilica Inc. +/ They may not be modified, copied, reproduced, distributed, or disclosed to +/ third parties in any manner, medium, or form, in whole or in part, without +/ the prior written consent of Tensilica Inc. +*/ + +/* xtav60.h - Xtensa Avnet LX60 (XT-AV60) board specific definitions */ + +#ifndef _INC_XTAV60_H_ +#define _INC_XTAV60_H_ + +#include +#include + +#define XTBOARD_NAME "XT-AV60" + + +/* + * Default assignment of XTAV60 devices to external interrupts. + */ + +/* Ethernet interrupt: */ +#ifdef XCHAL_EXTINT1_NUM +#define ETHERNET_INTNUM XCHAL_EXTINT1_NUM +#define ETHERNET_INTLEVEL XCHAL_EXTINT1_LEVEL +#define ETHERNET_INTMASK XCHAL_EXTINT1_MASK +#else +#define ETHERNET_INTMASK 0 +#endif + +/* UART interrupt: */ +#ifdef XCHAL_EXTINT0_NUM +#define UART16550_INTNUM XCHAL_EXTINT0_NUM +#define UART16550_INTLEVEL XCHAL_EXTINT0_LEVEL +#define UART16550_INTMASK XCHAL_EXTINT0_MASK +#else +#define UART16550_INTMASK 0 +#endif + +/* + * Device addresses. + * + * Note: for endianness-independence, use 32-bit loads and stores for all + * register accesses to Ethernet, UART and LED devices. Undefined bits + * may need to be masked out if needed when reading if the actual register + * size is smaller than 32 bits. + * + * Note: XTAV60 bus byte lanes are defined in terms of msbyte and lsbyte + * relative to the processor. So 32-bit registers are accessed consistently + * from both big and little endian processors. However, this means byte + * sequences are not consistent between big and little endian processors. + * This is fine for RAM, and for ROM if ROM is created for a specific + * processor (and thus has correct byte sequences). However this may be + * unexpected for Flash, which might contain a file-system that one wants + * to use for multiple processor configurations (eg. the Flash might contain + * the Ethernet card's address, endianness-independent application data, etc). + * That is, byte sequences written in Flash by a core of a given endianness + * will be byte-swapped when seen by a core of the other endianness. + * Someone implementing an endianness-independent Flash file system will + * likely handle this byte-swapping issue in the Flash driver software. + */ + +#define XTBOARD_FLASH_MAXSIZE 0x400000 /* 4 MB */ + +#ifdef XSHAL_IOBLOCK_BYPASS_PADDR + +/* Flash Memory: */ +# define XTBOARD_FLASH_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x08000000) + +/* FPGA registers: */ +# define XTBOARD_FPGAREGS_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D020000) + +/* Ethernet controller/transceiver SONIC SN83934: */ +# define ETHERNET_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D030000) +# define ETHERNET_CONTROLLER_PADDR ETHERNET_PADDR /* legacy macro */ + +/* Display controller Sunplus SPLC780D, LCD Display MYTech MOC-16216B-B: */ +# define SPLC780D_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D040000) + +/* UART National-Semi PC16550D: */ +# define UART16550_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D050000) + +/* Boot 128K Sram address: */ +# define BOOT_SRAM_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D400000) + +/* Ethernet buffer: */ +# define ETHERNET_BUFFER_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D800000) + +#endif /* XSHAL_IOBLOCK_BYPASS_PADDR */ + +/* These devices might be accessed cached: */ +#ifdef XSHAL_IOBLOCK_CACHED_PADDR +# define XTBOARD_FLASH_CACHED_PADDR (XSHAL_IOBLOCK_CACHED_PADDR+0x08000000) +# define ETHERNET_BUFFER_CACHED_PADDR (XSHAL_IOBLOCK_CACHED_PADDR+0x0D800000) +# define BOOT_SRAM_CACHED_PADDR (XSHAL_IOBLOCK_CACHED_PADDR+0x0D400000) +#endif /* XSHAL_IOBLOCK_CACHED_PADDR */ + + +/*** Same thing over again, this time with virtual addresses: ***/ + +#ifdef XSHAL_IOBLOCK_BYPASS_VADDR + +/* Flash Memory: */ +# define XTBOARD_FLASH_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x08000000) + +/* FPGA registers: */ +# define XTBOARD_FPGAREGS_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D020000) + +/* Ethernet controller/transceiver SONIC SN83934: */ +# define ETHERNET_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D030000) + +/* Display controller Sunplus SPLC780D, LCD Display MYTech MOC-16216B-B: */ +# define SPLC780D_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D040000) + +/* UART National-Semi PC16550D: */ +# define UART16550_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D050000) + +/* 128K Sram address: */ +# define BOOT_SRAM_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D400000) + +/* Ethernet buffer: */ +# define ETHERNET_BUFFER_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D800000) + +#endif /* XSHAL_IOBLOCK_BYPASS_VADDR */ + +/* These devices might be accessed cached: */ +#ifdef XSHAL_IOBLOCK_CACHED_VADDR +# define XTBOARD_FLASH_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+0x08000000) +# define ETHERNET_BUFFER_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+0x0D800000) +# define BOOT_SRAM_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+0x0D400000) +#endif /* XSHAL_IOBLOCK_CACHED_VADDR */ + + +/* System ROM: */ +#define XTBOARD_ROM_SIZE XSHAL_ROM_SIZE +#ifdef XSHAL_ROM_VADDR +#define XTBOARD_ROM_VADDR XSHAL_ROM_VADDR +#endif +#ifdef XSHAL_ROM_PADDR +#define XTBOARD_ROM_PADDR XSHAL_ROM_PADDR +#endif + +/* System RAM: */ +#define XTBOARD_RAM_SIZE XSHAL_RAM_SIZE +#ifdef XSHAL_RAM_VADDR +#define XTBOARD_RAM_VADDR XSHAL_RAM_VADDR +#endif +#ifdef XSHAL_RAM_PADDR +#define XTBOARD_RAM_PADDR XSHAL_RAM_PADDR +#endif +#define XTBOARD_RAM_BYPASS_VADDR XSHAL_RAM_BYPASS_VADDR +#define XTBOARD_RAM_BYPASS_PADDR XSHAL_RAM_BYPASS_PADDR + + + +/* + * Things that depend on device addresses. + */ + + +#define XTBOARD_CACHEATTR_WRITEBACK XSHAL_XT2000_CACHEATTR_WRITEBACK +#define XTBOARD_CACHEATTR_WRITEALLOC XSHAL_XT2000_CACHEATTR_WRITEALLOC +#define XTBOARD_CACHEATTR_WRITETHRU XSHAL_XT2000_CACHEATTR_WRITETHRU +#define XTBOARD_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS +#define XTBOARD_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT + +#define XTBOARD_BUSINT_PIPE_REGIONS XSHAL_XT2000_PIPE_REGIONS +#define XTBOARD_BUSINT_SDRAM_REGIONS XSHAL_XT2000_SDRAM_REGIONS + + +/* + * FPGA registers. + * All these registers are normally accessed using 32-bit loads/stores. + */ + +/* Register offsets: */ +#define XTBOARD_DATECD_OFS 0x00 /* date code (read-only) */ +#define XTBOARD_CLKFRQ_OFS 0x04 /* clock frequency Hz (read-only) */ +#define XTBOARD_DIPSW_OFS 0x0C /* DIP switch bits (read-only) */ +#define XTBOARD_SWRST_OFS 0x10 /* software reset */ + +/* Physical register addresses: */ +#ifdef XTBOARD_FPGAREGS_PADDR +#define XTBOARD_DATECD_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_DATECD_OFS) +#define XTBOARD_CLKFRQ_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_CLKFRQ_OFS) +#define XTBOARD_DIPSW_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_DIPSW_OFS) +#define XTBOARD_SWRST_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_SWRST_OFS) +#endif + +/* Virtual register addresses: */ +#ifdef XTBOARD_FPGAREGS_VADDR +#define XTBOARD_DATECD_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_DATECD_OFS) +#define XTBOARD_CLKFRQ_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_CLKFRQ_OFS) +#define XTBOARD_DIPSW_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_DIPSW_OFS) +#define XTBOARD_SWRST_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_SWRST_OFS) +/* Register access (for C code): */ +#define XTBOARD_DATECD_REG (*(volatile unsigned*) XTBOARD_DATECD_VADDR) +#define XTBOARD_CLKFRQ_REG (*(volatile unsigned*) XTBOARD_CLKFRQ_VADDR) +#define XTBOARD_DIPSW_REG (*(volatile unsigned*) XTBOARD_DIPSW_VADDR) +#define XTBOARD_SWRST_REG (*(volatile unsigned*) XTBOARD_SWRST_VADDR) +#endif + +/* DATECD (date code; when core was built) bit fields: */ +/* BCD-coded month (01..12): */ +#define XTBOARD_DATECD_MONTH_SHIFT 24 +#define XTBOARD_DATECD_MONTH_BITS 8 +#define XTBOARD_DATECD_MONTH_MASK 0xFF000000 +/* BCD-coded day (01..31): */ +#define XTBOARD_DATECD_DAY_SHIFT 16 +#define XTBOARD_DATECD_DAY_BITS 8 +#define XTBOARD_DATECD_DAY_MASK 0x00FF0000 +/* BCD-coded year (2001..9999): */ +#define XTBOARD_DATECD_YEAR_SHIFT 0 +#define XTBOARD_DATECD_YEAR_BITS 16 +#define XTBOARD_DATECD_YEAR_MASK 0x0000FFFF + +/* DIP Switch (left=sw1=lsb=bit0, right=sw8=msb=bit7; off=0, on=1): */ +/* DIP switch bit fields (bit6/sw7 is reserved and presently unused): */ +#define XTBOARD_DIPSW_USER_SHIFT 0 /* labeled 1-6 (1=lsb) */ +#define XTBOARD_DIPSW_USER_BITS 6 +#define XTBOARD_DIPSW_USER_MASK 0x0000003F +#define XTBOARD_DIPSW_BOOT_SHIFT 7 /* labeled 8 (msb) */ +#define XTBOARD_DIPSW_BOOT_BITS 1 +#define XTBOARD_DIPSW_BOOT_MASK 0x00000080 +/* Boot settings: bit7/sw8, off=0, on=1 (this switch controls hardware): */ +#define XTBOARD_DIPSW_BOOT_RAM (0< + diff --git a/tools/sdk/include/esp32/xtensa/xtav60/xtensa/lcd-splc780d-board.h b/tools/sdk/include/esp32/xtensa/xtav60/xtensa/lcd-splc780d-board.h new file mode 100755 index 00000000..629a3258 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/xtav60/xtensa/lcd-splc780d-board.h @@ -0,0 +1,60 @@ +/******************************************************************************* + +Copyright (c) 2006-2007 by Tensilica Inc. ALL RIGHTS RESERVED. +These coded instructions, statements, and computer programs are the +copyrighted works and confidential proprietary information of Tensilica Inc. +They may not be modified, copied, reproduced, distributed, or disclosed to +third parties in any manner, medium, or form, in whole or in part, without +the prior written consent of Tensilica Inc. +-------------------------------------------------------------------------------- + +lcd-splc780d-board.h Board-specific LCD info on Avnet AV60 (XT-AV60) board. + +Interface between board-independent driver and board-specific header. + +This is used by a board-independent SPLC780D LCD controller driver to obtain +board-specific information about LCD displays on the board, such as the +controller register base address and spacing (a function of how the address +lines are connected on the board) and length of the visible window of the +display (a function of the LCD panel the controller drives). The driver does +not refer directly to the board-specific header, which therefore is not +constrained to use macro names consistent with other boards. + +!! Must not contain any board-specific macro names (only controller specific) !! + +Included at compile-time via an include path specific to the board. + +The XT-AV60 board contains a single MYTech MOC-16216B-B display driven by +a Sunplus SPLC870D controller. + +*******************************************************************************/ + +#ifndef _LCD_SPLC780D_BOARD_H +#define _LCD_SPLC780D_BOARD_H + +#include /* Board info */ + + +/* Base address of the controller's registers. */ +#ifdef SPLC780D_VADDR +#define SPLC780D_REGBASE SPLC780D_VADDR +#endif + +/* +The controller's registers are connected at word addresses on the XT-AV60. +Each byte-wide register appears as the least-significant-byte (LSB) of the +word regardless of the endianness of the processor (so if using word accesses +then endianness doesn't matter). +*/ +#define SPLC780D_REGSPACING 4 +typedef unsigned splc780d_reg_t; + +/* Include generic information shared by all boards that use this device. */ +#include + + +/* Display limits of the LCD panel. */ +#define DISPLAY_VISIBLE_LEN 16 /* length (chars) of visible window */ + +#endif /* _LCD_SPLC780D_BOARD_H */ + diff --git a/tools/sdk/include/esp32/xtensa/xtbsp.h b/tools/sdk/include/esp32/xtensa/xtbsp.h new file mode 100755 index 00000000..62356dd8 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/xtbsp.h @@ -0,0 +1,269 @@ +/******************************************************************************* + + Copyright (c) 2006-2009 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +-------------------------------------------------------------------------------- + +xtbsp.h Xtensa Board Support Package API + +This API defines a minimal set of board-support functions that every supported +Xtensa board is expected to provide in the board-support-package (BSP) library +associated with the board-specific LSP. Only basic board functions are provided +in this board-independent API. API functions not applicable to a board must be +stubbed in its BSP library. More complex operations must use a board-specific +interface. Functions are grouped by type of peripheral device. + +*******************************************************************************/ + +#ifndef _XTBSP_H_ +#define _XTBSP_H_ + + +#ifdef __cplusplus +extern "C" { +#endif + + +/******************************************************************************* +BOARD INITIALIZATION. +The board with all its devices is initialized by xtbsp_board_init(). +Individual devices represented by this API can be reinitialized at any +time by calling their inidividual device init functions (grouped with +other device functions). This might be useful to (say) change the baud +rate of the UART. +*/ + + +/* +Initialize the board. Must call before any other API function. +Iniitializes BSP, board in general, and all devices on the board. +*/ +extern void xtbsp_board_init(void); + + +/******************************************************************************* +BOARD CHARACTERISTICS and CONVENIENCE FUNCTIONS. +Board support functions not associated with a particular peripheral device. +*/ + +/* +Return a short string representing the type of board. +If the board has a display, the string must fit on a single line. +*/ +extern const char * xtbsp_board_name(void); + +/* +Hardware reset the entire board (if possible). Does not return if successful. +If this function returns, it is stubbed out or not possible with this board. +*/ +extern void xtbsp_board_reset(void); + +/* +Return the clock frequency in Hertz. May be constant or computed. +*/ +extern unsigned xtbsp_clock_freq_hz(void); + +/* +Return the clock period in picoseconds. May be constant or computed. +*/ +extern unsigned xtbsp_clock_period_ps(void); + +/* +Spin (at least) a number of cycles per the processor's CCOUNT register. +Unlike a s/w delay loop, the duration is not affected by compiler +optimization or interrupts completed within the delay period. +If the processor doesn't have CCOUNT, a s/w delay loop is used to obtain +a rough approximation of the cycle count. +*/ +extern void xtbsp_delay_cycles(unsigned cycles); + +/* +Spin at least a number of nanoseconds (approximate and err in the high side). +BSP implementation should do this efficiently, avoiding integer overflow or +excessive loss of precision, run-time division or floating point. +Function implementation (vs. macro) allows BSP to optimize for the clock +frequency by pre-computing (or using constant) scale factors. +*/ +extern void xtbsp_delay_ns(unsigned ns); + + +/******************************************************************************* +C LIBRARY SUPPORT. +These functions are called by the C library libgloss interface. +Their names are predetermined apart from this BSP API. +*/ + +/* +Initialize the board. Called by C library initialization code. +Usually simply calls xtbsp_board_init(). +*/ +extern void board_init(void); + +/* +(Wait for and) Input a single byte from the default character I/O +device. Return -1 if there is no input device. +This device is usually a UART and this function calls xtbsp_uart_getchar(). +On some boards (eg.) it might be a directly connected keyboard. +*/ +extern int inbyte(void); + +/* +Output a single char to the default character I/O device (and wait +until it's been taken). +This device is usually a UART and this function calls xtbsp_uart_putchar(). +On some boards (eg.) it might be a directly connected bit-mapped screen. +*/ +extern void outbyte(int c); + + +/******************************************************************************* +UART (SERIAL I/O). +Supports a single UART in a simple polling mode and provides control of +receiver and transmitter data interrupts (client must provide handler). +Provides a mapping to processor interrupt number which can be used with +the HAL to control processor interrupt enable (INTENABLE) etc. +*/ + +/* Bitmasks to identify UART interrupts. */ +typedef enum xtbsp_uart_int { + xtbsp_uart_int_rx = 1<<0, + xtbsp_uart_int_tx = 1<<1, + /* mask of all valid interrupt bits */ + xtbsp_uart_int_all = (1<<2)-1 +} xtbsp_uart_int; + +/* +Return non-zero if the board has a UART. +*/ +extern int xtbsp_uart_exists(void); + +/* +Initialize the UART: + parity = 0 (none), 1 (odd), or 2 (even). + nstop = 1 or 2 (stop bits). + ndata = 7 or 8 (data bits). +Disables all UART interrupts. +Returns non-zero if failed (perhaps due to unsupported parameter values). +Must call before any of the following functions. +*/ +extern int xtbsp_uart_init(unsigned baud, unsigned ndata, + unsigned parity, unsigned nstop); +#define xtbsp_uart_init_default() xtbsp_uart_init(38400, 8, 0, 1) + +/* +(Wait for and) Input a single char from the UART. +Any pending xtbsp_uart_int_rx interrupt is cleared. +*/ +extern char xtbsp_uart_getchar(void); + +/* +(Wait for transmitter ready and) Output a single char to the UART. +Any pending xtbsp_uart_int_tx interrupt is cleared. +*/ +extern void xtbsp_uart_putchar(const char c); + +/* +Return true (non-zero) if a character has been received and is ready +to be input by xtbsp_uart_getchar() without waiting, else return 0. +*/ +extern int xtbsp_uart_get_isready(void); + +/* +Return non-zero if a character may be output by xtbsp_uart_putchar() +without waiting, else return 0. +Any pending xtbsp_uart_int_tx interrupt is cleared. +*/ +extern int xtbsp_uart_put_isready(void); + +/* +Return the enable status of all UART interrupts represented by this API, +that is those with bits defined in type xtbsp_uart_int (1 bit = enabled). +This is the enable status at the device, not the processor's INTENABLE. +*/ +extern xtbsp_uart_int xtbsp_uart_int_enable_status(void); + +/* +Enable selected UART interrupts at the device. +*/ +extern void xtbsp_uart_int_enable(const xtbsp_uart_int mask); + +/* +Disable selected UART interrupts at the device. +*/ +extern void xtbsp_uart_int_disable(const xtbsp_uart_int mask); + +/* +Return the interrupt number (0..31) to which the selected UART interrupt +is connected. May be used with the link-time HAL to obtain more information, +eg. Xthal_intlevel_mask[xtbsp_uart_int_number(xtbsp_uart_int_rx)] +This information can be used to control the processor's INTENABLE, etc. +Result is -1 if not connected, undefined if mask has more than 1 bit set. +*/ +extern int xtbsp_uart_int_number(const xtbsp_uart_int mask); + + +/******************************************************************************* +DISPLAY. +Supports a single display that can render a series of ASCII characters. +Functions are provided to perform generic display tasks such as display +a string, display character by character, or blank the display. +Chars are 7-bit printable ASCII. Strings are C style NUL \0 terminated. +These functions busy-wait for any required timing delays so the caller does +not have to deal with timing. Some displays require long delays which in +some client applications warrant a board and RTOS specific approach to +driving the display, however that is beyond the scope of this API. +*/ + +/* +Return non-zero if board has a display. +*/ +extern int xtbsp_display_exists(void); + +/* +Initialize the display. Must call before any of the following functions. +*/ +extern void xtbsp_display_init(void); + +/* +Display a single char at position pos (0 is leftmost). Other positions are +left untouched. Positions beyond the width of the display are ignored. +*/ +extern void xtbsp_display_char(unsigned pos, const char c); + +/* +Display a string. Blank-pad to or truncate at the end of the display +(overwrites any previous string so don't need to blank display first). +*/ +extern void xtbsp_display_string(const char *s); + +/* +Blank (clear) the entire display. +*/ +extern void xtbsp_display_blank(void); + + + +#ifdef __cplusplus +} +#endif + +#endif /* _XTBSP_H_ */ diff --git a/tools/sdk/include/esp32/xtensa/xtensa-libdb-macros.h b/tools/sdk/include/esp32/xtensa/xtensa-libdb-macros.h new file mode 100755 index 00000000..fbbe5096 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/xtensa-libdb-macros.h @@ -0,0 +1,161 @@ +/* + * xtensa-libdb-macros.h + */ + +/* $Id: //depot/rel/Eaglenest/Xtensa/Software/libdb/xtensa-libdb-macros.h#1 $ */ + +/* Copyright (c) 2004-2008 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef __H_LIBDB_MACROS +#define __H_LIBDB_MACROS + +/* + * This header file provides macros used to construct, identify and use + * "target numbers" that are assigned to various types of Xtensa processor + * registers and states. These target numbers are used by GDB in the remote + * protocol, and are thus used by all GDB debugger agents (targets). + * They are also used in ELF debugger information sections (stabs, dwarf, etc). + * + * These macros are separated from xtensa-libdb.h because they are needed + * by certain debugger agents that do not use or have access to libdb, + * e.g. the OCD daemon, RedBoot, XMON, etc. + * + * For the time being, for compatibility with certain 3rd party debugger + * software vendors, target numbers are limited to 16 bits. It is + * conceivable that this will be extended in the future to 32 bits. + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef uint32 + #define uint32 unsigned int +#endif +#ifndef int32 + #define int32 int +#endif + + +/* + * Macros to form register "target numbers" for various standard registers/states: + */ +#define XTENSA_DBREGN_INVALID -1 /* not a valid target number */ +#define XTENSA_DBREGN_A(n) (0x0000+(n)) /* address registers a0..a15 */ +#define XTENSA_DBREGN_B(n) (0x0010+(n)) /* boolean bits b0..b15 */ +#define XTENSA_DBREGN_PC 0x0020 /* program counter */ + /* 0x0021 RESERVED for use by Tensilica */ +#define XTENSA_DBREGN_BO(n) (0x0022+(n)) /* boolean octuple-bits bo0..bo1 */ +#define XTENSA_DBREGN_BQ(n) (0x0024+(n)) /* boolean quadruple-bits bq0..bq3 */ +#define XTENSA_DBREGN_BD(n) (0x0028+(n)) /* boolean double-bits bd0..bd7 */ +#define XTENSA_DBREGN_F(n) (0x0030+(n)) /* floating point registers f0..f15 */ +#define XTENSA_DBREGN_VEC(n) (0x0040+(n)) /* Vectra vec regs v0..v15 */ +#define XTENSA_DBREGN_VSEL(n) (0x0050+(n)) /* Vectra sel s0..s3 (V1) ..s7 (V2) */ +#define XTENSA_DBREGN_VALIGN(n) (0x0058+(n)) /* Vectra valign regs u0..u3 */ +#define XTENSA_DBREGN_VCOEFF(n) (0x005C+(n)) /* Vectra I vcoeff regs c0..c1 */ + /* 0x005E..0x005F RESERVED for use by Tensilica */ +#define XTENSA_DBREGN_AEP(n) (0x0060+(n)) /* HiFi2 Audio Engine regs aep0..aep7 */ +#define XTENSA_DBREGN_AEQ(n) (0x0068+(n)) /* HiFi2 Audio Engine regs aeq0..aeq3 */ + /* 0x006C..0x00FF RESERVED for use by Tensilica */ +#define XTENSA_DBREGN_AR(n) (0x0100+(n)) /* physical address regs ar0..ar63 + (note: only with window option) */ + /* 0x0140..0x01FF RESERVED for use by Tensilica */ +#define XTENSA_DBREGN_SREG(n) (0x0200+(n)) /* special registers 0..255 (core) */ +#define XTENSA_DBREGN_BR XTENSA_DBREGN_SREG(0x04) /* all 16 boolean bits, BR */ +#define XTENSA_DBREGN_MR(n) XTENSA_DBREGN_SREG(0x20+(n)) /* MAC16 registers m0..m3 */ +#define XTENSA_DBREGN_UREG(n) (0x0300+(n)) /* user registers 0..255 (TIE) */ + /* 0x0400..0x0FFF RESERVED for use by Tensilica */ + /* 0x1000..0x1FFF user-defined regfiles */ + /* 0x2000..0xEFFF other states (and regfiles) */ +#define XTENSA_DBREGN_DBAGENT(n) (0xF000+(n)) /* non-processor "registers" 0..4095 for + 3rd-party debugger agent defined use */ + /* > 0xFFFF (32-bit) RESERVED for use by Tensilica */ +/*#define XTENSA_DBREGN_CONTEXT(n) (0x02000000+((n)<<20))*/ /* add this macro's value to a target + number to identify a specific context 0..31 + for context-replicated registers */ +#define XTENSA_DBREGN_MASK 0xFFFF /* mask of valid target_number bits */ +#define XTENSA_DBREGN_WRITE_SIDE 0x04000000 /* flag to request write half of a register + split into distinct read and write entries + with the same target number (currently only + valid in a couple of libdb API functions; + see xtensa-libdb.h for details) */ + +/* + * Macros to identify specific ranges of target numbers (formed above): + * NOTE: any context number (or other upper 12 bits) are considered + * modifiers and are thus stripped out for identification purposes. + */ +#define XTENSA_DBREGN_IS_VALID(tn) (((tn) & ~0xFFFF) == 0) /* just tests it's 16-bit unsigned */ +#define XTENSA_DBREGN_IS_A(tn) (((tn) & 0xFFF0)==0x0000) /* is a0..a15 */ +#define XTENSA_DBREGN_IS_B(tn) (((tn) & 0xFFF0)==0x0010) /* is b0..b15 */ +#define XTENSA_DBREGN_IS_PC(tn) (((tn) & 0xFFFF)==0x0020) /* is program counter */ +#define XTENSA_DBREGN_IS_BO(tn) (((tn) & 0xFFFE)==0x0022) /* is bo0..bo1 */ +#define XTENSA_DBREGN_IS_BQ(tn) (((tn) & 0xFFFC)==0x0024) /* is bq0..bq3 */ +#define XTENSA_DBREGN_IS_BD(tn) (((tn) & 0xFFF8)==0x0028) /* is bd0..bd7 */ +#define XTENSA_DBREGN_IS_F(tn) (((tn) & 0xFFF0)==0x0030) /* is f0..f15 */ +#define XTENSA_DBREGN_IS_VEC(tn) (((tn) & 0xFFF0)==0x0040) /* is v0..v15 */ +#define XTENSA_DBREGN_IS_VSEL(tn) (((tn) & 0xFFF8)==0x0050) /* is s0..s7 (s0..s3 in V1) */ +#define XTENSA_DBREGN_IS_VALIGN(tn) (((tn) & 0xFFFC)==0x0058) /* is u0..u3 */ +#define XTENSA_DBREGN_IS_VCOEFF(tn) (((tn) & 0xFFFE)==0x005C) /* is c0..c1 */ +#define XTENSA_DBREGN_IS_AEP(tn) (((tn) & 0xFFF8)==0x0060) /* is aep0..aep7 */ +#define XTENSA_DBREGN_IS_AEQ(tn) (((tn) & 0xFFFC)==0x0068) /* is aeq0..aeq3 */ +#define XTENSA_DBREGN_IS_AR(tn) (((tn) & 0xFFC0)==0x0100) /* is ar0..ar63 */ +#define XTENSA_DBREGN_IS_SREG(tn) (((tn) & 0xFF00)==0x0200) /* is special register */ +#define XTENSA_DBREGN_IS_BR(tn) (((tn) & 0xFFFF)==XTENSA_DBREGN_SREG(0x04)) /* is BR */ +#define XTENSA_DBREGN_IS_MR(tn) (((tn) & 0xFFFC)==XTENSA_DBREGN_SREG(0x20)) /* m0..m3 */ +#define XTENSA_DBREGN_IS_UREG(tn) (((tn) & 0xFF00)==0x0300) /* is user register */ +#define XTENSA_DBREGN_IS_DBAGENT(tn) (((tn) & 0xF000)==0xF000) /* is non-processor */ +/*#define XTENSA_DBREGN_IS_CONTEXT(tn) (((tn) & 0x02000000) != 0)*/ /* specifies context # */ + +/* + * Macros to extract register index from a register "target number" + * when a specific range has been identified using one of the _IS_ macros above. + * These macros only return a useful value if the corresponding _IS_ macro returns true. + */ +#define XTENSA_DBREGN_A_INDEX(tn) ((tn) & 0x0F) /* 0..15 for a0..a15 */ +#define XTENSA_DBREGN_B_INDEX(tn) ((tn) & 0x0F) /* 0..15 for b0..b15 */ +#define XTENSA_DBREGN_BO_INDEX(tn) ((tn) & 0x01) /* 0..1 for bo0..bo1 */ +#define XTENSA_DBREGN_BQ_INDEX(tn) ((tn) & 0x03) /* 0..3 for bq0..bq3 */ +#define XTENSA_DBREGN_BD_INDEX(tn) ((tn) & 0x07) /* 0..7 for bd0..bd7 */ +#define XTENSA_DBREGN_F_INDEX(tn) ((tn) & 0x0F) /* 0..15 for f0..f15 */ +#define XTENSA_DBREGN_VEC_INDEX(tn) ((tn) & 0x0F) /* 0..15 for v0..v15 */ +#define XTENSA_DBREGN_VSEL_INDEX(tn) ((tn) & 0x07) /* 0..7 for s0..s7 */ +#define XTENSA_DBREGN_VALIGN_INDEX(tn) ((tn) & 0x03) /* 0..3 for u0..u3 */ +#define XTENSA_DBREGN_VCOEFF_INDEX(tn) ((tn) & 0x01) /* 0..1 for c0..c1 */ +#define XTENSA_DBREGN_AEP_INDEX(tn) ((tn) & 0x07) /* 0..7 for aep0..aep7 */ +#define XTENSA_DBREGN_AEQ_INDEX(tn) ((tn) & 0x03) /* 0..3 for aeq0..aeq3 */ +#define XTENSA_DBREGN_AR_INDEX(tn) ((tn) & 0x3F) /* 0..63 for ar0..ar63 */ +#define XTENSA_DBREGN_SREG_INDEX(tn) ((tn) & 0xFF) /* 0..255 for special registers */ +#define XTENSA_DBREGN_MR_INDEX(tn) ((tn) & 0x03) /* 0..3 for m0..m3 */ +#define XTENSA_DBREGN_UREG_INDEX(tn) ((tn) & 0xFF) /* 0..255 for user registers */ +#define XTENSA_DBREGN_DBAGENT_INDEX(tn) ((tn) & 0xFFF) /* 0..4095 for non-processor */ +/*#define XTENSA_DBREGN_CONTEXT_INDEX(tn) (((tn) >> 20) & 0x1F)*/ /* 0..31 context numbers */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __H_LIBDB_MACROS */ + diff --git a/tools/sdk/include/esp32/xtensa/xtensa-versions.h b/tools/sdk/include/esp32/xtensa/xtensa-versions.h new file mode 100755 index 00000000..abed3a18 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/xtensa-versions.h @@ -0,0 +1,347 @@ +/* + xtensa-versions.h -- definitions of Xtensa version and release numbers + + This file defines most Xtensa-related product versions and releases + that exist so far. + It also provides a bit of information about which ones are current. + This file changes every release, as versions/releases get added. + + + $Id: //depot/rel/Eaglenest/Xtensa/Software/misc/xtensa-versions.h.tpp#2 $ + + Copyright (c) 2006-2010 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + +#ifndef XTENSA_VERSIONS_H +#define XTENSA_VERSIONS_H + + +/* + * NOTE: A "release" is a collection of product versions + * made available at once (together) to customers. + * In the past, release and version names all matched in T####.# form, + * making the distinction irrelevant. + * Starting with the RA-2004.1 release, this is no longer the case. + */ + + +/* Hardware (Xtensa/Diamond processor) versions: */ +#define XTENSA_HWVERSION_T1020_0 102000 /* versions T1020.0 */ +#define XTENSA_HWCIDSCHEME_T1020_0 10 +#define XTENSA_HWCIDVERS_T1020_0 2 +#define XTENSA_HWVERSION_T1020_1 102001 /* versions T1020.1 */ +#define XTENSA_HWCIDSCHEME_T1020_1 10 +#define XTENSA_HWCIDVERS_T1020_1 3 +#define XTENSA_HWVERSION_T1020_2B 102002 /* versions T1020.2b */ +#define XTENSA_HWCIDSCHEME_T1020_2B 10 +#define XTENSA_HWCIDVERS_T1020_2B 5 +#define XTENSA_HWVERSION_T1020_2 102002 /* versions T1020.2 */ +#define XTENSA_HWCIDSCHEME_T1020_2 10 +#define XTENSA_HWCIDVERS_T1020_2 4 +#define XTENSA_HWVERSION_T1020_3 102003 /* versions T1020.3 */ +#define XTENSA_HWCIDSCHEME_T1020_3 10 +#define XTENSA_HWCIDVERS_T1020_3 6 +#define XTENSA_HWVERSION_T1020_4 102004 /* versions T1020.4 */ +#define XTENSA_HWCIDSCHEME_T1020_4 10 +#define XTENSA_HWCIDVERS_T1020_4 7 +#define XTENSA_HWVERSION_T1030_0 103000 /* versions T1030.0 */ +#define XTENSA_HWCIDSCHEME_T1030_0 10 +#define XTENSA_HWCIDVERS_T1030_0 9 +#define XTENSA_HWVERSION_T1030_1 103001 /* versions T1030.1 */ +#define XTENSA_HWCIDSCHEME_T1030_1 10 +#define XTENSA_HWCIDVERS_T1030_1 10 +#define XTENSA_HWVERSION_T1030_2 103002 /* versions T1030.2 */ +#define XTENSA_HWCIDSCHEME_T1030_2 10 +#define XTENSA_HWCIDVERS_T1030_2 11 +#define XTENSA_HWVERSION_T1030_3 103003 /* versions T1030.3 */ +#define XTENSA_HWCIDSCHEME_T1030_3 10 +#define XTENSA_HWCIDVERS_T1030_3 12 +#define XTENSA_HWVERSION_T1040_0 104000 /* versions T1040.0 */ +#define XTENSA_HWCIDSCHEME_T1040_0 10 +#define XTENSA_HWCIDVERS_T1040_0 15 +#define XTENSA_HWVERSION_T1040_1 104001 /* versions T1040.1 */ +#define XTENSA_HWCIDSCHEME_T1040_1 01 +#define XTENSA_HWCIDVERS_T1040_1 32 +#define XTENSA_HWVERSION_T1040_1P 104001 /* versions T1040.1-prehotfix */ +#define XTENSA_HWCIDSCHEME_T1040_1P 10 +#define XTENSA_HWCIDVERS_T1040_1P 16 +#define XTENSA_HWVERSION_T1040_2 104002 /* versions T1040.2 */ +#define XTENSA_HWCIDSCHEME_T1040_2 01 +#define XTENSA_HWCIDVERS_T1040_2 33 +#define XTENSA_HWVERSION_T1040_3 104003 /* versions T1040.3 */ +#define XTENSA_HWCIDSCHEME_T1040_3 01 +#define XTENSA_HWCIDVERS_T1040_3 34 +#define XTENSA_HWVERSION_T1050_0 105000 /* versions T1050.0 */ +#define XTENSA_HWCIDSCHEME_T1050_0 1100 +#define XTENSA_HWCIDVERS_T1050_0 1 +#define XTENSA_HWVERSION_T1050_1 105001 /* versions T1050.1 */ +#define XTENSA_HWCIDSCHEME_T1050_1 1100 +#define XTENSA_HWCIDVERS_T1050_1 2 +#define XTENSA_HWVERSION_T1050_2 105002 /* versions T1050.2 */ +#define XTENSA_HWCIDSCHEME_T1050_2 1100 +#define XTENSA_HWCIDVERS_T1050_2 4 +#define XTENSA_HWVERSION_T1050_3 105003 /* versions T1050.3 */ +#define XTENSA_HWCIDSCHEME_T1050_3 1100 +#define XTENSA_HWCIDVERS_T1050_3 6 +#define XTENSA_HWVERSION_T1050_4 105004 /* versions T1050.4 */ +#define XTENSA_HWCIDSCHEME_T1050_4 1100 +#define XTENSA_HWCIDVERS_T1050_4 7 +#define XTENSA_HWVERSION_T1050_5 105005 /* versions T1050.5 */ +#define XTENSA_HWCIDSCHEME_T1050_5 1100 +#define XTENSA_HWCIDVERS_T1050_5 8 +#define XTENSA_HWVERSION_RA_2004_1 210000 /* versions LX1.0.0 */ +#define XTENSA_HWCIDSCHEME_RA_2004_1 1100 +#define XTENSA_HWCIDVERS_RA_2004_1 3 +#define XTENSA_HWVERSION_RA_2005_1 210001 /* versions LX1.0.1 */ +#define XTENSA_HWCIDSCHEME_RA_2005_1 1100 +#define XTENSA_HWCIDVERS_RA_2005_1 20 +#define XTENSA_HWVERSION_RA_2005_2 210002 /* versions LX1.0.2 */ +#define XTENSA_HWCIDSCHEME_RA_2005_2 1100 +#define XTENSA_HWCIDVERS_RA_2005_2 21 +#define XTENSA_HWVERSION_RA_2005_3 210003 /* versions LX1.0.3, X6.0.3 */ +#define XTENSA_HWCIDSCHEME_RA_2005_3 1100 +#define XTENSA_HWCIDVERS_RA_2005_3 22 +#define XTENSA_HWVERSION_RA_2006_4 210004 /* versions LX1.0.4, X6.0.4 */ +#define XTENSA_HWCIDSCHEME_RA_2006_4 1100 +#define XTENSA_HWCIDVERS_RA_2006_4 23 +#define XTENSA_HWVERSION_RA_2006_5 210005 /* versions LX1.0.5, X6.0.5 */ +#define XTENSA_HWCIDSCHEME_RA_2006_5 1100 +#define XTENSA_HWCIDVERS_RA_2006_5 24 +#define XTENSA_HWVERSION_RA_2006_6 210006 /* versions LX1.0.6, X6.0.6 */ +#define XTENSA_HWCIDSCHEME_RA_2006_6 1100 +#define XTENSA_HWCIDVERS_RA_2006_6 25 +#define XTENSA_HWVERSION_RA_2007_7 210007 /* versions LX1.0.7, X6.0.7 */ +#define XTENSA_HWCIDSCHEME_RA_2007_7 1100 +#define XTENSA_HWCIDVERS_RA_2007_7 26 +#define XTENSA_HWVERSION_RA_2008_8 210008 /* versions LX1.0.8, X6.0.8 */ +#define XTENSA_HWCIDSCHEME_RA_2008_8 1100 +#define XTENSA_HWCIDVERS_RA_2008_8 27 +#define XTENSA_HWVERSION_RB_2006_0 220000 /* versions LX2.0.0, X7.0.0 */ +#define XTENSA_HWCIDSCHEME_RB_2006_0 1100 +#define XTENSA_HWCIDVERS_RB_2006_0 48 +#define XTENSA_HWVERSION_RB_2007_1 220001 /* versions LX2.0.1, X7.0.1 */ +#define XTENSA_HWCIDSCHEME_RB_2007_1 1100 +#define XTENSA_HWCIDVERS_RB_2007_1 49 +#define XTENSA_HWVERSION_RB_2007_2 221000 /* versions LX2.1.0, X7.1.0 */ +#define XTENSA_HWCIDSCHEME_RB_2007_2 1100 +#define XTENSA_HWCIDVERS_RB_2007_2 52 +#define XTENSA_HWVERSION_RB_2008_3 221001 /* versions LX2.1.1, X7.1.1 */ +#define XTENSA_HWCIDSCHEME_RB_2008_3 1100 +#define XTENSA_HWCIDVERS_RB_2008_3 53 +#define XTENSA_HWVERSION_RB_2008_4 221002 /* versions LX2.1.2, X7.1.2 */ +#define XTENSA_HWCIDSCHEME_RB_2008_4 1100 +#define XTENSA_HWCIDVERS_RB_2008_4 54 +#define XTENSA_HWVERSION_RB_2009_5 221003 /* versions LX2.1.3, X7.1.3 */ +#define XTENSA_HWCIDSCHEME_RB_2009_5 1100 +#define XTENSA_HWCIDVERS_RB_2009_5 55 +#define XTENSA_HWVERSION_RB_2007_2_MP 221100 /* versions LX2.1.8-MP, X7.1.8-MP */ +#define XTENSA_HWCIDSCHEME_RB_2007_2_MP 1100 +#define XTENSA_HWCIDVERS_RB_2007_2_MP 64 +#define XTENSA_HWVERSION_RC_2009_0 230000 /* versions LX3.0.0, X8.0.0, MX1.0.0 */ +#define XTENSA_HWCIDSCHEME_RC_2009_0 1100 +#define XTENSA_HWCIDVERS_RC_2009_0 65 +#define XTENSA_HWVERSION_RC_2010_1 230001 /* versions LX3.0.1, X8.0.1, MX1.0.1 */ +#define XTENSA_HWCIDSCHEME_RC_2010_1 1100 +#define XTENSA_HWCIDVERS_RC_2010_1 66 +#define XTENSA_HWVERSION_RC_2010_2 230002 /* versions LX3.0.2, X8.0.2, MX1.0.2 */ +#define XTENSA_HWCIDSCHEME_RC_2010_2 1100 +#define XTENSA_HWCIDVERS_RC_2010_2 67 +#define XTENSA_HWVERSION_RC_2011_3 230003 /* versions LX3.0.3, X8.0.3, MX1.0.3 */ +#define XTENSA_HWCIDSCHEME_RC_2011_3 1100 +#define XTENSA_HWCIDVERS_RC_2011_3 68 +#define XTENSA_HWVERSION_RD_2010_0 240000 /* versions LX4.0.0, X9.0.0, MX1.1.0, TX1.0.0 */ +#define XTENSA_HWCIDSCHEME_RD_2010_0 1100 +#define XTENSA_HWCIDVERS_RD_2010_0 80 +#define XTENSA_HWVERSION_RD_2011_1 240001 /* versions LX4.0.1, X9.0.1, MX1.1.1, TX1.0.1 */ +#define XTENSA_HWCIDSCHEME_RD_2011_1 1100 +#define XTENSA_HWCIDVERS_RD_2011_1 81 +#define XTENSA_HWVERSION_RD_2011_2 240002 /* versions LX4.0.2, X9.0.2, MX1.1.2, TX1.0.2 */ +#define XTENSA_HWCIDSCHEME_RD_2011_2 1100 +#define XTENSA_HWCIDVERS_RD_2011_2 82 +#define XTENSA_HWVERSION_RD_2011_3 240003 /* versions LX4.0.3, X9.0.3, MX1.1.3, TX1.0.3 */ +#define XTENSA_HWCIDSCHEME_RD_2011_3 1100 +#define XTENSA_HWCIDVERS_RD_2011_3 83 +#define XTENSA_HWVERSION_RD_2012_4 240004 /* versions LX4.0.4, X9.0.4, MX1.1.4, TX1.0.4 */ +#define XTENSA_HWCIDSCHEME_RD_2012_4 1100 +#define XTENSA_HWCIDVERS_RD_2012_4 84 +#define XTENSA_HWVERSION_RD_2012_5 240005 /* versions LX4.0.5, X9.0.5, MX1.1.5, TX1.0.5 */ +#define XTENSA_HWCIDSCHEME_RD_2012_5 1100 +#define XTENSA_HWCIDVERS_RD_2012_5 85 +#define XTENSA_HWVERSION_RE_2012_0 250000 /* versions LX5.0.0, X10.0.0, MX1.2.0, TX2.0.0 */ +#define XTENSA_HWCIDSCHEME_RE_2012_0 1100 +#define XTENSA_HWCIDVERS_RE_2012_0 96 +#define XTENSA_HWVERSION_RE_2012_1 250001 /* versions LX5.0.1, X10.0.1, MX1.2.1, TX2.0.1 */ +#define XTENSA_HWCIDSCHEME_RE_2012_1 1100 +#define XTENSA_HWCIDVERS_RE_2012_1 97 +#define XTENSA_HWVERSION_RE_2013_2 250002 /* versions LX5.0.2, X10.0.2, MX1.2.2, TX2.0.2 */ +#define XTENSA_HWCIDSCHEME_RE_2013_2 1100 +#define XTENSA_HWCIDVERS_RE_2013_2 98 +#define XTENSA_HWVERSION_RE_2013_3 250003 /* versions LX5.0.3, X10.0.3, MX1.2.3, TX2.0.3 */ +#define XTENSA_HWCIDSCHEME_RE_2013_3 1100 +#define XTENSA_HWCIDVERS_RE_2013_3 99 +#define XTENSA_HWVERSION_RE_2013_4 250004 /* versions LX5.0.4, X10.0.4, MX1.2.4, TX2.0.4 */ +#define XTENSA_HWCIDSCHEME_RE_2013_4 1100 +#define XTENSA_HWCIDVERS_RE_2013_4 100 +#define XTENSA_HWVERSION_RE_2014_5 250005 /* versions LX5.0.5, X10.0.5, MX1.2.5, TX2.0.5 */ +#define XTENSA_HWCIDSCHEME_RE_2014_5 1100 +#define XTENSA_HWCIDVERS_RE_2014_5 101 +#define XTENSA_HWVERSION_RE_2015_6 250006 /* versions LX5.0.6, X10.0.6, MX1.2.6, TX2.0.6 */ +#define XTENSA_HWCIDSCHEME_RE_2015_6 1100 +#define XTENSA_HWCIDVERS_RE_2015_6 102 +#define XTENSA_HWVERSION_RF_2014_0 260000 /* versions LX6.0.0, X11.0.0, MX1.3.0, TX3.0.0 */ +#define XTENSA_HWCIDSCHEME_RF_2014_0 1100 +#define XTENSA_HWCIDVERS_RF_2014_0 112 +#define XTENSA_HWVERSION_RF_2014_1 260001 /* versions LX6.0.1, X11.0.1 */ +#define XTENSA_HWCIDSCHEME_RF_2014_1 1100 +#define XTENSA_HWCIDVERS_RF_2014_1 113 +#define XTENSA_HWVERSION_RF_2015_2 260002 /* versions LX6.0.2, X11.0.2 */ +#define XTENSA_HWCIDSCHEME_RF_2015_2 1100 +#define XTENSA_HWCIDVERS_RF_2015_2 114 +#define XTENSA_HWVERSION_RF_2015_3 260003 /* versions LX6.0.3, X11.0.3 */ +#define XTENSA_HWCIDSCHEME_RF_2015_3 1100 +#define XTENSA_HWCIDVERS_RF_2015_3 115 +#define XTENSA_HWVERSION_RG_2015_0 270000 /* versions LX7.0.0, X12.0.0, NX1.0.0, SX1.0.0, MX1.4.0, TX4.0.0 */ +#define XTENSA_HWCIDSCHEME_RG_2015_0 1100 +#define XTENSA_HWCIDVERS_RG_2015_0 128 + +/* Software (Xtensa Tools) versions: */ +#define XTENSA_SWVERSION_T1020_0 102000 /* versions T1020.0 */ +#define XTENSA_SWVERSION_T1020_1 102001 /* versions T1020.1 */ +#define XTENSA_SWVERSION_T1020_2B 102002 /* versions T1020.2b */ +#define XTENSA_SWVERSION_T1020_2 102002 /* versions T1020.2 */ +#define XTENSA_SWVERSION_T1020_3 102003 /* versions T1020.3 */ +#define XTENSA_SWVERSION_T1020_4 102004 /* versions T1020.4 */ +#define XTENSA_SWVERSION_T1030_0 103000 /* versions T1030.0 */ +#define XTENSA_SWVERSION_T1030_1 103001 /* versions T1030.1 */ +#define XTENSA_SWVERSION_T1030_2 103002 /* versions T1030.2 */ +#define XTENSA_SWVERSION_T1030_3 103003 /* versions T1030.3 */ +#define XTENSA_SWVERSION_T1040_0 104000 /* versions T1040.0 */ +#define XTENSA_SWVERSION_T1040_1 104001 /* versions T1040.1 */ +#define XTENSA_SWVERSION_T1040_1P 104001 /* versions T1040.1-prehotfix */ +#define XTENSA_SWVERSION_T1040_2 104002 /* versions T1040.2 */ +#define XTENSA_SWVERSION_T1040_3 104003 /* versions T1040.3 */ +#define XTENSA_SWVERSION_T1050_0 105000 /* versions T1050.0 */ +#define XTENSA_SWVERSION_T1050_1 105001 /* versions T1050.1 */ +#define XTENSA_SWVERSION_T1050_2 105002 /* versions T1050.2 */ +#define XTENSA_SWVERSION_T1050_3 105003 /* versions T1050.3 */ +#define XTENSA_SWVERSION_T1050_4 105004 /* versions T1050.4 */ +#define XTENSA_SWVERSION_T1050_5 105005 /* versions T1050.5 */ +#define XTENSA_SWVERSION_RA_2004_1 600000 /* versions 6.0.0 */ +#define XTENSA_SWVERSION_RA_2005_1 600001 /* versions 6.0.1 */ +#define XTENSA_SWVERSION_RA_2005_2 600002 /* versions 6.0.2 */ +#define XTENSA_SWVERSION_RA_2005_3 600003 /* versions 6.0.3 */ +#define XTENSA_SWVERSION_RA_2006_4 600004 /* versions 6.0.4 */ +#define XTENSA_SWVERSION_RA_2006_5 600005 /* versions 6.0.5 */ +#define XTENSA_SWVERSION_RA_2006_6 600006 /* versions 6.0.6 */ +#define XTENSA_SWVERSION_RA_2007_7 600007 /* versions 6.0.7 */ +#define XTENSA_SWVERSION_RA_2008_8 600008 /* versions 6.0.8 */ +#define XTENSA_SWVERSION_RB_2006_0 700000 /* versions 7.0.0 */ +#define XTENSA_SWVERSION_RB_2007_1 700001 /* versions 7.0.1 */ +#define XTENSA_SWVERSION_RB_2007_2 701000 /* versions 7.1.0 */ +#define XTENSA_SWVERSION_RB_2008_3 701001 /* versions 7.1.1 */ +#define XTENSA_SWVERSION_RB_2008_4 701002 /* versions 7.1.2 */ +#define XTENSA_SWVERSION_RB_2009_5 701003 /* versions 7.1.3 */ +#define XTENSA_SWVERSION_RB_2007_2_MP 701100 /* versions 7.1.8-MP */ +#define XTENSA_SWVERSION_RC_2009_0 800000 /* versions 8.0.0 */ +#define XTENSA_SWVERSION_RC_2010_1 800001 /* versions 8.0.1 */ +#define XTENSA_SWVERSION_RC_2010_2 800002 /* versions 8.0.2 */ +#define XTENSA_SWVERSION_RC_2011_3 800003 /* versions 8.0.3 */ +#define XTENSA_SWVERSION_RD_2010_0 900000 /* versions 9.0.0 */ +#define XTENSA_SWVERSION_RD_2011_1 900001 /* versions 9.0.1 */ +#define XTENSA_SWVERSION_RD_2011_2 900002 /* versions 9.0.2 */ +#define XTENSA_SWVERSION_RD_2011_3 900003 /* versions 9.0.3 */ +#define XTENSA_SWVERSION_RD_2012_4 900004 /* versions 9.0.4 */ +#define XTENSA_SWVERSION_RD_2012_5 900005 /* versions 9.0.5 */ +#define XTENSA_SWVERSION_RE_2012_0 1000000 /* versions 10.0.0 */ +#define XTENSA_SWVERSION_RE_2012_1 1000001 /* versions 10.0.1 */ +#define XTENSA_SWVERSION_RE_2013_2 1000002 /* versions 10.0.2 */ +#define XTENSA_SWVERSION_RE_2013_3 1000003 /* versions 10.0.3 */ +#define XTENSA_SWVERSION_RE_2013_4 1000004 /* versions 10.0.4 */ +#define XTENSA_SWVERSION_RE_2014_5 1000005 /* versions 10.0.5 */ +#define XTENSA_SWVERSION_RE_2015_6 1000006 /* versions 10.0.6 */ +#define XTENSA_SWVERSION_RF_2014_0 1100000 /* versions 11.0.0 */ +#define XTENSA_SWVERSION_RF_2014_1 1100001 /* versions 11.0.1 */ +#define XTENSA_SWVERSION_RF_2015_2 1100002 /* versions 11.0.2 */ +#define XTENSA_SWVERSION_RF_2015_3 1100003 /* versions 11.0.3 */ +#define XTENSA_SWVERSION_RG_2015_0 1200000 /* versions 12.0.0 */ +#define XTENSA_SWVERSION_T1040_1_PREHOTFIX XTENSA_SWVERSION_T1040_1P /* T1040.1-prehotfix */ +#define XTENSA_SWVERSION_6_0_0 XTENSA_SWVERSION_RA_2004_1 /* 6.0.0 */ +#define XTENSA_SWVERSION_6_0_1 XTENSA_SWVERSION_RA_2005_1 /* 6.0.1 */ +#define XTENSA_SWVERSION_6_0_2 XTENSA_SWVERSION_RA_2005_2 /* 6.0.2 */ +#define XTENSA_SWVERSION_6_0_3 XTENSA_SWVERSION_RA_2005_3 /* 6.0.3 */ +#define XTENSA_SWVERSION_6_0_4 XTENSA_SWVERSION_RA_2006_4 /* 6.0.4 */ +#define XTENSA_SWVERSION_6_0_5 XTENSA_SWVERSION_RA_2006_5 /* 6.0.5 */ +#define XTENSA_SWVERSION_6_0_6 XTENSA_SWVERSION_RA_2006_6 /* 6.0.6 */ +#define XTENSA_SWVERSION_6_0_7 XTENSA_SWVERSION_RA_2007_7 /* 6.0.7 */ +#define XTENSA_SWVERSION_6_0_8 XTENSA_SWVERSION_RA_2008_8 /* 6.0.8 */ +#define XTENSA_SWVERSION_7_0_0 XTENSA_SWVERSION_RB_2006_0 /* 7.0.0 */ +#define XTENSA_SWVERSION_7_0_1 XTENSA_SWVERSION_RB_2007_1 /* 7.0.1 */ +#define XTENSA_SWVERSION_7_1_0 XTENSA_SWVERSION_RB_2007_2 /* 7.1.0 */ +#define XTENSA_SWVERSION_7_1_1 XTENSA_SWVERSION_RB_2008_3 /* 7.1.1 */ +#define XTENSA_SWVERSION_7_1_2 XTENSA_SWVERSION_RB_2008_4 /* 7.1.2 */ +#define XTENSA_SWVERSION_7_1_3 XTENSA_SWVERSION_RB_2009_5 /* 7.1.3 */ +#define XTENSA_SWVERSION_7_1_8_MP XTENSA_SWVERSION_RB_2007_2_MP /* 7.1.8-MP */ +#define XTENSA_SWVERSION_8_0_0 XTENSA_SWVERSION_RC_2009_0 /* 8.0.0 */ +#define XTENSA_SWVERSION_8_0_1 XTENSA_SWVERSION_RC_2010_1 /* 8.0.1 */ +#define XTENSA_SWVERSION_8_0_2 XTENSA_SWVERSION_RC_2010_2 /* 8.0.2 */ +#define XTENSA_SWVERSION_8_0_3 XTENSA_SWVERSION_RC_2011_3 /* 8.0.3 */ +#define XTENSA_SWVERSION_9_0_0 XTENSA_SWVERSION_RD_2010_0 /* 9.0.0 */ +#define XTENSA_SWVERSION_9_0_1 XTENSA_SWVERSION_RD_2011_1 /* 9.0.1 */ +#define XTENSA_SWVERSION_9_0_2 XTENSA_SWVERSION_RD_2011_2 /* 9.0.2 */ +#define XTENSA_SWVERSION_9_0_3 XTENSA_SWVERSION_RD_2011_3 /* 9.0.3 */ +#define XTENSA_SWVERSION_9_0_4 XTENSA_SWVERSION_RD_2012_4 /* 9.0.4 */ +#define XTENSA_SWVERSION_9_0_5 XTENSA_SWVERSION_RD_2012_5 /* 9.0.5 */ +#define XTENSA_SWVERSION_10_0_0 XTENSA_SWVERSION_RE_2012_0 /* 10.0.0 */ +#define XTENSA_SWVERSION_10_0_1 XTENSA_SWVERSION_RE_2012_1 /* 10.0.1 */ +#define XTENSA_SWVERSION_10_0_2 XTENSA_SWVERSION_RE_2013_2 /* 10.0.2 */ +#define XTENSA_SWVERSION_10_0_3 XTENSA_SWVERSION_RE_2013_3 /* 10.0.3 */ +#define XTENSA_SWVERSION_10_0_4 XTENSA_SWVERSION_RE_2013_4 /* 10.0.4 */ +#define XTENSA_SWVERSION_10_0_5 XTENSA_SWVERSION_RE_2014_5 /* 10.0.5 */ +#define XTENSA_SWVERSION_10_0_6 XTENSA_SWVERSION_RE_2015_6 /* 10.0.6 */ +#define XTENSA_SWVERSION_11_0_0 XTENSA_SWVERSION_RF_2014_0 /* 11.0.0 */ +#define XTENSA_SWVERSION_11_0_1 XTENSA_SWVERSION_RF_2014_1 /* 11.0.1 */ +#define XTENSA_SWVERSION_11_0_2 XTENSA_SWVERSION_RF_2015_2 /* 11.0.2 */ +#define XTENSA_SWVERSION_11_0_3 XTENSA_SWVERSION_RF_2015_3 /* 11.0.3 */ +#define XTENSA_SWVERSION_12_0_0 XTENSA_SWVERSION_RG_2015_0 /* 12.0.0 */ + + +/* The current release: */ +#define XTENSA_RELEASE_NAME "RF-2015.3" +#define XTENSA_RELEASE_CANONICAL_NAME "RF-2015.3" + +/* The product versions within the current release: */ +#define XTENSA_SWVERSION XTENSA_SWVERSION_RF_2015_3 +#define XTENSA_SWVERSION_NAME "11.0.3" +#define XTENSA_SWVERSION_CANONICAL_NAME "11.0.3" +#define XTENSA_SWVERSION_MAJORMID_NAME "11.0" +#define XTENSA_SWVERSION_MAJOR_NAME "11" +/* For product licensing (not necessarily same as *_MAJORMID_NAME): */ +#define XTENSA_SWVERSION_LICENSE_NAME "11.0" + +/* Note: there may be multiple hardware products in one release, + and software can target older hardware, so the notion of + "current" hardware versions is partially configuration dependent. + For now, "current" hardware product version info is left out + to avoid confusion. */ + +#endif /*XTENSA_VERSIONS_H*/ + diff --git a/tools/sdk/include/esp32/xtensa/xtensa-xer.h b/tools/sdk/include/esp32/xtensa/xtensa-xer.h new file mode 100755 index 00000000..900bda33 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/xtensa-xer.h @@ -0,0 +1,149 @@ +/* xer-constants.h -- various constants describing external registers accessed + via wer and rer. + + TODO: find a better prefix. Also conditionalize certain constants based + on number of cores and interrupts actually present. +*/ + +/* + * Copyright (c) 1999-2008 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include + +#define NUM_INTERRUPTS 27 +#define NUM_CORES 4 + +/* Routing of NMI (BInterrupt2) and interrupts 0..n-1 (BInterrupt3+) + RER reads + WER writes + */ + +#define XER_MIROUT 0x0000 +#define XER_MIROUT_LAST (XER_MIROUT + NUM_INTERRUPTS) + + +/* IPI to core M (all 16 causes). + + RER reads + WER clears + */ +#define XER_MIPICAUSE 0x0100 +#define XER_MIPICAUSE_FIELD_A_FIRST 0x0 +#define XER_MIPICAUSE_FIELD_A_LAST 0x0 +#define XER_MIPICAUSE_FIELD_B_FIRST 0x1 +#define XER_MIPICAUSE_FIELD_B_LAST 0x3 +#define XER_MIPICAUSE_FIELD_C_FIRST 0x4 +#define XER_MIPICAUSE_FIELD_C_LAST 0x7 +#define XER_MIPICAUSE_FIELD_D_FIRST 0x8 +#define XER_MIPICAUSE_FIELD_D_LAST 0xF + + +/* IPI from cause bit 0..15 + + RER invalid + WER sets +*/ +#define XER_MIPISET 0x0140 +#define XER_MIPISET_LAST 0x014F + + +/* Global enable + + RER read + WER clear +*/ +#define XER_MIENG 0x0180 + + +/* Global enable + + RER invalid + WER set +*/ +#define XER_MIENG_SET 0x0184 + +/* Global assert + + RER read + WER clear +*/ +#define XER_MIASG 0x0188 + + +/* Global enable + + RER invalid + WER set +*/ +#define XER_MIASG_SET 0x018C + + +/* IPI partition register + + RER read + WER write +*/ +#define XER_PART 0x0190 +#define XER_IPI0 0x0 +#define XER_IPI1 0x1 +#define XER_IPI2 0x2 +#define XER_IPI3 0x3 + +#define XER_PART_ROUTE_IPI(NUM, FIELD) ((NUM) << ((FIELD) << 2)) + +#define XER_PART_ROUTE_IPI_CAUSE(TO_A, TO_B, TO_C, TO_D) \ + (XER_PART_ROUTE_IPI(TO_A, XER_IPI0) | \ + XER_PART_ROUTE_IPI(TO_B, XER_IPI1) | \ + XER_PART_ROUTE_IPI(TO_C, XER_IPI2) | \ + XER_PART_ROUTE_IPI(TO_D, XER_IPI3)) + +#define XER_IPI_WAKE_EXT_INTERRUPT XCHAL_EXTINT0_NUM +#define XER_IPI_WAKE_CAUSE XER_MIPICAUSE_FIELD_C_FIRST +#define XER_IPI_WAKE_ADDRESS (XER_MIPISET + XER_IPI_WAKE_CAUSE) +#define XER_DEFAULT_IPI_ROUTING XER_PART_ROUTE_IPI_CAUSE(XER_IPI1, XER_IPI0, XER_IPI2, XER_IPI3) + + +/* System configuration ID + + RER read + WER invalid +*/ +#define XER_SYSCFGID 0x01A0 + + +/* RunStall to slave processors + + RER read + WER write +*/ +#define XER_MPSCORE 0x0200 + + +/* Cache coherency ON + + RER read + WER write +*/ +#define XER_CCON 0x0220 + + diff --git a/tools/sdk/include/esp32/xtensa/xtkc705.h b/tools/sdk/include/esp32/xtensa/xtkc705.h new file mode 100755 index 00000000..831c15d5 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/xtkc705.h @@ -0,0 +1,14 @@ +/* Copyright (c) 2006-2013 by Tensilica Inc. ALL RIGHTS RESERVED. +/ These coded instructions, statements, and computer programs are the +/ copyrighted works and confidential proprietary information of Tensilica Inc. +/ They may not be modified, copied, reproduced, distributed, or disclosed to +/ third parties in any manner, medium, or form, in whole or in part, without +/ the prior written consent of Tensilica Inc. +*/ + +/* xtkc705.h - Xtensa Xilinx KC705 (XT-KC705) board specific definitions */ + +/* 99.9% same as ML605, just indicate we're KC705 and include ML605 header: */ +#define XTBOARD_IS_KC705 1 +#include + diff --git a/tools/sdk/include/esp32/xtensa/xtkc705/xtensa/board.h b/tools/sdk/include/esp32/xtensa/xtkc705/xtensa/board.h new file mode 100755 index 00000000..5d2d8348 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/xtkc705/xtensa/board.h @@ -0,0 +1,13 @@ +/* + * board.h - Include board-specific definitions + * + * Copyright (c) 2013 by Tensilica Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of Tensilica Inc. + * They may not be modified, copied, reproduced, distributed, or disclosed to + * third parties in any manner, medium, or form, in whole or in part, without + * the prior written consent of Tensilica Inc. + */ + +#include + diff --git a/tools/sdk/include/esp32/xtensa/xtload-api.h b/tools/sdk/include/esp32/xtensa/xtload-api.h new file mode 100755 index 00000000..4e2297f5 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/xtload-api.h @@ -0,0 +1,77 @@ +/* Customer ID=11656; Build=0x5f626; Copyright (c) 2003-2012 Tensilica Inc. ALL RIGHTS RESERVED. + These coded instructions, statements, and computer programs are the + copyrighted works and confidential proprietary information of Tensilica Inc. + They may not be modified, copied, reproduced, distributed, or disclosed to + third parties in any manner, medium, or form, in whole or in part, without + the prior written consent of Tensilica Inc. */ + +#ifndef _XTLOAD_API_H +#define _XTLOAD_API_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define XTENSA_BYTES_PER_WORD 4 +#define XLOAD_ALL_CORES -1 + +typedef int core_number_t; +typedef uint32_t xtload_address_t; +typedef uint32_t xtload_word_count_t; +typedef uint32_t * xtload_word_ptr_t; + +/* These functions correspond one-to-one with xt-load script + commands. See the documentation for xt-load for their usage. + + There are however, several higher-level script commands--such as + load-elf-file--which don't have direct analogues here. These + "missing" commands are essentially just macros that result in + several of these commands below. Note that you can execute several + of these commands, then the results of a script, or vice-versa. + */ + +void xtload_bootloader_wake (void); +void xtload_bootloader_sleep (void); +void xtload_bootloader_done (void); +void xtload_bootloader_not_done (void); +void xtload_reset_and_cont (core_number_t core); +void xtload_stall_and_reset (core_number_t core); +#define xtload_reset_and_stall xtload_stall_and_reset +void xtload_stall_and_target (core_number_t core); +void xtload_ignore_and_stall (core_number_t core); +void xtload_ignore_and_cont (core_number_t core); +#define xtload_ignore_and_continue xtload_ignore_and_cont +void xtload_read_words (xtload_address_t addr, xtload_word_count_t count); +void xtload_zero_words (xtload_address_t addr, xtload_word_count_t count); +void xtload_write_words (int swap, xtload_address_t addr, + xtload_word_ptr_t ptr, xtload_word_count_t count); +void xtload_setup_write_words (xtload_address_t addr, xtload_word_count_t count); +void xtload_read_register (core_number_t core); + +/* *I M P O R T A N T* + + The bootloader API calls this function whenever it outputs a word + to the bootloader hardware chain. + + Because the API has no information about how the bootloader + hardware is connected to the host hardware, the user must + implement this function to write a word to the bootloader's register. + + A user's implementation might write the bytes to an Xtensa queue or + to a memory-mapped register. + + For example, xt-load uses this API just like any other client. Its + implementation of this function simply writes this word to an + output file. +*/ + +void xtload_user_output_word (uint32_t word); + +#ifdef __cplusplus +} +#endif + +#endif /* _XTLOAD_API_H */ + diff --git a/tools/sdk/include/esp32/xtensa/xtml605.h b/tools/sdk/include/esp32/xtensa/xtml605.h new file mode 100755 index 00000000..5f54d700 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/xtml605.h @@ -0,0 +1,338 @@ +/* Copyright (c) 2007-2013 by Tensilica Inc. ALL RIGHTS RESERVED. +/ These coded instructions, statements, and computer programs are the +/ copyrighted works and confidential proprietary information of Tensilica Inc. +/ They may not be modified, copied, reproduced, distributed, or disclosed to +/ third parties in any manner, medium, or form, in whole or in part, without +/ the prior written consent of Tensilica Inc. +*/ + +/* xtml605.h - Xtensa Xilinx ML605 (XT-ML605) board specific definitions */ +/* xtkc705.h - Also includes this, for the Xilinx KC705 (XT-KC705). */ + +#ifndef _INC_ML605_H_ +#define _INC_ML605_H_ + +#include +#include + +#if XTBOARD_IS_KC705 +#define XTBOARD_NAME "XT-KC705" +#else +#define XTBOARD_NAME "XT-ML605" +#endif + + +/* + * Default assignment of ML605 devices to external interrupts. + */ + +/* Ethernet interrupt: */ +#ifdef XCHAL_EXTINT1_NUM +#define ETHERNET_INTNUM XCHAL_EXTINT1_NUM +#define ETHERNET_INTLEVEL XCHAL_EXTINT1_LEVEL +#define ETHERNET_INTMASK XCHAL_EXTINT1_MASK +#else +#define ETHERNET_INTMASK 0 +#endif + +/* UART interrupt: */ +#ifdef XCHAL_EXTINT0_NUM +#define UART16550_INTNUM XCHAL_EXTINT0_NUM +#define UART16550_INTLEVEL XCHAL_EXTINT0_LEVEL +#define UART16550_INTMASK XCHAL_EXTINT0_MASK +#else +#define UART16550_INTMASK 0 +#endif + +/* Audio output interrupt (I2S transmitter FIFO): */ +#ifdef XCHAL_EXTINT2_NUM +#define AUDIO_I2S_OUT_INTNUM XCHAL_EXTINT2_NUM +#define AUDIO_I2S_OUT_INTLEVEL XCHAL_EXTINT2_LEVEL +#define AUDIO_I2S_OUT_INTMASK XCHAL_EXTINT2_MASK +#else +#define AUDIO_I2S_OUT_INTMASK 0 +#endif + +/* Audio input interrupt (I2S receiver FIFO): */ +#ifdef XCHAL_EXTINT3_NUM +#define AUDIO_I2S_IN_INTNUM XCHAL_EXTINT3_NUM +#define AUDIO_I2S_IN_INTLEVEL XCHAL_EXTINT3_LEVEL +#define AUDIO_I2S_IN_INTMASK XCHAL_EXTINT3_MASK +#else +#define AUDIO_I2S_IN_INTMASK 0 +#endif + +/* I2C interrupt */ +#ifdef XCHAL_EXTINT4_NUM +#define I2C_INTNUM XCHAL_EXTINT4_NUM +#define I2C_INTLEVEL XCHAL_EXTINT4_LEVEL +#define I2C_INTMASK XCHAL_EXTINT4_MASK +#else +#define I2C_INTMASK 0 +#endif + +/* USB interrupt */ +#ifdef XCHAL_EXTINT5_NUM +#define USB_INTNUM XCHAL_EXTINT5_NUM +#define USB_INTLEVEL XCHAL_EXTINT5_LEVEL +#define USB_INTMASK XCHAL_EXTINT5_MASK +#else +#define USB_INTMASK 0 +#endif + +/* + * Device addresses. + * + * Note: for endianness-independence, use 32-bit loads and stores for all + * register accesses to Ethernet, UART and LED devices. Undefined bits + * may need to be masked out if needed when reading if the actual register + * size is smaller than 32 bits. + * + * Note: ML605 bus byte lanes are defined in terms of msbyte and lsbyte + * relative to the processor. So 32-bit registers are accessed consistently + * from both big and little endian processors. However, this means byte + * sequences are not consistent between big and little endian processors. + * This is fine for RAM, and for ROM if ROM is created for a specific + * processor (and thus has correct byte sequences). However this may be + * unexpected for Flash, which might contain a file-system that one wants + * to use for multiple processor configurations (eg. the Flash might contain + * the Ethernet card's address, endianness-independent application data, etc). + * That is, byte sequences written in Flash by a core of a given endianness + * will be byte-swapped when seen by a core of the other endianness. + * Someone implementing an endianness-independent Flash file system will + * likely handle this byte-swapping issue in the Flash driver software. + */ + +#define ML605_FLASH_MAXSIZE 0x01000000 /* 16 MB */ +#define ML605_FLASH_IOBLOCK_OFS 0x08000000 + +#define KC705_FLASH_MAXSIZE 0x08000000 /* 128 MB */ +#define KC705_FLASH_IOBLOCK_OFS 0x00000000 + +#if XTBOARD_IS_KC705 +#define XTBOARD_FLASH_MAXSIZE KC705_FLASH_MAXSIZE +#define XTBOARD_FLASH_IO_OFS KC705_FLASH_IOBLOCK_OFS +#else +#define XTBOARD_FLASH_MAXSIZE ML605_FLASH_MAXSIZE +#define XTBOARD_FLASH_IO_OFS ML605_FLASH_IOBLOCK_OFS +#endif + +#ifdef XSHAL_IOBLOCK_BYPASS_PADDR + +/* Flash Memory: */ +# define XTBOARD_FLASH_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+XTBOARD_FLASH_IO_OFS) + +/* FPGA registers: */ +# define XTBOARD_FPGAREGS_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D020000) + +/* Ethernet controller/transceiver SONIC SN83934: */ +# define ETHERNET_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D030000) + + +/* UART National-Semi PC16550D: */ +# define UART16550_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D050000) + +/* I2S transmitter */ +# define AUDIO_I2S_OUT_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D080000) + +/* I2S receiver */ +# define AUDIO_I2S_IN_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D088000) + +/* I2C master */ +# define I2C_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D090000) + +/* SPI controller */ +# define SPI_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D0A0000) + +/* Display controller Sunplus SPLC780D, 4bit mode, + * LCD Display MYTech MOC-16216B-B: */ +# define SPLC780D_4BIT_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D0C0000) + +/* USB Controller */ +# define USB_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D0D0000) + +/* Ethernet buffer: */ +# define ETHERNET_BUFFER_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D800000) + +#endif /* XSHAL_IOBLOCK_BYPASS_PADDR */ + +/* These devices might be accessed cached: */ +#ifdef XSHAL_IOBLOCK_CACHED_PADDR +# define XTBOARD_FLASH_CACHED_PADDR (XSHAL_IOBLOCK_CACHED_PADDR+XTBOARD_FLASH_IO_OFS) +# define ETHERNET_BUFFER_CACHED_PADDR (XSHAL_IOBLOCK_CACHED_PADDR+0x0D800000) +#endif /* XSHAL_IOBLOCK_CACHED_PADDR */ + + +/*** Same thing over again, this time with virtual addresses: ***/ + +#ifdef XSHAL_IOBLOCK_BYPASS_VADDR + +/* Flash Memory: */ +# define XTBOARD_FLASH_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+XTBOARD_FLASH_IO_OFS) + +/* FPGA registers: */ +# define XTBOARD_FPGAREGS_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D020000) + +/* Ethernet controller/transceiver SONIC SN83934: */ +# define ETHERNET_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D030000) + + +/* UART National-Semi PC16550D: */ +# define UART16550_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D050000) + +/* I2S transmitter */ +# define AUDIO_I2S_OUT_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D080000) + +/* I2S receiver */ +# define AUDIO_I2S_IN_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D088000) + +/* I2C master */ +# define I2C_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D090000) + +/* SPI controller */ +# define SPI_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D0A0000) + +/* Display controller Sunplus SPLC780D, 4bit mode, + * LCD Display MYTech MOC-16216B-B: */ +# define SPLC780D_4BIT_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D0C0000) + +/* USB Controller */ +# define USB_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D0D0000) + +/* Ethernet buffer: */ +# define ETHERNET_BUFFER_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D800000) + +#endif /* XSHAL_IOBLOCK_BYPASS_VADDR */ + +/* These devices might be accessed cached: */ +#ifdef XSHAL_IOBLOCK_CACHED_VADDR +# define XTBOARD_FLASH_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+XTBOARD_FLASH_IO_OFS) +# define ETHERNET_BUFFER_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+0x0D800000) +#endif /* XSHAL_IOBLOCK_CACHED_VADDR */ + + +/* System ROM: */ +#define XTBOARD_ROM_SIZE XSHAL_ROM_SIZE +#ifdef XSHAL_ROM_VADDR +#define XTBOARD_ROM_VADDR XSHAL_ROM_VADDR +#endif +#ifdef XSHAL_ROM_PADDR +#define XTBOARD_ROM_PADDR XSHAL_ROM_PADDR +#endif + +/* System RAM: */ +#define XTBOARD_RAM_SIZE XSHAL_RAM_SIZE +#ifdef XSHAL_RAM_VADDR +#define XTBOARD_RAM_VADDR XSHAL_RAM_VADDR +#endif +#ifdef XSHAL_RAM_PADDR +#define XTBOARD_RAM_PADDR XSHAL_RAM_PADDR +#endif +#define XTBOARD_RAM_BYPASS_VADDR XSHAL_RAM_BYPASS_VADDR +#define XTBOARD_RAM_BYPASS_PADDR XSHAL_RAM_BYPASS_PADDR + + + +/* + * Things that depend on device addresses. + */ + + +#define XTBOARD_CACHEATTR_WRITEBACK XSHAL_XT2000_CACHEATTR_WRITEBACK +#define XTBOARD_CACHEATTR_WRITEALLOC XSHAL_XT2000_CACHEATTR_WRITEALLOC +#define XTBOARD_CACHEATTR_WRITETHRU XSHAL_XT2000_CACHEATTR_WRITETHRU +#define XTBOARD_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS +#define XTBOARD_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT + +#define XTBOARD_BUSINT_PIPE_REGIONS XSHAL_XT2000_PIPE_REGIONS +#define XTBOARD_BUSINT_SDRAM_REGIONS XSHAL_XT2000_SDRAM_REGIONS + + +/* + * FPGA registers. + * All these registers are normally accessed using 32-bit loads/stores. + */ + +/* Register offsets: */ +#define XTBOARD_DATECD_OFS 0x00 /* date code (read-only) */ +#define XTBOARD_CLKFRQ_OFS 0x04 /* clock frequency Hz (read-only) */ +#define XTBOARD_SYSLED_OFS 0x08 /* LEDs */ +#define XTBOARD_DIPSW_OFS 0x0C /* DIP switch bits (read-only) */ +#define XTBOARD_SWRST_OFS 0x10 /* software reset */ + +/* Physical register addresses: */ +#ifdef XTBOARD_FPGAREGS_PADDR +#define XTBOARD_DATECD_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_DATECD_OFS) +#define XTBOARD_CLKFRQ_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_CLKFRQ_OFS) +#define XTBOARD_SYSLED_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_SYSLED_OFS) +#define XTBOARD_DIPSW_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_DIPSW_OFS) +#define XTBOARD_SWRST_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_SWRST_OFS) +#endif + +/* Virtual register addresses: */ +#ifdef XTBOARD_FPGAREGS_VADDR +#define XTBOARD_DATECD_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_DATECD_OFS) +#define XTBOARD_CLKFRQ_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_CLKFRQ_OFS) +#define XTBOARD_SYSLED_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_SYSLED_OFS) +#define XTBOARD_DIPSW_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_DIPSW_OFS) +#define XTBOARD_SWRST_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_SWRST_OFS) +/* Register access (for C code): */ +#define XTBOARD_DATECD_REG (*(volatile unsigned*) XTBOARD_DATECD_VADDR) +#define XTBOARD_CLKFRQ_REG (*(volatile unsigned*) XTBOARD_CLKFRQ_VADDR) +#define XTBOARD_SYSLED_REG (*(volatile unsigned*) XTBOARD_SYSLED_VADDR) +#define XTBOARD_DIPSW_REG (*(volatile unsigned*) XTBOARD_DIPSW_VADDR) +#define XTBOARD_SWRST_REG (*(volatile unsigned*) XTBOARD_SWRST_VADDR) +#endif + +/* DATECD (date code; when core was built) bit fields: */ +/* BCD-coded month (01..12): */ +#define XTBOARD_DATECD_MONTH_SHIFT 24 +#define XTBOARD_DATECD_MONTH_BITS 8 +#define XTBOARD_DATECD_MONTH_MASK 0xFF000000 +/* BCD-coded day (01..31): */ +#define XTBOARD_DATECD_DAY_SHIFT 16 +#define XTBOARD_DATECD_DAY_BITS 8 +#define XTBOARD_DATECD_DAY_MASK 0x00FF0000 +/* BCD-coded year (2001..9999): */ +#define XTBOARD_DATECD_YEAR_SHIFT 0 +#define XTBOARD_DATECD_YEAR_BITS 16 +#define XTBOARD_DATECD_YEAR_MASK 0x0000FFFF + +/* SYSLED (system LED) bit fields: */ + +/* LED control bits (off=0, on=1): */ +#define XTBOARD_SYSLED_USER_SHIFT 0 +#define XTBOARD_SYSLED_USER_BITS 2 +#define XTBOARD_SYSLED_USER_MASK 0x00000003 + +/* DIP Switch SW? (left=sw1=lsb=bit0, right=sw4=msb=bit3; off=0, on=1): */ +/* DIP switch bit fields (bit2/sw3 is reserved and presently unused): */ +#if XTBOARD_IS_KC705 +#define XTBOARD_DIPSW_USER_SHIFT 0 +#define XTBOARD_DIPSW_USER_BITS 2 +#define XTBOARD_DIPSW_USER_MASK 0x00000003 +#define XTBOARD_DIPSW_BOOT_SHIFT 3 +#define XTBOARD_DIPSW_BOOT_BITS 1 +#define XTBOARD_DIPSW_BOOT_MASK 0x00000008 +#else /* ML605: */ +#define XTBOARD_DIPSW_USER_SHIFT 0 +#define XTBOARD_DIPSW_USER_BITS 6 +#define XTBOARD_DIPSW_USER_MASK 0x0000003F +#define XTBOARD_DIPSW_BOOT_SHIFT 7 +#define XTBOARD_DIPSW_BOOT_BITS 1 +#define XTBOARD_DIPSW_BOOT_MASK 0x00000080 +#endif /*ML605*/ +#define XTBOARD_DIPSW_BOOT_RAM (0< + diff --git a/tools/sdk/include/esp32/xtensa/xtruntime-core-state.h b/tools/sdk/include/esp32/xtensa/xtruntime-core-state.h new file mode 100755 index 00000000..37d203c2 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/xtruntime-core-state.h @@ -0,0 +1,212 @@ +/* xtruntime-core-state.h - core state save area (used eg. by PSO) */ +/* $Id: //depot/rel/Eaglenest/Xtensa/OS/include/xtensa/xtruntime-core-state.h#1 $ */ + +/* + * Copyright (c) 2012-2013 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _XTOS_CORE_STATE_H_ +#define _XTOS_CORE_STATE_H_ + +/* Import STRUCT_xxx macros for defining structures: */ +#include +#include +#include + +//#define XTOS_PSO_TEST 1 // uncommented for internal PSO testing only + +#define CORE_STATE_SIGNATURE 0xB1C5AFED // pattern that indicates state was saved + + +/* + * Save area for saving entire core state, such as across Power Shut-Off (PSO). + */ + +STRUCT_BEGIN +STRUCT_FIELD (long,4,CS_SA_,signature) // for checking whether state was saved +STRUCT_FIELD (long,4,CS_SA_,restore_label) +STRUCT_FIELD (long,4,CS_SA_,aftersave_label) +STRUCT_AFIELD(long,4,CS_SA_,areg,XCHAL_NUM_AREGS) +#if XCHAL_HAVE_WINDOWED +STRUCT_AFIELD(long,4,CS_SA_,caller_regs,16) // save a max of 16 caller regs +STRUCT_FIELD (long,4,CS_SA_,caller_regs_saved) // flag to show if caller regs saved +#endif +#if XCHAL_HAVE_PSO_CDM +STRUCT_FIELD (long,4,CS_SA_,pwrctl) +#endif +#if XCHAL_HAVE_WINDOWED +STRUCT_FIELD (long,4,CS_SA_,windowbase) +STRUCT_FIELD (long,4,CS_SA_,windowstart) +#endif +STRUCT_FIELD (long,4,CS_SA_,sar) +#if XCHAL_HAVE_EXCEPTIONS +STRUCT_FIELD (long,4,CS_SA_,epc1) +STRUCT_FIELD (long,4,CS_SA_,ps) +STRUCT_FIELD (long,4,CS_SA_,excsave1) +# ifdef XCHAL_DOUBLEEXC_VECTOR_VADDR +STRUCT_FIELD (long,4,CS_SA_,depc) +# endif +#endif +#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 2 +STRUCT_AFIELD(long,4,CS_SA_,epc, XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI - 1) +STRUCT_AFIELD(long,4,CS_SA_,eps, XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI - 1) +STRUCT_AFIELD(long,4,CS_SA_,excsave,XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI - 1) +#endif +#if XCHAL_HAVE_LOOPS +STRUCT_FIELD (long,4,CS_SA_,lcount) +STRUCT_FIELD (long,4,CS_SA_,lbeg) +STRUCT_FIELD (long,4,CS_SA_,lend) +#endif +#if XCHAL_HAVE_ABSOLUTE_LITERALS +STRUCT_FIELD (long,4,CS_SA_,litbase) +#endif +#if XCHAL_HAVE_VECBASE +STRUCT_FIELD (long,4,CS_SA_,vecbase) +#endif +#if XCHAL_HAVE_S32C1I && (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0) /* have ATOMCTL ? */ +STRUCT_FIELD (long,4,CS_SA_,atomctl) +#endif +#if XCHAL_HAVE_PREFETCH +STRUCT_FIELD (long,4,CS_SA_,prefctl) +#endif +#if XCHAL_USE_MEMCTL +STRUCT_FIELD (long,4,CS_SA_,memctl) +#endif +#if XCHAL_HAVE_CCOUNT +STRUCT_FIELD (long,4,CS_SA_,ccount) +STRUCT_AFIELD(long,4,CS_SA_,ccompare, XCHAL_NUM_TIMERS) +#endif +#if XCHAL_HAVE_INTERRUPTS +STRUCT_FIELD (long,4,CS_SA_,intenable) +STRUCT_FIELD (long,4,CS_SA_,interrupt) +#endif +#if XCHAL_HAVE_DEBUG +STRUCT_FIELD (long,4,CS_SA_,icount) +STRUCT_FIELD (long,4,CS_SA_,icountlevel) +STRUCT_FIELD (long,4,CS_SA_,debugcause) +// DDR not saved +# if XCHAL_NUM_DBREAK +STRUCT_AFIELD(long,4,CS_SA_,dbreakc, XCHAL_NUM_DBREAK) +STRUCT_AFIELD(long,4,CS_SA_,dbreaka, XCHAL_NUM_DBREAK) +# endif +# if XCHAL_NUM_IBREAK +STRUCT_AFIELD(long,4,CS_SA_,ibreaka, XCHAL_NUM_IBREAK) +STRUCT_FIELD (long,4,CS_SA_,ibreakenable) +# endif +#endif +#if XCHAL_NUM_MISC_REGS +STRUCT_AFIELD(long,4,CS_SA_,misc,XCHAL_NUM_MISC_REGS) +#endif +#if XCHAL_HAVE_MEM_ECC_PARITY +STRUCT_FIELD (long,4,CS_SA_,mepc) +STRUCT_FIELD (long,4,CS_SA_,meps) +STRUCT_FIELD (long,4,CS_SA_,mesave) +STRUCT_FIELD (long,4,CS_SA_,mesr) +STRUCT_FIELD (long,4,CS_SA_,mecr) +STRUCT_FIELD (long,4,CS_SA_,mevaddr) +#endif + +/* We put this ahead of TLB and other TIE state, + to keep it within S32I/L32I offset range. */ +#if XCHAL_HAVE_CP +STRUCT_FIELD (long,4,CS_SA_,cpenable) +#endif + +/* TLB state */ +#if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR +STRUCT_AFIELD(long,4,CS_SA_,tlbs,8*2) +#endif +#if XCHAL_HAVE_PTP_MMU +/* Compute number of auto-refill (ARF) entries as max of I and D, + to simplify TLB save logic. On the unusual configs with + ITLB ARF != DTLB ARF entries, we'll just end up + saving/restoring some extra entries redundantly. */ +# if XCHAL_DTLB_ARF_ENTRIES_LOG2 + XCHAL_ITLB_ARF_ENTRIES_LOG2 > 4 +# define ARF_ENTRIES 8 +# else +# define ARF_ENTRIES 4 +# endif +STRUCT_FIELD (long,4,CS_SA_,ptevaddr) +STRUCT_FIELD (long,4,CS_SA_,rasid) +STRUCT_FIELD (long,4,CS_SA_,dtlbcfg) +STRUCT_FIELD (long,4,CS_SA_,itlbcfg) +/*** WARNING: past this point, field offsets may be larger than S32I/L32I range ***/ +STRUCT_AFIELD(long,4,CS_SA_,tlbs,((4*ARF_ENTRIES+4)*2+3)*2) +# if XCHAL_HAVE_SPANNING_WAY /* MMU v3 */ +STRUCT_AFIELD(long,4,CS_SA_,tlbs_ways56,(4+8)*2*2) +# endif +#endif + +/* TIE state */ +/* NOTE: NCP area is aligned to XCHAL_TOTAL_SA_ALIGN not XCHAL_NCP_SA_ALIGN, + because the offsets of all subsequent coprocessor save areas are relative + to the NCP save area. */ +STRUCT_AFIELD_A(char,1,XCHAL_TOTAL_SA_ALIGN,CS_SA_,ncp,XCHAL_NCP_SA_SIZE) +#if XCHAL_HAVE_CP +STRUCT_AFIELD_A(char,1,XCHAL_CP0_SA_ALIGN,CS_SA_,cp0,XCHAL_CP0_SA_SIZE) +STRUCT_AFIELD_A(char,1,XCHAL_CP1_SA_ALIGN,CS_SA_,cp1,XCHAL_CP1_SA_SIZE) +STRUCT_AFIELD_A(char,1,XCHAL_CP2_SA_ALIGN,CS_SA_,cp2,XCHAL_CP2_SA_SIZE) +STRUCT_AFIELD_A(char,1,XCHAL_CP3_SA_ALIGN,CS_SA_,cp3,XCHAL_CP3_SA_SIZE) +STRUCT_AFIELD_A(char,1,XCHAL_CP4_SA_ALIGN,CS_SA_,cp4,XCHAL_CP4_SA_SIZE) +STRUCT_AFIELD_A(char,1,XCHAL_CP5_SA_ALIGN,CS_SA_,cp5,XCHAL_CP5_SA_SIZE) +STRUCT_AFIELD_A(char,1,XCHAL_CP6_SA_ALIGN,CS_SA_,cp6,XCHAL_CP6_SA_SIZE) +STRUCT_AFIELD_A(char,1,XCHAL_CP7_SA_ALIGN,CS_SA_,cp7,XCHAL_CP7_SA_SIZE) +//STRUCT_AFIELD_A(char,1,XCHAL_CP8_SA_ALIGN,CS_SA_,cp8,XCHAL_CP8_SA_SIZE) +//STRUCT_AFIELD_A(char,1,XCHAL_CP9_SA_ALIGN,CS_SA_,cp9,XCHAL_CP9_SA_SIZE) +//STRUCT_AFIELD_A(char,1,XCHAL_CP10_SA_ALIGN,CS_SA_,cp10,XCHAL_CP10_SA_SIZE) +//STRUCT_AFIELD_A(char,1,XCHAL_CP11_SA_ALIGN,CS_SA_,cp11,XCHAL_CP11_SA_SIZE) +//STRUCT_AFIELD_A(char,1,XCHAL_CP12_SA_ALIGN,CS_SA_,cp12,XCHAL_CP12_SA_SIZE) +//STRUCT_AFIELD_A(char,1,XCHAL_CP13_SA_ALIGN,CS_SA_,cp13,XCHAL_CP13_SA_SIZE) +//STRUCT_AFIELD_A(char,1,XCHAL_CP14_SA_ALIGN,CS_SA_,cp14,XCHAL_CP14_SA_SIZE) +//STRUCT_AFIELD_A(char,1,XCHAL_CP15_SA_ALIGN,CS_SA_,cp15,XCHAL_CP15_SA_SIZE) +#endif + +STRUCT_END(XtosCoreState) + + + +// These are part of non-coprocessor state (ncp): +#if XCHAL_HAVE_MAC16 +//STRUCT_FIELD (long,4,CS_SA_,acclo) +//STRUCT_FIELD (long,4,CS_SA_,acchi) +//STRUCT_AFIELD(long,4,CS_SA_,mr, 4) +#endif +#if XCHAL_HAVE_THREADPTR +//STRUCT_FIELD (long,4,CS_SA_,threadptr) +#endif +#if XCHAL_HAVE_S32C1I +//STRUCT_FIELD (long,4,CS_SA_,scompare1) +#endif +#if XCHAL_HAVE_BOOLEANS +//STRUCT_FIELD (long,4,CS_SA_,br) +#endif + +// Not saved: +// EXCCAUSE ?? +// DEBUGCAUSE ?? +// EXCVADDR ?? +// DDR +// INTERRUPT +// ... locked cache lines ... + +#endif /* _XTOS_CORE_STATE_H_ */ + diff --git a/tools/sdk/include/esp32/xtensa/xtruntime-frames.h b/tools/sdk/include/esp32/xtensa/xtruntime-frames.h new file mode 100755 index 00000000..8b5a7463 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/xtruntime-frames.h @@ -0,0 +1,162 @@ +/* xtruntime-frames.h - exception stack frames for single-threaded run-time */ +/* $Id: //depot/rel/Eaglenest/Xtensa/OS/include/xtensa/xtruntime-frames.h#1 $ */ + +/* + * Copyright (c) 2002-2012 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _XTRUNTIME_FRAMES_H_ +#define _XTRUNTIME_FRAMES_H_ + +#include + +/* Macros that help define structures for both C and assembler: */ +#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__) +#define STRUCT_BEGIN .pushsection .text; .struct 0 +#define STRUCT_FIELD(ctype,size,pre,name) pre##name: .space size +#define STRUCT_AFIELD(ctype,size,pre,name,n) pre##name: .if n ; .space (size)*(n) ; .endif +#define STRUCT_AFIELD_A(ctype,size,align,pre,name,n) .balign align ; pre##name: .if n ; .space (size)*(n) ; .endif +#define STRUCT_END(sname) sname##Size:; .popsection +#else /*_ASMLANGUAGE||__ASSEMBLER__*/ +#define STRUCT_BEGIN typedef struct { +#define STRUCT_FIELD(ctype,size,pre,name) ctype name; +#define STRUCT_AFIELD(ctype,size,pre,name,n) ctype name[n]; +#define STRUCT_AFIELD_A(ctype,size,align,pre,name,n) ctype name[n] __attribute__((aligned(align))); +#define STRUCT_END(sname) } sname; +#endif /*_ASMLANGUAGE||__ASSEMBLER__*/ + + +/* + * Kernel vector mode exception stack frame. + * + * NOTE: due to the limited range of addi used in the current + * kernel exception vector, and the fact that historically + * the vector is limited to 12 bytes, the size of this + * stack frame is limited to 128 bytes (currently at 64). + */ +STRUCT_BEGIN +STRUCT_FIELD (long,4,KEXC_,pc) /* "parm" */ +STRUCT_FIELD (long,4,KEXC_,ps) +STRUCT_AFIELD(long,4,KEXC_,areg, 4) /* a12 .. a15 */ +STRUCT_FIELD (long,4,KEXC_,sar) /* "save" */ +#if XCHAL_HAVE_LOOPS +STRUCT_FIELD (long,4,KEXC_,lcount) +STRUCT_FIELD (long,4,KEXC_,lbeg) +STRUCT_FIELD (long,4,KEXC_,lend) +#endif +#if XCHAL_HAVE_MAC16 +STRUCT_FIELD (long,4,KEXC_,acclo) +STRUCT_FIELD (long,4,KEXC_,acchi) +STRUCT_AFIELD(long,4,KEXC_,mr, 4) +#endif +STRUCT_END(KernelFrame) + + +/* + * User vector mode exception stack frame: + * + * WARNING: if you modify this structure, you MUST modify the + * computation of the pad size (ALIGNPAD) accordingly. + */ +STRUCT_BEGIN +STRUCT_FIELD (long,4,UEXC_,pc) +STRUCT_FIELD (long,4,UEXC_,ps) +STRUCT_FIELD (long,4,UEXC_,sar) +STRUCT_FIELD (long,4,UEXC_,vpri) +#ifdef __XTENSA_CALL0_ABI__ +STRUCT_FIELD (long,4,UEXC_,a0) +#endif +STRUCT_FIELD (long,4,UEXC_,a2) +STRUCT_FIELD (long,4,UEXC_,a3) +STRUCT_FIELD (long,4,UEXC_,a4) +STRUCT_FIELD (long,4,UEXC_,a5) +#ifdef __XTENSA_CALL0_ABI__ +STRUCT_FIELD (long,4,UEXC_,a6) +STRUCT_FIELD (long,4,UEXC_,a7) +STRUCT_FIELD (long,4,UEXC_,a8) +STRUCT_FIELD (long,4,UEXC_,a9) +STRUCT_FIELD (long,4,UEXC_,a10) +STRUCT_FIELD (long,4,UEXC_,a11) +STRUCT_FIELD (long,4,UEXC_,a12) +STRUCT_FIELD (long,4,UEXC_,a13) +STRUCT_FIELD (long,4,UEXC_,a14) +STRUCT_FIELD (long,4,UEXC_,a15) +#endif +STRUCT_FIELD (long,4,UEXC_,exccause) /* NOTE: can probably rid of this one (pass direct) */ +#if XCHAL_HAVE_LOOPS +STRUCT_FIELD (long,4,UEXC_,lcount) +STRUCT_FIELD (long,4,UEXC_,lbeg) +STRUCT_FIELD (long,4,UEXC_,lend) +#endif +#if XCHAL_HAVE_MAC16 +STRUCT_FIELD (long,4,UEXC_,acclo) +STRUCT_FIELD (long,4,UEXC_,acchi) +STRUCT_AFIELD(long,4,UEXC_,mr, 4) +#endif +/* ALIGNPAD is the 16-byte alignment padding. */ +#ifdef __XTENSA_CALL0_ABI__ +# define CALL0_ABI 1 +#else +# define CALL0_ABI 0 +#endif +#define ALIGNPAD ((3 + XCHAL_HAVE_LOOPS*1 + XCHAL_HAVE_MAC16*2 + CALL0_ABI*1) & 3) +#if ALIGNPAD +STRUCT_AFIELD(long,4,UEXC_,pad, ALIGNPAD) /* 16-byte alignment padding */ +#endif +/*STRUCT_AFIELD_A(char,1,XCHAL_CPEXTRA_SA_ALIGN,UEXC_,ureg, (XCHAL_CPEXTRA_SA_SIZE+3)&-4)*/ /* not used */ +STRUCT_END(UserFrame) + + +#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__) + + +/* Check for UserFrameSize small enough not to require rounding...: */ + /* Skip 16-byte save area, then 32-byte space for 8 regs of call12 + * (which overlaps with 16-byte GCC nested func chaining area), + * then exception stack frame: */ + .set UserFrameTotalSize, 16+32+UserFrameSize + /* Greater than 112 bytes? (max range of ADDI, both signs, when aligned to 16 bytes): */ + .ifgt UserFrameTotalSize-112 + /* Round up to 256-byte multiple to accelerate immediate adds: */ + .set UserFrameTotalSize, ((UserFrameTotalSize+255) & 0xFFFFFF00) + .endif +# define ESF_TOTALSIZE UserFrameTotalSize + +#endif /* _ASMLANGUAGE || __ASSEMBLER__ */ + + +#if XCHAL_NUM_CONTEXTS > 1 +/* Structure of info stored on new context's stack for setup: */ +STRUCT_BEGIN +STRUCT_FIELD (long,4,INFO_,sp) +STRUCT_FIELD (long,4,INFO_,arg1) +STRUCT_FIELD (long,4,INFO_,funcpc) +STRUCT_FIELD (long,4,INFO_,prevps) +STRUCT_END(SetupInfo) +#endif + + +#define KERNELSTACKSIZE 1024 + + +#endif /* _XTRUNTIME_FRAMES_H_ */ + diff --git a/tools/sdk/include/esp32/xtensa/xtruntime.h b/tools/sdk/include/esp32/xtensa/xtruntime.h new file mode 100755 index 00000000..9dae1f4b --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/xtruntime.h @@ -0,0 +1,221 @@ +/* + * xtruntime.h -- general C definitions for single-threaded run-time + * + * Copyright (c) 2002-2013 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef XTRUNTIME_H +#define XTRUNTIME_H + +#include +#include +#include + +#ifndef XTSTR +#define _XTSTR(x) # x +#define XTSTR(x) _XTSTR(x) +#endif + +/* _xtos_core_shutoff() flags parameter values: */ +#define XTOS_KEEPON_MEM 0x00000100 /* ==PWRCTL_MEM_WAKEUP */ +#define XTOS_KEEPON_MEM_SHIFT 8 +#define XTOS_KEEPON_DEBUG 0x00001000 /* ==PWRCTL_DEBUG_WAKEUP */ +#define XTOS_KEEPON_DEBUG_SHIFT 12 + +#define XTOS_COREF_PSO 0x00000001 /* do power shutoff */ +#define XTOS_COREF_PSO_SHIFT 0 + +#define _xtos_set_execption_handler _xtos_set_exception_handler /* backward compatibility */ +#define _xtos_set_saved_intenable _xtos_ints_on /* backward compatibility */ +#define _xtos_clear_saved_intenable _xtos_ints_off /* backward compatibility */ + +#if !defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__) + +#ifdef __cplusplus +extern "C" { +#endif + +/*typedef void (_xtos_timerdelta_func)(int);*/ +#ifdef __cplusplus +typedef void (_xtos_handler_func)(...); +#else +typedef void (_xtos_handler_func)(); +#endif +typedef _xtos_handler_func *_xtos_handler; + +/* + * unsigned XTOS_SET_INTLEVEL(int intlevel); + * This macro sets the current interrupt level. + * The 'intlevel' parameter must be a constant. + * This macro returns a 32-bit value that must be passed to + * XTOS_RESTORE_INTLEVEL() to restore the previous interrupt level. + * XTOS_RESTORE_JUST_INTLEVEL() also does this, but in XEA2 configs + * it restores only PS.INTLEVEL rather than the entire PS register + * and thus is slower. + */ +#if !XCHAL_HAVE_INTERRUPTS +# define XTOS_SET_INTLEVEL(intlevel) 0 +# define XTOS_SET_MIN_INTLEVEL(intlevel) 0 +# define XTOS_RESTORE_INTLEVEL(restoreval) +# define XTOS_RESTORE_JUST_INTLEVEL(restoreval) +#elif XCHAL_HAVE_XEA2 +/* In XEA2, we can simply safely set PS.INTLEVEL directly: */ +/* NOTE: these asm macros don't modify memory, but they are marked + * as such to act as memory access barriers to the compiler because + * these macros are sometimes used to delineate critical sections; + * function calls are natural barriers (the compiler does not know + * whether a function modifies memory) unless declared to be inlined. */ +# define XTOS_SET_INTLEVEL(intlevel) ({ unsigned __tmp; \ + __asm__ __volatile__( "rsil %0, " XTSTR(intlevel) "\n" \ + : "=a" (__tmp) : : "memory" ); \ + __tmp;}) +# define XTOS_SET_MIN_INTLEVEL(intlevel) ({ unsigned __tmp, __tmp2, __tmp3; \ + __asm__ __volatile__( "rsr %0, " XTSTR(PS) "\n" /* get old (current) PS.INTLEVEL */ \ + "movi %2, " XTSTR(intlevel) "\n" \ + "extui %1, %0, 0, 4\n" /* keep only INTLEVEL bits of parameter */ \ + "blt %2, %1, 1f\n" \ + "rsil %0, " XTSTR(intlevel) "\n" \ + "1:\n" \ + : "=a" (__tmp), "=&a" (__tmp2), "=&a" (__tmp3) : : "memory" ); \ + __tmp;}) +# define XTOS_RESTORE_INTLEVEL(restoreval) do{ unsigned __tmp = (restoreval); \ + __asm__ __volatile__( "wsr %0, " XTSTR(PS) " ; rsync\n" \ + : : "a" (__tmp) : "memory" ); \ + }while(0) +# define XTOS_RESTORE_JUST_INTLEVEL(restoreval) _xtos_set_intlevel(restoreval) +#else +/* In XEA1, we have to rely on INTENABLE register virtualization: */ +extern unsigned _xtos_set_vpri( unsigned vpri ); +extern unsigned _xtos_vpri_enabled; /* current virtual priority */ +# define XTOS_SET_INTLEVEL(intlevel) _xtos_set_vpri(~XCHAL_INTLEVEL_ANDBELOW_MASK(intlevel)) +# define XTOS_SET_MIN_INTLEVEL(intlevel) _xtos_set_vpri(_xtos_vpri_enabled & ~XCHAL_INTLEVEL_ANDBELOW_MASK(intlevel)) +# define XTOS_RESTORE_INTLEVEL(restoreval) _xtos_set_vpri(restoreval) +# define XTOS_RESTORE_JUST_INTLEVEL(restoreval) _xtos_set_vpri(restoreval) +#endif + +/* + * The following macros build upon the above. They are generally used + * instead of invoking the SET_INTLEVEL and SET_MIN_INTLEVEL macros directly. + * They all return a value that can be used with XTOS_RESTORE_INTLEVEL() + * or _xtos_restore_intlevel() or _xtos_restore_just_intlevel() to restore + * the effective interrupt level to what it was before the macro was invoked. + * In XEA2, the DISABLE macros are much faster than the MASK macros + * (in all configs, DISABLE sets the effective interrupt level, whereas MASK + * makes ensures the effective interrupt level is at least the level given + * without lowering it; in XEA2 with INTENABLE virtualization, these macros + * affect PS.INTLEVEL only, not the virtual priority, so DISABLE has partial + * MASK semantics). + * + * A typical critical section sequence might be: + * unsigned rval = XTOS_DISABLE_EXCM_INTERRUPTS; + * ... critical section ... + * XTOS_RESTORE_INTLEVEL(rval); + */ +/* Enable all interrupts (those activated with _xtos_ints_on()): */ +#define XTOS_ENABLE_INTERRUPTS XTOS_SET_INTLEVEL(0) +/* Disable low priority level interrupts (they can interact with the OS): */ +#define XTOS_DISABLE_LOWPRI_INTERRUPTS XTOS_SET_INTLEVEL(XCHAL_NUM_LOWPRI_LEVELS) +#define XTOS_MASK_LOWPRI_INTERRUPTS XTOS_SET_MIN_INTLEVEL(XCHAL_NUM_LOWPRI_LEVELS) +/* Disable interrupts that can interact with the OS: */ +#define XTOS_DISABLE_EXCM_INTERRUPTS XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL) +#define XTOS_MASK_EXCM_INTERRUPTS XTOS_SET_MIN_INTLEVEL(XCHAL_EXCM_LEVEL) +#if 0 /* XTOS_LOCK_LEVEL is not exported to applications */ +/* Disable interrupts that can interact with the OS, or manipulate virtual INTENABLE: */ +#define XTOS_DISABLE_LOCK_INTERRUPTS XTOS_SET_INTLEVEL(XTOS_LOCK_LEVEL) +#define XTOS_MASK_LOCK_INTERRUPTS XTOS_SET_MIN_INTLEVEL(XTOS_LOCK_LEVEL) +#endif +/* Disable ALL interrupts (not for common use, particularly if one's processor + * configuration has high-level interrupts and one cares about their latency): */ +#define XTOS_DISABLE_ALL_INTERRUPTS XTOS_SET_INTLEVEL(15) + + +extern unsigned int _xtos_ints_off( unsigned int mask ); +extern unsigned int _xtos_ints_on( unsigned int mask ); +extern unsigned _xtos_set_intlevel( int intlevel ); +extern unsigned _xtos_set_min_intlevel( int intlevel ); +extern unsigned _xtos_restore_intlevel( unsigned restoreval ); +extern unsigned _xtos_restore_just_intlevel( unsigned restoreval ); +extern _xtos_handler _xtos_set_interrupt_handler( int n, _xtos_handler f ); +extern _xtos_handler _xtos_set_interrupt_handler_arg( int n, _xtos_handler f, void *arg ); +extern _xtos_handler _xtos_set_exception_handler( int n, _xtos_handler f ); + +extern void _xtos_memep_initrams( void ); +extern void _xtos_memep_enable( int flags ); + +/* For use with the tiny LSP (see LSP reference manual). */ +#if XCHAL_NUM_INTLEVELS >= 1 +extern void _xtos_dispatch_level1_interrupts( void ); +#endif +#if XCHAL_NUM_INTLEVELS >= 2 +extern void _xtos_dispatch_level2_interrupts( void ); +#endif +#if XCHAL_NUM_INTLEVELS >= 3 +extern void _xtos_dispatch_level3_interrupts( void ); +#endif +#if XCHAL_NUM_INTLEVELS >= 4 +extern void _xtos_dispatch_level4_interrupts( void ); +#endif +#if XCHAL_NUM_INTLEVELS >= 5 +extern void _xtos_dispatch_level5_interrupts( void ); +#endif +#if XCHAL_NUM_INTLEVELS >= 6 +extern void _xtos_dispatch_level6_interrupts( void ); +#endif + +/* Deprecated (but kept because they were documented): */ +extern unsigned int _xtos_read_ints( void ); /* use xthal_get_interrupt() instead */ +extern void _xtos_clear_ints( unsigned int mask ); /* use xthal_set_intclear() instead */ + + +/* Power shut-off related routines. */ +extern int _xtos_core_shutoff(unsigned flags); +extern int _xtos_core_save(unsigned flags, XtosCoreState *savearea, void *code); +extern void _xtos_core_restore(unsigned retvalue, XtosCoreState *savearea); + + +#if XCHAL_NUM_CONTEXTS > 1 +extern unsigned _xtos_init_context(int context_num, int stack_size, + _xtos_handler_func *start_func, int arg1); +#endif + +/* Deprecated: */ +#if XCHAL_NUM_TIMERS > 0 +extern void _xtos_timer_0_delta( int cycles ); +#endif +#if XCHAL_NUM_TIMERS > 1 +extern void _xtos_timer_1_delta( int cycles ); +#endif +#if XCHAL_NUM_TIMERS > 2 +extern void _xtos_timer_2_delta( int cycles ); +#endif +#if XCHAL_NUM_TIMERS > 3 +extern void _xtos_timer_3_delta( int cycles ); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* !_ASMLANGUAGE && !__ASSEMBLER__ */ + +#endif /* XTRUNTIME_H */ + diff --git a/tools/sdk/include/esp32/xtensa/xtutil.h b/tools/sdk/include/esp32/xtensa/xtutil.h new file mode 100755 index 00000000..fb05c370 --- /dev/null +++ b/tools/sdk/include/esp32/xtensa/xtutil.h @@ -0,0 +1,61 @@ + +/* $Id$ */ +/*******************************************************************************/ +/* Copyright (c) 2001-2013 by Tensilica Inc. ALL RIGHTS RESERVED. */ +/* These coded instructions, statements, and computer programs are the */ +/* copyrighted works and confidential proprietary information of Tensilica Inc.*/ +/* They may not be modified, copied, reproduced, distributed, or disclosed to */ +/* third parties in any manner, medium, or form, in whole or in part, without */ +/* the prior written consent of Tensilica Inc. */ +/*******************************************************************************/ + +#ifndef XTUTIL_H +#define XTUTIL_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern int xt_putchar(int c); +extern int xt_puts(const char * s); +extern void xt_putn(unsigned n); +extern int xt_atoi(const char * s); +extern int xt_printf(const char *fmt, ...); +extern int xt_sprintf(char * buf, const char * fmt, ...); + +typedef int xt_output_fn(int *, int, const void *, int); +extern xt_output_fn * xt_set_output_fn(xt_output_fn * fn); + +#ifdef XTUTIL_LIB + +// Only defined if building library + +typedef void (xt_outbuf_fn)(void *, char *, int); + +extern int xt_vprintf(xt_outbuf_fn * out, void * outarg, const char * fmt, va_list ap); + +#else + +// Only defined if building application and overriding + +#ifndef XTUTIL_NO_OVERRIDE + +#define putchar xt_putchar +#define puts xt_puts +#define putn xt_putn +#define atoi xt_atoi +#define printf xt_printf +#define sprintf xt_sprintf + +#endif // XTUTIL_NO_OVERRIDE + +#endif // XTUTIL_LIB + +#ifdef __cplusplus +} +#endif + +#endif // XTUTIL_H + diff --git a/tools/sdk/include/expat/ascii.h b/tools/sdk/include/expat/ascii.h new file mode 100644 index 00000000..d10530b0 --- /dev/null +++ b/tools/sdk/include/expat/ascii.h @@ -0,0 +1,92 @@ +/* Copyright (c) 1998, 1999 Thai Open Source Software Center Ltd + See the file COPYING for copying permission. +*/ + +#define ASCII_A 0x41 +#define ASCII_B 0x42 +#define ASCII_C 0x43 +#define ASCII_D 0x44 +#define ASCII_E 0x45 +#define ASCII_F 0x46 +#define ASCII_G 0x47 +#define ASCII_H 0x48 +#define ASCII_I 0x49 +#define ASCII_J 0x4A +#define ASCII_K 0x4B +#define ASCII_L 0x4C +#define ASCII_M 0x4D +#define ASCII_N 0x4E +#define ASCII_O 0x4F +#define ASCII_P 0x50 +#define ASCII_Q 0x51 +#define ASCII_R 0x52 +#define ASCII_S 0x53 +#define ASCII_T 0x54 +#define ASCII_U 0x55 +#define ASCII_V 0x56 +#define ASCII_W 0x57 +#define ASCII_X 0x58 +#define ASCII_Y 0x59 +#define ASCII_Z 0x5A + +#define ASCII_a 0x61 +#define ASCII_b 0x62 +#define ASCII_c 0x63 +#define ASCII_d 0x64 +#define ASCII_e 0x65 +#define ASCII_f 0x66 +#define ASCII_g 0x67 +#define ASCII_h 0x68 +#define ASCII_i 0x69 +#define ASCII_j 0x6A +#define ASCII_k 0x6B +#define ASCII_l 0x6C +#define ASCII_m 0x6D +#define ASCII_n 0x6E +#define ASCII_o 0x6F +#define ASCII_p 0x70 +#define ASCII_q 0x71 +#define ASCII_r 0x72 +#define ASCII_s 0x73 +#define ASCII_t 0x74 +#define ASCII_u 0x75 +#define ASCII_v 0x76 +#define ASCII_w 0x77 +#define ASCII_x 0x78 +#define ASCII_y 0x79 +#define ASCII_z 0x7A + +#define ASCII_0 0x30 +#define ASCII_1 0x31 +#define ASCII_2 0x32 +#define ASCII_3 0x33 +#define ASCII_4 0x34 +#define ASCII_5 0x35 +#define ASCII_6 0x36 +#define ASCII_7 0x37 +#define ASCII_8 0x38 +#define ASCII_9 0x39 + +#define ASCII_TAB 0x09 +#define ASCII_SPACE 0x20 +#define ASCII_EXCL 0x21 +#define ASCII_QUOT 0x22 +#define ASCII_AMP 0x26 +#define ASCII_APOS 0x27 +#define ASCII_MINUS 0x2D +#define ASCII_PERIOD 0x2E +#define ASCII_COLON 0x3A +#define ASCII_SEMI 0x3B +#define ASCII_LT 0x3C +#define ASCII_EQUALS 0x3D +#define ASCII_GT 0x3E +#define ASCII_LSQB 0x5B +#define ASCII_RSQB 0x5D +#define ASCII_UNDERSCORE 0x5F +#define ASCII_LPAREN 0x28 +#define ASCII_RPAREN 0x29 +#define ASCII_FF 0x0C +#define ASCII_SLASH 0x2F +#define ASCII_HASH 0x23 +#define ASCII_PIPE 0x7C +#define ASCII_COMMA 0x2C diff --git a/tools/sdk/include/expat/asciitab.h b/tools/sdk/include/expat/asciitab.h new file mode 100644 index 00000000..79a15c28 --- /dev/null +++ b/tools/sdk/include/expat/asciitab.h @@ -0,0 +1,36 @@ +/* Copyright (c) 1998, 1999 Thai Open Source Software Center Ltd + See the file COPYING for copying permission. +*/ + +/* 0x00 */ BT_NONXML, BT_NONXML, BT_NONXML, BT_NONXML, +/* 0x04 */ BT_NONXML, BT_NONXML, BT_NONXML, BT_NONXML, +/* 0x08 */ BT_NONXML, BT_S, BT_LF, BT_NONXML, +/* 0x0C */ BT_NONXML, BT_CR, BT_NONXML, BT_NONXML, +/* 0x10 */ BT_NONXML, BT_NONXML, BT_NONXML, BT_NONXML, +/* 0x14 */ BT_NONXML, BT_NONXML, BT_NONXML, BT_NONXML, +/* 0x18 */ BT_NONXML, BT_NONXML, BT_NONXML, BT_NONXML, +/* 0x1C */ BT_NONXML, BT_NONXML, BT_NONXML, BT_NONXML, +/* 0x20 */ BT_S, BT_EXCL, BT_QUOT, BT_NUM, +/* 0x24 */ BT_OTHER, BT_PERCNT, BT_AMP, BT_APOS, +/* 0x28 */ BT_LPAR, BT_RPAR, BT_AST, BT_PLUS, +/* 0x2C */ BT_COMMA, BT_MINUS, BT_NAME, BT_SOL, +/* 0x30 */ BT_DIGIT, BT_DIGIT, BT_DIGIT, BT_DIGIT, +/* 0x34 */ BT_DIGIT, BT_DIGIT, BT_DIGIT, BT_DIGIT, +/* 0x38 */ BT_DIGIT, BT_DIGIT, BT_COLON, BT_SEMI, +/* 0x3C */ BT_LT, BT_EQUALS, BT_GT, BT_QUEST, +/* 0x40 */ BT_OTHER, BT_HEX, BT_HEX, BT_HEX, +/* 0x44 */ BT_HEX, BT_HEX, BT_HEX, BT_NMSTRT, +/* 0x48 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, +/* 0x4C */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, +/* 0x50 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, +/* 0x54 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, +/* 0x58 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_LSQB, +/* 0x5C */ BT_OTHER, BT_RSQB, BT_OTHER, BT_NMSTRT, +/* 0x60 */ BT_OTHER, BT_HEX, BT_HEX, BT_HEX, +/* 0x64 */ BT_HEX, BT_HEX, BT_HEX, BT_NMSTRT, +/* 0x68 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, +/* 0x6C */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, +/* 0x70 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, +/* 0x74 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, +/* 0x78 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_OTHER, +/* 0x7C */ BT_VERBAR, BT_OTHER, BT_OTHER, BT_OTHER, diff --git a/tools/sdk/include/expat/chardata.h b/tools/sdk/include/expat/chardata.h new file mode 100644 index 00000000..e8dc4ce2 --- /dev/null +++ b/tools/sdk/include/expat/chardata.h @@ -0,0 +1,40 @@ +/* chardata.h + + Interface to some helper routines used to accumulate and check text + and attribute content. +*/ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef XML_CHARDATA_H +#define XML_CHARDATA_H 1 + +#ifndef XML_VERSION +#include "expat.h" /* need XML_Char */ +#endif + + +typedef struct { + int count; /* # of chars, < 0 if not set */ + XML_Char data[1024]; +} CharData; + + +void CharData_Init(CharData *storage); + +void CharData_AppendString(CharData *storage, const char *s); + +void CharData_AppendXMLChars(CharData *storage, const XML_Char *s, int len); + +int CharData_CheckString(CharData *storage, const char *s); + +int CharData_CheckXMLChars(CharData *storage, const XML_Char *s); + + +#endif /* XML_CHARDATA_H */ + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/include/expat/expat.h b/tools/sdk/include/expat/expat.h new file mode 100644 index 00000000..086e24b3 --- /dev/null +++ b/tools/sdk/include/expat/expat.h @@ -0,0 +1,1048 @@ +/* Copyright (c) 1998, 1999, 2000 Thai Open Source Software Center Ltd + See the file COPYING for copying permission. +*/ + +#ifndef Expat_INCLUDED +#define Expat_INCLUDED 1 + +#ifdef __VMS +/* 0 1 2 3 0 1 2 3 + 1234567890123456789012345678901 1234567890123456789012345678901 */ +#define XML_SetProcessingInstructionHandler XML_SetProcessingInstrHandler +#define XML_SetUnparsedEntityDeclHandler XML_SetUnparsedEntDeclHandler +#define XML_SetStartNamespaceDeclHandler XML_SetStartNamespcDeclHandler +#define XML_SetExternalEntityRefHandlerArg XML_SetExternalEntRefHandlerArg +#endif + +#include +#include "expat_external.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct XML_ParserStruct; +typedef struct XML_ParserStruct *XML_Parser; + +/* Should this be defined using stdbool.h when C99 is available? */ +typedef unsigned char XML_Bool; +#define XML_TRUE ((XML_Bool) 1) +#define XML_FALSE ((XML_Bool) 0) + +/* The XML_Status enum gives the possible return values for several + API functions. The preprocessor #defines are included so this + stanza can be added to code that still needs to support older + versions of Expat 1.95.x: + + #ifndef XML_STATUS_OK + #define XML_STATUS_OK 1 + #define XML_STATUS_ERROR 0 + #endif + + Otherwise, the #define hackery is quite ugly and would have been + dropped. +*/ +enum XML_Status { + XML_STATUS_ERROR = 0, +#define XML_STATUS_ERROR XML_STATUS_ERROR + XML_STATUS_OK = 1, +#define XML_STATUS_OK XML_STATUS_OK + XML_STATUS_SUSPENDED = 2 +#define XML_STATUS_SUSPENDED XML_STATUS_SUSPENDED +}; + +enum XML_Error { + XML_ERROR_NONE, + XML_ERROR_NO_MEMORY, + XML_ERROR_SYNTAX, + XML_ERROR_NO_ELEMENTS, + XML_ERROR_INVALID_TOKEN, + XML_ERROR_UNCLOSED_TOKEN, + XML_ERROR_PARTIAL_CHAR, + XML_ERROR_TAG_MISMATCH, + XML_ERROR_DUPLICATE_ATTRIBUTE, + XML_ERROR_JUNK_AFTER_DOC_ELEMENT, + XML_ERROR_PARAM_ENTITY_REF, + XML_ERROR_UNDEFINED_ENTITY, + XML_ERROR_RECURSIVE_ENTITY_REF, + XML_ERROR_ASYNC_ENTITY, + XML_ERROR_BAD_CHAR_REF, + XML_ERROR_BINARY_ENTITY_REF, + XML_ERROR_ATTRIBUTE_EXTERNAL_ENTITY_REF, + XML_ERROR_MISPLACED_XML_PI, + XML_ERROR_UNKNOWN_ENCODING, + XML_ERROR_INCORRECT_ENCODING, + XML_ERROR_UNCLOSED_CDATA_SECTION, + XML_ERROR_EXTERNAL_ENTITY_HANDLING, + XML_ERROR_NOT_STANDALONE, + XML_ERROR_UNEXPECTED_STATE, + XML_ERROR_ENTITY_DECLARED_IN_PE, + XML_ERROR_FEATURE_REQUIRES_XML_DTD, + XML_ERROR_CANT_CHANGE_FEATURE_ONCE_PARSING, + /* Added in 1.95.7. */ + XML_ERROR_UNBOUND_PREFIX, + /* Added in 1.95.8. */ + XML_ERROR_UNDECLARING_PREFIX, + XML_ERROR_INCOMPLETE_PE, + XML_ERROR_XML_DECL, + XML_ERROR_TEXT_DECL, + XML_ERROR_PUBLICID, + XML_ERROR_SUSPENDED, + XML_ERROR_NOT_SUSPENDED, + XML_ERROR_ABORTED, + XML_ERROR_FINISHED, + XML_ERROR_SUSPEND_PE, + /* Added in 2.0. */ + XML_ERROR_RESERVED_PREFIX_XML, + XML_ERROR_RESERVED_PREFIX_XMLNS, + XML_ERROR_RESERVED_NAMESPACE_URI +}; + +enum XML_Content_Type { + XML_CTYPE_EMPTY = 1, + XML_CTYPE_ANY, + XML_CTYPE_MIXED, + XML_CTYPE_NAME, + XML_CTYPE_CHOICE, + XML_CTYPE_SEQ +}; + +enum XML_Content_Quant { + XML_CQUANT_NONE, + XML_CQUANT_OPT, + XML_CQUANT_REP, + XML_CQUANT_PLUS +}; + +/* If type == XML_CTYPE_EMPTY or XML_CTYPE_ANY, then quant will be + XML_CQUANT_NONE, and the other fields will be zero or NULL. + If type == XML_CTYPE_MIXED, then quant will be NONE or REP and + numchildren will contain number of elements that may be mixed in + and children point to an array of XML_Content cells that will be + all of XML_CTYPE_NAME type with no quantification. + + If type == XML_CTYPE_NAME, then the name points to the name, and + the numchildren field will be zero and children will be NULL. The + quant fields indicates any quantifiers placed on the name. + + CHOICE and SEQ will have name NULL, the number of children in + numchildren and children will point, recursively, to an array + of XML_Content cells. + + The EMPTY, ANY, and MIXED types will only occur at top level. +*/ + +typedef struct XML_cp XML_Content; + +struct XML_cp { + enum XML_Content_Type type; + enum XML_Content_Quant quant; + XML_Char * name; + unsigned int numchildren; + XML_Content * children; +}; + + +/* This is called for an element declaration. See above for + description of the model argument. It's the caller's responsibility + to free model when finished with it. +*/ +typedef void (XMLCALL *XML_ElementDeclHandler) (void *userData, + const XML_Char *name, + XML_Content *model); + +XMLPARSEAPI(void) +XML_SetElementDeclHandler(XML_Parser parser, + XML_ElementDeclHandler eldecl); + +/* The Attlist declaration handler is called for *each* attribute. So + a single Attlist declaration with multiple attributes declared will + generate multiple calls to this handler. The "default" parameter + may be NULL in the case of the "#IMPLIED" or "#REQUIRED" + keyword. The "isrequired" parameter will be true and the default + value will be NULL in the case of "#REQUIRED". If "isrequired" is + true and default is non-NULL, then this is a "#FIXED" default. +*/ +typedef void (XMLCALL *XML_AttlistDeclHandler) ( + void *userData, + const XML_Char *elname, + const XML_Char *attname, + const XML_Char *att_type, + const XML_Char *dflt, + int isrequired); + +XMLPARSEAPI(void) +XML_SetAttlistDeclHandler(XML_Parser parser, + XML_AttlistDeclHandler attdecl); + +/* The XML declaration handler is called for *both* XML declarations + and text declarations. The way to distinguish is that the version + parameter will be NULL for text declarations. The encoding + parameter may be NULL for XML declarations. The standalone + parameter will be -1, 0, or 1 indicating respectively that there + was no standalone parameter in the declaration, that it was given + as no, or that it was given as yes. +*/ +typedef void (XMLCALL *XML_XmlDeclHandler) (void *userData, + const XML_Char *version, + const XML_Char *encoding, + int standalone); + +XMLPARSEAPI(void) +XML_SetXmlDeclHandler(XML_Parser parser, + XML_XmlDeclHandler xmldecl); + + +typedef struct { + void *(*malloc_fcn)(size_t size); + void *(*realloc_fcn)(void *ptr, size_t size); + void (*free_fcn)(void *ptr); +} XML_Memory_Handling_Suite; + +/* Constructs a new parser; encoding is the encoding specified by the + external protocol or NULL if there is none specified. +*/ +XMLPARSEAPI(XML_Parser) +XML_ParserCreate(const XML_Char *encoding); + +/* Constructs a new parser and namespace processor. Element type + names and attribute names that belong to a namespace will be + expanded; unprefixed attribute names are never expanded; unprefixed + element type names are expanded only if there is a default + namespace. The expanded name is the concatenation of the namespace + URI, the namespace separator character, and the local part of the + name. If the namespace separator is '\0' then the namespace URI + and the local part will be concatenated without any separator. + It is a programming error to use the separator '\0' with namespace + triplets (see XML_SetReturnNSTriplet). +*/ +XMLPARSEAPI(XML_Parser) +XML_ParserCreateNS(const XML_Char *encoding, XML_Char namespaceSeparator); + + +/* Constructs a new parser using the memory management suite referred to + by memsuite. If memsuite is NULL, then use the standard library memory + suite. If namespaceSeparator is non-NULL it creates a parser with + namespace processing as described above. The character pointed at + will serve as the namespace separator. + + All further memory operations used for the created parser will come from + the given suite. +*/ +XMLPARSEAPI(XML_Parser) +XML_ParserCreate_MM(const XML_Char *encoding, + const XML_Memory_Handling_Suite *memsuite, + const XML_Char *namespaceSeparator); + +/* Prepare a parser object to be re-used. This is particularly + valuable when memory allocation overhead is disproportionatly high, + such as when a large number of small documnents need to be parsed. + All handlers are cleared from the parser, except for the + unknownEncodingHandler. The parser's external state is re-initialized + except for the values of ns and ns_triplets. + + Added in Expat 1.95.3. +*/ +XMLPARSEAPI(XML_Bool) +XML_ParserReset(XML_Parser parser, const XML_Char *encoding); + +/* atts is array of name/value pairs, terminated by 0; + names and values are 0 terminated. +*/ +typedef void (XMLCALL *XML_StartElementHandler) (void *userData, + const XML_Char *name, + const XML_Char **atts); + +typedef void (XMLCALL *XML_EndElementHandler) (void *userData, + const XML_Char *name); + + +/* s is not 0 terminated. */ +typedef void (XMLCALL *XML_CharacterDataHandler) (void *userData, + const XML_Char *s, + int len); + +/* target and data are 0 terminated */ +typedef void (XMLCALL *XML_ProcessingInstructionHandler) ( + void *userData, + const XML_Char *target, + const XML_Char *data); + +/* data is 0 terminated */ +typedef void (XMLCALL *XML_CommentHandler) (void *userData, + const XML_Char *data); + +typedef void (XMLCALL *XML_StartCdataSectionHandler) (void *userData); +typedef void (XMLCALL *XML_EndCdataSectionHandler) (void *userData); + +/* This is called for any characters in the XML document for which + there is no applicable handler. This includes both characters that + are part of markup which is of a kind that is not reported + (comments, markup declarations), or characters that are part of a + construct which could be reported but for which no handler has been + supplied. The characters are passed exactly as they were in the XML + document except that they will be encoded in UTF-8 or UTF-16. + Line boundaries are not normalized. Note that a byte order mark + character is not passed to the default handler. There are no + guarantees about how characters are divided between calls to the + default handler: for example, a comment might be split between + multiple calls. +*/ +typedef void (XMLCALL *XML_DefaultHandler) (void *userData, + const XML_Char *s, + int len); + +/* This is called for the start of the DOCTYPE declaration, before + any DTD or internal subset is parsed. +*/ +typedef void (XMLCALL *XML_StartDoctypeDeclHandler) ( + void *userData, + const XML_Char *doctypeName, + const XML_Char *sysid, + const XML_Char *pubid, + int has_internal_subset); + +/* This is called for the start of the DOCTYPE declaration when the + closing > is encountered, but after processing any external + subset. +*/ +typedef void (XMLCALL *XML_EndDoctypeDeclHandler)(void *userData); + +/* This is called for entity declarations. The is_parameter_entity + argument will be non-zero if the entity is a parameter entity, zero + otherwise. + + For internal entities (), value will + be non-NULL and systemId, publicID, and notationName will be NULL. + The value string is NOT nul-terminated; the length is provided in + the value_length argument. Since it is legal to have zero-length + values, do not use this argument to test for internal entities. + + For external entities, value will be NULL and systemId will be + non-NULL. The publicId argument will be NULL unless a public + identifier was provided. The notationName argument will have a + non-NULL value only for unparsed entity declarations. + + Note that is_parameter_entity can't be changed to XML_Bool, since + that would break binary compatibility. +*/ +typedef void (XMLCALL *XML_EntityDeclHandler) ( + void *userData, + const XML_Char *entityName, + int is_parameter_entity, + const XML_Char *value, + int value_length, + const XML_Char *base, + const XML_Char *systemId, + const XML_Char *publicId, + const XML_Char *notationName); + +XMLPARSEAPI(void) +XML_SetEntityDeclHandler(XML_Parser parser, + XML_EntityDeclHandler handler); + +/* OBSOLETE -- OBSOLETE -- OBSOLETE + This handler has been superseded by the EntityDeclHandler above. + It is provided here for backward compatibility. + + This is called for a declaration of an unparsed (NDATA) entity. + The base argument is whatever was set by XML_SetBase. The + entityName, systemId and notationName arguments will never be + NULL. The other arguments may be. +*/ +typedef void (XMLCALL *XML_UnparsedEntityDeclHandler) ( + void *userData, + const XML_Char *entityName, + const XML_Char *base, + const XML_Char *systemId, + const XML_Char *publicId, + const XML_Char *notationName); + +/* This is called for a declaration of notation. The base argument is + whatever was set by XML_SetBase. The notationName will never be + NULL. The other arguments can be. +*/ +typedef void (XMLCALL *XML_NotationDeclHandler) ( + void *userData, + const XML_Char *notationName, + const XML_Char *base, + const XML_Char *systemId, + const XML_Char *publicId); + +/* When namespace processing is enabled, these are called once for + each namespace declaration. The call to the start and end element + handlers occur between the calls to the start and end namespace + declaration handlers. For an xmlns attribute, prefix will be + NULL. For an xmlns="" attribute, uri will be NULL. +*/ +typedef void (XMLCALL *XML_StartNamespaceDeclHandler) ( + void *userData, + const XML_Char *prefix, + const XML_Char *uri); + +typedef void (XMLCALL *XML_EndNamespaceDeclHandler) ( + void *userData, + const XML_Char *prefix); + +/* This is called if the document is not standalone, that is, it has an + external subset or a reference to a parameter entity, but does not + have standalone="yes". If this handler returns XML_STATUS_ERROR, + then processing will not continue, and the parser will return a + XML_ERROR_NOT_STANDALONE error. + If parameter entity parsing is enabled, then in addition to the + conditions above this handler will only be called if the referenced + entity was actually read. +*/ +typedef int (XMLCALL *XML_NotStandaloneHandler) (void *userData); + +/* This is called for a reference to an external parsed general + entity. The referenced entity is not automatically parsed. The + application can parse it immediately or later using + XML_ExternalEntityParserCreate. + + The parser argument is the parser parsing the entity containing the + reference; it can be passed as the parser argument to + XML_ExternalEntityParserCreate. The systemId argument is the + system identifier as specified in the entity declaration; it will + not be NULL. + + The base argument is the system identifier that should be used as + the base for resolving systemId if systemId was relative; this is + set by XML_SetBase; it may be NULL. + + The publicId argument is the public identifier as specified in the + entity declaration, or NULL if none was specified; the whitespace + in the public identifier will have been normalized as required by + the XML spec. + + The context argument specifies the parsing context in the format + expected by the context argument to XML_ExternalEntityParserCreate; + context is valid only until the handler returns, so if the + referenced entity is to be parsed later, it must be copied. + context is NULL only when the entity is a parameter entity. + + The handler should return XML_STATUS_ERROR if processing should not + continue because of a fatal error in the handling of the external + entity. In this case the calling parser will return an + XML_ERROR_EXTERNAL_ENTITY_HANDLING error. + + Note that unlike other handlers the first argument is the parser, + not userData. +*/ +typedef int (XMLCALL *XML_ExternalEntityRefHandler) ( + XML_Parser parser, + const XML_Char *context, + const XML_Char *base, + const XML_Char *systemId, + const XML_Char *publicId); + +/* This is called in two situations: + 1) An entity reference is encountered for which no declaration + has been read *and* this is not an error. + 2) An internal entity reference is read, but not expanded, because + XML_SetDefaultHandler has been called. + Note: skipped parameter entities in declarations and skipped general + entities in attribute values cannot be reported, because + the event would be out of sync with the reporting of the + declarations or attribute values +*/ +typedef void (XMLCALL *XML_SkippedEntityHandler) ( + void *userData, + const XML_Char *entityName, + int is_parameter_entity); + +/* This structure is filled in by the XML_UnknownEncodingHandler to + provide information to the parser about encodings that are unknown + to the parser. + + The map[b] member gives information about byte sequences whose + first byte is b. + + If map[b] is c where c is >= 0, then b by itself encodes the + Unicode scalar value c. + + If map[b] is -1, then the byte sequence is malformed. + + If map[b] is -n, where n >= 2, then b is the first byte of an + n-byte sequence that encodes a single Unicode scalar value. + + The data member will be passed as the first argument to the convert + function. + + The convert function is used to convert multibyte sequences; s will + point to a n-byte sequence where map[(unsigned char)*s] == -n. The + convert function must return the Unicode scalar value represented + by this byte sequence or -1 if the byte sequence is malformed. + + The convert function may be NULL if the encoding is a single-byte + encoding, that is if map[b] >= -1 for all bytes b. + + When the parser is finished with the encoding, then if release is + not NULL, it will call release passing it the data member; once + release has been called, the convert function will not be called + again. + + Expat places certain restrictions on the encodings that are supported + using this mechanism. + + 1. Every ASCII character that can appear in a well-formed XML document, + other than the characters + + $@\^`{}~ + + must be represented by a single byte, and that byte must be the + same byte that represents that character in ASCII. + + 2. No character may require more than 4 bytes to encode. + + 3. All characters encoded must have Unicode scalar values <= + 0xFFFF, (i.e., characters that would be encoded by surrogates in + UTF-16 are not allowed). Note that this restriction doesn't + apply to the built-in support for UTF-8 and UTF-16. + + 4. No Unicode character may be encoded by more than one distinct + sequence of bytes. +*/ +typedef struct { + int map[256]; + void *data; + int (XMLCALL *convert)(void *data, const char *s); + void (XMLCALL *release)(void *data); +} XML_Encoding; + +/* This is called for an encoding that is unknown to the parser. + + The encodingHandlerData argument is that which was passed as the + second argument to XML_SetUnknownEncodingHandler. + + The name argument gives the name of the encoding as specified in + the encoding declaration. + + If the callback can provide information about the encoding, it must + fill in the XML_Encoding structure, and return XML_STATUS_OK. + Otherwise it must return XML_STATUS_ERROR. + + If info does not describe a suitable encoding, then the parser will + return an XML_UNKNOWN_ENCODING error. +*/ +typedef int (XMLCALL *XML_UnknownEncodingHandler) ( + void *encodingHandlerData, + const XML_Char *name, + XML_Encoding *info); + +XMLPARSEAPI(void) +XML_SetElementHandler(XML_Parser parser, + XML_StartElementHandler start, + XML_EndElementHandler end); + +XMLPARSEAPI(void) +XML_SetStartElementHandler(XML_Parser parser, + XML_StartElementHandler handler); + +XMLPARSEAPI(void) +XML_SetEndElementHandler(XML_Parser parser, + XML_EndElementHandler handler); + +XMLPARSEAPI(void) +XML_SetCharacterDataHandler(XML_Parser parser, + XML_CharacterDataHandler handler); + +XMLPARSEAPI(void) +XML_SetProcessingInstructionHandler(XML_Parser parser, + XML_ProcessingInstructionHandler handler); +XMLPARSEAPI(void) +XML_SetCommentHandler(XML_Parser parser, + XML_CommentHandler handler); + +XMLPARSEAPI(void) +XML_SetCdataSectionHandler(XML_Parser parser, + XML_StartCdataSectionHandler start, + XML_EndCdataSectionHandler end); + +XMLPARSEAPI(void) +XML_SetStartCdataSectionHandler(XML_Parser parser, + XML_StartCdataSectionHandler start); + +XMLPARSEAPI(void) +XML_SetEndCdataSectionHandler(XML_Parser parser, + XML_EndCdataSectionHandler end); + +/* This sets the default handler and also inhibits expansion of + internal entities. These entity references will be passed to the + default handler, or to the skipped entity handler, if one is set. +*/ +XMLPARSEAPI(void) +XML_SetDefaultHandler(XML_Parser parser, + XML_DefaultHandler handler); + +/* This sets the default handler but does not inhibit expansion of + internal entities. The entity reference will not be passed to the + default handler. +*/ +XMLPARSEAPI(void) +XML_SetDefaultHandlerExpand(XML_Parser parser, + XML_DefaultHandler handler); + +XMLPARSEAPI(void) +XML_SetDoctypeDeclHandler(XML_Parser parser, + XML_StartDoctypeDeclHandler start, + XML_EndDoctypeDeclHandler end); + +XMLPARSEAPI(void) +XML_SetStartDoctypeDeclHandler(XML_Parser parser, + XML_StartDoctypeDeclHandler start); + +XMLPARSEAPI(void) +XML_SetEndDoctypeDeclHandler(XML_Parser parser, + XML_EndDoctypeDeclHandler end); + +XMLPARSEAPI(void) +XML_SetUnparsedEntityDeclHandler(XML_Parser parser, + XML_UnparsedEntityDeclHandler handler); + +XMLPARSEAPI(void) +XML_SetNotationDeclHandler(XML_Parser parser, + XML_NotationDeclHandler handler); + +XMLPARSEAPI(void) +XML_SetNamespaceDeclHandler(XML_Parser parser, + XML_StartNamespaceDeclHandler start, + XML_EndNamespaceDeclHandler end); + +XMLPARSEAPI(void) +XML_SetStartNamespaceDeclHandler(XML_Parser parser, + XML_StartNamespaceDeclHandler start); + +XMLPARSEAPI(void) +XML_SetEndNamespaceDeclHandler(XML_Parser parser, + XML_EndNamespaceDeclHandler end); + +XMLPARSEAPI(void) +XML_SetNotStandaloneHandler(XML_Parser parser, + XML_NotStandaloneHandler handler); + +XMLPARSEAPI(void) +XML_SetExternalEntityRefHandler(XML_Parser parser, + XML_ExternalEntityRefHandler handler); + +/* If a non-NULL value for arg is specified here, then it will be + passed as the first argument to the external entity ref handler + instead of the parser object. +*/ +XMLPARSEAPI(void) +XML_SetExternalEntityRefHandlerArg(XML_Parser parser, + void *arg); + +XMLPARSEAPI(void) +XML_SetSkippedEntityHandler(XML_Parser parser, + XML_SkippedEntityHandler handler); + +XMLPARSEAPI(void) +XML_SetUnknownEncodingHandler(XML_Parser parser, + XML_UnknownEncodingHandler handler, + void *encodingHandlerData); + +/* This can be called within a handler for a start element, end + element, processing instruction or character data. It causes the + corresponding markup to be passed to the default handler. +*/ +XMLPARSEAPI(void) +XML_DefaultCurrent(XML_Parser parser); + +/* If do_nst is non-zero, and namespace processing is in effect, and + a name has a prefix (i.e. an explicit namespace qualifier) then + that name is returned as a triplet in a single string separated by + the separator character specified when the parser was created: URI + + sep + local_name + sep + prefix. + + If do_nst is zero, then namespace information is returned in the + default manner (URI + sep + local_name) whether or not the name + has a prefix. + + Note: Calling XML_SetReturnNSTriplet after XML_Parse or + XML_ParseBuffer has no effect. +*/ + +XMLPARSEAPI(void) +XML_SetReturnNSTriplet(XML_Parser parser, int do_nst); + +/* This value is passed as the userData argument to callbacks. */ +XMLPARSEAPI(void) +XML_SetUserData(XML_Parser parser, void *userData); + +/* Returns the last value set by XML_SetUserData or NULL. */ +#define XML_GetUserData(parser) (*(void **)(parser)) + +/* This is equivalent to supplying an encoding argument to + XML_ParserCreate. On success XML_SetEncoding returns non-zero, + zero otherwise. + Note: Calling XML_SetEncoding after XML_Parse or XML_ParseBuffer + has no effect and returns XML_STATUS_ERROR. +*/ +XMLPARSEAPI(enum XML_Status) +XML_SetEncoding(XML_Parser parser, const XML_Char *encoding); + +/* If this function is called, then the parser will be passed as the + first argument to callbacks instead of userData. The userData will + still be accessible using XML_GetUserData. +*/ +XMLPARSEAPI(void) +XML_UseParserAsHandlerArg(XML_Parser parser); + +/* If useDTD == XML_TRUE is passed to this function, then the parser + will assume that there is an external subset, even if none is + specified in the document. In such a case the parser will call the + externalEntityRefHandler with a value of NULL for the systemId + argument (the publicId and context arguments will be NULL as well). + Note: For the purpose of checking WFC: Entity Declared, passing + useDTD == XML_TRUE will make the parser behave as if the document + had a DTD with an external subset. + Note: If this function is called, then this must be done before + the first call to XML_Parse or XML_ParseBuffer, since it will + have no effect after that. Returns + XML_ERROR_CANT_CHANGE_FEATURE_ONCE_PARSING. + Note: If the document does not have a DOCTYPE declaration at all, + then startDoctypeDeclHandler and endDoctypeDeclHandler will not + be called, despite an external subset being parsed. + Note: If XML_DTD is not defined when Expat is compiled, returns + XML_ERROR_FEATURE_REQUIRES_XML_DTD. +*/ +XMLPARSEAPI(enum XML_Error) +XML_UseForeignDTD(XML_Parser parser, XML_Bool useDTD); + + +/* Sets the base to be used for resolving relative URIs in system + identifiers in declarations. Resolving relative identifiers is + left to the application: this value will be passed through as the + base argument to the XML_ExternalEntityRefHandler, + XML_NotationDeclHandler and XML_UnparsedEntityDeclHandler. The base + argument will be copied. Returns XML_STATUS_ERROR if out of memory, + XML_STATUS_OK otherwise. +*/ +XMLPARSEAPI(enum XML_Status) +XML_SetBase(XML_Parser parser, const XML_Char *base); + +XMLPARSEAPI(const XML_Char *) +XML_GetBase(XML_Parser parser); + +/* Returns the number of the attribute/value pairs passed in last call + to the XML_StartElementHandler that were specified in the start-tag + rather than defaulted. Each attribute/value pair counts as 2; thus + this correspondds to an index into the atts array passed to the + XML_StartElementHandler. +*/ +XMLPARSEAPI(int) +XML_GetSpecifiedAttributeCount(XML_Parser parser); + +/* Returns the index of the ID attribute passed in the last call to + XML_StartElementHandler, or -1 if there is no ID attribute. Each + attribute/value pair counts as 2; thus this correspondds to an + index into the atts array passed to the XML_StartElementHandler. +*/ +XMLPARSEAPI(int) +XML_GetIdAttributeIndex(XML_Parser parser); + +#ifdef XML_ATTR_INFO +/* Source file byte offsets for the start and end of attribute names and values. + The value indices are exclusive of surrounding quotes; thus in a UTF-8 source + file an attribute value of "blah" will yield: + info->valueEnd - info->valueStart = 4 bytes. +*/ +typedef struct { + XML_Index nameStart; /* Offset to beginning of the attribute name. */ + XML_Index nameEnd; /* Offset after the attribute name's last byte. */ + XML_Index valueStart; /* Offset to beginning of the attribute value. */ + XML_Index valueEnd; /* Offset after the attribute value's last byte. */ +} XML_AttrInfo; + +/* Returns an array of XML_AttrInfo structures for the attribute/value pairs + passed in last call to the XML_StartElementHandler that were specified + in the start-tag rather than defaulted. Each attribute/value pair counts + as 1; thus the number of entries in the array is + XML_GetSpecifiedAttributeCount(parser) / 2. +*/ +XMLPARSEAPI(const XML_AttrInfo *) +XML_GetAttributeInfo(XML_Parser parser); +#endif + +/* Parses some input. Returns XML_STATUS_ERROR if a fatal error is + detected. The last call to XML_Parse must have isFinal true; len + may be zero for this call (or any other). + + Though the return values for these functions has always been + described as a Boolean value, the implementation, at least for the + 1.95.x series, has always returned exactly one of the XML_Status + values. +*/ +XMLPARSEAPI(enum XML_Status) +XML_Parse(XML_Parser parser, const char *s, int len, int isFinal); + +XMLPARSEAPI(void *) +XML_GetBuffer(XML_Parser parser, int len); + +XMLPARSEAPI(enum XML_Status) +XML_ParseBuffer(XML_Parser parser, int len, int isFinal); + +/* Stops parsing, causing XML_Parse() or XML_ParseBuffer() to return. + Must be called from within a call-back handler, except when aborting + (resumable = 0) an already suspended parser. Some call-backs may + still follow because they would otherwise get lost. Examples: + - endElementHandler() for empty elements when stopped in + startElementHandler(), + - endNameSpaceDeclHandler() when stopped in endElementHandler(), + and possibly others. + + Can be called from most handlers, including DTD related call-backs, + except when parsing an external parameter entity and resumable != 0. + Returns XML_STATUS_OK when successful, XML_STATUS_ERROR otherwise. + Possible error codes: + - XML_ERROR_SUSPENDED: when suspending an already suspended parser. + - XML_ERROR_FINISHED: when the parser has already finished. + - XML_ERROR_SUSPEND_PE: when suspending while parsing an external PE. + + When resumable != 0 (true) then parsing is suspended, that is, + XML_Parse() and XML_ParseBuffer() return XML_STATUS_SUSPENDED. + Otherwise, parsing is aborted, that is, XML_Parse() and XML_ParseBuffer() + return XML_STATUS_ERROR with error code XML_ERROR_ABORTED. + + *Note*: + This will be applied to the current parser instance only, that is, if + there is a parent parser then it will continue parsing when the + externalEntityRefHandler() returns. It is up to the implementation of + the externalEntityRefHandler() to call XML_StopParser() on the parent + parser (recursively), if one wants to stop parsing altogether. + + When suspended, parsing can be resumed by calling XML_ResumeParser(). +*/ +XMLPARSEAPI(enum XML_Status) +XML_StopParser(XML_Parser parser, XML_Bool resumable); + +/* Resumes parsing after it has been suspended with XML_StopParser(). + Must not be called from within a handler call-back. Returns same + status codes as XML_Parse() or XML_ParseBuffer(). + Additional error code XML_ERROR_NOT_SUSPENDED possible. + + *Note*: + This must be called on the most deeply nested child parser instance + first, and on its parent parser only after the child parser has finished, + to be applied recursively until the document entity's parser is restarted. + That is, the parent parser will not resume by itself and it is up to the + application to call XML_ResumeParser() on it at the appropriate moment. +*/ +XMLPARSEAPI(enum XML_Status) +XML_ResumeParser(XML_Parser parser); + +enum XML_Parsing { + XML_INITIALIZED, + XML_PARSING, + XML_FINISHED, + XML_SUSPENDED +}; + +typedef struct { + enum XML_Parsing parsing; + XML_Bool finalBuffer; +} XML_ParsingStatus; + +/* Returns status of parser with respect to being initialized, parsing, + finished, or suspended and processing the final buffer. + XXX XML_Parse() and XML_ParseBuffer() should return XML_ParsingStatus, + XXX with XML_FINISHED_OK or XML_FINISHED_ERROR replacing XML_FINISHED +*/ +XMLPARSEAPI(void) +XML_GetParsingStatus(XML_Parser parser, XML_ParsingStatus *status); + +/* Creates an XML_Parser object that can parse an external general + entity; context is a '\0'-terminated string specifying the parse + context; encoding is a '\0'-terminated string giving the name of + the externally specified encoding, or NULL if there is no + externally specified encoding. The context string consists of a + sequence of tokens separated by formfeeds (\f); a token consisting + of a name specifies that the general entity of the name is open; a + token of the form prefix=uri specifies the namespace for a + particular prefix; a token of the form =uri specifies the default + namespace. This can be called at any point after the first call to + an ExternalEntityRefHandler so longer as the parser has not yet + been freed. The new parser is completely independent and may + safely be used in a separate thread. The handlers and userData are + initialized from the parser argument. Returns NULL if out of memory. + Otherwise returns a new XML_Parser object. +*/ +XMLPARSEAPI(XML_Parser) +XML_ExternalEntityParserCreate(XML_Parser parser, + const XML_Char *context, + const XML_Char *encoding); + +enum XML_ParamEntityParsing { + XML_PARAM_ENTITY_PARSING_NEVER, + XML_PARAM_ENTITY_PARSING_UNLESS_STANDALONE, + XML_PARAM_ENTITY_PARSING_ALWAYS +}; + +/* Controls parsing of parameter entities (including the external DTD + subset). If parsing of parameter entities is enabled, then + references to external parameter entities (including the external + DTD subset) will be passed to the handler set with + XML_SetExternalEntityRefHandler. The context passed will be 0. + + Unlike external general entities, external parameter entities can + only be parsed synchronously. If the external parameter entity is + to be parsed, it must be parsed during the call to the external + entity ref handler: the complete sequence of + XML_ExternalEntityParserCreate, XML_Parse/XML_ParseBuffer and + XML_ParserFree calls must be made during this call. After + XML_ExternalEntityParserCreate has been called to create the parser + for the external parameter entity (context must be 0 for this + call), it is illegal to make any calls on the old parser until + XML_ParserFree has been called on the newly created parser. + If the library has been compiled without support for parameter + entity parsing (ie without XML_DTD being defined), then + XML_SetParamEntityParsing will return 0 if parsing of parameter + entities is requested; otherwise it will return non-zero. + Note: If XML_SetParamEntityParsing is called after XML_Parse or + XML_ParseBuffer, then it has no effect and will always return 0. +*/ +XMLPARSEAPI(int) +XML_SetParamEntityParsing(XML_Parser parser, + enum XML_ParamEntityParsing parsing); + +/* Sets the hash salt to use for internal hash calculations. + Helps in preventing DoS attacks based on predicting hash + function behavior. This must be called before parsing is started. + Returns 1 if successful, 0 when called after parsing has started. +*/ +XMLPARSEAPI(int) +XML_SetHashSalt(XML_Parser parser, + unsigned long hash_salt); + +/* If XML_Parse or XML_ParseBuffer have returned XML_STATUS_ERROR, then + XML_GetErrorCode returns information about the error. +*/ +XMLPARSEAPI(enum XML_Error) +XML_GetErrorCode(XML_Parser parser); + +/* These functions return information about the current parse + location. They may be called from any callback called to report + some parse event; in this case the location is the location of the + first of the sequence of characters that generated the event. When + called from callbacks generated by declarations in the document + prologue, the location identified isn't as neatly defined, but will + be within the relevant markup. When called outside of the callback + functions, the position indicated will be just past the last parse + event (regardless of whether there was an associated callback). + + They may also be called after returning from a call to XML_Parse + or XML_ParseBuffer. If the return value is XML_STATUS_ERROR then + the location is the location of the character at which the error + was detected; otherwise the location is the location of the last + parse event, as described above. +*/ +XMLPARSEAPI(XML_Size) XML_GetCurrentLineNumber(XML_Parser parser); +XMLPARSEAPI(XML_Size) XML_GetCurrentColumnNumber(XML_Parser parser); +XMLPARSEAPI(XML_Index) XML_GetCurrentByteIndex(XML_Parser parser); + +/* Return the number of bytes in the current event. + Returns 0 if the event is in an internal entity. +*/ +XMLPARSEAPI(int) +XML_GetCurrentByteCount(XML_Parser parser); + +/* If XML_CONTEXT_BYTES is defined, returns the input buffer, sets + the integer pointed to by offset to the offset within this buffer + of the current parse position, and sets the integer pointed to by size + to the size of this buffer (the number of input bytes). Otherwise + returns a NULL pointer. Also returns a NULL pointer if a parse isn't + active. + + NOTE: The character pointer returned should not be used outside + the handler that makes the call. +*/ +XMLPARSEAPI(const char *) +XML_GetInputContext(XML_Parser parser, + int *offset, + int *size); + +/* For backwards compatibility with previous versions. */ +#define XML_GetErrorLineNumber XML_GetCurrentLineNumber +#define XML_GetErrorColumnNumber XML_GetCurrentColumnNumber +#define XML_GetErrorByteIndex XML_GetCurrentByteIndex + +/* Frees the content model passed to the element declaration handler */ +XMLPARSEAPI(void) +XML_FreeContentModel(XML_Parser parser, XML_Content *model); + +/* Exposing the memory handling functions used in Expat */ +XMLPARSEAPI(void *) +XML_ATTR_MALLOC +XML_ATTR_ALLOC_SIZE(2) +XML_MemMalloc(XML_Parser parser, size_t size); + +XMLPARSEAPI(void *) +XML_ATTR_ALLOC_SIZE(3) +XML_MemRealloc(XML_Parser parser, void *ptr, size_t size); + +XMLPARSEAPI(void) +XML_MemFree(XML_Parser parser, void *ptr); + +/* Frees memory used by the parser. */ +XMLPARSEAPI(void) +XML_ParserFree(XML_Parser parser); + +/* Returns a string describing the error. */ +XMLPARSEAPI(const XML_LChar *) +XML_ErrorString(enum XML_Error code); + +/* Return a string containing the version number of this expat */ +XMLPARSEAPI(const XML_LChar *) +XML_ExpatVersion(void); + +typedef struct { + int major; + int minor; + int micro; +} XML_Expat_Version; + +/* Return an XML_Expat_Version structure containing numeric version + number information for this version of expat. +*/ +XMLPARSEAPI(XML_Expat_Version) +XML_ExpatVersionInfo(void); + +/* Added in Expat 1.95.5. */ +enum XML_FeatureEnum { + XML_FEATURE_END = 0, + XML_FEATURE_UNICODE, + XML_FEATURE_UNICODE_WCHAR_T, + XML_FEATURE_DTD, + XML_FEATURE_CONTEXT_BYTES, + XML_FEATURE_MIN_SIZE, + XML_FEATURE_SIZEOF_XML_CHAR, + XML_FEATURE_SIZEOF_XML_LCHAR, + XML_FEATURE_NS, + XML_FEATURE_LARGE_SIZE, + XML_FEATURE_ATTR_INFO + /* Additional features must be added to the end of this enum. */ +}; + +typedef struct { + enum XML_FeatureEnum feature; + const XML_LChar *name; + long int value; +} XML_Feature; + +XMLPARSEAPI(const XML_Feature *) +XML_GetFeatureList(void); + + +/* Expat follows the semantic versioning convention. + See http://semver.org. +*/ +#define XML_MAJOR_VERSION 2 +#define XML_MINOR_VERSION 2 +#define XML_MICRO_VERSION 0 + +#ifdef __cplusplus +} +#endif + +#endif /* not Expat_INCLUDED */ diff --git a/tools/sdk/include/expat/expat_config.h b/tools/sdk/include/expat/expat_config.h new file mode 100644 index 00000000..207d1a77 --- /dev/null +++ b/tools/sdk/include/expat/expat_config.h @@ -0,0 +1,103 @@ +/* expat_config.h. Generated from expat_config.h.in by configure. */ +/* expat_config.h.in. Generated from configure.ac by autoheader. */ + +/* 1234 = LIL_ENDIAN, 4321 = BIGENDIAN */ +#define BYTEORDER 1234 + +/* Define to 1 if you have the `bcopy' function. */ +#define HAVE_BCOPY 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DLFCN_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_FCNTL_H 1 + +/* Define to 1 if you have the `getpagesize' function. */ +#define HAVE_GETPAGESIZE 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_INTTYPES_H 1 + +/* Define to 1 if you have the `memmove' function. */ +#define HAVE_MEMMOVE 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_MEMORY_H 1 + +/* Define to 1 if you have a working `mmap' system call. */ +#define HAVE_MMAP 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_STDINT_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_STDLIB_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_STRINGS_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_STRING_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_SYS_PARAM_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_SYS_STAT_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_SYS_TYPES_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_UNISTD_H 1 + +/* Define to the sub-directory in which libtool stores uninstalled libraries. + */ +#define LT_OBJDIR ".libs/" + +/* Define to the address where bug reports for this package should be sent. */ +#define PACKAGE_BUGREPORT "expat-bugs@libexpat.org" + +/* Define to the full name of this package. */ +#define PACKAGE_NAME "expat" + +/* Define to the full name and version of this package. */ +#define PACKAGE_STRING "expat 2.2.0" + +/* Define to the one symbol short name of this package. */ +#define PACKAGE_TARNAME "expat" + +/* Define to the home page for this package. */ +#define PACKAGE_URL "" + +/* Define to the version of this package. */ +#define PACKAGE_VERSION "2.2.0" + +/* Define to 1 if you have the ANSI C header files. */ +#define STDC_HEADERS 1 + +/* whether byteorder is bigendian */ +/* #undef WORDS_BIGENDIAN */ + +/* Define to specify how much context to retain around the current parse + point. */ +#define XML_CONTEXT_BYTES 1024 + +/* Define to make parameter entity parsing functionality available. */ +#define XML_DTD 1 + +/* Define to make XML Namespaces functionality available. */ +#define XML_NS 1 + +/* Define to __FUNCTION__ or "" if `__func__' does not conform to ANSI C. */ +/* #undef __func__ */ + +/* Define to empty if `const' does not conform to ANSI C. */ +/* #undef const */ + +/* Define to `long int' if does not define. */ +/* #undef off_t */ + +/* Define to `unsigned int' if does not define. */ +/* #undef size_t */ diff --git a/tools/sdk/include/expat/expat_external.h b/tools/sdk/include/expat/expat_external.h new file mode 100644 index 00000000..aa08a2f8 --- /dev/null +++ b/tools/sdk/include/expat/expat_external.h @@ -0,0 +1,129 @@ +/* Copyright (c) 1998, 1999, 2000 Thai Open Source Software Center Ltd + See the file COPYING for copying permission. +*/ + +#ifndef Expat_External_INCLUDED +#define Expat_External_INCLUDED 1 + +/* External API definitions */ + +#if defined(_MSC_EXTENSIONS) && !defined(__BEOS__) && !defined(__CYGWIN__) +#define XML_USE_MSC_EXTENSIONS 1 +#endif + +/* Expat tries very hard to make the API boundary very specifically + defined. There are two macros defined to control this boundary; + each of these can be defined before including this header to + achieve some different behavior, but doing so it not recommended or + tested frequently. + + XMLCALL - The calling convention to use for all calls across the + "library boundary." This will default to cdecl, and + try really hard to tell the compiler that's what we + want. + + XMLIMPORT - Whatever magic is needed to note that a function is + to be imported from a dynamically loaded library + (.dll, .so, or .sl, depending on your platform). + + The XMLCALL macro was added in Expat 1.95.7. The only one which is + expected to be directly useful in client code is XMLCALL. + + Note that on at least some Unix versions, the Expat library must be + compiled with the cdecl calling convention as the default since + system headers may assume the cdecl convention. +*/ +#ifndef XMLCALL +#if defined(_MSC_VER) +#define XMLCALL __cdecl +#elif defined(__GNUC__) && defined(__i386) && !defined(__INTEL_COMPILER) +#define XMLCALL __attribute__((cdecl)) +#else +/* For any platform which uses this definition and supports more than + one calling convention, we need to extend this definition to + declare the convention used on that platform, if it's possible to + do so. + + If this is the case for your platform, please file a bug report + with information on how to identify your platform via the C + pre-processor and how to specify the same calling convention as the + platform's malloc() implementation. +*/ +#define XMLCALL +#endif +#endif /* not defined XMLCALL */ + + +#if !defined(XML_STATIC) && !defined(XMLIMPORT) +#ifndef XML_BUILDING_EXPAT +/* using Expat from an application */ + +#ifdef XML_USE_MSC_EXTENSIONS +#define XMLIMPORT __declspec(dllimport) +#endif + +#endif +#endif /* not defined XML_STATIC */ + +#if !defined(XMLIMPORT) && defined(__GNUC__) && (__GNUC__ >= 4) +#define XMLIMPORT __attribute__ ((visibility ("default"))) +#endif + +/* If we didn't define it above, define it away: */ +#ifndef XMLIMPORT +#define XMLIMPORT +#endif + +#if defined(__GNUC__) && (__GNUC__ > 2 || (__GNUC__ == 2 && __GNUC_MINOR__ >= 96)) +#define XML_ATTR_MALLOC __attribute__((__malloc__)) +#else +#define XML_ATTR_MALLOC +#endif + +#if defined(__GNUC__) && ((__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 3)) +#define XML_ATTR_ALLOC_SIZE(x) __attribute__((__alloc_size__(x))) +#else +#define XML_ATTR_ALLOC_SIZE(x) +#endif + +#define XMLPARSEAPI(type) XMLIMPORT type XMLCALL + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef XML_UNICODE_WCHAR_T +#define XML_UNICODE +#endif + +#ifdef XML_UNICODE /* Information is UTF-16 encoded. */ +#ifdef XML_UNICODE_WCHAR_T +typedef wchar_t XML_Char; +typedef wchar_t XML_LChar; +#else +typedef unsigned short XML_Char; +typedef char XML_LChar; +#endif /* XML_UNICODE_WCHAR_T */ +#else /* Information is UTF-8 encoded. */ +typedef char XML_Char; +typedef char XML_LChar; +#endif /* XML_UNICODE */ + +#ifdef XML_LARGE_SIZE /* Use large integers for file/stream positions. */ +#if defined(XML_USE_MSC_EXTENSIONS) && _MSC_VER < 1400 +typedef __int64 XML_Index; +typedef unsigned __int64 XML_Size; +#else +typedef long long XML_Index; +typedef unsigned long long XML_Size; +#endif +#else +typedef long XML_Index; +typedef unsigned long XML_Size; +#endif /* XML_LARGE_SIZE */ + +#ifdef __cplusplus +} +#endif + +#endif /* not Expat_External_INCLUDED */ diff --git a/tools/sdk/include/expat/iasciitab.h b/tools/sdk/include/expat/iasciitab.h new file mode 100644 index 00000000..24a1d5cc --- /dev/null +++ b/tools/sdk/include/expat/iasciitab.h @@ -0,0 +1,37 @@ +/* Copyright (c) 1998, 1999 Thai Open Source Software Center Ltd + See the file COPYING for copying permission. +*/ + +/* Like asciitab.h, except that 0xD has code BT_S rather than BT_CR */ +/* 0x00 */ BT_NONXML, BT_NONXML, BT_NONXML, BT_NONXML, +/* 0x04 */ BT_NONXML, BT_NONXML, BT_NONXML, BT_NONXML, +/* 0x08 */ BT_NONXML, BT_S, BT_LF, BT_NONXML, +/* 0x0C */ BT_NONXML, BT_S, BT_NONXML, BT_NONXML, +/* 0x10 */ BT_NONXML, BT_NONXML, BT_NONXML, BT_NONXML, +/* 0x14 */ BT_NONXML, BT_NONXML, BT_NONXML, BT_NONXML, +/* 0x18 */ BT_NONXML, BT_NONXML, BT_NONXML, BT_NONXML, +/* 0x1C */ BT_NONXML, BT_NONXML, BT_NONXML, BT_NONXML, +/* 0x20 */ BT_S, BT_EXCL, BT_QUOT, BT_NUM, +/* 0x24 */ BT_OTHER, BT_PERCNT, BT_AMP, BT_APOS, +/* 0x28 */ BT_LPAR, BT_RPAR, BT_AST, BT_PLUS, +/* 0x2C */ BT_COMMA, BT_MINUS, BT_NAME, BT_SOL, +/* 0x30 */ BT_DIGIT, BT_DIGIT, BT_DIGIT, BT_DIGIT, +/* 0x34 */ BT_DIGIT, BT_DIGIT, BT_DIGIT, BT_DIGIT, +/* 0x38 */ BT_DIGIT, BT_DIGIT, BT_COLON, BT_SEMI, +/* 0x3C */ BT_LT, BT_EQUALS, BT_GT, BT_QUEST, +/* 0x40 */ BT_OTHER, BT_HEX, BT_HEX, BT_HEX, +/* 0x44 */ BT_HEX, BT_HEX, BT_HEX, BT_NMSTRT, +/* 0x48 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, +/* 0x4C */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, +/* 0x50 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, +/* 0x54 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, +/* 0x58 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_LSQB, +/* 0x5C */ BT_OTHER, BT_RSQB, BT_OTHER, BT_NMSTRT, +/* 0x60 */ BT_OTHER, BT_HEX, BT_HEX, BT_HEX, +/* 0x64 */ BT_HEX, BT_HEX, BT_HEX, BT_NMSTRT, +/* 0x68 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, +/* 0x6C */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, +/* 0x70 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, +/* 0x74 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, +/* 0x78 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_OTHER, +/* 0x7C */ BT_VERBAR, BT_OTHER, BT_OTHER, BT_OTHER, diff --git a/tools/sdk/include/expat/internal.h b/tools/sdk/include/expat/internal.h new file mode 100644 index 00000000..94cb98e1 --- /dev/null +++ b/tools/sdk/include/expat/internal.h @@ -0,0 +1,95 @@ +/* internal.h + + Internal definitions used by Expat. This is not needed to compile + client code. + + The following calling convention macros are defined for frequently + called functions: + + FASTCALL - Used for those internal functions that have a simple + body and a low number of arguments and local variables. + + PTRCALL - Used for functions called though function pointers. + + PTRFASTCALL - Like PTRCALL, but for low number of arguments. + + inline - Used for selected internal functions for which inlining + may improve performance on some platforms. + + Note: Use of these macros is based on judgement, not hard rules, + and therefore subject to change. +*/ + +#if defined(__GNUC__) && defined(__i386__) && !defined(__MINGW32__) +/* We'll use this version by default only where we know it helps. + + regparm() generates warnings on Solaris boxes. See SF bug #692878. + + Instability reported with egcs on a RedHat Linux 7.3. + Let's comment out: + #define FASTCALL __attribute__((stdcall, regparm(3))) + and let's try this: +*/ +#define FASTCALL __attribute__((regparm(3))) +#define PTRFASTCALL __attribute__((regparm(3))) +#endif + +/* Using __fastcall seems to have an unexpected negative effect under + MS VC++, especially for function pointers, so we won't use it for + now on that platform. It may be reconsidered for a future release + if it can be made more effective. + Likely reason: __fastcall on Windows is like stdcall, therefore + the compiler cannot perform stack optimizations for call clusters. +*/ + +/* Make sure all of these are defined if they aren't already. */ + +#ifndef FASTCALL +#define FASTCALL +#endif + +#ifndef PTRCALL +#define PTRCALL +#endif + +#ifndef PTRFASTCALL +#define PTRFASTCALL +#endif + +#ifndef XML_MIN_SIZE +#if !defined(__cplusplus) && !defined(inline) +#ifdef __GNUC__ +#define inline __inline +#endif /* __GNUC__ */ +#endif +#endif /* XML_MIN_SIZE */ + +#ifdef __cplusplus +#define inline inline +#else +#ifndef inline +#define inline +#endif +#endif + +#ifndef UNUSED_P +# ifdef __GNUC__ +# define UNUSED_P(p) UNUSED_ ## p __attribute__((__unused__)) +# else +# define UNUSED_P(p) UNUSED_ ## p +# endif +#endif + + +#ifdef __cplusplus +extern "C" { +#endif + + +void +align_limit_to_full_utf8_characters(const char * from, const char ** fromLimRef); + + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/include/expat/latin1tab.h b/tools/sdk/include/expat/latin1tab.h new file mode 100644 index 00000000..53c25d76 --- /dev/null +++ b/tools/sdk/include/expat/latin1tab.h @@ -0,0 +1,36 @@ +/* Copyright (c) 1998, 1999 Thai Open Source Software Center Ltd + See the file COPYING for copying permission. +*/ + +/* 0x80 */ BT_OTHER, BT_OTHER, BT_OTHER, BT_OTHER, +/* 0x84 */ BT_OTHER, BT_OTHER, BT_OTHER, BT_OTHER, +/* 0x88 */ BT_OTHER, BT_OTHER, BT_OTHER, BT_OTHER, +/* 0x8C */ BT_OTHER, BT_OTHER, BT_OTHER, BT_OTHER, +/* 0x90 */ BT_OTHER, BT_OTHER, BT_OTHER, BT_OTHER, +/* 0x94 */ BT_OTHER, BT_OTHER, BT_OTHER, BT_OTHER, +/* 0x98 */ BT_OTHER, BT_OTHER, BT_OTHER, BT_OTHER, +/* 0x9C */ BT_OTHER, BT_OTHER, BT_OTHER, BT_OTHER, +/* 0xA0 */ BT_OTHER, BT_OTHER, BT_OTHER, BT_OTHER, +/* 0xA4 */ BT_OTHER, BT_OTHER, BT_OTHER, BT_OTHER, +/* 0xA8 */ BT_OTHER, BT_OTHER, BT_NMSTRT, BT_OTHER, +/* 0xAC */ BT_OTHER, BT_OTHER, BT_OTHER, BT_OTHER, +/* 0xB0 */ BT_OTHER, BT_OTHER, BT_OTHER, BT_OTHER, +/* 0xB4 */ BT_OTHER, BT_NMSTRT, BT_OTHER, BT_NAME, +/* 0xB8 */ BT_OTHER, BT_OTHER, BT_NMSTRT, BT_OTHER, +/* 0xBC */ BT_OTHER, BT_OTHER, BT_OTHER, BT_OTHER, +/* 0xC0 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, +/* 0xC4 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, +/* 0xC8 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, +/* 0xCC */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, +/* 0xD0 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, +/* 0xD4 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_OTHER, +/* 0xD8 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, +/* 0xDC */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, +/* 0xE0 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, +/* 0xE4 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, +/* 0xE8 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, +/* 0xEC */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, +/* 0xF0 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, +/* 0xF4 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_OTHER, +/* 0xF8 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, +/* 0xFC */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, diff --git a/tools/sdk/include/expat/minicheck.h b/tools/sdk/include/expat/minicheck.h new file mode 100644 index 00000000..d54801d1 --- /dev/null +++ b/tools/sdk/include/expat/minicheck.h @@ -0,0 +1,95 @@ +/* Miniature re-implementation of the "check" library. + * + * This is intended to support just enough of check to run the Expat + * tests. This interface is based entirely on the portion of the + * check library being used. + * + * This is *source* compatible, but not necessary *link* compatible. + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#define CK_NOFORK 0 +#define CK_FORK 1 + +#define CK_SILENT 0 +#define CK_NORMAL 1 +#define CK_VERBOSE 2 + +/* Workaround for Microsoft's compiler and Tru64 Unix systems where the + C compiler has a working __func__, but the C++ compiler only has a + working __FUNCTION__. This could be fixed in configure.in, but it's + not worth it right now. */ +#if defined (_MSC_VER) || (defined(__osf__) && defined(__cplusplus)) +#define __func__ __FUNCTION__ +#endif + +/* ISO C90 does not support '__func__' predefined identifier */ +#if defined(__STDC_VERSION__) && (__STDC_VERSION__ < 199901) +# define __func__ "(unknown)" +#endif + +#define START_TEST(testname) static void testname(void) { \ + _check_set_test_info(__func__, __FILE__, __LINE__); \ + { +#define END_TEST + +#define fail(msg) _fail_unless(0, __FILE__, __LINE__, msg) + +typedef void (*tcase_setup_function)(void); +typedef void (*tcase_teardown_function)(void); +typedef void (*tcase_test_function)(void); + +typedef struct SRunner SRunner; +typedef struct Suite Suite; +typedef struct TCase TCase; + +struct SRunner { + Suite *suite; + int nchecks; + int nfailures; +}; + +struct Suite { + const char *name; + TCase *tests; +}; + +struct TCase { + const char *name; + tcase_setup_function setup; + tcase_teardown_function teardown; + tcase_test_function *tests; + int ntests; + int allocated; + TCase *next_tcase; +}; + + +/* Internal helper. */ +void _check_set_test_info(char const *function, + char const *filename, int lineno); + + +/* + * Prototypes for the actual implementation. + */ + +void _fail_unless(int condition, const char *file, int line, const char *msg); +Suite *suite_create(const char *name); +TCase *tcase_create(const char *name); +void suite_add_tcase(Suite *suite, TCase *tc); +void tcase_add_checked_fixture(TCase *, + tcase_setup_function, + tcase_teardown_function); +void tcase_add_test(TCase *tc, tcase_test_function test); +SRunner *srunner_create(Suite *suite); +void srunner_run_all(SRunner *runner, int verbosity); +int srunner_ntests_failed(SRunner *runner); +void srunner_free(SRunner *runner); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/include/expat/nametab.h b/tools/sdk/include/expat/nametab.h new file mode 100644 index 00000000..b05e62c7 --- /dev/null +++ b/tools/sdk/include/expat/nametab.h @@ -0,0 +1,150 @@ +static const unsigned namingBitmap[] = { +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +0x00000000, 0x04000000, 0x87FFFFFE, 0x07FFFFFE, +0x00000000, 0x00000000, 0xFF7FFFFF, 0xFF7FFFFF, +0xFFFFFFFF, 0x7FF3FFFF, 0xFFFFFDFE, 0x7FFFFFFF, +0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFE00F, 0xFC31FFFF, +0x00FFFFFF, 0x00000000, 0xFFFF0000, 0xFFFFFFFF, +0xFFFFFFFF, 0xF80001FF, 0x00000003, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0xFFFFD740, 0xFFFFFFFB, 0x547F7FFF, 0x000FFFFD, +0xFFFFDFFE, 0xFFFFFFFF, 0xDFFEFFFF, 0xFFFFFFFF, +0xFFFF0003, 0xFFFFFFFF, 0xFFFF199F, 0x033FCFFF, +0x00000000, 0xFFFE0000, 0x027FFFFF, 0xFFFFFFFE, +0x0000007F, 0x00000000, 0xFFFF0000, 0x000707FF, +0x00000000, 0x07FFFFFE, 0x000007FE, 0xFFFE0000, +0xFFFFFFFF, 0x7CFFFFFF, 0x002F7FFF, 0x00000060, +0xFFFFFFE0, 0x23FFFFFF, 0xFF000000, 0x00000003, +0xFFF99FE0, 0x03C5FDFF, 0xB0000000, 0x00030003, +0xFFF987E0, 0x036DFDFF, 0x5E000000, 0x001C0000, +0xFFFBAFE0, 0x23EDFDFF, 0x00000000, 0x00000001, +0xFFF99FE0, 0x23CDFDFF, 0xB0000000, 0x00000003, +0xD63DC7E0, 0x03BFC718, 0x00000000, 0x00000000, +0xFFFDDFE0, 0x03EFFDFF, 0x00000000, 0x00000003, +0xFFFDDFE0, 0x03EFFDFF, 0x40000000, 0x00000003, +0xFFFDDFE0, 0x03FFFDFF, 0x00000000, 0x00000003, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0xFFFFFFFE, 0x000D7FFF, 0x0000003F, 0x00000000, +0xFEF02596, 0x200D6CAE, 0x0000001F, 0x00000000, +0x00000000, 0x00000000, 0xFFFFFEFF, 0x000003FF, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0xFFFFFFFF, 0xFFFF003F, 0x007FFFFF, +0x0007DAED, 0x50000000, 0x82315001, 0x002C62AB, +0x40000000, 0xF580C900, 0x00000007, 0x02010800, +0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +0x0FFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x03FFFFFF, +0x3F3FFFFF, 0xFFFFFFFF, 0xAAFF3F3F, 0x3FFFFFFF, +0xFFFFFFFF, 0x5FDFFFFF, 0x0FCF1FDC, 0x1FDC1FFF, +0x00000000, 0x00004C40, 0x00000000, 0x00000000, +0x00000007, 0x00000000, 0x00000000, 0x00000000, +0x00000080, 0x000003FE, 0xFFFFFFFE, 0xFFFFFFFF, +0x001FFFFF, 0xFFFFFFFE, 0xFFFFFFFF, 0x07FFFFFF, +0xFFFFFFE0, 0x00001FFF, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +0xFFFFFFFF, 0x0000003F, 0x00000000, 0x00000000, +0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +0xFFFFFFFF, 0x0000000F, 0x00000000, 0x00000000, +0x00000000, 0x07FF6000, 0x87FFFFFE, 0x07FFFFFE, +0x00000000, 0x00800000, 0xFF7FFFFF, 0xFF7FFFFF, +0x00FFFFFF, 0x00000000, 0xFFFF0000, 0xFFFFFFFF, +0xFFFFFFFF, 0xF80001FF, 0x00030003, 0x00000000, +0xFFFFFFFF, 0xFFFFFFFF, 0x0000003F, 0x00000003, +0xFFFFD7C0, 0xFFFFFFFB, 0x547F7FFF, 0x000FFFFD, +0xFFFFDFFE, 0xFFFFFFFF, 0xDFFEFFFF, 0xFFFFFFFF, +0xFFFF007B, 0xFFFFFFFF, 0xFFFF199F, 0x033FCFFF, +0x00000000, 0xFFFE0000, 0x027FFFFF, 0xFFFFFFFE, +0xFFFE007F, 0xBBFFFFFB, 0xFFFF0016, 0x000707FF, +0x00000000, 0x07FFFFFE, 0x0007FFFF, 0xFFFF03FF, +0xFFFFFFFF, 0x7CFFFFFF, 0xFFEF7FFF, 0x03FF3DFF, +0xFFFFFFEE, 0xF3FFFFFF, 0xFF1E3FFF, 0x0000FFCF, +0xFFF99FEE, 0xD3C5FDFF, 0xB080399F, 0x0003FFCF, +0xFFF987E4, 0xD36DFDFF, 0x5E003987, 0x001FFFC0, +0xFFFBAFEE, 0xF3EDFDFF, 0x00003BBF, 0x0000FFC1, +0xFFF99FEE, 0xF3CDFDFF, 0xB0C0398F, 0x0000FFC3, +0xD63DC7EC, 0xC3BFC718, 0x00803DC7, 0x0000FF80, +0xFFFDDFEE, 0xC3EFFDFF, 0x00603DDF, 0x0000FFC3, +0xFFFDDFEC, 0xC3EFFDFF, 0x40603DDF, 0x0000FFC3, +0xFFFDDFEC, 0xC3FFFDFF, 0x00803DCF, 0x0000FFC3, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0xFFFFFFFE, 0x07FF7FFF, 0x03FF7FFF, 0x00000000, +0xFEF02596, 0x3BFF6CAE, 0x03FF3F5F, 0x00000000, +0x03000000, 0xC2A003FF, 0xFFFFFEFF, 0xFFFE03FF, +0xFEBF0FDF, 0x02FE3FFF, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x1FFF0000, 0x00000002, +0x000000A0, 0x003EFFFE, 0xFFFFFFFE, 0xFFFFFFFF, +0x661FFFFF, 0xFFFFFFFE, 0xFFFFFFFF, 0x77FFFFFF, +}; +static const unsigned char nmstrtPages[] = { +0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x00, +0x00, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, +0x10, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x13, +0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x15, 0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, +0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, +0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, +0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, +0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, +0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, +0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, +0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, +0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, +0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, +0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x17, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, +0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, +0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, +0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, +0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, +0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x18, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; +static const unsigned char namePages[] = { +0x19, 0x03, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x00, +0x00, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, +0x10, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x13, +0x26, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x27, 0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, +0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, +0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, +0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, +0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, +0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, +0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, +0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, +0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, +0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, +0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x17, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, +0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, +0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, +0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, +0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, +0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x18, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; diff --git a/tools/sdk/include/expat/utf8tab.h b/tools/sdk/include/expat/utf8tab.h new file mode 100644 index 00000000..7bb3e776 --- /dev/null +++ b/tools/sdk/include/expat/utf8tab.h @@ -0,0 +1,37 @@ +/* Copyright (c) 1998, 1999 Thai Open Source Software Center Ltd + See the file COPYING for copying permission. +*/ + + +/* 0x80 */ BT_TRAIL, BT_TRAIL, BT_TRAIL, BT_TRAIL, +/* 0x84 */ BT_TRAIL, BT_TRAIL, BT_TRAIL, BT_TRAIL, +/* 0x88 */ BT_TRAIL, BT_TRAIL, BT_TRAIL, BT_TRAIL, +/* 0x8C */ BT_TRAIL, BT_TRAIL, BT_TRAIL, BT_TRAIL, +/* 0x90 */ BT_TRAIL, BT_TRAIL, BT_TRAIL, BT_TRAIL, +/* 0x94 */ BT_TRAIL, BT_TRAIL, BT_TRAIL, BT_TRAIL, +/* 0x98 */ BT_TRAIL, BT_TRAIL, BT_TRAIL, BT_TRAIL, +/* 0x9C */ BT_TRAIL, BT_TRAIL, BT_TRAIL, BT_TRAIL, +/* 0xA0 */ BT_TRAIL, BT_TRAIL, BT_TRAIL, BT_TRAIL, +/* 0xA4 */ BT_TRAIL, BT_TRAIL, BT_TRAIL, BT_TRAIL, +/* 0xA8 */ BT_TRAIL, BT_TRAIL, BT_TRAIL, BT_TRAIL, +/* 0xAC */ BT_TRAIL, BT_TRAIL, BT_TRAIL, BT_TRAIL, +/* 0xB0 */ BT_TRAIL, BT_TRAIL, BT_TRAIL, BT_TRAIL, +/* 0xB4 */ BT_TRAIL, BT_TRAIL, BT_TRAIL, BT_TRAIL, +/* 0xB8 */ BT_TRAIL, BT_TRAIL, BT_TRAIL, BT_TRAIL, +/* 0xBC */ BT_TRAIL, BT_TRAIL, BT_TRAIL, BT_TRAIL, +/* 0xC0 */ BT_LEAD2, BT_LEAD2, BT_LEAD2, BT_LEAD2, +/* 0xC4 */ BT_LEAD2, BT_LEAD2, BT_LEAD2, BT_LEAD2, +/* 0xC8 */ BT_LEAD2, BT_LEAD2, BT_LEAD2, BT_LEAD2, +/* 0xCC */ BT_LEAD2, BT_LEAD2, BT_LEAD2, BT_LEAD2, +/* 0xD0 */ BT_LEAD2, BT_LEAD2, BT_LEAD2, BT_LEAD2, +/* 0xD4 */ BT_LEAD2, BT_LEAD2, BT_LEAD2, BT_LEAD2, +/* 0xD8 */ BT_LEAD2, BT_LEAD2, BT_LEAD2, BT_LEAD2, +/* 0xDC */ BT_LEAD2, BT_LEAD2, BT_LEAD2, BT_LEAD2, +/* 0xE0 */ BT_LEAD3, BT_LEAD3, BT_LEAD3, BT_LEAD3, +/* 0xE4 */ BT_LEAD3, BT_LEAD3, BT_LEAD3, BT_LEAD3, +/* 0xE8 */ BT_LEAD3, BT_LEAD3, BT_LEAD3, BT_LEAD3, +/* 0xEC */ BT_LEAD3, BT_LEAD3, BT_LEAD3, BT_LEAD3, +/* 0xF0 */ BT_LEAD4, BT_LEAD4, BT_LEAD4, BT_LEAD4, +/* 0xF4 */ BT_LEAD4, BT_NONXML, BT_NONXML, BT_NONXML, +/* 0xF8 */ BT_NONXML, BT_NONXML, BT_NONXML, BT_NONXML, +/* 0xFC */ BT_NONXML, BT_NONXML, BT_MALFORM, BT_MALFORM, diff --git a/tools/sdk/include/expat/xmlrole.h b/tools/sdk/include/expat/xmlrole.h new file mode 100644 index 00000000..4dd9f06f --- /dev/null +++ b/tools/sdk/include/expat/xmlrole.h @@ -0,0 +1,114 @@ +/* Copyright (c) 1998, 1999 Thai Open Source Software Center Ltd + See the file COPYING for copying permission. +*/ + +#ifndef XmlRole_INCLUDED +#define XmlRole_INCLUDED 1 + +#ifdef __VMS +/* 0 1 2 3 0 1 2 3 + 1234567890123456789012345678901 1234567890123456789012345678901 */ +#define XmlPrologStateInitExternalEntity XmlPrologStateInitExternalEnt +#endif + +#include "xmltok.h" + +#ifdef __cplusplus +extern "C" { +#endif + +enum { + XML_ROLE_ERROR = -1, + XML_ROLE_NONE = 0, + XML_ROLE_XML_DECL, + XML_ROLE_INSTANCE_START, + XML_ROLE_DOCTYPE_NONE, + XML_ROLE_DOCTYPE_NAME, + XML_ROLE_DOCTYPE_SYSTEM_ID, + XML_ROLE_DOCTYPE_PUBLIC_ID, + XML_ROLE_DOCTYPE_INTERNAL_SUBSET, + XML_ROLE_DOCTYPE_CLOSE, + XML_ROLE_GENERAL_ENTITY_NAME, + XML_ROLE_PARAM_ENTITY_NAME, + XML_ROLE_ENTITY_NONE, + XML_ROLE_ENTITY_VALUE, + XML_ROLE_ENTITY_SYSTEM_ID, + XML_ROLE_ENTITY_PUBLIC_ID, + XML_ROLE_ENTITY_COMPLETE, + XML_ROLE_ENTITY_NOTATION_NAME, + XML_ROLE_NOTATION_NONE, + XML_ROLE_NOTATION_NAME, + XML_ROLE_NOTATION_SYSTEM_ID, + XML_ROLE_NOTATION_NO_SYSTEM_ID, + XML_ROLE_NOTATION_PUBLIC_ID, + XML_ROLE_ATTRIBUTE_NAME, + XML_ROLE_ATTRIBUTE_TYPE_CDATA, + XML_ROLE_ATTRIBUTE_TYPE_ID, + XML_ROLE_ATTRIBUTE_TYPE_IDREF, + XML_ROLE_ATTRIBUTE_TYPE_IDREFS, + XML_ROLE_ATTRIBUTE_TYPE_ENTITY, + XML_ROLE_ATTRIBUTE_TYPE_ENTITIES, + XML_ROLE_ATTRIBUTE_TYPE_NMTOKEN, + XML_ROLE_ATTRIBUTE_TYPE_NMTOKENS, + XML_ROLE_ATTRIBUTE_ENUM_VALUE, + XML_ROLE_ATTRIBUTE_NOTATION_VALUE, + XML_ROLE_ATTLIST_NONE, + XML_ROLE_ATTLIST_ELEMENT_NAME, + XML_ROLE_IMPLIED_ATTRIBUTE_VALUE, + XML_ROLE_REQUIRED_ATTRIBUTE_VALUE, + XML_ROLE_DEFAULT_ATTRIBUTE_VALUE, + XML_ROLE_FIXED_ATTRIBUTE_VALUE, + XML_ROLE_ELEMENT_NONE, + XML_ROLE_ELEMENT_NAME, + XML_ROLE_CONTENT_ANY, + XML_ROLE_CONTENT_EMPTY, + XML_ROLE_CONTENT_PCDATA, + XML_ROLE_GROUP_OPEN, + XML_ROLE_GROUP_CLOSE, + XML_ROLE_GROUP_CLOSE_REP, + XML_ROLE_GROUP_CLOSE_OPT, + XML_ROLE_GROUP_CLOSE_PLUS, + XML_ROLE_GROUP_CHOICE, + XML_ROLE_GROUP_SEQUENCE, + XML_ROLE_CONTENT_ELEMENT, + XML_ROLE_CONTENT_ELEMENT_REP, + XML_ROLE_CONTENT_ELEMENT_OPT, + XML_ROLE_CONTENT_ELEMENT_PLUS, + XML_ROLE_PI, + XML_ROLE_COMMENT, +#ifdef XML_DTD + XML_ROLE_TEXT_DECL, + XML_ROLE_IGNORE_SECT, + XML_ROLE_INNER_PARAM_ENTITY_REF, +#endif /* XML_DTD */ + XML_ROLE_PARAM_ENTITY_REF +}; + +typedef struct prolog_state { + int (PTRCALL *handler) (struct prolog_state *state, + int tok, + const char *ptr, + const char *end, + const ENCODING *enc); + unsigned level; + int role_none; +#ifdef XML_DTD + unsigned includeLevel; + int documentEntity; + int inEntityValue; +#endif /* XML_DTD */ +} PROLOG_STATE; + +void XmlPrologStateInit(PROLOG_STATE *); +#ifdef XML_DTD +void XmlPrologStateInitExternalEntity(PROLOG_STATE *); +#endif /* XML_DTD */ + +#define XmlTokenRole(state, tok, ptr, end, enc) \ + (((state)->handler)(state, tok, ptr, end, enc)) + +#ifdef __cplusplus +} +#endif + +#endif /* not XmlRole_INCLUDED */ diff --git a/tools/sdk/include/expat/xmltok.h b/tools/sdk/include/expat/xmltok.h new file mode 100644 index 00000000..752007e8 --- /dev/null +++ b/tools/sdk/include/expat/xmltok.h @@ -0,0 +1,322 @@ +/* Copyright (c) 1998, 1999 Thai Open Source Software Center Ltd + See the file COPYING for copying permission. +*/ + +#ifndef XmlTok_INCLUDED +#define XmlTok_INCLUDED 1 + +#ifdef __cplusplus +extern "C" { +#endif + +/* The following token may be returned by XmlContentTok */ +#define XML_TOK_TRAILING_RSQB -5 /* ] or ]] at the end of the scan; might be + start of illegal ]]> sequence */ +/* The following tokens may be returned by both XmlPrologTok and + XmlContentTok. +*/ +#define XML_TOK_NONE -4 /* The string to be scanned is empty */ +#define XML_TOK_TRAILING_CR -3 /* A CR at the end of the scan; + might be part of CRLF sequence */ +#define XML_TOK_PARTIAL_CHAR -2 /* only part of a multibyte sequence */ +#define XML_TOK_PARTIAL -1 /* only part of a token */ +#define XML_TOK_INVALID 0 + +/* The following tokens are returned by XmlContentTok; some are also + returned by XmlAttributeValueTok, XmlEntityTok, XmlCdataSectionTok. +*/ +#define XML_TOK_START_TAG_WITH_ATTS 1 +#define XML_TOK_START_TAG_NO_ATTS 2 +#define XML_TOK_EMPTY_ELEMENT_WITH_ATTS 3 /* empty element tag */ +#define XML_TOK_EMPTY_ELEMENT_NO_ATTS 4 +#define XML_TOK_END_TAG 5 +#define XML_TOK_DATA_CHARS 6 +#define XML_TOK_DATA_NEWLINE 7 +#define XML_TOK_CDATA_SECT_OPEN 8 +#define XML_TOK_ENTITY_REF 9 +#define XML_TOK_CHAR_REF 10 /* numeric character reference */ + +/* The following tokens may be returned by both XmlPrologTok and + XmlContentTok. +*/ +#define XML_TOK_PI 11 /* processing instruction */ +#define XML_TOK_XML_DECL 12 /* XML decl or text decl */ +#define XML_TOK_COMMENT 13 +#define XML_TOK_BOM 14 /* Byte order mark */ + +/* The following tokens are returned only by XmlPrologTok */ +#define XML_TOK_PROLOG_S 15 +#define XML_TOK_DECL_OPEN 16 /* */ +#define XML_TOK_NAME 18 +#define XML_TOK_NMTOKEN 19 +#define XML_TOK_POUND_NAME 20 /* #name */ +#define XML_TOK_OR 21 /* | */ +#define XML_TOK_PERCENT 22 +#define XML_TOK_OPEN_PAREN 23 +#define XML_TOK_CLOSE_PAREN 24 +#define XML_TOK_OPEN_BRACKET 25 +#define XML_TOK_CLOSE_BRACKET 26 +#define XML_TOK_LITERAL 27 +#define XML_TOK_PARAM_ENTITY_REF 28 +#define XML_TOK_INSTANCE_START 29 + +/* The following occur only in element type declarations */ +#define XML_TOK_NAME_QUESTION 30 /* name? */ +#define XML_TOK_NAME_ASTERISK 31 /* name* */ +#define XML_TOK_NAME_PLUS 32 /* name+ */ +#define XML_TOK_COND_SECT_OPEN 33 /* */ +#define XML_TOK_CLOSE_PAREN_QUESTION 35 /* )? */ +#define XML_TOK_CLOSE_PAREN_ASTERISK 36 /* )* */ +#define XML_TOK_CLOSE_PAREN_PLUS 37 /* )+ */ +#define XML_TOK_COMMA 38 + +/* The following token is returned only by XmlAttributeValueTok */ +#define XML_TOK_ATTRIBUTE_VALUE_S 39 + +/* The following token is returned only by XmlCdataSectionTok */ +#define XML_TOK_CDATA_SECT_CLOSE 40 + +/* With namespace processing this is returned by XmlPrologTok for a + name with a colon. +*/ +#define XML_TOK_PREFIXED_NAME 41 + +#ifdef XML_DTD +#define XML_TOK_IGNORE_SECT 42 +#endif /* XML_DTD */ + +#ifdef XML_DTD +#define XML_N_STATES 4 +#else /* not XML_DTD */ +#define XML_N_STATES 3 +#endif /* not XML_DTD */ + +#define XML_PROLOG_STATE 0 +#define XML_CONTENT_STATE 1 +#define XML_CDATA_SECTION_STATE 2 +#ifdef XML_DTD +#define XML_IGNORE_SECTION_STATE 3 +#endif /* XML_DTD */ + +#define XML_N_LITERAL_TYPES 2 +#define XML_ATTRIBUTE_VALUE_LITERAL 0 +#define XML_ENTITY_VALUE_LITERAL 1 + +/* The size of the buffer passed to XmlUtf8Encode must be at least this. */ +#define XML_UTF8_ENCODE_MAX 4 +/* The size of the buffer passed to XmlUtf16Encode must be at least this. */ +#define XML_UTF16_ENCODE_MAX 2 + +typedef struct position { + /* first line and first column are 0 not 1 */ + XML_Size lineNumber; + XML_Size columnNumber; +} POSITION; + +typedef struct { + const char *name; + const char *valuePtr; + const char *valueEnd; + char normalized; +} ATTRIBUTE; + +struct encoding; +typedef struct encoding ENCODING; + +typedef int (PTRCALL *SCANNER)(const ENCODING *, + const char *, + const char *, + const char **); + +enum XML_Convert_Result { + XML_CONVERT_COMPLETED = 0, + XML_CONVERT_INPUT_INCOMPLETE = 1, + XML_CONVERT_OUTPUT_EXHAUSTED = 2 /* and therefore potentially input remaining as well */ +}; + +struct encoding { + SCANNER scanners[XML_N_STATES]; + SCANNER literalScanners[XML_N_LITERAL_TYPES]; + int (PTRCALL *sameName)(const ENCODING *, + const char *, + const char *); + int (PTRCALL *nameMatchesAscii)(const ENCODING *, + const char *, + const char *, + const char *); + int (PTRFASTCALL *nameLength)(const ENCODING *, const char *); + const char *(PTRFASTCALL *skipS)(const ENCODING *, const char *); + int (PTRCALL *getAtts)(const ENCODING *enc, + const char *ptr, + int attsMax, + ATTRIBUTE *atts); + int (PTRFASTCALL *charRefNumber)(const ENCODING *enc, const char *ptr); + int (PTRCALL *predefinedEntityName)(const ENCODING *, + const char *, + const char *); + void (PTRCALL *updatePosition)(const ENCODING *, + const char *ptr, + const char *end, + POSITION *); + int (PTRCALL *isPublicId)(const ENCODING *enc, + const char *ptr, + const char *end, + const char **badPtr); + enum XML_Convert_Result (PTRCALL *utf8Convert)(const ENCODING *enc, + const char **fromP, + const char *fromLim, + char **toP, + const char *toLim); + enum XML_Convert_Result (PTRCALL *utf16Convert)(const ENCODING *enc, + const char **fromP, + const char *fromLim, + unsigned short **toP, + const unsigned short *toLim); + int minBytesPerChar; + char isUtf8; + char isUtf16; +}; + +/* Scan the string starting at ptr until the end of the next complete + token, but do not scan past eptr. Return an integer giving the + type of token. + + Return XML_TOK_NONE when ptr == eptr; nextTokPtr will not be set. + + Return XML_TOK_PARTIAL when the string does not contain a complete + token; nextTokPtr will not be set. + + Return XML_TOK_INVALID when the string does not start a valid + token; nextTokPtr will be set to point to the character which made + the token invalid. + + Otherwise the string starts with a valid token; nextTokPtr will be + set to point to the character following the end of that token. + + Each data character counts as a single token, but adjacent data + characters may be returned together. Similarly for characters in + the prolog outside literals, comments and processing instructions. +*/ + + +#define XmlTok(enc, state, ptr, end, nextTokPtr) \ + (((enc)->scanners[state])(enc, ptr, end, nextTokPtr)) + +#define XmlPrologTok(enc, ptr, end, nextTokPtr) \ + XmlTok(enc, XML_PROLOG_STATE, ptr, end, nextTokPtr) + +#define XmlContentTok(enc, ptr, end, nextTokPtr) \ + XmlTok(enc, XML_CONTENT_STATE, ptr, end, nextTokPtr) + +#define XmlCdataSectionTok(enc, ptr, end, nextTokPtr) \ + XmlTok(enc, XML_CDATA_SECTION_STATE, ptr, end, nextTokPtr) + +#ifdef XML_DTD + +#define XmlIgnoreSectionTok(enc, ptr, end, nextTokPtr) \ + XmlTok(enc, XML_IGNORE_SECTION_STATE, ptr, end, nextTokPtr) + +#endif /* XML_DTD */ + +/* This is used for performing a 2nd-level tokenization on the content + of a literal that has already been returned by XmlTok. +*/ +#define XmlLiteralTok(enc, literalType, ptr, end, nextTokPtr) \ + (((enc)->literalScanners[literalType])(enc, ptr, end, nextTokPtr)) + +#define XmlAttributeValueTok(enc, ptr, end, nextTokPtr) \ + XmlLiteralTok(enc, XML_ATTRIBUTE_VALUE_LITERAL, ptr, end, nextTokPtr) + +#define XmlEntityValueTok(enc, ptr, end, nextTokPtr) \ + XmlLiteralTok(enc, XML_ENTITY_VALUE_LITERAL, ptr, end, nextTokPtr) + +#define XmlSameName(enc, ptr1, ptr2) (((enc)->sameName)(enc, ptr1, ptr2)) + +#define XmlNameMatchesAscii(enc, ptr1, end1, ptr2) \ + (((enc)->nameMatchesAscii)(enc, ptr1, end1, ptr2)) + +#define XmlNameLength(enc, ptr) \ + (((enc)->nameLength)(enc, ptr)) + +#define XmlSkipS(enc, ptr) \ + (((enc)->skipS)(enc, ptr)) + +#define XmlGetAttributes(enc, ptr, attsMax, atts) \ + (((enc)->getAtts)(enc, ptr, attsMax, atts)) + +#define XmlCharRefNumber(enc, ptr) \ + (((enc)->charRefNumber)(enc, ptr)) + +#define XmlPredefinedEntityName(enc, ptr, end) \ + (((enc)->predefinedEntityName)(enc, ptr, end)) + +#define XmlUpdatePosition(enc, ptr, end, pos) \ + (((enc)->updatePosition)(enc, ptr, end, pos)) + +#define XmlIsPublicId(enc, ptr, end, badPtr) \ + (((enc)->isPublicId)(enc, ptr, end, badPtr)) + +#define XmlUtf8Convert(enc, fromP, fromLim, toP, toLim) \ + (((enc)->utf8Convert)(enc, fromP, fromLim, toP, toLim)) + +#define XmlUtf16Convert(enc, fromP, fromLim, toP, toLim) \ + (((enc)->utf16Convert)(enc, fromP, fromLim, toP, toLim)) + +typedef struct { + ENCODING initEnc; + const ENCODING **encPtr; +} INIT_ENCODING; + +int XmlParseXmlDecl(int isGeneralTextEntity, + const ENCODING *enc, + const char *ptr, + const char *end, + const char **badPtr, + const char **versionPtr, + const char **versionEndPtr, + const char **encodingNamePtr, + const ENCODING **namedEncodingPtr, + int *standalonePtr); + +int XmlInitEncoding(INIT_ENCODING *, const ENCODING **, const char *name); +const ENCODING *XmlGetUtf8InternalEncoding(void); +const ENCODING *XmlGetUtf16InternalEncoding(void); +int FASTCALL XmlUtf8Encode(int charNumber, char *buf); +int FASTCALL XmlUtf16Encode(int charNumber, unsigned short *buf); +int XmlSizeOfUnknownEncoding(void); + + +typedef int (XMLCALL *CONVERTER) (void *userData, const char *p); + +ENCODING * +XmlInitUnknownEncoding(void *mem, + int *table, + CONVERTER convert, + void *userData); + +int XmlParseXmlDeclNS(int isGeneralTextEntity, + const ENCODING *enc, + const char *ptr, + const char *end, + const char **badPtr, + const char **versionPtr, + const char **versionEndPtr, + const char **encodingNamePtr, + const ENCODING **namedEncodingPtr, + int *standalonePtr); + +int XmlInitEncodingNS(INIT_ENCODING *, const ENCODING **, const char *name); +const ENCODING *XmlGetUtf8InternalEncodingNS(void); +const ENCODING *XmlGetUtf16InternalEncodingNS(void); +ENCODING * +XmlInitUnknownEncodingNS(void *mem, + int *table, + CONVERTER convert, + void *userData); +#ifdef __cplusplus +} +#endif + +#endif /* not XmlTok_INCLUDED */ diff --git a/tools/sdk/include/expat/xmltok_impl.h b/tools/sdk/include/expat/xmltok_impl.h new file mode 100644 index 00000000..da0ea60a --- /dev/null +++ b/tools/sdk/include/expat/xmltok_impl.h @@ -0,0 +1,46 @@ +/* +Copyright (c) 1998, 1999 Thai Open Source Software Center Ltd +See the file COPYING for copying permission. +*/ + +enum { + BT_NONXML, + BT_MALFORM, + BT_LT, + BT_AMP, + BT_RSQB, + BT_LEAD2, + BT_LEAD3, + BT_LEAD4, + BT_TRAIL, + BT_CR, + BT_LF, + BT_GT, + BT_QUOT, + BT_APOS, + BT_EQUALS, + BT_QUEST, + BT_EXCL, + BT_SOL, + BT_SEMI, + BT_NUM, + BT_LSQB, + BT_S, + BT_NMSTRT, + BT_COLON, + BT_HEX, + BT_DIGIT, + BT_NAME, + BT_MINUS, + BT_OTHER, /* known not to be a name or name start character */ + BT_NONASCII, /* might be a name or name start character */ + BT_PERCNT, + BT_LPAR, + BT_RPAR, + BT_AST, + BT_PLUS, + BT_COMMA, + BT_VERBAR +}; + +#include diff --git a/tools/sdk/include/freertos/freertos/FreeRTOS.h b/tools/sdk/include/freertos/freertos/FreeRTOS.h new file mode 100644 index 00000000..04b39b65 --- /dev/null +++ b/tools/sdk/include/freertos/freertos/FreeRTOS.h @@ -0,0 +1,799 @@ +/* + FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef INC_FREERTOS_H +#define INC_FREERTOS_H + +/* + * Include the generic headers required for the FreeRTOS port being used. + */ +#include + +/* + * If stdint.h cannot be located then: + * + If using GCC ensure the -nostdint options is *not* being used. + * + Ensure the project's include path includes the directory in which your + * compiler stores stdint.h. + * + Set any compiler options necessary for it to support C99, as technically + * stdint.h is only mandatory with C99 (FreeRTOS does not require C99 in any + * other way). + * + The FreeRTOS download includes a simple stdint.h definition that can be + * used in cases where none is provided by the compiler. The files only + * contains the typedefs required to build FreeRTOS. Read the instructions + * in FreeRTOS/source/stdint.readme for more information. + */ +#include /* READ COMMENT ABOVE. */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Application specific configuration options. */ +#include "FreeRTOSConfig.h" + +/* Basic FreeRTOS definitions. */ +#include "projdefs.h" + +/* Definitions specific to the port being used. */ +#include "portable.h" + +/* + * Check all the required application specific macros have been defined. + * These macros are application specific and (as downloaded) are defined + * within FreeRTOSConfig.h. + */ + +#ifndef configMINIMAL_STACK_SIZE + #error Missing definition: configMINIMAL_STACK_SIZE must be defined in FreeRTOSConfig.h. configMINIMAL_STACK_SIZE defines the size (in words) of the stack allocated to the idle task. Refer to the demo project provided for your port for a suitable value. +#endif + +#ifndef configMAX_PRIORITIES + #error Missing definition: configMAX_PRIORITIES must be defined in FreeRTOSConfig.h. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_PREEMPTION + #error Missing definition: configUSE_PREEMPTION must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_IDLE_HOOK + #error Missing definition: configUSE_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_TICK_HOOK + #error Missing definition: configUSE_TICK_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_CO_ROUTINES + #error Missing definition: configUSE_CO_ROUTINES must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef INCLUDE_vTaskPrioritySet + #error Missing definition: INCLUDE_vTaskPrioritySet must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef INCLUDE_uxTaskPriorityGet + #error Missing definition: INCLUDE_uxTaskPriorityGet must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef INCLUDE_vTaskDelete + #error Missing definition: INCLUDE_vTaskDelete must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef INCLUDE_vTaskSuspend + #error Missing definition: INCLUDE_vTaskSuspend must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef INCLUDE_vTaskDelayUntil + #error Missing definition: INCLUDE_vTaskDelayUntil must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef INCLUDE_vTaskDelay + #error Missing definition: INCLUDE_vTaskDelay must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_16_BIT_TICKS + #error Missing definition: configUSE_16_BIT_TICKS must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#if configUSE_CO_ROUTINES != 0 + #ifndef configMAX_CO_ROUTINE_PRIORITIES + #error configMAX_CO_ROUTINE_PRIORITIES must be greater than or equal to 1. + #endif +#endif + +#ifndef configMAX_PRIORITIES + #error configMAX_PRIORITIES must be defined to be greater than or equal to 1. +#endif + +#ifndef INCLUDE_xTaskGetIdleTaskHandle + #define INCLUDE_xTaskGetIdleTaskHandle 0 +#endif + +#ifndef INCLUDE_xTimerGetTimerDaemonTaskHandle + #define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#endif + +#ifndef INCLUDE_xQueueGetMutexHolder + #define INCLUDE_xQueueGetMutexHolder 0 +#endif + +#ifndef INCLUDE_xSemaphoreGetMutexHolder + #define INCLUDE_xSemaphoreGetMutexHolder INCLUDE_xQueueGetMutexHolder +#endif + +#ifndef INCLUDE_pcTaskGetTaskName +#if ( configENABLE_MEMORY_DEBUG == 1) + #define INCLUDE_pcTaskGetTaskName 1 +#else + #define INCLUDE_pcTaskGetTaskName 0 +#endif +#endif + +#ifndef configUSE_APPLICATION_TASK_TAG + #define configUSE_APPLICATION_TASK_TAG 0 +#endif + +#ifndef INCLUDE_uxTaskGetStackHighWaterMark + #define INCLUDE_uxTaskGetStackHighWaterMark 0 +#endif + +#ifndef INCLUDE_eTaskGetState + #define INCLUDE_eTaskGetState 0 +#endif + +#ifndef configUSE_RECURSIVE_MUTEXES + #define configUSE_RECURSIVE_MUTEXES 0 +#endif + +#ifndef configUSE_MUTEXES + #define configUSE_MUTEXES 0 +#endif + +#ifndef configUSE_TIMERS + #define configUSE_TIMERS 0 +#endif + +#ifndef configUSE_COUNTING_SEMAPHORES + #define configUSE_COUNTING_SEMAPHORES 0 +#endif + +#ifndef configUSE_ALTERNATIVE_API + #define configUSE_ALTERNATIVE_API 0 +#endif + +#ifndef portCRITICAL_NESTING_IN_TCB + #define portCRITICAL_NESTING_IN_TCB 0 +#endif + +#ifndef configMAX_TASK_NAME_LEN + #define configMAX_TASK_NAME_LEN 16 +#endif + +#ifndef configIDLE_SHOULD_YIELD + #define configIDLE_SHOULD_YIELD 1 +#endif + +#if configMAX_TASK_NAME_LEN < 1 + #error configMAX_TASK_NAME_LEN must be set to a minimum of 1 in FreeRTOSConfig.h +#endif + +#ifndef INCLUDE_xTaskResumeFromISR + #define INCLUDE_xTaskResumeFromISR 1 +#endif + +#ifndef INCLUDE_xEventGroupSetBitFromISR + #define INCLUDE_xEventGroupSetBitFromISR 0 +#endif + +#ifndef INCLUDE_xTimerPendFunctionCall + #define INCLUDE_xTimerPendFunctionCall 0 +#endif + +#ifndef configASSERT + #define configASSERT( x ) + #define configASSERT_DEFINED 0 +#else + #define configASSERT_DEFINED 1 +#endif + +/* The timers module relies on xTaskGetSchedulerState(). */ +#if configUSE_TIMERS == 1 + + #ifndef configTIMER_TASK_PRIORITY + #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_PRIORITY must also be defined. + #endif /* configTIMER_TASK_PRIORITY */ + + #ifndef configTIMER_QUEUE_LENGTH + #error If configUSE_TIMERS is set to 1 then configTIMER_QUEUE_LENGTH must also be defined. + #endif /* configTIMER_QUEUE_LENGTH */ + + #ifndef configTIMER_TASK_STACK_DEPTH + #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_STACK_DEPTH must also be defined. + #endif /* configTIMER_TASK_STACK_DEPTH */ + +#endif /* configUSE_TIMERS */ + +#ifndef INCLUDE_xTaskGetSchedulerState + #define INCLUDE_xTaskGetSchedulerState 0 +#endif + +#ifndef INCLUDE_xTaskGetCurrentTaskHandle + #define INCLUDE_xTaskGetCurrentTaskHandle 0 +#endif + + +#ifndef portSET_INTERRUPT_MASK_FROM_ISR + #define portSET_INTERRUPT_MASK_FROM_ISR() 0 +#endif + +#ifndef portCLEAR_INTERRUPT_MASK_FROM_ISR + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue +#endif + +#ifndef portCLEAN_UP_TCB + #define portCLEAN_UP_TCB( pxTCB ) ( void ) pxTCB +#endif + +#ifndef portPRE_TASK_DELETE_HOOK + #define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxYieldPending ) +#endif + +#ifndef portSETUP_TCB + #define portSETUP_TCB( pxTCB ) ( void ) pxTCB +#endif + +#ifndef configQUEUE_REGISTRY_SIZE + #define configQUEUE_REGISTRY_SIZE 0U +#endif + +#if ( configQUEUE_REGISTRY_SIZE < 1 ) + #define vQueueAddToRegistry( xQueue, pcName ) + #define vQueueUnregisterQueue( xQueue ) +#endif + +#ifndef portPOINTER_SIZE_TYPE + #define portPOINTER_SIZE_TYPE uint32_t +#endif + +/* Remove any unused trace macros. */ +#ifndef traceSTART + /* Used to perform any necessary initialisation - for example, open a file + into which trace is to be written. */ + #define traceSTART() +#endif + +#ifndef traceEND + /* Use to close a trace, for example close a file into which trace has been + written. */ + #define traceEND() +#endif + +#ifndef traceTASK_SWITCHED_IN + /* Called after a task has been selected to run. pxCurrentTCB holds a pointer + to the task control block of the selected task. */ + #define traceTASK_SWITCHED_IN() +#endif + +#ifndef traceINCREASE_TICK_COUNT + /* Called before stepping the tick count after waking from tickless idle + sleep. */ + #define traceINCREASE_TICK_COUNT( x ) +#endif + +#ifndef traceLOW_POWER_IDLE_BEGIN + /* Called immediately before entering tickless idle. */ + #define traceLOW_POWER_IDLE_BEGIN() +#endif + +#ifndef traceLOW_POWER_IDLE_END + /* Called when returning to the Idle task after a tickless idle. */ + #define traceLOW_POWER_IDLE_END() +#endif + +#ifndef traceTASK_SWITCHED_OUT + /* Called before a task has been selected to run. pxCurrentTCB holds a pointer + to the task control block of the task being switched out. */ + #define traceTASK_SWITCHED_OUT() +#endif + +#ifndef traceTASK_PRIORITY_INHERIT + /* Called when a task attempts to take a mutex that is already held by a + lower priority task. pxTCBOfMutexHolder is a pointer to the TCB of the task + that holds the mutex. uxInheritedPriority is the priority the mutex holder + will inherit (the priority of the task that is attempting to obtain the + muted. */ + #define traceTASK_PRIORITY_INHERIT( pxTCBOfMutexHolder, uxInheritedPriority ) +#endif + +#ifndef traceTASK_PRIORITY_DISINHERIT + /* Called when a task releases a mutex, the holding of which had resulted in + the task inheriting the priority of a higher priority task. + pxTCBOfMutexHolder is a pointer to the TCB of the task that is releasing the + mutex. uxOriginalPriority is the task's configured (base) priority. */ + #define traceTASK_PRIORITY_DISINHERIT( pxTCBOfMutexHolder, uxOriginalPriority ) +#endif + +#ifndef traceBLOCKING_ON_QUEUE_RECEIVE + /* Task is about to block because it cannot read from a + queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore + upon which the read was attempted. pxCurrentTCB points to the TCB of the + task that attempted the read. */ + #define traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ) +#endif + +#ifndef traceBLOCKING_ON_QUEUE_SEND + /* Task is about to block because it cannot write to a + queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore + upon which the write was attempted. pxCurrentTCB points to the TCB of the + task that attempted the write. */ + #define traceBLOCKING_ON_QUEUE_SEND( pxQueue ) +#endif + +#ifndef configCHECK_FOR_STACK_OVERFLOW + #define configCHECK_FOR_STACK_OVERFLOW 0 +#endif + +/* The following event macros are embedded in the kernel API calls. */ + +#ifndef traceMOVED_TASK_TO_READY_STATE + #define traceMOVED_TASK_TO_READY_STATE( pxTCB ) +#endif + +#ifndef traceQUEUE_CREATE + #define traceQUEUE_CREATE( pxNewQueue ) +#endif + +#ifndef traceQUEUE_CREATE_FAILED + #define traceQUEUE_CREATE_FAILED( ucQueueType ) +#endif + +#ifndef traceCREATE_MUTEX + #define traceCREATE_MUTEX( pxNewQueue ) +#endif + +#ifndef traceCREATE_MUTEX_FAILED + #define traceCREATE_MUTEX_FAILED() +#endif + +#ifndef traceGIVE_MUTEX_RECURSIVE + #define traceGIVE_MUTEX_RECURSIVE( pxMutex ) +#endif + +#ifndef traceGIVE_MUTEX_RECURSIVE_FAILED + #define traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex ) +#endif + +#ifndef traceTAKE_MUTEX_RECURSIVE + #define traceTAKE_MUTEX_RECURSIVE( pxMutex ) +#endif + +#ifndef traceTAKE_MUTEX_RECURSIVE_FAILED + #define traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex ) +#endif + +#ifndef traceCREATE_COUNTING_SEMAPHORE + #define traceCREATE_COUNTING_SEMAPHORE() +#endif + +#ifndef traceCREATE_COUNTING_SEMAPHORE_FAILED + #define traceCREATE_COUNTING_SEMAPHORE_FAILED() +#endif + +#ifndef traceQUEUE_SEND + #define traceQUEUE_SEND( pxQueue ) +#endif + +#ifndef traceQUEUE_SEND_FAILED + #define traceQUEUE_SEND_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE + #define traceQUEUE_RECEIVE( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK + #define traceQUEUE_PEEK( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK_FROM_ISR + #define traceQUEUE_PEEK_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE_FAILED + #define traceQUEUE_RECEIVE_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_SEND_FROM_ISR + #define traceQUEUE_SEND_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_SEND_FROM_ISR_FAILED + #define traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE_FROM_ISR + #define traceQUEUE_RECEIVE_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE_FROM_ISR_FAILED + #define traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK_FROM_ISR_FAILED + #define traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_DELETE + #define traceQUEUE_DELETE( pxQueue ) +#endif + +#ifndef traceTASK_CREATE + #define traceTASK_CREATE( pxNewTCB ) +#endif + +#ifndef traceTASK_CREATE_FAILED + #define traceTASK_CREATE_FAILED() +#endif + +#ifndef traceTASK_DELETE + #define traceTASK_DELETE( pxTaskToDelete ) +#endif + +#ifndef traceTASK_DELAY_UNTIL + #define traceTASK_DELAY_UNTIL() +#endif + +#ifndef traceTASK_DELAY + #define traceTASK_DELAY() +#endif + +#ifndef traceTASK_PRIORITY_SET + #define traceTASK_PRIORITY_SET( pxTask, uxNewPriority ) +#endif + +#ifndef traceTASK_SUSPEND + #define traceTASK_SUSPEND( pxTaskToSuspend ) +#endif + +#ifndef traceTASK_RESUME + #define traceTASK_RESUME( pxTaskToResume ) +#endif + +#ifndef traceTASK_RESUME_FROM_ISR + #define traceTASK_RESUME_FROM_ISR( pxTaskToResume ) +#endif + +#ifndef traceTASK_INCREMENT_TICK + #define traceTASK_INCREMENT_TICK( xTickCount ) +#endif + +#ifndef traceTIMER_CREATE + #define traceTIMER_CREATE( pxNewTimer ) +#endif + +#ifndef traceTIMER_CREATE_FAILED + #define traceTIMER_CREATE_FAILED() +#endif + +#ifndef traceTIMER_COMMAND_SEND + #define traceTIMER_COMMAND_SEND( xTimer, xMessageID, xMessageValueValue, xReturn ) +#endif + +#ifndef traceTIMER_EXPIRED + #define traceTIMER_EXPIRED( pxTimer ) +#endif + +#ifndef traceTIMER_COMMAND_RECEIVED + #define traceTIMER_COMMAND_RECEIVED( pxTimer, xMessageID, xMessageValue ) +#endif + +#ifndef traceMALLOC + #define traceMALLOC( pvAddress, uiSize ) +#endif + +#ifndef traceFREE + #define traceFREE( pvAddress, uiSize ) +#endif + +#ifndef traceEVENT_GROUP_CREATE + #define traceEVENT_GROUP_CREATE( xEventGroup ) +#endif + +#ifndef traceEVENT_GROUP_CREATE_FAILED + #define traceEVENT_GROUP_CREATE_FAILED() +#endif + +#ifndef traceEVENT_GROUP_SYNC_BLOCK + #define traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor ) +#endif + +#ifndef traceEVENT_GROUP_SYNC_END + #define traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred +#endif + +#ifndef traceEVENT_GROUP_WAIT_BITS_BLOCK + #define traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor ) +#endif + +#ifndef traceEVENT_GROUP_WAIT_BITS_END + #define traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred +#endif + +#ifndef traceEVENT_GROUP_CLEAR_BITS + #define traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear ) +#endif + +#ifndef traceEVENT_GROUP_CLEAR_BITS_FROM_ISR + #define traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear ) +#endif + +#ifndef traceEVENT_GROUP_SET_BITS + #define traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet ) +#endif + +#ifndef traceEVENT_GROUP_SET_BITS_FROM_ISR + #define traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet ) +#endif + +#ifndef traceEVENT_GROUP_DELETE + #define traceEVENT_GROUP_DELETE( xEventGroup ) +#endif + +#ifndef tracePEND_FUNC_CALL + #define tracePEND_FUNC_CALL(xFunctionToPend, pvParameter1, ulParameter2, ret) +#endif + +#ifndef tracePEND_FUNC_CALL_FROM_ISR + #define tracePEND_FUNC_CALL_FROM_ISR(xFunctionToPend, pvParameter1, ulParameter2, ret) +#endif + +#ifndef traceQUEUE_REGISTRY_ADD + #define traceQUEUE_REGISTRY_ADD(xQueue, pcQueueName) +#endif + +#ifndef configGENERATE_RUN_TIME_STATS + #define configGENERATE_RUN_TIME_STATS 0 +#endif + +#if ( configGENERATE_RUN_TIME_STATS == 1 ) + + #ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS + #error If configGENERATE_RUN_TIME_STATS is defined then portCONFIGURE_TIMER_FOR_RUN_TIME_STATS must also be defined. portCONFIGURE_TIMER_FOR_RUN_TIME_STATS should call a port layer function to setup a peripheral timer/counter that can then be used as the run time counter time base. + #endif /* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS */ + + #ifndef portGET_RUN_TIME_COUNTER_VALUE + #ifndef portALT_GET_RUN_TIME_COUNTER_VALUE + #error If configGENERATE_RUN_TIME_STATS is defined then either portGET_RUN_TIME_COUNTER_VALUE or portALT_GET_RUN_TIME_COUNTER_VALUE must also be defined. See the examples provided and the FreeRTOS web site for more information. + #endif /* portALT_GET_RUN_TIME_COUNTER_VALUE */ + #endif /* portGET_RUN_TIME_COUNTER_VALUE */ + +#endif /* configGENERATE_RUN_TIME_STATS */ + +#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS + #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() +#endif + +#ifndef configUSE_MALLOC_FAILED_HOOK + #define configUSE_MALLOC_FAILED_HOOK 0 +#endif + +#ifndef portPRIVILEGE_BIT + #define portPRIVILEGE_BIT ( ( UBaseType_t ) 0x00 ) +#endif + +#ifndef portYIELD_WITHIN_API + #define portYIELD_WITHIN_API portYIELD +#endif + +#ifndef pvPortMallocAligned + #define pvPortMallocAligned( x, puxStackBuffer ) ( ( ( puxStackBuffer ) == NULL ) ? ( pvPortMalloc( ( x ) ) ) : ( puxStackBuffer ) ) +#endif + +#ifndef vPortFreeAligned + #define vPortFreeAligned( pvBlockToFree ) vPortFree( pvBlockToFree ) +#endif + +#ifndef portSUPPRESS_TICKS_AND_SLEEP + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) +#endif + +#ifndef configEXPECTED_IDLE_TIME_BEFORE_SLEEP + #define configEXPECTED_IDLE_TIME_BEFORE_SLEEP 2 +#endif + +#if configEXPECTED_IDLE_TIME_BEFORE_SLEEP < 2 + #error configEXPECTED_IDLE_TIME_BEFORE_SLEEP must not be less than 2 +#endif + +#ifndef configUSE_TICKLESS_IDLE + #define configUSE_TICKLESS_IDLE 0 +#endif + +#ifndef configPRE_SLEEP_PROCESSING + #define configPRE_SLEEP_PROCESSING( x ) +#endif + +#ifndef configPOST_SLEEP_PROCESSING + #define configPOST_SLEEP_PROCESSING( x ) +#endif + +#ifndef configUSE_QUEUE_SETS + #define configUSE_QUEUE_SETS 0 +#endif + +#ifndef portTASK_USES_FLOATING_POINT + #define portTASK_USES_FLOATING_POINT() +#endif + +#ifndef configUSE_TIME_SLICING + #define configUSE_TIME_SLICING 1 +#endif + +#ifndef configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS + #define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS 0 +#endif + +#ifndef configUSE_NEWLIB_REENTRANT + #define configUSE_NEWLIB_REENTRANT 0 +#endif + +#ifndef configUSE_STATS_FORMATTING_FUNCTIONS + #define configUSE_STATS_FORMATTING_FUNCTIONS 0 +#endif + +#ifndef portASSERT_IF_INTERRUPT_PRIORITY_INVALID + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() +#endif + +#ifndef configUSE_TRACE_FACILITY + #define configUSE_TRACE_FACILITY 0 +#endif + +#ifndef mtCOVERAGE_TEST_MARKER + #define mtCOVERAGE_TEST_MARKER() +#endif + +#ifndef portASSERT_IF_IN_ISR + #define portASSERT_IF_IN_ISR() +#endif + +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#endif + +#ifndef configAPPLICATION_ALLOCATED_HEAP + #define configAPPLICATION_ALLOCATED_HEAP 0 +#endif + +#ifndef configUSE_TASK_NOTIFICATIONS + #define configUSE_TASK_NOTIFICATIONS 1 +#endif + +#ifndef portTICK_TYPE_IS_ATOMIC + #define portTICK_TYPE_IS_ATOMIC 0 +#endif + +#if( portTICK_TYPE_IS_ATOMIC == 0 ) + /* Either variables of tick type cannot be read atomically, or + portTICK_TYPE_IS_ATOMIC was not set - map the critical sections used when + the tick count is returned to the standard critical section macros. */ + #define portTICK_TYPE_ENTER_CRITICAL(mux) portENTER_CRITICAL(mux) + #define portTICK_TYPE_EXIT_CRITICAL(mux) portEXIT_CRITICAL(mux) + #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR() + #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( ( x ) ) +#else + /* The tick type can be read atomically, so critical sections used when the + tick count is returned can be defined away. */ + #define portTICK_TYPE_ENTER_CRITICAL() + #define portTICK_TYPE_EXIT_CRITICAL() + #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() 0 + #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) ( void ) x +#endif + +/* Definitions to allow backward compatibility with FreeRTOS versions prior to +V8 if desired. */ +#ifndef configENABLE_BACKWARD_COMPATIBILITY + #define configENABLE_BACKWARD_COMPATIBILITY 1 +#endif + +#if configENABLE_BACKWARD_COMPATIBILITY == 1 + #define eTaskStateGet eTaskGetState + #define portTickType TickType_t + #define xTaskHandle TaskHandle_t + #define xQueueHandle QueueHandle_t + #define xSemaphoreHandle SemaphoreHandle_t + #define xQueueSetHandle QueueSetHandle_t + #define xQueueSetMemberHandle QueueSetMemberHandle_t + #define xTimeOutType TimeOut_t + #define xMemoryRegion MemoryRegion_t + #define xTaskParameters TaskParameters_t + #define xTaskStatusType TaskStatus_t + #define xTimerHandle TimerHandle_t + #define xCoRoutineHandle CoRoutineHandle_t + #define pdTASK_HOOK_CODE TaskHookFunction_t + #define portTICK_RATE_MS portTICK_PERIOD_MS + + /* Backward compatibility within the scheduler code only - these definitions + are not really required but are included for completeness. */ + #define tmrTIMER_CALLBACK TimerCallbackFunction_t + #define pdTASK_CODE TaskFunction_t + #define xListItem ListItem_t + #define xList List_t +#endif /* configENABLE_BACKWARD_COMPATIBILITY */ + +#ifndef configESP32_PER_TASK_DATA + #define configESP32_PER_TASK_DATA 1 +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* INC_FREERTOS_H */ + diff --git a/tools/sdk/include/freertos/freertos/FreeRTOSConfig.h b/tools/sdk/include/freertos/freertos/FreeRTOSConfig.h new file mode 100644 index 00000000..d1958e77 --- /dev/null +++ b/tools/sdk/include/freertos/freertos/FreeRTOSConfig.h @@ -0,0 +1,279 @@ +/* + FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include "sdkconfig.h" + + +/* ESP31 and ESP32 are dualcore processors. */ +#ifndef CONFIG_FREERTOS_UNICORE +#define portNUM_PROCESSORS 2 +#else +#define portNUM_PROCESSORS 1 +#endif + +#define XT_USE_THREAD_SAFE_CLIB 0 +#define configASSERT_2 0 +#define portUSING_MPU_WRAPPERS 0 +#define configUSE_MUTEX 1 +#undef XT_USE_SWPRI + +#if CONFIG_FREERTOS_CORETIMER_0 +#define XT_TIMER_INDEX 0 +#elif CONFIG_FREERTOS_CORETIMER_1 +#define XT_TIMER_INDEX 1 +#elif CONFIG_FREERTOS_CORETIMER_2 +#define XT_TIMER_INDEX 2 +#elif CONFIG_FREERTOS_CORETIMER_3 +#define XT_TIMER_INDEX 3 +#endif + +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS +#define configTHREAD_LOCAL_STORAGE_DELETE_CALLBACKS 1 + +/* TODO: config freq by menuconfig */ +#define XT_CLOCK_FREQ (CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ * 1000000) + +/* Required for configuration-dependent settings */ +#include "xtensa_config.h" + + +/* configASSERT behaviour */ +#ifndef __ASSEMBLER__ +#include "rom/ets_sys.h" + +#if defined(CONFIG_FREERTOS_ASSERT_DISABLE) +#define configASSERT(a) /* assertions disabled */ +#elif defined(CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE) +#define configASSERT(a) if (!(a)) { \ + ets_printf("%s:%d (%s)- assert failed!\n", __FILE__, __LINE__, \ + __FUNCTION__); \ + } +#else /* CONFIG_FREERTOS_ASSERT_FAIL_ABORT */ +#define configASSERT(a) if (!(a)) { \ + ets_printf("%s:%d (%s)- assert failed!\n", __FILE__, __LINE__, \ + __FUNCTION__); \ + abort(); \ + } +#endif + +#if CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION +#include +#include "rom/ets_sys.h" +#define UNTESTED_FUNCTION() { ets_printf("Untested FreeRTOS function %s\r\n", __FUNCTION__); configASSERT(false); } while(0) +#else +#define UNTESTED_FUNCTION() +#endif + + +#endif /* def __ASSEMBLER__ */ + + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * Note that the default heap size is deliberately kept small so that + * the build is more likely to succeed for configurations with limited + * memory. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 + +#define configUSE_TICK_HOOK 0 + +#define configTICK_RATE_HZ ( CONFIG_FREERTOS_HZ ) + +/* Default clock rate for simulator */ +//#define configCPU_CLOCK_HZ 80000000 + +/* This has impact on speed of search for highest priority */ +#ifdef SMALL_TEST +#define configMAX_PRIORITIES ( 7 ) +#else +#define configMAX_PRIORITIES ( 25 ) +#endif + +/* Minimal stack size. This may need to be increased for your application */ +/* NOTE: The FreeRTOS demos may not work reliably with stack size < 4KB. */ +/* The Xtensa-specific examples should be fine with XT_STACK_MIN_SIZE. */ +#if !(defined XT_STACK_MIN_SIZE) +#error XT_STACK_MIN_SIZE not defined, did you include xtensa_config.h ? +#endif + +#define configMINIMAL_STACK_SIZE (XT_STACK_MIN_SIZE > 1024 ? XT_STACK_MIN_SIZE : 1024) + +/* The Xtensa port uses a separate interrupt stack. Adjust the stack size */ +/* to suit the needs of your specific application. */ +#ifndef configISR_STACK_SIZE +#define configISR_STACK_SIZE 1024//2048 +#endif + +/* Minimal heap size to make sure examples can run on memory limited + configs. Adjust this to suit your system. */ + + +//We define the heap to span all of the non-statically-allocated shared RAM. ToDo: Make sure there +//is some space left for the app and main cpu when running outside of a thread. +#define configAPPLICATION_ALLOCATED_HEAP 1 +#define configTOTAL_HEAP_SIZE (&_heap_end - &_heap_start)//( ( size_t ) (64 * 1024) ) + +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 0 /* Used by vTaskList in main.c */ +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 /* Used by vTaskList in main.c */ +#define configUSE_TRACE_FACILITY_2 0 /* Provided by Xtensa port patch */ +#define configBENCHMARK 0 /* Provided by Xtensa port patch */ +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configQUEUE_REGISTRY_SIZE 0 + +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 + +#if CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE +#define configCHECK_FOR_STACK_OVERFLOW 0 +#elif CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL +#define configCHECK_FOR_STACK_OVERFLOW 1 +#elif CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY +#define configCHECK_FOR_STACK_OVERFLOW 2 +#endif + + + + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero + to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 + +#if CONFIG_ENABLE_MEMORY_DEBUG +#define configENABLE_MEMORY_DEBUG 1 +#else +#define configENABLE_MEMORY_DEBUG 0 +#endif + +#define INCLUDE_xSemaphoreGetMutexHolder 1 + +/* The priority at which the tick interrupt runs. This should probably be + kept at 1. */ +#define configKERNEL_INTERRUPT_PRIORITY 1 + +/* The maximum interrupt priority from which FreeRTOS.org API functions can + be called. Only API functions that end in ...FromISR() can be used within + interrupts. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY XCHAL_EXCM_LEVEL + +#define configUSE_NEWLIB_REENTRANT 1 + +/* Test FreeRTOS timers (with timer task) and more. */ +/* Some files don't compile if this flag is disabled */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY 1 +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_eTaskGetState 1 +#define configUSE_QUEUE_SETS 1 + +#if (!defined XT_INTEXC_HOOKS) +#define configXT_INTEXC_HOOKS 1 /* Exception hooks used by certain tests */ +#if configUSE_TRACE_FACILITY_2 +#define configASSERT_2 1 /* Specific to Xtensa port */ +#endif +#endif + +#define configXT_BOARD 1 /* Board mode */ +#define configXT_SIMULATOR 0 + + + + +#endif /* FREERTOS_CONFIG_H */ + diff --git a/tools/sdk/include/freertos/freertos/StackMacros.h b/tools/sdk/include/freertos/freertos/StackMacros.h new file mode 100644 index 00000000..50d2e198 --- /dev/null +++ b/tools/sdk/include/freertos/freertos/StackMacros.h @@ -0,0 +1,184 @@ +/* + FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef STACK_MACROS_H +#define STACK_MACROS_H + +/* + * Call the stack overflow hook function if the stack of the task being swapped + * out is currently overflowed, or looks like it might have overflowed in the + * past. + * + * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check + * the current stack state only - comparing the current top of stack value to + * the stack limit. Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1 + * will also cause the last few stack bytes to be checked to ensure the value + * to which the bytes were set when the task was created have not been + * overwritten. Note this second test does not guarantee that an overflowed + * stack will always be recognised. + */ + +/*-----------------------------------------------------------*/ + +#if( configCHECK_FOR_STACK_OVERFLOW == 0 ) + + /* FreeRTOSConfig.h is not set to check for stack overflows. */ + #define taskFIRST_CHECK_FOR_STACK_OVERFLOW() + #define taskSECOND_CHECK_FOR_STACK_OVERFLOW() + +#endif /* configCHECK_FOR_STACK_OVERFLOW == 0 */ +/*-----------------------------------------------------------*/ + +#if( configCHECK_FOR_STACK_OVERFLOW == 1 ) + + /* FreeRTOSConfig.h is only set to use the first method of + overflow checking. */ + #define taskSECOND_CHECK_FOR_STACK_OVERFLOW() + +#endif +/*-----------------------------------------------------------*/ + +#if( ( configCHECK_FOR_STACK_OVERFLOW > 0 ) && ( portSTACK_GROWTH < 0 ) ) + + /* Only the current stack state is to be checked. */ + #define taskFIRST_CHECK_FOR_STACK_OVERFLOW() \ + { \ + /* Is the currently saved stack pointer within the stack limit? */ \ + if( pxCurrentTCB[ xPortGetCoreID() ]->pxTopOfStack <= pxCurrentTCB[ xPortGetCoreID() ]->pxStack ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB[ xPortGetCoreID() ], pxCurrentTCB[ xPortGetCoreID() ]->pcTaskName ); \ + } \ + } + +#endif /* configCHECK_FOR_STACK_OVERFLOW > 0 */ +/*-----------------------------------------------------------*/ + +#if( ( configCHECK_FOR_STACK_OVERFLOW > 0 ) && ( portSTACK_GROWTH > 0 ) ) + + /* Only the current stack state is to be checked. */ + #define taskFIRST_CHECK_FOR_STACK_OVERFLOW() \ + { \ + \ + /* Is the currently saved stack pointer within the stack limit? */ \ + if( pxCurrentTCB[ xPortGetCoreID() ]->pxTopOfStack >= pxCurrentTCB[ xPortGetCoreID() ]->pxEndOfStack ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB[ xPortGetCoreID() ], pxCurrentTCB[ xPortGetCoreID() ]->pcTaskName ); \ + } \ + } + +#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */ +/*-----------------------------------------------------------*/ + +#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) ) + + #define taskSECOND_CHECK_FOR_STACK_OVERFLOW() \ + { \ + static const uint8_t ucExpectedStackBytes[] = { tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE }; \ + \ + \ + /* Has the extremity of the task stack ever been written over? */ \ + if( memcmp( ( void * ) pxCurrentTCB[ xPortGetCoreID() ]->pxStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB[ xPortGetCoreID() ], pxCurrentTCB[ xPortGetCoreID() ]->pcTaskName ); \ + } \ + } + +#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */ +/*-----------------------------------------------------------*/ + +#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) ) + + #define taskSECOND_CHECK_FOR_STACK_OVERFLOW() \ + { \ + int8_t *pcEndOfStack = ( int8_t * ) pxCurrentTCB[ xPortGetCoreID() ]->pxEndOfStack; \ + static const uint8_t ucExpectedStackBytes[] = { tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE }; \ + \ + \ + pcEndOfStack -= sizeof( ucExpectedStackBytes ); \ + \ + /* Has the extremity of the task stack ever been written over? */ \ + if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB[ xPortGetCoreID() ], pxCurrentTCB[ xPortGetCoreID() ]->pcTaskName ); \ + } \ + } + +#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */ +/*-----------------------------------------------------------*/ + +#endif /* STACK_MACROS_H */ + diff --git a/tools/sdk/include/freertos/freertos/croutine.h b/tools/sdk/include/freertos/freertos/croutine.h new file mode 100644 index 00000000..7dfd4b8c --- /dev/null +++ b/tools/sdk/include/freertos/freertos/croutine.h @@ -0,0 +1,762 @@ +/* + FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef CO_ROUTINE_H +#define CO_ROUTINE_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include croutine.h" +#endif + +#include "list.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Used to hide the implementation of the co-routine control block. The +control block structure however has to be included in the header due to +the macro implementation of the co-routine functionality. */ +typedef void * CoRoutineHandle_t; + +/* Defines the prototype to which co-routine functions must conform. */ +typedef void (*crCOROUTINE_CODE)( CoRoutineHandle_t, UBaseType_t ); + +typedef struct corCoRoutineControlBlock +{ + crCOROUTINE_CODE pxCoRoutineFunction; + ListItem_t xGenericListItem; /*< List item used to place the CRCB in ready and blocked queues. */ + ListItem_t xEventListItem; /*< List item used to place the CRCB in event lists. */ + UBaseType_t uxPriority; /*< The priority of the co-routine in relation to other co-routines. */ + UBaseType_t uxIndex; /*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */ + uint16_t uxState; /*< Used internally by the co-routine implementation. */ +} CRCB_t; /* Co-routine control block. Note must be identical in size down to uxPriority with TCB_t. */ + +/** + * croutine. h + *
+ BaseType_t xCoRoutineCreate(
+                                 crCOROUTINE_CODE pxCoRoutineCode,
+                                 UBaseType_t uxPriority,
+                                 UBaseType_t uxIndex
+                               );
+ * + * Create a new co-routine and add it to the list of co-routines that are + * ready to run. + * + * @param pxCoRoutineCode Pointer to the co-routine function. Co-routine + * functions require special syntax - see the co-routine section of the WEB + * documentation for more information. + * + * @param uxPriority The priority with respect to other co-routines at which + * the co-routine will run. + * + * @param uxIndex Used to distinguish between different co-routines that + * execute the same function. See the example below and the co-routine section + * of the WEB documentation for further information. + * + * @return pdPASS if the co-routine was successfully created and added to a ready + * list, otherwise an error code defined with ProjDefs.h. + * + * Example usage: + 
+ // Co-routine to be created.
+ void vFlashCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ // This may not be necessary for const variables.
+ static const char cLedToFlash[ 2 ] = { 5, 6 };
+ static const TickType_t uxFlashRates[ 2 ] = { 200, 400 };
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+         // This co-routine just delays for a fixed period, then toggles
+         // an LED.  Two co-routines are created using this function, so
+         // the uxIndex parameter is used to tell the co-routine which
+         // LED to flash and how int32_t to delay.  This assumes xQueue has
+         // already been created.
+         vParTestToggleLED( cLedToFlash[ uxIndex ] );
+         crDELAY( xHandle, uxFlashRates[ uxIndex ] );
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }
+
+ // Function that creates two co-routines.
+ void vOtherFunction( void )
+ {
+ uint8_t ucParameterToPass;
+ TaskHandle_t xHandle;
+
+     // Create two co-routines at priority 0.  The first is given index 0
+     // so (from the code above) toggles LED 5 every 200 ticks.  The second
+     // is given index 1 so toggles LED 6 every 400 ticks.
+     for( uxIndex = 0; uxIndex < 2; uxIndex++ )
+     {
+         xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );
+     }
+ }
+
+ * \defgroup xCoRoutineCreate xCoRoutineCreate + * \ingroup Tasks + */ +BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPriority, UBaseType_t uxIndex ); + + +/** + * croutine. h + *
+ void vCoRoutineSchedule( void );
+ * + * Run a co-routine. + * + * vCoRoutineSchedule() executes the highest priority co-routine that is able + * to run. The co-routine will execute until it either blocks, yields or is + * preempted by a task. Co-routines execute cooperatively so one + * co-routine cannot be preempted by another, but can be preempted by a task. + * + * If an application comprises of both tasks and co-routines then + * vCoRoutineSchedule should be called from the idle task (in an idle task + * hook). + * + * Example usage: + 
+ // This idle task hook will schedule a co-routine each time it is called.
+ // The rest of the idle task will execute between co-routine calls.
+ void vApplicationIdleHook( void )
+ {
+	vCoRoutineSchedule();
+ }
+
+ // Alternatively, if you do not require any other part of the idle task to
+ // execute, the idle task hook can call vCoRoutineScheduler() within an
+ // infinite loop.
+ void vApplicationIdleHook( void )
+ {
+    for( ;; )
+    {
+        vCoRoutineSchedule();
+    }
+ }
+
+ * \defgroup vCoRoutineSchedule vCoRoutineSchedule + * \ingroup Tasks + */ +void vCoRoutineSchedule( void ); + +/** + * croutine. h + * 
+ crSTART( CoRoutineHandle_t xHandle );
+ * + * This macro MUST always be called at the start of a co-routine function. + * + * Example usage: + 
+ // Co-routine to be created.
+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static int32_t ulAVariable;
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+          // Co-routine functionality goes here.
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }
+ * \defgroup crSTART crSTART + * \ingroup Tasks + */ +#define crSTART( pxCRCB ) switch( ( ( CRCB_t * )( pxCRCB ) )->uxState ) { case 0: + +/** + * croutine. h + * 
+ crEND();
+ * + * This macro MUST always be called at the end of a co-routine function. + * + * Example usage: + 
+ // Co-routine to be created.
+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static int32_t ulAVariable;
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+          // Co-routine functionality goes here.
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }
+ * \defgroup crSTART crSTART + * \ingroup Tasks + */ +#define crEND() } + +/* + * These macros are intended for internal use by the co-routine implementation + * only. The macros should not be used directly by application writers. + */ +#define crSET_STATE0( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = (__LINE__ * 2); return; case (__LINE__ * 2): +#define crSET_STATE1( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = ((__LINE__ * 2)+1); return; case ((__LINE__ * 2)+1): + +/** + * croutine. h + *
+ crDELAY( CoRoutineHandle_t xHandle, TickType_t xTicksToDelay );
+ * + * Delay a co-routine for a fixed period of time. + * + * crDELAY can only be called from the co-routine function itself - not + * from within a function called by the co-routine function. This is because + * co-routines do not maintain their own stack. + * + * @param xHandle The handle of the co-routine to delay. This is the xHandle + * parameter of the co-routine function. + * + * @param xTickToDelay The number of ticks that the co-routine should delay + * for. The actual amount of time this equates to is defined by + * configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant portTICK_PERIOD_MS + * can be used to convert ticks to milliseconds. + * + * Example usage: + 
+ // Co-routine to be created.
+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ // This may not be necessary for const variables.
+ // We are to delay for 200ms.
+ static const xTickType xDelayTime = 200 / portTICK_PERIOD_MS;
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+        // Delay for 200ms.
+        crDELAY( xHandle, xDelayTime );
+
+        // Do something here.
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }
+ * \defgroup crDELAY crDELAY + * \ingroup Tasks + */ +#define crDELAY( xHandle, xTicksToDelay ) \ + if( ( xTicksToDelay ) > 0 ) \ + { \ + vCoRoutineAddToDelayedList( ( xTicksToDelay ), NULL ); \ + } \ + crSET_STATE0( ( xHandle ) ); + +/** + * 
+ crQUEUE_SEND(
+                  CoRoutineHandle_t xHandle,
+                  QueueHandle_t pxQueue,
+                  void *pvItemToQueue,
+                  TickType_t xTicksToWait,
+                  BaseType_t *pxResult
+             )
+ * + * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine + * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. + * + * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas + * xQueueSend() and xQueueReceive() can only be used from tasks. + * + * crQUEUE_SEND can only be called from the co-routine function itself - not + * from within a function called by the co-routine function. This is because + * co-routines do not maintain their own stack. + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xHandle The handle of the calling co-routine. This is the xHandle + * parameter of the co-routine function. + * + * @param pxQueue The handle of the queue on which the data will be posted. + * The handle is obtained as the return value when the queue is created using + * the xQueueCreate() API function. + * + * @param pvItemToQueue A pointer to the data being posted onto the queue. + * The number of bytes of each queued item is specified when the queue is + * created. This number of bytes is copied from pvItemToQueue into the queue + * itself. + * + * @param xTickToDelay The number of ticks that the co-routine should block + * to wait for space to become available on the queue, should space not be + * available immediately. The actual amount of time this equates to is defined + * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant + * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see example + * below). + * + * @param pxResult The variable pointed to by pxResult will be set to pdPASS if + * data was successfully posted onto the queue, otherwise it will be set to an + * error defined within ProjDefs.h. + * + * Example usage: + 
+ // Co-routine function that blocks for a fixed period then posts a number onto
+ // a queue.
+ static void prvCoRoutineFlashTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static BaseType_t xNumberToPost = 0;
+ static BaseType_t xResult;
+
+    // Co-routines must begin with a call to crSTART().
+    crSTART( xHandle );
+
+    for( ;; )
+    {
+        // This assumes the queue has already been created.
+        crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );
+
+        if( xResult != pdPASS )
+        {
+            // The message was not posted!
+        }
+
+        // Increment the number to be posted onto the queue.
+        xNumberToPost++;
+
+        // Delay for 100 ticks.
+        crDELAY( xHandle, 100 );
+    }
+
+    // Co-routines must end with a call to crEND().
+    crEND();
+ }
+ * \defgroup crQUEUE_SEND crQUEUE_SEND + * \ingroup Tasks + */ +#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult ) \ +{ \ + *( pxResult ) = xQueueCRSend( ( pxQueue) , ( pvItemToQueue) , ( xTicksToWait ) ); \ + if( *( pxResult ) == errQUEUE_BLOCKED ) \ + { \ + crSET_STATE0( ( xHandle ) ); \ + *pxResult = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), 0 ); \ + } \ + if( *pxResult == errQUEUE_YIELD ) \ + { \ + crSET_STATE1( ( xHandle ) ); \ + *pxResult = pdPASS; \ + } \ +} + +/** + * croutine. h + * 
+  crQUEUE_RECEIVE(
+                     CoRoutineHandle_t xHandle,
+                     QueueHandle_t pxQueue,
+                     void *pvBuffer,
+                     TickType_t xTicksToWait,
+                     BaseType_t *pxResult
+                 )
+ * + * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine + * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. + * + * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas + * xQueueSend() and xQueueReceive() can only be used from tasks. + * + * crQUEUE_RECEIVE can only be called from the co-routine function itself - not + * from within a function called by the co-routine function. This is because + * co-routines do not maintain their own stack. + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xHandle The handle of the calling co-routine. This is the xHandle + * parameter of the co-routine function. + * + * @param pxQueue The handle of the queue from which the data will be received. + * The handle is obtained as the return value when the queue is created using + * the xQueueCreate() API function. + * + * @param pvBuffer The buffer into which the received item is to be copied. + * The number of bytes of each queued item is specified when the queue is + * created. This number of bytes is copied into pvBuffer. + * + * @param xTickToDelay The number of ticks that the co-routine should block + * to wait for data to become available from the queue, should data not be + * available immediately. The actual amount of time this equates to is defined + * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant + * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see the + * crQUEUE_SEND example). + * + * @param pxResult The variable pointed to by pxResult will be set to pdPASS if + * data was successfully retrieved from the queue, otherwise it will be set to + * an error code as defined within ProjDefs.h. + * + * Example usage: + 
+ // A co-routine receives the number of an LED to flash from a queue.  It
+ // blocks on the queue until the number is received.
+ static void prvCoRoutineFlashWorkTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static BaseType_t xResult;
+ static UBaseType_t uxLEDToFlash;
+
+    // All co-routines must start with a call to crSTART().
+    crSTART( xHandle );
+
+    for( ;; )
+    {
+        // Wait for data to become available on the queue.
+        crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+
+        if( xResult == pdPASS )
+        {
+            // We received the LED to flash - flash it!
+            vParTestToggleLED( uxLEDToFlash );
+        }
+    }
+
+    crEND();
+ }
+ * \defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE + * \ingroup Tasks + */ +#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult ) \ +{ \ + *( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), ( xTicksToWait ) ); \ + if( *( pxResult ) == errQUEUE_BLOCKED ) \ + { \ + crSET_STATE0( ( xHandle ) ); \ + *( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), 0 ); \ + } \ + if( *( pxResult ) == errQUEUE_YIELD ) \ + { \ + crSET_STATE1( ( xHandle ) ); \ + *( pxResult ) = pdPASS; \ + } \ +} + +/** + * croutine. h + * 
+  crQUEUE_SEND_FROM_ISR(
+                            QueueHandle_t pxQueue,
+                            void *pvItemToQueue,
+                            BaseType_t xCoRoutinePreviouslyWoken
+                       )
+ * + * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the + * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() + * functions used by tasks. + * + * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to + * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and + * xQueueReceiveFromISR() can only be used to pass data between a task and and + * ISR. + * + * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue + * that is being used from within a co-routine. + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto + * the same queue multiple times from a single interrupt. The first call + * should always pass in pdFALSE. Subsequent calls should pass in + * the value returned from the previous call. + * + * @return pdTRUE if a co-routine was woken by posting onto the queue. This is + * used by the ISR to determine if a context switch may be required following + * the ISR. + * + * Example usage: + 
+ // A co-routine that blocks on a queue waiting for characters to be received.
+ static void vReceivingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ char cRxedChar;
+ BaseType_t xResult;
+
+     // All co-routines must start with a call to crSTART().
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+         // Wait for data to become available on the queue.  This assumes the
+         // queue xCommsRxQueue has already been created!
+         crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+
+         // Was a character received?
+         if( xResult == pdPASS )
+         {
+             // Process the character here.
+         }
+     }
+
+     // All co-routines must end with a call to crEND().
+     crEND();
+ }
+
+ // An ISR that uses a queue to send characters received on a serial port to
+ // a co-routine.
+ void vUART_ISR( void )
+ {
+ char cRxedChar;
+ BaseType_t xCRWokenByPost = pdFALSE;
+
+     // We loop around reading characters until there are none left in the UART.
+     while( UART_RX_REG_NOT_EMPTY() )
+     {
+         // Obtain the character from the UART.
+         cRxedChar = UART_RX_REG;
+
+         // Post the character onto a queue.  xCRWokenByPost will be pdFALSE
+         // the first time around the loop.  If the post causes a co-routine
+         // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.
+         // In this manner we can ensure that if more than one co-routine is
+         // blocked on the queue only one is woken by this ISR no matter how
+         // many characters are posted to the queue.
+         xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );
+     }
+ }
+ * \defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR + * \ingroup Tasks + */ +#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) xQueueCRSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( xCoRoutinePreviouslyWoken ) ) + + +/** + * croutine. h + * 
+  crQUEUE_SEND_FROM_ISR(
+                            QueueHandle_t pxQueue,
+                            void *pvBuffer,
+                            BaseType_t * pxCoRoutineWoken
+                       )
+ * + * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the + * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() + * functions used by tasks. + * + * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to + * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and + * xQueueReceiveFromISR() can only be used to pass data between a task and and + * ISR. + * + * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data + * from a queue that is being used from within a co-routine (a co-routine + * posted to the queue). + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvBuffer A pointer to a buffer into which the received item will be + * placed. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from the queue into + * pvBuffer. + * + * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become + * available on the queue. If crQUEUE_RECEIVE_FROM_ISR causes such a + * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise + * *pxCoRoutineWoken will remain unchanged. + * + * @return pdTRUE an item was successfully received from the queue, otherwise + * pdFALSE. + * + * Example usage: + 
+ // A co-routine that posts a character to a queue then blocks for a fixed
+ // period.  The character is incremented each time.
+ static void vSendingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // cChar holds its value while this co-routine is blocked and must therefore
+ // be declared static.
+ static char cCharToTx = 'a';
+ BaseType_t xResult;
+
+     // All co-routines must start with a call to crSTART().
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+         // Send the next character to the queue.
+         crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );
+
+         if( xResult == pdPASS )
+         {
+             // The character was successfully posted to the queue.
+         }
+		 else
+		 {
+			// Could not post the character to the queue.
+		 }
+
+         // Enable the UART Tx interrupt to cause an interrupt in this
+		 // hypothetical UART.  The interrupt will obtain the character
+		 // from the queue and send it.
+		 ENABLE_RX_INTERRUPT();
+
+		 // Increment to the next character then block for a fixed period.
+		 // cCharToTx will maintain its value across the delay as it is
+		 // declared static.
+		 cCharToTx++;
+		 if( cCharToTx > 'x' )
+		 {
+			cCharToTx = 'a';
+		 }
+		 crDELAY( 100 );
+     }
+
+     // All co-routines must end with a call to crEND().
+     crEND();
+ }
+
+ // An ISR that uses a queue to receive characters to send on a UART.
+ void vUART_ISR( void )
+ {
+ char cCharToTx;
+ BaseType_t xCRWokenByPost = pdFALSE;
+
+     while( UART_TX_REG_EMPTY() )
+     {
+         // Are there any characters in the queue waiting to be sent?
+		 // xCRWokenByPost will automatically be set to pdTRUE if a co-routine
+		 // is woken by the post - ensuring that only a single co-routine is
+		 // woken no matter how many times we go around this loop.
+         if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )
+		 {
+			 SEND_CHARACTER( cCharToTx );
+		 }
+     }
+ }
+ * \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR + * \ingroup Tasks + */ +#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) xQueueCRReceiveFromISR( ( pxQueue ), ( pvBuffer ), ( pxCoRoutineWoken ) ) + +/* + * This function is intended for internal use by the co-routine macros only. + * The macro nature of the co-routine implementation requires that the + * prototype appears here. The function should not be used by application + * writers. + * + * Removes the current co-routine from its ready list and places it in the + * appropriate delayed list. + */ +void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, List_t *pxEventList ); + +/* + * This function is intended for internal use by the queue implementation only. + * The function should not be used by application writers. + * + * Removes the highest priority co-routine from the event list and places it in + * the pending ready list. + */ +BaseType_t xCoRoutineRemoveFromEventList( const List_t *pxEventList ); + +#ifdef __cplusplus +} +#endif + +#endif /* CO_ROUTINE_H */ diff --git a/tools/sdk/include/freertos/freertos/deprecated_definitions.h b/tools/sdk/include/freertos/freertos/deprecated_definitions.h new file mode 100644 index 00000000..fb031cdd --- /dev/null +++ b/tools/sdk/include/freertos/freertos/deprecated_definitions.h @@ -0,0 +1,321 @@ +/* + FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef DEPRECATED_DEFINITIONS_H +#define DEPRECATED_DEFINITIONS_H + + +/* Each FreeRTOS port has a unique portmacro.h header file. Originally a +pre-processor definition was used to ensure the pre-processor found the correct +portmacro.h file for the port being used. That scheme was deprecated in favour +of setting the compiler's include path such that it found the correct +portmacro.h file - removing the need for the constant and allowing the +portmacro.h file to be located anywhere in relation to the port being used. The +definitions below remain in the code for backward compatibility only. New +projects should not use them. */ + +#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT + #include "..\..\Source\portable\owatcom\16bitdos\pc\portmacro.h" + typedef void ( __interrupt __far *pxISR )(); +#endif + +#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT + #include "..\..\Source\portable\owatcom\16bitdos\flsh186\portmacro.h" + typedef void ( __interrupt __far *pxISR )(); +#endif + +#ifdef GCC_MEGA_AVR + #include "../portable/GCC/ATMega323/portmacro.h" +#endif + +#ifdef IAR_MEGA_AVR + #include "../portable/IAR/ATMega323/portmacro.h" +#endif + +#ifdef MPLAB_PIC24_PORT + #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h" +#endif + +#ifdef MPLAB_DSPIC_PORT + #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h" +#endif + +#ifdef MPLAB_PIC18F_PORT + #include "../../Source/portable/MPLAB/PIC18F/portmacro.h" +#endif + +#ifdef MPLAB_PIC32MX_PORT + #include "../../Source/portable/MPLAB/PIC32MX/portmacro.h" +#endif + +#ifdef _FEDPICC + #include "libFreeRTOS/Include/portmacro.h" +#endif + +#ifdef SDCC_CYGNAL + #include "../../Source/portable/SDCC/Cygnal/portmacro.h" +#endif + +#ifdef GCC_ARM7 + #include "../../Source/portable/GCC/ARM7_LPC2000/portmacro.h" +#endif + +#ifdef GCC_ARM7_ECLIPSE + #include "portmacro.h" +#endif + +#ifdef ROWLEY_LPC23xx + #include "../../Source/portable/GCC/ARM7_LPC23xx/portmacro.h" +#endif + +#ifdef IAR_MSP430 + #include "..\..\Source\portable\IAR\MSP430\portmacro.h" +#endif + +#ifdef GCC_MSP430 + #include "../../Source/portable/GCC/MSP430F449/portmacro.h" +#endif + +#ifdef ROWLEY_MSP430 + #include "../../Source/portable/Rowley/MSP430F449/portmacro.h" +#endif + +#ifdef ARM7_LPC21xx_KEIL_RVDS + #include "..\..\Source\portable\RVDS\ARM7_LPC21xx\portmacro.h" +#endif + +#ifdef SAM7_GCC + #include "../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h" +#endif + +#ifdef SAM7_IAR + #include "..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h" +#endif + +#ifdef SAM9XE_IAR + #include "..\..\Source\portable\IAR\AtmelSAM9XE\portmacro.h" +#endif + +#ifdef LPC2000_IAR + #include "..\..\Source\portable\IAR\LPC2000\portmacro.h" +#endif + +#ifdef STR71X_IAR + #include "..\..\Source\portable\IAR\STR71x\portmacro.h" +#endif + +#ifdef STR75X_IAR + #include "..\..\Source\portable\IAR\STR75x\portmacro.h" +#endif + +#ifdef STR75X_GCC + #include "..\..\Source\portable\GCC\STR75x\portmacro.h" +#endif + +#ifdef STR91X_IAR + #include "..\..\Source\portable\IAR\STR91x\portmacro.h" +#endif + +#ifdef GCC_H8S + #include "../../Source/portable/GCC/H8S2329/portmacro.h" +#endif + +#ifdef GCC_AT91FR40008 + #include "../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h" +#endif + +#ifdef RVDS_ARMCM3_LM3S102 + #include "../../Source/portable/RVDS/ARM_CM3/portmacro.h" +#endif + +#ifdef GCC_ARMCM3_LM3S102 + #include "../../Source/portable/GCC/ARM_CM3/portmacro.h" +#endif + +#ifdef GCC_ARMCM3 + #include "../../Source/portable/GCC/ARM_CM3/portmacro.h" +#endif + +#ifdef IAR_ARM_CM3 + #include "../../Source/portable/IAR/ARM_CM3/portmacro.h" +#endif + +#ifdef IAR_ARMCM3_LM + #include "../../Source/portable/IAR/ARM_CM3/portmacro.h" +#endif + +#ifdef HCS12_CODE_WARRIOR + #include "../../Source/portable/CodeWarrior/HCS12/portmacro.h" +#endif + +#ifdef MICROBLAZE_GCC + #include "../../Source/portable/GCC/MicroBlaze/portmacro.h" +#endif + +#ifdef TERN_EE + #include "..\..\Source\portable\Paradigm\Tern_EE\small\portmacro.h" +#endif + +#ifdef GCC_HCS12 + #include "../../Source/portable/GCC/HCS12/portmacro.h" +#endif + +#ifdef GCC_MCF5235 + #include "../../Source/portable/GCC/MCF5235/portmacro.h" +#endif + +#ifdef COLDFIRE_V2_GCC + #include "../../../Source/portable/GCC/ColdFire_V2/portmacro.h" +#endif + +#ifdef COLDFIRE_V2_CODEWARRIOR + #include "../../Source/portable/CodeWarrior/ColdFire_V2/portmacro.h" +#endif + +#ifdef GCC_PPC405 + #include "../../Source/portable/GCC/PPC405_Xilinx/portmacro.h" +#endif + +#ifdef GCC_PPC440 + #include "../../Source/portable/GCC/PPC440_Xilinx/portmacro.h" +#endif + +#ifdef _16FX_SOFTUNE + #include "..\..\Source\portable\Softune\MB96340\portmacro.h" +#endif + +#ifdef BCC_INDUSTRIAL_PC_PORT + /* A short file name has to be used in place of the normal + FreeRTOSConfig.h when using the Borland compiler. */ + #include "frconfig.h" + #include "..\portable\BCC\16BitDOS\PC\prtmacro.h" + typedef void ( __interrupt __far *pxISR )(); +#endif + +#ifdef BCC_FLASH_LITE_186_PORT + /* A short file name has to be used in place of the normal + FreeRTOSConfig.h when using the Borland compiler. */ + #include "frconfig.h" + #include "..\portable\BCC\16BitDOS\flsh186\prtmacro.h" + typedef void ( __interrupt __far *pxISR )(); +#endif + +#ifdef __GNUC__ + #ifdef __AVR32_AVR32A__ + #include "portmacro.h" + #endif +#endif + +#ifdef __ICCAVR32__ + #ifdef __CORE__ + #if __CORE__ == __AVR32A__ + #include "portmacro.h" + #endif + #endif +#endif + +#ifdef __91467D + #include "portmacro.h" +#endif + +#ifdef __96340 + #include "portmacro.h" +#endif + + +#ifdef __IAR_V850ES_Fx3__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Jx3__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Jx3_L__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Jx2__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Hx2__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_78K0R_Kx3__ + #include "../../Source/portable/IAR/78K0R/portmacro.h" +#endif + +#ifdef __IAR_78K0R_Kx3L__ + #include "../../Source/portable/IAR/78K0R/portmacro.h" +#endif + +#endif /* DEPRECATED_DEFINITIONS_H */ + diff --git a/tools/sdk/include/freertos/freertos/event_groups.h b/tools/sdk/include/freertos/freertos/event_groups.h new file mode 100644 index 00000000..c7d0156a --- /dev/null +++ b/tools/sdk/include/freertos/freertos/event_groups.h @@ -0,0 +1,730 @@ +/* + FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef EVENT_GROUPS_H +#define EVENT_GROUPS_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h" must appear in source files before "include event_groups.h" +#endif + +#include "timers.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * An event group is a collection of bits to which an application can assign a + * meaning. For example, an application may create an event group to convey + * the status of various CAN bus related events in which bit 0 might mean "A CAN + * message has been received and is ready for processing", bit 1 might mean "The + * application has queued a message that is ready for sending onto the CAN + * network", and bit 2 might mean "It is time to send a SYNC message onto the + * CAN network" etc. A task can then test the bit values to see which events + * are active, and optionally enter the Blocked state to wait for a specified + * bit or a group of specified bits to be active. To continue the CAN bus + * example, a CAN controlling task can enter the Blocked state (and therefore + * not consume any processing time) until either bit 0, bit 1 or bit 2 are + * active, at which time the bit that was actually active would inform the task + * which action it had to take (process a received message, send a message, or + * send a SYNC). + * + * The event groups implementation contains intelligence to avoid race + * conditions that would otherwise occur were an application to use a simple + * variable for the same purpose. This is particularly important with respect + * to when a bit within an event group is to be cleared, and when bits have to + * be set and then tested atomically - as is the case where event groups are + * used to create a synchronisation point between multiple tasks (a + * 'rendezvous'). + * + * \defgroup EventGroup + */ + + + +/** + * event_groups.h + * + * Type by which event groups are referenced. For example, a call to + * xEventGroupCreate() returns an EventGroupHandle_t variable that can then + * be used as a parameter to other event group functions. + * + * \defgroup EventGroupHandle_t EventGroupHandle_t + * \ingroup EventGroup + */ +typedef void * EventGroupHandle_t; + +/* + * The type that holds event bits always matches TickType_t - therefore the + * number of bits it holds is set by configUSE_16_BIT_TICKS (16 bits if set to 1, + * 32 bits if set to 0. + * + * \defgroup EventBits_t EventBits_t + * \ingroup EventGroup + */ +typedef TickType_t EventBits_t; + +/** + * event_groups.h + *
+ EventGroupHandle_t xEventGroupCreate( void );
+
+ * + * Create a new event group. This function cannot be called from an interrupt. + * + * Although event groups are not related to ticks, for internal implementation + * reasons the number of bits available for use in an event group is dependent + * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h. If + * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit + * 0 to bit 7). If configUSE_16_BIT_TICKS is set to 0 then each event group has + * 24 usable bits (bit 0 to bit 23). The EventBits_t type is used to store + * event bits within an event group. + * + * @return If the event group was created then a handle to the event group is + * returned. If there was insufficient FreeRTOS heap available to create the + * event group then NULL is returned. See http://www.freertos.org/a00111.html + * + * Example usage: + 
+	// Declare a variable to hold the created event group.
+	EventGroupHandle_t xCreatedEventGroup;
+
+	// Attempt to create the event group.
+	xCreatedEventGroup = xEventGroupCreate();
+
+	// Was the event group created successfully?
+	if( xCreatedEventGroup == NULL )
+	{
+		// The event group was not created because there was insufficient
+		// FreeRTOS heap available.
+	}
+	else
+	{
+		// The event group was created.
+	}
+
+ * \defgroup xEventGroupCreate xEventGroupCreate + * \ingroup EventGroup + */ +EventGroupHandle_t xEventGroupCreate( void ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + *
+	EventBits_t xEventGroupWaitBits( 	EventGroupHandle_t xEventGroup,
+										const EventBits_t uxBitsToWaitFor,
+										const BaseType_t xClearOnExit,
+										const BaseType_t xWaitForAllBits,
+										const TickType_t xTicksToWait );
+
+ * + * [Potentially] block to wait for one or more bits to be set within a + * previously created event group. + * + * This function cannot be called from an interrupt. + * + * @param xEventGroup The event group in which the bits are being tested. The + * event group must have previously been created using a call to + * xEventGroupCreate(). + * + * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test + * inside the event group. For example, to wait for bit 0 and/or bit 2 set + * uxBitsToWaitFor to 0x05. To wait for bits 0 and/or bit 1 and/or bit 2 set + * uxBitsToWaitFor to 0x07. Etc. + * + * @param xClearOnExit If xClearOnExit is set to pdTRUE then any bits within + * uxBitsToWaitFor that are set within the event group will be cleared before + * xEventGroupWaitBits() returns if the wait condition was met (if the function + * returns for a reason other than a timeout). If xClearOnExit is set to + * pdFALSE then the bits set in the event group are not altered when the call to + * xEventGroupWaitBits() returns. + * + * @param xWaitForAllBits If xWaitForAllBits is set to pdTRUE then + * xEventGroupWaitBits() will return when either all the bits in uxBitsToWaitFor + * are set or the specified block time expires. If xWaitForAllBits is set to + * pdFALSE then xEventGroupWaitBits() will return when any one of the bits set + * in uxBitsToWaitFor is set or the specified block time expires. The block + * time is specified by the xTicksToWait parameter. + * + * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait + * for one/all (depending on the xWaitForAllBits value) of the bits specified by + * uxBitsToWaitFor to become set. + * + * @return The value of the event group at the time either the bits being waited + * for became set, or the block time expired. Test the return value to know + * which bits were set. If xEventGroupWaitBits() returned because its timeout + * expired then not all the bits being waited for will be set. If + * xEventGroupWaitBits() returned because the bits it was waiting for were set + * then the returned value is the event group value before any bits were + * automatically cleared in the case that xClearOnExit parameter was set to + * pdTRUE. + * + * Example usage: + 
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   void aFunction( EventGroupHandle_t xEventGroup )
+   {
+   EventBits_t uxBits;
+   const TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
+
+		// Wait a maximum of 100ms for either bit 0 or bit 4 to be set within
+		// the event group.  Clear the bits before exiting.
+		uxBits = xEventGroupWaitBits(
+					xEventGroup,	// The event group being tested.
+					BIT_0 | BIT_4,	// The bits within the event group to wait for.
+					pdTRUE,			// BIT_0 and BIT_4 should be cleared before returning.
+					pdFALSE,		// Don't wait for both bits, either bit will do.
+					xTicksToWait );	// Wait a maximum of 100ms for either bit to be set.
+
+		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+		{
+			// xEventGroupWaitBits() returned because both bits were set.
+		}
+		else if( ( uxBits & BIT_0 ) != 0 )
+		{
+			// xEventGroupWaitBits() returned because just BIT_0 was set.
+		}
+		else if( ( uxBits & BIT_4 ) != 0 )
+		{
+			// xEventGroupWaitBits() returned because just BIT_4 was set.
+		}
+		else
+		{
+			// xEventGroupWaitBits() returned because xTicksToWait ticks passed
+			// without either BIT_0 or BIT_4 becoming set.
+		}
+   }
+
+ * \defgroup xEventGroupWaitBits xEventGroupWaitBits + * \ingroup EventGroup + */ +EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + *
+	EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear );
+
+ * + * Clear bits within an event group. This function cannot be called from an + * interrupt. + * + * @param xEventGroup The event group in which the bits are to be cleared. + * + * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear + * in the event group. For example, to clear bit 3 only, set uxBitsToClear to + * 0x08. To clear bit 3 and bit 0 set uxBitsToClear to 0x09. + * + * @return The value of the event group before the specified bits were cleared. + * + * Example usage: + 
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   void aFunction( EventGroupHandle_t xEventGroup )
+   {
+   EventBits_t uxBits;
+
+		// Clear bit 0 and bit 4 in xEventGroup.
+		uxBits = xEventGroupClearBits(
+								xEventGroup,	// The event group being updated.
+								BIT_0 | BIT_4 );// The bits being cleared.
+
+		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+		{
+			// Both bit 0 and bit 4 were set before xEventGroupClearBits() was
+			// called.  Both will now be clear (not set).
+		}
+		else if( ( uxBits & BIT_0 ) != 0 )
+		{
+			// Bit 0 was set before xEventGroupClearBits() was called.  It will
+			// now be clear.
+		}
+		else if( ( uxBits & BIT_4 ) != 0 )
+		{
+			// Bit 4 was set before xEventGroupClearBits() was called.  It will
+			// now be clear.
+		}
+		else
+		{
+			// Neither bit 0 nor bit 4 were set in the first place.
+		}
+   }
+
+ * \defgroup xEventGroupClearBits xEventGroupClearBits + * \ingroup EventGroup + */ +EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + *
+	BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+
+ * + * A version of xEventGroupClearBits() that can be called from an interrupt. + * + * Setting bits in an event group is not a deterministic operation because there + * are an unknown number of tasks that may be waiting for the bit or bits being + * set. FreeRTOS does not allow nondeterministic operations to be performed + * while interrupts are disabled, so protects event groups that are accessed + * from tasks by suspending the scheduler rather than disabling interrupts. As + * a result event groups cannot be accessed directly from an interrupt service + * routine. Therefore xEventGroupClearBitsFromISR() sends a message to the + * timer task to have the clear operation performed in the context of the timer + * task. + * + * @param xEventGroup The event group in which the bits are to be cleared. + * + * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear. + * For example, to clear bit 3 only, set uxBitsToClear to 0x08. To clear bit 3 + * and bit 0 set uxBitsToClear to 0x09. + * + * @return If the request to execute the function was posted successfully then + * pdPASS is returned, otherwise pdFALSE is returned. pdFALSE will be returned + * if the timer service queue was full. + * + * Example usage: + 
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   // An event group which it is assumed has already been created by a call to
+   // xEventGroupCreate().
+   EventGroupHandle_t xEventGroup;
+
+   void anInterruptHandler( void )
+   {
+		// Clear bit 0 and bit 4 in xEventGroup.
+		xResult = xEventGroupClearBitsFromISR(
+							xEventGroup,	 // The event group being updated.
+							BIT_0 | BIT_4 ); // The bits being set.
+
+		if( xResult == pdPASS )
+		{
+			// The message was posted successfully.
+		}
+  }
+
+ * \defgroup xEventGroupSetBitsFromISR xEventGroupSetBitsFromISR + * \ingroup EventGroup + */ +#if( configUSE_TRACE_FACILITY == 1 ) + BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ); +#else + #define xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ) xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ) +#endif + +/** + * event_groups.h + *
+	EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+
+ * + * Set bits within an event group. + * This function cannot be called from an interrupt. xEventGroupSetBitsFromISR() + * is a version that can be called from an interrupt. + * + * Setting bits in an event group will automatically unblock tasks that are + * blocked waiting for the bits. + * + * @param xEventGroup The event group in which the bits are to be set. + * + * @param uxBitsToSet A bitwise value that indicates the bit or bits to set. + * For example, to set bit 3 only, set uxBitsToSet to 0x08. To set bit 3 + * and bit 0 set uxBitsToSet to 0x09. + * + * @return The value of the event group at the time the call to + * xEventGroupSetBits() returns. There are two reasons why the returned value + * might have the bits specified by the uxBitsToSet parameter cleared. First, + * if setting a bit results in a task that was waiting for the bit leaving the + * blocked state then it is possible the bit will be cleared automatically + * (see the xClearBitOnExit parameter of xEventGroupWaitBits()). Second, any + * unblocked (or otherwise Ready state) task that has a priority above that of + * the task that called xEventGroupSetBits() will execute and may change the + * event group value before the call to xEventGroupSetBits() returns. + * + * Example usage: + 
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   void aFunction( EventGroupHandle_t xEventGroup )
+   {
+   EventBits_t uxBits;
+
+		// Set bit 0 and bit 4 in xEventGroup.
+		uxBits = xEventGroupSetBits(
+							xEventGroup,	// The event group being updated.
+							BIT_0 | BIT_4 );// The bits being set.
+
+		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+		{
+			// Both bit 0 and bit 4 remained set when the function returned.
+		}
+		else if( ( uxBits & BIT_0 ) != 0 )
+		{
+			// Bit 0 remained set when the function returned, but bit 4 was
+			// cleared.  It might be that bit 4 was cleared automatically as a
+			// task that was waiting for bit 4 was removed from the Blocked
+			// state.
+		}
+		else if( ( uxBits & BIT_4 ) != 0 )
+		{
+			// Bit 4 remained set when the function returned, but bit 0 was
+			// cleared.  It might be that bit 0 was cleared automatically as a
+			// task that was waiting for bit 0 was removed from the Blocked
+			// state.
+		}
+		else
+		{
+			// Neither bit 0 nor bit 4 remained set.  It might be that a task
+			// was waiting for both of the bits to be set, and the bits were
+			// cleared as the task left the Blocked state.
+		}
+   }
+
+ * \defgroup xEventGroupSetBits xEventGroupSetBits + * \ingroup EventGroup + */ +EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + *
+	BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken );
+
+ * + * A version of xEventGroupSetBits() that can be called from an interrupt. + * + * Setting bits in an event group is not a deterministic operation because there + * are an unknown number of tasks that may be waiting for the bit or bits being + * set. FreeRTOS does not allow nondeterministic operations to be performed in + * interrupts or from critical sections. Therefore xEventGroupSetBitFromISR() + * sends a message to the timer task to have the set operation performed in the + * context of the timer task - where a scheduler lock is used in place of a + * critical section. + * + * @param xEventGroup The event group in which the bits are to be set. + * + * @param uxBitsToSet A bitwise value that indicates the bit or bits to set. + * For example, to set bit 3 only, set uxBitsToSet to 0x08. To set bit 3 + * and bit 0 set uxBitsToSet to 0x09. + * + * @param pxHigherPriorityTaskWoken As mentioned above, calling this function + * will result in a message being sent to the timer daemon task. If the + * priority of the timer daemon task is higher than the priority of the + * currently running task (the task the interrupt interrupted) then + * *pxHigherPriorityTaskWoken will be set to pdTRUE by + * xEventGroupSetBitsFromISR(), indicating that a context switch should be + * requested before the interrupt exits. For that reason + * *pxHigherPriorityTaskWoken must be initialised to pdFALSE. See the + * example code below. + * + * @return If the request to execute the function was posted successfully then + * pdPASS is returned, otherwise pdFALSE is returned. pdFALSE will be returned + * if the timer service queue was full. + * + * Example usage: + 
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   // An event group which it is assumed has already been created by a call to
+   // xEventGroupCreate().
+   EventGroupHandle_t xEventGroup;
+
+   void anInterruptHandler( void )
+   {
+   BaseType_t xHigherPriorityTaskWoken, xResult;
+
+		// xHigherPriorityTaskWoken must be initialised to pdFALSE.
+		xHigherPriorityTaskWoken = pdFALSE;
+
+		// Set bit 0 and bit 4 in xEventGroup.
+		xResult = xEventGroupSetBitsFromISR(
+							xEventGroup,	// The event group being updated.
+							BIT_0 | BIT_4   // The bits being set.
+							&xHigherPriorityTaskWoken );
+
+		// Was the message posted successfully?
+		if( xResult == pdPASS )
+		{
+			// If xHigherPriorityTaskWoken is now set to pdTRUE then a context
+			// switch should be requested.  The macro used is port specific and 
+			// will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - 
+			// refer to the documentation page for the port being used.
+			portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+		}
+  }
+
+ * \defgroup xEventGroupSetBitsFromISR xEventGroupSetBitsFromISR + * \ingroup EventGroup + */ +#if( configUSE_TRACE_FACILITY == 1 ) + BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken ); +#else + #define xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken ) xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ) +#endif + +/** + * event_groups.h + *
+	EventBits_t xEventGroupSync(	EventGroupHandle_t xEventGroup,
+									const EventBits_t uxBitsToSet,
+									const EventBits_t uxBitsToWaitFor,
+									TickType_t xTicksToWait );
+
+ * + * Atomically set bits within an event group, then wait for a combination of + * bits to be set within the same event group. This functionality is typically + * used to synchronise multiple tasks, where each task has to wait for the other + * tasks to reach a synchronisation point before proceeding. + * + * This function cannot be used from an interrupt. + * + * The function will return before its block time expires if the bits specified + * by the uxBitsToWait parameter are set, or become set within that time. In + * this case all the bits specified by uxBitsToWait will be automatically + * cleared before the function returns. + * + * @param xEventGroup The event group in which the bits are being tested. The + * event group must have previously been created using a call to + * xEventGroupCreate(). + * + * @param uxBitsToSet The bits to set in the event group before determining + * if, and possibly waiting for, all the bits specified by the uxBitsToWait + * parameter are set. + * + * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test + * inside the event group. For example, to wait for bit 0 and bit 2 set + * uxBitsToWaitFor to 0x05. To wait for bits 0 and bit 1 and bit 2 set + * uxBitsToWaitFor to 0x07. Etc. + * + * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait + * for all of the bits specified by uxBitsToWaitFor to become set. + * + * @return The value of the event group at the time either the bits being waited + * for became set, or the block time expired. Test the return value to know + * which bits were set. If xEventGroupSync() returned because its timeout + * expired then not all the bits being waited for will be set. If + * xEventGroupSync() returned because all the bits it was waiting for were + * set then the returned value is the event group value before any bits were + * automatically cleared. + * + * Example usage: + 
+ // Bits used by the three tasks.
+ #define TASK_0_BIT		( 1 << 0 )
+ #define TASK_1_BIT		( 1 << 1 )
+ #define TASK_2_BIT		( 1 << 2 )
+
+ #define ALL_SYNC_BITS ( TASK_0_BIT | TASK_1_BIT | TASK_2_BIT )
+
+ // Use an event group to synchronise three tasks.  It is assumed this event
+ // group has already been created elsewhere.
+ EventGroupHandle_t xEventBits;
+
+ void vTask0( void *pvParameters )
+ {
+ EventBits_t uxReturn;
+ TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
+
+	 for( ;; )
+	 {
+		// Perform task functionality here.
+
+		// Set bit 0 in the event flag to note this task has reached the
+		// sync point.  The other two tasks will set the other two bits defined
+		// by ALL_SYNC_BITS.  All three tasks have reached the synchronisation
+		// point when all the ALL_SYNC_BITS are set.  Wait a maximum of 100ms
+		// for this to happen.
+		uxReturn = xEventGroupSync( xEventBits, TASK_0_BIT, ALL_SYNC_BITS, xTicksToWait );
+
+		if( ( uxReturn & ALL_SYNC_BITS ) == ALL_SYNC_BITS )
+		{
+			// All three tasks reached the synchronisation point before the call
+			// to xEventGroupSync() timed out.
+		}
+	}
+ }
+
+ void vTask1( void *pvParameters )
+ {
+	 for( ;; )
+	 {
+		// Perform task functionality here.
+
+		// Set bit 1 in the event flag to note this task has reached the
+		// synchronisation point.  The other two tasks will set the other two
+		// bits defined by ALL_SYNC_BITS.  All three tasks have reached the
+		// synchronisation point when all the ALL_SYNC_BITS are set.  Wait
+		// indefinitely for this to happen.
+		xEventGroupSync( xEventBits, TASK_1_BIT, ALL_SYNC_BITS, portMAX_DELAY );
+
+		// xEventGroupSync() was called with an indefinite block time, so
+		// this task will only reach here if the syncrhonisation was made by all
+		// three tasks, so there is no need to test the return value.
+	 }
+ }
+
+ void vTask2( void *pvParameters )
+ {
+	 for( ;; )
+	 {
+		// Perform task functionality here.
+
+		// Set bit 2 in the event flag to note this task has reached the
+		// synchronisation point.  The other two tasks will set the other two
+		// bits defined by ALL_SYNC_BITS.  All three tasks have reached the
+		// synchronisation point when all the ALL_SYNC_BITS are set.  Wait
+		// indefinitely for this to happen.
+		xEventGroupSync( xEventBits, TASK_2_BIT, ALL_SYNC_BITS, portMAX_DELAY );
+
+		// xEventGroupSync() was called with an indefinite block time, so
+		// this task will only reach here if the syncrhonisation was made by all
+		// three tasks, so there is no need to test the return value.
+	}
+ }
+
+
+ * \defgroup xEventGroupSync xEventGroupSync + * \ingroup EventGroup + */ +EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + + +/** + * event_groups.h + *
+	EventBits_t xEventGroupGetBits( EventGroupHandle_t xEventGroup );
+
+ * + * Returns the current value of the bits in an event group. This function + * cannot be used from an interrupt. + * + * @param xEventGroup The event group being queried. + * + * @return The event group bits at the time xEventGroupGetBits() was called. + * + * \defgroup xEventGroupGetBits xEventGroupGetBits + * \ingroup EventGroup + */ +#define xEventGroupGetBits( xEventGroup ) xEventGroupClearBits( xEventGroup, 0 ) + +/** + * event_groups.h + *
+	EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup );
+
+ * + * A version of xEventGroupGetBits() that can be called from an ISR. + * + * @param xEventGroup The event group being queried. + * + * @return The event group bits at the time xEventGroupGetBitsFromISR() was called. + * + * \defgroup xEventGroupGetBitsFromISR xEventGroupGetBitsFromISR + * \ingroup EventGroup + */ +EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ); + +/** + * event_groups.h + *
+	void xEventGroupDelete( EventGroupHandle_t xEventGroup );
+
+ * + * Delete an event group that was previously created by a call to + * xEventGroupCreate(). Tasks that are blocked on the event group will be + * unblocked and obtain 0 as the event group's value. + * + * @param xEventGroup The event group being deleted. + */ +void vEventGroupDelete( EventGroupHandle_t xEventGroup ); + +/* For internal use only. */ +void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet ); +void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear ); + +#if (configUSE_TRACE_FACILITY == 1) + UBaseType_t uxEventGroupGetNumber( void* xEventGroup ); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* EVENT_GROUPS_H */ + + diff --git a/tools/sdk/include/freertos/freertos/heap_regions.h b/tools/sdk/include/freertos/freertos/heap_regions.h new file mode 100644 index 00000000..aedea42a --- /dev/null +++ b/tools/sdk/include/freertos/freertos/heap_regions.h @@ -0,0 +1,34 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _HEAP_REGIONS_H +#define _HEAP_REGIONS_H + +#include "freertos/FreeRTOS.h" + + +typedef struct HeapRegionTagged +{ + uint8_t *pucStartAddress; + size_t xSizeInBytes; + BaseType_t xTag; + uint32_t xExecAddr; +} HeapRegionTagged_t; + + +void vPortDefineHeapRegionsTagged( const HeapRegionTagged_t * const pxHeapRegions ); +void *pvPortMallocTagged( size_t xWantedSize, BaseType_t tag ); + + + +#endif \ No newline at end of file diff --git a/tools/sdk/include/freertos/freertos/heap_regions_debug.h b/tools/sdk/include/freertos/freertos/heap_regions_debug.h new file mode 100644 index 00000000..81bf1d6c --- /dev/null +++ b/tools/sdk/include/freertos/freertos/heap_regions_debug.h @@ -0,0 +1,78 @@ +#ifndef _HEAP_REGION_DEBUG_H +#define _HEAP_REGION_DEBUG_H + +#include "FreeRTOS.h" + +#if (configENABLE_MEMORY_DEBUG == 1) + +#define DEBUG_DOG_VALUE 0x1a2b3c4d +#define DEBUG_MAX_INFO_NUM 20 +#define DEBUG_TYPE_MALLOC 1 +#define DEBUG_TYPE_FREE 2 + +typedef struct { + unsigned int dog; + char task[4]; + unsigned int pc; +}block_head_t; + +typedef struct { + unsigned int dog; +}block_tail_t; + +/* Please keep this definition same as BlockLink_t */ +typedef struct _os_block_t { + struct _os_block_t *next; + size_t size; + unsigned int xtag; +}os_block_t; + +typedef struct { + block_head_t head; + os_block_t os_block; +}debug_block_t; + +typedef struct _mem_dbg_info{ + void *addr; + char *task; + uint32_t pc; + uint32_t time; + uint8_t type; +}mem_dbg_info_t; + +typedef struct _mem_dbg_ctl{ + mem_dbg_info_t info[DEBUG_MAX_INFO_NUM]; + uint32_t cnt; +}mem_dbg_ctl_t; + +#define BLOCK_HEAD_LEN sizeof(block_head_t) +#define BLOCK_TAIL_LEN sizeof(block_tail_t) +#define OS_BLOCK(_b) ((os_block_t*)((debug_block_t*)((char*)(_b) + BLOCK_HEAD_LEN))) +#define DEBUG_BLOCK(_b) ((debug_block_t*)((char*)(_b) - BLOCK_HEAD_LEN)) +#define HEAD_DOG(_b) ((_b)->head.dog) +#define TAIL_DOG(_b) (*(unsigned int*)((char*)(_b) + (((_b)->os_block.size & (~g_alloc_bit) ) - BLOCK_TAIL_LEN))) + +#define DOG_ASSERT()\ +{\ + mem_debug_show();\ + abort();\ +} + +extern void mem_check_block(void * data); +extern void mem_init_dog(void *data); +extern void mem_debug_init(size_t size, void *start, void *end, portMUX_TYPE *mutex, unsigned int alloc_bit); +extern void mem_malloc_block(void *data); +extern void mem_free_block(void *data); +extern void mem_check_all(void* pv); + +#else + +#define mem_check_block(...) +#define mem_init_dog(...) + +#define BLOCK_HEAD_LEN 0 +#define BLOCK_TAIL_LEN 0 + +#endif + +#endif diff --git a/tools/sdk/include/freertos/freertos/list.h b/tools/sdk/include/freertos/freertos/list.h new file mode 100644 index 00000000..b63df7f7 --- /dev/null +++ b/tools/sdk/include/freertos/freertos/list.h @@ -0,0 +1,453 @@ +/* + FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* + * This is the list implementation used by the scheduler. While it is tailored + * heavily for the schedulers needs, it is also available for use by + * application code. + * + * list_ts can only store pointers to list_item_ts. Each ListItem_t contains a + * numeric value (xItemValue). Most of the time the lists are sorted in + * descending item value order. + * + * Lists are created already containing one list item. The value of this + * item is the maximum possible that can be stored, it is therefore always at + * the end of the list and acts as a marker. The list member pxHead always + * points to this marker - even though it is at the tail of the list. This + * is because the tail contains a wrap back pointer to the true head of + * the list. + * + * In addition to it's value, each list item contains a pointer to the next + * item in the list (pxNext), a pointer to the list it is in (pxContainer) + * and a pointer to back to the object that contains it. These later two + * pointers are included for efficiency of list manipulation. There is + * effectively a two way link between the object containing the list item and + * the list item itself. + * + * + * \page ListIntroduction List Implementation + * \ingroup FreeRTOSIntro + */ + +#ifndef INC_FREERTOS_H + #error FreeRTOS.h must be included before list.h +#endif + +#ifndef LIST_H +#define LIST_H + +/* + * The list structure members are modified from within interrupts, and therefore + * by rights should be declared volatile. However, they are only modified in a + * functionally atomic way (within critical sections of with the scheduler + * suspended) and are either passed by reference into a function or indexed via + * a volatile variable. Therefore, in all use cases tested so far, the volatile + * qualifier can be omitted in order to provide a moderate performance + * improvement without adversely affecting functional behaviour. The assembly + * instructions generated by the IAR, ARM and GCC compilers when the respective + * compiler's options were set for maximum optimisation has been inspected and + * deemed to be as intended. That said, as compiler technology advances, and + * especially if aggressive cross module optimisation is used (a use case that + * has not been exercised to any great extend) then it is feasible that the + * volatile qualifier will be needed for correct optimisation. It is expected + * that a compiler removing essential code because, without the volatile + * qualifier on the list structure members and with aggressive cross module + * optimisation, the compiler deemed the code unnecessary will result in + * complete and obvious failure of the scheduler. If this is ever experienced + * then the volatile qualifier can be inserted in the relevant places within the + * list structures by simply defining configLIST_VOLATILE to volatile in + * FreeRTOSConfig.h (as per the example at the bottom of this comment block). + * If configLIST_VOLATILE is not defined then the preprocessor directives below + * will simply #define configLIST_VOLATILE away completely. + * + * To use volatile list structure members then add the following line to + * FreeRTOSConfig.h (without the quotes): + * "#define configLIST_VOLATILE volatile" + */ +#ifndef configLIST_VOLATILE + #define configLIST_VOLATILE +#endif /* configSUPPORT_CROSS_MODULE_OPTIMISATION */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Macros that can be used to place known values within the list structures, +then check that the known values do not get corrupted during the execution of +the application. These may catch the list data structures being overwritten in +memory. They will not catch data errors caused by incorrect configuration or +use of FreeRTOS.*/ +#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 ) + /* Define the macros to do nothing. */ + #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE + #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE + #define listFIRST_LIST_INTEGRITY_CHECK_VALUE + #define listSECOND_LIST_INTEGRITY_CHECK_VALUE + #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) + #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) + #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ) + #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ) + #define listTEST_LIST_ITEM_INTEGRITY( pxItem ) + #define listTEST_LIST_INTEGRITY( pxList ) +#else + /* Define macros that add new members into the list structures. */ + #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE TickType_t xListItemIntegrityValue1; + #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE TickType_t xListItemIntegrityValue2; + #define listFIRST_LIST_INTEGRITY_CHECK_VALUE TickType_t xListIntegrityValue1; + #define listSECOND_LIST_INTEGRITY_CHECK_VALUE TickType_t xListIntegrityValue2; + + /* Define macros that set the new structure members to known values. */ + #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) ( pxItem )->xListItemIntegrityValue1 = pdINTEGRITY_CHECK_VALUE + #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) ( pxItem )->xListItemIntegrityValue2 = pdINTEGRITY_CHECK_VALUE + #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ) ( pxList )->xListIntegrityValue1 = pdINTEGRITY_CHECK_VALUE + #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ) ( pxList )->xListIntegrityValue2 = pdINTEGRITY_CHECK_VALUE + + /* Define macros that will assert if one of the structure members does not + contain its expected value. */ + #define listTEST_LIST_ITEM_INTEGRITY( pxItem ) configASSERT( ( ( pxItem )->xListItemIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxItem )->xListItemIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) ) + #define listTEST_LIST_INTEGRITY( pxList ) configASSERT( ( ( pxList )->xListIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxList )->xListIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) ) +#endif /* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES */ + + +/* + * Definition of the only type of object that a list can contain. + */ +struct xLIST_ITEM +{ + listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + configLIST_VOLATILE TickType_t xItemValue; /*< The value being listed. In most cases this is used to sort the list in descending order. */ + struct xLIST_ITEM * configLIST_VOLATILE pxNext; /*< Pointer to the next ListItem_t in the list. */ + struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; /*< Pointer to the previous ListItem_t in the list. */ + void * pvOwner; /*< Pointer to the object (normally a TCB) that contains the list item. There is therefore a two way link between the object containing the list item and the list item itself. */ + void * configLIST_VOLATILE pvContainer; /*< Pointer to the list in which this list item is placed (if any). */ + listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ +}; +typedef struct xLIST_ITEM ListItem_t; /* For some reason lint wants this as two separate definitions. */ + +struct xMINI_LIST_ITEM +{ + listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + configLIST_VOLATILE TickType_t xItemValue; + struct xLIST_ITEM * configLIST_VOLATILE pxNext; + struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; +}; +typedef struct xMINI_LIST_ITEM MiniListItem_t; + +/* + * Definition of the type of queue used by the scheduler. + */ +typedef struct xLIST +{ + listFIRST_LIST_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + configLIST_VOLATILE UBaseType_t uxNumberOfItems; + ListItem_t * configLIST_VOLATILE pxIndex; /*< Used to walk through the list. Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */ + MiniListItem_t xListEnd; /*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */ + listSECOND_LIST_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ +} List_t; + +/* + * Access macro to set the owner of a list item. The owner of a list item + * is the object (usually a TCB) that contains the list item. + * + * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER + * \ingroup LinkedList + */ +#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner ) ( ( pxListItem )->pvOwner = ( void * ) ( pxOwner ) ) + +/* + * Access macro to get the owner of a list item. The owner of a list item + * is the object (usually a TCB) that contains the list item. + * + * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER + * \ingroup LinkedList + */ +#define listGET_LIST_ITEM_OWNER( pxListItem ) ( ( pxListItem )->pvOwner ) + +/* + * Access macro to set the value of the list item. In most cases the value is + * used to sort the list in descending order. + * + * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listSET_LIST_ITEM_VALUE( pxListItem, xValue ) ( ( pxListItem )->xItemValue = ( xValue ) ) + +/* + * Access macro to retrieve the value of the list item. The value can + * represent anything - for example the priority of a task, or the time at + * which a task should be unblocked. + * + * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listGET_LIST_ITEM_VALUE( pxListItem ) ( ( pxListItem )->xItemValue ) + +/* + * Access macro to retrieve the value of the list item at the head of a given + * list. + * + * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxList ) ( ( ( pxList )->xListEnd ).pxNext->xItemValue ) + +/* + * Return the list item at the head of the list. + * + * \page listGET_HEAD_ENTRY listGET_HEAD_ENTRY + * \ingroup LinkedList + */ +#define listGET_HEAD_ENTRY( pxList ) ( ( ( pxList )->xListEnd ).pxNext ) + +/* + * Return the list item at the head of the list. + * + * \page listGET_NEXT listGET_NEXT + * \ingroup LinkedList + */ +#define listGET_NEXT( pxListItem ) ( ( pxListItem )->pxNext ) + +/* + * Return the list item that marks the end of the list + * + * \page listGET_END_MARKER listGET_END_MARKER + * \ingroup LinkedList + */ +#define listGET_END_MARKER( pxList ) ( ( ListItem_t const * ) ( &( ( pxList )->xListEnd ) ) ) + +/* + * Access macro to determine if a list contains any items. The macro will + * only have the value true if the list is empty. + * + * \page listLIST_IS_EMPTY listLIST_IS_EMPTY + * \ingroup LinkedList + */ +#define listLIST_IS_EMPTY( pxList ) ( ( BaseType_t ) ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) ) + +/* + * Access macro to return the number of items in the list. + */ +#define listCURRENT_LIST_LENGTH( pxList ) ( ( pxList )->uxNumberOfItems ) + +/* + * Access function to obtain the owner of the next entry in a list. + * + * The list member pxIndex is used to walk through a list. Calling + * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list + * and returns that entry's pxOwner parameter. Using multiple calls to this + * function it is therefore possible to move through every item contained in + * a list. + * + * The pxOwner parameter of a list item is a pointer to the object that owns + * the list item. In the scheduler this is normally a task control block. + * The pxOwner parameter effectively creates a two way link between the list + * item and its owner. + * + * @param pxTCB pxTCB is set to the address of the owner of the next list item. + * @param pxList The list from which the next item owner is to be returned. + * + * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY + * \ingroup LinkedList + */ +#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList ) \ +{ \ +List_t * const pxConstList = ( pxList ); \ + /* Increment the index to the next item and return the item, ensuring */ \ + /* we don't return the marker used at the end of the list. */ \ + ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \ + if( ( void * ) ( pxConstList )->pxIndex == ( void * ) &( ( pxConstList )->xListEnd ) ) \ + { \ + ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \ + } \ + ( pxTCB ) = ( pxConstList )->pxIndex->pvOwner; \ +} + + +/* + * Access function to obtain the owner of the first entry in a list. Lists + * are normally sorted in ascending item value order. + * + * This function returns the pxOwner member of the first item in the list. + * The pxOwner parameter of a list item is a pointer to the object that owns + * the list item. In the scheduler this is normally a task control block. + * The pxOwner parameter effectively creates a two way link between the list + * item and its owner. + * + * @param pxList The list from which the owner of the head item is to be + * returned. + * + * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY + * \ingroup LinkedList + */ +#define listGET_OWNER_OF_HEAD_ENTRY( pxList ) ( (&( ( pxList )->xListEnd ))->pxNext->pvOwner ) + +/* + * Check to see if a list item is within a list. The list item maintains a + * "container" pointer that points to the list it is in. All this macro does + * is check to see if the container and the list match. + * + * @param pxList The list we want to know if the list item is within. + * @param pxListItem The list item we want to know if is in the list. + * @return pdTRUE if the list item is in the list, otherwise pdFALSE. + */ +#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( BaseType_t ) ( ( pxListItem )->pvContainer == ( void * ) ( pxList ) ) ) + +/* + * Return the list a list item is contained within (referenced from). + * + * @param pxListItem The list item being queried. + * @return A pointer to the List_t object that references the pxListItem + */ +#define listLIST_ITEM_CONTAINER( pxListItem ) ( ( pxListItem )->pvContainer ) + +/* + * This provides a crude means of knowing if a list has been initialised, as + * pxList->xListEnd.xItemValue is set to portMAX_DELAY by the vListInitialise() + * function. + */ +#define listLIST_IS_INITIALISED( pxList ) ( ( pxList )->xListEnd.xItemValue == portMAX_DELAY ) + +/* + * Must be called before a list is used! This initialises all the members + * of the list structure and inserts the xListEnd item into the list as a + * marker to the back of the list. + * + * @param pxList Pointer to the list being initialised. + * + * \page vListInitialise vListInitialise + * \ingroup LinkedList + */ +void vListInitialise( List_t * const pxList ); + +/* + * Must be called before a list item is used. This sets the list container to + * null so the item does not think that it is already contained in a list. + * + * @param pxItem Pointer to the list item being initialised. + * + * \page vListInitialiseItem vListInitialiseItem + * \ingroup LinkedList + */ +void vListInitialiseItem( ListItem_t * const pxItem ); + +/* + * Insert a list item into a list. The item will be inserted into the list in + * a position determined by its item value (descending item value order). + * + * @param pxList The list into which the item is to be inserted. + * + * @param pxNewListItem The item that is to be placed in the list. + * + * \page vListInsert vListInsert + * \ingroup LinkedList + */ +void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ); + +/* + * Insert a list item into a list. The item will be inserted in a position + * such that it will be the last item within the list returned by multiple + * calls to listGET_OWNER_OF_NEXT_ENTRY. + * + * The list member pvIndex is used to walk through a list. Calling + * listGET_OWNER_OF_NEXT_ENTRY increments pvIndex to the next item in the list. + * Placing an item in a list using vListInsertEnd effectively places the item + * in the list position pointed to by pvIndex. This means that every other + * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before + * the pvIndex parameter again points to the item being inserted. + * + * @param pxList The list into which the item is to be inserted. + * + * @param pxNewListItem The list item to be inserted into the list. + * + * \page vListInsertEnd vListInsertEnd + * \ingroup LinkedList + */ +void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ); + +/* + * Remove an item from a list. The list item has a pointer to the list that + * it is in, so only the list item need be passed into the function. + * + * @param uxListRemove The item to be removed. The item will remove itself from + * the list pointed to by it's pxContainer parameter. + * + * @return The number of items that remain in the list after the list item has + * been removed. + * + * \page uxListRemove uxListRemove + * \ingroup LinkedList + */ +UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/tools/sdk/include/freertos/freertos/mpu_wrappers.h b/tools/sdk/include/freertos/freertos/mpu_wrappers.h new file mode 100644 index 00000000..504f6d93 --- /dev/null +++ b/tools/sdk/include/freertos/freertos/mpu_wrappers.h @@ -0,0 +1,157 @@ +/* + FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef MPU_WRAPPERS_H +#define MPU_WRAPPERS_H + +/* This file redefines API functions to be called through a wrapper macro, but +only for ports that are using the MPU. */ +#if portUSING_MPU_WRAPPERS + + /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE will be defined when this file is + included from queue.c or task.c to prevent it from having an effect within + those files. */ + #ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + + #define xTaskGenericCreate MPU_xTaskGenericCreate + #define vTaskAllocateMPURegions MPU_vTaskAllocateMPURegions + #define vTaskDelete MPU_vTaskDelete + #define vTaskDelayUntil MPU_vTaskDelayUntil + #define vTaskDelay MPU_vTaskDelay + #define uxTaskPriorityGet MPU_uxTaskPriorityGet + #define vTaskPrioritySet MPU_vTaskPrioritySet + #define eTaskGetState MPU_eTaskGetState + #define vTaskSuspend MPU_vTaskSuspend + #define vTaskResume MPU_vTaskResume + #define vTaskSuspendAll MPU_vTaskSuspendAll + #define xTaskResumeAll MPU_xTaskResumeAll + #define xTaskGetTickCount MPU_xTaskGetTickCount + #define uxTaskGetNumberOfTasks MPU_uxTaskGetNumberOfTasks + #define vTaskList MPU_vTaskList + #define vTaskGetRunTimeStats MPU_vTaskGetRunTimeStats + #define vTaskSetApplicationTaskTag MPU_vTaskSetApplicationTaskTag + #define xTaskGetApplicationTaskTag MPU_xTaskGetApplicationTaskTag + #define xTaskCallApplicationTaskHook MPU_xTaskCallApplicationTaskHook + #define uxTaskGetStackHighWaterMark MPU_uxTaskGetStackHighWaterMark + #define xTaskGetCurrentTaskHandle MPU_xTaskGetCurrentTaskHandle + #define xTaskGetSchedulerState MPU_xTaskGetSchedulerState + #define xTaskGetIdleTaskHandle MPU_xTaskGetIdleTaskHandle + #define uxTaskGetSystemState MPU_uxTaskGetSystemState + + #define xQueueGenericCreate MPU_xQueueGenericCreate + #define xQueueCreateMutex MPU_xQueueCreateMutex + #define xQueueGiveMutexRecursive MPU_xQueueGiveMutexRecursive + #define xQueueTakeMutexRecursive MPU_xQueueTakeMutexRecursive + #define xQueueCreateCountingSemaphore MPU_xQueueCreateCountingSemaphore + #define xQueueGenericSend MPU_xQueueGenericSend + #define xQueueAltGenericSend MPU_xQueueAltGenericSend + #define xQueueAltGenericReceive MPU_xQueueAltGenericReceive + #define xQueueGenericReceive MPU_xQueueGenericReceive + #define uxQueueMessagesWaiting MPU_uxQueueMessagesWaiting + #define vQueueDelete MPU_vQueueDelete + #define xQueueGenericReset MPU_xQueueGenericReset + #define xQueueCreateSet MPU_xQueueCreateSet + #define xQueueSelectFromSet MPU_xQueueSelectFromSet + #define xQueueAddToSet MPU_xQueueAddToSet + #define xQueueRemoveFromSet MPU_xQueueRemoveFromSet + #define xQueuePeekFromISR MPU_xQueuePeekFromISR + #define xQueueGetMutexHolder MPU_xQueueGetMutexHolder + + #define pvPortMalloc MPU_pvPortMalloc + #define vPortFree MPU_vPortFree + #define xPortGetFreeHeapSize MPU_xPortGetFreeHeapSize + #define vPortInitialiseBlocks MPU_vPortInitialiseBlocks + + #if configQUEUE_REGISTRY_SIZE > 0 + #define vQueueAddToRegistry MPU_vQueueAddToRegistry + #define vQueueUnregisterQueue MPU_vQueueUnregisterQueue + #endif + + /* Remove the privileged function macro. */ + #define PRIVILEGED_FUNCTION + + #else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */ + + /* Ensure API functions go in the privileged execution section. */ + #define PRIVILEGED_FUNCTION __attribute__((section("privileged_functions"))) + #define PRIVILEGED_DATA __attribute__((section("privileged_data"))) + + #endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */ + +#else /* portUSING_MPU_WRAPPERS */ + + #define PRIVILEGED_FUNCTION + #define PRIVILEGED_DATA + #define portUSING_MPU_WRAPPERS 0 + +#endif /* portUSING_MPU_WRAPPERS */ + + +#endif /* MPU_WRAPPERS_H */ + diff --git a/tools/sdk/include/freertos/freertos/panic.h b/tools/sdk/include/freertos/freertos/panic.h new file mode 100644 index 00000000..9e902ed2 --- /dev/null +++ b/tools/sdk/include/freertos/freertos/panic.h @@ -0,0 +1,7 @@ +#ifndef PANIC_H +#define PANIC_H + +void setBreakpointIfJtag(void *fn); + + +#endif \ No newline at end of file diff --git a/tools/sdk/include/freertos/freertos/portable.h b/tools/sdk/include/freertos/freertos/portable.h new file mode 100644 index 00000000..4030ca0c --- /dev/null +++ b/tools/sdk/include/freertos/freertos/portable.h @@ -0,0 +1,203 @@ +/* + FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/*----------------------------------------------------------- + * Portable layer API. Each function must be defined for each port. + *----------------------------------------------------------*/ + +#ifndef PORTABLE_H +#define PORTABLE_H + +/* Each FreeRTOS port has a unique portmacro.h header file. Originally a +pre-processor definition was used to ensure the pre-processor found the correct +portmacro.h file for the port being used. That scheme was deprecated in favour +of setting the compiler's include path such that it found the correct +portmacro.h file - removing the need for the constant and allowing the +portmacro.h file to be located anywhere in relation to the port being used. +Purely for reasons of backward compatibility the old method is still valid, but +to make it clear that new projects should not use it, support for the port +specific constants has been moved into the deprecated_definitions.h header +file. */ +#include "deprecated_definitions.h" + +/* If portENTER_CRITICAL is not defined then including deprecated_definitions.h +did not result in a portmacro.h header file being included - and it should be +included here. In this case the path to the correct portmacro.h header file +must be set in the compiler's include path. */ +#ifndef portENTER_CRITICAL + #include "portmacro.h" +#endif + +#if portBYTE_ALIGNMENT == 8 + #define portBYTE_ALIGNMENT_MASK ( 0x0007U ) +#endif + +#if portBYTE_ALIGNMENT == 4 + #define portBYTE_ALIGNMENT_MASK ( 0x0003 ) +#endif + +#if portBYTE_ALIGNMENT == 2 + #define portBYTE_ALIGNMENT_MASK ( 0x0001 ) +#endif + +#if portBYTE_ALIGNMENT == 1 + #define portBYTE_ALIGNMENT_MASK ( 0x0000 ) +#endif + +#ifndef portBYTE_ALIGNMENT_MASK + #error "Invalid portBYTE_ALIGNMENT definition" +#endif + +#ifndef portNUM_CONFIGURABLE_REGIONS + #define portNUM_CONFIGURABLE_REGIONS 1 +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#include "mpu_wrappers.h" + +/* + * Setup the stack of a new task so it is ready to be placed under the + * scheduler control. The registers have to be placed on the stack in + * the order that the port expects to find them. + * + */ +#if( portUSING_MPU_WRAPPERS == 1 ) + StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION; +#else + StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION; +#endif + +/* Used by heap_5.c. */ +typedef struct HeapRegion +{ + uint8_t *pucStartAddress; + size_t xSizeInBytes; +} HeapRegion_t; + +/* + * Used to define multiple heap regions for use by heap_5.c. This function + * must be called before any calls to pvPortMalloc() - not creating a task, + * queue, semaphore, mutex, software timer, event group, etc. will result in + * pvPortMalloc being called. + * + * pxHeapRegions passes in an array of HeapRegion_t structures - each of which + * defines a region of memory that can be used as the heap. The array is + * terminated by a HeapRegions_t structure that has a size of 0. The region + * with the lowest start address must appear first in the array. + */ +void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ); + + +/* + * Map to the memory management routines required for the port. + */ +void *pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION; +void vPortFree( void *pv ) PRIVILEGED_FUNCTION; +void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION; +size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION; +size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION; + +/* + * Setup the hardware ready for the scheduler to take control. This generally + * sets up a tick interrupt and sets timers for the correct tick frequency. + */ +BaseType_t xPortStartScheduler( void ) PRIVILEGED_FUNCTION; + +/* + * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so + * the hardware is left in its original condition after the scheduler stops + * executing. + */ +void vPortEndScheduler( void ) PRIVILEGED_FUNCTION; + +/* + * The structures and methods of manipulating the MPU are contained within the + * port layer. + * + * Fills the xMPUSettings structure with the memory region information + * contained in xRegions. + */ +#if( portUSING_MPU_WRAPPERS == 1 ) + struct xMEMORY_REGION; + void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint16_t usStackDepth ) PRIVILEGED_FUNCTION; +#endif + +/* Multi-core: get current core ID */ +int xPortGetCoreID( void ); + + +#ifdef __cplusplus +} +#endif + +#endif /* PORTABLE_H */ + diff --git a/tools/sdk/include/freertos/freertos/portbenchmark.h b/tools/sdk/include/freertos/freertos/portbenchmark.h new file mode 100644 index 00000000..4ce41d3d --- /dev/null +++ b/tools/sdk/include/freertos/freertos/portbenchmark.h @@ -0,0 +1,46 @@ +/******************************************************************************* +// Copyright (c) 2003-2015 Cadence Design Systems, Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +-------------------------------------------------------------------------------- +*/ + +/* + * This utility helps benchmarking interrupt latency and context switches. + * In order to enable it, set configBENCHMARK to 1 in FreeRTOSConfig.h. + * You will also need to download the FreeRTOS_trace patch that contains + * portbenchmark.c and the complete version of portbenchmark.h + */ + +#ifndef PORTBENCHMARK_H +#define PORTBENCHMARK_H + +#if configBENCHMARK + #error "You need to download the FreeRTOS_trace patch that overwrites this file" +#endif + +#define portbenchmarkINTERRUPT_DISABLE() +#define portbenchmarkINTERRUPT_RESTORE(newstate) +#define portbenchmarkIntLatency() +#define portbenchmarkIntWait() +#define portbenchmarkReset() +#define portbenchmarkPrint() + +#endif /* PORTBENCHMARK */ diff --git a/tools/sdk/include/freertos/freertos/portmacro.h b/tools/sdk/include/freertos/freertos/portmacro.h new file mode 100644 index 00000000..ab83b0e0 --- /dev/null +++ b/tools/sdk/include/freertos/freertos/portmacro.h @@ -0,0 +1,302 @@ +/* + FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef __ASSEMBLER__ + +#include + +#include +#include +#include +#include /* required for XSHAL_CLIB */ +#include + +//#include "xtensa_context.h" + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ + +#define portCHAR int8_t +#define portFLOAT float +#define portDOUBLE double +#define portLONG int32_t +#define portSHORT int16_t +#define portSTACK_TYPE uint8_t +#define portBASE_TYPE int + +typedef portSTACK_TYPE StackType_t; +typedef portBASE_TYPE BaseType_t; +typedef unsigned portBASE_TYPE UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +// portbenchmark +#include "portbenchmark.h" + +#include "sdkconfig.h" + +#define portFIRST_TASK_HOOK CONFIG_FREERTOS_BREAK_ON_SCHEDULER_START_JTAG + + +typedef struct { + volatile uint32_t mux; +#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG + const char *lastLockedFn; + int lastLockedLine; +#endif +} portMUX_TYPE; + + /* + * Kernel mux values can be: + * 0 - Uninitialized + * (0-portNUM_PROCESSORS)|(recCnt<<8)|0xB33F0000 - taken by core (val), recurse count is (recCnt) + * 0xB33FFFFF - free + * + * The magic number in the top 16 bits is there so we can detect uninitialized and corrupted muxes. + */ + +#define portMUX_MAGIC_VAL 0xB33F0000 +#define portMUX_FREE_VAL 0xB33FFFFF +#define portMUX_MAGIC_MASK 0xFFFF0000 +#define portMUX_MAGIC_SHIFT 16 +#define portMUX_CNT_MASK 0x0000FF00 +#define portMUX_CNT_SHIFT 8 +#define portMUX_VAL_MASK 0x000000FF +#define portMUX_VAL_SHIFT 0 + +//Keep this in sync with the portMUX_TYPE struct definition please. +#ifndef CONFIG_FREERTOS_PORTMUX_DEBUG +#define portMUX_INITIALIZER_UNLOCKED { \ + .mux = portMUX_MAGIC_VAL|portMUX_FREE_VAL \ + } +#else +#define portMUX_INITIALIZER_UNLOCKED { \ + .mux = portMUX_MAGIC_VAL|portMUX_FREE_VAL, \ + .lastLockedFn = "(never locked)", \ + .lastLockedLine = -1 \ + } +#endif + +/* Critical section management. NW-TODO: replace XTOS_SET_INTLEVEL with more efficient version, if any? */ +// These cannot be nested. They should be used with a lot of care and cannot be called from interrupt level. +#define portDISABLE_INTERRUPTS() do { XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL); portbenchmarkINTERRUPT_DISABLE(); } while (0) +#define portENABLE_INTERRUPTS() do { portbenchmarkINTERRUPT_RESTORE(0); XTOS_SET_INTLEVEL(0); } while (0) + +#define portASSERT_IF_IN_ISR() vPortAssertIfInISR() +void vPortAssertIfInISR(); + +#define portCRITICAL_NESTING_IN_TCB 1 + +/* +Modifications to portENTER_CRITICAL: + +The original portENTER_CRITICAL only disabled the ISRs. This is enough for single-CPU operation: by +disabling the interrupts, there is no task switch so no other tasks can meddle in the data, and because +interrupts are disabled, ISRs can't corrupt data structures either. + +For multiprocessing, things get a bit more hairy. First of all, disabling the interrupts doesn't stop +the tasks or ISRs on the other processors meddling with our CPU. For tasks, this is solved by adding +a spinlock to the portENTER_CRITICAL macro. A task running on the other CPU accessing the same data will +spinlock in the portENTER_CRITICAL code until the first CPU is done. + +For ISRs, we now also need muxes: while portENTER_CRITICAL disabling interrupts will stop ISRs on the same +CPU from meddling with the data, it does not stop interrupts on the other cores from interfering with the +data. For this, we also use a spinlock in the routines called by the ISR, but these spinlocks +do not disable the interrupts (because they already are). + +This all assumes that interrupts are either entirely disabled or enabled. Interrupr priority levels +will break this scheme. +*/ +void vPortCPUInitializeMutex(portMUX_TYPE *mux); +#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG +void vPortCPUAcquireMutex(portMUX_TYPE *mux, const char *function, int line); +portBASE_TYPE vPortCPUReleaseMutex(portMUX_TYPE *mux, const char *function, int line); +void vTaskEnterCritical( portMUX_TYPE *mux, const char *function, int line ); +void vTaskExitCritical( portMUX_TYPE *mux, const char *function, int line ); +#define portENTER_CRITICAL(mux) vTaskEnterCritical(mux, __FUNCTION__, __LINE__) +#define portEXIT_CRITICAL(mux) vTaskExitCritical(mux, __FUNCTION__, __LINE__) +#define portENTER_CRITICAL_ISR(mux) vPortCPUAcquireMutex(mux, __FUNCTION__, __LINE__) +#define portEXIT_CRITICAL_ISR(mux) vPortCPUReleaseMutex(mux, __FUNCTION__, __LINE__) +#else +void vTaskExitCritical( portMUX_TYPE *mux ); +void vTaskEnterCritical( portMUX_TYPE *mux ); +void vPortCPUAcquireMutex(portMUX_TYPE *mux); +portBASE_TYPE vPortCPUReleaseMutex(portMUX_TYPE *mux); +#define portENTER_CRITICAL(mux) vTaskEnterCritical(mux) +#define portEXIT_CRITICAL(mux) vTaskExitCritical(mux) +#define portENTER_CRITICAL_ISR(mux) vPortCPUAcquireMutex(mux) +#define portEXIT_CRITICAL_ISR(mux) vPortCPUReleaseMutex(mux) +#endif + + +// Cleaner and preferred solution allows nested interrupts disabling and restoring via local registers or stack. +// They can be called from interrupts too. +//NOT SMP-COMPATIBLE! Use only if all you want is to disable the interrupts locally! +static inline unsigned portENTER_CRITICAL_NESTED() { unsigned state = XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL); portbenchmarkINTERRUPT_DISABLE(); return state; } +#define portEXIT_CRITICAL_NESTED(state) do { portbenchmarkINTERRUPT_RESTORE(state); XTOS_RESTORE_JUST_INTLEVEL(state); } while (0) + +// These FreeRTOS versions are similar to the nested versions above +#define portSET_INTERRUPT_MASK_FROM_ISR() portENTER_CRITICAL_NESTED() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR(state) portEXIT_CRITICAL_NESTED(state) + + +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +#define portNOP() XT_NOP() +/*-----------------------------------------------------------*/ + +/* Fine resolution time */ +#define portGET_RUN_TIME_COUNTER_VALUE() xthal_get_ccount() + +/* Kernel utilities. */ +void vPortYield( void ); +void _frxt_setup_switch( void ); +#define portYIELD() vPortYield() +#define portYIELD_FROM_ISR() _frxt_setup_switch() +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +// When coprocessors are defined, we to maintain a pointer to coprocessors area. +// We currently use a hack: redefine field xMPU_SETTINGS in TCB block as a structure that can hold: +// MPU wrappers, coprocessor area pointer, trace code structure, and more if needed. +// The field is normally used for memory protection. FreeRTOS should create another general purpose field. +typedef struct { + #if XCHAL_CP_NUM > 0 + volatile StackType_t* coproc_area; // Pointer to coprocessor save area; MUST BE FIRST + #endif + + #if portUSING_MPU_WRAPPERS + // Define here mpu_settings, which is port dependent + int mpu_setting; // Just a dummy example here; MPU not ported to Xtensa yet + #endif + + #if configUSE_TRACE_FACILITY_2 + struct { + // Cf. porttraceStamp() + int taskstamp; /* Stamp from inside task to see where we are */ + int taskstampcount; /* A counter usually incremented when we restart the task's loop */ + } porttrace; + #endif +} xMPU_SETTINGS; + +// Main hack to use MPU_wrappers even when no MPU is defined (warning: mpu_setting should not be accessed; otherwise move this above xMPU_SETTINGS) +#if (XCHAL_CP_NUM > 0 || configUSE_TRACE_FACILITY_2) && !portUSING_MPU_WRAPPERS // If MPU wrappers not used, we still need to allocate coproc area + #undef portUSING_MPU_WRAPPERS + #define portUSING_MPU_WRAPPERS 1 // Enable it to allocate coproc area + #define MPU_WRAPPERS_H // Override mpu_wrapper.h to disable unwanted code + #define PRIVILEGED_FUNCTION + #define PRIVILEGED_DATA +#endif + +// porttrace +#if configUSE_TRACE_FACILITY_2 +#include "porttrace.h" +#endif + +// configASSERT_2 if requested +#if configASSERT_2 +#include +void exit(int); +#define configASSERT( x ) if (!(x)) { porttracePrint(-1); printf("\nAssertion failed in %s:%d\n", __FILE__, __LINE__); exit(-1); } +#endif + +#endif // __ASSEMBLER__ + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/tools/sdk/include/freertos/freertos/porttrace.h b/tools/sdk/include/freertos/freertos/porttrace.h new file mode 100644 index 00000000..bf2fb412 --- /dev/null +++ b/tools/sdk/include/freertos/freertos/porttrace.h @@ -0,0 +1,42 @@ +/******************************************************************************* +// Copyright (c) 2003-2015 Cadence Design Systems, Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +-------------------------------------------------------------------------------- + +/* + * This utility helps tracing the entering and exiting from tasks. It maintains a circular buffer + * of tasks in the order they execute, and their execution time. + * In order to enable it, set configUSE_TRACE_FACILITY_2 to 1 in FreeRTOSConfig.h. + * You will also need to download the FreeRTOS_trace patch that contains + * porttrace.c and the complete version of porttrace.h + */ + +#ifndef PORTTRACE_H +#define PORTTRACE_H + +#if configUSE_TRACE_FACILITY_2 + #error "You need to download the FreeRTOS_trace patch that overwrites this file" +#endif + +#define porttracePrint(nelements) +#define porttraceStamp(stamp, count_incr) + +#endif /* PORTTRACE_H */ diff --git a/tools/sdk/include/freertos/freertos/projdefs.h b/tools/sdk/include/freertos/freertos/projdefs.h new file mode 100644 index 00000000..1bd39c58 --- /dev/null +++ b/tools/sdk/include/freertos/freertos/projdefs.h @@ -0,0 +1,109 @@ +/* + FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef PROJDEFS_H +#define PROJDEFS_H + +/* + * Defines the prototype to which task functions must conform. Defined in this + * file to ensure the type is known before portable.h is included. + */ +typedef void (*TaskFunction_t)( void * ); + +/* Converts a time in milliseconds to a time in ticks. */ +#define pdMS_TO_TICKS( xTimeInMs ) ( ( ( TickType_t ) ( xTimeInMs ) * configTICK_RATE_HZ ) / ( TickType_t ) 1000 ) + +#define pdFALSE ( ( BaseType_t ) 0 ) +#define pdTRUE ( ( BaseType_t ) 1 ) + +#define pdPASS ( pdTRUE ) +#define pdFAIL ( pdFALSE ) +#define errQUEUE_EMPTY ( ( BaseType_t ) 0 ) +#define errQUEUE_FULL ( ( BaseType_t ) 0 ) + +/* Error definitions. */ +#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ( -1 ) +#define errQUEUE_BLOCKED ( -4 ) +#define errQUEUE_YIELD ( -5 ) + +/* Macros used for basic data corruption checks. */ +#ifndef configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES + #define configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES 0 +#endif + +#if( configUSE_16_BIT_TICKS == 1 ) + #define pdINTEGRITY_CHECK_VALUE 0x5a5a +#else + #define pdINTEGRITY_CHECK_VALUE 0x5a5a5a5aUL +#endif + +#endif /* PROJDEFS_H */ + + + diff --git a/tools/sdk/include/freertos/freertos/queue.h b/tools/sdk/include/freertos/freertos/queue.h new file mode 100644 index 00000000..2095c59b --- /dev/null +++ b/tools/sdk/include/freertos/freertos/queue.h @@ -0,0 +1,1693 @@ +/* + FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + +#ifndef QUEUE_H +#define QUEUE_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h" must appear in source files before "include queue.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * Type by which queues are referenced. For example, a call to xQueueCreate() + * returns an QueueHandle_t variable that can then be used as a parameter to + * xQueueSend(), xQueueReceive(), etc. + */ +typedef void * QueueHandle_t; + +/** + * Type by which queue sets are referenced. For example, a call to + * xQueueCreateSet() returns an xQueueSet variable that can then be used as a + * parameter to xQueueSelectFromSet(), xQueueAddToSet(), etc. + */ +typedef void * QueueSetHandle_t; + +/** + * Queue sets can contain both queues and semaphores, so the + * QueueSetMemberHandle_t is defined as a type to be used where a parameter or + * return value can be either an QueueHandle_t or an SemaphoreHandle_t. + */ +typedef void * QueueSetMemberHandle_t; + +/* For internal use only. */ +#define queueSEND_TO_BACK ( ( BaseType_t ) 0 ) +#define queueSEND_TO_FRONT ( ( BaseType_t ) 1 ) +#define queueOVERWRITE ( ( BaseType_t ) 2 ) + +/* For internal use only. These definitions *must* match those in queue.c. */ +#define queueQUEUE_TYPE_BASE ( ( uint8_t ) 0U ) +#define queueQUEUE_TYPE_SET ( ( uint8_t ) 0U ) +#define queueQUEUE_TYPE_MUTEX ( ( uint8_t ) 1U ) +#define queueQUEUE_TYPE_COUNTING_SEMAPHORE ( ( uint8_t ) 2U ) +#define queueQUEUE_TYPE_BINARY_SEMAPHORE ( ( uint8_t ) 3U ) +#define queueQUEUE_TYPE_RECURSIVE_MUTEX ( ( uint8_t ) 4U ) + +/** + * queue. h + * 
+ QueueHandle_t xQueueCreate(
+							  UBaseType_t uxQueueLength,
+							  UBaseType_t uxItemSize
+						  );
+ *
+ * + * Creates a new queue instance. This allocates the storage required by the + * new queue and returns a handle for the queue. + * + * @param uxQueueLength The maximum number of items that the queue can contain. + * + * @param uxItemSize The number of bytes each item in the queue will require. + * Items are queued by copy, not by reference, so this is the number of bytes + * that will be copied for each posted item. Each item on the queue must be + * the same size. + * + * @return If the queue is successfully create then a handle to the newly + * created queue is returned. If the queue cannot be created then 0 is + * returned. + * + * Example usage: + 
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ };
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+	if( xQueue1 == 0 )
+	{
+		// Queue was not created and must not be used.
+	}
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+	if( xQueue2 == 0 )
+	{
+		// Queue was not created and must not be used.
+	}
+
+	// ... Rest of task code.
+ }
+
+ * \defgroup xQueueCreate xQueueCreate + * \ingroup QueueManagement + */ +#define xQueueCreate( uxQueueLength, uxItemSize ) xQueueGenericCreate( uxQueueLength, uxItemSize, queueQUEUE_TYPE_BASE ) + +/** + * queue. h + * 
+ BaseType_t xQueueSendToToFront(
+								   QueueHandle_t	xQueue,
+								   const void		*pvItemToQueue,
+								   TickType_t		xTicksToWait
+							   );
+ *
+ * + * This is a macro that calls xQueueGenericSend(). + * + * Post an item to the front of a queue. The item is queued by copy, not by + * reference. This function must not be called from an interrupt service + * routine. See xQueueSendFromISR () for an alternative which may be used + * in an ISR. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for space to become available on the queue, should it already + * be full. The call will return immediately if this is set to 0 and the + * queue is full. The time is defined in tick periods so the constant + * portTICK_PERIOD_MS should be used to convert to real time if this is required. + * + * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. + * + * Example usage: + 
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueSendToFront( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueSendToFront( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+	}
+
+	// ... Rest of task code.
+ }
+
+ * \defgroup xQueueSend xQueueSend + * \ingroup QueueManagement + */ +#define xQueueSendToFront( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT ) + +/** + * queue. h + * 
+ BaseType_t xQueueSendToBack(
+								   QueueHandle_t	xQueue,
+								   const void		*pvItemToQueue,
+								   TickType_t		xTicksToWait
+							   );
+ *
+ * + * This is a macro that calls xQueueGenericSend(). + * + * Post an item to the back of a queue. The item is queued by copy, not by + * reference. This function must not be called from an interrupt service + * routine. See xQueueSendFromISR () for an alternative which may be used + * in an ISR. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for space to become available on the queue, should it already + * be full. The call will return immediately if this is set to 0 and the queue + * is full. The time is defined in tick periods so the constant + * portTICK_PERIOD_MS should be used to convert to real time if this is required. + * + * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. + * + * Example usage: + 
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueSendToBack( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueSendToBack( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+	}
+
+	// ... Rest of task code.
+ }
+
+ * \defgroup xQueueSend xQueueSend + * \ingroup QueueManagement + */ +#define xQueueSendToBack( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK ) + +/** + * queue. h + * 
+ BaseType_t xQueueSend(
+							  QueueHandle_t xQueue,
+							  const void * pvItemToQueue,
+							  TickType_t xTicksToWait
+						 );
+ *
+ * + * This is a macro that calls xQueueGenericSend(). It is included for + * backward compatibility with versions of FreeRTOS.org that did not + * include the xQueueSendToFront() and xQueueSendToBack() macros. It is + * equivalent to xQueueSendToBack(). + * + * Post an item on a queue. The item is queued by copy, not by reference. + * This function must not be called from an interrupt service routine. + * See xQueueSendFromISR () for an alternative which may be used in an ISR. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for space to become available on the queue, should it already + * be full. The call will return immediately if this is set to 0 and the + * queue is full. The time is defined in tick periods so the constant + * portTICK_PERIOD_MS should be used to convert to real time if this is required. + * + * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. + * + * Example usage: + 
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+	}
+
+	// ... Rest of task code.
+ }
+
+ * \defgroup xQueueSend xQueueSend + * \ingroup QueueManagement + */ +#define xQueueSend( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK ) + +/** + * queue. h + * 
+ BaseType_t xQueueOverwrite(
+							  QueueHandle_t xQueue,
+							  const void * pvItemToQueue
+						 );
+ *
+ * + * Only for use with queues that have a length of one - so the queue is either + * empty or full. + * + * Post an item on a queue. If the queue is already full then overwrite the + * value held in the queue. The item is queued by copy, not by reference. + * + * This function must not be called from an interrupt service routine. + * See xQueueOverwriteFromISR () for an alternative which may be used in an ISR. + * + * @param xQueue The handle of the queue to which the data is being sent. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @return xQueueOverwrite() is a macro that calls xQueueGenericSend(), and + * therefore has the same return values as xQueueSendToFront(). However, pdPASS + * is the only value that can be returned because xQueueOverwrite() will write + * to the queue even when the queue is already full. + * + * Example usage: + 
+
+ void vFunction( void *pvParameters )
+ {
+ QueueHandle_t xQueue;
+ uint32_t ulVarToSend, ulValReceived;
+
+	// Create a queue to hold one uint32_t value.  It is strongly
+	// recommended *not* to use xQueueOverwrite() on queues that can
+	// contain more than one value, and doing so will trigger an assertion
+	// if configASSERT() is defined.
+	xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
+
+	// Write the value 10 to the queue using xQueueOverwrite().
+	ulVarToSend = 10;
+	xQueueOverwrite( xQueue, &ulVarToSend );
+
+	// Peeking the queue should now return 10, but leave the value 10 in
+	// the queue.  A block time of zero is used as it is known that the
+	// queue holds a value.
+	ulValReceived = 0;
+	xQueuePeek( xQueue, &ulValReceived, 0 );
+
+	if( ulValReceived != 10 )
+	{
+		// Error unless the item was removed by a different task.
+	}
+
+	// The queue is still full.  Use xQueueOverwrite() to overwrite the
+	// value held in the queue with 100.
+	ulVarToSend = 100;
+	xQueueOverwrite( xQueue, &ulVarToSend );
+
+	// This time read from the queue, leaving the queue empty once more.
+	// A block time of 0 is used again.
+	xQueueReceive( xQueue, &ulValReceived, 0 );
+
+	// The value read should be the last value written, even though the
+	// queue was already full when the value was written.
+	if( ulValReceived != 100 )
+	{
+		// Error!
+	}
+
+	// ...
+}
+
+ * \defgroup xQueueOverwrite xQueueOverwrite + * \ingroup QueueManagement + */ +#define xQueueOverwrite( xQueue, pvItemToQueue ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), 0, queueOVERWRITE ) + + +/** + * queue. h + * 
+ BaseType_t xQueueGenericSend(
+									QueueHandle_t xQueue,
+									const void * pvItemToQueue,
+									TickType_t xTicksToWait
+									BaseType_t xCopyPosition
+								);
+ *
+ * + * It is preferred that the macros xQueueSend(), xQueueSendToFront() and + * xQueueSendToBack() are used in place of calling this function directly. + * + * Post an item on a queue. The item is queued by copy, not by reference. + * This function must not be called from an interrupt service routine. + * See xQueueSendFromISR () for an alternative which may be used in an ISR. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for space to become available on the queue, should it already + * be full. The call will return immediately if this is set to 0 and the + * queue is full. The time is defined in tick periods so the constant + * portTICK_PERIOD_MS should be used to convert to real time if this is required. + * + * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the + * item at the back of the queue, or queueSEND_TO_FRONT to place the item + * at the front of the queue (for high priority messages). + * + * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. + * + * Example usage: + 
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueGenericSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10, queueSEND_TO_BACK ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueGenericSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0, queueSEND_TO_BACK );
+	}
+
+	// ... Rest of task code.
+ }
+
+ * \defgroup xQueueSend xQueueSend + * \ingroup QueueManagement + */ +BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * 
+ BaseType_t xQueuePeek(
+							 QueueHandle_t xQueue,
+							 void *pvBuffer,
+							 TickType_t xTicksToWait
+						 );
+ * + * This is a macro that calls the xQueueGenericReceive() function. + * + * Receive an item from a queue without removing the item from the queue. + * The item is received by copy so a buffer of adequate size must be + * provided. The number of bytes copied into the buffer was defined when + * the queue was created. + * + * Successfully received items remain on the queue so will be returned again + * by the next call, or a call to xQueueReceive(). + * + * This macro must not be used in an interrupt service routine. See + * xQueuePeekFromISR() for an alternative that can be called from an interrupt + * service routine. + * + * @param xQueue The handle to the queue from which the item is to be + * received. + * + * @param pvBuffer Pointer to the buffer into which the received item will + * be copied. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for an item to receive should the queue be empty at the time + * of the call. The time is defined in tick periods so the constant + * portTICK_PERIOD_MS should be used to convert to real time if this is required. + * xQueuePeek() will return immediately if xTicksToWait is 0 and the queue + * is empty. + * + * @return pdTRUE if an item was successfully received from the queue, + * otherwise pdFALSE. + * + * Example usage: + 
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ QueueHandle_t xQueue;
+
+ // Task to create a queue and post a value.
+ void vATask( void *pvParameters )
+ {
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+	if( xQueue == 0 )
+	{
+		// Failed to create the queue.
+	}
+
+	// ...
+
+	// Send a pointer to a struct AMessage object.  Don't block if the
+	// queue is already full.
+	pxMessage = & xMessage;
+	xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
+
+	// ... Rest of task code.
+ }
+
+ // Task to peek the data from the queue.
+ void vADifferentTask( void *pvParameters )
+ {
+ struct AMessage *pxRxedMessage;
+
+	if( xQueue != 0 )
+	{
+		// Peek a message on the created queue.  Block for 10 ticks if a
+		// message is not immediately available.
+		if( xQueuePeek( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
+		{
+			// pcRxedMessage now points to the struct AMessage variable posted
+			// by vATask, but the item still remains on the queue.
+		}
+	}
+
+	// ... Rest of task code.
+ }
+
+ * \defgroup xQueueReceive xQueueReceive + * \ingroup QueueManagement + */ +#define xQueuePeek( xQueue, pvBuffer, xTicksToWait ) xQueueGenericReceive( ( xQueue ), ( pvBuffer ), ( xTicksToWait ), pdTRUE ) + +/** + * queue. h + * 
+ BaseType_t xQueuePeekFromISR(
+									QueueHandle_t xQueue,
+									void *pvBuffer,
+								);
+ * + * A version of xQueuePeek() that can be called from an interrupt service + * routine (ISR). + * + * Receive an item from a queue without removing the item from the queue. + * The item is received by copy so a buffer of adequate size must be + * provided. The number of bytes copied into the buffer was defined when + * the queue was created. + * + * Successfully received items remain on the queue so will be returned again + * by the next call, or a call to xQueueReceive(). + * + * @param xQueue The handle to the queue from which the item is to be + * received. + * + * @param pvBuffer Pointer to the buffer into which the received item will + * be copied. + * + * @return pdTRUE if an item was successfully received from the queue, + * otherwise pdFALSE. + * + * \defgroup xQueuePeekFromISR xQueuePeekFromISR + * \ingroup QueueManagement + */ +BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * 
+ BaseType_t xQueueReceive(
+								 QueueHandle_t xQueue,
+								 void *pvBuffer,
+								 TickType_t xTicksToWait
+							);
+ * + * This is a macro that calls the xQueueGenericReceive() function. + * + * Receive an item from a queue. The item is received by copy so a buffer of + * adequate size must be provided. The number of bytes copied into the buffer + * was defined when the queue was created. + * + * Successfully received items are removed from the queue. + * + * This function must not be used in an interrupt service routine. See + * xQueueReceiveFromISR for an alternative that can. + * + * @param xQueue The handle to the queue from which the item is to be + * received. + * + * @param pvBuffer Pointer to the buffer into which the received item will + * be copied. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for an item to receive should the queue be empty at the time + * of the call. xQueueReceive() will return immediately if xTicksToWait + * is zero and the queue is empty. The time is defined in tick periods so the + * constant portTICK_PERIOD_MS should be used to convert to real time if this is + * required. + * + * @return pdTRUE if an item was successfully received from the queue, + * otherwise pdFALSE. + * + * Example usage: + 
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ QueueHandle_t xQueue;
+
+ // Task to create a queue and post a value.
+ void vATask( void *pvParameters )
+ {
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+	if( xQueue == 0 )
+	{
+		// Failed to create the queue.
+	}
+
+	// ...
+
+	// Send a pointer to a struct AMessage object.  Don't block if the
+	// queue is already full.
+	pxMessage = & xMessage;
+	xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
+
+	// ... Rest of task code.
+ }
+
+ // Task to receive from the queue.
+ void vADifferentTask( void *pvParameters )
+ {
+ struct AMessage *pxRxedMessage;
+
+	if( xQueue != 0 )
+	{
+		// Receive a message on the created queue.  Block for 10 ticks if a
+		// message is not immediately available.
+		if( xQueueReceive( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
+		{
+			// pcRxedMessage now points to the struct AMessage variable posted
+			// by vATask.
+		}
+	}
+
+	// ... Rest of task code.
+ }
+
+ * \defgroup xQueueReceive xQueueReceive + * \ingroup QueueManagement + */ +#define xQueueReceive( xQueue, pvBuffer, xTicksToWait ) xQueueGenericReceive( ( xQueue ), ( pvBuffer ), ( xTicksToWait ), pdFALSE ) + + +/** + * queue. h + * 
+ BaseType_t xQueueGenericReceive(
+									   QueueHandle_t	xQueue,
+									   void	*pvBuffer,
+									   TickType_t	xTicksToWait
+									   BaseType_t	xJustPeek
+									);
+ * + * It is preferred that the macro xQueueReceive() be used rather than calling + * this function directly. + * + * Receive an item from a queue. The item is received by copy so a buffer of + * adequate size must be provided. The number of bytes copied into the buffer + * was defined when the queue was created. + * + * This function must not be used in an interrupt service routine. See + * xQueueReceiveFromISR for an alternative that can. + * + * @param xQueue The handle to the queue from which the item is to be + * received. + * + * @param pvBuffer Pointer to the buffer into which the received item will + * be copied. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for an item to receive should the queue be empty at the time + * of the call. The time is defined in tick periods so the constant + * portTICK_PERIOD_MS should be used to convert to real time if this is required. + * xQueueGenericReceive() will return immediately if the queue is empty and + * xTicksToWait is 0. + * + * @param xJustPeek When set to true, the item received from the queue is not + * actually removed from the queue - meaning a subsequent call to + * xQueueReceive() will return the same item. When set to false, the item + * being received from the queue is also removed from the queue. + * + * @return pdTRUE if an item was successfully received from the queue, + * otherwise pdFALSE. + * + * Example usage: + 
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ QueueHandle_t xQueue;
+
+ // Task to create a queue and post a value.
+ void vATask( void *pvParameters )
+ {
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+	if( xQueue == 0 )
+	{
+		// Failed to create the queue.
+	}
+
+	// ...
+
+	// Send a pointer to a struct AMessage object.  Don't block if the
+	// queue is already full.
+	pxMessage = & xMessage;
+	xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
+
+	// ... Rest of task code.
+ }
+
+ // Task to receive from the queue.
+ void vADifferentTask( void *pvParameters )
+ {
+ struct AMessage *pxRxedMessage;
+
+	if( xQueue != 0 )
+	{
+		// Receive a message on the created queue.  Block for 10 ticks if a
+		// message is not immediately available.
+		if( xQueueGenericReceive( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
+		{
+			// pcRxedMessage now points to the struct AMessage variable posted
+			// by vATask.
+		}
+	}
+
+	// ... Rest of task code.
+ }
+
+ * \defgroup xQueueReceive xQueueReceive + * \ingroup QueueManagement + */ +BaseType_t xQueueGenericReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait, const BaseType_t xJustPeek ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * 
UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue );
+ * + * Return the number of messages stored in a queue. + * + * @param xQueue A handle to the queue being queried. + * + * @return The number of messages available in the queue. + * + * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting + * \ingroup QueueManagement + */ +UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * 
UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue );
+ * + * Return the number of free spaces available in a queue. This is equal to the + * number of items that can be sent to the queue before the queue becomes full + * if no items are removed. + * + * @param xQueue A handle to the queue being queried. + * + * @return The number of spaces available in the queue. + * + * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting + * \ingroup QueueManagement + */ +UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * 
void vQueueDelete( QueueHandle_t xQueue );
+ * + * Delete a queue - freeing all the memory allocated for storing of items + * placed on the queue. + * + * @param xQueue A handle to the queue to be deleted. + * + * \defgroup vQueueDelete vQueueDelete + * \ingroup QueueManagement + */ +void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * 
+ BaseType_t xQueueSendToFrontFromISR(
+										 QueueHandle_t xQueue,
+										 const void *pvItemToQueue,
+										 BaseType_t *pxHigherPriorityTaskWoken
+									  );
+
+ * + * This is a macro that calls xQueueGenericSendFromISR(). + * + * Post an item to the front of a queue. It is safe to use this macro from + * within an interrupt service routine. + * + * Items are queued by copy not reference so it is preferable to only + * queue small items, especially when called from an ISR. In most cases + * it would be preferable to store a pointer to the item being queued. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param pxHigherPriorityTaskWoken xQueueSendToFrontFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xQueueSendToFromFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @return pdTRUE if the data was successfully sent to the queue, otherwise + * errQUEUE_FULL. + * + * Example usage for buffered IO (where the ISR can obtain more than one value + * per call): + 
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPrioritTaskWoken;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWoken = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post the byte.
+		xQueueSendToFrontFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.
+	if( xHigherPriorityTaskWoken )
+	{
+		taskYIELD ();
+	}
+ }
+
+ * + * \defgroup xQueueSendFromISR xQueueSendFromISR + * \ingroup QueueManagement + */ +#define xQueueSendToFrontFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_FRONT ) + + +/** + * queue. h + * 
+ BaseType_t xQueueSendToBackFromISR(
+										 QueueHandle_t xQueue,
+										 const void *pvItemToQueue,
+										 BaseType_t *pxHigherPriorityTaskWoken
+									  );
+
+ * + * This is a macro that calls xQueueGenericSendFromISR(). + * + * Post an item to the back of a queue. It is safe to use this macro from + * within an interrupt service routine. + * + * Items are queued by copy not reference so it is preferable to only + * queue small items, especially when called from an ISR. In most cases + * it would be preferable to store a pointer to the item being queued. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param pxHigherPriorityTaskWoken xQueueSendToBackFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xQueueSendToBackFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @return pdTRUE if the data was successfully sent to the queue, otherwise + * errQUEUE_FULL. + * + * Example usage for buffered IO (where the ISR can obtain more than one value + * per call): + 
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWoken;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWoken = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post the byte.
+		xQueueSendToBackFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.
+	if( xHigherPriorityTaskWoken )
+	{
+		taskYIELD ();
+	}
+ }
+
+ * + * \defgroup xQueueSendFromISR xQueueSendFromISR + * \ingroup QueueManagement + */ +#define xQueueSendToBackFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK ) + +/** + * queue. h + * 
+ BaseType_t xQueueOverwriteFromISR(
+							  QueueHandle_t xQueue,
+							  const void * pvItemToQueue,
+							  BaseType_t *pxHigherPriorityTaskWoken
+						 );
+ *
+ * + * A version of xQueueOverwrite() that can be used in an interrupt service + * routine (ISR). + * + * Only for use with queues that can hold a single item - so the queue is either + * empty or full. + * + * Post an item on a queue. If the queue is already full then overwrite the + * value held in the queue. The item is queued by copy, not by reference. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param pxHigherPriorityTaskWoken xQueueOverwriteFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xQueueOverwriteFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @return xQueueOverwriteFromISR() is a macro that calls + * xQueueGenericSendFromISR(), and therefore has the same return values as + * xQueueSendToFrontFromISR(). However, pdPASS is the only value that can be + * returned because xQueueOverwriteFromISR() will write to the queue even when + * the queue is already full. + * + * Example usage: + 
+
+ QueueHandle_t xQueue;
+
+ void vFunction( void *pvParameters )
+ {
+ 	// Create a queue to hold one uint32_t value.  It is strongly
+	// recommended *not* to use xQueueOverwriteFromISR() on queues that can
+	// contain more than one value, and doing so will trigger an assertion
+	// if configASSERT() is defined.
+	xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
+}
+
+void vAnInterruptHandler( void )
+{
+// xHigherPriorityTaskWoken must be set to pdFALSE before it is used.
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+uint32_t ulVarToSend, ulValReceived;
+
+	// Write the value 10 to the queue using xQueueOverwriteFromISR().
+	ulVarToSend = 10;
+	xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
+
+	// The queue is full, but calling xQueueOverwriteFromISR() again will still
+	// pass because the value held in the queue will be overwritten with the
+	// new value.
+	ulVarToSend = 100;
+	xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
+
+	// Reading from the queue will now return 100.
+
+	// ...
+
+	if( xHigherPrioritytaskWoken == pdTRUE )
+	{
+		// Writing to the queue caused a task to unblock and the unblocked task
+		// has a priority higher than or equal to the priority of the currently
+		// executing task (the task this interrupt interrupted).  Perform a context
+		// switch so this interrupt returns directly to the unblocked task.
+		portYIELD_FROM_ISR(); // or portEND_SWITCHING_ISR() depending on the port.
+	}
+}
+
+ * \defgroup xQueueOverwriteFromISR xQueueOverwriteFromISR + * \ingroup QueueManagement + */ +#define xQueueOverwriteFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueOVERWRITE ) + +/** + * queue. h + * 
+ BaseType_t xQueueSendFromISR(
+									 QueueHandle_t xQueue,
+									 const void *pvItemToQueue,
+									 BaseType_t *pxHigherPriorityTaskWoken
+								);
+
+ * + * This is a macro that calls xQueueGenericSendFromISR(). It is included + * for backward compatibility with versions of FreeRTOS.org that did not + * include the xQueueSendToBackFromISR() and xQueueSendToFrontFromISR() + * macros. + * + * Post an item to the back of a queue. It is safe to use this function from + * within an interrupt service routine. + * + * Items are queued by copy not reference so it is preferable to only + * queue small items, especially when called from an ISR. In most cases + * it would be preferable to store a pointer to the item being queued. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param pxHigherPriorityTaskWoken xQueueSendFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xQueueSendFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @return pdTRUE if the data was successfully sent to the queue, otherwise + * errQUEUE_FULL. + * + * Example usage for buffered IO (where the ISR can obtain more than one value + * per call): + 
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWoken;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWoken = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post the byte.
+		xQueueSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.
+	if( xHigherPriorityTaskWoken )
+	{
+		// Actual macro used here is port specific.
+		portYIELD_FROM_ISR ();
+	}
+ }
+
+ * + * \defgroup xQueueSendFromISR xQueueSendFromISR + * \ingroup QueueManagement + */ +#define xQueueSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK ) + +/** + * queue. h + * 
+ BaseType_t xQueueGenericSendFromISR(
+										   QueueHandle_t		xQueue,
+										   const	void	*pvItemToQueue,
+										   BaseType_t	*pxHigherPriorityTaskWoken,
+										   BaseType_t	xCopyPosition
+									   );
+
+ * + * It is preferred that the macros xQueueSendFromISR(), + * xQueueSendToFrontFromISR() and xQueueSendToBackFromISR() be used in place + * of calling this function directly. xQueueGiveFromISR() is an + * equivalent for use by semaphores that don't actually copy any data. + * + * Post an item on a queue. It is safe to use this function from within an + * interrupt service routine. + * + * Items are queued by copy not reference so it is preferable to only + * queue small items, especially when called from an ISR. In most cases + * it would be preferable to store a pointer to the item being queued. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param pxHigherPriorityTaskWoken xQueueGenericSendFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xQueueGenericSendFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the + * item at the back of the queue, or queueSEND_TO_FRONT to place the item + * at the front of the queue (for high priority messages). + * + * @return pdTRUE if the data was successfully sent to the queue, otherwise + * errQUEUE_FULL. + * + * Example usage for buffered IO (where the ISR can obtain more than one value + * per call): + 
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWokenByPost;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWokenByPost = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post each byte.
+		xQueueGenericSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWokenByPost, queueSEND_TO_BACK );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.  Note that the
+	// name of the yield function required is port specific.
+	if( xHigherPriorityTaskWokenByPost )
+	{
+		taskYIELD_YIELD_FROM_ISR();
+	}
+ }
+
+ * + * \defgroup xQueueSendFromISR xQueueSendFromISR + * \ingroup QueueManagement + */ +BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION; +BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * 
+ BaseType_t xQueueReceiveFromISR(
+									   QueueHandle_t	xQueue,
+									   void	*pvBuffer,
+									   BaseType_t *pxTaskWoken
+								   );
+ *
+ * + * Receive an item from a queue. It is safe to use this function from within an + * interrupt service routine. + * + * @param xQueue The handle to the queue from which the item is to be + * received. + * + * @param pvBuffer Pointer to the buffer into which the received item will + * be copied. + * + * @param pxTaskWoken A task may be blocked waiting for space to become + * available on the queue. If xQueueReceiveFromISR causes such a task to + * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will + * remain unchanged. + * + * @return pdTRUE if an item was successfully received from the queue, + * otherwise pdFALSE. + * + * Example usage: + 
+
+ QueueHandle_t xQueue;
+
+ // Function to create a queue and post some values.
+ void vAFunction( void *pvParameters )
+ {
+ char cValueToPost;
+ const TickType_t xTicksToWait = ( TickType_t )0xff;
+
+	// Create a queue capable of containing 10 characters.
+	xQueue = xQueueCreate( 10, sizeof( char ) );
+	if( xQueue == 0 )
+	{
+		// Failed to create the queue.
+	}
+
+	// ...
+
+	// Post some characters that will be used within an ISR.  If the queue
+	// is full then this task will block for xTicksToWait ticks.
+	cValueToPost = 'a';
+	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+	cValueToPost = 'b';
+	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+
+	// ... keep posting characters ... this task may block when the queue
+	// becomes full.
+
+	cValueToPost = 'c';
+	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+ }
+
+ // ISR that outputs all the characters received on the queue.
+ void vISR_Routine( void )
+ {
+ BaseType_t xTaskWokenByReceive = pdFALSE;
+ char cRxedChar;
+
+	while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )
+	{
+		// A character was received.  Output the character now.
+		vOutputCharacter( cRxedChar );
+
+		// If removing the character from the queue woke the task that was
+		// posting onto the queue cTaskWokenByReceive will have been set to
+		// pdTRUE.  No matter how many times this loop iterates only one
+		// task will be woken.
+	}
+
+	if( cTaskWokenByPost != ( char ) pdFALSE;
+	{
+		taskYIELD ();
+	}
+ }
+
+ * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR + * \ingroup QueueManagement + */ +BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; + +/* + * Utilities to query queues that are safe to use from an ISR. These utilities + * should be used only from witin an ISR, or within a critical section. + */ +BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; +BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; +UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; + + +/* + * xQueueAltGenericSend() is an alternative version of xQueueGenericSend(). + * Likewise xQueueAltGenericReceive() is an alternative version of + * xQueueGenericReceive(). + * + * The source code that implements the alternative (Alt) API is much + * simpler because it executes everything from within a critical section. + * This is the approach taken by many other RTOSes, but FreeRTOS.org has the + * preferred fully featured API too. The fully featured API has more + * complex code that takes longer to execute, but makes much less use of + * critical sections. Therefore the alternative API sacrifices interrupt + * responsiveness to gain execution speed, whereas the fully featured API + * sacrifices execution speed to ensure better interrupt responsiveness. + */ +BaseType_t xQueueAltGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, BaseType_t xCopyPosition ); +BaseType_t xQueueAltGenericReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait, BaseType_t xJustPeeking ); +#define xQueueAltSendToFront( xQueue, pvItemToQueue, xTicksToWait ) xQueueAltGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT ) +#define xQueueAltSendToBack( xQueue, pvItemToQueue, xTicksToWait ) xQueueAltGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK ) +#define xQueueAltReceive( xQueue, pvBuffer, xTicksToWait ) xQueueAltGenericReceive( ( xQueue ), ( pvBuffer ), ( xTicksToWait ), pdFALSE ) +#define xQueueAltPeek( xQueue, pvBuffer, xTicksToWait ) xQueueAltGenericReceive( ( xQueue ), ( pvBuffer ), ( xTicksToWait ), pdTRUE ) + +/* + * The functions defined above are for passing data to and from tasks. The + * functions below are the equivalents for passing data to and from + * co-routines. + * + * These functions are called from the co-routine macro implementation and + * should not be called directly from application code. Instead use the macro + * wrappers defined within croutine.h. + */ +BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken ); +BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxTaskWoken ); +BaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait ); +BaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait ); + +/* + * For internal use only. Use xSemaphoreCreateMutex(), + * xSemaphoreCreateCounting() or xSemaphoreGetMutexHolder() instead of calling + * these functions directly. + */ +QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION; +QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION; +void* xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION; + +/* + * For internal use only. Use xSemaphoreTakeMutexRecursive() or + * xSemaphoreGiveMutexRecursive() instead of calling these functions directly. + */ +BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +BaseType_t xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) PRIVILEGED_FUNCTION; + +/* + * Reset a queue back to its original empty state. pdPASS is returned if the + * queue is successfully reset. pdFAIL is returned if the queue could not be + * reset because there are tasks blocked on the queue waiting to either + * receive from the queue or send to the queue. + */ +#define xQueueReset( xQueue ) xQueueGenericReset( xQueue, pdFALSE ) + +/* + * The registry is provided as a means for kernel aware debuggers to + * locate queues, semaphores and mutexes. Call vQueueAddToRegistry() add + * a queue, semaphore or mutex handle to the registry if you want the handle + * to be available to a kernel aware debugger. If you are not using a kernel + * aware debugger then this function can be ignored. + * + * configQUEUE_REGISTRY_SIZE defines the maximum number of handles the + * registry can hold. configQUEUE_REGISTRY_SIZE must be greater than 0 + * within FreeRTOSConfig.h for the registry to be available. Its value + * does not effect the number of queues, semaphores and mutexes that can be + * created - just the number that the registry can hold. + * + * @param xQueue The handle of the queue being added to the registry. This + * is the handle returned by a call to xQueueCreate(). Semaphore and mutex + * handles can also be passed in here. + * + * @param pcName The name to be associated with the handle. This is the + * name that the kernel aware debugger will display. The queue registry only + * stores a pointer to the string - so the string must be persistent (global or + * preferably in ROM/Flash), not on the stack. + */ +#if configQUEUE_REGISTRY_SIZE > 0 + void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ +#endif + +/* + * The registry is provided as a means for kernel aware debuggers to + * locate queues, semaphores and mutexes. Call vQueueAddToRegistry() add + * a queue, semaphore or mutex handle to the registry if you want the handle + * to be available to a kernel aware debugger, and vQueueUnregisterQueue() to + * remove the queue, semaphore or mutex from the register. If you are not using + * a kernel aware debugger then this function can be ignored. + * + * @param xQueue The handle of the queue being removed from the registry. + */ +#if configQUEUE_REGISTRY_SIZE > 0 + void vQueueUnregisterQueue( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; +#endif + +/* + * Generic version of the queue creation function, which is in turn called by + * any queue, semaphore or mutex creation function or macro. + */ +QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) PRIVILEGED_FUNCTION; + +/* + * Queue sets provide a mechanism to allow a task to block (pend) on a read + * operation from multiple queues or semaphores simultaneously. + * + * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this + * function. + * + * A queue set must be explicitly created using a call to xQueueCreateSet() + * before it can be used. Once created, standard FreeRTOS queues and semaphores + * can be added to the set using calls to xQueueAddToSet(). + * xQueueSelectFromSet() is then used to determine which, if any, of the queues + * or semaphores contained in the set is in a state where a queue read or + * semaphore take operation would be successful. + * + * Note 1: See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html + * for reasons why queue sets are very rarely needed in practice as there are + * simpler methods of blocking on multiple objects. + * + * Note 2: Blocking on a queue set that contains a mutex will not cause the + * mutex holder to inherit the priority of the blocked task. + * + * Note 3: An additional 4 bytes of RAM is required for each space in a every + * queue added to a queue set. Therefore counting semaphores that have a high + * maximum count value should not be added to a queue set. + * + * Note 4: A receive (in the case of a queue) or take (in the case of a + * semaphore) operation must not be performed on a member of a queue set unless + * a call to xQueueSelectFromSet() has first returned a handle to that set member. + * + * @param uxEventQueueLength Queue sets store events that occur on + * the queues and semaphores contained in the set. uxEventQueueLength specifies + * the maximum number of events that can be queued at once. To be absolutely + * certain that events are not lost uxEventQueueLength should be set to the + * total sum of the length of the queues added to the set, where binary + * semaphores and mutexes have a length of 1, and counting semaphores have a + * length set by their maximum count value. Examples: + * + If a queue set is to hold a queue of length 5, another queue of length 12, + * and a binary semaphore, then uxEventQueueLength should be set to + * (5 + 12 + 1), or 18. + * + If a queue set is to hold three binary semaphores then uxEventQueueLength + * should be set to (1 + 1 + 1 ), or 3. + * + If a queue set is to hold a counting semaphore that has a maximum count of + * 5, and a counting semaphore that has a maximum count of 3, then + * uxEventQueueLength should be set to (5 + 3), or 8. + * + * @return If the queue set is created successfully then a handle to the created + * queue set is returned. Otherwise NULL is returned. + */ +QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION; + +/* + * Adds a queue or semaphore to a queue set that was previously created by a + * call to xQueueCreateSet(). + * + * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this + * function. + * + * Note 1: A receive (in the case of a queue) or take (in the case of a + * semaphore) operation must not be performed on a member of a queue set unless + * a call to xQueueSelectFromSet() has first returned a handle to that set member. + * + * @param xQueueOrSemaphore The handle of the queue or semaphore being added to + * the queue set (cast to an QueueSetMemberHandle_t type). + * + * @param xQueueSet The handle of the queue set to which the queue or semaphore + * is being added. + * + * @return If the queue or semaphore was successfully added to the queue set + * then pdPASS is returned. If the queue could not be successfully added to the + * queue set because it is already a member of a different queue set then pdFAIL + * is returned. + */ +BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION; + +/* + * Removes a queue or semaphore from a queue set. A queue or semaphore can only + * be removed from a set if the queue or semaphore is empty. + * + * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this + * function. + * + * @param xQueueOrSemaphore The handle of the queue or semaphore being removed + * from the queue set (cast to an QueueSetMemberHandle_t type). + * + * @param xQueueSet The handle of the queue set in which the queue or semaphore + * is included. + * + * @return If the queue or semaphore was successfully removed from the queue set + * then pdPASS is returned. If the queue was not in the queue set, or the + * queue (or semaphore) was not empty, then pdFAIL is returned. + */ +BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION; + +/* + * xQueueSelectFromSet() selects from the members of a queue set a queue or + * semaphore that either contains data (in the case of a queue) or is available + * to take (in the case of a semaphore). xQueueSelectFromSet() effectively + * allows a task to block (pend) on a read operation on all the queues and + * semaphores in a queue set simultaneously. + * + * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this + * function. + * + * Note 1: See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html + * for reasons why queue sets are very rarely needed in practice as there are + * simpler methods of blocking on multiple objects. + * + * Note 2: Blocking on a queue set that contains a mutex will not cause the + * mutex holder to inherit the priority of the blocked task. + * + * Note 3: A receive (in the case of a queue) or take (in the case of a + * semaphore) operation must not be performed on a member of a queue set unless + * a call to xQueueSelectFromSet() has first returned a handle to that set member. + * + * @param xQueueSet The queue set on which the task will (potentially) block. + * + * @param xTicksToWait The maximum time, in ticks, that the calling task will + * remain in the Blocked state (with other tasks executing) to wait for a member + * of the queue set to be ready for a successful queue read or semaphore take + * operation. + * + * @return xQueueSelectFromSet() will return the handle of a queue (cast to + * a QueueSetMemberHandle_t type) contained in the queue set that contains data, + * or the handle of a semaphore (cast to a QueueSetMemberHandle_t type) contained + * in the queue set that is available, or NULL if no such queue or semaphore + * exists before before the specified block time expires. + */ +QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/* + * A version of xQueueSelectFromSet() that can be used from an ISR. + */ +QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION; + +/* Not public API functions. */ +void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) PRIVILEGED_FUNCTION; +void vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) PRIVILEGED_FUNCTION; +UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; +uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; + + +#ifdef __cplusplus +} +#endif + +#endif /* QUEUE_H */ + diff --git a/tools/sdk/include/freertos/freertos/ringbuf.h b/tools/sdk/include/freertos/freertos/ringbuf.h new file mode 100644 index 00000000..7884e985 --- /dev/null +++ b/tools/sdk/include/freertos/freertos/ringbuf.h @@ -0,0 +1,206 @@ +#ifndef FREERTOS_RINGBUF_H +#define FREERTOS_RINGBUF_H + +/* +Header definitions for a FreeRTOS ringbuffer object + +A ringbuffer instantiated by these functions essentially acts like a FreeRTOS queue, with the +difference that it's strictly FIFO and with the main advantage that you can put in randomly-sized +items. The capacity, accordingly, isn't measured in the amount of items, but the amount of memory +that is used for storing the items. Dependent on the size of the items, more or less of them will +fit in the ring buffer. + +This ringbuffer tries to be efficient with memory: when inserting an item, the item data will +be copied to the ringbuffer memory. When retrieving an item, however, a reference to ringbuffer +memory will be returned. The returned memory is guaranteed to be 32-bit aligned and contiguous. +The application can use this memory, but as long as it does, ringbuffer writes that would write +to this bit of memory will block. + +The requirement for items to be contiguous is slightly problematic when the only way to place +the next item would involve a wraparound from the end to the beginning of the ringbuffer. This can +be solved in two ways: +- allow_split_items = pdTRUE: The insertion code will split the item in two items; one which fits +in the space left at the end of the ringbuffer, one that contains the remaining data which is placed +in the beginning. Two xRingbufferReceive calls will be needed to retrieve the data. +- allow_split_items = pdFALSE: The insertion code will leave the room at the end of the ringbuffer +unused and instead will put the entire item at the start of the ringbuffer, as soon as there is +enough free space. + +The maximum size of an item will be affected by this decision. When split items are allowed, it's +acceptable to push items of (buffer_size)-16 bytes into the buffer. When it's not allowed, the +maximum size is (buffer_size/2)-8 bytes. +*/ + +//An opaque handle for a ringbuff object. +typedef void * RingbufHandle_t; + + +/** + * @brief Create a ring buffer + * + * @param buf_length : Length of circular buffer, in bytes. Each entry will take up its own length, plus a header + * that at the moment is equal to sizeof(size_t). + * @param allow_split_items : pdTRUE if it is acceptable that item data is inserted as two + * items instead of one. + * + * @return A RingbufHandle_t handle to the created ringbuffer, or NULL in case of error. + */ +RingbufHandle_t xRingbufferCreate(size_t buf_length, BaseType_t allow_split_items); + + +/** + * @brief Delete a ring buffer + * + * @param ringbuf - Ring buffer to delete + * + * @return void + */ +void vRingbufferDelete(RingbufHandle_t ringbuf); + + +/** + * @brief Get maximum size of an item that can be placed in the ring buffer + * + * @param ringbuf - Ring buffer to query + * + * @return Maximum size, in bytes, of an item that can be placed in a ring buffer. + */ +size_t xRingbufferGetMaxItemSize(RingbufHandle_t ringbuf); + + +/** + * @brief Insert an item into the ring buffer + * + * @param ringbuf - Ring buffer to insert the item into + * @param data - Pointer to data to insert. NULL is allowed if data_size is 0. + * @param data_size - Size of data to insert. A value of 0 is allowed. + * @param xTicksToWait - Ticks to wait for room in the ringbuffer. + * + * @return pdTRUE if succeeded, pdFALSE on time-out or when the buffer is larger + * than indicated by xRingbufferGetMaxItemSize(ringbuf). + */ +BaseType_t xRingbufferSend(RingbufHandle_t ringbuf, void *data, size_t data_size, TickType_t ticks_to_wait); + + +/** + * @brief Insert an item into the ring buffer from an ISR + * + * @param ringbuf - Ring buffer to insert the item into + * @param data - Pointer to data to insert. NULL is allowed if data_size is 0. + * @param data_size - Size of data to insert. A value of 0 is allowed. + * @param higher_prio_task_awoken - Value pointed to will be set to pdTRUE if the push woke up a higher + * priority task. + * + * @return pdTRUE if succeeded, pdFALSE when the ring buffer does not have space. + */ +BaseType_t xRingbufferSendFromISR(RingbufHandle_t ringbuf, void *data, size_t data_size, BaseType_t *higher_prio_task_awoken); + +/** + * @brief Retrieve an item from the ring buffer + * + * @param ringbuf - Ring buffer to retrieve the item from + * @param item_size - Pointer to a variable to which the size of the retrieved item will be written. + * @param xTicksToWait - Ticks to wait for items in the ringbuffer. + * + * @return Pointer to the retrieved item on success; *item_size filled with the length of the + * item. NULL on timeout, *item_size is untouched in that case. + */ +void *xRingbufferReceive(RingbufHandle_t ringbuf, size_t *item_size, TickType_t ticks_to_wait); + + +/** + * @brief Retrieve an item from the ring buffer from an ISR + * + * @param ringbuf - Ring buffer to retrieve the item from + * @param item_size - Pointer to a variable to which the size of the retrieved item will be written. + * + * @return Pointer to the retrieved item on success; *item_size filled with the length of the + * item. NULL when the ringbuffer is empty, *item_size is untouched in that case. + */ +void *xRingbufferReceiveFromISR(RingbufHandle_t ringbuf, size_t *item_size); + + +/** + * @brief Return a previously-retrieved item to the ringbuffer + * + * @param ringbuf - Ring buffer the item was retrieved from + * @param item - Item that was received earlier + * + * @return void + */ +void vRingbufferReturnItem(RingbufHandle_t ringbuf, void *item); + + + +/** + * @brief Return a previously-retrieved item to the ringbuffer from an ISR + * + * @param ringbuf - Ring buffer the item was retrieved from + * @param item - Item that was received earlier + * @param higher_prio_task_awoken - Value pointed to will be set to pdTRUE if the push woke up a higher + * priority task. + * + * @return void + */ +void vRingbufferReturnItemFromISR(RingbufHandle_t ringbuf, void *item, BaseType_t *higher_prio_task_awoken); + + +/** + * @brief Add the ringbuffer to a queue set. This specifically adds the semaphore that indicates + * more space has become available in the ringbuffer. + * + * @param ringbuf - Ring buffer to add to the queue set + * @param xQueueSet - Queue set to add the ringbuffer to + * + * @return pdTRUE on success, pdFALSE otherwise + */ +BaseType_t xRingbufferAddToQueueSetRead(RingbufHandle_t ringbuf, QueueSetHandle_t xQueueSet); + + +/** + * @brief Add the ringbuffer to a queue set. This specifically adds the semaphore that indicates + * something has been written into the ringbuffer. + * + * @param ringbuf - Ring buffer to add to the queue set + * @param xQueueSet - Queue set to add the ringbuffer to + * + * @return pdTRUE on success, pdFALSE otherwise + */ +BaseType_t xRingbufferAddToQueueSetWrite(RingbufHandle_t ringbuf, QueueSetHandle_t xQueueSet); + + +/** + * @brief Remove the ringbuffer from a queue set. This specifically removes the semaphore that indicates + * more space has become available in the ringbuffer. + * + * @param ringbuf - Ring buffer to remove from the queue set + * @param xQueueSet - Queue set to remove the ringbuffer from + * + * @return pdTRUE on success, pdFALSE otherwise + */ +BaseType_t xRingbufferRemoveFromQueueSetRead(RingbufHandle_t ringbuf, QueueSetHandle_t xQueueSet); + + +/** + * @brief Remove the ringbuffer from a queue set. This specifically removes the semaphore that indicates + * something has been written to the ringbuffer. + * + * @param ringbuf - Ring buffer to remove from the queue set + * @param xQueueSet - Queue set to remove the ringbuffer from + * + * @return pdTRUE on success, pdFALSE otherwise + */ +BaseType_t xRingbufferRemoveFromQueueSetWrite(RingbufHandle_t ringbuf, QueueSetHandle_t xQueueSet); + + +/** + * @brief Debugging function to print the internal pointers in the ring buffer + * + * @param ringbuf - Ring buffer to show + * + * @return void + */ +void xRingbufferPrintInfo(RingbufHandle_t ringbuf); + + +#endif diff --git a/tools/sdk/include/freertos/freertos/semphr.h b/tools/sdk/include/freertos/freertos/semphr.h new file mode 100644 index 00000000..5866ab1e --- /dev/null +++ b/tools/sdk/include/freertos/freertos/semphr.h @@ -0,0 +1,844 @@ +/* + FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef SEMAPHORE_H +#define SEMAPHORE_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h" must appear in source files before "include semphr.h" +#endif + +#include "queue.h" + +typedef QueueHandle_t SemaphoreHandle_t; + +#define semBINARY_SEMAPHORE_QUEUE_LENGTH ( ( uint8_t ) 1U ) +#define semSEMAPHORE_QUEUE_ITEM_LENGTH ( ( uint8_t ) 0U ) +#define semGIVE_BLOCK_TIME ( ( TickType_t ) 0U ) + + +/** + * semphr. h + * 
vSemaphoreCreateBinary( SemaphoreHandle_t xSemaphore )
+ * + * This old vSemaphoreCreateBinary() macro is now deprecated in favour of the + * xSemaphoreCreateBinary() function. Note that binary semaphores created using + * the vSemaphoreCreateBinary() macro are created in a state such that the + * first call to 'take' the semaphore would pass, whereas binary semaphores + * created using xSemaphoreCreateBinary() are created in a state such that the + * the semaphore must first be 'given' before it can be 'taken'. + * + * Macro that implements a semaphore by using the existing queue mechanism. + * The queue length is 1 as this is a binary semaphore. The data size is 0 + * as we don't want to actually store any data - we just want to know if the + * queue is empty or full. + * + * This type of semaphore can be used for pure synchronisation between tasks or + * between an interrupt and a task. The semaphore need not be given back once + * obtained, so one task/interrupt can continuously 'give' the semaphore while + * another continuously 'takes' the semaphore. For this reason this type of + * semaphore does not use a priority inheritance mechanism. For an alternative + * that does use priority inheritance see xSemaphoreCreateMutex(). + * + * @param xSemaphore Handle to the created semaphore. Should be of type SemaphoreHandle_t. + * + * Example usage: + 
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().
+    // This is a macro so pass the variable in directly.
+    vSemaphoreCreateBinary( xSemaphore );
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+
+ * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary + * \ingroup Semaphores + */ +#define vSemaphoreCreateBinary( xSemaphore ) \ + { \ + ( xSemaphore ) = xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE ); \ + if( ( xSemaphore ) != NULL ) \ + { \ + ( void ) xSemaphoreGive( ( xSemaphore ) ); \ + } \ + } + +/** + * semphr. h + * 
SemaphoreHandle_t xSemaphoreCreateBinary( void )
+ * + * The old vSemaphoreCreateBinary() macro is now deprecated in favour of this + * xSemaphoreCreateBinary() function. Note that binary semaphores created using + * the vSemaphoreCreateBinary() macro are created in a state such that the + * first call to 'take' the semaphore would pass, whereas binary semaphores + * created using xSemaphoreCreateBinary() are created in a state such that the + * the semaphore must first be 'given' before it can be 'taken'. + * + * Function that creates a semaphore by using the existing queue mechanism. + * The queue length is 1 as this is a binary semaphore. The data size is 0 + * as nothing is actually stored - all that is important is whether the queue is + * empty or full (the binary semaphore is available or not). + * + * This type of semaphore can be used for pure synchronisation between tasks or + * between an interrupt and a task. The semaphore need not be given back once + * obtained, so one task/interrupt can continuously 'give' the semaphore while + * another continuously 'takes' the semaphore. For this reason this type of + * semaphore does not use a priority inheritance mechanism. For an alternative + * that does use priority inheritance see xSemaphoreCreateMutex(). + * + * @return Handle to the created semaphore. + * + * Example usage: + 
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().
+    // This is a macro so pass the variable in directly.
+    xSemaphore = xSemaphoreCreateBinary();
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+
+ * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary + * \ingroup Semaphores + */ +#define xSemaphoreCreateBinary() xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE ) + +/** + * semphr. h + * 
xSemaphoreTake(
+ *                   SemaphoreHandle_t xSemaphore,
+ *                   TickType_t xBlockTime
+ *               )
+ * + * Macro to obtain a semaphore. The semaphore must have previously been + * created with a call to vSemaphoreCreateBinary(), xSemaphoreCreateMutex() or + * xSemaphoreCreateCounting(). + * + * @param xSemaphore A handle to the semaphore being taken - obtained when + * the semaphore was created. + * + * @param xBlockTime The time in ticks to wait for the semaphore to become + * available. The macro portTICK_PERIOD_MS can be used to convert this to a + * real time. A block time of zero can be used to poll the semaphore. A block + * time of portMAX_DELAY can be used to block indefinitely (provided + * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h). + * + * @return pdTRUE if the semaphore was obtained. pdFALSE + * if xBlockTime expired without the semaphore becoming available. + * + * Example usage: + 
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ // A task that creates a semaphore.
+ void vATask( void * pvParameters )
+ {
+    // Create the semaphore to guard a shared resource.
+    vSemaphoreCreateBinary( xSemaphore );
+ }
+
+ // A task that uses the semaphore.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xSemaphore != NULL )
+    {
+        // See if we can obtain the semaphore.  If the semaphore is not available
+        // wait 10 ticks to see if it becomes free.
+        if( xSemaphoreTake( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the semaphore and can now access the
+            // shared resource.
+
+            // ...
+
+            // We have finished accessing the shared resource.  Release the
+            // semaphore.
+            xSemaphoreGive( xSemaphore );
+        }
+        else
+        {
+            // We could not obtain the semaphore and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+
+ * \defgroup xSemaphoreTake xSemaphoreTake + * \ingroup Semaphores + */ +#define xSemaphoreTake( xSemaphore, xBlockTime ) xQueueGenericReceive( ( QueueHandle_t ) ( xSemaphore ), NULL, ( xBlockTime ), pdFALSE ) + +/** + * semphr. h + * xSemaphoreTakeRecursive( + * SemaphoreHandle_t xMutex, + * TickType_t xBlockTime + * ) + * + * Macro to recursively obtain, or 'take', a mutex type semaphore. + * The mutex must have previously been created using a call to + * xSemaphoreCreateRecursiveMutex(); + * + * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this + * macro to be available. + * + * This macro must not be used on mutexes created using xSemaphoreCreateMutex(). + * + * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex + * doesn't become available again until the owner has called + * xSemaphoreGiveRecursive() for each successful 'take' request. For example, + * if a task successfully 'takes' the same mutex 5 times then the mutex will + * not be available to any other task until it has also 'given' the mutex back + * exactly five times. + * + * @param xMutex A handle to the mutex being obtained. This is the + * handle returned by xSemaphoreCreateRecursiveMutex(); + * + * @param xBlockTime The time in ticks to wait for the semaphore to become + * available. The macro portTICK_PERIOD_MS can be used to convert this to a + * real time. A block time of zero can be used to poll the semaphore. If + * the task already owns the semaphore then xSemaphoreTakeRecursive() will + * return immediately no matter what the value of xBlockTime. + * + * @return pdTRUE if the semaphore was obtained. pdFALSE if xBlockTime + * expired without the semaphore becoming available. + * + * Example usage: + 
+ SemaphoreHandle_t xMutex = NULL;
+
+ // A task that creates a mutex.
+ void vATask( void * pvParameters )
+ {
+    // Create the mutex to guard a shared resource.
+    xMutex = xSemaphoreCreateRecursiveMutex();
+ }
+
+ // A task that uses the mutex.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xMutex != NULL )
+    {
+        // See if we can obtain the mutex.  If the mutex is not available
+        // wait 10 ticks to see if it becomes free.
+        if( xSemaphoreTakeRecursive( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the mutex and can now access the
+            // shared resource.
+
+            // ...
+            // For some reason due to the nature of the code further calls to
+			// xSemaphoreTakeRecursive() are made on the same mutex.  In real
+			// code these would not be just sequential calls as this would make
+			// no sense.  Instead the calls are likely to be buried inside
+			// a more complex call structure.
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+
+            // The mutex has now been 'taken' three times, so will not be
+			// available to another task until it has also been given back
+			// three times.  Again it is unlikely that real code would have
+			// these calls sequentially, but instead buried in a more complex
+			// call structure.  This is just for illustrative purposes.
+            xSemaphoreGiveRecursive( xMutex );
+			xSemaphoreGiveRecursive( xMutex );
+			xSemaphoreGiveRecursive( xMutex );
+
+			// Now the mutex can be taken by other tasks.
+        }
+        else
+        {
+            // We could not obtain the mutex and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+
+ * \defgroup xSemaphoreTakeRecursive xSemaphoreTakeRecursive + * \ingroup Semaphores + */ +#define xSemaphoreTakeRecursive( xMutex, xBlockTime ) xQueueTakeMutexRecursive( ( xMutex ), ( xBlockTime ) ) + + +/* + * xSemaphoreAltTake() is an alternative version of xSemaphoreTake(). + * + * The source code that implements the alternative (Alt) API is much + * simpler because it executes everything from within a critical section. + * This is the approach taken by many other RTOSes, but FreeRTOS.org has the + * preferred fully featured API too. The fully featured API has more + * complex code that takes longer to execute, but makes much less use of + * critical sections. Therefore the alternative API sacrifices interrupt + * responsiveness to gain execution speed, whereas the fully featured API + * sacrifices execution speed to ensure better interrupt responsiveness. + */ +#define xSemaphoreAltTake( xSemaphore, xBlockTime ) xQueueAltGenericReceive( ( QueueHandle_t ) ( xSemaphore ), NULL, ( xBlockTime ), pdFALSE ) + +/** + * semphr. h + * 
xSemaphoreGive( SemaphoreHandle_t xSemaphore )
+ * + * Macro to release a semaphore. The semaphore must have previously been + * created with a call to vSemaphoreCreateBinary(), xSemaphoreCreateMutex() or + * xSemaphoreCreateCounting(). and obtained using sSemaphoreTake(). + * + * This macro must not be used from an ISR. See xSemaphoreGiveFromISR () for + * an alternative which can be used from an ISR. + * + * This macro must also not be used on semaphores created using + * xSemaphoreCreateRecursiveMutex(). + * + * @param xSemaphore A handle to the semaphore being released. This is the + * handle returned when the semaphore was created. + * + * @return pdTRUE if the semaphore was released. pdFALSE if an error occurred. + * Semaphores are implemented using queues. An error can occur if there is + * no space on the queue to post a message - indicating that the + * semaphore was not first obtained correctly. + * + * Example usage: + 
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+    // Create the semaphore to guard a shared resource.
+    vSemaphoreCreateBinary( xSemaphore );
+
+    if( xSemaphore != NULL )
+    {
+        if( xSemaphoreGive( xSemaphore ) != pdTRUE )
+        {
+            // We would expect this call to fail because we cannot give
+            // a semaphore without first "taking" it!
+        }
+
+        // Obtain the semaphore - don't block if the semaphore is not
+        // immediately available.
+        if( xSemaphoreTake( xSemaphore, ( TickType_t ) 0 ) )
+        {
+            // We now have the semaphore and can access the shared resource.
+
+            // ...
+
+            // We have finished accessing the shared resource so can free the
+            // semaphore.
+            if( xSemaphoreGive( xSemaphore ) != pdTRUE )
+            {
+                // We would not expect this call to fail because we must have
+                // obtained the semaphore to get here.
+            }
+        }
+    }
+ }
+
+ * \defgroup xSemaphoreGive xSemaphoreGive + * \ingroup Semaphores + */ +#define xSemaphoreGive( xSemaphore ) xQueueGenericSend( ( QueueHandle_t ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK ) + +/** + * semphr. h + * 
xSemaphoreGiveRecursive( SemaphoreHandle_t xMutex )
+ * + * Macro to recursively release, or 'give', a mutex type semaphore. + * The mutex must have previously been created using a call to + * xSemaphoreCreateRecursiveMutex(); + * + * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this + * macro to be available. + * + * This macro must not be used on mutexes created using xSemaphoreCreateMutex(). + * + * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex + * doesn't become available again until the owner has called + * xSemaphoreGiveRecursive() for each successful 'take' request. For example, + * if a task successfully 'takes' the same mutex 5 times then the mutex will + * not be available to any other task until it has also 'given' the mutex back + * exactly five times. + * + * @param xMutex A handle to the mutex being released, or 'given'. This is the + * handle returned by xSemaphoreCreateMutex(); + * + * @return pdTRUE if the semaphore was given. + * + * Example usage: + 
+ SemaphoreHandle_t xMutex = NULL;
+
+ // A task that creates a mutex.
+ void vATask( void * pvParameters )
+ {
+    // Create the mutex to guard a shared resource.
+    xMutex = xSemaphoreCreateRecursiveMutex();
+ }
+
+ // A task that uses the mutex.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xMutex != NULL )
+    {
+        // See if we can obtain the mutex.  If the mutex is not available
+        // wait 10 ticks to see if it becomes free.
+        if( xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the mutex and can now access the
+            // shared resource.
+
+            // ...
+            // For some reason due to the nature of the code further calls to
+			// xSemaphoreTakeRecursive() are made on the same mutex.  In real
+			// code these would not be just sequential calls as this would make
+			// no sense.  Instead the calls are likely to be buried inside
+			// a more complex call structure.
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+
+            // The mutex has now been 'taken' three times, so will not be
+			// available to another task until it has also been given back
+			// three times.  Again it is unlikely that real code would have
+			// these calls sequentially, it would be more likely that the calls
+			// to xSemaphoreGiveRecursive() would be called as a call stack
+			// unwound.  This is just for demonstrative purposes.
+            xSemaphoreGiveRecursive( xMutex );
+			xSemaphoreGiveRecursive( xMutex );
+			xSemaphoreGiveRecursive( xMutex );
+
+			// Now the mutex can be taken by other tasks.
+        }
+        else
+        {
+            // We could not obtain the mutex and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+
+ * \defgroup xSemaphoreGiveRecursive xSemaphoreGiveRecursive + * \ingroup Semaphores + */ +#define xSemaphoreGiveRecursive( xMutex ) xQueueGiveMutexRecursive( ( xMutex ) ) + +/* + * xSemaphoreAltGive() is an alternative version of xSemaphoreGive(). + * + * The source code that implements the alternative (Alt) API is much + * simpler because it executes everything from within a critical section. + * This is the approach taken by many other RTOSes, but FreeRTOS.org has the + * preferred fully featured API too. The fully featured API has more + * complex code that takes longer to execute, but makes much less use of + * critical sections. Therefore the alternative API sacrifices interrupt + * responsiveness to gain execution speed, whereas the fully featured API + * sacrifices execution speed to ensure better interrupt responsiveness. + */ +#define xSemaphoreAltGive( xSemaphore ) xQueueAltGenericSend( ( QueueHandle_t ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK ) + +/** + * semphr. h + * 
+ xSemaphoreGiveFromISR(
+                          SemaphoreHandle_t xSemaphore,
+                          BaseType_t *pxHigherPriorityTaskWoken
+                      )
+ * + * Macro to release a semaphore. The semaphore must have previously been + * created with a call to vSemaphoreCreateBinary() or xSemaphoreCreateCounting(). + * + * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex()) + * must not be used with this macro. + * + * This macro can be used from an ISR. + * + * @param xSemaphore A handle to the semaphore being released. This is the + * handle returned when the semaphore was created. + * + * @param pxHigherPriorityTaskWoken xSemaphoreGiveFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if giving the semaphore caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xSemaphoreGiveFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @return pdTRUE if the semaphore was successfully given, otherwise errQUEUE_FULL. + * + * Example usage: + 
+ \#define LONG_TIME 0xffff
+ \#define TICKS_TO_WAIT	10
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ // Repetitive task.
+ void vATask( void * pvParameters )
+ {
+    for( ;; )
+    {
+        // We want this task to run every 10 ticks of a timer.  The semaphore
+        // was created before this task was started.
+
+        // Block waiting for the semaphore to become available.
+        if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )
+        {
+            // It is time to execute.
+
+            // ...
+
+            // We have finished our task.  Return to the top of the loop where
+            // we will block on the semaphore until it is time to execute
+            // again.  Note when using the semaphore for synchronisation with an
+			// ISR in this manner there is no need to 'give' the semaphore back.
+        }
+    }
+ }
+
+ // Timer ISR
+ void vTimerISR( void * pvParameters )
+ {
+ static uint8_t ucLocalTickCount = 0;
+ static BaseType_t xHigherPriorityTaskWoken;
+
+    // A timer tick has occurred.
+
+    // ... Do other time functions.
+
+    // Is it time for vATask () to run?
+	xHigherPriorityTaskWoken = pdFALSE;
+    ucLocalTickCount++;
+    if( ucLocalTickCount >= TICKS_TO_WAIT )
+    {
+        // Unblock the task by releasing the semaphore.
+        xSemaphoreGiveFromISR( xSemaphore, &xHigherPriorityTaskWoken );
+
+        // Reset the count so we release the semaphore again in 10 ticks time.
+        ucLocalTickCount = 0;
+    }
+
+    if( xHigherPriorityTaskWoken != pdFALSE )
+    {
+        // We can force a context switch here.  Context switching from an
+        // ISR uses port specific syntax.  Check the demo task for your port
+        // to find the syntax required.
+    }
+ }
+
+ * \defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR + * \ingroup Semaphores + */ +#define xSemaphoreGiveFromISR( xSemaphore, pxHigherPriorityTaskWoken ) xQueueGiveFromISR( ( QueueHandle_t ) ( xSemaphore ), ( pxHigherPriorityTaskWoken ) ) + +/** + * semphr. h + * 
+ xSemaphoreTakeFromISR(
+                          SemaphoreHandle_t xSemaphore,
+                          BaseType_t *pxHigherPriorityTaskWoken
+                      )
+ * + * Macro to take a semaphore from an ISR. The semaphore must have + * previously been created with a call to vSemaphoreCreateBinary() or + * xSemaphoreCreateCounting(). + * + * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex()) + * must not be used with this macro. + * + * This macro can be used from an ISR, however taking a semaphore from an ISR + * is not a common operation. It is likely to only be useful when taking a + * counting semaphore when an interrupt is obtaining an object from a resource + * pool (when the semaphore count indicates the number of resources available). + * + * @param xSemaphore A handle to the semaphore being taken. This is the + * handle returned when the semaphore was created. + * + * @param pxHigherPriorityTaskWoken xSemaphoreTakeFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if taking the semaphore caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xSemaphoreTakeFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @return pdTRUE if the semaphore was successfully taken, otherwise + * pdFALSE + */ +#define xSemaphoreTakeFromISR( xSemaphore, pxHigherPriorityTaskWoken ) xQueueReceiveFromISR( ( QueueHandle_t ) ( xSemaphore ), NULL, ( pxHigherPriorityTaskWoken ) ) + +/** + * semphr. h + * 
SemaphoreHandle_t xSemaphoreCreateMutex( void )
+ * + * Macro that implements a mutex semaphore by using the existing queue + * mechanism. + * + * Mutexes created using this macro can be accessed using the xSemaphoreTake() + * and xSemaphoreGive() macros. The xSemaphoreTakeRecursive() and + * xSemaphoreGiveRecursive() macros should not be used. + * + * This type of semaphore uses a priority inheritance mechanism so a task + * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the + * semaphore it is no longer required. + * + * Mutex type semaphores cannot be used from within interrupt service routines. + * + * See vSemaphoreCreateBinary() for an alternative implementation that can be + * used for pure synchronisation (where one task or interrupt always 'gives' the + * semaphore and another always 'takes' the semaphore) and from within interrupt + * service routines. + * + * @return xSemaphore Handle to the created mutex semaphore. Should be of type + * SemaphoreHandle_t. + * + * Example usage: + 
+ SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
+    // This is a macro so pass the variable in directly.
+    xSemaphore = xSemaphoreCreateMutex();
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+
+ * \defgroup vSemaphoreCreateMutex vSemaphoreCreateMutex + * \ingroup Semaphores + */ +#define xSemaphoreCreateMutex() xQueueCreateMutex( queueQUEUE_TYPE_MUTEX ) + + +/** + * semphr. h + * 
SemaphoreHandle_t xSemaphoreCreateRecursiveMutex( void )
+ * + * Macro that implements a recursive mutex by using the existing queue + * mechanism. + * + * Mutexes created using this macro can be accessed using the + * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros. The + * xSemaphoreTake() and xSemaphoreGive() macros should not be used. + * + * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex + * doesn't become available again until the owner has called + * xSemaphoreGiveRecursive() for each successful 'take' request. For example, + * if a task successfully 'takes' the same mutex 5 times then the mutex will + * not be available to any other task until it has also 'given' the mutex back + * exactly five times. + * + * This type of semaphore uses a priority inheritance mechanism so a task + * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the + * semaphore it is no longer required. + * + * Mutex type semaphores cannot be used from within interrupt service routines. + * + * See vSemaphoreCreateBinary() for an alternative implementation that can be + * used for pure synchronisation (where one task or interrupt always 'gives' the + * semaphore and another always 'takes' the semaphore) and from within interrupt + * service routines. + * + * @return xSemaphore Handle to the created mutex semaphore. Should be of type + * SemaphoreHandle_t. + * + * Example usage: + 
+ SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
+    // This is a macro so pass the variable in directly.
+    xSemaphore = xSemaphoreCreateRecursiveMutex();
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+
+ * \defgroup vSemaphoreCreateMutex vSemaphoreCreateMutex + * \ingroup Semaphores + */ +#define xSemaphoreCreateRecursiveMutex() xQueueCreateMutex( queueQUEUE_TYPE_RECURSIVE_MUTEX ) + +/** + * semphr. h + * 
SemaphoreHandle_t xSemaphoreCreateCounting( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount )
+ * + * Macro that creates a counting semaphore by using the existing + * queue mechanism. + * + * Counting semaphores are typically used for two things: + * + * 1) Counting events. + * + * In this usage scenario an event handler will 'give' a semaphore each time + * an event occurs (incrementing the semaphore count value), and a handler + * task will 'take' a semaphore each time it processes an event + * (decrementing the semaphore count value). The count value is therefore + * the difference between the number of events that have occurred and the + * number that have been processed. In this case it is desirable for the + * initial count value to be zero. + * + * 2) Resource management. + * + * In this usage scenario the count value indicates the number of resources + * available. To obtain control of a resource a task must first obtain a + * semaphore - decrementing the semaphore count value. When the count value + * reaches zero there are no free resources. When a task finishes with the + * resource it 'gives' the semaphore back - incrementing the semaphore count + * value. In this case it is desirable for the initial count value to be + * equal to the maximum count value, indicating that all resources are free. + * + * @param uxMaxCount The maximum count value that can be reached. When the + * semaphore reaches this value it can no longer be 'given'. + * + * @param uxInitialCount The count value assigned to the semaphore when it is + * created. + * + * @return Handle to the created semaphore. Null if the semaphore could not be + * created. + * + * Example usage: + 
+ SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+ SemaphoreHandle_t xSemaphore = NULL;
+
+    // Semaphore cannot be used before a call to xSemaphoreCreateCounting().
+    // The max value to which the semaphore can count should be 10, and the
+    // initial value assigned to the count should be 0.
+    xSemaphore = xSemaphoreCreateCounting( 10, 0 );
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+
+ * \defgroup xSemaphoreCreateCounting xSemaphoreCreateCounting + * \ingroup Semaphores + */ +#define xSemaphoreCreateCounting( uxMaxCount, uxInitialCount ) xQueueCreateCountingSemaphore( ( uxMaxCount ), ( uxInitialCount ) ) + +/** + * semphr. h + * 
void vSemaphoreDelete( SemaphoreHandle_t xSemaphore );
+ * + * Delete a semaphore. This function must be used with care. For example, + * do not delete a mutex type semaphore if the mutex is held by a task. + * + * @param xSemaphore A handle to the semaphore to be deleted. + * + * \defgroup vSemaphoreDelete vSemaphoreDelete + * \ingroup Semaphores + */ +#define vSemaphoreDelete( xSemaphore ) vQueueDelete( ( QueueHandle_t ) ( xSemaphore ) ) + +/** + * semphr.h + * 
TaskHandle_t xSemaphoreGetMutexHolder( SemaphoreHandle_t xMutex );
+ * + * If xMutex is indeed a mutex type semaphore, return the current mutex holder. + * If xMutex is not a mutex type semaphore, or the mutex is available (not held + * by a task), return NULL. + * + * Note: This is a good way of determining if the calling task is the mutex + * holder, but not a good way of determining the identity of the mutex holder as + * the holder may change between the function exiting and the returned value + * being tested. + */ +#define xSemaphoreGetMutexHolder( xSemaphore ) xQueueGetMutexHolder( ( xSemaphore ) ) + +#endif /* SEMAPHORE_H */ + + diff --git a/tools/sdk/include/freertos/freertos/task.h b/tools/sdk/include/freertos/freertos/task.h new file mode 100644 index 00000000..9f3f3d65 --- /dev/null +++ b/tools/sdk/include/freertos/freertos/task.h @@ -0,0 +1,2032 @@ +/* + FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + +#ifndef INC_TASK_H +#define INC_TASK_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include task.h" +#endif + +#include + +#include "list.h" +#include "portmacro.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * MACROS AND DEFINITIONS + *----------------------------------------------------------*/ + +#define tskKERNEL_VERSION_NUMBER "V8.2.0" +#define tskKERNEL_VERSION_MAJOR 8 +#define tskKERNEL_VERSION_MINOR 2 +#define tskKERNEL_VERSION_BUILD 0 + +#define tskNO_AFFINITY INT_MAX + +/** + * task. h + * + * Type by which tasks are referenced. For example, a call to xTaskCreate + * returns (via a pointer parameter) an TaskHandle_t variable that can then + * be used as a parameter to vTaskDelete to delete the task. + * + * \defgroup TaskHandle_t TaskHandle_t + * \ingroup Tasks + */ +typedef void * TaskHandle_t; + +/* + * Defines the prototype to which the application task hook function must + * conform. + */ +typedef BaseType_t (*TaskHookFunction_t)( void * ); + +/* Task states returned by eTaskGetState. */ +typedef enum +{ + eRunning = 0, /* A task is querying the state of itself, so must be running. */ + eReady, /* The task being queried is in a read or pending ready list. */ + eBlocked, /* The task being queried is in the Blocked state. */ + eSuspended, /* The task being queried is in the Suspended state, or is in the Blocked state with an infinite time out. */ + eDeleted /* The task being queried has been deleted, but its TCB has not yet been freed. */ +} eTaskState; + +/* Actions that can be performed when vTaskNotify() is called. */ +typedef enum +{ + eNoAction = 0, /* Notify the task without updating its notify value. */ + eSetBits, /* Set bits in the task's notification value. */ + eIncrement, /* Increment the task's notification value. */ + eSetValueWithOverwrite, /* Set the task's notification value to a specific value even if the previous value has not yet been read by the task. */ + eSetValueWithoutOverwrite /* Set the task's notification value if the previous value has been read by the task. */ +} eNotifyAction; + +/* + * Used internally only. + */ +typedef struct xTIME_OUT +{ + BaseType_t xOverflowCount; + TickType_t xTimeOnEntering; +} TimeOut_t; + +/* + * Defines the memory ranges allocated to the task when an MPU is used. + */ +typedef struct xMEMORY_REGION +{ + void *pvBaseAddress; + uint32_t ulLengthInBytes; + uint32_t ulParameters; +} MemoryRegion_t; + +/* + * Parameters required to create an MPU protected task. + */ +typedef struct xTASK_PARAMETERS +{ + TaskFunction_t pvTaskCode; + const char * const pcName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + uint16_t usStackDepth; + void *pvParameters; + UBaseType_t uxPriority; + StackType_t *puxStackBuffer; + MemoryRegion_t xRegions[ portNUM_CONFIGURABLE_REGIONS ]; +} TaskParameters_t; + +/* Used with the uxTaskGetSystemState() function to return the state of each task +in the system. */ +typedef struct xTASK_STATUS +{ + TaskHandle_t xHandle; /* The handle of the task to which the rest of the information in the structure relates. */ + const char *pcTaskName; /* A pointer to the task's name. This value will be invalid if the task was deleted since the structure was populated! */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + UBaseType_t xTaskNumber; /* A number unique to the task. */ + eTaskState eCurrentState; /* The state in which the task existed when the structure was populated. */ + UBaseType_t uxCurrentPriority; /* The priority at which the task was running (may be inherited) when the structure was populated. */ + UBaseType_t uxBasePriority; /* The priority to which the task will return if the task's current priority has been inherited to avoid unbounded priority inversion when obtaining a mutex. Only valid if configUSE_MUTEXES is defined as 1 in FreeRTOSConfig.h. */ + uint32_t ulRunTimeCounter; /* The total run time allocated to the task so far, as defined by the run time stats clock. See http://www.freertos.org/rtos-run-time-stats.html. Only valid when configGENERATE_RUN_TIME_STATS is defined as 1 in FreeRTOSConfig.h. */ + uint16_t usStackHighWaterMark; /* The minimum amount of stack space that has remained for the task since the task was created. The closer this value is to zero the closer the task has come to overflowing its stack. */ +} TaskStatus_t; + +/* Possible return values for eTaskConfirmSleepModeStatus(). */ +typedef enum +{ + eAbortSleep = 0, /* A task has been made ready or a context switch pended since portSUPPORESS_TICKS_AND_SLEEP() was called - abort entering a sleep mode. */ + eStandardSleep, /* Enter a sleep mode that will not last any longer than the expected idle time. */ + eNoTasksWaitingTimeout /* No tasks are waiting for a timeout so it is safe to enter a sleep mode that can only be exited by an external interrupt. */ +} eSleepModeStatus; + + +/** + * Defines the priority used by the idle task. This must not be modified. + * + * \ingroup TaskUtils + */ +#define tskIDLE_PRIORITY ( ( UBaseType_t ) 0U ) + +/** + * task. h + * + * Macro for forcing a context switch. + * + * \defgroup taskYIELD taskYIELD + * \ingroup SchedulerControl + */ +#define taskYIELD() portYIELD() + +/** + * task. h + * + * Macro to mark the start of a critical code region. Preemptive context + * switches cannot occur when in a critical region. + * + * NOTE: This may alter the stack (depending on the portable implementation) + * so must be used with care! + * + * \defgroup taskENTER_CRITICAL taskENTER_CRITICAL + * \ingroup SchedulerControl + */ +#define taskENTER_CRITICAL(mux) portENTER_CRITICAL(mux) +#define taskENTER_CRITICAL_ISR(mux) portENTER_CRITICAL_ISR(mux) + +/** + * task. h + * + * Macro to mark the end of a critical code region. Preemptive context + * switches cannot occur when in a critical region. + * + * NOTE: This may alter the stack (depending on the portable implementation) + * so must be used with care! + * + * \defgroup taskEXIT_CRITICAL taskEXIT_CRITICAL + * \ingroup SchedulerControl + */ +#define taskEXIT_CRITICAL(mux) portEXIT_CRITICAL(mux) +#define taskEXIT_CRITICAL_ISR(mux) portEXIT_CRITICAL_ISR(mux) + +/** + * task. h + * + * Macro to disable all maskable interrupts. + * + * \defgroup taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS + * \ingroup SchedulerControl + */ +#define taskDISABLE_INTERRUPTS() portDISABLE_INTERRUPTS() + +/** + * task. h + * + * Macro to enable microcontroller interrupts. + * + * \defgroup taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS + * \ingroup SchedulerControl + */ +#define taskENABLE_INTERRUPTS() portENABLE_INTERRUPTS() + +/* Definitions returned by xTaskGetSchedulerState(). taskSCHEDULER_SUSPENDED is +0 to generate more optimal code when configASSERT() is defined as the constant +is used in assert() statements. */ +#define taskSCHEDULER_SUSPENDED ( ( BaseType_t ) 0 ) +#define taskSCHEDULER_NOT_STARTED ( ( BaseType_t ) 1 ) +#define taskSCHEDULER_RUNNING ( ( BaseType_t ) 2 ) + + +/*----------------------------------------------------------- + * TASK CREATION API + *----------------------------------------------------------*/ + +/** + * task. h + *
+ BaseType_t xTaskCreate(
+							  TaskFunction_t pvTaskCode,
+							  const char * const pcName,
+							  uint16_t usStackDepth,
+							  void *pvParameters,
+							  UBaseType_t uxPriority,
+							  TaskHandle_t *pvCreatedTask
+						  );
+ * + * Create a new task and add it to the list of tasks that are ready to run. + * On multicore environments, this will give no specific affinity to the task. + * Use xTaskCreatePinnedToCore to give affinity. + * + * xTaskCreate() can only be used to create a task that has unrestricted + * access to the entire microcontroller memory map. Systems that include MPU + * support can alternatively create an MPU constrained task using + * xTaskCreateRestricted(). + * + * @param pvTaskCode Pointer to the task entry function. Tasks + * must be implemented to never return (i.e. continuous loop). + * + * @param pcName A descriptive name for the task. This is mainly used to + * facilitate debugging. Max length defined by configMAX_TASK_NAME_LEN - default + * is 16. + * + * @param usStackDepth The size of the task stack specified as the number of + * variables the stack can hold - not the number of bytes. For example, if + * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes + * will be allocated for stack storage. + * + * @param pvParameters Pointer that will be used as the parameter for the task + * being created. + * + * @param uxPriority The priority at which the task should run. Systems that + * include MPU support can optionally create tasks in a privileged (system) + * mode by setting bit portPRIVILEGE_BIT of the priority parameter. For + * example, to create a privileged task at priority 2 the uxPriority parameter + * should be set to ( 2 | portPRIVILEGE_BIT ). + * + * @param pvCreatedTask Used to pass back a handle by which the created task + * can be referenced. + * + * @return pdPASS if the task was successfully created and added to a ready + * list, otherwise an error code defined in the file projdefs.h + * + * Example usage: + 
+ // Task to be created.
+ void vTaskCode( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+	 }
+ }
+
+ // Function that creates a task.
+ void vOtherFunction( void )
+ {
+ static uint8_t ucParameterToPass;
+ TaskHandle_t xHandle = NULL;
+
+	 // Create the task, storing the handle.  Note that the passed parameter ucParameterToPass
+	 // must exist for the lifetime of the task, so in this case is declared static.  If it was just an
+	 // an automatic stack variable it might no longer exist, or at least have been corrupted, by the time
+	 // the new task attempts to access it.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle );
+     configASSERT( xHandle );
+
+	 // Use the handle to delete the task.
+     if( xHandle != NULL )
+     {
+	     vTaskDelete( xHandle );
+     }
+ }
+
+ * \defgroup xTaskCreate xTaskCreate + * \ingroup Tasks + */ +#define xTaskCreate( pvTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask ) xTaskGenericCreate( ( pvTaskCode ), ( pcName ), ( usStackDepth ), ( pvParameters ), ( uxPriority ), ( pxCreatedTask ), ( NULL ), ( NULL ), tskNO_AFFINITY ) +#define xTaskCreatePinnedToCore( pvTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask, xCoreID ) xTaskGenericCreate( ( pvTaskCode ), ( pcName ), ( usStackDepth ), ( pvParameters ), ( uxPriority ), ( pxCreatedTask ), ( NULL ), ( NULL ), xCoreID ) + +/** + * task. h + *
+ BaseType_t xTaskCreateRestricted( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );
+ * + * xTaskCreateRestricted() should only be used in systems that include an MPU + * implementation. + * + * Create a new task and add it to the list of tasks that are ready to run. + * The function parameters define the memory regions and associated access + * permissions allocated to the task. + * + * @param pxTaskDefinition Pointer to a structure that contains a member + * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API + * documentation) plus an optional stack buffer and the memory region + * definitions. + * + * @param pxCreatedTask Used to pass back a handle by which the created task + * can be referenced. + * + * @return pdPASS if the task was successfully created and added to a ready + * list, otherwise an error code defined in the file projdefs.h + * + * Example usage: + 
+// Create an TaskParameters_t structure that defines the task to be created.
+static const TaskParameters_t xCheckTaskParameters =
+{
+	vATask,		// pvTaskCode - the function that implements the task.
+	"ATask",	// pcName - just a text name for the task to assist debugging.
+	100,		// usStackDepth	- the stack size DEFINED IN WORDS.
+	NULL,		// pvParameters - passed into the task function as the function parameters.
+	( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
+	cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
+
+	// xRegions - Allocate up to three separate memory regions for access by
+	// the task, with appropriate access permissions.  Different processors have
+	// different memory alignment requirements - refer to the FreeRTOS documentation
+	// for full information.
+	{
+		// Base address					Length	Parameters
+        { cReadWriteArray,				32,		portMPU_REGION_READ_WRITE },
+        { cReadOnlyArray,				32,		portMPU_REGION_READ_ONLY },
+        { cPrivilegedOnlyAccessArray,	128,	portMPU_REGION_PRIVILEGED_READ_WRITE }
+	}
+};
+
+int main( void )
+{
+TaskHandle_t xHandle;
+
+	// Create a task from the const structure defined above.  The task handle
+	// is requested (the second parameter is not NULL) but in this case just for
+	// demonstration purposes as its not actually used.
+	xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
+
+	// Start the scheduler.
+	vTaskStartScheduler();
+
+	// Will only get here if there was insufficient memory to create the idle
+	// and/or timer task.
+	for( ;; );
+}
+
+ * \defgroup xTaskCreateRestricted xTaskCreateRestricted + * \ingroup Tasks + */ +#define xTaskCreateRestricted( x, pxCreatedTask ) xTaskGenericCreate( ((x)->pvTaskCode), ((x)->pcName), ((x)->usStackDepth), ((x)->pvParameters), ((x)->uxPriority), (pxCreatedTask), ((x)->puxStackBuffer), ((x)->xRegions) ) + +/** + * task. h + *
+ void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions );
+ * + * Memory regions are assigned to a restricted task when the task is created by + * a call to xTaskCreateRestricted(). These regions can be redefined using + * vTaskAllocateMPURegions(). + * + * @param xTask The handle of the task being updated. + * + * @param xRegions A pointer to an MemoryRegion_t structure that contains the + * new memory region definitions. + * + * Example usage: + 
+// Define an array of MemoryRegion_t structures that configures an MPU region
+// allowing read/write access for 1024 bytes starting at the beginning of the
+// ucOneKByte array.  The other two of the maximum 3 definable regions are
+// unused so set to zero.
+static const MemoryRegion_t xAltRegions[ portNUM_CONFIGURABLE_REGIONS ] =
+{
+	// Base address		Length		Parameters
+	{ ucOneKByte,		1024,		portMPU_REGION_READ_WRITE },
+	{ 0,				0,			0 },
+	{ 0,				0,			0 }
+};
+
+void vATask( void *pvParameters )
+{
+	// This task was created such that it has access to certain regions of
+	// memory as defined by the MPU configuration.  At some point it is
+	// desired that these MPU regions are replaced with that defined in the
+	// xAltRegions const struct above.  Use a call to vTaskAllocateMPURegions()
+	// for this purpose.  NULL is used as the task handle to indicate that this
+	// function should modify the MPU regions of the calling task.
+	vTaskAllocateMPURegions( NULL, xAltRegions );
+
+	// Now the task can continue its function, but from this point on can only
+	// access its stack and the ucOneKByte array (unless any other statically
+	// defined or shared regions have been declared elsewhere).
+}
+
+ * \defgroup xTaskCreateRestricted xTaskCreateRestricted + * \ingroup Tasks + */ +void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
void vTaskDelete( TaskHandle_t xTask );
+ * + * INCLUDE_vTaskDelete must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Remove a task from the RTOS real time kernel's management. The task being + * deleted will be removed from all ready, blocked, suspended and event lists. + * + * NOTE: The idle task is responsible for freeing the kernel allocated + * memory from tasks that have been deleted. It is therefore important that + * the idle task is not starved of microcontroller processing time if your + * application makes any calls to vTaskDelete (). Memory allocated by the + * task code is not automatically freed, and should be freed before the task + * is deleted. + * + * See the demo application file death.c for sample code that utilises + * vTaskDelete (). + * + * @param xTask The handle of the task to be deleted. Passing NULL will + * cause the calling task to be deleted. + * + * Example usage: + 
+ void vOtherFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create the task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // Use the handle to delete the task.
+	 vTaskDelete( xHandle );
+ }
+
+ * \defgroup vTaskDelete vTaskDelete + * \ingroup Tasks + */ +void vTaskDelete( TaskHandle_t xTaskToDelete ) PRIVILEGED_FUNCTION; + +/*----------------------------------------------------------- + * TASK CONTROL API + *----------------------------------------------------------*/ + +/** + * task. h + * 
void vTaskDelay( const TickType_t xTicksToDelay );
+ * + * Delay a task for a given number of ticks. The actual time that the + * task remains blocked depends on the tick rate. The constant + * portTICK_PERIOD_MS can be used to calculate real time from the tick + * rate - with the resolution of one tick period. + * + * INCLUDE_vTaskDelay must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * + * vTaskDelay() specifies a time at which the task wishes to unblock relative to + * the time at which vTaskDelay() is called. For example, specifying a block + * period of 100 ticks will cause the task to unblock 100 ticks after + * vTaskDelay() is called. vTaskDelay() does not therefore provide a good method + * of controlling the frequency of a periodic task as the path taken through the + * code, as well as other task and interrupt activity, will effect the frequency + * at which vTaskDelay() gets called and therefore the time at which the task + * next executes. See vTaskDelayUntil() for an alternative API function designed + * to facilitate fixed frequency execution. It does this by specifying an + * absolute time (rather than a relative time) at which the calling task should + * unblock. + * + * @param xTicksToDelay The amount of time, in tick periods, that + * the calling task should block. + * + * Example usage: + + void vTaskFunction( void * pvParameters ) + { + // Block for 500ms. + const TickType_t xDelay = 500 / portTICK_PERIOD_MS; + + for( ;; ) + { + // Simply toggle the LED every 500ms, blocking between each toggle. + vToggleLED(); + vTaskDelay( xDelay ); + } + } + + * \defgroup vTaskDelay vTaskDelay + * \ingroup TaskCtrl + */ +void vTaskDelay( const TickType_t xTicksToDelay ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
void vTaskDelayUntil( TickType_t *pxPreviousWakeTime, const TickType_t xTimeIncrement );
+ * + * INCLUDE_vTaskDelayUntil must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Delay a task until a specified time. This function can be used by periodic + * tasks to ensure a constant execution frequency. + * + * This function differs from vTaskDelay () in one important aspect: vTaskDelay () will + * cause a task to block for the specified number of ticks from the time vTaskDelay () is + * called. It is therefore difficult to use vTaskDelay () by itself to generate a fixed + * execution frequency as the time between a task starting to execute and that task + * calling vTaskDelay () may not be fixed [the task may take a different path though the + * code between calls, or may get interrupted or preempted a different number of times + * each time it executes]. + * + * Whereas vTaskDelay () specifies a wake time relative to the time at which the function + * is called, vTaskDelayUntil () specifies the absolute (exact) time at which it wishes to + * unblock. + * + * The constant portTICK_PERIOD_MS can be used to calculate real time from the tick + * rate - with the resolution of one tick period. + * + * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the + * task was last unblocked. The variable must be initialised with the current time + * prior to its first use (see the example below). Following this the variable is + * automatically updated within vTaskDelayUntil (). + * + * @param xTimeIncrement The cycle time period. The task will be unblocked at + * time *pxPreviousWakeTime + xTimeIncrement. Calling vTaskDelayUntil with the + * same xTimeIncrement parameter value will cause the task to execute with + * a fixed interface period. + * + * Example usage: + 
+ // Perform an action every 10 ticks.
+ void vTaskFunction( void * pvParameters )
+ {
+ TickType_t xLastWakeTime;
+ const TickType_t xFrequency = 10;
+
+	 // Initialise the xLastWakeTime variable with the current time.
+	 xLastWakeTime = xTaskGetTickCount ();
+	 for( ;; )
+	 {
+		 // Wait for the next cycle.
+		 vTaskDelayUntil( &xLastWakeTime, xFrequency );
+
+		 // Perform action here.
+	 }
+ }
+
+ * \defgroup vTaskDelayUntil vTaskDelayUntil + * \ingroup TaskCtrl + */ +void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
UBaseType_t uxTaskPriorityGet( TaskHandle_t xTask );
+ * + * INCLUDE_uxTaskPriorityGet must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Obtain the priority of any task. + * + * @param xTask Handle of the task to be queried. Passing a NULL + * handle results in the priority of the calling task being returned. + * + * @return The priority of xTask. + * + * Example usage: + 
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to obtain the priority of the created task.
+	 // It was created with tskIDLE_PRIORITY, but may have changed
+	 // it itself.
+	 if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )
+	 {
+		 // The task has changed it's priority.
+	 }
+
+	 // ...
+
+	 // Is our priority higher than the created task?
+	 if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )
+	 {
+		 // Our priority (obtained using NULL handle) is higher.
+	 }
+ }
+
+ * \defgroup uxTaskPriorityGet uxTaskPriorityGet + * \ingroup TaskCtrl + */ +UBaseType_t uxTaskPriorityGet( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
UBaseType_t uxTaskPriorityGetFromISR( TaskHandle_t xTask );
+ * + * A version of uxTaskPriorityGet() that can be used from an ISR. + */ +UBaseType_t uxTaskPriorityGetFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
eTaskState eTaskGetState( TaskHandle_t xTask );
+ * + * INCLUDE_eTaskGetState must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Obtain the state of any task. States are encoded by the eTaskState + * enumerated type. + * + * @param xTask Handle of the task to be queried. + * + * @return The state of xTask at the time the function was called. Note the + * state of the task might change between the function being called, and the + * functions return value being tested by the calling task. + */ +eTaskState eTaskGetState( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority );
+ * + * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Set the priority of any task. + * + * A context switch will occur before the function returns if the priority + * being set is higher than the currently executing task. + * + * @param xTask Handle to the task for which the priority is being set. + * Passing a NULL handle results in the priority of the calling task being set. + * + * @param uxNewPriority The priority to which the task will be set. + * + * Example usage: + 
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to raise the priority of the created task.
+	 vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );
+
+	 // ...
+
+	 // Use a NULL handle to raise our priority to the same value.
+	 vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );
+ }
+
+ * \defgroup vTaskPrioritySet vTaskPrioritySet + * \ingroup TaskCtrl + */ +void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
void vTaskSuspend( TaskHandle_t xTaskToSuspend );
+ * + * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Suspend any task. When suspended a task will never get any microcontroller + * processing time, no matter what its priority. + * + * Calls to vTaskSuspend are not accumulative - + * i.e. calling vTaskSuspend () twice on the same task still only requires one + * call to vTaskResume () to ready the suspended task. + * + * @param xTaskToSuspend Handle to the task being suspended. Passing a NULL + * handle will cause the calling task to be suspended. + * + * Example usage: + 
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to suspend the created task.
+	 vTaskSuspend( xHandle );
+
+	 // ...
+
+	 // The created task will not run during this period, unless
+	 // another task calls vTaskResume( xHandle ).
+
+	 //...
+
+
+	 // Suspend ourselves.
+	 vTaskSuspend( NULL );
+
+	 // We cannot get here unless another task calls vTaskResume
+	 // with our handle as the parameter.
+ }
+
+ * \defgroup vTaskSuspend vTaskSuspend + * \ingroup TaskCtrl + */ +void vTaskSuspend( TaskHandle_t xTaskToSuspend ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
void vTaskResume( TaskHandle_t xTaskToResume );
+ * + * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Resumes a suspended task. + * + * A task that has been suspended by one or more calls to vTaskSuspend () + * will be made available for running again by a single call to + * vTaskResume (). + * + * @param xTaskToResume Handle to the task being readied. + * + * Example usage: + 
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to suspend the created task.
+	 vTaskSuspend( xHandle );
+
+	 // ...
+
+	 // The created task will not run during this period, unless
+	 // another task calls vTaskResume( xHandle ).
+
+	 //...
+
+
+	 // Resume the suspended task ourselves.
+	 vTaskResume( xHandle );
+
+	 // The created task will once again get microcontroller processing
+	 // time in accordance with its priority within the system.
+ }
+
+ * \defgroup vTaskResume vTaskResume + * \ingroup TaskCtrl + */ +void vTaskResume( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
void xTaskResumeFromISR( TaskHandle_t xTaskToResume );
+ * + * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be + * available. See the configuration section for more information. + * + * An implementation of vTaskResume() that can be called from within an ISR. + * + * A task that has been suspended by one or more calls to vTaskSuspend () + * will be made available for running again by a single call to + * xTaskResumeFromISR (). + * + * xTaskResumeFromISR() should not be used to synchronise a task with an + * interrupt if there is a chance that the interrupt could arrive prior to the + * task being suspended - as this can lead to interrupts being missed. Use of a + * semaphore as a synchronisation mechanism would avoid this eventuality. + * + * @param xTaskToResume Handle to the task being readied. + * + * @return pdTRUE if resuming the task should result in a context switch, + * otherwise pdFALSE. This is used by the ISR to determine if a context switch + * may be required following the ISR. + * + * \defgroup vTaskResumeFromISR vTaskResumeFromISR + * \ingroup TaskCtrl + */ +BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION; + +/*----------------------------------------------------------- + * SCHEDULER CONTROL + *----------------------------------------------------------*/ + +/** + * task. h + * 
void vTaskStartScheduler( void );
+ * + * Starts the real time kernel tick processing. After calling the kernel + * has control over which tasks are executed and when. + * + * See the demo application file main.c for an example of creating + * tasks and starting the kernel. + * + * Example usage: + 
+ void vAFunction( void )
+ {
+	 // Create at least one task before starting the kernel.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+
+	 // Start the real time kernel with preemption.
+	 vTaskStartScheduler ();
+
+	 // Will not get here unless a task calls vTaskEndScheduler ()
+ }
+
+ * + * \defgroup vTaskStartScheduler vTaskStartScheduler + * \ingroup SchedulerControl + */ +void vTaskStartScheduler( void ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
void vTaskEndScheduler( void );
+ * + * NOTE: At the time of writing only the x86 real mode port, which runs on a PC + * in place of DOS, implements this function. + * + * Stops the real time kernel tick. All created tasks will be automatically + * deleted and multitasking (either preemptive or cooperative) will + * stop. Execution then resumes from the point where vTaskStartScheduler () + * was called, as if vTaskStartScheduler () had just returned. + * + * See the demo application file main. c in the demo/PC directory for an + * example that uses vTaskEndScheduler (). + * + * vTaskEndScheduler () requires an exit function to be defined within the + * portable layer (see vPortEndScheduler () in port. c for the PC port). This + * performs hardware specific operations such as stopping the kernel tick. + * + * vTaskEndScheduler () will cause all of the resources allocated by the + * kernel to be freed - but will not free resources allocated by application + * tasks. + * + * Example usage: + 
+ void vTaskCode( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+
+		 // At some point we want to end the real time kernel processing
+		 // so call ...
+		 vTaskEndScheduler ();
+	 }
+ }
+
+ void vAFunction( void )
+ {
+	 // Create at least one task before starting the kernel.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+
+	 // Start the real time kernel with preemption.
+	 vTaskStartScheduler ();
+
+	 // Will only get here when the vTaskCode () task has called
+	 // vTaskEndScheduler ().  When we get here we are back to single task
+	 // execution.
+ }
+
+ * + * \defgroup vTaskEndScheduler vTaskEndScheduler + * \ingroup SchedulerControl + */ +void vTaskEndScheduler( void ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
void vTaskSuspendAll( void );
+ * + * Suspends the scheduler without disabling interrupts. Context switches will + * not occur while the scheduler is suspended. + * + * After calling vTaskSuspendAll () the calling task will continue to execute + * without risk of being swapped out until a call to xTaskResumeAll () has been + * made. + * + * API functions that have the potential to cause a context switch (for example, + * vTaskDelayUntil(), xQueueSend(), etc.) must not be called while the scheduler + * is suspended. + * + * Example usage: + 
+ void vTask1( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+
+		 // ...
+
+		 // At some point the task wants to perform a long operation during
+		 // which it does not want to get swapped out.  It cannot use
+		 // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
+		 // operation may cause interrupts to be missed - including the
+		 // ticks.
+
+		 // Prevent the real time kernel swapping out the task.
+		 vTaskSuspendAll ();
+
+		 // Perform the operation here.  There is no need to use critical
+		 // sections as we have all the microcontroller processing time.
+		 // During this time interrupts will still operate and the kernel
+		 // tick count will be maintained.
+
+		 // ...
+
+		 // The operation is complete.  Restart the kernel.
+		 xTaskResumeAll ();
+	 }
+ }
+
+ * \defgroup vTaskSuspendAll vTaskSuspendAll + * \ingroup SchedulerControl + */ +void vTaskSuspendAll( void ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
BaseType_t xTaskResumeAll( void );
+ * + * Resumes scheduler activity after it was suspended by a call to + * vTaskSuspendAll(). + * + * xTaskResumeAll() only resumes the scheduler. It does not unsuspend tasks + * that were previously suspended by a call to vTaskSuspend(). + * + * @return If resuming the scheduler caused a context switch then pdTRUE is + * returned, otherwise pdFALSE is returned. + * + * Example usage: + 
+ void vTask1( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+
+		 // ...
+
+		 // At some point the task wants to perform a long operation during
+		 // which it does not want to get swapped out.  It cannot use
+		 // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
+		 // operation may cause interrupts to be missed - including the
+		 // ticks.
+
+		 // Prevent the real time kernel swapping out the task.
+		 vTaskSuspendAll ();
+
+		 // Perform the operation here.  There is no need to use critical
+		 // sections as we have all the microcontroller processing time.
+		 // During this time interrupts will still operate and the real
+		 // time kernel tick count will be maintained.
+
+		 // ...
+
+		 // The operation is complete.  Restart the kernel.  We want to force
+		 // a context switch - but there is no point if resuming the scheduler
+		 // caused a context switch already.
+		 if( !xTaskResumeAll () )
+		 {
+			  taskYIELD ();
+		 }
+	 }
+ }
+
+ * \defgroup xTaskResumeAll xTaskResumeAll + * \ingroup SchedulerControl + */ +BaseType_t xTaskResumeAll( void ) PRIVILEGED_FUNCTION; + +/*----------------------------------------------------------- + * TASK UTILITIES + *----------------------------------------------------------*/ + +/** + * task. h + * 
TickType_t xTaskGetTickCount( void );
+ * + * @return The count of ticks since vTaskStartScheduler was called. + * + * \defgroup xTaskGetTickCount xTaskGetTickCount + * \ingroup TaskUtils + */ +TickType_t xTaskGetTickCount( void ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
TickType_t xTaskGetTickCountFromISR( void );
+ * + * @return The count of ticks since vTaskStartScheduler was called. + * + * This is a version of xTaskGetTickCount() that is safe to be called from an + * ISR - provided that TickType_t is the natural word size of the + * microcontroller being used or interrupt nesting is either not supported or + * not being used. + * + * \defgroup xTaskGetTickCountFromISR xTaskGetTickCountFromISR + * \ingroup TaskUtils + */ +TickType_t xTaskGetTickCountFromISR( void ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
uint16_t uxTaskGetNumberOfTasks( void );
+ * + * @return The number of tasks that the real time kernel is currently managing. + * This includes all ready, blocked and suspended tasks. A task that + * has been deleted but not yet freed by the idle task will also be + * included in the count. + * + * \defgroup uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks + * \ingroup TaskUtils + */ +UBaseType_t uxTaskGetNumberOfTasks( void ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
char *pcTaskGetTaskName( TaskHandle_t xTaskToQuery );
+ * + * @return The text (human readable) name of the task referenced by the handle + * xTaskToQuery. A task can query its own name by either passing in its own + * handle, or by setting xTaskToQuery to NULL. INCLUDE_pcTaskGetTaskName must be + * set to 1 in FreeRTOSConfig.h for pcTaskGetTaskName() to be available. + * + * \defgroup pcTaskGetTaskName pcTaskGetTaskName + * \ingroup TaskUtils + */ +char *pcTaskGetTaskName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + +/** + * task.h + * 
UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask );
+ * + * INCLUDE_uxTaskGetStackHighWaterMark must be set to 1 in FreeRTOSConfig.h for + * this function to be available. + * + * Returns the high water mark of the stack associated with xTask. That is, + * the minimum free stack space there has been (in words, so on a 32 bit machine + * a value of 1 means 4 bytes) since the task started. The smaller the returned + * number the closer the task has come to overflowing its stack. + * + * @param xTask Handle of the task associated with the stack to be checked. + * Set xTask to NULL to check the stack of the calling task. + * + * @return The smallest amount of free stack space there has been (in words, so + * actual spaces on the stack rather than bytes) since the task referenced by + * xTask was created. + */ +UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +/* When using trace macros it is sometimes necessary to include task.h before +FreeRTOS.h. When this is done TaskHookFunction_t will not yet have been defined, +so the following two prototypes will cause a compilation error. This can be +fixed by simply guarding against the inclusion of these two prototypes unless +they are explicitly required by the configUSE_APPLICATION_TASK_TAG configuration +constant. */ +#ifdef configUSE_APPLICATION_TASK_TAG + #if configUSE_APPLICATION_TASK_TAG == 1 + /** + * task.h + * 
void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction );
+ * + * Sets pxHookFunction to be the task hook function used by the task xTask. + * Passing xTask as NULL has the effect of setting the calling tasks hook + * function. + */ + void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) PRIVILEGED_FUNCTION; + + /** + * task.h + * 
void xTaskGetApplicationTaskTag( TaskHandle_t xTask );
+ * + * Returns the pxHookFunction value assigned to the task xTask. + */ + TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + #endif /* configUSE_APPLICATION_TASK_TAG ==1 */ +#endif /* ifdef configUSE_APPLICATION_TASK_TAG */ +#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 ) + + /* Each task contains an array of pointers that is dimensioned by the + configNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h. The + kernel does not use the pointers itself, so the application writer can use + the pointers for any purpose they wish. The following two functions are + used to set and query a pointer respectively. */ + void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) PRIVILEGED_FUNCTION; + void *pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) PRIVILEGED_FUNCTION; + + #if ( configTHREAD_LOCAL_STORAGE_DELETE_CALLBACKS ) + typedef void (*TlsDeleteCallbackFunction_t)( int, void * ); + void vTaskSetThreadLocalStoragePointerAndDelCallback( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue , TlsDeleteCallbackFunction_t xDelCallback); + #endif + +#endif + +/** + * task.h + * 
BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter );
+ * + * Calls the hook function associated with xTask. Passing xTask as NULL has + * the effect of calling the Running tasks (the calling task) hook function. + * + * pvParameter is passed to the hook function for the task to interpret as it + * wants. The return value is the value returned by the task hook function + * registered by the user. + */ +BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) PRIVILEGED_FUNCTION; + +/** + * xTaskGetIdleTaskHandle() is only available if + * INCLUDE_xTaskGetIdleTaskHandle is set to 1 in FreeRTOSConfig.h. + * + * Simply returns the handle of the idle task. It is not valid to call + * xTaskGetIdleTaskHandle() before the scheduler has been started. + */ +TaskHandle_t xTaskGetIdleTaskHandle( void ); + +/** + * configUSE_TRACE_FACILITY must be defined as 1 in FreeRTOSConfig.h for + * uxTaskGetSystemState() to be available. + * + * uxTaskGetSystemState() populates an TaskStatus_t structure for each task in + * the system. TaskStatus_t structures contain, among other things, members + * for the task handle, task name, task priority, task state, and total amount + * of run time consumed by the task. See the TaskStatus_t structure + * definition in this file for the full member list. + * + * NOTE: This function is intended for debugging use only as its use results in + * the scheduler remaining suspended for an extended period. + * + * @param pxTaskStatusArray A pointer to an array of TaskStatus_t structures. + * The array must contain at least one TaskStatus_t structure for each task + * that is under the control of the RTOS. The number of tasks under the control + * of the RTOS can be determined using the uxTaskGetNumberOfTasks() API function. + * + * @param uxArraySize The size of the array pointed to by the pxTaskStatusArray + * parameter. The size is specified as the number of indexes in the array, or + * the number of TaskStatus_t structures contained in the array, not by the + * number of bytes in the array. + * + * @param pulTotalRunTime If configGENERATE_RUN_TIME_STATS is set to 1 in + * FreeRTOSConfig.h then *pulTotalRunTime is set by uxTaskGetSystemState() to the + * total run time (as defined by the run time stats clock, see + * http://www.freertos.org/rtos-run-time-stats.html) since the target booted. + * pulTotalRunTime can be set to NULL to omit the total run time information. + * + * @return The number of TaskStatus_t structures that were populated by + * uxTaskGetSystemState(). This should equal the number returned by the + * uxTaskGetNumberOfTasks() API function, but will be zero if the value passed + * in the uxArraySize parameter was too small. + * + * Example usage: + 
+    // This example demonstrates how a human readable table of run time stats
+	// information is generated from raw data provided by uxTaskGetSystemState().
+	// The human readable table is written to pcWriteBuffer
+	void vTaskGetRunTimeStats( char *pcWriteBuffer )
+	{
+	TaskStatus_t *pxTaskStatusArray;
+	volatile UBaseType_t uxArraySize, x;
+	uint32_t ulTotalRunTime, ulStatsAsPercentage;
+
+		// Make sure the write buffer does not contain a string.
+		*pcWriteBuffer = 0x00;
+
+		// Take a snapshot of the number of tasks in case it changes while this
+		// function is executing.
+		uxArraySize = uxTaskGetNumberOfTasks();
+
+		// Allocate a TaskStatus_t structure for each task.  An array could be
+		// allocated statically at compile time.
+		pxTaskStatusArray = pvPortMalloc( uxArraySize * sizeof( TaskStatus_t ) );
+
+		if( pxTaskStatusArray != NULL )
+		{
+			// Generate raw status information about each task.
+			uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalRunTime );
+
+			// For percentage calculations.
+			ulTotalRunTime /= 100UL;
+
+			// Avoid divide by zero errors.
+			if( ulTotalRunTime > 0 )
+			{
+				// For each populated position in the pxTaskStatusArray array,
+				// format the raw data as human readable ASCII data
+				for( x = 0; x < uxArraySize; x++ )
+				{
+					// What percentage of the total run time has the task used?
+					// This will always be rounded down to the nearest integer.
+					// ulTotalRunTimeDiv100 has already been divided by 100.
+					ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalRunTime;
+
+					if( ulStatsAsPercentage > 0UL )
+					{
+						sprintf( pcWriteBuffer, "%s\t\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
+					}
+					else
+					{
+						// If the percentage is zero here then the task has
+						// consumed less than 1% of the total run time.
+						sprintf( pcWriteBuffer, "%s\t\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter );
+					}
+
+					pcWriteBuffer += strlen( ( char * ) pcWriteBuffer );
+				}
+			}
+
+			// The array is no longer needed, free the memory it consumes.
+			vPortFree( pxTaskStatusArray );
+		}
+	}
+
+ */ +UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime ); + +/** + * task. h + * 
void vTaskList( char *pcWriteBuffer );
+ * + * configUSE_TRACE_FACILITY and configUSE_STATS_FORMATTING_FUNCTIONS must + * both be defined as 1 for this function to be available. See the + * configuration section of the FreeRTOS.org website for more information. + * + * NOTE 1: This function will disable interrupts for its duration. It is + * not intended for normal application runtime use but as a debug aid. + * + * Lists all the current tasks, along with their current state and stack + * usage high water mark. + * + * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or + * suspended ('S'). + * + * PLEASE NOTE: + * + * This function is provided for convenience only, and is used by many of the + * demo applications. Do not consider it to be part of the scheduler. + * + * vTaskList() calls uxTaskGetSystemState(), then formats part of the + * uxTaskGetSystemState() output into a human readable table that displays task + * names, states and stack usage. + * + * vTaskList() has a dependency on the sprintf() C library function that might + * bloat the code size, use a lot of stack, and provide different results on + * different platforms. An alternative, tiny, third party, and limited + * functionality implementation of sprintf() is provided in many of the + * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note + * printf-stdarg.c does not provide a full snprintf() implementation!). + * + * It is recommended that production systems call uxTaskGetSystemState() + * directly to get access to raw stats data, rather than indirectly through a + * call to vTaskList(). + * + * @param pcWriteBuffer A buffer into which the above mentioned details + * will be written, in ASCII form. This buffer is assumed to be large + * enough to contain the generated report. Approximately 40 bytes per + * task should be sufficient. + * + * \defgroup vTaskList vTaskList + * \ingroup TaskUtils + */ +void vTaskList( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + +/** + * task. h + * 
void vTaskGetRunTimeStats( char *pcWriteBuffer );
+ * + * configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS + * must both be defined as 1 for this function to be available. The application + * must also then provide definitions for + * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE() + * to configure a peripheral timer/counter and return the timers current count + * value respectively. The counter should be at least 10 times the frequency of + * the tick count. + * + * NOTE 1: This function will disable interrupts for its duration. It is + * not intended for normal application runtime use but as a debug aid. + * + * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total + * accumulated execution time being stored for each task. The resolution + * of the accumulated time value depends on the frequency of the timer + * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro. + * Calling vTaskGetRunTimeStats() writes the total execution time of each + * task into a buffer, both as an absolute count value and as a percentage + * of the total system execution time. + * + * NOTE 2: + * + * This function is provided for convenience only, and is used by many of the + * demo applications. Do not consider it to be part of the scheduler. + * + * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part of the + * uxTaskGetSystemState() output into a human readable table that displays the + * amount of time each task has spent in the Running state in both absolute and + * percentage terms. + * + * vTaskGetRunTimeStats() has a dependency on the sprintf() C library function + * that might bloat the code size, use a lot of stack, and provide different + * results on different platforms. An alternative, tiny, third party, and + * limited functionality implementation of sprintf() is provided in many of the + * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note + * printf-stdarg.c does not provide a full snprintf() implementation!). + * + * It is recommended that production systems call uxTaskGetSystemState() directly + * to get access to raw stats data, rather than indirectly through a call to + * vTaskGetRunTimeStats(). + * + * @param pcWriteBuffer A buffer into which the execution times will be + * written, in ASCII form. This buffer is assumed to be large enough to + * contain the generated report. Approximately 40 bytes per task should + * be sufficient. + * + * \defgroup vTaskGetRunTimeStats vTaskGetRunTimeStats + * \ingroup TaskUtils + */ +void vTaskGetRunTimeStats( char *pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + +/** + * task. h + * 
BaseType_t xTaskNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction );
+ * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this + * function to be available. + * + * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private + * "notification value", which is a 32-bit unsigned integer (uint32_t). + * + * Events can be sent to a task using an intermediary object. Examples of such + * objects are queues, semaphores, mutexes and event groups. Task notifications + * are a method of sending an event directly to a task without the need for such + * an intermediary object. + * + * A notification sent to a task can optionally perform an action, such as + * update, overwrite or increment the task's notification value. In that way + * task notifications can be used to send data to a task, or be used as light + * weight and fast binary or counting semaphores. + * + * A notification sent to a task will remain pending until it is cleared by the + * task calling xTaskNotifyWait() or ulTaskNotifyTake(). If the task was + * already in the Blocked state to wait for a notification when the notification + * arrives then the task will automatically be removed from the Blocked state + * (unblocked) and the notification cleared. + * + * A task can use xTaskNotifyWait() to [optionally] block to wait for a + * notification to be pending, or ulTaskNotifyTake() to [optionally] block + * to wait for its notification value to have a non-zero value. The task does + * not consume any CPU time while it is in the Blocked state. + * + * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * @param xTaskToNotify The handle of the task being notified. The handle to a + * task can be returned from the xTaskCreate() API function used to create the + * task, and the handle of the currently running task can be obtained by calling + * xTaskGetCurrentTaskHandle(). + * + * @param ulValue Data that can be sent with the notification. How the data is + * used depends on the value of the eAction parameter. + * + * @param eAction Specifies how the notification updates the task's notification + * value, if at all. Valid values for eAction are as follows: + * + * eSetBits - + * The task's notification value is bitwise ORed with ulValue. xTaskNofify() + * always returns pdPASS in this case. + * + * eIncrement - + * The task's notification value is incremented. ulValue is not used and + * xTaskNotify() always returns pdPASS in this case. + * + * eSetValueWithOverwrite - + * The task's notification value is set to the value of ulValue, even if the + * task being notified had not yet processed the previous notification (the + * task already had a notification pending). xTaskNotify() always returns + * pdPASS in this case. + * + * eSetValueWithoutOverwrite - + * If the task being notified did not already have a notification pending then + * the task's notification value is set to ulValue and xTaskNotify() will + * return pdPASS. If the task being notified already had a notification + * pending then no action is performed and pdFAIL is returned. + * + * eNoAction - + * The task receives a notification without its notification value being + * updated. ulValue is not used and xTaskNotify() always returns pdPASS in + * this case. + * + * @return Dependent on the value of eAction. See the description of the + * eAction parameter. + * + * \defgroup xTaskNotify xTaskNotify + * \ingroup TaskNotifications + */ +BaseType_t xTaskNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction ); + +/** + * task. h + * 
BaseType_t xTaskNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken );
+ * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this + * function to be available. + * + * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private + * "notification value", which is a 32-bit unsigned integer (uint32_t). + * + * A version of xTaskNotify() that can be used from an interrupt service routine + * (ISR). + * + * Events can be sent to a task using an intermediary object. Examples of such + * objects are queues, semaphores, mutexes and event groups. Task notifications + * are a method of sending an event directly to a task without the need for such + * an intermediary object. + * + * A notification sent to a task can optionally perform an action, such as + * update, overwrite or increment the task's notification value. In that way + * task notifications can be used to send data to a task, or be used as light + * weight and fast binary or counting semaphores. + * + * A notification sent to a task will remain pending until it is cleared by the + * task calling xTaskNotifyWait() or ulTaskNotifyTake(). If the task was + * already in the Blocked state to wait for a notification when the notification + * arrives then the task will automatically be removed from the Blocked state + * (unblocked) and the notification cleared. + * + * A task can use xTaskNotifyWait() to [optionally] block to wait for a + * notification to be pending, or ulTaskNotifyTake() to [optionally] block + * to wait for its notification value to have a non-zero value. The task does + * not consume any CPU time while it is in the Blocked state. + * + * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * @param xTaskToNotify The handle of the task being notified. The handle to a + * task can be returned from the xTaskCreate() API function used to create the + * task, and the handle of the currently running task can be obtained by calling + * xTaskGetCurrentTaskHandle(). + * + * @param ulValue Data that can be sent with the notification. How the data is + * used depends on the value of the eAction parameter. + * + * @param eAction Specifies how the notification updates the task's notification + * value, if at all. Valid values for eAction are as follows: + * + * eSetBits - + * The task's notification value is bitwise ORed with ulValue. xTaskNofify() + * always returns pdPASS in this case. + * + * eIncrement - + * The task's notification value is incremented. ulValue is not used and + * xTaskNotify() always returns pdPASS in this case. + * + * eSetValueWithOverwrite - + * The task's notification value is set to the value of ulValue, even if the + * task being notified had not yet processed the previous notification (the + * task already had a notification pending). xTaskNotify() always returns + * pdPASS in this case. + * + * eSetValueWithoutOverwrite - + * If the task being notified did not already have a notification pending then + * the task's notification value is set to ulValue and xTaskNotify() will + * return pdPASS. If the task being notified already had a notification + * pending then no action is performed and pdFAIL is returned. + * + * eNoAction - + * The task receives a notification without its notification value being + * updated. ulValue is not used and xTaskNotify() always returns pdPASS in + * this case. + * + * @param pxHigherPriorityTaskWoken xTaskNotifyFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the + * task to which the notification was sent to leave the Blocked state, and the + * unblocked task has a priority higher than the currently running task. If + * xTaskNotifyFromISR() sets this value to pdTRUE then a context switch should + * be requested before the interrupt is exited. How a context switch is + * requested from an ISR is dependent on the port - see the documentation page + * for the port in use. + * + * @return Dependent on the value of eAction. See the description of the + * eAction parameter. + * + * \defgroup xTaskNotify xTaskNotify + * \ingroup TaskNotifications + */ +BaseType_t xTaskNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken ); + +/** + * task. h + * 
BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait );
+ * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this + * function to be available. + * + * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private + * "notification value", which is a 32-bit unsigned integer (uint32_t). + * + * Events can be sent to a task using an intermediary object. Examples of such + * objects are queues, semaphores, mutexes and event groups. Task notifications + * are a method of sending an event directly to a task without the need for such + * an intermediary object. + * + * A notification sent to a task can optionally perform an action, such as + * update, overwrite or increment the task's notification value. In that way + * task notifications can be used to send data to a task, or be used as light + * weight and fast binary or counting semaphores. + * + * A notification sent to a task will remain pending until it is cleared by the + * task calling xTaskNotifyWait() or ulTaskNotifyTake(). If the task was + * already in the Blocked state to wait for a notification when the notification + * arrives then the task will automatically be removed from the Blocked state + * (unblocked) and the notification cleared. + * + * A task can use xTaskNotifyWait() to [optionally] block to wait for a + * notification to be pending, or ulTaskNotifyTake() to [optionally] block + * to wait for its notification value to have a non-zero value. The task does + * not consume any CPU time while it is in the Blocked state. + * + * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * @param ulBitsToClearOnEntry Bits that are set in ulBitsToClearOnEntry value + * will be cleared in the calling task's notification value before the task + * checks to see if any notifications are pending, and optionally blocks if no + * notifications are pending. Setting ulBitsToClearOnEntry to ULONG_MAX (if + * limits.h is included) or 0xffffffffUL (if limits.h is not included) will have + * the effect of resetting the task's notification value to 0. Setting + * ulBitsToClearOnEntry to 0 will leave the task's notification value unchanged. + * + * @param ulBitsToClearOnExit If a notification is pending or received before + * the calling task exits the xTaskNotifyWait() function then the task's + * notification value (see the xTaskNotify() API function) is passed out using + * the pulNotificationValue parameter. Then any bits that are set in + * ulBitsToClearOnExit will be cleared in the task's notification value (note + * *pulNotificationValue is set before any bits are cleared). Setting + * ulBitsToClearOnExit to ULONG_MAX (if limits.h is included) or 0xffffffffUL + * (if limits.h is not included) will have the effect of resetting the task's + * notification value to 0 before the function exits. Setting + * ulBitsToClearOnExit to 0 will leave the task's notification value unchanged + * when the function exits (in which case the value passed out in + * pulNotificationValue will match the task's notification value). + * + * @param pulNotificationValue Used to pass the task's notification value out + * of the function. Note the value passed out will not be effected by the + * clearing of any bits caused by ulBitsToClearOnExit being non-zero. + * + * @param xTicksToWait The maximum amount of time that the task should wait in + * the Blocked state for a notification to be received, should a notification + * not already be pending when xTaskNotifyWait() was called. The task + * will not consume any processing time while it is in the Blocked state. This + * is specified in kernel ticks, the macro pdMS_TO_TICSK( value_in_ms ) can be + * used to convert a time specified in milliseconds to a time specified in + * ticks. + * + * @return If a notification was received (including notifications that were + * already pending when xTaskNotifyWait was called) then pdPASS is + * returned. Otherwise pdFAIL is returned. + * + * \defgroup xTaskNotifyWait xTaskNotifyWait + * \ingroup TaskNotifications + */ +BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ); + +/** + * task. h + * 
BaseType_t xTaskNotifyGive( TaskHandle_t xTaskToNotify );
+ * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro + * to be available. + * + * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private + * "notification value", which is a 32-bit unsigned integer (uint32_t). + * + * Events can be sent to a task using an intermediary object. Examples of such + * objects are queues, semaphores, mutexes and event groups. Task notifications + * are a method of sending an event directly to a task without the need for such + * an intermediary object. + * + * A notification sent to a task can optionally perform an action, such as + * update, overwrite or increment the task's notification value. In that way + * task notifications can be used to send data to a task, or be used as light + * weight and fast binary or counting semaphores. + * + * xTaskNotifyGive() is a helper macro intended for use when task notifications + * are used as light weight and faster binary or counting semaphore equivalents. + * Actual FreeRTOS semaphores are given using the xSemaphoreGive() API function, + * the equivalent action that instead uses a task notification is + * xTaskNotifyGive(). + * + * When task notifications are being used as a binary or counting semaphore + * equivalent then the task being notified should wait for the notification + * using the ulTaskNotificationTake() API function rather than the + * xTaskNotifyWait() API function. + * + * See http://www.FreeRTOS.org/RTOS-task-notifications.html for more details. + * + * @param xTaskToNotify The handle of the task being notified. The handle to a + * task can be returned from the xTaskCreate() API function used to create the + * task, and the handle of the currently running task can be obtained by calling + * xTaskGetCurrentTaskHandle(). + * + * @return xTaskNotifyGive() is a macro that calls xTaskNotify() with the + * eAction parameter set to eIncrement - so pdPASS is always returned. + * + * \defgroup xTaskNotifyGive xTaskNotifyGive + * \ingroup TaskNotifications + */ +#define xTaskNotifyGive( xTaskToNotify ) xTaskNotify( ( xTaskToNotify ), 0, eIncrement ); + +/** + * task. h + * 
void vTaskNotifyGiveFromISR( TaskHandle_t xTaskHandle, BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro
+ * to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * A version of xTaskNotifyGive() that can be called from an interrupt service
+ * routine (ISR).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * vTaskNotifyGiveFromISR() is intended for use when task notifications are
+ * used as light weight and faster binary or counting semaphore equivalents.
+ * Actual FreeRTOS semaphores are given from an ISR using the
+ * xSemaphoreGiveFromISR() API function, the equivalent action that instead uses
+ * a task notification is vTaskNotifyGiveFromISR().
+ *
+ * When task notifications are being used as a binary or counting semaphore
+ * equivalent then the task being notified should wait for the notification
+ * using the ulTaskNotificationTake() API function rather than the
+ * xTaskNotifyWait() API function.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for more details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param pxHigherPriorityTaskWoken  vTaskNotifyGiveFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the
+ * task to which the notification was sent to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently running task.  If
+ * vTaskNotifyGiveFromISR() sets this value to pdTRUE then a context switch
+ * should be requested before the interrupt is exited.  How a context switch is
+ * requested from an ISR is dependent on the port - see the documentation page
+ * for the port in use.
+ *
+ * \defgroup xTaskNotifyWait xTaskNotifyWait
+ * \ingroup TaskNotifications
+ */
+void vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPriorityTaskWoken );
+
+/**
+ * task. h
+ * 
uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait );

+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * ulTaskNotifyTake() is intended for use when a task notification is used as a
+ * faster and lighter weight binary or counting semaphore alternative.  Actual
+ * FreeRTOS semaphores are taken using the xSemaphoreTake() API function, the
+ * equivalent action that instead uses a task notification is
+ * ulTaskNotifyTake().
+ *
+ * When a task is using its notification value as a binary or counting semaphore
+ * other tasks should send notifications to it using the xTaskNotifyGive()
+ * macro, or xTaskNotify() function with the eAction parameter set to
+ * eIncrement.
+ *
+ * ulTaskNotifyTake() can either clear the task's notification value to
+ * zero on exit, in which case the notification value acts like a binary
+ * semaphore, or decrement the task's notification value on exit, in which case
+ * the notification value acts like a counting semaphore.
+ *
+ * A task can use ulTaskNotifyTake() to [optionally] block to wait for a
+ * the task's notification value to be non-zero.  The task does not consume any
+ * CPU time while it is in the Blocked state.
+ *
+ * Where as xTaskNotifyWait() will return when a notification is pending,
+ * ulTaskNotifyTake() will return when the task's notification value is
+ * not zero.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param xClearCountOnExit if xClearCountOnExit is pdFALSE then the task's
+ * notification value is decremented when the function exits.  In this way the
+ * notification value acts like a counting semaphore.  If xClearCountOnExit is
+ * not pdFALSE then the task's notification value is cleared to zero when the
+ * function exits.  In this way the notification value acts like a binary
+ * semaphore.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait in
+ * the Blocked state for the task's notification value to be greater than zero,
+ * should the count not already be greater than zero when
+ * ulTaskNotifyTake() was called.  The task will not consume any processing
+ * time while it is in the Blocked state.  This is specified in kernel ticks,
+ * the macro pdMS_TO_TICSK( value_in_ms ) can be used to convert a time
+ * specified in milliseconds to a time specified in ticks.
+ *
+ * @return The task's notification count before it is either cleared to zero or
+ * decremented (see the xClearCountOnExit parameter).
+ *
+ * \defgroup ulTaskNotifyTake ulTaskNotifyTake
+ * \ingroup TaskNotifications
+ */
+uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait );
+
+/*-----------------------------------------------------------
+ * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES
+ *----------------------------------------------------------*/
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY
+ * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
+ * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * Called from the real time kernel tick (either preemptive or cooperative),
+ * this increments the tick count and checks if any tasks that are blocked
+ * for a finite period required removing from a blocked list and placing on
+ * a ready list.  If a non-zero value is returned then a context switch is
+ * required because either:
+ *   + A task was removed from a blocked list because its timeout had expired,
+ *     or
+ *   + Time slicing is in use and there is a task of equal priority to the
+ *     currently running task.
+ */
+BaseType_t xTaskIncrementTick( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * Removes the calling task from the ready list and places it both
+ * on the list of tasks waiting for a particular event, and the
+ * list of delayed tasks.  The task will be removed from both lists
+ * and replaced on the ready list should either the event occur (and
+ * there be no higher priority tasks waiting on the same event) or
+ * the delay period expires.
+ *
+ * The 'unordered' version replaces the event list item value with the
+ * xItemValue value, and inserts the list item at the end of the list.
+ *
+ * The 'ordered' version uses the existing event list item value (which is the
+ * owning tasks priority) to insert the list item into the event list is task
+ * priority order.
+ *
+ * @param pxEventList The list containing tasks that are blocked waiting
+ * for the event to occur.
+ *
+ * @param xItemValue The item value to use for the event list item when the
+ * event list is not ordered by task priority.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait
+ * for the event to occur.  This is specified in kernel ticks,the constant
+ * portTICK_PERIOD_MS can be used to convert kernel ticks into a real time
+ * period.
+ */
+void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * This function performs nearly the same function as vTaskPlaceOnEventList().
+ * The difference being that this function does not permit tasks to block
+ * indefinitely, whereas vTaskPlaceOnEventList() does.
+ *
+ */
+void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * Removes a task from both the specified event list and the list of blocked
+ * tasks, and places it on a ready queue.
+ *
+ * xTaskRemoveFromEventList()/xTaskRemoveFromUnorderedEventList() will be called
+ * if either an event occurs to unblock a task, or the block timeout period
+ * expires.
+ *
+ * xTaskRemoveFromEventList() is used when the event list is in task priority
+ * order.  It removes the list item from the head of the event list as that will
+ * have the highest priority owning task of all the tasks on the event list.
+ * xTaskRemoveFromUnorderedEventList() is used when the event list is not
+ * ordered and the event list items hold something other than the owning tasks
+ * priority.  In this case the event list item value is updated to the value
+ * passed in the xItemValue parameter.
+ *
+ * @return pdTRUE if the task being removed has a higher priority than the task
+ * making the call, otherwise pdFALSE.
+ */
+BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) PRIVILEGED_FUNCTION;
+BaseType_t xTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY
+ * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
+ * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * Sets the pointer to the current TCB to the TCB of the highest priority task
+ * that is ready to run.
+ */
+void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * THESE FUNCTIONS MUST NOT BE USED FROM APPLICATION CODE.  THEY ARE USED BY
+ * THE EVENT BITS MODULE.
+ */
+TickType_t uxTaskResetEventItemValue( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Return the handle of the calling task.
+ */
+TaskHandle_t xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Capture the current time status for future reference.
+ */
+void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;
+
+/*
+ * Compare the time status now with that previously captured to see if the
+ * timeout has expired.
+ */
+BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*
+ * Shortcut used by the queue implementation to prevent unnecessary call to
+ * taskYIELD();
+ */
+void vTaskMissedYield( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Returns the scheduler state as taskSCHEDULER_RUNNING,
+ * taskSCHEDULER_NOT_STARTED or taskSCHEDULER_SUSPENDED.
+ */
+BaseType_t xTaskGetSchedulerState( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Raises the priority of the mutex holder to that of the calling task should
+ * the mutex holder have a priority less than the calling task.
+ */
+void vTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
+
+/*
+ * Set the priority of a task back to its proper priority in the case that it
+ * inherited a higher priority while it was holding a semaphore.
+ */
+BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
+
+/*
+ * Generic version of the task creation function which is in turn called by the
+ * xTaskCreate() and xTaskCreateRestricted() macros.
+ */
+BaseType_t xTaskGenericCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask, StackType_t * const puxStackBuffer, const MemoryRegion_t * const xRegions, const BaseType_t xCoreID) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/*
+ * Get the uxTCBNumber assigned to the task referenced by the xTask parameter.
+ */
+UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+
+/*
+ * Get the current core affinity of a task
+ */
+BaseType_t xTaskGetAffinity( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/*
+ * Set the uxTaskNumber of the task referenced by the xTask parameter to
+ * uxHandle.
+ */
+void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle ) PRIVILEGED_FUNCTION;
+
+/*
+ * Only available when configUSE_TICKLESS_IDLE is set to 1.
+ * If tickless mode is being used, or a low power mode is implemented, then
+ * the tick interrupt will not execute during idle periods.  When this is the
+ * case, the tick count value maintained by the scheduler needs to be kept up
+ * to date with the actual execution time by being skipped forward by a time
+ * equal to the idle period.
+ */
+void vTaskStepTick( const TickType_t xTicksToJump ) PRIVILEGED_FUNCTION;
+
+/*
+ * Only avilable when configUSE_TICKLESS_IDLE is set to 1.
+ * Provided for use within portSUPPRESS_TICKS_AND_SLEEP() to allow the port
+ * specific sleep function to determine if it is ok to proceed with the sleep,
+ * and if it is ok to proceed, if it is ok to sleep indefinitely.
+ *
+ * This function is necessary because portSUPPRESS_TICKS_AND_SLEEP() is only
+ * called with the scheduler suspended, not from within a critical section.  It
+ * is therefore possible for an interrupt to request a context switch between
+ * portSUPPRESS_TICKS_AND_SLEEP() and the low power mode actually being
+ * entered.  eTaskConfirmSleepModeStatus() should be called from a short
+ * critical section between the timer being stopped and the sleep mode being
+ * entered to ensure it is ok to proceed into the sleep mode.
+ */
+eSleepModeStatus eTaskConfirmSleepModeStatus( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only.  Increment the mutex held count when a mutex is
+ * taken and return the handle of the task that has taken the mutex.
+ */
+void *pvTaskIncrementMutexHeldCount( void );
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* INC_TASK_H */
+
+
+
diff --git a/tools/sdk/include/freertos/freertos/timers.h b/tools/sdk/include/freertos/freertos/timers.h
new file mode 100644
index 00000000..f89cd1d7
--- /dev/null
+++ b/tools/sdk/include/freertos/freertos/timers.h
@@ -0,0 +1,1125 @@
+/*
+    FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+	***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+	***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+	the FAQ page "My application does not run, what could be wrong?".  Have you
+	defined configASSERT()?
+
+	http://www.FreeRTOS.org/support - In return for receiving this top quality
+	embedded software for free we request you assist our global community by
+	participating in the support forum.
+
+	http://www.FreeRTOS.org/training - Investing in training allows your team to
+	be as productive as possible as early as possible.  Now you can receive
+	FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+	Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+
+#ifndef TIMERS_H
+#define TIMERS_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h must appear in source files before include timers.h"
+#endif
+
+/*lint -e537 This headers are only multiply included if the application code
+happens to also be including task.h. */
+#include "task.h"
+/*lint +e537 */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * MACROS AND DEFINITIONS
+ *----------------------------------------------------------*/
+
+/* IDs for commands that can be sent/received on the timer queue.  These are to
+be used solely through the macros that make up the public software timer API,
+as defined below.  The commands that are sent from interrupts must use the
+highest numbers as tmrFIRST_FROM_ISR_COMMAND is used to determine if the task
+or interrupt version of the queue send function should be used. */
+#define tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR 	( ( BaseType_t ) -2 )
+#define tmrCOMMAND_EXECUTE_CALLBACK				( ( BaseType_t ) -1 )
+#define tmrCOMMAND_START_DONT_TRACE				( ( BaseType_t ) 0 )
+#define tmrCOMMAND_START					    ( ( BaseType_t ) 1 )
+#define tmrCOMMAND_RESET						( ( BaseType_t ) 2 )
+#define tmrCOMMAND_STOP							( ( BaseType_t ) 3 )
+#define tmrCOMMAND_CHANGE_PERIOD				( ( BaseType_t ) 4 )
+#define tmrCOMMAND_DELETE						( ( BaseType_t ) 5 )
+
+#define tmrFIRST_FROM_ISR_COMMAND				( ( BaseType_t ) 6 )
+#define tmrCOMMAND_START_FROM_ISR				( ( BaseType_t ) 6 )
+#define tmrCOMMAND_RESET_FROM_ISR				( ( BaseType_t ) 7 )
+#define tmrCOMMAND_STOP_FROM_ISR				( ( BaseType_t ) 8 )
+#define tmrCOMMAND_CHANGE_PERIOD_FROM_ISR		( ( BaseType_t ) 9 )
+
+
+/**
+ * Type by which software timers are referenced.  For example, a call to
+ * xTimerCreate() returns an TimerHandle_t variable that can then be used to
+ * reference the subject timer in calls to other software timer API functions
+ * (for example, xTimerStart(), xTimerReset(), etc.).
+ */
+typedef void * TimerHandle_t;
+
+/*
+ * Defines the prototype to which timer callback functions must conform.
+ */
+typedef void (*TimerCallbackFunction_t)( TimerHandle_t xTimer );
+
+/*
+ * Defines the prototype to which functions used with the
+ * xTimerPendFunctionCallFromISR() function must conform.
+ */
+typedef void (*PendedFunction_t)( void *, uint32_t );
+
+/**
+ * TimerHandle_t xTimerCreate( 	const char * const pcTimerName,
+ * 								TickType_t xTimerPeriodInTicks,
+ * 								UBaseType_t uxAutoReload,
+ * 								void * pvTimerID,
+ * 								TimerCallbackFunction_t pxCallbackFunction );
+ *
+ * Creates a new software timer instance.  This allocates the storage required
+ * by the new timer, initialises the new timers internal state, and returns a
+ * handle by which the new timer can be referenced.
+ *
+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a
+ * timer into the active state.
+ *
+ * @param pcTimerName A text name that is assigned to the timer.  This is done
+ * purely to assist debugging.  The kernel itself only ever references a timer
+ * by its handle, and never by its name.
+ *
+ * @param xTimerPeriodInTicks The timer period.  The time is defined in tick
+ * periods so the constant portTICK_PERIOD_MS can be used to convert a time that
+ * has been specified in milliseconds.  For example, if the timer must expire
+ * after 100 ticks, then xTimerPeriodInTicks should be set to 100.
+ * Alternatively, if the timer must expire after 500ms, then xPeriod can be set
+ * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or
+ * equal to 1000.
+ *
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.
+ * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ *
+ * @param pvTimerID An identifier that is assigned to the timer being created.
+ * Typically this would be used in the timer callback function to identify which
+ * timer expired when the same callback function is assigned to more than one
+ * timer.
+ *
+ * @param pxCallbackFunction The function to call when the timer expires.
+ * Callback functions must have the prototype defined by TimerCallbackFunction_t,
+ * which is	"void vCallbackFunction( TimerHandle_t xTimer );".
+ *
+ * @return If the timer is successfully created then a handle to the newly
+ * created timer is returned.  If the timer cannot be created (because either
+ * there is insufficient FreeRTOS heap remaining to allocate the timer
+ * structures, or the timer period was set to 0) then NULL is returned.
+ *
+ * Example usage:
+ * @verbatim
+ * #define NUM_TIMERS 5
+ *
+ * // An array to hold handles to the created timers.
+ * TimerHandle_t xTimers[ NUM_TIMERS ];
+ *
+ * // An array to hold a count of the number of times each timer expires.
+ * int32_t lExpireCounters[ NUM_TIMERS ] = { 0 };
+ *
+ * // Define a callback function that will be used by multiple timer instances.
+ * // The callback function does nothing but count the number of times the
+ * // associated timer expires, and stop the timer once the timer has expired
+ * // 10 times.
+ * void vTimerCallback( TimerHandle_t pxTimer )
+ * {
+ * int32_t lArrayIndex;
+ * const int32_t xMaxExpiryCountBeforeStopping = 10;
+ *
+ * 	   // Optionally do something if the pxTimer parameter is NULL.
+ * 	   configASSERT( pxTimer );
+ *
+ *     // Which timer expired?
+ *     lArrayIndex = ( int32_t ) pvTimerGetTimerID( pxTimer );
+ *
+ *     // Increment the number of times that pxTimer has expired.
+ *     lExpireCounters[ lArrayIndex ] += 1;
+ *
+ *     // If the timer has expired 10 times then stop it from running.
+ *     if( lExpireCounters[ lArrayIndex ] == xMaxExpiryCountBeforeStopping )
+ *     {
+ *         // Do not use a block time if calling a timer API function from a
+ *         // timer callback function, as doing so could cause a deadlock!
+ *         xTimerStop( pxTimer, 0 );
+ *     }
+ * }
+ *
+ * void main( void )
+ * {
+ * int32_t x;
+ *
+ *     // Create then start some timers.  Starting the timers before the scheduler
+ *     // has been started means the timers will start running immediately that
+ *     // the scheduler starts.
+ *     for( x = 0; x < NUM_TIMERS; x++ )
+ *     {
+ *         xTimers[ x ] = xTimerCreate(    "Timer",       // Just a text name, not used by the kernel.
+ *                                         ( 100 * x ),   // The timer period in ticks.
+ *                                         pdTRUE,        // The timers will auto-reload themselves when they expire.
+ *                                         ( void * ) x,  // Assign each timer a unique id equal to its array index.
+ *                                         vTimerCallback // Each timer calls the same callback when it expires.
+ *                                     );
+ *
+ *         if( xTimers[ x ] == NULL )
+ *         {
+ *             // The timer was not created.
+ *         }
+ *         else
+ *         {
+ *             // Start the timer.  No block time is specified, and even if one was
+ *             // it would be ignored because the scheduler has not yet been
+ *             // started.
+ *             if( xTimerStart( xTimers[ x ], 0 ) != pdPASS )
+ *             {
+ *                 // The timer could not be set into the Active state.
+ *             }
+ *         }
+ *     }
+ *
+ *     // ...
+ *     // Create tasks here.
+ *     // ...
+ *
+ *     // Starting the scheduler will start the timers running as they have already
+ *     // been set into the active state.
+ *     xTaskStartScheduler();
+ *
+ *     // Should not reach here.
+ *     for( ;; );
+ * }
+ * @endverbatim
+ */
+TimerHandle_t xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * void *pvTimerGetTimerID( TimerHandle_t xTimer );
+ *
+ * Returns the ID assigned to the timer.
+ *
+ * IDs are assigned to timers using the pvTimerID parameter of the call to
+ * xTimerCreated() that was used to create the timer.
+ *
+ * If the same callback function is assigned to multiple timers then the timer
+ * ID can be used within the callback function to identify which timer actually
+ * expired.
+ *
+ * @param xTimer The timer being queried.
+ *
+ * @return The ID assigned to the timer being queried.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ */
+void *pvTimerGetTimerID( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer );
+ *
+ * Queries a timer to see if it is active or dormant.
+ *
+ * A timer will be dormant if:
+ *     1) It has been created but not started, or
+ *     2) It is an expired one-shot timer that has not been restarted.
+ *
+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a timer into the
+ * active state.
+ *
+ * @param xTimer The timer being queried.
+ *
+ * @return pdFALSE will be returned if the timer is dormant.  A value other than
+ * pdFALSE will be returned if the timer is active.
+ *
+ * Example usage:
+ * @verbatim
+ * // This function assumes xTimer has already been created.
+ * void vAFunction( TimerHandle_t xTimer )
+ * {
+ *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"
+ *     {
+ *         // xTimer is active, do something.
+ *     }
+ *     else
+ *     {
+ *         // xTimer is not active, do something else.
+ *     }
+ * }
+ * @endverbatim
+ */
+BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * TaskHandle_t xTimerGetTimerDaemonTaskHandle( void );
+ *
+ * xTimerGetTimerDaemonTaskHandle() is only available if
+ * INCLUDE_xTimerGetTimerDaemonTaskHandle is set to 1 in FreeRTOSConfig.h.
+ *
+ * Simply returns the handle of the timer service/daemon task.  It it not valid
+ * to call xTimerGetTimerDaemonTaskHandle() before the scheduler has been started.
+ */
+TaskHandle_t xTimerGetTimerDaemonTaskHandle( void );
+
+/**
+ * BaseType_t xTimerStart( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerStart() starts a timer that was previously created using the
+ * xTimerCreate() API function.  If the timer had already been started and was
+ * already in the active state, then xTimerStart() has equivalent functionality
+ * to the xTimerReset() API function.
+ *
+ * Starting a timer ensures the timer is in the active state.  If the timer
+ * is not stopped, deleted, or reset in the mean time, the callback function
+ * associated with the timer will get called 'n' ticks after xTimerStart() was
+ * called, where 'n' is the timers defined period.
+ *
+ * It is valid to call xTimerStart() before the scheduler has been started, but
+ * when this is done the timer will not actually start until the scheduler is
+ * started, and the timers expiry time will be relative to when the scheduler is
+ * started, not relative to when xTimerStart() was called.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStart()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being started/restarted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the start command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerStart() was called.  xTicksToWait is ignored if xTimerStart() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the start command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system, although the
+ * timers expiry time is relative to when xTimerStart() is actually called.  The
+ * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ *
+ */
+#define xTimerStart( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerStop( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerStop() stops a timer that was previously started using either of the
+ * The xTimerStart(), xTimerReset(), xTimerStartFromISR(), xTimerResetFromISR(),
+ * xTimerChangePeriod() or xTimerChangePeriodFromISR() API functions.
+ *
+ * Stopping a timer ensures the timer is not in the active state.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStop()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being stopped.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the stop command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerStop() was called.  xTicksToWait is ignored if xTimerStop() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the stop command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system.  The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ *
+ */
+#define xTimerStop( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP, 0U, NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerChangePeriod( 	TimerHandle_t xTimer,
+ *										TickType_t xNewPeriod,
+ *										TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerChangePeriod() changes the period of a timer that was previously
+ * created using the xTimerCreate() API function.
+ *
+ * xTimerChangePeriod() can be called to change the period of an active or
+ * dormant state timer.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for
+ * xTimerChangePeriod() to be available.
+ *
+ * @param xTimer The handle of the timer that is having its period changed.
+ *
+ * @param xNewPeriod The new period for xTimer. Timer periods are specified in
+ * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time
+ * that has been specified in milliseconds.  For example, if the timer must
+ * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,
+ * if the timer must expire after 500ms, then xNewPeriod can be set to
+ * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than
+ * or equal to 1000.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the change period command to be
+ * successfully sent to the timer command queue, should the queue already be
+ * full when xTimerChangePeriod() was called.  xTicksToWait is ignored if
+ * xTimerChangePeriod() is called before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the change period command could not be
+ * sent to the timer command queue even after xTicksToWait ticks had passed.
+ * pdPASS will be returned if the command was successfully sent to the timer
+ * command queue.  When the command is actually processed will depend on the
+ * priority of the timer service/daemon task relative to other tasks in the
+ * system.  The timer service/daemon task priority is set by the
+ * configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This function assumes xTimer has already been created.  If the timer
+ * // referenced by xTimer is already active when it is called, then the timer
+ * // is deleted.  If the timer referenced by xTimer is not active when it is
+ * // called, then the period of the timer is set to 500ms and the timer is
+ * // started.
+ * void vAFunction( TimerHandle_t xTimer )
+ * {
+ *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"
+ *     {
+ *         // xTimer is already active - delete it.
+ *         xTimerDelete( xTimer );
+ *     }
+ *     else
+ *     {
+ *         // xTimer is not active, change its period to 500ms.  This will also
+ *         // cause the timer to start.  Block for a maximum of 100 ticks if the
+ *         // change period command cannot immediately be sent to the timer
+ *         // command queue.
+ *         if( xTimerChangePeriod( xTimer, 500 / portTICK_PERIOD_MS, 100 ) == pdPASS )
+ *         {
+ *             // The command was successfully sent.
+ *         }
+ *         else
+ *         {
+ *             // The command could not be sent, even after waiting for 100 ticks
+ *             // to pass.  Take appropriate action here.
+ *         }
+ *     }
+ * }
+ * @endverbatim
+ */
+ #define xTimerChangePeriod( xTimer, xNewPeriod, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD, ( xNewPeriod ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerDelete( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerDelete() deletes a timer that was previously created using the
+ * xTimerCreate() API function.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for
+ * xTimerDelete() to be available.
+ *
+ * @param xTimer The handle of the timer being deleted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the delete command to be
+ * successfully sent to the timer command queue, should the queue already be
+ * full when xTimerDelete() was called.  xTicksToWait is ignored if xTimerDelete()
+ * is called before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the delete command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system.  The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerChangePeriod() API function example usage scenario.
+ */
+#define xTimerDelete( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_DELETE, 0U, NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerReset( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerReset() re-starts a timer that was previously created using the
+ * xTimerCreate() API function.  If the timer had already been started and was
+ * already in the active state, then xTimerReset() will cause the timer to
+ * re-evaluate its expiry time so that it is relative to when xTimerReset() was
+ * called.  If the timer was in the dormant state then xTimerReset() has
+ * equivalent functionality to the xTimerStart() API function.
+ *
+ * Resetting a timer ensures the timer is in the active state.  If the timer
+ * is not stopped, deleted, or reset in the mean time, the callback function
+ * associated with the timer will get called 'n' ticks after xTimerReset() was
+ * called, where 'n' is the timers defined period.
+ *
+ * It is valid to call xTimerReset() before the scheduler has been started, but
+ * when this is done the timer will not actually start until the scheduler is
+ * started, and the timers expiry time will be relative to when the scheduler is
+ * started, not relative to when xTimerReset() was called.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerReset()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being reset/started/restarted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the reset command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerReset() was called.  xTicksToWait is ignored if xTimerReset() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the reset command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system, although the
+ * timers expiry time is relative to when xTimerStart() is actually called.  The
+ * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // When a key is pressed, an LCD back-light is switched on.  If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off.  In
+ * // this case, the timer is a one-shot timer.
+ *
+ * TimerHandle_t xBacklightTimer = NULL;
+ *
+ * // The callback function assigned to the one-shot timer.  In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ *     // The timer expired, therefore 5 seconds must have passed since a key
+ *     // was pressed.  Switch off the LCD back-light.
+ *     vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press event handler.
+ * void vKeyPressEventHandler( char cKey )
+ * {
+ *     // Ensure the LCD back-light is on, then reset the timer that is
+ *     // responsible for turning the back-light off after 5 seconds of
+ *     // key inactivity.  Wait 10 ticks for the command to be successfully sent
+ *     // if it cannot be sent immediately.
+ *     vSetBacklightState( BACKLIGHT_ON );
+ *     if( xTimerReset( xBacklightTimer, 100 ) != pdPASS )
+ *     {
+ *         // The reset command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // Perform the rest of the key processing here.
+ * }
+ *
+ * void main( void )
+ * {
+ * int32_t x;
+ *
+ *     // Create then start the one-shot timer that is responsible for turning
+ *     // the back-light off if no keys are pressed within a 5 second period.
+ *     xBacklightTimer = xTimerCreate( "BacklightTimer",           // Just a text name, not used by the kernel.
+ *                                     ( 5000 / portTICK_PERIOD_MS), // The timer period in ticks.
+ *                                     pdFALSE,                    // The timer is a one-shot timer.
+ *                                     0,                          // The id is not used by the callback so can take any value.
+ *                                     vBacklightTimerCallback     // The callback function that switches the LCD back-light off.
+ *                                   );
+ *
+ *     if( xBacklightTimer == NULL )
+ *     {
+ *         // The timer was not created.
+ *     }
+ *     else
+ *     {
+ *         // Start the timer.  No block time is specified, and even if one was
+ *         // it would be ignored because the scheduler has not yet been
+ *         // started.
+ *         if( xTimerStart( xBacklightTimer, 0 ) != pdPASS )
+ *         {
+ *             // The timer could not be set into the Active state.
+ *         }
+ *     }
+ *
+ *     // ...
+ *     // Create tasks here.
+ *     // ...
+ *
+ *     // Starting the scheduler will start the timer running as it has already
+ *     // been set into the active state.
+ *     xTaskStartScheduler();
+ *
+ *     // Should not reach here.
+ *     for( ;; );
+ * }
+ * @endverbatim
+ */
+#define xTimerReset( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerStartFromISR( 	TimerHandle_t xTimer,
+ *									BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerStart() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer being started/restarted.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerStartFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state.  If calling xTimerStartFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerStartFromISR() function.  If
+ * xTimerStartFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the start command could not be sent to
+ * the timer command queue.  pdPASS will be returned if the command was
+ * successfully sent to the timer command queue.  When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system, although the timers expiry time is
+ * relative to when xTimerStartFromISR() is actually called.  The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xBacklightTimer has already been created.  When a
+ * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off.  In
+ * // this case, the timer is a one-shot timer, and unlike the example given for
+ * // the xTimerReset() function, the key press event handler is an interrupt
+ * // service routine.
+ *
+ * // The callback function assigned to the one-shot timer.  In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ *     // The timer expired, therefore 5 seconds must have passed since a key
+ *     // was pressed.  Switch off the LCD back-light.
+ *     vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press interrupt service routine.
+ * void vKeyPressEventInterruptHandler( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // Ensure the LCD back-light is on, then restart the timer that is
+ *     // responsible for turning the back-light off after 5 seconds of
+ *     // key inactivity.  This is an interrupt service routine so can only
+ *     // call FreeRTOS API functions that end in "FromISR".
+ *     vSetBacklightState( BACKLIGHT_ON );
+ *
+ *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here
+ *     // as both cause the timer to re-calculate its expiry time.
+ *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was
+ *     // declared (in this function).
+ *     if( xTimerStartFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The start command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // Perform the rest of the key processing here.
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerStartFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerStopFromISR( 	TimerHandle_t xTimer,
+ *									BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerStop() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer being stopped.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerStopFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state.  If calling xTimerStopFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerStopFromISR() function.  If
+ * xTimerStopFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the stop command could not be sent to
+ * the timer command queue.  pdPASS will be returned if the command was
+ * successfully sent to the timer command queue.  When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system.  The timer service/daemon task
+ * priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xTimer has already been created and started.  When
+ * // an interrupt occurs, the timer should be simply stopped.
+ *
+ * // The interrupt service routine that stops the timer.
+ * void vAnExampleInterruptServiceRoutine( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // The interrupt has occurred - simply stop the timer.
+ *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined
+ *     // (within this function).  As this is an interrupt service routine, only
+ *     // FreeRTOS API functions that end in "FromISR" can be used.
+ *     if( xTimerStopFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The stop command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerStopFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP_FROM_ISR, 0, ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerChangePeriodFromISR( TimerHandle_t xTimer,
+ *										 TickType_t xNewPeriod,
+ *										 BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerChangePeriod() that can be called from an interrupt
+ * service routine.
+ *
+ * @param xTimer The handle of the timer that is having its period changed.
+ *
+ * @param xNewPeriod The new period for xTimer. Timer periods are specified in
+ * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time
+ * that has been specified in milliseconds.  For example, if the timer must
+ * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,
+ * if the timer must expire after 500ms, then xNewPeriod can be set to
+ * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than
+ * or equal to 1000.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerChangePeriodFromISR() writes a message to the
+ * timer command queue, so has the potential to transition the timer service/
+ * daemon task out of the Blocked state.  If calling xTimerChangePeriodFromISR()
+ * causes the timer service/daemon task to leave the Blocked state, and the
+ * timer service/daemon task has a priority equal to or greater than the
+ * currently executing task (the task that was interrupted), then
+ * *pxHigherPriorityTaskWoken will get set to pdTRUE internally within the
+ * xTimerChangePeriodFromISR() function.  If xTimerChangePeriodFromISR() sets
+ * this value to pdTRUE then a context switch should be performed before the
+ * interrupt exits.
+ *
+ * @return pdFAIL will be returned if the command to change the timers period
+ * could not be sent to the timer command queue.  pdPASS will be returned if the
+ * command was successfully sent to the timer command queue.  When the command
+ * is actually processed will depend on the priority of the timer service/daemon
+ * task relative to other tasks in the system.  The timer service/daemon task
+ * priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xTimer has already been created and started.  When
+ * // an interrupt occurs, the period of xTimer should be changed to 500ms.
+ *
+ * // The interrupt service routine that changes the period of xTimer.
+ * void vAnExampleInterruptServiceRoutine( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // The interrupt has occurred - change the period of xTimer to 500ms.
+ *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined
+ *     // (within this function).  As this is an interrupt service routine, only
+ *     // FreeRTOS API functions that end in "FromISR" can be used.
+ *     if( xTimerChangePeriodFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The command to change the timers period was not executed
+ *         // successfully.  Take appropriate action here.
+ *     }
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerChangePeriodFromISR( xTimer, xNewPeriod, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD_FROM_ISR, ( xNewPeriod ), ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerResetFromISR( 	TimerHandle_t xTimer,
+ *									BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerReset() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer that is to be started, reset, or
+ * restarted.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerResetFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state.  If calling xTimerResetFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerResetFromISR() function.  If
+ * xTimerResetFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the reset command could not be sent to
+ * the timer command queue.  pdPASS will be returned if the command was
+ * successfully sent to the timer command queue.  When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system, although the timers expiry time is
+ * relative to when xTimerResetFromISR() is actually called.  The timer service/daemon
+ * task priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xBacklightTimer has already been created.  When a
+ * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off.  In
+ * // this case, the timer is a one-shot timer, and unlike the example given for
+ * // the xTimerReset() function, the key press event handler is an interrupt
+ * // service routine.
+ *
+ * // The callback function assigned to the one-shot timer.  In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ *     // The timer expired, therefore 5 seconds must have passed since a key
+ *     // was pressed.  Switch off the LCD back-light.
+ *     vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press interrupt service routine.
+ * void vKeyPressEventInterruptHandler( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // Ensure the LCD back-light is on, then reset the timer that is
+ *     // responsible for turning the back-light off after 5 seconds of
+ *     // key inactivity.  This is an interrupt service routine so can only
+ *     // call FreeRTOS API functions that end in "FromISR".
+ *     vSetBacklightState( BACKLIGHT_ON );
+ *
+ *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here
+ *     // as both cause the timer to re-calculate its expiry time.
+ *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was
+ *     // declared (in this function).
+ *     if( xTimerResetFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The reset command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // Perform the rest of the key processing here.
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerResetFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )
+
+
+/**
+ * BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,
+ *                                          void *pvParameter1,
+ *                                          uint32_t ulParameter2,
+ *                                          BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ *
+ * Used from application interrupt service routines to defer the execution of a
+ * function to the RTOS daemon task (the timer service task, hence this function
+ * is implemented in timers.c and is prefixed with 'Timer').
+ *
+ * Ideally an interrupt service routine (ISR) is kept as short as possible, but
+ * sometimes an ISR either has a lot of processing to do, or needs to perform
+ * processing that is not deterministic.  In these cases
+ * xTimerPendFunctionCallFromISR() can be used to defer processing of a function
+ * to the RTOS daemon task.
+ *
+ * A mechanism is provided that allows the interrupt to return directly to the
+ * task that will subsequently execute the pended callback function.  This
+ * allows the callback function to execute contiguously in time with the
+ * interrupt - just as if the callback had executed in the interrupt itself.
+ *
+ * @param xFunctionToPend The function to execute from the timer service/
+ * daemon task.  The function must conform to the PendedFunction_t
+ * prototype.
+ *
+ * @param pvParameter1 The value of the callback function's first parameter.
+ * The parameter has a void * type to allow it to be used to pass any type.
+ * For example, unsigned longs can be cast to a void *, or the void * can be
+ * used to point to a structure.
+ *
+ * @param ulParameter2 The value of the callback function's second parameter.
+ *
+ * @param pxHigherPriorityTaskWoken As mentioned above, calling this function
+ * will result in a message being sent to the timer daemon task.  If the
+ * priority of the timer daemon task (which is set using
+ * configTIMER_TASK_PRIORITY in FreeRTOSConfig.h) is higher than the priority of
+ * the currently running task (the task the interrupt interrupted) then
+ * *pxHigherPriorityTaskWoken will be set to pdTRUE within
+ * xTimerPendFunctionCallFromISR(), indicating that a context switch should be
+ * requested before the interrupt exits.  For that reason
+ * *pxHigherPriorityTaskWoken must be initialised to pdFALSE.  See the
+ * example code below.
+ *
+ * @return pdPASS is returned if the message was successfully sent to the
+ * timer daemon task, otherwise pdFALSE is returned.
+ *
+ * Example usage:
+ * @verbatim
+ *
+ *	// The callback function that will execute in the context of the daemon task.
+ *  // Note callback functions must all use this same prototype.
+ *  void vProcessInterface( void *pvParameter1, uint32_t ulParameter2 )
+ *	{
+ *		BaseType_t xInterfaceToService;
+ *
+ *		// The interface that requires servicing is passed in the second
+ *      // parameter.  The first parameter is not used in this case.
+ *		xInterfaceToService = ( BaseType_t ) ulParameter2;
+ *
+ *		// ...Perform the processing here...
+ *	}
+ *
+ *	// An ISR that receives data packets from multiple interfaces
+ *  void vAnISR( void )
+ *	{
+ *		BaseType_t xInterfaceToService, xHigherPriorityTaskWoken;
+ *
+ *		// Query the hardware to determine which interface needs processing.
+ *		xInterfaceToService = prvCheckInterfaces();
+ *
+ *      // The actual processing is to be deferred to a task.  Request the
+ *      // vProcessInterface() callback function is executed, passing in the
+ *		// number of the interface that needs processing.  The interface to
+ *		// service is passed in the second parameter.  The first parameter is
+ *		// not used in this case.
+ *		xHigherPriorityTaskWoken = pdFALSE;
+ *		xTimerPendFunctionCallFromISR( vProcessInterface, NULL, ( uint32_t ) xInterfaceToService, &xHigherPriorityTaskWoken );
+ *
+ *		// If xHigherPriorityTaskWoken is now set to pdTRUE then a context
+ *		// switch should be requested.  The macro used is port specific and will
+ *		// be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - refer to
+ *		// the documentation page for the port being used.
+ *		portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ *
+ *	}
+ * @endverbatim
+ */
+BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken );
+
+ /**
+  * BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
+  *                                    void *pvParameter1,
+  *                                    uint32_t ulParameter2,
+  *                                    TickType_t xTicksToWait );
+  *
+  *
+  * Used to defer the execution of a function to the RTOS daemon task (the timer
+  * service task, hence this function is implemented in timers.c and is prefixed
+  * with 'Timer').
+  *
+  * @param xFunctionToPend The function to execute from the timer service/
+  * daemon task.  The function must conform to the PendedFunction_t
+  * prototype.
+  *
+  * @param pvParameter1 The value of the callback function's first parameter.
+  * The parameter has a void * type to allow it to be used to pass any type.
+  * For example, unsigned longs can be cast to a void *, or the void * can be
+  * used to point to a structure.
+  *
+  * @param ulParameter2 The value of the callback function's second parameter.
+  *
+  * @param xTicksToWait Calling this function will result in a message being
+  * sent to the timer daemon task on a queue.  xTicksToWait is the amount of
+  * time the calling task should remain in the Blocked state (so not using any
+  * processing time) for space to become available on the timer queue if the
+  * queue is found to be full.
+  *
+  * @return pdPASS is returned if the message was successfully sent to the
+  * timer daemon task, otherwise pdFALSE is returned.
+  *
+  */
+BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait );
+
+/**
+ * const char * const pcTimerGetTimerName( TimerHandle_t xTimer );
+ *
+ * Returns the name that was assigned to a timer when the timer was created.
+ *
+ * @param xTimer The handle of the timer being queried.
+ *
+ * @return The name assigned to the timer specified by the xTimer parameter.
+ */
+const char * pcTimerGetTimerName( TimerHandle_t xTimer ); /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/*
+ * Functions beyond this part are not part of the public API and are intended
+ * for use by the kernel only.
+ */
+BaseType_t xTimerCreateTimerTask( void ) PRIVILEGED_FUNCTION;
+BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* TIMERS_H */
+
+
+
diff --git a/tools/sdk/include/freertos/freertos/xtensa_api.h b/tools/sdk/include/freertos/freertos/xtensa_api.h
new file mode 100644
index 00000000..04ad7d62
--- /dev/null
+++ b/tools/sdk/include/freertos/freertos/xtensa_api.h
@@ -0,0 +1,118 @@
+/*******************************************************************************
+Copyright (c) 2006-2015 Cadence Design Systems Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice shall be included
+in all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+******************************************************************************/
+
+/******************************************************************************
+  Xtensa-specific API for RTOS ports.
+******************************************************************************/
+
+#ifndef __XTENSA_API_H__
+#define __XTENSA_API_H__
+
+#include 
+
+#include "xtensa_context.h"
+
+
+/* Typedef for C-callable interrupt handler function */
+typedef void (*xt_handler)(void *);
+
+/* Typedef for C-callable exception handler function */
+typedef void (*xt_exc_handler)(XtExcFrame *);
+
+
+/*
+-------------------------------------------------------------------------------
+  Call this function to set a handler for the specified exception.
+
+    n        - Exception number (type)
+    f        - Handler function address, NULL to uninstall handler.
+
+  The handler will be passed a pointer to the exception frame, which is created
+  on the stack of the thread that caused the exception.
+
+  If the handler returns, the thread context will be restored and the faulting
+  instruction will be retried. Any values in the exception frame that are
+  modified by the handler will be restored as part of the context. For details
+  of the exception frame structure see xtensa_context.h.
+-------------------------------------------------------------------------------
+*/
+extern xt_exc_handler xt_set_exception_handler(int n, xt_exc_handler f);
+
+
+/*
+-------------------------------------------------------------------------------
+  Call this function to set a handler for the specified interrupt.
+ 
+    n        - Interrupt number.
+    f        - Handler function address, NULL to uninstall handler.
+    arg      - Argument to be passed to handler.
+-------------------------------------------------------------------------------
+*/
+extern xt_handler xt_set_interrupt_handler(int n, xt_handler f, void * arg);
+
+
+/*
+-------------------------------------------------------------------------------
+  Call this function to enable the specified interrupts.
+
+    mask     - Bit mask of interrupts to be enabled.
+-------------------------------------------------------------------------------
+*/
+extern void xt_ints_on(unsigned int mask);
+
+
+/*
+-------------------------------------------------------------------------------
+  Call this function to disable the specified interrupts.
+
+    mask     - Bit mask of interrupts to be disabled.
+-------------------------------------------------------------------------------
+*/
+extern void xt_ints_off(unsigned int mask);
+
+
+/*
+-------------------------------------------------------------------------------
+  Call this function to set the specified (s/w) interrupt.
+-------------------------------------------------------------------------------
+*/
+static inline void xt_set_intset(unsigned int arg)
+{
+    xthal_set_intset(arg);
+}
+
+
+/*
+-------------------------------------------------------------------------------
+  Call this function to clear the specified (s/w or edge-triggered)
+  interrupt.
+-------------------------------------------------------------------------------
+*/
+static inline void xt_set_intclear(unsigned int arg)
+{
+    xthal_set_intclear(arg);
+}
+
+
+#endif /* __XTENSA_API_H__ */
+
diff --git a/tools/sdk/include/freertos/freertos/xtensa_config.h b/tools/sdk/include/freertos/freertos/xtensa_config.h
new file mode 100644
index 00000000..58baee2d
--- /dev/null
+++ b/tools/sdk/include/freertos/freertos/xtensa_config.h
@@ -0,0 +1,146 @@
+/*******************************************************************************
+// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
+//
+// Permission is hereby granted, free of charge, to any person obtaining
+// a copy of this software and associated documentation files (the
+// "Software"), to deal in the Software without restriction, including
+// without limitation the rights to use, copy, modify, merge, publish,
+// distribute, sublicense, and/or sell copies of the Software, and to
+// permit persons to whom the Software is furnished to do so, subject to
+// the following conditions:
+//
+// The above copyright notice and this permission notice shall be included
+// in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+--------------------------------------------------------------------------------
+
+  Configuration-specific information for Xtensa build. This file must be
+  included in FreeRTOSConfig.h to properly set up the config-dependent
+  parameters correctly.
+
+  NOTE: To enable thread-safe C library support, XT_USE_THREAD_SAFE_CLIB must
+  be defined to be > 0 somewhere above or on the command line.
+
+*******************************************************************************/
+
+#ifndef XTENSA_CONFIG_H
+#define XTENSA_CONFIG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include 
+#include 
+#include 	/* required for XSHAL_CLIB */
+
+#include "xtensa_context.h"
+
+
+/*-----------------------------------------------------------------------------
+*                                 STACK REQUIREMENTS
+*
+* This section defines the minimum stack size, and the extra space required to
+* be allocated for saving coprocessor state and/or C library state information
+* (if thread safety is enabled for the C library). The sizes are in bytes.
+*
+* Stack sizes for individual tasks should be derived from these minima based on
+* the maximum call depth of the task and the maximum level of interrupt nesting.
+* A minimum stack size is defined by XT_STACK_MIN_SIZE. This minimum is based
+* on the requirement for a task that calls nothing else but can be interrupted.
+* This assumes that interrupt handlers do not call more than a few levels deep.
+* If this is not true, i.e. one or more interrupt handlers make deep calls then
+* the minimum must be increased.
+*
+* If the Xtensa processor configuration includes coprocessors, then space is 
+* allocated to save the coprocessor state on the stack.
+*
+* If thread safety is enabled for the C runtime library, (XT_USE_THREAD_SAFE_CLIB
+* is defined) then space is allocated to save the C library context in the TCB.
+* 
+* Allocating insufficient stack space is a common source of hard-to-find errors.
+* During development, it is best to enable the FreeRTOS stack checking features.
+*
+* Usage:
+* 
+* XT_USE_THREAD_SAFE_CLIB -- Define this to a nonzero value to enable thread-safe
+*                            use of the C library. This will require extra stack
+*                            space to be allocated for tasks that use the C library
+*                            reentrant functions. See below for more information.
+* 
+* NOTE: The Xtensa toolchain supports multiple C libraries and not all of them
+* support thread safety. Check your core configuration to see which C library
+* was chosen for your system.
+* 
+* XT_STACK_MIN_SIZE       -- The minimum stack size for any task. It is recommended
+*                            that you do not use a stack smaller than this for any
+*                            task. In case you want to use stacks smaller than this
+*                            size, you must verify that the smaller size(s) will work
+*                            under all operating conditions.
+*
+* XT_STACK_EXTRA          -- The amount of extra stack space to allocate for a task
+*                            that does not make C library reentrant calls. Add this
+*                            to the amount of stack space required by the task itself.
+*
+* XT_STACK_EXTRA_CLIB     -- The amount of space to allocate for C library state.
+*
+-----------------------------------------------------------------------------*/
+
+/* Extra space required for interrupt/exception hooks. */
+#ifdef XT_INTEXC_HOOKS
+  #ifdef __XTENSA_CALL0_ABI__
+    #define STK_INTEXC_EXTRA        0x200
+  #else
+    #define STK_INTEXC_EXTRA        0x180
+  #endif
+#else
+  #define STK_INTEXC_EXTRA          0
+#endif
+
+#define XT_CLIB_CONTEXT_AREA_SIZE         0
+
+/*------------------------------------------------------------------------------
+  Extra size -- interrupt frame plus coprocessor save area plus hook space.
+  NOTE: Make sure XT_INTEXC_HOOKS is undefined unless you really need the hooks.
+------------------------------------------------------------------------------*/
+#ifdef __XTENSA_CALL0_ABI__
+  #define XT_XTRA_SIZE            (XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x10 + XT_CP_SIZE)
+#else
+  #define XT_XTRA_SIZE            (XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x20 + XT_CP_SIZE)
+#endif
+
+/*------------------------------------------------------------------------------
+  Space allocated for user code -- function calls and local variables.
+  NOTE: This number can be adjusted to suit your needs. You must verify that the
+  amount of space you reserve is adequate for the worst-case conditions in your
+  application.
+  NOTE: The windowed ABI requires more stack, since space has to be reserved
+  for spilling register windows.
+------------------------------------------------------------------------------*/
+#ifdef __XTENSA_CALL0_ABI__
+  #define XT_USER_SIZE            0x200
+#else
+  #define XT_USER_SIZE            0x400
+#endif
+
+/* Minimum recommended stack size. */
+#define XT_STACK_MIN_SIZE         ((XT_XTRA_SIZE + XT_USER_SIZE) / sizeof(unsigned char))
+
+/* OS overhead with and without C library thread context. */
+#define XT_STACK_EXTRA            (XT_XTRA_SIZE)
+#define XT_STACK_EXTRA_CLIB       (XT_XTRA_SIZE + XT_CLIB_CONTEXT_AREA_SIZE)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XTENSA_CONFIG_H */
+
diff --git a/tools/sdk/include/freertos/freertos/xtensa_context.h b/tools/sdk/include/freertos/freertos/xtensa_context.h
new file mode 100644
index 00000000..3167c847
--- /dev/null
+++ b/tools/sdk/include/freertos/freertos/xtensa_context.h
@@ -0,0 +1,383 @@
+/*******************************************************************************
+Copyright (c) 2006-2015 Cadence Design Systems Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice shall be included
+in all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+--------------------------------------------------------------------------------
+
+        XTENSA CONTEXT FRAMES AND MACROS FOR RTOS ASSEMBLER SOURCES
+
+This header contains definitions and macros for use primarily by Xtensa
+RTOS assembly coded source files. It includes and uses the Xtensa hardware
+abstraction layer (HAL) to deal with config specifics. It may also be
+included in C source files.
+
+!! Supports only Xtensa Exception Architecture 2 (XEA2). XEA1 not supported. !!
+
+NOTE: The Xtensa architecture requires stack pointer alignment to 16 bytes.
+
+*******************************************************************************/
+
+#ifndef XTENSA_CONTEXT_H
+#define XTENSA_CONTEXT_H
+
+#ifdef __ASSEMBLER__
+#include    
+#endif
+
+#include    
+#include    
+#include    
+#include 
+
+
+/* Align a value up to nearest n-byte boundary, where n is a power of 2. */
+#define ALIGNUP(n, val) (((val) + (n)-1) & -(n))
+
+
+/*
+-------------------------------------------------------------------------------
+  Macros that help define structures for both C and assembler.
+-------------------------------------------------------------------------------
+*/
+
+#ifdef STRUCT_BEGIN
+#undef STRUCT_BEGIN
+#undef STRUCT_FIELD
+#undef STRUCT_AFIELD
+#undef STRUCT_END
+#endif
+
+#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
+
+#define STRUCT_BEGIN            .pushsection .text; .struct 0
+#define STRUCT_FIELD(ctype,size,asname,name)    asname: .space  size
+#define STRUCT_AFIELD(ctype,size,asname,name,n) asname: .space  (size)*(n)
+#define STRUCT_END(sname)       sname##Size:; .popsection
+
+#else
+
+#define STRUCT_BEGIN            typedef struct {
+#define STRUCT_FIELD(ctype,size,asname,name)    ctype   name;
+#define STRUCT_AFIELD(ctype,size,asname,name,n) ctype   name[n];
+#define STRUCT_END(sname)       } sname;
+
+#endif //_ASMLANGUAGE || __ASSEMBLER__
+
+
+/*
+-------------------------------------------------------------------------------
+  INTERRUPT/EXCEPTION STACK FRAME FOR A THREAD OR NESTED INTERRUPT
+
+  A stack frame of this structure is allocated for any interrupt or exception.
+  It goes on the current stack. If the RTOS has a system stack for handling 
+  interrupts, every thread stack must allow space for just one interrupt stack 
+  frame, then nested interrupt stack frames go on the system stack.
+
+  The frame includes basic registers (explicit) and "extra" registers introduced 
+  by user TIE or the use of the MAC16 option in the user's Xtensa config.
+  The frame size is minimized by omitting regs not applicable to user's config.
+
+  For Windowed ABI, this stack frame includes the interruptee's base save area,
+  another base save area to manage gcc nested functions, and a little temporary 
+  space to help manage the spilling of the register windows.
+-------------------------------------------------------------------------------
+*/
+
+STRUCT_BEGIN
+STRUCT_FIELD (long, 4, XT_STK_EXIT,     exit) /* exit point for dispatch */
+STRUCT_FIELD (long, 4, XT_STK_PC,       pc)   /* return PC */
+STRUCT_FIELD (long, 4, XT_STK_PS,       ps)   /* return PS */
+STRUCT_FIELD (long, 4, XT_STK_A0,       a0)
+STRUCT_FIELD (long, 4, XT_STK_A1,       a1)   /* stack pointer before interrupt */
+STRUCT_FIELD (long, 4, XT_STK_A2,       a2)
+STRUCT_FIELD (long, 4, XT_STK_A3,       a3)
+STRUCT_FIELD (long, 4, XT_STK_A4,       a4)
+STRUCT_FIELD (long, 4, XT_STK_A5,       a5)
+STRUCT_FIELD (long, 4, XT_STK_A6,       a6)
+STRUCT_FIELD (long, 4, XT_STK_A7,       a7)
+STRUCT_FIELD (long, 4, XT_STK_A8,       a8)
+STRUCT_FIELD (long, 4, XT_STK_A9,       a9)
+STRUCT_FIELD (long, 4, XT_STK_A10,      a10)
+STRUCT_FIELD (long, 4, XT_STK_A11,      a11)
+STRUCT_FIELD (long, 4, XT_STK_A12,      a12)
+STRUCT_FIELD (long, 4, XT_STK_A13,      a13)
+STRUCT_FIELD (long, 4, XT_STK_A14,      a14)
+STRUCT_FIELD (long, 4, XT_STK_A15,      a15)
+STRUCT_FIELD (long, 4, XT_STK_SAR,      sar)
+STRUCT_FIELD (long, 4, XT_STK_EXCCAUSE, exccause)
+STRUCT_FIELD (long, 4, XT_STK_EXCVADDR, excvaddr)
+#if XCHAL_HAVE_LOOPS
+STRUCT_FIELD (long, 4, XT_STK_LBEG,   lbeg)
+STRUCT_FIELD (long, 4, XT_STK_LEND,   lend)
+STRUCT_FIELD (long, 4, XT_STK_LCOUNT, lcount)
+#endif
+#ifndef __XTENSA_CALL0_ABI__
+/* Temporary space for saving stuff during window spill */
+STRUCT_FIELD (long, 4, XT_STK_TMP0,   tmp0)
+STRUCT_FIELD (long, 4, XT_STK_TMP1,   tmp1)
+STRUCT_FIELD (long, 4, XT_STK_TMP2,   tmp2)
+#endif
+#ifdef XT_USE_SWPRI
+/* Storage for virtual priority mask */
+STRUCT_FIELD (long, 4, XT_STK_VPRI,   vpri)
+#endif
+#ifdef XT_USE_OVLY
+/* Storage for overlay state */
+STRUCT_FIELD (long, 4, XT_STK_OVLY,   ovly)
+#endif
+STRUCT_END(XtExcFrame)
+
+#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
+#define XT_STK_NEXT1      XtExcFrameSize
+#else
+#define XT_STK_NEXT1      sizeof(XtExcFrame)
+#endif
+
+/* Allocate extra storage if needed */
+#if XCHAL_EXTRA_SA_SIZE != 0
+
+#if XCHAL_EXTRA_SA_ALIGN <= 16
+#define XT_STK_EXTRA            ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1)
+#else
+/* If need more alignment than stack, add space for dynamic alignment */
+#define XT_STK_EXTRA            (ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1) + XCHAL_EXTRA_SA_ALIGN)
+#endif
+#define XT_STK_NEXT2            (XT_STK_EXTRA + XCHAL_EXTRA_SA_SIZE)
+
+#else
+
+#define XT_STK_NEXT2            XT_STK_NEXT1   
+
+#endif
+
+/*
+-------------------------------------------------------------------------------
+  This is the frame size. Add space for 4 registers (interruptee's base save
+  area) and some space for gcc nested functions if any.
+-------------------------------------------------------------------------------
+*/
+#define XT_STK_FRMSZ            (ALIGNUP(0x10, XT_STK_NEXT2) + 0x20)
+
+
+/*
+-------------------------------------------------------------------------------
+  SOLICITED STACK FRAME FOR A THREAD
+
+  A stack frame of this structure is allocated whenever a thread enters the 
+  RTOS kernel intentionally (and synchronously) to submit to thread scheduling.
+  It goes on the current thread's stack.
+
+  The solicited frame only includes registers that are required to be preserved
+  by the callee according to the compiler's ABI conventions, some space to save 
+  the return address for returning to the caller, and the caller's PS register.
+
+  For Windowed ABI, this stack frame includes the caller's base save area.
+
+  Note on XT_SOL_EXIT field:
+      It is necessary to distinguish a solicited from an interrupt stack frame.
+      This field corresponds to XT_STK_EXIT in the interrupt stack frame and is
+      always at the same offset (0). It can be written with a code (usually 0) 
+      to distinguish a solicted frame from an interrupt frame. An RTOS port may
+      opt to ignore this field if it has another way of distinguishing frames.
+-------------------------------------------------------------------------------
+*/
+
+STRUCT_BEGIN
+#ifdef __XTENSA_CALL0_ABI__
+STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit)
+STRUCT_FIELD (long, 4, XT_SOL_PC,   pc)
+STRUCT_FIELD (long, 4, XT_SOL_PS,   ps)
+STRUCT_FIELD (long, 4, XT_SOL_NEXT, next)
+STRUCT_FIELD (long, 4, XT_SOL_A12,  a12)    /* should be on 16-byte alignment */
+STRUCT_FIELD (long, 4, XT_SOL_A13,  a13)
+STRUCT_FIELD (long, 4, XT_SOL_A14,  a14)
+STRUCT_FIELD (long, 4, XT_SOL_A15,  a15)
+#else
+STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit)
+STRUCT_FIELD (long, 4, XT_SOL_PC,   pc)
+STRUCT_FIELD (long, 4, XT_SOL_PS,   ps)
+STRUCT_FIELD (long, 4, XT_SOL_NEXT, next)
+STRUCT_FIELD (long, 4, XT_SOL_A0,   a0)    /* should be on 16-byte alignment */
+STRUCT_FIELD (long, 4, XT_SOL_A1,   a1)
+STRUCT_FIELD (long, 4, XT_SOL_A2,   a2)
+STRUCT_FIELD (long, 4, XT_SOL_A3,   a3)
+#endif
+STRUCT_END(XtSolFrame)
+
+/* Size of solicited stack frame */
+#define XT_SOL_FRMSZ            ALIGNUP(0x10, XtSolFrameSize)
+
+
+/*
+-------------------------------------------------------------------------------
+  CO-PROCESSOR STATE SAVE AREA FOR A THREAD
+
+  The RTOS must provide an area per thread to save the state of co-processors
+  when that thread does not have control. Co-processors are context-switched
+  lazily (on demand) only when a new thread uses a co-processor instruction,
+  otherwise a thread retains ownership of the co-processor even when it loses
+  control of the processor. An Xtensa co-processor exception is triggered when
+  any co-processor instruction is executed by a thread that is not the owner,
+  and the context switch of that co-processor is then peformed by the handler.
+  Ownership represents which thread's state is currently in the co-processor.
+
+  Co-processors may not be used by interrupt or exception handlers. If an 
+  co-processor instruction is executed by an interrupt or exception handler,
+  the co-processor exception handler will trigger a kernel panic and freeze.
+  This restriction is introduced to reduce the overhead of saving and restoring
+  co-processor state (which can be quite large) and in particular remove that
+  overhead from interrupt handlers.
+
+  The co-processor state save area may be in any convenient per-thread location
+  such as in the thread control block or above the thread stack area. It need
+  not be in the interrupt stack frame since interrupts don't use co-processors.
+
+  Along with the save area for each co-processor, two bitmasks with flags per 
+  co-processor (laid out as in the CPENABLE reg) help manage context-switching
+  co-processors as efficiently as possible:
+
+  XT_CPENABLE
+    The contents of a non-running thread's CPENABLE register.
+    It represents the co-processors owned (and whose state is still needed)
+    by the thread. When a thread is preempted, its CPENABLE is saved here.
+    When a thread solicits a context-swtich, its CPENABLE is cleared - the
+    compiler has saved the (caller-saved) co-proc state if it needs to.
+    When a non-running thread loses ownership of a CP, its bit is cleared.
+    When a thread runs, it's XT_CPENABLE is loaded into the CPENABLE reg.
+    Avoids co-processor exceptions when no change of ownership is needed.
+
+  XT_CPSTORED
+    A bitmask with the same layout as CPENABLE, a bit per co-processor.
+    Indicates whether the state of each co-processor is saved in the state 
+    save area. When a thread enters the kernel, only the state of co-procs
+    still enabled in CPENABLE is saved. When the co-processor exception 
+    handler assigns ownership of a co-processor to a thread, it restores 
+    the saved state only if this bit is set, and clears this bit.
+
+  XT_CP_CS_ST
+    A bitmask with the same layout as CPENABLE, a bit per co-processor.
+    Indicates whether callee-saved state is saved in the state save area.
+    Callee-saved state is saved by itself on a solicited context switch,
+    and restored when needed by the coprocessor exception handler.
+    Unsolicited switches will cause the entire coprocessor to be saved
+    when necessary.
+
+  XT_CP_ASA
+    Pointer to the aligned save area.  Allows it to be aligned more than
+    the overall save area (which might only be stack-aligned or TCB-aligned).
+    Especially relevant for Xtensa cores configured with a very large data
+    path that requires alignment greater than 16 bytes (ABI stack alignment).
+-------------------------------------------------------------------------------
+*/
+
+#if XCHAL_CP_NUM > 0
+
+/*  Offsets of each coprocessor save area within the 'aligned save area':  */
+#define XT_CP0_SA   0
+#define XT_CP1_SA   ALIGNUP(XCHAL_CP1_SA_ALIGN, XT_CP0_SA + XCHAL_CP0_SA_SIZE)
+#define XT_CP2_SA   ALIGNUP(XCHAL_CP2_SA_ALIGN, XT_CP1_SA + XCHAL_CP1_SA_SIZE)
+#define XT_CP3_SA   ALIGNUP(XCHAL_CP3_SA_ALIGN, XT_CP2_SA + XCHAL_CP2_SA_SIZE)
+#define XT_CP4_SA   ALIGNUP(XCHAL_CP4_SA_ALIGN, XT_CP3_SA + XCHAL_CP3_SA_SIZE)
+#define XT_CP5_SA   ALIGNUP(XCHAL_CP5_SA_ALIGN, XT_CP4_SA + XCHAL_CP4_SA_SIZE)
+#define XT_CP6_SA   ALIGNUP(XCHAL_CP6_SA_ALIGN, XT_CP5_SA + XCHAL_CP5_SA_SIZE)
+#define XT_CP7_SA   ALIGNUP(XCHAL_CP7_SA_ALIGN, XT_CP6_SA + XCHAL_CP6_SA_SIZE)
+#define XT_CP_SA_SIZE   ALIGNUP(16, XT_CP7_SA + XCHAL_CP7_SA_SIZE)
+
+/*  Offsets within the overall save area:  */
+#define XT_CPENABLE 0   /* (2 bytes) coprocessors active for this thread */
+#define XT_CPSTORED 2   /* (2 bytes) coprocessors saved for this thread */
+#define XT_CP_CS_ST 4   /* (2 bytes) coprocessor callee-saved regs stored for this thread */
+#define XT_CP_ASA   8   /* (4 bytes) ptr to aligned save area */
+/*  Overall size allows for dynamic alignment:  */
+#define XT_CP_SIZE  (12 + XT_CP_SA_SIZE + XCHAL_TOTAL_SA_ALIGN)
+#else
+#define XT_CP_SIZE  0
+#endif
+
+
+/*
+ Macro to get the current core ID. Only uses the reg given as an argument.
+ Reading PRID on the ESP108 architecture gives us 0xCDCD on the PRO processor
+ and 0xABAB on the APP CPU. We distinguish between the two by simply checking 
+ bit 1: it's 1 on the APP and 0 on the PRO processor.
+*/
+
+#ifdef __ASSEMBLER__
+	.macro getcoreid reg
+	rsr.prid \reg
+	bbci \reg,1,1f
+	movi \reg,1
+	j 2f
+1:
+	movi \reg,0
+2:
+	.endm
+#endif
+
+
+
+/*
+-------------------------------------------------------------------------------
+  MACROS TO HANDLE ABI SPECIFICS OF FUNCTION ENTRY AND RETURN
+
+  Convenient where the frame size requirements are the same for both ABIs.
+    ENTRY(sz), RET(sz) are for framed functions (have locals or make calls).
+    ENTRY0,    RET0    are for frameless functions (no locals, no calls).
+
+  where size = size of stack frame in bytes (must be >0 and aligned to 16).
+  For framed functions the frame is created and the return address saved at
+  base of frame (Call0 ABI) or as determined by hardware (Windowed ABI).
+  For frameless functions, there is no frame and return address remains in a0.
+  Note: Because CPP macros expand to a single line, macros requiring multi-line 
+  expansions are implemented as assembler macros.
+-------------------------------------------------------------------------------
+*/
+
+#ifdef __ASSEMBLER__
+#ifdef __XTENSA_CALL0_ABI__
+  /* Call0 */
+  #define ENTRY(sz)     entry1  sz
+    .macro  entry1 size=0x10
+    addi    sp, sp, -\size
+    s32i    a0, sp, 0
+    .endm
+  #define ENTRY0      
+  #define RET(sz)       ret1    sz
+    .macro  ret1 size=0x10
+    l32i    a0, sp, 0
+    addi    sp, sp, \size
+    ret
+    .endm
+  #define RET0          ret
+#else
+  /* Windowed */
+  #define ENTRY(sz)     entry   sp, sz
+  #define ENTRY0        entry   sp, 0x10
+  #define RET(sz)       retw
+  #define RET0          retw
+#endif
+#endif
+
+
+
+
+
+#endif /* XTENSA_CONTEXT_H */
+
diff --git a/tools/sdk/include/freertos/freertos/xtensa_rtos.h b/tools/sdk/include/freertos/freertos/xtensa_rtos.h
new file mode 100644
index 00000000..980cc92e
--- /dev/null
+++ b/tools/sdk/include/freertos/freertos/xtensa_rtos.h
@@ -0,0 +1,233 @@
+/*******************************************************************************
+// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
+//
+// Permission is hereby granted, free of charge, to any person obtaining
+// a copy of this software and associated documentation files (the
+// "Software"), to deal in the Software without restriction, including
+// without limitation the rights to use, copy, modify, merge, publish,
+// distribute, sublicense, and/or sell copies of the Software, and to
+// permit persons to whom the Software is furnished to do so, subject to
+// the following conditions:
+//
+// The above copyright notice and this permission notice shall be included
+// in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+--------------------------------------------------------------------------------
+
+        RTOS-SPECIFIC INFORMATION FOR XTENSA RTOS ASSEMBLER SOURCES
+                            (FreeRTOS Port)
+
+This header is the primary glue between generic Xtensa RTOS support
+sources and a specific RTOS port for Xtensa.  It contains definitions
+and macros for use primarily by Xtensa assembly coded source files.
+
+Macros in this header map callouts from generic Xtensa files to specific
+RTOS functions. It may also be included in C source files.
+
+Xtensa RTOS ports support all RTOS-compatible configurations of the Xtensa 
+architecture, using the Xtensa hardware abstraction layer (HAL) to deal 
+with configuration specifics.
+
+Should be included by all Xtensa generic and RTOS port-specific sources.
+
+*******************************************************************************/
+
+#ifndef XTENSA_RTOS_H
+#define XTENSA_RTOS_H
+
+#ifdef __ASSEMBLER__
+#include    
+#else
+#include    
+#endif
+
+#include    
+#include    
+#include    
+
+/*
+Include any RTOS specific definitions that are needed by this header.
+*/
+#include    
+
+/*
+Convert FreeRTOSConfig definitions to XTENSA definitions.
+However these can still be overridden from the command line.
+*/
+
+#ifndef XT_SIMULATOR
+  #if configXT_SIMULATOR
+    #define XT_SIMULATOR             1  /* Simulator mode */
+  #endif
+#endif
+
+#ifndef XT_BOARD
+  #if configXT_BOARD
+    #define XT_BOARD                 1  /* Board mode */
+  #endif
+#endif
+
+#ifndef XT_TIMER_INDEX
+  #if defined configXT_TIMER_INDEX
+    #define XT_TIMER_INDEX           configXT_TIMER_INDEX  /* Index of hardware timer to be used */
+  #endif
+#endif
+
+#ifndef XT_INTEXC_HOOKS
+  #if configXT_INTEXC_HOOKS
+    #define XT_INTEXC_HOOKS          1  /* Enables exception hooks */
+  #endif
+#endif
+
+#if !defined(XT_SIMULATOR) && !defined(XT_BOARD)
+  #error Either XT_SIMULATOR or XT_BOARD must be defined.
+#endif
+
+
+/*
+Name of RTOS (for messages).
+*/
+#define XT_RTOS_NAME    FreeRTOS
+
+/*
+Check some Xtensa configuration requirements and report error if not met.
+Error messages can be customize to the RTOS port.
+*/
+
+#if !XCHAL_HAVE_XEA2
+#error "FreeRTOS/Xtensa requires XEA2 (exception architecture 2)."
+#endif
+
+
+/*******************************************************************************
+
+RTOS CALLOUT MACROS MAPPED TO RTOS PORT-SPECIFIC FUNCTIONS.
+
+Define callout macros used in generic Xtensa code to interact with the RTOS.
+The macros are simply the function names for use in calls from assembler code.
+Some of these functions may call back to generic functions in xtensa_context.h .
+
+*******************************************************************************/
+
+/*
+Inform RTOS of entry into an interrupt handler that will affect it. 
+Allows RTOS to manage switch to any system stack and count nesting level.
+Called after minimal context has been saved, with interrupts disabled.
+RTOS port can call0 _xt_context_save to save the rest of the context.
+May only be called from assembly code by the 'call0' instruction.
+*/
+// void XT_RTOS_INT_ENTER(void)
+#define XT_RTOS_INT_ENTER   _frxt_int_enter
+
+/*
+Inform RTOS of completion of an interrupt handler, and give control to
+RTOS to perform thread/task scheduling, switch back from any system stack
+and restore the context, and return to the exit dispatcher saved in the
+stack frame at XT_STK_EXIT. RTOS port can call0 _xt_context_restore
+to save the context saved in XT_RTOS_INT_ENTER via _xt_context_save,
+leaving only a minimal part of the context to be restored by the exit
+dispatcher. This function does not return to the place it was called from.
+May only be called from assembly code by the 'call0' instruction.
+*/
+// void XT_RTOS_INT_EXIT(void)
+#define XT_RTOS_INT_EXIT    _frxt_int_exit
+
+/*
+Inform RTOS of the occurrence of a tick timer interrupt.
+If RTOS has no tick timer, leave XT_RTOS_TIMER_INT undefined.
+May be coded in or called from C or assembly, per ABI conventions.
+RTOS may optionally define XT_TICK_PER_SEC in its own way (eg. macro).
+*/
+// void XT_RTOS_TIMER_INT(void)
+#define XT_RTOS_TIMER_INT   _frxt_timer_int
+#define XT_TICK_PER_SEC     configTICK_RATE_HZ
+
+/*
+Return in a15 the base address of the co-processor state save area for the 
+thread that triggered a co-processor exception, or 0 if no thread was running.
+The state save area is structured as defined in xtensa_context.h and has size 
+XT_CP_SIZE. Co-processor instructions should only be used in thread code, never
+in interrupt handlers or the RTOS kernel. May only be called from assembly code
+and by the 'call0' instruction. A result of 0 indicates an unrecoverable error. 
+The implementation may use only a2-4, a15 (all other regs must be preserved).
+*/
+// void* XT_RTOS_CP_STATE(void)
+#define XT_RTOS_CP_STATE    _frxt_task_coproc_state
+
+
+/*******************************************************************************
+
+HOOKS TO DYNAMICALLY INSTALL INTERRUPT AND EXCEPTION HANDLERS PER LEVEL.
+
+This Xtensa RTOS port provides hooks for dynamically installing exception
+and interrupt handlers to facilitate automated testing where each test
+case can install its own handler for user exceptions and each interrupt
+priority (level). This consists of an array of function pointers indexed
+by interrupt priority, with index 0 being the user exception handler hook.
+Each entry in the array is initially 0, and may be replaced by a function 
+pointer of type XT_INTEXC_HOOK. A handler may be uninstalled by installing 0.
+
+The handler for low and medium priority obeys ABI conventions so may be coded
+in C. For the exception handler, the cause is the contents of the EXCCAUSE
+reg, and the result is -1 if handled, else the cause (still needs handling).
+For interrupt handlers, the cause is a mask of pending enabled interrupts at
+that level, and the result is the same mask with the bits for the handled
+interrupts cleared (those not cleared still need handling). This allows a test
+case to either pre-handle or override the default handling for the exception
+or interrupt level (see xtensa_vectors.S).
+
+High priority handlers (including NMI) must be coded in assembly, are always
+called by 'call0' regardless of ABI, must preserve all registers except a0,
+and must not use or modify the interrupted stack. The hook argument 'cause'
+is not passed and the result is ignored, so as not to burden the caller with
+saving and restoring a2 (it assumes only one interrupt per level - see the
+discussion in high priority interrupts in xtensa_vectors.S). The handler
+therefore should be coded to prototype 'void h(void)' even though it plugs
+into an array of handlers of prototype 'unsigned h(unsigned)'.
+
+To enable interrupt/exception hooks, compile the RTOS with '-DXT_INTEXC_HOOKS'.
+
+*******************************************************************************/
+
+#define XT_INTEXC_HOOK_NUM  (1 + XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI)
+
+#ifndef __ASSEMBLER__
+typedef unsigned (*XT_INTEXC_HOOK)(unsigned cause);
+extern  volatile XT_INTEXC_HOOK _xt_intexc_hooks[XT_INTEXC_HOOK_NUM];
+#endif
+
+
+/*******************************************************************************
+
+CONVENIENCE INCLUSIONS.
+
+Ensures RTOS specific files need only include this one Xtensa-generic header.
+These headers are included last so they can use the RTOS definitions above.
+
+*******************************************************************************/
+
+#include    "xtensa_context.h"
+
+#ifdef XT_RTOS_TIMER_INT
+#include    "xtensa_timer.h"
+#endif
+
+
+/*******************************************************************************
+
+Xtensa Port Version.
+
+*******************************************************************************/
+
+#define XTENSA_PORT_VERSION             1.4.2
+#define XTENSA_PORT_VERSION_STRING      "1.4.2"
+
+#endif /* XTENSA_RTOS_H */
+
diff --git a/tools/sdk/include/freertos/freertos/xtensa_timer.h b/tools/sdk/include/freertos/freertos/xtensa_timer.h
new file mode 100644
index 00000000..9bb8648f
--- /dev/null
+++ b/tools/sdk/include/freertos/freertos/xtensa_timer.h
@@ -0,0 +1,159 @@
+/*******************************************************************************
+// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
+//
+// Permission is hereby granted, free of charge, to any person obtaining
+// a copy of this software and associated documentation files (the
+// "Software"), to deal in the Software without restriction, including
+// without limitation the rights to use, copy, modify, merge, publish,
+// distribute, sublicense, and/or sell copies of the Software, and to
+// permit persons to whom the Software is furnished to do so, subject to
+// the following conditions:
+//
+// The above copyright notice and this permission notice shall be included
+// in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+--------------------------------------------------------------------------------
+
+        XTENSA INFORMATION FOR RTOS TICK TIMER AND CLOCK FREQUENCY
+
+This header contains definitions and macros for use primarily by Xtensa
+RTOS assembly coded source files. It includes and uses the Xtensa hardware
+abstraction layer (HAL) to deal with config specifics. It may also be
+included in C source files.
+
+User may edit to modify timer selection and to specify clock frequency and
+tick duration to match timer interrupt to the real-time tick duration.
+
+If the RTOS has no timer interrupt, then there is no tick timer and the
+clock frequency is irrelevant, so all of these macros are left undefined
+and the Xtensa core configuration need not have a timer.
+
+*******************************************************************************/
+
+#ifndef XTENSA_TIMER_H
+#define XTENSA_TIMER_H
+
+#ifdef __ASSEMBLER__
+#include    
+#endif
+
+#include    
+#include    
+
+#include    "xtensa_rtos.h"     /* in case this wasn't included directly */
+
+#include    
+
+/*
+Select timer to use for periodic tick, and determine its interrupt number 
+and priority. User may specify a timer by defining XT_TIMER_INDEX with -D,
+in which case its validity is checked (it must exist in this core and must 
+not be on a high priority interrupt - an error will be reported in invalid).
+Otherwise select the first low or medium priority interrupt timer available.
+*/
+#if XCHAL_NUM_TIMERS == 0
+
+  #error "This Xtensa configuration is unsupported, it has no timers."
+
+#else
+
+#ifndef XT_TIMER_INDEX
+  #if XCHAL_TIMER3_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
+    #if XCHAL_INT_LEVEL(XCHAL_TIMER3_INTERRUPT) <= XCHAL_EXCM_LEVEL
+      #undef  XT_TIMER_INDEX
+      #define XT_TIMER_INDEX    3
+    #endif
+  #endif
+  #if XCHAL_TIMER2_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
+    #if XCHAL_INT_LEVEL(XCHAL_TIMER2_INTERRUPT) <= XCHAL_EXCM_LEVEL
+      #undef  XT_TIMER_INDEX
+      #define XT_TIMER_INDEX    2
+    #endif
+  #endif
+  #if XCHAL_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
+    #if XCHAL_INT_LEVEL(XCHAL_TIMER1_INTERRUPT) <= XCHAL_EXCM_LEVEL
+      #undef  XT_TIMER_INDEX
+      #define XT_TIMER_INDEX    1
+    #endif
+  #endif
+  #if XCHAL_TIMER0_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
+    #if XCHAL_INT_LEVEL(XCHAL_TIMER0_INTERRUPT) <= XCHAL_EXCM_LEVEL
+      #undef  XT_TIMER_INDEX
+      #define XT_TIMER_INDEX    0
+    #endif
+  #endif
+#endif
+#ifndef XT_TIMER_INDEX
+  #error "There is no suitable timer in this Xtensa configuration."
+#endif
+
+#define XT_CCOMPARE             (CCOMPARE + XT_TIMER_INDEX)
+#define XT_TIMER_INTNUM         XCHAL_TIMER_INTERRUPT(XT_TIMER_INDEX)
+#define XT_TIMER_INTPRI         XCHAL_INT_LEVEL(XT_TIMER_INTNUM)
+#define XT_TIMER_INTEN          (1 << XT_TIMER_INTNUM)
+
+#if XT_TIMER_INTNUM == XTHAL_TIMER_UNCONFIGURED
+  #error "The timer selected by XT_TIMER_INDEX does not exist in this core."
+#elif XT_TIMER_INTPRI > XCHAL_EXCM_LEVEL
+  #error "The timer interrupt cannot be high priority (use medium or low)."
+#endif
+
+#endif /* XCHAL_NUM_TIMERS */
+
+/*
+Set processor clock frequency, used to determine clock divisor for timer tick.
+User should BE SURE TO ADJUST THIS for the Xtensa platform being used.
+If using a supported board via the board-independent API defined in xtbsp.h,
+this may be left undefined and frequency and tick divisor will be computed 
+and cached during run-time initialization.
+
+NOTE ON SIMULATOR:
+Under the Xtensa instruction set simulator, the frequency can only be estimated 
+because it depends on the speed of the host and the version of the simulator.
+Also because it runs much slower than hardware, it is not possible to achieve
+real-time performance for most applications under the simulator. A frequency
+too low does not allow enough time between timer interrupts, starving threads.
+To obtain a more convenient but non-real-time tick duration on the simulator, 
+compile with xt-xcc option "-DXT_SIMULATOR".
+Adjust this frequency to taste (it's not real-time anyway!).
+*/
+#if defined(XT_SIMULATOR) && !defined(XT_CLOCK_FREQ)
+#define XT_CLOCK_FREQ       configCPU_CLOCK_HZ
+#endif
+
+#if !defined(XT_CLOCK_FREQ) && !defined(XT_BOARD)
+  #error "XT_CLOCK_FREQ must be defined for the target platform."
+#endif
+
+/*
+Default number of timer "ticks" per second (default 100 for 10ms tick).
+RTOS may define this in its own way (if applicable) in xtensa_rtos.h.
+User may redefine this to an optimal value for the application, either by
+editing this here or in xtensa_rtos.h, or compiling with xt-xcc option
+"-DXT_TICK_PER_SEC=" where  is a suitable number.
+*/
+#ifndef XT_TICK_PER_SEC
+#define XT_TICK_PER_SEC    configTICK_RATE_HZ        /* 10 ms tick = 100 ticks per second */
+#endif
+
+/*
+Derivation of clock divisor for timer tick and interrupt (one per tick).
+*/
+#ifdef XT_CLOCK_FREQ
+#define XT_TICK_DIVISOR     (XT_CLOCK_FREQ / XT_TICK_PER_SEC)
+#endif
+
+#ifndef __ASSEMBLER__
+extern unsigned _xt_tick_divisor;
+extern void     _xt_tick_divisor_init(void);
+#endif
+
+#endif  /* XTENSA_TIMER_H */
+
diff --git a/tools/sdk/include/json/cJSON.h b/tools/sdk/include/json/cJSON.h
new file mode 100644
index 00000000..466d10db
--- /dev/null
+++ b/tools/sdk/include/json/cJSON.h
@@ -0,0 +1,149 @@
+/*
+  Copyright (c) 2009 Dave Gamble
+ 
+  Permission is hereby granted, free of charge, to any person obtaining a copy
+  of this software and associated documentation files (the "Software"), to deal
+  in the Software without restriction, including without limitation the rights
+  to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+  copies of the Software, and to permit persons to whom the Software is
+  furnished to do so, subject to the following conditions:
+ 
+  The above copyright notice and this permission notice shall be included in
+  all copies or substantial portions of the Software.
+ 
+  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+  AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+  OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+  THE SOFTWARE.
+*/
+
+#ifndef cJSON__h
+#define cJSON__h
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* cJSON Types: */
+#define cJSON_False 0
+#define cJSON_True 1
+#define cJSON_NULL 2
+#define cJSON_Number 3
+#define cJSON_String 4
+#define cJSON_Array 5
+#define cJSON_Object 6
+	
+#define cJSON_IsReference 256
+#define cJSON_StringIsConst 512
+
+/* The cJSON structure: */
+typedef struct cJSON {
+	struct cJSON *next,*prev;	/* next/prev allow you to walk array/object chains. Alternatively, use GetArraySize/GetArrayItem/GetObjectItem */
+	struct cJSON *child;		/* An array or object item will have a child pointer pointing to a chain of the items in the array/object. */
+
+	int type;					/* The type of the item, as above. */
+
+	char *valuestring;			/* The item's string, if type==cJSON_String */
+	int valueint;				/* The item's number, if type==cJSON_Number */
+	double valuedouble;			/* The item's number, if type==cJSON_Number */
+
+	char *string;				/* The item's name string, if this item is the child of, or is in the list of subitems of an object. */
+} cJSON;
+
+typedef struct cJSON_Hooks {
+      void *(*malloc_fn)(size_t sz);
+      void (*free_fn)(void *ptr);
+} cJSON_Hooks;
+
+/* Supply malloc, realloc and free functions to cJSON */
+extern void cJSON_InitHooks(cJSON_Hooks* hooks);
+
+
+/* Supply a block of JSON, and this returns a cJSON object you can interrogate. Call cJSON_Delete when finished. */
+extern cJSON *cJSON_Parse(const char *value);
+/* Render a cJSON entity to text for transfer/storage. Free the char* when finished. */
+extern char  *cJSON_Print(cJSON *item);
+/* Render a cJSON entity to text for transfer/storage without any formatting. Free the char* when finished. */
+extern char  *cJSON_PrintUnformatted(cJSON *item);
+/* Render a cJSON entity to text using a buffered strategy. prebuffer is a guess at the final size. guessing well reduces reallocation. fmt=0 gives unformatted, =1 gives formatted */
+extern char *cJSON_PrintBuffered(cJSON *item,int prebuffer,int fmt);
+/* Delete a cJSON entity and all subentities. */
+extern void   cJSON_Delete(cJSON *c);
+
+/* Returns the number of items in an array (or object). */
+extern int	  cJSON_GetArraySize(cJSON *array);
+/* Retrieve item number "item" from array "array". Returns NULL if unsuccessful. */
+extern cJSON *cJSON_GetArrayItem(cJSON *array,int item);
+/* Get item "string" from object. Case insensitive. */
+extern cJSON *cJSON_GetObjectItem(cJSON *object,const char *string);
+
+/* For analysing failed parses. This returns a pointer to the parse error. You'll probably need to look a few chars back to make sense of it. Defined when cJSON_Parse() returns 0. 0 when cJSON_Parse() succeeds. */
+extern const char *cJSON_GetErrorPtr(void);
+	
+/* These calls create a cJSON item of the appropriate type. */
+extern cJSON *cJSON_CreateNull(void);
+extern cJSON *cJSON_CreateTrue(void);
+extern cJSON *cJSON_CreateFalse(void);
+extern cJSON *cJSON_CreateBool(int b);
+extern cJSON *cJSON_CreateNumber(double num);
+extern cJSON *cJSON_CreateString(const char *string);
+extern cJSON *cJSON_CreateArray(void);
+extern cJSON *cJSON_CreateObject(void);
+
+/* These utilities create an Array of count items. */
+extern cJSON *cJSON_CreateIntArray(const int *numbers,int count);
+extern cJSON *cJSON_CreateFloatArray(const float *numbers,int count);
+extern cJSON *cJSON_CreateDoubleArray(const double *numbers,int count);
+extern cJSON *cJSON_CreateStringArray(const char **strings,int count);
+
+/* Append item to the specified array/object. */
+extern void cJSON_AddItemToArray(cJSON *array, cJSON *item);
+extern void	cJSON_AddItemToObject(cJSON *object,const char *string,cJSON *item);
+extern void	cJSON_AddItemToObjectCS(cJSON *object,const char *string,cJSON *item);	/* Use this when string is definitely const (i.e. a literal, or as good as), and will definitely survive the cJSON object */
+/* Append reference to item to the specified array/object. Use this when you want to add an existing cJSON to a new cJSON, but don't want to corrupt your existing cJSON. */
+extern void cJSON_AddItemReferenceToArray(cJSON *array, cJSON *item);
+extern void	cJSON_AddItemReferenceToObject(cJSON *object,const char *string,cJSON *item);
+
+/* Remove/Detatch items from Arrays/Objects. */
+extern cJSON *cJSON_DetachItemFromArray(cJSON *array,int which);
+extern void   cJSON_DeleteItemFromArray(cJSON *array,int which);
+extern cJSON *cJSON_DetachItemFromObject(cJSON *object,const char *string);
+extern void   cJSON_DeleteItemFromObject(cJSON *object,const char *string);
+	
+/* Update array items. */
+extern void cJSON_InsertItemInArray(cJSON *array,int which,cJSON *newitem);	/* Shifts pre-existing items to the right. */
+extern void cJSON_ReplaceItemInArray(cJSON *array,int which,cJSON *newitem);
+extern void cJSON_ReplaceItemInObject(cJSON *object,const char *string,cJSON *newitem);
+
+/* Duplicate a cJSON item */
+extern cJSON *cJSON_Duplicate(cJSON *item,int recurse);
+/* Duplicate will create a new, identical cJSON item to the one you pass, in new memory that will
+need to be released. With recurse!=0, it will duplicate any children connected to the item.
+The item->next and ->prev pointers are always zero on return from Duplicate. */
+
+/* ParseWithOpts allows you to require (and check) that the JSON is null terminated, and to retrieve the pointer to the final byte parsed. */
+extern cJSON *cJSON_ParseWithOpts(const char *value,const char **return_parse_end,int require_null_terminated);
+
+extern void cJSON_Minify(char *json);
+
+/* Macros for creating things quickly. */
+#define cJSON_AddNullToObject(object,name)		cJSON_AddItemToObject(object, name, cJSON_CreateNull())
+#define cJSON_AddTrueToObject(object,name)		cJSON_AddItemToObject(object, name, cJSON_CreateTrue())
+#define cJSON_AddFalseToObject(object,name)		cJSON_AddItemToObject(object, name, cJSON_CreateFalse())
+#define cJSON_AddBoolToObject(object,name,b)	cJSON_AddItemToObject(object, name, cJSON_CreateBool(b))
+#define cJSON_AddNumberToObject(object,name,n)	cJSON_AddItemToObject(object, name, cJSON_CreateNumber(n))
+#define cJSON_AddStringToObject(object,name,s)	cJSON_AddItemToObject(object, name, cJSON_CreateString(s))
+
+/* When assigning an integer value, it needs to be propagated to valuedouble too. */
+#define cJSON_SetIntValue(object,val)			((object)?(object)->valueint=(object)->valuedouble=(val):(val))
+#define cJSON_SetNumberValue(object,val)		((object)?(object)->valueint=(object)->valuedouble=(val):(val))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tools/sdk/include/json/cJSON_Utils.h b/tools/sdk/include/json/cJSON_Utils.h
new file mode 100644
index 00000000..b129b062
--- /dev/null
+++ b/tools/sdk/include/json/cJSON_Utils.h
@@ -0,0 +1,30 @@
+#include "cJSON.h"
+
+/* Implement RFC6901 (https://tools.ietf.org/html/rfc6901) JSON Pointer spec.	*/
+cJSON *cJSONUtils_GetPointer(cJSON *object,const char *pointer);
+
+/* Implement RFC6902 (https://tools.ietf.org/html/rfc6902) JSON Patch spec.		*/
+cJSON* cJSONUtils_GeneratePatches(cJSON *from,cJSON *to);
+void cJSONUtils_AddPatchToArray(cJSON *array,const char *op,const char *path,cJSON *val);	/* Utility for generating patch array entries.	*/
+int cJSONUtils_ApplyPatches(cJSON *object,cJSON *patches);	/* Returns 0 for success. */
+
+/*
+// Note that ApplyPatches is NOT atomic on failure. To implement an atomic ApplyPatches, use:
+//int cJSONUtils_AtomicApplyPatches(cJSON **object, cJSON *patches)
+//{
+//	cJSON *modme=cJSON_Duplicate(*object,1);
+//	int error=cJSONUtils_ApplyPatches(modme,patches);
+//	if (!error)	{cJSON_Delete(*object);*object=modme;}
+//	else		cJSON_Delete(modme);
+//	return error;
+//}
+// Code not added to library since this strategy is a LOT slower.
+*/
+
+/* Implement RFC7386 (https://tools.ietf.org/html/rfc7396) JSON Merge Patch spec. */
+cJSON* cJSONUtils_MergePatch(cJSON *target, cJSON *patch); /* target will be modified by patch. return value is new ptr for target. */
+cJSON *cJSONUtils_GenerateMergePatch(cJSON *from,cJSON *to); /* generates a patch to move from -> to */
+
+char *cJSONUtils_FindPointerFromObjectTo(cJSON *object,cJSON *target);	/* Given a root object and a target object, construct a pointer from one to the other.	*/
+
+void cJSONUtils_SortObject(cJSON *object);	/* Sorts the members of the object into alphabetical order.	*/
diff --git a/tools/sdk/include/log/esp_log.h b/tools/sdk/include/log/esp_log.h
new file mode 100644
index 00000000..8ca6e241
--- /dev/null
+++ b/tools/sdk/include/log/esp_log.h
@@ -0,0 +1,209 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef __ESP_LOG_H__
+#define __ESP_LOG_H__
+
+#include 
+#include 
+#include "sdkconfig.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Logging library
+ *
+ * Log library has two ways of managing log verbosity: compile time, set via
+ * menuconfig, and runtime, using esp_log_set_level function.
+ *
+ * At compile time, filtering is done using CONFIG_LOG_DEFAULT_LEVEL macro, set via
+ * menuconfig. All logging statments for levels higher than CONFIG_LOG_DEFAULT_LEVEL
+ * will be removed by the preprocessor.
+ *
+ * At run time, all logs below CONFIG_LOG_DEFAULT_LEVEL are enabled by default.
+ * esp_log_set_level function may be used to set logging level per module.
+ * Modules are identified by their tags, which are human-readable ASCII
+ * zero-terminated strings.
+ *
+ * How to use this library:
+ *
+ * In each C file which uses logging functionality, define TAG variable like this:
+ *
+ *      static const char* TAG = "MyModule";
+ *
+ * then use one of logging macros to produce output, e.g:
+ *
+ *      ESP_LOGW(TAG, "Baud rate error %.1f%%. Requested: %d baud, actual: %d baud", error * 100, baud_req, baud_real);
+ *
+ * Several macros are available for different verbosity levels:
+ *
+ *      ESP_LOGE — error
+ *      ESP_LOGW — warning
+ *      ESP_LOGI — info
+ *      ESP_LOGD - debug
+ *      ESP_LOGV - verbose
+ *
+ * Additionally there is an _EARLY_ variant for each of these macros (e.g. ESP_EARLY_LOGE).
+ * These variants can run in startup code, before heap allocator and syscalls
+ * have been initialized.
+ * When compiling bootloader, normal ESP_LOGx macros fall back to the same implementation
+ * as ESP_EARLY_LOGx macros. So the only place where ESP_EARLY_LOGx have to be used explicitly
+ * is the early startup code, such as heap allocator initialization code.
+ *
+ * (Note that such distinction would not have been necessary if we would have an
+ * ets_vprintf function in the ROM. Then it would be possible to switch implementation
+ * from _EARLY version to normal version on the fly. Unfortunately, ets_vprintf in ROM
+ * has been inlined by the compiler into ets_printf, so it is not accessible outside.)
+ *
+ * To override default verbosity level at file or component scope, define LOG_LOCAL_LEVEL macro.
+ * At file scope, define it before including esp_log.h, e.g.:
+ *
+ *      #define LOG_LOCAL_LEVEL ESP_LOG_VERBOSE
+ *      #include "esp_log.h"
+ *
+ * At component scope, define it in component makefile:
+ *
+ *      CFLAGS += -D LOG_LOCAL_LEVEL=ESP_LOG_DEBUG
+ *
+ * To configure logging output per module at runtime, add calls to esp_log_set_level function:
+ *
+ *      esp_log_set_level("*", ESP_LOG_ERROR);        // set all components to ERROR level
+ *      esp_log_set_level("wifi", ESP_LOG_WARN);      // enable WARN logs from WiFi stack
+ *      esp_log_set_level("dhcpc", ESP_LOG_INFO);     // enable INFO logs from DHCP client
+ *
+ */
+
+
+typedef enum {
+    ESP_LOG_NONE,       // No log output
+    ESP_LOG_ERROR,      // Critical errors, software module can not recover on its own
+    ESP_LOG_WARN,       // Error conditions from which recovery measures have been taken
+    ESP_LOG_INFO,       // Information messages which describe normal flow of events
+    ESP_LOG_DEBUG,      // Extra information which is not necessary for normal use (values, pointers, sizes, etc).
+    ESP_LOG_VERBOSE     // Bigger chunks of debugging information, or frequent messages which can potentially flood the output.
+} esp_log_level_t;
+
+typedef int (*vprintf_like_t)(const char *, va_list);
+
+/**
+ * @brief Set log level for given tag
+ *
+ * If logging for given component has already been enabled, changes previous setting.
+ *
+ * @param tag Tag of the log entries to enable. Must be a non-NULL zero terminated string.
+ *            Value "*" resets log level for all tags to the given value.
+ *
+ * @param level  Selects log level to enable. Only logs at this and lower levels will be shown.
+ */
+void esp_log_level_set(const char* tag, esp_log_level_t level);
+
+/**
+ * @brief Set function used to output log entries
+ *
+ * By default, log output goes to UART0. This function can be used to redirect log
+ * output to some other destination, such as file or network.
+ *
+ * @param func Function used for output. Must have same signature as vprintf.
+ */
+void esp_log_set_vprintf(vprintf_like_t func);
+
+/**
+ * @brief Write message into the log
+ *
+ * This function is not intended to be used directly. Instead, use one of
+ * ESP_LOGE, ESP_LOGW, ESP_LOGI, ESP_LOGD, ESP_LOGV macros.
+ *
+ * This function or these macros should not be used from an interrupt.
+ */
+void esp_log_write(esp_log_level_t level, const char* tag, const char* format, ...) __attribute__ ((format (printf, 3, 4)));
+
+
+/**
+ * @brief Function which returns timestamp to be used in log output
+ *
+ * This function is used in expansion of ESP_LOGx macros.
+ * In the 2nd stage bootloader, and at early application startup stage
+ * this function uses CPU cycle counter as time source. Later when
+ * FreeRTOS scheduler start running, it switches to FreeRTOS tick count.
+ *
+ * For now, we ignore millisecond counter overflow.
+ *
+ * @return timestamp, in milliseconds
+ */
+uint32_t esp_log_timestamp();
+
+
+#if CONFIG_LOG_COLORS
+#define LOG_COLOR_BLACK   "30"
+#define LOG_COLOR_RED     "31"
+#define LOG_COLOR_GREEN   "32"
+#define LOG_COLOR_BROWN   "33"
+#define LOG_COLOR_BLUE    "34"
+#define LOG_COLOR_PURPLE  "35"
+#define LOG_COLOR_CYAN    "36"
+#define LOG_COLOR(COLOR)  "\033[0;" COLOR "m"
+#define LOG_BOLD(COLOR)   "\033[1;" COLOR "m"
+#define LOG_RESET_COLOR   "\033[0m"
+#define LOG_COLOR_E       LOG_COLOR(LOG_COLOR_RED)
+#define LOG_COLOR_W       LOG_COLOR(LOG_COLOR_BROWN)
+#define LOG_COLOR_I       LOG_COLOR(LOG_COLOR_GREEN)
+#define LOG_COLOR_D
+#define LOG_COLOR_V
+#else //CONFIG_LOG_COLORS
+#define LOG_COLOR_E
+#define LOG_COLOR_W
+#define LOG_COLOR_I
+#define LOG_COLOR_D
+#define LOG_COLOR_V
+#define LOG_RESET_COLOR
+#endif //CONFIG_LOG_COLORS
+
+#define LOG_FORMAT(letter, format)  LOG_COLOR_ ## letter #letter " (%d) %s: " format LOG_RESET_COLOR "\n"
+
+#ifndef LOG_LOCAL_LEVEL
+#ifndef BOOTLOADER_BUILD
+#define LOG_LOCAL_LEVEL  ((esp_log_level_t) CONFIG_LOG_DEFAULT_LEVEL)
+#else
+#define LOG_LOCAL_LEVEL  ((esp_log_level_t) CONFIG_LOG_BOOTLOADER_LEVEL)
+#endif
+#endif
+
+#define ESP_EARLY_LOGE( tag, format, ... )  if (LOG_LOCAL_LEVEL >= ESP_LOG_ERROR)   { ets_printf(LOG_FORMAT(E, format), esp_log_timestamp(), tag, ##__VA_ARGS__); }
+#define ESP_EARLY_LOGW( tag, format, ... )  if (LOG_LOCAL_LEVEL >= ESP_LOG_WARN)    { ets_printf(LOG_FORMAT(W, format), esp_log_timestamp(), tag, ##__VA_ARGS__); }
+#define ESP_EARLY_LOGI( tag, format, ... )  if (LOG_LOCAL_LEVEL >= ESP_LOG_INFO)    { ets_printf(LOG_FORMAT(I, format), esp_log_timestamp(), tag, ##__VA_ARGS__); }
+#define ESP_EARLY_LOGD( tag, format, ... )  if (LOG_LOCAL_LEVEL >= ESP_LOG_DEBUG)   { ets_printf(LOG_FORMAT(D, format), esp_log_timestamp(), tag, ##__VA_ARGS__); }
+#define ESP_EARLY_LOGV( tag, format, ... )  if (LOG_LOCAL_LEVEL >= ESP_LOG_VERBOSE) { ets_printf(LOG_FORMAT(V, format), esp_log_timestamp(), tag, ##__VA_ARGS__); }
+
+#ifndef BOOTLOADER_BUILD
+#define ESP_LOGE( tag, format, ... )  if (LOG_LOCAL_LEVEL >= ESP_LOG_ERROR)   { esp_log_write(ESP_LOG_ERROR,   tag, LOG_FORMAT(E, format), esp_log_timestamp(), tag, ##__VA_ARGS__); }
+#define ESP_LOGW( tag, format, ... )  if (LOG_LOCAL_LEVEL >= ESP_LOG_WARN)    { esp_log_write(ESP_LOG_WARN,    tag, LOG_FORMAT(W, format), esp_log_timestamp(), tag, ##__VA_ARGS__); }
+#define ESP_LOGI( tag, format, ... )  if (LOG_LOCAL_LEVEL >= ESP_LOG_INFO)    { esp_log_write(ESP_LOG_INFO,    tag, LOG_FORMAT(I, format), esp_log_timestamp(), tag, ##__VA_ARGS__); }
+#define ESP_LOGD( tag, format, ... )  if (LOG_LOCAL_LEVEL >= ESP_LOG_DEBUG)   { esp_log_write(ESP_LOG_DEBUG,   tag, LOG_FORMAT(D, format), esp_log_timestamp(), tag, ##__VA_ARGS__); }
+#define ESP_LOGV( tag, format, ... )  if (LOG_LOCAL_LEVEL >= ESP_LOG_VERBOSE) { esp_log_write(ESP_LOG_VERBOSE, tag, LOG_FORMAT(V, format), esp_log_timestamp(), tag, ##__VA_ARGS__); }
+#else
+#define ESP_LOGE( tag, format, ... )  ESP_EARLY_LOGE(tag, format, ##__VA_ARGS__)
+#define ESP_LOGW( tag, format, ... )  ESP_EARLY_LOGW(tag, format, ##__VA_ARGS__)
+#define ESP_LOGI( tag, format, ... )  ESP_EARLY_LOGI(tag, format, ##__VA_ARGS__)
+#define ESP_LOGD( tag, format, ... )  ESP_EARLY_LOGD(tag, format, ##__VA_ARGS__)
+#define ESP_LOGV( tag, format, ... )  ESP_EARLY_LOGV(tag, format, ##__VA_ARGS__)
+#endif  // BOOTLOADER_BUILD
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __ESP_LOG_H__ */
diff --git a/tools/sdk/include/lwip/apps/dhcpserver.h b/tools/sdk/include/lwip/apps/dhcpserver.h
new file mode 100644
index 00000000..39781d96
--- /dev/null
+++ b/tools/sdk/include/lwip/apps/dhcpserver.h
@@ -0,0 +1,200 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef __DHCPS_H__
+#define __DHCPS_H__
+
+#include "lwip/ip_addr.h"
+//#include "esp_common.h"
+#define USE_DNS
+
+typedef struct dhcps_state{
+        s16_t state;
+} dhcps_state;
+
+typedef struct dhcps_msg {
+        u8_t op, htype, hlen, hops;
+        u8_t xid[4];
+        u16_t secs, flags;
+        u8_t ciaddr[4];
+        u8_t yiaddr[4];
+        u8_t siaddr[4];
+        u8_t giaddr[4];
+        u8_t chaddr[16];
+        u8_t sname[64];
+        u8_t file[128];
+        u8_t options[312];
+}dhcps_msg;
+
+/** DHCP OPTIONS CODE **/
+typedef enum
+{
+    /* RFC 1497 Vendor Extensions */
+
+    PAD = 0,
+    END = 255,
+
+    SUBNET_MASK = 1,
+    TIME_OFFSET = 2,
+    ROUTER = 3,
+    TIME_SERVER = 4,
+    NAME_SERVER = 5,
+    DOMAIN_NAME_SERVER = 6,
+    LOG_SERVER = 7,
+    COOKIE_SERVER = 8,
+    LPR_SERVER = 9,
+    IMPRESS_SERVER = 10,
+    RESOURCE_LOCATION_SERVER = 11,
+    HOST_NAME = 12,
+    BOOT_FILE_SIZE = 13,
+    MERIT_DUMP_FILE = 14,
+    DOMAIN_NAME = 15,
+    SWAP_SERVER = 16,
+    ROOT_PATH = 17,
+    EXTENSIONS_PATH = 18,
+
+    /* IP Layer Parameters per Host */
+
+    IP_FORWARDING = 19,
+    NON_LOCAL_SOURCE_ROUTING = 20,
+    POLICY_FILTER = 21,
+    MAXIMUM_DATAGRAM_REASSEMBLY_SIZE = 22,
+    DEFAULT_IP_TIME_TO_LIVE = 23,
+    PATH_MTU_AGING_TIMEOUT = 24,
+    PATH_MTU_PLATEAU_TABLE = 25,
+
+    /* IP Layer Parameters per Interface */
+
+    INTERFACE_MTU = 26,
+    ALL_SUBNETS_ARE_LOCAL = 27,
+    BROADCAST_ADDRESS = 28,
+    PERFORM_MASK_DISCOVERY = 29,
+    MASK_SUPPLIER = 30,
+    PERFORM_ROUTER_DISCOVERY = 31,
+    ROUTER_SOLICITATION_ADDRESS = 32,
+    STATIC_ROUTE = 33,
+
+    /* Link Layer Parameters per Interface */
+
+    TRAILER_ENCAPSULATION = 34,
+    ARP_CACHE_TIMEOUT = 35,
+    ETHERNET_ENCAPSULATION = 36,
+
+    /* TCP Parameters */
+
+    TCP_DEFAULT_TTL = 37,
+    TCP_KEEPALIVE_INTERVAL = 38,
+    TCP_KEEPALIVE_GARBAGE = 39,
+
+    /* Application and Service Parameters */
+
+    NETWORK_INFORMATION_SERVICE_DOMAIN = 40,
+    NETWORK_INFORMATION_SERVERS = 41,
+    NETWORK_TIME_PROTOCOL_SERVERS = 42,
+    VENDOR_SPECIFIC_INFORMATION = 43,
+    NETBIOS_OVER_TCP_IP_NAME_SERVER = 44,
+    NETBIOS_OVER_TCP_IP_DATAGRAM_DISTRIBUTION_SERVER = 45,
+    NETBIOS_OVER_TCP_IP_NODE_TYPE = 46,
+    NETBIOS_OVER_TCP_IP_SCOPE = 47,
+    X_WINDOW_SYSTEM_FONT_SERVER = 48,
+    X_WINDOW_SYSTEM_DISPLAY_MANAGER = 49,
+    NETWORK_INFORMATION_SERVICE_PLUS_DOMAIN = 64,
+    NETWORK_INFORMATION_SERVICE_PLUS_SERVERS = 65,
+    MOBILE_IP_HOME_AGENT = 68,
+    SMTP_SERVER = 69,
+    POP3_SERVER = 70,
+    NNTP_SERVER = 71,
+    DEFAULT_WWW_SERVER = 72,
+    DEFAULT_FINGER_SERVER = 73,
+    DEFAULT_IRC_SERVER = 74,
+    STREETTALK_SERVER = 75,
+    STREETTALK_DIRECTORY_ASSISTANCE_SERVER = 76,
+
+    /* DHCP Extensions */
+
+    REQUESTED_IP_ADDRESS = 50,
+    IP_ADDRESS_LEASE_TIME = 51,
+    OPTION_OVERLOAD = 52,
+    TFTP_SERVER_NAME = 66,
+    BOOTFILE_NAME = 67,
+    DHCP_MESSAGE_TYPE = 53,
+    SERVER_IDENTIFIER = 54,
+    PARAMETER_REQUEST_LIST = 55,
+    MESSAGE = 56,
+    MAXIMUM_DHCP_MESSAGE_SIZE = 57,
+    RENEWAL_T1_TIME_VALUE = 58,
+    REBINDING_T2_TIME_VALUE = 59,
+    VENDOR_CLASS_IDENTIFIER = 60,
+    CLIENT_IDENTIFIER = 61,
+
+    USER_CLASS = 77,
+    FQDN = 81,
+    DHCP_AGENT_OPTIONS = 82,
+    NDS_SERVERS = 85,
+    NDS_TREE_NAME = 86,
+    NDS_CONTEXT = 87,
+    CLIENT_LAST_TRANSACTION_TIME = 91,
+    ASSOCIATED_IP = 92,
+    USER_AUTHENTICATION_PROTOCOL = 98,
+    AUTO_CONFIGURE = 116,
+    NAME_SERVICE_SEARCH = 117,
+    SUBNET_SELECTION = 118,
+    DOMAIN_SEARCH = 119,
+    CLASSLESS_ROUTE = 121,
+} dhcp_msg_option;
+
+/*   Defined in esp_misc.h */
+typedef struct {
+	bool enable;
+	ip4_addr_t start_ip;
+	ip4_addr_t end_ip;
+} dhcps_lease_t;
+
+enum dhcps_offer_option{
+	OFFER_START = 0x00,
+	OFFER_ROUTER = 0x01,
+	OFFER_END
+};
+
+#define DHCPS_MAX_LEASE 0x64
+#define DHCPS_LEASE_TIME_DEF	(120)
+
+struct dhcps_pool{
+	ip4_addr_t ip;
+	u8_t mac[6];
+	u32_t lease_timer;
+};
+
+typedef struct _list_node{
+	void *pnode;
+	struct _list_node *pnext;
+}list_node;
+
+typedef u32_t dhcps_time_t;
+typedef u8_t dhcps_offer_t;
+
+typedef struct {
+	dhcps_offer_t dhcps_offer;
+	dhcps_time_t  dhcps_time;
+	dhcps_lease_t dhcps_poll;
+} dhcps_options_t;
+
+#define dhcps_router_enabled(offer) ((offer & OFFER_ROUTER) != 0)
+
+void dhcps_start(struct netif *netif, ip4_addr_t ip);
+void dhcps_stop(struct netif *netif);
+void *dhcps_option_info(u8_t op_id, u32_t opt_len);
+bool dhcp_search_ip_on_mac(u8_t *mac, ip4_addr_t *ip);
+
+#endif
+
diff --git a/tools/sdk/include/lwip/apps/sntp/sntp.h b/tools/sdk/include/lwip/apps/sntp/sntp.h
new file mode 100644
index 00000000..b0086936
--- /dev/null
+++ b/tools/sdk/include/lwip/apps/sntp/sntp.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2007-2009 Frédéric Bernon, Simon Goldschmidt
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Frédéric Bernon, Simon Goldschmidt
+ *
+ */
+#ifndef LWIP_HDR_APPS_SNTP_H
+#define LWIP_HDR_APPS_SNTP_H
+
+#include "apps/sntp/sntp_opts.h"
+#include "lwip/ip_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* SNTP operating modes: default is to poll using unicast.
+   The mode has to be set before calling sntp_init(). */
+#define SNTP_OPMODE_POLL            0
+#define SNTP_OPMODE_LISTENONLY      1
+void sntp_setoperatingmode(u8_t operating_mode);
+u8_t sntp_getoperatingmode(void);
+
+void sntp_init(void);
+void sntp_stop(void);
+u8_t sntp_enabled(void);
+
+void sntp_setserver(u8_t idx, const ip_addr_t *addr);
+ip_addr_t sntp_getserver(u8_t idx);
+
+#if SNTP_SERVER_DNS
+void sntp_setservername(u8_t idx, char *server);
+char *sntp_getservername(u8_t idx);
+#endif /* SNTP_SERVER_DNS */
+
+#if SNTP_GET_SERVERS_FROM_DHCP
+void sntp_servermode_dhcp(int set_servers_from_dhcp);
+#else /* SNTP_GET_SERVERS_FROM_DHCP */
+#define sntp_servermode_dhcp(x)
+#endif /* SNTP_GET_SERVERS_FROM_DHCP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_APPS_SNTP_H */
diff --git a/tools/sdk/include/lwip/apps/sntp/sntp_opts.h b/tools/sdk/include/lwip/apps/sntp/sntp_opts.h
new file mode 100644
index 00000000..c8a39649
--- /dev/null
+++ b/tools/sdk/include/lwip/apps/sntp/sntp_opts.h
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2007-2009 Frédéric Bernon, Simon Goldschmidt
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Frédéric Bernon, Simon Goldschmidt
+ *
+ */
+#ifndef LWIP_HDR_APPS_SNTP_OPTS_H
+#define LWIP_HDR_APPS_SNTP_OPTS_H
+
+#include "lwip/opt.h"
+
+/** SNTP macro to change system time in seconds
+ * Define SNTP_SET_SYSTEM_TIME_US(sec, us) to set the time in microseconds instead of this one
+ * if you need the additional precision.
+ */
+#ifndef SNTP_SET_SYSTEM_TIME
+#define SNTP_SET_SYSTEM_TIME(sec)   LWIP_UNUSED_ARG(sec)
+#endif
+
+/** The maximum number of SNTP servers that can be set */
+#ifndef SNTP_MAX_SERVERS
+#define SNTP_MAX_SERVERS           LWIP_DHCP_MAX_NTP_SERVERS
+#endif
+
+/** Set this to 1 to implement the callback function called by dhcp when
+ * NTP servers are received. */
+#ifndef SNTP_GET_SERVERS_FROM_DHCP
+#define SNTP_GET_SERVERS_FROM_DHCP LWIP_DHCP_GET_NTP_SRV
+#endif
+
+/* Set this to 1 to support DNS names (or IP address strings) to set sntp servers */
+#ifndef SNTP_SERVER_DNS
+#define SNTP_SERVER_DNS            1
+#endif
+
+/** One server address/name can be defined as default if SNTP_SERVER_DNS == 1:
+ * #define SNTP_SERVER_ADDRESS "pool.ntp.org"
+ */
+
+/**
+ * SNTP_DEBUG: Enable debugging for SNTP.
+ */
+#ifndef SNTP_DEBUG
+#define SNTP_DEBUG                  LWIP_DBG_OFF
+#endif
+
+/** SNTP server port */
+#ifndef SNTP_PORT
+#define SNTP_PORT                   123
+#endif
+
+/** Set this to 1 to allow config of SNTP server(s) by DNS name */
+#ifndef SNTP_SERVER_DNS
+#define SNTP_SERVER_DNS             0
+#endif
+
+/** Sanity check:
+ * Define this to
+ * - 0 to turn off sanity checks (default; smaller code)
+ * - >= 1 to check address and port of the response packet to ensure the
+ *        response comes from the server we sent the request to.
+ * - >= 2 to check returned Originate Timestamp against Transmit Timestamp
+ *        sent to the server (to ensure response to older request).
+ * - >= 3 @todo: discard reply if any of the LI, Stratum, or Transmit Timestamp
+ *        fields is 0 or the Mode field is not 4 (unicast) or 5 (broadcast).
+ * - >= 4 @todo: to check that the Root Delay and Root Dispersion fields are each
+ *        greater than or equal to 0 and less than infinity, where infinity is
+ *        currently a cozy number like one second. This check avoids using a
+ *        server whose synchronization source has expired for a very long time.
+ */
+#ifndef SNTP_CHECK_RESPONSE
+#define SNTP_CHECK_RESPONSE         0
+#endif
+
+/** According to the RFC, this shall be a random delay
+ * between 1 and 5 minutes (in milliseconds) to prevent load peaks.
+ * This can be defined to a random generation function,
+ * which must return the delay in milliseconds as u32_t.
+ * Turned off by default.
+ */
+#ifndef SNTP_STARTUP_DELAY
+#define SNTP_STARTUP_DELAY          0
+#endif
+
+/** If you want the startup delay to be a function, define this
+ * to a function (including the brackets) and define SNTP_STARTUP_DELAY to 1.
+ */
+#ifndef SNTP_STARTUP_DELAY_FUNC
+#define SNTP_STARTUP_DELAY_FUNC     SNTP_STARTUP_DELAY
+#endif
+
+/** SNTP receive timeout - in milliseconds
+ * Also used as retry timeout - this shouldn't be too low.
+ * Default is 3 seconds.
+ */
+#ifndef SNTP_RECV_TIMEOUT
+#define SNTP_RECV_TIMEOUT           3000
+#endif
+
+/** SNTP update delay - in milliseconds
+ * Default is 1 hour. Must not be beolw 15 seconds by specification (i.e. 15000)
+ */
+#ifndef SNTP_UPDATE_DELAY
+#define SNTP_UPDATE_DELAY           3600000
+#endif
+
+/** SNTP macro to get system time, used with SNTP_CHECK_RESPONSE >= 2
+ * to send in request and compare in response.
+ */
+#ifndef SNTP_GET_SYSTEM_TIME
+#define SNTP_GET_SYSTEM_TIME(sec, us)     do { (sec) = 0; (us) = 0; } while(0)
+#endif
+
+/** Default retry timeout (in milliseconds) if the response
+ * received is invalid.
+ * This is doubled with each retry until SNTP_RETRY_TIMEOUT_MAX is reached.
+ */
+#ifndef SNTP_RETRY_TIMEOUT
+#define SNTP_RETRY_TIMEOUT          SNTP_RECV_TIMEOUT
+#endif
+
+/** Maximum retry timeout (in milliseconds). */
+#ifndef SNTP_RETRY_TIMEOUT_MAX
+#define SNTP_RETRY_TIMEOUT_MAX      (SNTP_RETRY_TIMEOUT * 10)
+#endif
+
+/** Increase retry timeout with every retry sent
+ * Default is on to conform to RFC.
+ */
+#ifndef SNTP_RETRY_TIMEOUT_EXP
+#define SNTP_RETRY_TIMEOUT_EXP      1
+#endif
+
+#endif /* LWIP_HDR_APPS_SNTP_OPTS_H */
diff --git a/tools/sdk/include/lwip/arch/cc.h b/tools/sdk/include/lwip/arch/cc.h
new file mode 100644
index 00000000..6fc1da18
--- /dev/null
+++ b/tools/sdk/include/lwip/arch/cc.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2001, Swedish Institute of Computer Science.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. Neither the name of the Institute nor the names of its contributors 
+ *    may be used to endorse or promote products derived from this software 
+ *    without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+ * SUCH DAMAGE. 
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __ARCH_CC_H__
+#define __ARCH_CC_H__
+
+#include 
+#include 
+
+#include "arch/sys_arch.h"
+
+#define BYTE_ORDER LITTLE_ENDIAN
+
+typedef uint8_t  u8_t;
+typedef int8_t   s8_t;
+typedef uint16_t u16_t;
+typedef int16_t  s16_t;
+typedef uint32_t u32_t;
+typedef int32_t  s32_t;
+
+typedef unsigned long   mem_ptr_t;
+typedef int sys_prot_t;
+
+#define S16_F "d"
+#define U16_F "d"
+#define X16_F "x"
+
+#define S32_F "d"
+#define U32_F "d"
+#define X32_F "x"
+
+#define PACK_STRUCT_FIELD(x) x
+#define PACK_STRUCT_STRUCT __attribute__((packed))
+#define PACK_STRUCT_BEGIN
+#define PACK_STRUCT_END
+
+#include 
+
+#define LWIP_PLATFORM_DIAG(x)   do {printf x;} while(0)
+#define LWIP_PLATFORM_ASSERT(x) do {printf(x); sys_arch_assert(__FILE__, __LINE__);} while(0)
+
+//#define LWIP_DEBUG
+#define LWIP_NOASSERT
+//#define LWIP_ERROR
+
+#endif /* __ARCH_CC_H__ */
diff --git a/tools/sdk/include/lwip/arch/perf.h b/tools/sdk/include/lwip/arch/perf.h
new file mode 100644
index 00000000..089facac
--- /dev/null
+++ b/tools/sdk/include/lwip/arch/perf.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2001, Swedish Institute of Computer Science.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. Neither the name of the Institute nor the names of its contributors 
+ *    may be used to endorse or promote products derived from this software 
+ *    without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+ * SUCH DAMAGE. 
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __PERF_H__
+#define __PERF_H__
+
+#define PERF_START    /* null definition */
+#define PERF_STOP(x)  /* null definition */
+
+#endif /* __PERF_H__ */
diff --git a/tools/sdk/include/lwip/arch/sys_arch.h b/tools/sdk/include/lwip/arch/sys_arch.h
new file mode 100644
index 00000000..a8633482
--- /dev/null
+++ b/tools/sdk/include/lwip/arch/sys_arch.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+ 
+#ifndef __SYS_ARCH_H__
+#define __SYS_ARCH_H__
+
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "freertos/queue.h"
+#include "freertos/semphr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+typedef xSemaphoreHandle sys_sem_t;
+typedef xSemaphoreHandle sys_mutex_t;
+typedef xTaskHandle sys_thread_t;
+
+typedef struct sys_mbox_s {
+  xQueueHandle os_mbox;
+  sys_mutex_t  lock;
+  uint8_t      alive;
+}* sys_mbox_t;
+
+
+#define LWIP_COMPAT_MUTEX 0
+
+#if !LWIP_COMPAT_MUTEX
+#define sys_mutex_valid( x ) ( ( ( *x ) == NULL) ? pdFALSE : pdTRUE )
+#define sys_mutex_set_invalid( x ) ( ( *x ) = NULL )
+#endif
+
+#define sys_mbox_valid( x ) ( ( ( *x ) == NULL) ? pdFALSE : pdTRUE )
+#define sys_mbox_set_invalid( x ) ( ( *x ) = NULL )
+
+#define sys_sem_valid( x ) ( ( ( *x ) == NULL) ? pdFALSE : pdTRUE )
+#define sys_sem_set_invalid( x ) ( ( *x ) = NULL )
+
+void sys_arch_assert(const char *file, int line);
+uint32_t system_get_time(void);
+void sys_delay_ms(uint32_t ms);
+sys_sem_t* sys_thread_sem_init(void);
+void sys_thread_sem_deinit(void);
+sys_sem_t* sys_thread_sem_get(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYS_ARCH_H__ */
+
diff --git a/tools/sdk/include/lwip/lwip/api.h b/tools/sdk/include/lwip/lwip/api.h
new file mode 100755
index 00000000..985eb76d
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/api.h
@@ -0,0 +1,368 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef LWIP_HDR_API_H
+#define LWIP_HDR_API_H
+
+#include "lwip/opt.h"
+
+#if LWIP_NETCONN || LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */
+/* Note: Netconn API is always available when sockets are enabled -
+ * sockets are implemented on top of them */
+
+#include  /* for size_t */
+
+#include "lwip/netbuf.h"
+#include "lwip/sys.h"
+#include "lwip/ip_addr.h"
+#include "lwip/err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Throughout this file, IP addresses and port numbers are expected to be in
+ * the same byte order as in the corresponding pcb.
+ */
+
+/* Flags for netconn_write (u8_t) */
+#define NETCONN_NOFLAG    0x00
+#define NETCONN_NOCOPY    0x00 /* Only for source code compatibility */
+#define NETCONN_COPY      0x01
+#define NETCONN_MORE      0x02
+#define NETCONN_DONTBLOCK 0x04
+
+/* Flags for struct netconn.flags (u8_t) */
+/** Should this netconn avoid blocking? */
+#define NETCONN_FLAG_NON_BLOCKING             0x02
+/** Was the last connect action a non-blocking one? */
+#define NETCONN_FLAG_IN_NONBLOCKING_CONNECT   0x04
+/** If this is set, a TCP netconn must call netconn_recved() to update
+    the TCP receive window (done automatically if not set). */
+#define NETCONN_FLAG_NO_AUTO_RECVED           0x08
+/** If a nonblocking write has been rejected before, poll_tcp needs to
+    check if the netconn is writable again */
+#define NETCONN_FLAG_CHECK_WRITESPACE         0x10
+#if LWIP_IPV6
+/** If this flag is set then only IPv6 communication is allowed on the
+    netconn. As per RFC#3493 this features defaults to OFF allowing
+    dual-stack usage by default. */
+#define NETCONN_FLAG_IPV6_V6ONLY              0x20
+#endif /* LWIP_IPV6 */
+
+
+    /* Helpers to process several netconn_types by the same code */
+#define NETCONNTYPE_GROUP(t)         ((t)&0xF0)
+#define NETCONNTYPE_DATAGRAM(t)      ((t)&0xE0)
+#if LWIP_IPV6
+#define NETCONN_TYPE_IPV6            0x08
+#define NETCONNTYPE_ISIPV6(t)        (((t)&NETCONN_TYPE_IPV6) != 0)
+#define NETCONNTYPE_ISUDPLITE(t)     (((t)&0xF3) == NETCONN_UDPLITE)
+#define NETCONNTYPE_ISUDPNOCHKSUM(t) (((t)&0xF3) == NETCONN_UDPNOCHKSUM)
+#else /* LWIP_IPV6 */
+#define NETCONNTYPE_ISUDPLITE(t)     ((t) == NETCONN_UDPLITE)
+#define NETCONNTYPE_ISUDPNOCHKSUM(t) ((t) == NETCONN_UDPNOCHKSUM)
+#endif /* LWIP_IPV6 */
+
+/** Protocol family and type of the netconn */
+enum netconn_type {
+  NETCONN_INVALID     = 0,
+  /* NETCONN_TCP Group */
+  NETCONN_TCP         = 0x10,
+#if LWIP_IPV6
+  NETCONN_TCP_IPV6    = NETCONN_TCP | NETCONN_TYPE_IPV6 /* 0x18 */,
+#endif /* LWIP_IPV6 */
+  /* NETCONN_UDP Group */
+  NETCONN_UDP         = 0x20,
+  NETCONN_UDPLITE     = 0x21,
+  NETCONN_UDPNOCHKSUM = 0x22,
+
+#if LWIP_IPV6
+  NETCONN_UDP_IPV6         = NETCONN_UDP | NETCONN_TYPE_IPV6 /* 0x28 */,
+  NETCONN_UDPLITE_IPV6     = NETCONN_UDPLITE | NETCONN_TYPE_IPV6 /* 0x29 */,
+  NETCONN_UDPNOCHKSUM_IPV6 = NETCONN_UDPNOCHKSUM | NETCONN_TYPE_IPV6 /* 0x2a */,
+#endif /* LWIP_IPV6 */
+
+  /* NETCONN_RAW Group */
+  NETCONN_RAW         = 0x40
+#if LWIP_IPV6
+  , NETCONN_RAW_IPV6    = NETCONN_RAW | NETCONN_TYPE_IPV6 /* 0x48 */
+#endif /* LWIP_IPV6 */
+};
+
+/** Current state of the netconn. Non-TCP netconns are always
+ * in state NETCONN_NONE! */
+enum netconn_state {
+  NETCONN_NONE,
+  NETCONN_WRITE,
+  NETCONN_LISTEN,
+  NETCONN_CONNECT,
+  NETCONN_CLOSE
+};
+
+/** Use to inform the callback function about changes */
+enum netconn_evt {
+  NETCONN_EVT_RCVPLUS,
+  NETCONN_EVT_RCVMINUS,
+  NETCONN_EVT_SENDPLUS,
+  NETCONN_EVT_SENDMINUS,
+  NETCONN_EVT_ERROR
+};
+
+#if LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD)
+/** Used for netconn_join_leave_group() */
+enum netconn_igmp {
+  NETCONN_JOIN,
+  NETCONN_LEAVE
+};
+#endif /* LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) */
+
+#if LWIP_DNS
+/* Used for netconn_gethostbyname_addrtype(), these should match the DNS_ADDRTYPE defines in dns.h */
+#define NETCONN_DNS_DEFAULT   NETCONN_DNS_IPV4_IPV6
+#define NETCONN_DNS_IPV4      0
+#define NETCONN_DNS_IPV6      1
+#define NETCONN_DNS_IPV4_IPV6 2 /* try to resolve IPv4 first, try IPv6 if IPv4 fails only */
+#define NETCONN_DNS_IPV6_IPV4 3 /* try to resolve IPv6 first, try IPv4 if IPv6 fails only */
+#endif /* LWIP_DNS */
+
+/* forward-declare some structs to avoid to include their headers */
+struct ip_pcb;
+struct tcp_pcb;
+struct udp_pcb;
+struct raw_pcb;
+struct netconn;
+struct api_msg_msg;
+
+/** A callback prototype to inform about events for a netconn */
+typedef void (* netconn_callback)(struct netconn *, enum netconn_evt, u16_t len);
+
+/** A netconn descriptor */
+struct netconn {
+  /** type of the netconn (TCP, UDP or RAW) */
+  enum netconn_type type;
+  /** current state of the netconn */
+  enum netconn_state state;
+  /** the lwIP internal protocol control block */
+  union {
+    struct ip_pcb  *ip;
+    struct tcp_pcb *tcp;
+    struct udp_pcb *udp;
+    struct raw_pcb *raw;
+  } pcb;
+  /** the last error this netconn had */
+  err_t last_err;
+  
+#if !LWIP_NETCONN_SEM_PER_THREAD
+  /** sem that is used to synchronously execute functions in the core context */
+  sys_sem_t op_completed;
+
+#ifdef LWIP_ESP8266
+  sys_sem_t snd_op_completed;	//only for snd semphore
+#endif
+  
+#endif
+
+  /** mbox where received packets are stored until they are fetched
+      by the netconn application thread (can grow quite big) */
+  sys_mbox_t recvmbox;
+#if LWIP_TCP
+  /** mbox where new connections are stored until processed
+      by the application thread */
+  sys_mbox_t acceptmbox;
+#endif /* LWIP_TCP */
+  /** only used for socket layer */
+#if LWIP_SOCKET
+  int socket;
+#endif /* LWIP_SOCKET */
+#if LWIP_SO_SNDTIMEO
+  /** timeout to wait for sending data (which means enqueueing data for sending
+      in internal buffers) in milliseconds */
+  s32_t send_timeout;
+#endif /* LWIP_SO_RCVTIMEO */
+#if LWIP_SO_RCVTIMEO
+  /** timeout in milliseconds to wait for new data to be received
+      (or connections to arrive for listening netconns) */
+  int recv_timeout;
+#endif /* LWIP_SO_RCVTIMEO */
+#if LWIP_SO_RCVBUF
+  /** maximum amount of bytes queued in recvmbox
+      not used for TCP: adjust TCP_WND instead! */
+  int recv_bufsize;
+  /** number of bytes currently in recvmbox to be received,
+      tested against recv_bufsize to limit bytes on recvmbox
+      for UDP and RAW, used for FIONREAD */
+  int recv_avail;
+#endif /* LWIP_SO_RCVBUF */
+#if LWIP_SO_LINGER
+   /** values <0 mean linger is disabled, values > 0 are seconds to linger */
+  s16_t linger;
+#endif /* LWIP_SO_LINGER */
+  /** flags holding more netconn-internal state, see NETCONN_FLAG_* defines */
+  u8_t flags;
+#if LWIP_TCP
+  /** TCP: when data passed to netconn_write doesn't fit into the send buffer,
+      this temporarily stores how much is already sent. */
+  size_t write_offset;
+  /** TCP: when data passed to netconn_write doesn't fit into the send buffer,
+      this temporarily stores the message.
+      Also used during connect and close. */
+  struct api_msg_msg *current_msg;
+#endif /* LWIP_TCP */
+  /** A callback function that is informed about events for this netconn */
+  netconn_callback callback;
+};
+
+/** Register an Network connection event */
+#define API_EVENT(c,e,l) if (c->callback) {         \
+                           (*c->callback)(c, e, l); \
+                         }
+
+/** Set conn->last_err to err but don't overwrite fatal errors */
+#define NETCONN_SET_SAFE_ERR(conn, err) do { if ((conn) != NULL) { \
+  SYS_ARCH_DECL_PROTECT(netconn_set_safe_err_lev); \
+  SYS_ARCH_PROTECT(netconn_set_safe_err_lev); \
+  if (!ERR_IS_FATAL((conn)->last_err)) { \
+    (conn)->last_err = err; \
+  } \
+  SYS_ARCH_UNPROTECT(netconn_set_safe_err_lev); \
+}} while(0);
+
+/* Network connection functions: */
+#define netconn_new(t)                  netconn_new_with_proto_and_callback(t, 0, NULL)
+#define netconn_new_with_callback(t, c) netconn_new_with_proto_and_callback(t, 0, c)
+struct netconn *netconn_new_with_proto_and_callback(enum netconn_type t, u8_t proto,
+                                             netconn_callback callback);
+err_t   netconn_delete(struct netconn *conn);
+/** Get the type of a netconn (as enum netconn_type). */
+#define netconn_type(conn) (conn->type)
+
+err_t   netconn_getaddr(struct netconn *conn, ip_addr_t *addr,
+                        u16_t *port, u8_t local);
+#define netconn_peer(c,i,p) netconn_getaddr(c,i,p,0)
+#define netconn_addr(c,i,p) netconn_getaddr(c,i,p,1)
+
+err_t   netconn_bind(struct netconn *conn, const ip_addr_t *addr, u16_t port);
+err_t   netconn_connect(struct netconn *conn, const ip_addr_t *addr, u16_t port);
+err_t   netconn_disconnect (struct netconn *conn);
+err_t   netconn_listen_with_backlog(struct netconn *conn, u8_t backlog);
+#define netconn_listen(conn) netconn_listen_with_backlog(conn, TCP_DEFAULT_LISTEN_BACKLOG)
+err_t   netconn_accept(struct netconn *conn, struct netconn **new_conn);
+err_t   netconn_recv(struct netconn *conn, struct netbuf **new_buf);
+err_t   netconn_recv_tcp_pbuf(struct netconn *conn, struct pbuf **new_buf);
+void    netconn_recved(struct netconn *conn, u32_t length);
+err_t   netconn_sendto(struct netconn *conn, struct netbuf *buf,
+                             const ip_addr_t *addr, u16_t port);
+err_t   netconn_send(struct netconn *conn, struct netbuf *buf);
+err_t   netconn_write_partly(struct netconn *conn, const void *dataptr, size_t size,
+                             u8_t apiflags, size_t *bytes_written);
+#define netconn_write(conn, dataptr, size, apiflags) \
+          netconn_write_partly(conn, dataptr, size, apiflags, NULL)
+err_t   netconn_close(struct netconn *conn);
+err_t   netconn_shutdown(struct netconn *conn, u8_t shut_rx, u8_t shut_tx);
+
+#if LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD)
+err_t   netconn_join_leave_group(struct netconn *conn, const ip_addr_t *multiaddr,
+                             const ip_addr_t *netif_addr, enum netconn_igmp join_or_leave);
+#endif /* LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) */
+#if LWIP_DNS
+#if LWIP_IPV4 && LWIP_IPV6
+err_t   netconn_gethostbyname_addrtype(const char *name, ip_addr_t *addr, u8_t dns_addrtype);
+#define netconn_gethostbyname(name, addr) netconn_gethostbyname_addrtype(name, addr, NETCONN_DNS_DEFAULT)
+#else /* LWIP_IPV4 && LWIP_IPV6 */
+err_t   netconn_gethostbyname(const char *name, ip_addr_t *addr);
+#define netconn_gethostbyname_addrtype(name, addr, dns_addrtype) netconn_gethostbyname(name, addr)
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+#endif /* LWIP_DNS */
+
+#define netconn_err(conn)               ((conn)->last_err)
+#define netconn_recv_bufsize(conn)      ((conn)->recv_bufsize)
+
+/** Set the blocking status of netconn calls (@todo: write/send is missing) */
+#define netconn_set_nonblocking(conn, val)  do { if(val) { \
+  (conn)->flags |= NETCONN_FLAG_NON_BLOCKING; \
+} else { \
+  (conn)->flags &= ~ NETCONN_FLAG_NON_BLOCKING; }} while(0)
+/** Get the blocking status of netconn calls (@todo: write/send is missing) */
+#define netconn_is_nonblocking(conn)        (((conn)->flags & NETCONN_FLAG_NON_BLOCKING) != 0)
+
+/** TCP: Set the no-auto-recved status of netconn calls (see NETCONN_FLAG_NO_AUTO_RECVED) */
+#define netconn_set_noautorecved(conn, val)  do { if(val) { \
+  (conn)->flags |= NETCONN_FLAG_NO_AUTO_RECVED; \
+} else { \
+  (conn)->flags &= ~ NETCONN_FLAG_NO_AUTO_RECVED; }} while(0)
+/** TCP: Get the no-auto-recved status of netconn calls (see NETCONN_FLAG_NO_AUTO_RECVED) */
+#define netconn_get_noautorecved(conn)        (((conn)->flags & NETCONN_FLAG_NO_AUTO_RECVED) != 0)
+
+#if LWIP_IPV6
+/** TCP: Set the IPv6 ONLY status of netconn calls (see NETCONN_FLAG_IPV6_V6ONLY) */
+#define netconn_set_ipv6only(conn, val)  do { if(val) { \
+  (conn)->flags |= NETCONN_FLAG_IPV6_V6ONLY; \
+} else { \
+  (conn)->flags &= ~ NETCONN_FLAG_IPV6_V6ONLY; }} while(0)
+/** TCP: Get the IPv6 ONLY status of netconn calls (see NETCONN_FLAG_IPV6_V6ONLY) */
+#define netconn_get_ipv6only(conn)        (((conn)->flags & NETCONN_FLAG_IPV6_V6ONLY) != 0)
+#endif /* LWIP_IPV6 */
+
+#if LWIP_SO_SNDTIMEO
+/** Set the send timeout in milliseconds */
+#define netconn_set_sendtimeout(conn, timeout)      ((conn)->send_timeout = (timeout))
+/** Get the send timeout in milliseconds */
+#define netconn_get_sendtimeout(conn)               ((conn)->send_timeout)
+#endif /* LWIP_SO_SNDTIMEO */
+#if LWIP_SO_RCVTIMEO
+/** Set the receive timeout in milliseconds */
+#define netconn_set_recvtimeout(conn, timeout)      ((conn)->recv_timeout = (timeout))
+/** Get the receive timeout in milliseconds */
+#define netconn_get_recvtimeout(conn)               ((conn)->recv_timeout)
+#endif /* LWIP_SO_RCVTIMEO */
+#if LWIP_SO_RCVBUF
+/** Set the receive buffer in bytes */
+#define netconn_set_recvbufsize(conn, recvbufsize)  ((conn)->recv_bufsize = (recvbufsize))
+/** Get the receive buffer in bytes */
+#define netconn_get_recvbufsize(conn)               ((conn)->recv_bufsize)
+#endif /* LWIP_SO_RCVBUF*/
+
+#if LWIP_NETCONN_SEM_PER_THREAD
+void netconn_thread_init(void);
+void netconn_thread_cleanup(void);
+#else /* LWIP_NETCONN_SEM_PER_THREAD */
+#define netconn_thread_init()
+#define netconn_thread_cleanup()
+#endif /* LWIP_NETCONN_SEM_PER_THREAD */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_NETCONN || LWIP_SOCKET */
+
+#endif /* LWIP_HDR_API_H */
diff --git a/tools/sdk/include/lwip/lwip/arch.h b/tools/sdk/include/lwip/lwip/arch.h
new file mode 100755
index 00000000..7b99c260
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/arch.h
@@ -0,0 +1,233 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef LWIP_HDR_ARCH_H
+#define LWIP_HDR_ARCH_H
+
+#ifndef LITTLE_ENDIAN
+#define LITTLE_ENDIAN 1234
+#endif
+
+#ifndef BIG_ENDIAN
+#define BIG_ENDIAN 4321
+#endif
+
+#include "arch/cc.h"
+
+/** Temporary: define format string for size_t if not defined in cc.h */
+#ifndef SZT_F
+#define SZT_F U32_F
+#endif /* SZT_F */
+/** Temporary upgrade helper: define format string for u8_t as hex if not
+    defined in cc.h */
+#ifndef X8_F
+#define X8_F  "02x"
+#endif /* X8_F */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef PACK_STRUCT_BEGIN
+#define PACK_STRUCT_BEGIN
+#endif /* PACK_STRUCT_BEGIN */
+
+#ifndef PACK_STRUCT_END
+#define PACK_STRUCT_END
+#endif /* PACK_STRUCT_END */
+
+#ifndef PACK_STRUCT_STRUCT
+#define PACK_STRUCT_STRUCT
+#endif /* PACK_STRUCT_STRUCT */
+
+#ifndef PACK_STRUCT_FIELD
+#define PACK_STRUCT_FIELD(x) x
+#endif /* PACK_STRUCT_FIELD */
+
+/* Used for struct fields of u8_t,
+ * where some compilers warn that packing is not necessary */
+#ifndef PACK_STRUCT_FLD_8
+#define PACK_STRUCT_FLD_8(x) PACK_STRUCT_FIELD(x)
+#endif /* PACK_STRUCT_FLD_8 */
+
+/* Used for struct fields of that are packed structs themself,
+ * where some compilers warn that packing is not necessary */
+#ifndef PACK_STRUCT_FLD_S
+#define PACK_STRUCT_FLD_S(x) PACK_STRUCT_FIELD(x)
+#endif /* PACK_STRUCT_FLD_S */
+
+
+#ifndef LWIP_UNUSED_ARG
+#define LWIP_UNUSED_ARG(x) (void)x
+#endif /* LWIP_UNUSED_ARG */
+
+
+#ifdef LWIP_PROVIDE_ERRNO
+
+#define  EPERM         1  /* Operation not permitted */
+#define  ENOENT        2  /* No such file or directory */
+#define  ESRCH         3  /* No such process */
+#define  EINTR         4  /* Interrupted system call */
+#define  EIO           5  /* I/O error */
+#define  ENXIO         6  /* No such device or address */
+#define  E2BIG         7  /* Arg list too long */
+#define  ENOEXEC       8  /* Exec format error */
+#define  EBADF         9  /* Bad file number */
+#define  ECHILD       10  /* No child processes */
+#define  EAGAIN       11  /* Try again */
+#define  ENOMEM       12  /* Out of memory */
+#define  EACCES       13  /* Permission denied */
+#define  EFAULT       14  /* Bad address */
+#define  ENOTBLK      15  /* Block device required */
+#define  EBUSY        16  /* Device or resource busy */
+#define  EEXIST       17  /* File exists */
+#define  EXDEV        18  /* Cross-device link */
+#define  ENODEV       19  /* No such device */
+#define  ENOTDIR      20  /* Not a directory */
+#define  EISDIR       21  /* Is a directory */
+#define  EINVAL       22  /* Invalid argument */
+#define  ENFILE       23  /* File table overflow */
+#define  EMFILE       24  /* Too many open files */
+#define  ENOTTY       25  /* Not a typewriter */
+#define  ETXTBSY      26  /* Text file busy */
+#define  EFBIG        27  /* File too large */
+#define  ENOSPC       28  /* No space left on device */
+#define  ESPIPE       29  /* Illegal seek */
+#define  EROFS        30  /* Read-only file system */
+#define  EMLINK       31  /* Too many links */
+#define  EPIPE        32  /* Broken pipe */
+#define  EDOM         33  /* Math argument out of domain of func */
+#define  ERANGE       34  /* Math result not representable */
+#define  EDEADLK      35  /* Resource deadlock would occur */
+#define  ENAMETOOLONG 36  /* File name too long */
+#define  ENOLCK       37  /* No record locks available */
+#define  ENOSYS       38  /* Function not implemented */
+#define  ENOTEMPTY    39  /* Directory not empty */
+#define  ELOOP        40  /* Too many symbolic links encountered */
+#define  EWOULDBLOCK  EAGAIN  /* Operation would block */
+#define  ENOMSG       42  /* No message of desired type */
+#define  EIDRM        43  /* Identifier removed */
+#define  ECHRNG       44  /* Channel number out of range */
+#define  EL2NSYNC     45  /* Level 2 not synchronized */
+#define  EL3HLT       46  /* Level 3 halted */
+#define  EL3RST       47  /* Level 3 reset */
+#define  ELNRNG       48  /* Link number out of range */
+#define  EUNATCH      49  /* Protocol driver not attached */
+#define  ENOCSI       50  /* No CSI structure available */
+#define  EL2HLT       51  /* Level 2 halted */
+#define  EBADE        52  /* Invalid exchange */
+#define  EBADR        53  /* Invalid request descriptor */
+#define  EXFULL       54  /* Exchange full */
+#define  ENOANO       55  /* No anode */
+#define  EBADRQC      56  /* Invalid request code */
+#define  EBADSLT      57  /* Invalid slot */
+
+#define  EDEADLOCK    EDEADLK
+
+#define  EBFONT       59  /* Bad font file format */
+#define  ENOSTR       60  /* Device not a stream */
+#define  ENODATA      61  /* No data available */
+#define  ETIME        62  /* Timer expired */
+#define  ENOSR        63  /* Out of streams resources */
+#define  ENONET       64  /* Machine is not on the network */
+#define  ENOPKG       65  /* Package not installed */
+#define  EREMOTE      66  /* Object is remote */
+#define  ENOLINK      67  /* Link has been severed */
+#define  EADV         68  /* Advertise error */
+#define  ESRMNT       69  /* Srmount error */
+#define  ECOMM        70  /* Communication error on send */
+#define  EPROTO       71  /* Protocol error */
+#define  EMULTIHOP    72  /* Multihop attempted */
+#define  EDOTDOT      73  /* RFS specific error */
+#define  EBADMSG      74  /* Not a data message */
+#define  EOVERFLOW    75  /* Value too large for defined data type */
+#define  ENOTUNIQ     76  /* Name not unique on network */
+#define  EBADFD       77  /* File descriptor in bad state */
+#define  EREMCHG      78  /* Remote address changed */
+#define  ELIBACC      79  /* Can not access a needed shared library */
+#define  ELIBBAD      80  /* Accessing a corrupted shared library */
+#define  ELIBSCN      81  /* .lib section in a.out corrupted */
+#define  ELIBMAX      82  /* Attempting to link in too many shared libraries */
+#define  ELIBEXEC     83  /* Cannot exec a shared library directly */
+#define  EILSEQ       84  /* Illegal byte sequence */
+#define  ERESTART     85  /* Interrupted system call should be restarted */
+#define  ESTRPIPE     86  /* Streams pipe error */
+#define  EUSERS       87  /* Too many users */
+#define  ENOTSOCK     88  /* Socket operation on non-socket */
+#define  EDESTADDRREQ 89  /* Destination address required */
+#define  EMSGSIZE     90  /* Message too long */
+#define  EPROTOTYPE   91  /* Protocol wrong type for socket */
+#define  ENOPROTOOPT  92  /* Protocol not available */
+#define  EPROTONOSUPPORT 93  /* Protocol not supported */
+#define  ESOCKTNOSUPPORT 94  /* Socket type not supported */
+#define  EOPNOTSUPP      95  /* Operation not supported on transport endpoint */
+#define  EPFNOSUPPORT    96  /* Protocol family not supported */
+#define  EAFNOSUPPORT    97  /* Address family not supported by protocol */
+#define  EADDRINUSE      98  /* Address already in use */
+#define  EADDRNOTAVAIL   99  /* Cannot assign requested address */
+#define  ENETDOWN       100  /* Network is down */
+#define  ENETUNREACH    101  /* Network is unreachable */
+#define  ENETRESET      102  /* Network dropped connection because of reset */
+#define  ECONNABORTED   103  /* Software caused connection abort */
+#define  ECONNRESET     104  /* Connection reset by peer */
+#define  ENOBUFS        105  /* No buffer space available */
+#define  EISCONN        106  /* Transport endpoint is already connected */
+#define  ENOTCONN       107  /* Transport endpoint is not connected */
+#define  ESHUTDOWN      108  /* Cannot send after transport endpoint shutdown */
+#define  ETOOMANYREFS   109  /* Too many references: cannot splice */
+#define  ETIMEDOUT      110  /* Connection timed out */
+#define  ECONNREFUSED   111  /* Connection refused */
+#define  EHOSTDOWN      112  /* Host is down */
+#define  EHOSTUNREACH   113  /* No route to host */
+#define  EALREADY       114  /* Operation already in progress */
+#define  EINPROGRESS    115  /* Operation now in progress */
+#define  ESTALE         116  /* Stale NFS file handle */
+#define  EUCLEAN        117  /* Structure needs cleaning */
+#define  ENOTNAM        118  /* Not a XENIX named type file */
+#define  ENAVAIL        119  /* No XENIX semaphores available */
+#define  EISNAM         120  /* Is a named type file */
+#define  EREMOTEIO      121  /* Remote I/O error */
+#define  EDQUOT         122  /* Quota exceeded */
+
+#define  ENOMEDIUM      123  /* No medium found */
+#define  EMEDIUMTYPE    124  /* Wrong medium type */
+
+#ifndef errno
+extern int errno;
+#endif
+
+#endif /* LWIP_PROVIDE_ERRNO */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_ARCH_H */
diff --git a/tools/sdk/include/lwip/lwip/autoip.h b/tools/sdk/include/lwip/lwip/autoip.h
new file mode 100755
index 00000000..c89fe3ff
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/autoip.h
@@ -0,0 +1,124 @@
+/**
+ * @file
+ *
+ * AutoIP Automatic LinkLocal IP Configuration
+ */
+
+/*
+ *
+ * Copyright (c) 2007 Dominik Spies 
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Dominik Spies 
+ *
+ * This is a AutoIP implementation for the lwIP TCP/IP stack. It aims to conform
+ * with RFC 3927.
+ *
+ *
+ * Please coordinate changes and requests with Dominik Spies
+ * 
+ */
+
+#ifndef LWIP_HDR_AUTOIP_H
+#define LWIP_HDR_AUTOIP_H
+
+#include "lwip/opt.h"
+
+#if LWIP_IPV4 && LWIP_AUTOIP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/netif.h"
+/* #include "lwip/udp.h" */
+#include "netif/etharp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* AutoIP Timing */
+#define AUTOIP_TMR_INTERVAL      100
+#define AUTOIP_TICKS_PER_SECOND (1000 / AUTOIP_TMR_INTERVAL)
+
+/* RFC 3927 Constants */
+#define PROBE_WAIT               1   /* second   (initial random delay)                 */
+#define PROBE_MIN                1   /* second   (minimum delay till repeated probe)    */
+#define PROBE_MAX                2   /* seconds  (maximum delay till repeated probe)    */
+#define PROBE_NUM                3   /*          (number of probe packets)              */
+#define ANNOUNCE_NUM             2   /*          (number of announcement packets)       */
+#define ANNOUNCE_INTERVAL        2   /* seconds  (time between announcement packets)    */
+#define ANNOUNCE_WAIT            2   /* seconds  (delay before announcing)              */
+#define MAX_CONFLICTS            10  /*          (max conflicts before rate limiting)   */
+#define RATE_LIMIT_INTERVAL      60  /* seconds  (delay between successive attempts)    */
+#define DEFEND_INTERVAL          10  /* seconds  (min. wait between defensive ARPs)     */
+
+/* AutoIP client states */
+#define AUTOIP_STATE_OFF         0
+#define AUTOIP_STATE_PROBING     1
+#define AUTOIP_STATE_ANNOUNCING  2
+#define AUTOIP_STATE_BOUND       3
+
+struct autoip
+{
+  ip4_addr_t llipaddr;      /* the currently selected, probed, announced or used LL IP-Address */
+  u8_t state;               /* current AutoIP state machine state */
+  u8_t sent_num;            /* sent number of probes or announces, dependent on state */
+  u16_t ttw;                /* ticks to wait, tick is AUTOIP_TMR_INTERVAL long */
+  u8_t lastconflict;        /* ticks until a conflict can be solved by defending */
+  u8_t tried_llipaddr;      /* total number of probed/used Link Local IP-Addresses */
+};
+
+
+#define autoip_init() /* Compatibility define, no init needed. */
+
+/** Set a struct autoip allocated by the application to work with */
+void autoip_set_struct(struct netif *netif, struct autoip *autoip);
+
+/** Remove a struct autoip previously set to the netif using autoip_set_struct() */
+#define autoip_remove_struct(netif) do { (netif)->autoip = NULL; } while (0)
+
+/** Start AutoIP client */
+err_t autoip_start(struct netif *netif);
+
+/** Stop AutoIP client */
+err_t autoip_stop(struct netif *netif);
+
+/** Handles every incoming ARP Packet, called by etharp_arp_input */
+void autoip_arp_reply(struct netif *netif, struct etharp_hdr *hdr);
+
+/** Has to be called in loop every AUTOIP_TMR_INTERVAL milliseconds */
+void autoip_tmr(void);
+
+/** Handle a possible change in the network configuration */
+void autoip_network_changed(struct netif *netif);
+
+/** check if AutoIP supplied netif->ip_addr */
+u8_t autoip_supplied_address(struct netif *netif);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV4 && LWIP_AUTOIP */
+
+#endif /* LWIP_HDR_AUTOIP_H */
diff --git a/tools/sdk/include/lwip/lwip/debug.h b/tools/sdk/include/lwip/lwip/debug.h
new file mode 100755
index 00000000..973a633d
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/debug.h
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef LWIP_HDR_DEBUG_H
+#define LWIP_HDR_DEBUG_H
+
+#include "lwip/arch.h"
+#include "lwip/opt.h"
+
+/** lower two bits indicate debug level
+ * - 0 all
+ * - 1 warning
+ * - 2 serious
+ * - 3 severe
+ */
+#define LWIP_DBG_LEVEL_ALL     0x00
+#define LWIP_DBG_LEVEL_OFF     LWIP_DBG_LEVEL_ALL /* compatibility define only */
+#define LWIP_DBG_LEVEL_WARNING 0x01 /* bad checksums, dropped packets, ... */
+#define LWIP_DBG_LEVEL_SERIOUS 0x02 /* memory allocation failures, ... */
+#define LWIP_DBG_LEVEL_SEVERE  0x03
+#define LWIP_DBG_MASK_LEVEL    0x03
+
+/** flag for LWIP_DEBUGF to enable that debug message */
+#define LWIP_DBG_ON            0x80U
+/** flag for LWIP_DEBUGF to disable that debug message */
+#define LWIP_DBG_OFF           0x00U
+
+/** flag for LWIP_DEBUGF indicating a tracing message (to follow program flow) */
+#define LWIP_DBG_TRACE         0x40U
+/** flag for LWIP_DEBUGF indicating a state debug message (to follow module states) */
+#define LWIP_DBG_STATE         0x20U
+/** flag for LWIP_DEBUGF indicating newly added code, not thoroughly tested yet */
+#define LWIP_DBG_FRESH         0x10U
+/** flag for LWIP_DEBUGF to halt after printing this debug message */
+#define LWIP_DBG_HALT          0x08U
+
+/**
+ * LWIP_NOASSERT: Disable LWIP_ASSERT checks.
+ * -- To disable assertions define LWIP_NOASSERT in arch/cc.h.
+ */
+#ifndef LWIP_NOASSERT
+#define LWIP_ASSERT(message, assertion) do { if(!(assertion)) \
+  LWIP_PLATFORM_ASSERT(message); } while(0)
+#ifndef LWIP_PLATFORM_ASSERT
+#error "If you want to use LWIP_ASSERT, LWIP_PLATFORM_ASSERT(message) needs to be defined in your arch/cc.h"
+#endif
+#else  /* LWIP_NOASSERT */
+#define LWIP_ASSERT(message, assertion)
+#endif /* LWIP_NOASSERT */
+
+/** if "expression" isn't true, then print "message" and execute "handler" expression */
+#ifndef LWIP_ERROR
+#ifndef LWIP_NOASSERT
+#define LWIP_PLATFORM_ERROR(message) LWIP_PLATFORM_ASSERT(message)
+#elif defined LWIP_DEBUG
+#define LWIP_PLATFORM_ERROR(message) LWIP_PLATFORM_DIAG((message))
+#else
+#define LWIP_PLATFORM_ERROR(message)
+#endif
+
+#define LWIP_ERROR(message, expression, handler) do { if (!(expression)) { \
+  LWIP_PLATFORM_ERROR(message); handler;}} while(0)
+#endif /* LWIP_ERROR */
+
+#ifdef LWIP_DEBUG
+#ifndef LWIP_PLATFORM_DIAG
+#error "If you want to use LWIP_DEBUG, LWIP_PLATFORM_DIAG(message) needs to be defined in your arch/cc.h"
+#endif
+/** print debug message only if debug message type is enabled...
+ *  AND is of correct type AND is at least LWIP_DBG_LEVEL
+ */
+#define LWIP_DEBUGF(debug, message) do { \
+                               if ( \
+                                   ((debug) & LWIP_DBG_ON) && \
+                                   ((debug) & LWIP_DBG_TYPES_ON) && \
+                                   ((s16_t)((debug) & LWIP_DBG_MASK_LEVEL) >= LWIP_DBG_MIN_LEVEL)) { \
+                                 LWIP_PLATFORM_DIAG(message); \
+                                 if ((debug) & LWIP_DBG_HALT) { \
+                                   while(1); \
+                                 } \
+                               } \
+                             } while(0)
+
+#else  /* LWIP_DEBUG */
+#define LWIP_DEBUGF(debug, message)
+#endif /* LWIP_DEBUG */
+
+#endif /* LWIP_HDR_DEBUG_H */
+
diff --git a/tools/sdk/include/lwip/lwip/def.h b/tools/sdk/include/lwip/lwip/def.h
new file mode 100755
index 00000000..49571363
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/def.h
@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef LWIP_HDR_DEF_H
+#define LWIP_HDR_DEF_H
+
+/* arch.h might define NULL already */
+#include "lwip/arch.h"
+#include "lwip/opt.h"
+#if LWIP_PERF
+#include "arch/perf.h"
+#else /* LWIP_PERF */
+#define PERF_START    /* null definition */
+#define PERF_STOP(x)  /* null definition */
+#endif /* LWIP_PERF */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LWIP_MAX(x , y)  (((x) > (y)) ? (x) : (y))
+#define LWIP_MIN(x , y)  (((x) < (y)) ? (x) : (y))
+
+/* Get the number of entries in an array ('x' must NOT be a pointer!) */
+#define LWIP_ARRAYSIZE(x) (sizeof(x)/sizeof((x)[0]))
+
+#ifndef NULL
+#define NULL ((void *)0)
+#endif
+
+/* Endianess-optimized shifting of two u8_t to create one u16_t */
+#if BYTE_ORDER == LITTLE_ENDIAN
+#define LWIP_MAKE_U16(a, b) ((a << 8) | b)
+#else
+#define LWIP_MAKE_U16(a, b) ((b << 8) | a)
+#endif
+
+#ifndef LWIP_PLATFORM_BYTESWAP
+#define LWIP_PLATFORM_BYTESWAP 0
+#endif
+
+#ifndef LWIP_PREFIX_BYTEORDER_FUNCS
+/* workaround for naming collisions on some platforms */
+
+#ifdef htons
+#undef htons
+#endif /* htons */
+#ifdef htonl
+#undef htonl
+#endif /* htonl */
+#ifdef ntohs
+#undef ntohs
+#endif /* ntohs */
+#ifdef ntohl
+#undef ntohl
+#endif /* ntohl */
+
+#define htons(x) lwip_htons(x)
+#define ntohs(x) lwip_ntohs(x)
+#define htonl(x) lwip_htonl(x)
+#define ntohl(x) lwip_ntohl(x)
+#endif /* LWIP_PREFIX_BYTEORDER_FUNCS */
+
+#if BYTE_ORDER == BIG_ENDIAN
+#define lwip_htons(x) (x)
+#define lwip_ntohs(x) (x)
+#define lwip_htonl(x) (x)
+#define lwip_ntohl(x) (x)
+#define PP_HTONS(x) (x)
+#define PP_NTOHS(x) (x)
+#define PP_HTONL(x) (x)
+#define PP_NTOHL(x) (x)
+#else /* BYTE_ORDER != BIG_ENDIAN */
+#if LWIP_PLATFORM_BYTESWAP
+#define lwip_htons(x) LWIP_PLATFORM_HTONS(x)
+#define lwip_ntohs(x) LWIP_PLATFORM_HTONS(x)
+#define lwip_htonl(x) LWIP_PLATFORM_HTONL(x)
+#define lwip_ntohl(x) LWIP_PLATFORM_HTONL(x)
+#else /* LWIP_PLATFORM_BYTESWAP */
+u16_t lwip_htons(u16_t x);
+u16_t lwip_ntohs(u16_t x);
+u32_t lwip_htonl(u32_t x);
+u32_t lwip_ntohl(u32_t x);
+#endif /* LWIP_PLATFORM_BYTESWAP */
+
+/* These macros should be calculated by the preprocessor and are used
+   with compile-time constants only (so that there is no little-endian
+   overhead at runtime). */
+#define PP_HTONS(x) ((((x) & 0xff) << 8) | (((x) & 0xff00) >> 8))
+#define PP_NTOHS(x) PP_HTONS(x)
+#define PP_HTONL(x) ((((x) & 0xff) << 24) | \
+                     (((x) & 0xff00) << 8) | \
+                     (((x) & 0xff0000UL) >> 8) | \
+                     (((x) & 0xff000000UL) >> 24))
+#define PP_NTOHL(x) PP_HTONL(x)
+
+#endif /* BYTE_ORDER == BIG_ENDIAN */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_DEF_H */
+
diff --git a/tools/sdk/include/lwip/lwip/dhcp.h b/tools/sdk/include/lwip/lwip/dhcp.h
new file mode 100755
index 00000000..2d8926ec
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/dhcp.h
@@ -0,0 +1,306 @@
+/*
+ * Copyright (c) 2001-2004 Leon Woestenberg 
+ * Copyright (c) 2001-2004 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Leon Woestenberg 
+ *
+ */
+#ifndef LWIP_HDR_DHCP_H
+#define LWIP_HDR_DHCP_H
+
+#include "lwip/opt.h"
+
+#if LWIP_DHCP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/netif.h"
+#include "lwip/udp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** period (in seconds) of the application calling dhcp_coarse_tmr() */
+#define DHCP_COARSE_TIMER_SECS 60
+/** period (in milliseconds) of the application calling dhcp_coarse_tmr() */
+#define DHCP_COARSE_TIMER_MSECS (DHCP_COARSE_TIMER_SECS * 1000UL)
+/** period (in milliseconds) of the application calling dhcp_fine_tmr() */
+#define DHCP_FINE_TIMER_MSECS 500
+
+#define DHCP_CHADDR_LEN 16U
+#define DHCP_SNAME_LEN  64U
+#define DHCP_FILE_LEN   128U
+
+struct dhcp
+{
+  /** transaction identifier of last sent request */
+  u32_t xid;
+  /** incoming msg */
+  struct dhcp_msg *msg_in;
+  /** track PCB allocation state */
+  u8_t pcb_allocated;
+  /** current DHCP state machine state */
+  u8_t state;
+  /** retries of current request */
+  u8_t tries;
+#if LWIP_DHCP_AUTOIP_COOP
+  u8_t autoip_coop_state;
+#endif
+  u8_t subnet_mask_given;
+
+  struct pbuf *p_out; /* pbuf of outcoming msg */
+  struct dhcp_msg *msg_out; /* outgoing msg */
+  u16_t options_out_len; /* outgoing msg options length */
+  u16_t request_timeout; /* #ticks with period DHCP_FINE_TIMER_SECS for request timeout */
+  u16_t t1_timeout;  /* #ticks with period DHCP_COARSE_TIMER_SECS for renewal time */
+  u16_t t2_timeout;  /* #ticks with period DHCP_COARSE_TIMER_SECS for rebind time */
+  u16_t t1_renew_time;  /* #ticks with period DHCP_COARSE_TIMER_SECS until next renew try */
+  u16_t t2_rebind_time; /* #ticks with period DHCP_COARSE_TIMER_SECS until next rebind try */
+  u16_t lease_used; /* #ticks with period DHCP_COARSE_TIMER_SECS since last received DHCP ack */
+  u16_t t0_timeout; /* #ticks with period DHCP_COARSE_TIMER_SECS for lease time */
+  ip_addr_t server_ip_addr; /* dhcp server address that offered this lease (ip_addr_t because passed to UDP) */
+  ip4_addr_t offered_ip_addr;
+  ip4_addr_t offered_sn_mask;
+  ip4_addr_t offered_gw_addr;
+
+  u32_t offered_t0_lease; /* lease period (in seconds) */
+  u32_t offered_t1_renew; /* recommended renew time (usually 50% of lease period) */
+  u32_t offered_t2_rebind; /* recommended rebind time (usually 87.5 of lease period)  */
+#if LWIP_DHCP_BOOTP_FILE
+  ip_addr_t offered_si_addr;
+  char boot_file_name[DHCP_FILE_LEN];
+#endif /* LWIP_DHCP_BOOTPFILE */
+
+  /* Espressif add start. */
+  void (*cb)(void); /* callback for dhcp, add a parameter to show dhcp status if needed */
+  /* Espressif add end. */
+};
+
+/* MUST be compiled with "pack structs" or equivalent! */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+/** minimum set of fields of any DHCP message */
+struct dhcp_msg
+{
+  PACK_STRUCT_FLD_8(u8_t op);
+  PACK_STRUCT_FLD_8(u8_t htype);
+  PACK_STRUCT_FLD_8(u8_t hlen);
+  PACK_STRUCT_FLD_8(u8_t hops);
+  PACK_STRUCT_FIELD(u32_t xid);
+  PACK_STRUCT_FIELD(u16_t secs);
+  PACK_STRUCT_FIELD(u16_t flags);
+  PACK_STRUCT_FLD_S(ip4_addr_p_t ciaddr);
+  PACK_STRUCT_FLD_S(ip4_addr_p_t yiaddr);
+  PACK_STRUCT_FLD_S(ip4_addr_p_t siaddr);
+  PACK_STRUCT_FLD_S(ip4_addr_p_t giaddr);
+  PACK_STRUCT_FLD_8(u8_t chaddr[DHCP_CHADDR_LEN]);
+  PACK_STRUCT_FLD_8(u8_t sname[DHCP_SNAME_LEN]);
+  PACK_STRUCT_FLD_8(u8_t file[DHCP_FILE_LEN]);
+  PACK_STRUCT_FIELD(u32_t cookie);
+#define DHCP_MIN_OPTIONS_LEN 68U
+/** make sure user does not configure this too small */
+#if ((defined(DHCP_OPTIONS_LEN)) && (DHCP_OPTIONS_LEN < DHCP_MIN_OPTIONS_LEN))
+#  undef DHCP_OPTIONS_LEN
+#endif
+/** allow this to be configured in lwipopts.h, but not too small */
+#if (!defined(DHCP_OPTIONS_LEN))
+/** set this to be sufficient for your options in outgoing DHCP msgs */
+#  define DHCP_OPTIONS_LEN DHCP_MIN_OPTIONS_LEN
+#endif
+  PACK_STRUCT_FLD_8(u8_t options[DHCP_OPTIONS_LEN]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+void dhcp_set_struct(struct netif *netif, struct dhcp *dhcp);
+/** Remove a struct dhcp previously set to the netif using dhcp_set_struct() */
+#define dhcp_remove_struct(netif) do { (netif)->dhcp = NULL; } while(0)
+void dhcp_cleanup(struct netif *netif);
+/* Espressif add start. */
+/** set callback for DHCP */
+void dhcp_set_cb(struct netif *netif, void (*cb)(void));
+/* Espressif add end. */
+/** start DHCP configuration */
+err_t dhcp_start(struct netif *netif);
+/** enforce early lease renewal (not needed normally)*/
+err_t dhcp_renew(struct netif *netif);
+/** release the DHCP lease, usually called before dhcp_stop()*/
+err_t dhcp_release(struct netif *netif);
+/** stop DHCP configuration */
+void dhcp_stop(struct netif *netif);
+/** inform server of our manual IP address */
+void dhcp_inform(struct netif *netif);
+/** Handle a possible change in the network configuration */
+void dhcp_network_changed(struct netif *netif);
+
+/** if enabled, check whether the offered IP address is not in use, using ARP */
+#if DHCP_DOES_ARP_CHECK
+void dhcp_arp_reply(struct netif *netif, const ip4_addr_t *addr);
+#endif
+
+/** check if DHCP supplied netif->ip_addr */
+u8_t dhcp_supplied_address(struct netif *netif);
+
+/** to be called every minute */
+void dhcp_coarse_tmr(void);
+/** to be called every half second */
+void dhcp_fine_tmr(void);
+
+/** DHCP message item offsets and length */
+#define DHCP_OP_OFS       0
+#define DHCP_HTYPE_OFS    1
+#define DHCP_HLEN_OFS     2
+#define DHCP_HOPS_OFS     3
+#define DHCP_XID_OFS      4
+#define DHCP_SECS_OFS     8
+#define DHCP_FLAGS_OFS    10
+#define DHCP_CIADDR_OFS   12
+#define DHCP_YIADDR_OFS   16
+#define DHCP_SIADDR_OFS   20
+#define DHCP_GIADDR_OFS   24
+#define DHCP_CHADDR_OFS   28
+#define DHCP_SNAME_OFS    44
+#define DHCP_FILE_OFS     108
+#define DHCP_MSG_LEN      236
+
+#define DHCP_COOKIE_OFS   DHCP_MSG_LEN
+#define DHCP_OPTIONS_OFS  (DHCP_MSG_LEN + 4)
+
+#define DHCP_CLIENT_PORT  68
+#define DHCP_SERVER_PORT  67
+
+/** DHCP client states */
+#define DHCP_STATE_OFF          0
+#define DHCP_STATE_REQUESTING   1
+#define DHCP_STATE_INIT         2
+#define DHCP_STATE_REBOOTING    3
+#define DHCP_STATE_REBINDING    4
+#define DHCP_STATE_RENEWING     5
+#define DHCP_STATE_SELECTING    6
+#define DHCP_STATE_INFORMING    7
+#define DHCP_STATE_CHECKING     8
+/** not yet implemented #define DHCP_STATE_PERMANENT 9 */
+#define DHCP_STATE_BOUND        10
+/** not yet implemented #define DHCP_STATE_RELEASING 11 */
+#define DHCP_STATE_BACKING_OFF  12
+
+/** AUTOIP cooperation flags */
+#define DHCP_AUTOIP_COOP_STATE_OFF  0
+#define DHCP_AUTOIP_COOP_STATE_ON   1
+
+#define DHCP_BOOTREQUEST  1
+#define DHCP_BOOTREPLY    2
+
+/** DHCP message types */
+#define DHCP_DISCOVER 1
+#define DHCP_OFFER    2
+#define DHCP_REQUEST  3
+#define DHCP_DECLINE  4
+#define DHCP_ACK      5
+#define DHCP_NAK      6
+#define DHCP_RELEASE  7
+#define DHCP_INFORM   8
+
+/** DHCP hardware type, currently only ethernet is supported */
+#define DHCP_HTYPE_ETH 1
+
+#define DHCP_MAGIC_COOKIE 0x63825363UL
+
+/* This is a list of options for BOOTP and DHCP, see RFC 2132 for descriptions */
+
+/** BootP options */
+#define DHCP_OPTION_PAD 0
+#define DHCP_OPTION_SUBNET_MASK 1 /* RFC 2132 3.3 */
+#define DHCP_OPTION_ROUTER 3
+#define DHCP_OPTION_DNS_SERVER 6
+#define DHCP_OPTION_HOSTNAME 12
+#define DHCP_OPTION_IP_TTL 23
+#define DHCP_OPTION_MTU 26
+#define DHCP_OPTION_BROADCAST 28
+#define DHCP_OPTION_TCP_TTL 37
+#define DHCP_OPTION_NTP 42
+#define DHCP_OPTION_END 255
+
+#ifdef LWIP_ESP8266
+/**add options for support more router by liuHan**/
+#define DHCP_OPTION_DOMAIN_NAME 15
+#define DHCP_OPTION_PRD 31
+#define DHCP_OPTION_STATIC_ROUTER 33
+#define DHCP_OPTION_VSN 43
+#define DHCP_OPTION_NB_TINS 44
+#define DHCP_OPTION_NB_TINT 46
+#define DHCP_OPTION_NB_TIS 47
+#define DHCP_OPTION_CLASSLESS_STATIC_ROUTER 121
+#endif
+
+
+
+/** DHCP options */
+#define DHCP_OPTION_REQUESTED_IP 50 /* RFC 2132 9.1, requested IP address */
+#define DHCP_OPTION_LEASE_TIME 51 /* RFC 2132 9.2, time in seconds, in 4 bytes */
+#define DHCP_OPTION_OVERLOAD 52 /* RFC2132 9.3, use file and/or sname field for options */
+
+#define DHCP_OPTION_MESSAGE_TYPE 53 /* RFC 2132 9.6, important for DHCP */
+#define DHCP_OPTION_MESSAGE_TYPE_LEN 1
+
+#define DHCP_OPTION_SERVER_ID 54 /* RFC 2132 9.7, server IP address */
+#define DHCP_OPTION_PARAMETER_REQUEST_LIST 55 /* RFC 2132 9.8, requested option types */
+
+#define DHCP_OPTION_MAX_MSG_SIZE 57 /* RFC 2132 9.10, message size accepted >= 576 */
+#define DHCP_OPTION_MAX_MSG_SIZE_LEN 2
+
+#define DHCP_OPTION_T1 58 /* T1 renewal time */
+#define DHCP_OPTION_T2 59 /* T2 rebinding time */
+#define DHCP_OPTION_US 60
+#define DHCP_OPTION_CLIENT_ID 61
+#define DHCP_OPTION_TFTP_SERVERNAME 66
+#define DHCP_OPTION_BOOTFILE 67
+
+/** possible combinations of overloading the file and sname fields with options */
+#define DHCP_OVERLOAD_NONE 0
+#define DHCP_OVERLOAD_FILE 1
+#define DHCP_OVERLOAD_SNAME  2
+#define DHCP_OVERLOAD_SNAME_FILE 3
+
+#if LWIP_DHCP_GET_NTP_SRV
+/** This function must exist, in other to add offered NTP servers to
+ * the NTP (or SNTP) engine.
+ * See LWIP_DHCP_MAX_NTP_SERVERS */
+extern void dhcp_set_ntp_servers(u8_t num_ntp_servers, const ip4_addr_t* ntp_server_addrs);
+#endif /* LWIP_DHCP_GET_NTP_SRV */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_DHCP */
+
+#endif /*LWIP_HDR_DHCP_H*/
diff --git a/tools/sdk/include/lwip/lwip/dhcp6.h b/tools/sdk/include/lwip/lwip/dhcp6.h
new file mode 100755
index 00000000..345bcf00
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/dhcp6.h
@@ -0,0 +1,58 @@
+/**
+ * @file
+ *
+ * IPv6 address autoconfiguration as per RFC 4862.
+ */
+
+/*
+ * Copyright (c) 2010 Inico Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Ivan Delamer 
+ *
+ * IPv6 address autoconfiguration as per RFC 4862.
+ *
+ * Please coordinate changes and requests with Ivan Delamer
+ * 
+ */
+
+#ifndef LWIP_HDR_IP6_DHCP6_H
+#define LWIP_HDR_IP6_DHCP6_H
+
+#include "lwip/opt.h"
+
+#if LWIP_IPV6_DHCP6  /* don't build if not configured for use in lwipopts.h */
+
+
+struct dhcp6
+{
+  /*TODO: implement DHCP6*/
+};
+
+#endif /* LWIP_IPV6_DHCP6 */
+
+#endif /* LWIP_HDR_IP6_DHCP6_H */
diff --git a/tools/sdk/include/lwip/lwip/dns.h b/tools/sdk/include/lwip/lwip/dns.h
new file mode 100755
index 00000000..1ceed0d8
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/dns.h
@@ -0,0 +1,118 @@
+/**
+ * lwip DNS resolver header file.
+
+ * Author: Jim Pettinato
+ *   April 2007
+
+ * ported from uIP resolv.c Copyright (c) 2002-2003, Adam Dunkels.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LWIP_HDR_DNS_H
+#define LWIP_HDR_DNS_H
+
+#include "lwip/opt.h"
+
+#ifdef LWIP_ESP8266
+#include "lwip/err.h"
+#endif
+
+
+#if LWIP_DNS
+
+#include "lwip/ip_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** DNS timer period */
+#define DNS_TMR_INTERVAL          1000
+
+/* DNS resolve types: */
+#define LWIP_DNS_ADDRTYPE_IPV4      0
+#define LWIP_DNS_ADDRTYPE_IPV6      1
+#define LWIP_DNS_ADDRTYPE_IPV4_IPV6 2 /* try to resolve IPv4 first, try IPv6 if IPv4 fails only */
+#define LWIP_DNS_ADDRTYPE_IPV6_IPV4 3 /* try to resolve IPv6 first, try IPv4 if IPv6 fails only */
+#if LWIP_IPV4 && LWIP_IPV6
+#ifndef LWIP_DNS_ADDRTYPE_DEFAULT
+#define LWIP_DNS_ADDRTYPE_DEFAULT   LWIP_DNS_ADDRTYPE_IPV4_IPV6
+#endif
+#elif defined(LWIP_IPV4)
+#define LWIP_DNS_ADDRTYPE_DEFAULT   LWIP_DNS_ADDRTYPE_IPV4
+#else
+#define LWIP_DNS_ADDRTYPE_DEFAULT   LWIP_DNS_ADDRTYPE_IPV6
+#endif
+
+#if DNS_LOCAL_HOSTLIST
+/** struct used for local host-list */
+struct local_hostlist_entry {
+  /** static hostname */
+  const char *name;
+  /** static host address in network byteorder */
+  ip_addr_t addr;
+  struct local_hostlist_entry *next;
+};
+#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC
+#ifndef DNS_LOCAL_HOSTLIST_MAX_NAMELEN
+#define DNS_LOCAL_HOSTLIST_MAX_NAMELEN  DNS_MAX_NAME_LENGTH
+#endif
+#define LOCALHOSTLIST_ELEM_SIZE ((sizeof(struct local_hostlist_entry) + DNS_LOCAL_HOSTLIST_MAX_NAMELEN + 1))
+#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */
+#endif /* DNS_LOCAL_HOSTLIST */
+
+/** Callback which is invoked when a hostname is found.
+ * A function of this type must be implemented by the application using the DNS resolver.
+ * @param name pointer to the name that was looked up.
+ * @param ipaddr pointer to an ip_addr_t containing the IP address of the hostname,
+ *        or NULL if the name could not be found (or on any other error).
+ * @param callback_arg a user-specified callback argument passed to dns_gethostbyname
+*/
+typedef void (*dns_found_callback)(const char *name, const ip_addr_t *ipaddr, void *callback_arg);
+
+void           dns_init(void);
+void           dns_tmr(void);
+void           dns_setserver(u8_t numdns, const ip_addr_t *dnsserver);
+ip_addr_t      dns_getserver(u8_t numdns);
+err_t          dns_gethostbyname(const char *hostname, ip_addr_t *addr,
+                                 dns_found_callback found, void *callback_arg);
+err_t          dns_gethostbyname_addrtype(const char *hostname, ip_addr_t *addr,
+                                 dns_found_callback found, void *callback_arg,
+                                 u8_t dns_addrtype);
+
+
+#if DNS_LOCAL_HOSTLIST && DNS_LOCAL_HOSTLIST_IS_DYNAMIC
+int            dns_local_removehost(const char *hostname, const ip_addr_t *addr);
+err_t          dns_local_addhost(const char *hostname, const ip_addr_t *addr);
+#endif /* DNS_LOCAL_HOSTLIST && DNS_LOCAL_HOSTLIST_IS_DYNAMIC */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_DNS */
+
+#endif /* LWIP_HDR_DNS_H */
diff --git a/tools/sdk/include/lwip/lwip/err.h b/tools/sdk/include/lwip/lwip/err.h
new file mode 100755
index 00000000..26fb91db
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/err.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef LWIP_HDR_ERR_H
+#define LWIP_HDR_ERR_H
+
+#include "lwip/opt.h"
+#include "lwip/arch.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Define LWIP_ERR_T in cc.h if you want to use
+ *  a different type for your platform (must be signed). */
+#ifdef LWIP_ERR_T
+typedef LWIP_ERR_T err_t;
+#else /* LWIP_ERR_T */
+typedef s8_t err_t;
+#endif /* LWIP_ERR_T*/
+
+/* Definitions for error constants. */
+
+#define ERR_OK          0    /* No error, everything OK. */
+#define ERR_MEM        -1    /* Out of memory error.     */
+#define ERR_BUF        -2    /* Buffer error.            */
+#define ERR_TIMEOUT    -3    /* Timeout.                 */
+#define ERR_RTE        -4    /* Routing problem.         */
+#define ERR_INPROGRESS -5    /* Operation in progress    */
+#define ERR_VAL        -6    /* Illegal value.           */
+#define ERR_WOULDBLOCK -7    /* Operation would block.   */
+#define ERR_USE        -8    /* Address in use.          */
+
+
+#ifdef LWIP_ESP8266
+#define ERR_ALREADY    -9	 /* Already connected.       */
+#define ERR_ISCONN     -10   /* Conn already established.*/
+#define ERR_IS_FATAL(e) ((e) < ERR_ISCONN)
+#define ERR_ABRT       -11   /* Connection aborted.      */
+#define ERR_RST        -12   /* Connection reset.        */
+#define ERR_CLSD       -13   /* Connection closed.       */
+#define ERR_CONN       -14   /* Not connected.           */
+#define ERR_ARG        -15   /* Illegal argument.        */
+#define ERR_IF         -16   /* Low-level netif error    */
+#else
+#define ERR_ALREADY    -9    /* Already connecting.      */
+#define ERR_ISCONN     -10   /* Conn already established.*/
+#define ERR_CONN       -11   /* Not connected.           */
+#define ERR_IF         -12   /* Low-level netif error    */
+#define ERR_IS_FATAL(e) ((e) <= ERR_ABRT)
+#define ERR_ABRT       -13   /* Connection aborted.      */
+#define ERR_RST        -14   /* Connection reset.        */
+#define ERR_CLSD       -15   /* Connection closed.       */
+#define ERR_ARG        -16   /* Illegal argument.        */
+#endif
+
+#ifdef LWIP_DEBUG
+extern const char *lwip_strerr(err_t err);
+#else
+#define lwip_strerr(x) ""
+#endif /* LWIP_DEBUG */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_ERR_H */
diff --git a/tools/sdk/include/lwip/lwip/ethip6.h b/tools/sdk/include/lwip/lwip/ethip6.h
new file mode 100755
index 00000000..5e88dffd
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/ethip6.h
@@ -0,0 +1,68 @@
+/**
+ * @file
+ *
+ * Ethernet output for IPv6. Uses ND tables for link-layer addressing.
+ */
+
+/*
+ * Copyright (c) 2010 Inico Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Ivan Delamer 
+ *
+ *
+ * Please coordinate changes and requests with Ivan Delamer
+ * 
+ */
+
+#ifndef LWIP_HDR_ETHIP6_H
+#define LWIP_HDR_ETHIP6_H
+
+#include "lwip/opt.h"
+
+#if LWIP_IPV6 && LWIP_ETHERNET /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/pbuf.h"
+#include "lwip/ip6.h"
+#include "lwip/ip6_addr.h"
+#include "lwip/netif.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+err_t ethip6_output(struct netif *netif, struct pbuf *q, const ip6_addr_t *ip6addr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV6 && LWIP_ETHERNET */
+
+#endif /* LWIP_HDR_ETHIP6_H */
diff --git a/tools/sdk/include/lwip/lwip/icmp.h b/tools/sdk/include/lwip/lwip/icmp.h
new file mode 100755
index 00000000..af3a4550
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/icmp.h
@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef LWIP_HDR_ICMP_H
+#define LWIP_HDR_ICMP_H
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+
+#if LWIP_IPV6 && LWIP_ICMP6
+#include "lwip/icmp6.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ICMP_ER   0    /* echo reply */
+#define ICMP_DUR  3    /* destination unreachable */
+#define ICMP_SQ   4    /* source quench */
+#define ICMP_RD   5    /* redirect */
+#define ICMP_ECHO 8    /* echo */
+#define ICMP_TE  11    /* time exceeded */
+#define ICMP_PP  12    /* parameter problem */
+#define ICMP_TS  13    /* timestamp */
+#define ICMP_TSR 14    /* timestamp reply */
+#define ICMP_IRQ 15    /* information request */
+#define ICMP_IR  16    /* information reply */
+#define ICMP_AM  17    /* address mask request */
+#define ICMP_AMR 18    /* address mask reply */
+
+enum icmp_dur_type {
+  ICMP_DUR_NET   = 0,  /* net unreachable */
+  ICMP_DUR_HOST  = 1,  /* host unreachable */
+  ICMP_DUR_PROTO = 2,  /* protocol unreachable */
+  ICMP_DUR_PORT  = 3,  /* port unreachable */
+  ICMP_DUR_FRAG  = 4,  /* fragmentation needed and DF set */
+  ICMP_DUR_SR    = 5   /* source route failed */
+};
+
+enum icmp_te_type {
+  ICMP_TE_TTL  = 0,    /* time to live exceeded in transit */
+  ICMP_TE_FRAG = 1     /* fragment reassembly time exceeded */
+};
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+/** This is the standard ICMP header only that the u32_t data
+ *  is split to two u16_t like ICMP echo needs it.
+ *  This header is also used for other ICMP types that do not
+ *  use the data part.
+ */
+PACK_STRUCT_BEGIN
+struct icmp_echo_hdr {
+  PACK_STRUCT_FLD_8(u8_t type);
+  PACK_STRUCT_FLD_8(u8_t code);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FIELD(u16_t id);
+  PACK_STRUCT_FIELD(u16_t seqno);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define ICMPH_TYPE(hdr) ((hdr)->type)
+#define ICMPH_CODE(hdr) ((hdr)->code)
+
+/** Combines type and code to an u16_t */
+#define ICMPH_TYPE_SET(hdr, t) ((hdr)->type = (t))
+#define ICMPH_CODE_SET(hdr, c) ((hdr)->code = (c))
+
+
+#if LWIP_IPV4 && LWIP_ICMP /* don't build if not configured for use in lwipopts.h */
+
+void icmp_input(struct pbuf *p, struct netif *inp);
+void icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t);
+void icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t);
+
+#endif /* LWIP_IPV4 && LWIP_ICMP */
+
+#if LWIP_IPV4 && LWIP_IPV6
+#if LWIP_ICMP && LWIP_ICMP6
+#define icmp_port_unreach(isipv6, pbuf) ((isipv6) ? \
+                                         icmp6_dest_unreach(pbuf, ICMP6_DUR_PORT) : \
+                                         icmp_dest_unreach(pbuf, ICMP_DUR_PORT))
+#elif LWIP_ICMP
+#define icmp_port_unreach(isipv6, pbuf) do{ if(!(isipv6)) { icmp_dest_unreach(pbuf, ICMP_DUR_PORT);}}while(0)
+#elif LWIP_ICMP6
+#define icmp_port_unreach(isipv6, pbuf) do{ if(isipv6) { icmp6_dest_unreach(pbuf, ICMP6_DUR_PORT);}}while(0)
+#else
+#define icmp_port_unreach(isipv6, pbuf)
+#endif
+#elif LWIP_IPV6 && LWIP_ICMP6
+#define icmp_port_unreach(isipv6, pbuf) icmp6_dest_unreach(pbuf, ICMP6_DUR_PORT)
+#elif LWIP_IPV4 && LWIP_ICMP
+#define icmp_port_unreach(isipv6, pbuf) icmp_dest_unreach(pbuf, ICMP_DUR_PORT)
+#else /* (LWIP_IPV6 && LWIP_ICMP6) || (LWIP_IPV4 && LWIP_ICMP) */
+#define icmp_port_unreach(isipv6, pbuf)
+#endif /* (LWIP_IPV6 && LWIP_ICMP6) || (LWIP_IPV4 && LWIP_ICMP) LWIP_IPV4*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_ICMP_H */
diff --git a/tools/sdk/include/lwip/lwip/icmp6.h b/tools/sdk/include/lwip/lwip/icmp6.h
new file mode 100755
index 00000000..9d57103f
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/icmp6.h
@@ -0,0 +1,152 @@
+/**
+ * @file
+ *
+ * IPv6 version of ICMP, as per RFC 4443.
+ */
+
+/*
+ * Copyright (c) 2010 Inico Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Ivan Delamer 
+ *
+ *
+ * Please coordinate changes and requests with Ivan Delamer
+ * 
+ */
+#ifndef LWIP_HDR_ICMP6_H
+#define LWIP_HDR_ICMP6_H
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip6_addr.h"
+#include "lwip/netif.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+enum icmp6_type {
+  ICMP6_TYPE_DUR = 1,  /* Destination unreachable */
+  ICMP6_TYPE_PTB = 2,  /* Packet too big */
+  ICMP6_TYPE_TE = 3,   /* Time exceeded */
+  ICMP6_TYPE_PP = 4,   /* Parameter problem */
+  ICMP6_TYPE_PE1 = 100,  /* Private experimentation */
+  ICMP6_TYPE_PE2 = 101,  /* Private experimentation */
+  ICMP6_TYPE_RSV_ERR = 127,  /* Reserved for expansion of error messages */
+
+  ICMP6_TYPE_EREQ = 128,  /* Echo request */
+  ICMP6_TYPE_EREP = 129,  /* Echo reply */
+  ICMP6_TYPE_MLQ = 130,  /* Multicast listener query */
+  ICMP6_TYPE_MLR = 131,  /* Multicast listener report */
+  ICMP6_TYPE_MLD = 132,  /* Multicast listener done */
+  ICMP6_TYPE_RS = 133,  /* Router solicitation */
+  ICMP6_TYPE_RA = 134,  /* Router advertisement */
+  ICMP6_TYPE_NS = 135,  /* Neighbor solicitation */
+  ICMP6_TYPE_NA = 136,  /* Neighbor advertisement */
+  ICMP6_TYPE_RD = 137,  /* Redirect */
+  ICMP6_TYPE_MRA = 151,  /* Multicast router advertisement */
+  ICMP6_TYPE_MRS = 152,  /* Multicast router solicitation */
+  ICMP6_TYPE_MRT = 153,  /* Multicast router termination */
+  ICMP6_TYPE_PE3 = 200,  /* Private experimentation */
+  ICMP6_TYPE_PE4 = 201,  /* Private experimentation */
+  ICMP6_TYPE_RSV_INF = 255  /* Reserved for expansion of informational messages */
+};
+
+enum icmp6_dur_code {
+  ICMP6_DUR_NO_ROUTE = 0,     /* No route to destination */
+  ICMP6_DUR_PROHIBITED = 1,   /* Communication with destination administratively prohibited */
+  ICMP6_DUR_SCOPE = 2,        /* Beyond scope of source address */
+  ICMP6_DUR_ADDRESS = 3,      /* Address unreachable */
+  ICMP6_DUR_PORT = 4,         /* Port unreachable */
+  ICMP6_DUR_POLICY = 5,       /* Source address failed ingress/egress policy */
+  ICMP6_DUR_REJECT_ROUTE = 6  /* Reject route to destination */
+};
+
+enum icmp6_te_code {
+  ICMP6_TE_HL = 0,   /* Hop limit exceeded in transit */
+  ICMP6_TE_FRAG = 1  /* Fragment reassembly time exceeded */
+};
+
+enum icmp6_pp_code {
+  ICMP6_PP_FIELD = 0,   /* Erroneous header field encountered */
+  ICMP6_PP_HEADER = 1,  /* Unrecognized next header type encountered */
+  ICMP6_PP_OPTION = 2   /* Unrecognized IPv6 option encountered */
+};
+
+/** This is the standard ICMP6 header. */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct icmp6_hdr {
+  PACK_STRUCT_FLD_8(u8_t type);
+  PACK_STRUCT_FLD_8(u8_t code);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FIELD(u32_t data);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/** This is the ICMP6 header adapted for echo req/resp. */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct icmp6_echo_hdr {
+  PACK_STRUCT_FLD_8(u8_t type);
+  PACK_STRUCT_FLD_8(u8_t code);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FIELD(u16_t id);
+  PACK_STRUCT_FIELD(u16_t seqno);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+
+#if LWIP_ICMP6 && LWIP_IPV6 /* don't build if not configured for use in lwipopts.h */
+
+void icmp6_input(struct pbuf *p, struct netif *inp);
+void icmp6_dest_unreach(struct pbuf *p, enum icmp6_dur_code c);
+void icmp6_packet_too_big(struct pbuf *p, u32_t mtu);
+void icmp6_time_exceeded(struct pbuf *p, enum icmp6_te_code c);
+void icmp6_param_problem(struct pbuf *p, enum icmp6_pp_code c, u32_t pointer);
+
+#endif /* LWIP_ICMP6 && LWIP_IPV6 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* LWIP_HDR_ICMP6_H */
diff --git a/tools/sdk/include/lwip/lwip/igmp.h b/tools/sdk/include/lwip/lwip/igmp.h
new file mode 100755
index 00000000..bff1a613
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/igmp.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2002 CITEL Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of CITEL Technologies Ltd nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY CITEL TECHNOLOGIES AND CONTRIBUTORS ``AS IS''
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL CITEL TECHNOLOGIES OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is a contribution to the lwIP TCP/IP stack.
+ * The Swedish Institute of Computer Science and Adam Dunkels
+ * are specifically granted permission to redistribute this
+ * source code.
+*/
+
+#ifndef LWIP_HDR_IGMP_H
+#define LWIP_HDR_IGMP_H
+
+#include "lwip/opt.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/pbuf.h"
+
+#if LWIP_IPV4 && LWIP_IGMP /* don't build if not configured for use in lwipopts.h */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* IGMP timer */
+#define IGMP_TMR_INTERVAL              100 /* Milliseconds */
+#define IGMP_V1_DELAYING_MEMBER_TMR   (1000/IGMP_TMR_INTERVAL)
+#define IGMP_JOIN_DELAYING_MEMBER_TMR (500 /IGMP_TMR_INTERVAL)
+
+/* MAC Filter Actions, these are passed to a netif's
+ * igmp_mac_filter callback function. */
+#define IGMP_DEL_MAC_FILTER            0
+#define IGMP_ADD_MAC_FILTER            1
+
+
+/**
+ * igmp group structure - there is
+ * a list of groups for each interface
+ * these should really be linked from the interface, but
+ * if we keep them separate we will not affect the lwip original code
+ * too much
+ *
+ * There will be a group for the all systems group address but this
+ * will not run the state machine as it is used to kick off reports
+ * from all the other groups
+ */
+struct igmp_group {
+    /** next link */
+  struct igmp_group *next;
+  /** interface on which the group is active */
+  struct netif      *netif;
+  /** multicast address */
+  ip4_addr_t         group_address;
+  /** signifies we were the last person to report */
+  u8_t               last_reporter_flag;
+  /** current state of the group */
+  u8_t               group_state;
+  /** timer for reporting, negative is OFF */
+  u16_t              timer;
+  /** counter of simultaneous uses */
+  u8_t               use; 
+};
+
+/*  Prototypes */
+void   igmp_init(void);
+err_t  igmp_start(struct netif *netif);
+err_t  igmp_stop(struct netif *netif);
+void   igmp_report_groups(struct netif *netif);
+struct igmp_group *igmp_lookfor_group(struct netif *ifp, const ip4_addr_t *addr);
+void   igmp_input(struct pbuf *p, struct netif *inp, const ip4_addr_t *dest);
+err_t  igmp_joingroup(const ip4_addr_t *ifaddr, const ip4_addr_t *groupaddr);
+err_t  igmp_joingroup_netif(struct netif *netif, const ip4_addr_t *groupaddr);
+err_t  igmp_leavegroup(const ip4_addr_t *ifaddr, const ip4_addr_t *groupaddr);
+err_t  igmp_leavegroup_netif(struct netif *netif, const ip4_addr_t *groupaddr);
+void   igmp_tmr(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV4 && LWIP_IGMP */
+
+#endif /* LWIP_HDR_IGMP_H */
diff --git a/tools/sdk/include/lwip/lwip/inet.h b/tools/sdk/include/lwip/lwip/inet.h
new file mode 100755
index 00000000..036cd988
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/inet.h
@@ -0,0 +1,172 @@
+/**
+ * @file
+ * This file (together with sockets.h) aims to provide structs and functions from
+ * - arpa/inet.h
+ * - netinet/in.h
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef LWIP_HDR_INET_H
+#define LWIP_HDR_INET_H
+
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/ip_addr.h"
+#include "lwip/ip6_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* If your port already typedef's in_addr_t, define IN_ADDR_T_DEFINED
+   to prevent this code from redefining it. */
+#if !defined(in_addr_t) && !defined(IN_ADDR_T_DEFINED)
+typedef u32_t in_addr_t;
+#endif
+
+struct in_addr {
+  in_addr_t s_addr;
+};
+
+struct in6_addr {
+  union {
+    u32_t u32_addr[4];
+    u8_t  u8_addr[16];
+  } un;
+#define s6_addr  un.u8_addr
+};
+
+/** 255.255.255.255 */
+#define INADDR_NONE         IPADDR_NONE
+/** 127.0.0.1 */
+#define INADDR_LOOPBACK     IPADDR_LOOPBACK
+/** 0.0.0.0 */
+#define INADDR_ANY          IPADDR_ANY
+/** 255.255.255.255 */
+#define INADDR_BROADCAST    IPADDR_BROADCAST
+
+/** This macro can be used to initialize a variable of type struct in6_addr
+    to the IPv6 wildcard address. */
+#define IN6ADDR_ANY_INIT {{{0,0,0,0}}}
+/** This macro can be used to initialize a variable of type struct in6_addr
+    to the IPv6 loopback address. */
+#define IN6ADDR_LOOPBACK_INIT {{{0,0,0,PP_HTONL(1)}}}
+/** This variable is initialized by the system to contain the wildcard IPv6 address. */
+extern const struct in6_addr in6addr_any;
+
+/* Definitions of the bits in an (IPv4) Internet address integer.
+
+   On subnets, host and network parts are found according to
+   the subnet mask, not these masks.  */
+#define IN_CLASSA(a)        IP_CLASSA(a)
+#define IN_CLASSA_NET       IP_CLASSA_NET
+#define IN_CLASSA_NSHIFT    IP_CLASSA_NSHIFT
+#define IN_CLASSA_HOST      IP_CLASSA_HOST
+#define IN_CLASSA_MAX       IP_CLASSA_MAX
+
+#define IN_CLASSB(b)        IP_CLASSB(b)
+#define IN_CLASSB_NET       IP_CLASSB_NET
+#define IN_CLASSB_NSHIFT    IP_CLASSB_NSHIFT
+#define IN_CLASSB_HOST      IP_CLASSB_HOST
+#define IN_CLASSB_MAX       IP_CLASSB_MAX
+
+#define IN_CLASSC(c)        IP_CLASSC(c)
+#define IN_CLASSC_NET       IP_CLASSC_NET
+#define IN_CLASSC_NSHIFT    IP_CLASSC_NSHIFT
+#define IN_CLASSC_HOST      IP_CLASSC_HOST
+#define IN_CLASSC_MAX       IP_CLASSC_MAX
+
+#define IN_CLASSD(d)        IP_CLASSD(d)
+#define IN_CLASSD_NET       IP_CLASSD_NET     /* These ones aren't really */
+#define IN_CLASSD_NSHIFT    IP_CLASSD_NSHIFT  /*   net and host fields, but */
+#define IN_CLASSD_HOST      IP_CLASSD_HOST    /*   routing needn't know. */
+#define IN_CLASSD_MAX       IP_CLASSD_MAX
+
+#define IN_MULTICAST(a)     IP_MULTICAST(a)
+
+#define IN_EXPERIMENTAL(a)  IP_EXPERIMENTAL(a)
+#define IN_BADCLASS(a)      IP_BADCLASS(a)
+
+#define IN_LOOPBACKNET      IP_LOOPBACKNET
+
+
+#ifndef INET_ADDRSTRLEN
+#define INET_ADDRSTRLEN     IP4ADDR_STRLEN_MAX
+#endif
+#if LWIP_IPV6
+#ifndef INET6_ADDRSTRLEN
+#define INET6_ADDRSTRLEN    IP6ADDR_STRLEN_MAX
+#endif
+#endif
+
+#if LWIP_IPV4
+
+#define inet_addr_from_ipaddr(target_inaddr, source_ipaddr) ((target_inaddr)->s_addr = ip4_addr_get_u32(source_ipaddr))
+#define inet_addr_to_ipaddr(target_ipaddr, source_inaddr)   (ip4_addr_set_u32(target_ipaddr, (source_inaddr)->s_addr))
+/* ATTENTION: the next define only works because both s_addr and ip_addr_t are an u32_t effectively! */
+#define inet_addr_to_ipaddr_p(target_ipaddr_p, source_inaddr)   ((target_ipaddr_p) = (ip_addr_t*)&((source_inaddr)->s_addr))
+
+/* directly map this to the lwip internal functions */
+#define inet_addr(cp)                   ipaddr_addr(cp)
+#define inet_aton(cp, addr)             ip4addr_aton(cp, (ip4_addr_t*)addr)
+#define inet_ntoa(addr)                 ip4addr_ntoa((const ip4_addr_t*)&(addr))
+#define inet_ntoa_r(addr, buf, buflen)  ip4addr_ntoa_r((const ip4_addr_t*)&(addr), buf, buflen)
+
+#endif /* LWIP_IPV4 */
+
+#if LWIP_IPV6
+#define inet6_addr_from_ip6addr(target_in6addr, source_ip6addr) {(target_in6addr)->un.u32_addr[0] = (source_ip6addr)->addr[0]; \
+                                                                 (target_in6addr)->un.u32_addr[1] = (source_ip6addr)->addr[1]; \
+                                                                 (target_in6addr)->un.u32_addr[2] = (source_ip6addr)->addr[2]; \
+                                                                 (target_in6addr)->un.u32_addr[3] = (source_ip6addr)->addr[3];}
+#define inet6_addr_to_ip6addr(target_ip6addr, source_in6addr)   {(target_ip6addr)->addr[0] = (source_in6addr)->un.u32_addr[0]; \
+                                                                 (target_ip6addr)->addr[1] = (source_in6addr)->un.u32_addr[1]; \
+                                                                 (target_ip6addr)->addr[2] = (source_in6addr)->un.u32_addr[2]; \
+                                                                 (target_ip6addr)->addr[3] = (source_in6addr)->un.u32_addr[3];}
+/* ATTENTION: the next define only works because both in6_addr and ip6_addr_t are an u32_t[4] effectively! */
+#define inet6_addr_to_ip6addr_p(target_ip6addr_p, source_in6addr)   ((target_ip6addr_p) = (ip6_addr_t*)(source_in6addr))
+
+/* directly map this to the lwip internal functions */
+#define inet6_aton(cp, addr)            ip6addr_aton(cp, (ip6_addr_t*)addr)
+#define inet6_ntoa(addr)                ip6addr_ntoa((const ip6_addr_t*)&(addr))
+#define inet6_ntoa_r(addr, buf, buflen) ip6addr_ntoa_r((const ip6_addr_t*)&(addr), buf, buflen)
+
+#endif /* LWIP_IPV6 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_INET_H */
diff --git a/tools/sdk/include/lwip/lwip/inet_chksum.h b/tools/sdk/include/lwip/lwip/inet_chksum.h
new file mode 100755
index 00000000..1766f4b5
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/inet_chksum.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef LWIP_HDR_INET_CHKSUM_H
+#define LWIP_HDR_INET_CHKSUM_H
+
+#include "lwip/opt.h"
+
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+
+/** Swap the bytes in an u16_t: much like htons() for little-endian */
+#ifndef SWAP_BYTES_IN_WORD
+#if LWIP_PLATFORM_BYTESWAP && (BYTE_ORDER == LITTLE_ENDIAN)
+/* little endian and PLATFORM_BYTESWAP defined */
+#define SWAP_BYTES_IN_WORD(w) LWIP_PLATFORM_HTONS(w)
+#else /* LWIP_PLATFORM_BYTESWAP && (BYTE_ORDER == LITTLE_ENDIAN) */
+/* can't use htons on big endian (or PLATFORM_BYTESWAP not defined)... */
+#define SWAP_BYTES_IN_WORD(w) (((w) & 0xff) << 8) | (((w) & 0xff00) >> 8)
+#endif /* LWIP_PLATFORM_BYTESWAP && (BYTE_ORDER == LITTLE_ENDIAN)*/
+#endif /* SWAP_BYTES_IN_WORD */
+
+/** Split an u32_t in two u16_ts and add them up */
+#ifndef FOLD_U32T
+#define FOLD_U32T(u)          (((u) >> 16) + ((u) & 0x0000ffffUL))
+#endif
+
+#if LWIP_CHECKSUM_ON_COPY
+/** Function-like macro: same as MEMCPY but returns the checksum of copied data
+    as u16_t */
+# ifndef LWIP_CHKSUM_COPY
+#  define LWIP_CHKSUM_COPY(dst, src, len) lwip_chksum_copy(dst, src, len)
+#  ifndef LWIP_CHKSUM_COPY_ALGORITHM
+#   define LWIP_CHKSUM_COPY_ALGORITHM 1
+#  endif /* LWIP_CHKSUM_COPY_ALGORITHM */
+# else /* LWIP_CHKSUM_COPY */
+#  define LWIP_CHKSUM_COPY_ALGORITHM 0
+# endif /* LWIP_CHKSUM_COPY */
+#else /* LWIP_CHECKSUM_ON_COPY */
+# define LWIP_CHKSUM_COPY_ALGORITHM 0
+#endif /* LWIP_CHECKSUM_ON_COPY */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+u16_t inet_chksum(const void *dataptr, u16_t len);
+u16_t inet_chksum_pbuf(struct pbuf *p);
+#if LWIP_CHKSUM_COPY_ALGORITHM
+u16_t lwip_chksum_copy(void *dst, const void *src, u16_t len);
+#endif /* LWIP_CHKSUM_COPY_ALGORITHM */
+
+#if LWIP_IPV4
+u16_t inet_chksum_pseudo(struct pbuf *p, u8_t proto, u16_t proto_len,
+       const ip4_addr_t *src, const ip4_addr_t *dest);
+u16_t inet_chksum_pseudo_partial(struct pbuf *p, u8_t proto,
+       u16_t proto_len, u16_t chksum_len, const ip4_addr_t *src, const ip4_addr_t *dest);
+#endif /* LWIP_IPV4 */
+
+#if LWIP_IPV6
+u16_t ip6_chksum_pseudo(struct pbuf *p, u8_t proto, u16_t proto_len,
+       const ip6_addr_t *src, const ip6_addr_t *dest);
+u16_t ip6_chksum_pseudo_partial(struct pbuf *p, u8_t proto, u16_t proto_len,
+       u16_t chksum_len, const ip6_addr_t *src, const ip6_addr_t *dest);
+#endif /* LWIP_IPV6 */
+
+
+u16_t ip_chksum_pseudo(struct pbuf *p, u8_t proto, u16_t proto_len,
+       const ip_addr_t *src, const ip_addr_t *dest);
+u16_t ip_chksum_pseudo_partial(struct pbuf *p, u8_t proto, u16_t proto_len,
+       u16_t chksum_len, const ip_addr_t *src, const ip_addr_t *dest);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_INET_H */
+
diff --git a/tools/sdk/include/lwip/lwip/init.h b/tools/sdk/include/lwip/lwip/init.h
new file mode 100755
index 00000000..70351b86
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/init.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef LWIP_HDR_INIT_H
+#define LWIP_HDR_INIT_H
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** X.x.x: Major version of the stack */
+#define LWIP_VERSION_MAJOR      1U
+/** x.X.x: Minor version of the stack */
+#define LWIP_VERSION_MINOR      5U
+/** x.x.X: Revision of the stack */
+#define LWIP_VERSION_REVISION   0U
+/** For release candidates, this is set to 1..254
+  * For official releases, this is set to 255 (LWIP_RC_RELEASE)
+  * For development versions (Git), this is set to 0 (LWIP_RC_DEVELOPMENT) */
+#define LWIP_VERSION_RC         0U
+
+/** LWIP_VERSION_RC is set to LWIP_RC_RELEASE for official releases */
+#define LWIP_RC_RELEASE         255U
+/** LWIP_VERSION_RC is set to LWIP_RC_DEVELOPMENT for Git versions */
+#define LWIP_RC_DEVELOPMENT     0U
+
+#define LWIP_VERSION_IS_RELEASE     (LWIP_VERSION_RC == LWIP_RC_RELEASE)
+#define LWIP_VERSION_IS_DEVELOPMENT (LWIP_VERSION_RC == LWIP_RC_DEVELOPMENT)
+#define LWIP_VERSION_IS_RC          ((LWIP_VERSION_RC != LWIP_RC_RELEASE) && (LWIP_VERSION_RC != LWIP_RC_DEVELOPMENT))
+
+/** Provides the version of the stack */
+#define LWIP_VERSION   (LWIP_VERSION_MAJOR << 24   | LWIP_VERSION_MINOR << 16 | \
+                        LWIP_VERSION_REVISION << 8 | LWIP_VERSION_RC)
+
+/* Modules initialization */
+void lwip_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_INIT_H */
diff --git a/tools/sdk/include/lwip/lwip/ip.h b/tools/sdk/include/lwip/lwip/ip.h
new file mode 100755
index 00000000..d42fe681
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/ip.h
@@ -0,0 +1,304 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef LWIP_HDR_IP_H__
+#define LWIP_HDR_IP_H__
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+#include "lwip/err.h"
+#include "lwip/netif.h"
+#include "lwip/ip4.h"
+#include "lwip/ip6.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define IP_PROTO_ICMP    1
+#define IP_PROTO_IGMP    2
+#define IP_PROTO_UDP     17
+#define IP_PROTO_UDPLITE 136
+#define IP_PROTO_TCP     6
+
+/** This operates on a void* by loading the first byte */
+#define IP_HDR_GET_VERSION(ptr)   ((*(u8_t*)(ptr)) >> 4)
+
+/* This is passed as the destination address to ip_output_if (not
+   to ip_output), meaning that an IP header already is constructed
+   in the pbuf. This is used when TCP retransmits. */
+#ifdef IP_HDRINCL
+#undef IP_HDRINCL
+#endif /* IP_HDRINCL */
+#define IP_HDRINCL  NULL
+
+/** pbufs passed to IP must have a ref-count of 1 as their payload pointer
+    gets altered as the packet is passed down the stack */
+#ifndef LWIP_IP_CHECK_PBUF_REF_COUNT_FOR_TX
+#define LWIP_IP_CHECK_PBUF_REF_COUNT_FOR_TX(p) LWIP_ASSERT("p->ref == 1", (p)->ref == 1)
+#endif
+
+#if LWIP_NETIF_HWADDRHINT
+#define IP_PCB_ADDRHINT ;u8_t addr_hint
+#else
+#define IP_PCB_ADDRHINT
+#endif /* LWIP_NETIF_HWADDRHINT */
+
+/* This is the common part of all PCB types. It needs to be at the
+   beginning of a PCB type definition. It is located here so that
+   changes to this common part are made in one location instead of
+   having to change all PCB structs. */
+#define IP_PCB \
+  /* ip addresses in network byte order */ \
+  ip_addr_t local_ip; \
+  ip_addr_t remote_ip; \
+   /* Socket options */  \
+  u8_t so_options;      \
+   /* Type Of Service */ \
+  u8_t tos;              \
+  /* Time To Live */     \
+  u8_t ttl               \
+  /* link layer address resolution hint */ \
+  IP_PCB_ADDRHINT
+
+struct ip_pcb {
+/* Common members of all PCB types */
+  IP_PCB;
+};
+
+/*
+ * Option flags per-socket. These are the same like SO_XXX in sockets.h
+ */
+#define SOF_REUSEADDR     0x04U  /* allow local address reuse */
+#define SOF_KEEPALIVE     0x08U  /* keep connections alive */
+#define SOF_BROADCAST     0x20U  /* permit to send and to receive broadcast messages (see IP_SOF_BROADCAST option) */
+
+/* These flags are inherited (e.g. from a listen-pcb to a connection-pcb): */
+#define SOF_INHERITED   (SOF_REUSEADDR|SOF_KEEPALIVE)
+
+/* Global variables of this module, kept in a struct for efficient access using base+index. */
+struct ip_globals
+{
+  /** The interface that accepted the packet for the current callback invocation. */
+  struct netif *current_netif;
+  /** The interface that received the packet for the current callback invocation. */
+  struct netif *current_input_netif;
+#if LWIP_IPV4
+  /** Header of the input packet currently being processed. */
+  struct ip_hdr *current_ip4_header;
+#endif /* LWIP_IPV4 */
+#if LWIP_IPV6
+  /** Header of the input IPv6 packet currently being processed. */
+  struct ip6_hdr *current_ip6_header;
+#endif /* LWIP_IPV6 */
+  /** Total header length of current_ip4/6_header (i.e. after this, the UDP/TCP header starts) */
+  u16_t current_ip_header_tot_len;
+  /** Source IP address of current_header */
+  ip_addr_t current_iphdr_src;
+  /** Destination IP address of current_header */
+  ip_addr_t current_iphdr_dest;
+};
+extern struct ip_globals ip_data;
+
+
+/** Get the interface that accepted the current packet.
+ * This may or may not be the receiving netif, depending on your netif/network setup.
+ * This function must only be called from a receive callback (udp_recv,
+ * raw_recv, tcp_accept). It will return NULL otherwise. */
+#define ip_current_netif()      (ip_data.current_netif)
+/** Get the interface that received the current packet.
+ * This function must only be called from a receive callback (udp_recv,
+ * raw_recv, tcp_accept). It will return NULL otherwise. */
+#define ip_current_input_netif() (ip_data.current_input_netif)
+/** Total header length of ip(6)_current_header() (i.e. after this, the UDP/TCP header starts) */
+#define ip_current_header_tot_len() (ip_data.current_ip_header_tot_len)
+/** Source IP address of current_header */
+#define ip_current_src_addr()   (&ip_data.current_iphdr_src)
+/** Destination IP address of current_header */
+#define ip_current_dest_addr()  (&ip_data.current_iphdr_dest)
+
+#if LWIP_IPV4 && LWIP_IPV6
+/** Get the IPv4 header of the current packet.
+ * This function must only be called from a receive callback (udp_recv,
+ * raw_recv, tcp_accept). It will return NULL otherwise. */
+#define ip4_current_header()     ((const struct ip_hdr*)(ip_data.current_ip4_header))
+/** Get the IPv6 header of the current packet.
+ * This function must only be called from a receive callback (udp_recv,
+ * raw_recv, tcp_accept). It will return NULL otherwise. */
+#define ip6_current_header()      ((const struct ip6_hdr*)(ip_data.current_ip6_header))
+/** Returns TRUE if the current IP input packet is IPv6, FALSE if it is IPv4 */
+#define ip_current_is_v6()        (ip6_current_header() != NULL)
+/** Source IPv6 address of current_header */
+#define ip6_current_src_addr()    (ip_2_ip6(&ip_data.current_iphdr_src))
+/** Destination IPv6 address of current_header */
+#define ip6_current_dest_addr()   (ip_2_ip6(&ip_data.current_iphdr_dest))
+/** Get the transport layer protocol */
+#define ip_current_header_proto() (ip_current_is_v6() ? \
+                                   IP6H_NEXTH(ip6_current_header()) :\
+                                   IPH_PROTO(ip4_current_header()))
+/** Get the transport layer header */
+#define ip_next_header_ptr()     ((const void*)((ip_current_is_v6() ? \
+  (const u8_t*)ip6_current_header() : (const u8_t*)ip4_current_header())  + ip_current_header_tot_len()))
+
+/** Source IP4 address of current_header */
+#define ip4_current_src_addr()     (ip_2_ip4(&ip_data.current_iphdr_src))
+/** Destination IP4 address of current_header */
+#define ip4_current_dest_addr()    (ip_2_ip4(&ip_data.current_iphdr_dest))
+
+#elif LWIP_IPV4 /* LWIP_IPV4 && LWIP_IPV6 */
+
+/** Get the IPv4 header of the current packet.
+ * This function must only be called from a receive callback (udp_recv,
+ * raw_recv, tcp_accept). It will return NULL otherwise. */
+#define ip4_current_header()     ((const struct ip_hdr*)(ip_data.current_ip4_header))
+/** Always returns FALSE when only supporting IPv4 only */
+#define ip_current_is_v6()        0
+/** Get the transport layer protocol */
+#define ip_current_header_proto() IPH_PROTO(ip4_current_header())
+/** Get the transport layer header */
+#define ip_next_header_ptr()     ((const void*)((const u8_t*)ip4_current_header() + ip_current_header_tot_len()))
+/** Source IP4 address of current_header */
+#define ip4_current_src_addr()     (&ip_data.current_iphdr_src)
+/** Destination IP4 address of current_header */
+#define ip4_current_dest_addr()    (&ip_data.current_iphdr_dest)
+
+#elif LWIP_IPV6 /* LWIP_IPV4 && LWIP_IPV6 */
+
+/** Get the IPv6 header of the current packet.
+ * This function must only be called from a receive callback (udp_recv,
+ * raw_recv, tcp_accept). It will return NULL otherwise. */
+#define ip6_current_header()      ((const struct ip6_hdr*)(ip_data.current_ip6_header))
+/** Always returns TRUE when only supporting IPv6 only */
+#define ip_current_is_v6()        1
+/** Get the transport layer protocol */
+#define ip_current_header_proto() IP6H_NEXTH(ip6_current_header())
+/** Get the transport layer header */
+#define ip_next_header_ptr()     ((const void*)((const u8_t*)ip6_current_header()))
+/** Source IP6 address of current_header */
+#define ip6_current_src_addr()    (&ip_data.current_iphdr_src)
+/** Destination IP6 address of current_header */
+#define ip6_current_dest_addr()   (&ip_data.current_iphdr_dest)
+
+#endif /* LWIP_IPV6 */
+
+/** Union source address of current_header */
+#define ip_current_src_addr()    (&ip_data.current_iphdr_src)
+/** Union destination address of current_header */
+#define ip_current_dest_addr()   (&ip_data.current_iphdr_dest)
+
+/** Gets an IP pcb option (SOF_* flags) */
+#define ip_get_option(pcb, opt)   ((pcb)->so_options & (opt))
+/** Sets an IP pcb option (SOF_* flags) */
+#define ip_set_option(pcb, opt)   ((pcb)->so_options |= (opt))
+/** Resets an IP pcb option (SOF_* flags) */
+#define ip_reset_option(pcb, opt) ((pcb)->so_options &= ~(opt))
+
+#if LWIP_IPV4 && LWIP_IPV6
+#define ip_output(p, src, dest, ttl, tos, proto) \
+        (IP_IS_V6(dest) ? \
+        ip6_output(p, ip_2_ip6(src), ip_2_ip6(dest), ttl, tos, proto) : \
+        ip4_output(p, ip_2_ip4(src), ip_2_ip4(dest), ttl, tos, proto))
+#define ip_output_if(p, src, dest, ttl, tos, proto, netif) \
+        (IP_IS_V6(dest) ? \
+        ip6_output_if(p, ip_2_ip6(src), ip_2_ip6(dest), ttl, tos, proto, netif) : \
+        ip4_output_if(p, ip_2_ip4(src), ip_2_ip4(dest), ttl, tos, proto, netif))
+#define ip_output_if_src(p, src, dest, ttl, tos, proto, netif) \
+        (IP_IS_V6(dest) ? \
+        ip6_output_if_src(p, ip_2_ip6(src), ip_2_ip6(dest), ttl, tos, proto, netif) : \
+        ip4_output_if_src(p, ip_2_ip4(src), ip_2_ip4(dest), ttl, tos, proto, netif))
+#define ip_output_hinted(p, src, dest, ttl, tos, proto, addr_hint) \
+        (IP_IS_V6(dest) ? \
+        ip6_output_hinted(p, ip_2_ip6(src), ip_2_ip6(dest), ttl, tos, proto, addr_hint) : \
+        ip4_output_hinted(p, ip_2_ip4(src), ip_2_ip4(dest), ttl, tos, proto, addr_hint))
+#define ip_route(src, dest) \
+        (IP_IS_V6(dest) ? \
+        ip6_route(ip_2_ip6(src), ip_2_ip6(dest)) : \
+        ip4_route_src(ip_2_ip4(dest), ip_2_ip4(src)))
+#define ip_netif_get_local_ip(netif, dest) (IP_IS_V6(dest) ? \
+        ip6_netif_get_local_ip(netif, ip_2_ip6(dest)) : \
+        ip4_netif_get_local_ip(netif))
+#define ip_debug_print(is_ipv6, p) ((is_ipv6) ? ip6_debug_print(p) : ip4_debug_print(p))
+
+err_t ip_input(struct pbuf *p, struct netif *inp);
+
+#elif LWIP_IPV4 /* LWIP_IPV4 && LWIP_IPV6 */
+
+#define ip_output(p, src, dest, ttl, tos, proto) \
+        ip4_output(p, src, dest, ttl, tos, proto)
+#define ip_output_if(p, src, dest, ttl, tos, proto, netif) \
+        ip4_output_if(p, src, dest, ttl, tos, proto, netif)
+#define ip_output_if_src(p, src, dest, ttl, tos, proto, netif) \
+        ip4_output_if_src(p, src, dest, ttl, tos, proto, netif)
+#define ip_output_hinted(p, src, dest, ttl, tos, proto, addr_hint) \
+        ip4_output_hinted(p, src, dest, ttl, tos, proto, addr_hint)
+#define ip_route(src, dest) \
+        ip4_route_src(dest, src)
+#define ip_netif_get_local_ip(netif, dest) \
+        ip4_netif_get_local_ip(netif)
+#define ip_debug_print(is_ipv6, p) ip4_debug_print(p)
+
+#define ip_input ip4_input
+
+#elif LWIP_IPV6 /* LWIP_IPV4 && LWIP_IPV6 */
+
+#define ip_output(p, src, dest, ttl, tos, proto) \
+        ip6_output(p, src, dest, ttl, tos, proto)
+#define ip_output_if(p, src, dest, ttl, tos, proto, netif) \
+        ip6_output_if(p, src, dest, ttl, tos, proto, netif)
+#define ip_output_if_src(p, src, dest, ttl, tos, proto, netif) \
+        ip6_output_if_src(p, src, dest, ttl, tos, proto, netif)
+#define ip_output_hinted(p, src, dest, ttl, tos, proto, addr_hint) \
+        ip6_output_hinted(p, src, dest, ttl, tos, proto, addr_hint)
+#define ip_route(src, dest) \
+        ip6_route(src, dest)
+#define ip_netif_get_local_ip(netif, dest) \
+        ip6_netif_get_local_ip(netif, dest)
+#define ip_debug_print(is_ipv6, p) ip6_debug_print(p)
+
+#define ip_input ip6_input
+
+#endif /* LWIP_IPV6 */
+
+#define ip_route_get_local_ip(src, dest, netif, ipaddr) do { \
+  (netif) = ip_route(src, dest); \
+  (ipaddr) = ip_netif_get_local_ip(netif, dest); \
+}while(0)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_IP_H__ */
+
+
diff --git a/tools/sdk/include/lwip/lwip/ip4.h b/tools/sdk/include/lwip/lwip/ip4.h
new file mode 100755
index 00000000..e69e55c7
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/ip4.h
@@ -0,0 +1,161 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef LWIP_HDR_IP4_H
+#define LWIP_HDR_IP4_H
+
+#include "lwip/opt.h"
+
+#if LWIP_IPV4
+
+#include "lwip/def.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip4_addr.h"
+#include "lwip/err.h"
+#include "lwip/netif.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef LWIP_HOOK_IP4_ROUTE_SRC
+#define LWIP_IPV4_SRC_ROUTING   1
+#else
+#define LWIP_IPV4_SRC_ROUTING   0
+#endif
+
+/** Currently, the function ip_output_if_opt() is only used with IGMP */
+#define IP_OPTIONS_SEND   (LWIP_IPV4 && LWIP_IGMP)
+
+#define IP_HLEN 20
+
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip_hdr {
+  /* version / header length */
+  PACK_STRUCT_FLD_8(u8_t _v_hl);
+  /* type of service */
+  PACK_STRUCT_FLD_8(u8_t _tos);
+  /* total length */
+  PACK_STRUCT_FIELD(u16_t _len);
+  /* identification */
+  PACK_STRUCT_FIELD(u16_t _id);
+  /* fragment offset field */
+  PACK_STRUCT_FIELD(u16_t _offset);
+#define IP_RF 0x8000U        /* reserved fragment flag */
+#define IP_DF 0x4000U        /* don't fragment flag */
+#define IP_MF 0x2000U        /* more fragments flag */
+#define IP_OFFMASK 0x1fffU   /* mask for fragmenting bits */
+  /* time to live */
+  PACK_STRUCT_FLD_8(u8_t _ttl);
+  /* protocol*/
+  PACK_STRUCT_FLD_8(u8_t _proto);
+  /* checksum */
+  PACK_STRUCT_FIELD(u16_t _chksum);
+  /* source and destination IP addresses */
+  PACK_STRUCT_FLD_S(ip4_addr_p_t src);
+  PACK_STRUCT_FLD_S(ip4_addr_p_t dest);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define IPH_V(hdr)  ((hdr)->_v_hl >> 4)
+#define IPH_HL(hdr) ((hdr)->_v_hl & 0x0f)
+#define IPH_TOS(hdr) ((hdr)->_tos)
+#define IPH_LEN(hdr) ((hdr)->_len)
+#define IPH_ID(hdr) ((hdr)->_id)
+#define IPH_OFFSET(hdr) ((hdr)->_offset)
+#define IPH_TTL(hdr) ((hdr)->_ttl)
+#define IPH_PROTO(hdr) ((hdr)->_proto)
+#define IPH_CHKSUM(hdr) ((hdr)->_chksum)
+
+#define IPH_VHL_SET(hdr, v, hl) (hdr)->_v_hl = (u8_t)((((v) << 4) | (hl)))
+#define IPH_TOS_SET(hdr, tos) (hdr)->_tos = (tos)
+#define IPH_LEN_SET(hdr, len) (hdr)->_len = (len)
+#define IPH_ID_SET(hdr, id) (hdr)->_id = (id)
+#define IPH_OFFSET_SET(hdr, off) (hdr)->_offset = (off)
+#define IPH_TTL_SET(hdr, ttl) (hdr)->_ttl = (u8_t)(ttl)
+#define IPH_PROTO_SET(hdr, proto) (hdr)->_proto = (u8_t)(proto)
+#define IPH_CHKSUM_SET(hdr, chksum) (hdr)->_chksum = (chksum)
+
+#define ip_init() /* Compatibility define, no init needed. */
+struct netif *ip4_route(const ip4_addr_t *dest);
+#if LWIP_IPV4_SRC_ROUTING
+struct netif *ip4_route_src(const ip4_addr_t *dest, const ip4_addr_t *src);
+#else /* LWIP_IPV4_SRC_ROUTING */
+#define ip4_route_src(dest, src) ip4_route(dest)
+#endif /* LWIP_IPV4_SRC_ROUTING */
+err_t ip4_input(struct pbuf *p, struct netif *inp);
+err_t ip4_output(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
+       u8_t ttl, u8_t tos, u8_t proto);
+err_t ip4_output_if(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
+       u8_t ttl, u8_t tos, u8_t proto, struct netif *netif);
+err_t ip4_output_if_src(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
+       u8_t ttl, u8_t tos, u8_t proto, struct netif *netif);
+#if LWIP_NETIF_HWADDRHINT
+err_t ip4_output_hinted(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
+       u8_t ttl, u8_t tos, u8_t proto, u8_t *addr_hint);
+#endif /* LWIP_NETIF_HWADDRHINT */
+#if IP_OPTIONS_SEND
+err_t ip4_output_if_opt(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
+       u8_t ttl, u8_t tos, u8_t proto, struct netif *netif, void *ip_options,
+       u16_t optlen);
+err_t ip4_output_if_opt_src(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
+       u8_t ttl, u8_t tos, u8_t proto, struct netif *netif, void *ip_options,
+       u16_t optlen);
+#endif /* IP_OPTIONS_SEND */
+
+#if LWIP_MULTICAST_TX_OPTIONS
+void  ip4_set_default_multicast_netif(struct netif* default_multicast_netif);
+#endif /* LWIP_MULTICAST_TX_OPTIONS */
+
+#define ip4_netif_get_local_ip(netif) (((netif) != NULL) ? netif_ip_addr4(netif) : NULL)
+
+#if IP_DEBUG
+void ip4_debug_print(struct pbuf *p);
+#else
+#define ip4_debug_print(p)
+#endif /* IP_DEBUG */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV4 */
+
+#endif /* LWIP_HDR_IP_H */
+
+
diff --git a/tools/sdk/include/lwip/lwip/ip4_addr.h b/tools/sdk/include/lwip/lwip/ip4_addr.h
new file mode 100755
index 00000000..9483a2f7
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/ip4_addr.h
@@ -0,0 +1,253 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef LWIP_HDR_IP4_ADDR_H
+#define LWIP_HDR_IP4_ADDR_H
+
+#include "lwip/opt.h"
+#include "lwip/def.h"
+
+#if LWIP_IPV4
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* This is the aligned version of ip4_addr_t,
+   used as local variable, on the stack, etc. */
+struct ip4_addr {
+  u32_t addr;
+};
+
+/* This is the packed version of ip4_addr_t,
+   used in network headers that are itself packed */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip4_addr_packed {
+  PACK_STRUCT_FIELD(u32_t addr);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/** ip4_addr_t uses a struct for convenience only, so that the same defines can
+ * operate both on ip4_addr_t as well as on ip4_addr_p_t. */
+typedef struct ip4_addr ip4_addr_t;
+typedef struct ip4_addr_packed ip4_addr_p_t;
+
+/*
+ * struct ipaddr2 is used in the definition of the ARP packet format in
+ * order to support compilers that don't have structure packing.
+ */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip4_addr2 {
+  PACK_STRUCT_FIELD(u16_t addrw[2]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/* Forward declaration to not include netif.h */
+struct netif;
+
+/** 255.255.255.255 */
+#define IPADDR_NONE         ((u32_t)0xffffffffUL)
+/** 127.0.0.1 */
+#define IPADDR_LOOPBACK     ((u32_t)0x7f000001UL)
+/** 0.0.0.0 */
+#define IPADDR_ANY          ((u32_t)0x00000000UL)
+/** 255.255.255.255 */
+#define IPADDR_BROADCAST    ((u32_t)0xffffffffUL)
+
+/* Definitions of the bits in an Internet address integer.
+
+   On subnets, host and network parts are found according to
+   the subnet mask, not these masks.  */
+#define IP_CLASSA(a)        ((((u32_t)(a)) & 0x80000000UL) == 0)
+#define IP_CLASSA_NET       0xff000000
+#define IP_CLASSA_NSHIFT    24
+#define IP_CLASSA_HOST      (0xffffffff & ~IP_CLASSA_NET)
+#define IP_CLASSA_MAX       128
+
+#define IP_CLASSB(a)        ((((u32_t)(a)) & 0xc0000000UL) == 0x80000000UL)
+#define IP_CLASSB_NET       0xffff0000
+#define IP_CLASSB_NSHIFT    16
+#define IP_CLASSB_HOST      (0xffffffff & ~IP_CLASSB_NET)
+#define IP_CLASSB_MAX       65536
+
+#define IP_CLASSC(a)        ((((u32_t)(a)) & 0xe0000000UL) == 0xc0000000UL)
+#define IP_CLASSC_NET       0xffffff00
+#define IP_CLASSC_NSHIFT    8
+#define IP_CLASSC_HOST      (0xffffffff & ~IP_CLASSC_NET)
+
+#define IP_CLASSD(a)        (((u32_t)(a) & 0xf0000000UL) == 0xe0000000UL)
+#define IP_CLASSD_NET       0xf0000000          /* These ones aren't really */
+#define IP_CLASSD_NSHIFT    28                  /*   net and host fields, but */
+#define IP_CLASSD_HOST      0x0fffffff          /*   routing needn't know. */
+#define IP_MULTICAST(a)     IP_CLASSD(a)
+
+#define IP_EXPERIMENTAL(a)  (((u32_t)(a) & 0xf0000000UL) == 0xf0000000UL)
+#define IP_BADCLASS(a)      (((u32_t)(a) & 0xf0000000UL) == 0xf0000000UL)
+
+#define IP_LOOPBACKNET      127                 /* official! */
+
+
+#if BYTE_ORDER == BIG_ENDIAN
+/** Set an IP address given by the four byte-parts */
+#define IP4_ADDR(ipaddr, a,b,c,d) \
+        (ipaddr)->addr = ((u32_t)((a) & 0xff) << 24) | \
+                         ((u32_t)((b) & 0xff) << 16) | \
+                         ((u32_t)((c) & 0xff) << 8)  | \
+                          (u32_t)((d) & 0xff)
+#else
+/** Set an IP address given by the four byte-parts.
+    Little-endian version that prevents the use of htonl. */
+#define IP4_ADDR(ipaddr, a,b,c,d) \
+        (ipaddr)->addr = ((u32_t)((d) & 0xff) << 24) | \
+                         ((u32_t)((c) & 0xff) << 16) | \
+                         ((u32_t)((b) & 0xff) << 8)  | \
+                          (u32_t)((a) & 0xff)
+#endif
+
+/** MEMCPY-like copying of IP addresses where addresses are known to be
+ * 16-bit-aligned if the port is correctly configured (so a port could define
+ * this to copying 2 u16_t's) - no NULL-pointer-checking needed. */
+#ifndef IPADDR2_COPY
+#define IPADDR2_COPY(dest, src) SMEMCPY(dest, src, sizeof(ip4_addr_t))
+#endif
+
+/** Copy IP address - faster than ip4_addr_set: no NULL check */
+#define ip4_addr_copy(dest, src) ((dest).addr = (src).addr)
+/** Safely copy one IP address to another (src may be NULL) */
+#define ip4_addr_set(dest, src) ((dest)->addr = \
+                                    ((src) == NULL ? 0 : \
+                                    (src)->addr))
+/** Set complete address to zero */
+#define ip4_addr_set_zero(ipaddr)     ((ipaddr)->addr = 0)
+/** Set address to IPADDR_ANY (no need for htonl()) */
+#define ip4_addr_set_any(ipaddr)      ((ipaddr)->addr = IPADDR_ANY)
+/** Set address to loopback address */
+#define ip4_addr_set_loopback(ipaddr) ((ipaddr)->addr = PP_HTONL(IPADDR_LOOPBACK))
+/** Check if an address is in the loopback region */
+#define ip4_addr_isloopback(ipaddr)    (((ipaddr)->addr & PP_HTONL(IP_CLASSA_NET)) == PP_HTONL(((u32_t)IP_LOOPBACKNET) << 24))
+/** Safely copy one IP address to another and change byte order
+ * from host- to network-order. */
+#define ip4_addr_set_hton(dest, src) ((dest)->addr = \
+                               ((src) == NULL ? 0:\
+                               htonl((src)->addr)))
+/** IPv4 only: set the IP address given as an u32_t */
+#define ip4_addr_set_u32(dest_ipaddr, src_u32) ((dest_ipaddr)->addr = (src_u32))
+/** IPv4 only: get the IP address as an u32_t */
+#define ip4_addr_get_u32(src_ipaddr) ((src_ipaddr)->addr)
+
+/** Get the network address by combining host address with netmask */
+#define ip4_addr_get_network(target, host, netmask) do { ((target)->addr = ((host)->addr) & ((netmask)->addr)); } while(0)
+
+/**
+ * Determine if two address are on the same network.
+ *
+ * @arg addr1 IP address 1
+ * @arg addr2 IP address 2
+ * @arg mask network identifier mask
+ * @return !0 if the network identifiers of both address match
+ */
+#define ip4_addr_netcmp(addr1, addr2, mask) (((addr1)->addr & \
+                                              (mask)->addr) == \
+                                             ((addr2)->addr & \
+                                              (mask)->addr))
+#define ip4_addr_cmp(addr1, addr2) ((addr1)->addr == (addr2)->addr)
+
+#define ip4_addr_isany_val(addr1)   ((addr1).addr == IPADDR_ANY)
+#define ip4_addr_isany(addr1) ((addr1) == NULL || ip4_addr_isany_val(*(addr1)))
+
+#define ip4_addr_isbroadcast(addr1, netif) ip4_addr_isbroadcast_u32((addr1)->addr, netif)
+u8_t ip4_addr_isbroadcast_u32(u32_t addr, const struct netif *netif);
+
+#define ip_addr_netmask_valid(netmask) ip4_addr_netmask_valid((netmask)->addr)
+u8_t ip4_addr_netmask_valid(u32_t netmask);
+
+#define ip4_addr_ismulticast(addr1) (((addr1)->addr & PP_HTONL(0xf0000000UL)) == PP_HTONL(0xe0000000UL))
+
+#define ip4_addr_islinklocal(addr1) (((addr1)->addr & PP_HTONL(0xffff0000UL)) == PP_HTONL(0xa9fe0000UL))
+
+#define ip4_addr_debug_print_parts(debug, a, b, c, d) \
+  LWIP_DEBUGF(debug, ("%" U16_F ".%" U16_F ".%" U16_F ".%" U16_F, a, b, c, d))
+#define ip4_addr_debug_print(debug, ipaddr) \
+  ip4_addr_debug_print_parts(debug, \
+                      (ipaddr) != NULL ? ip4_addr1_16(ipaddr) : 0,       \
+                      (ipaddr) != NULL ? ip4_addr2_16(ipaddr) : 0,       \
+                      (ipaddr) != NULL ? ip4_addr3_16(ipaddr) : 0,       \
+                      (ipaddr) != NULL ? ip4_addr4_16(ipaddr) : 0)
+#define ip4_addr_debug_print_val(debug, ipaddr) \
+  ip4_addr_debug_print_parts(debug, \
+                      ip4_addr1_16(&(ipaddr)),       \
+                      ip4_addr2_16(&(ipaddr)),       \
+                      ip4_addr3_16(&(ipaddr)),       \
+                      ip4_addr4_16(&(ipaddr)))
+
+/* Get one byte from the 4-byte address */
+#define ip4_addr1(ipaddr) (((const u8_t*)(&(ipaddr)->addr))[0])
+#define ip4_addr2(ipaddr) (((const u8_t*)(&(ipaddr)->addr))[1])
+#define ip4_addr3(ipaddr) (((const u8_t*)(&(ipaddr)->addr))[2])
+#define ip4_addr4(ipaddr) (((const u8_t*)(&(ipaddr)->addr))[3])
+/* These are cast to u16_t, with the intent that they are often arguments
+ * to printf using the U16_F format from cc.h. */
+#define ip4_addr1_16(ipaddr) ((u16_t)ip4_addr1(ipaddr))
+#define ip4_addr2_16(ipaddr) ((u16_t)ip4_addr2(ipaddr))
+#define ip4_addr3_16(ipaddr) ((u16_t)ip4_addr3(ipaddr))
+#define ip4_addr4_16(ipaddr) ((u16_t)ip4_addr4(ipaddr))
+
+#define IP4ADDR_STRLEN_MAX  16
+#define IPADDR_STRLEN_MAX   IP4ADDR_STRLEN_MAX
+
+/** For backwards compatibility */
+#define ip_ntoa(ipaddr)  ipaddr_ntoa(ipaddr)
+
+u32_t ipaddr_addr(const char *cp);
+int ip4addr_aton(const char *cp, ip4_addr_t *addr);
+/** returns ptr to static buffer; not reentrant! */
+char *ip4addr_ntoa(const ip4_addr_t *addr);
+char *ip4addr_ntoa_r(const ip4_addr_t *addr, char *buf, int buflen);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV4 */
+
+#endif /* LWIP_HDR_IP_ADDR_H */
diff --git a/tools/sdk/include/lwip/lwip/ip6.h b/tools/sdk/include/lwip/lwip/ip6.h
new file mode 100755
index 00000000..f1ffb6b7
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/ip6.h
@@ -0,0 +1,197 @@
+/**
+ * @file
+ *
+ * IPv6 layer.
+ */
+
+/*
+ * Copyright (c) 2010 Inico Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Ivan Delamer 
+ *
+ *
+ * Please coordinate changes and requests with Ivan Delamer
+ * 
+ */
+#ifndef LWIP_HDR_IP6_H
+#define LWIP_HDR_IP6_H
+
+#include "lwip/opt.h"
+
+#if LWIP_IPV6  /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/ip6_addr.h"
+#include "lwip/def.h"
+#include "lwip/pbuf.h"
+#include "lwip/netif.h"
+
+#include "lwip/err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define IP6_HLEN 40
+
+#define IP6_NEXTH_HOPBYHOP  0
+#define IP6_NEXTH_TCP       6
+#define IP6_NEXTH_UDP       17
+#define IP6_NEXTH_ENCAPS    41
+#define IP6_NEXTH_ROUTING   43
+#define IP6_NEXTH_FRAGMENT  44
+#define IP6_NEXTH_ICMP6     58
+#define IP6_NEXTH_NONE      59
+#define IP6_NEXTH_DESTOPTS  60
+#define IP6_NEXTH_UDPLITE   136
+
+
+/* The IPv6 header. */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip6_hdr {
+  /* version / traffic class / flow label */
+  PACK_STRUCT_FIELD(u32_t _v_tc_fl);
+  /* payload length */
+  PACK_STRUCT_FIELD(u16_t _plen);
+  /* next header */
+  PACK_STRUCT_FLD_8(u8_t _nexth);
+  /* hop limit */
+  PACK_STRUCT_FLD_8(u8_t _hoplim);
+  /* source and destination IP addresses */
+  PACK_STRUCT_FLD_S(ip6_addr_p_t src);
+  PACK_STRUCT_FLD_S(ip6_addr_p_t dest);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/* Hop-by-hop router alert option. */
+#define IP6_HBH_HLEN    8
+#define IP6_PAD1_OPTION         0
+#define IP6_PADN_ALERT_OPTION   1
+#define IP6_ROUTER_ALERT_OPTION 5
+#define IP6_ROUTER_ALERT_VALUE_MLD 0
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip6_hbh_hdr {
+  /* next header */
+  PACK_STRUCT_FLD_8(u8_t _nexth);
+  /* header length */
+  PACK_STRUCT_FLD_8(u8_t _hlen);
+  /* router alert option type */
+  PACK_STRUCT_FLD_8(u8_t _ra_opt_type);
+  /* router alert option data len */
+  PACK_STRUCT_FLD_8(u8_t _ra_opt_dlen);
+  /* router alert option data */
+  PACK_STRUCT_FIELD(u16_t _ra_opt_data);
+  /* PadN option type */
+  PACK_STRUCT_FLD_8(u8_t _padn_opt_type);
+  /* PadN option data len */
+  PACK_STRUCT_FLD_8(u8_t _padn_opt_dlen);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/* Fragment header. */
+#define IP6_FRAG_HLEN    8
+#define IP6_FRAG_OFFSET_MASK    0xfff8
+#define IP6_FRAG_MORE_FLAG      0x0001
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip6_frag_hdr {
+  /* next header */
+  PACK_STRUCT_FLD_8(u8_t _nexth);
+  /* reserved */
+  PACK_STRUCT_FLD_8(u8_t reserved);
+  /* fragment offset */
+  PACK_STRUCT_FIELD(u16_t _fragment_offset);
+  /* fragmented packet identification */
+  PACK_STRUCT_FIELD(u32_t _identification);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define IP6H_V(hdr)  ((ntohl((hdr)->_v_tc_fl) >> 28) & 0x0f)
+#define IP6H_TC(hdr) ((ntohl((hdr)->_v_tc_fl) >> 20) & 0xff)
+#define IP6H_FL(hdr) (ntohl((hdr)->_v_tc_fl) & 0x000fffff)
+#define IP6H_PLEN(hdr) (ntohs((hdr)->_plen))
+#define IP6H_NEXTH(hdr) ((hdr)->_nexth)
+#define IP6H_NEXTH_P(hdr) ((u8_t *)(hdr) + 6)
+#define IP6H_HOPLIM(hdr) ((hdr)->_hoplim)
+
+#define IP6H_VTCFL_SET(hdr, v, tc, fl) (hdr)->_v_tc_fl = (htonl((((u32_t)(v)) << 28) | (((u32_t)(tc)) << 20) | (fl)))
+#define IP6H_PLEN_SET(hdr, plen) (hdr)->_plen = htons(plen)
+#define IP6H_NEXTH_SET(hdr, nexth) (hdr)->_nexth = (nexth)
+#define IP6H_HOPLIM_SET(hdr, hl) (hdr)->_hoplim = (u8_t)(hl)
+
+
+struct netif *ip6_route(const ip6_addr_t *src, const ip6_addr_t *dest);
+const ip_addr_t *ip6_select_source_address(struct netif *netif, const ip6_addr_t * dest);
+err_t         ip6_input(struct pbuf *p, struct netif *inp);
+err_t         ip6_output(struct pbuf *p, const ip6_addr_t *src, const ip6_addr_t *dest,
+                         u8_t hl, u8_t tc, u8_t nexth);
+err_t         ip6_output_if(struct pbuf *p, const ip6_addr_t *src, const ip6_addr_t *dest,
+                            u8_t hl, u8_t tc, u8_t nexth, struct netif *netif);
+err_t         ip6_output_if_src(struct pbuf *p, const ip6_addr_t *src, const ip6_addr_t *dest,
+                            u8_t hl, u8_t tc, u8_t nexth, struct netif *netif);
+#if LWIP_NETIF_HWADDRHINT
+err_t         ip6_output_hinted(struct pbuf *p, const ip6_addr_t *src, const ip6_addr_t *dest,
+                                u8_t hl, u8_t tc, u8_t nexth, u8_t *addr_hint);
+#endif /* LWIP_NETIF_HWADDRHINT */
+#if LWIP_IPV6_MLD
+err_t         ip6_options_add_hbh_ra(struct pbuf * p, u8_t nexth, u8_t value);
+#endif /* LWIP_IPV6_MLD */
+
+#define ip6_netif_get_local_ip(netif, dest) (((netif) != NULL) ? \
+  ip6_select_source_address(netif, dest) : NULL)
+
+#if IP6_DEBUG
+void ip6_debug_print(struct pbuf *p);
+#else
+#define ip6_debug_print(p)
+#endif /* IP6_DEBUG */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV6 */
+
+#endif /* LWIP_HDR_IP6_H */
diff --git a/tools/sdk/include/lwip/lwip/ip6_addr.h b/tools/sdk/include/lwip/lwip/ip6_addr.h
new file mode 100755
index 00000000..a75d8948
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/ip6_addr.h
@@ -0,0 +1,301 @@
+/**
+ * @file
+ *
+ * IPv6 addresses.
+ */
+
+/*
+ * Copyright (c) 2010 Inico Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Ivan Delamer 
+ *
+ * Structs and macros for handling IPv6 addresses.
+ *
+ * Please coordinate changes and requests with Ivan Delamer
+ * 
+ */
+#ifndef LWIP_HDR_IP6_ADDR_H
+#define LWIP_HDR_IP6_ADDR_H
+
+#include "lwip/opt.h"
+
+#if LWIP_IPV6  /* don't build if not configured for use in lwipopts.h */
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* This is the aligned version of ip6_addr_t,
+   used as local variable, on the stack, etc. */
+struct ip6_addr {
+  u32_t addr[4];
+};
+
+/* This is the packed version of ip6_addr_t,
+   used in network headers that are itself packed */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip6_addr_packed {
+  PACK_STRUCT_FIELD(u32_t addr[4]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+typedef struct ip6_addr ip6_addr_t;
+typedef struct ip6_addr_packed ip6_addr_p_t;
+
+
+#if BYTE_ORDER == BIG_ENDIAN
+/** Set an IPv6 partial address given by byte-parts. */
+#define IP6_ADDR_PART(ip6addr, index, a,b,c,d) \
+  (ip6addr)->addr[index] = ((u32_t)((a) & 0xff) << 24) | \
+                           ((u32_t)((b) & 0xff) << 16) | \
+                           ((u32_t)((c) & 0xff) << 8)  | \
+                            (u32_t)((d) & 0xff)
+#else
+/** Set an IPv6 partial address given by byte-parts.
+Little-endian version, stored in network order (no htonl). */
+#define IP6_ADDR_PART(ip6addr, index, a,b,c,d) \
+  (ip6addr)->addr[index] = ((u32_t)((d) & 0xff) << 24) | \
+                           ((u32_t)((c) & 0xff) << 16) | \
+                           ((u32_t)((b) & 0xff) << 8)  | \
+                            (u32_t)((a) & 0xff)
+#endif
+
+/** Set a full IPv6 address by passing the 4 u32_t indices in network byte order
+    (use PP_HTONL() for constants) */
+#define IP6_ADDR(ip6addr, idx0, idx1, idx2, idx3) do { \
+  (ip6addr)->addr[0] = idx0; \
+  (ip6addr)->addr[1] = idx1; \
+  (ip6addr)->addr[2] = idx2; \
+  (ip6addr)->addr[3] = idx3; } while(0)
+
+/** Access address in 16-bit block */
+#define IP6_ADDR_BLOCK1(ip6addr) ((u16_t)(htonl((ip6addr)->addr[0]) >> 16) & 0xffff)
+#define IP6_ADDR_BLOCK2(ip6addr) ((u16_t)(htonl((ip6addr)->addr[0])) & 0xffff)
+#define IP6_ADDR_BLOCK3(ip6addr) ((u16_t)(htonl((ip6addr)->addr[1]) >> 16) & 0xffff)
+#define IP6_ADDR_BLOCK4(ip6addr) ((u16_t)(htonl((ip6addr)->addr[1])) & 0xffff)
+#define IP6_ADDR_BLOCK5(ip6addr) ((u16_t)(htonl((ip6addr)->addr[2]) >> 16) & 0xffff)
+#define IP6_ADDR_BLOCK6(ip6addr) ((u16_t)(htonl((ip6addr)->addr[2])) & 0xffff)
+#define IP6_ADDR_BLOCK7(ip6addr) ((u16_t)(htonl((ip6addr)->addr[3]) >> 16) & 0xffff)
+#define IP6_ADDR_BLOCK8(ip6addr) ((u16_t)(htonl((ip6addr)->addr[3])) & 0xffff)
+
+/** Copy IPv6 address - faster than ip6_addr_set: no NULL check */
+#define ip6_addr_copy(dest, src) do{(dest).addr[0] = (src).addr[0]; \
+                                    (dest).addr[1] = (src).addr[1]; \
+                                    (dest).addr[2] = (src).addr[2]; \
+                                    (dest).addr[3] = (src).addr[3];}while(0)
+/** Safely copy one IPv6 address to another (src may be NULL) */
+#define ip6_addr_set(dest, src) do{(dest)->addr[0] = (src) == NULL ? 0 : (src)->addr[0]; \
+                                   (dest)->addr[1] = (src) == NULL ? 0 : (src)->addr[1]; \
+                                   (dest)->addr[2] = (src) == NULL ? 0 : (src)->addr[2]; \
+                                   (dest)->addr[3] = (src) == NULL ? 0 : (src)->addr[3];}while(0)
+
+/** Set complete address to zero */
+#define ip6_addr_set_zero(ip6addr)    do{(ip6addr)->addr[0] = 0; \
+                                         (ip6addr)->addr[1] = 0; \
+                                         (ip6addr)->addr[2] = 0; \
+                                         (ip6addr)->addr[3] = 0;}while(0)
+
+/** Set address to ipv6 'any' (no need for htonl()) */
+#define ip6_addr_set_any(ip6addr)       ip6_addr_set_zero(ip6addr)
+/** Set address to ipv6 loopback address */
+#define ip6_addr_set_loopback(ip6addr) do{(ip6addr)->addr[0] = 0; \
+                                          (ip6addr)->addr[1] = 0; \
+                                          (ip6addr)->addr[2] = 0; \
+                                          (ip6addr)->addr[3] = PP_HTONL(0x00000001UL);}while(0)
+/** Safely copy one IPv6 address to another and change byte order
+ * from host- to network-order. */
+#define ip6_addr_set_hton(dest, src) do{(dest)->addr[0] = (src) == NULL ? 0 : htonl((src)->addr[0]); \
+                                        (dest)->addr[1] = (src) == NULL ? 0 : htonl((src)->addr[1]); \
+                                        (dest)->addr[2] = (src) == NULL ? 0 : htonl((src)->addr[2]); \
+                                        (dest)->addr[3] = (src) == NULL ? 0 : htonl((src)->addr[3]);}while(0)
+
+
+/**
+ * Determine if two IPv6 address are on the same network.
+ *
+ * @arg addr1 IPv6 address 1
+ * @arg addr2 IPv6 address 2
+ * @return !0 if the network identifiers of both address match
+ */
+#define ip6_addr_netcmp(addr1, addr2) (((addr1)->addr[0] == (addr2)->addr[0]) && \
+                                       ((addr1)->addr[1] == (addr2)->addr[1]))
+
+#define ip6_addr_cmp(addr1, addr2) (((addr1)->addr[0] == (addr2)->addr[0]) && \
+                                    ((addr1)->addr[1] == (addr2)->addr[1]) && \
+                                    ((addr1)->addr[2] == (addr2)->addr[2]) && \
+                                    ((addr1)->addr[3] == (addr2)->addr[3]))
+
+#define ip6_get_subnet_id(ip6addr)   (htonl((ip6addr)->addr[2]) & 0x0000ffffUL)
+
+#define ip6_addr_isany_val(ip6addr) (((ip6addr).addr[0] == 0) && \
+                                     ((ip6addr).addr[1] == 0) && \
+                                     ((ip6addr).addr[2] == 0) && \
+                                     ((ip6addr).addr[3] == 0))
+#define ip6_addr_isany(ip6addr) (((ip6addr) == NULL) || ip6_addr_isany_val(*(ip6addr)))
+
+#define ip6_addr_isloopback(ip6addr) (((ip6addr)->addr[0] == 0UL) && \
+                                      ((ip6addr)->addr[1] == 0UL) && \
+                                      ((ip6addr)->addr[2] == 0UL) && \
+                                      ((ip6addr)->addr[3] == PP_HTONL(0x00000001UL)))
+
+#define ip6_addr_isglobal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xe0000000UL)) == PP_HTONL(0x20000000UL))
+
+#define ip6_addr_islinklocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xffc00000UL)) == PP_HTONL(0xfe800000UL))
+
+#define ip6_addr_issitelocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xffc00000UL)) == PP_HTONL(0xfec00000UL))
+
+#define ip6_addr_isuniquelocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xfe000000UL)) == PP_HTONL(0xfc000000UL))
+
+#define ip6_addr_ismulticast(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xff000000UL)) == PP_HTONL(0xff000000UL))
+#define ip6_addr_multicast_transient_flag(ip6addr)  ((ip6addr)->addr[0] & PP_HTONL(0x00100000UL))
+#define ip6_addr_multicast_prefix_flag(ip6addr)     ((ip6addr)->addr[0] & PP_HTONL(0x00200000UL))
+#define ip6_addr_multicast_rendezvous_flag(ip6addr) ((ip6addr)->addr[0] & PP_HTONL(0x00400000UL))
+#define ip6_addr_multicast_scope(ip6addr) ((htonl((ip6addr)->addr[0]) >> 16) & 0xf)
+#define IP6_MULTICAST_SCOPE_RESERVED            0x0
+#define IP6_MULTICAST_SCOPE_RESERVED0           0x0
+#define IP6_MULTICAST_SCOPE_INTERFACE_LOCAL     0x1
+#define IP6_MULTICAST_SCOPE_LINK_LOCAL          0x2
+#define IP6_MULTICAST_SCOPE_RESERVED3           0x3
+#define IP6_MULTICAST_SCOPE_ADMIN_LOCAL         0x4
+#define IP6_MULTICAST_SCOPE_SITE_LOCAL          0x5
+#define IP6_MULTICAST_SCOPE_ORGANIZATION_LOCAL  0x8
+#define IP6_MULTICAST_SCOPE_GLOBAL              0xe
+#define IP6_MULTICAST_SCOPE_RESERVEDF           0xf
+#define ip6_addr_ismulticast_iflocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xff8f0000UL)) == PP_HTONL(0xff010000UL))
+#define ip6_addr_ismulticast_linklocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xff8f0000UL)) == PP_HTONL(0xff020000UL))
+#define ip6_addr_ismulticast_adminlocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xff8f0000UL)) == PP_HTONL(0xff040000UL))
+#define ip6_addr_ismulticast_sitelocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xff8f0000UL)) == PP_HTONL(0xff050000UL))
+#define ip6_addr_ismulticast_orglocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xff8f0000UL)) == PP_HTONL(0xff080000UL))
+#define ip6_addr_ismulticast_global(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xff8f0000UL)) == PP_HTONL(0xff0e0000UL))
+
+/* TODO define get/set for well-know multicast addresses, e.g. ff02::1 */
+#define ip6_addr_isallnodes_iflocal(ip6addr) (((ip6addr)->addr[0] == PP_HTONL(0xff010000UL)) && \
+    ((ip6addr)->addr[1] == 0UL) && \
+    ((ip6addr)->addr[2] == 0UL) && \
+    ((ip6addr)->addr[3] == PP_HTONL(0x00000001UL)))
+
+#define ip6_addr_isallnodes_linklocal(ip6addr) (((ip6addr)->addr[0] == PP_HTONL(0xff020000UL)) && \
+    ((ip6addr)->addr[1] == 0UL) && \
+    ((ip6addr)->addr[2] == 0UL) && \
+    ((ip6addr)->addr[3] == PP_HTONL(0x00000001UL)))
+#define ip6_addr_set_allnodes_linklocal(ip6addr) do{(ip6addr)->addr[0] = PP_HTONL(0xff020000UL); \
+                (ip6addr)->addr[1] = 0; \
+                (ip6addr)->addr[2] = 0; \
+                (ip6addr)->addr[3] = PP_HTONL(0x00000001UL);}while(0)
+
+#define ip6_addr_isallrouters_linklocal(ip6addr) (((ip6addr)->addr[0] == PP_HTONL(0xff020000UL)) && \
+    ((ip6addr)->addr[1] == 0UL) && \
+    ((ip6addr)->addr[2] == 0UL) && \
+    ((ip6addr)->addr[3] == PP_HTONL(0x00000002UL)))
+#define ip6_addr_set_allrouters_linklocal(ip6addr) do{(ip6addr)->addr[0] = PP_HTONL(0xff020000UL); \
+                (ip6addr)->addr[1] = 0; \
+                (ip6addr)->addr[2] = 0; \
+                (ip6addr)->addr[3] = PP_HTONL(0x00000002UL);}while(0)
+
+#define ip6_addr_issolicitednode(ip6addr) ( ((ip6addr)->addr[0] == PP_HTONL(0xff020000UL)) && \
+        ((ip6addr)->addr[2] == PP_HTONL(0x00000001UL)) && \
+        (((ip6addr)->addr[3] & PP_HTONL(0xff000000UL)) == PP_HTONL(0xff000000UL)) )
+
+#define ip6_addr_set_solicitednode(ip6addr, if_id) do{(ip6addr)->addr[0] = PP_HTONL(0xff020000UL); \
+                (ip6addr)->addr[1] = 0; \
+                (ip6addr)->addr[2] = PP_HTONL(0x00000001UL); \
+                (ip6addr)->addr[3] = (PP_HTONL(0xff000000UL) | (if_id));}while(0)
+
+#define ip6_addr_cmp_solicitednode(ip6addr, sn_addr) (((ip6addr)->addr[0] == PP_HTONL(0xff020000UL)) && \
+                                    ((ip6addr)->addr[1] == 0) && \
+                                    ((ip6addr)->addr[2] == PP_HTONL(0x00000001UL)) && \
+                                    ((ip6addr)->addr[3] == (PP_HTONL(0xff000000UL) | (sn_addr)->addr[3])))
+
+/* IPv6 address states. */
+#define IP6_ADDR_INVALID      0x00
+#define IP6_ADDR_TENTATIVE    0x08
+#define IP6_ADDR_TENTATIVE_1  0x09 /* 1 probe sent */
+#define IP6_ADDR_TENTATIVE_2  0x0a /* 2 probes sent */
+#define IP6_ADDR_TENTATIVE_3  0x0b /* 3 probes sent */
+#define IP6_ADDR_TENTATIVE_4  0x0c /* 4 probes sent */
+#define IP6_ADDR_TENTATIVE_5  0x0d /* 5 probes sent */
+#define IP6_ADDR_TENTATIVE_6  0x0e /* 6 probes sent */
+#define IP6_ADDR_TENTATIVE_7  0x0f /* 7 probes sent */
+#define IP6_ADDR_VALID        0x10
+#define IP6_ADDR_PREFERRED    0x30
+#define IP6_ADDR_DEPRECATED   0x50
+
+#define ip6_addr_isinvalid(addr_state) (addr_state == IP6_ADDR_INVALID)
+#define ip6_addr_istentative(addr_state) (addr_state & IP6_ADDR_TENTATIVE)
+#define ip6_addr_isvalid(addr_state) (addr_state & IP6_ADDR_VALID) /* Include valid, preferred, and deprecated. */
+#define ip6_addr_ispreferred(addr_state) (addr_state == IP6_ADDR_PREFERRED)
+#define ip6_addr_isdeprecated(addr_state) (addr_state == IP6_ADDR_DEPRECATED)
+
+#define ip6_addr_debug_print_parts(debug, a, b, c, d, e, f, g, h) \
+  LWIP_DEBUGF(debug, ("%" X16_F ":%" X16_F ":%" X16_F ":%" X16_F ":%" X16_F ":%" X16_F ":%" X16_F ":%" X16_F, \
+                      a, b, c, d, e, f, g, h))
+#define ip6_addr_debug_print(debug, ipaddr) \
+  ip6_addr_debug_print_parts(debug, \
+                      (ipaddr) != NULL ? IP6_ADDR_BLOCK1(ipaddr) : 0,    \
+                      (ipaddr) != NULL ? IP6_ADDR_BLOCK2(ipaddr) : 0,    \
+                      (ipaddr) != NULL ? IP6_ADDR_BLOCK3(ipaddr) : 0,    \
+                      (ipaddr) != NULL ? IP6_ADDR_BLOCK4(ipaddr) : 0,    \
+                      (ipaddr) != NULL ? IP6_ADDR_BLOCK5(ipaddr) : 0,    \
+                      (ipaddr) != NULL ? IP6_ADDR_BLOCK6(ipaddr) : 0,    \
+                      (ipaddr) != NULL ? IP6_ADDR_BLOCK7(ipaddr) : 0,    \
+                      (ipaddr) != NULL ? IP6_ADDR_BLOCK8(ipaddr) : 0)
+#define ip6_addr_debug_print_val(debug, ipaddr) \
+  ip6_addr_debug_print_parts(debug, \
+                      IP6_ADDR_BLOCK1(&(ipaddr)),    \
+                      IP6_ADDR_BLOCK2(&(ipaddr)),    \
+                      IP6_ADDR_BLOCK3(&(ipaddr)),    \
+                      IP6_ADDR_BLOCK4(&(ipaddr)),    \
+                      IP6_ADDR_BLOCK5(&(ipaddr)),    \
+                      IP6_ADDR_BLOCK6(&(ipaddr)),    \
+                      IP6_ADDR_BLOCK7(&(ipaddr)),    \
+                      IP6_ADDR_BLOCK8(&(ipaddr)))
+
+#define IP6ADDR_STRLEN_MAX    46
+
+int ip6addr_aton(const char *cp, ip6_addr_t *addr);
+/** returns ptr to static buffer; not reentrant! */
+char *ip6addr_ntoa(const ip6_addr_t *addr);
+char *ip6addr_ntoa_r(const ip6_addr_t *addr, char *buf, int buflen);
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV6 */
+
+#endif /* LWIP_HDR_IP6_ADDR_H */
diff --git a/tools/sdk/include/lwip/lwip/ip6_frag.h b/tools/sdk/include/lwip/lwip/ip6_frag.h
new file mode 100755
index 00000000..16336e58
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/ip6_frag.h
@@ -0,0 +1,120 @@
+/**
+ * @file
+ *
+ * IPv6 fragmentation and reassembly.
+ */
+
+/*
+ * Copyright (c) 2010 Inico Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Ivan Delamer 
+ *
+ *
+ * Please coordinate changes and requests with Ivan Delamer
+ * 
+ */
+#ifndef LWIP_HDR_IP6_FRAG_H
+#define LWIP_HDR_IP6_FRAG_H
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip6_addr.h"
+#include "lwip/ip6.h"
+#include "lwip/netif.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if LWIP_IPV6 && LWIP_IPV6_REASS  /* don't build if not configured for use in lwipopts.h */
+
+/** IP6_FRAG_COPYHEADER==1: for platforms where sizeof(void*) > 4, this needs to
+ * be enabled (to not overwrite part of the data). When enabled, the IPv6 header
+ * is copied instead of referencing it, which gives more room for struct ip6_reass_helper */
+#ifndef IPV6_FRAG_COPYHEADER
+#define IPV6_FRAG_COPYHEADER   0
+#endif
+
+/* The IPv6 reassembly timer interval in milliseconds. */
+#define IP6_REASS_TMR_INTERVAL 1000
+
+/* Copy the complete header of the first fragment to struct ip6_reassdata
+   or just point to its original location in the first pbuf? */
+#if IPV6_FRAG_COPYHEADER
+#define IPV6_FRAG_HDRPTR
+#define IPV6_FRAG_HDRREF(hdr) (&(hdr))
+#else /* IPV6_FRAG_COPYHEADER */
+#define IPV6_FRAG_HDRPTR *
+#define IPV6_FRAG_HDRREF(hdr) (hdr)
+#endif /* IPV6_FRAG_COPYHEADER */
+
+/* IPv6 reassembly helper struct.
+ * This is exported because memp needs to know the size.
+ */
+struct ip6_reassdata {
+  struct ip6_reassdata *next;
+  struct pbuf *p;
+  struct ip6_hdr IPV6_FRAG_HDRPTR iphdr;
+  u32_t identification;
+  u16_t datagram_len;
+  u8_t nexth;
+  u8_t timer;
+};
+
+#define ip6_reass_init() /* Compatibility define */
+void ip6_reass_tmr(void);
+struct pbuf * ip6_reass(struct pbuf *p);
+
+#endif /* LWIP_IPV6 && LWIP_IPV6_REASS */
+
+#if LWIP_IPV6 && LWIP_IPV6_FRAG  /* don't build if not configured for use in lwipopts.h */
+
+/** A custom pbuf that holds a reference to another pbuf, which is freed
+ * when this custom pbuf is freed. This is used to create a custom PBUF_REF
+ * that points into the original pbuf. */
+#ifndef LWIP_PBUF_CUSTOM_REF_DEFINED
+#define LWIP_PBUF_CUSTOM_REF_DEFINED
+struct pbuf_custom_ref {
+  /** 'base class' */
+  struct pbuf_custom pc;
+  /** pointer to the original pbuf that is referenced */
+  struct pbuf *original;
+};
+#endif /* LWIP_PBUF_CUSTOM_REF_DEFINED */
+
+err_t ip6_frag(struct pbuf *p, struct netif *netif, const ip6_addr_t *dest);
+
+#endif /* LWIP_IPV6 && LWIP_IPV6_FRAG */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_IP6_FRAG_H */
diff --git a/tools/sdk/include/lwip/lwip/ip_addr.h b/tools/sdk/include/lwip/lwip/ip_addr.h
new file mode 100755
index 00000000..1e1ffb3f
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/ip_addr.h
@@ -0,0 +1,291 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef LWIP_HDR_IP_ADDR_H__
+#define LWIP_HDR_IP_ADDR_H__
+
+#include "lwip/opt.h"
+#include "lwip/def.h"
+
+#include "lwip/ip4_addr.h"
+#include "lwip/ip6_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** These are the values for ip_addr_t.type */
+#define IPADDR_TYPE_V4                0U
+#define IPADDR_TYPE_V6                6U
+#define IPADDR_TYPE_ANY               46U
+
+#if LWIP_IPV4 && LWIP_IPV6
+/** A union struct for both IP version's addresses.
+ * ATTENTION: watch out for its size when adding IPv6 address scope!
+ */
+typedef struct _ip_addr {
+  union {
+    ip6_addr_t ip6;
+    ip4_addr_t ip4;
+  } u_addr;
+  u8_t type;
+} ip_addr_t;
+
+extern const ip_addr_t ip_addr_any_type;
+
+#define IPADDR4_INIT(u32val)          { { { { u32val, 0ul, 0ul, 0ul } } }, IPADDR_TYPE_V4 }
+#define IPADDR6_INIT(a, b, c, d)      { { { { a, b, c, d } } }, IPADDR_TYPE_V6 }
+
+#define IP_IS_ANY_TYPE_VAL(ipaddr)    (IP_GET_TYPE(&ipaddr) == IPADDR_TYPE_ANY)
+#define IPADDR_ANY_TYPE_INIT          { { { { 0ul, 0ul, 0ul, 0ul } } }, IPADDR_TYPE_ANY }
+
+#define IP_IS_V6_VAL(ipaddr)          (IP_GET_TYPE(&ipaddr) == IPADDR_TYPE_V6)
+#define IP_IS_V6(ipaddr)              (((ipaddr) != NULL) && IP_IS_V6_VAL(*(ipaddr)))
+#define IP_SET_TYPE_VAL(ipaddr, iptype) do { (ipaddr).type = (iptype); }while(0)
+#define IP_SET_TYPE(ipaddr, iptype)     do { if((ipaddr) != NULL) { IP_SET_TYPE_VAL(*(ipaddr), iptype); }}while(0)
+#define IP_GET_TYPE(ipaddr)           ((ipaddr)->type)
+
+#define IP_ADDR_PCB_VERSION_MATCH_EXACT(pcb, ipaddr) (IP_GET_TYPE(&pcb->local_ip) == IP_GET_TYPE(ipaddr))
+#define IP_ADDR_PCB_VERSION_MATCH(pcb, ipaddr) (IP_IS_ANY_TYPE_VAL(pcb->local_ip) || IP_ADDR_PCB_VERSION_MATCH_EXACT(pcb, ipaddr))
+
+/* Convert generic ip address to specific protocol version */
+#define ip_2_ip6(ipaddr)   (&((ipaddr)->u_addr.ip6))
+#define ip_2_ip4(ipaddr)   (&((ipaddr)->u_addr.ip4))
+
+#define IP_ADDR4(ipaddr,a,b,c,d)      do { IP4_ADDR(ip_2_ip4(ipaddr),a,b,c,d); \
+                                           IP_SET_TYPE_VAL(*(ipaddr), IPADDR_TYPE_V4); } while(0)
+#define IP_ADDR6(ipaddr,i0,i1,i2,i3)  do { IP6_ADDR(ip_2_ip6(ipaddr),i0,i1,i2,i3); \
+                                           IP_SET_TYPE_VAL(*(ipaddr), IPADDR_TYPE_V6); } while(0)
+
+#define ip_addr_copy(dest, src)      do{ IP_SET_TYPE_VAL(dest, IP_GET_TYPE(&src)); if(IP_IS_V6_VAL(src)){ \
+  ip6_addr_copy(*ip_2_ip6(&(dest)), *ip_2_ip6(&(src))); }else{ \
+  ip4_addr_copy(*ip_2_ip4(&(dest)), *ip_2_ip4(&(src))); }}while(0)
+#define ip_addr_copy_from_ip6(dest, src)      do{ \
+  ip6_addr_copy(*ip_2_ip6(&(dest)), src); IP_SET_TYPE_VAL(dest, IPADDR_TYPE_V6); }while(0)
+#define ip_addr_copy_from_ip4(dest, src)      do{ \
+  ip4_addr_copy(*ip_2_ip4(&(dest)), src); IP_SET_TYPE_VAL(dest, IPADDR_TYPE_V4); }while(0)
+#define ip_addr_set_ip4_u32(ipaddr, val)  do{if(ipaddr){ip4_addr_set_u32(ip_2_ip4(ipaddr), val); \
+  IP_SET_TYPE(ipaddr, IPADDR_TYPE_V4); }}while(0)
+#define ip_addr_get_ip4_u32(ipaddr)  (((ipaddr) && !IP_IS_V6(ipaddr)) ? \
+  ip4_addr_get_u32(ip_2_ip4(ipaddr)) : 0)
+
+#define ip_addr_set(dest, src) do{ IP_SET_TYPE(dest, IP_GET_TYPE(src)); if(IP_IS_V6(src)){ \
+  ip6_addr_set(ip_2_ip6(dest), ip_2_ip6(src)); }else{ \
+  ip4_addr_set(ip_2_ip4(dest), ip_2_ip4(src)); }}while(0)
+  
+#define ip_addr_set_ipaddr(dest, src) ip_addr_set(dest, src)
+#define ip_addr_set_zero(ipaddr)     do{ \
+  ip6_addr_set_zero(ip_2_ip6(ipaddr)); IP_SET_TYPE(ipaddr, 0); }while(0)
+#define ip_addr_set_zero_ip4(ipaddr)     do{ \
+  ip6_addr_set_zero(ip_2_ip6(ipaddr)); IP_SET_TYPE(ipaddr, IPADDR_TYPE_V4); }while(0)
+#define ip_addr_set_zero_ip6(ipaddr)     do{ \
+  ip6_addr_set_zero(ip_2_ip6(ipaddr)); IP_SET_TYPE(ipaddr, IPADDR_TYPE_V6); }while(0)
+#define ip_addr_set_any(is_ipv6, ipaddr)      do{if(is_ipv6){ \
+  ip6_addr_set_any(ip_2_ip6(ipaddr)); IP_SET_TYPE(ipaddr, IPADDR_TYPE_V6); }else{ \
+  ip4_addr_set_any(ip_2_ip4(ipaddr)); IP_SET_TYPE(ipaddr, IPADDR_TYPE_V4); }}while(0)
+#define ip_addr_set_loopback(is_ipv6, ipaddr) do{if(is_ipv6){ \
+  ip6_addr_set_loopback(ip_2_ip6(ipaddr)); IP_SET_TYPE(ipaddr, IPADDR_TYPE_V6); }else{ \
+  ip4_addr_set_loopback(ip_2_ip4(ipaddr)); IP_SET_TYPE(ipaddr, IPADDR_TYPE_V4); }}while(0)
+#define ip_addr_set_hton(dest, src)  do{if(IP_IS_V6(src)){ \
+  ip6_addr_set_hton(ip_2_ip6(ipaddr), (src)); IP_SET_TYPE(dest, IPADDR_TYPE_V6); }else{ \
+  ip4_addr_set_hton(ip_2_ip4(ipaddr), (src)); IP_SET_TYPE(dest, IPADDR_TYPE_V4); }}while(0)
+#define ip_addr_get_network(target, host, netmask) do{if(IP_IS_V6(host)){ \
+  ip4_addr_set_zero(ip_2_ip4(target)); IP_SET_TYPE(target, IPADDR_TYPE_V6); } else { \
+  ip4_addr_get_network(ip_2_ip4(target), ip_2_ip4(host), ip_2_ip4(netmask)); IP_SET_TYPE(target, IPADDR_TYPE_V4); }}while(0)
+#define ip_addr_netcmp(addr1, addr2, mask) ((IP_IS_V6(addr1) && IP_IS_V6(addr2)) ? \
+  0 : \
+  ip4_addr_netcmp(ip_2_ip4(addr1), ip_2_ip4(addr2), mask))
+#define ip_addr_cmp(addr1, addr2)    ((IP_GET_TYPE(addr1) != IP_GET_TYPE(addr2)) ? 0 : (IP_IS_V6_VAL(*(addr1)) ? \
+  ip6_addr_cmp(ip_2_ip6(addr1), ip_2_ip6(addr2)) : \
+  ip4_addr_cmp(ip_2_ip4(addr1), ip_2_ip4(addr2))))
+#define ip_addr_isany(ipaddr)        ((IP_IS_V6(ipaddr)) ? \
+  ip6_addr_isany(ip_2_ip6(ipaddr)) : \
+  ip4_addr_isany(ip_2_ip4(ipaddr)))
+#define ip_addr_isany_val(ipaddr)        ((IP_IS_V6_VAL(ipaddr)) ? \
+  ip6_addr_isany_val(*ip_2_ip6(&(ipaddr))) : \
+  ip4_addr_isany_val(*ip_2_ip4(&(ipaddr))))
+#define ip_addr_isbroadcast(ipaddr, netif) ((IP_IS_V6(ipaddr)) ? \
+  0 : \
+  ip4_addr_isbroadcast(ip_2_ip4(ipaddr), netif))
+#define ip_addr_ismulticast(ipaddr)  ((IP_IS_V6(ipaddr)) ? \
+  ip6_addr_ismulticast(ip_2_ip6(ipaddr)) : \
+  ip4_addr_ismulticast(ip_2_ip4(ipaddr)))
+#define ip_addr_isloopback(ipaddr)  ((IP_IS_V6(ipaddr)) ? \
+  ip6_addr_isloopback(ip_2_ip6(ipaddr)) : \
+  ip4_addr_isloopback(ip_2_ip4(ipaddr)))
+#define ip_addr_islinklocal(ipaddr)  ((IP_IS_V6(ipaddr)) ? \
+  ip6_addr_islinklocal(ip_2_ip6(ipaddr)) : \
+  ip4_addr_islinklocal(ip_2_ip4(ipaddr)))
+#define ip_addr_debug_print(debug, ipaddr) do { if(IP_IS_V6(ipaddr)) { \
+  ip6_addr_debug_print(debug, ip_2_ip6(ipaddr)); } else { \
+  ip4_addr_debug_print(debug, ip_2_ip4(ipaddr)); }}while(0)
+#define ip_addr_debug_print_val(debug, ipaddr) do { if(IP_IS_V6_VAL(ipaddr)) { \
+  ip6_addr_debug_print_val(debug, *ip_2_ip6(&(ipaddr))); } else { \
+  ip4_addr_debug_print_val(debug, *ip_2_ip4(&(ipaddr))); }}while(0)
+#define ipaddr_ntoa(addr)   (((addr) == NULL) ? "NULL" : \
+  ((IP_IS_V6(addr)) ? ip6addr_ntoa(ip_2_ip6(addr)) : ip4addr_ntoa(ip_2_ip4(addr))))
+#define ipaddr_ntoa_r(addr, buf, buflen)   (((addr) == NULL) ? "NULL" : \
+  ((IP_IS_V6(addr)) ? ip6addr_ntoa_r(ip_2_ip6(addr), buf, buflen) : ip4addr_ntoa_r(ip_2_ip4(addr), buf, buflen)))
+int ipaddr_aton(const char *cp, ip_addr_t *addr);
+
+#else /* LWIP_IPV4 && LWIP_IPV6 */
+
+#define IP_ADDR_PCB_VERSION_MATCH(addr, pcb)         1
+#define IP_ADDR_PCB_VERSION_MATCH_EXACT(pcb, ipaddr) 1
+
+#if LWIP_IPV4
+
+typedef ip4_addr_t ip_addr_t;
+#define IPADDR4_INIT(u32val)                    { u32val }
+#define IP_IS_V6_VAL(ipaddr)                    0
+#define IP_IS_V6(ipaddr)                        0
+#define IP_IS_ANY_TYPE_VAL(ipaddr)              0
+#define IP_SET_TYPE_VAL(ipaddr, iptype)
+#define IP_SET_TYPE(ipaddr, iptype)
+#define IP_GET_TYPE(ipaddr)                     IPADDR_TYPE_V4
+#define ip_2_ip4(ipaddr)                        (ipaddr)
+#define IP_ADDR4(ipaddr,a,b,c,d)                IP4_ADDR(ipaddr,a,b,c,d)
+
+#define ip_addr_copy(dest, src)                 ip4_addr_copy(dest, src)
+#define ip_addr_copy_from_ip4(dest, src)        ip4_addr_copy(dest, src)
+#define ip_addr_set_ip4_u32(ipaddr, val)        ip4_addr_set_u32(ip_2_ip4(ipaddr), val)
+#define ip_addr_get_ip4_u32(ipaddr)             ip4_addr_get_u32(ip_2_ip4(ipaddr))
+#define ip_addr_set(dest, src)                  ip4_addr_set(dest, src)
+#define ip_addr_set_ipaddr(dest, src)           ip4_addr_set(dest, src)
+#define ip_addr_set_zero(ipaddr)                ip4_addr_set_zero(ipaddr)
+#define ip_addr_set_zero_ip4(ipaddr)            ip4_addr_set_zero(ipaddr)
+#define ip_addr_set_any(is_ipv6, ipaddr)        ip4_addr_set_any(ipaddr)
+#define ip_addr_set_loopback(is_ipv6, ipaddr)   ip4_addr_set_loopback(ipaddr)
+#define ip_addr_set_hton(dest, src)             ip4_addr_set_hton(dest, src)
+#define ip_addr_get_network(target, host, mask) ip4_addr_get_network(target, host, mask)
+#define ip_addr_netcmp(addr1, addr2, mask)      ip4_addr_netcmp(addr1, addr2, mask)
+#define ip_addr_cmp(addr1, addr2)               ip4_addr_cmp(addr1, addr2)
+#define ip_addr_isany(ipaddr)                   ip4_addr_isany(ipaddr)
+#define ip_addr_isany_val(ipaddr)               ip4_addr_isany_val(ipaddr)
+#define ip_addr_isloopback(ipaddr)              ip4_addr_isloopback(ipaddr)
+#define ip_addr_islinklocal(ipaddr)             ip4_addr_islinklocal(ipaddr)
+#define ip_addr_isbroadcast(addr, netif)        ip4_addr_isbroadcast(addr, netif)
+#define ip_addr_ismulticast(ipaddr)             ip4_addr_ismulticast(ipaddr)
+#define ip_addr_debug_print(debug, ipaddr)      ip4_addr_debug_print(debug, ipaddr)
+#define ip_addr_debug_print_val(debug, ipaddr)  ip4_addr_debug_print_val(debug, ipaddr)
+#define ipaddr_ntoa(ipaddr)                     ip4addr_ntoa(ipaddr)
+#define ipaddr_ntoa_r(ipaddr, buf, buflen)      ip4addr_ntoa_r(ipaddr, buf, buflen)
+#define ipaddr_aton(cp, addr)                   ip4addr_aton(cp, addr)
+
+#else /* LWIP_IPV4 */
+
+typedef ip6_addr_t ip_addr_t;
+#define IPADDR6_INIT(a, b, c, d)                { { a, b, c, d } }
+#define IP_IS_V6_VAL(ipaddr)                    1
+#define IP_IS_V6(ipaddr)                        1
+#define IP_IS_ANY_TYPE_VAL(ipaddr)              0
+#define IP_SET_TYPE_VAL(ipaddr, iptype)
+#define IP_SET_TYPE(ipaddr, iptype)
+#define IP_GET_TYPE(ipaddr)                     IPADDR_TYPE_V6
+#define ip_2_ip6(ipaddr)                        (ipaddr)
+#define IP_ADDR6(ipaddr,i0,i1,i2,i3)            IP6_ADDR(ipaddr,i0,i1,i2,i3)
+
+#define ip_addr_copy(dest, src)                 ip6_addr_copy(dest, src)
+#define ip_addr_copy_from_ip6(dest, src)        ip6_addr_copy(dest, src)
+#define ip_addr_set(dest, src)                  ip6_addr_set(dest, src)
+#define ip_addr_set_ipaddr(dest, src)           ip6_addr_set(dest, src)
+#define ip_addr_set_zero(ipaddr)                ip6_addr_set_zero(ipaddr)
+#define ip_addr_set_zero_ip6(ipaddr)            ip6_addr_set_zero(ipaddr)
+#define ip_addr_set_any(is_ipv6, ipaddr)        ip6_addr_set_any(ipaddr)
+#define ip_addr_set_loopback(is_ipv6, ipaddr)   ip6_addr_set_loopback(ipaddr)
+#define ip_addr_set_hton(dest, src)             ip6_addr_set_hton(dest, src)
+#define ip_addr_get_network(target, host, mask) ip6_addr_set_zero(target)
+#define ip_addr_netcmp(addr1, addr2, mask)      0
+#define ip_addr_cmp(addr1, addr2)               ip6_addr_cmp(addr1, addr2)
+#define ip_addr_isany(ipaddr)                   ip6_addr_isany(ipaddr)
+#define ip_addr_isany_val(ipaddr)               ip6_addr_isany_val(ipaddr)
+#define ip_addr_isloopback(ipaddr)              ip6_addr_isloopback(ipaddr)
+#define ip_addr_islinklocal(ipaddr)             ip6_addr_islinklocal(ipaddr)
+#define ip_addr_isbroadcast(addr, netif)        0
+#define ip_addr_ismulticast(ipaddr)             ip6_addr_ismulticast(ipaddr)
+#define ip_addr_debug_print(debug, ipaddr)      ip6_addr_debug_print(debug, ipaddr)
+#define ip_addr_debug_print_val(debug, ipaddr)  ip6_addr_debug_print_val(debug, ipaddr)
+#define ipaddr_ntoa(ipaddr)                     ip6addr_ntoa(ipaddr)
+#define ipaddr_ntoa_r(ipaddr, buf, buflen)      ip6addr_ntoa_r(ipaddr, buf, buflen)
+#define ipaddr_aton(cp, addr)                   ip6addr_aton(cp, addr)
+
+#endif /* LWIP_IPV4 */
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+
+#if LWIP_IPV4
+
+extern const ip_addr_t ip_addr_any;
+extern const ip_addr_t ip_addr_broadcast;
+
+/** IP_ADDR_ can be used as a fixed/const ip_addr_t
+ *  for the IPv4 wildcard and the broadcast address
+ */
+#define IP_ADDR_ANY         (&ip_addr_any)
+#define IP_ADDR_BROADCAST   (&ip_addr_broadcast)
+/** IP4_ADDR_ can be used as a fixed/const ip4_addr_t
+ *  for the wildcard and the broadcast address
+ */
+#define IP4_ADDR_ANY        (ip_2_ip4(&ip_addr_any))
+#define IP4_ADDR_BROADCAST  (ip_2_ip4(&ip_addr_broadcast))
+
+#endif /* LWIP_IPV4*/
+
+#if LWIP_IPV6
+
+extern const ip_addr_t ip6_addr_any;
+
+/** IP6_ADDR_ANY can be used as a fixed ip_addr_t
+ *  for the IPv6 wildcard address
+ */
+#define IP6_ADDR_ANY   (&ip6_addr_any)
+/** IP6_ADDR_ANY6 can be used as a fixed ip6_addr_t
+ *  for the IPv6 wildcard address
+ */
+#define IP6_ADDR_ANY6  (ip_2_ip6(&ip6_addr_any))
+
+#if !LWIP_IPV4
+/** Just a little upgrade-helper for IPv6-only configurations: */
+#define IP_ADDR_ANY IP6_ADDR_ANY
+#endif /* !LWIP_IPV4 */
+
+#endif
+
+#if LWIP_IPV4 && LWIP_IPV6
+#define IP_ANY_TYPE    (&ip_addr_any_type)
+#else
+#define IP_ANY_TYPE    IP_ADDR_ANY
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_IP_ADDR_H__ */
diff --git a/tools/sdk/include/lwip/lwip/ip_frag.h b/tools/sdk/include/lwip/lwip/ip_frag.h
new file mode 100755
index 00000000..deeb2f4e
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/ip_frag.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Jani Monoses 
+ *
+ */
+
+#ifndef LWIP_HDR_IP_FRAG_H
+#define LWIP_HDR_IP_FRAG_H
+
+#include "lwip/opt.h"
+#include "lwip/err.h"
+#include "lwip/pbuf.h"
+#include "lwip/netif.h"
+#include "lwip/ip_addr.h"
+#include "lwip/ip.h"
+
+#if LWIP_IPV4
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if IP_REASSEMBLY
+/* The IP reassembly timer interval in milliseconds. */
+#define IP_TMR_INTERVAL 1000
+
+/* IP reassembly helper struct.
+ * This is exported because memp needs to know the size.
+ */
+struct ip_reassdata {
+  struct ip_reassdata *next;
+  struct pbuf *p;
+  struct ip_hdr iphdr;
+  u16_t datagram_len;
+  u8_t flags;
+  u8_t timer;
+};
+
+void ip_reass_init(void);
+void ip_reass_tmr(void);
+struct pbuf * ip4_reass(struct pbuf *p);
+#endif /* IP_REASSEMBLY */
+
+#if IP_FRAG
+#if !IP_FRAG_USES_STATIC_BUF && !LWIP_NETIF_TX_SINGLE_PBUF
+/** A custom pbuf that holds a reference to another pbuf, which is freed
+ * when this custom pbuf is freed. This is used to create a custom PBUF_REF
+ * that points into the original pbuf. */
+#ifndef LWIP_PBUF_CUSTOM_REF_DEFINED
+#define LWIP_PBUF_CUSTOM_REF_DEFINED
+struct pbuf_custom_ref {
+  /** 'base class' */
+  struct pbuf_custom pc;
+  /** pointer to the original pbuf that is referenced */
+  struct pbuf *original;
+};
+#endif /* LWIP_PBUF_CUSTOM_REF_DEFINED */
+#endif /* !IP_FRAG_USES_STATIC_BUF && !LWIP_NETIF_TX_SINGLE_PBUF */
+
+err_t ip4_frag(struct pbuf *p, struct netif *netif, const ip4_addr_t *dest);
+#endif /* IP_FRAG */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV4 */
+
+#endif /* LWIP_HDR_IP_FRAG_H */
diff --git a/tools/sdk/include/lwip/lwip/lwip_debug.h b/tools/sdk/include/lwip/lwip/lwip_debug.h
new file mode 100644
index 00000000..abfcd2c1
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/lwip_debug.h
@@ -0,0 +1,24 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+#ifndef _LWIP_DEBUG_H
+#define _LWIP_DEBUG_H
+
+void dbg_lwip_tcp_pcb_show(void);
+void dbg_lwip_udp_pcb_show(void);
+void dbg_lwip_tcp_rxtx_show(void);
+void dbg_lwip_udp_rxtx_show(void);
+
+#endif
diff --git a/tools/sdk/include/lwip/lwip/mem.h b/tools/sdk/include/lwip/lwip/mem.h
new file mode 100755
index 00000000..ca76f663
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/mem.h
@@ -0,0 +1,162 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef LWIP_HDR_MEM_H
+#define LWIP_HDR_MEM_H
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if MEM_LIBC_MALLOC
+
+#include  /* for size_t */
+
+typedef size_t mem_size_t;
+#define MEM_SIZE_F SZT_F
+
+/* aliases for C library malloc() */
+#define mem_init()
+/* in case C library malloc() needs extra protection,
+ * allow these defines to be overridden.
+ */
+
+#ifndef MEMLEAK_DEBUG
+
+#ifndef mem_free
+#define mem_free free
+#endif
+#ifndef mem_malloc
+#define mem_malloc malloc
+#endif
+#ifndef mem_calloc
+#define mem_calloc calloc
+#endif
+
+/*      DYC_NEED_TO_DO_LATER
+#ifndef mem_realloc
+#define mem_realloc 
+#endif
+#ifndef mem_zalloc
+#define mem_zalloc
+#endif
+*/
+
+#else
+/*
+#ifndef mem_free
+#define mem_free(s) \
+	do{\
+		const char *file = mem_debug_file;\
+		vPortFree(s, file, __LINE__);\
+	}while(0)
+#endif
+#ifndef mem_malloc
+#define mem_malloc(s) ({const char *file = mem_debug_file; pvPortMalloc(s, file, __LINE__);})
+#endif
+#ifndef mem_calloc
+#define mem_calloc(s) ({const char *file = mem_debug_file; pvPortCalloc(s, file, __LINE__);})
+#endif
+#ifndef mem_realloc
+#define mem_realloc(p, s) ({const char *file = mem_debug_file; pvPortRealloc(p, s, file, __LINE__);})
+#endif
+#ifndef mem_zalloc
+#define mem_zalloc(s) ({const char *file = mem_debug_file; pvPortZalloc(s, file, __LINE__);})
+#endif
+*/
+#endif
+
+
+
+/* Since there is no C library allocation function to shrink memory without
+   moving it, define this to nothing. */
+#ifndef mem_trim
+#define mem_trim(mem, size) (mem)
+#endif
+#else /* MEM_LIBC_MALLOC */
+
+/* MEM_SIZE would have to be aligned, but using 64000 here instead of
+ * 65535 leaves some room for alignment...
+ */
+#if MEM_SIZE > 64000L
+typedef u32_t mem_size_t;
+#define MEM_SIZE_F U32_F
+#else
+typedef u16_t mem_size_t;
+#define MEM_SIZE_F U16_F
+#endif /* MEM_SIZE > 64000 */
+
+#if MEM_USE_POOLS
+/** mem_init is not used when using pools instead of a heap */
+#define mem_init()
+/** mem_trim is not used when using pools instead of a heap:
+    we can't free part of a pool element and don't want to copy the rest */
+#define mem_trim(mem, size) (mem)
+#else /* MEM_USE_POOLS */
+/* lwIP alternative malloc */
+void  mem_init(void);
+void *mem_trim(void *mem, mem_size_t size);
+#endif /* MEM_USE_POOLS */
+void *mem_malloc(mem_size_t size);
+void *mem_calloc(mem_size_t count, mem_size_t size);
+void  mem_free(void *mem);
+#endif /* MEM_LIBC_MALLOC */
+
+/** Calculate memory size for an aligned buffer - returns the next highest
+ * multiple of MEM_ALIGNMENT (e.g. LWIP_MEM_ALIGN_SIZE(3) and
+ * LWIP_MEM_ALIGN_SIZE(4) will both yield 4 for MEM_ALIGNMENT == 4).
+ */
+#ifndef LWIP_MEM_ALIGN_SIZE
+#define LWIP_MEM_ALIGN_SIZE(size) (((size) + MEM_ALIGNMENT - 1U) & ~(MEM_ALIGNMENT-1U))
+#endif
+
+/** Calculate safe memory size for an aligned buffer when using an unaligned
+ * type as storage. This includes a safety-margin on (MEM_ALIGNMENT - 1) at the
+ * start (e.g. if buffer is u8_t[] and actual data will be u32_t*)
+ */
+#ifndef LWIP_MEM_ALIGN_BUFFER
+#define LWIP_MEM_ALIGN_BUFFER(size) (((size) + MEM_ALIGNMENT - 1U))
+#endif
+
+/** Align a memory pointer to the alignment defined by MEM_ALIGNMENT
+ * so that ADDR % MEM_ALIGNMENT == 0
+ */
+#ifndef LWIP_MEM_ALIGN
+#define LWIP_MEM_ALIGN(addr) ((void *)(((mem_ptr_t)(addr) + MEM_ALIGNMENT - 1) & ~(mem_ptr_t)(MEM_ALIGNMENT-1)))
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_MEM_H */
diff --git a/tools/sdk/include/lwip/lwip/memp.h b/tools/sdk/include/lwip/lwip/memp.h
new file mode 100755
index 00000000..d7463f2b
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/memp.h
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#ifndef LWIP_HDR_MEMP_H
+#define LWIP_HDR_MEMP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* run once with empty definition to handle all custom includes in lwippools.h */
+#define LWIP_MEMPOOL(name,num,size,desc)
+#include "lwip/priv/memp_std.h"
+
+/* Create the list of all memory pools managed by memp. MEMP_MAX represents a NULL pool at the end */
+typedef enum {
+#define LWIP_MEMPOOL(name,num,size,desc)  MEMP_##name,
+#include "lwip/priv/memp_std.h"
+  MEMP_MAX
+} memp_t;
+
+#include "lwip/priv/memp_priv.h"
+
+/* Private mempools example:
+ * .h: only when pool is used in multiple .c files: LWIP_MEMPOOL_PROTOTYPE(my_private_pool);
+ * .c:
+ *   - in global variables section: LWIP_MEMPOOL_DECLARE(my_private_pool, 10, sizeof(foo), "Some description")
+ *   - call ONCE before using pool (e.g. in some init() function): LWIP_MEMPOOL_INIT(my_private_pool);
+ *   - allocate: void* my_new_mem = LWIP_MEMPOOL_ALLOC(my_private_pool);
+ *   - free: LWIP_MEMPOOL_FREE(my_private_pool, my_new_mem);
+ *
+ * To relocate a pool, declare it as extern in cc.h. Example for GCC:
+ *   extern u8_t __attribute__((section(".onchip_mem"))) memp_memory_my_private_pool[];
+ */
+
+extern const struct memp_desc* const memp_pools[MEMP_MAX];
+
+#define LWIP_MEMPOOL_PROTOTYPE(name) extern const struct memp_desc memp_ ## name
+
+#if MEMP_MEM_MALLOC
+
+#include "lwip/mem.h"
+
+#define memp_init()
+#define memp_malloc(type)     mem_malloc(memp_pools[type]->size)
+#define memp_free(type, mem)  mem_free(mem)
+
+#define LWIP_MEMPOOL_DECLARE(name,num,size,desc) \
+  const struct memp_desc memp_ ## name = { \
+    LWIP_MEM_ALIGN_SIZE(size) \
+  };
+
+#define LWIP_MEMPOOL_INIT(name)
+#define LWIP_MEMPOOL_ALLOC(name)   mem_malloc(memp_ ## name.size)
+#define LWIP_MEMPOOL_FREE(name, x) mem_free(x)
+
+#else /* MEMP_MEM_MALLOC */
+
+#define LWIP_MEMPOOL_DECLARE(name,num,size,desc) u8_t memp_memory_ ## name ## _base \
+    [((num) * (MEMP_SIZE + MEMP_ALIGN_SIZE(size)))]; \
+    \
+  static struct memp *memp_tab_ ## name; \
+    \
+  const struct memp_desc memp_ ## name = { \
+    LWIP_MEM_ALIGN_SIZE(size), \
+    (num), \
+    DECLARE_LWIP_MEMPOOL_DESC(desc) \
+    memp_memory_ ## name ## _base, \
+    &memp_tab_ ## name \
+  };
+
+#define LWIP_MEMPOOL_INIT(name)    memp_init_pool(&memp_ ## name)
+#define LWIP_MEMPOOL_ALLOC(name)   memp_malloc_pool(&memp_ ## name)
+#define LWIP_MEMPOOL_FREE(name, x) memp_free_pool(&memp_ ## name, (x))
+
+#if MEM_USE_POOLS
+/** This structure is used to save the pool one element came from. */
+struct memp_malloc_helper
+{
+   memp_t poolnr;
+#if MEMP_OVERFLOW_CHECK
+   u16_t size;
+#endif /* MEMP_OVERFLOW_CHECK */
+};
+
+#endif /* MEM_USE_POOLS */
+
+void  memp_init(void);
+
+#if MEMP_OVERFLOW_CHECK
+void *memp_malloc_fn(memp_t type, const char* file, const int line);
+#define memp_malloc(t) memp_malloc_fn((t), __FILE__, __LINE__)
+#else
+void *memp_malloc(memp_t type);
+#endif
+void  memp_free(memp_t type, void *mem);
+
+#endif /* MEMP_MEM_MALLOC */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_MEMP_H */
diff --git a/tools/sdk/include/lwip/lwip/mld6.h b/tools/sdk/include/lwip/lwip/mld6.h
new file mode 100755
index 00000000..a54dd49e
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/mld6.h
@@ -0,0 +1,119 @@
+/**
+ * @file
+ *
+ * Multicast listener discovery for IPv6. Aims to be compliant with RFC 2710.
+ * No support for MLDv2.
+ */
+
+/*
+ * Copyright (c) 2010 Inico Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Ivan Delamer 
+ *
+ *
+ * Please coordinate changes and requests with Ivan Delamer
+ * 
+ */
+
+#ifndef LWIP_HDR_MLD6_H
+#define LWIP_HDR_MLD6_H
+
+#include "lwip/opt.h"
+
+#if LWIP_IPV6_MLD && LWIP_IPV6  /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/pbuf.h"
+#include "lwip/netif.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct mld_group {
+  /** next link */
+  struct mld_group *next;
+  /** interface on which the group is active */
+  struct netif      *netif;
+  /** multicast address */
+  ip6_addr_t         group_address;
+  /** signifies we were the last person to report */
+  u8_t               last_reporter_flag;
+  /** current state of the group */
+  u8_t               group_state;
+  /** timer for reporting */
+  u16_t              timer;
+  /** counter of simultaneous uses */
+  u8_t               use;
+};
+
+/** Multicast listener report/query/done message header. */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct mld_header {
+  PACK_STRUCT_FLD_8(u8_t type);
+  PACK_STRUCT_FLD_8(u8_t code);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FIELD(u16_t max_resp_delay);
+  PACK_STRUCT_FIELD(u16_t reserved);
+  PACK_STRUCT_FLD_S(ip6_addr_p_t multicast_address);
+  /* Options follow. */
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define MLD6_TMR_INTERVAL              100 /* Milliseconds */
+
+/* MAC Filter Actions, these are passed to a netif's
+ * mld_mac_filter callback function. */
+#define MLD6_DEL_MAC_FILTER            0
+#define MLD6_ADD_MAC_FILTER            1
+
+
+err_t  mld6_stop(struct netif *netif);
+void   mld6_report_groups(struct netif *netif);
+void   mld6_tmr(void);
+struct mld_group *mld6_lookfor_group(struct netif *ifp, const ip6_addr_t *addr);
+void   mld6_input(struct pbuf *p, struct netif *inp);
+err_t  mld6_joingroup(const ip6_addr_t *srcaddr, const ip6_addr_t *groupaddr);
+err_t  mld6_joingroup_netif(struct netif *netif, const ip6_addr_t *groupaddr);
+err_t  mld6_leavegroup(const ip6_addr_t *srcaddr, const ip6_addr_t *groupaddr);
+err_t  mld6_leavegroup_netif(struct netif *netif, const ip6_addr_t *groupaddr);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV6_MLD && LWIP_IPV6 */
+
+#endif /* LWIP_HDR_MLD6_H */
diff --git a/tools/sdk/include/lwip/lwip/nd6.h b/tools/sdk/include/lwip/lwip/nd6.h
new file mode 100755
index 00000000..d0646f1b
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/nd6.h
@@ -0,0 +1,361 @@
+/**
+ * @file
+ *
+ * Neighbor discovery and stateless address autoconfiguration for IPv6.
+ * Aims to be compliant with RFC 4861 (Neighbor discovery) and RFC 4862
+ * (Address autoconfiguration).
+ */
+
+/*
+ * Copyright (c) 2010 Inico Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Ivan Delamer 
+ *
+ *
+ * Please coordinate changes and requests with Ivan Delamer
+ * 
+ */
+
+#ifndef LWIP_HDR_ND6_H
+#define LWIP_HDR_ND6_H
+
+#include "lwip/opt.h"
+
+#if LWIP_IPV6  /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/pbuf.h"
+#include "lwip/ip6.h"
+#include "lwip/ip6_addr.h"
+#include "lwip/netif.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Struct for tables. */
+struct nd6_neighbor_cache_entry {
+  ip6_addr_t next_hop_address;
+  struct netif * netif;
+  u8_t lladdr[NETIF_MAX_HWADDR_LEN];
+  /*u32_t pmtu;*/
+#if LWIP_ND6_QUEUEING
+  /** Pointer to queue of pending outgoing packets on this entry. */
+  struct nd6_q_entry *q;
+#else /* LWIP_ND6_QUEUEING */
+  /** Pointer to a single pending outgoing packet on this entry. */
+  struct pbuf *q;
+#endif /* LWIP_ND6_QUEUEING */
+  u8_t state;
+  u8_t isrouter;
+  union {
+    u32_t reachable_time;
+    u32_t delay_time;
+    u32_t probes_sent;
+    u32_t stale_time;
+  } counter;
+};
+
+struct nd6_destination_cache_entry {
+  ip6_addr_t destination_addr;
+  ip6_addr_t next_hop_addr;
+  u16_t pmtu;
+  u32_t age;
+};
+
+struct nd6_prefix_list_entry {
+  ip6_addr_t prefix;
+  struct netif * netif;
+  u32_t invalidation_timer;
+#if LWIP_IPV6_AUTOCONFIG
+  u8_t flags;
+#define ND6_PREFIX_AUTOCONFIG_AUTONOMOUS 0x01
+#define ND6_PREFIX_AUTOCONFIG_ADDRESS_GENERATED 0x02
+#define ND6_PREFIX_AUTOCONFIG_ADDRESS_DUPLICATE 0x04
+#endif /* LWIP_IPV6_AUTOCONFIG */
+};
+
+struct nd6_router_list_entry {
+  struct nd6_neighbor_cache_entry * neighbor_entry;
+  u32_t invalidation_timer;
+  u8_t flags;
+};
+
+
+enum nd6_neighbor_cache_entry_state {
+  ND6_NO_ENTRY = 0,
+  ND6_INCOMPLETE,
+  ND6_REACHABLE,
+  ND6_STALE,
+  ND6_DELAY,
+  ND6_PROBE
+};
+
+#if LWIP_ND6_QUEUEING
+/** struct for queueing outgoing packets for unknown address
+  * defined here to be accessed by memp.h
+  */
+struct nd6_q_entry {
+  struct nd6_q_entry *next;
+  struct pbuf *p;
+};
+#endif /* LWIP_ND6_QUEUEING */
+
+/** Neighbor solicitation message header. */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ns_header {
+  PACK_STRUCT_FLD_8(u8_t type);
+  PACK_STRUCT_FLD_8(u8_t code);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FIELD(u32_t reserved);
+  PACK_STRUCT_FLD_S(ip6_addr_p_t target_address);
+  /* Options follow. */
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/** Neighbor advertisement message header. */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct na_header {
+  PACK_STRUCT_FLD_8(u8_t type);
+  PACK_STRUCT_FLD_8(u8_t code);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FLD_8(u8_t flags);
+  PACK_STRUCT_FLD_8(u8_t reserved[3]);
+  PACK_STRUCT_FLD_S(ip6_addr_p_t target_address);
+  /* Options follow. */
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+#define ND6_FLAG_ROUTER      (0x80)
+#define ND6_FLAG_SOLICITED   (0x40)
+#define ND6_FLAG_OVERRIDE    (0x20)
+
+/** Router solicitation message header. */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct rs_header {
+  PACK_STRUCT_FLD_8(u8_t type);
+  PACK_STRUCT_FLD_8(u8_t code);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FIELD(u32_t reserved);
+  /* Options follow. */
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/** Router advertisement message header. */
+#define ND6_RA_FLAG_MANAGED_ADDR_CONFIG (0x80)
+#define ND6_RA_FLAG_OTHER_CONFIG (0x40)
+#define ND6_RA_FLAG_HOME_AGENT (0x20)
+#define ND6_RA_PREFERENCE_MASK (0x18)
+#define ND6_RA_PREFERENCE_HIGH (0x08)
+#define ND6_RA_PREFERENCE_MEDIUM (0x00)
+#define ND6_RA_PREFERENCE_LOW (0x18)
+#define ND6_RA_PREFERENCE_DISABLED (0x10)
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ra_header {
+  PACK_STRUCT_FLD_8(u8_t type);
+  PACK_STRUCT_FLD_8(u8_t code);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FLD_8(u8_t current_hop_limit);
+  PACK_STRUCT_FLD_8(u8_t flags);
+  PACK_STRUCT_FIELD(u16_t router_lifetime);
+  PACK_STRUCT_FIELD(u32_t reachable_time);
+  PACK_STRUCT_FIELD(u32_t retrans_timer);
+  /* Options follow. */
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/** Redirect message header. */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct redirect_header {
+  PACK_STRUCT_FLD_8(u8_t type);
+  PACK_STRUCT_FLD_8(u8_t code);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FIELD(u32_t reserved);
+  PACK_STRUCT_FLD_S(ip6_addr_p_t target_address);
+  PACK_STRUCT_FLD_S(ip6_addr_p_t destination_address);
+  /* Options follow. */
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/** Link-layer address option. */
+#define ND6_OPTION_TYPE_SOURCE_LLADDR (0x01)
+#define ND6_OPTION_TYPE_TARGET_LLADDR (0x02)
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct lladdr_option {
+  PACK_STRUCT_FLD_8(u8_t type);
+  PACK_STRUCT_FLD_8(u8_t length);
+  PACK_STRUCT_FLD_8(u8_t addr[NETIF_MAX_HWADDR_LEN]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/** Prefix information option. */
+#define ND6_OPTION_TYPE_PREFIX_INFO (0x03)
+#define ND6_PREFIX_FLAG_ON_LINK (0x80)
+#define ND6_PREFIX_FLAG_AUTONOMOUS (0x40)
+#define ND6_PREFIX_FLAG_ROUTER_ADDRESS (0x20)
+#define ND6_PREFIX_FLAG_SITE_PREFIX (0x10)
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct prefix_option {
+  PACK_STRUCT_FLD_8(u8_t type);
+  PACK_STRUCT_FLD_8(u8_t length);
+  PACK_STRUCT_FLD_8(u8_t prefix_length);
+  PACK_STRUCT_FLD_8(u8_t flags);
+  PACK_STRUCT_FIELD(u32_t valid_lifetime);
+  PACK_STRUCT_FIELD(u32_t preferred_lifetime);
+  PACK_STRUCT_FLD_8(u8_t reserved2[3]);
+  PACK_STRUCT_FLD_8(u8_t site_prefix_length);
+  PACK_STRUCT_FLD_S(ip6_addr_p_t prefix);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/** Redirected header option. */
+#define ND6_OPTION_TYPE_REDIR_HDR (0x04)
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct redirected_header_option {
+  PACK_STRUCT_FLD_8(u8_t type);
+  PACK_STRUCT_FLD_8(u8_t length);
+  PACK_STRUCT_FLD_8(u8_t reserved[6]);
+  /* Portion of redirected packet follows. */
+  /* PACK_STRUCT_FLD_8(u8_t redirected[8]); */
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/** MTU option. */
+#define ND6_OPTION_TYPE_MTU (0x05)
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct mtu_option {
+  PACK_STRUCT_FLD_8(u8_t type);
+  PACK_STRUCT_FLD_8(u8_t length);
+  PACK_STRUCT_FIELD(u16_t reserved);
+  PACK_STRUCT_FIELD(u32_t mtu);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/** Route information option. */
+#define ND6_OPTION_TYPE_ROUTE_INFO (24)
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct route_option {
+  PACK_STRUCT_FLD_8(u8_t type);
+  PACK_STRUCT_FLD_8(u8_t length);
+  PACK_STRUCT_FLD_8(u8_t prefix_length);
+  PACK_STRUCT_FLD_8(u8_t preference);
+  PACK_STRUCT_FIELD(u32_t route_lifetime);
+  PACK_STRUCT_FLD_S(ip6_addr_p_t prefix);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/** 1 second period */
+#define ND6_TMR_INTERVAL 1000
+
+/* Router tables. */
+/* TODO make these static? and entries accessible through API? */
+extern struct nd6_neighbor_cache_entry neighbor_cache[];
+extern struct nd6_destination_cache_entry destination_cache[];
+extern struct nd6_prefix_list_entry prefix_list[];
+extern struct nd6_router_list_entry default_router_list[];
+
+/* Default values, can be updated by a RA message. */
+extern u32_t reachable_time;
+extern u32_t retrans_timer;
+
+void nd6_tmr(void);
+void nd6_input(struct pbuf *p, struct netif *inp);
+s8_t nd6_get_next_hop_entry(const ip6_addr_t * ip6addr, struct netif * netif);
+s8_t nd6_select_router(const ip6_addr_t * ip6addr, struct netif * netif);
+u16_t nd6_get_destination_mtu(const ip6_addr_t * ip6addr, struct netif * netif);
+err_t nd6_queue_packet(s8_t neighbor_index, struct pbuf * p);
+#if LWIP_ND6_TCP_REACHABILITY_HINTS
+void nd6_reachability_hint(const ip6_addr_t * ip6addr);
+#endif /* LWIP_ND6_TCP_REACHABILITY_HINTS */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV6 */
+
+#endif /* LWIP_HDR_ND6_H */
diff --git a/tools/sdk/include/lwip/lwip/netbuf.h b/tools/sdk/include/lwip/lwip/netbuf.h
new file mode 100755
index 00000000..8875e12d
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/netbuf.h
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef LWIP_HDR_NETBUF_H
+#define LWIP_HDR_NETBUF_H
+
+#include "lwip/opt.h"
+
+#if LWIP_NETCONN || LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */
+/* Note: Netconn API is always available when sockets are enabled -
+ * sockets are implemented on top of them */
+
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+#include "lwip/ip6_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** This netbuf has dest-addr/port set */
+#define NETBUF_FLAG_DESTADDR    0x01
+/** This netbuf includes a checksum */
+#define NETBUF_FLAG_CHKSUM      0x02
+
+struct netbuf {
+  struct pbuf *p, *ptr;
+  ip_addr_t addr;
+  u16_t port;
+#if LWIP_NETBUF_RECVINFO || LWIP_CHECKSUM_ON_COPY
+#if LWIP_CHECKSUM_ON_COPY
+  u8_t flags;
+#endif /* LWIP_CHECKSUM_ON_COPY */
+  u16_t toport_chksum;
+#if LWIP_NETBUF_RECVINFO
+  ip_addr_t toaddr;
+#endif /* LWIP_NETBUF_RECVINFO */
+#endif /* LWIP_NETBUF_RECVINFO || LWIP_CHECKSUM_ON_COPY */
+};
+
+/* Network buffer functions: */
+struct netbuf *   netbuf_new      (void);
+void              netbuf_delete   (struct netbuf *buf);
+void *            netbuf_alloc    (struct netbuf *buf, u16_t size);
+void              netbuf_free     (struct netbuf *buf);
+err_t             netbuf_ref      (struct netbuf *buf,
+                                   const void *dataptr, u16_t size);
+void              netbuf_chain    (struct netbuf *head, struct netbuf *tail);
+
+err_t             netbuf_data     (struct netbuf *buf,
+                                   void **dataptr, u16_t *len);
+s8_t              netbuf_next     (struct netbuf *buf);
+void              netbuf_first    (struct netbuf *buf);
+
+
+#define netbuf_copy_partial(buf, dataptr, len, offset) \
+  pbuf_copy_partial((buf)->p, (dataptr), (len), (offset))
+#define netbuf_copy(buf,dataptr,len) netbuf_copy_partial(buf, dataptr, len, 0)
+#define netbuf_take(buf, dataptr, len) pbuf_take((buf)->p, dataptr, len)
+#define netbuf_len(buf)              ((buf)->p->tot_len)
+#define netbuf_fromaddr(buf)         (&((buf)->addr))
+#define netbuf_set_fromaddr(buf, fromaddr) ip_addr_set(&((buf)->addr), fromaddr)
+#define netbuf_fromport(buf)         ((buf)->port)
+#if LWIP_NETBUF_RECVINFO
+#define netbuf_destaddr(buf)         (&((buf)->toaddr))
+#define netbuf_set_destaddr(buf, destaddr) ip_addr_set(&((buf)->toaddr), destaddr)
+#if LWIP_CHECKSUM_ON_COPY
+#define netbuf_destport(buf)         (((buf)->flags & NETBUF_FLAG_DESTADDR) ? (buf)->toport_chksum : 0)
+#else /* LWIP_CHECKSUM_ON_COPY */
+#define netbuf_destport(buf)         ((buf)->toport_chksum)
+#endif /* LWIP_CHECKSUM_ON_COPY */
+#endif /* LWIP_NETBUF_RECVINFO */
+#if LWIP_CHECKSUM_ON_COPY
+#define netbuf_set_chksum(buf, chksum) do { (buf)->flags = NETBUF_FLAG_CHKSUM; \
+                                            (buf)->toport_chksum = chksum; } while(0)
+#endif /* LWIP_CHECKSUM_ON_COPY */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_NETCONN || LWIP_SOCKET */
+
+#endif /* LWIP_HDR_NETBUF_H */
diff --git a/tools/sdk/include/lwip/lwip/netdb.h b/tools/sdk/include/lwip/lwip/netdb.h
new file mode 100755
index 00000000..144a6e0b
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/netdb.h
@@ -0,0 +1,142 @@
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Simon Goldschmidt
+ *
+ */
+#ifndef LWIP_HDR_NETDB_H
+#define LWIP_HDR_NETDB_H
+
+#include "lwip/opt.h"
+
+#if LWIP_DNS && LWIP_SOCKET
+
+#include  /* for size_t */
+
+#include "lwip/inet.h"
+#include "lwip/sockets.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* some rarely used options */
+#ifndef LWIP_DNS_API_DECLARE_H_ERRNO
+#define LWIP_DNS_API_DECLARE_H_ERRNO  1
+#endif
+
+#ifndef LWIP_DNS_API_DEFINE_ERRORS
+#define LWIP_DNS_API_DEFINE_ERRORS    1
+#endif
+
+#ifndef LWIP_DNS_API_DEFINE_FLAGS
+#define LWIP_DNS_API_DEFINE_FLAGS     1
+#endif
+
+#ifndef LWIP_DNS_API_DECLARE_STRUCTS
+#define LWIP_DNS_API_DECLARE_STRUCTS  1
+#endif
+
+#if LWIP_DNS_API_DEFINE_ERRORS
+/** Errors used by the DNS API functions, h_errno can be one of them */
+#define EAI_NONAME      200
+#define EAI_SERVICE     201
+#define EAI_FAIL        202
+#define EAI_MEMORY      203
+#define EAI_FAMILY      204
+
+#define HOST_NOT_FOUND  210
+#define NO_DATA         211
+#define NO_RECOVERY     212
+#define TRY_AGAIN       213
+#endif /* LWIP_DNS_API_DEFINE_ERRORS */
+
+#if LWIP_DNS_API_DEFINE_FLAGS
+/* input flags for struct addrinfo */
+#define AI_PASSIVE      0x01
+#define AI_CANONNAME    0x02
+#define AI_NUMERICHOST  0x04
+#define AI_NUMERICSERV  0x08
+#define AI_V4MAPPED     0x10
+#define AI_ALL          0x20
+#define AI_ADDRCONFIG   0x40
+#endif /* LWIP_DNS_API_DEFINE_FLAGS */
+
+#if LWIP_DNS_API_DECLARE_STRUCTS
+struct hostent {
+    char  *h_name;      /* Official name of the host. */
+    char **h_aliases;   /* A pointer to an array of pointers to alternative host names,
+                           terminated by a null pointer. */
+    int    h_addrtype;  /* Address type. */
+    int    h_length;    /* The length, in bytes, of the address. */
+    char **h_addr_list; /* A pointer to an array of pointers to network addresses (in
+                           network byte order) for the host, terminated by a null pointer. */
+#define h_addr h_addr_list[0] /* for backward compatibility */
+};
+
+struct addrinfo {
+    int               ai_flags;      /* Input flags. */
+    int               ai_family;     /* Address family of socket. */
+    int               ai_socktype;   /* Socket type. */
+    int               ai_protocol;   /* Protocol of socket. */
+    socklen_t         ai_addrlen;    /* Length of socket address. */
+    struct sockaddr  *ai_addr;       /* Socket address of socket. */
+    char             *ai_canonname;  /* Canonical name of service location. */
+    struct addrinfo  *ai_next;       /* Pointer to next in list. */
+};
+#endif /* LWIP_DNS_API_DECLARE_STRUCTS */
+
+#define NETDB_ELEM_SIZE           (sizeof(struct addrinfo) + sizeof(struct sockaddr_storage) + DNS_MAX_NAME_LENGTH + 1)
+
+#if LWIP_DNS_API_DECLARE_H_ERRNO
+/* application accessible error code set by the DNS API functions */
+extern int h_errno;
+#endif /* LWIP_DNS_API_DECLARE_H_ERRNO*/
+
+struct hostent *lwip_gethostbyname(const char *name);
+int lwip_gethostbyname_r(const char *name, struct hostent *ret, char *buf,
+                size_t buflen, struct hostent **result, int *h_errnop);
+void lwip_freeaddrinfo(struct addrinfo *ai);
+int lwip_getaddrinfo(const char *nodename,
+       const char *servname,
+       const struct addrinfo *hints,
+       struct addrinfo **res);
+
+#if LWIP_COMPAT_SOCKETS
+#define gethostbyname(name) lwip_gethostbyname(name)
+#define gethostbyname_r(name, ret, buf, buflen, result, h_errnop) \
+       lwip_gethostbyname_r(name, ret, buf, buflen, result, h_errnop)
+#define freeaddrinfo(addrinfo) lwip_freeaddrinfo(addrinfo)
+#define getaddrinfo(nodname, servname, hints, res) \
+       lwip_getaddrinfo(nodname, servname, hints, res)
+#endif /* LWIP_COMPAT_SOCKETS */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_DNS && LWIP_SOCKET */
+
+#endif /* LWIP_HDR_NETDB_H */
diff --git a/tools/sdk/include/lwip/lwip/netif.h b/tools/sdk/include/lwip/lwip/netif.h
new file mode 100755
index 00000000..99066a5a
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/netif.h
@@ -0,0 +1,447 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef LWIP_HDR_NETIF_H
+#define LWIP_HDR_NETIF_H
+
+#include "lwip/opt.h"
+
+#define ENABLE_LOOPBACK (LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF)
+
+#include "lwip/err.h"
+
+#include "lwip/ip_addr.h"
+
+#include "lwip/def.h"
+#include "lwip/pbuf.h"
+#include "lwip/stats.h"
+
+#if LWIP_DHCP
+struct dhcp;
+#endif
+#if LWIP_AUTOIP
+struct autoip;
+#endif
+#if LWIP_IPV6_DHCP6
+struct dhcp6;
+#endif /* LWIP_IPV6_DHCP6 */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Throughout this file, IP addresses are expected to be in
+ * the same byte order as in IP_PCB. */
+
+/** Must be the maximum of all used hardware address lengths
+    across all types of interfaces in use.
+    This does not have to be changed, normally. */
+#ifndef NETIF_MAX_HWADDR_LEN
+#define NETIF_MAX_HWADDR_LEN 6U
+#endif
+
+/** Whether the network interface is 'up'. This is
+ * a software flag used to control whether this network
+ * interface is enabled and processes traffic.
+ * It must be set by the startup code before this netif can be used
+ * (also for dhcp/autoip).
+ */
+#define NETIF_FLAG_UP           0x01U
+/** If set, the netif has broadcast capability.
+ * Set by the netif driver in its init function. */
+#define NETIF_FLAG_BROADCAST    0x02U
+/** If set, the interface has an active link
+ *  (set by the network interface driver).
+ * Either set by the netif driver in its init function (if the link
+ * is up at that time) or at a later point once the link comes up
+ * (if link detection is supported by the hardware). */
+#define NETIF_FLAG_LINK_UP      0x04U
+/** If set, the netif is an ethernet device using ARP.
+ * Set by the netif driver in its init function.
+ * Used to check input packet types and use of DHCP. */
+#define NETIF_FLAG_ETHARP       0x08U
+/** If set, the netif is an ethernet device. It might not use
+ * ARP or TCP/IP if it is used for PPPoE only.
+ */
+#define NETIF_FLAG_ETHERNET     0x10U
+/** If set, the netif has IGMP capability.
+ * Set by the netif driver in its init function. */
+#define NETIF_FLAG_IGMP         0x20U
+/** If set, the netif has MLD6 capability.
+ * Set by the netif driver in its init function. */
+#define NETIF_FLAG_MLD6         0x40U
+
+#if LWIP_CHECKSUM_CTRL_PER_NETIF
+#define NETIF_CHECKSUM_GEN_IP       0x0001
+#define NETIF_CHECKSUM_GEN_UDP      0x0002
+#define NETIF_CHECKSUM_GEN_TCP      0x0004
+#define NETIF_CHECKSUM_GEN_ICMP     0x0008
+#define NETIF_CHECKSUM_GEN_ICMP6    0x0010
+#define NETIF_CHECKSUM_CHECK_IP     0x0100
+#define NETIF_CHECKSUM_CHECK_UDP    0x0200
+#define NETIF_CHECKSUM_CHECK_TCP    0x0400
+#define NETIF_CHECKSUM_CHECK_ICMP   0x0800
+#define NETIF_CHECKSUM_CHECK_ICMP6  0x1000
+#define NETIF_CHECKSUM_ENABLE_ALL   0xFFFF
+#define NETIF_CHECKSUM_DISABLE_ALL  0x0000
+#endif /* LWIP_CHECKSUM_CTRL_PER_NETIF */
+
+struct netif;
+
+/** Function prototype for netif init functions. Set up flags and output/linkoutput
+ * callback functions in this function.
+ *
+ * @param netif The netif to initialize
+ */
+typedef err_t (*netif_init_fn)(struct netif *netif);
+/** Function prototype for netif->input functions. This function is saved as 'input'
+ * callback function in the netif struct. Call it when a packet has been received.
+ *
+ * @param p The received packet, copied into a pbuf
+ * @param inp The netif which received the packet
+ */
+typedef err_t (*netif_input_fn)(struct pbuf *p, struct netif *inp);
+
+#if LWIP_IPV4
+/** Function prototype for netif->output functions. Called by lwIP when a packet
+ * shall be sent. For ethernet netif, set this to 'etharp_output' and set
+ * 'linkoutput'.
+ *
+ * @param netif The netif which shall send a packet
+ * @param p The packet to send (p->payload points to IP header)
+ * @param ipaddr The IP address to which the packet shall be sent
+ */
+typedef err_t (*netif_output_fn)(struct netif *netif, struct pbuf *p,
+       const ip4_addr_t *ipaddr);
+#endif /* LWIP_IPV4*/
+
+#if LWIP_IPV6
+/** Function prototype for netif->output_ip6 functions. Called by lwIP when a packet
+ * shall be sent. For ethernet netif, set this to 'ethip6_output' and set
+ * 'linkoutput'.
+ *
+ * @param netif The netif which shall send a packet
+ * @param p The packet to send (p->payload points to IP header)
+ * @param ipaddr The IPv6 address to which the packet shall be sent
+ */
+typedef err_t (*netif_output_ip6_fn)(struct netif *netif, struct pbuf *p,
+       const ip6_addr_t *ipaddr);
+#endif /* LWIP_IPV6 */
+
+/** Function prototype for netif->linkoutput functions. Only used for ethernet
+ * netifs. This function is called by ARP when a packet shall be sent.
+ *
+ * @param netif The netif which shall send a packet
+ * @param p The packet to send (raw ethernet packet)
+ */
+typedef err_t (*netif_linkoutput_fn)(struct netif *netif, struct pbuf *p);
+/** Function prototype for netif status- or link-callback functions. */
+typedef void (*netif_status_callback_fn)(struct netif *netif);
+#if LWIP_IPV4 && LWIP_IGMP
+/** Function prototype for netif igmp_mac_filter functions */
+typedef err_t (*netif_igmp_mac_filter_fn)(struct netif *netif,
+       const ip4_addr_t *group, u8_t action);
+#endif /* LWIP_IPV4 && LWIP_IGMP */
+#if LWIP_IPV6 && LWIP_IPV6_MLD
+/** Function prototype for netif mld_mac_filter functions */
+typedef err_t (*netif_mld_mac_filter_fn)(struct netif *netif,
+       const ip6_addr_t *group, u8_t action);
+#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */
+
+
+#ifdef LWIP_ESP8266
+/*add DHCP event processing by LiuHan*/
+typedef void (*dhcp_event_fn)(void);
+#endif
+
+
+/** Generic data structure used for all lwIP network interfaces.
+ *  The following fields should be filled in by the initialization
+ *  function for the device driver: hwaddr_len, hwaddr[], mtu, flags */
+struct netif {
+  /** pointer to next in linked list */
+  struct netif *next;
+
+#ifdef LWIP_ESP8266
+//ip_addr_t  is changed   by marco  IPV4, IPV6
+  ip_addr_t link_local_addr;
+#endif
+
+#if LWIP_IPV4
+  /** IP address configuration in network byte order */
+  ip_addr_t ip_addr;
+  ip_addr_t netmask;
+  ip_addr_t gw;
+#endif /* LWIP_IPV4 */
+#if LWIP_IPV6
+  /** Array of IPv6 addresses for this netif. */
+  ip_addr_t ip6_addr[LWIP_IPV6_NUM_ADDRESSES];
+  /** The state of each IPv6 address (Tentative, Preferred, etc).
+   * @see ip6_addr.h */
+  u8_t ip6_addr_state[LWIP_IPV6_NUM_ADDRESSES];
+#endif /* LWIP_IPV6 */
+  /** This function is called by the network device driver
+   *  to pass a packet up the TCP/IP stack. */
+  netif_input_fn input;
+#if LWIP_IPV4
+  /** This function is called by the IP module when it wants
+   *  to send a packet on the interface. This function typically
+   *  first resolves the hardware address, then sends the packet. */
+  netif_output_fn output;
+#endif /* LWIP_IPV4 */
+  /** This function is called by the ARP module when it wants
+   *  to send a packet on the interface. This function outputs
+   *  the pbuf as-is on the link medium. */
+  netif_linkoutput_fn linkoutput;
+#if LWIP_IPV6
+  /** This function is called by the IPv6 module when it wants
+   *  to send a packet on the interface. This function typically
+   *  first resolves the hardware address, then sends the packet. */
+  netif_output_ip6_fn output_ip6;
+#endif /* LWIP_IPV6 */
+#if LWIP_NETIF_STATUS_CALLBACK
+  /** This function is called when the netif state is set to up or down
+   */
+  netif_status_callback_fn status_callback;
+#endif /* LWIP_NETIF_STATUS_CALLBACK */
+#if LWIP_NETIF_LINK_CALLBACK
+  /** This function is called when the netif link is set to up or down
+   */
+  netif_status_callback_fn link_callback;
+#endif /* LWIP_NETIF_LINK_CALLBACK */
+#if LWIP_NETIF_REMOVE_CALLBACK
+  /** This function is called when the netif has been removed */
+  netif_status_callback_fn remove_callback;
+#endif /* LWIP_NETIF_REMOVE_CALLBACK */
+  /** This field can be set by the device driver and could point
+   *  to state information for the device. */
+  void *state;
+#if LWIP_DHCP
+  /** the DHCP client state information for this netif */
+  struct dhcp *dhcp;
+
+#ifdef LWIP_ESP8266
+  struct udp_pcb *dhcps_pcb;	
+  dhcp_event_fn dhcp_event;
+#endif  
+
+#endif /* LWIP_DHCP */
+
+#if LWIP_AUTOIP
+  /** the AutoIP client state information for this netif */
+  struct autoip *autoip;
+#endif
+
+#if LWIP_IPV6_AUTOCONFIG
+  /** is this netif enabled for IPv6 autoconfiguration */
+  u8_t ip6_autoconfig_enabled;
+#endif /* LWIP_IPV6_AUTOCONFIG */
+
+#if LWIP_IPV6_SEND_ROUTER_SOLICIT
+  /** Number of Router Solicitation messages that remain to be sent. */
+  u8_t rs_count;
+#endif /* LWIP_IPV6_SEND_ROUTER_SOLICIT */
+
+#if LWIP_IPV6_DHCP6
+  /** the DHCPv6 client state information for this netif */
+  struct dhcp6 *dhcp6;
+#endif /* LWIP_IPV6_DHCP6 */
+
+#if LWIP_NETIF_HOSTNAME
+  /* the hostname for this netif, NULL is a valid value */
+  const char*  hostname;
+#endif /* LWIP_NETIF_HOSTNAME */
+
+#if LWIP_CHECKSUM_CTRL_PER_NETIF
+  u16_t chksum_flags;
+#endif /* LWIP_CHECKSUM_CTRL_PER_NETIF*/
+
+  /** maximum transfer unit (in bytes) */
+  u16_t mtu;
+  /** number of bytes used in hwaddr */
+  u8_t hwaddr_len;
+  /** link level hardware address of this interface */
+  u8_t hwaddr[NETIF_MAX_HWADDR_LEN];
+  /** flags (see NETIF_FLAG_ above) */
+  u8_t flags;
+  /** descriptive abbreviation */
+  char name[2];
+  /** number of this interface */
+  u8_t num;
+  
+#if MIB2_STATS
+  /** link type (from "snmp_ifType" enum from snmp_mib2.h) */
+  u8_t link_type;
+  /** (estimate) link speed */
+  u32_t link_speed;
+  /** timestamp at last change made (up/down) */
+  u32_t ts;
+  /** counters */
+  struct stats_mib2_netif_ctrs mib2_counters;
+#endif /* MIB2_STATS */
+
+#if LWIP_IPV4 && LWIP_IGMP
+  /** This function could be called to add or delete an entry in the multicast
+      filter table of the ethernet MAC.*/
+  netif_igmp_mac_filter_fn igmp_mac_filter;
+#endif /* LWIP_IPV4 && LWIP_IGMP */
+
+#if LWIP_IPV6 && LWIP_IPV6_MLD
+  /** This function could be called to add or delete an entry in the IPv6 multicast
+      filter table of the ethernet MAC. */
+  netif_mld_mac_filter_fn mld_mac_filter;
+#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */
+
+#if LWIP_NETIF_HWADDRHINT
+  u8_t *addr_hint;
+#endif /* LWIP_NETIF_HWADDRHINT */
+#if ENABLE_LOOPBACK
+  /* List of packets to be queued for ourselves. */
+  struct pbuf *loop_first;
+  struct pbuf *loop_last;
+#if LWIP_LOOPBACK_MAX_PBUFS
+  u16_t loop_cnt_current;
+#endif /* LWIP_LOOPBACK_MAX_PBUFS */
+#endif /* ENABLE_LOOPBACK */
+};
+
+#if LWIP_CHECKSUM_CTRL_PER_NETIF
+#define NETIF_SET_CHECKSUM_CTRL(netif, chksumflags) do { \
+  (netif)->chksum_flags = chksumflags; } while(0)
+#define IF__NETIF_CHECKSUM_ENABLED(netif, chksumflag) if (((netif) == NULL) || (((netif)->chksum_flags & (chksumflag)) != 0))
+#else /* LWIP_CHECKSUM_CTRL_PER_NETIF */
+#define NETIF_SET_CHECKSUM_CTRL(netif, chksumflags)
+#define IF__NETIF_CHECKSUM_ENABLED(netif, chksumflag)
+#endif /* LWIP_CHECKSUM_CTRL_PER_NETIF */
+
+/** The list of network interfaces. */
+extern struct netif *netif_list;
+/** The default network interface. */
+extern struct netif *netif_default;
+
+void netif_init(void);
+
+struct netif *netif_add(struct netif *netif,
+#if LWIP_IPV4
+                        const ip4_addr_t *ipaddr, const ip4_addr_t *netmask, const ip4_addr_t *gw,
+#endif /* LWIP_IPV4 */
+                        void *state, netif_init_fn init, netif_input_fn input);
+#if LWIP_IPV4
+void netif_set_addr(struct netif *netif, const ip4_addr_t *ipaddr, const ip4_addr_t *netmask,
+                    const ip4_addr_t *gw);
+#endif /* LWIP_IPV4 */
+void netif_remove(struct netif * netif);
+
+/* Returns a network interface given its name. The name is of the form
+   "et0", where the first two letters are the "name" field in the
+   netif structure, and the digit is in the num field in the same
+   structure. */
+struct netif *netif_find(const char *name);
+
+void netif_set_default(struct netif *netif);
+
+#if LWIP_IPV4
+void netif_set_ipaddr(struct netif *netif, const ip4_addr_t *ipaddr);
+void netif_set_netmask(struct netif *netif, const ip4_addr_t *netmask);
+void netif_set_gw(struct netif *netif, const ip4_addr_t *gw);
+#define netif_ip4_addr(netif)    ((const ip4_addr_t*)ip_2_ip4(&((netif)->ip_addr)))
+#define netif_ip4_netmask(netif) ((const ip4_addr_t*)ip_2_ip4(&((netif)->netmask)))
+#define netif_ip4_gw(netif)      ((const ip4_addr_t*)ip_2_ip4(&((netif)->gw)))
+#define netif_ip_addr4(netif)    ((const ip_addr_t*)&((netif)->ip_addr))
+#define netif_ip_gw4(netif)      ((const ip_addr_t*)&((netif)->gw))
+#endif /* LWIP_IPV4 */
+
+void netif_set_up(struct netif *netif);
+void netif_set_down(struct netif *netif);
+/** Ask if an interface is up */
+#define netif_is_up(netif) (((netif)->flags & NETIF_FLAG_UP) ? (u8_t)1 : (u8_t)0)
+
+#if LWIP_NETIF_STATUS_CALLBACK
+void netif_set_status_callback(struct netif *netif, netif_status_callback_fn status_callback);
+#endif /* LWIP_NETIF_STATUS_CALLBACK */
+#if LWIP_NETIF_REMOVE_CALLBACK
+void netif_set_remove_callback(struct netif *netif, netif_status_callback_fn remove_callback);
+#endif /* LWIP_NETIF_REMOVE_CALLBACK */
+
+void netif_set_link_up(struct netif *netif);
+void netif_set_link_down(struct netif *netif);
+/** Ask if a link is up */
+#define netif_is_link_up(netif) (((netif)->flags & NETIF_FLAG_LINK_UP) ? (u8_t)1 : (u8_t)0)
+
+#if LWIP_NETIF_LINK_CALLBACK
+void netif_set_link_callback(struct netif *netif, netif_status_callback_fn link_callback);
+#endif /* LWIP_NETIF_LINK_CALLBACK */
+
+#if LWIP_NETIF_HOSTNAME
+#define netif_set_hostname(netif, name) do { if((netif) != NULL) { (netif)->hostname = name; }}while(0)
+#define netif_get_hostname(netif) (((netif) != NULL) ? ((netif)->hostname) : NULL)
+#endif /* LWIP_NETIF_HOSTNAME */
+
+#if LWIP_IGMP
+#define netif_set_igmp_mac_filter(netif, function) do { if((netif) != NULL) { (netif)->igmp_mac_filter = function; }}while(0)
+#define netif_get_igmp_mac_filter(netif) (((netif) != NULL) ? ((netif)->igmp_mac_filter) : NULL)
+#endif /* LWIP_IGMP */
+
+#if LWIP_IPV6 && LWIP_IPV6_MLD
+#define netif_set_mld_mac_filter(netif, function) do { if((netif) != NULL) { (netif)->mld_mac_filter = function; }}while(0)
+#define netif_get_mld_mac_filter(netif) (((netif) != NULL) ? ((netif)->mld_mac_filter) : NULL)
+#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */
+
+#if ENABLE_LOOPBACK
+err_t netif_loop_output(struct netif *netif, struct pbuf *p);
+void netif_poll(struct netif *netif);
+#if !LWIP_NETIF_LOOPBACK_MULTITHREADING
+void netif_poll_all(void);
+#endif /* !LWIP_NETIF_LOOPBACK_MULTITHREADING */
+#endif /* ENABLE_LOOPBACK */
+
+#if LWIP_IPV6
+#define netif_ip_addr6(netif, i)  ((const ip_addr_t*)(&((netif)->ip6_addr[i])))
+#define netif_ip6_addr(netif, i)  ((const ip6_addr_t*)ip_2_ip6(&((netif)->ip6_addr[i])))
+#define netif_ip6_addr_set(netif, i, addr6) do { ip6_addr_set(ip_2_ip6(&((netif)->ip6_addr[i])), addr6); IP_SET_TYPE_VAL((netif)->ip6_addr[i], IPADDR_TYPE_V6); } while(0)
+#define netif_ip6_addr_state(netif, i)  ((netif)->ip6_addr_state[i])
+#define netif_ip6_addr_set_state(netif, i, state)  ((netif)->ip6_addr_state[i] = (state))
+s8_t netif_get_ip6_addr_match(struct netif *netif, const ip6_addr_t *ip6addr);
+void netif_create_ip6_linklocal_address(struct netif *netif, u8_t from_mac_48bit);
+err_t netif_add_ip6_address(struct netif *netif, const ip6_addr_t *ip6addr, s8_t *chosen_idx);
+#endif /* LWIP_IPV6 */
+
+#if LWIP_NETIF_HWADDRHINT
+#define NETIF_SET_HWADDRHINT(netif, hint) ((netif)->addr_hint = (hint))
+#else /* LWIP_NETIF_HWADDRHINT */
+#define NETIF_SET_HWADDRHINT(netif, hint)
+#endif /* LWIP_NETIF_HWADDRHINT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_NETIF_H */
diff --git a/tools/sdk/include/lwip/lwip/netifapi.h b/tools/sdk/include/lwip/lwip/netifapi.h
new file mode 100755
index 00000000..b09316be
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/netifapi.h
@@ -0,0 +1,108 @@
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+#ifndef LWIP_HDR_NETIFAPI_H
+#define LWIP_HDR_NETIFAPI_H
+
+#include "lwip/opt.h"
+
+#if LWIP_NETIF_API /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/sys.h"
+#include "lwip/netif.h"
+#include "lwip/dhcp.h"
+#include "lwip/autoip.h"
+#include "lwip/priv/tcpip_priv.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if LWIP_MPU_COMPATIBLE
+#define NETIFAPI_IPADDR_DEF(type, m)  type m
+#else /* LWIP_MPU_COMPATIBLE */
+#define NETIFAPI_IPADDR_DEF(type, m)  const type * m
+#endif /* LWIP_MPU_COMPATIBLE */
+
+typedef void (*netifapi_void_fn)(struct netif *netif);
+typedef err_t (*netifapi_errt_fn)(struct netif *netif);
+
+struct netifapi_msg {
+  struct tcpip_api_call call;
+  struct netif *netif;
+  union {
+    struct {
+#if LWIP_IPV4
+      NETIFAPI_IPADDR_DEF(ip4_addr_t, ipaddr);
+      NETIFAPI_IPADDR_DEF(ip4_addr_t, netmask);
+      NETIFAPI_IPADDR_DEF(ip4_addr_t, gw);
+#endif /* LWIP_IPV4 */
+      void *state;
+      netif_init_fn init;
+      netif_input_fn input;
+    } add;
+    struct {
+      netifapi_void_fn voidfunc;
+      netifapi_errt_fn errtfunc;
+    } common;
+  } msg;
+};
+
+
+/* API for application */
+err_t netifapi_netif_add(struct netif *netif,
+#if LWIP_IPV4
+                         const ip4_addr_t *ipaddr, const ip4_addr_t *netmask, const ip4_addr_t *gw,
+#endif /* LWIP_IPV4 */
+                         void *state, netif_init_fn init, netif_input_fn input);
+
+#if LWIP_IPV4
+err_t netifapi_netif_set_addr(struct netif *netif, const ip4_addr_t *ipaddr,
+                              const ip4_addr_t *netmask, const ip4_addr_t *gw);
+#endif /* LWIP_IPV4*/
+
+err_t netifapi_netif_common(struct netif *netif, netifapi_void_fn voidfunc,
+                            netifapi_errt_fn errtfunc);
+
+#define netifapi_netif_remove(n)      netifapi_netif_common(n, netif_remove, NULL)
+#define netifapi_netif_set_up(n)      netifapi_netif_common(n, netif_set_up, NULL)
+#define netifapi_netif_set_down(n)    netifapi_netif_common(n, netif_set_down, NULL)
+#define netifapi_netif_set_default(n) netifapi_netif_common(n, netif_set_default, NULL)
+#define netifapi_dhcp_start(n)        netifapi_netif_common(n, NULL, dhcp_start)
+#define netifapi_dhcp_stop(n)         netifapi_netif_common(n, dhcp_stop, NULL)
+#define netifapi_dhcp_inform(n)       netifapi_netif_common(n, dhcp_inform, NULL)
+#define netifapi_dhcp_renew(n)        netifapi_netif_common(n, NULL, dhcp_renew)
+#define netifapi_dhcp_release(n)      netifapi_netif_common(n, NULL, dhcp_release)
+#define netifapi_autoip_start(n)      netifapi_netif_common(n, NULL, autoip_start)
+#define netifapi_autoip_stop(n)       netifapi_netif_common(n, NULL, autoip_stop)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_NETIF_API */
+
+#endif /* LWIP_HDR_NETIFAPI_H */
diff --git a/tools/sdk/include/lwip/lwip/opt.h b/tools/sdk/include/lwip/lwip/opt.h
new file mode 100755
index 00000000..76fff880
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/opt.h
@@ -0,0 +1,3015 @@
+/**
+ * @file
+ *
+ * lwIP Options Configuration
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef LWIP_HDR_OPT_H
+#define LWIP_HDR_OPT_H
+
+/*
+ * Include user defined options first. Anything not defined in these files
+ * will be set to standard values. Override anything you don't like!
+ */
+#include "lwipopts.h"
+#include "lwip/debug.h"
+
+/*
+   -----------------------------------------------
+   ---------- Platform specific locking ----------
+   -----------------------------------------------
+*/
+
+/**
+ * SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain
+ * critical regions during buffer allocation, deallocation and memory
+ * allocation and deallocation.
+ */
+#ifndef SYS_LIGHTWEIGHT_PROT
+#define SYS_LIGHTWEIGHT_PROT            0
+#endif
+
+/**
+ * NO_SYS==1: Provides VERY minimal functionality. Otherwise,
+ * use lwIP facilities.
+ */
+#ifndef NO_SYS
+#define NO_SYS                          0
+#endif
+
+/**
+ * NO_SYS_NO_TIMERS==1: Drop support for sys_timeout when NO_SYS==1
+ * Mainly for compatibility to old versions.
+ */
+#ifndef NO_SYS_NO_TIMERS
+#define NO_SYS_NO_TIMERS                0
+#endif
+
+/**
+ * MEMCPY: override this if you have a faster implementation at hand than the
+ * one included in your C library
+ */
+#ifndef MEMCPY
+#define MEMCPY(dst,src,len)             memcpy(dst,src,len)
+#endif
+
+/**
+ * SMEMCPY: override this with care! Some compilers (e.g. gcc) can inline a
+ * call to memcpy() if the length is known at compile time and is small.
+ */
+#ifndef SMEMCPY
+#define SMEMCPY(dst,src,len)            memcpy(dst,src,len)
+#endif
+
+/**
+ * LWIP_MPU_COMPATIBLE: enables special memory management mechanism
+ * which makes lwip able to work on MPU (Memory Protection Unit) system
+ * by not passing stack-pointers to other threads
+ * (this decreases performance)
+ */
+#ifndef LWIP_MPU_COMPATIBLE
+#define LWIP_MPU_COMPATIBLE             0
+#endif
+
+/*
+   ------------------------------------
+   ---------- Memory options ----------
+   ------------------------------------
+*/
+/**
+ * MEM_LIBC_MALLOC==1: Use malloc/free/realloc provided by your C-library
+ * instead of the lwip internal allocator. Can save code size if you
+ * already use it.
+ */
+#ifndef MEM_LIBC_MALLOC
+#define MEM_LIBC_MALLOC                 0
+#endif
+
+/**
+* MEMP_MEM_MALLOC==1: Use mem_malloc/mem_free instead of the lwip pool allocator.
+* Especially useful with MEM_LIBC_MALLOC but handle with care regarding execution
+* speed and usage from interrupts!
+*/
+#ifndef MEMP_MEM_MALLOC
+#define MEMP_MEM_MALLOC                 0
+#endif
+
+/**
+ * MEM_ALIGNMENT: should be set to the alignment of the CPU
+ *    4 byte alignment -> #define MEM_ALIGNMENT 4
+ *    2 byte alignment -> #define MEM_ALIGNMENT 2
+ */
+#ifndef MEM_ALIGNMENT
+#define MEM_ALIGNMENT                   1
+#endif
+
+/**
+ * MEM_SIZE: the size of the heap memory. If the application will send
+ * a lot of data that needs to be copied, this should be set high.
+ */
+#ifndef MEM_SIZE
+#define MEM_SIZE                        1600
+#endif
+
+/**
+ * MEMP_OVERFLOW_CHECK: memp overflow protection reserves a configurable
+ * amount of bytes before and after each memp element in every pool and fills
+ * it with a prominent default value.
+ *    MEMP_OVERFLOW_CHECK == 0 no checking
+ *    MEMP_OVERFLOW_CHECK == 1 checks each element when it is freed
+ *    MEMP_OVERFLOW_CHECK >= 2 checks each element in every pool every time
+ *      memp_malloc() or memp_free() is called (useful but slow!)
+ */
+#ifndef MEMP_OVERFLOW_CHECK
+#define MEMP_OVERFLOW_CHECK             0
+#endif
+
+/**
+ * MEMP_SANITY_CHECK==1: run a sanity check after each memp_free() to make
+ * sure that there are no cycles in the linked lists.
+ */
+#ifndef MEMP_SANITY_CHECK
+#define MEMP_SANITY_CHECK               0
+#endif
+
+/**
+ * MEM_USE_POOLS==1: Use an alternative to malloc() by allocating from a set
+ * of memory pools of various sizes. When mem_malloc is called, an element of
+ * the smallest pool that can provide the length needed is returned.
+ * To use this, MEMP_USE_CUSTOM_POOLS also has to be enabled.
+ */
+#ifndef MEM_USE_POOLS
+#define MEM_USE_POOLS                   0
+#endif
+
+/**
+ * MEM_USE_POOLS_TRY_BIGGER_POOL==1: if one malloc-pool is empty, try the next
+ * bigger pool - WARNING: THIS MIGHT WASTE MEMORY but it can make a system more
+ * reliable. */
+#ifndef MEM_USE_POOLS_TRY_BIGGER_POOL
+#define MEM_USE_POOLS_TRY_BIGGER_POOL   0
+#endif
+
+/**
+ * MEMP_USE_CUSTOM_POOLS==1: whether to include a user file lwippools.h
+ * that defines additional pools beyond the "standard" ones required
+ * by lwIP. If you set this to 1, you must have lwippools.h in your
+ * include path somewhere.
+ */
+#ifndef MEMP_USE_CUSTOM_POOLS
+#define MEMP_USE_CUSTOM_POOLS           0
+#endif
+
+/**
+ * Set this to 1 if you want to free PBUF_RAM pbufs (or call mem_free()) from
+ * interrupt context (or another context that doesn't allow waiting for a
+ * semaphore).
+ * If set to 1, mem_malloc will be protected by a semaphore and SYS_ARCH_PROTECT,
+ * while mem_free will only use SYS_ARCH_PROTECT. mem_malloc SYS_ARCH_UNPROTECTs
+ * with each loop so that mem_free can run.
+ *
+ * ATTENTION: As you can see from the above description, this leads to dis-/
+ * enabling interrupts often, which can be slow! Also, on low memory, mem_malloc
+ * can need longer.
+ *
+ * If you don't want that, at least for NO_SYS=0, you can still use the following
+ * functions to enqueue a deallocation call which then runs in the tcpip_thread
+ * context:
+ * - pbuf_free_callback(p);
+ * - mem_free_callback(m);
+ */
+#ifndef LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
+#define LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT 0
+#endif
+
+/*
+   ------------------------------------------------
+   ---------- Internal Memory Pool Sizes ----------
+   ------------------------------------------------
+*/
+/**
+ * MEMP_NUM_PBUF: the number of memp struct pbufs (used for PBUF_ROM and PBUF_REF).
+ * If the application sends a lot of data out of ROM (or other static memory),
+ * this should be set high.
+ */
+#ifndef MEMP_NUM_PBUF
+#define MEMP_NUM_PBUF                   16
+#endif
+
+/**
+ * MEMP_NUM_RAW_PCB: Number of raw connection PCBs
+ * (requires the LWIP_RAW option)
+ */
+#ifndef MEMP_NUM_RAW_PCB
+#define MEMP_NUM_RAW_PCB                4
+#endif
+
+/**
+ * MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
+ * per active UDP "connection".
+ * (requires the LWIP_UDP option)
+ */
+#ifndef MEMP_NUM_UDP_PCB
+#define MEMP_NUM_UDP_PCB                4
+#endif
+
+/**
+ * MEMP_NUM_TCP_PCB: the number of simultaneously active TCP connections.
+ * (requires the LWIP_TCP option)
+ */
+#ifndef MEMP_NUM_TCP_PCB
+#define MEMP_NUM_TCP_PCB                5
+#endif
+
+/**
+ * MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP connections.
+ * (requires the LWIP_TCP option)
+ */
+#ifndef MEMP_NUM_TCP_PCB_LISTEN
+#define MEMP_NUM_TCP_PCB_LISTEN         8
+#endif
+
+/**
+ * MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP segments.
+ * (requires the LWIP_TCP option)
+ */
+#ifndef MEMP_NUM_TCP_SEG
+#define MEMP_NUM_TCP_SEG                16
+#endif
+
+/**
+ * MEMP_NUM_REASSDATA: the number of IP packets simultaneously queued for
+ * reassembly (whole packets, not fragments!)
+ */
+#ifndef MEMP_NUM_REASSDATA
+#define MEMP_NUM_REASSDATA              5
+#endif
+
+/**
+ * MEMP_NUM_FRAG_PBUF: the number of IP fragments simultaneously sent
+ * (fragments, not whole packets!).
+ * This is only used with IP_FRAG_USES_STATIC_BUF==0 and
+ * LWIP_NETIF_TX_SINGLE_PBUF==0 and only has to be > 1 with DMA-enabled MACs
+ * where the packet is not yet sent when netif->output returns.
+ */
+#ifndef MEMP_NUM_FRAG_PBUF
+#define MEMP_NUM_FRAG_PBUF              15
+#endif
+
+/**
+ * MEMP_NUM_ARP_QUEUE: the number of simultaneously queued outgoing
+ * packets (pbufs) that are waiting for an ARP request (to resolve
+ * their destination address) to finish.
+ * (requires the ARP_QUEUEING option)
+ */
+#ifndef MEMP_NUM_ARP_QUEUE
+#define MEMP_NUM_ARP_QUEUE              30
+#endif
+
+/**
+ * MEMP_NUM_IGMP_GROUP: The number of multicast groups whose network interfaces
+ * can be members at the same time (one per netif - allsystems group -, plus one
+ * per netif membership).
+ * (requires the LWIP_IGMP option)
+ */
+#ifndef MEMP_NUM_IGMP_GROUP
+#define MEMP_NUM_IGMP_GROUP             8
+#endif
+
+/**
+ * MEMP_NUM_SYS_TIMEOUT: the number of simultaneously active timeouts.
+ * The default number of timeouts is calculated here for all enabled modules.
+ * The formula expects settings to be either '0' or '1'.
+ */
+#ifndef MEMP_NUM_SYS_TIMEOUT
+#define MEMP_NUM_SYS_TIMEOUT            (LWIP_TCP + IP_REASSEMBLY + LWIP_ARP + (2*LWIP_DHCP) + LWIP_AUTOIP + LWIP_IGMP + LWIP_DNS + (PPP_SUPPORT*6*MEMP_NUM_PPP_PCB) + (LWIP_IPV6 ? (1 + LWIP_IPV6_REASS + LWIP_IPV6_MLD) : 0))
+#endif
+
+/**
+ * MEMP_NUM_NETBUF: the number of struct netbufs.
+ * (only needed if you use the sequential API, like api_lib.c)
+ */
+#ifndef MEMP_NUM_NETBUF
+#define MEMP_NUM_NETBUF                 2
+#endif
+
+/**
+ * MEMP_NUM_NETCONN: the number of struct netconns.
+ * (only needed if you use the sequential API, like api_lib.c)
+ */
+#ifndef MEMP_NUM_NETCONN
+#define MEMP_NUM_NETCONN                4
+#endif
+
+/**
+ * MEMP_NUM_TCPIP_MSG_API: the number of struct tcpip_msg, which are used
+ * for callback/timeout API communication.
+ * (only needed if you use tcpip.c)
+ */
+#ifndef MEMP_NUM_TCPIP_MSG_API
+#define MEMP_NUM_TCPIP_MSG_API          8
+#endif
+
+/**
+ * MEMP_NUM_TCPIP_MSG_INPKT: the number of struct tcpip_msg, which are used
+ * for incoming packets.
+ * (only needed if you use tcpip.c)
+ */
+#ifndef MEMP_NUM_TCPIP_MSG_INPKT
+#define MEMP_NUM_TCPIP_MSG_INPKT        8
+#endif
+
+/**
+ * MEMP_NUM_NETDB: the number of concurrently running lwip_addrinfo() calls
+ * (before freeing the corresponding memory using lwip_freeaddrinfo()).
+ */
+#ifndef MEMP_NUM_NETDB
+#define MEMP_NUM_NETDB                  1
+#endif
+
+/**
+ * MEMP_NUM_LOCALHOSTLIST: the number of host entries in the local host list
+ * if DNS_LOCAL_HOSTLIST_IS_DYNAMIC==1.
+ */
+#ifndef MEMP_NUM_LOCALHOSTLIST
+#define MEMP_NUM_LOCALHOSTLIST          1
+#endif
+
+/**
+ * MEMP_NUM_PPP_PCB: the number of simultaneously active PPP
+ * connections (requires the PPP_SUPPORT option)
+ */
+#ifndef MEMP_NUM_PPP_PCB
+#define MEMP_NUM_PPP_PCB       1
+#endif
+
+/**
+ * MEMP_NUM_PPPOS_INTERFACES: the number of concurrently active PPPoS
+ * interfaces (only used with PPPOS_SUPPORT==1)
+ */
+#ifndef MEMP_NUM_PPPOS_INTERFACES
+#define MEMP_NUM_PPPOS_INTERFACES       MEMP_NUM_PPP_PCB
+#endif
+
+/**
+ * MEMP_NUM_PPPOE_INTERFACES: the number of concurrently active PPPoE
+ * interfaces (only used with PPPOE_SUPPORT==1)
+ */
+#ifndef MEMP_NUM_PPPOE_INTERFACES
+#define MEMP_NUM_PPPOE_INTERFACES       1
+#endif
+
+/**
+ * MEMP_NUM_PPPOL2TP_INTERFACES: the number of concurrently active PPPoL2TP
+ * interfaces (only used with PPPOL2TP_SUPPORT==1)
+ */
+#ifndef MEMP_NUM_PPPOL2TP_INTERFACES
+#define MEMP_NUM_PPPOL2TP_INTERFACES       1
+#endif
+
+/**
+ * PBUF_POOL_SIZE: the number of buffers in the pbuf pool.
+ */
+#ifndef PBUF_POOL_SIZE
+#define PBUF_POOL_SIZE                  16
+#endif
+
+/** MEMP_NUM_API_MSG: the number of concurrently active calls to various
+ * socket, netconn, and tcpip functions
+ */
+#ifndef MEMP_NUM_API_MSG
+#define MEMP_NUM_API_MSG                MEMP_NUM_TCPIP_MSG_API
+#endif
+
+/** MEMP_NUM_DNS_API_MSG: the number of concurrently active calls to netconn_gethostbyname
+ */
+#ifndef MEMP_NUM_DNS_API_MSG
+#define MEMP_NUM_DNS_API_MSG            MEMP_NUM_TCPIP_MSG_API
+#endif
+
+/** MEMP_NUM_SOCKET_SETGETSOCKOPT_DATA: the number of concurrently active calls
+ * to getsockopt/setsockopt
+ */
+#ifndef MEMP_NUM_SOCKET_SETGETSOCKOPT_DATA
+#define MEMP_NUM_SOCKET_SETGETSOCKOPT_DATA MEMP_NUM_TCPIP_MSG_API
+#endif
+
+/** MEMP_NUM_NETIFAPI_MSG: the number of concurrently active calls to the
+ * netifapi functions
+ */
+#ifndef MEMP_NUM_NETIFAPI_MSG
+#define MEMP_NUM_NETIFAPI_MSG           MEMP_NUM_TCPIP_MSG_API
+#endif
+
+/*
+   ---------------------------------
+   ---------- ARP options ----------
+   ---------------------------------
+*/
+/**
+ * LWIP_ARP==1: Enable ARP functionality.
+ */
+#ifndef LWIP_ARP
+#define LWIP_ARP                        1
+#endif
+
+/**
+ * ARP_TABLE_SIZE: Number of active MAC-IP address pairs cached.
+ */
+#ifndef ARP_TABLE_SIZE
+#define ARP_TABLE_SIZE                  10
+#endif
+
+/** the time an ARP entry stays valid after its last update,
+ *  for ARP_TMR_INTERVAL = 1000, this is
+ *  (60 * 5) seconds = 5 minutes.
+ */
+#ifndef ARP_MAXAGE
+#define ARP_MAXAGE                      300
+#endif
+
+/**
+ * ARP_QUEUEING==1: Multiple outgoing packets are queued during hardware address
+ * resolution. By default, only the most recent packet is queued per IP address.
+ * This is sufficient for most protocols and mainly reduces TCP connection
+ * startup time. Set this to 1 if you know your application sends more than one
+ * packet in a row to an IP address that is not in the ARP cache.
+ */
+#ifndef ARP_QUEUEING
+#define ARP_QUEUEING                    0
+#endif
+
+/** The maximum number of packets which may be queued for each
+ *  unresolved address by other network layers. Defaults to 3, 0 means disabled.
+ *  Old packets are dropped, new packets are queued.
+ */
+#ifndef ARP_QUEUE_LEN
+#define ARP_QUEUE_LEN                   3
+#endif
+
+/**
+ * ETHARP_TRUST_IP_MAC==1: Incoming IP packets cause the ARP table to be
+ * updated with the source MAC and IP addresses supplied in the packet.
+ * You may want to disable this if you do not trust LAN peers to have the
+ * correct addresses, or as a limited approach to attempt to handle
+ * spoofing. If disabled, lwIP will need to make a new ARP request if
+ * the peer is not already in the ARP table, adding a little latency.
+ * The peer *is* in the ARP table if it requested our address before.
+ * Also notice that this slows down input processing of every IP packet!
+ */
+#ifndef ETHARP_TRUST_IP_MAC
+#define ETHARP_TRUST_IP_MAC             0
+#endif
+
+/**
+ * ETHARP_SUPPORT_VLAN==1: support receiving and sending ethernet packets with
+ * VLAN header. See the description of LWIP_HOOK_VLAN_CHECK and
+ * LWIP_HOOK_VLAN_SET hooks to check/set VLAN headers.
+ * Additionally, you can define ETHARP_VLAN_CHECK to an u16_t VLAN ID to check.
+ * If ETHARP_VLAN_CHECK is defined, only VLAN-traffic for this VLAN is accepted.
+ * If ETHARP_VLAN_CHECK is not defined, all traffic is accepted.
+ * Alternatively, define a function/define ETHARP_VLAN_CHECK_FN(eth_hdr, vlan)
+ * that returns 1 to accept a packet or 0 to drop a packet.
+ */
+#ifndef ETHARP_SUPPORT_VLAN
+#define ETHARP_SUPPORT_VLAN             0
+#endif
+
+/** LWIP_ETHERNET==1: enable ethernet support for PPPoE even though ARP
+ * might be disabled
+ */
+#ifndef LWIP_ETHERNET
+#define LWIP_ETHERNET                   (LWIP_ARP || PPPOE_SUPPORT)
+#endif
+
+/** ETH_PAD_SIZE: number of bytes added before the ethernet header to ensure
+ * alignment of payload after that header. Since the header is 14 bytes long,
+ * without this padding e.g. addresses in the IP header will not be aligned
+ * on a 32-bit boundary, so setting this to 2 can speed up 32-bit-platforms.
+ */
+#ifndef ETH_PAD_SIZE
+#define ETH_PAD_SIZE                    0
+#endif
+
+/** ETHARP_SUPPORT_STATIC_ENTRIES==1: enable code to support static ARP table
+ * entries (using etharp_add_static_entry/etharp_remove_static_entry).
+ */
+#ifndef ETHARP_SUPPORT_STATIC_ENTRIES
+#define ETHARP_SUPPORT_STATIC_ENTRIES   0
+#endif
+
+/** ETHARP_TABLE_MATCH_NETIF==1: Match netif for ARP table entries.
+ * If disabled, duplicate IP address on multiple netifs are not supported
+ * (but this should only occur for AutoIP).
+ */
+#ifndef ETHARP_TABLE_MATCH_NETIF
+#define ETHARP_TABLE_MATCH_NETIF        0
+#endif
+
+/*
+   --------------------------------
+   ---------- IP options ----------
+   --------------------------------
+*/
+/**
+ * LWIP_IPV4==1: Enable IPv4
+ */
+#ifndef LWIP_IPV4
+#define LWIP_IPV4                       1
+#endif
+
+/**
+ * IP_FORWARD==1: Enables the ability to forward IP packets across network
+ * interfaces. If you are going to run lwIP on a device with only one network
+ * interface, define this to 0.
+ */
+#ifndef IP_FORWARD
+#define IP_FORWARD                      0
+#endif
+
+/**
+ * IP_REASSEMBLY==1: Reassemble incoming fragmented IP packets. Note that
+ * this option does not affect outgoing packet sizes, which can be controlled
+ * via IP_FRAG.
+ */
+#ifndef IP_REASSEMBLY
+#define IP_REASSEMBLY                   1
+#endif
+
+/**
+ * IP_FRAG==1: Fragment outgoing IP packets if their size exceeds MTU. Note
+ * that this option does not affect incoming packet sizes, which can be
+ * controlled via IP_REASSEMBLY.
+ */
+#ifndef IP_FRAG
+#define IP_FRAG                         1
+#endif
+
+#if !LWIP_IPV4
+/* disable IPv4 extensions when IPv4 is disabled */
+#undef IP_FORWARD
+#define IP_FORWARD                      0
+#undef IP_REASSEMBLY
+#define IP_REASSEMBLY                   0
+#undef IP_FRAG
+#define IP_FRAG                         0
+#endif /* !LWIP_IPV4 */
+
+/**
+ * IP_OPTIONS_ALLOWED: Defines the behavior for IP options.
+ *      IP_OPTIONS_ALLOWED==0: All packets with IP options are dropped.
+ *      IP_OPTIONS_ALLOWED==1: IP options are allowed (but not parsed).
+ */
+#ifndef IP_OPTIONS_ALLOWED
+#define IP_OPTIONS_ALLOWED              1
+#endif
+
+/**
+ * IP_REASS_MAXAGE: Maximum time (in multiples of IP_TMR_INTERVAL - so seconds, normally)
+ * a fragmented IP packet waits for all fragments to arrive. If not all fragments arrived
+ * in this time, the whole packet is discarded.
+ */
+#ifndef IP_REASS_MAXAGE
+#define IP_REASS_MAXAGE                 3
+#endif
+
+/**
+ * IP_REASS_MAX_PBUFS: Total maximum amount of pbufs waiting to be reassembled.
+ * Since the received pbufs are enqueued, be sure to configure
+ * PBUF_POOL_SIZE > IP_REASS_MAX_PBUFS so that the stack is still able to receive
+ * packets even if the maximum amount of fragments is enqueued for reassembly!
+ */
+#ifndef IP_REASS_MAX_PBUFS
+#define IP_REASS_MAX_PBUFS              10
+#endif
+
+/**
+ * IP_FRAG_USES_STATIC_BUF==1: Use a static MTU-sized buffer for IP
+ * fragmentation. Otherwise pbufs are allocated and reference the original
+ * packet data to be fragmented (or with LWIP_NETIF_TX_SINGLE_PBUF==1,
+ * new PBUF_RAM pbufs are used for fragments).
+ * ATTENTION: IP_FRAG_USES_STATIC_BUF==1 may not be used for DMA-enabled MACs!
+ */
+#ifndef IP_FRAG_USES_STATIC_BUF
+#define IP_FRAG_USES_STATIC_BUF         0
+#endif
+
+/**
+ * IP_FRAG_MAX_MTU: Assumed max MTU on any interface for IP frag buffer
+ * (requires IP_FRAG_USES_STATIC_BUF==1)
+ */
+#if IP_FRAG_USES_STATIC_BUF && !defined(IP_FRAG_MAX_MTU)
+#define IP_FRAG_MAX_MTU                 1500
+#endif
+
+/**
+ * IP_DEFAULT_TTL: Default value for Time-To-Live used by transport layers.
+ */
+#ifndef IP_DEFAULT_TTL
+#define IP_DEFAULT_TTL                  255
+#endif
+
+/**
+ * IP_SOF_BROADCAST=1: Use the SOF_BROADCAST field to enable broadcast
+ * filter per pcb on udp and raw send operations. To enable broadcast filter
+ * on recv operations, you also have to set IP_SOF_BROADCAST_RECV=1.
+ */
+#ifndef IP_SOF_BROADCAST
+#define IP_SOF_BROADCAST                0
+#endif
+
+/**
+ * IP_SOF_BROADCAST_RECV (requires IP_SOF_BROADCAST=1) enable the broadcast
+ * filter on recv operations.
+ */
+#ifndef IP_SOF_BROADCAST_RECV
+#define IP_SOF_BROADCAST_RECV           0
+#endif
+
+/**
+ * IP_FORWARD_ALLOW_TX_ON_RX_NETIF==1: allow ip_forward() to send packets back
+ * out on the netif where it was received. This should only be used for
+ * wireless networks.
+ * ATTENTION: When this is 1, make sure your netif driver correctly marks incoming
+ * link-layer-broadcast/multicast packets as such using the corresponding pbuf flags!
+ */
+#ifndef IP_FORWARD_ALLOW_TX_ON_RX_NETIF
+#define IP_FORWARD_ALLOW_TX_ON_RX_NETIF 0
+#endif
+
+/**
+ * LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS==1: randomize the local port for the first
+ * local TCP/UDP pcb (default==0). This can prevent creating predictable port
+ * numbers after booting a device.
+ */
+#ifndef LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS
+#define LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS 0
+#endif
+
+/*
+   ----------------------------------
+   ---------- ICMP options ----------
+   ----------------------------------
+*/
+/**
+ * LWIP_ICMP==1: Enable ICMP module inside the IP stack.
+ * Be careful, disable that make your product non-compliant to RFC1122
+ */
+#ifndef LWIP_ICMP
+#define LWIP_ICMP                       1
+#endif
+
+/**
+ * ICMP_TTL: Default value for Time-To-Live used by ICMP packets.
+ */
+#ifndef ICMP_TTL
+#define ICMP_TTL                       (IP_DEFAULT_TTL)
+#endif
+
+/**
+ * LWIP_BROADCAST_PING==1: respond to broadcast pings (default is unicast only)
+ */
+#ifndef LWIP_BROADCAST_PING
+#define LWIP_BROADCAST_PING             0
+#endif
+
+/**
+ * LWIP_MULTICAST_PING==1: respond to multicast pings (default is unicast only)
+ */
+#ifndef LWIP_MULTICAST_PING
+#define LWIP_MULTICAST_PING             0
+#endif
+
+/*
+   ---------------------------------
+   ---------- RAW options ----------
+   ---------------------------------
+*/
+/**
+ * LWIP_RAW==1: Enable application layer to hook into the IP layer itself.
+ */
+#ifndef LWIP_RAW
+#define LWIP_RAW                        0
+#endif
+
+/**
+ * LWIP_RAW==1: Enable application layer to hook into the IP layer itself.
+ */
+#ifndef RAW_TTL
+#define RAW_TTL                        (IP_DEFAULT_TTL)
+#endif
+
+/*
+   ----------------------------------
+   ---------- DHCP options ----------
+   ----------------------------------
+*/
+/**
+ * LWIP_DHCP==1: Enable DHCP module.
+ */
+#ifndef LWIP_DHCP
+#define LWIP_DHCP                       0
+#endif
+#if !LWIP_IPV4
+/* disable DHCP when IPv4 is disabled */
+#undef LWIP_DHCP
+#define LWIP_DHCP                       0
+#endif /* !LWIP_IPV4 */
+
+/**
+ * DHCP_DOES_ARP_CHECK==1: Do an ARP check on the offered address.
+ */
+#ifndef DHCP_DOES_ARP_CHECK
+#define DHCP_DOES_ARP_CHECK             ((LWIP_DHCP) && (LWIP_ARP))
+#endif
+
+/**
+ * LWIP_DHCP_CHECK_LINK_UP==1: dhcp_start() only really starts if the netif has
+ * NETIF_FLAG_LINK_UP set in its flags. As this is only an optimization and
+ * netif drivers might not set this flag, the default is off. If enabled,
+ * netif_set_link_up() must be called to continue dhcp starting.
+ */
+#ifndef LWIP_DHCP_CHECK_LINK_UP
+#define LWIP_DHCP_CHECK_LINK_UP         0
+#endif
+
+/**
+ * LWIP_DHCP_BOOTP_FILE==1: Store offered_si_addr and boot_file_name.
+ */
+#ifndef LWIP_DHCP_BOOTP_FILE
+#define LWIP_DHCP_BOOTP_FILE            0
+#endif
+
+/**
+ * LWIP_DHCP_GETS_NTP==1: Request NTP servers with discover/select. For each
+ * response packet, an callback is called, which has to be provided by the port:
+ * void dhcp_set_ntp_servers(u8_t num_ntp_servers, ip_addr_t* ntp_server_addrs);
+*/
+#ifndef LWIP_DHCP_GET_NTP_SRV
+#define LWIP_DHCP_GET_NTP_SRV           0
+#endif
+
+/**
+ * The maximum of NTP servers requested
+ */
+#ifndef LWIP_DHCP_MAX_NTP_SERVERS
+#define LWIP_DHCP_MAX_NTP_SERVERS       1
+#endif
+
+/*
+   ------------------------------------
+   ---------- AUTOIP options ----------
+   ------------------------------------
+*/
+/**
+ * LWIP_AUTOIP==1: Enable AUTOIP module.
+ */
+#ifndef LWIP_AUTOIP
+#define LWIP_AUTOIP                     0
+#endif
+#if !LWIP_IPV4
+/* disable AUTOIP when IPv4 is disabled */
+#undef LWIP_AUTOIP
+#define LWIP_AUTOIP                     0
+#endif /* !LWIP_IPV4 */
+
+/**
+ * LWIP_DHCP_AUTOIP_COOP==1: Allow DHCP and AUTOIP to be both enabled on
+ * the same interface at the same time.
+ */
+#ifndef LWIP_DHCP_AUTOIP_COOP
+#define LWIP_DHCP_AUTOIP_COOP           0
+#endif
+
+/**
+ * LWIP_DHCP_AUTOIP_COOP_TRIES: Set to the number of DHCP DISCOVER probes
+ * that should be sent before falling back on AUTOIP. This can be set
+ * as low as 1 to get an AutoIP address very quickly, but you should
+ * be prepared to handle a changing IP address when DHCP overrides
+ * AutoIP.
+ */
+#ifndef LWIP_DHCP_AUTOIP_COOP_TRIES
+#define LWIP_DHCP_AUTOIP_COOP_TRIES     9
+#endif
+
+/*
+   ----------------------------------
+   ----- SNMP MIB2 support      -----
+   ----------------------------------
+*/
+/**
+ * LWIP_MIB2_CALLBACKS==1: Turn on SNMP MIB2 callbacks.
+ * Turn this on to get callbacks needed to implement MIB2.
+ * Usually MIB2_STATS should be enabled, too.
+ */
+#ifndef LWIP_MIB2_CALLBACKS
+#define LWIP_MIB2_CALLBACKS             0
+#endif
+
+/*
+   ----------------------------------
+   ----- Multicast/IGMP options -----
+   ----------------------------------
+*/
+/**
+ * LWIP_IGMP==1: Turn on IGMP module.
+ */
+#ifndef LWIP_IGMP
+#define LWIP_IGMP                       1
+#endif
+#if !LWIP_IPV4
+#undef LWIP_IGMP
+#define LWIP_IGMP                       0
+#endif
+
+/**
+ * LWIP_MULTICAST_TX_OPTIONS==1: Enable multicast TX support like the socket options
+ * IP_MULTICAST_TTL/IP_MULTICAST_IF/IP_MULTICAST_LOOP
+ */
+#ifndef LWIP_MULTICAST_TX_OPTIONS
+#define LWIP_MULTICAST_TX_OPTIONS       LWIP_IGMP
+#endif
+
+/*
+   ----------------------------------
+   ---------- DNS options -----------
+   ----------------------------------
+*/
+/**
+ * LWIP_DNS==1: Turn on DNS module. UDP must be available for DNS
+ * transport.
+ */
+#ifndef LWIP_DNS
+#define LWIP_DNS                        0
+#endif
+
+/** DNS maximum number of entries to maintain locally. */
+#ifndef DNS_TABLE_SIZE
+#define DNS_TABLE_SIZE                  4
+#endif
+
+/** DNS maximum host name length supported in the name table. */
+#ifndef DNS_MAX_NAME_LENGTH
+#define DNS_MAX_NAME_LENGTH             256
+#endif
+
+/** The maximum of DNS servers
+ * The first server can be initialized automatically by defining
+ * DNS_SERVER_ADDRESS(ipaddr), where 'ipaddr' is an 'ip_addr_t*'
+ */
+#ifndef DNS_MAX_SERVERS
+#define DNS_MAX_SERVERS                 2
+#endif
+
+/** DNS do a name checking between the query and the response. */
+#ifndef DNS_DOES_NAME_CHECK
+#define DNS_DOES_NAME_CHECK             1
+#endif
+
+/** LWIP_DNS_SECURE: controls the security level of the DNS implementation
+ * Use all DNS security features by default.
+ * This is overridable but should only be needed by very small targets
+ * or when using against non standard DNS servers. */
+#ifndef LWIP_DNS_SECURE
+#define LWIP_DNS_SECURE (LWIP_DNS_SECURE_RAND_XID | LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING | LWIP_DNS_SECURE_RAND_SRC_PORT)
+#endif
+/* A list of DNS security features follows */
+#define LWIP_DNS_SECURE_RAND_XID                1
+#define LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING 2
+#define LWIP_DNS_SECURE_RAND_SRC_PORT           4
+
+/** DNS_LOCAL_HOSTLIST: Implements a local host-to-address list. If enabled,
+ *  you have to define
+ *    #define DNS_LOCAL_HOSTLIST_INIT {{"host1", 0x123}, {"host2", 0x234}}
+ *  (an array of structs name/address, where address is an u32_t in network
+ *  byte order).
+ *
+ *  Instead, you can also use an external function:
+ *  #define DNS_LOOKUP_LOCAL_EXTERN(x) extern u32_t my_lookup_function(const char *name)
+ *  that returns the IP address or INADDR_NONE if not found.
+ */
+#ifndef DNS_LOCAL_HOSTLIST
+#define DNS_LOCAL_HOSTLIST              0
+#endif /* DNS_LOCAL_HOSTLIST */
+
+/** If this is turned on, the local host-list can be dynamically changed
+ *  at runtime. */
+#ifndef DNS_LOCAL_HOSTLIST_IS_DYNAMIC
+#define DNS_LOCAL_HOSTLIST_IS_DYNAMIC   0
+#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */
+
+/*
+   ---------------------------------
+   ---------- UDP options ----------
+   ---------------------------------
+*/
+/**
+ * LWIP_UDP==1: Turn on UDP.
+ */
+#ifndef LWIP_UDP
+#define LWIP_UDP                        1
+#endif
+
+/**
+ * LWIP_UDPLITE==1: Turn on UDP-Lite. (Requires LWIP_UDP)
+ */
+#ifndef LWIP_UDPLITE
+#define LWIP_UDPLITE                    0
+#endif
+
+/**
+ * UDP_TTL: Default Time-To-Live value.
+ */
+#ifndef UDP_TTL
+#define UDP_TTL                         (IP_DEFAULT_TTL)
+#endif
+
+/**
+ * LWIP_NETBUF_RECVINFO==1: append destination addr and port to every netbuf.
+ */
+#ifndef LWIP_NETBUF_RECVINFO
+#define LWIP_NETBUF_RECVINFO            0
+#endif
+
+/*
+   ---------------------------------
+   ---------- TCP options ----------
+   ---------------------------------
+*/
+/**
+ * LWIP_TCP==1: Turn on TCP.
+ */
+#ifndef LWIP_TCP
+#define LWIP_TCP                        1
+#endif
+
+/**
+ * TCP_TTL: Default Time-To-Live value.
+ */
+#ifndef TCP_TTL
+#define TCP_TTL                         (IP_DEFAULT_TTL)
+#endif
+
+/**
+ * TCP_WND: The size of a TCP window.  This must be at least
+ * (2 * TCP_MSS) for things to work well
+ */
+#ifndef TCP_WND
+#define TCP_WND                         (4 * TCP_MSS)
+#endif
+
+/**
+ * TCP_MAXRTX: Maximum number of retransmissions of data segments.
+ */
+#ifndef TCP_MAXRTX
+#define TCP_MAXRTX                      12
+#endif
+
+/**
+ * TCP_SYNMAXRTX: Maximum number of retransmissions of SYN segments.
+ */
+#ifndef TCP_SYNMAXRTX
+#define TCP_SYNMAXRTX                   6
+#endif
+
+/**
+ * TCP_QUEUE_OOSEQ==1: TCP will queue segments that arrive out of order.
+ * Define to 0 if your device is low on memory.
+ */
+#ifndef TCP_QUEUE_OOSEQ
+#define TCP_QUEUE_OOSEQ                 (LWIP_TCP)
+#endif
+
+/**
+ * TCP_MSS: TCP Maximum segment size. (default is 536, a conservative default,
+ * you might want to increase this.)
+ * For the receive side, this MSS is advertised to the remote side
+ * when opening a connection. For the transmit size, this MSS sets
+ * an upper limit on the MSS advertised by the remote host.
+ */
+#ifndef TCP_MSS
+#define TCP_MSS                         536
+#endif
+
+/**
+ * TCP_CALCULATE_EFF_SEND_MSS: "The maximum size of a segment that TCP really
+ * sends, the 'effective send MSS,' MUST be the smaller of the send MSS (which
+ * reflects the available reassembly buffer size at the remote host) and the
+ * largest size permitted by the IP layer" (RFC 1122)
+ * Setting this to 1 enables code that checks TCP_MSS against the MTU of the
+ * netif used for a connection and limits the MSS if it would be too big otherwise.
+ */
+#ifndef TCP_CALCULATE_EFF_SEND_MSS
+#define TCP_CALCULATE_EFF_SEND_MSS      1
+#endif
+
+
+/**
+ * TCP_SND_BUF: TCP sender buffer space (bytes).
+ * To achieve good performance, this should be at least 2 * TCP_MSS.
+ */
+#ifndef TCP_SND_BUF
+#define TCP_SND_BUF                     (2 * TCP_MSS)
+#endif
+
+/**
+ * TCP_SND_QUEUELEN: TCP sender buffer space (pbufs). This must be at least
+ * as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work.
+ */
+#ifndef TCP_SND_QUEUELEN
+#define TCP_SND_QUEUELEN                ((4 * (TCP_SND_BUF) + (TCP_MSS - 1))/(TCP_MSS))
+#endif
+
+/**
+ * TCP_SNDLOWAT: TCP writable space (bytes). This must be less than
+ * TCP_SND_BUF. It is the amount of space which must be available in the
+ * TCP snd_buf for select to return writable (combined with TCP_SNDQUEUELOWAT).
+ */
+#ifndef TCP_SNDLOWAT
+#define TCP_SNDLOWAT                    LWIP_MIN(LWIP_MAX(((TCP_SND_BUF)/2), (2 * TCP_MSS) + 1), (TCP_SND_BUF) - 1)
+#endif
+
+/**
+ * TCP_SNDQUEUELOWAT: TCP writable bufs (pbuf count). This must be less
+ * than TCP_SND_QUEUELEN. If the number of pbufs queued on a pcb drops below
+ * this number, select returns writable (combined with TCP_SNDLOWAT).
+ */
+#ifndef TCP_SNDQUEUELOWAT
+#define TCP_SNDQUEUELOWAT               LWIP_MAX(((TCP_SND_QUEUELEN)/2), 5)
+#endif
+
+/**
+ * TCP_OOSEQ_MAX_BYTES: The maximum number of bytes queued on ooseq per pcb.
+ * Default is 0 (no limit). Only valid for TCP_QUEUE_OOSEQ==0.
+ */
+#ifndef TCP_OOSEQ_MAX_BYTES
+#define TCP_OOSEQ_MAX_BYTES             0
+#endif
+
+/**
+ * TCP_OOSEQ_MAX_PBUFS: The maximum number of pbufs queued on ooseq per pcb.
+ * Default is 0 (no limit). Only valid for TCP_QUEUE_OOSEQ==0.
+ */
+#ifndef TCP_OOSEQ_MAX_PBUFS
+#define TCP_OOSEQ_MAX_PBUFS             0
+#endif
+
+/**
+ * TCP_LISTEN_BACKLOG: Enable the backlog option for tcp listen pcb.
+ */
+#ifndef TCP_LISTEN_BACKLOG
+#define TCP_LISTEN_BACKLOG              0
+#endif
+
+/**
+ * The maximum allowed backlog for TCP listen netconns.
+ * This backlog is used unless another is explicitly specified.
+ * 0xff is the maximum (u8_t).
+ */
+#ifndef TCP_DEFAULT_LISTEN_BACKLOG
+#define TCP_DEFAULT_LISTEN_BACKLOG      0xff
+#endif
+
+/**
+ * TCP_OVERSIZE: The maximum number of bytes that tcp_write may
+ * allocate ahead of time in an attempt to create shorter pbuf chains
+ * for transmission. The meaningful range is 0 to TCP_MSS. Some
+ * suggested values are:
+ *
+ * 0:         Disable oversized allocation. Each tcp_write() allocates a new
+              pbuf (old behaviour).
+ * 1:         Allocate size-aligned pbufs with minimal excess. Use this if your
+ *            scatter-gather DMA requires aligned fragments.
+ * 128:       Limit the pbuf/memory overhead to 20%.
+ * TCP_MSS:   Try to create unfragmented TCP packets.
+ * TCP_MSS/4: Try to create 4 fragments or less per TCP packet.
+ */
+#ifndef TCP_OVERSIZE
+#define TCP_OVERSIZE                    TCP_MSS
+#endif
+
+/**
+ * LWIP_TCP_TIMESTAMPS==1: support the TCP timestamp option.
+ * The timestamp option is currently only used to help remote hosts, it is not
+ * really used locally. Therefore, it is only enabled when a TS option is
+ * received in the initial SYN packet from a remote host.
+ */
+#ifndef LWIP_TCP_TIMESTAMPS
+#define LWIP_TCP_TIMESTAMPS             0
+#endif
+
+/**
+ * TCP_WND_UPDATE_THRESHOLD: difference in window to trigger an
+ * explicit window update
+ */
+#ifndef TCP_WND_UPDATE_THRESHOLD
+#define TCP_WND_UPDATE_THRESHOLD   LWIP_MIN((TCP_WND / 4), (TCP_MSS * 4))
+#endif
+
+/**
+ * LWIP_EVENT_API and LWIP_CALLBACK_API: Only one of these should be set to 1.
+ *     LWIP_EVENT_API==1: The user defines lwip_tcp_event() to receive all
+ *         events (accept, sent, etc) that happen in the system.
+ *     LWIP_CALLBACK_API==1: The PCB callback function is called directly
+ *         for the event. This is the default.
+ */
+#if !defined(LWIP_EVENT_API) && !defined(LWIP_CALLBACK_API)
+#define LWIP_EVENT_API                  0
+#define LWIP_CALLBACK_API               1
+#endif
+
+/**
+ * LWIP_WND_SCALE and TCP_RCV_SCALE:
+ * Set LWIP_WND_SCALE to 1 to enable window scaling.
+ * Set TCP_RCV_SCALE to the desired scaling factor (shift count in the
+ * range of [0..14]).
+ * When LWIP_WND_SCALE is enabled but TCP_RCV_SCALE is 0, we can use a large
+ * send window while having a small receive window only.
+ */
+#ifndef LWIP_WND_SCALE
+#define LWIP_WND_SCALE                  0
+#define TCP_RCV_SCALE                   0
+#endif
+
+
+/*
+   ----------------------------------
+   ---------- Pbuf options ----------
+   ----------------------------------
+*/
+/**
+ * PBUF_LINK_HLEN: the number of bytes that should be allocated for a
+ * link level header. The default is 14, the standard value for
+ * Ethernet.
+ */
+#ifndef PBUF_LINK_HLEN
+#ifdef LWIP_HOOK_VLAN_SET
+#define PBUF_LINK_HLEN                  (18 + ETH_PAD_SIZE)
+#else /* LWIP_HOOK_VLAN_SET */
+#define PBUF_LINK_HLEN                  (14 + ETH_PAD_SIZE)
+#endif /* LWIP_HOOK_VLAN_SET */
+#endif
+
+/**
+ * PBUF_LINK_ENCAPSULATION_HLEN: the number of bytes that should be allocated
+ * for an additional encapsulation header before ethernet headers (e.g. 802.11)
+ */
+#ifndef PBUF_LINK_ENCAPSULATION_HLEN
+#define PBUF_LINK_ENCAPSULATION_HLEN    0
+#endif
+
+/**
+ * PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. The default is
+ * designed to accommodate single full size TCP frame in one pbuf, including
+ * TCP_MSS, IP header, and link header.
+ */
+#ifndef PBUF_POOL_BUFSIZE
+#define PBUF_POOL_BUFSIZE               LWIP_MEM_ALIGN_SIZE(TCP_MSS+40+PBUF_LINK_ENCAPSULATION_HLEN+PBUF_LINK_HLEN)
+#endif
+
+/*
+   ------------------------------------------------
+   ---------- Network Interfaces options ----------
+   ------------------------------------------------
+*/
+/**
+ * LWIP_NETIF_HOSTNAME==1: use DHCP_OPTION_HOSTNAME with netif's hostname
+ * field.
+ */
+#ifndef LWIP_NETIF_HOSTNAME
+#define LWIP_NETIF_HOSTNAME             0
+#endif
+
+/**
+ * LWIP_NETIF_API==1: Support netif api (in netifapi.c)
+ */
+#ifndef LWIP_NETIF_API
+#define LWIP_NETIF_API                  0
+#endif
+
+/**
+ * LWIP_NETIF_STATUS_CALLBACK==1: Support a callback function whenever an interface
+ * changes its up/down status (i.e., due to DHCP IP acquisition)
+ */
+#ifndef LWIP_NETIF_STATUS_CALLBACK
+#define LWIP_NETIF_STATUS_CALLBACK      0
+#endif
+
+/**
+ * LWIP_NETIF_LINK_CALLBACK==1: Support a callback function from an interface
+ * whenever the link changes (i.e., link down)
+ */
+#ifndef LWIP_NETIF_LINK_CALLBACK
+#define LWIP_NETIF_LINK_CALLBACK        0
+#endif
+
+/**
+ * LWIP_NETIF_REMOVE_CALLBACK==1: Support a callback function that is called
+ * when a netif has been removed
+ */
+#ifndef LWIP_NETIF_REMOVE_CALLBACK
+#define LWIP_NETIF_REMOVE_CALLBACK      0
+#endif
+
+/**
+ * LWIP_NETIF_HWADDRHINT==1: Cache link-layer-address hints (e.g. table
+ * indices) in struct netif. TCP and UDP can make use of this to prevent
+ * scanning the ARP table for every sent packet. While this is faster for big
+ * ARP tables or many concurrent connections, it might be counterproductive
+ * if you have a tiny ARP table or if there never are concurrent connections.
+ */
+#ifndef LWIP_NETIF_HWADDRHINT
+#define LWIP_NETIF_HWADDRHINT           0
+#endif
+
+/**
+ * LWIP_NETIF_LOOPBACK==1: Support sending packets with a destination IP
+ * address equal to the netif IP address, looping them back up the stack.
+ */
+#ifndef LWIP_NETIF_LOOPBACK
+#define LWIP_NETIF_LOOPBACK             0
+#endif
+
+/**
+ * LWIP_LOOPBACK_MAX_PBUFS: Maximum number of pbufs on queue for loopback
+ * sending for each netif (0 = disabled)
+ */
+#ifndef LWIP_LOOPBACK_MAX_PBUFS
+#define LWIP_LOOPBACK_MAX_PBUFS         0
+#endif
+
+/**
+ * LWIP_NETIF_LOOPBACK_MULTITHREADING: Indicates whether threading is enabled in
+ * the system, as netifs must change how they behave depending on this setting
+ * for the LWIP_NETIF_LOOPBACK option to work.
+ * Setting this is needed to avoid reentering non-reentrant functions like
+ * tcp_input().
+ *    LWIP_NETIF_LOOPBACK_MULTITHREADING==1: Indicates that the user is using a
+ *       multithreaded environment like tcpip.c. In this case, netif->input()
+ *       is called directly.
+ *    LWIP_NETIF_LOOPBACK_MULTITHREADING==0: Indicates a polling (or NO_SYS) setup.
+ *       The packets are put on a list and netif_poll() must be called in
+ *       the main application loop.
+ */
+#ifndef LWIP_NETIF_LOOPBACK_MULTITHREADING
+#define LWIP_NETIF_LOOPBACK_MULTITHREADING    (!NO_SYS)
+#endif
+
+/**
+ * LWIP_NETIF_TX_SINGLE_PBUF: if this is set to 1, lwIP tries to put all data
+ * to be sent into one single pbuf. This is for compatibility with DMA-enabled
+ * MACs that do not support scatter-gather.
+ * Beware that this might involve CPU-memcpy before transmitting that would not
+ * be needed without this flag! Use this only if you need to!
+ *
+ * @todo: TCP and IP-frag do not work with this, yet:
+ */
+#ifndef LWIP_NETIF_TX_SINGLE_PBUF
+#define LWIP_NETIF_TX_SINGLE_PBUF             0
+#endif /* LWIP_NETIF_TX_SINGLE_PBUF */
+
+/*
+   ------------------------------------
+   ---------- LOOPIF options ----------
+   ------------------------------------
+*/
+/**
+ * LWIP_HAVE_LOOPIF==1: Support loop interface (127.0.0.1).
+ * This is only needed when no real netifs are available. If at least one other
+ * netif is available, loopback traffic uses this netif.
+ */
+#ifndef LWIP_HAVE_LOOPIF
+#define LWIP_HAVE_LOOPIF                LWIP_NETIF_LOOPBACK
+#endif
+
+/**
+ * LWIP_LOOPIF_MULTICAST==1: Support multicast/IGMP on loop interface (127.0.0.1).
+ */
+#ifndef LWIP_LOOPIF_MULTICAST
+#define LWIP_LOOPIF_MULTICAST               0
+#endif
+
+/*
+   ------------------------------------
+   ---------- SLIPIF options ----------
+   ------------------------------------
+*/
+/**
+ * LWIP_HAVE_SLIPIF==1: Support slip interface and slipif.c
+ */
+#ifndef LWIP_HAVE_SLIPIF
+#define LWIP_HAVE_SLIPIF                0
+#endif
+
+/*
+   ------------------------------------
+   ---------- Thread options ----------
+   ------------------------------------
+*/
+/**
+ * TCPIP_THREAD_NAME: The name assigned to the main tcpip thread.
+ */
+#ifndef TCPIP_THREAD_NAME
+#define TCPIP_THREAD_NAME              "tcpip_thread"
+#endif
+
+/**
+ * TCPIP_THREAD_STACKSIZE: The stack size used by the main tcpip thread.
+ * The stack size value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef TCPIP_THREAD_STACKSIZE
+#define TCPIP_THREAD_STACKSIZE          0
+#endif
+
+/**
+ * TCPIP_THREAD_PRIO: The priority assigned to the main tcpip thread.
+ * The priority value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef TCPIP_THREAD_PRIO
+#define TCPIP_THREAD_PRIO               1
+#endif
+
+/**
+ * TCPIP_MBOX_SIZE: The mailbox size for the tcpip thread messages
+ * The queue size value itself is platform-dependent, but is passed to
+ * sys_mbox_new() when tcpip_init is called.
+ */
+#ifndef TCPIP_MBOX_SIZE
+#define TCPIP_MBOX_SIZE                 0
+#endif
+
+/**
+ * SLIPIF_THREAD_NAME: The name assigned to the slipif_loop thread.
+ */
+#ifndef SLIPIF_THREAD_NAME
+#define SLIPIF_THREAD_NAME             "slipif_loop"
+#endif
+
+/**
+ * SLIP_THREAD_STACKSIZE: The stack size used by the slipif_loop thread.
+ * The stack size value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef SLIPIF_THREAD_STACKSIZE
+#define SLIPIF_THREAD_STACKSIZE         0
+#endif
+
+/**
+ * SLIPIF_THREAD_PRIO: The priority assigned to the slipif_loop thread.
+ * The priority value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef SLIPIF_THREAD_PRIO
+#define SLIPIF_THREAD_PRIO              1
+#endif
+
+/**
+ * DEFAULT_THREAD_NAME: The name assigned to any other lwIP thread.
+ */
+#ifndef DEFAULT_THREAD_NAME
+#define DEFAULT_THREAD_NAME            "lwIP"
+#endif
+
+/**
+ * DEFAULT_THREAD_STACKSIZE: The stack size used by any other lwIP thread.
+ * The stack size value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef DEFAULT_THREAD_STACKSIZE
+#define DEFAULT_THREAD_STACKSIZE        0
+#endif
+
+/**
+ * DEFAULT_THREAD_PRIO: The priority assigned to any other lwIP thread.
+ * The priority value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef DEFAULT_THREAD_PRIO
+#define DEFAULT_THREAD_PRIO             1
+#endif
+
+/**
+ * DEFAULT_RAW_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
+ * NETCONN_RAW. The queue size value itself is platform-dependent, but is passed
+ * to sys_mbox_new() when the recvmbox is created.
+ */
+#ifndef DEFAULT_RAW_RECVMBOX_SIZE
+#define DEFAULT_RAW_RECVMBOX_SIZE       0
+#endif
+
+/**
+ * DEFAULT_UDP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
+ * NETCONN_UDP. The queue size value itself is platform-dependent, but is passed
+ * to sys_mbox_new() when the recvmbox is created.
+ */
+#ifndef DEFAULT_UDP_RECVMBOX_SIZE
+#define DEFAULT_UDP_RECVMBOX_SIZE       0
+#endif
+
+/**
+ * DEFAULT_TCP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
+ * NETCONN_TCP. The queue size value itself is platform-dependent, but is passed
+ * to sys_mbox_new() when the recvmbox is created.
+ */
+#ifndef DEFAULT_TCP_RECVMBOX_SIZE
+#define DEFAULT_TCP_RECVMBOX_SIZE       0
+#endif
+
+/**
+ * DEFAULT_ACCEPTMBOX_SIZE: The mailbox size for the incoming connections.
+ * The queue size value itself is platform-dependent, but is passed to
+ * sys_mbox_new() when the acceptmbox is created.
+ */
+#ifndef DEFAULT_ACCEPTMBOX_SIZE
+#define DEFAULT_ACCEPTMBOX_SIZE         0
+#endif
+
+/*
+   ----------------------------------------------
+   ---------- Sequential layer options ----------
+   ----------------------------------------------
+*/
+/**
+ * LWIP_TCPIP_CORE_LOCKING: (EXPERIMENTAL!)
+ * Don't use it if you're not an active lwIP project member
+ */
+#ifndef LWIP_TCPIP_CORE_LOCKING
+#define LWIP_TCPIP_CORE_LOCKING         0
+#endif
+
+/**
+ * LWIP_TCPIP_CORE_LOCKING_INPUT: (EXPERIMENTAL!)
+ * Don't use it if you're not an active lwIP project member
+ */
+#ifndef LWIP_TCPIP_CORE_LOCKING_INPUT
+#define LWIP_TCPIP_CORE_LOCKING_INPUT   0
+#endif
+
+/**
+ * LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c)
+ */
+#ifndef LWIP_NETCONN
+#define LWIP_NETCONN                    1
+#endif
+
+/** LWIP_TCPIP_TIMEOUT==1: Enable tcpip_timeout/tcpip_untimeout to create
+ * timers running in tcpip_thread from another thread.
+ */
+#ifndef LWIP_TCPIP_TIMEOUT
+#define LWIP_TCPIP_TIMEOUT              0
+#endif
+
+/** LWIP_NETCONN_SEM_PER_THREAD==1: Use one (thread-local) semaphore per
+ * thread calling socket/netconn functions instead of allocating one
+ * semaphore per netconn (and per select etc.)
+ * ATTENTION: a thread-local semaphore for API calls is needed:
+ * - LWIP_NETCONN_THREAD_SEM_GET() returning a sys_sem_t*
+ * - LWIP_NETCONN_THREAD_SEM_ALLOC() creating the semaphore
+ * - LWIP_NETCONN_THREAD_SEM_FREE() freeing the semaphore
+ * The latter 2 can be invoked up by calling netconn_thread_init()/netconn_thread_cleanup().
+ * Ports may call these for threads created with sys_thread_new().
+ */
+#ifndef LWIP_NETCONN_SEM_PER_THREAD
+#define LWIP_NETCONN_SEM_PER_THREAD     0
+#endif
+
+/** LWIP_NETCONN_FULLDUPLEX==1: Enable code that allows reading from one thread,
+ * writing from a 2nd thread and closing from a 3rd thread at the same time.
+ * ATTENTION: This is currently really alpha! Some requirements:
+ * - LWIP_NETCONN_SEM_PER_THREAD==1 is required to use one socket/netconn from
+ *   multiple threads at once
+ * - sys_mbox_free() has to unblock receive tasks waiting on recvmbox/acceptmbox
+ *   and prevent a task pending on this during/after deletion
+ */
+#ifndef LWIP_NETCONN_FULLDUPLEX
+#define LWIP_NETCONN_FULLDUPLEX         0
+#endif
+
+/*
+   ------------------------------------
+   ---------- Socket options ----------
+   ------------------------------------
+*/
+/**
+ * LWIP_SOCKET==1: Enable Socket API (require to use sockets.c)
+ */
+#ifndef LWIP_SOCKET
+#define LWIP_SOCKET                     1
+#endif
+
+/* LWIP_SOCKET_SET_ERRNO==1: Set errno when socket functions cannot complete
+ * successfully, as required by POSIX. Default is POSIX-compliant.
+ */
+#ifndef LWIP_SOCKET_SET_ERRNO
+#define LWIP_SOCKET_SET_ERRNO           1
+#endif
+
+/**
+ * LWIP_COMPAT_SOCKETS==1: Enable BSD-style sockets functions names through defines.
+ * LWIP_COMPAT_SOCKETS==2: Same as ==1 but correctly named functions are created.
+ * While this helps code completion, it might conflict with existing libraries.
+ * (only used if you use sockets.c)
+ */
+#ifndef LWIP_COMPAT_SOCKETS
+#define LWIP_COMPAT_SOCKETS             1
+#endif
+
+/**
+ * LWIP_POSIX_SOCKETS_IO_NAMES==1: Enable POSIX-style sockets functions names.
+ * Disable this option if you use a POSIX operating system that uses the same
+ * names (read, write & close). (only used if you use sockets.c)
+ */
+#ifndef LWIP_POSIX_SOCKETS_IO_NAMES
+#define LWIP_POSIX_SOCKETS_IO_NAMES     1
+#endif
+
+/**
+ * LWIP_SOCKET_OFFSET==n: Increases the file descriptor number created by LwIP with n.
+ * This can be useful when there are multiple APIs which create file descriptors.
+ * When they all start with a different offset and you won't make them overlap you can
+ * re implement read/write/close/ioctl/fnctl to send the requested action to the right
+ * library (sharing select will need more work though).
+ */
+#ifndef LWIP_SOCKET_OFFSET
+#define LWIP_SOCKET_OFFSET              0
+#endif
+
+/**
+ * LWIP_TCP_KEEPALIVE==1: Enable TCP_KEEPIDLE, TCP_KEEPINTVL and TCP_KEEPCNT
+ * options processing. Note that TCP_KEEPIDLE and TCP_KEEPINTVL have to be set
+ * in seconds. (does not require sockets.c, and will affect tcp.c)
+ */
+#ifndef LWIP_TCP_KEEPALIVE
+#define LWIP_TCP_KEEPALIVE              0
+#endif
+
+/**
+ * LWIP_SO_SNDTIMEO==1: Enable send timeout for sockets/netconns and
+ * SO_SNDTIMEO processing.
+ */
+#ifndef LWIP_SO_SNDTIMEO
+#define LWIP_SO_SNDTIMEO                0
+#endif
+
+/**
+ * LWIP_SO_RCVTIMEO==1: Enable receive timeout for sockets/netconns and
+ * SO_RCVTIMEO processing.
+ */
+#ifndef LWIP_SO_RCVTIMEO
+#define LWIP_SO_RCVTIMEO                0
+#endif
+
+/**
+ * LWIP_SO_SNDRCVTIMEO_NONSTANDARD==1: SO_RCVTIMEO/SO_SNDTIMEO take an int
+ * (milliseconds, much like winsock does) instead of a struct timeval (default).
+ */
+#ifndef LWIP_SO_SNDRCVTIMEO_NONSTANDARD
+#define LWIP_SO_SNDRCVTIMEO_NONSTANDARD 0
+#endif
+
+/**
+ * LWIP_SO_RCVBUF==1: Enable SO_RCVBUF processing.
+ */
+#ifndef LWIP_SO_RCVBUF
+#define LWIP_SO_RCVBUF                  0
+#endif
+
+/**
+ * LWIP_SO_LINGER==1: Enable SO_LINGER processing.
+ */
+#ifndef LWIP_SO_LINGER
+#define LWIP_SO_LINGER                  0
+#endif
+
+/**
+ * If LWIP_SO_RCVBUF is used, this is the default value for recv_bufsize.
+ */
+#ifndef RECV_BUFSIZE_DEFAULT
+#define RECV_BUFSIZE_DEFAULT            INT_MAX
+#endif
+
+/**
+ * By default, TCP socket/netconn close waits 20 seconds max to send the FIN
+ */
+#ifndef LWIP_TCP_CLOSE_TIMEOUT_MS_DEFAULT
+#define LWIP_TCP_CLOSE_TIMEOUT_MS_DEFAULT 20000
+#endif
+
+/**
+ * SO_REUSE==1: Enable SO_REUSEADDR option.
+ */
+#ifndef SO_REUSE
+#define SO_REUSE                        0
+#endif
+
+/**
+ * SO_REUSE_RXTOALL==1: Pass a copy of incoming broadcast/multicast packets
+ * to all local matches if SO_REUSEADDR is turned on.
+ * WARNING: Adds a memcpy for every packet if passing to more than one pcb!
+ */
+#ifndef SO_REUSE_RXTOALL
+#define SO_REUSE_RXTOALL                0
+#endif
+
+/**
+ * LWIP_FIONREAD_LINUXMODE==0 (default): ioctl/FIONREAD returns the amount of
+ * pending data in the network buffer. This is the way windows does it. It's
+ * the default for lwIP since it is smaller.
+ * LWIP_FIONREAD_LINUXMODE==1: ioctl/FIONREAD returns the size of the next
+ * pending datagram in bytes. This is the way linux does it. This code is only
+ * here for compatibility.
+ */
+#ifndef LWIP_FIONREAD_LINUXMODE
+#define LWIP_FIONREAD_LINUXMODE         0
+#endif
+
+/*
+   ----------------------------------------
+   ---------- Statistics options ----------
+   ----------------------------------------
+*/
+/**
+ * LWIP_STATS==1: Enable statistics collection in lwip_stats.
+ */
+#ifndef LWIP_STATS
+#define LWIP_STATS                      1
+#endif
+
+#if LWIP_STATS
+
+/**
+ * LWIP_STATS_DISPLAY==1: Compile in the statistics output functions.
+ */
+#ifndef LWIP_STATS_DISPLAY
+#define LWIP_STATS_DISPLAY              0
+#endif
+
+/**
+ * LINK_STATS==1: Enable link stats.
+ */
+#ifndef LINK_STATS
+#define LINK_STATS                      1
+#endif
+
+/**
+ * ETHARP_STATS==1: Enable etharp stats.
+ */
+#ifndef ETHARP_STATS
+#define ETHARP_STATS                    (LWIP_ARP)
+#endif
+
+/**
+ * IP_STATS==1: Enable IP stats.
+ */
+#ifndef IP_STATS
+#define IP_STATS                        1
+#endif
+
+/**
+ * IPFRAG_STATS==1: Enable IP fragmentation stats. Default is
+ * on if using either frag or reass.
+ */
+#ifndef IPFRAG_STATS
+#define IPFRAG_STATS                    (IP_REASSEMBLY || IP_FRAG)
+#endif
+
+/**
+ * ICMP_STATS==1: Enable ICMP stats.
+ */
+#ifndef ICMP_STATS
+#define ICMP_STATS                      1
+#endif
+
+/**
+ * IGMP_STATS==1: Enable IGMP stats.
+ */
+#ifndef IGMP_STATS
+#define IGMP_STATS                      (LWIP_IGMP)
+#endif
+
+/**
+ * UDP_STATS==1: Enable UDP stats. Default is on if
+ * UDP enabled, otherwise off.
+ */
+#ifndef UDP_STATS
+#define UDP_STATS                       (LWIP_UDP)
+#endif
+
+/**
+ * TCP_STATS==1: Enable TCP stats. Default is on if TCP
+ * enabled, otherwise off.
+ */
+#ifndef TCP_STATS
+#define TCP_STATS                       (LWIP_TCP)
+#endif
+
+/**
+ * MEM_STATS==1: Enable mem.c stats.
+ */
+#ifndef MEM_STATS
+#define MEM_STATS                       ((MEM_LIBC_MALLOC == 0) && (MEM_USE_POOLS == 0))
+#endif
+
+/**
+ * MEMP_STATS==1: Enable memp.c pool stats.
+ */
+#ifndef MEMP_STATS
+#define MEMP_STATS                      (MEMP_MEM_MALLOC == 0)
+#endif
+
+/**
+ * SYS_STATS==1: Enable system stats (sem and mbox counts, etc).
+ */
+#ifndef SYS_STATS
+#define SYS_STATS                       (NO_SYS == 0)
+#endif
+
+/**
+ * IP6_STATS==1: Enable IPv6 stats.
+ */
+#ifndef IP6_STATS
+#define IP6_STATS                       (LWIP_IPV6)
+#endif
+
+/**
+ * ICMP6_STATS==1: Enable ICMP for IPv6 stats.
+ */
+#ifndef ICMP6_STATS
+#define ICMP6_STATS                     (LWIP_IPV6 && LWIP_ICMP6)
+#endif
+
+/**
+ * IP6_FRAG_STATS==1: Enable IPv6 fragmentation stats.
+ */
+#ifndef IP6_FRAG_STATS
+#define IP6_FRAG_STATS                  (LWIP_IPV6 && (LWIP_IPV6_FRAG || LWIP_IPV6_REASS))
+#endif
+
+/**
+ * MLD6_STATS==1: Enable MLD for IPv6 stats.
+ */
+#ifndef MLD6_STATS
+#define MLD6_STATS                      (LWIP_IPV6 && LWIP_IPV6_MLD)
+#endif
+
+/**
+ * ND6_STATS==1: Enable Neighbor discovery for IPv6 stats.
+ */
+#ifndef ND6_STATS
+#define ND6_STATS                       (LWIP_IPV6)
+#endif
+
+/**
+ * MIB2_STATS==1: Stats for SNMP MIB2.
+ */
+#ifndef MIB2_STATS
+#define MIB2_STATS                      0
+#endif
+
+#else
+
+#define LINK_STATS                      0
+#define ETHARP_STATS                    0
+#define IP_STATS                        0
+#define IPFRAG_STATS                    0
+#define ICMP_STATS                      0
+#define IGMP_STATS                      0
+#define UDP_STATS                       0
+#define TCP_STATS                       0
+#define MEM_STATS                       0
+#define MEMP_STATS                      0
+#define SYS_STATS                       0
+#define LWIP_STATS_DISPLAY              0
+#define IP6_STATS                       0
+#define ICMP6_STATS                     0
+#define IP6_FRAG_STATS                  0
+#define MLD6_STATS                      0
+#define ND6_STATS                       0
+#define MIB2_STATS                      0
+
+#endif /* LWIP_STATS */
+
+/*
+   ---------------------------------
+   ---------- PPP options ----------
+   ---------------------------------
+*/
+
+/**
+ * PPP_SUPPORT==1: Enable PPP.
+ */
+#ifndef PPP_SUPPORT
+#define PPP_SUPPORT                     0
+#endif
+
+/**
+ * PPPOE_SUPPORT==1: Enable PPP Over Ethernet
+ */
+#ifndef PPPOE_SUPPORT
+#define PPPOE_SUPPORT                   0
+#endif
+
+/**
+ * PPPOL2TP_SUPPORT==1: Enable PPP Over L2TP
+ */
+#ifndef PPPOL2TP_SUPPORT
+#define PPPOL2TP_SUPPORT                0
+#endif
+
+/**
+ * PPPOL2TP_AUTH_SUPPORT==1: Enable PPP Over L2TP Auth (enable MD5 support)
+ */
+#ifndef PPPOL2TP_AUTH_SUPPORT
+#define PPPOL2TP_AUTH_SUPPORT           PPPOL2TP_SUPPORT
+#endif
+
+/**
+ * PPPOS_SUPPORT==1: Enable PPP Over Serial
+ */
+#ifndef PPPOS_SUPPORT
+#define PPPOS_SUPPORT                   PPP_SUPPORT
+#endif
+
+/**
+ * LWIP_PPP_API==1: Enable PPP API (in pppapi.c)
+ */
+#ifndef LWIP_PPP_API
+#define LWIP_PPP_API                    (PPP_SUPPORT && (NO_SYS == 0))
+#endif
+
+#if PPP_SUPPORT
+
+/**
+ * PPP_INPROC_IRQ_SAFE==1 call pppos_input() using tcpip_callback().
+ *
+ * Please read the "PPPoS input path" chapter in the PPP documentation about this option.
+ */
+#ifndef PPP_INPROC_IRQ_SAFE
+#define PPP_INPROC_IRQ_SAFE             0
+#endif
+
+/**
+ * PRINTPKT_SUPPORT==1: Enable PPP print packet support
+ *
+ * Mandatory for debugging, it displays exchanged packet content in debug trace.
+ */
+#ifndef PRINTPKT_SUPPORT
+#define PRINTPKT_SUPPORT                0
+#endif
+
+/**
+ * PPP_IPV4_SUPPORT==1: Enable PPP IPv4 support
+ */
+#ifndef PPP_IPV4_SUPPORT
+#define PPP_IPV4_SUPPORT                (LWIP_IPV4)
+#endif
+
+/**
+ * PPP_IPV6_SUPPORT==1: Enable PPP IPv6 support
+ */
+#ifndef PPP_IPV6_SUPPORT
+#define PPP_IPV6_SUPPORT                (LWIP_IPV6)
+#endif
+
+/**
+ * PPP_NOTIFY_PHASE==1: Support PPP notify phase support
+ *
+ * PPP notify phase support allows you to set a callback which is
+ * called on change of the internal PPP state machine.
+ *
+ * This can be used for example to set a LED pattern depending on the
+ * current phase of the PPP session.
+ */
+#ifndef PPP_NOTIFY_PHASE
+#define PPP_NOTIFY_PHASE                0
+#endif
+
+/**
+ * pbuf_type PPP is using for LCP, PAP, CHAP, EAP, CCP, IPCP and IP6CP packets.
+ *
+ * Memory allocated must be single buffered for PPP to works, it requires pbuf
+ * that are not going to be chained when allocated. This requires setting
+ * PBUF_POOL_BUFSIZE to at least 512 bytes, which is quite huge for small systems.
+ *
+ * Setting PPP_USE_PBUF_RAM to 1 makes PPP use memory from heap where continuous
+ * buffers are required, allowing you to use a smaller PBUF_POOL_BUFSIZE.
+ */
+#ifndef PPP_USE_PBUF_RAM
+#define PPP_USE_PBUF_RAM                0
+#endif
+
+/**
+ * PPP_FCS_TABLE: Keep a 256*2 byte table to speed up FCS calculation for PPPoS
+ */
+#ifndef PPP_FCS_TABLE
+#define PPP_FCS_TABLE                   1
+#endif
+
+/**
+ * PAP_SUPPORT==1: Support PAP.
+ */
+#ifndef PAP_SUPPORT
+#define PAP_SUPPORT                     0
+#endif
+
+/**
+ * CHAP_SUPPORT==1: Support CHAP.
+ */
+#ifndef CHAP_SUPPORT
+#define CHAP_SUPPORT                    0
+#endif
+
+/**
+ * MSCHAP_SUPPORT==1: Support MSCHAP.
+ */
+#ifndef MSCHAP_SUPPORT
+#define MSCHAP_SUPPORT                  0
+#endif
+#if MSCHAP_SUPPORT
+/* MSCHAP requires CHAP support */
+#undef CHAP_SUPPORT
+#define CHAP_SUPPORT                    1
+#endif /* MSCHAP_SUPPORT */
+
+/**
+ * EAP_SUPPORT==1: Support EAP.
+ */
+#ifndef EAP_SUPPORT
+#define EAP_SUPPORT                     0
+#endif
+
+/**
+ * CCP_SUPPORT==1: Support CCP.
+ */
+#ifndef CCP_SUPPORT
+#define CCP_SUPPORT                     0
+#endif
+
+/**
+ * MPPE_SUPPORT==1: Support MPPE.
+ */
+#ifndef MPPE_SUPPORT
+#define MPPE_SUPPORT                    0
+#endif
+#if MPPE_SUPPORT
+/* MPPE requires CCP support */
+#undef CCP_SUPPORT
+#define CCP_SUPPORT                     1
+/* MPPE requires MSCHAP support */
+#undef MSCHAP_SUPPORT
+#define MSCHAP_SUPPORT                  1
+/* MSCHAP requires CHAP support */
+#undef CHAP_SUPPORT
+#define CHAP_SUPPORT                    1
+#endif /* MPPE_SUPPORT */
+
+/**
+ * CBCP_SUPPORT==1: Support CBCP. CURRENTLY NOT SUPPORTED! DO NOT SET!
+ */
+#ifndef CBCP_SUPPORT
+#define CBCP_SUPPORT                    0
+#endif
+
+/**
+ * ECP_SUPPORT==1: Support ECP. CURRENTLY NOT SUPPORTED! DO NOT SET!
+ */
+#ifndef ECP_SUPPORT
+#define ECP_SUPPORT                     0
+#endif
+
+/**
+ * DEMAND_SUPPORT==1: Support dial on demand. CURRENTLY NOT SUPPORTED! DO NOT SET!
+ */
+#ifndef DEMAND_SUPPORT
+#define DEMAND_SUPPORT                  0
+#endif
+
+/**
+ * LQR_SUPPORT==1: Support Link Quality Report. Do nothing except exchanging some LCP packets.
+ */
+#ifndef LQR_SUPPORT
+#define LQR_SUPPORT                     0
+#endif
+
+/**
+ * PPP_SERVER==1: Enable PPP server support (waiting for incoming PPP session).
+ *
+ * Currently only supported for PPPoS.
+ */
+#ifndef PPP_SERVER
+#define PPP_SERVER                      0
+#endif
+
+#if PPP_SERVER
+/*
+ * PPP_OUR_NAME: Our name for authentication purposes
+ */
+#ifndef PPP_OUR_NAME
+#define PPP_OUR_NAME                    "lwIP"
+#endif
+#endif /* PPP_SERVER */
+
+/**
+ * VJ_SUPPORT==1: Support VJ header compression.
+ */
+#ifndef VJ_SUPPORT
+#define VJ_SUPPORT                      1
+#endif
+/* VJ compression is only supported for IPv4 over PPPoS. */
+#if !PPPOS_SUPPORT || !PPP_IPV4_SUPPORT
+#undef VJ_SUPPORT
+#define VJ_SUPPORT                      0
+#endif /* !PPPOS_SUPPORT */
+
+/**
+ * PPP_MD5_RANDM==1: Use MD5 for better randomness.
+ * Enabled by default if CHAP, EAP, or L2TP AUTH support is enabled.
+ */
+#ifndef PPP_MD5_RANDM
+#define PPP_MD5_RANDM                   (CHAP_SUPPORT || EAP_SUPPORT || PPPOL2TP_AUTH_SUPPORT)
+#endif
+
+/**
+ * PolarSSL library, used if necessary and not previously disabled
+ *
+ *
+ * lwIP contains some files fetched from the latest BSD release of
+ * the PolarSSL project for ciphers and encryption methods we need for lwIP
+ * PPP support.
+ *
+ * The PolarSSL files were cleaned to contain only the necessary struct
+ * fields and functions needed for lwIP.
+ *
+ * The PolarSSL API was not changed at all, so if you are already using
+ * PolarSSL you can choose to skip the compilation of the included PolarSSL
+ * library into lwIP:
+ *
+ * The following defines are available for flexibility:
+ *
+ * LWIP_INCLUDED_POLARSSL_MD4   ; Use lwIP internal PolarSSL for MD4
+ * LWIP_INCLUDED_POLARSSL_MD5   ; Use lwIP internal PolarSSL for MD5
+ * LWIP_INCLUDED_POLARSSL_SHA1  ; Use lwIP internal PolarSSL for SHA1
+ * LWIP_INCLUDED_POLARSSL_DES   ; Use lwIP internal PolarSSL for DES
+ *
+ * If set (=1), the default if required by another enabled PPP feature unless
+ * explicitly set to 0, using included lwIP PolarSSL.
+ *
+ * If clear (=0), not needed or using external PolarSSL.
+ *
+ * Beware of the stack requirements which can be a lot larger if you are not
+ * using our cleaned PolarSSL library.
+ */
+
+/* CHAP, EAP, L2TP AUTH and MD5 Random require MD5 support */
+#if CHAP_SUPPORT || EAP_SUPPORT || PPPOL2TP_AUTH_SUPPORT || PPP_MD5_RANDM
+#ifndef LWIP_INCLUDED_POLARSSL_MD5
+#define LWIP_INCLUDED_POLARSSL_MD5        1
+#endif /* LWIP_INCLUDED_POLARSSL_MD5 */
+#endif /* CHAP_SUPPORT || EAP_SUPPORT || PPPOL2TP_AUTH_SUPPORT || PPP_MD5_RANDM */
+
+#if MSCHAP_SUPPORT
+/* MSCHAP require MD4 support */
+#ifndef LWIP_INCLUDED_POLARSSL_MD4
+#define LWIP_INCLUDED_POLARSSL_MD4      1
+#endif /* LWIP_INCLUDED_POLARSSL_MD4 */
+/* MSCHAP require SHA1 support */
+#ifndef LWIP_INCLUDED_POLARSSL_SHA1
+#define LWIP_INCLUDED_POLARSSL_SHA1     1
+#endif /* LWIP_INCLUDED_POLARSSL_SHA1 */
+/* MSCHAP require DES support */
+#ifndef LWIP_INCLUDED_POLARSSL_DES
+#define LWIP_INCLUDED_POLARSSL_DES      1
+#endif /* LWIP_INCLUDED_POLARSSL_DES */
+/* MS-CHAP support is required for MPPE */
+#if MPPE_SUPPORT
+/* MPPE require ARC4 support */
+#ifndef LWIP_INCLUDED_POLARSSL_ARC4
+#define LWIP_INCLUDED_POLARSSL_ARC4     1
+#endif /* LWIP_INCLUDED_POLARSSL_ARC4*/
+#endif /* MPPE_SUPPORT */
+#endif /* MSCHAP_SUPPORT */
+
+/* Default value if unset */
+#ifndef LWIP_INCLUDED_POLARSSL_MD4
+#define LWIP_INCLUDED_POLARSSL_MD4      0
+#endif /* LWIP_INCLUDED_POLARSSL_MD4 */
+#ifndef LWIP_INCLUDED_POLARSSL_MD5
+#define LWIP_INCLUDED_POLARSSL_MD5      0
+#endif /* LWIP_INCLUDED_POLARSSL_MD5 */
+#ifndef LWIP_INCLUDED_POLARSSL_SHA1
+#define LWIP_INCLUDED_POLARSSL_SHA1     0
+#endif /* LWIP_INCLUDED_POLARSSL_SHA1 */
+#ifndef LWIP_INCLUDED_POLARSSL_DES
+#define LWIP_INCLUDED_POLARSSL_DES      0
+#endif /* LWIP_INCLUDED_POLARSSL_DES */
+#ifndef LWIP_INCLUDED_POLARSSL_ARC4
+#define LWIP_INCLUDED_POLARSSL_ARC4     0
+#endif /* LWIP_INCLUDED_POLARSSL_ARC4 */
+
+/*
+ * PPP Timeouts
+ */
+
+/**
+ * FSM_DEFTIMEOUT: Timeout time in seconds
+ */
+#ifndef FSM_DEFTIMEOUT
+#define FSM_DEFTIMEOUT                  6
+#endif
+
+/**
+ * FSM_DEFMAXTERMREQS: Maximum Terminate-Request transmissions
+ */
+#ifndef FSM_DEFMAXTERMREQS
+#define FSM_DEFMAXTERMREQS              2
+#endif
+
+/**
+ * FSM_DEFMAXCONFREQS: Maximum Configure-Request transmissions
+ */
+#ifndef FSM_DEFMAXCONFREQS
+#define FSM_DEFMAXCONFREQS              10
+#endif
+
+/**
+ * FSM_DEFMAXNAKLOOPS: Maximum number of nak loops
+ */
+#ifndef FSM_DEFMAXNAKLOOPS
+#define FSM_DEFMAXNAKLOOPS              5
+#endif
+
+/**
+ * UPAP_DEFTIMEOUT: Timeout (seconds) for retransmitting req
+ */
+#ifndef UPAP_DEFTIMEOUT
+#define UPAP_DEFTIMEOUT                 6
+#endif
+
+/**
+ * UPAP_DEFTRANSMITS: Maximum number of auth-reqs to send
+ */
+#ifndef UPAP_DEFTRANSMITS
+#define UPAP_DEFTRANSMITS               10
+#endif
+
+#if PPP_SERVER
+/**
+ * UPAP_DEFREQTIME: Time to wait for auth-req from peer
+ */
+#ifndef UPAP_DEFREQTIME
+#define UPAP_DEFREQTIME                 30
+#endif
+#endif /* PPP_SERVER */
+
+/**
+ * CHAP_DEFTIMEOUT: Timeout (seconds) for retransmitting req
+ */
+#ifndef CHAP_DEFTIMEOUT
+#define CHAP_DEFTIMEOUT                 6
+#endif
+
+/**
+ * CHAP_DEFTRANSMITS: max # times to send challenge
+ */
+#ifndef CHAP_DEFTRANSMITS
+#define CHAP_DEFTRANSMITS               10
+#endif
+
+#if PPP_SERVER
+/**
+ * CHAP_DEFRECHALLENGETIME: If this option is > 0, rechallenge the peer every n seconds
+ */
+#ifndef CHAP_DEFRECHALLENGETIME
+#define CHAP_DEFRECHALLENGETIME         0
+#endif
+#endif /* PPP_SERVER */
+
+/**
+ * EAP_DEFREQTIME: Time to wait for peer request
+ */
+#ifndef EAP_DEFREQTIME
+#define EAP_DEFREQTIME                  6
+#endif
+
+/**
+ * EAP_DEFALLOWREQ: max # times to accept requests
+ */
+#ifndef EAP_DEFALLOWREQ
+#define EAP_DEFALLOWREQ                 10
+#endif
+
+#if PPP_SERVER
+/**
+ * EAP_DEFTIMEOUT: Timeout (seconds) for rexmit
+ */
+#ifndef EAP_DEFTIMEOUT
+#define EAP_DEFTIMEOUT                  6
+#endif
+
+/**
+ * EAP_DEFTRANSMITS: max # times to transmit
+ */
+#ifndef EAP_DEFTRANSMITS
+#define EAP_DEFTRANSMITS                10
+#endif
+#endif /* PPP_SERVER */
+
+/**
+ * LCP_DEFLOOPBACKFAIL: Default number of times we receive our magic number from the peer
+ * before deciding the link is looped-back.
+ */
+#ifndef LCP_DEFLOOPBACKFAIL
+#define LCP_DEFLOOPBACKFAIL             10
+#endif
+
+/**
+ * LCP_ECHOINTERVAL: Interval in seconds between keepalive echo requests, 0 to disable.
+ */
+#ifndef LCP_ECHOINTERVAL
+#define LCP_ECHOINTERVAL                0
+#endif
+
+/**
+ * LCP_MAXECHOFAILS: Number of unanswered echo requests before failure.
+ */
+#ifndef LCP_MAXECHOFAILS
+#define LCP_MAXECHOFAILS                3
+#endif
+
+/**
+ * PPP_MAXIDLEFLAG: Max Xmit idle time (in ms) before resend flag char.
+ */
+#ifndef PPP_MAXIDLEFLAG
+#define PPP_MAXIDLEFLAG                 100
+#endif
+
+/**
+ * PPP Packet sizes
+ */
+
+/**
+ * PPP_MRU: Default MRU
+ */
+#ifndef PPP_MRU
+#define PPP_MRU                         1500
+#endif
+
+/**
+ * PPP_DEFMRU: Default MRU to try
+ */
+#ifndef PPP_DEFMRU
+#define PPP_DEFMRU                      1500
+#endif
+
+/**
+ * PPP_MAXMRU: Normally limit MRU to this (pppd default = 16384)
+ */
+#ifndef PPP_MAXMRU
+#define PPP_MAXMRU                      1500
+#endif
+
+/**
+ * PPP_MINMRU: No MRUs below this
+ */
+#ifndef PPP_MINMRU
+#define PPP_MINMRU                      128
+#endif
+
+/**
+ * PPPOL2TP_DEFMRU: Default MTU and MRU for L2TP
+ * Default = 1500 - PPPoE(6) - PPP Protocol(2) - IPv4 header(20) - UDP Header(8)
+ * - L2TP Header(6) - HDLC Header(2) - PPP Protocol(2) - MPPE Header(2) - PPP Protocol(2)
+ */
+#if PPPOL2TP_SUPPORT
+#ifndef PPPOL2TP_DEFMRU
+#define PPPOL2TP_DEFMRU                 1450
+#endif
+#endif /* PPPOL2TP_SUPPORT */
+
+/**
+ * MAXNAMELEN: max length of hostname or name for auth
+ */
+#ifndef MAXNAMELEN
+#define MAXNAMELEN                      256
+#endif
+
+/**
+ * MAXSECRETLEN: max length of password or secret
+ */
+#ifndef MAXSECRETLEN
+#define MAXSECRETLEN                    256
+#endif
+
+#endif /* PPP_SUPPORT */
+
+/*
+   --------------------------------------
+   ---------- Checksum options ----------
+   --------------------------------------
+*/
+
+/**
+ * LWIP_CHECKSUM_CTRL_PER_NETIF==1: Checksum generation/check can be enabled/disabled
+ * per netif.
+ * ATTENTION: if enabled, the CHECKSUM_GEN_* and CHECKSUM_CHECK_* defines must be enabled!
+ */
+#ifndef LWIP_CHECKSUM_CTRL_PER_NETIF
+#define LWIP_CHECKSUM_CTRL_PER_NETIF    0
+#endif
+
+/**
+ * CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets.
+ */
+#ifndef CHECKSUM_GEN_IP
+#define CHECKSUM_GEN_IP                 1
+#endif
+
+/**
+ * CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets.
+ */
+#ifndef CHECKSUM_GEN_UDP
+#define CHECKSUM_GEN_UDP                1
+#endif
+
+/**
+ * CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets.
+ */
+#ifndef CHECKSUM_GEN_TCP
+#define CHECKSUM_GEN_TCP                1
+#endif
+
+/**
+ * CHECKSUM_GEN_ICMP==1: Generate checksums in software for outgoing ICMP packets.
+ */
+#ifndef CHECKSUM_GEN_ICMP
+#define CHECKSUM_GEN_ICMP               1
+#endif
+
+/**
+ * CHECKSUM_GEN_ICMP6==1: Generate checksums in software for outgoing ICMP6 packets.
+ */
+#ifndef CHECKSUM_GEN_ICMP6
+#define CHECKSUM_GEN_ICMP6              1
+#endif
+
+/**
+ * CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets.
+ */
+#ifndef CHECKSUM_CHECK_IP
+#define CHECKSUM_CHECK_IP               1
+#endif
+
+/**
+ * CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets.
+ */
+#ifndef CHECKSUM_CHECK_UDP
+#define CHECKSUM_CHECK_UDP              1
+#endif
+
+/**
+ * CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets.
+ */
+#ifndef CHECKSUM_CHECK_TCP
+#define CHECKSUM_CHECK_TCP              1
+#endif
+
+/**
+ * CHECKSUM_CHECK_ICMP==1: Check checksums in software for incoming ICMP packets.
+ */
+#ifndef CHECKSUM_CHECK_ICMP
+#define CHECKSUM_CHECK_ICMP             1
+#endif
+
+/**
+ * CHECKSUM_CHECK_ICMP6==1: Check checksums in software for incoming ICMPv6 packets
+ */
+#ifndef CHECKSUM_CHECK_ICMP6
+#define CHECKSUM_CHECK_ICMP6            1
+#endif
+
+/**
+ * LWIP_CHECKSUM_ON_COPY==1: Calculate checksum when copying data from
+ * application buffers to pbufs.
+ */
+#ifndef LWIP_CHECKSUM_ON_COPY
+#define LWIP_CHECKSUM_ON_COPY           0
+#endif
+
+/*
+   ---------------------------------------
+   ---------- IPv6 options ---------------
+   ---------------------------------------
+*/
+/**
+ * LWIP_IPV6==1: Enable IPv6
+ */
+#ifndef LWIP_IPV6
+#define LWIP_IPV6                       0
+#endif
+
+/**
+ * LWIP_IPV6_NUM_ADDRESSES: Number of IPv6 addresses per netif.
+ */
+#ifndef LWIP_IPV6_NUM_ADDRESSES
+#define LWIP_IPV6_NUM_ADDRESSES         3
+#endif
+
+/**
+ * LWIP_IPV6_FORWARD==1: Forward IPv6 packets across netifs
+ */
+#ifndef LWIP_IPV6_FORWARD
+#define LWIP_IPV6_FORWARD               0
+#endif
+
+/**
+ * LWIP_ICMP6==1: Enable ICMPv6 (mandatory per RFC)
+ */
+#ifndef LWIP_ICMP6
+#define LWIP_ICMP6                      (LWIP_IPV6)
+#endif
+
+/**
+ * LWIP_ICMP6_DATASIZE: bytes from original packet to send back in
+ * ICMPv6 error messages.
+ */
+#ifndef LWIP_ICMP6_DATASIZE
+#define LWIP_ICMP6_DATASIZE             8
+#endif
+
+/**
+ * LWIP_ICMP6_HL: default hop limit for ICMPv6 messages
+ */
+#ifndef LWIP_ICMP6_HL
+#define LWIP_ICMP6_HL                   255
+#endif
+
+/**
+ * LWIP_IPV6_MLD==1: Enable multicast listener discovery protocol.
+ */
+#ifndef LWIP_IPV6_MLD
+#define LWIP_IPV6_MLD                   (LWIP_IPV6)
+#endif
+
+/**
+ * MEMP_NUM_MLD6_GROUP: Max number of IPv6 multicast that can be joined.
+ */
+#ifndef MEMP_NUM_MLD6_GROUP
+#define MEMP_NUM_MLD6_GROUP             4
+#endif
+
+/**
+ * LWIP_IPV6_FRAG==1: Fragment outgoing IPv6 packets that are too big.
+ */
+#ifndef LWIP_IPV6_FRAG
+#define LWIP_IPV6_FRAG                  0
+#endif
+
+/**
+ * LWIP_IPV6_REASS==1: reassemble incoming IPv6 packets that fragmented
+ */
+#ifndef LWIP_IPV6_REASS
+#define LWIP_IPV6_REASS                 (LWIP_IPV6)
+#endif
+
+/**
+ * LWIP_ND6_QUEUEING==1: queue outgoing IPv6 packets while MAC address
+ * is being resolved.
+ */
+#ifndef LWIP_ND6_QUEUEING
+#define LWIP_ND6_QUEUEING               (LWIP_IPV6)
+#endif
+
+/**
+ * MEMP_NUM_ND6_QUEUE: Max number of IPv6 packets to queue during MAC resolution.
+ */
+#ifndef MEMP_NUM_ND6_QUEUE
+#define MEMP_NUM_ND6_QUEUE              20
+#endif
+
+/**
+ * LWIP_ND6_NUM_NEIGHBORS: Number of entries in IPv6 neighbor cache
+ */
+#ifndef LWIP_ND6_NUM_NEIGHBORS
+#define LWIP_ND6_NUM_NEIGHBORS          10
+#endif
+
+/**
+ * LWIP_ND6_NUM_DESTINATIONS: number of entries in IPv6 destination cache
+ */
+#ifndef LWIP_ND6_NUM_DESTINATIONS
+#define LWIP_ND6_NUM_DESTINATIONS       10
+#endif
+
+/**
+ * LWIP_ND6_NUM_PREFIXES: number of entries in IPv6 on-link prefixes cache
+ */
+#ifndef LWIP_ND6_NUM_PREFIXES
+#define LWIP_ND6_NUM_PREFIXES           5
+#endif
+
+/**
+ * LWIP_ND6_NUM_ROUTERS: number of entries in IPv6 default router cache
+ */
+#ifndef LWIP_ND6_NUM_ROUTERS
+#define LWIP_ND6_NUM_ROUTERS            3
+#endif
+
+/**
+ * LWIP_ND6_MAX_MULTICAST_SOLICIT: max number of multicast solicit messages to send
+ * (neighbor solicit and router solicit)
+ */
+#ifndef LWIP_ND6_MAX_MULTICAST_SOLICIT
+#define LWIP_ND6_MAX_MULTICAST_SOLICIT  3
+#endif
+
+/**
+ * LWIP_ND6_MAX_UNICAST_SOLICIT: max number of unicast neighbor solicitation messages
+ * to send during neighbor reachability detection.
+ */
+#ifndef LWIP_ND6_MAX_UNICAST_SOLICIT
+#define LWIP_ND6_MAX_UNICAST_SOLICIT    3
+#endif
+
+/**
+ * Unused: See ND RFC (time in milliseconds).
+ */
+#ifndef LWIP_ND6_MAX_ANYCAST_DELAY_TIME
+#define LWIP_ND6_MAX_ANYCAST_DELAY_TIME 1000
+#endif
+
+/**
+ * Unused: See ND RFC
+ */
+#ifndef LWIP_ND6_MAX_NEIGHBOR_ADVERTISEMENT
+#define LWIP_ND6_MAX_NEIGHBOR_ADVERTISEMENT  3
+#endif
+
+/**
+ * LWIP_ND6_REACHABLE_TIME: default neighbor reachable time (in milliseconds).
+ * May be updated by router advertisement messages.
+ */
+#ifndef LWIP_ND6_REACHABLE_TIME
+#define LWIP_ND6_REACHABLE_TIME         30000
+#endif
+
+/**
+ * LWIP_ND6_RETRANS_TIMER: default retransmission timer for solicitation messages
+ */
+#ifndef LWIP_ND6_RETRANS_TIMER
+#define LWIP_ND6_RETRANS_TIMER          1000
+#endif
+
+/**
+ * LWIP_ND6_DELAY_FIRST_PROBE_TIME: Delay before first unicast neighbor solicitation
+ * message is sent, during neighbor reachability detection.
+ */
+#ifndef LWIP_ND6_DELAY_FIRST_PROBE_TIME
+#define LWIP_ND6_DELAY_FIRST_PROBE_TIME 5000
+#endif
+
+/**
+ * LWIP_ND6_ALLOW_RA_UPDATES==1: Allow Router Advertisement messages to update
+ * Reachable time and retransmission timers, and netif MTU.
+ */
+#ifndef LWIP_ND6_ALLOW_RA_UPDATES
+#define LWIP_ND6_ALLOW_RA_UPDATES       1
+#endif
+
+/**
+ * LWIP_IPV6_SEND_ROUTER_SOLICIT==1: Send router solicitation messages during
+ * network startup.
+ */
+#ifndef LWIP_IPV6_SEND_ROUTER_SOLICIT
+#define LWIP_IPV6_SEND_ROUTER_SOLICIT   1
+#endif
+
+/**
+ * LWIP_ND6_TCP_REACHABILITY_HINTS==1: Allow TCP to provide Neighbor Discovery
+ * with reachability hints for connected destinations. This helps avoid sending
+ * unicast neighbor solicitation messages.
+ */
+#ifndef LWIP_ND6_TCP_REACHABILITY_HINTS
+#define LWIP_ND6_TCP_REACHABILITY_HINTS 1
+#endif
+
+/**
+ * LWIP_IPV6_AUTOCONFIG==1: Enable stateless address autoconfiguration as per RFC 4862.
+ */
+#ifndef LWIP_IPV6_AUTOCONFIG
+#define LWIP_IPV6_AUTOCONFIG            (LWIP_IPV6)
+#endif
+
+/**
+ * LWIP_IPV6_DUP_DETECT_ATTEMPTS: Number of duplicate address detection attempts.
+ */
+#ifndef LWIP_IPV6_DUP_DETECT_ATTEMPTS
+#define LWIP_IPV6_DUP_DETECT_ATTEMPTS   1
+#endif
+
+/**
+ * LWIP_IPV6_DHCP6==1: enable DHCPv6 stateful address autoconfiguration.
+ */
+#ifndef LWIP_IPV6_DHCP6
+#define LWIP_IPV6_DHCP6                 0
+#endif
+
+/*
+   ---------------------------------------
+   ---------- Hook options ---------------
+   ---------------------------------------
+*/
+
+/* Hooks are undefined by default, define them to a function if you need them. */
+
+/**
+ * LWIP_HOOK_IP4_INPUT(pbuf, input_netif):
+ * - called from ip_input() (IPv4)
+ * - pbuf: received struct pbuf passed to ip_input()
+ * - input_netif: struct netif on which the packet has been received
+ * Return values:
+ * - 0: Hook has not consumed the packet, packet is processed as normal
+ * - != 0: Hook has consumed the packet.
+ * If the hook consumed the packet, 'pbuf' is in the responsibility of the hook
+ * (i.e. free it when done).
+ */
+
+/**
+ * LWIP_HOOK_IP4_ROUTE(dest):
+ * - called from ip_route() (IPv4)
+ * - dest: destination IPv4 address
+ * Returns the destination netif or NULL if no destination netif is found. In
+ * that case, ip_route() continues as normal.
+ */
+
+/**
+ * LWIP_HOOK_IP4_ROUTE_SRC(dest, src):
+ * - source-based routing for IPv4 (see LWIP_HOOK_IP4_ROUTE(), src may be NULL)
+ */
+
+/**
+ * LWIP_HOOK_ETHARP_GET_GW(netif, dest):
+ * - called from etharp_output() (IPv4)
+ * - netif: the netif used for sending
+ * - dest: the destination IPv4 address
+ * Returns the IPv4 address of the gateway to handle the specified destination
+ * IPv4 address. If NULL is returned, the netif's default gateway is used.
+ * The returned address MUST be reachable on the specified netif!
+ * This function is meant to implement advanced IPv4 routing together with
+ * LWIP_HOOK_IP4_ROUTE(). The actual routing/gateway table implementation is
+ * not part of lwIP but can e.g. be hidden in the netif's state argument.
+*/
+
+/**
+ * LWIP_HOOK_IP6_INPUT(pbuf, input_netif):
+ * - called from ip6_input() (IPv6)
+ * - pbuf: received struct pbuf passed to ip6_input()
+ * - input_netif: struct netif on which the packet has been received
+ * Return values:
+ * - 0: Hook has not consumed the packet, packet is processed as normal
+ * - != 0: Hook has consumed the packet.
+ * If the hook consumed the packet, 'pbuf' is in the responsibility of the hook
+ * (i.e. free it when done).
+ */
+
+/**
+ * LWIP_HOOK_IP6_ROUTE(src, dest):
+ * - called from ip6_route() (IPv6)
+ * - src: sourc IPv6 address
+ * - dest: destination IPv6 address
+ * Returns the destination netif or NULL if no destination netif is found. In
+ * that case, ip6_route() continues as normal.
+ */
+
+/**
+ * LWIP_HOOK_VLAN_CHECK(netif, eth_hdr, vlan_hdr):
+ * - called from ethernet_input() if VLAN support is enabled
+ * - netif: struct netif on which the packet has been received
+ * - eth_hdr: struct eth_hdr of the packet
+ * - vlan_hdr: struct eth_vlan_hdr of the packet
+ * Return values:
+ * - 0: Packet must be dropped.
+ * - != 0: Packet must be accepted.
+ */
+
+/**
+ * LWIP_HOOK_VLAN_SET(netif, eth_hdr, vlan_hdr):
+ * - called from etharp_raw() and etharp_send_ip() if VLAN support is enabled
+ * - netif: struct netif that the packet will be sent through
+ * - eth_hdr: struct eth_hdr of the packet
+ * - vlan_hdr: struct eth_vlan_hdr of the packet
+ * Return values:
+ * - 0: Packet shall not contain VLAN header.
+ * - != 0: Packet shall contain VLAN header.
+ * Hook can be used to set prio_vid field of vlan_hdr.
+ */
+
+/**
+ * LWIP_HOOK_MEMP_AVAILABLE(memp_t_type):
+ * - called from memp_free() when a memp pool was empty and an item is now available
+ */
+
+/*
+   ---------------------------------------
+   ---------- Debugging options ----------
+   ---------------------------------------
+*/
+/**
+ * LWIP_DBG_MIN_LEVEL: After masking, the value of the debug is
+ * compared against this value. If it is smaller, then debugging
+ * messages are written.
+ */
+#ifndef LWIP_DBG_MIN_LEVEL
+#define LWIP_DBG_MIN_LEVEL              LWIP_DBG_LEVEL_ALL
+#endif
+
+/**
+ * LWIP_DBG_TYPES_ON: A mask that can be used to globally enable/disable
+ * debug messages of certain types.
+ */
+#ifndef LWIP_DBG_TYPES_ON
+#define LWIP_DBG_TYPES_ON               LWIP_DBG_ON
+#endif
+
+/**
+ * ETHARP_DEBUG: Enable debugging in etharp.c.
+ */
+#ifndef ETHARP_DEBUG
+#define ETHARP_DEBUG                    LWIP_DBG_OFF
+#endif
+
+/**
+ * NETIF_DEBUG: Enable debugging in netif.c.
+ */
+#ifndef NETIF_DEBUG
+#define NETIF_DEBUG                     LWIP_DBG_OFF
+#endif
+
+/**
+ * PBUF_DEBUG: Enable debugging in pbuf.c.
+ */
+#ifndef PBUF_DEBUG
+#define PBUF_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/**
+ * API_LIB_DEBUG: Enable debugging in api_lib.c.
+ */
+#ifndef API_LIB_DEBUG
+#define API_LIB_DEBUG                   LWIP_DBG_OFF
+#endif
+
+/**
+ * API_MSG_DEBUG: Enable debugging in api_msg.c.
+ */
+#ifndef API_MSG_DEBUG
+#define API_MSG_DEBUG                   LWIP_DBG_OFF
+#endif
+
+/**
+ * SOCKETS_DEBUG: Enable debugging in sockets.c.
+ */
+#ifndef SOCKETS_DEBUG
+#define SOCKETS_DEBUG                   LWIP_DBG_OFF
+#endif
+
+/**
+ * ICMP_DEBUG: Enable debugging in icmp.c.
+ */
+#ifndef ICMP_DEBUG
+#define ICMP_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/**
+ * IGMP_DEBUG: Enable debugging in igmp.c.
+ */
+#ifndef IGMP_DEBUG
+#define IGMP_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/**
+ * INET_DEBUG: Enable debugging in inet.c.
+ */
+#ifndef INET_DEBUG
+#define INET_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/**
+ * IP_DEBUG: Enable debugging for IP.
+ */
+#ifndef IP_DEBUG
+#define IP_DEBUG                        LWIP_DBG_OFF
+#endif
+
+/**
+ * IP_REASS_DEBUG: Enable debugging in ip_frag.c for both frag & reass.
+ */
+#ifndef IP_REASS_DEBUG
+#define IP_REASS_DEBUG                  LWIP_DBG_OFF
+#endif
+
+/**
+ * RAW_DEBUG: Enable debugging in raw.c.
+ */
+#ifndef RAW_DEBUG
+#define RAW_DEBUG                       LWIP_DBG_OFF
+#endif
+
+/**
+ * MEM_DEBUG: Enable debugging in mem.c.
+ */
+#ifndef MEM_DEBUG
+#define MEM_DEBUG                       LWIP_DBG_OFF
+#endif
+
+/**
+ * MEMP_DEBUG: Enable debugging in memp.c.
+ */
+#ifndef MEMP_DEBUG
+#define MEMP_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/**
+ * SYS_DEBUG: Enable debugging in sys.c.
+ */
+#ifndef SYS_DEBUG
+#define SYS_DEBUG                       LWIP_DBG_OFF
+#endif
+
+/**
+ * TIMERS_DEBUG: Enable debugging in timers.c.
+ */
+#ifndef TIMERS_DEBUG
+#define TIMERS_DEBUG                    LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_DEBUG: Enable debugging for TCP.
+ */
+#ifndef TCP_DEBUG
+#define TCP_DEBUG                       LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_INPUT_DEBUG: Enable debugging in tcp_in.c for incoming debug.
+ */
+#ifndef TCP_INPUT_DEBUG
+#define TCP_INPUT_DEBUG                 LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_FR_DEBUG: Enable debugging in tcp_in.c for fast retransmit.
+ */
+#ifndef TCP_FR_DEBUG
+#define TCP_FR_DEBUG                    LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_RTO_DEBUG: Enable debugging in TCP for retransmit
+ * timeout.
+ */
+#ifndef TCP_RTO_DEBUG
+#define TCP_RTO_DEBUG                   LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_CWND_DEBUG: Enable debugging for TCP congestion window.
+ */
+#ifndef TCP_CWND_DEBUG
+#define TCP_CWND_DEBUG                  LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_WND_DEBUG: Enable debugging in tcp_in.c for window updating.
+ */
+#ifndef TCP_WND_DEBUG
+#define TCP_WND_DEBUG                   LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_OUTPUT_DEBUG: Enable debugging in tcp_out.c output functions.
+ */
+#ifndef TCP_OUTPUT_DEBUG
+#define TCP_OUTPUT_DEBUG                LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_RST_DEBUG: Enable debugging for TCP with the RST message.
+ */
+#ifndef TCP_RST_DEBUG
+#define TCP_RST_DEBUG                   LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_QLEN_DEBUG: Enable debugging for TCP queue lengths.
+ */
+#ifndef TCP_QLEN_DEBUG
+#define TCP_QLEN_DEBUG                  LWIP_DBG_OFF
+#endif
+
+/**
+ * UDP_DEBUG: Enable debugging in UDP.
+ */
+#ifndef UDP_DEBUG
+#define UDP_DEBUG                       LWIP_DBG_OFF
+#endif
+
+/**
+ * TCPIP_DEBUG: Enable debugging in tcpip.c.
+ */
+#ifndef TCPIP_DEBUG
+#define TCPIP_DEBUG                     LWIP_DBG_OFF
+#endif
+
+/**
+ * PPP_DEBUG: Enable debugging for PPP.
+ */
+#ifndef PPP_DEBUG
+#define PPP_DEBUG                       LWIP_DBG_OFF
+#endif
+
+/**
+ * SLIP_DEBUG: Enable debugging in slipif.c.
+ */
+#ifndef SLIP_DEBUG
+#define SLIP_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/**
+ * DHCP_DEBUG: Enable debugging in dhcp.c.
+ */
+#ifndef DHCP_DEBUG
+#define DHCP_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/**
+ * AUTOIP_DEBUG: Enable debugging in autoip.c.
+ */
+#ifndef AUTOIP_DEBUG
+#define AUTOIP_DEBUG                    LWIP_DBG_OFF
+#endif
+
+/**
+ * DNS_DEBUG: Enable debugging for DNS.
+ */
+#ifndef DNS_DEBUG
+#define DNS_DEBUG                       LWIP_DBG_OFF
+#endif
+
+/**
+ * IP6_DEBUG: Enable debugging for IPv6.
+ */
+#ifndef IP6_DEBUG
+#define IP6_DEBUG                       LWIP_DBG_OFF
+#endif
+
+/*
+   --------------------------------------------------
+   ---------- Performance tracking options ----------
+   --------------------------------------------------
+*/
+/**
+ * LWIP_PERF: Enable performance testing for lwIP
+ * (if enabled, arch/perf.h is included)
+ */
+#ifndef LWIP_PERF
+#define LWIP_PERF                       0
+#endif
+
+#ifndef THREAD_SAFE_DEBUG
+#define THREAD_SAFE_DEBUG               0
+#endif
+
+#endif /* LWIP_HDR_OPT_H */
diff --git a/tools/sdk/include/lwip/lwip/pbuf.h b/tools/sdk/include/lwip/lwip/pbuf.h
new file mode 100755
index 00000000..aaf5e294
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/pbuf.h
@@ -0,0 +1,231 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#ifndef LWIP_HDR_PBUF_H
+#define LWIP_HDR_PBUF_H
+
+#include "lwip/opt.h"
+#include "lwip/err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** LWIP_SUPPORT_CUSTOM_PBUF==1: Custom pbufs behave much like their pbuf type
+ * but they are allocated by external code (initialised by calling
+ * pbuf_alloced_custom()) and when pbuf_free gives up their last reference, they
+ * are freed by calling pbuf_custom->custom_free_function().
+ * Currently, the pbuf_custom code is only needed for one specific configuration
+ * of IP_FRAG, unless required by external driver/application code. */
+#ifndef LWIP_SUPPORT_CUSTOM_PBUF
+#define LWIP_SUPPORT_CUSTOM_PBUF ((IP_FRAG && !IP_FRAG_USES_STATIC_BUF && !LWIP_NETIF_TX_SINGLE_PBUF) || (LWIP_IPV6 && LWIP_IPV6_FRAG))
+#endif
+
+/* @todo: We need a mechanism to prevent wasting memory in every pbuf
+   (TCP vs. UDP, IPv4 vs. IPv6: UDP/IPv4 packets may waste up to 28 bytes) */
+
+#define PBUF_TRANSPORT_HLEN 20
+#if LWIP_IPV6
+#define PBUF_IP_HLEN        40
+#else
+#define PBUF_IP_HLEN        20
+#endif
+
+typedef enum {
+  PBUF_TRANSPORT,
+  PBUF_IP,
+  PBUF_LINK,
+  PBUF_RAW_TX,
+  PBUF_RAW
+} pbuf_layer;
+
+typedef enum {
+  /** pbuf data is stored in RAM, used for TX mostly, struct pbuf and its payload
+      are allocated in one piece of contiguous memory (so the first payload byte
+      can be calculated from struct pbuf)
+      pbuf_alloc() allocates PBUF_RAM pbufs as unchained pbufs (although that might
+      change in future versions) */
+  PBUF_RAM,
+  /** pbuf data is stored in ROM, i.e. struct pbuf and its payload are located in
+      totally different memory areas. Since it points to ROM, payload does not
+      have to be copied when queued for transmission. */
+  PBUF_ROM,
+  /** pbuf comes from the pbuf pool. Much like PBUF_ROM but payload might change
+      so it has to be duplicated when queued before transmitting, depending on
+      who has a 'ref' to it. */
+  PBUF_REF,
+  /** pbuf payload refers to RAM. This one comes from a pool and should be used
+      for RX. Payload can be chained (scatter-gather RX) but like PBUF_RAM, struct
+      pbuf and its payload are allocated in one piece of contiguous memory (so
+      the first payload byte can be calculated from struct pbuf) */
+  PBUF_POOL
+} pbuf_type;
+
+
+/** indicates this packet's data should be immediately passed to the application */
+#define PBUF_FLAG_PUSH      0x01U
+/** indicates this is a custom pbuf: pbuf_free calls pbuf_custom->custom_free_function()
+    when the last reference is released (plus custom PBUF_RAM cannot be trimmed) */
+#define PBUF_FLAG_IS_CUSTOM 0x02U
+/** indicates this pbuf is UDP multicast to be looped back */
+#define PBUF_FLAG_MCASTLOOP 0x04U
+/** indicates this pbuf was received as link-level broadcast */
+#define PBUF_FLAG_LLBCAST   0x08U
+/** indicates this pbuf was received as link-level multicast */
+#define PBUF_FLAG_LLMCAST   0x10U
+/** indicates this pbuf includes a TCP FIN flag */
+#define PBUF_FLAG_TCP_FIN   0x20U
+
+struct pbuf {
+  /** next pbuf in singly linked pbuf chain */
+  struct pbuf *next;
+
+  /** pointer to the actual data in the buffer */
+  void *payload;
+
+  /**
+   * total length of this buffer and all next buffers in chain
+   * belonging to the same packet.
+   *
+   * For non-queue packet chains this is the invariant:
+   * p->tot_len == p->len + (p->next? p->next->tot_len: 0)
+   */
+  u16_t tot_len;
+
+  /** length of this buffer */
+  u16_t len;
+
+  /** pbuf_type as u8_t instead of enum to save space */
+  u8_t /*pbuf_type*/ type;
+
+  /** misc flags */
+  u8_t flags;
+
+  /**
+   * the reference count always equals the number of pointers
+   * that refer to this pbuf. This can be pointers from an application,
+   * the stack itself, or pbuf->next pointers from a chain.
+   */
+  u16_t ref;
+  
+#ifdef LWIP_ESP8266
+  void  *eb;
+#endif
+};
+
+
+/** Helper struct for const-correctness only.
+ * The only meaning of this one is to provide a const payload pointer
+ * for PBUF_ROM type.
+ */
+struct pbuf_rom {
+  /** next pbuf in singly linked pbuf chain */
+  struct pbuf *next;
+
+  /** pointer to the actual data in the buffer */
+  const void *payload;
+};
+
+#if LWIP_SUPPORT_CUSTOM_PBUF
+/** Prototype for a function to free a custom pbuf */
+typedef void (*pbuf_free_custom_fn)(struct pbuf *p);
+
+/** A custom pbuf: like a pbuf, but following a function pointer to free it. */
+struct pbuf_custom {
+  /** The actual pbuf */
+  struct pbuf pbuf;
+  /** This function is called when pbuf_free deallocates this pbuf(_custom) */
+  pbuf_free_custom_fn custom_free_function;
+};
+#endif /* LWIP_SUPPORT_CUSTOM_PBUF */
+
+#if LWIP_TCP && TCP_QUEUE_OOSEQ
+/** Define this to 0 to prevent freeing ooseq pbufs when the PBUF_POOL is empty */
+#ifndef PBUF_POOL_FREE_OOSEQ
+#define PBUF_POOL_FREE_OOSEQ 1
+#endif /* PBUF_POOL_FREE_OOSEQ */
+#if NO_SYS && PBUF_POOL_FREE_OOSEQ
+extern volatile u8_t pbuf_free_ooseq_pending;
+void pbuf_free_ooseq(void);
+/** When not using sys_check_timeouts(), call PBUF_CHECK_FREE_OOSEQ()
+    at regular intervals from main level to check if ooseq pbufs need to be
+    freed! */
+#define PBUF_CHECK_FREE_OOSEQ() do { if(pbuf_free_ooseq_pending) { \
+  /* pbuf_alloc() reported PBUF_POOL to be empty -> try to free some \
+     ooseq queued pbufs now */ \
+  pbuf_free_ooseq(); }}while(0)
+#endif /* NO_SYS && PBUF_POOL_FREE_OOSEQ*/
+#endif /* LWIP_TCP && TCP_QUEUE_OOSEQ */
+
+/* Initializes the pbuf module. This call is empty for now, but may not be in future. */
+#define pbuf_init()
+
+struct pbuf *pbuf_alloc(pbuf_layer l, u16_t length, pbuf_type type);
+#if LWIP_SUPPORT_CUSTOM_PBUF
+struct pbuf *pbuf_alloced_custom(pbuf_layer l, u16_t length, pbuf_type type,
+                                 struct pbuf_custom *p, void *payload_mem,
+                                 u16_t payload_mem_len);
+#endif /* LWIP_SUPPORT_CUSTOM_PBUF */
+void pbuf_realloc(struct pbuf *p, u16_t size);
+u8_t pbuf_header(struct pbuf *p, s16_t header_size);
+u8_t pbuf_header_force(struct pbuf *p, s16_t header_size);
+void pbuf_ref(struct pbuf *p);
+u8_t pbuf_free(struct pbuf *p);
+u8_t pbuf_clen(struct pbuf *p);
+void pbuf_cat(struct pbuf *head, struct pbuf *tail);
+void pbuf_chain(struct pbuf *head, struct pbuf *tail);
+struct pbuf *pbuf_dechain(struct pbuf *p);
+err_t pbuf_copy(struct pbuf *p_to, struct pbuf *p_from);
+u16_t pbuf_copy_partial(struct pbuf *p, void *dataptr, u16_t len, u16_t offset);
+err_t pbuf_take(struct pbuf *buf, const void *dataptr, u16_t len);
+err_t pbuf_take_at(struct pbuf *buf, const void *dataptr, u16_t len, u16_t offset);
+struct pbuf *pbuf_skip(struct pbuf* in, u16_t in_offset, u16_t* out_offset);
+struct pbuf *pbuf_coalesce(struct pbuf *p, pbuf_layer layer);
+#if LWIP_CHECKSUM_ON_COPY
+err_t pbuf_fill_chksum(struct pbuf *p, u16_t start_offset, const void *dataptr,
+                       u16_t len, u16_t *chksum);
+#endif /* LWIP_CHECKSUM_ON_COPY */
+#if LWIP_TCP && TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
+void pbuf_split_64k(struct pbuf *p, struct pbuf **rest);
+#endif /* LWIP_TCP && TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
+
+u8_t pbuf_get_at(struct pbuf* p, u16_t offset);
+void pbuf_put_at(struct pbuf* p, u16_t offset, u8_t data);
+u16_t pbuf_memcmp(struct pbuf* p, u16_t offset, const void* s2, u16_t n);
+u16_t pbuf_memfind(struct pbuf* p, const void* mem, u16_t mem_len, u16_t start_offset);
+u16_t pbuf_strstr(struct pbuf* p, const char* substr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_PBUF_H */
diff --git a/tools/sdk/include/lwip/lwip/pppapi.h b/tools/sdk/include/lwip/lwip/pppapi.h
new file mode 100755
index 00000000..3ddf3daf
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/pppapi.h
@@ -0,0 +1,148 @@
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#ifndef __LWIP_PPPAPI_H__
+#define __LWIP_PPPAPI_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_PPP_API /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/sys.h"
+#include "lwip/netif.h"
+#include "lwip/priv/tcpip_priv.h"
+#include "netif/ppp/ppp.h"
+#if PPPOS_SUPPORT
+#include "netif/ppp/pppos.h"
+#endif /* PPPOS_SUPPORT */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct pppapi_msg_msg {
+  ppp_pcb *ppp;
+  union {
+    struct {
+      u8_t authtype;
+      const char *user;
+      const char *passwd;
+    } setauth;
+#if PPP_NOTIFY_PHASE
+    struct {
+      ppp_notify_phase_cb_fn notify_phase_cb;
+    } setnotifyphasecb;
+#endif /* PPP_NOTIFY_PHASE */
+#if PPPOS_SUPPORT
+    struct {
+      struct netif *pppif;
+      pppos_output_cb_fn output_cb;
+      ppp_link_status_cb_fn link_status_cb;
+      void *ctx_cb;
+    } serialcreate;
+#endif /* PPPOS_SUPPORT */
+#if PPPOE_SUPPORT
+    struct {
+      struct netif *pppif;
+      struct netif *ethif;
+      const char *service_name;
+      const char *concentrator_name;
+      ppp_link_status_cb_fn link_status_cb;
+      void *ctx_cb;
+    } ethernetcreate;
+#endif /* PPPOE_SUPPORT */
+#if PPPOL2TP_SUPPORT
+    struct {
+      struct netif *pppif;
+      struct netif *netif;
+      ip_addr_t *ipaddr;
+      u16_t port;
+#if PPPOL2TP_AUTH_SUPPORT
+      const u8_t *secret;
+      u8_t secret_len;
+#endif /* PPPOL2TP_AUTH_SUPPORT */
+      ppp_link_status_cb_fn link_status_cb;
+      void *ctx_cb;
+    } l2tpcreate;
+#endif /* PPPOL2TP_SUPPORT */
+    struct {
+      u16_t holdoff;
+    } connect;
+#if PPP_SERVER
+    struct {
+      struct ppp_addrs *addrs;
+    } listen;
+#endif /* PPP_SERVER */
+    struct {
+      u8_t nocarrier;
+    } close;
+    struct {
+      u8_t cmd;
+      void *arg;
+    } ioctl;
+  } msg;
+};
+
+struct pppapi_msg {
+  struct tcpip_api_call call;
+  struct pppapi_msg_msg msg;
+};
+
+/* API for application */
+void pppapi_set_default(ppp_pcb *pcb);
+void pppapi_set_auth(ppp_pcb *pcb, u8_t authtype, const char *user, const char *passwd);
+#if PPP_NOTIFY_PHASE
+void pppapi_set_notify_phase_callback(ppp_pcb *pcb, ppp_notify_phase_cb_fn notify_phase_cb);
+#endif /* PPP_NOTIFY_PHASE */
+#if PPPOS_SUPPORT
+ppp_pcb *pppapi_pppos_create(struct netif *pppif, pppos_output_cb_fn output_cb, ppp_link_status_cb_fn link_status_cb, void *ctx_cb);
+#endif /* PPPOS_SUPPORT */
+#if PPPOE_SUPPORT
+ppp_pcb *pppapi_pppoe_create(struct netif *pppif, struct netif *ethif, const char *service_name,
+                                const char *concentrator_name, ppp_link_status_cb_fn link_status_cb,
+                                void *ctx_cb);
+#endif /* PPPOE_SUPPORT */
+#if PPPOL2TP_SUPPORT
+ppp_pcb *pppapi_pppol2tp_create(struct netif *pppif, struct netif *netif, ip_addr_t *ipaddr, u16_t port,
+                            const u8_t *secret, u8_t secret_len,
+                            ppp_link_status_cb_fn link_status_cb, void *ctx_cb);
+#endif /* PPPOL2TP_SUPPORT */
+err_t pppapi_connect(ppp_pcb *pcb, u16_t holdoff);
+#if PPP_SERVER
+err_t pppapi_listen(ppp_pcb *pcb, struct ppp_addrs *addrs);
+#endif /* PPP_SERVER */
+err_t pppapi_close(ppp_pcb *pcb, u8_t nocarrier);
+err_t pppapi_free(ppp_pcb *pcb);
+err_t pppapi_ioctl(ppp_pcb *pcb, u8_t cmd, void *arg);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_PPP_API */
+
+#endif /* __LWIP_PPPAPI_H__ */
diff --git a/tools/sdk/include/lwip/lwip/priv/api_msg.h b/tools/sdk/include/lwip/lwip/priv/api_msg.h
new file mode 100755
index 00000000..329fa0de
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/priv/api_msg.h
@@ -0,0 +1,260 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef LWIP_HDR_API_MSG_H
+#define LWIP_HDR_API_MSG_H
+
+#include "lwip/opt.h"
+
+#if LWIP_NETCONN || LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */
+/* Note: Netconn API is always available when sockets are enabled -
+ * sockets are implemented on top of them */
+
+#include  /* for size_t */
+
+#include "lwip/ip_addr.h"
+#include "lwip/err.h"
+#include "lwip/sys.h"
+#include "lwip/igmp.h"
+#include "lwip/api.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if LWIP_MPU_COMPATIBLE
+#define API_MSG_M_DEF(m)      m
+#define API_MSG_M_DEF_C(t, m) t m
+#if LWIP_NETCONN_SEM_PER_THREAD
+#define API_MSG_M_DEF_SEM(m)  *m
+#else
+#define API_MSG_M_DEF_SEM(m)  API_MSG_M_DEF(m)
+#endif
+#else /* LWIP_MPU_COMPATIBLE */
+#define API_MSG_M_DEF(m)      *m
+#define API_MSG_M_DEF_C(t, m) const t * m
+#define API_MSG_M_DEF_SEM(m)  API_MSG_M_DEF(m)
+#endif /* LWIP_MPU_COMPATIBLE */
+
+/* For the netconn API, these values are use as a bitmask! */
+#define NETCONN_SHUT_RD   1
+#define NETCONN_SHUT_WR   2
+#define NETCONN_SHUT_RDWR (NETCONN_SHUT_RD | NETCONN_SHUT_WR)
+
+/* IP addresses and port numbers are expected to be in
+ * the same byte order as in the corresponding pcb.
+ */
+/** This struct includes everything that is necessary to execute a function
+    for a netconn in another thread context (mainly used to process netconns
+    in the tcpip_thread context to be thread safe). */
+struct api_msg_msg {
+  /** The netconn which to process - always needed: it includes the semaphore
+      which is used to block the application thread until the function finished. */
+  struct netconn *conn;
+  /** The return value of the function executed in tcpip_thread. */
+  err_t err;
+  /** Depending on the executed function, one of these union members is used */
+  union {
+    /** used for lwip_netconn_do_send */
+    struct netbuf *b;
+    /** used for lwip_netconn_do_newconn */
+    struct {
+      u8_t proto;
+    } n;
+    /** used for lwip_netconn_do_bind and lwip_netconn_do_connect */
+    struct {
+      API_MSG_M_DEF_C(ip_addr_t, ipaddr);
+      u16_t port;
+    } bc;
+    /** used for lwip_netconn_do_getaddr */
+    struct {
+      ip_addr_t API_MSG_M_DEF(ipaddr);
+      u16_t API_MSG_M_DEF(port);
+      u8_t local;
+    } ad;
+    /** used for lwip_netconn_do_write */
+    struct {
+      const void *dataptr;
+      size_t len;
+      u8_t apiflags;
+#if LWIP_SO_SNDTIMEO
+      u32_t time_started;
+#endif /* LWIP_SO_SNDTIMEO */
+    } w;
+    /** used for lwip_netconn_do_recv */
+    struct {
+      u32_t len;
+    } r;
+#if LWIP_TCP
+    /** used for lwip_netconn_do_close (/shutdown) */
+    struct {
+      u8_t shut;
+#if LWIP_SO_SNDTIMEO || LWIP_SO_LINGER
+      u32_t time_started;
+#else /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */
+      u8_t polls_left;
+#endif /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */
+    } sd;
+#endif /* LWIP_TCP */
+#if LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD)
+    /** used for lwip_netconn_do_join_leave_group */
+    struct {
+      API_MSG_M_DEF_C(ip_addr_t, multiaddr);
+      API_MSG_M_DEF_C(ip_addr_t, netif_addr);
+      enum netconn_igmp join_or_leave;
+    } jl;
+#endif /* LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) */
+#if TCP_LISTEN_BACKLOG
+    struct {
+      u8_t backlog;
+    } lb;
+#endif /* TCP_LISTEN_BACKLOG */
+  } msg;
+#if LWIP_NETCONN_SEM_PER_THREAD
+  sys_sem_t* op_completed_sem;
+#endif /* LWIP_NETCONN_SEM_PER_THREAD */
+};
+
+#if LWIP_NETCONN_SEM_PER_THREAD
+#define LWIP_API_MSG_SEM(msg)          ((msg)->op_completed_sem)
+#else /* LWIP_NETCONN_SEM_PER_THREAD */
+#define LWIP_API_MSG_SEM(msg)          (&(msg)->conn->op_completed)
+#endif /* LWIP_NETCONN_SEM_PER_THREAD */
+
+
+/** This struct contains a function to execute in another thread context and
+    a struct api_msg_msg that serves as an argument for this function.
+    This is passed to tcpip_apimsg to execute functions in tcpip_thread context. */
+struct api_msg {
+  /** function to execute in tcpip_thread context */
+  void (* function)(void *msg);
+  /** arguments for this function */
+  struct api_msg_msg msg;
+};
+
+#if LWIP_DNS
+/** As lwip_netconn_do_gethostbyname requires more arguments but doesn't require a netconn,
+    it has its own struct (to avoid struct api_msg getting bigger than necessary).
+    lwip_netconn_do_gethostbyname must be called using tcpip_callback instead of tcpip_apimsg
+    (see netconn_gethostbyname). */
+struct dns_api_msg {
+  /** Hostname to query or dotted IP address string */
+#if LWIP_MPU_COMPATIBLE
+  char name[DNS_MAX_NAME_LENGTH];
+#else /* LWIP_MPU_COMPATIBLE */
+  const char *name;
+#endif /* LWIP_MPU_COMPATIBLE */
+  /** The resolved address is stored here */
+  ip_addr_t API_MSG_M_DEF(addr);
+#if LWIP_IPV4 && LWIP_IPV6
+  /** Type of resolve call */
+  u8_t dns_addrtype;
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+  /** This semaphore is posted when the name is resolved, the application thread
+      should wait on it. */
+  sys_sem_t API_MSG_M_DEF_SEM(sem);
+  /** Errors are given back here */
+  err_t API_MSG_M_DEF(err);
+};
+#endif /* LWIP_DNS */
+
+#if LWIP_NETCONN_SEM_PER_THREAD
+#ifdef LWIP_ESP8266
+#define LWIP_NETCONN_THREAD_SEM_GET() sys_thread_sem_get()
+#define LWIP_NETCONN_THREAD_SEM_ALLOC() sys_thread_sem_init()
+#define LWIP_NETCONN_THREAD_SEM_FREE() sys_thread_sem_deinit()
+#endif
+#endif
+
+#if LWIP_TCPIP_CORE_LOCKING
+#ifdef LWIP_DEBUG
+#define TCIP_APIMSG_SET_ERR(m, e) (m)->msg.err = e  /* catch functions that don't set err */
+#else
+#define TCIP_APIMSG_SET_ERR(m, e)
+#endif
+#if LWIP_NETCONN_SEM_PER_THREAD
+#define TCPIP_APIMSG_SET_SEM(m) ((m)->msg.op_completed_sem = LWIP_NETCONN_THREAD_SEM_GET())
+#else
+#define TCPIP_APIMSG_SET_SEM(m)
+#endif
+#define TCPIP_APIMSG_NOERR(m,f) do { \
+  TCIP_APIMSG_SET_ERR(m, ERR_VAL); \
+  TCPIP_APIMSG_SET_SEM(m); \
+  LOCK_TCPIP_CORE(); \
+  f(&((m)->msg)); \
+  UNLOCK_TCPIP_CORE(); \
+} while(0)
+#define TCPIP_APIMSG(m,f,e)   do { \
+  TCPIP_APIMSG_NOERR(m,f); \
+  (e) = (m)->msg.err; \
+} while(0)
+#define TCPIP_APIMSG_ACK(m)   NETCONN_SET_SAFE_ERR((m)->conn, (m)->err)
+#else /* LWIP_TCPIP_CORE_LOCKING */
+#define TCPIP_APIMSG_NOERR(m,f) do { (m)->function = f; tcpip_apimsg(m); } while(0)
+#define TCPIP_APIMSG(m,f,e)   do { (m)->function = f; (e) = tcpip_apimsg(m); } while(0)
+#define TCPIP_APIMSG_ACK(m)   do { NETCONN_SET_SAFE_ERR((m)->conn, (m)->err); sys_sem_signal(LWIP_API_MSG_SEM(m)); } while(0)
+
+#ifdef LWIP_ESP8266
+#define TCPIP_APIMSG_ACK_SND(m)  do { NETCONN_SET_SAFE_ERR((m)->conn, (m)->err); sys_sem_signal(LWIP_API_MSG_SND_SEM(m)); } while(0) 
+#endif
+
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+
+void lwip_netconn_do_newconn         (void *m);
+void lwip_netconn_do_delconn         (void *m);
+void lwip_netconn_do_bind            (void *m);
+void lwip_netconn_do_connect         (void *m);
+void lwip_netconn_do_disconnect      (void *m);
+void lwip_netconn_do_listen          (void *m);
+void lwip_netconn_do_send            (void *m);
+void lwip_netconn_do_recv            (void *m);
+void lwip_netconn_do_write           (void *m);
+void lwip_netconn_do_getaddr         (void *m);
+void lwip_netconn_do_close           (void *m);
+void lwip_netconn_do_shutdown        (void *m);
+#if LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD)
+void lwip_netconn_do_join_leave_group(void *m);
+#endif /* LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) */
+
+#if LWIP_DNS
+void lwip_netconn_do_gethostbyname(void *arg);
+#endif /* LWIP_DNS */
+
+struct netconn* netconn_alloc(enum netconn_type t, netconn_callback callback);
+void netconn_free(struct netconn *conn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_NETCONN || LWIP_SOCKET */
+
+#endif /* LWIP_HDR_API_MSG_H */
diff --git a/tools/sdk/include/lwip/lwip/priv/memp_priv.h b/tools/sdk/include/lwip/lwip/priv/memp_priv.h
new file mode 100755
index 00000000..34edb9d9
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/priv/memp_priv.h
@@ -0,0 +1,163 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#ifndef LWIP_HDR_MEMP_PRIV_H
+#define LWIP_HDR_MEMP_PRIV_H
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+    
+#include "lwip/mem.h"
+
+#if MEMP_OVERFLOW_CHECK
+/* if MEMP_OVERFLOW_CHECK is turned on, we reserve some bytes at the beginning
+ * and at the end of each element, initialize them as 0xcd and check
+ * them later. */
+/* If MEMP_OVERFLOW_CHECK is >= 2, on every call to memp_malloc or memp_free,
+ * every single element in each pool is checked!
+ * This is VERY SLOW but also very helpful. */
+/* MEMP_SANITY_REGION_BEFORE and MEMP_SANITY_REGION_AFTER can be overridden in
+ * lwipopts.h to change the amount reserved for checking. */
+#ifndef MEMP_SANITY_REGION_BEFORE
+#define MEMP_SANITY_REGION_BEFORE  16
+#endif /* MEMP_SANITY_REGION_BEFORE*/
+#if MEMP_SANITY_REGION_BEFORE > 0
+#define MEMP_SANITY_REGION_BEFORE_ALIGNED    LWIP_MEM_ALIGN_SIZE(MEMP_SANITY_REGION_BEFORE)
+#else
+#define MEMP_SANITY_REGION_BEFORE_ALIGNED    0
+#endif /* MEMP_SANITY_REGION_BEFORE*/
+#ifndef MEMP_SANITY_REGION_AFTER
+#define MEMP_SANITY_REGION_AFTER   16
+#endif /* MEMP_SANITY_REGION_AFTER*/
+#if MEMP_SANITY_REGION_AFTER > 0
+#define MEMP_SANITY_REGION_AFTER_ALIGNED     LWIP_MEM_ALIGN_SIZE(MEMP_SANITY_REGION_AFTER)
+#else
+#define MEMP_SANITY_REGION_AFTER_ALIGNED     0
+#endif /* MEMP_SANITY_REGION_AFTER*/
+
+/* MEMP_SIZE: save space for struct memp and for sanity check */
+#define MEMP_SIZE          (LWIP_MEM_ALIGN_SIZE(sizeof(struct memp)) + MEMP_SANITY_REGION_BEFORE_ALIGNED)
+#define MEMP_ALIGN_SIZE(x) (LWIP_MEM_ALIGN_SIZE(x) + MEMP_SANITY_REGION_AFTER_ALIGNED)
+
+#else /* MEMP_OVERFLOW_CHECK */
+
+/* No sanity checks
+ * We don't need to preserve the struct memp while not allocated, so we
+ * can save a little space and set MEMP_SIZE to 0.
+ */
+#define MEMP_SIZE           0
+#define MEMP_ALIGN_SIZE(x) (LWIP_MEM_ALIGN_SIZE(x))
+
+#endif /* MEMP_OVERFLOW_CHECK */
+
+struct memp {
+  struct memp *next;
+#if MEMP_OVERFLOW_CHECK
+  const char *file;
+  int line;
+#endif /* MEMP_OVERFLOW_CHECK */
+};
+
+#if MEM_USE_POOLS
+/* Use a helper type to get the start and end of the user "memory pools" for mem_malloc */
+typedef enum {
+    /* Get the first (via:
+       MEMP_POOL_HELPER_START = ((u8_t) 1*MEMP_POOL_A + 0*MEMP_POOL_B + 0*MEMP_POOL_C + 0)*/
+    MEMP_POOL_HELPER_FIRST = ((u8_t)
+#define LWIP_MEMPOOL(name,num,size,desc)
+#define LWIP_MALLOC_MEMPOOL_START 1
+#define LWIP_MALLOC_MEMPOOL(num, size) * MEMP_POOL_##size + 0
+#define LWIP_MALLOC_MEMPOOL_END
+#include "lwip/priv/memp_std.h"
+    ) ,
+    /* Get the last (via:
+       MEMP_POOL_HELPER_END = ((u8_t) 0 + MEMP_POOL_A*0 + MEMP_POOL_B*0 + MEMP_POOL_C*1) */
+    MEMP_POOL_HELPER_LAST = ((u8_t)
+#define LWIP_MEMPOOL(name,num,size,desc)
+#define LWIP_MALLOC_MEMPOOL_START
+#define LWIP_MALLOC_MEMPOOL(num, size) 0 + MEMP_POOL_##size *
+#define LWIP_MALLOC_MEMPOOL_END 1
+#include "lwip/priv/memp_std.h"
+    )
+} memp_pool_helper_t;
+
+/* The actual start and stop values are here (cast them over)
+   We use this helper type and these defines so we can avoid using const memp_t values */
+#define MEMP_POOL_FIRST ((memp_t) MEMP_POOL_HELPER_FIRST)
+#define MEMP_POOL_LAST   ((memp_t) MEMP_POOL_HELPER_LAST)
+#endif /* MEM_USE_POOLS */
+
+struct memp_desc {
+  /** Element size */
+  u16_t size;
+
+#if !MEMP_MEM_MALLOC
+  /** Number of elements */
+  u16_t num;
+
+#if defined(LWIP_DEBUG) || MEMP_OVERFLOW_CHECK
+  /** Textual description */
+  const char *desc;
+#endif /* LWIP_DEBUG || MEMP_OVERFLOW_CHECK */
+
+  /** Base */
+  u8_t *base;  
+
+  /** First free element of each pool. Elements form a linked list. */
+  struct memp **tab;
+#endif /* MEMP_MEM_MALLOC */
+};
+
+#ifdef LWIP_DEBUG
+#define DECLARE_LWIP_MEMPOOL_DESC(desc) (desc),
+#else
+#define DECLARE_LWIP_MEMPOOL_DESC(desc)
+#endif
+
+void memp_init_pool(const struct memp_desc *desc);
+
+#if MEMP_OVERFLOW_CHECK
+void *memp_malloc_pool_fn(const struct memp_desc* desc, const char* file, const int line);
+#define memp_malloc_pool(d) memp_malloc_pool_fn((d), __FILE__, __LINE__)
+#else
+void *memp_malloc_pool(const struct memp_desc *desc);
+#endif
+void  memp_free_pool(const struct memp_desc* desc, void *mem);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_MEMP_PRIV_H */
diff --git a/tools/sdk/include/lwip/lwip/priv/memp_std.h b/tools/sdk/include/lwip/lwip/priv/memp_std.h
new file mode 100755
index 00000000..4def116d
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/priv/memp_std.h
@@ -0,0 +1,151 @@
+/*
+ * SETUP: Make sure we define everything we will need.
+ *
+ * We have create three types of pools:
+ *   1) MEMPOOL - standard pools
+ *   2) MALLOC_MEMPOOL - to be used by mem_malloc in mem.c
+ *   3) PBUF_MEMPOOL - a mempool of pbuf's, so include space for the pbuf struct
+ *
+ * If the include'r doesn't require any special treatment of each of the types
+ * above, then will declare #2 & #3 to be just standard mempools.
+ */
+#ifndef LWIP_MALLOC_MEMPOOL
+/* This treats "malloc pools" just like any other pool.
+   The pools are a little bigger to provide 'size' as the amount of user data. */
+#define LWIP_MALLOC_MEMPOOL(num, size) LWIP_MEMPOOL(POOL_##size, num, (size + LWIP_MEM_ALIGN_SIZE(sizeof(struct memp_malloc_helper))), "MALLOC_"#size)
+#define LWIP_MALLOC_MEMPOOL_START
+#define LWIP_MALLOC_MEMPOOL_END
+#endif /* LWIP_MALLOC_MEMPOOL */
+
+#ifndef LWIP_PBUF_MEMPOOL
+/* This treats "pbuf pools" just like any other pool.
+ * Allocates buffers for a pbuf struct AND a payload size */
+#define LWIP_PBUF_MEMPOOL(name, num, payload, desc) LWIP_MEMPOOL(name, num, (MEMP_ALIGN_SIZE(sizeof(struct pbuf)) + MEMP_ALIGN_SIZE(payload)), desc)
+#endif /* LWIP_PBUF_MEMPOOL */
+
+
+/*
+ * A list of internal pools used by LWIP.
+ *
+ * LWIP_MEMPOOL(pool_name, number_elements, element_size, pool_description)
+ *     creates a pool name MEMP_pool_name. description is used in stats.c
+ */
+#if LWIP_RAW
+LWIP_MEMPOOL(RAW_PCB,        MEMP_NUM_RAW_PCB,         sizeof(struct raw_pcb),        "RAW_PCB")
+#endif /* LWIP_RAW */
+
+#if LWIP_UDP
+LWIP_MEMPOOL(UDP_PCB,        MEMP_NUM_UDP_PCB,         sizeof(struct udp_pcb),        "UDP_PCB")
+#endif /* LWIP_UDP */
+
+#if LWIP_TCP
+LWIP_MEMPOOL(TCP_PCB,        MEMP_NUM_TCP_PCB,         sizeof(struct tcp_pcb),        "TCP_PCB")
+LWIP_MEMPOOL(TCP_PCB_LISTEN, MEMP_NUM_TCP_PCB_LISTEN,  sizeof(struct tcp_pcb_listen), "TCP_PCB_LISTEN")
+LWIP_MEMPOOL(TCP_SEG,        MEMP_NUM_TCP_SEG,         sizeof(struct tcp_seg),        "TCP_SEG")
+#endif /* LWIP_TCP */
+
+#if LWIP_IPV4 && IP_REASSEMBLY
+LWIP_MEMPOOL(REASSDATA,      MEMP_NUM_REASSDATA,       sizeof(struct ip_reassdata),   "REASSDATA")
+#endif /* LWIP_IPV4 && IP_REASSEMBLY */
+#if (IP_FRAG && !IP_FRAG_USES_STATIC_BUF && !LWIP_NETIF_TX_SINGLE_PBUF) || (LWIP_IPV6 && LWIP_IPV6_FRAG)
+LWIP_MEMPOOL(FRAG_PBUF,      MEMP_NUM_FRAG_PBUF,       sizeof(struct pbuf_custom_ref),"FRAG_PBUF")
+#endif /* IP_FRAG && !IP_FRAG_USES_STATIC_BUF && !LWIP_NETIF_TX_SINGLE_PBUF */
+
+#if LWIP_NETCONN || LWIP_SOCKET
+LWIP_MEMPOOL(NETBUF,         MEMP_NUM_NETBUF,          sizeof(struct netbuf),         "NETBUF")
+LWIP_MEMPOOL(NETCONN,        MEMP_NUM_NETCONN,         sizeof(struct netconn),        "NETCONN")
+#endif /* LWIP_NETCONN || LWIP_SOCKET */
+
+#if NO_SYS==0
+LWIP_MEMPOOL(TCPIP_MSG_API,  MEMP_NUM_TCPIP_MSG_API,   sizeof(struct tcpip_msg),      "TCPIP_MSG_API")
+#if LWIP_MPU_COMPATIBLE
+LWIP_MEMPOOL(API_MSG,        MEMP_NUM_API_MSG,         sizeof(struct api_msg),        "API_MSG")
+#if LWIP_DNS
+LWIP_MEMPOOL(DNS_API_MSG,    MEMP_NUM_DNS_API_MSG,     sizeof(struct dns_api_msg),    "DNS_API_MSG")
+#endif
+#if LWIP_SOCKET && !LWIP_TCPIP_CORE_LOCKING
+LWIP_MEMPOOL(SOCKET_SETGETSOCKOPT_DATA, MEMP_NUM_SOCKET_SETGETSOCKOPT_DATA, sizeof(struct lwip_setgetsockopt_data), "SOCKET_SETGETSOCKOPT_DATA")
+#endif
+#if LWIP_NETIF_API
+LWIP_MEMPOOL(NETIFAPI_MSG,   MEMP_NUM_NETIFAPI_MSG,    sizeof(struct netifapi_msg),   "NETIFAPI_MSG")
+#endif
+#endif /* LWIP_MPU_COMPATIBLE */
+#if !LWIP_TCPIP_CORE_LOCKING_INPUT
+LWIP_MEMPOOL(TCPIP_MSG_INPKT,MEMP_NUM_TCPIP_MSG_INPKT, sizeof(struct tcpip_msg),      "TCPIP_MSG_INPKT")
+#endif /* !LWIP_TCPIP_CORE_LOCKING_INPUT */
+#endif /* NO_SYS==0 */
+
+#if LWIP_IPV4 && LWIP_ARP && ARP_QUEUEING
+LWIP_MEMPOOL(ARP_QUEUE,      MEMP_NUM_ARP_QUEUE,       sizeof(struct etharp_q_entry), "ARP_QUEUE")
+#endif /* LWIP_IPV4 && LWIP_ARP && ARP_QUEUEING */
+
+#if LWIP_IGMP
+LWIP_MEMPOOL(IGMP_GROUP,     MEMP_NUM_IGMP_GROUP,      sizeof(struct igmp_group),     "IGMP_GROUP")
+#endif /* LWIP_IGMP */
+
+#if (!NO_SYS || (NO_SYS && !NO_SYS_NO_TIMERS)) /* LWIP_TIMERS */
+LWIP_MEMPOOL(SYS_TIMEOUT,    MEMP_NUM_SYS_TIMEOUT,     sizeof(struct sys_timeo),      "SYS_TIMEOUT")
+#endif /* LWIP_TIMERS */
+
+#if LWIP_DNS && LWIP_SOCKET
+LWIP_MEMPOOL(NETDB,          MEMP_NUM_NETDB,           NETDB_ELEM_SIZE,               "NETDB")
+#endif /* LWIP_DNS && LWIP_SOCKET */
+#if LWIP_DNS && DNS_LOCAL_HOSTLIST && DNS_LOCAL_HOSTLIST_IS_DYNAMIC
+LWIP_MEMPOOL(LOCALHOSTLIST,  MEMP_NUM_LOCALHOSTLIST,   LOCALHOSTLIST_ELEM_SIZE,       "LOCALHOSTLIST")
+#endif /* LWIP_DNS && DNS_LOCAL_HOSTLIST && DNS_LOCAL_HOSTLIST_IS_DYNAMIC */
+
+#if PPP_SUPPORT
+LWIP_MEMPOOL(PPP_PCB,       MEMP_NUM_PPP_PCB,              sizeof(ppp_pcb),             "PPP_PCB")
+#if PPPOS_SUPPORT
+LWIP_MEMPOOL(PPPOS_PCB,     MEMP_NUM_PPPOS_INTERFACES,     sizeof(pppos_pcb),           "PPPOS_PCB")
+#endif /* PPPOS_SUPPORT */
+#if PPPOE_SUPPORT
+LWIP_MEMPOOL(PPPOE_IF,      MEMP_NUM_PPPOE_INTERFACES,     sizeof(struct pppoe_softc),  "PPPOE_IF")
+#endif /* PPPOE_SUPPORT */
+#if PPPOL2TP_SUPPORT
+LWIP_MEMPOOL(PPPOL2TP_PCB,  MEMP_NUM_PPPOL2TP_INTERFACES,  sizeof(pppol2tp_pcb),        "PPPOL2TP_PCB")
+#endif /* PPPOL2TP_SUPPORT */
+#endif /* PPP_SUPPORT */
+
+#if LWIP_IPV6 && LWIP_ND6_QUEUEING
+LWIP_MEMPOOL(ND6_QUEUE,      MEMP_NUM_ND6_QUEUE,       sizeof(struct nd6_q_entry), "ND6_QUEUE")
+#endif /* LWIP_IPV6 && LWIP_ND6_QUEUEING */
+
+#if LWIP_IPV6 && LWIP_IPV6_REASS
+LWIP_MEMPOOL(IP6_REASSDATA,      MEMP_NUM_REASSDATA,       sizeof(struct ip6_reassdata),   "IP6_REASSDATA")
+#endif /* LWIP_IPV6 && LWIP_IPV6_REASS */
+
+#if LWIP_IPV6 && LWIP_IPV6_MLD
+LWIP_MEMPOOL(MLD6_GROUP,     MEMP_NUM_MLD6_GROUP,      sizeof(struct mld_group),     "MLD6_GROUP")
+#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */
+
+
+/*
+ * A list of pools of pbuf's used by LWIP.
+ *
+ * LWIP_PBUF_MEMPOOL(pool_name, number_elements, pbuf_payload_size, pool_description)
+ *     creates a pool name MEMP_pool_name. description is used in stats.c
+ *     This allocates enough space for the pbuf struct and a payload.
+ *     (Example: pbuf_payload_size=0 allocates only size for the struct)
+ */
+LWIP_PBUF_MEMPOOL(PBUF,      MEMP_NUM_PBUF,            0,                             "PBUF_REF/ROM")
+LWIP_PBUF_MEMPOOL(PBUF_POOL, PBUF_POOL_SIZE,           PBUF_POOL_BUFSIZE,             "PBUF_POOL")
+
+
+/*
+ * Allow for user-defined pools; this must be explicitly set in lwipopts.h
+ * since the default is to NOT look for lwippools.h
+ */
+#if MEMP_USE_CUSTOM_POOLS
+#include "lwippools.h"
+#endif /* MEMP_USE_CUSTOM_POOLS */
+
+/*
+ * REQUIRED CLEANUP: Clear up so we don't get "multiply defined" error later
+ * (#undef is ignored for something that is not defined)
+ */
+#undef LWIP_MEMPOOL
+#undef LWIP_MALLOC_MEMPOOL
+#undef LWIP_MALLOC_MEMPOOL_START
+#undef LWIP_MALLOC_MEMPOOL_END
+#undef LWIP_PBUF_MEMPOOL
diff --git a/tools/sdk/include/lwip/lwip/priv/tcp_priv.h b/tools/sdk/include/lwip/lwip/priv/tcp_priv.h
new file mode 100755
index 00000000..b5261b44
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/priv/tcp_priv.h
@@ -0,0 +1,545 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef LWIP_HDR_TCP_IMPL_H
+#define LWIP_HDR_TCP_IMPL_H
+
+#include "lwip/opt.h"
+
+#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/tcp.h"
+#include "lwip/mem.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip.h"
+#include "lwip/icmp.h"
+#include "lwip/err.h"
+#include "lwip/ip6.h"
+#include "lwip/ip6_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Functions for interfacing with TCP: */
+
+/* Lower layer interface to TCP: */
+void             tcp_init    (void);  /* Initialize this module. */
+void             tcp_tmr     (void);  /* Must be called every
+                                         TCP_TMR_INTERVAL
+                                         ms. (Typically 250 ms). */
+/* It is also possible to call these two functions at the right
+   intervals (instead of calling tcp_tmr()). */
+void             tcp_slowtmr (void);
+void             tcp_fasttmr (void);
+
+/* Call this from a netif driver (watch out for threading issues!) that has
+   returned a memory error on transmit and now has free buffers to send more.
+   This iterates all active pcbs that had an error and tries to call
+   tcp_output, so use this with care as it might slow down the system. */
+void             tcp_txnow   (void);
+
+/* Only used by IP to pass a TCP segment to TCP: */
+void             tcp_input   (struct pbuf *p, struct netif *inp);
+/* Used within the TCP code only: */
+struct tcp_pcb * tcp_alloc   (u8_t prio);
+void             tcp_abandon (struct tcp_pcb *pcb, int reset);
+err_t            tcp_send_empty_ack(struct tcp_pcb *pcb);
+void             tcp_rexmit  (struct tcp_pcb *pcb);
+void             tcp_rexmit_rto  (struct tcp_pcb *pcb);
+void             tcp_rexmit_fast (struct tcp_pcb *pcb);
+u32_t            tcp_update_rcv_ann_wnd(struct tcp_pcb *pcb);
+err_t            tcp_process_refused_data(struct tcp_pcb *pcb);
+
+/**
+ * This is the Nagle algorithm: try to combine user data to send as few TCP
+ * segments as possible. Only send if
+ * - no previously transmitted data on the connection remains unacknowledged or
+ * - the TF_NODELAY flag is set (nagle algorithm turned off for this pcb) or
+ * - the only unsent segment is at least pcb->mss bytes long (or there is more
+ *   than one unsent segment - with lwIP, this can happen although unsent->len < mss)
+ * - or if we are in fast-retransmit (TF_INFR)
+ */
+#define tcp_do_output_nagle(tpcb) ((((tpcb)->unacked == NULL) || \
+                            ((tpcb)->flags & (TF_NODELAY | TF_INFR)) || \
+                            (((tpcb)->unsent != NULL) && (((tpcb)->unsent->next != NULL) || \
+                              ((tpcb)->unsent->len >= (tpcb)->mss))) || \
+                            ((tcp_sndbuf(tpcb) == 0) || (tcp_sndqueuelen(tpcb) >= TCP_SND_QUEUELEN)) \
+                            ) ? 1 : 0)
+#define tcp_output_nagle(tpcb) (tcp_do_output_nagle(tpcb) ? tcp_output(tpcb) : ERR_OK)
+
+
+#define TCP_SEQ_LT(a,b)     ((s32_t)((u32_t)(a) - (u32_t)(b)) < 0)
+#define TCP_SEQ_LEQ(a,b)    ((s32_t)((u32_t)(a) - (u32_t)(b)) <= 0)
+#define TCP_SEQ_GT(a,b)     ((s32_t)((u32_t)(a) - (u32_t)(b)) > 0)
+#define TCP_SEQ_GEQ(a,b)    ((s32_t)((u32_t)(a) - (u32_t)(b)) >= 0)
+/* is b<=a<=c? */
+#if 0 /* see bug #10548 */
+#define TCP_SEQ_BETWEEN(a,b,c) ((c)-(b) >= (a)-(b))
+#endif
+#define TCP_SEQ_BETWEEN(a,b,c) (TCP_SEQ_GEQ(a,b) && TCP_SEQ_LEQ(a,c))
+#define TCP_FIN 0x01U
+#define TCP_SYN 0x02U
+#define TCP_RST 0x04U
+#define TCP_PSH 0x08U
+#define TCP_ACK 0x10U
+#define TCP_URG 0x20U
+#define TCP_ECE 0x40U
+#define TCP_CWR 0x80U
+
+#define TCP_FLAGS 0x3fU
+
+/* Length of the TCP header, excluding options. */
+#define TCP_HLEN 20
+
+#ifndef TCP_TMR_INTERVAL
+#define TCP_TMR_INTERVAL       250  /* The TCP timer interval in milliseconds. */
+#endif /* TCP_TMR_INTERVAL */
+
+#ifndef TCP_FAST_INTERVAL
+#define TCP_FAST_INTERVAL      TCP_TMR_INTERVAL /* the fine grained timeout in milliseconds */
+#endif /* TCP_FAST_INTERVAL */
+
+#ifndef TCP_SLOW_INTERVAL
+#define TCP_SLOW_INTERVAL      (2*TCP_TMR_INTERVAL)  /* the coarse grained timeout in milliseconds */
+#endif /* TCP_SLOW_INTERVAL */
+
+#define TCP_FIN_WAIT_TIMEOUT 20000 /* milliseconds */
+#define TCP_SYN_RCVD_TIMEOUT 20000 /* milliseconds */
+
+#define TCP_OOSEQ_TIMEOUT        6U /* x RTO */
+
+#ifndef TCP_MSL
+#define TCP_MSL 60000UL /* The maximum segment lifetime in milliseconds */
+#endif
+
+/* Keepalive values, compliant with RFC 1122. Don't change this unless you know what you're doing */
+#ifndef  TCP_KEEPIDLE_DEFAULT
+#define  TCP_KEEPIDLE_DEFAULT     7200000UL /* Default KEEPALIVE timer in milliseconds */
+#endif
+
+#ifndef  TCP_KEEPINTVL_DEFAULT
+#define  TCP_KEEPINTVL_DEFAULT    75000UL   /* Default Time between KEEPALIVE probes in milliseconds */
+#endif
+
+#ifndef  TCP_KEEPCNT_DEFAULT
+#define  TCP_KEEPCNT_DEFAULT      9U        /* Default Counter for KEEPALIVE probes */
+#endif
+
+#define  TCP_MAXIDLE              TCP_KEEPCNT_DEFAULT * TCP_KEEPINTVL_DEFAULT  /* Maximum KEEPALIVE probe time */
+
+/* Fields are (of course) in network byte order.
+ * Some fields are converted to host byte order in tcp_input().
+ */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct tcp_hdr {
+  PACK_STRUCT_FIELD(u16_t src);
+  PACK_STRUCT_FIELD(u16_t dest);
+  PACK_STRUCT_FIELD(u32_t seqno);
+  PACK_STRUCT_FIELD(u32_t ackno);
+  PACK_STRUCT_FIELD(u16_t _hdrlen_rsvd_flags);
+  PACK_STRUCT_FIELD(u16_t wnd);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FIELD(u16_t urgp);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define TCPH_HDRLEN(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) >> 12)
+#define TCPH_FLAGS(phdr)  (ntohs((phdr)->_hdrlen_rsvd_flags) & TCP_FLAGS)
+
+#define TCPH_HDRLEN_SET(phdr, len) (phdr)->_hdrlen_rsvd_flags = htons(((len) << 12) | TCPH_FLAGS(phdr))
+#define TCPH_FLAGS_SET(phdr, flags) (phdr)->_hdrlen_rsvd_flags = (((phdr)->_hdrlen_rsvd_flags & PP_HTONS(~TCP_FLAGS)) | htons(flags))
+#define TCPH_HDRLEN_FLAGS_SET(phdr, len, flags) (phdr)->_hdrlen_rsvd_flags = htons(((len) << 12) | (flags))
+
+#define TCPH_SET_FLAG(phdr, flags ) (phdr)->_hdrlen_rsvd_flags = ((phdr)->_hdrlen_rsvd_flags | htons(flags))
+#define TCPH_UNSET_FLAG(phdr, flags) (phdr)->_hdrlen_rsvd_flags = ((phdr)->_hdrlen_rsvd_flags & ~htons(flags))
+
+#define TCP_TCPLEN(seg) ((seg)->len + (((TCPH_FLAGS((seg)->tcphdr) & (TCP_FIN | TCP_SYN)) != 0) ? 1U : 0U))
+
+/** Flags used on input processing, not on pcb->flags
+*/
+#define TF_RESET     (u8_t)0x08U   /* Connection was reset. */
+#define TF_CLOSED    (u8_t)0x10U   /* Connection was successfully closed. */
+#define TF_GOT_FIN   (u8_t)0x20U   /* Connection was closed by the remote end. */
+
+
+#if LWIP_EVENT_API
+
+#define TCP_EVENT_ACCEPT(pcb,err,ret)    ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                LWIP_EVENT_ACCEPT, NULL, 0, err)
+#define TCP_EVENT_SENT(pcb,space,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                   LWIP_EVENT_SENT, NULL, space, ERR_OK)
+#define TCP_EVENT_RECV(pcb,p,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                LWIP_EVENT_RECV, (p), 0, (err))
+#define TCP_EVENT_CLOSED(pcb,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                LWIP_EVENT_RECV, NULL, 0, ERR_OK)
+#define TCP_EVENT_CONNECTED(pcb,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                LWIP_EVENT_CONNECTED, NULL, 0, (err))
+#define TCP_EVENT_POLL(pcb,ret)       ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                LWIP_EVENT_POLL, NULL, 0, ERR_OK)
+#define TCP_EVENT_ERR(errf,arg,err)  lwip_tcp_event((arg), NULL, \
+                LWIP_EVENT_ERR, NULL, 0, (err))
+
+#else /* LWIP_EVENT_API */
+
+#define TCP_EVENT_ACCEPT(pcb,err,ret)                          \
+  do {                                                         \
+    if((pcb)->accept != NULL)                                  \
+      (ret) = (pcb)->accept((pcb)->callback_arg,(pcb),(err));  \
+    else (ret) = ERR_ARG;                                      \
+  } while (0)
+
+#define TCP_EVENT_SENT(pcb,space,ret)                          \
+  do {                                                         \
+    if((pcb)->sent != NULL)                                    \
+      (ret) = (pcb)->sent((pcb)->callback_arg,(pcb),(space));  \
+    else (ret) = ERR_OK;                                       \
+  } while (0)
+
+#define TCP_EVENT_RECV(pcb,p,err,ret)                          \
+  do {                                                         \
+    if((pcb)->recv != NULL) {                                  \
+      (ret) = (pcb)->recv((pcb)->callback_arg,(pcb),(p),(err));\
+    } else {                                                   \
+      (ret) = tcp_recv_null(NULL, (pcb), (p), (err));          \
+    }                                                          \
+  } while (0)
+
+#define TCP_EVENT_CLOSED(pcb,ret)                                \
+  do {                                                           \
+    if(((pcb)->recv != NULL)) {                                  \
+      (ret) = (pcb)->recv((pcb)->callback_arg,(pcb),NULL,ERR_OK);\
+    } else {                                                     \
+      (ret) = ERR_OK;                                            \
+    }                                                            \
+  } while (0)
+
+#define TCP_EVENT_CONNECTED(pcb,err,ret)                         \
+  do {                                                           \
+    if((pcb)->connected != NULL)                                 \
+      (ret) = (pcb)->connected((pcb)->callback_arg,(pcb),(err)); \
+    else (ret) = ERR_OK;                                         \
+  } while (0)
+
+#define TCP_EVENT_POLL(pcb,ret)                                \
+  do {                                                         \
+    if((pcb)->poll != NULL)                                    \
+      (ret) = (pcb)->poll((pcb)->callback_arg,(pcb));          \
+    else (ret) = ERR_OK;                                       \
+  } while (0)
+
+#define TCP_EVENT_ERR(errf,arg,err)                            \
+  do {                                                         \
+    if((errf) != NULL)                                         \
+      (errf)((arg),(err));                                     \
+  } while (0)
+
+#endif /* LWIP_EVENT_API */
+
+/** Enabled extra-check for TCP_OVERSIZE if LWIP_DEBUG is enabled */
+#if TCP_OVERSIZE && defined(LWIP_DEBUG)
+#define TCP_OVERSIZE_DBGCHECK 1
+#else
+#define TCP_OVERSIZE_DBGCHECK 0
+#endif
+
+/** Don't generate checksum on copy if CHECKSUM_GEN_TCP is disabled */
+#define TCP_CHECKSUM_ON_COPY  (LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_TCP)
+
+/* This structure represents a TCP segment on the unsent, unacked and ooseq queues */
+struct tcp_seg {
+  struct tcp_seg *next;    /* used when putting segments on a queue */
+  struct pbuf *p;          /* buffer containing data + TCP header */
+  u16_t len;               /* the TCP length of this segment */
+#if TCP_OVERSIZE_DBGCHECK
+  u16_t oversize_left;     /* Extra bytes available at the end of the last
+                              pbuf in unsent (used for asserting vs.
+                              tcp_pcb.unsent_oversized only) */
+#endif /* TCP_OVERSIZE_DBGCHECK */
+#if TCP_CHECKSUM_ON_COPY
+  u16_t chksum;
+  u8_t  chksum_swapped;
+#endif /* TCP_CHECKSUM_ON_COPY */
+  u8_t  flags;
+#define TF_SEG_OPTS_MSS         (u8_t)0x01U /* Include MSS option. */
+#define TF_SEG_OPTS_TS          (u8_t)0x02U /* Include timestamp option. */
+#define TF_SEG_DATA_CHECKSUMMED (u8_t)0x04U /* ALL data (not the header) is
+                                               checksummed into 'chksum' */
+#define TF_SEG_OPTS_WND_SCALE   (u8_t)0x08U /* Include WND SCALE option */
+  struct tcp_hdr *tcphdr;  /* the TCP header */
+};
+
+#define LWIP_TCP_OPT_EOL        0
+#define LWIP_TCP_OPT_NOP        1
+#define LWIP_TCP_OPT_MSS        2
+#define LWIP_TCP_OPT_WS         3
+#define LWIP_TCP_OPT_TS         8
+
+#define LWIP_TCP_OPT_LEN_MSS    4
+#if LWIP_TCP_TIMESTAMPS
+#define LWIP_TCP_OPT_LEN_TS     10
+#define LWIP_TCP_OPT_LEN_TS_OUT 12 /* aligned for output (includes NOP padding) */
+#else
+#define LWIP_TCP_OPT_LEN_TS_OUT 0
+#endif
+#if LWIP_WND_SCALE
+#define LWIP_TCP_OPT_LEN_WS     3
+#define LWIP_TCP_OPT_LEN_WS_OUT 4 /* aligned for output (includes NOP padding) */
+#else
+#define LWIP_TCP_OPT_LEN_WS_OUT 0
+#endif
+
+#define LWIP_TCP_OPT_LENGTH(flags) \
+  (flags & TF_SEG_OPTS_MSS       ? LWIP_TCP_OPT_LEN_MSS    : 0) + \
+  (flags & TF_SEG_OPTS_TS        ? LWIP_TCP_OPT_LEN_TS_OUT : 0) + \
+  (flags & TF_SEG_OPTS_WND_SCALE ? LWIP_TCP_OPT_LEN_WS_OUT : 0)
+
+/** This returns a TCP header option for MSS in an u32_t */
+#define TCP_BUILD_MSS_OPTION(mss) htonl(0x02040000 | ((mss) & 0xFFFF))
+
+#if LWIP_WND_SCALE
+#define TCPWNDSIZE_F       U32_F
+#define TCPWND_MAX         0xFFFFFFFFU
+#define TCPWND_CHECK16(x)  LWIP_ASSERT("window size > 0xFFFF", (x) <= 0xFFFF)
+#define TCPWND_MIN16(x)    ((u16_t)LWIP_MIN((x), 0xFFFF))
+#else /* LWIP_WND_SCALE */
+#define TCPWNDSIZE_F       U16_F
+#define TCPWND_MAX         0xFFFFU
+#define TCPWND_CHECK16(x)
+#define TCPWND_MIN16(x)    x
+#endif /* LWIP_WND_SCALE */
+
+/* Global variables: */
+extern struct tcp_pcb *tcp_input_pcb;
+extern u32_t tcp_ticks;
+extern u8_t tcp_active_pcbs_changed;
+
+/* The TCP PCB lists. */
+union tcp_listen_pcbs_t { /* List of all TCP PCBs in LISTEN state. */
+  struct tcp_pcb_listen *listen_pcbs;
+  struct tcp_pcb *pcbs;
+};
+extern struct tcp_pcb *tcp_bound_pcbs;
+extern union tcp_listen_pcbs_t tcp_listen_pcbs;
+extern struct tcp_pcb *tcp_active_pcbs;  /* List of all TCP PCBs that are in a
+              state in which they accept or send
+              data. */
+extern struct tcp_pcb *tcp_tw_pcbs;      /* List of all TCP PCBs in TIME-WAIT. */
+
+#define NUM_TCP_PCB_LISTS_NO_TIME_WAIT  3
+#define NUM_TCP_PCB_LISTS               4
+extern struct tcp_pcb ** const tcp_pcb_lists[NUM_TCP_PCB_LISTS];
+
+/* Axioms about the above lists:
+   1) Every TCP PCB that is not CLOSED is in one of the lists.
+   2) A PCB is only in one of the lists.
+   3) All PCBs in the tcp_listen_pcbs list is in LISTEN state.
+   4) All PCBs in the tcp_tw_pcbs list is in TIME-WAIT state.
+*/
+/* Define two macros, TCP_REG and TCP_RMV that registers a TCP PCB
+   with a PCB list or removes a PCB from a list, respectively. */
+#ifndef TCP_DEBUG_PCB_LISTS
+#define TCP_DEBUG_PCB_LISTS 0
+#endif
+#if TCP_DEBUG_PCB_LISTS
+#define TCP_REG(pcbs, npcb) do {\
+                            struct tcp_pcb *tcp_tmp_pcb; \
+                            LWIP_DEBUGF(TCP_DEBUG, ("TCP_REG %p local port %d\n", (npcb), (npcb)->local_port)); \
+                            for (tcp_tmp_pcb = *(pcbs); \
+          tcp_tmp_pcb != NULL; \
+        tcp_tmp_pcb = tcp_tmp_pcb->next) { \
+                                LWIP_ASSERT("TCP_REG: already registered\n", tcp_tmp_pcb != (npcb)); \
+                            } \
+                            LWIP_ASSERT("TCP_REG: pcb->state != CLOSED", ((pcbs) == &tcp_bound_pcbs) || ((npcb)->state != CLOSED)); \
+                            (npcb)->next = *(pcbs); \
+                            LWIP_ASSERT("TCP_REG: npcb->next != npcb", (npcb)->next != (npcb)); \
+                            *(pcbs) = (npcb); \
+                            LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \
+              tcp_timer_needed(); \
+                            } while(0)
+#define TCP_RMV(pcbs, npcb) do { \
+                            struct tcp_pcb *tcp_tmp_pcb; \
+                            LWIP_ASSERT("TCP_RMV: pcbs != NULL", *(pcbs) != NULL); \
+                            LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removing %p from %p\n", (npcb), *(pcbs))); \
+                            if(*(pcbs) == (npcb)) { \
+                               *(pcbs) = (*pcbs)->next; \
+                            } else for (tcp_tmp_pcb = *(pcbs); tcp_tmp_pcb != NULL; tcp_tmp_pcb = tcp_tmp_pcb->next) { \
+                               if(tcp_tmp_pcb->next == (npcb)) { \
+                                  tcp_tmp_pcb->next = (npcb)->next; \
+                                  break; \
+                               } \
+                            } \
+                            (npcb)->next = NULL; \
+                            LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \
+                            LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removed %p from %p\n", (npcb), *(pcbs))); \
+                            } while(0)
+
+#else /* LWIP_DEBUG */
+
+#define TCP_REG(pcbs, npcb)                        \
+  do {                                             \
+    (npcb)->next = *pcbs;                          \
+    *(pcbs) = (npcb);                              \
+    tcp_timer_needed();                            \
+  } while (0)
+
+#define TCP_RMV(pcbs, npcb)                        \
+  do {                                             \
+    if(*(pcbs) == (npcb)) {                        \
+      (*(pcbs)) = (*pcbs)->next;                   \
+    }                                              \
+    else {                                         \
+      struct tcp_pcb *tcp_tmp_pcb;                 \
+      for (tcp_tmp_pcb = *pcbs;                    \
+          tcp_tmp_pcb != NULL;                     \
+          tcp_tmp_pcb = tcp_tmp_pcb->next) {       \
+        if(tcp_tmp_pcb->next == (npcb)) {          \
+          tcp_tmp_pcb->next = (npcb)->next;        \
+          break;                                   \
+        }                                          \
+      }                                            \
+    }                                              \
+    (npcb)->next = NULL;                           \
+  } while(0)
+
+#endif /* LWIP_DEBUG */
+
+#define TCP_REG_ACTIVE(npcb)                       \
+  do {                                             \
+    TCP_REG(&tcp_active_pcbs, npcb);               \
+    tcp_active_pcbs_changed = 1;                   \
+  } while (0)
+
+#define TCP_RMV_ACTIVE(npcb)                       \
+  do {                                             \
+    TCP_RMV(&tcp_active_pcbs, npcb);               \
+    tcp_active_pcbs_changed = 1;                   \
+  } while (0)
+
+#define TCP_PCB_REMOVE_ACTIVE(pcb)                 \
+  do {                                             \
+    tcp_pcb_remove(&tcp_active_pcbs, pcb);         \
+    tcp_active_pcbs_changed = 1;                   \
+  } while (0)
+
+
+/* Internal functions: */
+struct tcp_pcb *tcp_pcb_copy(struct tcp_pcb *pcb);
+void tcp_pcb_purge(struct tcp_pcb *pcb);
+void tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb);
+
+void tcp_segs_free(struct tcp_seg *seg);
+void tcp_seg_free(struct tcp_seg *seg);
+struct tcp_seg *tcp_seg_copy(struct tcp_seg *seg);
+
+#define tcp_ack(pcb)                               \
+  do {                                             \
+    if((pcb)->flags & TF_ACK_DELAY) {              \
+      (pcb)->flags &= ~TF_ACK_DELAY;               \
+      (pcb)->flags |= TF_ACK_NOW;                  \
+    }                                              \
+    else {                                         \
+      (pcb)->flags |= TF_ACK_DELAY;                \
+    }                                              \
+  } while (0)
+
+#define tcp_ack_now(pcb)                           \
+  do {                                             \
+    (pcb)->flags |= TF_ACK_NOW;                    \
+  } while (0)
+
+err_t tcp_send_fin(struct tcp_pcb *pcb);
+err_t tcp_enqueue_flags(struct tcp_pcb *pcb, u8_t flags);
+
+void tcp_rexmit_seg(struct tcp_pcb *pcb, struct tcp_seg *seg);
+
+void tcp_rst(u32_t seqno, u32_t ackno,
+       const ip_addr_t *local_ip, const ip_addr_t *remote_ip,
+       u16_t local_port, u16_t remote_port);
+
+u32_t tcp_next_iss(void);
+
+err_t tcp_keepalive(struct tcp_pcb *pcb);
+err_t tcp_zero_window_probe(struct tcp_pcb *pcb);
+void  tcp_trigger_input_pcb_close(void);
+
+#if TCP_CALCULATE_EFF_SEND_MSS
+u16_t tcp_eff_send_mss_impl(u16_t sendmss, const ip_addr_t *dest
+#if LWIP_IPV6 || LWIP_IPV4_SRC_ROUTING
+                           , const ip_addr_t *src
+#endif /* LWIP_IPV6 || LWIP_IPV4_SRC_ROUTING */
+                           );
+#if LWIP_IPV6 || LWIP_IPV4_SRC_ROUTING
+#define tcp_eff_send_mss(sendmss, src, dest) tcp_eff_send_mss_impl(sendmss, dest, src)
+#else /* LWIP_IPV6 || LWIP_IPV4_SRC_ROUTING */
+#define tcp_eff_send_mss(sendmss, src, dest) tcp_eff_send_mss_impl(sendmss, dest)
+#endif /* LWIP_IPV6 || LWIP_IPV4_SRC_ROUTING */
+#endif /* TCP_CALCULATE_EFF_SEND_MSS */
+
+#if LWIP_CALLBACK_API
+err_t tcp_recv_null(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err);
+#endif /* LWIP_CALLBACK_API */
+
+#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG
+void tcp_debug_print(struct tcp_hdr *tcphdr);
+void tcp_debug_print_flags(u8_t flags);
+void tcp_debug_print_state(enum tcp_state s);
+void tcp_debug_print_pcbs(void);
+s16_t tcp_pcbs_sane(void);
+#else
+#  define tcp_debug_print(tcphdr)
+#  define tcp_debug_print_flags(flags)
+#  define tcp_debug_print_state(s)
+#  define tcp_debug_print_pcbs()
+#  define tcp_pcbs_sane() 1
+#endif /* TCP_DEBUG */
+
+/** External function (implemented in timers.c), called when TCP detects
+ * that a timer is needed (i.e. active- or time-wait-pcb found). */
+void tcp_timer_needed(void);
+
+#if LWIP_IPV4
+void tcp_netif_ipv4_addr_changed(const ip4_addr_t* old_addr, const ip4_addr_t* new_addr);
+#endif /* LWIP_IPV4 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_TCP */
+
+#endif /* LWIP_HDR_TCP_H */
diff --git a/tools/sdk/include/lwip/lwip/priv/tcpip_priv.h b/tools/sdk/include/lwip/lwip/priv/tcpip_priv.h
new file mode 100755
index 00000000..cc1c54eb
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/priv/tcpip_priv.h
@@ -0,0 +1,163 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef LWIP_HDR_TCPIP_PRIV_H
+#define LWIP_HDR_TCPIP_PRIV_H
+
+#include "lwip/opt.h"
+
+#if !NO_SYS /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/tcpip.h"
+#include "lwip/sys.h"
+#include "lwip/timers.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  
+struct pbuf;
+struct netif;
+
+/** Define this to something that triggers a watchdog. This is called from
+ * tcpip_thread after processing a message. */
+#ifndef LWIP_TCPIP_THREAD_ALIVE
+#define LWIP_TCPIP_THREAD_ALIVE()
+#endif
+
+#if LWIP_TCPIP_CORE_LOCKING
+/** The global semaphore to lock the stack. */
+extern sys_mutex_t lock_tcpip_core;
+#define LOCK_TCPIP_CORE()     sys_mutex_lock(&lock_tcpip_core)
+#define UNLOCK_TCPIP_CORE()   sys_mutex_unlock(&lock_tcpip_core)
+#else /* LWIP_TCPIP_CORE_LOCKING */
+#define LOCK_TCPIP_CORE()
+#define UNLOCK_TCPIP_CORE()
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+
+#if LWIP_MPU_COMPATIBLE
+#define API_VAR_REF(name)               (*(name))
+#define API_VAR_DECLARE(type, name)     type * name
+#define API_VAR_ALLOC(type, pool, name) do { \
+                                          name = (type *)memp_malloc(pool); \
+                                          if (name == NULL) { \
+                                            return ERR_MEM; \
+                                          } \
+                                        } while(0)
+#define API_VAR_ALLOC_DONTFAIL(type, pool, name) do { \
+                                          name = (type *)memp_malloc(pool); \
+                                          LWIP_ASSERT("pool empty", name != NULL); \
+                                        } while(0)
+#define API_VAR_FREE(pool, name)        memp_free(pool, name)
+#define API_EXPR_REF(expr)              &(expr)
+#if LWIP_NETCONN_SEM_PER_THREAD
+#define API_EXPR_REF_SEM(expr)          (expr)
+#else
+#define API_EXPR_REF_SEM(expr)          API_EXPR_REF(expr)
+#endif
+#define API_EXPR_DEREF(expr)            expr
+#else /* LWIP_MPU_COMPATIBLE */
+#define API_VAR_REF(name)               name
+#define API_VAR_DECLARE(type, name)     type name
+#define API_VAR_ALLOC(type, pool, name)
+#define API_VAR_ALLOC_DONTFAIL(type, pool, name)
+#define API_VAR_FREE(pool, name)
+#define API_EXPR_REF(expr)              expr
+#define API_EXPR_REF_SEM(expr)          API_EXPR_REF(expr)
+#define API_EXPR_DEREF(expr)            *(expr)
+#endif /* LWIP_MPU_COMPATIBLE */
+
+#if !LWIP_TCPIP_CORE_LOCKING
+err_t tcpip_send_api_msg(tcpip_callback_fn fn, void *apimsg, sys_sem_t* sem);
+#endif /* !LWIP_TCPIP_CORE_LOCKING */
+
+struct tcpip_api_call;
+typedef err_t (*tcpip_api_call_fn)(struct tcpip_api_call* call);
+struct tcpip_api_call
+{
+  tcpip_api_call_fn function;
+#if !LWIP_TCPIP_CORE_LOCKING
+#if LWIP_NETCONN_SEM_PER_THREAD
+  sys_sem_t *sem;
+#else /* LWIP_NETCONN_SEM_PER_THREAD */
+  sys_sem_t sem;
+#endif /* LWIP_NETCONN_SEM_PER_THREAD */
+  err_t err;
+#endif /* !LWIP_TCPIP_CORE_LOCKING */
+};
+err_t tcpip_api_call(tcpip_api_call_fn fn, struct tcpip_api_call *call);
+
+enum tcpip_msg_type {
+  TCPIP_MSG_API,
+  TCPIP_MSG_API_CALL,
+  TCPIP_MSG_INPKT,
+#if LWIP_TCPIP_TIMEOUT
+  TCPIP_MSG_TIMEOUT,
+  TCPIP_MSG_UNTIMEOUT,
+#endif /* LWIP_TCPIP_TIMEOUT */
+  TCPIP_MSG_CALLBACK,
+  TCPIP_MSG_CALLBACK_STATIC
+};
+
+struct tcpip_msg {
+  enum tcpip_msg_type type;
+  union {
+    struct {
+      tcpip_callback_fn function;
+      void* msg;
+    } api;
+    struct tcpip_api_call *api_call;
+    struct {
+      struct pbuf *p;
+      struct netif *netif;
+      netif_input_fn input_fn;
+    } inp;
+    struct {
+      tcpip_callback_fn function;
+      void *ctx;
+    } cb;
+#if LWIP_TCPIP_TIMEOUT
+    struct {
+      u32_t msecs;
+      sys_timeout_handler h;
+      void *arg;
+    } tmo;
+#endif /* LWIP_TCPIP_TIMEOUT */
+  } msg;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !NO_SYS */
+
+#endif /* LWIP_HDR_TCPIP_PRIV_H */
diff --git a/tools/sdk/include/lwip/lwip/raw.h b/tools/sdk/include/lwip/lwip/raw.h
new file mode 100755
index 00000000..474fdc15
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/raw.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef LWIP_HDR_RAW_H
+#define LWIP_HDR_RAW_H
+
+#include "lwip/opt.h"
+
+#if LWIP_RAW /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/pbuf.h"
+#include "lwip/def.h"
+#include "lwip/ip.h"
+#include "lwip/ip_addr.h"
+#include "lwip/ip6_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct raw_pcb;
+
+/** Function prototype for raw pcb receive callback functions.
+ * @param arg user supplied argument (raw_pcb.recv_arg)
+ * @param pcb the raw_pcb which received data
+ * @param p the packet buffer that was received
+ * @param addr the remote IP address from which the packet was received
+ * @return 1 if the packet was 'eaten' (aka. deleted),
+ *         0 if the packet lives on
+ * If returning 1, the callback is responsible for freeing the pbuf
+ * if it's not used any more.
+ */
+typedef u8_t (*raw_recv_fn)(void *arg, struct raw_pcb *pcb, struct pbuf *p,
+    const ip_addr_t *addr);
+
+struct raw_pcb {
+  /* Common members of all PCB types */
+  IP_PCB;
+
+  struct raw_pcb *next;
+
+  u8_t protocol;
+
+  /** receive callback function */
+  raw_recv_fn recv;
+  /* user-supplied argument for the recv callback */
+  void *recv_arg;
+#if LWIP_IPV6
+  /* fields for handling checksum computations as per RFC3542. */
+  u16_t chksum_offset;
+  u8_t  chksum_reqd;
+#endif
+};
+
+/* The following functions is the application layer interface to the
+   RAW code. */
+struct raw_pcb * raw_new        (u8_t proto);
+struct raw_pcb * raw_new_ip_type(u8_t type, u8_t proto);
+void             raw_remove     (struct raw_pcb *pcb);
+err_t            raw_bind       (struct raw_pcb *pcb, const ip_addr_t *ipaddr);
+err_t            raw_connect    (struct raw_pcb *pcb, const ip_addr_t *ipaddr);
+
+err_t            raw_sendto     (struct raw_pcb *pcb, struct pbuf *p, const ip_addr_t *ipaddr);
+err_t            raw_send       (struct raw_pcb *pcb, struct pbuf *p);
+
+void             raw_recv       (struct raw_pcb *pcb, raw_recv_fn recv, void *recv_arg);
+
+/* The following functions are the lower layer interface to RAW. */
+u8_t             raw_input      (struct pbuf *p, struct netif *inp);
+#define raw_init() /* Compatibility define, no init needed. */
+
+/* for compatibility with older implementation */
+#define raw_new_ip6(proto) raw_new_ip_type(IPADDR_TYPE_V6, proto)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_RAW */
+
+#endif /* LWIP_HDR_RAW_H */
diff --git a/tools/sdk/include/lwip/lwip/sio.h b/tools/sdk/include/lwip/lwip/sio.h
new file mode 100755
index 00000000..09cf799a
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/sio.h
@@ -0,0 +1,141 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ */
+
+/*
+ * This is the interface to the platform specific serial IO module
+ * It needs to be implemented by those platforms which need SLIP or PPP
+ */
+
+#ifndef SIO_H
+#define SIO_H
+
+#include "lwip/arch.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* If you want to define sio_fd_t elsewhere or differently,
+   define this in your cc.h file. */
+#ifndef __sio_fd_t_defined
+typedef void * sio_fd_t;
+#endif
+
+/* The following functions can be defined to something else in your cc.h file
+   or be implemented in your custom sio.c file. */
+
+#ifndef sio_open
+/**
+ * Opens a serial device for communication.
+ *
+ * @param devnum device number
+ * @return handle to serial device if successful, NULL otherwise
+ */
+sio_fd_t sio_open(u8_t devnum);
+#endif
+
+#ifndef sio_send
+/**
+ * Sends a single character to the serial device.
+ *
+ * @param c character to send
+ * @param fd serial device handle
+ *
+ * @note This function will block until the character can be sent.
+ */
+void sio_send(u8_t c, sio_fd_t fd);
+#endif
+
+#ifndef sio_recv
+/**
+ * Receives a single character from the serial device.
+ *
+ * @param fd serial device handle
+ *
+ * @note This function will block until a character is received.
+ */
+u8_t sio_recv(sio_fd_t fd);
+#endif
+
+#ifndef sio_read
+/**
+ * Reads from the serial device.
+ *
+ * @param fd serial device handle
+ * @param data pointer to data buffer for receiving
+ * @param len maximum length (in bytes) of data to receive
+ * @return number of bytes actually received - may be 0 if aborted by sio_read_abort
+ *
+ * @note This function will block until data can be received. The blocking
+ * can be cancelled by calling sio_read_abort().
+ */
+u32_t sio_read(sio_fd_t fd, u8_t *data, u32_t len);
+#endif
+
+#ifndef sio_tryread
+/**
+ * Tries to read from the serial device. Same as sio_read but returns
+ * immediately if no data is available and never blocks.
+ *
+ * @param fd serial device handle
+ * @param data pointer to data buffer for receiving
+ * @param len maximum length (in bytes) of data to receive
+ * @return number of bytes actually received
+ */
+u32_t sio_tryread(sio_fd_t fd, u8_t *data, u32_t len);
+#endif
+
+#ifndef sio_write
+/**
+ * Writes to the serial device.
+ *
+ * @param fd serial device handle
+ * @param data pointer to data to send
+ * @param len length (in bytes) of data to send
+ * @return number of bytes actually sent
+ *
+ * @note This function will block until all data can be sent.
+ */
+u32_t sio_write(sio_fd_t fd, u8_t *data, u32_t len);
+#endif
+
+#ifndef sio_read_abort
+/**
+ * Aborts a blocking sio_read() call.
+ *
+ * @param fd serial device handle
+ */
+void sio_read_abort(sio_fd_t fd);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SIO_H */
diff --git a/tools/sdk/include/lwip/lwip/snmp.h b/tools/sdk/include/lwip/lwip/snmp.h
new file mode 100755
index 00000000..07368cc6
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/snmp.h
@@ -0,0 +1,195 @@
+/**
+ * @file
+ * MIB2 callback functions called from throughout the stack to integrate a MIB2
+ * into lwIP (together with MIB2_STATS).
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Dirk Ziegelmeier 
+ *
+ */
+#ifndef LWIP_HDR_SNMP_H
+#define LWIP_HDR_SNMP_H
+
+#include "lwip/opt.h"
+#include "lwip/ip_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct udp_pcb;
+struct netif;
+
+/* MIB2 statistics functions */
+#if MIB2_STATS  /* don't build if not configured for use in lwipopts.h */
+/**
+ * @see RFC1213, "MIB-II, 6. Definitions"
+ */
+enum snmp_ifType {
+  snmp_ifType_other=1,                /* none of the following */
+  snmp_ifType_regular1822,
+  snmp_ifType_hdh1822,
+  snmp_ifType_ddn_x25,
+  snmp_ifType_rfc877_x25,
+  snmp_ifType_ethernet_csmacd,
+  snmp_ifType_iso88023_csmacd,
+  snmp_ifType_iso88024_tokenBus,
+  snmp_ifType_iso88025_tokenRing,
+  snmp_ifType_iso88026_man,
+  snmp_ifType_starLan,
+  snmp_ifType_proteon_10Mbit,
+  snmp_ifType_proteon_80Mbit,
+  snmp_ifType_hyperchannel,
+  snmp_ifType_fddi,
+  snmp_ifType_lapb,
+  snmp_ifType_sdlc,
+  snmp_ifType_ds1,                    /* T-1 */
+  snmp_ifType_e1,                     /* european equiv. of T-1 */
+  snmp_ifType_basicISDN,
+  snmp_ifType_primaryISDN,            /* proprietary serial */
+  snmp_ifType_propPointToPointSerial,
+  snmp_ifType_ppp,
+  snmp_ifType_softwareLoopback,
+  snmp_ifType_eon,                    /* CLNP over IP [11] */
+  snmp_ifType_ethernet_3Mbit,
+  snmp_ifType_nsip,                   /* XNS over IP */
+  snmp_ifType_slip,                   /* generic SLIP */
+  snmp_ifType_ultra,                  /* ULTRA technologies */
+  snmp_ifType_ds3,                    /* T-3 */
+  snmp_ifType_sip,                    /* SMDS */
+  snmp_ifType_frame_relay
+};
+
+/* This macro has a precision of ~49 days because sys_now returns u32_t. #define your own if you want ~490 days. */
+#ifndef MIB2_COPY_SYSUPTIME_TO
+#define MIB2_COPY_SYSUPTIME_TO(ptrToVal) (*(ptrToVal) = (sys_now() / 10))
+#endif
+
+#define MIB2_STATS_NETIF_INC(n, x)      do { ++(n)->mib2_counters.x; } while(0)
+#define MIB2_STATS_NETIF_ADD(n, x, val) do { (n)->mib2_counters.x += (val); } while(0)
+
+#define MIB2_INIT_NETIF(netif, type, speed) do { \
+  /* use "snmp_ifType" enum from snmp_mib2.h for "type", snmp_ifType_ethernet_csmacd by example */ \
+  (netif)->link_type = (type);  \
+  /* your link speed here (units: bits per second) */  \
+  (netif)->link_speed = (speed);\
+  (netif)->ts = 0;              \
+  (netif)->mib2_counters.ifinoctets = 0;      \
+  (netif)->mib2_counters.ifinucastpkts = 0;   \
+  (netif)->mib2_counters.ifinnucastpkts = 0;  \
+  (netif)->mib2_counters.ifindiscards = 0;    \
+  (netif)->mib2_counters.ifinerrors = 0;    \
+  (netif)->mib2_counters.ifinunknownprotos = 0;    \
+  (netif)->mib2_counters.ifoutoctets = 0;     \
+  (netif)->mib2_counters.ifoutucastpkts = 0;  \
+  (netif)->mib2_counters.ifoutnucastpkts = 0; \
+  (netif)->mib2_counters.ifoutdiscards = 0; \
+  (netif)->mib2_counters.ifouterrors = 0; } while(0)
+#else /* MIB2_STATS */
+#ifndef MIB2_COPY_SYSUPTIME_TO
+#define MIB2_COPY_SYSUPTIME_TO(ptrToVal)
+#endif
+#define MIB2_INIT_NETIF(netif, type, speed)
+#define MIB2_STATS_NETIF_INC(n, x)
+#define MIB2_STATS_NETIF_ADD(n, x, val)
+#endif /* MIB2_STATS */
+
+/* LWIP MIB2 callbacks */
+#if LWIP_MIB2_CALLBACKS /* don't build if not configured for use in lwipopts.h */
+/* network interface */
+void mib2_netif_added(struct netif *ni);
+void mib2_netif_removed(struct netif *ni);
+
+#if LWIP_IPV4 && LWIP_ARP
+/* ARP (for atTable and ipNetToMediaTable) */
+void mib2_add_arp_entry(struct netif *ni, ip4_addr_t *ip);
+void mib2_remove_arp_entry(struct netif *ni, ip4_addr_t *ip);
+#else /* LWIP_IPV4 && LWIP_ARP */
+#define mib2_add_arp_entry(ni,ip)
+#define mib2_remove_arp_entry(ni,ip)
+#endif /* LWIP_IPV4 && LWIP_ARP */
+
+/* IP */
+#if LWIP_IPV4
+void mib2_add_ip4(struct netif *ni);
+void mib2_remove_ip4(struct netif *ni);
+void mib2_add_route_ip4(u8_t dflt, struct netif *ni);
+void mib2_remove_route_ip4(u8_t dflt, struct netif *ni);
+#endif /* LWIP_IPV4 */
+
+/* UDP */
+#if LWIP_UDP
+void mib2_udp_bind(struct udp_pcb *pcb);
+void mib2_udp_unbind(struct udp_pcb *pcb);
+#endif /* LWIP_UDP */
+
+#else /* LWIP_MIB2_CALLBACKS */
+/* LWIP_MIB2_CALLBACKS support not available */
+/* define everything to be empty */
+
+/* network interface */
+#define mib2_netif_added(ni)
+#define mib2_netif_removed(ni)
+
+/* ARP */
+#define mib2_add_arp_entry(ni,ip)
+#define mib2_remove_arp_entry(ni,ip)
+
+/* IP */
+#define mib2_add_ip4(ni)
+#define mib2_remove_ip4(ni)
+#define mib2_add_route_ip4(dflt, ni)
+#define mib2_remove_route_ip4(dflt, ni)
+
+/* UDP */
+#define mib2_udp_bind(pcb)
+#define mib2_udp_unbind(pcb)
+#endif /* LWIP_MIB2_CALLBACKS */
+
+/* for source-code compatibility reasons only, can be removed (not used internally) */
+#define NETIF_INIT_SNMP                MIB2_INIT_NETIF
+#define snmp_add_ifinoctets(ni,value)  MIB2_STATS_NETIF_ADD(ni, ifinoctets, value)
+#define snmp_inc_ifinucastpkts(ni)     MIB2_STATS_NETIF_INC(ni, ifinucastpkts)
+#define snmp_inc_ifinnucastpkts(ni)    MIB2_STATS_NETIF_INC(ni, ifinnucastpkts)
+#define snmp_inc_ifindiscards(ni)      MIB2_STATS_NETIF_INC(ni, ifindiscards)
+#define snmp_inc_ifinerrors(ni)        MIB2_STATS_NETIF_INC(ni, ifinerrors)
+#define snmp_inc_ifinunknownprotos(ni) MIB2_STATS_NETIF_INC(ni, ifinunknownprotos)
+#define snmp_add_ifoutoctets(ni,value) MIB2_STATS_NETIF_ADD(ni, ifoutoctets, value)
+#define snmp_inc_ifoutucastpkts(ni)    MIB2_STATS_NETIF_INC(ni, ifoutucastpkts)
+#define snmp_inc_ifoutnucastpkts(ni)   MIB2_STATS_NETIF_INC(ni, ifoutnucastpkts)
+#define snmp_inc_ifoutdiscards(ni)     MIB2_STATS_NETIF_INC(ni, ifoutdiscards)
+#define snmp_inc_ifouterrors(ni)       MIB2_STATS_NETIF_INC(ni, ifouterrors)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_SNMP_H */
diff --git a/tools/sdk/include/lwip/lwip/sockets.h b/tools/sdk/include/lwip/lwip/sockets.h
new file mode 100755
index 00000000..aafb3d5c
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/sockets.h
@@ -0,0 +1,624 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+
+#ifndef LWIP_HDR_SOCKETS_H
+#define LWIP_HDR_SOCKETS_H
+
+#include "lwip/opt.h"
+
+#if LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */
+
+#include  /* for size_t */
+
+#include "lwip/ip_addr.h"
+#include "lwip/err.h"
+#include "lwip/inet.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* If your port already typedef's sa_family_t, define SA_FAMILY_T_DEFINED
+   to prevent this code from redefining it. */
+#if !defined(sa_family_t) && !defined(SA_FAMILY_T_DEFINED)
+typedef u8_t sa_family_t;
+#endif
+/* If your port already typedef's in_port_t, define IN_PORT_T_DEFINED
+   to prevent this code from redefining it. */
+#if !defined(in_port_t) && !defined(IN_PORT_T_DEFINED)
+typedef u16_t in_port_t;
+#endif
+
+#if LWIP_IPV4
+/* members are in network byte order */
+struct sockaddr_in {
+  u8_t            sin_len;
+  sa_family_t     sin_family;
+  in_port_t       sin_port;
+  struct in_addr  sin_addr;
+#define SIN_ZERO_LEN 8
+  char            sin_zero[SIN_ZERO_LEN];
+};
+#endif /* LWIP_IPV4 */
+
+#if LWIP_IPV6
+struct sockaddr_in6 {
+  u8_t            sin6_len;      /* length of this structure    */
+  sa_family_t     sin6_family;   /* AF_INET6                    */
+  in_port_t       sin6_port;     /* Transport layer port #      */
+  u32_t           sin6_flowinfo; /* IPv6 flow information       */
+  struct in6_addr sin6_addr;     /* IPv6 address                */
+  u32_t           sin6_scope_id; /* Set of interfaces for scope */
+};
+#endif /* LWIP_IPV6 */
+
+struct sockaddr {
+  u8_t        sa_len;
+  sa_family_t sa_family;
+  char        sa_data[14];
+};
+
+struct sockaddr_storage {
+  u8_t        s2_len;
+  sa_family_t ss_family;
+  char        s2_data1[2];
+  u32_t       s2_data2[3];
+#if LWIP_IPV6
+  u32_t       s2_data3[3];
+#endif /* LWIP_IPV6 */
+};
+
+/* If your port already typedef's socklen_t, define SOCKLEN_T_DEFINED
+   to prevent this code from redefining it. */
+#if !defined(socklen_t) && !defined(SOCKLEN_T_DEFINED)
+typedef u32_t socklen_t;
+#endif
+
+struct lwip_sock;
+
+#if !LWIP_TCPIP_CORE_LOCKING
+/** Maximum optlen used by setsockopt/getsockopt */
+#define LWIP_SETGETSOCKOPT_MAXOPTLEN 16
+
+/** This struct is used to pass data to the set/getsockopt_internal
+ * functions running in tcpip_thread context (only a void* is allowed) */
+struct lwip_setgetsockopt_data {
+  /** socket index for which to change options */
+  int s;
+  /** level of the option to process */
+  int level;
+  /** name of the option to process */
+  int optname;
+  /** set: value to set the option to
+    * get: value of the option is stored here */
+#if LWIP_MPU_COMPATIBLE
+  u8_t optval[LWIP_SETGETSOCKOPT_MAXOPTLEN];
+#else
+  union {
+     void *p;
+     const void *pc;
+  } optval;
+#endif
+  /** size of *optval */
+  socklen_t optlen;
+  /** if an error occurs, it is temporarily stored here */
+  err_t err;
+  /** semaphore to wake up the calling task */
+  void* completed_sem;
+};
+#endif /* !LWIP_TCPIP_CORE_LOCKING */
+
+#if !defined(iovec)
+struct iovec {
+  void  *iov_base;
+  size_t iov_len;
+};
+#endif
+
+struct msghdr {
+  void         *msg_name;
+  socklen_t     msg_namelen;
+  struct iovec *msg_iov;
+  int           msg_iovlen;
+  void         *msg_control;
+  socklen_t     msg_controllen;
+  int           msg_flags;
+};
+
+/* Socket protocol types (TCP/UDP/RAW) */
+#define SOCK_STREAM     1
+#define SOCK_DGRAM      2
+#define SOCK_RAW        3
+
+/*
+ * Option flags per-socket. These must match the SOF_ flags in ip.h (checked in init.c)
+ */
+#define SO_REUSEADDR   0x0004 /* Allow local address reuse */
+#define SO_KEEPALIVE   0x0008 /* keep connections alive */
+#define SO_BROADCAST   0x0020 /* permit to send and to receive broadcast messages (see IP_SOF_BROADCAST option) */
+
+
+/*
+ * Additional options, not kept in so_options.
+ */
+#define SO_DEBUG       0x0001 /* Unimplemented: turn on debugging info recording */
+#define SO_ACCEPTCONN  0x0002 /* socket has had listen() */
+#define SO_DONTROUTE   0x0010 /* Unimplemented: just use interface addresses */
+#define SO_USELOOPBACK 0x0040 /* Unimplemented: bypass hardware when possible */
+#define SO_LINGER      0x0080 /* linger on close if data present */
+#define SO_DONTLINGER  ((int)(~SO_LINGER))
+#define SO_OOBINLINE   0x0100 /* Unimplemented: leave received OOB data in line */
+#define SO_REUSEPORT   0x0200 /* Unimplemented: allow local address & port reuse */
+#define SO_SNDBUF      0x1001 /* Unimplemented: send buffer size */
+#define SO_RCVBUF      0x1002 /* receive buffer size */
+#define SO_SNDLOWAT    0x1003 /* Unimplemented: send low-water mark */
+#define SO_RCVLOWAT    0x1004 /* Unimplemented: receive low-water mark */
+#define SO_SNDTIMEO    0x1005 /* send timeout */
+#define SO_RCVTIMEO    0x1006 /* receive timeout */
+#define SO_ERROR       0x1007 /* get error status and clear */
+#define SO_TYPE        0x1008 /* get socket type */
+#define SO_CONTIMEO    0x1009 /* Unimplemented: connect timeout */
+#define SO_NO_CHECK    0x100a /* don't create UDP checksum */
+
+
+/*
+ * Structure used for manipulating linger option.
+ */
+struct linger {
+       int l_onoff;                /* option on/off */
+       int l_linger;               /* linger time in seconds */
+};
+
+/*
+ * Level number for (get/set)sockopt() to apply to socket itself.
+ */
+#define  SOL_SOCKET  0xfff    /* options for socket level */
+
+
+#define AF_UNSPEC       0
+#define AF_INET         2
+#if LWIP_IPV6
+#define AF_INET6        10
+#else /* LWIP_IPV6 */
+#define AF_INET6        AF_UNSPEC
+#endif /* LWIP_IPV6 */
+#define PF_INET         AF_INET
+#define PF_INET6        AF_INET6
+#define PF_UNSPEC       AF_UNSPEC
+
+#define IPPROTO_IP      0
+#define IPPROTO_ICMP    1
+#define IPPROTO_TCP     6
+#define IPPROTO_UDP     17
+#if LWIP_IPV6
+#define IPPROTO_IPV6    41
+#define IPPROTO_ICMPV6  58
+#endif /* LWIP_IPV6 */
+#define IPPROTO_UDPLITE 136
+#define IPPROTO_RAW     255
+
+/* Flags we can use with send and recv. */
+#define MSG_PEEK       0x01    /* Peeks at an incoming message */
+#define MSG_WAITALL    0x02    /* Unimplemented: Requests that the function block until the full amount of data requested can be returned */
+#define MSG_OOB        0x04    /* Unimplemented: Requests out-of-band data. The significance and semantics of out-of-band data are protocol-specific */
+#define MSG_DONTWAIT   0x08    /* Nonblocking i/o for this operation only */
+#define MSG_MORE       0x10    /* Sender will send more */
+
+
+/*
+ * Options for level IPPROTO_IP
+ */
+#define IP_TOS             1
+#define IP_TTL             2
+
+#if LWIP_TCP
+/*
+ * Options for level IPPROTO_TCP
+ */
+#define TCP_NODELAY    0x01    /* don't delay send to coalesce packets */
+#define TCP_KEEPALIVE  0x02    /* send KEEPALIVE probes when idle for pcb->keep_idle milliseconds */
+#define TCP_KEEPIDLE   0x03    /* set pcb->keep_idle  - Same as TCP_KEEPALIVE, but use seconds for get/setsockopt */
+#define TCP_KEEPINTVL  0x04    /* set pcb->keep_intvl - Use seconds for get/setsockopt */
+#define TCP_KEEPCNT    0x05    /* set pcb->keep_cnt   - Use number of probes sent for get/setsockopt */
+#endif /* LWIP_TCP */
+
+#if LWIP_IPV6
+/*
+ * Options for level IPPROTO_IPV6
+ */
+#define IPV6_CHECKSUM       7  /* RFC3542: calculate and insert the ICMPv6 checksum for raw sockets. */
+#define IPV6_V6ONLY         27 /* RFC3493: boolean control to restrict AF_INET6 sockets to IPv6 communications only. */
+#endif /* LWIP_IPV6 */
+
+#if LWIP_UDP && LWIP_UDPLITE
+/*
+ * Options for level IPPROTO_UDPLITE
+ */
+#define UDPLITE_SEND_CSCOV 0x01 /* sender checksum coverage */
+#define UDPLITE_RECV_CSCOV 0x02 /* minimal receiver checksum coverage */
+#endif /* LWIP_UDP && LWIP_UDPLITE*/
+
+
+#if LWIP_MULTICAST_TX_OPTIONS
+/*
+ * Options and types for UDP multicast traffic handling
+ */
+#define IP_MULTICAST_TTL   5
+#define IP_MULTICAST_IF    6
+#define IP_MULTICAST_LOOP  7
+#endif /* LWIP_MULTICAST_TX_OPTIONS */
+
+#if LWIP_IGMP
+/*
+ * Options and types related to multicast membership
+ */
+#define IP_ADD_MEMBERSHIP  3
+#define IP_DROP_MEMBERSHIP 4
+
+typedef struct ip_mreq {
+    struct in_addr imr_multiaddr; /* IP multicast address of group */
+    struct in_addr imr_interface; /* local IP address of interface */
+} ip_mreq;
+#endif /* LWIP_IGMP */
+
+/*
+ * The Type of Service provides an indication of the abstract
+ * parameters of the quality of service desired.  These parameters are
+ * to be used to guide the selection of the actual service parameters
+ * when transmitting a datagram through a particular network.  Several
+ * networks offer service precedence, which somehow treats high
+ * precedence traffic as more important than other traffic (generally
+ * by accepting only traffic above a certain precedence at time of high
+ * load).  The major choice is a three way tradeoff between low-delay,
+ * high-reliability, and high-throughput.
+ * The use of the Delay, Throughput, and Reliability indications may
+ * increase the cost (in some sense) of the service.  In many networks
+ * better performance for one of these parameters is coupled with worse
+ * performance on another.  Except for very unusual cases at most two
+ * of these three indications should be set.
+ */
+#define IPTOS_TOS_MASK          0x1E
+#define IPTOS_TOS(tos)          ((tos) & IPTOS_TOS_MASK)
+#define IPTOS_LOWDELAY          0x10
+#define IPTOS_THROUGHPUT        0x08
+#define IPTOS_RELIABILITY       0x04
+#define IPTOS_LOWCOST           0x02
+#define IPTOS_MINCOST           IPTOS_LOWCOST
+
+/*
+ * The Network Control precedence designation is intended to be used
+ * within a network only.  The actual use and control of that
+ * designation is up to each network. The Internetwork Control
+ * designation is intended for use by gateway control originators only.
+ * If the actual use of these precedence designations is of concern to
+ * a particular network, it is the responsibility of that network to
+ * control the access to, and use of, those precedence designations.
+ */
+#define IPTOS_PREC_MASK                 0xe0
+#define IPTOS_PREC(tos)                ((tos) & IPTOS_PREC_MASK)
+#define IPTOS_PREC_NETCONTROL           0xe0
+#define IPTOS_PREC_INTERNETCONTROL      0xc0
+#define IPTOS_PREC_CRITIC_ECP           0xa0
+#define IPTOS_PREC_FLASHOVERRIDE        0x80
+#define IPTOS_PREC_FLASH                0x60
+#define IPTOS_PREC_IMMEDIATE            0x40
+#define IPTOS_PREC_PRIORITY             0x20
+#define IPTOS_PREC_ROUTINE              0x00
+
+
+/*
+ * Commands for ioctlsocket(),  taken from the BSD file fcntl.h.
+ * lwip_ioctl only supports FIONREAD and FIONBIO, for now
+ *
+ * Ioctl's have the command encoded in the lower word,
+ * and the size of any in or out parameters in the upper
+ * word.  The high 2 bits of the upper word are used
+ * to encode the in/out status of the parameter; for now
+ * we restrict parameters to at most 128 bytes.
+ */
+#if !defined(FIONREAD) || !defined(FIONBIO)
+#define IOCPARM_MASK    0x7fU           /* parameters must be < 128 bytes */
+#define IOC_VOID        0x20000000UL    /* no parameters */
+#define IOC_OUT         0x40000000UL    /* copy out parameters */
+#define IOC_IN          0x80000000UL    /* copy in parameters */
+#define IOC_INOUT       (IOC_IN|IOC_OUT)
+                                        /* 0x20000000 distinguishes new &
+                                           old ioctl's */
+#define _IO(x,y)        (IOC_VOID|((x)<<8)|(y))
+
+#define _IOR(x,y,t)     (IOC_OUT|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y))
+
+#define _IOW(x,y,t)     (IOC_IN|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y))
+#endif /* !defined(FIONREAD) || !defined(FIONBIO) */
+
+#ifndef FIONREAD
+#define FIONREAD    _IOR('f', 127, unsigned long) /* get # bytes to read */
+#endif
+#ifndef FIONBIO
+#define FIONBIO     _IOW('f', 126, unsigned long) /* set/clear non-blocking i/o */
+#endif
+
+/* Socket I/O Controls: unimplemented */
+#ifndef SIOCSHIWAT
+#define SIOCSHIWAT  _IOW('s',  0, unsigned long)  /* set high watermark */
+#define SIOCGHIWAT  _IOR('s',  1, unsigned long)  /* get high watermark */
+#define SIOCSLOWAT  _IOW('s',  2, unsigned long)  /* set low watermark */
+#define SIOCGLOWAT  _IOR('s',  3, unsigned long)  /* get low watermark */
+#define SIOCATMARK  _IOR('s',  7, unsigned long)  /* at oob mark? */
+#endif
+
+/* commands for fnctl */
+#ifndef F_GETFL
+#define F_GETFL 3
+#endif
+#ifndef F_SETFL
+#define F_SETFL 4
+#endif
+
+/* File status flags and file access modes for fnctl,
+   these are bits in an int. */
+#ifndef O_NONBLOCK
+#define O_NONBLOCK  1 /* nonblocking I/O */
+#endif
+#ifndef O_NDELAY
+#define O_NDELAY    1 /* same as O_NONBLOCK, for compatibility */
+#endif
+
+#ifndef SHUT_RD
+  #define SHUT_RD   0
+  #define SHUT_WR   1
+  #define SHUT_RDWR 2
+#endif
+
+/* FD_SET used for lwip_select */
+#ifndef FD_SET
+#undef  FD_SETSIZE
+/* Make FD_SETSIZE match NUM_SOCKETS in socket.c */
+#define FD_SETSIZE    MEMP_NUM_NETCONN
+#define FDSETSAFESET(n, code) do { \
+  if (((n) - LWIP_SOCKET_OFFSET < MEMP_NUM_NETCONN) && (((int)(n) - LWIP_SOCKET_OFFSET) >= 0)) { \
+  code; }} while(0)
+#define FDSETSAFEGET(n, code) (((n) - LWIP_SOCKET_OFFSET < MEMP_NUM_NETCONN) && (((int)(n) - LWIP_SOCKET_OFFSET) >= 0) ?\
+  (code) : 0)
+#define FD_SET(n, p)  FDSETSAFESET(n, (p)->fd_bits[((n)-LWIP_SOCKET_OFFSET)/8] |=  (1 << (((n)-LWIP_SOCKET_OFFSET) & 7)))
+#define FD_CLR(n, p)  FDSETSAFESET(n, (p)->fd_bits[((n)-LWIP_SOCKET_OFFSET)/8] &= ~(1 << (((n)-LWIP_SOCKET_OFFSET) & 7)))
+#define FD_ISSET(n,p) FDSETSAFEGET(n, (p)->fd_bits[((n)-LWIP_SOCKET_OFFSET)/8] &   (1 << (((n)-LWIP_SOCKET_OFFSET) & 7)))
+#define FD_ZERO(p)    memset((void*)(p), 0, sizeof(*(p)))
+
+typedef struct fd_set
+{
+  unsigned char fd_bits [(FD_SETSIZE+7)/8];
+} fd_set;
+
+#elif LWIP_SOCKET_OFFSET
+#error LWIP_SOCKET_OFFSET does not work with external FD_SET!
+#endif /* FD_SET */
+
+/** LWIP_TIMEVAL_PRIVATE: if you want to use the struct timeval provided
+ * by your system, set this to 0 and include  in cc.h */
+#ifndef LWIP_TIMEVAL_PRIVATE
+#define LWIP_TIMEVAL_PRIVATE 1
+#endif
+
+#if LWIP_TIMEVAL_PRIVATE
+struct timeval {
+  long    tv_sec;         /* seconds */
+  long    tv_usec;        /* and microseconds */
+};
+#endif /* LWIP_TIMEVAL_PRIVATE */
+
+#define lwip_socket_init() /* Compatibility define, no init needed. */
+void lwip_socket_thread_init(void); /* LWIP_NETCONN_SEM_PER_THREAD==1: initialize thread-local semaphore */
+void lwip_socket_thread_cleanup(void); /* LWIP_NETCONN_SEM_PER_THREAD==1: destroy thread-local semaphore */
+
+#if LWIP_COMPAT_SOCKETS == 2
+
+
+/* This helps code parsers/code completion by not having the COMPAT functions as defines */
+#define lwip_accept       accept
+#define lwip_bind         bind
+#define lwip_shutdown     shutdown
+#define lwip_getpeername  getpeername
+#define lwip_getsockname  getsockname
+#define lwip_setsockopt   setsockopt
+#define lwip_getsockopt   getsockopt
+#define lwip_close        closesocket
+#define lwip_connect      connect
+#define lwip_listen       listen
+#define lwip_recv         recv
+#define lwip_recvfrom     recvfrom
+#define lwip_send         send
+#define lwip_sendmsg      sendmsg
+#define lwip_sendto       sendto
+#define lwip_socket       socket
+#define lwip_select       select
+#define lwip_ioctlsocket  ioctl
+
+#if LWIP_POSIX_SOCKETS_IO_NAMES
+#define lwip_read         read
+#define lwip_write        write
+#define lwip_writev       writev
+#undef lwip_close
+#define lwip_close        close
+#define closesocket(s)    close(s)
+#define lwip_fcntl        fcntl
+#define lwip_ioctl        ioctl
+#endif /* LWIP_POSIX_SOCKETS_IO_NAMES */
+#endif /* LWIP_COMPAT_SOCKETS == 2 */
+
+int lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen);
+int lwip_bind(int s, const struct sockaddr *name, socklen_t namelen);
+int lwip_shutdown(int s, int how);
+int lwip_getpeername (int s, struct sockaddr *name, socklen_t *namelen);
+int lwip_getsockname (int s, struct sockaddr *name, socklen_t *namelen);
+int lwip_getsockopt (int s, int level, int optname, void *optval, socklen_t *optlen);
+int lwip_setsockopt (int s, int level, int optname, const void *optval, socklen_t optlen);
+int lwip_close(int s);
+int lwip_connect(int s, const struct sockaddr *name, socklen_t namelen);
+int lwip_listen(int s, int backlog);
+int lwip_recv(int s, void *mem, size_t len, int flags);
+int lwip_read(int s, void *mem, size_t len);
+int lwip_recvfrom(int s, void *mem, size_t len, int flags,
+      struct sockaddr *from, socklen_t *fromlen);
+int lwip_send(int s, const void *dataptr, size_t size, int flags);
+int lwip_sendmsg(int s, const struct msghdr *message, int flags);
+int lwip_sendto(int s, const void *dataptr, size_t size, int flags,
+    const struct sockaddr *to, socklen_t tolen);
+int lwip_socket(int domain, int type, int protocol);
+int lwip_write(int s, const void *dataptr, size_t size);
+int lwip_writev(int s, const struct iovec *iov, int iovcnt);
+int lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset,
+                struct timeval *timeout);
+int lwip_ioctl(int s, long cmd, void *argp);
+int lwip_fcntl(int s, int cmd, int val);
+
+#if LWIP_COMPAT_SOCKETS
+#if LWIP_COMPAT_SOCKETS != 2
+
+#if LWIP_THREAD_SAFE
+
+int lwip_accept_r(int s, struct sockaddr *addr, socklen_t *addrlen);
+int lwip_bind_r(int s, const struct sockaddr *name, socklen_t namelen);
+int lwip_shutdown_r(int s, int how);
+int lwip_getpeername_r (int s, struct sockaddr *name, socklen_t *namelen);
+int lwip_getsockname_r (int s, struct sockaddr *name, socklen_t *namelen);
+int lwip_getsockopt_r (int s, int level, int optname, void *optval, socklen_t *optlen);
+int lwip_setsockopt_r (int s, int level, int optname, const void *optval, socklen_t optlen);
+int lwip_close_r(int s);
+int lwip_connect_r(int s, const struct sockaddr *name, socklen_t namelen);
+int lwip_listen_r(int s, int backlog);
+int lwip_recv_r(int s, void *mem, size_t len, int flags);
+int lwip_read_r(int s, void *mem, size_t len); 
+int lwip_recvfrom_r(int s, void *mem, size_t len, int flags,
+      struct sockaddr *from, socklen_t *fromlen);
+int lwip_send_r(int s, const void *dataptr, size_t size, int flags);
+int lwip_sendmsg_r(int s, const struct msghdr *message, int flags);
+int lwip_sendto_r(int s, const void *dataptr, size_t size, int flags,
+    const struct sockaddr *to, socklen_t tolen);
+int lwip_socket(int domain, int type, int protocol);
+int lwip_write_r(int s, const void *dataptr, size_t size);
+int lwip_writev_r(int s, const struct iovec *iov, int iovcnt);
+int lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset,
+                struct timeval *timeout);
+int lwip_ioctl_r(int s, long cmd, void *argp);
+int lwip_fcntl_r(int s, int cmd, int val);
+
+#define accept(s,addr,addrlen)                    lwip_accept_r(s,addr,addrlen)
+#define bind(s,name,namelen)                      lwip_bind_r(s,name,namelen)
+#define shutdown(s,how)                           lwip_shutdown_r(s,how)
+#define getpeername(s,name,namelen)               lwip_getpeername_r(s,name,namelen)
+#define getsockname(s,name,namelen)               lwip_getsockname_r(s,name,namelen)
+#define setsockopt(s,level,optname,opval,optlen)  lwip_setsockopt_r(s,level,optname,opval,optlen)
+#define getsockopt(s,level,optname,opval,optlen)  lwip_getsockopt_r(s,level,optname,opval,optlen)
+#define closesocket(s)                            lwip_close_r(s)
+#define connect(s,name,namelen)                   lwip_connect_r(s,name,namelen)
+#define listen(s,backlog)                         lwip_listen_r(s,backlog)
+#define recv(s,mem,len,flags)                     lwip_recv_r(s,mem,len,flags)
+#define recvfrom(s,mem,len,flags,from,fromlen)    lwip_recvfrom_r(s,mem,len,flags,from,fromlen)
+#define send(s,dataptr,size,flags)                lwip_send_r(s,dataptr,size,flags)
+#define sendmsg(s,message,flags)                  lwip_sendmsg_r(s,message,flags)
+#define sendto(s,dataptr,size,flags,to,tolen)     lwip_sendto_r(s,dataptr,size,flags,to,tolen)
+#define socket(domain,type,protocol)              lwip_socket(domain,type,protocol)
+#define select(maxfdp1,readset,writeset,exceptset,timeout)     lwip_select(maxfdp1,readset,writeset,exceptset,timeout)
+#define ioctlsocket(s,cmd,argp)                   lwip_ioctl_r(s,cmd,argp)
+
+#if LWIP_POSIX_SOCKETS_IO_NAMES
+#define read(s,mem,len)                           lwip_read_r(s,mem,len)
+#define write(s,dataptr,len)                      lwip_write_r(s,dataptr,len)
+#define writev(s,iov,iovcnt)                      lwip_writev_r(s,iov,iovcnt)
+#define close(s)                                  lwip_close_r(s)
+#define fcntl(s,cmd,val)                          lwip_fcntl_r(s,cmd,val)
+#define ioctl(s,cmd,argp)                         lwip_ioctl_r(s,cmd,argp)
+#endif /* LWIP_POSIX_SOCKETS_IO_NAMES */
+
+#else
+
+#define accept(s,addr,addrlen)                    lwip_accept(s,addr,addrlen)
+#define bind(s,name,namelen)                      lwip_bind(s,name,namelen)
+#define shutdown(s,how)                           lwip_shutdown(s,how)
+#define getpeername(s,name,namelen)               lwip_getpeername(s,name,namelen)
+#define getsockname(s,name,namelen)               lwip_getsockname(s,name,namelen)
+#define setsockopt(s,level,optname,opval,optlen)  lwip_setsockopt(s,level,optname,opval,optlen)
+#define getsockopt(s,level,optname,opval,optlen)  lwip_getsockopt(s,level,optname,opval,optlen)
+#define closesocket(s)                            lwip_close(s)
+#define connect(s,name,namelen)                   lwip_connect(s,name,namelen)
+#define listen(s,backlog)                         lwip_listen(s,backlog)
+#define recv(s,mem,len,flags)                     lwip_recv(s,mem,len,flags)
+#define recvfrom(s,mem,len,flags,from,fromlen)    lwip_recvfrom(s,mem,len,flags,from,fromlen)
+#define send(s,dataptr,size,flags)                lwip_send(s,dataptr,size,flags)
+#define sendmsg(s,message,flags)                  lwip_sendmsg(s,message,flags)
+#define sendto(s,dataptr,size,flags,to,tolen)     lwip_sendto(s,dataptr,size,flags,to,tolen)
+#define socket(domain,type,protocol)              lwip_socket(domain,type,protocol)
+#define select(maxfdp1,readset,writeset,exceptset,timeout)     lwip_select(maxfdp1,readset,writeset,exceptset,timeout)
+#define ioctlsocket(s,cmd,argp)                   lwip_ioctl(s,cmd,argp)
+
+#if LWIP_POSIX_SOCKETS_IO_NAMES
+#define read(s,mem,len)                           lwip_read(s,mem,len)
+#define write(s,dataptr,len)                      lwip_write(s,dataptr,len)
+#define writev(s,iov,iovcnt)                      lwip_writev(s,iov,iovcnt)
+#define close(s)                                  lwip_close(s)
+#define fcntl(s,cmd,val)                          lwip_fcntl(s,cmd,val)
+#define ioctl(s,cmd,argp)                         lwip_ioctl(s,cmd,argp)
+#endif /* LWIP_POSIX_SOCKETS_IO_NAMES */
+#endif /* LWIP_THREAD_SAFE */
+
+#endif /* LWIP_COMPAT_SOCKETS != 2 */
+
+#if LWIP_IPV4 && LWIP_IPV6
+#define inet_ntop(af,src,dst,size) \
+    (((af) == AF_INET6) ? ip6addr_ntoa_r((const ip6_addr_t*)(src),(dst),(size)) \
+     : (((af) == AF_INET) ? ip4addr_ntoa_r((const ip4_addr_t*)(src),(dst),(size)) : NULL))
+#define inet_pton(af,src,dst) \
+    (((af) == AF_INET6) ? ip6addr_aton((src),(ip6_addr_t*)(dst)) \
+     : (((af) == AF_INET) ? ip4addr_aton((src),(ip4_addr_t*)(dst)) : 0))
+#elif LWIP_IPV4 /* LWIP_IPV4 && LWIP_IPV6 */
+#define inet_ntop(af,src,dst,size) \
+    (((af) == AF_INET) ? ip4addr_ntoa_r((const ip4_addr_t*)(src),(dst),(size)) : NULL)
+#define inet_pton(af,src,dst) \
+    (((af) == AF_INET) ? ip4addr_aton((src),(ip4_addr_t*)(dst)) : 0)
+#else /* LWIP_IPV4 && LWIP_IPV6 */
+#define inet_ntop(af,src,dst,size) \
+    (((af) == AF_INET6) ? ip6addr_ntoa_r((const ip6_addr_t*)(src),(dst),(size)) : NULL)
+#define inet_pton(af,src,dst) \
+    (((af) == AF_INET6) ? ip6addr_aton((src),(ip6_addr_t*)(dst)) : 0)
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+
+#endif /* LWIP_COMPAT_SOCKETS */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_SOCKET */
+
+#endif /* LWIP_HDR_SOCKETS_H */
diff --git a/tools/sdk/include/lwip/lwip/stats.h b/tools/sdk/include/lwip/lwip/stats.h
new file mode 100755
index 00000000..176723d2
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/stats.h
@@ -0,0 +1,462 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef LWIP_HDR_STATS_H
+#define LWIP_HDR_STATS_H
+
+#include "lwip/opt.h"
+
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if LWIP_STATS
+
+#ifndef LWIP_STATS_LARGE
+#define LWIP_STATS_LARGE 0
+#endif
+
+#if LWIP_STATS_LARGE
+#define STAT_COUNTER     u32_t
+#define STAT_COUNTER_F   U32_F
+#else
+#define STAT_COUNTER     u16_t
+#define STAT_COUNTER_F   U16_F
+#endif
+
+struct stats_proto {
+  STAT_COUNTER xmit;             /* Transmitted packets. */
+  STAT_COUNTER recv;             /* Received packets. */
+  STAT_COUNTER fw;               /* Forwarded packets. */
+  STAT_COUNTER drop;             /* Dropped packets. */
+  STAT_COUNTER chkerr;           /* Checksum error. */
+  STAT_COUNTER lenerr;           /* Invalid length error. */
+  STAT_COUNTER memerr;           /* Out of memory error. */
+  STAT_COUNTER rterr;            /* Routing error. */
+  STAT_COUNTER proterr;          /* Protocol error. */
+  STAT_COUNTER opterr;           /* Error in options. */
+  STAT_COUNTER err;              /* Misc error. */
+  STAT_COUNTER cachehit;
+};
+
+struct stats_igmp {
+  STAT_COUNTER xmit;             /* Transmitted packets. */
+  STAT_COUNTER recv;             /* Received packets. */
+  STAT_COUNTER drop;             /* Dropped packets. */
+  STAT_COUNTER chkerr;           /* Checksum error. */
+  STAT_COUNTER lenerr;           /* Invalid length error. */
+  STAT_COUNTER memerr;           /* Out of memory error. */
+  STAT_COUNTER proterr;          /* Protocol error. */
+  STAT_COUNTER rx_v1;            /* Received v1 frames. */
+  STAT_COUNTER rx_group;         /* Received group-specific queries. */
+  STAT_COUNTER rx_general;       /* Received general queries. */
+  STAT_COUNTER rx_report;        /* Received reports. */
+  STAT_COUNTER tx_join;          /* Sent joins. */
+  STAT_COUNTER tx_leave;         /* Sent leaves. */
+  STAT_COUNTER tx_report;        /* Sent reports. */
+};
+
+struct stats_mem {
+#ifdef LWIP_DEBUG
+  const char *name;
+#endif /* LWIP_DEBUG */
+  STAT_COUNTER err;
+  mem_size_t avail;
+  mem_size_t used;
+  mem_size_t max;
+  STAT_COUNTER illegal;
+};
+
+struct stats_syselem {
+  STAT_COUNTER used;
+  STAT_COUNTER max;
+  STAT_COUNTER err;
+};
+
+struct stats_sys {
+  struct stats_syselem sem;
+  struct stats_syselem mutex;
+  struct stats_syselem mbox;
+};
+
+struct stats_mib2 {
+  /* IP */
+  u32_t ipinhdrerrors;
+  u32_t ipinaddrerrors;
+  u32_t ipinunknownprotos;
+  u32_t ipindiscards;
+  u32_t ipindelivers;
+  u32_t ipoutrequests;
+  u32_t ipoutdiscards;
+  u32_t ipoutnoroutes;
+  u32_t ipreasmoks;
+  u32_t ipreasmfails;
+  u32_t ipfragoks;
+  u32_t ipfragfails;
+  u32_t ipfragcreates;
+  u32_t ipreasmreqds;
+  u32_t ipforwdatagrams;
+  u32_t ipinreceives;
+
+  /* TCP */
+  u32_t tcpactiveopens;
+  u32_t tcppassiveopens;
+  u32_t tcpattemptfails;
+  u32_t tcpestabresets;
+  u32_t tcpoutsegs;
+  u32_t tcpretranssegs;
+  u32_t tcpinsegs;
+  u32_t tcpinerrs;
+  u32_t tcpoutrsts;
+
+  /* UDP */
+  u32_t udpindatagrams;
+  u32_t udpnoports;
+  u32_t udpinerrors;
+  u32_t udpoutdatagrams;
+
+  /* ICMP */
+  u32_t icmpinmsgs;
+  u32_t icmpinerrors;
+  u32_t icmpindestunreachs;
+  u32_t icmpintimeexcds;
+  u32_t icmpinparmprobs;
+  u32_t icmpinsrcquenchs;
+  u32_t icmpinredirects;
+  u32_t icmpinechos;
+  u32_t icmpinechoreps;
+  u32_t icmpintimestamps;
+  u32_t icmpintimestampreps;
+  u32_t icmpinaddrmasks;
+  u32_t icmpinaddrmaskreps;
+  u32_t icmpoutmsgs;
+  u32_t icmpouterrors;
+  u32_t icmpoutdestunreachs;
+  u32_t icmpouttimeexcds;
+  u32_t icmpoutechos; /* can be incremented by user application ('ping') */
+  u32_t icmpoutechoreps;
+};
+
+struct stats_mib2_netif_ctrs {
+  /* The total number of octets received on the interface, including framing characters */
+  u32_t ifinoctets;
+  /* The number of packets, delivered by this sub-layer to a higher (sub-)layer, which were
+   * not addressed to a multicast or broadcast address at this sub-layer */
+  u32_t ifinucastpkts;
+  /* The number of packets, delivered by this sub-layer to a higher (sub-)layer, which were 
+   * addressed to a multicast or broadcast address at this sub-layer */
+  u32_t ifinnucastpkts;
+  /* The number of inbound packets which were chosen to be discarded even though no errors had 
+   * been detected to prevent their being deliverable to a higher-layer protocol. One possible 
+   * reason for discarding such a packet could be to free up buffer space */
+  u32_t ifindiscards;
+  /* For packet-oriented interfaces, the number of inbound packets that contained errors 
+   * preventing them from being deliverable to a higher-layer protocol.  For character-
+   * oriented or fixed-length interfaces, the number of inbound transmission units that 
+   * contained errors preventing them from being deliverable to a higher-layer protocol. */
+  u32_t ifinerrors;
+  /* For packet-oriented interfaces, the number of packets received via the interface which
+   * were discarded because of an unknown or unsupported protocol.  For character-oriented
+   * or fixed-length interfaces that support protocol multiplexing the number of transmission
+   * units received via the interface which were discarded because of an unknown or unsupported
+   * protocol. For any interface that does not support protocol multiplexing, this counter will
+   * always be 0 */
+  u32_t ifinunknownprotos;
+  /* The total number of octets transmitted out of the interface, including framing characters. */
+  u32_t ifoutoctets;
+  /* The total number of packets that higher-level protocols requested be transmitted, and
+   * which were not addressed to a multicast or broadcast address at this sub-layer, including
+   * those that were discarded or not sent. */
+  u32_t ifoutucastpkts;
+  /* The total number of packets that higher-level protocols requested be transmitted, and which
+   * were addressed to a multicast or broadcast address at this sub-layer, including
+   * those that were discarded or not sent. */
+  u32_t ifoutnucastpkts;
+  /* The number of outbound packets which were chosen to be discarded even though no errors had
+   * been detected to prevent their being transmitted.  One possible reason for discarding
+   * such a packet could be to free up buffer space. */
+  u32_t ifoutdiscards;
+  /* For packet-oriented interfaces, the number of outbound packets that could not be transmitted
+   * because of errors. For character-oriented or fixed-length interfaces, the number of outbound
+   * transmission units that could not be transmitted because of errors. */
+  u32_t ifouterrors;
+};
+
+struct stats_ {
+#if LINK_STATS
+  struct stats_proto link;
+#endif
+#if ETHARP_STATS
+  struct stats_proto etharp;
+#endif
+#if IPFRAG_STATS
+  struct stats_proto ip_frag;
+#endif
+#if IP_STATS
+  struct stats_proto ip;
+#endif
+#if ICMP_STATS
+  struct stats_proto icmp;
+#endif
+#if IGMP_STATS
+  struct stats_igmp igmp;
+#endif
+#if UDP_STATS
+  struct stats_proto udp;
+#endif
+#if TCP_STATS
+  struct stats_proto tcp;
+#endif
+#if MEM_STATS
+  struct stats_mem mem;
+#endif
+#if MEMP_STATS
+  struct stats_mem memp[MEMP_MAX];
+#endif
+#if SYS_STATS
+  struct stats_sys sys;
+#endif
+#if IP6_STATS
+  struct stats_proto ip6;
+#endif
+#if ICMP6_STATS
+  struct stats_proto icmp6;
+#endif
+#if IP6_FRAG_STATS
+  struct stats_proto ip6_frag;
+#endif
+#if MLD6_STATS
+  struct stats_igmp mld6;
+#endif
+#if ND6_STATS
+  struct stats_proto nd6;
+#endif
+#if MIB2_STATS
+  struct stats_mib2 mib2;
+#endif
+};
+
+extern struct stats_ lwip_stats;
+
+void stats_init(void);
+
+#define STATS_INC(x) ++lwip_stats.x
+#define STATS_DEC(x) --lwip_stats.x
+#define STATS_INC_USED(x, y) do { lwip_stats.x.used += y; \
+                                if (lwip_stats.x.max < lwip_stats.x.used) { \
+                                    lwip_stats.x.max = lwip_stats.x.used; \
+                                } \
+                             } while(0)
+#define STATS_GET(x) lwip_stats.x
+#else /* LWIP_STATS */
+#define stats_init()
+#define STATS_INC(x)
+#define STATS_DEC(x)
+#define STATS_INC_USED(x)
+#endif /* LWIP_STATS */
+
+#if TCP_STATS
+#define TCP_STATS_INC(x) STATS_INC(x)
+#define TCP_STATS_DISPLAY() stats_display_proto(&lwip_stats.tcp, "TCP")
+#else
+#define TCP_STATS_INC(x)
+#define TCP_STATS_DISPLAY()
+#endif
+
+#if UDP_STATS
+#define UDP_STATS_INC(x) STATS_INC(x)
+#define UDP_STATS_DISPLAY() stats_display_proto(&lwip_stats.udp, "UDP")
+#else
+#define UDP_STATS_INC(x)
+#define UDP_STATS_DISPLAY()
+#endif
+
+#if ICMP_STATS
+#define ICMP_STATS_INC(x) STATS_INC(x)
+#define ICMP_STATS_DISPLAY() stats_display_proto(&lwip_stats.icmp, "ICMP")
+#else
+#define ICMP_STATS_INC(x)
+#define ICMP_STATS_DISPLAY()
+#endif
+
+#if IGMP_STATS
+#define IGMP_STATS_INC(x) STATS_INC(x)
+#define IGMP_STATS_DISPLAY() stats_display_igmp(&lwip_stats.igmp, "IGMP")
+#else
+#define IGMP_STATS_INC(x)
+#define IGMP_STATS_DISPLAY()
+#endif
+
+#if IP_STATS
+#define IP_STATS_INC(x) STATS_INC(x)
+#define IP_STATS_DISPLAY() stats_display_proto(&lwip_stats.ip, "IP")
+#else
+#define IP_STATS_INC(x)
+#define IP_STATS_DISPLAY()
+#endif
+
+#if IPFRAG_STATS
+#define IPFRAG_STATS_INC(x) STATS_INC(x)
+#define IPFRAG_STATS_DISPLAY() stats_display_proto(&lwip_stats.ip_frag, "IP_FRAG")
+#else
+#define IPFRAG_STATS_INC(x)
+#define IPFRAG_STATS_DISPLAY()
+#endif
+
+#if ETHARP_STATS
+#define ETHARP_STATS_INC(x) STATS_INC(x)
+#define ETHARP_STATS_DISPLAY() stats_display_proto(&lwip_stats.etharp, "ETHARP")
+#else
+#define ETHARP_STATS_INC(x)
+#define ETHARP_STATS_DISPLAY()
+#endif
+
+#if LINK_STATS
+#define LINK_STATS_INC(x) STATS_INC(x)
+#define LINK_STATS_DISPLAY() stats_display_proto(&lwip_stats.link, "LINK")
+#else
+#define LINK_STATS_INC(x)
+#define LINK_STATS_DISPLAY()
+#endif
+
+#if MEM_STATS
+#define MEM_STATS_AVAIL(x, y) lwip_stats.mem.x = y
+#define MEM_STATS_INC(x) STATS_INC(mem.x)
+#define MEM_STATS_INC_USED(x, y) STATS_INC_USED(mem, y)
+#define MEM_STATS_DEC_USED(x, y) lwip_stats.mem.x -= y
+#define MEM_STATS_DISPLAY() stats_display_mem(&lwip_stats.mem, "HEAP")
+#else
+#define MEM_STATS_AVAIL(x, y)
+#define MEM_STATS_INC(x)
+#define MEM_STATS_INC_USED(x, y)
+#define MEM_STATS_DEC_USED(x, y)
+#define MEM_STATS_DISPLAY()
+#endif
+
+#if MEMP_STATS
+#define MEMP_STATS_AVAIL(x, i, y) lwip_stats.memp[i].x = y
+#define MEMP_STATS_INC(x, i) STATS_INC(memp[i].x)
+#define MEMP_STATS_DEC(x, i) STATS_DEC(memp[i].x)
+#define MEMP_STATS_INC_USED(x, i) STATS_INC_USED(memp[i], 1)
+#define MEMP_STATS_DISPLAY(i) stats_display_memp(&lwip_stats.memp[i], i)
+#define MEMP_STATS_GET(x, i) STATS_GET(memp[i].x)
+#else
+#define MEMP_STATS_AVAIL(x, i, y)
+#define MEMP_STATS_INC(x, i)
+#define MEMP_STATS_DEC(x, i)
+#define MEMP_STATS_INC_USED(x, i)
+#define MEMP_STATS_DISPLAY(i)
+#define MEMP_STATS_GET(x, i) 0
+#endif
+
+#if SYS_STATS
+#define SYS_STATS_INC(x) STATS_INC(sys.x)
+#define SYS_STATS_DEC(x) STATS_DEC(sys.x)
+#define SYS_STATS_INC_USED(x) STATS_INC_USED(sys.x, 1)
+#define SYS_STATS_DISPLAY() stats_display_sys(&lwip_stats.sys)
+#else
+#define SYS_STATS_INC(x)
+#define SYS_STATS_DEC(x)
+#define SYS_STATS_INC_USED(x)
+#define SYS_STATS_DISPLAY()
+#endif
+
+#if IP6_STATS
+#define IP6_STATS_INC(x) STATS_INC(x)
+#define IP6_STATS_DISPLAY() stats_display_proto(&lwip_stats.ip6, "IPv6")
+#else
+#define IP6_STATS_INC(x)
+#define IP6_STATS_DISPLAY()
+#endif
+
+#if ICMP6_STATS
+#define ICMP6_STATS_INC(x) STATS_INC(x)
+#define ICMP6_STATS_DISPLAY() stats_display_proto(&lwip_stats.icmp6, "ICMPv6")
+#else
+#define ICMP6_STATS_INC(x)
+#define ICMP6_STATS_DISPLAY()
+#endif
+
+#if IP6_FRAG_STATS
+#define IP6_FRAG_STATS_INC(x) STATS_INC(x)
+#define IP6_FRAG_STATS_DISPLAY() stats_display_proto(&lwip_stats.ip6_frag, "IPv6 FRAG")
+#else
+#define IP6_FRAG_STATS_INC(x)
+#define IP6_FRAG_STATS_DISPLAY()
+#endif
+
+#if MLD6_STATS
+#define MLD6_STATS_INC(x) STATS_INC(x)
+#define MLD6_STATS_DISPLAY() stats_display_igmp(&lwip_stats.mld6, "MLDv1")
+#else
+#define MLD6_STATS_INC(x)
+#define MLD6_STATS_DISPLAY()
+#endif
+
+#if ND6_STATS
+#define ND6_STATS_INC(x) STATS_INC(x)
+#define ND6_STATS_DISPLAY() stats_display_proto(&lwip_stats.nd6, "ND")
+#else
+#define ND6_STATS_INC(x)
+#define ND6_STATS_DISPLAY()
+#endif
+
+#if MIB2_STATS
+#define MIB2_STATS_INC(x) STATS_INC(x)
+#else
+#define MIB2_STATS_INC(x)
+#endif
+
+/* Display of statistics */
+#if LWIP_STATS_DISPLAY
+void stats_display(void);
+void stats_display_proto(struct stats_proto *proto, const char *name);
+void stats_display_igmp(struct stats_igmp *igmp, const char *name);
+void stats_display_mem(struct stats_mem *mem, const char *name);
+void stats_display_memp(struct stats_mem *mem, int index);
+void stats_display_sys(struct stats_sys *sys);
+#else /* LWIP_STATS_DISPLAY */
+#define stats_display()
+#define stats_display_proto(proto, name)
+#define stats_display_igmp(igmp, name)
+#define stats_display_mem(mem, name)
+#define stats_display_memp(mem, index)
+#define stats_display_sys(sys)
+#endif /* LWIP_STATS_DISPLAY */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_STATS_H */
diff --git a/tools/sdk/include/lwip/lwip/sys.h b/tools/sdk/include/lwip/lwip/sys.h
new file mode 100755
index 00000000..86d0f3b3
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/sys.h
@@ -0,0 +1,362 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef LWIP_HDR_SYS_H
+#define LWIP_HDR_SYS_H
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if NO_SYS
+
+/* For a totally minimal and standalone system, we provide null
+   definitions of the sys_ functions. */
+typedef u8_t sys_sem_t;
+typedef u8_t sys_mutex_t;
+typedef u8_t sys_mbox_t;
+
+#define sys_sem_new(s, c) ERR_OK
+#define sys_sem_signal(s)
+#define sys_sem_wait(s)
+#define sys_arch_sem_wait(s,t)
+#define sys_sem_free(s)
+#define sys_sem_valid(s) 0
+#define sys_sem_valid_val(s) 0
+#define sys_sem_set_invalid(s)
+#define sys_sem_set_invalid_val(s)
+#define sys_mutex_new(mu) ERR_OK
+#define sys_mutex_lock(mu)
+#define sys_mutex_unlock(mu)
+#define sys_mutex_free(mu)
+#define sys_mutex_valid(mu) 0
+#define sys_mutex_set_invalid(mu)
+#define sys_mbox_new(m, s) ERR_OK
+#define sys_mbox_fetch(m,d)
+#define sys_mbox_tryfetch(m,d)
+#define sys_mbox_post(m,d)
+#define sys_mbox_trypost(m,d)
+#define sys_mbox_free(m)
+#define sys_mbox_valid(m)
+#define sys_mbox_valid_val(m)
+#define sys_mbox_set_invalid(m)
+#define sys_mbox_set_invalid_val(m)
+
+#define sys_thread_new(n,t,a,s,p)
+
+#define sys_msleep(t)
+
+#else /* NO_SYS */
+
+/** Return code for timeouts from sys_arch_mbox_fetch and sys_arch_sem_wait */
+#define SYS_ARCH_TIMEOUT 0xffffffffUL
+
+/** sys_mbox_tryfetch() returns SYS_MBOX_EMPTY if appropriate.
+ * For now we use the same magic value, but we allow this to change in future.
+ */
+#define SYS_MBOX_EMPTY SYS_ARCH_TIMEOUT
+
+#include "lwip/err.h"
+#include "arch/sys_arch.h"
+
+/** Function prototype for thread functions */
+typedef void (*lwip_thread_fn)(void *arg);
+
+/* Function prototypes for functions to be implemented by platform ports
+   (in sys_arch.c) */
+
+/* Mutex functions: */
+
+/** Define LWIP_COMPAT_MUTEX if the port has no mutexes and binary semaphores
+    should be used instead */
+#ifndef LWIP_COMPAT_MUTEX
+#define LWIP_COMPAT_MUTEX 0
+#endif
+
+#if LWIP_COMPAT_MUTEX
+/* for old ports that don't have mutexes: define them to binary semaphores */
+#define sys_mutex_t                   sys_sem_t
+#define sys_mutex_new(mutex)          sys_sem_new(mutex, 1)
+#define sys_mutex_lock(mutex)         sys_sem_wait(mutex)
+#define sys_mutex_unlock(mutex)       sys_sem_signal(mutex)
+#define sys_mutex_free(mutex)         sys_sem_free(mutex)
+#define sys_mutex_valid(mutex)        sys_sem_valid(mutex)
+#define sys_mutex_set_invalid(mutex)  sys_sem_set_invalid(mutex)
+
+#else /* LWIP_COMPAT_MUTEX */
+
+/** Create a new mutex
+ * @param mutex pointer to the mutex to create
+ * @return a new mutex */
+err_t sys_mutex_new(sys_mutex_t *mutex);
+/** Lock a mutex
+ * @param mutex the mutex to lock */
+void sys_mutex_lock(sys_mutex_t *mutex);
+/** Unlock a mutex
+ * @param mutex the mutex to unlock */
+void sys_mutex_unlock(sys_mutex_t *mutex);
+/** Delete a semaphore
+ * @param mutex the mutex to delete */
+void sys_mutex_free(sys_mutex_t *mutex);
+#ifndef sys_mutex_valid
+/** Check if a mutex is valid/allocated: return 1 for valid, 0 for invalid */
+int sys_mutex_valid(sys_mutex_t *mutex);
+#endif
+#ifndef sys_mutex_set_invalid
+/** Set a mutex invalid so that sys_mutex_valid returns 0 */
+void sys_mutex_set_invalid(sys_mutex_t *mutex);
+#endif
+#endif /* LWIP_COMPAT_MUTEX */
+
+/* Semaphore functions: */
+
+/** Create a new semaphore
+ * @param sem pointer to the semaphore to create
+ * @param count initial count of the semaphore
+ * @return ERR_OK if successful, another err_t otherwise */
+err_t sys_sem_new(sys_sem_t *sem, u8_t count);
+/** Signals a semaphore
+ * @param sem the semaphore to signal */
+void sys_sem_signal(sys_sem_t *sem);
+/** Wait for a semaphore for the specified timeout
+ * @param sem the semaphore to wait for
+ * @param timeout timeout in milliseconds to wait (0 = wait forever)
+ * @return time (in milliseconds) waited for the semaphore
+ *         or SYS_ARCH_TIMEOUT on timeout */
+u32_t sys_arch_sem_wait(sys_sem_t *sem, u32_t timeout);
+/** Delete a semaphore
+ * @param sem semaphore to delete */
+void sys_sem_free(sys_sem_t *sem);
+/** Wait for a semaphore - forever/no timeout */
+#define sys_sem_wait(sem)                  sys_arch_sem_wait(sem, 0)
+#ifndef sys_sem_valid
+/** Check if a semaphore is valid/allocated: return 1 for valid, 0 for invalid */
+int sys_sem_valid(sys_sem_t *sem);
+#endif
+#ifndef sys_sem_set_invalid
+/** Set a semaphore invalid so that sys_sem_valid returns 0 */
+void sys_sem_set_invalid(sys_sem_t *sem);
+#endif
+#ifndef sys_sem_valid_val
+/** Same as sys_sem_valid() but taking a value, not a pointer */
+#define sys_sem_valid_val(sem)       sys_sem_valid(&(sem))
+#endif
+#ifndef sys_sem_set_invalid_val
+/** Same as sys_sem_set_invalid() but taking a value, not a pointer */
+#define sys_sem_set_invalid_val(sem) sys_sem_set_invalid(&(sem))
+#endif
+
+/* Time functions. */
+#ifndef sys_msleep
+void sys_msleep(u32_t ms); /* only has a (close to) 1 ms resolution. */
+#endif
+
+/* Mailbox functions. */
+
+/** Create a new mbox of specified size
+ * @param mbox pointer to the mbox to create
+ * @param size (minimum) number of messages in this mbox
+ * @return ERR_OK if successful, another err_t otherwise */
+err_t sys_mbox_new(sys_mbox_t *mbox, int size);
+/** Post a message to an mbox - may not fail
+ * -> blocks if full, only used from tasks not from ISR
+ * @param mbox mbox to posts the message
+ * @param msg message to post (ATTENTION: can be NULL) */
+void sys_mbox_post(sys_mbox_t *mbox, void *msg);
+/** Try to post a message to an mbox - may fail if full or ISR
+ * @param mbox mbox to posts the message
+ * @param msg message to post (ATTENTION: can be NULL) */
+err_t sys_mbox_trypost(sys_mbox_t *mbox, void *msg);
+/** Wait for a new message to arrive in the mbox
+ * @param mbox mbox to get a message from
+ * @param msg pointer where the message is stored
+ * @param timeout maximum time (in milliseconds) to wait for a message (0 = wait forever)
+ * @return time (in milliseconds) waited for a message, may be 0 if not waited
+           or SYS_ARCH_TIMEOUT on timeout
+ *         The returned time has to be accurate to prevent timer jitter! */
+u32_t sys_arch_mbox_fetch(sys_mbox_t *mbox, void **msg, u32_t timeout);
+/* Allow port to override with a macro, e.g. special timeout for sys_arch_mbox_fetch() */
+#ifndef sys_arch_mbox_tryfetch
+/** Wait for a new message to arrive in the mbox
+ * @param mbox mbox to get a message from
+ * @param msg pointer where the message is stored
+ * @return 0 (milliseconds) if a message has been received
+ *         or SYS_MBOX_EMPTY if the mailbox is empty */
+u32_t sys_arch_mbox_tryfetch(sys_mbox_t *mbox, void **msg);
+#endif
+/** For now, we map straight to sys_arch implementation. */
+#define sys_mbox_tryfetch(mbox, msg) sys_arch_mbox_tryfetch(mbox, msg)
+/** Delete an mbox
+ * @param mbox mbox to delete */
+void sys_mbox_free(sys_mbox_t *mbox);
+#define sys_mbox_fetch(mbox, msg) sys_arch_mbox_fetch(mbox, msg, 0)
+#ifndef sys_mbox_valid
+/** Check if an mbox is valid/allocated: return 1 for valid, 0 for invalid */
+int sys_mbox_valid(sys_mbox_t *mbox);
+#endif
+#ifndef sys_mbox_set_invalid
+/** Set an mbox invalid so that sys_mbox_valid returns 0 */
+void sys_mbox_set_invalid(sys_mbox_t *mbox);
+#endif
+#ifndef sys_mbox_valid_val
+/** Same as sys_mbox_valid() but taking a value, not a pointer */
+#define sys_mbox_valid_val(mbox)       sys_mbox_valid(&(mbox))
+#endif
+#ifndef sys_mbox_set_invalid_val
+/** Same as sys_mbox_set_invalid() but taking a value, not a pointer */
+#define sys_mbox_set_invalid_val(mbox) sys_mbox_set_invalid(&(mbox))
+#endif
+
+
+/** The only thread function:
+ * Creates a new thread
+ * ATTENTION: although this function returns a value, it MUST NOT FAIL (ports have to assert this!)
+ * @param name human-readable name for the thread (used for debugging purposes)
+ * @param thread thread-function
+ * @param arg parameter passed to 'thread'
+ * @param stacksize stack size in bytes for the new thread (may be ignored by ports)
+ * @param prio priority of the new thread (may be ignored by ports) */
+sys_thread_t sys_thread_new(const char *name, lwip_thread_fn thread, void *arg, int stacksize, int prio);
+
+#endif /* NO_SYS */
+
+/* sys_init() must be called before anything else. */
+void sys_init(void);
+
+#ifndef sys_jiffies
+/** Ticks/jiffies since power up. */
+u32_t sys_jiffies(void);
+#endif
+
+/** Returns the current time in milliseconds,
+ * may be the same as sys_jiffies or at least based on it. */
+u32_t sys_now(void);
+
+/* Critical Region Protection */
+/* These functions must be implemented in the sys_arch.c file.
+   In some implementations they can provide a more light-weight protection
+   mechanism than using semaphores. Otherwise semaphores can be used for
+   implementation */
+#ifndef SYS_ARCH_PROTECT
+/** SYS_LIGHTWEIGHT_PROT
+ * define SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection
+ * for certain critical regions during buffer allocation, deallocation and memory
+ * allocation and deallocation.
+ */
+#if SYS_LIGHTWEIGHT_PROT
+
+/** SYS_ARCH_DECL_PROTECT
+ * declare a protection variable. This macro will default to defining a variable of
+ * type sys_prot_t. If a particular port needs a different implementation, then
+ * this macro may be defined in sys_arch.h.
+ */
+#define SYS_ARCH_DECL_PROTECT(lev) sys_prot_t lev
+/** SYS_ARCH_PROTECT
+ * Perform a "fast" protect. This could be implemented by
+ * disabling interrupts for an embedded system or by using a semaphore or
+ * mutex. The implementation should allow calling SYS_ARCH_PROTECT when
+ * already protected. The old protection level is returned in the variable
+ * "lev". This macro will default to calling the sys_arch_protect() function
+ * which should be implemented in sys_arch.c. If a particular port needs a
+ * different implementation, then this macro may be defined in sys_arch.h
+ */
+#define SYS_ARCH_PROTECT(lev) lev = sys_arch_protect()
+/** SYS_ARCH_UNPROTECT
+ * Perform a "fast" set of the protection level to "lev". This could be
+ * implemented by setting the interrupt level to "lev" within the MACRO or by
+ * using a semaphore or mutex.  This macro will default to calling the
+ * sys_arch_unprotect() function which should be implemented in
+ * sys_arch.c. If a particular port needs a different implementation, then
+ * this macro may be defined in sys_arch.h
+ */
+#define SYS_ARCH_UNPROTECT(lev) sys_arch_unprotect(lev)
+sys_prot_t sys_arch_protect(void);
+void sys_arch_unprotect(sys_prot_t pval);
+
+#else
+
+#define SYS_ARCH_DECL_PROTECT(lev)
+#define SYS_ARCH_PROTECT(lev)
+#define SYS_ARCH_UNPROTECT(lev)
+
+#endif /* SYS_LIGHTWEIGHT_PROT */
+
+#endif /* SYS_ARCH_PROTECT */
+
+/*
+ * Macros to set/get and increase/decrease variables in a thread-safe way.
+ * Use these for accessing variable that are used from more than one thread.
+ */
+
+#ifndef SYS_ARCH_INC
+#define SYS_ARCH_INC(var, val) do { \
+                                SYS_ARCH_DECL_PROTECT(old_level); \
+                                SYS_ARCH_PROTECT(old_level); \
+                                var += val; \
+                                SYS_ARCH_UNPROTECT(old_level); \
+                              } while(0)
+#endif /* SYS_ARCH_INC */
+
+#ifndef SYS_ARCH_DEC
+#define SYS_ARCH_DEC(var, val) do { \
+                                SYS_ARCH_DECL_PROTECT(old_level); \
+                                SYS_ARCH_PROTECT(old_level); \
+                                var -= val; \
+                                SYS_ARCH_UNPROTECT(old_level); \
+                              } while(0)
+#endif /* SYS_ARCH_DEC */
+
+#ifndef SYS_ARCH_GET
+#define SYS_ARCH_GET(var, ret) do { \
+                                SYS_ARCH_DECL_PROTECT(old_level); \
+                                SYS_ARCH_PROTECT(old_level); \
+                                ret = var; \
+                                SYS_ARCH_UNPROTECT(old_level); \
+                              } while(0)
+#endif /* SYS_ARCH_GET */
+
+#ifndef SYS_ARCH_SET
+#define SYS_ARCH_SET(var, val) do { \
+                                SYS_ARCH_DECL_PROTECT(old_level); \
+                                SYS_ARCH_PROTECT(old_level); \
+                                var = val; \
+                                SYS_ARCH_UNPROTECT(old_level); \
+                              } while(0)
+#endif /* SYS_ARCH_SET */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_SYS_H */
diff --git a/tools/sdk/include/lwip/lwip/tcp.h b/tools/sdk/include/lwip/lwip/tcp.h
new file mode 100755
index 00000000..d52040f9
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/tcp.h
@@ -0,0 +1,411 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef LWIP_HDR_TCP_H
+#define LWIP_HDR_TCP_H
+
+#include "lwip/opt.h"
+
+#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/mem.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip.h"
+#include "lwip/icmp.h"
+#include "lwip/err.h"
+#include "lwip/ip6.h"
+#include "lwip/ip6_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct tcp_pcb;
+
+/** Function prototype for tcp accept callback functions. Called when a new
+ * connection can be accepted on a listening pcb.
+ *
+ * @param arg Additional argument to pass to the callback function (@see tcp_arg())
+ * @param newpcb The new connection pcb
+ * @param err An error code if there has been an error accepting.
+ *            Only return ERR_ABRT if you have called tcp_abort from within the
+ *            callback function!
+ */
+typedef err_t (*tcp_accept_fn)(void *arg, struct tcp_pcb *newpcb, err_t err);
+
+/** Function prototype for tcp receive callback functions. Called when data has
+ * been received.
+ *
+ * @param arg Additional argument to pass to the callback function (@see tcp_arg())
+ * @param tpcb The connection pcb which received data
+ * @param p The received data (or NULL when the connection has been closed!)
+ * @param err An error code if there has been an error receiving
+ *            Only return ERR_ABRT if you have called tcp_abort from within the
+ *            callback function!
+ */
+typedef err_t (*tcp_recv_fn)(void *arg, struct tcp_pcb *tpcb,
+                             struct pbuf *p, err_t err);
+
+/** Function prototype for tcp sent callback functions. Called when sent data has
+ * been acknowledged by the remote side. Use it to free corresponding resources.
+ * This also means that the pcb has now space available to send new data.
+ *
+ * @param arg Additional argument to pass to the callback function (@see tcp_arg())
+ * @param tpcb The connection pcb for which data has been acknowledged
+ * @param len The amount of bytes acknowledged
+ * @return ERR_OK: try to send some data by calling tcp_output
+ *            Only return ERR_ABRT if you have called tcp_abort from within the
+ *            callback function!
+ */
+typedef err_t (*tcp_sent_fn)(void *arg, struct tcp_pcb *tpcb,
+                              u16_t len);
+
+/** Function prototype for tcp poll callback functions. Called periodically as
+ * specified by @see tcp_poll.
+ *
+ * @param arg Additional argument to pass to the callback function (@see tcp_arg())
+ * @param tpcb tcp pcb
+ * @return ERR_OK: try to send some data by calling tcp_output
+ *            Only return ERR_ABRT if you have called tcp_abort from within the
+ *            callback function!
+ */
+typedef err_t (*tcp_poll_fn)(void *arg, struct tcp_pcb *tpcb);
+
+/** Function prototype for tcp error callback functions. Called when the pcb
+ * receives a RST or is unexpectedly closed for any other reason.
+ *
+ * @note The corresponding pcb is already freed when this callback is called!
+ *
+ * @param arg Additional argument to pass to the callback function (@see tcp_arg())
+ * @param err Error code to indicate why the pcb has been closed
+ *            ERR_ABRT: aborted through tcp_abort or by a TCP timer
+ *            ERR_RST: the connection was reset by the remote host
+ */
+typedef void  (*tcp_err_fn)(void *arg, err_t err);
+
+/** Function prototype for tcp connected callback functions. Called when a pcb
+ * is connected to the remote side after initiating a connection attempt by
+ * calling tcp_connect().
+ *
+ * @param arg Additional argument to pass to the callback function (@see tcp_arg())
+ * @param tpcb The connection pcb which is connected
+ * @param err An unused error code, always ERR_OK currently ;-) TODO!
+ *            Only return ERR_ABRT if you have called tcp_abort from within the
+ *            callback function!
+ *
+ * @note When a connection attempt fails, the error callback is currently called!
+ */
+typedef err_t (*tcp_connected_fn)(void *arg, struct tcp_pcb *tpcb, err_t err);
+
+#if LWIP_WND_SCALE
+#define RCV_WND_SCALE(pcb, wnd) (((wnd) >> (pcb)->rcv_scale))
+#define SND_WND_SCALE(pcb, wnd) (((wnd) << (pcb)->snd_scale))
+#define TCPWND16(x)             ((u16_t)LWIP_MIN((x), 0xFFFF))
+#define TCP_WND_MAX(pcb)        ((tcpwnd_size_t)(((pcb)->flags & TF_WND_SCALE) ? TCP_WND : TCPWND16(TCP_WND)))
+typedef u32_t tcpwnd_size_t;
+typedef u16_t tcpflags_t;
+#else
+#define RCV_WND_SCALE(pcb, wnd) (wnd)
+#define SND_WND_SCALE(pcb, wnd) (wnd)
+#define TCPWND16(x)             (x)
+#define TCP_WND_MAX(pcb)        TCP_WND
+typedef u16_t tcpwnd_size_t;
+typedef u8_t tcpflags_t;
+#endif
+
+enum tcp_state {
+  CLOSED      = 0,
+  LISTEN      = 1,
+  SYN_SENT    = 2,
+  SYN_RCVD    = 3,
+  ESTABLISHED = 4,
+  FIN_WAIT_1  = 5,
+  FIN_WAIT_2  = 6,
+  CLOSE_WAIT  = 7,
+  CLOSING     = 8,
+  LAST_ACK    = 9,
+  TIME_WAIT   = 10
+};
+
+#if LWIP_CALLBACK_API
+  /* Function to call when a listener has been connected.
+   * @param arg user-supplied argument (tcp_pcb.callback_arg)
+   * @param pcb a new tcp_pcb that now is connected
+   * @param err an error argument (TODO: that is current always ERR_OK?)
+   * @return ERR_OK: accept the new connection,
+   *                 any other err_t aborts the new connection
+   */
+#define DEF_ACCEPT_CALLBACK  tcp_accept_fn accept;
+#else /* LWIP_CALLBACK_API */
+#define DEF_ACCEPT_CALLBACK
+#endif /* LWIP_CALLBACK_API */
+
+/**
+ * members common to struct tcp_pcb and struct tcp_listen_pcb
+ */
+#define TCP_PCB_COMMON(type) \
+  type *next; /* for the linked list */ \
+  void *callback_arg; \
+  /* the accept callback for listen- and normal pcbs, if LWIP_CALLBACK_API */ \
+  DEF_ACCEPT_CALLBACK \
+  enum tcp_state state; /* TCP state */ \
+  u8_t prio; \
+  /* ports are in host byte order */ \
+  u16_t local_port
+
+
+/* the TCP protocol control block */
+struct tcp_pcb {
+/** common PCB members */
+  IP_PCB;
+/** protocol specific PCB members */
+  TCP_PCB_COMMON(struct tcp_pcb);
+
+  /* ports are in host byte order */
+  u16_t remote_port;
+
+  tcpflags_t flags;
+#define TF_ACK_DELAY   0x01U   /* Delayed ACK. */
+#define TF_ACK_NOW     0x02U   /* Immediate ACK. */
+#define TF_INFR        0x04U   /* In fast recovery. */
+#define TF_TIMESTAMP   0x08U   /* Timestamp option enabled */
+#define TF_RXCLOSED    0x10U   /* rx closed by tcp_shutdown */
+#define TF_FIN         0x20U   /* Connection was closed locally (FIN segment enqueued). */
+#define TF_NODELAY     0x40U   /* Disable Nagle algorithm */
+#define TF_NAGLEMEMERR 0x80U   /* nagle enabled, memerr, try to output to prevent delayed ACK to happen */
+#if LWIP_WND_SCALE
+#define TF_WND_SCALE   0x0100U /* Window Scale option enabled */
+#endif
+
+  /* the rest of the fields are in host byte order
+     as we have to do some math with them */
+
+  /* Timers */
+  u8_t polltmr, pollinterval;
+  u8_t last_timer;
+  u32_t tmr;
+
+  /* receiver variables */
+  u32_t rcv_nxt;   /* next seqno expected */
+  tcpwnd_size_t rcv_wnd;   /* receiver window available */
+  tcpwnd_size_t rcv_ann_wnd; /* receiver window to announce */
+  u32_t rcv_ann_right_edge; /* announced right edge of window */
+
+  /* Retransmission timer. */
+  s16_t rtime;
+
+  u16_t mss;   /* maximum segment size */
+
+  /* RTT (round trip time) estimation variables */
+  u32_t rttest; /* RTT estimate in 500ms ticks */
+  u32_t rtseq;  /* sequence number being timed */
+  s16_t sa, sv; /* @todo document this */
+
+  s16_t rto;    /* retransmission time-out */
+  u8_t nrtx;    /* number of retransmissions */
+
+  /* fast retransmit/recovery */
+  u8_t dupacks;
+  u32_t lastack; /* Highest acknowledged seqno. */
+
+  /* congestion avoidance/control variables */
+  tcpwnd_size_t cwnd;
+  tcpwnd_size_t ssthresh;
+
+  /* sender variables */
+  u32_t snd_nxt;   /* next new seqno to be sent */
+  u32_t snd_wl1, snd_wl2; /* Sequence and acknowledgement numbers of last
+                             window update. */
+  u32_t snd_lbb;       /* Sequence number of next byte to be buffered. */
+  tcpwnd_size_t snd_wnd;   /* sender window */
+  tcpwnd_size_t snd_wnd_max; /* the maximum sender window announced by the remote host */
+
+  tcpwnd_size_t acked;
+
+  tcpwnd_size_t snd_buf;   /* Available buffer space for sending (in bytes). */
+#define TCP_SNDQUEUELEN_OVERFLOW (0xffffU-3)
+  u16_t snd_queuelen; /* Number of pbufs currently in the send buffer. */
+
+#if TCP_OVERSIZE
+  /* Extra bytes available at the end of the last pbuf in unsent. */
+  u16_t unsent_oversize;
+#endif /* TCP_OVERSIZE */
+
+  /* These are ordered by sequence number: */
+  struct tcp_seg *unsent;   /* Unsent (queued) segments. */
+  struct tcp_seg *unacked;  /* Sent but unacknowledged segments. */
+#if TCP_QUEUE_OOSEQ
+  struct tcp_seg *ooseq;    /* Received out of sequence segments. */
+#endif /* TCP_QUEUE_OOSEQ */
+
+  struct pbuf *refused_data; /* Data previously received but not yet taken by upper layer */
+
+#if LWIP_CALLBACK_API
+  /* Function to be called when more send buffer space is available. */
+  tcp_sent_fn sent;
+  /* Function to be called when (in-sequence) data has arrived. */
+  tcp_recv_fn recv;
+  /* Function to be called when a connection has been set up. */
+  tcp_connected_fn connected;
+  /* Function which is called periodically. */
+  tcp_poll_fn poll;
+  /* Function to be called whenever a fatal error occurs. */
+  tcp_err_fn errf;
+#endif /* LWIP_CALLBACK_API */
+
+#if LWIP_TCP_TIMESTAMPS
+  u32_t ts_lastacksent;
+  u32_t ts_recent;
+#endif /* LWIP_TCP_TIMESTAMPS */
+
+  /* idle time before KEEPALIVE is sent */
+  u32_t keep_idle;
+#if LWIP_TCP_KEEPALIVE
+  u32_t keep_intvl;
+  u32_t keep_cnt;
+#endif /* LWIP_TCP_KEEPALIVE */
+
+  /* Persist timer counter */
+  u8_t persist_cnt;
+  /* Persist timer back-off */
+  u8_t persist_backoff;
+
+  /* KEEPALIVE counter */
+  u8_t keep_cnt_sent;
+
+#if LWIP_WND_SCALE
+  u8_t snd_scale;
+  u8_t rcv_scale;
+#endif
+};
+
+struct tcp_pcb_listen {
+/* Common members of all PCB types */
+  IP_PCB;
+/* Protocol specific PCB members */
+  TCP_PCB_COMMON(struct tcp_pcb_listen);
+
+#if TCP_LISTEN_BACKLOG
+  u8_t backlog;
+  u8_t accepts_pending;
+#endif /* TCP_LISTEN_BACKLOG */
+};
+
+#if LWIP_EVENT_API
+
+enum lwip_event {
+  LWIP_EVENT_ACCEPT,
+  LWIP_EVENT_SENT,
+  LWIP_EVENT_RECV,
+  LWIP_EVENT_CONNECTED,
+  LWIP_EVENT_POLL,
+  LWIP_EVENT_ERR
+};
+
+err_t lwip_tcp_event(void *arg, struct tcp_pcb *pcb,
+         enum lwip_event,
+         struct pbuf *p,
+         u16_t size,
+         err_t err);
+
+#endif /* LWIP_EVENT_API */
+
+/* Application program's interface: */
+struct tcp_pcb * tcp_new     (void);
+struct tcp_pcb * tcp_new_ip_type (u8_t type);
+
+void             tcp_arg     (struct tcp_pcb *pcb, void *arg);
+void             tcp_accept  (struct tcp_pcb *pcb, tcp_accept_fn accept);
+void             tcp_recv    (struct tcp_pcb *pcb, tcp_recv_fn recv);
+void             tcp_sent    (struct tcp_pcb *pcb, tcp_sent_fn sent);
+void             tcp_poll    (struct tcp_pcb *pcb, tcp_poll_fn poll, u8_t interval);
+void             tcp_err     (struct tcp_pcb *pcb, tcp_err_fn err);
+
+#define          tcp_mss(pcb)             (((pcb)->flags & TF_TIMESTAMP) ? ((pcb)->mss - 12)  : (pcb)->mss)
+#define          tcp_sndbuf(pcb)          (TCPWND16((pcb)->snd_buf))
+#define          tcp_sndqueuelen(pcb)     ((pcb)->snd_queuelen)
+#define          tcp_nagle_disable(pcb)   ((pcb)->flags |= TF_NODELAY)
+#define          tcp_nagle_enable(pcb)    ((pcb)->flags = (tcpflags_t)((pcb)->flags & ~TF_NODELAY))
+#define          tcp_nagle_disabled(pcb)  (((pcb)->flags & TF_NODELAY) != 0)
+
+#if TCP_LISTEN_BACKLOG
+#define          tcp_accepted(pcb) do { \
+  LWIP_ASSERT("pcb->state == LISTEN (called for wrong pcb?)", pcb->state == LISTEN); \
+  (((struct tcp_pcb_listen *)(pcb))->accepts_pending--); } while(0)
+#define          tcp_backlog_set(pcb, new_backlog) do { \
+  LWIP_ASSERT("pcb->state == LISTEN (called for wrong pcb?)", (pcb)->state == LISTEN); \
+  ((struct tcp_pcb_listen *)(pcb))->backlog = ((new_backlog) ? (new_backlog) : 1); } while(0)
+#else  /* TCP_LISTEN_BACKLOG */
+#define          tcp_accepted(pcb) LWIP_ASSERT("pcb->state == LISTEN (called for wrong pcb?)", \
+                                               (pcb)->state == LISTEN)
+#endif /* TCP_LISTEN_BACKLOG */
+
+void             tcp_recved  (struct tcp_pcb *pcb, u16_t len);
+err_t            tcp_bind    (struct tcp_pcb *pcb, const ip_addr_t *ipaddr,
+                              u16_t port);
+err_t            tcp_connect (struct tcp_pcb *pcb, const ip_addr_t *ipaddr,
+                              u16_t port, tcp_connected_fn connected);
+
+struct tcp_pcb * tcp_listen_with_backlog(struct tcp_pcb *pcb, u8_t backlog);
+#define          tcp_listen(pcb) tcp_listen_with_backlog(pcb, TCP_DEFAULT_LISTEN_BACKLOG)
+
+void             tcp_abort (struct tcp_pcb *pcb);
+err_t            tcp_close   (struct tcp_pcb *pcb);
+err_t            tcp_shutdown(struct tcp_pcb *pcb, int shut_rx, int shut_tx);
+
+/* Flags for "apiflags" parameter in tcp_write */
+#define TCP_WRITE_FLAG_COPY 0x01
+#define TCP_WRITE_FLAG_MORE 0x02
+
+err_t            tcp_write   (struct tcp_pcb *pcb, const void *dataptr, u16_t len,
+                              u8_t apiflags);
+
+void             tcp_setprio (struct tcp_pcb *pcb, u8_t prio);
+
+#define TCP_PRIO_MIN    1
+#define TCP_PRIO_NORMAL 64
+#define TCP_PRIO_MAX    127
+
+err_t            tcp_output  (struct tcp_pcb *pcb);
+
+
+const char* tcp_debug_state_str(enum tcp_state s);
+
+/* for compatibility with older implementation */
+#define tcp_new_ip6() tcp_new_ip_type(IPADDR_TYPE_V6)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_TCP */
+
+#endif /* LWIP_HDR_TCP_H */
diff --git a/tools/sdk/include/lwip/lwip/tcpip.h b/tools/sdk/include/lwip/lwip/tcpip.h
new file mode 100755
index 00000000..c1235865
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/tcpip.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef LWIP_HDR_TCPIP_H
+#define LWIP_HDR_TCPIP_H
+
+#include "lwip/opt.h"
+
+#if !NO_SYS /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/err.h"
+#include "lwip/timers.h"
+#include "lwip/netif.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct pbuf;
+struct netif;
+
+/** Function prototype for the init_done function passed to tcpip_init */
+typedef void (*tcpip_init_done_fn)(void *arg);
+/** Function prototype for functions passed to tcpip_callback() */
+typedef void (*tcpip_callback_fn)(void *ctx);
+
+/* Forward declarations */
+struct tcpip_callback_msg;
+
+void   tcpip_init(tcpip_init_done_fn tcpip_init_done, void *arg);
+
+err_t  tcpip_inpkt(struct pbuf *p, struct netif *inp, netif_input_fn input_fn);
+err_t  tcpip_input(struct pbuf *p, struct netif *inp);
+
+err_t  tcpip_callback_with_block(tcpip_callback_fn function, void *ctx, u8_t block);
+#define tcpip_callback(f, ctx)  tcpip_callback_with_block(f, ctx, 1)
+
+struct tcpip_callback_msg* tcpip_callbackmsg_new(tcpip_callback_fn function, void *ctx);
+void   tcpip_callbackmsg_delete(struct tcpip_callback_msg* msg);
+err_t  tcpip_trycallback(struct tcpip_callback_msg* msg);
+
+/* free pbufs or heap memory from another context without blocking */
+err_t  pbuf_free_callback(struct pbuf *p);
+err_t  mem_free_callback(void *m);
+
+#if LWIP_TCPIP_TIMEOUT
+err_t  tcpip_timeout(u32_t msecs, sys_timeout_handler h, void *arg);
+err_t  tcpip_untimeout(sys_timeout_handler h, void *arg);
+#endif /* LWIP_TCPIP_TIMEOUT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !NO_SYS */
+
+#endif /* LWIP_HDR_TCPIP_H */
diff --git a/tools/sdk/include/lwip/lwip/timers.h b/tools/sdk/include/lwip/lwip/timers.h
new file mode 100755
index 00000000..d735392d
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/timers.h
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *         Simon Goldschmidt
+ *
+ */
+#ifndef LWIP_HDR_TIMERS_H
+#define LWIP_HDR_TIMERS_H
+
+#include "lwip/opt.h"
+
+/* Timers are not supported when NO_SYS==1 and NO_SYS_NO_TIMERS==1 */
+#define LWIP_TIMERS (!NO_SYS || (NO_SYS && !NO_SYS_NO_TIMERS))
+
+#if LWIP_TIMERS
+
+#include "lwip/err.h"
+#if !NO_SYS
+#include "lwip/sys.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef LWIP_DEBUG_TIMERNAMES
+#ifdef LWIP_DEBUG
+#define LWIP_DEBUG_TIMERNAMES SYS_DEBUG
+#else /* LWIP_DEBUG */
+#define LWIP_DEBUG_TIMERNAMES 0
+#endif /* LWIP_DEBUG*/
+#endif
+
+/** Function prototype for a timeout callback function. Register such a function
+ * using sys_timeout().
+ *
+ * @param arg Additional argument to pass to the function - set up by sys_timeout()
+ */
+typedef void (* sys_timeout_handler)(void *arg);
+
+struct sys_timeo {
+  struct sys_timeo *next;
+  u32_t time;
+  sys_timeout_handler h;
+  void *arg;
+#if LWIP_DEBUG_TIMERNAMES
+  const char* handler_name;
+#endif /* LWIP_DEBUG_TIMERNAMES */
+};
+
+void sys_timeouts_init(void);
+
+#if LWIP_DEBUG_TIMERNAMES
+void sys_timeout_debug(u32_t msecs, sys_timeout_handler handler, void *arg, const char* handler_name);
+#define sys_timeout(msecs, handler, arg) sys_timeout_debug(msecs, handler, arg, #handler)
+#else /* LWIP_DEBUG_TIMERNAMES */
+void sys_timeout(u32_t msecs, sys_timeout_handler handler, void *arg);
+#endif /* LWIP_DEBUG_TIMERNAMES */
+
+void sys_untimeout(sys_timeout_handler handler, void *arg);
+#if NO_SYS
+void sys_check_timeouts(void);
+void sys_restart_timeouts(void);
+u32_t sys_timeouts_sleeptime(void);
+#else /* NO_SYS */
+void sys_timeouts_mbox_fetch(sys_mbox_t *mbox, void **msg);
+#endif /* NO_SYS */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_TIMERS */
+#endif /* LWIP_HDR_TIMERS_H */
diff --git a/tools/sdk/include/lwip/lwip/udp.h b/tools/sdk/include/lwip/lwip/udp.h
new file mode 100755
index 00000000..a370d3f9
--- /dev/null
+++ b/tools/sdk/include/lwip/lwip/udp.h
@@ -0,0 +1,194 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef LWIP_HDR_UDP_H
+#define LWIP_HDR_UDP_H
+
+#include "lwip/opt.h"
+
+#if LWIP_UDP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/pbuf.h"
+#include "lwip/netif.h"
+#include "lwip/ip_addr.h"
+#include "lwip/ip.h"
+#include "lwip/ip6_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define UDP_HLEN 8
+
+/* Fields are (of course) in network byte order. */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct udp_hdr {
+  PACK_STRUCT_FIELD(u16_t src);
+  PACK_STRUCT_FIELD(u16_t dest);  /* src/dest UDP ports */
+  PACK_STRUCT_FIELD(u16_t len);
+  PACK_STRUCT_FIELD(u16_t chksum);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define UDP_FLAGS_NOCHKSUM       0x01U
+#define UDP_FLAGS_UDPLITE        0x02U
+#define UDP_FLAGS_CONNECTED      0x04U
+#define UDP_FLAGS_MULTICAST_LOOP 0x08U
+
+struct udp_pcb;
+
+/** Function prototype for udp pcb receive callback functions
+ * addr and port are in same byte order as in the pcb
+ * The callback is responsible for freeing the pbuf
+ * if it's not used any more.
+ *
+ * ATTENTION: Be aware that 'addr' might point into the pbuf 'p' so freeing this pbuf
+ *            can make 'addr' invalid, too.
+ *
+ * @param arg user supplied argument (udp_pcb.recv_arg)
+ * @param pcb the udp_pcb which received data
+ * @param p the packet buffer that was received
+ * @param addr the remote IP address from which the packet was received
+ * @param port the remote port from which the packet was received
+ */
+typedef void (*udp_recv_fn)(void *arg, struct udp_pcb *pcb, struct pbuf *p,
+    const ip_addr_t *addr, u16_t port);
+
+struct udp_pcb {
+/* Common members of all PCB types */
+  IP_PCB;
+
+/* Protocol specific PCB members */
+
+  struct udp_pcb *next;
+
+  u8_t flags;
+  /** ports are in host byte order */
+  u16_t local_port, remote_port;
+
+#if LWIP_MULTICAST_TX_OPTIONS
+  /** outgoing network interface for multicast packets */
+  ip_addr_t multicast_ip;
+  /** TTL for outgoing multicast packets */
+  u8_t mcast_ttl;
+#endif /* LWIP_MULTICAST_TX_OPTIONS */
+
+#if LWIP_UDPLITE
+  /** used for UDP_LITE only */
+  u16_t chksum_len_rx, chksum_len_tx;
+#endif /* LWIP_UDPLITE */
+
+  /** receive callback function */
+  udp_recv_fn recv;
+  /** user-supplied argument for the recv callback */
+  void *recv_arg;
+};
+/* udp_pcbs export for external reference (e.g. SNMP agent) */
+extern struct udp_pcb *udp_pcbs;
+
+/* The following functions is the application layer interface to the
+   UDP code. */
+struct udp_pcb * udp_new        (void);
+struct udp_pcb * udp_new_ip_type(u8_t type);
+void             udp_remove     (struct udp_pcb *pcb);
+err_t            udp_bind       (struct udp_pcb *pcb, const ip_addr_t *ipaddr,
+                                 u16_t port);
+err_t            udp_connect    (struct udp_pcb *pcb, const ip_addr_t *ipaddr,
+                                 u16_t port);
+void             udp_disconnect (struct udp_pcb *pcb);
+void             udp_recv       (struct udp_pcb *pcb, udp_recv_fn recv,
+                                 void *recv_arg);
+err_t            udp_sendto_if  (struct udp_pcb *pcb, struct pbuf *p,
+                                 const ip_addr_t *dst_ip, u16_t dst_port,
+                                 struct netif *netif);
+err_t            udp_sendto_if_src(struct udp_pcb *pcb, struct pbuf *p,
+                                 const ip_addr_t *dst_ip, u16_t dst_port,
+                                 struct netif *netif, const ip_addr_t *src_ip);
+err_t            udp_sendto     (struct udp_pcb *pcb, struct pbuf *p,
+                                 const ip_addr_t *dst_ip, u16_t dst_port);
+err_t            udp_send       (struct udp_pcb *pcb, struct pbuf *p);
+
+#if LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP
+err_t            udp_sendto_if_chksum(struct udp_pcb *pcb, struct pbuf *p,
+                                 const ip_addr_t *dst_ip, u16_t dst_port,
+                                 struct netif *netif, u8_t have_chksum,
+                                 u16_t chksum);
+err_t            udp_sendto_chksum(struct udp_pcb *pcb, struct pbuf *p,
+                                 const ip_addr_t *dst_ip, u16_t dst_port,
+                                 u8_t have_chksum, u16_t chksum);
+err_t            udp_send_chksum(struct udp_pcb *pcb, struct pbuf *p,
+                                 u8_t have_chksum, u16_t chksum);
+err_t            udp_sendto_if_src_chksum(struct udp_pcb *pcb, struct pbuf *p,
+                                 const ip_addr_t *dst_ip, u16_t dst_port, struct netif *netif,
+                                 u8_t have_chksum, u16_t chksum, const ip_addr_t *src_ip);
+#endif /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */
+
+#define          udp_flags(pcb) ((pcb)->flags)
+#define          udp_setflags(pcb, f)  ((pcb)->flags = (f))
+
+/* The following functions are the lower layer interface to UDP. */
+void             udp_input      (struct pbuf *p, struct netif *inp);
+
+void             udp_init       (void);
+
+/* for compatibility with older implementation */
+#define udp_new_ip6() udp_new_ip_type(IPADDR_TYPE_V6)
+
+#if LWIP_MULTICAST_TX_OPTIONS
+#define udp_set_multicast_netif_addr(pcb, ip4addr) ip_addr_copy_from_ip4((pcb)->multicast_ip, *(ip4addr))
+#define udp_get_multicast_netif_addr(pcb)          ip_2_ip4(&(pcb)->multicast_ip)
+#define udp_set_multicast_ttl(pcb, value)      do { (pcb)->mcast_ttl = value; } while(0)
+#define udp_get_multicast_ttl(pcb)                 ((pcb)->mcast_ttl)
+#endif /* LWIP_MULTICAST_TX_OPTIONS */
+
+#if UDP_DEBUG
+void udp_debug_print(struct udp_hdr *udphdr);
+#else
+#define udp_debug_print(udphdr)
+#endif
+
+#if LWIP_IPV4
+void udp_netif_ipv4_addr_changed(const ip4_addr_t* old_addr, const ip4_addr_t* new_addr);
+#endif /* LWIP_IPV4 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_UDP */
+
+#endif /* LWIP_HDR_UDP_H */
diff --git a/tools/sdk/include/lwip/lwipopts.h b/tools/sdk/include/lwip/lwipopts.h
new file mode 100755
index 00000000..29506c0b
--- /dev/null
+++ b/tools/sdk/include/lwip/lwipopts.h
@@ -0,0 +1,531 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Simon Goldschmidt
+ *
+ */
+#ifndef __LWIPOPTS_H__
+#define __LWIPOPTS_H__
+
+#include 
+#include "esp_task.h"
+#include "sdkconfig.h"
+
+/* Enable all Espressif-only options */
+#define LWIP_ESP8266
+
+/*
+   -----------------------------------------------
+   ---------- Platform specific locking ----------
+   -----------------------------------------------
+*/
+/**
+ * SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain
+ * critical regions during buffer allocation, deallocation and memory
+ * allocation and deallocation.
+ */
+#define SYS_LIGHTWEIGHT_PROT        1
+
+/**
+ * MEMCPY: override this if you have a faster implementation at hand than the
+ * one included in your C library
+ */
+#define MEMCPY(dst,src,len)             memcpy(dst,src,len)
+
+/**
+ * SMEMCPY: override this with care! Some compilers (e.g. gcc) can inline a
+ * call to memcpy() if the length is known at compile time and is small.
+ */
+#define SMEMCPY(dst,src,len)            memcpy(dst,src,len)
+
+extern unsigned long os_random(void);
+#define LWIP_RAND	rand
+/*
+   ------------------------------------
+   ---------- Memory options ----------
+   ------------------------------------
+*/
+/**
+ * MEM_LIBC_MALLOC==1: Use malloc/free/realloc provided by your C-library
+ * instead of the lwip internal allocator. Can save code size if you
+ * already use it.
+ */
+#define MEM_LIBC_MALLOC        1
+
+/**
+* MEMP_MEM_MALLOC==1: Use mem_malloc/mem_free instead of the lwip pool allocator.
+* Especially useful with MEM_LIBC_MALLOC but handle with care regarding execution
+* speed and usage from interrupts!
+*/
+#define MEMP_MEM_MALLOC                 1
+
+/**
+ * MEM_ALIGNMENT: should be set to the alignment of the CPU
+ *    4 byte alignment -> #define MEM_ALIGNMENT 4
+ *    2 byte alignment -> #define MEM_ALIGNMENT 2
+ */
+#define MEM_ALIGNMENT           4
+
+/*
+   ------------------------------------------------
+   ---------- Internal Memory Pool Sizes ----------
+   ------------------------------------------------
+*/
+/**
+ * MEMP_NUM_TCP_PCB: the number of simulatenously active TCP connections.
+ * (requires the LWIP_TCP option)
+ */
+#define MEMP_NUM_TCP_PCB                5
+
+/**
+ * MEMP_NUM_NETCONN: the number of struct netconns.
+ * (only needed if you use the sequential API, like api_lib.c)
+ */
+#define MEMP_NUM_NETCONN                10
+
+/*
+   --------------------------------
+   ---------- ARP options -------
+   --------------------------------
+*/
+/**
+ * ARP_QUEUEING==1: Multiple outgoing packets are queued during hardware address
+ * resolution. By default, only the most recent packet is queued per IP address.
+ * This is sufficient for most protocols and mainly reduces TCP connection
+ * startup time. Set this to 1 if you know your application sends more than one
+ * packet in a row to an IP address that is not in the ARP cache.
+ */
+#define ARP_QUEUEING                    1
+
+/*
+   --------------------------------
+   ---------- IP options ----------
+   --------------------------------
+*/
+/**
+ * IP_REASSEMBLY==1: Reassemble incoming fragmented IP packets. Note that
+ * this option does not affect outgoing packet sizes, which can be controlled
+ * via IP_FRAG.
+ */
+#define IP_REASSEMBLY                   0
+
+/**
+ * IP_FRAG==1: Fragment outgoing IP packets if their size exceeds MTU. Note
+ * that this option does not affect incoming packet sizes, which can be
+ * controlled via IP_REASSEMBLY.
+ */
+#define IP_FRAG                         0
+
+/**
+ * IP_REASS_MAXAGE: Maximum time (in multiples of IP_TMR_INTERVAL - so seconds, normally)
+ * a fragmented IP packet waits for all fragments to arrive. If not all fragments arrived
+ * in this time, the whole packet is discarded.
+ */
+#define IP_REASS_MAXAGE                 3
+
+/**
+ * IP_REASS_MAX_PBUFS: Total maximum amount of pbufs waiting to be reassembled.
+ * Since the received pbufs are enqueued, be sure to configure
+ * PBUF_POOL_SIZE > IP_REASS_MAX_PBUFS so that the stack is still able to receive
+ * packets even if the maximum amount of fragments is enqueued for reassembly!
+ */
+#define IP_REASS_MAX_PBUFS              10
+
+/*
+   ----------------------------------
+   ---------- ICMP options ----------
+   ----------------------------------
+*/
+
+/*
+   ---------------------------------
+   ---------- RAW options ----------
+   ---------------------------------
+*/
+
+/*
+   ----------------------------------
+   ---------- DHCP options ----------
+   ----------------------------------
+*/
+/**
+ * LWIP_DHCP==1: Enable DHCP module.
+ */
+#define LWIP_DHCP                       1
+
+
+#define DHCP_MAXRTX						0   //(*(volatile uint32*)0x600011E0)
+/*
+   ------------------------------------
+   ---------- AUTOIP options ----------
+   ------------------------------------
+*/
+/*
+   ----------------------------------
+   ---------- SNMP options ----------
+   ----------------------------------
+*/
+/*
+   ----------------------------------
+   ---------- IGMP options ----------
+   ----------------------------------
+*/
+/**
+ * LWIP_IGMP==1: Turn on IGMP module.
+ */
+#define LWIP_IGMP                       1
+
+/*
+   ----------------------------------
+   ---------- DNS options -----------
+   ----------------------------------
+*/
+/**
+ * LWIP_DNS==1: Turn on DNS module. UDP must be available for DNS
+ * transport.
+ */
+#define LWIP_DNS                        1
+
+/*
+   ---------------------------------
+   ---------- UDP options ----------
+   ---------------------------------
+*/
+/*
+   ---------------------------------
+   ---------- TCP options ----------
+   ---------------------------------
+*/
+/**
+ * TCP_WND: The size of a TCP window.  This must be at least
+ * (2 * TCP_MSS) for things to work well
+ */
+#define PERF 1
+#ifdef PERF
+extern unsigned char misc_prof_get_tcpw(void);
+extern unsigned char misc_prof_get_tcp_snd_buf(void);
+#define TCP_WND                         (misc_prof_get_tcpw()*TCP_MSS)
+#define TCP_SND_BUF                     (misc_prof_get_tcp_snd_buf()*TCP_MSS)
+
+#else
+
+#define TCP_WND                         (4 * TCP_MSS)
+#define TCP_SND_BUF                     (2 * TCP_MSS)
+
+#endif
+
+
+/**
+ * TCP_QUEUE_OOSEQ==1: TCP will queue segments that arrive out of order.
+ * Define to 0 if your device is low on memory.
+ */
+#define TCP_QUEUE_OOSEQ                 1
+
+/*
+ *     LWIP_EVENT_API==1: The user defines lwip_tcp_event() to receive all
+ *         events (accept, sent, etc) that happen in the system.
+ *     LWIP_CALLBACK_API==1: The PCB callback function is called directly
+ *         for the event. This is the default.
+*/
+#define TCP_MSS                         1460
+
+/**
+ * TCP_MAXRTX: Maximum number of retransmissions of data segments.
+ */
+#define TCP_MAXRTX                      12  //(*(volatile uint32*)0x600011E8)
+
+/**
+ * TCP_SYNMAXRTX: Maximum number of retransmissions of SYN segments.
+ */
+#define TCP_SYNMAXRTX                   6   //(*(volatile uint32*)0x600011E4)
+
+/**
+ * TCP_LISTEN_BACKLOG: Enable the backlog option for tcp listen pcb.
+ */
+#define TCP_LISTEN_BACKLOG              1
+
+/*
+   ----------------------------------
+   ---------- Pbuf options ----------
+   ----------------------------------
+*/
+
+/*
+   ------------------------------------------------
+   ---------- Network Interfaces options ----------
+   ------------------------------------------------
+*/
+
+/**
+ * LWIP_NETIF_HOSTNAME==1: use DHCP_OPTION_HOSTNAME with netif's hostname
+ * field.
+ */
+#define LWIP_NETIF_HOSTNAME             1
+
+/**
+ * LWIP_NETIF_TX_SINGLE_PBUF: if this is set to 1, lwIP tries to put all data
+ * to be sent into one single pbuf. This is for compatibility with DMA-enabled
+ * MACs that do not support scatter-gather.
+ * Beware that this might involve CPU-memcpy before transmitting that would not
+ * be needed without this flag! Use this only if you need to!
+ *
+ * @todo: TCP and IP-frag do not work with this, yet:
+ */
+#define LWIP_NETIF_TX_SINGLE_PBUF             1
+
+/*
+   ------------------------------------
+   ---------- LOOPIF options ----------
+   ------------------------------------
+*/
+
+/*
+   ------------------------------------
+   ---------- SLIPIF options ----------
+   ------------------------------------
+*/
+
+/*
+   ------------------------------------
+   ---------- Thread options ----------
+   ------------------------------------
+*/
+/**
+ * TCPIP_THREAD_NAME: The name assigned to the main tcpip thread.
+ */
+#define TCPIP_THREAD_NAME              "tiT"
+
+/**
+ * TCPIP_THREAD_STACKSIZE: The stack size used by the main tcpip thread.
+ * The stack size value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#define TCPIP_THREAD_STACKSIZE          ESP_TASK_TCPIP_STACK
+
+/**
+ * TCPIP_THREAD_PRIO: The priority assigned to the main tcpip thread.
+ * The priority value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#define TCPIP_THREAD_PRIO               ESP_TASK_TCPIP_PRIO
+
+/**
+ * TCPIP_MBOX_SIZE: The mailbox size for the tcpip thread messages
+ * The queue size value itself is platform-dependent, but is passed to
+ * sys_mbox_new() when tcpip_init is called.
+ */
+#define TCPIP_MBOX_SIZE                 16
+
+/**
+ * DEFAULT_UDP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
+ * NETCONN_UDP. The queue size value itself is platform-dependent, but is passed
+ * to sys_mbox_new() when the recvmbox is created.
+ */
+#define DEFAULT_UDP_RECVMBOX_SIZE       16
+
+/**
+ * DEFAULT_TCP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
+ * NETCONN_TCP. The queue size value itself is platform-dependent, but is passed
+ * to sys_mbox_new() when the recvmbox is created.
+ */
+#define DEFAULT_TCP_RECVMBOX_SIZE       16
+//#define DEFAULT_TCP_RECVMBOX_SIZE       6
+
+/**
+ * DEFAULT_ACCEPTMBOX_SIZE: The mailbox size for the incoming connections.
+ * The queue size value itself is platform-dependent, but is passed to
+ * sys_mbox_new() when the acceptmbox is created.
+ */
+#define DEFAULT_ACCEPTMBOX_SIZE         6
+
+/*
+   ----------------------------------------------
+   ---------- Sequential layer options ----------
+   ----------------------------------------------
+*/
+/**
+ * LWIP_TCPIP_CORE_LOCKING: (EXPERIMENTAL!)
+ * Don't use it if you're not an active lwIP project member
+ */
+#define LWIP_TCPIP_CORE_LOCKING         0
+
+/*
+   ------------------------------------
+   ---------- Socket options ----------
+   ------------------------------------
+*/
+/**
+ * LWIP_SO_SNDTIMEO==1: Enable send timeout for sockets/netconns and
+ * SO_SNDTIMEO processing.
+ */
+#define LWIP_SO_SNDTIMEO                1
+
+/**
+ * LWIP_SO_RCVTIMEO==1: Enable receive timeout for sockets/netconns and
+ * SO_RCVTIMEO processing.
+ */
+#define LWIP_SO_RCVTIMEO                1
+
+/**
+ * LWIP_TCP_KEEPALIVE==1: Enable TCP_KEEPIDLE, TCP_KEEPINTVL and TCP_KEEPCNT
+ * options processing. Note that TCP_KEEPIDLE and TCP_KEEPINTVL have to be set
+ * in seconds. (does not require sockets.c, and will affect tcp.c)
+ */
+#define LWIP_TCP_KEEPALIVE              1
+
+/**
+ * LWIP_SO_RCVBUF==1: Enable SO_RCVBUF processing.
+ */
+#define LWIP_SO_RCVBUF                  1
+
+/**
+ * SO_REUSE==1: Enable SO_REUSEADDR option.
+ * This option is set via menuconfig.
+ */
+#define SO_REUSE                        CONFIG_LWIP_SO_REUSE
+
+/*
+   ----------------------------------------
+   ---------- Statistics options ----------
+   ----------------------------------------
+*/
+/**
+ * LWIP_STATS==1: Enable statistics collection in lwip_stats.
+ */
+#define LWIP_STATS                      0
+
+/*
+   ---------------------------------
+   ---------- PPP options ----------
+   ---------------------------------
+*/
+
+/*
+   --------------------------------------
+   ---------- Checksum options ----------
+   --------------------------------------
+*/
+
+/*
+   ---------------------------------------
+   ---------- IPv6 options ---------------
+   ---------------------------------------
+*/
+/**
+ * LWIP_IPV6==1: Enable IPv6
+ */
+#define LWIP_IPV6                       1
+
+/*
+   ---------------------------------------
+   ---------- Hook options ---------------
+   ---------------------------------------
+*/
+
+/*
+   ---------------------------------------
+   ---------- Debugging options ----------
+   ---------------------------------------
+*/
+/**
+ * ETHARP_DEBUG: Enable debugging in etharp.c.
+ */
+#define ETHARP_DEBUG                    LWIP_DBG_OFF
+
+/**
+ * NETIF_DEBUG: Enable debugging in netif.c.
+ */
+#define NETIF_DEBUG                     LWIP_DBG_OFF
+
+/**
+ * PBUF_DEBUG: Enable debugging in pbuf.c.
+ */
+#define PBUF_DEBUG                      LWIP_DBG_OFF
+
+/**
+ * API_LIB_DEBUG: Enable debugging in api_lib.c.
+ */
+#define API_LIB_DEBUG                   LWIP_DBG_OFF
+
+/**
+ * SOCKETS_DEBUG: Enable debugging in sockets.c.
+ */
+#define SOCKETS_DEBUG                   LWIP_DBG_OFF
+
+/**
+ * ICMP_DEBUG: Enable debugging in icmp.c.
+ */
+#define ICMP_DEBUG                      LWIP_DBG_OFF
+
+/**
+ * IP_DEBUG: Enable debugging for IP.
+ */
+#define IP_DEBUG                        LWIP_DBG_OFF
+
+/**
+ * MEMP_DEBUG: Enable debugging in memp.c.
+ */
+#define MEMP_DEBUG                      LWIP_DBG_OFF
+
+/**
+ * TCP_INPUT_DEBUG: Enable debugging in tcp_in.c for incoming debug.
+ */
+#define TCP_INPUT_DEBUG                 LWIP_DBG_OFF
+
+/**
+ * TCP_OUTPUT_DEBUG: Enable debugging in tcp_out.c output functions.
+ */
+#define TCP_OUTPUT_DEBUG                LWIP_DBG_OFF
+
+/**
+ * TCPIP_DEBUG: Enable debugging in tcpip.c.
+ */
+#define TCPIP_DEBUG                     LWIP_DBG_OFF
+
+/**
+ * DHCP_DEBUG: Enable debugging in dhcp.c.
+ */
+#define DHCP_DEBUG                      LWIP_DBG_OFF
+#define LWIP_DEBUG                      0
+#define TCP_DEBUG                       LWIP_DBG_OFF
+#define THREAD_SAFE_DEBUG               LWIP_DBG_OFF
+#define LWIP_THREAD_SAFE                1
+
+#define CHECKSUM_CHECK_UDP              0
+#define CHECKSUM_CHECK_IP               0
+
+#define HEAP_HIGHWAT                    20*1024
+
+#define LWIP_NETCONN_FULLDUPLEX         1
+#define LWIP_NETCONN_SEM_PER_THREAD     1
+
+
+
+#define SOC_SEND_LOG //printf
+
+#endif /* __LWIPOPTS_H__ */
diff --git a/tools/sdk/include/lwip/netdb.h b/tools/sdk/include/lwip/netdb.h
new file mode 100755
index 00000000..12d4c7f5
--- /dev/null
+++ b/tools/sdk/include/lwip/netdb.h
@@ -0,0 +1,33 @@
+/**
+ * @file
+ * This file is a posix wrapper for lwip/netdb.h.
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#include "lwip/netdb.h"
diff --git a/tools/sdk/include/lwip/netif/etharp.h b/tools/sdk/include/lwip/netif/etharp.h
new file mode 100755
index 00000000..e745dcc3
--- /dev/null
+++ b/tools/sdk/include/lwip/netif/etharp.h
@@ -0,0 +1,143 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * Copyright (c) 2003-2004 Leon Woestenberg 
+ * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#ifndef LWIP_HDR_NETIF_ETHARP_H
+#define LWIP_HDR_NETIF_ETHARP_H
+
+#include "lwip/opt.h"
+
+#if LWIP_ARP || LWIP_ETHERNET /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/pbuf.h"
+#include "lwip/ip4_addr.h"
+#include "lwip/netif.h"
+#include "lwip/ip4.h"
+#include "netif/ethernet.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if LWIP_IPV4 && LWIP_ARP /* don't build if not configured for use in lwipopts.h */
+
+#ifndef ETHARP_HWADDR_LEN
+#define ETHARP_HWADDR_LEN     ETH_HWADDR_LEN
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+/** the ARP message, see RFC 826 ("Packet format") */
+struct etharp_hdr {
+  PACK_STRUCT_FIELD(u16_t hwtype);
+  PACK_STRUCT_FIELD(u16_t proto);
+  PACK_STRUCT_FLD_8(u8_t  hwlen);
+  PACK_STRUCT_FLD_8(u8_t  protolen);
+  PACK_STRUCT_FIELD(u16_t opcode);
+  PACK_STRUCT_FLD_S(struct eth_addr shwaddr);
+  PACK_STRUCT_FLD_S(struct ip4_addr2 sipaddr);
+  PACK_STRUCT_FLD_S(struct eth_addr dhwaddr);
+  PACK_STRUCT_FLD_S(struct ip4_addr2 dipaddr);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define SIZEOF_ETHARP_HDR 28
+
+#define SIZEOF_ETHARP_PACKET    (SIZEOF_ETH_HDR + SIZEOF_ETHARP_HDR)
+#if ETHARP_SUPPORT_VLAN && defined(LWIP_HOOK_VLAN_SET)
+#define SIZEOF_ETHARP_PACKET_TX (SIZEOF_ETHARP_PACKET + SIZEOF_VLAN_HDR)
+#else /* ETHARP_SUPPORT_VLAN && defined(LWIP_HOOK_VLAN_SET) */
+#define SIZEOF_ETHARP_PACKET_TX SIZEOF_ETHARP_PACKET
+#endif /* ETHARP_SUPPORT_VLAN && defined(LWIP_HOOK_VLAN_SET) */
+
+/** 1 seconds period */
+#define ARP_TMR_INTERVAL 1000
+
+/** ARP message types (opcodes) */
+#define ARP_REQUEST 1
+#define ARP_REPLY   2
+
+#if ARP_QUEUEING
+/** struct for queueing outgoing packets for unknown address
+  * defined here to be accessed by memp.h
+  */
+struct etharp_q_entry {
+  struct etharp_q_entry *next;
+  struct pbuf *p;
+};
+#endif /* ARP_QUEUEING */
+
+#define etharp_init() /* Compatibility define, no init needed. */
+void etharp_tmr(void);
+s8_t etharp_find_addr(struct netif *netif, const ip4_addr_t *ipaddr,
+         struct eth_addr **eth_ret, const ip4_addr_t **ip_ret);
+u8_t etharp_get_entry(u8_t i, ip4_addr_t **ipaddr, struct netif **netif, struct eth_addr **eth_ret);
+err_t etharp_output(struct netif *netif, struct pbuf *q, const ip4_addr_t *ipaddr);
+err_t etharp_query(struct netif *netif, const ip4_addr_t *ipaddr, struct pbuf *q);
+err_t etharp_request(struct netif *netif, const ip4_addr_t *ipaddr);
+/** For Ethernet network interfaces, we might want to send "gratuitous ARP";
+ *  this is an ARP packet sent by a node in order to spontaneously cause other
+ *  nodes to update an entry in their ARP cache.
+ *  From RFC 3220 "IP Mobility Support for IPv4" section 4.6. */
+#define etharp_gratuitous(netif) etharp_request((netif), netif_ip4_addr(netif))
+void etharp_cleanup_netif(struct netif *netif);
+
+#if ETHARP_SUPPORT_STATIC_ENTRIES
+err_t etharp_add_static_entry(const ip4_addr_t *ipaddr, struct eth_addr *ethaddr);
+err_t etharp_remove_static_entry(const ip4_addr_t *ipaddr);
+#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */
+
+#if LWIP_AUTOIP
+err_t etharp_raw(struct netif *netif, const struct eth_addr *ethsrc_addr,
+                 const struct eth_addr *ethdst_addr,
+                 const struct eth_addr *hwsrc_addr, const ip4_addr_t *ipsrc_addr,
+                 const struct eth_addr *hwdst_addr, const ip4_addr_t *ipdst_addr,
+                 const u16_t opcode);
+#endif /* LWIP_AUTOIP */
+
+#endif /* LWIP_IPV4 && LWIP_ARP */
+
+void etharp_arp_input(struct netif *netif, struct eth_addr *ethaddr, struct pbuf *p);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_ARP || LWIP_ETHERNET */
+
+#endif /* LWIP_HDR_NETIF_ETHARP_H */
diff --git a/tools/sdk/include/lwip/netif/ethernet.h b/tools/sdk/include/lwip/netif/ethernet.h
new file mode 100755
index 00000000..17623e4a
--- /dev/null
+++ b/tools/sdk/include/lwip/netif/ethernet.h
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * Copyright (c) 2003-2004 Leon Woestenberg 
+ * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#ifndef LWIP_HDR_NETIF_ETHERNET_H
+#define LWIP_HDR_NETIF_ETHERNET_H
+
+#include "lwip/opt.h"
+
+#include "lwip/pbuf.h"
+#include "lwip/netif.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef ETH_HWADDR_LEN
+#ifdef ETHARP_HWADDR_LEN
+#define ETH_HWADDR_LEN    ETHARP_HWADDR_LEN /* compatibility mode */
+#else
+#define ETH_HWADDR_LEN    6
+#endif
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct eth_addr {
+  PACK_STRUCT_FLD_8(u8_t addr[ETH_HWADDR_LEN]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+/** Ethernet header */
+struct eth_hdr {
+#if ETH_PAD_SIZE
+  PACK_STRUCT_FLD_8(u8_t padding[ETH_PAD_SIZE]);
+#endif
+  PACK_STRUCT_FLD_S(struct eth_addr dest);
+  PACK_STRUCT_FLD_S(struct eth_addr src);
+  PACK_STRUCT_FIELD(u16_t type);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define SIZEOF_ETH_HDR (14 + ETH_PAD_SIZE)
+
+#if ETHARP_SUPPORT_VLAN
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+/** VLAN header inserted between ethernet header and payload
+ * if 'type' in ethernet header is ETHTYPE_VLAN.
+ * See IEEE802.Q */
+struct eth_vlan_hdr {
+  PACK_STRUCT_FIELD(u16_t prio_vid);
+  PACK_STRUCT_FIELD(u16_t tpid);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define SIZEOF_VLAN_HDR 4
+#define VLAN_ID(vlan_hdr) (htons((vlan_hdr)->prio_vid) & 0xFFF)
+
+#endif /* ETHARP_SUPPORT_VLAN */
+
+/* A list of often ethtypes (although lwIP does not use all of them): */
+#define ETHTYPE_IP        0x0800U  /* Internet protocol v4 */
+#define ETHTYPE_ARP       0x0806U  /* Address resolution protocol */
+#define ETHTYPE_WOL       0x0842U  /* Wake on lan */
+#define ETHTYPE_VLAN      0x8100U  /* Virtual local area network */
+#define ETHTYPE_IPV6      0x86DDU  /* Internet protocol v6 */
+#define ETHTYPE_PPPOEDISC 0x8863U  /* PPP Over Ethernet Discovery Stage */
+#define ETHTYPE_PPPOE     0x8864U  /* PPP Over Ethernet Session Stage */
+#define ETHTYPE_JUMBO     0x8870U  /* Jumbo Frames */
+#define ETHTYPE_PROFINET  0x8892U  /* Process field network */
+#define ETHTYPE_ETHERCAT  0x88A4U  /* Ethernet for control automation technology */
+#define ETHTYPE_LLDP      0x88CCU  /* Link layer discovery protocol */
+#define ETHTYPE_SERCOS    0x88CDU  /* Serial real-time communication system */
+#define ETHTYPE_PTP       0x88F7U  /* Precision time protocol */
+#define ETHTYPE_QINQ      0x9100U  /* Q-in-Q, 802.1ad */
+
+/** The 24-bit IANA IPv4-multicast OUI is 01-00-5e: */
+#define LL_IP4_MULTICAST_ADDR_0 0x01
+#define LL_IP4_MULTICAST_ADDR_1 0x00
+#define LL_IP4_MULTICAST_ADDR_2 0x5e
+
+/** IPv6 multicast uses this prefix */
+#define LL_IP6_MULTICAST_ADDR_0 0x33
+#define LL_IP6_MULTICAST_ADDR_1 0x33
+
+/** MEMCPY-like macro to copy to/from struct eth_addr's that are local variables
+ * or known to be 32-bit aligned within the protocol header. */
+#ifndef ETHADDR32_COPY
+#define ETHADDR32_COPY(dst, src)  SMEMCPY(dst, src, ETH_HWADDR_LEN)
+#endif
+
+/** MEMCPY-like macro to copy to/from struct eth_addr's that are no local
+ * variables and known to be 16-bit aligned within the protocol header. */
+#ifndef ETHADDR16_COPY
+#define ETHADDR16_COPY(dst, src)  SMEMCPY(dst, src, ETH_HWADDR_LEN)
+#endif
+
+#if LWIP_ARP || LWIP_ETHERNET
+
+/** Define this to 1 and define LWIP_ARP_FILTER_NETIF_FN(pbuf, netif, type)
+ * to a filter function that returns the correct netif when using multiple
+ * netifs on one hardware interface where the netif's low-level receive
+ * routine cannot decide for the correct netif (e.g. when mapping multiple
+ * IP addresses to one hardware interface).
+ */
+#ifndef LWIP_ARP_FILTER_NETIF
+#define LWIP_ARP_FILTER_NETIF 0
+#endif
+
+err_t ethernet_input(struct pbuf *p, struct netif *netif);
+
+#define eth_addr_cmp(addr1, addr2) (memcmp((addr1)->addr, (addr2)->addr, ETH_HWADDR_LEN) == 0)
+
+extern const struct eth_addr ethbroadcast, ethzero;
+
+#endif /* LWIP_ARP || LWIP_ETHERNET */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_NETIF_ETHERNET_H */
diff --git a/tools/sdk/include/lwip/netif/lowpan6.h b/tools/sdk/include/lwip/netif/lowpan6.h
new file mode 100755
index 00000000..21552938
--- /dev/null
+++ b/tools/sdk/include/lwip/netif/lowpan6.h
@@ -0,0 +1,84 @@
+/**
+ * @file
+ *
+ * 6LowPAN output for IPv6. Uses ND tables for link-layer addressing. Fragments packets to 6LowPAN units.
+ */
+
+/*
+ * Copyright (c) 2015 Inico Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Ivan Delamer 
+ *
+ *
+ * Please coordinate changes and requests with Ivan Delamer
+ * 
+ */
+
+#ifndef LWIP_HDR_LOWPAN6_H
+#define LWIP_HDR_LOWPAN6_H
+
+#include "netif/lowpan6_opts.h"
+
+#if LWIP_IPV6 && LWIP_6LOWPAN /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/pbuf.h"
+#include "lwip/ip.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** 1 second period */
+#define LOWPAN6_TMR_INTERVAL 1000
+
+void lowpan6_tmr(void);
+
+err_t lowpan6_set_context(u8_t index, const ip6_addr_t * context);
+err_t lowpan6_set_short_addr(u8_t addr_high, u8_t addr_low);
+
+#if LWIP_IPV4
+err_t lowpan4_output(struct netif *netif, struct pbuf *q, const ip4_addr_t *ipaddr);
+#endif /* LWIP_IPV4 */
+err_t lowpan6_output(struct netif *netif, struct pbuf *q, const ip6_addr_t *ip6addr);
+err_t lowpan6_input(struct pbuf * p, struct netif *netif);
+err_t lowpan6_if_init(struct netif *netif);
+
+/* pan_id in network byte order. */
+err_t lowpan6_set_pan_id(u16_t pan_id);
+
+err_t tcpip_6lowpan_input(struct pbuf *p, struct netif *inp);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV6 && LWIP_6LOWPAN */
+
+#endif /* LWIP_HDR_LOWPAN6_H */
diff --git a/tools/sdk/include/lwip/netif/lowpan6_opts.h b/tools/sdk/include/lwip/netif/lowpan6_opts.h
new file mode 100755
index 00000000..6a769575
--- /dev/null
+++ b/tools/sdk/include/lwip/netif/lowpan6_opts.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2015 Inico Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Ivan Delamer 
+ *
+ *
+ * Please coordinate changes and requests with Ivan Delamer
+ * 
+ */
+
+#ifndef LWIP_HDR_LOWPAN6_OPTS_H
+#define LWIP_HDR_LOWPAN6_OPTS_H
+
+#include "lwip/opt.h"
+
+#ifndef LWIP_6LOWPAN
+#define LWIP_6LOWPAN                     0
+#endif
+
+#ifndef LWIP_6LOWPAN_NUM_CONTEXTS
+#define LWIP_6LOWPAN_NUM_CONTEXTS        10
+#endif
+
+#ifndef LWIP_6LOWPAN_INFER_SHORT_ADDRESS
+#define LWIP_6LOWPAN_INFER_SHORT_ADDRESS 1
+#endif
+
+#ifndef LWIP_6LOWPAN_IPHC
+#define LWIP_6LOWPAN_IPHC                1
+#endif
+
+#ifndef LWIP_6LOWPAN_HW_CRC
+#define LWIP_6LOWPAN_HW_CRC              1
+#endif
+
+#ifndef LOWPAN6_DEBUG
+#define LOWPAN6_DEBUG                    LWIP_DBG_OFF
+#endif
+
+#endif /* LWIP_HDR_LOWPAN6_OPTS_H */
diff --git a/tools/sdk/include/lwip/netif/ppp/ccp.h b/tools/sdk/include/lwip/netif/ppp/ccp.h
new file mode 100755
index 00000000..a8eab9c0
--- /dev/null
+++ b/tools/sdk/include/lwip/netif/ppp/ccp.h
@@ -0,0 +1,156 @@
+/*
+ * ccp.h - Definitions for PPP Compression Control Protocol.
+ *
+ * Copyright (c) 1994-2002 Paul Mackerras. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. The name(s) of the authors of this software must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission.
+ *
+ * 3. Redistributions of any form whatsoever must retain the following
+ *    acknowledgment:
+ *    "This product includes software developed by Paul Mackerras
+ *     ".
+ *
+ * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ccp.h,v 1.12 2004/11/04 10:02:26 paulus Exp $
+ */
+
+#include "lwip/opt.h"
+#if PPP_SUPPORT && CCP_SUPPORT  /* don't build if not configured for use in lwipopts.h */
+
+#ifndef CCP_H
+#define CCP_H
+
+/*
+ * CCP codes.
+ */
+
+#define CCP_CONFREQ	1
+#define CCP_CONFACK	2
+#define CCP_TERMREQ	5
+#define CCP_TERMACK	6
+#define CCP_RESETREQ	14
+#define CCP_RESETACK	15
+
+/*
+ * Max # bytes for a CCP option
+ */
+
+#define CCP_MAX_OPTION_LENGTH	32
+
+/*
+ * Parts of a CCP packet.
+ */
+
+#define CCP_CODE(dp)		((dp)[0])
+#define CCP_ID(dp)		((dp)[1])
+#define CCP_LENGTH(dp)		(((dp)[2] << 8) + (dp)[3])
+#define CCP_HDRLEN		4
+
+#define CCP_OPT_CODE(dp)	((dp)[0])
+#define CCP_OPT_LENGTH(dp)	((dp)[1])
+#define CCP_OPT_MINLEN		2
+
+#if BSDCOMPRESS_SUPPORT
+/*
+ * Definitions for BSD-Compress.
+ */
+
+#define CI_BSD_COMPRESS		21	/* config. option for BSD-Compress */
+#define CILEN_BSD_COMPRESS	3	/* length of config. option */
+
+/* Macros for handling the 3rd byte of the BSD-Compress config option. */
+#define BSD_NBITS(x)		((x) & 0x1F)	/* number of bits requested */
+#define BSD_VERSION(x)		((x) >> 5)	/* version of option format */
+#define BSD_CURRENT_VERSION	1		/* current version number */
+#define BSD_MAKE_OPT(v, n)	(((v) << 5) | (n))
+
+#define BSD_MIN_BITS		9	/* smallest code size supported */
+#define BSD_MAX_BITS		15	/* largest code size supported */
+#endif /* BSDCOMPRESS_SUPPORT */
+
+#if DEFLATE_SUPPORT
+/*
+ * Definitions for Deflate.
+ */
+
+#define CI_DEFLATE		26	/* config option for Deflate */
+#define CI_DEFLATE_DRAFT	24	/* value used in original draft RFC */
+#define CILEN_DEFLATE		4	/* length of its config option */
+
+#define DEFLATE_MIN_SIZE	9
+#define DEFLATE_MAX_SIZE	15
+#define DEFLATE_METHOD_VAL	8
+#define DEFLATE_SIZE(x)		(((x) >> 4) + 8)
+#define DEFLATE_METHOD(x)	((x) & 0x0F)
+#define DEFLATE_MAKE_OPT(w)	((((w) - 8) << 4) + DEFLATE_METHOD_VAL)
+#define DEFLATE_CHK_SEQUENCE	0
+#endif /* DEFLATE_SUPPORT */
+
+#if MPPE_SUPPORT
+/*
+ * Definitions for MPPE.
+ */
+
+#define CI_MPPE                18      /* config option for MPPE */
+#define CILEN_MPPE              6      /* length of config option */
+#endif /* MPPE_SUPPORT */
+
+#if PREDICTOR_SUPPORT
+/*
+ * Definitions for other, as yet unsupported, compression methods.
+ */
+
+#define CI_PREDICTOR_1		1	/* config option for Predictor-1 */
+#define CILEN_PREDICTOR_1	2	/* length of its config option */
+#define CI_PREDICTOR_2		2	/* config option for Predictor-2 */
+#define CILEN_PREDICTOR_2	2	/* length of its config option */
+#endif /* PREDICTOR_SUPPORT */
+
+typedef struct ccp_options {
+#if DEFLATE_SUPPORT
+    unsigned int deflate          :1; /* do Deflate? */
+    unsigned int deflate_correct  :1; /* use correct code for deflate? */
+    unsigned int deflate_draft    :1; /* use draft RFC code for deflate? */
+#endif /* DEFLATE_SUPPORT */
+#if BSDCOMPRESS_SUPPORT
+    unsigned int bsd_compress     :1; /* do BSD Compress? */
+#endif /* BSDCOMPRESS_SUPPORT */
+#if PREDICTOR_SUPPORT
+    unsigned int predictor_1      :1; /* do Predictor-1? */
+    unsigned int predictor_2      :1; /* do Predictor-2? */
+#endif /* PREDICTOR_SUPPORT */
+
+#if MPPE_SUPPORT
+    u8_t mppe;			/* MPPE bitfield */
+#endif /* MPPE_SUPPORT */
+#if BSDCOMPRESS_SUPPORT
+    u_short bsd_bits;		/* # bits/code for BSD Compress */
+#endif /* BSDCOMPRESS_SUPPORT */
+#if DEFLATE_SUPPORT
+    u_short deflate_size;	/* lg(window size) for Deflate */
+#endif /* DEFLATE_SUPPORT */
+    u8_t method;		/* code for chosen compression method */
+} ccp_options;
+
+extern const struct protent ccp_protent;
+
+void ccp_resetrequest(ppp_pcb *pcb);  /* Issue a reset-request. */
+
+#endif /* CCP_H */
+#endif /* PPP_SUPPORT && CCP_SUPPORT */
diff --git a/tools/sdk/include/lwip/netif/ppp/chap-md5.h b/tools/sdk/include/lwip/netif/ppp/chap-md5.h
new file mode 100755
index 00000000..a05a157d
--- /dev/null
+++ b/tools/sdk/include/lwip/netif/ppp/chap-md5.h
@@ -0,0 +1,36 @@
+/*
+ * chap-md5.h - New CHAP/MD5 implementation.
+ *
+ * Copyright (c) 2003 Paul Mackerras. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. The name(s) of the authors of this software must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission.
+ *
+ * 3. Redistributions of any form whatsoever must retain the following
+ *    acknowledgment:
+ *    "This product includes software developed by Paul Mackerras
+ *     ".
+ *
+ * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "lwip/opt.h"
+#if PPP_SUPPORT && CHAP_SUPPORT  /* don't build if not configured for use in lwipopts.h */
+
+extern const struct chap_digest_type md5_digest;
+
+#endif /* PPP_SUPPORT && CHAP_SUPPORT */
diff --git a/tools/sdk/include/lwip/netif/ppp/chap-new.h b/tools/sdk/include/lwip/netif/ppp/chap-new.h
new file mode 100755
index 00000000..9b7c0487
--- /dev/null
+++ b/tools/sdk/include/lwip/netif/ppp/chap-new.h
@@ -0,0 +1,192 @@
+/*
+ * chap-new.c - New CHAP implementation.
+ *
+ * Copyright (c) 2003 Paul Mackerras. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. The name(s) of the authors of this software must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission.
+ *
+ * 3. Redistributions of any form whatsoever must retain the following
+ *    acknowledgment:
+ *    "This product includes software developed by Paul Mackerras
+ *     ".
+ *
+ * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "lwip/opt.h"
+#if PPP_SUPPORT && CHAP_SUPPORT  /* don't build if not configured for use in lwipopts.h */
+
+#ifndef CHAP_H
+#define CHAP_H
+
+#include "ppp.h"
+
+/*
+ * CHAP packets begin with a standard header with code, id, len (2 bytes).
+ */
+#define CHAP_HDRLEN	4
+
+/*
+ * Values for the code field.
+ */
+#define CHAP_CHALLENGE	1
+#define CHAP_RESPONSE	2
+#define CHAP_SUCCESS	3
+#define CHAP_FAILURE	4
+
+/*
+ * CHAP digest codes.
+ */
+#define CHAP_MD5		5
+#if MSCHAP_SUPPORT
+#define CHAP_MICROSOFT		0x80
+#define CHAP_MICROSOFT_V2	0x81
+#endif /* MSCHAP_SUPPORT */
+
+/*
+ * Semi-arbitrary limits on challenge and response fields.
+ */
+#define MAX_CHALLENGE_LEN	64
+#define MAX_RESPONSE_LEN	64
+
+/*
+ * These limits apply to challenge and response packets we send.
+ * The +4 is the +1 that we actually need rounded up.
+ */
+#define CHAL_MAX_PKTLEN	(PPP_HDRLEN + CHAP_HDRLEN + 4 + MAX_CHALLENGE_LEN + MAXNAMELEN)
+#define RESP_MAX_PKTLEN	(PPP_HDRLEN + CHAP_HDRLEN + 4 + MAX_RESPONSE_LEN + MAXNAMELEN)
+
+/* bitmask of supported algorithms */
+#if MSCHAP_SUPPORT
+#define MDTYPE_MICROSOFT_V2	0x1
+#define MDTYPE_MICROSOFT	0x2
+#endif /* MSCHAP_SUPPORT */
+#define MDTYPE_MD5		0x4
+#define MDTYPE_NONE		0
+
+#if MSCHAP_SUPPORT
+/* Return the digest alg. ID for the most preferred digest type. */
+#define CHAP_DIGEST(mdtype) \
+    ((mdtype) & MDTYPE_MD5)? CHAP_MD5: \
+    ((mdtype) & MDTYPE_MICROSOFT_V2)? CHAP_MICROSOFT_V2: \
+    ((mdtype) & MDTYPE_MICROSOFT)? CHAP_MICROSOFT: \
+    0
+#else /* !MSCHAP_SUPPORT */
+#define CHAP_DIGEST(mdtype) \
+    ((mdtype) & MDTYPE_MD5)? CHAP_MD5: \
+    0
+#endif /* MSCHAP_SUPPORT */
+
+/* Return the bit flag (lsb set) for our most preferred digest type. */
+#define CHAP_MDTYPE(mdtype) ((mdtype) ^ ((mdtype) - 1)) & (mdtype)
+
+/* Return the bit flag for a given digest algorithm ID. */
+#if MSCHAP_SUPPORT
+#define CHAP_MDTYPE_D(digest) \
+    ((digest) == CHAP_MICROSOFT_V2)? MDTYPE_MICROSOFT_V2: \
+    ((digest) == CHAP_MICROSOFT)? MDTYPE_MICROSOFT: \
+    ((digest) == CHAP_MD5)? MDTYPE_MD5: \
+    0
+#else /* !MSCHAP_SUPPORT */
+#define CHAP_MDTYPE_D(digest) \
+    ((digest) == CHAP_MD5)? MDTYPE_MD5: \
+    0
+#endif /* MSCHAP_SUPPORT */
+
+/* Can we do the requested digest? */
+#if MSCHAP_SUPPORT
+#define CHAP_CANDIGEST(mdtype, digest) \
+    ((digest) == CHAP_MICROSOFT_V2)? (mdtype) & MDTYPE_MICROSOFT_V2: \
+    ((digest) == CHAP_MICROSOFT)? (mdtype) & MDTYPE_MICROSOFT: \
+    ((digest) == CHAP_MD5)? (mdtype) & MDTYPE_MD5: \
+    0
+#else /* !MSCHAP_SUPPORT */
+#define CHAP_CANDIGEST(mdtype, digest) \
+    ((digest) == CHAP_MD5)? (mdtype) & MDTYPE_MD5: \
+    0
+#endif /* MSCHAP_SUPPORT */
+
+/*
+ * The code for each digest type has to supply one of these.
+ */
+struct chap_digest_type {
+	int code;
+
+#if PPP_SERVER
+	/*
+	 * Note: challenge and response arguments below are formatted as
+	 * a length byte followed by the actual challenge/response data.
+	 */
+	void (*generate_challenge)(ppp_pcb *pcb, unsigned char *challenge);
+	int (*verify_response)(ppp_pcb *pcb, int id, const char *name,
+		const unsigned char *secret, int secret_len,
+		const unsigned char *challenge, const unsigned char *response,
+		char *message, int message_space);
+#endif /* PPP_SERVER */
+	void (*make_response)(ppp_pcb *pcb, unsigned char *response, int id, const char *our_name,
+		const unsigned char *challenge, const char *secret, int secret_len,
+		unsigned char *priv);
+	int (*check_success)(ppp_pcb *pcb, unsigned char *pkt, int len, unsigned char *priv);
+	void (*handle_failure)(ppp_pcb *pcb, unsigned char *pkt, int len);
+};
+
+/*
+ * Each interface is described by chap structure.
+ */
+#if CHAP_SUPPORT
+typedef struct chap_client_state {
+	u8_t flags;
+	const char *name;
+	const struct chap_digest_type *digest;
+	unsigned char priv[64];		/* private area for digest's use */
+} chap_client_state;
+
+#if PPP_SERVER
+typedef struct chap_server_state {
+	u8_t flags;
+	u8_t id;
+	const char *name;
+	const struct chap_digest_type *digest;
+	int challenge_xmits;
+	int challenge_pktlen;
+	unsigned char challenge[CHAL_MAX_PKTLEN];
+} chap_server_state;
+#endif /* PPP_SERVER */
+#endif /* CHAP_SUPPORT */
+
+#if 0 /* UNUSED */
+/* Hook for a plugin to validate CHAP challenge */
+extern int (*chap_verify_hook)(char *name, char *ourname, int id,
+			const struct chap_digest_type *digest,
+			unsigned char *challenge, unsigned char *response,
+			char *message, int message_space);
+#endif /* UNUSED */
+
+#if PPP_SERVER
+/* Called by authentication code to start authenticating the peer. */
+extern void chap_auth_peer(ppp_pcb *pcb, const char *our_name, int digest_code);
+#endif /* PPP_SERVER */
+
+/* Called by auth. code to start authenticating us to the peer. */
+extern void chap_auth_with_peer(ppp_pcb *pcb, const char *our_name, int digest_code);
+
+/* Represents the CHAP protocol to the main pppd code */
+extern const struct protent chap_protent;
+
+#endif /* CHAP_H */
+#endif /* PPP_SUPPORT && CHAP_SUPPORT */
diff --git a/tools/sdk/include/lwip/netif/ppp/chap_ms.h b/tools/sdk/include/lwip/netif/ppp/chap_ms.h
new file mode 100755
index 00000000..709bb899
--- /dev/null
+++ b/tools/sdk/include/lwip/netif/ppp/chap_ms.h
@@ -0,0 +1,44 @@
+/*
+ * chap_ms.h - Challenge Handshake Authentication Protocol definitions.
+ *
+ * Copyright (c) 1995 Eric Rosenquist.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * 3. The name(s) of the authors of this software must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission.
+ *
+ * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: chap_ms.h,v 1.13 2004/11/15 22:13:26 paulus Exp $
+ */
+
+#include "lwip/opt.h"
+#if PPP_SUPPORT && MSCHAP_SUPPORT  /* don't build if not configured for use in lwipopts.h */
+
+#ifndef __CHAPMS_INCLUDE__
+
+extern const struct chap_digest_type chapms_digest;
+extern const struct chap_digest_type chapms2_digest;
+
+#define __CHAPMS_INCLUDE__
+#endif /* __CHAPMS_INCLUDE__ */
+
+#endif /* PPP_SUPPORT && MSCHAP_SUPPORT */
diff --git a/tools/sdk/include/lwip/netif/ppp/eap.h b/tools/sdk/include/lwip/netif/ppp/eap.h
new file mode 100755
index 00000000..7dfd6763
--- /dev/null
+++ b/tools/sdk/include/lwip/netif/ppp/eap.h
@@ -0,0 +1,169 @@
+/*
+ * eap.h - Extensible Authentication Protocol for PPP (RFC 2284)
+ *
+ * Copyright (c) 2001 by Sun Microsystems, Inc.
+ * All rights reserved.
+ *
+ * Non-exclusive rights to redistribute, modify, translate, and use
+ * this software in source and binary forms, in whole or in part, is
+ * hereby granted, provided that the above copyright notice is
+ * duplicated in any source form, and that neither the name of the
+ * copyright holder nor the author is used to endorse or promote
+ * products derived from this software.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Original version by James Carlson
+ *
+ * $Id: eap.h,v 1.2 2003/06/11 23:56:26 paulus Exp $
+ */
+
+#include "lwip/opt.h"
+#if PPP_SUPPORT && EAP_SUPPORT  /* don't build if not configured for use in lwipopts.h */
+
+#ifndef PPP_EAP_H
+#define	PPP_EAP_H
+
+#include "ppp.h"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/*
+ * Packet header = Code, id, length.
+ */
+#define	EAP_HEADERLEN	4
+
+
+/* EAP message codes. */
+#define	EAP_REQUEST	1
+#define	EAP_RESPONSE	2
+#define	EAP_SUCCESS	3
+#define	EAP_FAILURE	4
+
+/* EAP types */
+#define	EAPT_IDENTITY		1
+#define	EAPT_NOTIFICATION	2
+#define	EAPT_NAK		3	/* (response only) */
+#define	EAPT_MD5CHAP		4
+#define	EAPT_OTP		5	/* One-Time Password; RFC 1938 */
+#define	EAPT_TOKEN		6	/* Generic Token Card */
+/* 7 and 8 are unassigned. */
+#define	EAPT_RSA		9	/* RSA Public Key Authentication */
+#define	EAPT_DSS		10	/* DSS Unilateral */
+#define	EAPT_KEA		11	/* KEA */
+#define	EAPT_KEA_VALIDATE	12	/* KEA-VALIDATE	*/
+#define	EAPT_TLS		13	/* EAP-TLS */
+#define	EAPT_DEFENDER		14	/* Defender Token (AXENT) */
+#define	EAPT_W2K		15	/* Windows 2000 EAP */
+#define	EAPT_ARCOT		16	/* Arcot Systems */
+#define	EAPT_CISCOWIRELESS	17	/* Cisco Wireless */
+#define	EAPT_NOKIACARD		18	/* Nokia IP smart card */
+#define	EAPT_SRP		19	/* Secure Remote Password */
+/* 20 is deprecated */
+
+/* EAP SRP-SHA1 Subtypes */
+#define	EAPSRP_CHALLENGE	1	/* Request 1 - Challenge */
+#define	EAPSRP_CKEY		1	/* Response 1 - Client Key */
+#define	EAPSRP_SKEY		2	/* Request 2 - Server Key */
+#define	EAPSRP_CVALIDATOR	2	/* Response 2 - Client Validator */
+#define	EAPSRP_SVALIDATOR	3	/* Request 3 - Server Validator */
+#define	EAPSRP_ACK		3	/* Response 3 - final ack */
+#define	EAPSRP_LWRECHALLENGE	4	/* Req/resp 4 - Lightweight rechal */
+
+#define	SRPVAL_EBIT	0x00000001	/* Use shared key for ECP */
+
+#define	SRP_PSEUDO_ID	"pseudo_"
+#define	SRP_PSEUDO_LEN	7
+
+#define MD5_SIGNATURE_SIZE	16
+#define EAP_MIN_CHALLENGE_LENGTH	17
+#define EAP_MAX_CHALLENGE_LENGTH	24
+#define EAP_MIN_MAX_POWER_OF_TWO_CHALLENGE_LENGTH     3   /* 2^3-1 = 7, 17+7 = 24 */
+
+#define	EAP_STATES	\
+	"Initial", "Pending", "Closed", "Listen", "Identify", \
+	"SRP1", "SRP2", "SRP3", "MD5Chall", "Open", "SRP4", "BadAuth"
+
+#define	eap_client_active(pcb)	((pcb)->eap.es_client.ea_state == eapListen)
+#if PPP_SERVER
+#define	eap_server_active(pcb)	\
+	((pcb)->eap.es_server.ea_state >= eapIdentify && \
+	 (pcb)->eap.es_server.ea_state <= eapMD5Chall)
+#endif /* PPP_SERVER */
+
+/*
+ * Complete EAP state for one PPP session.
+ */
+enum eap_state_code {
+	eapInitial = 0,	/* No EAP authentication yet requested */
+	eapPending,	/* Waiting for LCP (no timer) */
+	eapClosed,	/* Authentication not in use */
+	eapListen,	/* Client ready (and timer running) */
+	eapIdentify,	/* EAP Identify sent */
+	eapSRP1,	/* Sent EAP SRP-SHA1 Subtype 1 */
+	eapSRP2,	/* Sent EAP SRP-SHA1 Subtype 2 */
+	eapSRP3,	/* Sent EAP SRP-SHA1 Subtype 3 */
+	eapMD5Chall,	/* Sent MD5-Challenge */
+	eapOpen,	/* Completed authentication */
+	eapSRP4,	/* Sent EAP SRP-SHA1 Subtype 4 */
+	eapBadAuth	/* Failed authentication */
+};
+
+struct eap_auth {
+	const char *ea_name;	/* Our name */
+	char ea_peer[MAXNAMELEN +1];	/* Peer's name */
+	void *ea_session;	/* Authentication library linkage */
+	u_char *ea_skey;	/* Shared encryption key */
+	u_short ea_namelen;	/* Length of our name */
+	u_short ea_peerlen;	/* Length of peer's name */
+	enum eap_state_code ea_state;
+	u_char ea_id;		/* Current id */
+	u_char ea_requests;	/* Number of Requests sent/received */
+	u_char ea_responses;	/* Number of Responses */
+	u_char ea_type;		/* One of EAPT_* */
+	u32_t ea_keyflags;	/* SRP shared key usage flags */
+};
+
+#ifndef EAP_MAX_CHALLENGE_LENGTH
+#define EAP_MAX_CHALLENGE_LENGTH	24
+#endif
+typedef struct eap_state {
+	struct eap_auth es_client;	/* Client (authenticatee) data */
+#if PPP_SERVER
+	struct eap_auth es_server;	/* Server (authenticator) data */
+#endif /* PPP_SERVER */
+	int es_savedtime;		/* Saved timeout */
+	int es_rechallenge;		/* EAP rechallenge interval */
+	int es_lwrechallenge;		/* SRP lightweight rechallenge inter */
+	u8_t es_usepseudo;		/* Use SRP Pseudonym if offered one */
+	int es_usedpseudo;		/* Set if we already sent PN */
+	int es_challen;			/* Length of challenge string */
+	u_char es_challenge[EAP_MAX_CHALLENGE_LENGTH];
+} eap_state;
+
+/*
+ * Timeouts.
+ */
+#if 0 /* moved to opt.h */
+#define	EAP_DEFTIMEOUT		3	/* Timeout (seconds) for rexmit */
+#define	EAP_DEFTRANSMITS	10	/* max # times to transmit */
+#define	EAP_DEFREQTIME		20	/* Time to wait for peer request */
+#define	EAP_DEFALLOWREQ		20	/* max # times to accept requests */
+#endif /* moved to opt.h */
+
+void eap_authwithpeer(ppp_pcb *pcb, const char *localname);
+void eap_authpeer(ppp_pcb *pcb, const char *localname);
+
+extern const struct protent eap_protent;
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* PPP_EAP_H */
+
+#endif /* PPP_SUPPORT && EAP_SUPPORT */
diff --git a/tools/sdk/include/lwip/netif/ppp/ecp.h b/tools/sdk/include/lwip/netif/ppp/ecp.h
new file mode 100755
index 00000000..cba6678e
--- /dev/null
+++ b/tools/sdk/include/lwip/netif/ppp/ecp.h
@@ -0,0 +1,50 @@
+/*
+ * ecp.h - Definitions for PPP Encryption Control Protocol.
+ *
+ * Copyright (c) 2002 Google, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * 3. The name(s) of the authors of this software must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission.
+ *
+ * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ecp.h,v 1.2 2003/01/10 07:12:36 fcusack Exp $
+ */
+
+#include "lwip/opt.h"
+#if PPP_SUPPORT && ECP_SUPPORT  /* don't build if not configured for use in lwipopts.h */
+
+typedef struct ecp_options {
+    bool required;		/* Is ECP required? */
+    unsigned enctype;		/* Encryption type */
+} ecp_options;
+
+extern fsm ecp_fsm[];
+extern ecp_options ecp_wantoptions[];
+extern ecp_options ecp_gotoptions[];
+extern ecp_options ecp_allowoptions[];
+extern ecp_options ecp_hisoptions[];
+
+extern const struct protent ecp_protent;
+
+#endif /* PPP_SUPPORT && ECP_SUPPORT */
diff --git a/tools/sdk/include/lwip/netif/ppp/eui64.h b/tools/sdk/include/lwip/netif/ppp/eui64.h
new file mode 100755
index 00000000..dffb5e41
--- /dev/null
+++ b/tools/sdk/include/lwip/netif/ppp/eui64.h
@@ -0,0 +1,94 @@
+/*
+ * eui64.h - EUI64 routines for IPv6CP.
+ *
+ * Copyright (c) 1999 Tommi Komulainen.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * 3. The name(s) of the authors of this software must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission.
+ *
+ * 4. Redistributions of any form whatsoever must retain the following
+ *    acknowledgment:
+ *    "This product includes software developed by Tommi Komulainen
+ *     ".
+ *
+ * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: eui64.h,v 1.6 2002/12/04 23:03:32 paulus Exp $
+*/
+
+#include "lwip/opt.h"
+#if PPP_SUPPORT && PPP_IPV6_SUPPORT  /* don't build if not configured for use in lwipopts.h */
+
+#ifndef __EUI64_H__
+#define __EUI64_H__
+
+/*
+ * TODO:
+ *
+ * Maybe this should be done by processing struct in6_addr directly...
+ */
+typedef union
+{
+    u8_t e8[8];
+    u16_t e16[4];
+    u32_t e32[2];
+} eui64_t;
+
+#define eui64_iszero(e)		(((e).e32[0] | (e).e32[1]) == 0)
+#define eui64_equals(e, o)	(((e).e32[0] == (o).e32[0]) && \
+				((e).e32[1] == (o).e32[1]))
+#define eui64_zero(e)		(e).e32[0] = (e).e32[1] = 0;
+
+#define eui64_copy(s, d)	memcpy(&(d), &(s), sizeof(eui64_t))
+
+#define eui64_magic(e)		do {			\
+				(e).e32[0] = magic();	\
+				(e).e32[1] = magic();	\
+				(e).e8[0] &= ~2;	\
+				} while (0)
+#define eui64_magic_nz(x)	do {				\
+				eui64_magic(x);			\
+				} while (eui64_iszero(x))
+#define eui64_magic_ne(x, y)	do {				\
+				eui64_magic(x);			\
+				} while (eui64_equals(x, y))
+
+#define eui64_get(ll, cp)	do {				\
+				eui64_copy((*cp), (ll));	\
+				(cp) += sizeof(eui64_t);	\
+				} while (0)
+
+#define eui64_put(ll, cp)	do {				\
+				eui64_copy((ll), (*cp));	\
+				(cp) += sizeof(eui64_t);	\
+				} while (0)
+
+#define eui64_set32(e, l)	do {			\
+				(e).e32[0] = 0;		\
+				(e).e32[1] = htonl(l);	\
+				} while (0)
+#define eui64_setlo32(e, l)	eui64_set32(e, l)
+
+char *eui64_ntoa(eui64_t);	/* Returns ascii representation of id */
+
+#endif /* __EUI64_H__ */
+#endif /* PPP_SUPPORT && PPP_IPV6_SUPPORT */
diff --git a/tools/sdk/include/lwip/netif/ppp/fsm.h b/tools/sdk/include/lwip/netif/ppp/fsm.h
new file mode 100755
index 00000000..fc0a4b10
--- /dev/null
+++ b/tools/sdk/include/lwip/netif/ppp/fsm.h
@@ -0,0 +1,175 @@
+/*
+ * fsm.h - {Link, IP} Control Protocol Finite State Machine definitions.
+ *
+ * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * 3. The name "Carnegie Mellon University" must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission. For permission or any legal
+ *    details, please contact
+ *      Office of Technology Transfer
+ *      Carnegie Mellon University
+ *      5000 Forbes Avenue
+ *      Pittsburgh, PA  15213-3890
+ *      (412) 268-4387, fax: (412) 268-7395
+ *      tech-transfer@andrew.cmu.edu
+ *
+ * 4. Redistributions of any form whatsoever must retain the following
+ *    acknowledgment:
+ *    "This product includes software developed by Computing Services
+ *     at Carnegie Mellon University (http://www.cmu.edu/computing/)."
+ *
+ * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE
+ * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: fsm.h,v 1.10 2004/11/13 02:28:15 paulus Exp $
+ */
+
+#include "lwip/opt.h"
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifndef FSM_H
+#define	FSM_H
+
+#include "ppp.h"
+
+/*
+ * Packet header = Code, id, length.
+ */
+#define HEADERLEN	4
+
+
+/*
+ *  CP (LCP, IPCP, etc.) codes.
+ */
+#define CONFREQ		1	/* Configuration Request */
+#define CONFACK		2	/* Configuration Ack */
+#define CONFNAK		3	/* Configuration Nak */
+#define CONFREJ		4	/* Configuration Reject */
+#define TERMREQ		5	/* Termination Request */
+#define TERMACK		6	/* Termination Ack */
+#define CODEREJ		7	/* Code Reject */
+
+
+/*
+ * Each FSM is described by an fsm structure and fsm callbacks.
+ */
+typedef struct fsm {
+    ppp_pcb *pcb;		/* PPP Interface */
+    const struct fsm_callbacks *callbacks;	/* Callback routines */
+    const char *term_reason;	/* Reason for closing protocol */
+    u8_t seen_ack;		/* Have received valid Ack/Nak/Rej to Req */
+				  /* -- This is our only flag, we might use u_int :1 if we have more flags */
+    u16_t protocol;		/* Data Link Layer Protocol field value */
+    u8_t state;			/* State */
+    u8_t flags;			/* Contains option bits */
+    u8_t id;			/* Current id */
+    u8_t reqid;			/* Current request id */
+    u8_t retransmits;		/* Number of retransmissions left */
+    u8_t nakloops;		/* Number of nak loops since last ack */
+    u8_t rnakloops;		/* Number of naks received */
+    u8_t maxnakloops;		/* Maximum number of nak loops tolerated
+				   (necessary because IPCP require a custom large max nak loops value) */
+    u8_t term_reason_len;	/* Length of term_reason */
+} fsm;
+
+
+typedef struct fsm_callbacks {
+    void (*resetci)		/* Reset our Configuration Information */
+		(fsm *);
+    int  (*cilen)		/* Length of our Configuration Information */
+		(fsm *);
+    void (*addci) 		/* Add our Configuration Information */
+		(fsm *, u_char *, int *);
+    int  (*ackci)		/* ACK our Configuration Information */
+		(fsm *, u_char *, int);
+    int  (*nakci)		/* NAK our Configuration Information */
+		(fsm *, u_char *, int, int);
+    int  (*rejci)		/* Reject our Configuration Information */
+		(fsm *, u_char *, int);
+    int  (*reqci)		/* Request peer's Configuration Information */
+		(fsm *, u_char *, int *, int);
+    void (*up)			/* Called when fsm reaches PPP_FSM_OPENED state */
+		(fsm *);
+    void (*down)		/* Called when fsm leaves PPP_FSM_OPENED state */
+		(fsm *);
+    void (*starting)		/* Called when we want the lower layer */
+		(fsm *);
+    void (*finished)		/* Called when we don't want the lower layer */
+		(fsm *);
+    void (*protreject)		/* Called when Protocol-Reject received */
+		(int);
+    void (*retransmit)		/* Retransmission is necessary */
+		(fsm *);
+    int  (*extcode)		/* Called when unknown code received */
+		(fsm *, int, int, u_char *, int);
+    const char *proto_name;	/* String name for protocol (for messages) */
+} fsm_callbacks;
+
+
+/*
+ * Link states.
+ */
+#define PPP_FSM_INITIAL		0	/* Down, hasn't been opened */
+#define PPP_FSM_STARTING	1	/* Down, been opened */
+#define PPP_FSM_CLOSED		2	/* Up, hasn't been opened */
+#define PPP_FSM_STOPPED		3	/* Open, waiting for down event */
+#define PPP_FSM_CLOSING		4	/* Terminating the connection, not open */
+#define PPP_FSM_STOPPING	5	/* Terminating, but open */
+#define PPP_FSM_REQSENT		6	/* We've sent a Config Request */
+#define PPP_FSM_ACKRCVD		7	/* We've received a Config Ack */
+#define PPP_FSM_ACKSENT		8	/* We've sent a Config Ack */
+#define PPP_FSM_OPENED		9	/* Connection available */
+
+
+/*
+ * Flags - indicate options controlling FSM operation
+ */
+#define OPT_PASSIVE	1	/* Don't die if we don't get a response */
+#define OPT_RESTART	2	/* Treat 2nd OPEN as DOWN, UP */
+#define OPT_SILENT	4	/* Wait for peer to speak first */
+
+
+/*
+ * Timeouts.
+ */
+#if 0 /* moved to opt.h */
+#define DEFTIMEOUT	3	/* Timeout time in seconds */
+#define DEFMAXTERMREQS	2	/* Maximum Terminate-Request transmissions */
+#define DEFMAXCONFREQS	10	/* Maximum Configure-Request transmissions */
+#define DEFMAXNAKLOOPS	5	/* Maximum number of nak loops */
+#endif /* moved to opt.h */
+
+
+/*
+ * Prototypes
+ */
+void fsm_init(fsm *f);
+void fsm_lowerup(fsm *f);
+void fsm_lowerdown(fsm *f);
+void fsm_open(fsm *f);
+void fsm_close(fsm *f, const char *reason);
+void fsm_input(fsm *f, u_char *inpacket, int l);
+void fsm_protreject(fsm *f);
+void fsm_sdata(fsm *f, u_char code, u_char id, const u_char *data, int datalen);
+
+
+#endif /* FSM_H */
+#endif /* PPP_SUPPORT */
diff --git a/tools/sdk/include/lwip/netif/ppp/ipcp.h b/tools/sdk/include/lwip/netif/ppp/ipcp.h
new file mode 100755
index 00000000..298f8dc6
--- /dev/null
+++ b/tools/sdk/include/lwip/netif/ppp/ipcp.h
@@ -0,0 +1,126 @@
+/*
+ * ipcp.h - IP Control Protocol definitions.
+ *
+ * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * 3. The name "Carnegie Mellon University" must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission. For permission or any legal
+ *    details, please contact
+ *      Office of Technology Transfer
+ *      Carnegie Mellon University
+ *      5000 Forbes Avenue
+ *      Pittsburgh, PA  15213-3890
+ *      (412) 268-4387, fax: (412) 268-7395
+ *      tech-transfer@andrew.cmu.edu
+ *
+ * 4. Redistributions of any form whatsoever must retain the following
+ *    acknowledgment:
+ *    "This product includes software developed by Computing Services
+ *     at Carnegie Mellon University (http://www.cmu.edu/computing/)."
+ *
+ * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE
+ * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ipcp.h,v 1.14 2002/12/04 23:03:32 paulus Exp $
+ */
+
+#include "lwip/opt.h"
+#if PPP_SUPPORT && PPP_IPV4_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifndef IPCP_H
+#define	IPCP_H
+
+/*
+ * Options.
+ */
+#define CI_ADDRS	1	/* IP Addresses */
+#if VJ_SUPPORT
+#define CI_COMPRESSTYPE	2	/* Compression Type */
+#endif /* VJ_SUPPORT */
+#define	CI_ADDR		3
+
+#if LWIP_DNS
+#define CI_MS_DNS1      129	/* Primary DNS value */
+#define CI_MS_DNS2      131     /* Secondary DNS value */
+#endif /* LWIP_DNS */
+#if 0 /* UNUSED - WINS */
+#define CI_MS_WINS1     130     /* Primary WINS value */
+#define CI_MS_WINS2     132	/* Secondary WINS value */
+#endif /* UNUSED - WINS */
+
+#if VJ_SUPPORT
+#define MAX_STATES 16		/* from slcompress.h */
+
+#define IPCP_VJMODE_OLD 1	/* "old" mode (option # = 0x0037) */
+#define IPCP_VJMODE_RFC1172 2	/* "old-rfc"mode (option # = 0x002d) */
+#define IPCP_VJMODE_RFC1332 3	/* "new-rfc"mode (option # = 0x002d, */
+                                /*  maxslot and slot number compression) */
+
+#define IPCP_VJ_COMP 0x002d	/* current value for VJ compression option*/
+#define IPCP_VJ_COMP_OLD 0x0037	/* "old" (i.e, broken) value for VJ */
+				/* compression option*/ 
+#endif /* VJ_SUPPORT */
+
+typedef struct ipcp_options {
+    unsigned int neg_addr               :1; /* Negotiate IP Address? */
+    unsigned int old_addrs              :1; /* Use old (IP-Addresses) option? */
+    unsigned int req_addr               :1; /* Ask peer to send IP address? */
+#if 0 /* UNUSED */
+    unsigned int default_route          :1; /* Assign default route through interface? */
+    unsigned int replace_default_route  :1; /* Replace default route through interface? */
+#endif /* UNUSED */
+#if 0 /* UNUSED - PROXY ARP */
+    unsigned int proxy_arp              :1; /* Make proxy ARP entry for peer? */
+#endif /* UNUSED - PROXY ARP */
+#if VJ_SUPPORT
+    unsigned int neg_vj                 :1; /* Van Jacobson Compression? */
+    unsigned int old_vj                 :1; /* use old (short) form of VJ option? */
+    unsigned int cflag                  :1;
+#endif /* VJ_SUPPORT */
+    unsigned int accept_local           :1; /* accept peer's value for ouraddr */
+    unsigned int accept_remote          :1; /* accept peer's value for hisaddr */
+#if LWIP_DNS
+    unsigned int req_dns1               :1; /* Ask peer to send primary DNS address? */
+    unsigned int req_dns2               :1; /* Ask peer to send secondary DNS address? */
+#endif /* LWIP_DNS */
+
+    u32_t ouraddr, hisaddr;	/* Addresses in NETWORK BYTE ORDER */
+#if LWIP_DNS
+    u32_t dnsaddr[2];	/* Primary and secondary MS DNS entries */
+#endif /* LWIP_DNS */
+#if 0 /* UNUSED - WINS */
+    u32_t winsaddr[2];	/* Primary and secondary MS WINS entries */
+#endif /* UNUSED - WINS */
+
+#if VJ_SUPPORT
+    u16_t vj_protocol;		/* protocol value to use in VJ option */
+    u8_t  maxslotindex;		/* values for RFC1332 VJ compression neg. */
+#endif /* VJ_SUPPORT */
+} ipcp_options;
+
+#if 0 /* UNUSED, already defined by lwIP */
+char *ip_ntoa (u32_t);
+#endif /* UNUSED, already defined by lwIP */
+
+extern const struct protent ipcp_protent;
+
+#endif /* IPCP_H */
+#endif /* PPP_SUPPORT && PPP_IPV4_SUPPORT */
diff --git a/tools/sdk/include/lwip/netif/ppp/ipv6cp.h b/tools/sdk/include/lwip/netif/ppp/ipv6cp.h
new file mode 100755
index 00000000..540a7d18
--- /dev/null
+++ b/tools/sdk/include/lwip/netif/ppp/ipv6cp.h
@@ -0,0 +1,183 @@
+/*
+ * ipv6cp.h - PPP IPV6 Control Protocol.
+ *
+ * Copyright (c) 1999 Tommi Komulainen.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * 3. The name(s) of the authors of this software must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission.
+ *
+ * 4. Redistributions of any form whatsoever must retain the following
+ *    acknowledgment:
+ *    "This product includes software developed by Tommi Komulainen
+ *     ".
+ *
+ * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+/*  Original version, based on RFC2023 :
+
+    Copyright (c) 1995, 1996, 1997 Francis.Dupont@inria.fr, INRIA Rocquencourt,
+    Alain.Durand@imag.fr, IMAG,
+    Jean-Luc.Richier@imag.fr, IMAG-LSR.
+
+    Copyright (c) 1998, 1999 Francis.Dupont@inria.fr, GIE DYADE,
+    Alain.Durand@imag.fr, IMAG,
+    Jean-Luc.Richier@imag.fr, IMAG-LSR.
+
+    Ce travail a été fait au sein du GIE DYADE (Groupement d'Intérêt
+    Économique ayant pour membres BULL S.A. et l'INRIA).
+
+    Ce logiciel informatique est disponible aux conditions
+    usuelles dans la recherche, c'est-à-dire qu'il peut
+    être utilisé, copié, modifié, distribué à l'unique
+    condition que ce texte soit conservé afin que
+    l'origine de ce logiciel soit reconnue.
+
+    Le nom de l'Institut National de Recherche en Informatique
+    et en Automatique (INRIA), de l'IMAG, ou d'une personne morale
+    ou physique ayant participé à l'élaboration de ce logiciel ne peut
+    être utilisé sans son accord préalable explicite.
+
+    Ce logiciel est fourni tel quel sans aucune garantie,
+    support ou responsabilité d'aucune sorte.
+    Ce logiciel est dérivé de sources d'origine
+    "University of California at Berkeley" et
+    "Digital Equipment Corporation" couvertes par des copyrights.
+
+    L'Institut d'Informatique et de Mathématiques Appliquées de Grenoble (IMAG)
+    est une fédération d'unités mixtes de recherche du CNRS, de l'Institut National
+    Polytechnique de Grenoble et de l'Université Joseph Fourier regroupant
+    sept laboratoires dont le laboratoire Logiciels, Systèmes, Réseaux (LSR).
+
+    This work has been done in the context of GIE DYADE (joint R & D venture
+    between BULL S.A. and INRIA).
+
+    This software is available with usual "research" terms
+    with the aim of retain credits of the software. 
+    Permission to use, copy, modify and distribute this software for any
+    purpose and without fee is hereby granted, provided that the above
+    copyright notice and this permission notice appear in all copies,
+    and the name of INRIA, IMAG, or any contributor not be used in advertising
+    or publicity pertaining to this material without the prior explicit
+    permission. The software is provided "as is" without any
+    warranties, support or liabilities of any kind.
+    This software is derived from source code from
+    "University of California at Berkeley" and
+    "Digital Equipment Corporation" protected by copyrights.
+
+    Grenoble's Institute of Computer Science and Applied Mathematics (IMAG)
+    is a federation of seven research units funded by the CNRS, National
+    Polytechnic Institute of Grenoble and University Joseph Fourier.
+    The research unit in Software, Systems, Networks (LSR) is member of IMAG.
+*/
+
+/*
+ * Derived from :
+ *
+ *
+ * ipcp.h - IP Control Protocol definitions.
+ *
+ * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * 3. The name "Carnegie Mellon University" must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission. For permission or any legal
+ *    details, please contact
+ *      Office of Technology Transfer
+ *      Carnegie Mellon University
+ *      5000 Forbes Avenue
+ *      Pittsburgh, PA  15213-3890
+ *      (412) 268-4387, fax: (412) 268-7395
+ *      tech-transfer@andrew.cmu.edu
+ *
+ * 4. Redistributions of any form whatsoever must retain the following
+ *    acknowledgment:
+ *    "This product includes software developed by Computing Services
+ *     at Carnegie Mellon University (http://www.cmu.edu/computing/)."
+ *
+ * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE
+ * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ipv6cp.h,v 1.7 2002/12/04 23:03:32 paulus Exp $
+ */
+
+#include "lwip/opt.h"
+#if PPP_SUPPORT && PPP_IPV6_SUPPORT  /* don't build if not configured for use in lwipopts.h */
+
+#ifndef IPV6CP_H
+#define	IPV6CP_H
+
+#include "eui64.h"
+
+/*
+ * Options.
+ */
+#define CI_IFACEID	1	/* Interface Identifier */
+#ifdef IPV6CP_COMP
+#define CI_COMPRESSTYPE	2	/* Compression Type     */
+#endif /* IPV6CP_COMP */
+
+/* No compression types yet defined.
+ *#define IPV6CP_COMP	0x004f
+ */
+typedef struct ipv6cp_options {
+    unsigned int neg_ifaceid    :1;  /* Negotiate interface identifier? */
+    unsigned int req_ifaceid    :1;  /* Ask peer to send interface identifier? */
+    unsigned int accept_local   :1;  /* accept peer's value for iface id? */
+    unsigned int opt_local      :1;  /* ourtoken set by option */
+    unsigned int opt_remote     :1;  /* histoken set by option */
+    unsigned int use_ip         :1;  /* use IP as interface identifier */
+#if 0
+    unsigned int use_persistent :1;  /* use uniquely persistent value for address */
+#endif
+#ifdef IPV6CP_COMP
+    unsigned int neg_vj         :1;  /* Van Jacobson Compression? */
+#endif /* IPV6CP_COMP */
+
+#ifdef IPV6CP_COMP
+    u_short vj_protocol;        /* protocol value to use in VJ option */
+#endif /* IPV6CP_COMP */
+    eui64_t ourid, hisid;       /* Interface identifiers */
+} ipv6cp_options;
+
+extern const struct protent ipv6cp_protent;
+
+#endif /* IPV6CP_H */
+#endif /* PPP_SUPPORT && PPP_IPV6_SUPPORT */
diff --git a/tools/sdk/include/lwip/netif/ppp/lcp.h b/tools/sdk/include/lwip/netif/ppp/lcp.h
new file mode 100755
index 00000000..04970699
--- /dev/null
+++ b/tools/sdk/include/lwip/netif/ppp/lcp.h
@@ -0,0 +1,169 @@
+/*
+ * lcp.h - Link Control Protocol definitions.
+ *
+ * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * 3. The name "Carnegie Mellon University" must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission. For permission or any legal
+ *    details, please contact
+ *      Office of Technology Transfer
+ *      Carnegie Mellon University
+ *      5000 Forbes Avenue
+ *      Pittsburgh, PA  15213-3890
+ *      (412) 268-4387, fax: (412) 268-7395
+ *      tech-transfer@andrew.cmu.edu
+ *
+ * 4. Redistributions of any form whatsoever must retain the following
+ *    acknowledgment:
+ *    "This product includes software developed by Computing Services
+ *     at Carnegie Mellon University (http://www.cmu.edu/computing/)."
+ *
+ * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE
+ * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: lcp.h,v 1.20 2004/11/14 22:53:42 carlsonj Exp $
+ */
+
+#include "lwip/opt.h"
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifndef LCP_H
+#define	LCP_H
+
+#include "ppp.h"
+
+/*
+ * Options.
+ */
+#define CI_VENDOR	0	/* Vendor Specific */
+#define CI_MRU		1	/* Maximum Receive Unit */
+#define CI_ASYNCMAP	2	/* Async Control Character Map */
+#define CI_AUTHTYPE	3	/* Authentication Type */
+#define CI_QUALITY	4	/* Quality Protocol */
+#define CI_MAGICNUMBER	5	/* Magic Number */
+#define CI_PCOMPRESSION	7	/* Protocol Field Compression */
+#define CI_ACCOMPRESSION 8	/* Address/Control Field Compression */
+#define CI_FCSALTERN	9	/* FCS-Alternatives */
+#define CI_SDP		10	/* Self-Describing-Pad */
+#define CI_NUMBERED	11	/* Numbered-Mode */
+#define CI_CALLBACK	13	/* callback */
+#define CI_MRRU		17	/* max reconstructed receive unit; multilink */
+#define CI_SSNHF	18	/* short sequence numbers for multilink */
+#define CI_EPDISC	19	/* endpoint discriminator */
+#define CI_MPPLUS	22	/* Multi-Link-Plus-Procedure */
+#define CI_LDISC	23	/* Link-Discriminator */
+#define CI_LCPAUTH	24	/* LCP Authentication */
+#define CI_COBS		25	/* Consistent Overhead Byte Stuffing */
+#define CI_PREFELIS	26	/* Prefix Elision */
+#define CI_MPHDRFMT	27	/* MP Header Format */
+#define CI_I18N		28	/* Internationalization */
+#define CI_SDL		29	/* Simple Data Link */
+
+/*
+ * LCP-specific packet types (code numbers).
+ */
+#define PROTREJ		8	/* Protocol Reject */
+#define ECHOREQ		9	/* Echo Request */
+#define ECHOREP		10	/* Echo Reply */
+#define DISCREQ		11	/* Discard Request */
+#define IDENTIF		12	/* Identification */
+#define TIMEREM		13	/* Time Remaining */
+
+/* Value used as data for CI_CALLBACK option */
+#define CBCP_OPT	6	/* Use callback control protocol */
+
+#if 0 /* moved to opt.h */
+#define DEFMRU	1500		/* Try for this */
+#define MINMRU	128		/* No MRUs below this */
+#define MAXMRU	16384		/* Normally limit MRU to this */
+#endif /* moved to opt.h */
+
+/* An endpoint discriminator, used with multilink. */
+#define MAX_ENDP_LEN	20	/* maximum length of discriminator value */
+struct epdisc {
+    unsigned char	class_; /* -- The word "class" is reserved in C++. */
+    unsigned char	length;
+    unsigned char	value[MAX_ENDP_LEN];
+};
+
+/*
+ * The state of options is described by an lcp_options structure.
+ */
+typedef struct lcp_options {
+    unsigned int passive           :1; /* Don't die if we don't get a response */
+    unsigned int silent            :1; /* Wait for the other end to start first */
+    unsigned int restart           :1; /* Restart vs. exit after close */
+    unsigned int neg_mru           :1; /* Negotiate the MRU? */
+    unsigned int neg_asyncmap      :1; /* Negotiate the async map? */
+#if PAP_SUPPORT
+    unsigned int neg_upap          :1; /* Ask for UPAP authentication? */
+#endif /* PAP_SUPPORT */
+#if CHAP_SUPPORT
+    unsigned int neg_chap          :1; /* Ask for CHAP authentication? */
+#endif /* CHAP_SUPPORT */
+#if EAP_SUPPORT
+    unsigned int neg_eap           :1; /* Ask for EAP authentication? */
+#endif /* EAP_SUPPORT */
+    unsigned int neg_magicnumber   :1; /* Ask for magic number? */
+    unsigned int neg_pcompression  :1; /* HDLC Protocol Field Compression? */
+    unsigned int neg_accompression :1; /* HDLC Address/Control Field Compression? */
+#if LQR_SUPPORT
+    unsigned int neg_lqr           :1; /* Negotiate use of Link Quality Reports */
+#endif /* LQR_SUPPORT */
+    unsigned int neg_cbcp          :1; /* Negotiate use of CBCP */
+#ifdef HAVE_MULTILINK
+    unsigned int neg_mrru          :1; /* negotiate multilink MRRU */
+#endif /* HAVE_MULTILINK */
+    unsigned int neg_ssnhf         :1; /* negotiate short sequence numbers */
+    unsigned int neg_endpoint      :1; /* negotiate endpoint discriminator */
+
+    u16_t mru;			/* Value of MRU */
+#ifdef HAVE_MULTILINK
+    u16_t mrru;			/* Value of MRRU, and multilink enable */
+#endif /* MULTILINK */
+#if CHAP_SUPPORT
+    u8_t chap_mdtype;		/* which MD types (hashing algorithm) */
+#endif /* CHAP_SUPPORT */
+    u32_t asyncmap;		/* Value of async map */
+    u32_t magicnumber;
+    u8_t  numloops;		/* Number of loops during magic number neg. */
+#if LQR_SUPPORT
+    u32_t lqr_period;	/* Reporting period for LQR 1/100ths second */
+#endif /* LQR_SUPPORT */
+    struct epdisc endpoint;	/* endpoint discriminator */
+} lcp_options;
+
+void lcp_open(ppp_pcb *pcb);
+void lcp_close(ppp_pcb *pcb, const char *reason);
+void lcp_lowerup(ppp_pcb *pcb);
+void lcp_lowerdown(ppp_pcb *pcb);
+void lcp_sprotrej(ppp_pcb *pcb, u_char *p, int len);    /* send protocol reject */
+
+extern const struct protent lcp_protent;
+
+#if 0 /* moved to opt.h */
+/* Default number of times we receive our magic number from the peer
+   before deciding the link is looped-back. */
+#define DEFLOOPBACKFAIL	10
+#endif /* moved to opt.h */
+
+#endif /* LCP_H */
+#endif /* PPP_SUPPORT */
diff --git a/tools/sdk/include/lwip/netif/ppp/magic.h b/tools/sdk/include/lwip/netif/ppp/magic.h
new file mode 100755
index 00000000..678ff724
--- /dev/null
+++ b/tools/sdk/include/lwip/netif/ppp/magic.h
@@ -0,0 +1,122 @@
+/*
+ * magic.h - PPP Magic Number definitions.
+ *
+ * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * 3. The name "Carnegie Mellon University" must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission. For permission or any legal
+ *    details, please contact
+ *      Office of Technology Transfer
+ *      Carnegie Mellon University
+ *      5000 Forbes Avenue
+ *      Pittsburgh, PA  15213-3890
+ *      (412) 268-4387, fax: (412) 268-7395
+ *      tech-transfer@andrew.cmu.edu
+ *
+ * 4. Redistributions of any form whatsoever must retain the following
+ *    acknowledgment:
+ *    "This product includes software developed by Computing Services
+ *     at Carnegie Mellon University (http://www.cmu.edu/computing/)."
+ *
+ * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE
+ * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: magic.h,v 1.5 2003/06/11 23:56:26 paulus Exp $
+ */
+/*****************************************************************************
+* randm.h - Random number generator header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1998 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 98-05-29 Guy Lancaster , Global Election Systems Inc.
+*   Extracted from avos.
+*****************************************************************************/
+
+#include "lwip/opt.h"
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifndef MAGIC_H
+#define MAGIC_H
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+
+/*
+ * Initialize the random number generator.
+ */
+void magic_init(void);
+
+/*
+ * Randomize our random seed value.  To be called for truely random events
+ * such as user operations and network traffic.
+ */
+void magic_randomize(void);
+
+/*
+ * Return a new random number.
+ */
+u32_t magic(void);	/* Returns the next magic number */
+
+/*
+ * Fill buffer with random bytes
+ *
+ * Use the random pool to generate random data.  This degrades to pseudo
+ * random when used faster than randomness is supplied using magic_churnrand().
+ * Thus it's important to make sure that the results of this are not
+ * published directly because one could predict the next result to at
+ * least some degree.  Also, it's important to get a good seed before
+ * the first use.
+ */
+void magic_random_bytes(unsigned char *buf, u32_t buf_len);
+
+/*
+ * Return a new random number between 0 and (2^pow)-1 included.
+ */
+u32_t magic_pow(u8_t pow);
+
+#endif /* MAGIC_H */
+
+#endif /* PPP_SUPPORT */
diff --git a/tools/sdk/include/lwip/netif/ppp/mppe.h b/tools/sdk/include/lwip/netif/ppp/mppe.h
new file mode 100755
index 00000000..93086955
--- /dev/null
+++ b/tools/sdk/include/lwip/netif/ppp/mppe.h
@@ -0,0 +1,177 @@
+/*
+ * mppe.h - Definitions for MPPE
+ *
+ * Copyright (c) 2008 Paul Mackerras. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * 3. The name(s) of the authors of this software must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission.
+ *
+ * 4. Redistributions of any form whatsoever must retain the following
+ *    acknowledgment:
+ *    "This product includes software developed by Paul Mackerras
+ *     ".
+ *
+ * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "lwip/opt.h"
+#if PPP_SUPPORT && MPPE_SUPPORT  /* don't build if not configured for use in lwipopts.h */
+
+#ifndef MPPE_H
+#define MPPE_H
+
+#if LWIP_INCLUDED_POLARSSL_ARC4
+#include "netif/ppp/polarssl/arc4.h"
+#else
+#include "polarssl/arc4.h"
+#endif
+
+#define MPPE_PAD		4	/* MPPE growth per frame */
+#define MPPE_MAX_KEY_LEN	16	/* largest key length (128-bit) */
+
+/* option bits for ccp_options.mppe */
+#define MPPE_OPT_40		0x01	/* 40 bit */
+#define MPPE_OPT_128		0x02	/* 128 bit */
+#define MPPE_OPT_STATEFUL	0x04	/* stateful mode */
+/* unsupported opts */
+#define MPPE_OPT_56		0x08	/* 56 bit */
+#define MPPE_OPT_MPPC		0x10	/* MPPC compression */
+#define MPPE_OPT_D		0x20	/* Unknown */
+#define MPPE_OPT_UNSUPPORTED (MPPE_OPT_56|MPPE_OPT_MPPC|MPPE_OPT_D)
+#define MPPE_OPT_UNKNOWN	0x40	/* Bits !defined in RFC 3078 were set */
+
+/*
+ * This is not nice ... the alternative is a bitfield struct though.
+ * And unfortunately, we cannot share the same bits for the option
+ * names above since C and H are the same bit.  We could do a u_int32
+ * but then we have to do a htonl() all the time and/or we still need
+ * to know which octet is which.
+ */
+#define MPPE_C_BIT		0x01	/* MPPC */
+#define MPPE_D_BIT		0x10	/* Obsolete, usage unknown */
+#define MPPE_L_BIT		0x20	/* 40-bit */
+#define MPPE_S_BIT		0x40	/* 128-bit */
+#define MPPE_M_BIT		0x80	/* 56-bit, not supported */
+#define MPPE_H_BIT		0x01	/* Stateless (in a different byte) */
+
+/* Does not include H bit; used for least significant octet only. */
+#define MPPE_ALL_BITS (MPPE_D_BIT|MPPE_L_BIT|MPPE_S_BIT|MPPE_M_BIT|MPPE_H_BIT)
+
+/* Build a CI from mppe opts (see RFC 3078) */
+#define MPPE_OPTS_TO_CI(opts, ci)		\
+    do {					\
+	u_char *ptr = ci; /* u_char[4] */	\
+						\
+	/* H bit */				\
+	if (opts & MPPE_OPT_STATEFUL)		\
+	    *ptr++ = 0x0;			\
+	else					\
+	    *ptr++ = MPPE_H_BIT;		\
+	*ptr++ = 0;				\
+	*ptr++ = 0;				\
+						\
+	/* S,L bits */				\
+	*ptr = 0;				\
+	if (opts & MPPE_OPT_128)		\
+	    *ptr |= MPPE_S_BIT;			\
+	if (opts & MPPE_OPT_40)			\
+	    *ptr |= MPPE_L_BIT;			\
+	/* M,D,C bits not supported */		\
+    } while (/* CONSTCOND */ 0)
+
+/* The reverse of the above */
+#define MPPE_CI_TO_OPTS(ci, opts)		\
+    do {					\
+	const u_char *ptr = ci; /* u_char[4] */	\
+						\
+	opts = 0;				\
+						\
+	/* H bit */				\
+	if (!(ptr[0] & MPPE_H_BIT))		\
+	    opts |= MPPE_OPT_STATEFUL;		\
+						\
+	/* S,L bits */				\
+	if (ptr[3] & MPPE_S_BIT)		\
+	    opts |= MPPE_OPT_128;		\
+	if (ptr[3] & MPPE_L_BIT)		\
+	    opts |= MPPE_OPT_40;		\
+						\
+	/* M,D,C bits */			\
+	if (ptr[3] & MPPE_M_BIT)		\
+	    opts |= MPPE_OPT_56;		\
+	if (ptr[3] & MPPE_D_BIT)		\
+	    opts |= MPPE_OPT_D;			\
+	if (ptr[3] & MPPE_C_BIT)		\
+	    opts |= MPPE_OPT_MPPC;		\
+						\
+	/* Other bits */			\
+	if (ptr[0] & ~MPPE_H_BIT)		\
+	    opts |= MPPE_OPT_UNKNOWN;		\
+	if (ptr[1] || ptr[2])			\
+	    opts |= MPPE_OPT_UNKNOWN;		\
+	if (ptr[3] & ~MPPE_ALL_BITS)		\
+	    opts |= MPPE_OPT_UNKNOWN;		\
+    } while (/* CONSTCOND */ 0)
+
+/* Shared MPPE padding between MSCHAP and MPPE */
+#define SHA1_PAD_SIZE 40
+
+static const u8_t mppe_sha1_pad1[SHA1_PAD_SIZE] = {
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+static const u8_t mppe_sha1_pad2[SHA1_PAD_SIZE] = {
+  0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2,
+  0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2,
+  0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2,
+  0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2
+};
+
+/*
+ * State for an MPPE (de)compressor.
+ */
+typedef struct ppp_mppe_state {
+	arc4_context arc4;
+	u8_t master_key[MPPE_MAX_KEY_LEN];
+	u8_t session_key[MPPE_MAX_KEY_LEN];
+	u8_t keylen;                /* key length in bytes */
+	/* NB: 128-bit == 16, 40-bit == 8!
+	 * If we want to support 56-bit, the unit has to change to bits
+	 */
+	u8_t bits;                  /* MPPE control bits */
+	u16_t ccount;               /* 12-bit coherency count (seqno)  */
+	u16_t sanity_errors;        /* take down LCP if too many */
+	unsigned int stateful  :1;  /* stateful mode flag */
+	unsigned int discard   :1;  /* stateful mode packet loss flag */
+} ppp_mppe_state;
+
+void mppe_set_key(ppp_pcb *pcb, ppp_mppe_state *state, u8_t *key);
+void mppe_init(ppp_pcb *pcb, ppp_mppe_state *state, u8_t options);
+void mppe_comp_reset(ppp_pcb *pcb, ppp_mppe_state *state);
+err_t mppe_compress(ppp_pcb *pcb, ppp_mppe_state *state, struct pbuf **pb, u16_t protocol);
+void mppe_decomp_reset(ppp_pcb *pcb, ppp_mppe_state *state);
+err_t mppe_decompress(ppp_pcb *pcb, ppp_mppe_state *state, struct pbuf **pb);
+
+#endif /* MPPE_H */
+#endif /* PPP_SUPPORT && MPPE_SUPPORT */
diff --git a/tools/sdk/include/lwip/netif/ppp/polarssl/arc4.h b/tools/sdk/include/lwip/netif/ppp/polarssl/arc4.h
new file mode 100755
index 00000000..95d9b34a
--- /dev/null
+++ b/tools/sdk/include/lwip/netif/ppp/polarssl/arc4.h
@@ -0,0 +1,81 @@
+/**
+ * \file arc4.h
+ *
+ *  Based on XySSL: Copyright (C) 2006-2008  Christophe Devine
+ *
+ *  Copyright (C) 2009  Paul Bakker 
+ *
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *  
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in the
+ *      documentation and/or other materials provided with the distribution.
+ *    * Neither the names of PolarSSL or XySSL nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *  
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ *  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ *  TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ *  PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ *  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ *  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "lwip/opt.h"
+#if LWIP_INCLUDED_POLARSSL_ARC4
+
+#ifndef LWIP_INCLUDED_POLARSSL_ARC4_H
+#define LWIP_INCLUDED_POLARSSL_ARC4_H
+
+/**
+ * \brief          ARC4 context structure
+ */
+typedef struct
+{
+    int x;                      /*!< permutation index */
+    int y;                      /*!< permutation index */
+    unsigned char m[256];       /*!< permutation table */
+}
+arc4_context;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          ARC4 key schedule
+ *
+ * \param ctx      ARC4 context to be initialized
+ * \param key      the secret key
+ * \param keylen   length of the key
+ */
+void arc4_setup( arc4_context *ctx, unsigned char *key, int keylen );
+
+/**
+ * \brief          ARC4 cipher function
+ *
+ * \param ctx      ARC4 context
+ * \param buf      buffer to be processed
+ * \param buflen   amount of data in buf
+ */
+void arc4_crypt( arc4_context *ctx, unsigned char *buf, int buflen );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_INCLUDED_POLARSSL_ARC4_H */
+
+#endif /* LWIP_INCLUDED_POLARSSL_ARC4 */
diff --git a/tools/sdk/include/lwip/netif/ppp/polarssl/des.h b/tools/sdk/include/lwip/netif/ppp/polarssl/des.h
new file mode 100755
index 00000000..d0858bd8
--- /dev/null
+++ b/tools/sdk/include/lwip/netif/ppp/polarssl/des.h
@@ -0,0 +1,92 @@
+/**
+ * \file des.h
+ *
+ *  Based on XySSL: Copyright (C) 2006-2008  Christophe Devine
+ *
+ *  Copyright (C) 2009  Paul Bakker 
+ *
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *  
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in the
+ *      documentation and/or other materials provided with the distribution.
+ *    * Neither the names of PolarSSL or XySSL nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *  
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ *  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ *  TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ *  PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ *  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ *  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "lwip/opt.h"
+#if LWIP_INCLUDED_POLARSSL_DES
+
+#ifndef LWIP_INCLUDED_POLARSSL_DES_H
+#define LWIP_INCLUDED_POLARSSL_DES_H
+
+#define DES_ENCRYPT     1
+#define DES_DECRYPT     0
+
+/**
+ * \brief          DES context structure
+ */
+typedef struct
+{
+    int mode;                   /*!<  encrypt/decrypt   */
+    unsigned long sk[32];       /*!<  DES subkeys       */
+}
+des_context;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          DES key schedule (56-bit, encryption)
+ *
+ * \param ctx      DES context to be initialized
+ * \param key      8-byte secret key
+ */
+void des_setkey_enc( des_context *ctx, unsigned char key[8] );
+
+/**
+ * \brief          DES key schedule (56-bit, decryption)
+ *
+ * \param ctx      DES context to be initialized
+ * \param key      8-byte secret key
+ */
+void des_setkey_dec( des_context *ctx, unsigned char key[8] );
+
+/**
+ * \brief          DES-ECB block encryption/decryption
+ *
+ * \param ctx      DES context
+ * \param input    64-bit input block
+ * \param output   64-bit output block
+ */
+void des_crypt_ecb( des_context *ctx,
+                    const unsigned char input[8],
+                    unsigned char output[8] );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_INCLUDED_POLARSSL_DES_H */
+
+#endif /* LWIP_INCLUDED_POLARSSL_DES */
diff --git a/tools/sdk/include/lwip/netif/ppp/polarssl/md4.h b/tools/sdk/include/lwip/netif/ppp/polarssl/md4.h
new file mode 100755
index 00000000..a382f85a
--- /dev/null
+++ b/tools/sdk/include/lwip/netif/ppp/polarssl/md4.h
@@ -0,0 +1,97 @@
+/**
+ * \file md4.h
+ *
+ *  Based on XySSL: Copyright (C) 2006-2008  Christophe Devine
+ *
+ *  Copyright (C) 2009  Paul Bakker 
+ *
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *  
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in the
+ *      documentation and/or other materials provided with the distribution.
+ *    * Neither the names of PolarSSL or XySSL nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *  
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ *  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ *  TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ *  PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ *  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ *  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "lwip/opt.h"
+#if LWIP_INCLUDED_POLARSSL_MD4
+
+#ifndef LWIP_INCLUDED_POLARSSL_MD4_H
+#define LWIP_INCLUDED_POLARSSL_MD4_H
+
+/**
+ * \brief          MD4 context structure
+ */
+typedef struct
+{
+    unsigned long total[2];     /*!< number of bytes processed  */
+    unsigned long state[4];     /*!< intermediate digest state  */
+    unsigned char buffer[64];   /*!< data block being processed */
+}
+md4_context;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          MD4 context setup
+ *
+ * \param ctx      context to be initialized
+ */
+void md4_starts( md4_context *ctx );
+
+/**
+ * \brief          MD4 process buffer
+ *
+ * \param ctx      MD4 context
+ * \param input    buffer holding the  data
+ * \param ilen     length of the input data
+ */
+void md4_update( md4_context *ctx, const unsigned char *input, int ilen );
+
+/**
+ * \brief          MD4 final digest
+ *
+ * \param ctx      MD4 context
+ * \param output   MD4 checksum result
+ */
+void md4_finish( md4_context *ctx, unsigned char output[16] );
+
+/**
+ * \brief          Output = MD4( input buffer )
+ *
+ * \param input    buffer holding the  data
+ * \param ilen     length of the input data
+ * \param output   MD4 checksum result
+ */
+void md4( unsigned char *input, int ilen, unsigned char output[16] );
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_INCLUDED_POLARSSL_MD4_H */
+
+#endif /* LWIP_INCLUDED_POLARSSL_MD4 */
diff --git a/tools/sdk/include/lwip/netif/ppp/polarssl/md5.h b/tools/sdk/include/lwip/netif/ppp/polarssl/md5.h
new file mode 100755
index 00000000..a299d98c
--- /dev/null
+++ b/tools/sdk/include/lwip/netif/ppp/polarssl/md5.h
@@ -0,0 +1,96 @@
+/**
+ * \file md5.h
+ *
+ *  Based on XySSL: Copyright (C) 2006-2008  Christophe Devine
+ *
+ *  Copyright (C) 2009  Paul Bakker 
+ *
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *  
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in the
+ *      documentation and/or other materials provided with the distribution.
+ *    * Neither the names of PolarSSL or XySSL nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *  
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ *  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ *  TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ *  PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ *  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ *  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "lwip/opt.h"
+#if LWIP_INCLUDED_POLARSSL_MD5
+
+#ifndef LWIP_INCLUDED_POLARSSL_MD5_H
+#define LWIP_INCLUDED_POLARSSL_MD5_H
+
+/**
+ * \brief          MD5 context structure
+ */
+typedef struct
+{
+    unsigned long total[2];     /*!< number of bytes processed  */
+    unsigned long state[4];     /*!< intermediate digest state  */
+    unsigned char buffer[64];   /*!< data block being processed */
+}
+md5_context;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          MD5 context setup
+ *
+ * \param ctx      context to be initialized
+ */
+void md5_starts( md5_context *ctx );
+
+/**
+ * \brief          MD5 process buffer
+ *
+ * \param ctx      MD5 context
+ * \param input    buffer holding the  data
+ * \param ilen     length of the input data
+ */
+void md5_update( md5_context *ctx, const unsigned char *input, int ilen );
+
+/**
+ * \brief          MD5 final digest
+ *
+ * \param ctx      MD5 context
+ * \param output   MD5 checksum result
+ */
+void md5_finish( md5_context *ctx, unsigned char output[16] );
+
+/**
+ * \brief          Output = MD5( input buffer )
+ *
+ * \param input    buffer holding the  data
+ * \param ilen     length of the input data
+ * \param output   MD5 checksum result
+ */
+void md5( unsigned char *input, int ilen, unsigned char output[16] );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_INCLUDED_POLARSSL_MD5_H */
+
+#endif /* LWIP_INCLUDED_POLARSSL_MD5 */
diff --git a/tools/sdk/include/lwip/netif/ppp/polarssl/sha1.h b/tools/sdk/include/lwip/netif/ppp/polarssl/sha1.h
new file mode 100755
index 00000000..56d947c2
--- /dev/null
+++ b/tools/sdk/include/lwip/netif/ppp/polarssl/sha1.h
@@ -0,0 +1,96 @@
+/**
+ * \file sha1.h
+ *
+ *  Based on XySSL: Copyright (C) 2006-2008  Christophe Devine
+ *
+ *  Copyright (C) 2009  Paul Bakker 
+ *
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *  
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in the
+ *      documentation and/or other materials provided with the distribution.
+ *    * Neither the names of PolarSSL or XySSL nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *  
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ *  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ *  TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ *  PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ *  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ *  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "lwip/opt.h"
+#if LWIP_INCLUDED_POLARSSL_SHA1
+
+#ifndef LWIP_INCLUDED_POLARSSL_SHA1_H
+#define LWIP_INCLUDED_POLARSSL_SHA1_H
+
+/**
+ * \brief          SHA-1 context structure
+ */
+typedef struct
+{
+    unsigned long total[2];     /*!< number of bytes processed  */
+    unsigned long state[5];     /*!< intermediate digest state  */
+    unsigned char buffer[64];   /*!< data block being processed */
+}
+sha1_context;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          SHA-1 context setup
+ *
+ * \param ctx      context to be initialized
+ */
+void sha1_starts( sha1_context *ctx );
+
+/**
+ * \brief          SHA-1 process buffer
+ *
+ * \param ctx      SHA-1 context
+ * \param input    buffer holding the  data
+ * \param ilen     length of the input data
+ */
+void sha1_update( sha1_context *ctx, const unsigned char *input, int ilen );
+
+/**
+ * \brief          SHA-1 final digest
+ *
+ * \param ctx      SHA-1 context
+ * \param output   SHA-1 checksum result
+ */
+void sha1_finish( sha1_context *ctx, unsigned char output[20] );
+
+/**
+ * \brief          Output = SHA-1( input buffer )
+ *
+ * \param input    buffer holding the  data
+ * \param ilen     length of the input data
+ * \param output   SHA-1 checksum result
+ */
+void sha1( unsigned char *input, int ilen, unsigned char output[20] );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_INCLUDED_POLARSSL_SHA1_H */
+
+#endif /* LWIP_INCLUDED_POLARSSL_SHA1 */
diff --git a/tools/sdk/include/lwip/netif/ppp/ppp.h b/tools/sdk/include/lwip/netif/ppp/ppp.h
new file mode 100755
index 00000000..4a502054
--- /dev/null
+++ b/tools/sdk/include/lwip/netif/ppp/ppp.h
@@ -0,0 +1,573 @@
+/*****************************************************************************
+* ppp.h - Network Point to Point Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-11-05 Guy Lancaster , Global Election Systems Inc.
+*   Original derived from BSD codes.
+*****************************************************************************/
+
+#include "lwip/opt.h"
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifndef PPP_H
+#define PPP_H
+
+#include "lwip/def.h"
+#include "lwip/stats.h"
+#include "lwip/mem.h"
+#include "lwip/netif.h"
+#include "lwip/sys.h"
+#include "lwip/sio.h"
+#include "lwip/timers.h"
+#if PPP_IPV6_SUPPORT
+#include "lwip/ip6_addr.h"
+#endif /* PPP_IPV6_SUPPORT */
+
+/* Disable non-working or rarely used PPP feature, so rarely that we don't want to bloat opt.h with them */
+#ifndef PPP_OPTIONS
+#define PPP_OPTIONS         0
+#endif
+
+#ifndef PPP_NOTIFY
+#define PPP_NOTIFY          0
+#endif
+
+#ifndef PPP_REMOTENAME
+#define PPP_REMOTENAME      0
+#endif
+
+#ifndef PPP_IDLETIMELIMIT
+#define PPP_IDLETIMELIMIT   0
+#endif
+
+#ifndef PPP_LCP_ADAPTIVE
+#define PPP_LCP_ADAPTIVE    0
+#endif
+
+#ifndef PPP_MAXCONNECT
+#define PPP_MAXCONNECT      0
+#endif
+
+#ifndef PPP_ALLOWED_ADDRS
+#define PPP_ALLOWED_ADDRS   0
+#endif
+
+#ifndef PPP_PROTOCOLNAME
+#define PPP_PROTOCOLNAME    0
+#endif
+
+#ifndef PPP_STATS_SUPPORT
+#define PPP_STATS_SUPPORT   0
+#endif
+
+#ifndef DEFLATE_SUPPORT
+#define DEFLATE_SUPPORT     0
+#endif
+
+#ifndef BSDCOMPRESS_SUPPORT
+#define BSDCOMPRESS_SUPPORT 0
+#endif
+
+#ifndef PREDICTOR_SUPPORT
+#define PREDICTOR_SUPPORT   0
+#endif
+
+/*************************
+*** PUBLIC DEFINITIONS ***
+*************************/
+
+/*
+ * The basic PPP frame.
+ */
+#define PPP_HDRLEN	4	/* octets for standard ppp header */
+#define PPP_FCSLEN	2	/* octets for FCS */
+
+/*
+ * Values for phase.
+ */
+#define PPP_PHASE_DEAD          0
+#define PPP_PHASE_INITIALIZE    1
+#define PPP_PHASE_SERIALCONN    2
+#define PPP_PHASE_DORMANT       3
+#define PPP_PHASE_ESTABLISH     4
+#define PPP_PHASE_AUTHENTICATE  5
+#define PPP_PHASE_CALLBACK      6
+#define PPP_PHASE_NETWORK       7
+#define PPP_PHASE_RUNNING       8
+#define PPP_PHASE_TERMINATE     9
+#define PPP_PHASE_DISCONNECT    10
+#define PPP_PHASE_HOLDOFF       11
+#define PPP_PHASE_MASTER        12
+
+/* Error codes. */
+#define PPPERR_NONE         0  /* No error. */
+#define PPPERR_PARAM        1  /* Invalid parameter. */
+#define PPPERR_OPEN         2  /* Unable to open PPP session. */
+#define PPPERR_DEVICE       3  /* Invalid I/O device for PPP. */
+#define PPPERR_ALLOC        4  /* Unable to allocate resources. */
+#define PPPERR_USER         5  /* User interrupt. */
+#define PPPERR_CONNECT      6  /* Connection lost. */
+#define PPPERR_AUTHFAIL     7  /* Failed authentication challenge. */
+#define PPPERR_PROTOCOL     8  /* Failed to meet protocol. */
+#define PPPERR_PEERDEAD     9  /* Connection timeout */
+#define PPPERR_IDLETIMEOUT  10 /* Idle Timeout */
+#define PPPERR_CONNECTTIME  11 /* Max connect time reached */
+#define PPPERR_LOOPBACK     12 /* Loopback detected */
+
+/* Whether auth support is enabled at all */
+#define PPP_AUTH_SUPPORT (PAP_SUPPORT || CHAP_SUPPORT || EAP_SUPPORT)
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+
+/*
+ * Other headers require ppp_pcb definition for prototypes, but ppp_pcb
+ * require some structure definition from other headers as well, we are
+ * fixing the dependency loop here by declaring the ppp_pcb type then
+ * by including headers containing necessary struct definition for ppp_pcb
+ */
+typedef struct ppp_pcb_s ppp_pcb;
+
+/* Type definitions for BSD code. */
+#ifndef __u_char_defined
+typedef unsigned long  u_long;
+typedef unsigned int   u_int;
+typedef unsigned short u_short;
+typedef unsigned char  u_char;
+#endif
+
+#include "fsm.h"
+#include "lcp.h"
+#if CCP_SUPPORT
+#include "ccp.h"
+#endif /* CCP_SUPPORT */
+#if MPPE_SUPPORT
+#include "mppe.h"
+#endif /* MPPE_SUPPORT */
+#if PPP_IPV4_SUPPORT
+#include "ipcp.h"
+#endif /* PPP_IPV4_SUPPORT */
+#if PPP_IPV6_SUPPORT
+#include "ipv6cp.h"
+#endif /* PPP_IPV6_SUPPORT */
+#if PAP_SUPPORT
+#include "upap.h"
+#endif /* PAP_SUPPORT */
+#if CHAP_SUPPORT
+#include "chap-new.h"
+#endif /* CHAP_SUPPORT */
+#if EAP_SUPPORT
+#include "eap.h"
+#endif /* EAP_SUPPORT */
+#if VJ_SUPPORT
+#include "vj.h"
+#endif /* VJ_SUPPORT */
+
+/* Link status callback function prototype */
+typedef void (*ppp_link_status_cb_fn)(ppp_pcb *pcb, int err_code, void *ctx);
+
+/*
+ * PPP configuration.
+ */
+typedef struct ppp_settings_s {
+
+#if PPP_SERVER && PPP_AUTH_SUPPORT
+  unsigned int  auth_required       :1;      /* Peer is required to authenticate */
+  unsigned int  null_login          :1;      /* Username of "" and a password of "" are acceptable */
+#endif /* PPP_SERVER && PPP_AUTH_SUPPORT */
+#if PPP_REMOTENAME
+  unsigned int  explicit_remote     :1;      /* remote_name specified with remotename opt */
+#endif /* PPP_REMOTENAME */
+#if PAP_SUPPORT
+  unsigned int  refuse_pap          :1;      /* Don't proceed auth. with PAP */
+#endif /* PAP_SUPPORT */
+#if CHAP_SUPPORT
+  unsigned int  refuse_chap         :1;      /* Don't proceed auth. with CHAP */
+#endif /* CHAP_SUPPORT */
+#if MSCHAP_SUPPORT
+  unsigned int  refuse_mschap       :1;      /* Don't proceed auth. with MS-CHAP */
+  unsigned int  refuse_mschap_v2    :1;      /* Don't proceed auth. with MS-CHAPv2 */
+#endif /* MSCHAP_SUPPORT */
+#if EAP_SUPPORT
+  unsigned int  refuse_eap          :1;      /* Don't proceed auth. with EAP */
+#endif /* EAP_SUPPORT */
+#if LWIP_DNS
+  unsigned int  usepeerdns          :1;      /* Ask peer for DNS adds */
+#endif /* LWIP_DNS */
+  unsigned int  persist             :1;      /* Persist mode, always try to open the connection */
+#if PRINTPKT_SUPPORT
+  unsigned int  hide_password       :1;      /* Hide password in dumped packets */
+#endif /* PRINTPKT_SUPPORT */
+  unsigned int  noremoteip          :1;      /* Let him have no IP address */
+  unsigned int  lax_recv            :1;      /* accept control chars in asyncmap */
+  unsigned int  noendpoint          :1;      /* don't send/accept endpoint discriminator */
+#if PPP_LCP_ADAPTIVE
+  unsigned int lcp_echo_adaptive    :1;      /* request echo only if the link was idle */
+#endif /* PPP_LCP_ADAPTIVE */
+#if MPPE_SUPPORT
+  unsigned int require_mppe         :1;      /* Require MPPE (Microsoft Point to Point Encryption) */
+  unsigned int refuse_mppe_40       :1;      /* Allow MPPE 40-bit mode? */
+  unsigned int refuse_mppe_128      :1;      /* Allow MPPE 128-bit mode? */
+  unsigned int refuse_mppe_stateful :1;      /* Allow MPPE stateful mode? */
+#endif /* MPPE_SUPPORT */
+
+  u16_t  listen_time;                 /* time to listen first (ms), waiting for peer to send LCP packet */
+
+#if PPP_IDLETIMELIMIT
+  u16_t  idle_time_limit;             /* Disconnect if idle for this many seconds */
+#endif /* PPP_IDLETIMELIMIT */
+#if PPP_MAXCONNECT
+  u32_t  maxconnect;                  /* Maximum connect time (seconds) */
+#endif /* PPP_MAXCONNECT */
+
+#if PPP_AUTH_SUPPORT
+  /* auth data */
+  const char  *user;                   /* Username for PAP */
+  const char  *passwd;                 /* Password for PAP, secret for CHAP */
+#if PPP_REMOTENAME
+  char  remote_name[MAXNAMELEN   + 1]; /* Peer's name for authentication */
+#endif /* PPP_REMOTENAME */
+
+#if PAP_SUPPORT
+  u8_t  pap_timeout_time;        /* Timeout (seconds) for auth-req retrans. */
+  u8_t  pap_max_transmits;       /* Number of auth-reqs sent */
+#if PPP_SERVER
+  u8_t  pap_req_timeout;         /* Time to wait for auth-req from peer */
+#endif /* PPP_SERVER */
+#endif /* PAP_SUPPPORT */
+
+#if CHAP_SUPPORT
+  u8_t  chap_timeout_time;       /* Timeout (seconds) for retransmitting req */
+  u8_t  chap_max_transmits;      /* max # times to send challenge */
+#if PPP_SERVER
+  u8_t  chap_rechallenge_time;   /* Time to wait for auth-req from peer */
+#endif /* PPP_SERVER */
+#endif /* CHAP_SUPPPORT */
+
+#if EAP_SUPPORT
+  u8_t  eap_req_time;            /* Time to wait (for retransmit/fail) */
+  u8_t  eap_allow_req;           /* Max Requests allowed */
+#if PPP_SERVER
+  u8_t  eap_timeout_time;        /* Time to wait (for retransmit/fail) */
+  u8_t  eap_max_transmits;       /* Max Requests allowed */
+#endif /* PPP_SERVER */
+#endif /* EAP_SUPPORT */
+
+#endif /* PPP_AUTH_SUPPORT */
+
+  u8_t  fsm_timeout_time;            /* Timeout time in seconds */
+  u8_t  fsm_max_conf_req_transmits;  /* Maximum Configure-Request transmissions */
+  u8_t  fsm_max_term_transmits;      /* Maximum Terminate-Request transmissions */
+  u8_t  fsm_max_nak_loops;           /* Maximum number of nak loops tolerated */
+
+  u8_t  lcp_loopbackfail;     /* Number of times we receive our magic number from the peer
+                                 before deciding the link is looped-back. */
+  u8_t  lcp_echo_interval;    /* Interval between LCP echo-requests */
+  u8_t  lcp_echo_fails;       /* Tolerance to unanswered echo-requests */
+
+} ppp_settings;
+
+#if PPP_SERVER
+struct ppp_addrs {
+#if PPP_IPV4_SUPPORT
+  ip4_addr_t our_ipaddr, his_ipaddr, netmask;
+#if LWIP_DNS
+  ip4_addr_t dns1, dns2;
+#endif /* LWIP_DNS */
+#endif /* PPP_IPV4_SUPPORT */
+#if PPP_IPV6_SUPPORT
+  ip6_addr_t our6_ipaddr, his6_ipaddr;
+#endif /* PPP_IPV6_SUPPORT */
+};
+#endif /* PPP_SERVER */
+
+/*
+ * PPP interface control block.
+ */
+struct ppp_pcb_s {
+  /* -- below are data that will NOT be cleared between two sessions */
+  ppp_settings settings;
+  const struct link_callbacks *link_cb;
+  void *link_ctx_cb;
+  void (*link_status_cb)(ppp_pcb *pcb, int err_code, void *ctx);  /* Status change callback */
+#if PPP_NOTIFY_PHASE
+  void (*notify_phase_cb)(ppp_pcb *pcb, u8_t phase, void *ctx);   /* Notify phase callback */
+#endif /* PPP_NOTIFY_PHASE */
+  void *ctx_cb;                  /* Callbacks optional pointer */
+  struct netif *netif;           /* PPP interface */
+
+  /* -- below are data that will be cleared between two sessions */
+
+  /*
+   * phase must be the first member of cleared members, because it is used to know
+   * which part must not be cleared.
+   */
+  u8_t phase;                    /* where the link is at */
+  u8_t err_code;                 /* Code indicating why interface is down. */
+
+  /* flags */
+#if PPP_IPV4_SUPPORT
+  unsigned int ipcp_is_open            :1; /* haven't called np_finished() */
+  unsigned int ipcp_is_up              :1; /* have called ipcp_up() */
+  unsigned int if4_up                  :1; /* True when the IPv4 interface is up. */
+#if 0 /* UNUSED - PROXY ARP */
+  unsigned int proxy_arp_set           :1; /* Have created proxy arp entry */
+#endif /* UNUSED - PROXY ARP */
+#endif /* PPP_IPV4_SUPPORT */
+#if PPP_IPV6_SUPPORT
+  unsigned int ipv6cp_is_up            :1; /* have called ip6cp_up() */
+  unsigned int if6_up                  :1; /* True when the IPv6 interface is up. */
+#endif /* PPP_IPV6_SUPPORT */
+  unsigned int lcp_echo_timer_running  :1; /* set if a timer is running */
+#if VJ_SUPPORT
+  unsigned int vj_enabled              :1; /* Flag indicating VJ compression enabled. */
+#endif /* VJ_SUPPORT */
+#if CCP_SUPPORT
+  unsigned int ccp_all_rejected        :1; /* we rejected all peer's options */
+#endif /* CCP_SUPPORT */
+#if MPPE_SUPPORT
+  unsigned int mppe_keys_set           :1; /* Have the MPPE keys been set? */
+#endif /* MPPE_SUPPORT */
+
+#if PPP_AUTH_SUPPORT
+  /* auth data */
+#if PPP_SERVER && defined(HAVE_MULTILINK)
+  char peer_authname[MAXNAMELEN + 1]; /* The name by which the peer authenticated itself to us. */
+#endif /* PPP_SERVER && defined(HAVE_MULTILINK) */
+  u16_t auth_pending;        /* Records which authentication operations haven't completed yet. */
+  u16_t auth_done;           /* Records which authentication operations have been completed. */
+
+#if PAP_SUPPORT
+  upap_state upap;           /* PAP data */
+#endif /* PAP_SUPPORT */
+
+#if CHAP_SUPPORT
+  chap_client_state chap_client;  /* CHAP client data */
+#if PPP_SERVER
+  chap_server_state chap_server;  /* CHAP server data */
+#endif /* PPP_SERVER */
+#endif /* CHAP_SUPPORT */
+
+#if EAP_SUPPORT
+  eap_state eap;            /* EAP data */
+#endif /* EAP_SUPPORT */
+#endif /* PPP_AUTH_SUPPORT */
+
+  fsm lcp_fsm;                   /* LCP fsm structure */
+  lcp_options lcp_wantoptions;   /* Options that we want to request */
+  lcp_options lcp_gotoptions;    /* Options that peer ack'd */
+  lcp_options lcp_allowoptions;  /* Options we allow peer to request */
+  lcp_options lcp_hisoptions;    /* Options that we ack'd */
+  u16_t peer_mru;                /* currently negotiated peer MRU */
+  u8_t lcp_echos_pending;        /* Number of outstanding echo msgs */
+  u8_t lcp_echo_number;          /* ID number of next echo frame */
+
+  u8_t num_np_open;              /* Number of network protocols which we have opened. */
+  u8_t num_np_up;                /* Number of network protocols which have come up. */
+
+#if VJ_SUPPORT
+  struct vjcompress vj_comp;     /* Van Jacobson compression header. */
+#endif /* VJ_SUPPORT */
+
+#if CCP_SUPPORT
+  fsm ccp_fsm;                   /* CCP fsm structure */
+  ccp_options ccp_wantoptions;   /* what to request the peer to use */
+  ccp_options ccp_gotoptions;    /* what the peer agreed to do */
+  ccp_options ccp_allowoptions;  /* what we'll agree to do */
+  ccp_options ccp_hisoptions;    /* what we agreed to do */
+  u8_t ccp_localstate;           /* Local state (mainly for handling reset-reqs and reset-acks). */
+  u8_t ccp_receive_method;       /* Method chosen on receive path */
+  u8_t ccp_transmit_method;      /* Method chosen on transmit path */
+#if MPPE_SUPPORT
+  ppp_mppe_state mppe_comp;      /* MPPE "compressor" structure */
+  ppp_mppe_state mppe_decomp;    /* MPPE "decompressor" structure */
+#endif /* MPPE_SUPPORT */
+#endif /* CCP_SUPPORT */
+
+#if PPP_IPV4_SUPPORT
+  fsm ipcp_fsm;                   /* IPCP fsm structure */
+  ipcp_options ipcp_wantoptions;  /* Options that we want to request */
+  ipcp_options ipcp_gotoptions;   /* Options that peer ack'd */
+  ipcp_options ipcp_allowoptions; /* Options we allow peer to request */
+  ipcp_options ipcp_hisoptions;   /* Options that we ack'd */
+#endif /* PPP_IPV4_SUPPORT */
+
+#if PPP_IPV6_SUPPORT
+  fsm ipv6cp_fsm;                     /* IPV6CP fsm structure */
+  ipv6cp_options ipv6cp_wantoptions;  /* Options that we want to request */
+  ipv6cp_options ipv6cp_gotoptions;   /* Options that peer ack'd */
+  ipv6cp_options ipv6cp_allowoptions; /* Options we allow peer to request */
+  ipv6cp_options ipv6cp_hisoptions;   /* Options that we ack'd */
+#endif /* PPP_IPV6_SUPPORT */
+};
+
+/************************
+ *** PUBLIC FUNCTIONS ***
+ ************************/
+
+/*
+ * Set auth helper, optional, you can either fill ppp_pcb->settings.
+ *
+ * Warning: Using PPPAUTHTYPE_ANY might have security consequences.
+ * RFC 1994 says:
+ *
+ * In practice, within or associated with each PPP server, there is a
+ * database which associates "user" names with authentication
+ * information ("secrets").  It is not anticipated that a particular
+ * named user would be authenticated by multiple methods.  This would
+ * make the user vulnerable to attacks which negotiate the least secure
+ * method from among a set (such as PAP rather than CHAP).  If the same
+ * secret was used, PAP would reveal the secret to be used later with
+ * CHAP.
+ *
+ * Instead, for each user name there should be an indication of exactly
+ * one method used to authenticate that user name.  If a user needs to
+ * make use of different authentication methods under different
+ * circumstances, then distinct user names SHOULD be employed, each of
+ * which identifies exactly one authentication method.
+ *
+ */
+#define PPPAUTHTYPE_NONE      0x00
+#define PPPAUTHTYPE_PAP       0x01
+#define PPPAUTHTYPE_CHAP      0x02
+#define PPPAUTHTYPE_MSCHAP    0x04
+#define PPPAUTHTYPE_MSCHAP_V2 0x08
+#define PPPAUTHTYPE_EAP       0x10
+#define PPPAUTHTYPE_ANY       0xff
+void ppp_set_auth(ppp_pcb *pcb, u8_t authtype, const char *user, const char *passwd);
+
+/*
+ * Set a PPP interface as the default network interface
+ * (used to output all packets for which no specific route is found).
+ */
+#define ppp_set_default(ppp)         netif_set_default(ppp->netif)
+
+#if PPP_NOTIFY_PHASE
+/*
+ * Set a PPP notify phase callback.
+ *
+ * This can be used for example to set a LED pattern depending on the
+ * current phase of the PPP session.
+ */
+typedef void (*ppp_notify_phase_cb_fn)(ppp_pcb *pcb, u8_t phase, void *ctx);
+void ppp_set_notify_phase_callback(ppp_pcb *pcb, ppp_notify_phase_cb_fn notify_phase_cb);
+#endif /* PPP_NOTIFY_PHASE */
+
+/*
+ * Initiate a PPP connection.
+ *
+ * This can only be called if PPP is in the dead phase.
+ *
+ * Holdoff is the time to wait (in seconds) before initiating
+ * the connection.
+ *
+ * If this port connects to a modem, the modem connection must be
+ * established before calling this.
+ */
+err_t ppp_connect(ppp_pcb *pcb, u16_t holdoff);
+
+#if PPP_SERVER
+/*
+ * Listen for an incoming PPP connection.
+ *
+ * This can only be called if PPP is in the dead phase.
+ *
+ * Local and remote interface IP addresses, as well as DNS are
+ * provided through a previously filled struct ppp_addrs.
+ *
+ * If this port connects to a modem, the modem connection must be
+ * established before calling this.
+ */
+err_t ppp_listen(ppp_pcb *pcb, struct ppp_addrs *addrs);
+#endif /* PPP_SERVER */
+
+/*
+ * Initiate the end of a PPP connection.
+ * Any outstanding packets in the queues are dropped.
+ *
+ * Setting nocarrier to 1 close the PPP connection without initiating the
+ * shutdown procedure. Always using nocarrier = 0 is still recommended,
+ * this is going to take a little longer time if your link is down, but
+ * is a safer choice for the PPP state machine.
+ *
+ * Return 0 on success, an error code on failure.
+ */
+err_t ppp_close(ppp_pcb *pcb, u8_t nocarrier);
+
+/*
+ * Release the control block.
+ *
+ * This can only be called if PPP is in the dead phase.
+ *
+ * You must use ppp_close() before if you wish to terminate
+ * an established PPP session.
+ *
+ * Return 0 on success, an error code on failure.
+ */
+err_t ppp_free(ppp_pcb *pcb);
+
+/*
+ * PPP IOCTL commands.
+ *
+ * Get the up status - 0 for down, non-zero for up.  The argument must
+ * point to an int.
+ */
+#define PPPCTLG_UPSTATUS 0
+
+/*
+ * Get the PPP error code.  The argument must point to an int.
+ * Returns a PPPERR_* value.
+ */
+#define PPPCTLG_ERRCODE  1
+
+/*
+ * Get the fd associated with a PPP over serial
+ */
+#define PPPCTLG_FD       2
+
+/*
+ * Get and set parameters for the given connection.
+ * Return 0 on success, an error code on failure.
+ */
+err_t ppp_ioctl(ppp_pcb *pcb, u8_t cmd, void *arg);
+
+/* Get the PPP netif interface */
+#define ppp_netif(ppp)               (ppp->netif)
+
+/* Set an lwIP-style status-callback for the selected PPP device */
+#define ppp_set_netif_statuscallback(ppp, status_cb)       \
+        netif_set_status_callback(ppp->netif, status_cb);
+
+/* Set an lwIP-style link-callback for the selected PPP device */
+#define ppp_set_netif_linkcallback(ppp, link_cb)           \
+        netif_set_link_callback(ppp->netif, link_cb);
+
+#endif /* PPP_H */
+
+#endif /* PPP_SUPPORT */
diff --git a/tools/sdk/include/lwip/netif/ppp/ppp_impl.h b/tools/sdk/include/lwip/netif/ppp/ppp_impl.h
new file mode 100755
index 00000000..324f4b05
--- /dev/null
+++ b/tools/sdk/include/lwip/netif/ppp/ppp_impl.h
@@ -0,0 +1,632 @@
+/*****************************************************************************
+* ppp.h - Network Point to Point Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-11-05 Guy Lancaster , Global Election Systems Inc.
+*   Original derived from BSD codes.
+*****************************************************************************/
+#ifndef LWIP_HDR_PPP_IMPL_H
+#define LWIP_HDR_PPP_IMPL_H
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifdef PPP_INCLUDE_SETTINGS_HEADER
+#include "ppp_settings.h"
+#endif
+
+#include  /* formats */
+#include 
+#include 
+#include  /* strtol() */
+
+#include "lwip/netif.h"
+#include "lwip/def.h"
+#include "lwip/timers.h"
+
+#include "ppp.h"
+#include "pppdebug.h"
+
+/*
+ * Memory used for control packets.
+ *
+ * PPP_CTRL_PBUF_MAX_SIZE is the amount of memory we allocate when we
+ * cannot figure out how much we are going to use before filling the buffer.
+ */
+#if PPP_USE_PBUF_RAM
+#define PPP_CTRL_PBUF_TYPE       PBUF_RAM
+#define PPP_CTRL_PBUF_MAX_SIZE   512
+#else /* PPP_USE_PBUF_RAM */
+#define PPP_CTRL_PBUF_TYPE       PBUF_POOL
+#define PPP_CTRL_PBUF_MAX_SIZE   PBUF_POOL_BUFSIZE
+#endif /* PPP_USE_PBUF_RAM */
+
+/*
+ * The basic PPP frame.
+ */
+#define PPP_ADDRESS(p)	(((u_char *)(p))[0])
+#define PPP_CONTROL(p)	(((u_char *)(p))[1])
+#define PPP_PROTOCOL(p)	((((u_char *)(p))[2] << 8) + ((u_char *)(p))[3])
+
+/*
+ * Significant octet values.
+ */
+#define	PPP_ALLSTATIONS	0xff	/* All-Stations broadcast address */
+#define	PPP_UI		0x03	/* Unnumbered Information */
+#define	PPP_FLAG	0x7e	/* Flag Sequence */
+#define	PPP_ESCAPE	0x7d	/* Asynchronous Control Escape */
+#define	PPP_TRANS	0x20	/* Asynchronous transparency modifier */
+
+/*
+ * Protocol field values.
+ */
+#define PPP_IP		0x21	/* Internet Protocol */
+#if 0 /* UNUSED */
+#define PPP_AT		0x29	/* AppleTalk Protocol */
+#define PPP_IPX		0x2b	/* IPX protocol */
+#endif /* UNUSED */
+#if VJ_SUPPORT
+#define	PPP_VJC_COMP	0x2d	/* VJ compressed TCP */
+#define	PPP_VJC_UNCOMP	0x2f	/* VJ uncompressed TCP */
+#endif /* VJ_SUPPORT */
+#if PPP_IPV6_SUPPORT
+#define PPP_IPV6	0x57	/* Internet Protocol Version 6 */
+#endif /* PPP_IPV6_SUPPORT */
+#if CCP_SUPPORT
+#define PPP_COMP	0xfd	/* compressed packet */
+#endif /* CCP_SUPPORT */
+#define PPP_IPCP	0x8021	/* IP Control Protocol */
+#if 0 /* UNUSED */
+#define PPP_ATCP	0x8029	/* AppleTalk Control Protocol */
+#define PPP_IPXCP	0x802b	/* IPX Control Protocol */
+#endif /* UNUSED */
+#if PPP_IPV6_SUPPORT
+#define PPP_IPV6CP	0x8057	/* IPv6 Control Protocol */
+#endif /* PPP_IPV6_SUPPORT */
+#if CCP_SUPPORT
+#define PPP_CCP		0x80fd	/* Compression Control Protocol */
+#endif /* CCP_SUPPORT */
+#if ECP_SUPPORT
+#define PPP_ECP		0x8053	/* Encryption Control Protocol */
+#endif /* ECP_SUPPORT */
+#define PPP_LCP		0xc021	/* Link Control Protocol */
+#if PAP_SUPPORT
+#define PPP_PAP		0xc023	/* Password Authentication Protocol */
+#endif /* PAP_SUPPORT */
+#if LQR_SUPPORT
+#define PPP_LQR		0xc025	/* Link Quality Report protocol */
+#endif /* LQR_SUPPORT */
+#if CHAP_SUPPORT
+#define PPP_CHAP	0xc223	/* Cryptographic Handshake Auth. Protocol */
+#endif /* CHAP_SUPPORT */
+#if CBCP_SUPPORT
+#define PPP_CBCP	0xc029	/* Callback Control Protocol */
+#endif /* CBCP_SUPPORT */
+#if EAP_SUPPORT
+#define PPP_EAP		0xc227	/* Extensible Authentication Protocol */
+#endif /* EAP_SUPPORT */
+
+/*
+ * The following struct gives the addresses of procedures to call
+ * for a particular lower link level protocol.
+ */
+struct link_callbacks {
+  /* Start a connection (e.g. Initiate discovery phase) */
+  err_t (*connect) (ppp_pcb *pcb, void *ctx);
+#if PPP_SERVER
+  /* Listen for an incoming connection (Passive mode) */
+  err_t (*listen) (ppp_pcb *pcb, void *ctx, struct ppp_addrs *addrs);
+#endif /* PPP_SERVER */
+  /* End a connection (i.e. initiate disconnect phase) */
+  void (*disconnect) (ppp_pcb *pcb, void *ctx);
+  /* Free lower protocol control block */
+  err_t (*free) (ppp_pcb *pcb, void *ctx);
+  /* Write a pbuf to a ppp link, only used from PPP functions to send PPP packets. */
+  err_t (*write)(ppp_pcb *pcb, void *ctx, struct pbuf *p);
+  /* Send a packet from lwIP core (IPv4 or IPv6) */
+  err_t (*netif_output)(ppp_pcb *pcb, void *ctx, struct pbuf *p, u_short protocol);
+  /* configure the transmit-side characteristics of the PPP interface */
+  void (*send_config)(ppp_pcb *pcb, void *ctx, u32_t accm, int pcomp, int accomp);
+  /* confire the receive-side characteristics of the PPP interface */
+  void (*recv_config)(ppp_pcb *pcb, void *ctx, u32_t accm, int pcomp, int accomp);
+};
+
+/*
+ * What to do with network protocol (NP) packets.
+ */
+enum NPmode {
+    NPMODE_PASS,		/* pass the packet through */
+    NPMODE_DROP,		/* silently drop the packet */
+    NPMODE_ERROR,		/* return an error */
+    NPMODE_QUEUE		/* save it up for later. */
+};
+
+/*
+ * Statistics.
+ */
+#if PPP_STATS_SUPPORT
+struct pppstat	{
+    unsigned int ppp_ibytes;	/* bytes received */
+    unsigned int ppp_ipackets;	/* packets received */
+    unsigned int ppp_ierrors;	/* receive errors */
+    unsigned int ppp_obytes;	/* bytes sent */
+    unsigned int ppp_opackets;	/* packets sent */
+    unsigned int ppp_oerrors;	/* transmit errors */
+};
+
+#if VJ_SUPPORT
+struct vjstat {
+    unsigned int vjs_packets;	/* outbound packets */
+    unsigned int vjs_compressed; /* outbound compressed packets */
+    unsigned int vjs_searches;	/* searches for connection state */
+    unsigned int vjs_misses;	/* times couldn't find conn. state */
+    unsigned int vjs_uncompressedin; /* inbound uncompressed packets */
+    unsigned int vjs_compressedin; /* inbound compressed packets */
+    unsigned int vjs_errorin;	/* inbound unknown type packets */
+    unsigned int vjs_tossed;	/* inbound packets tossed because of error */
+};
+#endif /* VJ_SUPPORT */
+
+struct ppp_stats {
+    struct pppstat p;		/* basic PPP statistics */
+#if VJ_SUPPORT
+    struct vjstat vj;		/* VJ header compression statistics */
+#endif /* VJ_SUPPORT */
+};
+
+#if CCP_SUPPORT
+struct compstat {
+    unsigned int unc_bytes;	/* total uncompressed bytes */
+    unsigned int unc_packets;	/* total uncompressed packets */
+    unsigned int comp_bytes;	/* compressed bytes */
+    unsigned int comp_packets;	/* compressed packets */
+    unsigned int inc_bytes;	/* incompressible bytes */
+    unsigned int inc_packets;	/* incompressible packets */
+    unsigned int ratio;		/* recent compression ratio << 8 */
+};
+
+struct ppp_comp_stats {
+    struct compstat c;		/* packet compression statistics */
+    struct compstat d;		/* packet decompression statistics */
+};
+#endif /* CCP_SUPPORT */
+
+#endif /* PPP_STATS_SUPPORT */
+
+#if PPP_IDLETIMELIMIT
+/*
+ * The following structure records the time in seconds since
+ * the last NP packet was sent or received.
+ */
+struct ppp_idle {
+    time_t xmit_idle;		/* time since last NP packet sent */
+    time_t recv_idle;		/* time since last NP packet received */
+};
+#endif /* PPP_IDLETIMELIMIT */
+
+/* values for epdisc.class */
+#define EPD_NULL	0	/* null discriminator, no data */
+#define EPD_LOCAL	1
+#define EPD_IP		2
+#define EPD_MAC		3
+#define EPD_MAGIC	4
+#define EPD_PHONENUM	5
+
+/*
+ * Global variables.
+ */
+#ifdef HAVE_MULTILINK
+extern u8_t	multilink;	/* enable multilink operation */
+extern u8_t	doing_multilink;
+extern u8_t	multilink_master;
+extern u8_t	bundle_eof;
+extern u8_t	bundle_terminating;
+#endif
+
+#ifdef MAXOCTETS
+extern unsigned int maxoctets;	     /* Maximum octetes per session (in bytes) */
+extern int       maxoctets_dir;      /* Direction :
+				      0 - in+out (default)
+				      1 - in
+				      2 - out
+				      3 - max(in,out) */
+extern int       maxoctets_timeout;  /* Timeout for check of octets limit */
+#define PPP_OCTETS_DIRECTION_SUM        0
+#define PPP_OCTETS_DIRECTION_IN         1
+#define PPP_OCTETS_DIRECTION_OUT        2
+#define PPP_OCTETS_DIRECTION_MAXOVERAL  3
+/* same as previos, but little different on RADIUS side */
+#define PPP_OCTETS_DIRECTION_MAXSESSION 4
+#endif
+
+/* Data input may be used by CCP and ECP, remove this entry
+ * from struct protent to save some flash
+ */
+#define PPP_DATAINPUT 0
+
+/*
+ * The following struct gives the addresses of procedures to call
+ * for a particular protocol.
+ */
+struct protent {
+    u_short protocol;		/* PPP protocol number */
+    /* Initialization procedure */
+    void (*init) (ppp_pcb *pcb);
+    /* Process a received packet */
+    void (*input) (ppp_pcb *pcb, u_char *pkt, int len);
+    /* Process a received protocol-reject */
+    void (*protrej) (ppp_pcb *pcb);
+    /* Lower layer has come up */
+    void (*lowerup) (ppp_pcb *pcb);
+    /* Lower layer has gone down */
+    void (*lowerdown) (ppp_pcb *pcb);
+    /* Open the protocol */
+    void (*open) (ppp_pcb *pcb);
+    /* Close the protocol */
+    void (*close) (ppp_pcb *pcb, const char *reason);
+#if PRINTPKT_SUPPORT
+    /* Print a packet in readable form */
+    int  (*printpkt) (const u_char *pkt, int len,
+			  void (*printer) (void *, const char *, ...),
+			  void *arg);
+#endif /* PRINTPKT_SUPPORT */
+#if PPP_DATAINPUT
+    /* Process a received data packet */
+    void (*datainput) (ppp_pcb *pcb, u_char *pkt, int len);
+#endif /* PPP_DATAINPUT */
+#if PRINTPKT_SUPPORT
+    const char *name;		/* Text name of protocol */
+    const char *data_name;	/* Text name of corresponding data protocol */
+#endif /* PRINTPKT_SUPPORT */
+#if PPP_OPTIONS
+    option_t *options;		/* List of command-line options */
+    /* Check requested options, assign defaults */
+    void (*check_options) (void);
+#endif /* PPP_OPTIONS */
+#if DEMAND_SUPPORT
+    /* Configure interface for demand-dial */
+    int  (*demand_conf) (int unit);
+    /* Say whether to bring up link for this pkt */
+    int  (*active_pkt) (u_char *pkt, int len);
+#endif /* DEMAND_SUPPORT */
+};
+
+/* Table of pointers to supported protocols */
+extern const struct protent* const protocols[];
+
+
+/* Values for auth_pending, auth_done */
+#if PAP_SUPPORT
+#define PAP_WITHPEER	0x1
+#define PAP_PEER	0x2
+#endif /* PAP_SUPPORT */
+#if CHAP_SUPPORT
+#define CHAP_WITHPEER	0x4
+#define CHAP_PEER	0x8
+#endif /* CHAP_SUPPORT */
+#if EAP_SUPPORT
+#define EAP_WITHPEER	0x10
+#define EAP_PEER	0x20
+#endif /* EAP_SUPPORT */
+
+/* Values for auth_done only */
+#if CHAP_SUPPORT
+#define CHAP_MD5_WITHPEER	0x40
+#define CHAP_MD5_PEER		0x80
+#if MSCHAP_SUPPORT
+#define CHAP_MS_SHIFT		8	/* LSB position for MS auths */
+#define CHAP_MS_WITHPEER	0x100
+#define CHAP_MS_PEER		0x200
+#define CHAP_MS2_WITHPEER	0x400
+#define CHAP_MS2_PEER		0x800
+#endif /* MSCHAP_SUPPORT */
+#endif /* CHAP_SUPPORT */
+
+/* Supported CHAP protocols */
+#if CHAP_SUPPORT
+
+#if MSCHAP_SUPPORT
+#define CHAP_MDTYPE_SUPPORTED (MDTYPE_MICROSOFT_V2 | MDTYPE_MICROSOFT | MDTYPE_MD5)
+#else /* MSCHAP_SUPPORT */
+#define CHAP_MDTYPE_SUPPORTED (MDTYPE_MD5)
+#endif /* MSCHAP_SUPPORT */
+
+#else /* CHAP_SUPPORT */
+#define CHAP_MDTYPE_SUPPORTED (MDTYPE_NONE)
+#endif /* CHAP_SUPPORT */
+
+#if PPP_STATS_SUPPORT
+/*
+ * PPP statistics structure
+ */
+struct pppd_stats {
+    unsigned int	bytes_in;
+    unsigned int	bytes_out;
+    unsigned int	pkts_in;
+    unsigned int	pkts_out;
+};
+#endif /* PPP_STATS_SUPPORT */
+
+
+/*
+ * PPP private functions
+ */
+
+/*
+ * Functions called from lwIP core.
+ */
+
+/* initialize the PPP subsystem */
+int ppp_init(void);
+
+
+/*
+ * Functions called from PPP link protocols.
+ */
+
+/* Create a new PPP control block */
+ppp_pcb *ppp_new(struct netif *pppif, const struct link_callbacks *callbacks, void *link_ctx_cb,
+                 ppp_link_status_cb_fn link_status_cb, void *ctx_cb);
+
+/* Set a PPP PCB to its initial state */
+void ppp_clear(ppp_pcb *pcb);
+
+/* Initiate LCP open request */
+void ppp_start(ppp_pcb *pcb);
+
+/* Called when link failed to setup */
+void ppp_link_failed(ppp_pcb *pcb);
+
+/* Called when link is normally down (i.e. it was asked to end) */
+void ppp_link_end(ppp_pcb *pcb);
+
+/* function called to process input packet */
+void ppp_input(ppp_pcb *pcb, struct pbuf *pb);
+
+/* helper function, merge a pbuf chain into one pbuf */
+struct pbuf *ppp_singlebuf(struct pbuf *p);
+
+
+/*
+ * Functions called by PPP protocols.
+ */
+
+/* function called by all PPP subsystems to send packets */
+err_t ppp_write(ppp_pcb *pcb, struct pbuf *p);
+
+/* functions called by auth.c link_terminated() */
+void ppp_link_terminated(ppp_pcb *pcb);
+
+void new_phase(ppp_pcb *pcb, int p);
+
+int ppp_send_config(ppp_pcb *pcb, int mtu, u32_t accm, int pcomp, int accomp);
+int ppp_recv_config(ppp_pcb *pcb, int mru, u32_t accm, int pcomp, int accomp);
+
+#if PPP_IPV4_SUPPORT
+int sifaddr(ppp_pcb *pcb, u32_t our_adr, u32_t his_adr, u32_t netmask);
+int cifaddr(ppp_pcb *pcb, u32_t our_adr, u32_t his_adr);
+#if 0 /* UNUSED - PROXY ARP */
+int sifproxyarp(ppp_pcb *pcb, u32_t his_adr);
+int cifproxyarp(ppp_pcb *pcb, u32_t his_adr);
+#endif /* UNUSED - PROXY ARP */
+#if LWIP_DNS
+int sdns(ppp_pcb *pcb, u32_t ns1, u32_t ns2);
+int cdns(ppp_pcb *pcb, u32_t ns1, u32_t ns2);
+#endif /* LWIP_DNS */
+#if VJ_SUPPORT
+int sifvjcomp(ppp_pcb *pcb, int vjcomp, int cidcomp, int maxcid);
+#endif /* VJ_SUPPORT */
+int sifup(ppp_pcb *pcb);
+int sifdown (ppp_pcb *pcb);
+u32_t get_mask(u32_t addr);
+#endif /* PPP_IPV4_SUPPORT */
+
+#if PPP_IPV6_SUPPORT
+int sif6addr(ppp_pcb *pcb, eui64_t our_eui64, eui64_t his_eui64);
+int cif6addr(ppp_pcb *pcb, eui64_t our_eui64, eui64_t his_eui64);
+int sif6up(ppp_pcb *pcb);
+int sif6down (ppp_pcb *pcb);
+#endif /* PPP_IPV6_SUPPORT */
+
+#if DEMAND_SUPPORT
+int sifnpmode(ppp_pcb *pcb, int proto, enum NPmode mode);
+#endif /* DEMAND_SUPPORt */
+
+void netif_set_mtu(ppp_pcb *pcb, int mtu);
+int netif_get_mtu(ppp_pcb *pcb);
+
+#if CCP_SUPPORT
+#if 0 /* unused */
+int ccp_test(ppp_pcb *pcb, u_char *opt_ptr, int opt_len, int for_transmit);
+#endif /* unused */
+void ccp_set(ppp_pcb *pcb, u8_t isopen, u8_t isup, u8_t receive_method, u8_t transmit_method);
+void ccp_reset_comp(ppp_pcb *pcb);
+void ccp_reset_decomp(ppp_pcb *pcb);
+#if 0 /* unused */
+int ccp_fatal_error(ppp_pcb *pcb);
+#endif /* unused */
+#endif /* CCP_SUPPORT */
+
+#if PPP_IDLETIMELIMIT
+int get_idle_time(ppp_pcb *pcb, struct ppp_idle *ip);
+#endif /* PPP_IDLETIMELIMIT */
+
+#if DEMAND_SUPPORT
+int get_loop_output(void);
+#endif /* DEMAND_SUPPORT */
+
+/* Optional protocol names list, to make our messages a little more informative. */
+#if PPP_PROTOCOLNAME
+const char * protocol_name(int proto);
+#endif /* PPP_PROTOCOLNAME  */
+
+/* Optional stats support, to get some statistics on the PPP interface */
+#if PPP_STATS_SUPPORT
+void print_link_stats(void); /* Print stats, if available */
+void reset_link_stats(int u); /* Reset (init) stats when link goes up */
+void update_link_stats(int u); /* Get stats at link termination */
+#endif /* PPP_STATS_SUPPORT */
+
+
+
+/*
+ * Inline versions of get/put char/short/long.
+ * Pointer is advanced; we assume that both arguments
+ * are lvalues and will already be in registers.
+ * cp MUST be u_char *.
+ */
+#define GETCHAR(c, cp) { \
+	(c) = *(cp)++; \
+}
+#define PUTCHAR(c, cp) { \
+	*(cp)++ = (u_char) (c); \
+}
+#define GETSHORT(s, cp) { \
+	(s) = *(cp)++ << 8; \
+	(s) |= *(cp)++; \
+}
+#define PUTSHORT(s, cp) { \
+	*(cp)++ = (u_char) ((s) >> 8); \
+	*(cp)++ = (u_char) (s); \
+}
+#define GETLONG(l, cp) { \
+	(l) = *(cp)++ << 8; \
+	(l) |= *(cp)++; (l) <<= 8; \
+	(l) |= *(cp)++; (l) <<= 8; \
+	(l) |= *(cp)++; \
+}
+#define PUTLONG(l, cp) { \
+	*(cp)++ = (u_char) ((l) >> 24); \
+	*(cp)++ = (u_char) ((l) >> 16); \
+	*(cp)++ = (u_char) ((l) >> 8); \
+	*(cp)++ = (u_char) (l); \
+}
+
+#define INCPTR(n, cp)	((cp) += (n))
+#define DECPTR(n, cp)	((cp) -= (n))
+
+/*
+ * System dependent definitions for user-level 4.3BSD UNIX implementation.
+ */
+#define TIMEOUT(f, a, t)        do { sys_untimeout((f), (a)); sys_timeout((t)*1000, (f), (a)); } while(0)
+#define TIMEOUTMS(f, a, t)      do { sys_untimeout((f), (a)); sys_timeout((t), (f), (a)); } while(0)
+#define UNTIMEOUT(f, a)         sys_untimeout((f), (a))
+
+#define BZERO(s, n)		memset(s, 0, n)
+#define	BCMP(s1, s2, l)		memcmp(s1, s2, l)
+
+#define PRINTMSG(m, l)		{ ppp_info("Remote message: %0.*v", l, m); }
+
+/*
+ * MAKEHEADER - Add Header fields to a packet.
+ */
+#define MAKEHEADER(p, t) { \
+    PUTCHAR(PPP_ALLSTATIONS, p); \
+    PUTCHAR(PPP_UI, p); \
+    PUTSHORT(t, p); }
+
+/* Procedures exported from auth.c */
+void link_required(ppp_pcb *pcb);     /* we are starting to use the link */
+void link_terminated(ppp_pcb *pcb);   /* we are finished with the link */
+void link_down(ppp_pcb *pcb);	      /* the LCP layer has left the Opened state */
+void upper_layers_down(ppp_pcb *pcb); /* take all NCPs down */
+void link_established(ppp_pcb *pcb);  /* the link is up; authenticate now */
+void start_networks(ppp_pcb *pcb);    /* start all the network control protos */
+void continue_networks(ppp_pcb *pcb); /* start network [ip, etc] control protos */
+#if PPP_AUTH_SUPPORT
+#if PPP_SERVER
+int auth_check_passwd(ppp_pcb *pcb, char *auser, int userlen, char *apasswd, int passwdlen, const char **msg, int *msglen);
+                                /* check the user name and passwd against configuration */
+void auth_peer_fail(ppp_pcb *pcb, int protocol);
+				/* peer failed to authenticate itself */
+void auth_peer_success(ppp_pcb *pcb, int protocol, int prot_flavor, const char *name, int namelen);
+				/* peer successfully authenticated itself */
+#endif /* PPP_SERVER */
+void auth_withpeer_fail(ppp_pcb *pcb, int protocol);
+				/* we failed to authenticate ourselves */
+void auth_withpeer_success(ppp_pcb *pcb, int protocol, int prot_flavor);
+				/* we successfully authenticated ourselves */
+#endif /* PPP_AUTH_SUPPORT */
+void np_up(ppp_pcb *pcb, int proto);    /* a network protocol has come up */
+void np_down(ppp_pcb *pcb, int proto);  /* a network protocol has gone down */
+void np_finished(ppp_pcb *pcb, int proto); /* a network protocol no longer needs link */
+#if PPP_AUTH_SUPPORT
+int get_secret(ppp_pcb *pcb, const char *client, const char *server, char *secret, int *secret_len, int am_server);
+				/* get "secret" for chap */
+#endif /* PPP_AUTH_SUPPORT */
+
+/* Procedures exported from ipcp.c */
+/* int parse_dotted_ip (char *, u32_t *); */
+
+/* Procedures exported from demand.c */
+#if DEMAND_SUPPORT
+void demand_conf (void);	/* config interface(s) for demand-dial */
+void demand_block (void);	/* set all NPs to queue up packets */
+void demand_unblock (void); /* set all NPs to pass packets */
+void demand_discard (void); /* set all NPs to discard packets */
+void demand_rexmit (int, u32_t); /* retransmit saved frames for an NP*/
+int  loop_chars (unsigned char *, int); /* process chars from loopback */
+int  loop_frame (unsigned char *, int); /* should we bring link up? */
+#endif /* DEMAND_SUPPORT */
+
+/* Procedures exported from multilink.c */
+#ifdef HAVE_MULTILINK
+void mp_check_options (void); /* Check multilink-related options */
+int  mp_join_bundle (void);  /* join our link to an appropriate bundle */
+void mp_exit_bundle (void);  /* have disconnected our link from bundle */
+void mp_bundle_terminated (void);
+char *epdisc_to_str (struct epdisc *); /* string from endpoint discrim. */
+int  str_to_epdisc (struct epdisc *, char *); /* endpt disc. from str */
+#else
+#define mp_bundle_terminated()	/* nothing */
+#define mp_exit_bundle()	/* nothing */
+#define doing_multilink		0
+#define multilink_master	0
+#endif
+
+/* Procedures exported from utils.c. */
+void ppp_print_string(const u_char *p, int len, void (*printer) (void *, const char *, ...), void *arg);   /* Format a string for output */
+int ppp_slprintf(char *buf, int buflen, const char *fmt, ...);            /* sprintf++ */
+int ppp_vslprintf(char *buf, int buflen, const char *fmt, va_list args);  /* vsprintf++ */
+size_t ppp_strlcpy(char *dest, const char *src, size_t len);        /* safe strcpy */
+size_t ppp_strlcat(char *dest, const char *src, size_t len);        /* safe strncpy */
+void ppp_dbglog(const char *fmt, ...);    /* log a debug message */
+void ppp_info(const char *fmt, ...);      /* log an informational message */
+void ppp_notice(const char *fmt, ...);    /* log a notice-level message */
+void ppp_warn(const char *fmt, ...);      /* log a warning message */
+void ppp_error(const char *fmt, ...);     /* log an error message */
+void ppp_fatal(const char *fmt, ...);     /* log an error message and die(1) */
+#if PRINTPKT_SUPPORT
+void ppp_dump_packet(const char *tag, unsigned char *p, int len);
+                                /* dump packet to debug log if interesting */
+#endif /* PRINTPKT_SUPPORT */
+
+
+#endif /* PPP_SUPPORT */
+#endif /* LWIP_HDR_PPP_IMPL_H */
diff --git a/tools/sdk/include/lwip/netif/ppp/pppcrypt.h b/tools/sdk/include/lwip/netif/ppp/pppcrypt.h
new file mode 100755
index 00000000..ef2e87de
--- /dev/null
+++ b/tools/sdk/include/lwip/netif/ppp/pppcrypt.h
@@ -0,0 +1,43 @@
+/*
+ * pppcrypt.c - PPP/DES linkage for MS-CHAP and EAP SRP-SHA1
+ *
+ * Extracted from chap_ms.c by James Carlson.
+ *
+ * Copyright (c) 1995 Eric Rosenquist.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * 3. The name(s) of the authors of this software must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission.
+ *
+ * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "lwip/opt.h"
+#if PPP_SUPPORT && MSCHAP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifndef PPPCRYPT_H
+#define	PPPCRYPT_H
+
+void pppcrypt_56_to_64_bit_key(u_char *key, u_char *des_key);
+
+#endif /* PPPCRYPT_H */
+
+#endif /* PPP_SUPPORT && MSCHAP_SUPPORT */
diff --git a/tools/sdk/include/lwip/netif/ppp/pppdebug.h b/tools/sdk/include/lwip/netif/ppp/pppdebug.h
new file mode 100755
index 00000000..e35c8e09
--- /dev/null
+++ b/tools/sdk/include/lwip/netif/ppp/pppdebug.h
@@ -0,0 +1,80 @@
+/*****************************************************************************
+* pppdebug.h - System debugging utilities.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1998 Global Election Systems Inc.
+* portions Copyright (c) 2001 by Cognizant Pty Ltd.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY (please don't use tabs!)
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 98-07-29 Guy Lancaster , Global Election Systems Inc.
+*   Original.
+*
+*****************************************************************************
+*/
+
+#include "lwip/opt.h"
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifndef PPPDEBUG_H
+#define PPPDEBUG_H
+
+/* Trace levels. */
+#define LOG_CRITICAL  (PPP_DEBUG | LWIP_DBG_LEVEL_SEVERE)
+#define LOG_ERR       (PPP_DEBUG | LWIP_DBG_LEVEL_SEVERE)
+#define LOG_NOTICE    (PPP_DEBUG | LWIP_DBG_LEVEL_WARNING)
+#define LOG_WARNING   (PPP_DEBUG | LWIP_DBG_LEVEL_WARNING)
+#define LOG_INFO      (PPP_DEBUG)
+#define LOG_DETAIL    (PPP_DEBUG)
+#define LOG_DEBUG     (PPP_DEBUG)
+
+#if PPP_DEBUG
+
+#define MAINDEBUG(a)    LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING, a)
+#define SYSDEBUG(a)     LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING, a)
+#define FSMDEBUG(a)     LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING, a)
+#define LCPDEBUG(a)     LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING, a)
+#define IPCPDEBUG(a)    LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING, a)
+#define IPV6CPDEBUG(a)  LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING, a)
+#define UPAPDEBUG(a)    LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING, a)
+#define CHAPDEBUG(a)    LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING, a)
+#define PPPDEBUG(a, b)  LWIP_DEBUGF(a, b)
+
+#else /* PPP_DEBUG */
+
+#define MAINDEBUG(a)
+#define SYSDEBUG(a)
+#define FSMDEBUG(a)
+#define LCPDEBUG(a)
+#define IPCPDEBUG(a)
+#define IPV6CPDEBUG(a)
+#define UPAPDEBUG(a)
+#define CHAPDEBUG(a)
+#define PPPDEBUG(a, b)
+
+#endif /* PPP_DEBUG */
+
+#endif /* PPPDEBUG_H */
+
+#endif /* PPP_SUPPORT */
diff --git a/tools/sdk/include/lwip/netif/ppp/pppoe.h b/tools/sdk/include/lwip/netif/ppp/pppoe.h
new file mode 100755
index 00000000..b1dd2fd9
--- /dev/null
+++ b/tools/sdk/include/lwip/netif/ppp/pppoe.h
@@ -0,0 +1,179 @@
+/*****************************************************************************
+* pppoe.h - PPP Over Ethernet implementation for lwIP.
+*
+* Copyright (c) 2006 by Marc Boucher, Services Informatiques (MBSI) inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 06-01-01 Marc Boucher 
+*   Ported to lwIP.
+*****************************************************************************/
+
+
+
+/* based on NetBSD: if_pppoe.c,v 1.64 2006/01/31 23:50:15 martin Exp */
+
+/*-
+ * Copyright (c) 2002 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Martin Husemann .
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "lwip/opt.h"
+#if PPP_SUPPORT && PPPOE_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifndef PPP_OE_H
+#define PPP_OE_H
+
+#include "ppp.h"
+#include "netif/etharp.h"
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct pppoehdr {
+  PACK_STRUCT_FLD_8(u8_t vertype);
+  PACK_STRUCT_FLD_8(u8_t code);
+  PACK_STRUCT_FIELD(u16_t session);
+  PACK_STRUCT_FIELD(u16_t plen);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct pppoetag {
+  PACK_STRUCT_FIELD(u16_t tag);
+  PACK_STRUCT_FIELD(u16_t len);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+
+#define PPPOE_STATE_INITIAL   0
+#define PPPOE_STATE_PADI_SENT 1
+#define PPPOE_STATE_PADR_SENT 2
+#define PPPOE_STATE_SESSION   3
+/* passive */
+#define PPPOE_STATE_PADO_SENT 1
+
+#define PPPOE_HEADERLEN       sizeof(struct pppoehdr)
+#define PPPOE_VERTYPE         0x11    /* VER=1, TYPE = 1 */
+
+#define PPPOE_TAG_EOL         0x0000  /* end of list */
+#define PPPOE_TAG_SNAME       0x0101  /* service name */
+#define PPPOE_TAG_ACNAME      0x0102  /* access concentrator name */
+#define PPPOE_TAG_HUNIQUE     0x0103  /* host unique */
+#define PPPOE_TAG_ACCOOKIE    0x0104  /* AC cookie */
+#define PPPOE_TAG_VENDOR      0x0105  /* vendor specific */
+#define PPPOE_TAG_RELAYSID    0x0110  /* relay session id */
+#define PPPOE_TAG_SNAME_ERR   0x0201  /* service name error */
+#define PPPOE_TAG_ACSYS_ERR   0x0202  /* AC system error */
+#define PPPOE_TAG_GENERIC_ERR 0x0203  /* gerneric error */
+
+#define PPPOE_CODE_PADI       0x09    /* Active Discovery Initiation */
+#define PPPOE_CODE_PADO       0x07    /* Active Discovery Offer */
+#define PPPOE_CODE_PADR       0x19    /* Active Discovery Request */
+#define PPPOE_CODE_PADS       0x65    /* Active Discovery Session confirmation */
+#define PPPOE_CODE_PADT       0xA7    /* Active Discovery Terminate */
+
+#ifndef PPPOE_MAX_AC_COOKIE_LEN
+#define PPPOE_MAX_AC_COOKIE_LEN   64
+#endif
+
+struct pppoe_softc {
+  struct pppoe_softc *next;
+  struct netif *sc_ethif;      /* ethernet interface we are using */
+  ppp_pcb *pcb;                /* PPP PCB */
+
+  struct eth_addr sc_dest;     /* hardware address of concentrator */
+  u16_t sc_session;            /* PPPoE session id */
+  u8_t sc_state;               /* discovery phase or session connected */
+
+#ifdef PPPOE_TODO
+  u8_t *sc_service_name;       /* if != NULL: requested name of service */
+  u8_t *sc_concentrator_name;  /* if != NULL: requested concentrator id */
+#endif /* PPPOE_TODO */
+  u8_t sc_ac_cookie[PPPOE_MAX_AC_COOKIE_LEN]; /* content of AC cookie we must echo back */
+  u8_t sc_ac_cookie_len;       /* length of cookie data */
+#ifdef PPPOE_SERVER
+  u8_t *sc_hunique;            /* content of host unique we must echo back */
+  u8_t sc_hunique_len;         /* length of host unique */
+#endif
+  u8_t sc_padi_retried;        /* number of PADI retries already done */
+  u8_t sc_padr_retried;        /* number of PADR retries already done */
+};
+
+
+#define pppoe_init() /* compatibility define, no initialization needed */
+
+ppp_pcb *pppoe_create(struct netif *pppif,
+       struct netif *ethif,
+       const char *service_name, const char *concentrator_name,
+       ppp_link_status_cb_fn link_status_cb, void *ctx_cb);
+
+/*
+ * Functions called from lwIP
+ * DO NOT CALL FROM lwIP USER APPLICATION.
+ */
+void pppoe_disc_input(struct netif *netif, struct pbuf *p);
+void pppoe_data_input(struct netif *netif, struct pbuf *p);
+
+#endif /* PPP_OE_H */
+
+#endif /* PPP_SUPPORT && PPPOE_SUPPORT */
diff --git a/tools/sdk/include/lwip/netif/ppp/pppol2tp.h b/tools/sdk/include/lwip/netif/ppp/pppol2tp.h
new file mode 100755
index 00000000..097b4d18
--- /dev/null
+++ b/tools/sdk/include/lwip/netif/ppp/pppol2tp.h
@@ -0,0 +1,201 @@
+/**
+ * @file
+ * Network Point to Point Protocol over Layer 2 Tunneling Protocol header file.
+ *
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#include "lwip/opt.h"
+#if PPP_SUPPORT && PPPOL2TP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifndef PPPOL2TP_H_
+#define PPPOL2TP_H_
+
+#include "ppp.h"
+
+/* Timeout */
+#define PPPOL2TP_CONTROL_TIMEOUT         (5*1000)  /* base for quick timeout calculation */
+#define PPPOL2TP_SLOW_RETRY              (60*1000) /* persistent retry interval */
+
+#define PPPOL2TP_MAXSCCRQ                4         /* retry SCCRQ four times (quickly) */
+#define PPPOL2TP_MAXICRQ                 4         /* retry IRCQ four times */
+#define PPPOL2TP_MAXICCN                 4         /* retry ICCN four times */
+
+/* L2TP header flags */
+#define PPPOL2TP_HEADERFLAG_CONTROL      0x8000
+#define PPPOL2TP_HEADERFLAG_LENGTH       0x4000
+#define PPPOL2TP_HEADERFLAG_SEQUENCE     0x0800
+#define PPPOL2TP_HEADERFLAG_OFFSET       0x0200
+#define PPPOL2TP_HEADERFLAG_PRIORITY     0x0100
+#define PPPOL2TP_HEADERFLAG_VERSION      0x0002
+
+/* Mandatory bits for control: Control, Length, Sequence, Version 2 */
+#define PPPOL2TP_HEADERFLAG_CONTROL_MANDATORY     (PPPOL2TP_HEADERFLAG_CONTROL|PPPOL2TP_HEADERFLAG_LENGTH|PPPOL2TP_HEADERFLAG_SEQUENCE|PPPOL2TP_HEADERFLAG_VERSION)
+/* Forbidden bits for control: Offset, Priority */
+#define PPPOL2TP_HEADERFLAG_CONTROL_FORBIDDEN     (PPPOL2TP_HEADERFLAG_OFFSET|PPPOL2TP_HEADERFLAG_PRIORITY)
+
+/* Mandatory bits for data: Version 2 */
+#define PPPOL2TP_HEADERFLAG_DATA_MANDATORY        (PPPOL2TP_HEADERFLAG_VERSION)
+
+/* AVP (Attribute Value Pair) header */
+#define PPPOL2TP_AVPHEADERFLAG_MANDATORY  0x8000
+#define PPPOL2TP_AVPHEADERFLAG_HIDDEN     0x4000
+#define PPPOL2TP_AVPHEADERFLAG_LENGTHMASK 0x03ff
+
+/* -- AVP - Message type */
+#define PPPOL2TP_AVPTYPE_MESSAGE      0 /* Message type */
+
+/* Control Connection Management */
+#define PPPOL2TP_MESSAGETYPE_SCCRQ    1 /* Start Control Connection Request */
+#define PPPOL2TP_MESSAGETYPE_SCCRP    2 /* Start Control Connection Reply */
+#define PPPOL2TP_MESSAGETYPE_SCCCN    3 /* Start Control Connection Connected */
+#define PPPOL2TP_MESSAGETYPE_STOPCCN  4 /* Stop Control Connection Notification */
+#define PPPOL2TP_MESSAGETYPE_HELLO    6 /* Hello */
+/* Call Management */
+#define PPPOL2TP_MESSAGETYPE_OCRQ     7 /* Outgoing Call Request */
+#define PPPOL2TP_MESSAGETYPE_OCRP     8 /* Outgoing Call Reply */
+#define PPPOL2TP_MESSAGETYPE_OCCN     9 /* Outgoing Call Connected */
+#define PPPOL2TP_MESSAGETYPE_ICRQ    10 /* Incoming Call Request */
+#define PPPOL2TP_MESSAGETYPE_ICRP    11 /* Incoming Call Reply */
+#define PPPOL2TP_MESSAGETYPE_ICCN    12 /* Incoming Call Connected */
+#define PPPOL2TP_MESSAGETYPE_CDN     14 /* Call Disconnect Notify */
+/* Error reporting */
+#define PPPOL2TP_MESSAGETYPE_WEN     15 /* WAN Error Notify */
+/* PPP Session Control */
+#define PPPOL2TP_MESSAGETYPE_SLI     16 /* Set Link Info */
+
+/* -- AVP - Result code */
+#define PPPOL2TP_AVPTYPE_RESULTCODE   1 /* Result code */
+#define PPPOL2TP_RESULTCODE           1 /* General request to clear control connection */
+
+/* -- AVP - Protocol version (!= L2TP Header version) */
+#define PPPOL2TP_AVPTYPE_VERSION      2
+#define PPPOL2TP_VERSION         0x0100 /* L2TP Protocol version 1, revision 0 */
+
+/* -- AVP - Framing capabilities */
+#define PPPOL2TP_AVPTYPE_FRAMINGCAPABILITIES           3 /* Bearer capabilities */
+#define PPPOL2TP_FRAMINGCAPABILITIES          0x00000003 /* Async + Sync framing */
+
+/* -- AVP - Bearer capabilities */
+#define PPPOL2TP_AVPTYPE_BEARERCAPABILITIES           4 /* Bearer capabilities */
+#define PPPOL2TP_BEARERCAPABILITIES          0x00000003 /* Analog + Digital Access */
+
+/* -- AVP - Tie breaker */
+#define PPPOL2TP_AVPTYPE_TIEBREAKER   5
+
+/* -- AVP - Host name */
+#define PPPOL2TP_AVPTYPE_HOSTNAME     7 /* Host name */
+#define PPPOL2TP_HOSTNAME        "lwIP" /* FIXME: make it configurable */
+
+/* -- AVP - Vendor name */
+#define PPPOL2TP_AVPTYPE_VENDORNAME   8 /* Vendor name */
+#define PPPOL2TP_VENDORNAME      "lwIP" /* FIXME: make it configurable */
+
+/* -- AVP - Assign tunnel ID */
+#define PPPOL2TP_AVPTYPE_TUNNELID     9 /* Assign Tunnel ID */
+
+/* -- AVP - Receive window size */
+#define PPPOL2TP_AVPTYPE_RECEIVEWINDOWSIZE  10 /* Receive window size */
+#define PPPOL2TP_RECEIVEWINDOWSIZE           8 /* FIXME: make it configurable */
+
+/* -- AVP - Challenge */
+#define PPPOL2TP_AVPTYPE_CHALLENGE   11 /* Challenge */
+
+/* -- AVP - Cause code */
+#define PPPOL2TP_AVPTYPE_CAUSECODE   12 /* Cause code*/
+
+/* -- AVP - Challenge response */
+#define PPPOL2TP_AVPTYPE_CHALLENGERESPONSE   13 /* Challenge response */
+#define PPPOL2TP_AVPTYPE_CHALLENGERESPONSE_SIZE  16
+
+/* -- AVP - Assign session ID */
+#define PPPOL2TP_AVPTYPE_SESSIONID   14 /* Assign Session ID */
+
+/* -- AVP - Call serial number */
+#define PPPOL2TP_AVPTYPE_CALLSERIALNUMBER   15 /* Call Serial Number */
+
+/* -- AVP - Framing type */
+#define PPPOL2TP_AVPTYPE_FRAMINGTYPE         19 /* Framing Type */
+#define PPPOL2TP_FRAMINGTYPE         0x00000001 /* Sync framing */
+
+/* -- AVP - TX Connect Speed */
+#define PPPOL2TP_AVPTYPE_TXCONNECTSPEED      24 /* TX Connect Speed */
+#define PPPOL2TP_TXCONNECTSPEED       100000000 /* Connect speed: 100 Mbits/s */
+
+/* L2TP Session state */
+#define PPPOL2TP_STATE_INITIAL     0
+#define PPPOL2TP_STATE_SCCRQ_SENT  1
+#define PPPOL2TP_STATE_ICRQ_SENT   2
+#define PPPOL2TP_STATE_ICCN_SENT   3
+#define PPPOL2TP_STATE_DATA        4
+
+#define PPPOL2TP_OUTPUT_DATA_HEADER_LEN   6 /* Our data header len */
+
+/*
+ * PPPoL2TP interface control block.
+ */
+typedef struct pppol2tp_pcb_s pppol2tp_pcb;
+struct pppol2tp_pcb_s {
+  ppp_pcb *ppp;                /* PPP PCB */
+  u8_t phase;                  /* L2TP phase */
+  struct udp_pcb *udp;         /* UDP L2TP Socket */
+  struct netif *netif;         /* Output interface, used as a default route */
+  ip_addr_t remote_ip;         /* LNS IP Address */
+  u16_t remote_port;           /* LNS port */
+#if PPPOL2TP_AUTH_SUPPORT
+  const u8_t *secret;          /* Secret string */
+  u8_t secret_len;             /* Secret string length */
+  u8_t secret_rv[16];          /* Random vector */
+  u8_t challenge_hash[16];     /* Challenge response */
+  u8_t send_challenge;         /* Boolean whether the next sent packet should contains a challenge response */
+#endif /* PPPOL2TP_AUTH_SUPPORT */
+
+  u16_t tunnel_port;           /* Tunnel port */
+  u16_t our_ns;                /* NS to peer */
+  u16_t peer_nr;               /* NR from peer */
+  u16_t peer_ns;               /* NS from peer */
+  u16_t source_tunnel_id;      /* Tunnel ID assigned by peer */
+  u16_t remote_tunnel_id;      /* Tunnel ID assigned to peer */
+  u16_t source_session_id;     /* Session ID assigned by peer */
+  u16_t remote_session_id;     /* Session ID assigned to peer */
+
+  u8_t sccrq_retried;          /* number of SCCRQ retries already done */
+  u8_t icrq_retried;           /* number of ICRQ retries already done */
+  u8_t iccn_retried;           /* number of ICCN retries already done */
+};
+
+
+/* Create a new L2TP session. */
+ppp_pcb *pppol2tp_create(struct netif *pppif,
+       struct netif *netif, ip_addr_t *ipaddr, u16_t port,
+       const u8_t *secret, u8_t secret_len,
+       ppp_link_status_cb_fn link_status_cb, void *ctx_cb);
+
+#endif /* PPPOL2TP_H_ */
+#endif /* PPP_SUPPORT && PPPOL2TP_SUPPORT */
diff --git a/tools/sdk/include/lwip/netif/ppp/pppos.h b/tools/sdk/include/lwip/netif/ppp/pppos.h
new file mode 100755
index 00000000..39b2b7d0
--- /dev/null
+++ b/tools/sdk/include/lwip/netif/ppp/pppos.h
@@ -0,0 +1,119 @@
+/**
+ * @file
+ * Network Point to Point Protocol over Serial header file.
+ *
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#include "lwip/opt.h"
+#if PPP_SUPPORT && PPPOS_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifndef PPPOS_H
+#define PPPOS_H
+
+#include "lwip/sys.h"
+#include "lwip/sio.h"
+
+#include "ppp.h"
+#include "vj.h"
+
+/* PPP packet parser states.  Current state indicates operation yet to be
+ * completed. */
+enum {
+  PDIDLE = 0,  /* Idle state - waiting. */
+  PDSTART,     /* Process start flag. */
+  PDADDRESS,   /* Process address field. */
+  PDCONTROL,   /* Process control field. */
+  PDPROTOCOL1, /* Process protocol field 1. */
+  PDPROTOCOL2, /* Process protocol field 2. */
+  PDDATA       /* Process data byte. */
+};
+
+/* PPPoS serial output callback function prototype */
+typedef u32_t (*pppos_output_cb_fn)(ppp_pcb *pcb, u8_t *data, u32_t len, void *ctx);
+
+/*
+ * Extended asyncmap - allows any character to be escaped.
+ */
+typedef u8_t ext_accm[32];
+
+/*
+ * PPPoS interface control block.
+ */
+typedef struct pppos_pcb_s pppos_pcb;
+struct pppos_pcb_s {
+  /* -- below are data that will NOT be cleared between two sessions */
+  ppp_pcb *ppp;                    /* PPP PCB */
+  pppos_output_cb_fn output_cb;    /* PPP serial output callback */
+
+  /* -- below are data that will be cleared between two sessions
+   *
+   * last_xmit must be the first member of cleared members, because it is
+   * used to know which part must not be cleared.
+   */
+  u32_t last_xmit;                 /* Time of last transmission. */
+  ext_accm out_accm;               /* Async-Ctl-Char-Map for output. */
+
+  /* flags */
+  unsigned int open            :1; /* Set if PPPoS is open */
+  unsigned int pcomp           :1; /* Does peer accept protocol compression? */
+  unsigned int accomp          :1; /* Does peer accept addr/ctl compression? */
+
+  /* PPPoS rx */
+  ext_accm in_accm;                /* Async-Ctl-Char-Map for input. */
+  struct pbuf *in_head, *in_tail;  /* The input packet. */
+  u16_t in_protocol;               /* The input protocol code. */
+  u16_t in_fcs;                    /* Input Frame Check Sequence value. */
+  u8_t in_state;                   /* The input process state. */
+  u8_t in_escaped;                 /* Escape next character. */
+};
+
+/* Create a new PPPoS session. */
+ppp_pcb *pppos_create(struct netif *pppif, pppos_output_cb_fn output_cb,
+       ppp_link_status_cb_fn link_status_cb, void *ctx_cb);
+
+#if !NO_SYS && !PPP_INPROC_IRQ_SAFE
+/* Pass received raw characters to PPPoS to be decoded through lwIP TCPIP thread. */
+err_t pppos_input_tcpip(ppp_pcb *ppp, u8_t *s, int l);
+#endif /* !NO_SYS && !PPP_INPROC_IRQ_SAFE */
+
+/* PPP over Serial: this is the input function to be called for received data. */
+void pppos_input(ppp_pcb *ppp, u8_t* data, int len);
+
+
+/*
+ * Functions called from lwIP
+ * DO NOT CALL FROM lwIP USER APPLICATION.
+ */
+#if !NO_SYS && !PPP_INPROC_IRQ_SAFE
+err_t pppos_input_sys(struct pbuf *p, struct netif *inp);
+#endif /* !NO_SYS && !PPP_INPROC_IRQ_SAFE */
+
+#endif /* PPPOS_H */
+#endif /* PPP_SUPPORT && PPPOL2TP_SUPPORT */
diff --git a/tools/sdk/include/lwip/netif/ppp/upap.h b/tools/sdk/include/lwip/netif/ppp/upap.h
new file mode 100755
index 00000000..bb9309bd
--- /dev/null
+++ b/tools/sdk/include/lwip/netif/ppp/upap.h
@@ -0,0 +1,123 @@
+/*
+ * upap.h - User/Password Authentication Protocol definitions.
+ *
+ * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * 3. The name "Carnegie Mellon University" must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission. For permission or any legal
+ *    details, please contact
+ *      Office of Technology Transfer
+ *      Carnegie Mellon University
+ *      5000 Forbes Avenue
+ *      Pittsburgh, PA  15213-3890
+ *      (412) 268-4387, fax: (412) 268-7395
+ *      tech-transfer@andrew.cmu.edu
+ *
+ * 4. Redistributions of any form whatsoever must retain the following
+ *    acknowledgment:
+ *    "This product includes software developed by Computing Services
+ *     at Carnegie Mellon University (http://www.cmu.edu/computing/)."
+ *
+ * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE
+ * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: upap.h,v 1.8 2002/12/04 23:03:33 paulus Exp $
+ */
+
+#include "lwip/opt.h"
+#if PPP_SUPPORT && PAP_SUPPORT  /* don't build if not configured for use in lwipopts.h */
+
+#ifndef UPAP_H
+#define UPAP_H
+
+#include "ppp.h"
+
+/*
+ * Packet header = Code, id, length.
+ */
+#define UPAP_HEADERLEN	4
+
+
+/*
+ * UPAP codes.
+ */
+#define UPAP_AUTHREQ	1	/* Authenticate-Request */
+#define UPAP_AUTHACK	2	/* Authenticate-Ack */
+#define UPAP_AUTHNAK	3	/* Authenticate-Nak */
+
+
+/*
+ * Client states.
+ */
+#define UPAPCS_INITIAL	0	/* Connection down */
+#define UPAPCS_CLOSED	1	/* Connection up, haven't requested auth */
+#define UPAPCS_PENDING	2	/* Connection down, have requested auth */
+#define UPAPCS_AUTHREQ	3	/* We've sent an Authenticate-Request */
+#define UPAPCS_OPEN	4	/* We've received an Ack */
+#define UPAPCS_BADAUTH	5	/* We've received a Nak */
+
+/*
+ * Server states.
+ */
+#define UPAPSS_INITIAL	0	/* Connection down */
+#define UPAPSS_CLOSED	1	/* Connection up, haven't requested auth */
+#define UPAPSS_PENDING	2	/* Connection down, have requested auth */
+#define UPAPSS_LISTEN	3	/* Listening for an Authenticate */
+#define UPAPSS_OPEN	4	/* We've sent an Ack */
+#define UPAPSS_BADAUTH	5	/* We've sent a Nak */
+
+
+/*
+ * Timeouts.
+ */
+#if 0 /* moved to opt.h */
+#define UPAP_DEFTIMEOUT	3	/* Timeout (seconds) for retransmitting req */
+#define UPAP_DEFREQTIME	30	/* Time to wait for auth-req from peer */
+#endif /* moved to opt.h */
+
+/*
+ * Each interface is described by upap structure.
+ */
+#if PAP_SUPPORT
+typedef struct upap_state {
+    const char *us_user;	/* User */
+    u8_t us_userlen;		/* User length */
+    const char *us_passwd;	/* Password */
+    u8_t us_passwdlen;		/* Password length */
+    u8_t us_clientstate;	/* Client state */
+#if PPP_SERVER
+    u8_t us_serverstate;	/* Server state */
+#endif /* PPP_SERVER */
+    u8_t us_id;		        /* Current id */
+    u8_t us_transmits;		/* Number of auth-reqs sent */
+} upap_state;
+#endif /* PAP_SUPPORT */
+
+
+void upap_authwithpeer(ppp_pcb *pcb, const char *user, const char *password);
+#if PPP_SERVER
+void upap_authpeer(ppp_pcb *pcb);
+#endif /* PPP_SERVER */
+
+extern const struct protent pap_protent;
+
+#endif /* UPAP_H */
+#endif /* PPP_SUPPORT && PAP_SUPPORT */
diff --git a/tools/sdk/include/lwip/netif/ppp/vj.h b/tools/sdk/include/lwip/netif/ppp/vj.h
new file mode 100755
index 00000000..f2e1f8b4
--- /dev/null
+++ b/tools/sdk/include/lwip/netif/ppp/vj.h
@@ -0,0 +1,161 @@
+/*
+ * Definitions for tcp compression routines.
+ *
+ * $Id: vj.h,v 1.7 2010/02/22 17:52:09 goldsimon Exp $
+ *
+ * Copyright (c) 1989 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the University of California, Berkeley.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Van Jacobson (van@helios.ee.lbl.gov), Dec 31, 1989:
+ * - Initial distribution.
+ */
+
+#include "lwip/opt.h"
+#if PPP_SUPPORT && VJ_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifndef VJ_H
+#define VJ_H
+
+#include "lwip/ip.h"
+#include "lwip/priv/tcp_priv.h"
+
+#define MAX_SLOTS 16 /* must be > 2 and < 256 */
+#define MAX_HDR   128
+
+/*
+ * Compressed packet format:
+ *
+ * The first octet contains the packet type (top 3 bits), TCP
+ * 'push' bit, and flags that indicate which of the 4 TCP sequence
+ * numbers have changed (bottom 5 bits).  The next octet is a
+ * conversation number that associates a saved IP/TCP header with
+ * the compressed packet.  The next two octets are the TCP checksum
+ * from the original datagram.  The next 0 to 15 octets are
+ * sequence number changes, one change per bit set in the header
+ * (there may be no changes and there are two special cases where
+ * the receiver implicitly knows what changed -- see below).
+ *
+ * There are 5 numbers which can change (they are always inserted
+ * in the following order): TCP urgent pointer, window,
+ * acknowlegement, sequence number and IP ID.  (The urgent pointer
+ * is different from the others in that its value is sent, not the
+ * change in value.)  Since typical use of SLIP links is biased
+ * toward small packets (see comments on MTU/MSS below), changes
+ * use a variable length coding with one octet for numbers in the
+ * range 1 - 255 and 3 octets (0, MSB, LSB) for numbers in the
+ * range 256 - 65535 or 0.  (If the change in sequence number or
+ * ack is more than 65535, an uncompressed packet is sent.)
+ */
+
+/*
+ * Packet types (must not conflict with IP protocol version)
+ *
+ * The top nibble of the first octet is the packet type.  There are
+ * three possible types: IP (not proto TCP or tcp with one of the
+ * control flags set); uncompressed TCP (a normal IP/TCP packet but
+ * with the 8-bit protocol field replaced by an 8-bit connection id --
+ * this type of packet syncs the sender & receiver); and compressed
+ * TCP (described above).
+ *
+ * LSB of 4-bit field is TCP "PUSH" bit (a worthless anachronism) and
+ * is logically part of the 4-bit "changes" field that follows.  Top
+ * three bits are actual packet type.  For backward compatibility
+ * and in the interest of conserving bits, numbers are chosen so the
+ * IP protocol version number (4) which normally appears in this nibble
+ * means "IP packet".
+ */
+
+/* packet types */
+#define TYPE_IP               0x40
+#define TYPE_UNCOMPRESSED_TCP 0x70
+#define TYPE_COMPRESSED_TCP   0x80
+#define TYPE_ERROR            0x00
+
+/* Bits in first octet of compressed packet */
+#define NEW_C 0x40 /* flag bits for what changed in a packet */
+#define NEW_I 0x20
+#define NEW_S 0x08
+#define NEW_A 0x04
+#define NEW_W 0x02
+#define NEW_U 0x01
+
+/* reserved, special-case values of above */
+#define SPECIAL_I (NEW_S|NEW_W|NEW_U) /* echoed interactive traffic */
+#define SPECIAL_D (NEW_S|NEW_A|NEW_W|NEW_U) /* unidirectional data */
+#define SPECIALS_MASK (NEW_S|NEW_A|NEW_W|NEW_U)
+
+#define TCP_PUSH_BIT 0x10
+
+
+/*
+ * "state" data for each active tcp conversation on the wire.  This is
+ * basically a copy of the entire IP/TCP header from the last packet
+ * we saw from the conversation together with a small identifier
+ * the transmit & receive ends of the line use to locate saved header.
+ */
+struct cstate {
+  struct cstate *cs_next; /* next most recently used state (xmit only) */
+  u16_t cs_hlen;        /* size of hdr (receive only) */
+  u8_t cs_id;           /* connection # associated with this state */
+  u8_t cs_filler;
+  union {
+    char csu_hdr[MAX_HDR];
+    struct ip_hdr csu_ip;     /* ip/tcp hdr from most recent packet */
+  } vjcs_u;
+};
+#define cs_ip vjcs_u.csu_ip
+#define cs_hdr vjcs_u.csu_hdr
+
+
+struct vjstat {
+  u32_t vjs_packets;        /* outbound packets */
+  u32_t vjs_compressed;     /* outbound compressed packets */
+  u32_t vjs_searches;       /* searches for connection state */
+  u32_t vjs_misses;         /* times couldn't find conn. state */
+  u32_t vjs_uncompressedin; /* inbound uncompressed packets */
+  u32_t vjs_compressedin;   /* inbound compressed packets */
+  u32_t vjs_errorin;        /* inbound unknown type packets */
+  u32_t vjs_tossed;         /* inbound packets tossed because of error */
+};
+
+/*
+ * all the state data for one serial line (we need one of these per line).
+ */
+struct vjcompress {
+  struct cstate *last_cs;          /* most recently used tstate */
+  u8_t last_recv;                /* last rcvd conn. id */
+  u8_t last_xmit;                /* last sent conn. id */
+  u16_t flags;
+  u8_t maxSlotIndex;
+  u8_t compressSlot;             /* Flag indicating OK to compress slot ID. */
+#if LINK_STATS
+  struct vjstat stats;
+#endif
+  struct cstate tstate[MAX_SLOTS]; /* xmit connection states */
+  struct cstate rstate[MAX_SLOTS]; /* receive connection states */
+};
+
+/* flag values */
+#define VJF_TOSS 1U /* tossing rcvd frames because of input err */
+
+extern void  vj_compress_init    (struct vjcompress *comp);
+extern u8_t  vj_compress_tcp     (struct vjcompress *comp, struct pbuf **pb);
+extern void  vj_uncompress_err   (struct vjcompress *comp);
+extern int   vj_uncompress_uncomp(struct pbuf *nb, struct vjcompress *comp);
+extern int   vj_uncompress_tcp   (struct pbuf **nb, struct vjcompress *comp);
+
+#endif /* VJ_H */
+
+#endif /* PPP_SUPPORT && VJ_SUPPORT */
diff --git a/tools/sdk/include/lwip/netif/slipif.h b/tools/sdk/include/lwip/netif/slipif.h
new file mode 100755
index 00000000..d164d448
--- /dev/null
+++ b/tools/sdk/include/lwip/netif/slipif.h
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2001, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef LWIP_HDR_NETIF_SLIPIF_H
+#define LWIP_HDR_NETIF_SLIPIF_H
+
+#include "lwip/opt.h"
+#include "lwip/netif.h"
+
+/** Set this to 1 to start a thread that blocks reading on the serial line
+ * (using sio_read()).
+ */
+#ifndef SLIP_USE_RX_THREAD
+#define SLIP_USE_RX_THREAD !NO_SYS
+#endif
+
+/** Set this to 1 to enable functions to pass in RX bytes from ISR context.
+ * If enabled, slipif_received_byte[s]() process incoming bytes and put assembled
+ * packets on a queue, which is fed into lwIP from slipif_poll().
+ * If disabled, slipif_poll() polls the serial line (using sio_tryread()).
+ */
+#ifndef SLIP_RX_FROM_ISR
+#define SLIP_RX_FROM_ISR 0
+#endif
+
+/** Set this to 1 (default for SLIP_RX_FROM_ISR) to queue incoming packets
+ * received by slipif_received_byte[s]() as long as PBUF_POOL pbufs are available.
+ * If disabled, packets will be dropped if more than one packet is received.
+ */
+#ifndef SLIP_RX_QUEUE
+#define SLIP_RX_QUEUE SLIP_RX_FROM_ISR
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+err_t slipif_init(struct netif * netif);
+void slipif_poll(struct netif *netif);
+#if SLIP_RX_FROM_ISR
+void slipif_process_rxqueue(struct netif *netif);
+void slipif_received_byte(struct netif *netif, u8_t data);
+void slipif_received_bytes(struct netif *netif, u8_t *data, u8_t len);
+#endif /* SLIP_RX_FROM_ISR */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_NETIF_SLIPIF_H */
+
diff --git a/tools/sdk/include/lwip/netif/wlanif.h b/tools/sdk/include/lwip/netif/wlanif.h
new file mode 100755
index 00000000..7eb303ea
--- /dev/null
+++ b/tools/sdk/include/lwip/netif/wlanif.h
@@ -0,0 +1,31 @@
+/*
+ *  Copyright (c) 2010-2011 	Espressif System
+ *   
+*/
+
+#ifndef _WLAN_LWIP_IF_H_
+#define _WLAN_LWIP_IF_H_
+
+#include "esp_wifi.h"
+
+#include "lwip/err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+err_t wlanif_init(struct netif *netif);
+
+void wlanif_input(struct netif *netif, void *buffer, u16_t len, void* eb);
+
+bool ieee80211_output(wifi_interface_t wifi_if, void *buffer, u16_t len);
+
+wifi_interface_t wifi_get_interface(void *dev);
+
+void netif_reg_addr_change_cb(void* cb);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*  _WLAN_LWIP_IF_H_ */
diff --git a/tools/sdk/include/lwip/port/arch/cc.h b/tools/sdk/include/lwip/port/arch/cc.h
new file mode 100644
index 00000000..6fc1da18
--- /dev/null
+++ b/tools/sdk/include/lwip/port/arch/cc.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2001, Swedish Institute of Computer Science.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. Neither the name of the Institute nor the names of its contributors 
+ *    may be used to endorse or promote products derived from this software 
+ *    without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+ * SUCH DAMAGE. 
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __ARCH_CC_H__
+#define __ARCH_CC_H__
+
+#include 
+#include 
+
+#include "arch/sys_arch.h"
+
+#define BYTE_ORDER LITTLE_ENDIAN
+
+typedef uint8_t  u8_t;
+typedef int8_t   s8_t;
+typedef uint16_t u16_t;
+typedef int16_t  s16_t;
+typedef uint32_t u32_t;
+typedef int32_t  s32_t;
+
+typedef unsigned long   mem_ptr_t;
+typedef int sys_prot_t;
+
+#define S16_F "d"
+#define U16_F "d"
+#define X16_F "x"
+
+#define S32_F "d"
+#define U32_F "d"
+#define X32_F "x"
+
+#define PACK_STRUCT_FIELD(x) x
+#define PACK_STRUCT_STRUCT __attribute__((packed))
+#define PACK_STRUCT_BEGIN
+#define PACK_STRUCT_END
+
+#include 
+
+#define LWIP_PLATFORM_DIAG(x)   do {printf x;} while(0)
+#define LWIP_PLATFORM_ASSERT(x) do {printf(x); sys_arch_assert(__FILE__, __LINE__);} while(0)
+
+//#define LWIP_DEBUG
+#define LWIP_NOASSERT
+//#define LWIP_ERROR
+
+#endif /* __ARCH_CC_H__ */
diff --git a/tools/sdk/include/lwip/port/arch/perf.h b/tools/sdk/include/lwip/port/arch/perf.h
new file mode 100644
index 00000000..089facac
--- /dev/null
+++ b/tools/sdk/include/lwip/port/arch/perf.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2001, Swedish Institute of Computer Science.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. Neither the name of the Institute nor the names of its contributors 
+ *    may be used to endorse or promote products derived from this software 
+ *    without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+ * SUCH DAMAGE. 
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __PERF_H__
+#define __PERF_H__
+
+#define PERF_START    /* null definition */
+#define PERF_STOP(x)  /* null definition */
+
+#endif /* __PERF_H__ */
diff --git a/tools/sdk/include/lwip/port/arch/sys_arch.h b/tools/sdk/include/lwip/port/arch/sys_arch.h
new file mode 100644
index 00000000..a8633482
--- /dev/null
+++ b/tools/sdk/include/lwip/port/arch/sys_arch.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+ 
+#ifndef __SYS_ARCH_H__
+#define __SYS_ARCH_H__
+
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "freertos/queue.h"
+#include "freertos/semphr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+typedef xSemaphoreHandle sys_sem_t;
+typedef xSemaphoreHandle sys_mutex_t;
+typedef xTaskHandle sys_thread_t;
+
+typedef struct sys_mbox_s {
+  xQueueHandle os_mbox;
+  sys_mutex_t  lock;
+  uint8_t      alive;
+}* sys_mbox_t;
+
+
+#define LWIP_COMPAT_MUTEX 0
+
+#if !LWIP_COMPAT_MUTEX
+#define sys_mutex_valid( x ) ( ( ( *x ) == NULL) ? pdFALSE : pdTRUE )
+#define sys_mutex_set_invalid( x ) ( ( *x ) = NULL )
+#endif
+
+#define sys_mbox_valid( x ) ( ( ( *x ) == NULL) ? pdFALSE : pdTRUE )
+#define sys_mbox_set_invalid( x ) ( ( *x ) = NULL )
+
+#define sys_sem_valid( x ) ( ( ( *x ) == NULL) ? pdFALSE : pdTRUE )
+#define sys_sem_set_invalid( x ) ( ( *x ) = NULL )
+
+void sys_arch_assert(const char *file, int line);
+uint32_t system_get_time(void);
+void sys_delay_ms(uint32_t ms);
+sys_sem_t* sys_thread_sem_init(void);
+void sys_thread_sem_deinit(void);
+sys_sem_t* sys_thread_sem_get(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYS_ARCH_H__ */
+
diff --git a/tools/sdk/include/lwip/port/lwipopts.h b/tools/sdk/include/lwip/port/lwipopts.h
new file mode 100755
index 00000000..29506c0b
--- /dev/null
+++ b/tools/sdk/include/lwip/port/lwipopts.h
@@ -0,0 +1,531 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Simon Goldschmidt
+ *
+ */
+#ifndef __LWIPOPTS_H__
+#define __LWIPOPTS_H__
+
+#include 
+#include "esp_task.h"
+#include "sdkconfig.h"
+
+/* Enable all Espressif-only options */
+#define LWIP_ESP8266
+
+/*
+   -----------------------------------------------
+   ---------- Platform specific locking ----------
+   -----------------------------------------------
+*/
+/**
+ * SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain
+ * critical regions during buffer allocation, deallocation and memory
+ * allocation and deallocation.
+ */
+#define SYS_LIGHTWEIGHT_PROT        1
+
+/**
+ * MEMCPY: override this if you have a faster implementation at hand than the
+ * one included in your C library
+ */
+#define MEMCPY(dst,src,len)             memcpy(dst,src,len)
+
+/**
+ * SMEMCPY: override this with care! Some compilers (e.g. gcc) can inline a
+ * call to memcpy() if the length is known at compile time and is small.
+ */
+#define SMEMCPY(dst,src,len)            memcpy(dst,src,len)
+
+extern unsigned long os_random(void);
+#define LWIP_RAND	rand
+/*
+   ------------------------------------
+   ---------- Memory options ----------
+   ------------------------------------
+*/
+/**
+ * MEM_LIBC_MALLOC==1: Use malloc/free/realloc provided by your C-library
+ * instead of the lwip internal allocator. Can save code size if you
+ * already use it.
+ */
+#define MEM_LIBC_MALLOC        1
+
+/**
+* MEMP_MEM_MALLOC==1: Use mem_malloc/mem_free instead of the lwip pool allocator.
+* Especially useful with MEM_LIBC_MALLOC but handle with care regarding execution
+* speed and usage from interrupts!
+*/
+#define MEMP_MEM_MALLOC                 1
+
+/**
+ * MEM_ALIGNMENT: should be set to the alignment of the CPU
+ *    4 byte alignment -> #define MEM_ALIGNMENT 4
+ *    2 byte alignment -> #define MEM_ALIGNMENT 2
+ */
+#define MEM_ALIGNMENT           4
+
+/*
+   ------------------------------------------------
+   ---------- Internal Memory Pool Sizes ----------
+   ------------------------------------------------
+*/
+/**
+ * MEMP_NUM_TCP_PCB: the number of simulatenously active TCP connections.
+ * (requires the LWIP_TCP option)
+ */
+#define MEMP_NUM_TCP_PCB                5
+
+/**
+ * MEMP_NUM_NETCONN: the number of struct netconns.
+ * (only needed if you use the sequential API, like api_lib.c)
+ */
+#define MEMP_NUM_NETCONN                10
+
+/*
+   --------------------------------
+   ---------- ARP options -------
+   --------------------------------
+*/
+/**
+ * ARP_QUEUEING==1: Multiple outgoing packets are queued during hardware address
+ * resolution. By default, only the most recent packet is queued per IP address.
+ * This is sufficient for most protocols and mainly reduces TCP connection
+ * startup time. Set this to 1 if you know your application sends more than one
+ * packet in a row to an IP address that is not in the ARP cache.
+ */
+#define ARP_QUEUEING                    1
+
+/*
+   --------------------------------
+   ---------- IP options ----------
+   --------------------------------
+*/
+/**
+ * IP_REASSEMBLY==1: Reassemble incoming fragmented IP packets. Note that
+ * this option does not affect outgoing packet sizes, which can be controlled
+ * via IP_FRAG.
+ */
+#define IP_REASSEMBLY                   0
+
+/**
+ * IP_FRAG==1: Fragment outgoing IP packets if their size exceeds MTU. Note
+ * that this option does not affect incoming packet sizes, which can be
+ * controlled via IP_REASSEMBLY.
+ */
+#define IP_FRAG                         0
+
+/**
+ * IP_REASS_MAXAGE: Maximum time (in multiples of IP_TMR_INTERVAL - so seconds, normally)
+ * a fragmented IP packet waits for all fragments to arrive. If not all fragments arrived
+ * in this time, the whole packet is discarded.
+ */
+#define IP_REASS_MAXAGE                 3
+
+/**
+ * IP_REASS_MAX_PBUFS: Total maximum amount of pbufs waiting to be reassembled.
+ * Since the received pbufs are enqueued, be sure to configure
+ * PBUF_POOL_SIZE > IP_REASS_MAX_PBUFS so that the stack is still able to receive
+ * packets even if the maximum amount of fragments is enqueued for reassembly!
+ */
+#define IP_REASS_MAX_PBUFS              10
+
+/*
+   ----------------------------------
+   ---------- ICMP options ----------
+   ----------------------------------
+*/
+
+/*
+   ---------------------------------
+   ---------- RAW options ----------
+   ---------------------------------
+*/
+
+/*
+   ----------------------------------
+   ---------- DHCP options ----------
+   ----------------------------------
+*/
+/**
+ * LWIP_DHCP==1: Enable DHCP module.
+ */
+#define LWIP_DHCP                       1
+
+
+#define DHCP_MAXRTX						0   //(*(volatile uint32*)0x600011E0)
+/*
+   ------------------------------------
+   ---------- AUTOIP options ----------
+   ------------------------------------
+*/
+/*
+   ----------------------------------
+   ---------- SNMP options ----------
+   ----------------------------------
+*/
+/*
+   ----------------------------------
+   ---------- IGMP options ----------
+   ----------------------------------
+*/
+/**
+ * LWIP_IGMP==1: Turn on IGMP module.
+ */
+#define LWIP_IGMP                       1
+
+/*
+   ----------------------------------
+   ---------- DNS options -----------
+   ----------------------------------
+*/
+/**
+ * LWIP_DNS==1: Turn on DNS module. UDP must be available for DNS
+ * transport.
+ */
+#define LWIP_DNS                        1
+
+/*
+   ---------------------------------
+   ---------- UDP options ----------
+   ---------------------------------
+*/
+/*
+   ---------------------------------
+   ---------- TCP options ----------
+   ---------------------------------
+*/
+/**
+ * TCP_WND: The size of a TCP window.  This must be at least
+ * (2 * TCP_MSS) for things to work well
+ */
+#define PERF 1
+#ifdef PERF
+extern unsigned char misc_prof_get_tcpw(void);
+extern unsigned char misc_prof_get_tcp_snd_buf(void);
+#define TCP_WND                         (misc_prof_get_tcpw()*TCP_MSS)
+#define TCP_SND_BUF                     (misc_prof_get_tcp_snd_buf()*TCP_MSS)
+
+#else
+
+#define TCP_WND                         (4 * TCP_MSS)
+#define TCP_SND_BUF                     (2 * TCP_MSS)
+
+#endif
+
+
+/**
+ * TCP_QUEUE_OOSEQ==1: TCP will queue segments that arrive out of order.
+ * Define to 0 if your device is low on memory.
+ */
+#define TCP_QUEUE_OOSEQ                 1
+
+/*
+ *     LWIP_EVENT_API==1: The user defines lwip_tcp_event() to receive all
+ *         events (accept, sent, etc) that happen in the system.
+ *     LWIP_CALLBACK_API==1: The PCB callback function is called directly
+ *         for the event. This is the default.
+*/
+#define TCP_MSS                         1460
+
+/**
+ * TCP_MAXRTX: Maximum number of retransmissions of data segments.
+ */
+#define TCP_MAXRTX                      12  //(*(volatile uint32*)0x600011E8)
+
+/**
+ * TCP_SYNMAXRTX: Maximum number of retransmissions of SYN segments.
+ */
+#define TCP_SYNMAXRTX                   6   //(*(volatile uint32*)0x600011E4)
+
+/**
+ * TCP_LISTEN_BACKLOG: Enable the backlog option for tcp listen pcb.
+ */
+#define TCP_LISTEN_BACKLOG              1
+
+/*
+   ----------------------------------
+   ---------- Pbuf options ----------
+   ----------------------------------
+*/
+
+/*
+   ------------------------------------------------
+   ---------- Network Interfaces options ----------
+   ------------------------------------------------
+*/
+
+/**
+ * LWIP_NETIF_HOSTNAME==1: use DHCP_OPTION_HOSTNAME with netif's hostname
+ * field.
+ */
+#define LWIP_NETIF_HOSTNAME             1
+
+/**
+ * LWIP_NETIF_TX_SINGLE_PBUF: if this is set to 1, lwIP tries to put all data
+ * to be sent into one single pbuf. This is for compatibility with DMA-enabled
+ * MACs that do not support scatter-gather.
+ * Beware that this might involve CPU-memcpy before transmitting that would not
+ * be needed without this flag! Use this only if you need to!
+ *
+ * @todo: TCP and IP-frag do not work with this, yet:
+ */
+#define LWIP_NETIF_TX_SINGLE_PBUF             1
+
+/*
+   ------------------------------------
+   ---------- LOOPIF options ----------
+   ------------------------------------
+*/
+
+/*
+   ------------------------------------
+   ---------- SLIPIF options ----------
+   ------------------------------------
+*/
+
+/*
+   ------------------------------------
+   ---------- Thread options ----------
+   ------------------------------------
+*/
+/**
+ * TCPIP_THREAD_NAME: The name assigned to the main tcpip thread.
+ */
+#define TCPIP_THREAD_NAME              "tiT"
+
+/**
+ * TCPIP_THREAD_STACKSIZE: The stack size used by the main tcpip thread.
+ * The stack size value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#define TCPIP_THREAD_STACKSIZE          ESP_TASK_TCPIP_STACK
+
+/**
+ * TCPIP_THREAD_PRIO: The priority assigned to the main tcpip thread.
+ * The priority value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#define TCPIP_THREAD_PRIO               ESP_TASK_TCPIP_PRIO
+
+/**
+ * TCPIP_MBOX_SIZE: The mailbox size for the tcpip thread messages
+ * The queue size value itself is platform-dependent, but is passed to
+ * sys_mbox_new() when tcpip_init is called.
+ */
+#define TCPIP_MBOX_SIZE                 16
+
+/**
+ * DEFAULT_UDP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
+ * NETCONN_UDP. The queue size value itself is platform-dependent, but is passed
+ * to sys_mbox_new() when the recvmbox is created.
+ */
+#define DEFAULT_UDP_RECVMBOX_SIZE       16
+
+/**
+ * DEFAULT_TCP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
+ * NETCONN_TCP. The queue size value itself is platform-dependent, but is passed
+ * to sys_mbox_new() when the recvmbox is created.
+ */
+#define DEFAULT_TCP_RECVMBOX_SIZE       16
+//#define DEFAULT_TCP_RECVMBOX_SIZE       6
+
+/**
+ * DEFAULT_ACCEPTMBOX_SIZE: The mailbox size for the incoming connections.
+ * The queue size value itself is platform-dependent, but is passed to
+ * sys_mbox_new() when the acceptmbox is created.
+ */
+#define DEFAULT_ACCEPTMBOX_SIZE         6
+
+/*
+   ----------------------------------------------
+   ---------- Sequential layer options ----------
+   ----------------------------------------------
+*/
+/**
+ * LWIP_TCPIP_CORE_LOCKING: (EXPERIMENTAL!)
+ * Don't use it if you're not an active lwIP project member
+ */
+#define LWIP_TCPIP_CORE_LOCKING         0
+
+/*
+   ------------------------------------
+   ---------- Socket options ----------
+   ------------------------------------
+*/
+/**
+ * LWIP_SO_SNDTIMEO==1: Enable send timeout for sockets/netconns and
+ * SO_SNDTIMEO processing.
+ */
+#define LWIP_SO_SNDTIMEO                1
+
+/**
+ * LWIP_SO_RCVTIMEO==1: Enable receive timeout for sockets/netconns and
+ * SO_RCVTIMEO processing.
+ */
+#define LWIP_SO_RCVTIMEO                1
+
+/**
+ * LWIP_TCP_KEEPALIVE==1: Enable TCP_KEEPIDLE, TCP_KEEPINTVL and TCP_KEEPCNT
+ * options processing. Note that TCP_KEEPIDLE and TCP_KEEPINTVL have to be set
+ * in seconds. (does not require sockets.c, and will affect tcp.c)
+ */
+#define LWIP_TCP_KEEPALIVE              1
+
+/**
+ * LWIP_SO_RCVBUF==1: Enable SO_RCVBUF processing.
+ */
+#define LWIP_SO_RCVBUF                  1
+
+/**
+ * SO_REUSE==1: Enable SO_REUSEADDR option.
+ * This option is set via menuconfig.
+ */
+#define SO_REUSE                        CONFIG_LWIP_SO_REUSE
+
+/*
+   ----------------------------------------
+   ---------- Statistics options ----------
+   ----------------------------------------
+*/
+/**
+ * LWIP_STATS==1: Enable statistics collection in lwip_stats.
+ */
+#define LWIP_STATS                      0
+
+/*
+   ---------------------------------
+   ---------- PPP options ----------
+   ---------------------------------
+*/
+
+/*
+   --------------------------------------
+   ---------- Checksum options ----------
+   --------------------------------------
+*/
+
+/*
+   ---------------------------------------
+   ---------- IPv6 options ---------------
+   ---------------------------------------
+*/
+/**
+ * LWIP_IPV6==1: Enable IPv6
+ */
+#define LWIP_IPV6                       1
+
+/*
+   ---------------------------------------
+   ---------- Hook options ---------------
+   ---------------------------------------
+*/
+
+/*
+   ---------------------------------------
+   ---------- Debugging options ----------
+   ---------------------------------------
+*/
+/**
+ * ETHARP_DEBUG: Enable debugging in etharp.c.
+ */
+#define ETHARP_DEBUG                    LWIP_DBG_OFF
+
+/**
+ * NETIF_DEBUG: Enable debugging in netif.c.
+ */
+#define NETIF_DEBUG                     LWIP_DBG_OFF
+
+/**
+ * PBUF_DEBUG: Enable debugging in pbuf.c.
+ */
+#define PBUF_DEBUG                      LWIP_DBG_OFF
+
+/**
+ * API_LIB_DEBUG: Enable debugging in api_lib.c.
+ */
+#define API_LIB_DEBUG                   LWIP_DBG_OFF
+
+/**
+ * SOCKETS_DEBUG: Enable debugging in sockets.c.
+ */
+#define SOCKETS_DEBUG                   LWIP_DBG_OFF
+
+/**
+ * ICMP_DEBUG: Enable debugging in icmp.c.
+ */
+#define ICMP_DEBUG                      LWIP_DBG_OFF
+
+/**
+ * IP_DEBUG: Enable debugging for IP.
+ */
+#define IP_DEBUG                        LWIP_DBG_OFF
+
+/**
+ * MEMP_DEBUG: Enable debugging in memp.c.
+ */
+#define MEMP_DEBUG                      LWIP_DBG_OFF
+
+/**
+ * TCP_INPUT_DEBUG: Enable debugging in tcp_in.c for incoming debug.
+ */
+#define TCP_INPUT_DEBUG                 LWIP_DBG_OFF
+
+/**
+ * TCP_OUTPUT_DEBUG: Enable debugging in tcp_out.c output functions.
+ */
+#define TCP_OUTPUT_DEBUG                LWIP_DBG_OFF
+
+/**
+ * TCPIP_DEBUG: Enable debugging in tcpip.c.
+ */
+#define TCPIP_DEBUG                     LWIP_DBG_OFF
+
+/**
+ * DHCP_DEBUG: Enable debugging in dhcp.c.
+ */
+#define DHCP_DEBUG                      LWIP_DBG_OFF
+#define LWIP_DEBUG                      0
+#define TCP_DEBUG                       LWIP_DBG_OFF
+#define THREAD_SAFE_DEBUG               LWIP_DBG_OFF
+#define LWIP_THREAD_SAFE                1
+
+#define CHECKSUM_CHECK_UDP              0
+#define CHECKSUM_CHECK_IP               0
+
+#define HEAP_HIGHWAT                    20*1024
+
+#define LWIP_NETCONN_FULLDUPLEX         1
+#define LWIP_NETCONN_SEM_PER_THREAD     1
+
+
+
+#define SOC_SEND_LOG //printf
+
+#endif /* __LWIPOPTS_H__ */
diff --git a/tools/sdk/include/lwip/port/netif/wlanif.h b/tools/sdk/include/lwip/port/netif/wlanif.h
new file mode 100755
index 00000000..7eb303ea
--- /dev/null
+++ b/tools/sdk/include/lwip/port/netif/wlanif.h
@@ -0,0 +1,31 @@
+/*
+ *  Copyright (c) 2010-2011 	Espressif System
+ *   
+*/
+
+#ifndef _WLAN_LWIP_IF_H_
+#define _WLAN_LWIP_IF_H_
+
+#include "esp_wifi.h"
+
+#include "lwip/err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+err_t wlanif_init(struct netif *netif);
+
+void wlanif_input(struct netif *netif, void *buffer, u16_t len, void* eb);
+
+bool ieee80211_output(wifi_interface_t wifi_if, void *buffer, u16_t len);
+
+wifi_interface_t wifi_get_interface(void *dev);
+
+void netif_reg_addr_change_cb(void* cb);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*  _WLAN_LWIP_IF_H_ */
diff --git a/tools/sdk/include/lwip/posix/netdb.h b/tools/sdk/include/lwip/posix/netdb.h
new file mode 100755
index 00000000..12d4c7f5
--- /dev/null
+++ b/tools/sdk/include/lwip/posix/netdb.h
@@ -0,0 +1,33 @@
+/**
+ * @file
+ * This file is a posix wrapper for lwip/netdb.h.
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#include "lwip/netdb.h"
diff --git a/tools/sdk/include/lwip/posix/sys/socket.h b/tools/sdk/include/lwip/posix/sys/socket.h
new file mode 100755
index 00000000..0ed9baf3
--- /dev/null
+++ b/tools/sdk/include/lwip/posix/sys/socket.h
@@ -0,0 +1,33 @@
+/**
+ * @file
+ * This file is a posix wrapper for lwip/sockets.h.
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#include "lwip/sockets.h"
diff --git a/tools/sdk/include/lwip/sys/socket.h b/tools/sdk/include/lwip/sys/socket.h
new file mode 100755
index 00000000..0ed9baf3
--- /dev/null
+++ b/tools/sdk/include/lwip/sys/socket.h
@@ -0,0 +1,33 @@
+/**
+ * @file
+ * This file is a posix wrapper for lwip/sockets.h.
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#include "lwip/sockets.h"
diff --git a/tools/sdk/include/mbedtls/.gitignore b/tools/sdk/include/mbedtls/.gitignore
new file mode 100644
index 00000000..bf67d02e
--- /dev/null
+++ b/tools/sdk/include/mbedtls/.gitignore
@@ -0,0 +1,4 @@
+Makefile
+*.sln
+*.vcxproj
+mbedtls/check_config
diff --git a/tools/sdk/include/mbedtls/aes_alt.h b/tools/sdk/include/mbedtls/aes_alt.h
new file mode 100644
index 00000000..7161b282
--- /dev/null
+++ b/tools/sdk/include/mbedtls/aes_alt.h
@@ -0,0 +1,59 @@
+/**
+ * \file aes_alt.h
+ *
+ * \brief AES block cipher
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *
+ */
+
+#ifndef AES_ALT_H
+#define AES_ALT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(MBEDTLS_AES_ALT)
+#include "hwcrypto/aes.h"
+
+typedef esp_aes_context mbedtls_aes_context;
+
+#define mbedtls_aes_init            esp_aes_init
+#define mbedtls_aes_free            esp_aes_free
+#define mbedtls_aes_setkey_enc      esp_aes_setkey_enc
+#define mbedtls_aes_setkey_dec      esp_aes_setkey_dec
+#define mbedtls_aes_crypt_ecb       esp_aes_crypt_ecb
+#if defined(MBEDTLS_CIPHER_MODE_CBC)
+#define mbedtls_aes_crypt_cbc       esp_aes_crypt_cbc
+#endif
+#if defined(MBEDTLS_CIPHER_MODE_CFB)
+#define mbedtls_aes_crypt_cfb128    esp_aes_crypt_cfb128
+#define mbedtls_aes_crypt_cfb8      esp_aes_crypt_cfb8
+#endif
+#if defined(MBEDTLS_CIPHER_MODE_CTR)
+#define mbedtls_aes_crypt_ctr       esp_aes_crypt_ctr
+#endif
+#define mbedtls_aes_encrypt         esp_aes_encrypt
+#define mbedtls_aes_decrypt         esp_aes_decrypt
+#endif /* MBEDTLS_AES_ALT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* aes.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/aes.h b/tools/sdk/include/mbedtls/mbedtls/aes.h
new file mode 100644
index 00000000..a36e825a
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/aes.h
@@ -0,0 +1,297 @@
+/**
+ * \file aes.h
+ *
+ * \brief AES block cipher
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_AES_H
+#define MBEDTLS_AES_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#include 
+#include 
+
+/* padlock.c and aesni.c rely on these values! */
+#define MBEDTLS_AES_ENCRYPT     1
+#define MBEDTLS_AES_DECRYPT     0
+
+#define MBEDTLS_ERR_AES_INVALID_KEY_LENGTH                -0x0020  /**< Invalid key length. */
+#define MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH              -0x0022  /**< Invalid data input length. */
+
+#if !defined(MBEDTLS_AES_ALT)
+// Regular implementation
+//
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          AES context structure
+ *
+ * \note           buf is able to hold 32 extra bytes, which can be used:
+ *                 - for alignment purposes if VIA padlock is used, and/or
+ *                 - to simplify key expansion in the 256-bit case by
+ *                 generating an extra round key
+ */
+typedef struct
+{
+    int nr;                     /*!<  number of rounds  */
+    uint32_t *rk;               /*!<  AES round keys    */
+    uint32_t buf[68];           /*!<  unaligned data    */
+}
+mbedtls_aes_context;
+
+/**
+ * \brief          Initialize AES context
+ *
+ * \param ctx      AES context to be initialized
+ */
+void mbedtls_aes_init( mbedtls_aes_context *ctx );
+
+/**
+ * \brief          Clear AES context
+ *
+ * \param ctx      AES context to be cleared
+ */
+void mbedtls_aes_free( mbedtls_aes_context *ctx );
+
+/**
+ * \brief          AES key schedule (encryption)
+ *
+ * \param ctx      AES context to be initialized
+ * \param key      encryption key
+ * \param keybits  must be 128, 192 or 256
+ *
+ * \return         0 if successful, or MBEDTLS_ERR_AES_INVALID_KEY_LENGTH
+ */
+int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key,
+                    unsigned int keybits );
+
+/**
+ * \brief          AES key schedule (decryption)
+ *
+ * \param ctx      AES context to be initialized
+ * \param key      decryption key
+ * \param keybits  must be 128, 192 or 256
+ *
+ * \return         0 if successful, or MBEDTLS_ERR_AES_INVALID_KEY_LENGTH
+ */
+int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key,
+                    unsigned int keybits );
+
+/**
+ * \brief          AES-ECB block encryption/decryption
+ *
+ * \param ctx      AES context
+ * \param mode     MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT
+ * \param input    16-byte input block
+ * \param output   16-byte output block
+ *
+ * \return         0 if successful
+ */
+int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx,
+                    int mode,
+                    const unsigned char input[16],
+                    unsigned char output[16] );
+
+#if defined(MBEDTLS_CIPHER_MODE_CBC)
+/**
+ * \brief          AES-CBC buffer encryption/decryption
+ *                 Length should be a multiple of the block
+ *                 size (16 bytes)
+ *
+ * \note           Upon exit, the content of the IV is updated so that you can
+ *                 call the function same function again on the following
+ *                 block(s) of data and get the same result as if it was
+ *                 encrypted in one call. This allows a "streaming" usage.
+ *                 If on the other hand you need to retain the contents of the
+ *                 IV, you should either save it manually or use the cipher
+ *                 module instead.
+ *
+ * \param ctx      AES context
+ * \param mode     MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT
+ * \param length   length of the input data
+ * \param iv       initialization vector (updated after use)
+ * \param input    buffer holding the input data
+ * \param output   buffer holding the output data
+ *
+ * \return         0 if successful, or MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH
+ */
+int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx,
+                    int mode,
+                    size_t length,
+                    unsigned char iv[16],
+                    const unsigned char *input,
+                    unsigned char *output );
+#endif /* MBEDTLS_CIPHER_MODE_CBC */
+
+#if defined(MBEDTLS_CIPHER_MODE_CFB)
+/**
+ * \brief          AES-CFB128 buffer encryption/decryption.
+ *
+ * Note: Due to the nature of CFB you should use the same key schedule for
+ * both encryption and decryption. So a context initialized with
+ * mbedtls_aes_setkey_enc() for both MBEDTLS_AES_ENCRYPT and MBEDTLS_AES_DECRYPT.
+ *
+ * \note           Upon exit, the content of the IV is updated so that you can
+ *                 call the function same function again on the following
+ *                 block(s) of data and get the same result as if it was
+ *                 encrypted in one call. This allows a "streaming" usage.
+ *                 If on the other hand you need to retain the contents of the
+ *                 IV, you should either save it manually or use the cipher
+ *                 module instead.
+ *
+ * \param ctx      AES context
+ * \param mode     MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT
+ * \param length   length of the input data
+ * \param iv_off   offset in IV (updated after use)
+ * \param iv       initialization vector (updated after use)
+ * \param input    buffer holding the input data
+ * \param output   buffer holding the output data
+ *
+ * \return         0 if successful
+ */
+int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx,
+                       int mode,
+                       size_t length,
+                       size_t *iv_off,
+                       unsigned char iv[16],
+                       const unsigned char *input,
+                       unsigned char *output );
+
+/**
+ * \brief          AES-CFB8 buffer encryption/decryption.
+ *
+ * Note: Due to the nature of CFB you should use the same key schedule for
+ * both encryption and decryption. So a context initialized with
+ * mbedtls_aes_setkey_enc() for both MBEDTLS_AES_ENCRYPT and MBEDTLS_AES_DECRYPT.
+ *
+ * \note           Upon exit, the content of the IV is updated so that you can
+ *                 call the function same function again on the following
+ *                 block(s) of data and get the same result as if it was
+ *                 encrypted in one call. This allows a "streaming" usage.
+ *                 If on the other hand you need to retain the contents of the
+ *                 IV, you should either save it manually or use the cipher
+ *                 module instead.
+ *
+ * \param ctx      AES context
+ * \param mode     MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT
+ * \param length   length of the input data
+ * \param iv       initialization vector (updated after use)
+ * \param input    buffer holding the input data
+ * \param output   buffer holding the output data
+ *
+ * \return         0 if successful
+ */
+int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx,
+                    int mode,
+                    size_t length,
+                    unsigned char iv[16],
+                    const unsigned char *input,
+                    unsigned char *output );
+#endif /*MBEDTLS_CIPHER_MODE_CFB */
+
+#if defined(MBEDTLS_CIPHER_MODE_CTR)
+/**
+ * \brief               AES-CTR buffer encryption/decryption
+ *
+ * Warning: You have to keep the maximum use of your counter in mind!
+ *
+ * Note: Due to the nature of CTR you should use the same key schedule for
+ * both encryption and decryption. So a context initialized with
+ * mbedtls_aes_setkey_enc() for both MBEDTLS_AES_ENCRYPT and MBEDTLS_AES_DECRYPT.
+ *
+ * \param ctx           AES context
+ * \param length        The length of the data
+ * \param nc_off        The offset in the current stream_block (for resuming
+ *                      within current cipher stream). The offset pointer to
+ *                      should be 0 at the start of a stream.
+ * \param nonce_counter The 128-bit nonce and counter.
+ * \param stream_block  The saved stream-block for resuming. Is overwritten
+ *                      by the function.
+ * \param input         The input data stream
+ * \param output        The output data stream
+ *
+ * \return         0 if successful
+ */
+int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx,
+                       size_t length,
+                       size_t *nc_off,
+                       unsigned char nonce_counter[16],
+                       unsigned char stream_block[16],
+                       const unsigned char *input,
+                       unsigned char *output );
+#endif /* MBEDTLS_CIPHER_MODE_CTR */
+
+/**
+ * \brief           Internal AES block encryption function
+ *                  (Only exposed to allow overriding it,
+ *                  see MBEDTLS_AES_ENCRYPT_ALT)
+ *
+ * \param ctx       AES context
+ * \param input     Plaintext block
+ * \param output    Output (ciphertext) block
+ */
+void mbedtls_aes_encrypt( mbedtls_aes_context *ctx,
+                          const unsigned char input[16],
+                          unsigned char output[16] );
+
+/**
+ * \brief           Internal AES block decryption function
+ *                  (Only exposed to allow overriding it,
+ *                  see MBEDTLS_AES_DECRYPT_ALT)
+ *
+ * \param ctx       AES context
+ * \param input     Ciphertext block
+ * \param output    Output (plaintext) block
+ */
+void mbedtls_aes_decrypt( mbedtls_aes_context *ctx,
+                          const unsigned char input[16],
+                          unsigned char output[16] );
+
+#ifdef __cplusplus
+}
+#endif
+
+#else  /* MBEDTLS_AES_ALT */
+#include "aes_alt.h"
+#endif /* MBEDTLS_AES_ALT */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          Checkup routine
+ *
+ * \return         0 if successful, or 1 if the test failed
+ */
+int mbedtls_aes_self_test( int verbose );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* aes.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/aesni.h b/tools/sdk/include/mbedtls/mbedtls/aesni.h
new file mode 100644
index 00000000..b1b7f1cd
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/aesni.h
@@ -0,0 +1,111 @@
+/**
+ * \file aesni.h
+ *
+ * \brief AES-NI for hardware AES acceleration on some Intel processors
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_AESNI_H
+#define MBEDTLS_AESNI_H
+
+#include "aes.h"
+
+#define MBEDTLS_AESNI_AES      0x02000000u
+#define MBEDTLS_AESNI_CLMUL    0x00000002u
+
+#if defined(MBEDTLS_HAVE_ASM) && defined(__GNUC__) &&  \
+    ( defined(__amd64__) || defined(__x86_64__) )   &&  \
+    ! defined(MBEDTLS_HAVE_X86_64)
+#define MBEDTLS_HAVE_X86_64
+#endif
+
+#if defined(MBEDTLS_HAVE_X86_64)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          AES-NI features detection routine
+ *
+ * \param what     The feature to detect
+ *                 (MBEDTLS_AESNI_AES or MBEDTLS_AESNI_CLMUL)
+ *
+ * \return         1 if CPU has support for the feature, 0 otherwise
+ */
+int mbedtls_aesni_has_support( unsigned int what );
+
+/**
+ * \brief          AES-NI AES-ECB block en(de)cryption
+ *
+ * \param ctx      AES context
+ * \param mode     MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT
+ * \param input    16-byte input block
+ * \param output   16-byte output block
+ *
+ * \return         0 on success (cannot fail)
+ */
+int mbedtls_aesni_crypt_ecb( mbedtls_aes_context *ctx,
+                     int mode,
+                     const unsigned char input[16],
+                     unsigned char output[16] );
+
+/**
+ * \brief          GCM multiplication: c = a * b in GF(2^128)
+ *
+ * \param c        Result
+ * \param a        First operand
+ * \param b        Second operand
+ *
+ * \note           Both operands and result are bit strings interpreted as
+ *                 elements of GF(2^128) as per the GCM spec.
+ */
+void mbedtls_aesni_gcm_mult( unsigned char c[16],
+                     const unsigned char a[16],
+                     const unsigned char b[16] );
+
+/**
+ * \brief           Compute decryption round keys from encryption round keys
+ *
+ * \param invkey    Round keys for the equivalent inverse cipher
+ * \param fwdkey    Original round keys (for encryption)
+ * \param nr        Number of rounds (that is, number of round keys minus one)
+ */
+void mbedtls_aesni_inverse_key( unsigned char *invkey,
+                        const unsigned char *fwdkey, int nr );
+
+/**
+ * \brief           Perform key expansion (for encryption)
+ *
+ * \param rk        Destination buffer where the round keys are written
+ * \param key       Encryption key
+ * \param bits      Key size in bits (must be 128, 192 or 256)
+ *
+ * \return          0 if successful, or MBEDTLS_ERR_AES_INVALID_KEY_LENGTH
+ */
+int mbedtls_aesni_setkey_enc( unsigned char *rk,
+                      const unsigned char *key,
+                      size_t bits );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MBEDTLS_HAVE_X86_64 */
+
+#endif /* MBEDTLS_AESNI_H */
diff --git a/tools/sdk/include/mbedtls/mbedtls/arc4.h b/tools/sdk/include/mbedtls/mbedtls/arc4.h
new file mode 100644
index 00000000..5fc5395a
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/arc4.h
@@ -0,0 +1,113 @@
+/**
+ * \file arc4.h
+ *
+ * \brief The ARCFOUR stream cipher
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_ARC4_H
+#define MBEDTLS_ARC4_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#include 
+
+#if !defined(MBEDTLS_ARC4_ALT)
+// Regular implementation
+//
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          ARC4 context structure
+ */
+typedef struct
+{
+    int x;                      /*!< permutation index */
+    int y;                      /*!< permutation index */
+    unsigned char m[256];       /*!< permutation table */
+}
+mbedtls_arc4_context;
+
+/**
+ * \brief          Initialize ARC4 context
+ *
+ * \param ctx      ARC4 context to be initialized
+ */
+void mbedtls_arc4_init( mbedtls_arc4_context *ctx );
+
+/**
+ * \brief          Clear ARC4 context
+ *
+ * \param ctx      ARC4 context to be cleared
+ */
+void mbedtls_arc4_free( mbedtls_arc4_context *ctx );
+
+/**
+ * \brief          ARC4 key schedule
+ *
+ * \param ctx      ARC4 context to be setup
+ * \param key      the secret key
+ * \param keylen   length of the key, in bytes
+ */
+void mbedtls_arc4_setup( mbedtls_arc4_context *ctx, const unsigned char *key,
+                 unsigned int keylen );
+
+/**
+ * \brief          ARC4 cipher function
+ *
+ * \param ctx      ARC4 context
+ * \param length   length of the input data
+ * \param input    buffer holding the input data
+ * \param output   buffer for the output data
+ *
+ * \return         0 if successful
+ */
+int mbedtls_arc4_crypt( mbedtls_arc4_context *ctx, size_t length, const unsigned char *input,
+                unsigned char *output );
+
+#ifdef __cplusplus
+}
+#endif
+
+#else  /* MBEDTLS_ARC4_ALT */
+#include "arc4_alt.h"
+#endif /* MBEDTLS_ARC4_ALT */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          Checkup routine
+ *
+ * \return         0 if successful, or 1 if the test failed
+ */
+int mbedtls_arc4_self_test( int verbose );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* arc4.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/asn1.h b/tools/sdk/include/mbedtls/mbedtls/asn1.h
new file mode 100644
index 00000000..082832c8
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/asn1.h
@@ -0,0 +1,342 @@
+/**
+ * \file asn1.h
+ *
+ * \brief Generic ASN.1 parsing
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_ASN1_H
+#define MBEDTLS_ASN1_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#include 
+
+#if defined(MBEDTLS_BIGNUM_C)
+#include "bignum.h"
+#endif
+
+/**
+ * \addtogroup asn1_module
+ * \{
+ */
+
+/**
+ * \name ASN1 Error codes
+ * These error codes are OR'ed to X509 error codes for
+ * higher error granularity.
+ * ASN1 is a standard to specify data structures.
+ * \{
+ */
+#define MBEDTLS_ERR_ASN1_OUT_OF_DATA                      -0x0060  /**< Out of data when parsing an ASN1 data structure. */
+#define MBEDTLS_ERR_ASN1_UNEXPECTED_TAG                   -0x0062  /**< ASN1 tag was of an unexpected value. */
+#define MBEDTLS_ERR_ASN1_INVALID_LENGTH                   -0x0064  /**< Error when trying to determine the length or invalid length. */
+#define MBEDTLS_ERR_ASN1_LENGTH_MISMATCH                  -0x0066  /**< Actual length differs from expected length. */
+#define MBEDTLS_ERR_ASN1_INVALID_DATA                     -0x0068  /**< Data is invalid. (not used) */
+#define MBEDTLS_ERR_ASN1_ALLOC_FAILED                     -0x006A  /**< Memory allocation failed */
+#define MBEDTLS_ERR_ASN1_BUF_TOO_SMALL                    -0x006C  /**< Buffer too small when writing ASN.1 data structure. */
+
+/* \} name */
+
+/**
+ * \name DER constants
+ * These constants comply with DER encoded the ANS1 type tags.
+ * DER encoding uses hexadecimal representation.
+ * An example DER sequence is:\n
+ * - 0x02 -- tag indicating INTEGER
+ * - 0x01 -- length in octets
+ * - 0x05 -- value
+ * Such sequences are typically read into \c ::mbedtls_x509_buf.
+ * \{
+ */
+#define MBEDTLS_ASN1_BOOLEAN                 0x01
+#define MBEDTLS_ASN1_INTEGER                 0x02
+#define MBEDTLS_ASN1_BIT_STRING              0x03
+#define MBEDTLS_ASN1_OCTET_STRING            0x04
+#define MBEDTLS_ASN1_NULL                    0x05
+#define MBEDTLS_ASN1_OID                     0x06
+#define MBEDTLS_ASN1_UTF8_STRING             0x0C
+#define MBEDTLS_ASN1_SEQUENCE                0x10
+#define MBEDTLS_ASN1_SET                     0x11
+#define MBEDTLS_ASN1_PRINTABLE_STRING        0x13
+#define MBEDTLS_ASN1_T61_STRING              0x14
+#define MBEDTLS_ASN1_IA5_STRING              0x16
+#define MBEDTLS_ASN1_UTC_TIME                0x17
+#define MBEDTLS_ASN1_GENERALIZED_TIME        0x18
+#define MBEDTLS_ASN1_UNIVERSAL_STRING        0x1C
+#define MBEDTLS_ASN1_BMP_STRING              0x1E
+#define MBEDTLS_ASN1_PRIMITIVE               0x00
+#define MBEDTLS_ASN1_CONSTRUCTED             0x20
+#define MBEDTLS_ASN1_CONTEXT_SPECIFIC        0x80
+/* \} name */
+/* \} addtogroup asn1_module */
+
+/** Returns the size of the binary string, without the trailing \\0 */
+#define MBEDTLS_OID_SIZE(x) (sizeof(x) - 1)
+
+/**
+ * Compares an mbedtls_asn1_buf structure to a reference OID.
+ *
+ * Only works for 'defined' oid_str values (MBEDTLS_OID_HMAC_SHA1), you cannot use a
+ * 'unsigned char *oid' here!
+ */
+#define MBEDTLS_OID_CMP(oid_str, oid_buf)                                   \
+        ( ( MBEDTLS_OID_SIZE(oid_str) != (oid_buf)->len ) ||                \
+          memcmp( (oid_str), (oid_buf)->p, (oid_buf)->len) != 0 )
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \name Functions to parse ASN.1 data structures
+ * \{
+ */
+
+/**
+ * Type-length-value structure that allows for ASN1 using DER.
+ */
+typedef struct mbedtls_asn1_buf
+{
+    int tag;                /**< ASN1 type, e.g. MBEDTLS_ASN1_UTF8_STRING. */
+    size_t len;             /**< ASN1 length, in octets. */
+    unsigned char *p;       /**< ASN1 data, e.g. in ASCII. */
+}
+mbedtls_asn1_buf;
+
+/**
+ * Container for ASN1 bit strings.
+ */
+typedef struct mbedtls_asn1_bitstring
+{
+    size_t len;                 /**< ASN1 length, in octets. */
+    unsigned char unused_bits;  /**< Number of unused bits at the end of the string */
+    unsigned char *p;           /**< Raw ASN1 data for the bit string */
+}
+mbedtls_asn1_bitstring;
+
+/**
+ * Container for a sequence of ASN.1 items
+ */
+typedef struct mbedtls_asn1_sequence
+{
+    mbedtls_asn1_buf buf;                   /**< Buffer containing the given ASN.1 item. */
+    struct mbedtls_asn1_sequence *next;    /**< The next entry in the sequence. */
+}
+mbedtls_asn1_sequence;
+
+/**
+ * Container for a sequence or list of 'named' ASN.1 data items
+ */
+typedef struct mbedtls_asn1_named_data
+{
+    mbedtls_asn1_buf oid;                   /**< The object identifier. */
+    mbedtls_asn1_buf val;                   /**< The named value. */
+    struct mbedtls_asn1_named_data *next;  /**< The next entry in the sequence. */
+    unsigned char next_merged;      /**< Merge next item into the current one? */
+}
+mbedtls_asn1_named_data;
+
+/**
+ * \brief       Get the length of an ASN.1 element.
+ *              Updates the pointer to immediately behind the length.
+ *
+ * \param p     The position in the ASN.1 data
+ * \param end   End of data
+ * \param len   The variable that will receive the value
+ *
+ * \return      0 if successful, MBEDTLS_ERR_ASN1_OUT_OF_DATA on reaching
+ *              end of data, MBEDTLS_ERR_ASN1_INVALID_LENGTH if length is
+ *              unparseable.
+ */
+int mbedtls_asn1_get_len( unsigned char **p,
+                  const unsigned char *end,
+                  size_t *len );
+
+/**
+ * \brief       Get the tag and length of the tag. Check for the requested tag.
+ *              Updates the pointer to immediately behind the tag and length.
+ *
+ * \param p     The position in the ASN.1 data
+ * \param end   End of data
+ * \param len   The variable that will receive the length
+ * \param tag   The expected tag
+ *
+ * \return      0 if successful, MBEDTLS_ERR_ASN1_UNEXPECTED_TAG if tag did
+ *              not match requested tag, or another specific ASN.1 error code.
+ */
+int mbedtls_asn1_get_tag( unsigned char **p,
+                  const unsigned char *end,
+                  size_t *len, int tag );
+
+/**
+ * \brief       Retrieve a boolean ASN.1 tag and its value.
+ *              Updates the pointer to immediately behind the full tag.
+ *
+ * \param p     The position in the ASN.1 data
+ * \param end   End of data
+ * \param val   The variable that will receive the value
+ *
+ * \return      0 if successful or a specific ASN.1 error code.
+ */
+int mbedtls_asn1_get_bool( unsigned char **p,
+                   const unsigned char *end,
+                   int *val );
+
+/**
+ * \brief       Retrieve an integer ASN.1 tag and its value.
+ *              Updates the pointer to immediately behind the full tag.
+ *
+ * \param p     The position in the ASN.1 data
+ * \param end   End of data
+ * \param val   The variable that will receive the value
+ *
+ * \return      0 if successful or a specific ASN.1 error code.
+ */
+int mbedtls_asn1_get_int( unsigned char **p,
+                  const unsigned char *end,
+                  int *val );
+
+/**
+ * \brief       Retrieve a bitstring ASN.1 tag and its value.
+ *              Updates the pointer to immediately behind the full tag.
+ *
+ * \param p     The position in the ASN.1 data
+ * \param end   End of data
+ * \param bs    The variable that will receive the value
+ *
+ * \return      0 if successful or a specific ASN.1 error code.
+ */
+int mbedtls_asn1_get_bitstring( unsigned char **p, const unsigned char *end,
+                        mbedtls_asn1_bitstring *bs);
+
+/**
+ * \brief       Retrieve a bitstring ASN.1 tag without unused bits and its
+ *              value.
+ *              Updates the pointer to the beginning of the bit/octet string.
+ *
+ * \param p     The position in the ASN.1 data
+ * \param end   End of data
+ * \param len   Length of the actual bit/octect string in bytes
+ *
+ * \return      0 if successful or a specific ASN.1 error code.
+ */
+int mbedtls_asn1_get_bitstring_null( unsigned char **p, const unsigned char *end,
+                             size_t *len );
+
+/**
+ * \brief       Parses and splits an ASN.1 "SEQUENCE OF "
+ *              Updated the pointer to immediately behind the full sequence tag.
+ *
+ * \param p     The position in the ASN.1 data
+ * \param end   End of data
+ * \param cur   First variable in the chain to fill
+ * \param tag   Type of sequence
+ *
+ * \return      0 if successful or a specific ASN.1 error code.
+ */
+int mbedtls_asn1_get_sequence_of( unsigned char **p,
+                          const unsigned char *end,
+                          mbedtls_asn1_sequence *cur,
+                          int tag);
+
+#if defined(MBEDTLS_BIGNUM_C)
+/**
+ * \brief       Retrieve a MPI value from an integer ASN.1 tag.
+ *              Updates the pointer to immediately behind the full tag.
+ *
+ * \param p     The position in the ASN.1 data
+ * \param end   End of data
+ * \param X     The MPI that will receive the value
+ *
+ * \return      0 if successful or a specific ASN.1 or MPI error code.
+ */
+int mbedtls_asn1_get_mpi( unsigned char **p,
+                  const unsigned char *end,
+                  mbedtls_mpi *X );
+#endif /* MBEDTLS_BIGNUM_C */
+
+/**
+ * \brief       Retrieve an AlgorithmIdentifier ASN.1 sequence.
+ *              Updates the pointer to immediately behind the full
+ *              AlgorithmIdentifier.
+ *
+ * \param p     The position in the ASN.1 data
+ * \param end   End of data
+ * \param alg   The buffer to receive the OID
+ * \param params The buffer to receive the params (if any)
+ *
+ * \return      0 if successful or a specific ASN.1 or MPI error code.
+ */
+int mbedtls_asn1_get_alg( unsigned char **p,
+                  const unsigned char *end,
+                  mbedtls_asn1_buf *alg, mbedtls_asn1_buf *params );
+
+/**
+ * \brief       Retrieve an AlgorithmIdentifier ASN.1 sequence with NULL or no
+ *              params.
+ *              Updates the pointer to immediately behind the full
+ *              AlgorithmIdentifier.
+ *
+ * \param p     The position in the ASN.1 data
+ * \param end   End of data
+ * \param alg   The buffer to receive the OID
+ *
+ * \return      0 if successful or a specific ASN.1 or MPI error code.
+ */
+int mbedtls_asn1_get_alg_null( unsigned char **p,
+                       const unsigned char *end,
+                       mbedtls_asn1_buf *alg );
+
+/**
+ * \brief       Find a specific named_data entry in a sequence or list based on
+ *              the OID.
+ *
+ * \param list  The list to seek through
+ * \param oid   The OID to look for
+ * \param len   Size of the OID
+ *
+ * \return      NULL if not found, or a pointer to the existing entry.
+ */
+mbedtls_asn1_named_data *mbedtls_asn1_find_named_data( mbedtls_asn1_named_data *list,
+                                       const char *oid, size_t len );
+
+/**
+ * \brief       Free a mbedtls_asn1_named_data entry
+ *
+ * \param entry The named data entry to free
+ */
+void mbedtls_asn1_free_named_data( mbedtls_asn1_named_data *entry );
+
+/**
+ * \brief       Free all entries in a mbedtls_asn1_named_data list
+ *              Head will be set to NULL
+ *
+ * \param head  Pointer to the head of the list of named data entries to free
+ */
+void mbedtls_asn1_free_named_data_list( mbedtls_asn1_named_data **head );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* asn1.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/asn1write.h b/tools/sdk/include/mbedtls/mbedtls/asn1write.h
new file mode 100644
index 00000000..73ff32b6
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/asn1write.h
@@ -0,0 +1,239 @@
+/**
+ * \file asn1write.h
+ *
+ * \brief ASN.1 buffer writing functionality
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_ASN1_WRITE_H
+#define MBEDTLS_ASN1_WRITE_H
+
+#include "asn1.h"
+
+#define MBEDTLS_ASN1_CHK_ADD(g, f) do { if( ( ret = f ) < 0 ) return( ret ); else   \
+                                g += ret; } while( 0 )
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief           Write a length field in ASN.1 format
+ *                  Note: function works backwards in data buffer
+ *
+ * \param p         reference to current position pointer
+ * \param start     start of the buffer (for bounds-checking)
+ * \param len       the length to write
+ *
+ * \return          the length written or a negative error code
+ */
+int mbedtls_asn1_write_len( unsigned char **p, unsigned char *start, size_t len );
+
+/**
+ * \brief           Write a ASN.1 tag in ASN.1 format
+ *                  Note: function works backwards in data buffer
+ *
+ * \param p         reference to current position pointer
+ * \param start     start of the buffer (for bounds-checking)
+ * \param tag       the tag to write
+ *
+ * \return          the length written or a negative error code
+ */
+int mbedtls_asn1_write_tag( unsigned char **p, unsigned char *start,
+                    unsigned char tag );
+
+/**
+ * \brief           Write raw buffer data
+ *                  Note: function works backwards in data buffer
+ *
+ * \param p         reference to current position pointer
+ * \param start     start of the buffer (for bounds-checking)
+ * \param buf       data buffer to write
+ * \param size      length of the data buffer
+ *
+ * \return          the length written or a negative error code
+ */
+int mbedtls_asn1_write_raw_buffer( unsigned char **p, unsigned char *start,
+                           const unsigned char *buf, size_t size );
+
+#if defined(MBEDTLS_BIGNUM_C)
+/**
+ * \brief           Write a big number (MBEDTLS_ASN1_INTEGER) in ASN.1 format
+ *                  Note: function works backwards in data buffer
+ *
+ * \param p         reference to current position pointer
+ * \param start     start of the buffer (for bounds-checking)
+ * \param X         the MPI to write
+ *
+ * \return          the length written or a negative error code
+ */
+int mbedtls_asn1_write_mpi( unsigned char **p, unsigned char *start, const mbedtls_mpi *X );
+#endif /* MBEDTLS_BIGNUM_C */
+
+/**
+ * \brief           Write a NULL tag (MBEDTLS_ASN1_NULL) with zero data in ASN.1 format
+ *                  Note: function works backwards in data buffer
+ *
+ * \param p         reference to current position pointer
+ * \param start     start of the buffer (for bounds-checking)
+ *
+ * \return          the length written or a negative error code
+ */
+int mbedtls_asn1_write_null( unsigned char **p, unsigned char *start );
+
+/**
+ * \brief           Write an OID tag (MBEDTLS_ASN1_OID) and data in ASN.1 format
+ *                  Note: function works backwards in data buffer
+ *
+ * \param p         reference to current position pointer
+ * \param start     start of the buffer (for bounds-checking)
+ * \param oid       the OID to write
+ * \param oid_len   length of the OID
+ *
+ * \return          the length written or a negative error code
+ */
+int mbedtls_asn1_write_oid( unsigned char **p, unsigned char *start,
+                    const char *oid, size_t oid_len );
+
+/**
+ * \brief           Write an AlgorithmIdentifier sequence in ASN.1 format
+ *                  Note: function works backwards in data buffer
+ *
+ * \param p         reference to current position pointer
+ * \param start     start of the buffer (for bounds-checking)
+ * \param oid       the OID of the algorithm
+ * \param oid_len   length of the OID
+ * \param par_len   length of parameters, which must be already written.
+ *                  If 0, NULL parameters are added
+ *
+ * \return          the length written or a negative error code
+ */
+int mbedtls_asn1_write_algorithm_identifier( unsigned char **p, unsigned char *start,
+                                     const char *oid, size_t oid_len,
+                                     size_t par_len );
+
+/**
+ * \brief           Write a boolean tag (MBEDTLS_ASN1_BOOLEAN) and value in ASN.1 format
+ *                  Note: function works backwards in data buffer
+ *
+ * \param p         reference to current position pointer
+ * \param start     start of the buffer (for bounds-checking)
+ * \param boolean   0 or 1
+ *
+ * \return          the length written or a negative error code
+ */
+int mbedtls_asn1_write_bool( unsigned char **p, unsigned char *start, int boolean );
+
+/**
+ * \brief           Write an int tag (MBEDTLS_ASN1_INTEGER) and value in ASN.1 format
+ *                  Note: function works backwards in data buffer
+ *
+ * \param p         reference to current position pointer
+ * \param start     start of the buffer (for bounds-checking)
+ * \param val       the integer value
+ *
+ * \return          the length written or a negative error code
+ */
+int mbedtls_asn1_write_int( unsigned char **p, unsigned char *start, int val );
+
+/**
+ * \brief           Write a printable string tag (MBEDTLS_ASN1_PRINTABLE_STRING) and
+ *                  value in ASN.1 format
+ *                  Note: function works backwards in data buffer
+ *
+ * \param p         reference to current position pointer
+ * \param start     start of the buffer (for bounds-checking)
+ * \param text      the text to write
+ * \param text_len  length of the text
+ *
+ * \return          the length written or a negative error code
+ */
+int mbedtls_asn1_write_printable_string( unsigned char **p, unsigned char *start,
+                                 const char *text, size_t text_len );
+
+/**
+ * \brief           Write an IA5 string tag (MBEDTLS_ASN1_IA5_STRING) and
+ *                  value in ASN.1 format
+ *                  Note: function works backwards in data buffer
+ *
+ * \param p         reference to current position pointer
+ * \param start     start of the buffer (for bounds-checking)
+ * \param text      the text to write
+ * \param text_len  length of the text
+ *
+ * \return          the length written or a negative error code
+ */
+int mbedtls_asn1_write_ia5_string( unsigned char **p, unsigned char *start,
+                           const char *text, size_t text_len );
+
+/**
+ * \brief           Write a bitstring tag (MBEDTLS_ASN1_BIT_STRING) and
+ *                  value in ASN.1 format
+ *                  Note: function works backwards in data buffer
+ *
+ * \param p         reference to current position pointer
+ * \param start     start of the buffer (for bounds-checking)
+ * \param buf       the bitstring
+ * \param bits      the total number of bits in the bitstring
+ *
+ * \return          the length written or a negative error code
+ */
+int mbedtls_asn1_write_bitstring( unsigned char **p, unsigned char *start,
+                          const unsigned char *buf, size_t bits );
+
+/**
+ * \brief           Write an octet string tag (MBEDTLS_ASN1_OCTET_STRING) and
+ *                  value in ASN.1 format
+ *                  Note: function works backwards in data buffer
+ *
+ * \param p         reference to current position pointer
+ * \param start     start of the buffer (for bounds-checking)
+ * \param buf       data buffer to write
+ * \param size      length of the data buffer
+ *
+ * \return          the length written or a negative error code
+ */
+int mbedtls_asn1_write_octet_string( unsigned char **p, unsigned char *start,
+                             const unsigned char *buf, size_t size );
+
+/**
+ * \brief           Create or find a specific named_data entry for writing in a
+ *                  sequence or list based on the OID. If not already in there,
+ *                  a new entry is added to the head of the list.
+ *                  Warning: Destructive behaviour for the val data!
+ *
+ * \param list      Pointer to the location of the head of the list to seek
+ *                  through (will be updated in case of a new entry)
+ * \param oid       The OID to look for
+ * \param oid_len   Size of the OID
+ * \param val       Data to store (can be NULL if you want to fill it by hand)
+ * \param val_len   Minimum length of the data buffer needed
+ *
+ * \return      NULL if if there was a memory allocation error, or a pointer
+ *              to the new / existing entry.
+ */
+mbedtls_asn1_named_data *mbedtls_asn1_store_named_data( mbedtls_asn1_named_data **list,
+                                        const char *oid, size_t oid_len,
+                                        const unsigned char *val,
+                                        size_t val_len );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MBEDTLS_ASN1_WRITE_H */
diff --git a/tools/sdk/include/mbedtls/mbedtls/base64.h b/tools/sdk/include/mbedtls/mbedtls/base64.h
new file mode 100644
index 00000000..352c652d
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/base64.h
@@ -0,0 +1,88 @@
+/**
+ * \file base64.h
+ *
+ * \brief RFC 1521 base64 encoding/decoding
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_BASE64_H
+#define MBEDTLS_BASE64_H
+
+#include 
+
+#define MBEDTLS_ERR_BASE64_BUFFER_TOO_SMALL               -0x002A  /**< Output buffer too small. */
+#define MBEDTLS_ERR_BASE64_INVALID_CHARACTER              -0x002C  /**< Invalid character in input. */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          Encode a buffer into base64 format
+ *
+ * \param dst      destination buffer
+ * \param dlen     size of the destination buffer
+ * \param olen     number of bytes written
+ * \param src      source buffer
+ * \param slen     amount of data to be encoded
+ *
+ * \return         0 if successful, or MBEDTLS_ERR_BASE64_BUFFER_TOO_SMALL.
+ *                 *olen is always updated to reflect the amount
+ *                 of data that has (or would have) been written.
+ *                 If that length cannot be represented, then no data is
+ *                 written to the buffer and *olen is set to the maximum
+ *                 length representable as a size_t.
+ *
+ * \note           Call this function with dlen = 0 to obtain the
+ *                 required buffer size in *olen
+ */
+int mbedtls_base64_encode( unsigned char *dst, size_t dlen, size_t *olen,
+                   const unsigned char *src, size_t slen );
+
+/**
+ * \brief          Decode a base64-formatted buffer
+ *
+ * \param dst      destination buffer (can be NULL for checking size)
+ * \param dlen     size of the destination buffer
+ * \param olen     number of bytes written
+ * \param src      source buffer
+ * \param slen     amount of data to be decoded
+ *
+ * \return         0 if successful, MBEDTLS_ERR_BASE64_BUFFER_TOO_SMALL, or
+ *                 MBEDTLS_ERR_BASE64_INVALID_CHARACTER if the input data is
+ *                 not correct. *olen is always updated to reflect the amount
+ *                 of data that has (or would have) been written.
+ *
+ * \note           Call this function with *dst = NULL or dlen = 0 to obtain
+ *                 the required buffer size in *olen
+ */
+int mbedtls_base64_decode( unsigned char *dst, size_t dlen, size_t *olen,
+                   const unsigned char *src, size_t slen );
+
+/**
+ * \brief          Checkup routine
+ *
+ * \return         0 if successful, or 1 if the test failed
+ */
+int mbedtls_base64_self_test( int verbose );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* base64.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/bignum.h b/tools/sdk/include/mbedtls/mbedtls/bignum.h
new file mode 100644
index 00000000..46f25076
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/bignum.h
@@ -0,0 +1,722 @@
+/**
+ * \file bignum.h
+ *
+ * \brief  Multi-precision integer library
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_BIGNUM_H
+#define MBEDTLS_BIGNUM_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#include 
+#include 
+
+#if defined(MBEDTLS_FS_IO)
+#include 
+#endif
+
+#define MBEDTLS_ERR_MPI_FILE_IO_ERROR                     -0x0002  /**< An error occurred while reading from or writing to a file. */
+#define MBEDTLS_ERR_MPI_BAD_INPUT_DATA                    -0x0004  /**< Bad input parameters to function. */
+#define MBEDTLS_ERR_MPI_INVALID_CHARACTER                 -0x0006  /**< There is an invalid character in the digit string. */
+#define MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL                  -0x0008  /**< The buffer is too small to write to. */
+#define MBEDTLS_ERR_MPI_NEGATIVE_VALUE                    -0x000A  /**< The input arguments are negative or result in illegal output. */
+#define MBEDTLS_ERR_MPI_DIVISION_BY_ZERO                  -0x000C  /**< The input argument for division is zero, which is not allowed. */
+#define MBEDTLS_ERR_MPI_NOT_ACCEPTABLE                    -0x000E  /**< The input arguments are not acceptable. */
+#define MBEDTLS_ERR_MPI_ALLOC_FAILED                      -0x0010  /**< Memory allocation failed. */
+
+#define MBEDTLS_MPI_CHK(f) do { if( ( ret = f ) != 0 ) goto cleanup; } while( 0 )
+
+/*
+ * Maximum size MPIs are allowed to grow to in number of limbs.
+ */
+#define MBEDTLS_MPI_MAX_LIMBS                             10000
+
+#if !defined(MBEDTLS_MPI_WINDOW_SIZE)
+/*
+ * Maximum window size used for modular exponentiation. Default: 6
+ * Minimum value: 1. Maximum value: 6.
+ *
+ * Result is an array of ( 2 << MBEDTLS_MPI_WINDOW_SIZE ) MPIs used
+ * for the sliding window calculation. (So 64 by default)
+ *
+ * Reduction in size, reduces speed.
+ */
+#define MBEDTLS_MPI_WINDOW_SIZE                           6        /**< Maximum windows size used. */
+#endif /* !MBEDTLS_MPI_WINDOW_SIZE */
+
+#if !defined(MBEDTLS_MPI_MAX_SIZE)
+/*
+ * Maximum size of MPIs allowed in bits and bytes for user-MPIs.
+ * ( Default: 512 bytes => 4096 bits, Maximum tested: 2048 bytes => 16384 bits )
+ *
+ * Note: Calculations can results temporarily in larger MPIs. So the number
+ * of limbs required (MBEDTLS_MPI_MAX_LIMBS) is higher.
+ */
+#define MBEDTLS_MPI_MAX_SIZE                              1024     /**< Maximum number of bytes for usable MPIs. */
+#endif /* !MBEDTLS_MPI_MAX_SIZE */
+
+#define MBEDTLS_MPI_MAX_BITS                              ( 8 * MBEDTLS_MPI_MAX_SIZE )    /**< Maximum number of bits for usable MPIs. */
+
+/*
+ * When reading from files with mbedtls_mpi_read_file() and writing to files with
+ * mbedtls_mpi_write_file() the buffer should have space
+ * for a (short) label, the MPI (in the provided radix), the newline
+ * characters and the '\0'.
+ *
+ * By default we assume at least a 10 char label, a minimum radix of 10
+ * (decimal) and a maximum of 4096 bit numbers (1234 decimal chars).
+ * Autosized at compile time for at least a 10 char label, a minimum radix
+ * of 10 (decimal) for a number of MBEDTLS_MPI_MAX_BITS size.
+ *
+ * This used to be statically sized to 1250 for a maximum of 4096 bit
+ * numbers (1234 decimal chars).
+ *
+ * Calculate using the formula:
+ *  MBEDTLS_MPI_RW_BUFFER_SIZE = ceil(MBEDTLS_MPI_MAX_BITS / ln(10) * ln(2)) +
+ *                                LabelSize + 6
+ */
+#define MBEDTLS_MPI_MAX_BITS_SCALE100          ( 100 * MBEDTLS_MPI_MAX_BITS )
+#define MBEDTLS_LN_2_DIV_LN_10_SCALE100                 332
+#define MBEDTLS_MPI_RW_BUFFER_SIZE             ( ((MBEDTLS_MPI_MAX_BITS_SCALE100 + MBEDTLS_LN_2_DIV_LN_10_SCALE100 - 1) / MBEDTLS_LN_2_DIV_LN_10_SCALE100) + 10 + 6 )
+
+#if !defined(MBEDTLS_BIGNUM_ALT)
+
+/*
+ * Define the base integer type, architecture-wise.
+ *
+ * 32-bit integers can be forced on 64-bit arches (eg. for testing purposes)
+ * by defining MBEDTLS_HAVE_INT32 and undefining MBEDTLS_HAVE_ASM
+ */
+#if ( ! defined(MBEDTLS_HAVE_INT32) && \
+        defined(_MSC_VER) && defined(_M_AMD64) )
+  #define MBEDTLS_HAVE_INT64
+  typedef  int64_t mbedtls_mpi_sint;
+  typedef uint64_t mbedtls_mpi_uint;
+#else
+  #if ( ! defined(MBEDTLS_HAVE_INT32) &&               \
+        defined(__GNUC__) && (                          \
+        defined(__amd64__) || defined(__x86_64__)    || \
+        defined(__ppc64__) || defined(__powerpc64__) || \
+        defined(__ia64__)  || defined(__alpha__)     || \
+        (defined(__sparc__) && defined(__arch64__))  || \
+        defined(__s390x__) || defined(__mips64) ) )
+     #define MBEDTLS_HAVE_INT64
+     typedef  int64_t mbedtls_mpi_sint;
+     typedef uint64_t mbedtls_mpi_uint;
+     /* mbedtls_t_udbl defined as 128-bit unsigned int */
+     typedef unsigned int mbedtls_t_udbl __attribute__((mode(TI)));
+     #define MBEDTLS_HAVE_UDBL
+  #else
+     #define MBEDTLS_HAVE_INT32
+     typedef  int32_t mbedtls_mpi_sint;
+     typedef uint32_t mbedtls_mpi_uint;
+     typedef uint64_t mbedtls_t_udbl;
+     #define MBEDTLS_HAVE_UDBL
+  #endif /* !MBEDTLS_HAVE_INT32 && __GNUC__ && 64-bit platform */
+#endif /* !MBEDTLS_HAVE_INT32 && _MSC_VER && _M_AMD64 */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          MPI structure
+ */
+typedef struct
+{
+    int s;              /*!<  integer sign      */
+    size_t n;           /*!<  total # of limbs  */
+    mbedtls_mpi_uint *p;          /*!<  pointer to limbs  */
+}
+mbedtls_mpi;
+
+/**
+ * \brief           Initialize one MPI (make internal references valid)
+ *                  This just makes it ready to be set or freed,
+ *                  but does not define a value for the MPI.
+ *
+ * \param X         One MPI to initialize.
+ */
+void mbedtls_mpi_init( mbedtls_mpi *X );
+
+/**
+ * \brief          Unallocate one MPI
+ *
+ * \param X        One MPI to unallocate.
+ */
+void mbedtls_mpi_free( mbedtls_mpi *X );
+
+/**
+ * \brief          Enlarge to the specified number of limbs
+ *
+ * \param X        MPI to grow
+ * \param nblimbs  The target number of limbs
+ *
+ * \return         0 if successful,
+ *                 MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed
+ */
+int mbedtls_mpi_grow( mbedtls_mpi *X, size_t nblimbs );
+
+/**
+ * \brief          Resize down, keeping at least the specified number of limbs
+ *
+ * \param X        MPI to shrink
+ * \param nblimbs  The minimum number of limbs to keep
+ *
+ * \return         0 if successful,
+ *                 MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed
+ */
+int mbedtls_mpi_shrink( mbedtls_mpi *X, size_t nblimbs );
+
+/**
+ * \brief          Copy the contents of Y into X
+ *
+ * \param X        Destination MPI
+ * \param Y        Source MPI
+ *
+ * \return         0 if successful,
+ *                 MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed
+ */
+int mbedtls_mpi_copy( mbedtls_mpi *X, const mbedtls_mpi *Y );
+
+/**
+ * \brief          Swap the contents of X and Y
+ *
+ * \param X        First MPI value
+ * \param Y        Second MPI value
+ */
+void mbedtls_mpi_swap( mbedtls_mpi *X, mbedtls_mpi *Y );
+
+/**
+ * \brief          Safe conditional assignement X = Y if assign is 1
+ *
+ * \param X        MPI to conditionally assign to
+ * \param Y        Value to be assigned
+ * \param assign   1: perform the assignment, 0: keep X's original value
+ *
+ * \return         0 if successful,
+ *                 MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed,
+ *
+ * \note           This function is equivalent to
+ *                      if( assign ) mbedtls_mpi_copy( X, Y );
+ *                 except that it avoids leaking any information about whether
+ *                 the assignment was done or not (the above code may leak
+ *                 information through branch prediction and/or memory access
+ *                 patterns analysis).
+ */
+int mbedtls_mpi_safe_cond_assign( mbedtls_mpi *X, const mbedtls_mpi *Y, unsigned char assign );
+
+/**
+ * \brief          Safe conditional swap X <-> Y if swap is 1
+ *
+ * \param X        First mbedtls_mpi value
+ * \param Y        Second mbedtls_mpi value
+ * \param assign   1: perform the swap, 0: keep X and Y's original values
+ *
+ * \return         0 if successful,
+ *                 MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed,
+ *
+ * \note           This function is equivalent to
+ *                      if( assign ) mbedtls_mpi_swap( X, Y );
+ *                 except that it avoids leaking any information about whether
+ *                 the assignment was done or not (the above code may leak
+ *                 information through branch prediction and/or memory access
+ *                 patterns analysis).
+ */
+int mbedtls_mpi_safe_cond_swap( mbedtls_mpi *X, mbedtls_mpi *Y, unsigned char assign );
+
+/**
+ * \brief          Set value from integer
+ *
+ * \param X        MPI to set
+ * \param z        Value to use
+ *
+ * \return         0 if successful,
+ *                 MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed
+ */
+int mbedtls_mpi_lset( mbedtls_mpi *X, mbedtls_mpi_sint z );
+
+/**
+ * \brief          Get a specific bit from X
+ *
+ * \param X        MPI to use
+ * \param pos      Zero-based index of the bit in X
+ *
+ * \return         Either a 0 or a 1
+ */
+int mbedtls_mpi_get_bit( const mbedtls_mpi *X, size_t pos );
+
+/**
+ * \brief          Set a bit of X to a specific value of 0 or 1
+ *
+ * \note           Will grow X if necessary to set a bit to 1 in a not yet
+ *                 existing limb. Will not grow if bit should be set to 0
+ *
+ * \param X        MPI to use
+ * \param pos      Zero-based index of the bit in X
+ * \param val      The value to set the bit to (0 or 1)
+ *
+ * \return         0 if successful,
+ *                 MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed,
+ *                 MBEDTLS_ERR_MPI_BAD_INPUT_DATA if val is not 0 or 1
+ */
+int mbedtls_mpi_set_bit( mbedtls_mpi *X, size_t pos, unsigned char val );
+
+/**
+ * \brief          Return the number of zero-bits before the least significant
+ *                 '1' bit
+ *
+ * Note: Thus also the zero-based index of the least significant '1' bit
+ *
+ * \param X        MPI to use
+ */
+size_t mbedtls_mpi_lsb( const mbedtls_mpi *X );
+
+/**
+ * \brief          Return the number of bits up to and including the most
+ *                 significant '1' bit'
+ *
+ * Note: Thus also the one-based index of the most significant '1' bit
+ *
+ * \param X        MPI to use
+ */
+size_t mbedtls_mpi_bitlen( const mbedtls_mpi *X );
+
+/**
+ * \brief          Return the total size in bytes
+ *
+ * \param X        MPI to use
+ */
+size_t mbedtls_mpi_size( const mbedtls_mpi *X );
+
+/**
+ * \brief          Import from an ASCII string
+ *
+ * \param X        Destination MPI
+ * \param radix    Input numeric base
+ * \param s        Null-terminated string buffer
+ *
+ * \return         0 if successful, or a MBEDTLS_ERR_MPI_XXX error code
+ */
+int mbedtls_mpi_read_string( mbedtls_mpi *X, int radix, const char *s );
+
+/**
+ * \brief          Export into an ASCII string
+ *
+ * \param X        Source MPI
+ * \param radix    Output numeric base
+ * \param buf      Buffer to write the string to
+ * \param buflen   Length of buf
+ * \param olen     Length of the string written, including final NUL byte
+ *
+ * \return         0 if successful, or a MBEDTLS_ERR_MPI_XXX error code.
+ *                 *olen is always updated to reflect the amount
+ *                 of data that has (or would have) been written.
+ *
+ * \note           Call this function with buflen = 0 to obtain the
+ *                 minimum required buffer size in *olen.
+ */
+int mbedtls_mpi_write_string( const mbedtls_mpi *X, int radix,
+                              char *buf, size_t buflen, size_t *olen );
+
+#if defined(MBEDTLS_FS_IO)
+/**
+ * \brief          Read X from an opened file
+ *
+ * \param X        Destination MPI
+ * \param radix    Input numeric base
+ * \param fin      Input file handle
+ *
+ * \return         0 if successful, MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL if
+ *                 the file read buffer is too small or a
+ *                 MBEDTLS_ERR_MPI_XXX error code
+ */
+int mbedtls_mpi_read_file( mbedtls_mpi *X, int radix, FILE *fin );
+
+/**
+ * \brief          Write X into an opened file, or stdout if fout is NULL
+ *
+ * \param p        Prefix, can be NULL
+ * \param X        Source MPI
+ * \param radix    Output numeric base
+ * \param fout     Output file handle (can be NULL)
+ *
+ * \return         0 if successful, or a MBEDTLS_ERR_MPI_XXX error code
+ *
+ * \note           Set fout == NULL to print X on the console.
+ */
+int mbedtls_mpi_write_file( const char *p, const mbedtls_mpi *X, int radix, FILE *fout );
+#endif /* MBEDTLS_FS_IO */
+
+/**
+ * \brief          Import X from unsigned binary data, big endian
+ *
+ * \param X        Destination MPI
+ * \param buf      Input buffer
+ * \param buflen   Input buffer size
+ *
+ * \return         0 if successful,
+ *                 MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed
+ */
+int mbedtls_mpi_read_binary( mbedtls_mpi *X, const unsigned char *buf, size_t buflen );
+
+/**
+ * \brief          Export X into unsigned binary data, big endian.
+ *                 Always fills the whole buffer, which will start with zeros
+ *                 if the number is smaller.
+ *
+ * \param X        Source MPI
+ * \param buf      Output buffer
+ * \param buflen   Output buffer size
+ *
+ * \return         0 if successful,
+ *                 MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL if buf isn't large enough
+ */
+int mbedtls_mpi_write_binary( const mbedtls_mpi *X, unsigned char *buf, size_t buflen );
+
+/**
+ * \brief          Left-shift: X <<= count
+ *
+ * \param X        MPI to shift
+ * \param count    Amount to shift
+ *
+ * \return         0 if successful,
+ *                 MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed
+ */
+int mbedtls_mpi_shift_l( mbedtls_mpi *X, size_t count );
+
+/**
+ * \brief          Right-shift: X >>= count
+ *
+ * \param X        MPI to shift
+ * \param count    Amount to shift
+ *
+ * \return         0 if successful,
+ *                 MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed
+ */
+int mbedtls_mpi_shift_r( mbedtls_mpi *X, size_t count );
+
+/**
+ * \brief          Compare unsigned values
+ *
+ * \param X        Left-hand MPI
+ * \param Y        Right-hand MPI
+ *
+ * \return         1 if |X| is greater than |Y|,
+ *                -1 if |X| is lesser  than |Y| or
+ *                 0 if |X| is equal to |Y|
+ */
+int mbedtls_mpi_cmp_abs( const mbedtls_mpi *X, const mbedtls_mpi *Y );
+
+/**
+ * \brief          Compare signed values
+ *
+ * \param X        Left-hand MPI
+ * \param Y        Right-hand MPI
+ *
+ * \return         1 if X is greater than Y,
+ *                -1 if X is lesser  than Y or
+ *                 0 if X is equal to Y
+ */
+int mbedtls_mpi_cmp_mpi( const mbedtls_mpi *X, const mbedtls_mpi *Y );
+
+/**
+ * \brief          Compare signed values
+ *
+ * \param X        Left-hand MPI
+ * \param z        The integer value to compare to
+ *
+ * \return         1 if X is greater than z,
+ *                -1 if X is lesser  than z or
+ *                 0 if X is equal to z
+ */
+int mbedtls_mpi_cmp_int( const mbedtls_mpi *X, mbedtls_mpi_sint z );
+
+/**
+ * \brief          Unsigned addition: X = |A| + |B|
+ *
+ * \param X        Destination MPI
+ * \param A        Left-hand MPI
+ * \param B        Right-hand MPI
+ *
+ * \return         0 if successful,
+ *                 MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed
+ */
+int mbedtls_mpi_add_abs( mbedtls_mpi *X, const mbedtls_mpi *A, const mbedtls_mpi *B );
+
+/**
+ * \brief          Unsigned subtraction: X = |A| - |B|
+ *
+ * \param X        Destination MPI
+ * \param A        Left-hand MPI
+ * \param B        Right-hand MPI
+ *
+ * \return         0 if successful,
+ *                 MBEDTLS_ERR_MPI_NEGATIVE_VALUE if B is greater than A
+ */
+int mbedtls_mpi_sub_abs( mbedtls_mpi *X, const mbedtls_mpi *A, const mbedtls_mpi *B );
+
+/**
+ * \brief          Signed addition: X = A + B
+ *
+ * \param X        Destination MPI
+ * \param A        Left-hand MPI
+ * \param B        Right-hand MPI
+ *
+ * \return         0 if successful,
+ *                 MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed
+ */
+int mbedtls_mpi_add_mpi( mbedtls_mpi *X, const mbedtls_mpi *A, const mbedtls_mpi *B );
+
+/**
+ * \brief          Signed subtraction: X = A - B
+ *
+ * \param X        Destination MPI
+ * \param A        Left-hand MPI
+ * \param B        Right-hand MPI
+ *
+ * \return         0 if successful,
+ *                 MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed
+ */
+int mbedtls_mpi_sub_mpi( mbedtls_mpi *X, const mbedtls_mpi *A, const mbedtls_mpi *B );
+
+/**
+ * \brief          Signed addition: X = A + b
+ *
+ * \param X        Destination MPI
+ * \param A        Left-hand MPI
+ * \param b        The integer value to add
+ *
+ * \return         0 if successful,
+ *                 MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed
+ */
+int mbedtls_mpi_add_int( mbedtls_mpi *X, const mbedtls_mpi *A, mbedtls_mpi_sint b );
+
+/**
+ * \brief          Signed subtraction: X = A - b
+ *
+ * \param X        Destination MPI
+ * \param A        Left-hand MPI
+ * \param b        The integer value to subtract
+ *
+ * \return         0 if successful,
+ *                 MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed
+ */
+int mbedtls_mpi_sub_int( mbedtls_mpi *X, const mbedtls_mpi *A, mbedtls_mpi_sint b );
+
+/**
+ * \brief          Baseline multiplication: X = A * B
+ *
+ * \param X        Destination MPI
+ * \param A        Left-hand MPI
+ * \param B        Right-hand MPI
+ *
+ * \return         0 if successful,
+ *                 MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed
+ */
+int mbedtls_mpi_mul_mpi( mbedtls_mpi *X, const mbedtls_mpi *A, const mbedtls_mpi *B );
+
+/**
+ * \brief          Baseline multiplication: X = A * b
+ *
+ * \param X        Destination MPI
+ * \param A        Left-hand MPI
+ * \param b        The unsigned integer value to multiply with
+ *
+ * \note           b is unsigned
+ *
+ * \return         0 if successful,
+ *                 MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed
+ */
+int mbedtls_mpi_mul_int( mbedtls_mpi *X, const mbedtls_mpi *A, mbedtls_mpi_uint b );
+
+/**
+ * \brief          Division by mbedtls_mpi: A = Q * B + R
+ *
+ * \param Q        Destination MPI for the quotient
+ * \param R        Destination MPI for the rest value
+ * \param A        Left-hand MPI
+ * \param B        Right-hand MPI
+ *
+ * \return         0 if successful,
+ *                 MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed,
+ *                 MBEDTLS_ERR_MPI_DIVISION_BY_ZERO if B == 0
+ *
+ * \note           Either Q or R can be NULL.
+ */
+int mbedtls_mpi_div_mpi( mbedtls_mpi *Q, mbedtls_mpi *R, const mbedtls_mpi *A, const mbedtls_mpi *B );
+
+/**
+ * \brief          Division by int: A = Q * b + R
+ *
+ * \param Q        Destination MPI for the quotient
+ * \param R        Destination MPI for the rest value
+ * \param A        Left-hand MPI
+ * \param b        Integer to divide by
+ *
+ * \return         0 if successful,
+ *                 MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed,
+ *                 MBEDTLS_ERR_MPI_DIVISION_BY_ZERO if b == 0
+ *
+ * \note           Either Q or R can be NULL.
+ */
+int mbedtls_mpi_div_int( mbedtls_mpi *Q, mbedtls_mpi *R, const mbedtls_mpi *A, mbedtls_mpi_sint b );
+
+/**
+ * \brief          Modulo: R = A mod B
+ *
+ * \param R        Destination MPI for the rest value
+ * \param A        Left-hand MPI
+ * \param B        Right-hand MPI
+ *
+ * \return         0 if successful,
+ *                 MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed,
+ *                 MBEDTLS_ERR_MPI_DIVISION_BY_ZERO if B == 0,
+ *                 MBEDTLS_ERR_MPI_NEGATIVE_VALUE if B < 0
+ */
+int mbedtls_mpi_mod_mpi( mbedtls_mpi *R, const mbedtls_mpi *A, const mbedtls_mpi *B );
+
+/**
+ * \brief          Modulo: r = A mod b
+ *
+ * \param r        Destination mbedtls_mpi_uint
+ * \param A        Left-hand MPI
+ * \param b        Integer to divide by
+ *
+ * \return         0 if successful,
+ *                 MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed,
+ *                 MBEDTLS_ERR_MPI_DIVISION_BY_ZERO if b == 0,
+ *                 MBEDTLS_ERR_MPI_NEGATIVE_VALUE if b < 0
+ */
+int mbedtls_mpi_mod_int( mbedtls_mpi_uint *r, const mbedtls_mpi *A, mbedtls_mpi_sint b );
+
+/**
+ * \brief          Sliding-window exponentiation: X = A^E mod N
+ *
+ * \param X        Destination MPI
+ * \param A        Left-hand MPI
+ * \param E        Exponent MPI
+ * \param N        Modular MPI
+ * \param _RR      Speed-up MPI used for recalculations
+ *
+ * \return         0 if successful,
+ *                 MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed,
+ *                 MBEDTLS_ERR_MPI_BAD_INPUT_DATA if N is negative or even or
+ *                 if E is negative
+ *
+ * \note           _RR is used to avoid re-computing R*R mod N across
+ *                 multiple calls, which speeds up things a bit. It can
+ *                 be set to NULL if the extra performance is unneeded.
+ */
+int mbedtls_mpi_exp_mod( mbedtls_mpi *X, const mbedtls_mpi *A, const mbedtls_mpi *E, const mbedtls_mpi *N, mbedtls_mpi *_RR );
+
+/**
+ * \brief          Fill an MPI X with size bytes of random
+ *
+ * \param X        Destination MPI
+ * \param size     Size in bytes
+ * \param f_rng    RNG function
+ * \param p_rng    RNG parameter
+ *
+ * \return         0 if successful,
+ *                 MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed
+ */
+int mbedtls_mpi_fill_random( mbedtls_mpi *X, size_t size,
+                     int (*f_rng)(void *, unsigned char *, size_t),
+                     void *p_rng );
+
+/**
+ * \brief          Greatest common divisor: G = gcd(A, B)
+ *
+ * \param G        Destination MPI
+ * \param A        Left-hand MPI
+ * \param B        Right-hand MPI
+ *
+ * \return         0 if successful,
+ *                 MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed
+ */
+int mbedtls_mpi_gcd( mbedtls_mpi *G, const mbedtls_mpi *A, const mbedtls_mpi *B );
+
+/**
+ * \brief          Modular inverse: X = A^-1 mod N
+ *
+ * \param X        Destination MPI
+ * \param A        Left-hand MPI
+ * \param N        Right-hand MPI
+ *
+ * \return         0 if successful,
+ *                 MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed,
+ *                 MBEDTLS_ERR_MPI_BAD_INPUT_DATA if N is negative or nil
+                   MBEDTLS_ERR_MPI_NOT_ACCEPTABLE if A has no inverse mod N
+ */
+int mbedtls_mpi_inv_mod( mbedtls_mpi *X, const mbedtls_mpi *A, const mbedtls_mpi *N );
+
+/**
+ * \brief          Miller-Rabin primality test
+ *
+ * \param X        MPI to check
+ * \param f_rng    RNG function
+ * \param p_rng    RNG parameter
+ *
+ * \return         0 if successful (probably prime),
+ *                 MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed,
+ *                 MBEDTLS_ERR_MPI_NOT_ACCEPTABLE if X is not prime
+ */
+int mbedtls_mpi_is_prime( const mbedtls_mpi *X,
+                  int (*f_rng)(void *, unsigned char *, size_t),
+                  void *p_rng );
+
+/**
+ * \brief          Prime number generation
+ *
+ * \param X        Destination MPI
+ * \param nbits    Required size of X in bits
+ *                 ( 3 <= nbits <= MBEDTLS_MPI_MAX_BITS )
+ * \param dh_flag  If 1, then (X-1)/2 will be prime too
+ * \param f_rng    RNG function
+ * \param p_rng    RNG parameter
+ *
+ * \return         0 if successful (probably prime),
+ *                 MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed,
+ *                 MBEDTLS_ERR_MPI_BAD_INPUT_DATA if nbits is < 3
+ */
+int mbedtls_mpi_gen_prime( mbedtls_mpi *X, size_t nbits, int dh_flag,
+                   int (*f_rng)(void *, unsigned char *, size_t),
+                   void *p_rng );
+#else /* MBEDTLS_BIGNUM_ALT */
+#include "bignum_alt.h"
+#endif /* MBEDTLS_BIGNUM_ALT */
+
+/**
+ * \brief          Checkup routine
+ *
+ * \return         0 if successful, or 1 if the test failed
+ */
+int mbedtls_mpi_self_test( int verbose );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* bignum.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/blowfish.h b/tools/sdk/include/mbedtls/mbedtls/blowfish.h
new file mode 100644
index 00000000..34626eef
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/blowfish.h
@@ -0,0 +1,203 @@
+/**
+ * \file blowfish.h
+ *
+ * \brief Blowfish block cipher
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_BLOWFISH_H
+#define MBEDTLS_BLOWFISH_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#include 
+#include 
+
+#define MBEDTLS_BLOWFISH_ENCRYPT     1
+#define MBEDTLS_BLOWFISH_DECRYPT     0
+#define MBEDTLS_BLOWFISH_MAX_KEY_BITS     448
+#define MBEDTLS_BLOWFISH_MIN_KEY_BITS     32
+#define MBEDTLS_BLOWFISH_ROUNDS      16         /**< Rounds to use. When increasing this value, make sure to extend the initialisation vectors */
+#define MBEDTLS_BLOWFISH_BLOCKSIZE   8          /* Blowfish uses 64 bit blocks */
+
+#define MBEDTLS_ERR_BLOWFISH_INVALID_KEY_LENGTH                -0x0016  /**< Invalid key length. */
+#define MBEDTLS_ERR_BLOWFISH_INVALID_INPUT_LENGTH              -0x0018  /**< Invalid data input length. */
+
+#if !defined(MBEDTLS_BLOWFISH_ALT)
+// Regular implementation
+//
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          Blowfish context structure
+ */
+typedef struct
+{
+    uint32_t P[MBEDTLS_BLOWFISH_ROUNDS + 2];    /*!<  Blowfish round keys    */
+    uint32_t S[4][256];                 /*!<  key dependent S-boxes  */
+}
+mbedtls_blowfish_context;
+
+/**
+ * \brief          Initialize Blowfish context
+ *
+ * \param ctx      Blowfish context to be initialized
+ */
+void mbedtls_blowfish_init( mbedtls_blowfish_context *ctx );
+
+/**
+ * \brief          Clear Blowfish context
+ *
+ * \param ctx      Blowfish context to be cleared
+ */
+void mbedtls_blowfish_free( mbedtls_blowfish_context *ctx );
+
+/**
+ * \brief          Blowfish key schedule
+ *
+ * \param ctx      Blowfish context to be initialized
+ * \param key      encryption key
+ * \param keybits  must be between 32 and 448 bits
+ *
+ * \return         0 if successful, or MBEDTLS_ERR_BLOWFISH_INVALID_KEY_LENGTH
+ */
+int mbedtls_blowfish_setkey( mbedtls_blowfish_context *ctx, const unsigned char *key,
+                     unsigned int keybits );
+
+/**
+ * \brief          Blowfish-ECB block encryption/decryption
+ *
+ * \param ctx      Blowfish context
+ * \param mode     MBEDTLS_BLOWFISH_ENCRYPT or MBEDTLS_BLOWFISH_DECRYPT
+ * \param input    8-byte input block
+ * \param output   8-byte output block
+ *
+ * \return         0 if successful
+ */
+int mbedtls_blowfish_crypt_ecb( mbedtls_blowfish_context *ctx,
+                        int mode,
+                        const unsigned char input[MBEDTLS_BLOWFISH_BLOCKSIZE],
+                        unsigned char output[MBEDTLS_BLOWFISH_BLOCKSIZE] );
+
+#if defined(MBEDTLS_CIPHER_MODE_CBC)
+/**
+ * \brief          Blowfish-CBC buffer encryption/decryption
+ *                 Length should be a multiple of the block
+ *                 size (8 bytes)
+ *
+ * \note           Upon exit, the content of the IV is updated so that you can
+ *                 call the function same function again on the following
+ *                 block(s) of data and get the same result as if it was
+ *                 encrypted in one call. This allows a "streaming" usage.
+ *                 If on the other hand you need to retain the contents of the
+ *                 IV, you should either save it manually or use the cipher
+ *                 module instead.
+ *
+ * \param ctx      Blowfish context
+ * \param mode     MBEDTLS_BLOWFISH_ENCRYPT or MBEDTLS_BLOWFISH_DECRYPT
+ * \param length   length of the input data
+ * \param iv       initialization vector (updated after use)
+ * \param input    buffer holding the input data
+ * \param output   buffer holding the output data
+ *
+ * \return         0 if successful, or
+ *                 MBEDTLS_ERR_BLOWFISH_INVALID_INPUT_LENGTH
+ */
+int mbedtls_blowfish_crypt_cbc( mbedtls_blowfish_context *ctx,
+                        int mode,
+                        size_t length,
+                        unsigned char iv[MBEDTLS_BLOWFISH_BLOCKSIZE],
+                        const unsigned char *input,
+                        unsigned char *output );
+#endif /* MBEDTLS_CIPHER_MODE_CBC */
+
+#if defined(MBEDTLS_CIPHER_MODE_CFB)
+/**
+ * \brief          Blowfish CFB buffer encryption/decryption.
+ *
+ * \note           Upon exit, the content of the IV is updated so that you can
+ *                 call the function same function again on the following
+ *                 block(s) of data and get the same result as if it was
+ *                 encrypted in one call. This allows a "streaming" usage.
+ *                 If on the other hand you need to retain the contents of the
+ *                 IV, you should either save it manually or use the cipher
+ *                 module instead.
+ *
+ * \param ctx      Blowfish context
+ * \param mode     MBEDTLS_BLOWFISH_ENCRYPT or MBEDTLS_BLOWFISH_DECRYPT
+ * \param length   length of the input data
+ * \param iv_off   offset in IV (updated after use)
+ * \param iv       initialization vector (updated after use)
+ * \param input    buffer holding the input data
+ * \param output   buffer holding the output data
+ *
+ * \return         0 if successful
+ */
+int mbedtls_blowfish_crypt_cfb64( mbedtls_blowfish_context *ctx,
+                          int mode,
+                          size_t length,
+                          size_t *iv_off,
+                          unsigned char iv[MBEDTLS_BLOWFISH_BLOCKSIZE],
+                          const unsigned char *input,
+                          unsigned char *output );
+#endif /*MBEDTLS_CIPHER_MODE_CFB */
+
+#if defined(MBEDTLS_CIPHER_MODE_CTR)
+/**
+ * \brief               Blowfish-CTR buffer encryption/decryption
+ *
+ * Warning: You have to keep the maximum use of your counter in mind!
+ *
+ * \param ctx           Blowfish context
+ * \param length        The length of the data
+ * \param nc_off        The offset in the current stream_block (for resuming
+ *                      within current cipher stream). The offset pointer to
+ *                      should be 0 at the start of a stream.
+ * \param nonce_counter The 64-bit nonce and counter.
+ * \param stream_block  The saved stream-block for resuming. Is overwritten
+ *                      by the function.
+ * \param input         The input data stream
+ * \param output        The output data stream
+ *
+ * \return         0 if successful
+ */
+int mbedtls_blowfish_crypt_ctr( mbedtls_blowfish_context *ctx,
+                        size_t length,
+                        size_t *nc_off,
+                        unsigned char nonce_counter[MBEDTLS_BLOWFISH_BLOCKSIZE],
+                        unsigned char stream_block[MBEDTLS_BLOWFISH_BLOCKSIZE],
+                        const unsigned char *input,
+                        unsigned char *output );
+#endif /* MBEDTLS_CIPHER_MODE_CTR */
+
+#ifdef __cplusplus
+}
+#endif
+
+#else  /* MBEDTLS_BLOWFISH_ALT */
+#include "blowfish_alt.h"
+#endif /* MBEDTLS_BLOWFISH_ALT */
+
+#endif /* blowfish.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/bn_mul.h b/tools/sdk/include/mbedtls/mbedtls/bn_mul.h
new file mode 100644
index 00000000..cac3f145
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/bn_mul.h
@@ -0,0 +1,885 @@
+/**
+ * \file bn_mul.h
+ *
+ * \brief  Multi-precision integer library
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+/*
+ *      Multiply source vector [s] with b, add result
+ *       to destination vector [d] and set carry c.
+ *
+ *      Currently supports:
+ *
+ *         . IA-32 (386+)         . AMD64 / EM64T
+ *         . IA-32 (SSE2)         . Motorola 68000
+ *         . PowerPC, 32-bit      . MicroBlaze
+ *         . PowerPC, 64-bit      . TriCore
+ *         . SPARC v8             . ARM v3+
+ *         . Alpha                . MIPS32
+ *         . C, longlong          . C, generic
+ */
+#ifndef MBEDTLS_BN_MUL_H
+#define MBEDTLS_BN_MUL_H
+
+#include "bignum.h"
+
+#if defined(MBEDTLS_HAVE_ASM)
+
+#ifndef asm
+#define asm __asm
+#endif
+
+/* armcc5 --gnu defines __GNUC__ but doesn't support GNU's extended asm */
+#if defined(__GNUC__) && \
+    ( !defined(__ARMCC_VERSION) || __ARMCC_VERSION >= 6000000 )
+#if defined(__i386__)
+
+#define MULADDC_INIT                        \
+    asm(                                    \
+        "movl   %%ebx, %0           \n\t"   \
+        "movl   %5, %%esi           \n\t"   \
+        "movl   %6, %%edi           \n\t"   \
+        "movl   %7, %%ecx           \n\t"   \
+        "movl   %8, %%ebx           \n\t"
+
+#define MULADDC_CORE                        \
+        "lodsl                      \n\t"   \
+        "mull   %%ebx               \n\t"   \
+        "addl   %%ecx,   %%eax      \n\t"   \
+        "adcl   $0,      %%edx      \n\t"   \
+        "addl   (%%edi), %%eax      \n\t"   \
+        "adcl   $0,      %%edx      \n\t"   \
+        "movl   %%edx,   %%ecx      \n\t"   \
+        "stosl                      \n\t"
+
+#if defined(MBEDTLS_HAVE_SSE2)
+
+#define MULADDC_HUIT                            \
+        "movd     %%ecx,     %%mm1      \n\t"   \
+        "movd     %%ebx,     %%mm0      \n\t"   \
+        "movd     (%%edi),   %%mm3      \n\t"   \
+        "paddq    %%mm3,     %%mm1      \n\t"   \
+        "movd     (%%esi),   %%mm2      \n\t"   \
+        "pmuludq  %%mm0,     %%mm2      \n\t"   \
+        "movd     4(%%esi),  %%mm4      \n\t"   \
+        "pmuludq  %%mm0,     %%mm4      \n\t"   \
+        "movd     8(%%esi),  %%mm6      \n\t"   \
+        "pmuludq  %%mm0,     %%mm6      \n\t"   \
+        "movd     12(%%esi), %%mm7      \n\t"   \
+        "pmuludq  %%mm0,     %%mm7      \n\t"   \
+        "paddq    %%mm2,     %%mm1      \n\t"   \
+        "movd     4(%%edi),  %%mm3      \n\t"   \
+        "paddq    %%mm4,     %%mm3      \n\t"   \
+        "movd     8(%%edi),  %%mm5      \n\t"   \
+        "paddq    %%mm6,     %%mm5      \n\t"   \
+        "movd     12(%%edi), %%mm4      \n\t"   \
+        "paddq    %%mm4,     %%mm7      \n\t"   \
+        "movd     %%mm1,     (%%edi)    \n\t"   \
+        "movd     16(%%esi), %%mm2      \n\t"   \
+        "pmuludq  %%mm0,     %%mm2      \n\t"   \
+        "psrlq    $32,       %%mm1      \n\t"   \
+        "movd     20(%%esi), %%mm4      \n\t"   \
+        "pmuludq  %%mm0,     %%mm4      \n\t"   \
+        "paddq    %%mm3,     %%mm1      \n\t"   \
+        "movd     24(%%esi), %%mm6      \n\t"   \
+        "pmuludq  %%mm0,     %%mm6      \n\t"   \
+        "movd     %%mm1,     4(%%edi)   \n\t"   \
+        "psrlq    $32,       %%mm1      \n\t"   \
+        "movd     28(%%esi), %%mm3      \n\t"   \
+        "pmuludq  %%mm0,     %%mm3      \n\t"   \
+        "paddq    %%mm5,     %%mm1      \n\t"   \
+        "movd     16(%%edi), %%mm5      \n\t"   \
+        "paddq    %%mm5,     %%mm2      \n\t"   \
+        "movd     %%mm1,     8(%%edi)   \n\t"   \
+        "psrlq    $32,       %%mm1      \n\t"   \
+        "paddq    %%mm7,     %%mm1      \n\t"   \
+        "movd     20(%%edi), %%mm5      \n\t"   \
+        "paddq    %%mm5,     %%mm4      \n\t"   \
+        "movd     %%mm1,     12(%%edi)  \n\t"   \
+        "psrlq    $32,       %%mm1      \n\t"   \
+        "paddq    %%mm2,     %%mm1      \n\t"   \
+        "movd     24(%%edi), %%mm5      \n\t"   \
+        "paddq    %%mm5,     %%mm6      \n\t"   \
+        "movd     %%mm1,     16(%%edi)  \n\t"   \
+        "psrlq    $32,       %%mm1      \n\t"   \
+        "paddq    %%mm4,     %%mm1      \n\t"   \
+        "movd     28(%%edi), %%mm5      \n\t"   \
+        "paddq    %%mm5,     %%mm3      \n\t"   \
+        "movd     %%mm1,     20(%%edi)  \n\t"   \
+        "psrlq    $32,       %%mm1      \n\t"   \
+        "paddq    %%mm6,     %%mm1      \n\t"   \
+        "movd     %%mm1,     24(%%edi)  \n\t"   \
+        "psrlq    $32,       %%mm1      \n\t"   \
+        "paddq    %%mm3,     %%mm1      \n\t"   \
+        "movd     %%mm1,     28(%%edi)  \n\t"   \
+        "addl     $32,       %%edi      \n\t"   \
+        "addl     $32,       %%esi      \n\t"   \
+        "psrlq    $32,       %%mm1      \n\t"   \
+        "movd     %%mm1,     %%ecx      \n\t"
+
+#define MULADDC_STOP                    \
+        "emms                   \n\t"   \
+        "movl   %4, %%ebx       \n\t"   \
+        "movl   %%ecx, %1       \n\t"   \
+        "movl   %%edi, %2       \n\t"   \
+        "movl   %%esi, %3       \n\t"   \
+        : "=m" (t), "=m" (c), "=m" (d), "=m" (s)        \
+        : "m" (t), "m" (s), "m" (d), "m" (c), "m" (b)   \
+        : "eax", "ecx", "edx", "esi", "edi"             \
+    );
+
+#else
+
+#define MULADDC_STOP                    \
+        "movl   %4, %%ebx       \n\t"   \
+        "movl   %%ecx, %1       \n\t"   \
+        "movl   %%edi, %2       \n\t"   \
+        "movl   %%esi, %3       \n\t"   \
+        : "=m" (t), "=m" (c), "=m" (d), "=m" (s)        \
+        : "m" (t), "m" (s), "m" (d), "m" (c), "m" (b)   \
+        : "eax", "ecx", "edx", "esi", "edi"             \
+    );
+#endif /* SSE2 */
+#endif /* i386 */
+
+#if defined(__amd64__) || defined (__x86_64__)
+
+#define MULADDC_INIT                        \
+    asm(                                    \
+        "xorq   %%r8, %%r8          \n\t"
+
+#define MULADDC_CORE                        \
+        "movq   (%%rsi), %%rax      \n\t"   \
+        "mulq   %%rbx               \n\t"   \
+        "addq   $8,      %%rsi      \n\t"   \
+        "addq   %%rcx,   %%rax      \n\t"   \
+        "movq   %%r8,    %%rcx      \n\t"   \
+        "adcq   $0,      %%rdx      \n\t"   \
+        "nop                        \n\t"   \
+        "addq   %%rax,   (%%rdi)    \n\t"   \
+        "adcq   %%rdx,   %%rcx      \n\t"   \
+        "addq   $8,      %%rdi      \n\t"
+
+#define MULADDC_STOP                        \
+        : "+c" (c), "+D" (d), "+S" (s)      \
+        : "b" (b)                           \
+        : "rax", "rdx", "r8"                \
+    );
+
+#endif /* AMD64 */
+
+#if defined(__mc68020__) || defined(__mcpu32__)
+
+#define MULADDC_INIT                    \
+    asm(                                \
+        "movl   %3, %%a2        \n\t"   \
+        "movl   %4, %%a3        \n\t"   \
+        "movl   %5, %%d3        \n\t"   \
+        "movl   %6, %%d2        \n\t"   \
+        "moveq  #0, %%d0        \n\t"
+
+#define MULADDC_CORE                    \
+        "movel  %%a2@+, %%d1    \n\t"   \
+        "mulul  %%d2, %%d4:%%d1 \n\t"   \
+        "addl   %%d3, %%d1      \n\t"   \
+        "addxl  %%d0, %%d4      \n\t"   \
+        "moveq  #0,   %%d3      \n\t"   \
+        "addl   %%d1, %%a3@+    \n\t"   \
+        "addxl  %%d4, %%d3      \n\t"
+
+#define MULADDC_STOP                    \
+        "movl   %%d3, %0        \n\t"   \
+        "movl   %%a3, %1        \n\t"   \
+        "movl   %%a2, %2        \n\t"   \
+        : "=m" (c), "=m" (d), "=m" (s)              \
+        : "m" (s), "m" (d), "m" (c), "m" (b)        \
+        : "d0", "d1", "d2", "d3", "d4", "a2", "a3"  \
+    );
+
+#define MULADDC_HUIT                        \
+        "movel  %%a2@+,  %%d1       \n\t"   \
+        "mulul  %%d2,    %%d4:%%d1  \n\t"   \
+        "addxl  %%d3,    %%d1       \n\t"   \
+        "addxl  %%d0,    %%d4       \n\t"   \
+        "addl   %%d1,    %%a3@+     \n\t"   \
+        "movel  %%a2@+,  %%d1       \n\t"   \
+        "mulul  %%d2,    %%d3:%%d1  \n\t"   \
+        "addxl  %%d4,    %%d1       \n\t"   \
+        "addxl  %%d0,    %%d3       \n\t"   \
+        "addl   %%d1,    %%a3@+     \n\t"   \
+        "movel  %%a2@+,  %%d1       \n\t"   \
+        "mulul  %%d2,    %%d4:%%d1  \n\t"   \
+        "addxl  %%d3,    %%d1       \n\t"   \
+        "addxl  %%d0,    %%d4       \n\t"   \
+        "addl   %%d1,    %%a3@+     \n\t"   \
+        "movel  %%a2@+,  %%d1       \n\t"   \
+        "mulul  %%d2,    %%d3:%%d1  \n\t"   \
+        "addxl  %%d4,    %%d1       \n\t"   \
+        "addxl  %%d0,    %%d3       \n\t"   \
+        "addl   %%d1,    %%a3@+     \n\t"   \
+        "movel  %%a2@+,  %%d1       \n\t"   \
+        "mulul  %%d2,    %%d4:%%d1  \n\t"   \
+        "addxl  %%d3,    %%d1       \n\t"   \
+        "addxl  %%d0,    %%d4       \n\t"   \
+        "addl   %%d1,    %%a3@+     \n\t"   \
+        "movel  %%a2@+,  %%d1       \n\t"   \
+        "mulul  %%d2,    %%d3:%%d1  \n\t"   \
+        "addxl  %%d4,    %%d1       \n\t"   \
+        "addxl  %%d0,    %%d3       \n\t"   \
+        "addl   %%d1,    %%a3@+     \n\t"   \
+        "movel  %%a2@+,  %%d1       \n\t"   \
+        "mulul  %%d2,    %%d4:%%d1  \n\t"   \
+        "addxl  %%d3,    %%d1       \n\t"   \
+        "addxl  %%d0,    %%d4       \n\t"   \
+        "addl   %%d1,    %%a3@+     \n\t"   \
+        "movel  %%a2@+,  %%d1       \n\t"   \
+        "mulul  %%d2,    %%d3:%%d1  \n\t"   \
+        "addxl  %%d4,    %%d1       \n\t"   \
+        "addxl  %%d0,    %%d3       \n\t"   \
+        "addl   %%d1,    %%a3@+     \n\t"   \
+        "addxl  %%d0,    %%d3       \n\t"
+
+#endif /* MC68000 */
+
+#if defined(__powerpc64__) || defined(__ppc64__)
+
+#if defined(__MACH__) && defined(__APPLE__)
+
+#define MULADDC_INIT                        \
+    asm(                                    \
+        "ld     r3, %3              \n\t"   \
+        "ld     r4, %4              \n\t"   \
+        "ld     r5, %5              \n\t"   \
+        "ld     r6, %6              \n\t"   \
+        "addi   r3, r3, -8          \n\t"   \
+        "addi   r4, r4, -8          \n\t"   \
+        "addic  r5, r5,  0          \n\t"
+
+#define MULADDC_CORE                        \
+        "ldu    r7, 8(r3)           \n\t"   \
+        "mulld  r8, r7, r6          \n\t"   \
+        "mulhdu r9, r7, r6          \n\t"   \
+        "adde   r8, r8, r5          \n\t"   \
+        "ld     r7, 8(r4)           \n\t"   \
+        "addze  r5, r9              \n\t"   \
+        "addc   r8, r8, r7          \n\t"   \
+        "stdu   r8, 8(r4)           \n\t"
+
+#define MULADDC_STOP                        \
+        "addze  r5, r5              \n\t"   \
+        "addi   r4, r4, 8           \n\t"   \
+        "addi   r3, r3, 8           \n\t"   \
+        "std    r5, %0              \n\t"   \
+        "std    r4, %1              \n\t"   \
+        "std    r3, %2              \n\t"   \
+        : "=m" (c), "=m" (d), "=m" (s)              \
+        : "m" (s), "m" (d), "m" (c), "m" (b)        \
+        : "r3", "r4", "r5", "r6", "r7", "r8", "r9"  \
+    );
+
+
+#else /* __MACH__ && __APPLE__ */
+
+#define MULADDC_INIT                        \
+    asm(                                    \
+        "ld     %%r3, %3            \n\t"   \
+        "ld     %%r4, %4            \n\t"   \
+        "ld     %%r5, %5            \n\t"   \
+        "ld     %%r6, %6            \n\t"   \
+        "addi   %%r3, %%r3, -8      \n\t"   \
+        "addi   %%r4, %%r4, -8      \n\t"   \
+        "addic  %%r5, %%r5,  0      \n\t"
+
+#define MULADDC_CORE                        \
+        "ldu    %%r7, 8(%%r3)       \n\t"   \
+        "mulld  %%r8, %%r7, %%r6    \n\t"   \
+        "mulhdu %%r9, %%r7, %%r6    \n\t"   \
+        "adde   %%r8, %%r8, %%r5    \n\t"   \
+        "ld     %%r7, 8(%%r4)       \n\t"   \
+        "addze  %%r5, %%r9          \n\t"   \
+        "addc   %%r8, %%r8, %%r7    \n\t"   \
+        "stdu   %%r8, 8(%%r4)       \n\t"
+
+#define MULADDC_STOP                        \
+        "addze  %%r5, %%r5          \n\t"   \
+        "addi   %%r4, %%r4, 8       \n\t"   \
+        "addi   %%r3, %%r3, 8       \n\t"   \
+        "std    %%r5, %0            \n\t"   \
+        "std    %%r4, %1            \n\t"   \
+        "std    %%r3, %2            \n\t"   \
+        : "=m" (c), "=m" (d), "=m" (s)              \
+        : "m" (s), "m" (d), "m" (c), "m" (b)        \
+        : "r3", "r4", "r5", "r6", "r7", "r8", "r9"  \
+    );
+
+#endif /* __MACH__ && __APPLE__ */
+
+#elif defined(__powerpc__) || defined(__ppc__) /* end PPC64/begin PPC32  */
+
+#if defined(__MACH__) && defined(__APPLE__)
+
+#define MULADDC_INIT                    \
+    asm(                                \
+        "lwz    r3, %3          \n\t"   \
+        "lwz    r4, %4          \n\t"   \
+        "lwz    r5, %5          \n\t"   \
+        "lwz    r6, %6          \n\t"   \
+        "addi   r3, r3, -4      \n\t"   \
+        "addi   r4, r4, -4      \n\t"   \
+        "addic  r5, r5,  0      \n\t"
+
+#define MULADDC_CORE                    \
+        "lwzu   r7, 4(r3)       \n\t"   \
+        "mullw  r8, r7, r6      \n\t"   \
+        "mulhwu r9, r7, r6      \n\t"   \
+        "adde   r8, r8, r5      \n\t"   \
+        "lwz    r7, 4(r4)       \n\t"   \
+        "addze  r5, r9          \n\t"   \
+        "addc   r8, r8, r7      \n\t"   \
+        "stwu   r8, 4(r4)       \n\t"
+
+#define MULADDC_STOP                    \
+        "addze  r5, r5          \n\t"   \
+        "addi   r4, r4, 4       \n\t"   \
+        "addi   r3, r3, 4       \n\t"   \
+        "stw    r5, %0          \n\t"   \
+        "stw    r4, %1          \n\t"   \
+        "stw    r3, %2          \n\t"   \
+        : "=m" (c), "=m" (d), "=m" (s)              \
+        : "m" (s), "m" (d), "m" (c), "m" (b)        \
+        : "r3", "r4", "r5", "r6", "r7", "r8", "r9"  \
+    );
+
+#else /* __MACH__ && __APPLE__ */
+
+#define MULADDC_INIT                        \
+    asm(                                    \
+        "lwz    %%r3, %3            \n\t"   \
+        "lwz    %%r4, %4            \n\t"   \
+        "lwz    %%r5, %5            \n\t"   \
+        "lwz    %%r6, %6            \n\t"   \
+        "addi   %%r3, %%r3, -4      \n\t"   \
+        "addi   %%r4, %%r4, -4      \n\t"   \
+        "addic  %%r5, %%r5,  0      \n\t"
+
+#define MULADDC_CORE                        \
+        "lwzu   %%r7, 4(%%r3)       \n\t"   \
+        "mullw  %%r8, %%r7, %%r6    \n\t"   \
+        "mulhwu %%r9, %%r7, %%r6    \n\t"   \
+        "adde   %%r8, %%r8, %%r5    \n\t"   \
+        "lwz    %%r7, 4(%%r4)       \n\t"   \
+        "addze  %%r5, %%r9          \n\t"   \
+        "addc   %%r8, %%r8, %%r7    \n\t"   \
+        "stwu   %%r8, 4(%%r4)       \n\t"
+
+#define MULADDC_STOP                        \
+        "addze  %%r5, %%r5          \n\t"   \
+        "addi   %%r4, %%r4, 4       \n\t"   \
+        "addi   %%r3, %%r3, 4       \n\t"   \
+        "stw    %%r5, %0            \n\t"   \
+        "stw    %%r4, %1            \n\t"   \
+        "stw    %%r3, %2            \n\t"   \
+        : "=m" (c), "=m" (d), "=m" (s)              \
+        : "m" (s), "m" (d), "m" (c), "m" (b)        \
+        : "r3", "r4", "r5", "r6", "r7", "r8", "r9"  \
+    );
+
+#endif /* __MACH__ && __APPLE__ */
+
+#endif /* PPC32 */
+
+/*
+ * The Sparc(64) assembly is reported to be broken.
+ * Disable it for now, until we're able to fix it.
+ */
+#if 0 && defined(__sparc__)
+#if defined(__sparc64__)
+
+#define MULADDC_INIT                                    \
+    asm(                                                \
+                "ldx     %3, %%o0               \n\t"   \
+                "ldx     %4, %%o1               \n\t"   \
+                "ld      %5, %%o2               \n\t"   \
+                "ld      %6, %%o3               \n\t"
+
+#define MULADDC_CORE                                    \
+                "ld      [%%o0], %%o4           \n\t"   \
+                "inc     4, %%o0                \n\t"   \
+                "ld      [%%o1], %%o5           \n\t"   \
+                "umul    %%o3, %%o4, %%o4       \n\t"   \
+                "addcc   %%o4, %%o2, %%o4       \n\t"   \
+                "rd      %%y, %%g1              \n\t"   \
+                "addx    %%g1, 0, %%g1          \n\t"   \
+                "addcc   %%o4, %%o5, %%o4       \n\t"   \
+                "st      %%o4, [%%o1]           \n\t"   \
+                "addx    %%g1, 0, %%o2          \n\t"   \
+                "inc     4, %%o1                \n\t"
+
+        #define MULADDC_STOP                            \
+                "st      %%o2, %0               \n\t"   \
+                "stx     %%o1, %1               \n\t"   \
+                "stx     %%o0, %2               \n\t"   \
+        : "=m" (c), "=m" (d), "=m" (s)          \
+        : "m" (s), "m" (d), "m" (c), "m" (b)    \
+        : "g1", "o0", "o1", "o2", "o3", "o4",   \
+          "o5"                                  \
+        );
+
+#else /* __sparc64__ */
+
+#define MULADDC_INIT                                    \
+    asm(                                                \
+                "ld      %3, %%o0               \n\t"   \
+                "ld      %4, %%o1               \n\t"   \
+                "ld      %5, %%o2               \n\t"   \
+                "ld      %6, %%o3               \n\t"
+
+#define MULADDC_CORE                                    \
+                "ld      [%%o0], %%o4           \n\t"   \
+                "inc     4, %%o0                \n\t"   \
+                "ld      [%%o1], %%o5           \n\t"   \
+                "umul    %%o3, %%o4, %%o4       \n\t"   \
+                "addcc   %%o4, %%o2, %%o4       \n\t"   \
+                "rd      %%y, %%g1              \n\t"   \
+                "addx    %%g1, 0, %%g1          \n\t"   \
+                "addcc   %%o4, %%o5, %%o4       \n\t"   \
+                "st      %%o4, [%%o1]           \n\t"   \
+                "addx    %%g1, 0, %%o2          \n\t"   \
+                "inc     4, %%o1                \n\t"
+
+#define MULADDC_STOP                                    \
+                "st      %%o2, %0               \n\t"   \
+                "st      %%o1, %1               \n\t"   \
+                "st      %%o0, %2               \n\t"   \
+        : "=m" (c), "=m" (d), "=m" (s)          \
+        : "m" (s), "m" (d), "m" (c), "m" (b)    \
+        : "g1", "o0", "o1", "o2", "o3", "o4",   \
+          "o5"                                  \
+        );
+
+#endif /* __sparc64__ */
+#endif /* __sparc__ */
+
+#if defined(__microblaze__) || defined(microblaze)
+
+#define MULADDC_INIT                    \
+    asm(                                \
+        "lwi   r3,   %3         \n\t"   \
+        "lwi   r4,   %4         \n\t"   \
+        "lwi   r5,   %5         \n\t"   \
+        "lwi   r6,   %6         \n\t"   \
+        "andi  r7,   r6, 0xffff \n\t"   \
+        "bsrli r6,   r6, 16     \n\t"
+
+#define MULADDC_CORE                    \
+        "lhui  r8,   r3,   0    \n\t"   \
+        "addi  r3,   r3,   2    \n\t"   \
+        "lhui  r9,   r3,   0    \n\t"   \
+        "addi  r3,   r3,   2    \n\t"   \
+        "mul   r10,  r9,  r6    \n\t"   \
+        "mul   r11,  r8,  r7    \n\t"   \
+        "mul   r12,  r9,  r7    \n\t"   \
+        "mul   r13,  r8,  r6    \n\t"   \
+        "bsrli  r8, r10,  16    \n\t"   \
+        "bsrli  r9, r11,  16    \n\t"   \
+        "add   r13, r13,  r8    \n\t"   \
+        "add   r13, r13,  r9    \n\t"   \
+        "bslli r10, r10,  16    \n\t"   \
+        "bslli r11, r11,  16    \n\t"   \
+        "add   r12, r12, r10    \n\t"   \
+        "addc  r13, r13,  r0    \n\t"   \
+        "add   r12, r12, r11    \n\t"   \
+        "addc  r13, r13,  r0    \n\t"   \
+        "lwi   r10,  r4,   0    \n\t"   \
+        "add   r12, r12, r10    \n\t"   \
+        "addc  r13, r13,  r0    \n\t"   \
+        "add   r12, r12,  r5    \n\t"   \
+        "addc   r5, r13,  r0    \n\t"   \
+        "swi   r12,  r4,   0    \n\t"   \
+        "addi   r4,  r4,   4    \n\t"
+
+#define MULADDC_STOP                    \
+        "swi   r5,   %0         \n\t"   \
+        "swi   r4,   %1         \n\t"   \
+        "swi   r3,   %2         \n\t"   \
+        : "=m" (c), "=m" (d), "=m" (s)              \
+        : "m" (s), "m" (d), "m" (c), "m" (b)        \
+        : "r3", "r4"  "r5", "r6", "r7", "r8",       \
+          "r9", "r10", "r11", "r12", "r13"          \
+    );
+
+#endif /* MicroBlaze */
+
+#if defined(__tricore__)
+
+#define MULADDC_INIT                            \
+    asm(                                        \
+        "ld.a   %%a2, %3                \n\t"   \
+        "ld.a   %%a3, %4                \n\t"   \
+        "ld.w   %%d4, %5                \n\t"   \
+        "ld.w   %%d1, %6                \n\t"   \
+        "xor    %%d5, %%d5              \n\t"
+
+#define MULADDC_CORE                            \
+        "ld.w   %%d0,   [%%a2+]         \n\t"   \
+        "madd.u %%e2, %%e4, %%d0, %%d1  \n\t"   \
+        "ld.w   %%d0,   [%%a3]          \n\t"   \
+        "addx   %%d2,    %%d2,  %%d0    \n\t"   \
+        "addc   %%d3,    %%d3,    0     \n\t"   \
+        "mov    %%d4,    %%d3           \n\t"   \
+        "st.w  [%%a3+],  %%d2           \n\t"
+
+#define MULADDC_STOP                            \
+        "st.w   %0, %%d4                \n\t"   \
+        "st.a   %1, %%a3                \n\t"   \
+        "st.a   %2, %%a2                \n\t"   \
+        : "=m" (c), "=m" (d), "=m" (s)          \
+        : "m" (s), "m" (d), "m" (c), "m" (b)    \
+        : "d0", "d1", "e2", "d4", "a2", "a3"    \
+    );
+
+#endif /* TriCore */
+
+/*
+ * gcc -O0 by default uses r7 for the frame pointer, so it complains about our
+ * use of r7 below, unless -fomit-frame-pointer is passed. Unfortunately,
+ * passing that option is not easy when building with yotta.
+ *
+ * On the other hand, -fomit-frame-pointer is implied by any -Ox options with
+ * x !=0, which we can detect using __OPTIMIZE__ (which is also defined by
+ * clang and armcc5 under the same conditions).
+ *
+ * So, only use the optimized assembly below for optimized build, which avoids
+ * the build error and is pretty reasonable anyway.
+ */
+#if defined(__GNUC__) && !defined(__OPTIMIZE__)
+#define MULADDC_CANNOT_USE_R7
+#endif
+
+#if defined(__arm__) && !defined(MULADDC_CANNOT_USE_R7)
+
+#if defined(__thumb__) && !defined(__thumb2__)
+
+#define MULADDC_INIT                                    \
+    asm(                                                \
+            "ldr    r0, %3                      \n\t"   \
+            "ldr    r1, %4                      \n\t"   \
+            "ldr    r2, %5                      \n\t"   \
+            "ldr    r3, %6                      \n\t"   \
+            "lsr    r7, r3, #16                 \n\t"   \
+            "mov    r9, r7                      \n\t"   \
+            "lsl    r7, r3, #16                 \n\t"   \
+            "lsr    r7, r7, #16                 \n\t"   \
+            "mov    r8, r7                      \n\t"
+
+#define MULADDC_CORE                                    \
+            "ldmia  r0!, {r6}                   \n\t"   \
+            "lsr    r7, r6, #16                 \n\t"   \
+            "lsl    r6, r6, #16                 \n\t"   \
+            "lsr    r6, r6, #16                 \n\t"   \
+            "mov    r4, r8                      \n\t"   \
+            "mul    r4, r6                      \n\t"   \
+            "mov    r3, r9                      \n\t"   \
+            "mul    r6, r3                      \n\t"   \
+            "mov    r5, r9                      \n\t"   \
+            "mul    r5, r7                      \n\t"   \
+            "mov    r3, r8                      \n\t"   \
+            "mul    r7, r3                      \n\t"   \
+            "lsr    r3, r6, #16                 \n\t"   \
+            "add    r5, r5, r3                  \n\t"   \
+            "lsr    r3, r7, #16                 \n\t"   \
+            "add    r5, r5, r3                  \n\t"   \
+            "add    r4, r4, r2                  \n\t"   \
+            "mov    r2, #0                      \n\t"   \
+            "adc    r5, r2                      \n\t"   \
+            "lsl    r3, r6, #16                 \n\t"   \
+            "add    r4, r4, r3                  \n\t"   \
+            "adc    r5, r2                      \n\t"   \
+            "lsl    r3, r7, #16                 \n\t"   \
+            "add    r4, r4, r3                  \n\t"   \
+            "adc    r5, r2                      \n\t"   \
+            "ldr    r3, [r1]                    \n\t"   \
+            "add    r4, r4, r3                  \n\t"   \
+            "adc    r2, r5                      \n\t"   \
+            "stmia  r1!, {r4}                   \n\t"
+
+#define MULADDC_STOP                                    \
+            "str    r2, %0                      \n\t"   \
+            "str    r1, %1                      \n\t"   \
+            "str    r0, %2                      \n\t"   \
+         : "=m" (c),  "=m" (d), "=m" (s)        \
+         : "m" (s), "m" (d), "m" (c), "m" (b)   \
+         : "r0", "r1", "r2", "r3", "r4", "r5",  \
+           "r6", "r7", "r8", "r9", "cc"         \
+         );
+
+#else
+
+#define MULADDC_INIT                                    \
+    asm(                                                \
+            "ldr    r0, %3                      \n\t"   \
+            "ldr    r1, %4                      \n\t"   \
+            "ldr    r2, %5                      \n\t"   \
+            "ldr    r3, %6                      \n\t"
+
+#define MULADDC_CORE                                    \
+            "ldr    r4, [r0], #4                \n\t"   \
+            "mov    r5, #0                      \n\t"   \
+            "ldr    r6, [r1]                    \n\t"   \
+            "umlal  r2, r5, r3, r4              \n\t"   \
+            "adds   r7, r6, r2                  \n\t"   \
+            "adc    r2, r5, #0                  \n\t"   \
+            "str    r7, [r1], #4                \n\t"
+
+#define MULADDC_STOP                                    \
+            "str    r2, %0                      \n\t"   \
+            "str    r1, %1                      \n\t"   \
+            "str    r0, %2                      \n\t"   \
+         : "=m" (c),  "=m" (d), "=m" (s)        \
+         : "m" (s), "m" (d), "m" (c), "m" (b)   \
+         : "r0", "r1", "r2", "r3", "r4", "r5",  \
+           "r6", "r7", "cc"                     \
+         );
+
+#endif /* Thumb */
+
+#endif /* ARMv3 */
+
+#if defined(__alpha__)
+
+#define MULADDC_INIT                    \
+    asm(                                \
+        "ldq    $1, %3          \n\t"   \
+        "ldq    $2, %4          \n\t"   \
+        "ldq    $3, %5          \n\t"   \
+        "ldq    $4, %6          \n\t"
+
+#define MULADDC_CORE                    \
+        "ldq    $6,  0($1)      \n\t"   \
+        "addq   $1,  8, $1      \n\t"   \
+        "mulq   $6, $4, $7      \n\t"   \
+        "umulh  $6, $4, $6      \n\t"   \
+        "addq   $7, $3, $7      \n\t"   \
+        "cmpult $7, $3, $3      \n\t"   \
+        "ldq    $5,  0($2)      \n\t"   \
+        "addq   $7, $5, $7      \n\t"   \
+        "cmpult $7, $5, $5      \n\t"   \
+        "stq    $7,  0($2)      \n\t"   \
+        "addq   $2,  8, $2      \n\t"   \
+        "addq   $6, $3, $3      \n\t"   \
+        "addq   $5, $3, $3      \n\t"
+
+#define MULADDC_STOP                                    \
+        "stq    $3, %0          \n\t"   \
+        "stq    $2, %1          \n\t"   \
+        "stq    $1, %2          \n\t"   \
+        : "=m" (c), "=m" (d), "=m" (s)              \
+        : "m" (s), "m" (d), "m" (c), "m" (b)        \
+        : "$1", "$2", "$3", "$4", "$5", "$6", "$7"  \
+    );
+#endif /* Alpha */
+
+#if defined(__mips__) && !defined(__mips64)
+
+#define MULADDC_INIT                    \
+    asm(                                \
+        "lw     $10, %3         \n\t"   \
+        "lw     $11, %4         \n\t"   \
+        "lw     $12, %5         \n\t"   \
+        "lw     $13, %6         \n\t"
+
+#define MULADDC_CORE                    \
+        "lw     $14, 0($10)     \n\t"   \
+        "multu  $13, $14        \n\t"   \
+        "addi   $10, $10, 4     \n\t"   \
+        "mflo   $14             \n\t"   \
+        "mfhi   $9              \n\t"   \
+        "addu   $14, $12, $14   \n\t"   \
+        "lw     $15, 0($11)     \n\t"   \
+        "sltu   $12, $14, $12   \n\t"   \
+        "addu   $15, $14, $15   \n\t"   \
+        "sltu   $14, $15, $14   \n\t"   \
+        "addu   $12, $12, $9    \n\t"   \
+        "sw     $15, 0($11)     \n\t"   \
+        "addu   $12, $12, $14   \n\t"   \
+        "addi   $11, $11, 4     \n\t"
+
+#define MULADDC_STOP                    \
+        "sw     $12, %0         \n\t"   \
+        "sw     $11, %1         \n\t"   \
+        "sw     $10, %2         \n\t"   \
+        : "=m" (c), "=m" (d), "=m" (s)                      \
+        : "m" (s), "m" (d), "m" (c), "m" (b)                \
+        : "$9", "$10", "$11", "$12", "$13", "$14", "$15"    \
+    );
+
+#endif /* MIPS */
+#endif /* GNUC */
+
+#if (defined(_MSC_VER) && defined(_M_IX86)) || defined(__WATCOMC__)
+
+#define MULADDC_INIT                            \
+    __asm   mov     esi, s                      \
+    __asm   mov     edi, d                      \
+    __asm   mov     ecx, c                      \
+    __asm   mov     ebx, b
+
+#define MULADDC_CORE                            \
+    __asm   lodsd                               \
+    __asm   mul     ebx                         \
+    __asm   add     eax, ecx                    \
+    __asm   adc     edx, 0                      \
+    __asm   add     eax, [edi]                  \
+    __asm   adc     edx, 0                      \
+    __asm   mov     ecx, edx                    \
+    __asm   stosd
+
+#if defined(MBEDTLS_HAVE_SSE2)
+
+#define EMIT __asm _emit
+
+#define MULADDC_HUIT                            \
+    EMIT 0x0F  EMIT 0x6E  EMIT 0xC9             \
+    EMIT 0x0F  EMIT 0x6E  EMIT 0xC3             \
+    EMIT 0x0F  EMIT 0x6E  EMIT 0x1F             \
+    EMIT 0x0F  EMIT 0xD4  EMIT 0xCB             \
+    EMIT 0x0F  EMIT 0x6E  EMIT 0x16             \
+    EMIT 0x0F  EMIT 0xF4  EMIT 0xD0             \
+    EMIT 0x0F  EMIT 0x6E  EMIT 0x66  EMIT 0x04  \
+    EMIT 0x0F  EMIT 0xF4  EMIT 0xE0             \
+    EMIT 0x0F  EMIT 0x6E  EMIT 0x76  EMIT 0x08  \
+    EMIT 0x0F  EMIT 0xF4  EMIT 0xF0             \
+    EMIT 0x0F  EMIT 0x6E  EMIT 0x7E  EMIT 0x0C  \
+    EMIT 0x0F  EMIT 0xF4  EMIT 0xF8             \
+    EMIT 0x0F  EMIT 0xD4  EMIT 0xCA             \
+    EMIT 0x0F  EMIT 0x6E  EMIT 0x5F  EMIT 0x04  \
+    EMIT 0x0F  EMIT 0xD4  EMIT 0xDC             \
+    EMIT 0x0F  EMIT 0x6E  EMIT 0x6F  EMIT 0x08  \
+    EMIT 0x0F  EMIT 0xD4  EMIT 0xEE             \
+    EMIT 0x0F  EMIT 0x6E  EMIT 0x67  EMIT 0x0C  \
+    EMIT 0x0F  EMIT 0xD4  EMIT 0xFC             \
+    EMIT 0x0F  EMIT 0x7E  EMIT 0x0F             \
+    EMIT 0x0F  EMIT 0x6E  EMIT 0x56  EMIT 0x10  \
+    EMIT 0x0F  EMIT 0xF4  EMIT 0xD0             \
+    EMIT 0x0F  EMIT 0x73  EMIT 0xD1  EMIT 0x20  \
+    EMIT 0x0F  EMIT 0x6E  EMIT 0x66  EMIT 0x14  \
+    EMIT 0x0F  EMIT 0xF4  EMIT 0xE0             \
+    EMIT 0x0F  EMIT 0xD4  EMIT 0xCB             \
+    EMIT 0x0F  EMIT 0x6E  EMIT 0x76  EMIT 0x18  \
+    EMIT 0x0F  EMIT 0xF4  EMIT 0xF0             \
+    EMIT 0x0F  EMIT 0x7E  EMIT 0x4F  EMIT 0x04  \
+    EMIT 0x0F  EMIT 0x73  EMIT 0xD1  EMIT 0x20  \
+    EMIT 0x0F  EMIT 0x6E  EMIT 0x5E  EMIT 0x1C  \
+    EMIT 0x0F  EMIT 0xF4  EMIT 0xD8             \
+    EMIT 0x0F  EMIT 0xD4  EMIT 0xCD             \
+    EMIT 0x0F  EMIT 0x6E  EMIT 0x6F  EMIT 0x10  \
+    EMIT 0x0F  EMIT 0xD4  EMIT 0xD5             \
+    EMIT 0x0F  EMIT 0x7E  EMIT 0x4F  EMIT 0x08  \
+    EMIT 0x0F  EMIT 0x73  EMIT 0xD1  EMIT 0x20  \
+    EMIT 0x0F  EMIT 0xD4  EMIT 0xCF             \
+    EMIT 0x0F  EMIT 0x6E  EMIT 0x6F  EMIT 0x14  \
+    EMIT 0x0F  EMIT 0xD4  EMIT 0xE5             \
+    EMIT 0x0F  EMIT 0x7E  EMIT 0x4F  EMIT 0x0C  \
+    EMIT 0x0F  EMIT 0x73  EMIT 0xD1  EMIT 0x20  \
+    EMIT 0x0F  EMIT 0xD4  EMIT 0xCA             \
+    EMIT 0x0F  EMIT 0x6E  EMIT 0x6F  EMIT 0x18  \
+    EMIT 0x0F  EMIT 0xD4  EMIT 0xF5             \
+    EMIT 0x0F  EMIT 0x7E  EMIT 0x4F  EMIT 0x10  \
+    EMIT 0x0F  EMIT 0x73  EMIT 0xD1  EMIT 0x20  \
+    EMIT 0x0F  EMIT 0xD4  EMIT 0xCC             \
+    EMIT 0x0F  EMIT 0x6E  EMIT 0x6F  EMIT 0x1C  \
+    EMIT 0x0F  EMIT 0xD4  EMIT 0xDD             \
+    EMIT 0x0F  EMIT 0x7E  EMIT 0x4F  EMIT 0x14  \
+    EMIT 0x0F  EMIT 0x73  EMIT 0xD1  EMIT 0x20  \
+    EMIT 0x0F  EMIT 0xD4  EMIT 0xCE             \
+    EMIT 0x0F  EMIT 0x7E  EMIT 0x4F  EMIT 0x18  \
+    EMIT 0x0F  EMIT 0x73  EMIT 0xD1  EMIT 0x20  \
+    EMIT 0x0F  EMIT 0xD4  EMIT 0xCB             \
+    EMIT 0x0F  EMIT 0x7E  EMIT 0x4F  EMIT 0x1C  \
+    EMIT 0x83  EMIT 0xC7  EMIT 0x20             \
+    EMIT 0x83  EMIT 0xC6  EMIT 0x20             \
+    EMIT 0x0F  EMIT 0x73  EMIT 0xD1  EMIT 0x20  \
+    EMIT 0x0F  EMIT 0x7E  EMIT 0xC9
+
+#define MULADDC_STOP                            \
+    EMIT 0x0F  EMIT 0x77                        \
+    __asm   mov     c, ecx                      \
+    __asm   mov     d, edi                      \
+    __asm   mov     s, esi                      \
+
+#else
+
+#define MULADDC_STOP                            \
+    __asm   mov     c, ecx                      \
+    __asm   mov     d, edi                      \
+    __asm   mov     s, esi                      \
+
+#endif /* SSE2 */
+#endif /* MSVC */
+
+#endif /* MBEDTLS_HAVE_ASM */
+
+#if !defined(MULADDC_CORE)
+#if defined(MBEDTLS_HAVE_UDBL)
+
+#define MULADDC_INIT                    \
+{                                       \
+    mbedtls_t_udbl r;                           \
+    mbedtls_mpi_uint r0, r1;
+
+#define MULADDC_CORE                    \
+    r   = *(s++) * (mbedtls_t_udbl) b;          \
+    r0  = (mbedtls_mpi_uint) r;                   \
+    r1  = (mbedtls_mpi_uint)( r >> biL );         \
+    r0 += c;  r1 += (r0 <  c);          \
+    r0 += *d; r1 += (r0 < *d);          \
+    c = r1; *(d++) = r0;
+
+#define MULADDC_STOP                    \
+}
+
+#else
+#define MULADDC_INIT                    \
+{                                       \
+    mbedtls_mpi_uint s0, s1, b0, b1;              \
+    mbedtls_mpi_uint r0, r1, rx, ry;              \
+    b0 = ( b << biH ) >> biH;           \
+    b1 = ( b >> biH );
+
+#define MULADDC_CORE                    \
+    s0 = ( *s << biH ) >> biH;          \
+    s1 = ( *s >> biH ); s++;            \
+    rx = s0 * b1; r0 = s0 * b0;         \
+    ry = s1 * b0; r1 = s1 * b1;         \
+    r1 += ( rx >> biH );                \
+    r1 += ( ry >> biH );                \
+    rx <<= biH; ry <<= biH;             \
+    r0 += rx; r1 += (r0 < rx);          \
+    r0 += ry; r1 += (r0 < ry);          \
+    r0 +=  c; r1 += (r0 <  c);          \
+    r0 += *d; r1 += (r0 < *d);          \
+    c = r1; *(d++) = r0;
+
+#define MULADDC_STOP                    \
+}
+
+#endif /* C (generic)  */
+#endif /* C (longlong) */
+
+#endif /* bn_mul.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/camellia.h b/tools/sdk/include/mbedtls/mbedtls/camellia.h
new file mode 100644
index 00000000..0424d623
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/camellia.h
@@ -0,0 +1,235 @@
+/**
+ * \file camellia.h
+ *
+ * \brief Camellia block cipher
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_CAMELLIA_H
+#define MBEDTLS_CAMELLIA_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#include 
+#include 
+
+#define MBEDTLS_CAMELLIA_ENCRYPT     1
+#define MBEDTLS_CAMELLIA_DECRYPT     0
+
+#define MBEDTLS_ERR_CAMELLIA_INVALID_KEY_LENGTH           -0x0024  /**< Invalid key length. */
+#define MBEDTLS_ERR_CAMELLIA_INVALID_INPUT_LENGTH         -0x0026  /**< Invalid data input length. */
+
+#if !defined(MBEDTLS_CAMELLIA_ALT)
+// Regular implementation
+//
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          CAMELLIA context structure
+ */
+typedef struct
+{
+    int nr;                     /*!<  number of rounds  */
+    uint32_t rk[68];            /*!<  CAMELLIA round keys    */
+}
+mbedtls_camellia_context;
+
+/**
+ * \brief          Initialize CAMELLIA context
+ *
+ * \param ctx      CAMELLIA context to be initialized
+ */
+void mbedtls_camellia_init( mbedtls_camellia_context *ctx );
+
+/**
+ * \brief          Clear CAMELLIA context
+ *
+ * \param ctx      CAMELLIA context to be cleared
+ */
+void mbedtls_camellia_free( mbedtls_camellia_context *ctx );
+
+/**
+ * \brief          CAMELLIA key schedule (encryption)
+ *
+ * \param ctx      CAMELLIA context to be initialized
+ * \param key      encryption key
+ * \param keybits  must be 128, 192 or 256
+ *
+ * \return         0 if successful, or MBEDTLS_ERR_CAMELLIA_INVALID_KEY_LENGTH
+ */
+int mbedtls_camellia_setkey_enc( mbedtls_camellia_context *ctx, const unsigned char *key,
+                         unsigned int keybits );
+
+/**
+ * \brief          CAMELLIA key schedule (decryption)
+ *
+ * \param ctx      CAMELLIA context to be initialized
+ * \param key      decryption key
+ * \param keybits  must be 128, 192 or 256
+ *
+ * \return         0 if successful, or MBEDTLS_ERR_CAMELLIA_INVALID_KEY_LENGTH
+ */
+int mbedtls_camellia_setkey_dec( mbedtls_camellia_context *ctx, const unsigned char *key,
+                         unsigned int keybits );
+
+/**
+ * \brief          CAMELLIA-ECB block encryption/decryption
+ *
+ * \param ctx      CAMELLIA context
+ * \param mode     MBEDTLS_CAMELLIA_ENCRYPT or MBEDTLS_CAMELLIA_DECRYPT
+ * \param input    16-byte input block
+ * \param output   16-byte output block
+ *
+ * \return         0 if successful
+ */
+int mbedtls_camellia_crypt_ecb( mbedtls_camellia_context *ctx,
+                    int mode,
+                    const unsigned char input[16],
+                    unsigned char output[16] );
+
+#if defined(MBEDTLS_CIPHER_MODE_CBC)
+/**
+ * \brief          CAMELLIA-CBC buffer encryption/decryption
+ *                 Length should be a multiple of the block
+ *                 size (16 bytes)
+ *
+ * \note           Upon exit, the content of the IV is updated so that you can
+ *                 call the function same function again on the following
+ *                 block(s) of data and get the same result as if it was
+ *                 encrypted in one call. This allows a "streaming" usage.
+ *                 If on the other hand you need to retain the contents of the
+ *                 IV, you should either save it manually or use the cipher
+ *                 module instead.
+ *
+ * \param ctx      CAMELLIA context
+ * \param mode     MBEDTLS_CAMELLIA_ENCRYPT or MBEDTLS_CAMELLIA_DECRYPT
+ * \param length   length of the input data
+ * \param iv       initialization vector (updated after use)
+ * \param input    buffer holding the input data
+ * \param output   buffer holding the output data
+ *
+ * \return         0 if successful, or
+ *                 MBEDTLS_ERR_CAMELLIA_INVALID_INPUT_LENGTH
+ */
+int mbedtls_camellia_crypt_cbc( mbedtls_camellia_context *ctx,
+                    int mode,
+                    size_t length,
+                    unsigned char iv[16],
+                    const unsigned char *input,
+                    unsigned char *output );
+#endif /* MBEDTLS_CIPHER_MODE_CBC */
+
+#if defined(MBEDTLS_CIPHER_MODE_CFB)
+/**
+ * \brief          CAMELLIA-CFB128 buffer encryption/decryption
+ *
+ * Note: Due to the nature of CFB you should use the same key schedule for
+ * both encryption and decryption. So a context initialized with
+ * mbedtls_camellia_setkey_enc() for both MBEDTLS_CAMELLIA_ENCRYPT and CAMELLIE_DECRYPT.
+ *
+ * \note           Upon exit, the content of the IV is updated so that you can
+ *                 call the function same function again on the following
+ *                 block(s) of data and get the same result as if it was
+ *                 encrypted in one call. This allows a "streaming" usage.
+ *                 If on the other hand you need to retain the contents of the
+ *                 IV, you should either save it manually or use the cipher
+ *                 module instead.
+ *
+ * \param ctx      CAMELLIA context
+ * \param mode     MBEDTLS_CAMELLIA_ENCRYPT or MBEDTLS_CAMELLIA_DECRYPT
+ * \param length   length of the input data
+ * \param iv_off   offset in IV (updated after use)
+ * \param iv       initialization vector (updated after use)
+ * \param input    buffer holding the input data
+ * \param output   buffer holding the output data
+ *
+ * \return         0 if successful, or
+ *                 MBEDTLS_ERR_CAMELLIA_INVALID_INPUT_LENGTH
+ */
+int mbedtls_camellia_crypt_cfb128( mbedtls_camellia_context *ctx,
+                       int mode,
+                       size_t length,
+                       size_t *iv_off,
+                       unsigned char iv[16],
+                       const unsigned char *input,
+                       unsigned char *output );
+#endif /* MBEDTLS_CIPHER_MODE_CFB */
+
+#if defined(MBEDTLS_CIPHER_MODE_CTR)
+/**
+ * \brief               CAMELLIA-CTR buffer encryption/decryption
+ *
+ * Warning: You have to keep the maximum use of your counter in mind!
+ *
+ * Note: Due to the nature of CTR you should use the same key schedule for
+ * both encryption and decryption. So a context initialized with
+ * mbedtls_camellia_setkey_enc() for both MBEDTLS_CAMELLIA_ENCRYPT and MBEDTLS_CAMELLIA_DECRYPT.
+ *
+ * \param ctx           CAMELLIA context
+ * \param length        The length of the data
+ * \param nc_off        The offset in the current stream_block (for resuming
+ *                      within current cipher stream). The offset pointer to
+ *                      should be 0 at the start of a stream.
+ * \param nonce_counter The 128-bit nonce and counter.
+ * \param stream_block  The saved stream-block for resuming. Is overwritten
+ *                      by the function.
+ * \param input         The input data stream
+ * \param output        The output data stream
+ *
+ * \return         0 if successful
+ */
+int mbedtls_camellia_crypt_ctr( mbedtls_camellia_context *ctx,
+                       size_t length,
+                       size_t *nc_off,
+                       unsigned char nonce_counter[16],
+                       unsigned char stream_block[16],
+                       const unsigned char *input,
+                       unsigned char *output );
+#endif /* MBEDTLS_CIPHER_MODE_CTR */
+
+#ifdef __cplusplus
+}
+#endif
+
+#else  /* MBEDTLS_CAMELLIA_ALT */
+#include "camellia_alt.h"
+#endif /* MBEDTLS_CAMELLIA_ALT */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          Checkup routine
+ *
+ * \return         0 if successful, or 1 if the test failed
+ */
+int mbedtls_camellia_self_test( int verbose );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* camellia.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/ccm.h b/tools/sdk/include/mbedtls/mbedtls/ccm.h
new file mode 100644
index 00000000..ef75839b
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/ccm.h
@@ -0,0 +1,141 @@
+/**
+ * \file ccm.h
+ *
+ * \brief Counter with CBC-MAC (CCM) for 128-bit block ciphers
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_CCM_H
+#define MBEDTLS_CCM_H
+
+#include "cipher.h"
+
+#define MBEDTLS_ERR_CCM_BAD_INPUT      -0x000D /**< Bad input parameters to function. */
+#define MBEDTLS_ERR_CCM_AUTH_FAILED    -0x000F /**< Authenticated decryption failed. */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          CCM context structure
+ */
+typedef struct {
+    mbedtls_cipher_context_t cipher_ctx;    /*!< cipher context used */
+}
+mbedtls_ccm_context;
+
+/**
+ * \brief           Initialize CCM context (just makes references valid)
+ *                  Makes the context ready for mbedtls_ccm_setkey() or
+ *                  mbedtls_ccm_free().
+ *
+ * \param ctx       CCM context to initialize
+ */
+void mbedtls_ccm_init( mbedtls_ccm_context *ctx );
+
+/**
+ * \brief           CCM initialization (encryption and decryption)
+ *
+ * \param ctx       CCM context to be initialized
+ * \param cipher    cipher to use (a 128-bit block cipher)
+ * \param key       encryption key
+ * \param keybits   key size in bits (must be acceptable by the cipher)
+ *
+ * \return          0 if successful, or a cipher specific error code
+ */
+int mbedtls_ccm_setkey( mbedtls_ccm_context *ctx,
+                        mbedtls_cipher_id_t cipher,
+                        const unsigned char *key,
+                        unsigned int keybits );
+
+/**
+ * \brief           Free a CCM context and underlying cipher sub-context
+ *
+ * \param ctx       CCM context to free
+ */
+void mbedtls_ccm_free( mbedtls_ccm_context *ctx );
+
+/**
+ * \brief           CCM buffer encryption
+ *
+ * \param ctx       CCM context
+ * \param length    length of the input data in bytes
+ * \param iv        nonce (initialization vector)
+ * \param iv_len    length of IV in bytes
+ *                  must be 2, 3, 4, 5, 6, 7 or 8
+ * \param add       additional data
+ * \param add_len   length of additional data in bytes
+ *                  must be less than 2^16 - 2^8
+ * \param input     buffer holding the input data
+ * \param output    buffer for holding the output data
+ *                  must be at least 'length' bytes wide
+ * \param tag       buffer for holding the tag
+ * \param tag_len   length of the tag to generate in bytes
+ *                  must be 4, 6, 8, 10, 14 or 16
+ *
+ * \note            The tag is written to a separate buffer. To get the tag
+ *                  concatenated with the output as in the CCM spec, use
+ *                  tag = output + length and make sure the output buffer is
+ *                  at least length + tag_len wide.
+ *
+ * \return          0 if successful
+ */
+int mbedtls_ccm_encrypt_and_tag( mbedtls_ccm_context *ctx, size_t length,
+                         const unsigned char *iv, size_t iv_len,
+                         const unsigned char *add, size_t add_len,
+                         const unsigned char *input, unsigned char *output,
+                         unsigned char *tag, size_t tag_len );
+
+/**
+ * \brief           CCM buffer authenticated decryption
+ *
+ * \param ctx       CCM context
+ * \param length    length of the input data
+ * \param iv        initialization vector
+ * \param iv_len    length of IV
+ * \param add       additional data
+ * \param add_len   length of additional data
+ * \param input     buffer holding the input data
+ * \param output    buffer for holding the output data
+ * \param tag       buffer holding the tag
+ * \param tag_len   length of the tag
+ *
+ * \return         0 if successful and authenticated,
+ *                 MBEDTLS_ERR_CCM_AUTH_FAILED if tag does not match
+ */
+int mbedtls_ccm_auth_decrypt( mbedtls_ccm_context *ctx, size_t length,
+                      const unsigned char *iv, size_t iv_len,
+                      const unsigned char *add, size_t add_len,
+                      const unsigned char *input, unsigned char *output,
+                      const unsigned char *tag, size_t tag_len );
+
+#if defined(MBEDTLS_SELF_TEST) && defined(MBEDTLS_AES_C)
+/**
+ * \brief          Checkup routine
+ *
+ * \return         0 if successful, or 1 if the test failed
+ */
+int mbedtls_ccm_self_test( int verbose );
+#endif /* MBEDTLS_SELF_TEST && MBEDTLS_AES_C */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MBEDTLS_CCM_H */
diff --git a/tools/sdk/include/mbedtls/mbedtls/certs.h b/tools/sdk/include/mbedtls/mbedtls/certs.h
new file mode 100644
index 00000000..ca49086e
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/certs.h
@@ -0,0 +1,99 @@
+/**
+ * \file certs.h
+ *
+ * \brief Sample certificates and DHM parameters for testing
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_CERTS_H
+#define MBEDTLS_CERTS_H
+
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(MBEDTLS_PEM_PARSE_C)
+/* Concatenation of all CA certificates in PEM format if available */
+extern const char   mbedtls_test_cas_pem[];
+extern const size_t mbedtls_test_cas_pem_len;
+#endif
+
+/* List of all CA certificates, terminated by NULL */
+extern const char * mbedtls_test_cas[];
+extern const size_t mbedtls_test_cas_len[];
+
+/*
+ * Convenience for users who just want a certificate:
+ * RSA by default, or ECDSA if RSA is not available
+ */
+extern const char * mbedtls_test_ca_crt;
+extern const size_t mbedtls_test_ca_crt_len;
+extern const char * mbedtls_test_ca_key;
+extern const size_t mbedtls_test_ca_key_len;
+extern const char * mbedtls_test_ca_pwd;
+extern const size_t mbedtls_test_ca_pwd_len;
+extern const char * mbedtls_test_srv_crt;
+extern const size_t mbedtls_test_srv_crt_len;
+extern const char * mbedtls_test_srv_key;
+extern const size_t mbedtls_test_srv_key_len;
+extern const char * mbedtls_test_cli_crt;
+extern const size_t mbedtls_test_cli_crt_len;
+extern const char * mbedtls_test_cli_key;
+extern const size_t mbedtls_test_cli_key_len;
+
+#if defined(MBEDTLS_ECDSA_C)
+extern const char   mbedtls_test_ca_crt_ec[];
+extern const size_t mbedtls_test_ca_crt_ec_len;
+extern const char   mbedtls_test_ca_key_ec[];
+extern const size_t mbedtls_test_ca_key_ec_len;
+extern const char   mbedtls_test_ca_pwd_ec[];
+extern const size_t mbedtls_test_ca_pwd_ec_len;
+extern const char   mbedtls_test_srv_crt_ec[];
+extern const size_t mbedtls_test_srv_crt_ec_len;
+extern const char   mbedtls_test_srv_key_ec[];
+extern const size_t mbedtls_test_srv_key_ec_len;
+extern const char   mbedtls_test_cli_crt_ec[];
+extern const size_t mbedtls_test_cli_crt_ec_len;
+extern const char   mbedtls_test_cli_key_ec[];
+extern const size_t mbedtls_test_cli_key_ec_len;
+#endif
+
+#if defined(MBEDTLS_RSA_C)
+extern const char   mbedtls_test_ca_crt_rsa[];
+extern const size_t mbedtls_test_ca_crt_rsa_len;
+extern const char   mbedtls_test_ca_key_rsa[];
+extern const size_t mbedtls_test_ca_key_rsa_len;
+extern const char   mbedtls_test_ca_pwd_rsa[];
+extern const size_t mbedtls_test_ca_pwd_rsa_len;
+extern const char   mbedtls_test_srv_crt_rsa[];
+extern const size_t mbedtls_test_srv_crt_rsa_len;
+extern const char   mbedtls_test_srv_key_rsa[];
+extern const size_t mbedtls_test_srv_key_rsa_len;
+extern const char   mbedtls_test_cli_crt_rsa[];
+extern const size_t mbedtls_test_cli_crt_rsa_len;
+extern const char   mbedtls_test_cli_key_rsa[];
+extern const size_t mbedtls_test_cli_key_rsa_len;
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* certs.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/check_config.h b/tools/sdk/include/mbedtls/mbedtls/check_config.h
new file mode 100644
index 00000000..a95af6ca
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/check_config.h
@@ -0,0 +1,587 @@
+/**
+ * \file check_config.h
+ *
+ * \brief Consistency checks for configuration options
+ *
+ *  Copyright (C) 2006-2016, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+
+/*
+ * It is recommended to include this file from your config.h
+ * in order to catch dependency issues early.
+ */
+
+#ifndef MBEDTLS_CHECK_CONFIG_H
+#define MBEDTLS_CHECK_CONFIG_H
+
+/*
+ * We assume CHAR_BIT is 8 in many places. In practice, this is true on our
+ * target platforms, so not an issue, but let's just be extra sure.
+ */
+#include 
+#if CHAR_BIT != 8
+#error "mbed TLS requires a platform with 8-bit chars"
+#endif
+
+#if defined(_WIN32)
+#if !defined(MBEDTLS_PLATFORM_C)
+#error "MBEDTLS_PLATFORM_C is required on Windows"
+#endif
+
+/* Fix the config here. Not convenient to put an #ifdef _WIN32 in config.h as
+ * it would confuse config.pl. */
+#if !defined(MBEDTLS_PLATFORM_SNPRINTF_ALT) && \
+    !defined(MBEDTLS_PLATFORM_SNPRINTF_MACRO)
+#define MBEDTLS_PLATFORM_SNPRINTF_ALT
+#endif
+#endif /* _WIN32 */
+
+#if defined(TARGET_LIKE_MBED) && \
+    ( defined(MBEDTLS_NET_C) || defined(MBEDTLS_TIMING_C) )
+#error "The NET and TIMING modules are not available for mbed OS - please use the network and timing functions provided by mbed OS"
+#endif
+
+#if defined(MBEDTLS_DEPRECATED_WARNING) && \
+    !defined(__GNUC__) && !defined(__clang__)
+#error "MBEDTLS_DEPRECATED_WARNING only works with GCC and Clang"
+#endif
+
+#if defined(MBEDTLS_HAVE_TIME_DATE) && !defined(MBEDTLS_HAVE_TIME)
+#error "MBEDTLS_HAVE_TIME_DATE without MBEDTLS_HAVE_TIME does not make sense"
+#endif
+
+#if defined(MBEDTLS_AESNI_C) && !defined(MBEDTLS_HAVE_ASM)
+#error "MBEDTLS_AESNI_C defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_CTR_DRBG_C) && !defined(MBEDTLS_AES_C)
+#error "MBEDTLS_CTR_DRBG_C defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_DHM_C) && !defined(MBEDTLS_BIGNUM_C)
+#error "MBEDTLS_DHM_C defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_ECDH_C) && !defined(MBEDTLS_ECP_C)
+#error "MBEDTLS_ECDH_C defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_ECDSA_C) &&            \
+    ( !defined(MBEDTLS_ECP_C) ||           \
+      !defined(MBEDTLS_ASN1_PARSE_C) ||    \
+      !defined(MBEDTLS_ASN1_WRITE_C) )
+#error "MBEDTLS_ECDSA_C defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_ECJPAKE_C) &&           \
+    ( !defined(MBEDTLS_ECP_C) || !defined(MBEDTLS_MD_C) )
+#error "MBEDTLS_ECJPAKE_C defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_ECDSA_DETERMINISTIC) && !defined(MBEDTLS_HMAC_DRBG_C)
+#error "MBEDTLS_ECDSA_DETERMINISTIC defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_ECP_C) && ( !defined(MBEDTLS_BIGNUM_C) || (   \
+    !defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) &&                  \
+    !defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) &&                  \
+    !defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) &&                  \
+    !defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) &&                  \
+    !defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) &&                  \
+    !defined(MBEDTLS_ECP_DP_BP256R1_ENABLED)   &&                  \
+    !defined(MBEDTLS_ECP_DP_BP384R1_ENABLED)   &&                  \
+    !defined(MBEDTLS_ECP_DP_BP512R1_ENABLED)   &&                  \
+    !defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) &&                  \
+    !defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) &&                  \
+    !defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) ) )
+#error "MBEDTLS_ECP_C defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_ENTROPY_C) && (!defined(MBEDTLS_SHA512_C) &&      \
+                                    !defined(MBEDTLS_SHA256_C))
+#error "MBEDTLS_ENTROPY_C defined, but not all prerequisites"
+#endif
+#if defined(MBEDTLS_ENTROPY_C) && defined(MBEDTLS_SHA512_C) &&         \
+    defined(MBEDTLS_CTR_DRBG_ENTROPY_LEN) && (MBEDTLS_CTR_DRBG_ENTROPY_LEN > 64)
+#error "MBEDTLS_CTR_DRBG_ENTROPY_LEN value too high"
+#endif
+#if defined(MBEDTLS_ENTROPY_C) &&                                            \
+    ( !defined(MBEDTLS_SHA512_C) || defined(MBEDTLS_ENTROPY_FORCE_SHA256) ) \
+    && defined(MBEDTLS_CTR_DRBG_ENTROPY_LEN) && (MBEDTLS_CTR_DRBG_ENTROPY_LEN > 32)
+#error "MBEDTLS_CTR_DRBG_ENTROPY_LEN value too high"
+#endif
+#if defined(MBEDTLS_ENTROPY_C) && \
+    defined(MBEDTLS_ENTROPY_FORCE_SHA256) && !defined(MBEDTLS_SHA256_C)
+#error "MBEDTLS_ENTROPY_FORCE_SHA256 defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_TEST_NULL_ENTROPY) && \
+    ( !defined(MBEDTLS_ENTROPY_C) || !defined(MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES) )
+#error "MBEDTLS_TEST_NULL_ENTROPY defined, but not all prerequisites"
+#endif
+#if defined(MBEDTLS_TEST_NULL_ENTROPY) && \
+     ( defined(MBEDTLS_ENTROPY_NV_SEED) || defined(MBEDTLS_ENTROPY_HARDWARE_ALT) || \
+    defined(MBEDTLS_HAVEGE_C) )
+#error "MBEDTLS_TEST_NULL_ENTROPY defined, but entropy sources too"
+#endif
+
+#if defined(MBEDTLS_GCM_C) && (                                        \
+        !defined(MBEDTLS_AES_C) && !defined(MBEDTLS_CAMELLIA_C) )
+#error "MBEDTLS_GCM_C defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_HAVEGE_C) && !defined(MBEDTLS_TIMING_C)
+#error "MBEDTLS_HAVEGE_C defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_HMAC_DRBG_C) && !defined(MBEDTLS_MD_C)
+#error "MBEDTLS_HMAC_DRBG_C defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED) &&                 \
+    ( !defined(MBEDTLS_ECDH_C) || !defined(MBEDTLS_X509_CRT_PARSE_C) )
+#error "MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED) &&                 \
+    ( !defined(MBEDTLS_ECDH_C) || !defined(MBEDTLS_X509_CRT_PARSE_C) )
+#error "MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED) && !defined(MBEDTLS_DHM_C)
+#error "MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED) &&                     \
+    !defined(MBEDTLS_ECDH_C)
+#error "MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED) &&                   \
+    ( !defined(MBEDTLS_DHM_C) || !defined(MBEDTLS_RSA_C) ||           \
+      !defined(MBEDTLS_X509_CRT_PARSE_C) || !defined(MBEDTLS_PKCS1_V15) )
+#error "MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED) &&                 \
+    ( !defined(MBEDTLS_ECDH_C) || !defined(MBEDTLS_RSA_C) ||          \
+      !defined(MBEDTLS_X509_CRT_PARSE_C) || !defined(MBEDTLS_PKCS1_V15) )
+#error "MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED) &&                 \
+    ( !defined(MBEDTLS_ECDH_C) || !defined(MBEDTLS_ECDSA_C) ||          \
+      !defined(MBEDTLS_X509_CRT_PARSE_C) )
+#error "MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED) &&                   \
+    ( !defined(MBEDTLS_RSA_C) || !defined(MBEDTLS_X509_CRT_PARSE_C) || \
+      !defined(MBEDTLS_PKCS1_V15) )
+#error "MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_KEY_EXCHANGE_RSA_ENABLED) &&                       \
+    ( !defined(MBEDTLS_RSA_C) || !defined(MBEDTLS_X509_CRT_PARSE_C) || \
+      !defined(MBEDTLS_PKCS1_V15) )
+#error "MBEDTLS_KEY_EXCHANGE_RSA_ENABLED defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED) &&                    \
+    ( !defined(MBEDTLS_ECJPAKE_C) || !defined(MBEDTLS_SHA256_C) ||      \
+      !defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) )
+#error "MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_MEMORY_BUFFER_ALLOC_C) &&                          \
+    ( !defined(MBEDTLS_PLATFORM_C) || !defined(MBEDTLS_PLATFORM_MEMORY) )
+#error "MBEDTLS_MEMORY_BUFFER_ALLOC_C defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_PADLOCK_C) && !defined(MBEDTLS_HAVE_ASM)
+#error "MBEDTLS_PADLOCK_C defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_PEM_PARSE_C) && !defined(MBEDTLS_BASE64_C)
+#error "MBEDTLS_PEM_PARSE_C defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_PEM_WRITE_C) && !defined(MBEDTLS_BASE64_C)
+#error "MBEDTLS_PEM_WRITE_C defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_PK_C) && \
+    ( !defined(MBEDTLS_RSA_C) && !defined(MBEDTLS_ECP_C) )
+#error "MBEDTLS_PK_C defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_PK_PARSE_C) && !defined(MBEDTLS_PK_C)
+#error "MBEDTLS_PK_PARSE_C defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_PK_WRITE_C) && !defined(MBEDTLS_PK_C)
+#error "MBEDTLS_PK_WRITE_C defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_PKCS11_C) && !defined(MBEDTLS_PK_C)
+#error "MBEDTLS_PKCS11_C defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_PLATFORM_EXIT_ALT) && !defined(MBEDTLS_PLATFORM_C)
+#error "MBEDTLS_PLATFORM_EXIT_ALT defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_PLATFORM_EXIT_MACRO) && !defined(MBEDTLS_PLATFORM_C)
+#error "MBEDTLS_PLATFORM_EXIT_MACRO defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_PLATFORM_EXIT_MACRO) &&\
+    ( defined(MBEDTLS_PLATFORM_STD_EXIT) ||\
+        defined(MBEDTLS_PLATFORM_EXIT_ALT) )
+#error "MBEDTLS_PLATFORM_EXIT_MACRO and MBEDTLS_PLATFORM_STD_EXIT/MBEDTLS_PLATFORM_EXIT_ALT cannot be defined simultaneously"
+#endif
+
+#if defined(MBEDTLS_PLATFORM_FPRINTF_ALT) && !defined(MBEDTLS_PLATFORM_C)
+#error "MBEDTLS_PLATFORM_FPRINTF_ALT defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_PLATFORM_FPRINTF_MACRO) && !defined(MBEDTLS_PLATFORM_C)
+#error "MBEDTLS_PLATFORM_FPRINTF_MACRO defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_PLATFORM_FPRINTF_MACRO) &&\
+    ( defined(MBEDTLS_PLATFORM_STD_FPRINTF) ||\
+        defined(MBEDTLS_PLATFORM_FPRINTF_ALT) )
+#error "MBEDTLS_PLATFORM_FPRINTF_MACRO and MBEDTLS_PLATFORM_STD_FPRINTF/MBEDTLS_PLATFORM_FPRINTF_ALT cannot be defined simultaneously"
+#endif
+
+#if defined(MBEDTLS_PLATFORM_FREE_MACRO) &&\
+    ( !defined(MBEDTLS_PLATFORM_C) || !defined(MBEDTLS_PLATFORM_MEMORY) )
+#error "MBEDTLS_PLATFORM_FREE_MACRO defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_PLATFORM_FREE_MACRO) &&\
+    defined(MBEDTLS_PLATFORM_STD_FREE)
+#error "MBEDTLS_PLATFORM_FREE_MACRO and MBEDTLS_PLATFORM_STD_FREE cannot be defined simultaneously"
+#endif
+
+#if defined(MBEDTLS_PLATFORM_FREE_MACRO) && !defined(MBEDTLS_PLATFORM_CALLOC_MACRO)
+#error "MBEDTLS_PLATFORM_CALLOC_MACRO must be defined if MBEDTLS_PLATFORM_FREE_MACRO is"
+#endif
+
+#if defined(MBEDTLS_PLATFORM_CALLOC_MACRO) &&\
+    ( !defined(MBEDTLS_PLATFORM_C) || !defined(MBEDTLS_PLATFORM_MEMORY) )
+#error "MBEDTLS_PLATFORM_CALLOC_MACRO defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_PLATFORM_CALLOC_MACRO) &&\
+    defined(MBEDTLS_PLATFORM_STD_CALLOC)
+#error "MBEDTLS_PLATFORM_CALLOC_MACRO and MBEDTLS_PLATFORM_STD_CALLOC cannot be defined simultaneously"
+#endif
+
+#if defined(MBEDTLS_PLATFORM_CALLOC_MACRO) && !defined(MBEDTLS_PLATFORM_FREE_MACRO)
+#error "MBEDTLS_PLATFORM_FREE_MACRO must be defined if MBEDTLS_PLATFORM_CALLOC_MACRO is"
+#endif
+
+#if defined(MBEDTLS_PLATFORM_MEMORY) && !defined(MBEDTLS_PLATFORM_C)
+#error "MBEDTLS_PLATFORM_MEMORY defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_PLATFORM_PRINTF_ALT) && !defined(MBEDTLS_PLATFORM_C)
+#error "MBEDTLS_PLATFORM_PRINTF_ALT defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_PLATFORM_PRINTF_MACRO) && !defined(MBEDTLS_PLATFORM_C)
+#error "MBEDTLS_PLATFORM_PRINTF_MACRO defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_PLATFORM_PRINTF_MACRO) &&\
+    ( defined(MBEDTLS_PLATFORM_STD_PRINTF) ||\
+        defined(MBEDTLS_PLATFORM_PRINTF_ALT) )
+#error "MBEDTLS_PLATFORM_PRINTF_MACRO and MBEDTLS_PLATFORM_STD_PRINTF/MBEDTLS_PLATFORM_PRINTF_ALT cannot be defined simultaneously"
+#endif
+
+#if defined(MBEDTLS_PLATFORM_SNPRINTF_ALT) && !defined(MBEDTLS_PLATFORM_C)
+#error "MBEDTLS_PLATFORM_SNPRINTF_ALT defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_PLATFORM_SNPRINTF_MACRO) && !defined(MBEDTLS_PLATFORM_C)
+#error "MBEDTLS_PLATFORM_SNPRINTF_MACRO defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_PLATFORM_SNPRINTF_MACRO) &&\
+    ( defined(MBEDTLS_PLATFORM_STD_SNPRINTF) ||\
+        defined(MBEDTLS_PLATFORM_SNPRINTF_ALT) )
+#error "MBEDTLS_PLATFORM_SNPRINTF_MACRO and MBEDTLS_PLATFORM_STD_SNPRINTF/MBEDTLS_PLATFORM_SNPRINTF_ALT cannot be defined simultaneously"
+#endif
+
+#if defined(MBEDTLS_PLATFORM_STD_MEM_HDR) &&\
+    !defined(MBEDTLS_PLATFORM_NO_STD_FUNCTIONS)
+#error "MBEDTLS_PLATFORM_STD_MEM_HDR defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_PLATFORM_STD_CALLOC) && !defined(MBEDTLS_PLATFORM_MEMORY)
+#error "MBEDTLS_PLATFORM_STD_CALLOC defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_PLATFORM_STD_CALLOC) && !defined(MBEDTLS_PLATFORM_MEMORY)
+#error "MBEDTLS_PLATFORM_STD_CALLOC defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_PLATFORM_STD_FREE) && !defined(MBEDTLS_PLATFORM_MEMORY)
+#error "MBEDTLS_PLATFORM_STD_FREE defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_PLATFORM_STD_EXIT) &&\
+    !defined(MBEDTLS_PLATFORM_EXIT_ALT)
+#error "MBEDTLS_PLATFORM_STD_EXIT defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_PLATFORM_STD_FPRINTF) &&\
+    !defined(MBEDTLS_PLATFORM_FPRINTF_ALT)
+#error "MBEDTLS_PLATFORM_STD_FPRINTF defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_PLATFORM_STD_PRINTF) &&\
+    !defined(MBEDTLS_PLATFORM_PRINTF_ALT)
+#error "MBEDTLS_PLATFORM_STD_PRINTF defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_PLATFORM_STD_SNPRINTF) &&\
+    !defined(MBEDTLS_PLATFORM_SNPRINTF_ALT)
+#error "MBEDTLS_PLATFORM_STD_SNPRINTF defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_ENTROPY_NV_SEED) &&\
+    ( !defined(MBEDTLS_PLATFORM_C) || !defined(MBEDTLS_ENTROPY_C) )
+#error "MBEDTLS_ENTROPY_NV_SEED defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_PLATFORM_NV_SEED_ALT) &&\
+    !defined(MBEDTLS_ENTROPY_NV_SEED)
+#error "MBEDTLS_PLATFORM_NV_SEED_ALT defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_PLATFORM_STD_NV_SEED_READ) &&\
+    !defined(MBEDTLS_PLATFORM_NV_SEED_ALT)
+#error "MBEDTLS_PLATFORM_STD_NV_SEED_READ defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_PLATFORM_STD_NV_SEED_WRITE) &&\
+    !defined(MBEDTLS_PLATFORM_NV_SEED_ALT)
+#error "MBEDTLS_PLATFORM_STD_NV_SEED_WRITE defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_PLATFORM_NV_SEED_READ_MACRO) &&\
+    ( defined(MBEDTLS_PLATFORM_STD_NV_SEED_READ) ||\
+      defined(MBEDTLS_PLATFORM_NV_SEED_ALT) )
+#error "MBEDTLS_PLATFORM_NV_SEED_READ_MACRO and MBEDTLS_PLATFORM_STD_NV_SEED_READ cannot be defined simultaneously"
+#endif
+
+#if defined(MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO) &&\
+    ( defined(MBEDTLS_PLATFORM_STD_NV_SEED_WRITE) ||\
+      defined(MBEDTLS_PLATFORM_NV_SEED_ALT) )
+#error "MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO and MBEDTLS_PLATFORM_STD_NV_SEED_WRITE cannot be defined simultaneously"
+#endif
+
+#if defined(MBEDTLS_RSA_C) && ( !defined(MBEDTLS_BIGNUM_C) ||         \
+    !defined(MBEDTLS_OID_C) )
+#error "MBEDTLS_RSA_C defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_RSA_C) && ( !defined(MBEDTLS_PKCS1_V21) &&         \
+    !defined(MBEDTLS_PKCS1_V15) )
+#error "MBEDTLS_RSA_C defined, but none of the PKCS1 versions enabled"
+#endif
+
+#if defined(MBEDTLS_X509_RSASSA_PSS_SUPPORT) &&                        \
+    ( !defined(MBEDTLS_RSA_C) || !defined(MBEDTLS_PKCS1_V21) )
+#error "MBEDTLS_X509_RSASSA_PSS_SUPPORT defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_SSL_PROTO_SSL3) && ( !defined(MBEDTLS_MD5_C) ||     \
+    !defined(MBEDTLS_SHA1_C) )
+#error "MBEDTLS_SSL_PROTO_SSL3 defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_SSL_PROTO_TLS1) && ( !defined(MBEDTLS_MD5_C) ||     \
+    !defined(MBEDTLS_SHA1_C) )
+#error "MBEDTLS_SSL_PROTO_TLS1 defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_SSL_PROTO_TLS1_1) && ( !defined(MBEDTLS_MD5_C) ||     \
+    !defined(MBEDTLS_SHA1_C) )
+#error "MBEDTLS_SSL_PROTO_TLS1_1 defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_SSL_PROTO_TLS1_2) && ( !defined(MBEDTLS_SHA1_C) &&     \
+    !defined(MBEDTLS_SHA256_C) && !defined(MBEDTLS_SHA512_C) )
+#error "MBEDTLS_SSL_PROTO_TLS1_2 defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_SSL_PROTO_DTLS)     && \
+    !defined(MBEDTLS_SSL_PROTO_TLS1_1)  && \
+    !defined(MBEDTLS_SSL_PROTO_TLS1_2)
+#error "MBEDTLS_SSL_PROTO_DTLS defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_SSL_CLI_C) && !defined(MBEDTLS_SSL_TLS_C)
+#error "MBEDTLS_SSL_CLI_C defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_SSL_TLS_C) && ( !defined(MBEDTLS_CIPHER_C) ||     \
+    !defined(MBEDTLS_MD_C) )
+#error "MBEDTLS_SSL_TLS_C defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_SSL_SRV_C) && !defined(MBEDTLS_SSL_TLS_C)
+#error "MBEDTLS_SSL_SRV_C defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_SSL_TLS_C) && (!defined(MBEDTLS_SSL_PROTO_SSL3) && \
+    !defined(MBEDTLS_SSL_PROTO_TLS1) && !defined(MBEDTLS_SSL_PROTO_TLS1_1) && \
+    !defined(MBEDTLS_SSL_PROTO_TLS1_2))
+#error "MBEDTLS_SSL_TLS_C defined, but no protocols are active"
+#endif
+
+#if defined(MBEDTLS_SSL_TLS_C) && (defined(MBEDTLS_SSL_PROTO_SSL3) && \
+    defined(MBEDTLS_SSL_PROTO_TLS1_1) && !defined(MBEDTLS_SSL_PROTO_TLS1))
+#error "Illegal protocol selection"
+#endif
+
+#if defined(MBEDTLS_SSL_TLS_C) && (defined(MBEDTLS_SSL_PROTO_TLS1) && \
+    defined(MBEDTLS_SSL_PROTO_TLS1_2) && !defined(MBEDTLS_SSL_PROTO_TLS1_1))
+#error "Illegal protocol selection"
+#endif
+
+#if defined(MBEDTLS_SSL_TLS_C) && (defined(MBEDTLS_SSL_PROTO_SSL3) && \
+    defined(MBEDTLS_SSL_PROTO_TLS1_2) && (!defined(MBEDTLS_SSL_PROTO_TLS1) || \
+    !defined(MBEDTLS_SSL_PROTO_TLS1_1)))
+#error "Illegal protocol selection"
+#endif
+
+#if defined(MBEDTLS_SSL_DTLS_HELLO_VERIFY) && !defined(MBEDTLS_SSL_PROTO_DTLS)
+#error "MBEDTLS_SSL_DTLS_HELLO_VERIFY  defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE) && \
+    !defined(MBEDTLS_SSL_DTLS_HELLO_VERIFY)
+#error "MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE  defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_SSL_DTLS_ANTI_REPLAY) &&                              \
+    ( !defined(MBEDTLS_SSL_TLS_C) || !defined(MBEDTLS_SSL_PROTO_DTLS) )
+#error "MBEDTLS_SSL_DTLS_ANTI_REPLAY  defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_SSL_DTLS_BADMAC_LIMIT) &&                              \
+    ( !defined(MBEDTLS_SSL_TLS_C) || !defined(MBEDTLS_SSL_PROTO_DTLS) )
+#error "MBEDTLS_SSL_DTLS_BADMAC_LIMIT  defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_SSL_ENCRYPT_THEN_MAC) &&   \
+    !defined(MBEDTLS_SSL_PROTO_TLS1)   &&      \
+    !defined(MBEDTLS_SSL_PROTO_TLS1_1) &&      \
+    !defined(MBEDTLS_SSL_PROTO_TLS1_2)
+#error "MBEDTLS_SSL_ENCRYPT_THEN_MAC defined, but not all prerequsites"
+#endif
+
+#if defined(MBEDTLS_SSL_EXTENDED_MASTER_SECRET) && \
+    !defined(MBEDTLS_SSL_PROTO_TLS1)   &&          \
+    !defined(MBEDTLS_SSL_PROTO_TLS1_1) &&          \
+    !defined(MBEDTLS_SSL_PROTO_TLS1_2)
+#error "MBEDTLS_SSL_EXTENDED_MASTER_SECRET defined, but not all prerequsites"
+#endif
+
+#if defined(MBEDTLS_SSL_TICKET_C) && !defined(MBEDTLS_CIPHER_C)
+#error "MBEDTLS_SSL_TICKET_C defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_SSL_CBC_RECORD_SPLITTING) && \
+    !defined(MBEDTLS_SSL_PROTO_SSL3) && !defined(MBEDTLS_SSL_PROTO_TLS1)
+#error "MBEDTLS_SSL_CBC_RECORD_SPLITTING defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_SSL_SERVER_NAME_INDICATION) && \
+        !defined(MBEDTLS_X509_CRT_PARSE_C)
+#error "MBEDTLS_SSL_SERVER_NAME_INDICATION defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_THREADING_PTHREAD)
+#if !defined(MBEDTLS_THREADING_C) || defined(MBEDTLS_THREADING_IMPL)
+#error "MBEDTLS_THREADING_PTHREAD defined, but not all prerequisites"
+#endif
+#define MBEDTLS_THREADING_IMPL
+#endif
+
+#if defined(MBEDTLS_THREADING_ALT)
+#if !defined(MBEDTLS_THREADING_C) || defined(MBEDTLS_THREADING_IMPL)
+#error "MBEDTLS_THREADING_ALT defined, but not all prerequisites"
+#endif
+#define MBEDTLS_THREADING_IMPL
+#endif
+
+#if defined(MBEDTLS_THREADING_C) && !defined(MBEDTLS_THREADING_IMPL)
+#error "MBEDTLS_THREADING_C defined, single threading implementation required"
+#endif
+#undef MBEDTLS_THREADING_IMPL
+
+#if defined(MBEDTLS_VERSION_FEATURES) && !defined(MBEDTLS_VERSION_C)
+#error "MBEDTLS_VERSION_FEATURES defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_X509_USE_C) && ( !defined(MBEDTLS_BIGNUM_C) ||  \
+    !defined(MBEDTLS_OID_C) || !defined(MBEDTLS_ASN1_PARSE_C) ||      \
+    !defined(MBEDTLS_PK_PARSE_C) )
+#error "MBEDTLS_X509_USE_C defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_X509_CREATE_C) && ( !defined(MBEDTLS_BIGNUM_C) ||  \
+    !defined(MBEDTLS_OID_C) || !defined(MBEDTLS_ASN1_WRITE_C) ||       \
+    !defined(MBEDTLS_PK_WRITE_C) )
+#error "MBEDTLS_X509_CREATE_C defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_X509_CRT_PARSE_C) && ( !defined(MBEDTLS_X509_USE_C) )
+#error "MBEDTLS_X509_CRT_PARSE_C defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_X509_CRL_PARSE_C) && ( !defined(MBEDTLS_X509_USE_C) )
+#error "MBEDTLS_X509_CRL_PARSE_C defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_X509_CSR_PARSE_C) && ( !defined(MBEDTLS_X509_USE_C) )
+#error "MBEDTLS_X509_CSR_PARSE_C defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_X509_CRT_WRITE_C) && ( !defined(MBEDTLS_X509_CREATE_C) )
+#error "MBEDTLS_X509_CRT_WRITE_C defined, but not all prerequisites"
+#endif
+
+#if defined(MBEDTLS_X509_CSR_WRITE_C) && ( !defined(MBEDTLS_X509_CREATE_C) )
+#error "MBEDTLS_X509_CSR_WRITE_C defined, but not all prerequisites"
+#endif
+
+/*
+ * Avoid warning from -pedantic. This is a convenient place for this
+ * workaround since this is included by every single file before the
+ * #if defined(MBEDTLS_xxx_C) that results in emtpy translation units.
+ */
+typedef int mbedtls_iso_c_forbids_empty_translation_units;
+
+#endif /* MBEDTLS_CHECK_CONFIG_H */
diff --git a/tools/sdk/include/mbedtls/mbedtls/cipher.h b/tools/sdk/include/mbedtls/mbedtls/cipher.h
new file mode 100644
index 00000000..c9675544
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/cipher.h
@@ -0,0 +1,699 @@
+/**
+ * \file cipher.h
+ *
+ * \brief Generic cipher wrapper.
+ *
+ * \author Adriaan de Jong 
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+
+#ifndef MBEDTLS_CIPHER_H
+#define MBEDTLS_CIPHER_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#include 
+
+#if defined(MBEDTLS_GCM_C) || defined(MBEDTLS_CCM_C)
+#define MBEDTLS_CIPHER_MODE_AEAD
+#endif
+
+#if defined(MBEDTLS_CIPHER_MODE_CBC)
+#define MBEDTLS_CIPHER_MODE_WITH_PADDING
+#endif
+
+#if defined(MBEDTLS_ARC4_C)
+#define MBEDTLS_CIPHER_MODE_STREAM
+#endif
+
+#if ( defined(__ARMCC_VERSION) || defined(_MSC_VER) ) && \
+    !defined(inline) && !defined(__cplusplus)
+#define inline __inline
+#endif
+
+#define MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE            -0x6080  /**< The selected feature is not available. */
+#define MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA                 -0x6100  /**< Bad input parameters to function. */
+#define MBEDTLS_ERR_CIPHER_ALLOC_FAILED                   -0x6180  /**< Failed to allocate memory. */
+#define MBEDTLS_ERR_CIPHER_INVALID_PADDING                -0x6200  /**< Input data contains invalid padding and is rejected. */
+#define MBEDTLS_ERR_CIPHER_FULL_BLOCK_EXPECTED            -0x6280  /**< Decryption of block requires a full block. */
+#define MBEDTLS_ERR_CIPHER_AUTH_FAILED                    -0x6300  /**< Authentication failed (for AEAD modes). */
+#define MBEDTLS_ERR_CIPHER_INVALID_CONTEXT              -0x6380  /**< The context is invalid, eg because it was free()ed. */
+
+#define MBEDTLS_CIPHER_VARIABLE_IV_LEN     0x01    /**< Cipher accepts IVs of variable length */
+#define MBEDTLS_CIPHER_VARIABLE_KEY_LEN    0x02    /**< Cipher accepts keys of variable length */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    MBEDTLS_CIPHER_ID_NONE = 0,
+    MBEDTLS_CIPHER_ID_NULL,
+    MBEDTLS_CIPHER_ID_AES,
+    MBEDTLS_CIPHER_ID_DES,
+    MBEDTLS_CIPHER_ID_3DES,
+    MBEDTLS_CIPHER_ID_CAMELLIA,
+    MBEDTLS_CIPHER_ID_BLOWFISH,
+    MBEDTLS_CIPHER_ID_ARC4,
+} mbedtls_cipher_id_t;
+
+typedef enum {
+    MBEDTLS_CIPHER_NONE = 0,
+    MBEDTLS_CIPHER_NULL,
+    MBEDTLS_CIPHER_AES_128_ECB,
+    MBEDTLS_CIPHER_AES_192_ECB,
+    MBEDTLS_CIPHER_AES_256_ECB,
+    MBEDTLS_CIPHER_AES_128_CBC,
+    MBEDTLS_CIPHER_AES_192_CBC,
+    MBEDTLS_CIPHER_AES_256_CBC,
+    MBEDTLS_CIPHER_AES_128_CFB128,
+    MBEDTLS_CIPHER_AES_192_CFB128,
+    MBEDTLS_CIPHER_AES_256_CFB128,
+    MBEDTLS_CIPHER_AES_128_CTR,
+    MBEDTLS_CIPHER_AES_192_CTR,
+    MBEDTLS_CIPHER_AES_256_CTR,
+    MBEDTLS_CIPHER_AES_128_GCM,
+    MBEDTLS_CIPHER_AES_192_GCM,
+    MBEDTLS_CIPHER_AES_256_GCM,
+    MBEDTLS_CIPHER_CAMELLIA_128_ECB,
+    MBEDTLS_CIPHER_CAMELLIA_192_ECB,
+    MBEDTLS_CIPHER_CAMELLIA_256_ECB,
+    MBEDTLS_CIPHER_CAMELLIA_128_CBC,
+    MBEDTLS_CIPHER_CAMELLIA_192_CBC,
+    MBEDTLS_CIPHER_CAMELLIA_256_CBC,
+    MBEDTLS_CIPHER_CAMELLIA_128_CFB128,
+    MBEDTLS_CIPHER_CAMELLIA_192_CFB128,
+    MBEDTLS_CIPHER_CAMELLIA_256_CFB128,
+    MBEDTLS_CIPHER_CAMELLIA_128_CTR,
+    MBEDTLS_CIPHER_CAMELLIA_192_CTR,
+    MBEDTLS_CIPHER_CAMELLIA_256_CTR,
+    MBEDTLS_CIPHER_CAMELLIA_128_GCM,
+    MBEDTLS_CIPHER_CAMELLIA_192_GCM,
+    MBEDTLS_CIPHER_CAMELLIA_256_GCM,
+    MBEDTLS_CIPHER_DES_ECB,
+    MBEDTLS_CIPHER_DES_CBC,
+    MBEDTLS_CIPHER_DES_EDE_ECB,
+    MBEDTLS_CIPHER_DES_EDE_CBC,
+    MBEDTLS_CIPHER_DES_EDE3_ECB,
+    MBEDTLS_CIPHER_DES_EDE3_CBC,
+    MBEDTLS_CIPHER_BLOWFISH_ECB,
+    MBEDTLS_CIPHER_BLOWFISH_CBC,
+    MBEDTLS_CIPHER_BLOWFISH_CFB64,
+    MBEDTLS_CIPHER_BLOWFISH_CTR,
+    MBEDTLS_CIPHER_ARC4_128,
+    MBEDTLS_CIPHER_AES_128_CCM,
+    MBEDTLS_CIPHER_AES_192_CCM,
+    MBEDTLS_CIPHER_AES_256_CCM,
+    MBEDTLS_CIPHER_CAMELLIA_128_CCM,
+    MBEDTLS_CIPHER_CAMELLIA_192_CCM,
+    MBEDTLS_CIPHER_CAMELLIA_256_CCM,
+} mbedtls_cipher_type_t;
+
+typedef enum {
+    MBEDTLS_MODE_NONE = 0,
+    MBEDTLS_MODE_ECB,
+    MBEDTLS_MODE_CBC,
+    MBEDTLS_MODE_CFB,
+    MBEDTLS_MODE_OFB, /* Unused! */
+    MBEDTLS_MODE_CTR,
+    MBEDTLS_MODE_GCM,
+    MBEDTLS_MODE_STREAM,
+    MBEDTLS_MODE_CCM,
+} mbedtls_cipher_mode_t;
+
+typedef enum {
+    MBEDTLS_PADDING_PKCS7 = 0,     /**< PKCS7 padding (default)        */
+    MBEDTLS_PADDING_ONE_AND_ZEROS, /**< ISO/IEC 7816-4 padding         */
+    MBEDTLS_PADDING_ZEROS_AND_LEN, /**< ANSI X.923 padding             */
+    MBEDTLS_PADDING_ZEROS,         /**< zero padding (not reversible!) */
+    MBEDTLS_PADDING_NONE,          /**< never pad (full blocks only)   */
+} mbedtls_cipher_padding_t;
+
+typedef enum {
+    MBEDTLS_OPERATION_NONE = -1,
+    MBEDTLS_DECRYPT = 0,
+    MBEDTLS_ENCRYPT,
+} mbedtls_operation_t;
+
+enum {
+    /** Undefined key length */
+    MBEDTLS_KEY_LENGTH_NONE = 0,
+    /** Key length, in bits (including parity), for DES keys */
+    MBEDTLS_KEY_LENGTH_DES  = 64,
+    /** Key length, in bits (including parity), for DES in two key EDE */
+    MBEDTLS_KEY_LENGTH_DES_EDE = 128,
+    /** Key length, in bits (including parity), for DES in three-key EDE */
+    MBEDTLS_KEY_LENGTH_DES_EDE3 = 192,
+};
+
+/** Maximum length of any IV, in bytes */
+#define MBEDTLS_MAX_IV_LENGTH      16
+/** Maximum block size of any cipher, in bytes */
+#define MBEDTLS_MAX_BLOCK_LENGTH   16
+
+/**
+ * Base cipher information (opaque struct).
+ */
+typedef struct mbedtls_cipher_base_t mbedtls_cipher_base_t;
+
+/**
+ * Cipher information. Allows cipher functions to be called in a generic way.
+ */
+typedef struct {
+    /** Full cipher identifier (e.g. MBEDTLS_CIPHER_AES_256_CBC) */
+    mbedtls_cipher_type_t type;
+
+    /** Cipher mode (e.g. MBEDTLS_MODE_CBC) */
+    mbedtls_cipher_mode_t mode;
+
+    /** Cipher key length, in bits (default length for variable sized ciphers)
+     *  (Includes parity bits for ciphers like DES) */
+    unsigned int key_bitlen;
+
+    /** Name of the cipher */
+    const char * name;
+
+    /** IV/NONCE size, in bytes.
+     *  For cipher that accept many sizes: recommended size */
+    unsigned int iv_size;
+
+    /** Flags for variable IV size, variable key size, etc. */
+    int flags;
+
+    /** block size, in bytes */
+    unsigned int block_size;
+
+    /** Base cipher information and functions */
+    const mbedtls_cipher_base_t *base;
+
+} mbedtls_cipher_info_t;
+
+/**
+ * Generic cipher context.
+ */
+typedef struct {
+    /** Information about the associated cipher */
+    const mbedtls_cipher_info_t *cipher_info;
+
+    /** Key length to use */
+    int key_bitlen;
+
+    /** Operation that the context's key has been initialised for */
+    mbedtls_operation_t operation;
+
+#if defined(MBEDTLS_CIPHER_MODE_WITH_PADDING)
+    /** Padding functions to use, if relevant for cipher mode */
+    void (*add_padding)( unsigned char *output, size_t olen, size_t data_len );
+    int (*get_padding)( unsigned char *input, size_t ilen, size_t *data_len );
+#endif
+
+    /** Buffer for data that hasn't been encrypted yet */
+    unsigned char unprocessed_data[MBEDTLS_MAX_BLOCK_LENGTH];
+
+    /** Number of bytes that still need processing */
+    size_t unprocessed_len;
+
+    /** Current IV or NONCE_COUNTER for CTR-mode */
+    unsigned char iv[MBEDTLS_MAX_IV_LENGTH];
+
+    /** IV size in bytes (for ciphers with variable-length IVs) */
+    size_t iv_size;
+
+    /** Cipher-specific context */
+    void *cipher_ctx;
+} mbedtls_cipher_context_t;
+
+/**
+ * \brief Returns the list of ciphers supported by the generic cipher module.
+ *
+ * \return              a statically allocated array of ciphers, the last entry
+ *                      is 0.
+ */
+const int *mbedtls_cipher_list( void );
+
+/**
+ * \brief               Returns the cipher information structure associated
+ *                      with the given cipher name.
+ *
+ * \param cipher_name   Name of the cipher to search for.
+ *
+ * \return              the cipher information structure associated with the
+ *                      given cipher_name, or NULL if not found.
+ */
+const mbedtls_cipher_info_t *mbedtls_cipher_info_from_string( const char *cipher_name );
+
+/**
+ * \brief               Returns the cipher information structure associated
+ *                      with the given cipher type.
+ *
+ * \param cipher_type   Type of the cipher to search for.
+ *
+ * \return              the cipher information structure associated with the
+ *                      given cipher_type, or NULL if not found.
+ */
+const mbedtls_cipher_info_t *mbedtls_cipher_info_from_type( const mbedtls_cipher_type_t cipher_type );
+
+/**
+ * \brief               Returns the cipher information structure associated
+ *                      with the given cipher id, key size and mode.
+ *
+ * \param cipher_id     Id of the cipher to search for
+ *                      (e.g. MBEDTLS_CIPHER_ID_AES)
+ * \param key_bitlen    Length of the key in bits
+ * \param mode          Cipher mode (e.g. MBEDTLS_MODE_CBC)
+ *
+ * \return              the cipher information structure associated with the
+ *                      given cipher_type, or NULL if not found.
+ */
+const mbedtls_cipher_info_t *mbedtls_cipher_info_from_values( const mbedtls_cipher_id_t cipher_id,
+                                              int key_bitlen,
+                                              const mbedtls_cipher_mode_t mode );
+
+/**
+ * \brief               Initialize a cipher_context (as NONE)
+ */
+void mbedtls_cipher_init( mbedtls_cipher_context_t *ctx );
+
+/**
+ * \brief               Free and clear the cipher-specific context of ctx.
+ *                      Freeing ctx itself remains the responsibility of the
+ *                      caller.
+ */
+void mbedtls_cipher_free( mbedtls_cipher_context_t *ctx );
+
+/**
+ * \brief               Initialises and fills the cipher context structure with
+ *                      the appropriate values.
+ *
+ * \note                Currently also clears structure. In future versions you
+ *                      will be required to call mbedtls_cipher_init() on the structure
+ *                      first.
+ *
+ * \param ctx           context to initialise. May not be NULL.
+ * \param cipher_info   cipher to use.
+ *
+ * \return              0 on success,
+ *                      MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on parameter failure,
+ *                      MBEDTLS_ERR_CIPHER_ALLOC_FAILED if allocation of the
+ *                      cipher-specific context failed.
+ */
+int mbedtls_cipher_setup( mbedtls_cipher_context_t *ctx, const mbedtls_cipher_info_t *cipher_info );
+
+/**
+ * \brief               Returns the block size of the given cipher.
+ *
+ * \param ctx           cipher's context. Must have been initialised.
+ *
+ * \return              size of the cipher's blocks, or 0 if ctx has not been
+ *                      initialised.
+ */
+static inline unsigned int mbedtls_cipher_get_block_size( const mbedtls_cipher_context_t *ctx )
+{
+    if( NULL == ctx || NULL == ctx->cipher_info )
+        return 0;
+
+    return ctx->cipher_info->block_size;
+}
+
+/**
+ * \brief               Returns the mode of operation for the cipher.
+ *                      (e.g. MBEDTLS_MODE_CBC)
+ *
+ * \param ctx           cipher's context. Must have been initialised.
+ *
+ * \return              mode of operation, or MBEDTLS_MODE_NONE if ctx
+ *                      has not been initialised.
+ */
+static inline mbedtls_cipher_mode_t mbedtls_cipher_get_cipher_mode( const mbedtls_cipher_context_t *ctx )
+{
+    if( NULL == ctx || NULL == ctx->cipher_info )
+        return MBEDTLS_MODE_NONE;
+
+    return ctx->cipher_info->mode;
+}
+
+/**
+ * \brief               Returns the size of the cipher's IV/NONCE in bytes.
+ *
+ * \param ctx           cipher's context. Must have been initialised.
+ *
+ * \return              If IV has not been set yet: (recommended) IV size
+ *                      (0 for ciphers not using IV/NONCE).
+ *                      If IV has already been set: actual size.
+ */
+static inline int mbedtls_cipher_get_iv_size( const mbedtls_cipher_context_t *ctx )
+{
+    if( NULL == ctx || NULL == ctx->cipher_info )
+        return 0;
+
+    if( ctx->iv_size != 0 )
+        return (int) ctx->iv_size;
+
+    return (int) ctx->cipher_info->iv_size;
+}
+
+/**
+ * \brief               Returns the type of the given cipher.
+ *
+ * \param ctx           cipher's context. Must have been initialised.
+ *
+ * \return              type of the cipher, or MBEDTLS_CIPHER_NONE if ctx has
+ *                      not been initialised.
+ */
+static inline mbedtls_cipher_type_t mbedtls_cipher_get_type( const mbedtls_cipher_context_t *ctx )
+{
+    if( NULL == ctx || NULL == ctx->cipher_info )
+        return MBEDTLS_CIPHER_NONE;
+
+    return ctx->cipher_info->type;
+}
+
+/**
+ * \brief               Returns the name of the given cipher, as a string.
+ *
+ * \param ctx           cipher's context. Must have been initialised.
+ *
+ * \return              name of the cipher, or NULL if ctx was not initialised.
+ */
+static inline const char *mbedtls_cipher_get_name( const mbedtls_cipher_context_t *ctx )
+{
+    if( NULL == ctx || NULL == ctx->cipher_info )
+        return 0;
+
+    return ctx->cipher_info->name;
+}
+
+/**
+ * \brief               Returns the key length of the cipher.
+ *
+ * \param ctx           cipher's context. Must have been initialised.
+ *
+ * \return              cipher's key length, in bits, or
+ *                      MBEDTLS_KEY_LENGTH_NONE if ctx has not been
+ *                      initialised.
+ */
+static inline int mbedtls_cipher_get_key_bitlen( const mbedtls_cipher_context_t *ctx )
+{
+    if( NULL == ctx || NULL == ctx->cipher_info )
+        return MBEDTLS_KEY_LENGTH_NONE;
+
+    return (int) ctx->cipher_info->key_bitlen;
+}
+
+/**
+ * \brief               Returns the operation of the given cipher.
+ *
+ * \param ctx           cipher's context. Must have been initialised.
+ *
+ * \return              operation (MBEDTLS_ENCRYPT or MBEDTLS_DECRYPT),
+ *                      or MBEDTLS_OPERATION_NONE if ctx has not been
+ *                      initialised.
+ */
+static inline mbedtls_operation_t mbedtls_cipher_get_operation( const mbedtls_cipher_context_t *ctx )
+{
+    if( NULL == ctx || NULL == ctx->cipher_info )
+        return MBEDTLS_OPERATION_NONE;
+
+    return ctx->operation;
+}
+
+/**
+ * \brief               Set the key to use with the given context.
+ *
+ * \param ctx           generic cipher context. May not be NULL. Must have been
+ *                      initialised using cipher_context_from_type or
+ *                      cipher_context_from_string.
+ * \param key           The key to use.
+ * \param key_bitlen    key length to use, in bits.
+ * \param operation     Operation that the key will be used for, either
+ *                      MBEDTLS_ENCRYPT or MBEDTLS_DECRYPT.
+ *
+ * \returns             0 on success, MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA if
+ *                      parameter verification fails or a cipher specific
+ *                      error code.
+ */
+int mbedtls_cipher_setkey( mbedtls_cipher_context_t *ctx, const unsigned char *key,
+                   int key_bitlen, const mbedtls_operation_t operation );
+
+#if defined(MBEDTLS_CIPHER_MODE_WITH_PADDING)
+/**
+ * \brief               Set padding mode, for cipher modes that use padding.
+ *                      (Default: PKCS7 padding.)
+ *
+ * \param ctx           generic cipher context
+ * \param mode          padding mode
+ *
+ * \returns             0 on success, MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE
+ *                      if selected padding mode is not supported, or
+ *                      MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA if the cipher mode
+ *                      does not support padding.
+ */
+int mbedtls_cipher_set_padding_mode( mbedtls_cipher_context_t *ctx, mbedtls_cipher_padding_t mode );
+#endif /* MBEDTLS_CIPHER_MODE_WITH_PADDING */
+
+/**
+ * \brief               Set the initialization vector (IV) or nonce
+ *
+ * \param ctx           generic cipher context
+ * \param iv            IV to use (or NONCE_COUNTER for CTR-mode ciphers)
+ * \param iv_len        IV length for ciphers with variable-size IV;
+ *                      discarded by ciphers with fixed-size IV.
+ *
+ * \returns             0 on success, or MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA
+ *
+ * \note                Some ciphers don't use IVs nor NONCE. For these
+ *                      ciphers, this function has no effect.
+ */
+int mbedtls_cipher_set_iv( mbedtls_cipher_context_t *ctx,
+                   const unsigned char *iv, size_t iv_len );
+
+/**
+ * \brief               Finish preparation of the given context
+ *
+ * \param ctx           generic cipher context
+ *
+ * \returns             0 on success, MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA
+ *                      if parameter verification fails.
+ */
+int mbedtls_cipher_reset( mbedtls_cipher_context_t *ctx );
+
+#if defined(MBEDTLS_GCM_C)
+/**
+ * \brief               Add additional data (for AEAD ciphers).
+ *                      Currently only supported with GCM.
+ *                      Must be called exactly once, after mbedtls_cipher_reset().
+ *
+ * \param ctx           generic cipher context
+ * \param ad            Additional data to use.
+ * \param ad_len        Length of ad.
+ *
+ * \return              0 on success, or a specific error code.
+ */
+int mbedtls_cipher_update_ad( mbedtls_cipher_context_t *ctx,
+                      const unsigned char *ad, size_t ad_len );
+#endif /* MBEDTLS_GCM_C */
+
+/**
+ * \brief               Generic cipher update function. Encrypts/decrypts
+ *                      using the given cipher context. Writes as many block
+ *                      size'd blocks of data as possible to output. Any data
+ *                      that cannot be written immediately will either be added
+ *                      to the next block, or flushed when cipher_final is
+ *                      called.
+ *                      Exception: for MBEDTLS_MODE_ECB, expects single block
+ *                                 in size (e.g. 16 bytes for AES)
+ *
+ * \param ctx           generic cipher context
+ * \param input         buffer holding the input data
+ * \param ilen          length of the input data
+ * \param output        buffer for the output data. Should be able to hold at
+ *                      least ilen + block_size. Cannot be the same buffer as
+ *                      input!
+ * \param olen          length of the output data, will be filled with the
+ *                      actual number of bytes written.
+ *
+ * \returns             0 on success, MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA if
+ *                      parameter verification fails,
+ *                      MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE on an
+ *                      unsupported mode for a cipher or a cipher specific
+ *                      error code.
+ *
+ * \note                If the underlying cipher is GCM, all calls to this
+ *                      function, except the last one before mbedtls_cipher_finish(),
+ *                      must have ilen a multiple of the block size.
+ */
+int mbedtls_cipher_update( mbedtls_cipher_context_t *ctx, const unsigned char *input,
+                   size_t ilen, unsigned char *output, size_t *olen );
+
+/**
+ * \brief               Generic cipher finalisation function. If data still
+ *                      needs to be flushed from an incomplete block, data
+ *                      contained within it will be padded with the size of
+ *                      the last block, and written to the output buffer.
+ *
+ * \param ctx           Generic cipher context
+ * \param output        buffer to write data to. Needs block_size available.
+ * \param olen          length of the data written to the output buffer.
+ *
+ * \returns             0 on success, MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA if
+ *                      parameter verification fails,
+ *                      MBEDTLS_ERR_CIPHER_FULL_BLOCK_EXPECTED if decryption
+ *                      expected a full block but was not provided one,
+ *                      MBEDTLS_ERR_CIPHER_INVALID_PADDING on invalid padding
+ *                      while decrypting or a cipher specific error code.
+ */
+int mbedtls_cipher_finish( mbedtls_cipher_context_t *ctx,
+                   unsigned char *output, size_t *olen );
+
+#if defined(MBEDTLS_GCM_C)
+/**
+ * \brief               Write tag for AEAD ciphers.
+ *                      Currently only supported with GCM.
+ *                      Must be called after mbedtls_cipher_finish().
+ *
+ * \param ctx           Generic cipher context
+ * \param tag           buffer to write the tag
+ * \param tag_len       Length of the tag to write
+ *
+ * \return              0 on success, or a specific error code.
+ */
+int mbedtls_cipher_write_tag( mbedtls_cipher_context_t *ctx,
+                      unsigned char *tag, size_t tag_len );
+
+/**
+ * \brief               Check tag for AEAD ciphers.
+ *                      Currently only supported with GCM.
+ *                      Must be called after mbedtls_cipher_finish().
+ *
+ * \param ctx           Generic cipher context
+ * \param tag           Buffer holding the tag
+ * \param tag_len       Length of the tag to check
+ *
+ * \return              0 on success, or a specific error code.
+ */
+int mbedtls_cipher_check_tag( mbedtls_cipher_context_t *ctx,
+                      const unsigned char *tag, size_t tag_len );
+#endif /* MBEDTLS_GCM_C */
+
+/**
+ * \brief               Generic all-in-one encryption/decryption
+ *                      (for all ciphers except AEAD constructs).
+ *
+ * \param ctx           generic cipher context
+ * \param iv            IV to use (or NONCE_COUNTER for CTR-mode ciphers)
+ * \param iv_len        IV length for ciphers with variable-size IV;
+ *                      discarded by ciphers with fixed-size IV.
+ * \param input         buffer holding the input data
+ * \param ilen          length of the input data
+ * \param output        buffer for the output data. Should be able to hold at
+ *                      least ilen + block_size. Cannot be the same buffer as
+ *                      input!
+ * \param olen          length of the output data, will be filled with the
+ *                      actual number of bytes written.
+ *
+ * \note                Some ciphers don't use IVs nor NONCE. For these
+ *                      ciphers, use iv = NULL and iv_len = 0.
+ *
+ * \returns             0 on success, or
+ *                      MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA, or
+ *                      MBEDTLS_ERR_CIPHER_FULL_BLOCK_EXPECTED if decryption
+ *                      expected a full block but was not provided one, or
+ *                      MBEDTLS_ERR_CIPHER_INVALID_PADDING on invalid padding
+ *                      while decrypting, or
+ *                      a cipher specific error code.
+ */
+int mbedtls_cipher_crypt( mbedtls_cipher_context_t *ctx,
+                  const unsigned char *iv, size_t iv_len,
+                  const unsigned char *input, size_t ilen,
+                  unsigned char *output, size_t *olen );
+
+#if defined(MBEDTLS_CIPHER_MODE_AEAD)
+/**
+ * \brief               Generic autenticated encryption (AEAD ciphers).
+ *
+ * \param ctx           generic cipher context
+ * \param iv            IV to use (or NONCE_COUNTER for CTR-mode ciphers)
+ * \param iv_len        IV length for ciphers with variable-size IV;
+ *                      discarded by ciphers with fixed-size IV.
+ * \param ad            Additional data to authenticate.
+ * \param ad_len        Length of ad.
+ * \param input         buffer holding the input data
+ * \param ilen          length of the input data
+ * \param output        buffer for the output data.
+ *                      Should be able to hold at least ilen.
+ * \param olen          length of the output data, will be filled with the
+ *                      actual number of bytes written.
+ * \param tag           buffer for the authentication tag
+ * \param tag_len       desired tag length
+ *
+ * \returns             0 on success, or
+ *                      MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA, or
+ *                      a cipher specific error code.
+ */
+int mbedtls_cipher_auth_encrypt( mbedtls_cipher_context_t *ctx,
+                         const unsigned char *iv, size_t iv_len,
+                         const unsigned char *ad, size_t ad_len,
+                         const unsigned char *input, size_t ilen,
+                         unsigned char *output, size_t *olen,
+                         unsigned char *tag, size_t tag_len );
+
+/**
+ * \brief               Generic autenticated decryption (AEAD ciphers).
+ *
+ * \param ctx           generic cipher context
+ * \param iv            IV to use (or NONCE_COUNTER for CTR-mode ciphers)
+ * \param iv_len        IV length for ciphers with variable-size IV;
+ *                      discarded by ciphers with fixed-size IV.
+ * \param ad            Additional data to be authenticated.
+ * \param ad_len        Length of ad.
+ * \param input         buffer holding the input data
+ * \param ilen          length of the input data
+ * \param output        buffer for the output data.
+ *                      Should be able to hold at least ilen.
+ * \param olen          length of the output data, will be filled with the
+ *                      actual number of bytes written.
+ * \param tag           buffer holding the authentication tag
+ * \param tag_len       length of the authentication tag
+ *
+ * \returns             0 on success, or
+ *                      MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA, or
+ *                      MBEDTLS_ERR_CIPHER_AUTH_FAILED if data isn't authentic,
+ *                      or a cipher specific error code.
+ *
+ * \note                If the data is not authentic, then the output buffer
+ *                      is zeroed out to prevent the unauthentic plaintext to
+ *                      be used by mistake, making this interface safer.
+ */
+int mbedtls_cipher_auth_decrypt( mbedtls_cipher_context_t *ctx,
+                         const unsigned char *iv, size_t iv_len,
+                         const unsigned char *ad, size_t ad_len,
+                         const unsigned char *input, size_t ilen,
+                         unsigned char *output, size_t *olen,
+                         const unsigned char *tag, size_t tag_len );
+#endif /* MBEDTLS_CIPHER_MODE_AEAD */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MBEDTLS_CIPHER_H */
diff --git a/tools/sdk/include/mbedtls/mbedtls/cipher_internal.h b/tools/sdk/include/mbedtls/mbedtls/cipher_internal.h
new file mode 100644
index 00000000..6c58bcc5
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/cipher_internal.h
@@ -0,0 +1,109 @@
+/**
+ * \file cipher_internal.h
+ *
+ * \brief Cipher wrappers.
+ *
+ * \author Adriaan de Jong 
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_CIPHER_WRAP_H
+#define MBEDTLS_CIPHER_WRAP_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#include "cipher.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Base cipher information. The non-mode specific functions and values.
+ */
+struct mbedtls_cipher_base_t
+{
+    /** Base Cipher type (e.g. MBEDTLS_CIPHER_ID_AES) */
+    mbedtls_cipher_id_t cipher;
+
+    /** Encrypt using ECB */
+    int (*ecb_func)( void *ctx, mbedtls_operation_t mode,
+                     const unsigned char *input, unsigned char *output );
+
+#if defined(MBEDTLS_CIPHER_MODE_CBC)
+    /** Encrypt using CBC */
+    int (*cbc_func)( void *ctx, mbedtls_operation_t mode, size_t length,
+                     unsigned char *iv, const unsigned char *input,
+                     unsigned char *output );
+#endif
+
+#if defined(MBEDTLS_CIPHER_MODE_CFB)
+    /** Encrypt using CFB (Full length) */
+    int (*cfb_func)( void *ctx, mbedtls_operation_t mode, size_t length, size_t *iv_off,
+                     unsigned char *iv, const unsigned char *input,
+                     unsigned char *output );
+#endif
+
+#if defined(MBEDTLS_CIPHER_MODE_CTR)
+    /** Encrypt using CTR */
+    int (*ctr_func)( void *ctx, size_t length, size_t *nc_off,
+                     unsigned char *nonce_counter, unsigned char *stream_block,
+                     const unsigned char *input, unsigned char *output );
+#endif
+
+#if defined(MBEDTLS_CIPHER_MODE_STREAM)
+    /** Encrypt using STREAM */
+    int (*stream_func)( void *ctx, size_t length,
+                        const unsigned char *input, unsigned char *output );
+#endif
+
+    /** Set key for encryption purposes */
+    int (*setkey_enc_func)( void *ctx, const unsigned char *key,
+                            unsigned int key_bitlen );
+
+    /** Set key for decryption purposes */
+    int (*setkey_dec_func)( void *ctx, const unsigned char *key,
+                            unsigned int key_bitlen);
+
+    /** Allocate a new context */
+    void * (*ctx_alloc_func)( void );
+
+    /** Free the given context */
+    void (*ctx_free_func)( void *ctx );
+
+};
+
+typedef struct
+{
+    mbedtls_cipher_type_t type;
+    const mbedtls_cipher_info_t *info;
+} mbedtls_cipher_definition_t;
+
+extern const mbedtls_cipher_definition_t mbedtls_cipher_definitions[];
+
+extern int mbedtls_cipher_supported[];
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MBEDTLS_CIPHER_WRAP_H */
diff --git a/tools/sdk/include/mbedtls/mbedtls/compat-1.3.h b/tools/sdk/include/mbedtls/mbedtls/compat-1.3.h
new file mode 100644
index 00000000..27abbd97
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/compat-1.3.h
@@ -0,0 +1,2634 @@
+/**
+ * \file compat-1.3.h
+ *
+ * \brief Compatibility definitions for using mbed TLS with client code written
+ *  for the PolarSSL naming conventions.
+ *
+ * \deprecated Use the new names directly instead
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+
+#if ! defined(MBEDTLS_DEPRECATED_REMOVED)
+
+#if defined(MBEDTLS_DEPRECATED_WARNING)
+#warning "Including compat-1.3.h is deprecated"
+#endif
+
+#ifndef MBEDTLS_COMPAT13_H
+#define MBEDTLS_COMPAT13_H
+
+/*
+ * config.h options
+ */
+#if defined MBEDTLS_AESNI_C
+#define POLARSSL_AESNI_C MBEDTLS_AESNI_C
+#endif
+#if defined MBEDTLS_AES_ALT
+#define POLARSSL_AES_ALT MBEDTLS_AES_ALT
+#endif
+#if defined MBEDTLS_AES_C
+#define POLARSSL_AES_C MBEDTLS_AES_C
+#endif
+#if defined MBEDTLS_AES_ROM_TABLES
+#define POLARSSL_AES_ROM_TABLES MBEDTLS_AES_ROM_TABLES
+#endif
+#if defined MBEDTLS_ARC4_ALT
+#define POLARSSL_ARC4_ALT MBEDTLS_ARC4_ALT
+#endif
+#if defined MBEDTLS_ARC4_C
+#define POLARSSL_ARC4_C MBEDTLS_ARC4_C
+#endif
+#if defined MBEDTLS_ASN1_PARSE_C
+#define POLARSSL_ASN1_PARSE_C MBEDTLS_ASN1_PARSE_C
+#endif
+#if defined MBEDTLS_ASN1_WRITE_C
+#define POLARSSL_ASN1_WRITE_C MBEDTLS_ASN1_WRITE_C
+#endif
+#if defined MBEDTLS_BASE64_C
+#define POLARSSL_BASE64_C MBEDTLS_BASE64_C
+#endif
+#if defined MBEDTLS_BIGNUM_C
+#define POLARSSL_BIGNUM_C MBEDTLS_BIGNUM_C
+#endif
+#if defined MBEDTLS_BLOWFISH_ALT
+#define POLARSSL_BLOWFISH_ALT MBEDTLS_BLOWFISH_ALT
+#endif
+#if defined MBEDTLS_BLOWFISH_C
+#define POLARSSL_BLOWFISH_C MBEDTLS_BLOWFISH_C
+#endif
+#if defined MBEDTLS_CAMELLIA_ALT
+#define POLARSSL_CAMELLIA_ALT MBEDTLS_CAMELLIA_ALT
+#endif
+#if defined MBEDTLS_CAMELLIA_C
+#define POLARSSL_CAMELLIA_C MBEDTLS_CAMELLIA_C
+#endif
+#if defined MBEDTLS_CAMELLIA_SMALL_MEMORY
+#define POLARSSL_CAMELLIA_SMALL_MEMORY MBEDTLS_CAMELLIA_SMALL_MEMORY
+#endif
+#if defined MBEDTLS_CCM_C
+#define POLARSSL_CCM_C MBEDTLS_CCM_C
+#endif
+#if defined MBEDTLS_CERTS_C
+#define POLARSSL_CERTS_C MBEDTLS_CERTS_C
+#endif
+#if defined MBEDTLS_CIPHER_C
+#define POLARSSL_CIPHER_C MBEDTLS_CIPHER_C
+#endif
+#if defined MBEDTLS_CIPHER_MODE_CBC
+#define POLARSSL_CIPHER_MODE_CBC MBEDTLS_CIPHER_MODE_CBC
+#endif
+#if defined MBEDTLS_CIPHER_MODE_CFB
+#define POLARSSL_CIPHER_MODE_CFB MBEDTLS_CIPHER_MODE_CFB
+#endif
+#if defined MBEDTLS_CIPHER_MODE_CTR
+#define POLARSSL_CIPHER_MODE_CTR MBEDTLS_CIPHER_MODE_CTR
+#endif
+#if defined MBEDTLS_CIPHER_NULL_CIPHER
+#define POLARSSL_CIPHER_NULL_CIPHER MBEDTLS_CIPHER_NULL_CIPHER
+#endif
+#if defined MBEDTLS_CIPHER_PADDING_ONE_AND_ZEROS
+#define POLARSSL_CIPHER_PADDING_ONE_AND_ZEROS MBEDTLS_CIPHER_PADDING_ONE_AND_ZEROS
+#endif
+#if defined MBEDTLS_CIPHER_PADDING_PKCS7
+#define POLARSSL_CIPHER_PADDING_PKCS7 MBEDTLS_CIPHER_PADDING_PKCS7
+#endif
+#if defined MBEDTLS_CIPHER_PADDING_ZEROS
+#define POLARSSL_CIPHER_PADDING_ZEROS MBEDTLS_CIPHER_PADDING_ZEROS
+#endif
+#if defined MBEDTLS_CIPHER_PADDING_ZEROS_AND_LEN
+#define POLARSSL_CIPHER_PADDING_ZEROS_AND_LEN MBEDTLS_CIPHER_PADDING_ZEROS_AND_LEN
+#endif
+#if defined MBEDTLS_CTR_DRBG_C
+#define POLARSSL_CTR_DRBG_C MBEDTLS_CTR_DRBG_C
+#endif
+#if defined MBEDTLS_DEBUG_C
+#define POLARSSL_DEBUG_C MBEDTLS_DEBUG_C
+#endif
+#if defined MBEDTLS_DEPRECATED_REMOVED
+#define POLARSSL_DEPRECATED_REMOVED MBEDTLS_DEPRECATED_REMOVED
+#endif
+#if defined MBEDTLS_DEPRECATED_WARNING
+#define POLARSSL_DEPRECATED_WARNING MBEDTLS_DEPRECATED_WARNING
+#endif
+#if defined MBEDTLS_DES_ALT
+#define POLARSSL_DES_ALT MBEDTLS_DES_ALT
+#endif
+#if defined MBEDTLS_DES_C
+#define POLARSSL_DES_C MBEDTLS_DES_C
+#endif
+#if defined MBEDTLS_DHM_C
+#define POLARSSL_DHM_C MBEDTLS_DHM_C
+#endif
+#if defined MBEDTLS_ECDH_C
+#define POLARSSL_ECDH_C MBEDTLS_ECDH_C
+#endif
+#if defined MBEDTLS_ECDSA_C
+#define POLARSSL_ECDSA_C MBEDTLS_ECDSA_C
+#endif
+#if defined MBEDTLS_ECDSA_DETERMINISTIC
+#define POLARSSL_ECDSA_DETERMINISTIC MBEDTLS_ECDSA_DETERMINISTIC
+#endif
+#if defined MBEDTLS_ECP_C
+#define POLARSSL_ECP_C MBEDTLS_ECP_C
+#endif
+#if defined MBEDTLS_ECP_DP_BP256R1_ENABLED
+#define POLARSSL_ECP_DP_BP256R1_ENABLED MBEDTLS_ECP_DP_BP256R1_ENABLED
+#endif
+#if defined MBEDTLS_ECP_DP_BP384R1_ENABLED
+#define POLARSSL_ECP_DP_BP384R1_ENABLED MBEDTLS_ECP_DP_BP384R1_ENABLED
+#endif
+#if defined MBEDTLS_ECP_DP_BP512R1_ENABLED
+#define POLARSSL_ECP_DP_BP512R1_ENABLED MBEDTLS_ECP_DP_BP512R1_ENABLED
+#endif
+#if defined MBEDTLS_ECP_DP_CURVE25519_ENABLED
+#define POLARSSL_ECP_DP_M255_ENABLED MBEDTLS_ECP_DP_CURVE25519_ENABLED
+#endif
+#if defined MBEDTLS_ECP_DP_SECP192K1_ENABLED
+#define POLARSSL_ECP_DP_SECP192K1_ENABLED MBEDTLS_ECP_DP_SECP192K1_ENABLED
+#endif
+#if defined MBEDTLS_ECP_DP_SECP192R1_ENABLED
+#define POLARSSL_ECP_DP_SECP192R1_ENABLED MBEDTLS_ECP_DP_SECP192R1_ENABLED
+#endif
+#if defined MBEDTLS_ECP_DP_SECP224K1_ENABLED
+#define POLARSSL_ECP_DP_SECP224K1_ENABLED MBEDTLS_ECP_DP_SECP224K1_ENABLED
+#endif
+#if defined MBEDTLS_ECP_DP_SECP224R1_ENABLED
+#define POLARSSL_ECP_DP_SECP224R1_ENABLED MBEDTLS_ECP_DP_SECP224R1_ENABLED
+#endif
+#if defined MBEDTLS_ECP_DP_SECP256K1_ENABLED
+#define POLARSSL_ECP_DP_SECP256K1_ENABLED MBEDTLS_ECP_DP_SECP256K1_ENABLED
+#endif
+#if defined MBEDTLS_ECP_DP_SECP256R1_ENABLED
+#define POLARSSL_ECP_DP_SECP256R1_ENABLED MBEDTLS_ECP_DP_SECP256R1_ENABLED
+#endif
+#if defined MBEDTLS_ECP_DP_SECP384R1_ENABLED
+#define POLARSSL_ECP_DP_SECP384R1_ENABLED MBEDTLS_ECP_DP_SECP384R1_ENABLED
+#endif
+#if defined MBEDTLS_ECP_DP_SECP521R1_ENABLED
+#define POLARSSL_ECP_DP_SECP521R1_ENABLED MBEDTLS_ECP_DP_SECP521R1_ENABLED
+#endif
+#if defined MBEDTLS_ECP_FIXED_POINT_OPTIM
+#define POLARSSL_ECP_FIXED_POINT_OPTIM MBEDTLS_ECP_FIXED_POINT_OPTIM
+#endif
+#if defined MBEDTLS_ECP_MAX_BITS
+#define POLARSSL_ECP_MAX_BITS MBEDTLS_ECP_MAX_BITS
+#endif
+#if defined MBEDTLS_ECP_NIST_OPTIM
+#define POLARSSL_ECP_NIST_OPTIM MBEDTLS_ECP_NIST_OPTIM
+#endif
+#if defined MBEDTLS_ECP_WINDOW_SIZE
+#define POLARSSL_ECP_WINDOW_SIZE MBEDTLS_ECP_WINDOW_SIZE
+#endif
+#if defined MBEDTLS_ENABLE_WEAK_CIPHERSUITES
+#define POLARSSL_ENABLE_WEAK_CIPHERSUITES MBEDTLS_ENABLE_WEAK_CIPHERSUITES
+#endif
+#if defined MBEDTLS_ENTROPY_C
+#define POLARSSL_ENTROPY_C MBEDTLS_ENTROPY_C
+#endif
+#if defined MBEDTLS_ENTROPY_FORCE_SHA256
+#define POLARSSL_ENTROPY_FORCE_SHA256 MBEDTLS_ENTROPY_FORCE_SHA256
+#endif
+#if defined MBEDTLS_ERROR_C
+#define POLARSSL_ERROR_C MBEDTLS_ERROR_C
+#endif
+#if defined MBEDTLS_ERROR_STRERROR_BC
+#define POLARSSL_ERROR_STRERROR_BC MBEDTLS_ERROR_STRERROR_BC
+#endif
+#if defined MBEDTLS_ERROR_STRERROR_DUMMY
+#define POLARSSL_ERROR_STRERROR_DUMMY MBEDTLS_ERROR_STRERROR_DUMMY
+#endif
+#if defined MBEDTLS_FS_IO
+#define POLARSSL_FS_IO MBEDTLS_FS_IO
+#endif
+#if defined MBEDTLS_GCM_C
+#define POLARSSL_GCM_C MBEDTLS_GCM_C
+#endif
+#if defined MBEDTLS_GENPRIME
+#define POLARSSL_GENPRIME MBEDTLS_GENPRIME
+#endif
+#if defined MBEDTLS_HAVEGE_C
+#define POLARSSL_HAVEGE_C MBEDTLS_HAVEGE_C
+#endif
+#if defined MBEDTLS_HAVE_ASM
+#define POLARSSL_HAVE_ASM MBEDTLS_HAVE_ASM
+#endif
+#if defined MBEDTLS_HAVE_SSE2
+#define POLARSSL_HAVE_SSE2 MBEDTLS_HAVE_SSE2
+#endif
+#if defined MBEDTLS_HAVE_TIME
+#define POLARSSL_HAVE_TIME MBEDTLS_HAVE_TIME
+#endif
+#if defined MBEDTLS_HMAC_DRBG_C
+#define POLARSSL_HMAC_DRBG_C MBEDTLS_HMAC_DRBG_C
+#endif
+#if defined MBEDTLS_HMAC_DRBG_MAX_INPUT
+#define POLARSSL_HMAC_DRBG_MAX_INPUT MBEDTLS_HMAC_DRBG_MAX_INPUT
+#endif
+#if defined MBEDTLS_HMAC_DRBG_MAX_REQUEST
+#define POLARSSL_HMAC_DRBG_MAX_REQUEST MBEDTLS_HMAC_DRBG_MAX_REQUEST
+#endif
+#if defined MBEDTLS_HMAC_DRBG_MAX_SEED_INPUT
+#define POLARSSL_HMAC_DRBG_MAX_SEED_INPUT MBEDTLS_HMAC_DRBG_MAX_SEED_INPUT
+#endif
+#if defined MBEDTLS_HMAC_DRBG_RESEED_INTERVAL
+#define POLARSSL_HMAC_DRBG_RESEED_INTERVAL MBEDTLS_HMAC_DRBG_RESEED_INTERVAL
+#endif
+#if defined MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED
+#define POLARSSL_KEY_EXCHANGE_DHE_PSK_ENABLED MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED
+#endif
+#if defined MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED
+#define POLARSSL_KEY_EXCHANGE_DHE_RSA_ENABLED MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED
+#endif
+#if defined MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED
+#define POLARSSL_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED
+#endif
+#if defined MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED
+#define POLARSSL_KEY_EXCHANGE_ECDHE_PSK_ENABLED MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED
+#endif
+#if defined MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED
+#define POLARSSL_KEY_EXCHANGE_ECDHE_RSA_ENABLED MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED
+#endif
+#if defined MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED
+#define POLARSSL_KEY_EXCHANGE_ECDH_ECDSA_ENABLED MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED
+#endif
+#if defined MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED
+#define POLARSSL_KEY_EXCHANGE_ECDH_RSA_ENABLED MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED
+#endif
+#if defined MBEDTLS_KEY_EXCHANGE_PSK_ENABLED
+#define POLARSSL_KEY_EXCHANGE_PSK_ENABLED MBEDTLS_KEY_EXCHANGE_PSK_ENABLED
+#endif
+#if defined MBEDTLS_KEY_EXCHANGE_RSA_ENABLED
+#define POLARSSL_KEY_EXCHANGE_RSA_ENABLED MBEDTLS_KEY_EXCHANGE_RSA_ENABLED
+#endif
+#if defined MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED
+#define POLARSSL_KEY_EXCHANGE_RSA_PSK_ENABLED MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED
+#endif
+#if defined MBEDTLS_MD2_ALT
+#define POLARSSL_MD2_ALT MBEDTLS_MD2_ALT
+#endif
+#if defined MBEDTLS_MD2_C
+#define POLARSSL_MD2_C MBEDTLS_MD2_C
+#endif
+#if defined MBEDTLS_MD2_PROCESS_ALT
+#define POLARSSL_MD2_PROCESS_ALT MBEDTLS_MD2_PROCESS_ALT
+#endif
+#if defined MBEDTLS_MD4_ALT
+#define POLARSSL_MD4_ALT MBEDTLS_MD4_ALT
+#endif
+#if defined MBEDTLS_MD4_C
+#define POLARSSL_MD4_C MBEDTLS_MD4_C
+#endif
+#if defined MBEDTLS_MD4_PROCESS_ALT
+#define POLARSSL_MD4_PROCESS_ALT MBEDTLS_MD4_PROCESS_ALT
+#endif
+#if defined MBEDTLS_MD5_ALT
+#define POLARSSL_MD5_ALT MBEDTLS_MD5_ALT
+#endif
+#if defined MBEDTLS_MD5_C
+#define POLARSSL_MD5_C MBEDTLS_MD5_C
+#endif
+#if defined MBEDTLS_MD5_PROCESS_ALT
+#define POLARSSL_MD5_PROCESS_ALT MBEDTLS_MD5_PROCESS_ALT
+#endif
+#if defined MBEDTLS_MD_C
+#define POLARSSL_MD_C MBEDTLS_MD_C
+#endif
+#if defined MBEDTLS_MEMORY_ALIGN_MULTIPLE
+#define POLARSSL_MEMORY_ALIGN_MULTIPLE MBEDTLS_MEMORY_ALIGN_MULTIPLE
+#endif
+#if defined MBEDTLS_MEMORY_BACKTRACE
+#define POLARSSL_MEMORY_BACKTRACE MBEDTLS_MEMORY_BACKTRACE
+#endif
+#if defined MBEDTLS_MEMORY_BUFFER_ALLOC_C
+#define POLARSSL_MEMORY_BUFFER_ALLOC_C MBEDTLS_MEMORY_BUFFER_ALLOC_C
+#endif
+#if defined MBEDTLS_MEMORY_C
+#define POLARSSL_MEMORY_C MBEDTLS_MEMORY_C
+#endif
+#if defined MBEDTLS_MEMORY_DEBUG
+#define POLARSSL_MEMORY_DEBUG MBEDTLS_MEMORY_DEBUG
+#endif
+#if defined MBEDTLS_MPI_MAX_SIZE
+#define POLARSSL_MPI_MAX_SIZE MBEDTLS_MPI_MAX_SIZE
+#endif
+#if defined MBEDTLS_MPI_WINDOW_SIZE
+#define POLARSSL_MPI_WINDOW_SIZE MBEDTLS_MPI_WINDOW_SIZE
+#endif
+#if defined MBEDTLS_NET_C
+#define POLARSSL_NET_C MBEDTLS_NET_C
+#endif
+#if defined MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES
+#define POLARSSL_NO_DEFAULT_ENTROPY_SOURCES MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES
+#endif
+#if defined MBEDTLS_NO_PLATFORM_ENTROPY
+#define POLARSSL_NO_PLATFORM_ENTROPY MBEDTLS_NO_PLATFORM_ENTROPY
+#endif
+#if defined MBEDTLS_OID_C
+#define POLARSSL_OID_C MBEDTLS_OID_C
+#endif
+#if defined MBEDTLS_PADLOCK_C
+#define POLARSSL_PADLOCK_C MBEDTLS_PADLOCK_C
+#endif
+#if defined MBEDTLS_PBKDF2_C
+#define POLARSSL_PBKDF2_C MBEDTLS_PBKDF2_C
+#endif
+#if defined MBEDTLS_PEM_PARSE_C
+#define POLARSSL_PEM_PARSE_C MBEDTLS_PEM_PARSE_C
+#endif
+#if defined MBEDTLS_PEM_WRITE_C
+#define POLARSSL_PEM_WRITE_C MBEDTLS_PEM_WRITE_C
+#endif
+#if defined MBEDTLS_PKCS11_C
+#define POLARSSL_PKCS11_C MBEDTLS_PKCS11_C
+#endif
+#if defined MBEDTLS_PKCS12_C
+#define POLARSSL_PKCS12_C MBEDTLS_PKCS12_C
+#endif
+#if defined MBEDTLS_PKCS1_V15
+#define POLARSSL_PKCS1_V15 MBEDTLS_PKCS1_V15
+#endif
+#if defined MBEDTLS_PKCS1_V21
+#define POLARSSL_PKCS1_V21 MBEDTLS_PKCS1_V21
+#endif
+#if defined MBEDTLS_PKCS5_C
+#define POLARSSL_PKCS5_C MBEDTLS_PKCS5_C
+#endif
+#if defined MBEDTLS_PK_C
+#define POLARSSL_PK_C MBEDTLS_PK_C
+#endif
+#if defined MBEDTLS_PK_PARSE_C
+#define POLARSSL_PK_PARSE_C MBEDTLS_PK_PARSE_C
+#endif
+#if defined MBEDTLS_PK_PARSE_EC_EXTENDED
+#define POLARSSL_PK_PARSE_EC_EXTENDED MBEDTLS_PK_PARSE_EC_EXTENDED
+#endif
+#if defined MBEDTLS_PK_RSA_ALT_SUPPORT
+#define POLARSSL_PK_RSA_ALT_SUPPORT MBEDTLS_PK_RSA_ALT_SUPPORT
+#endif
+#if defined MBEDTLS_PK_WRITE_C
+#define POLARSSL_PK_WRITE_C MBEDTLS_PK_WRITE_C
+#endif
+#if defined MBEDTLS_PLATFORM_C
+#define POLARSSL_PLATFORM_C MBEDTLS_PLATFORM_C
+#endif
+#if defined MBEDTLS_PLATFORM_EXIT_ALT
+#define POLARSSL_PLATFORM_EXIT_ALT MBEDTLS_PLATFORM_EXIT_ALT
+#endif
+#if defined MBEDTLS_PLATFORM_EXIT_MACRO
+#define POLARSSL_PLATFORM_EXIT_MACRO MBEDTLS_PLATFORM_EXIT_MACRO
+#endif
+#if defined MBEDTLS_PLATFORM_FPRINTF_ALT
+#define POLARSSL_PLATFORM_FPRINTF_ALT MBEDTLS_PLATFORM_FPRINTF_ALT
+#endif
+#if defined MBEDTLS_PLATFORM_FPRINTF_MACRO
+#define POLARSSL_PLATFORM_FPRINTF_MACRO MBEDTLS_PLATFORM_FPRINTF_MACRO
+#endif
+#if defined MBEDTLS_PLATFORM_FREE_MACRO
+#define POLARSSL_PLATFORM_FREE_MACRO MBEDTLS_PLATFORM_FREE_MACRO
+#endif
+#if defined MBEDTLS_PLATFORM_MEMORY
+#define POLARSSL_PLATFORM_MEMORY MBEDTLS_PLATFORM_MEMORY
+#endif
+#if defined MBEDTLS_PLATFORM_NO_STD_FUNCTIONS
+#define POLARSSL_PLATFORM_NO_STD_FUNCTIONS MBEDTLS_PLATFORM_NO_STD_FUNCTIONS
+#endif
+#if defined MBEDTLS_PLATFORM_PRINTF_ALT
+#define POLARSSL_PLATFORM_PRINTF_ALT MBEDTLS_PLATFORM_PRINTF_ALT
+#endif
+#if defined MBEDTLS_PLATFORM_PRINTF_MACRO
+#define POLARSSL_PLATFORM_PRINTF_MACRO MBEDTLS_PLATFORM_PRINTF_MACRO
+#endif
+#if defined MBEDTLS_PLATFORM_SNPRINTF_ALT
+#define POLARSSL_PLATFORM_SNPRINTF_ALT MBEDTLS_PLATFORM_SNPRINTF_ALT
+#endif
+#if defined MBEDTLS_PLATFORM_SNPRINTF_MACRO
+#define POLARSSL_PLATFORM_SNPRINTF_MACRO MBEDTLS_PLATFORM_SNPRINTF_MACRO
+#endif
+#if defined MBEDTLS_PLATFORM_STD_EXIT
+#define POLARSSL_PLATFORM_STD_EXIT MBEDTLS_PLATFORM_STD_EXIT
+#endif
+#if defined MBEDTLS_PLATFORM_STD_FPRINTF
+#define POLARSSL_PLATFORM_STD_FPRINTF MBEDTLS_PLATFORM_STD_FPRINTF
+#endif
+#if defined MBEDTLS_PLATFORM_STD_FREE
+#define POLARSSL_PLATFORM_STD_FREE MBEDTLS_PLATFORM_STD_FREE
+#endif
+#if defined MBEDTLS_PLATFORM_STD_MALLOC
+#define POLARSSL_PLATFORM_STD_MALLOC MBEDTLS_PLATFORM_STD_MALLOC
+#endif
+#if defined MBEDTLS_PLATFORM_STD_MEM_HDR
+#define POLARSSL_PLATFORM_STD_MEM_HDR MBEDTLS_PLATFORM_STD_MEM_HDR
+#endif
+#if defined MBEDTLS_PLATFORM_STD_PRINTF
+#define POLARSSL_PLATFORM_STD_PRINTF MBEDTLS_PLATFORM_STD_PRINTF
+#endif
+#if defined MBEDTLS_PLATFORM_STD_SNPRINTF
+#define POLARSSL_PLATFORM_STD_SNPRINTF MBEDTLS_PLATFORM_STD_SNPRINTF
+#endif
+#if defined MBEDTLS_PSK_MAX_LEN
+#define POLARSSL_PSK_MAX_LEN MBEDTLS_PSK_MAX_LEN
+#endif
+#if defined MBEDTLS_REMOVE_ARC4_CIPHERSUITES
+#define POLARSSL_REMOVE_ARC4_CIPHERSUITES MBEDTLS_REMOVE_ARC4_CIPHERSUITES
+#endif
+#if defined MBEDTLS_RIPEMD160_ALT
+#define POLARSSL_RIPEMD160_ALT MBEDTLS_RIPEMD160_ALT
+#endif
+#if defined MBEDTLS_RIPEMD160_C
+#define POLARSSL_RIPEMD160_C MBEDTLS_RIPEMD160_C
+#endif
+#if defined MBEDTLS_RIPEMD160_PROCESS_ALT
+#define POLARSSL_RIPEMD160_PROCESS_ALT MBEDTLS_RIPEMD160_PROCESS_ALT
+#endif
+#if defined MBEDTLS_RSA_C
+#define POLARSSL_RSA_C MBEDTLS_RSA_C
+#endif
+#if defined MBEDTLS_RSA_NO_CRT
+#define POLARSSL_RSA_NO_CRT MBEDTLS_RSA_NO_CRT
+#endif
+#if defined MBEDTLS_SELF_TEST
+#define POLARSSL_SELF_TEST MBEDTLS_SELF_TEST
+#endif
+#if defined MBEDTLS_SHA1_ALT
+#define POLARSSL_SHA1_ALT MBEDTLS_SHA1_ALT
+#endif
+#if defined MBEDTLS_SHA1_C
+#define POLARSSL_SHA1_C MBEDTLS_SHA1_C
+#endif
+#if defined MBEDTLS_SHA1_PROCESS_ALT
+#define POLARSSL_SHA1_PROCESS_ALT MBEDTLS_SHA1_PROCESS_ALT
+#endif
+#if defined MBEDTLS_SHA256_ALT
+#define POLARSSL_SHA256_ALT MBEDTLS_SHA256_ALT
+#endif
+#if defined MBEDTLS_SHA256_C
+#define POLARSSL_SHA256_C MBEDTLS_SHA256_C
+#endif
+#if defined MBEDTLS_SHA256_PROCESS_ALT
+#define POLARSSL_SHA256_PROCESS_ALT MBEDTLS_SHA256_PROCESS_ALT
+#endif
+#if defined MBEDTLS_SHA512_ALT
+#define POLARSSL_SHA512_ALT MBEDTLS_SHA512_ALT
+#endif
+#if defined MBEDTLS_SHA512_C
+#define POLARSSL_SHA512_C MBEDTLS_SHA512_C
+#endif
+#if defined MBEDTLS_SHA512_PROCESS_ALT
+#define POLARSSL_SHA512_PROCESS_ALT MBEDTLS_SHA512_PROCESS_ALT
+#endif
+#if defined MBEDTLS_SSL_AEAD_RANDOM_IV
+#define POLARSSL_SSL_AEAD_RANDOM_IV MBEDTLS_SSL_AEAD_RANDOM_IV
+#endif
+#if defined MBEDTLS_SSL_ALERT_MESSAGES
+#define POLARSSL_SSL_ALERT_MESSAGES MBEDTLS_SSL_ALERT_MESSAGES
+#endif
+#if defined MBEDTLS_SSL_ALL_ALERT_MESSAGES
+#define POLARSSL_SSL_ALL_ALERT_MESSAGES MBEDTLS_SSL_ALL_ALERT_MESSAGES
+#endif
+#if defined MBEDTLS_SSL_ALPN
+#define POLARSSL_SSL_ALPN MBEDTLS_SSL_ALPN
+#endif
+#if defined MBEDTLS_SSL_CACHE_C
+#define POLARSSL_SSL_CACHE_C MBEDTLS_SSL_CACHE_C
+#endif
+#if defined MBEDTLS_SSL_CBC_RECORD_SPLITTING
+#define POLARSSL_SSL_CBC_RECORD_SPLITTING MBEDTLS_SSL_CBC_RECORD_SPLITTING
+#endif
+#if defined MBEDTLS_SSL_CLI_C
+#define POLARSSL_SSL_CLI_C MBEDTLS_SSL_CLI_C
+#endif
+#if defined MBEDTLS_SSL_COOKIE_C
+#define POLARSSL_SSL_COOKIE_C MBEDTLS_SSL_COOKIE_C
+#endif
+#if defined MBEDTLS_SSL_COOKIE_TIMEOUT
+#define POLARSSL_SSL_COOKIE_TIMEOUT MBEDTLS_SSL_COOKIE_TIMEOUT
+#endif
+#if defined MBEDTLS_SSL_DEBUG_ALL
+#define POLARSSL_SSL_DEBUG_ALL MBEDTLS_SSL_DEBUG_ALL
+#endif
+#if defined MBEDTLS_SSL_DISABLE_RENEGOTIATION
+#define POLARSSL_SSL_DISABLE_RENEGOTIATION MBEDTLS_SSL_DISABLE_RENEGOTIATION
+#endif
+#if defined MBEDTLS_SSL_DTLS_ANTI_REPLAY
+#define POLARSSL_SSL_DTLS_ANTI_REPLAY MBEDTLS_SSL_DTLS_ANTI_REPLAY
+#endif
+#if defined MBEDTLS_SSL_DTLS_BADMAC_LIMIT
+#define POLARSSL_SSL_DTLS_BADMAC_LIMIT MBEDTLS_SSL_DTLS_BADMAC_LIMIT
+#endif
+#if defined MBEDTLS_SSL_DTLS_HELLO_VERIFY
+#define POLARSSL_SSL_DTLS_HELLO_VERIFY MBEDTLS_SSL_DTLS_HELLO_VERIFY
+#endif
+#if defined MBEDTLS_SSL_ENCRYPT_THEN_MAC
+#define POLARSSL_SSL_ENCRYPT_THEN_MAC MBEDTLS_SSL_ENCRYPT_THEN_MAC
+#endif
+#if defined MBEDTLS_SSL_EXTENDED_MASTER_SECRET
+#define POLARSSL_SSL_EXTENDED_MASTER_SECRET MBEDTLS_SSL_EXTENDED_MASTER_SECRET
+#endif
+#if defined MBEDTLS_SSL_FALLBACK_SCSV
+#define POLARSSL_SSL_FALLBACK_SCSV MBEDTLS_SSL_FALLBACK_SCSV
+#endif
+#if defined MBEDTLS_SSL_HW_RECORD_ACCEL
+#define POLARSSL_SSL_HW_RECORD_ACCEL MBEDTLS_SSL_HW_RECORD_ACCEL
+#endif
+#if defined MBEDTLS_SSL_MAX_FRAGMENT_LENGTH
+#define POLARSSL_SSL_MAX_FRAGMENT_LENGTH MBEDTLS_SSL_MAX_FRAGMENT_LENGTH
+#endif
+#if defined MBEDTLS_SSL_PROTO_DTLS
+#define POLARSSL_SSL_PROTO_DTLS MBEDTLS_SSL_PROTO_DTLS
+#endif
+#if defined MBEDTLS_SSL_PROTO_SSL3
+#define POLARSSL_SSL_PROTO_SSL3 MBEDTLS_SSL_PROTO_SSL3
+#endif
+#if defined MBEDTLS_SSL_PROTO_TLS1
+#define POLARSSL_SSL_PROTO_TLS1 MBEDTLS_SSL_PROTO_TLS1
+#endif
+#if defined MBEDTLS_SSL_PROTO_TLS1_1
+#define POLARSSL_SSL_PROTO_TLS1_1 MBEDTLS_SSL_PROTO_TLS1_1
+#endif
+#if defined MBEDTLS_SSL_PROTO_TLS1_2
+#define POLARSSL_SSL_PROTO_TLS1_2 MBEDTLS_SSL_PROTO_TLS1_2
+#endif
+#if defined MBEDTLS_SSL_RENEGOTIATION
+#define POLARSSL_SSL_RENEGOTIATION MBEDTLS_SSL_RENEGOTIATION
+#endif
+#if defined MBEDTLS_SSL_SERVER_NAME_INDICATION
+#define POLARSSL_SSL_SERVER_NAME_INDICATION MBEDTLS_SSL_SERVER_NAME_INDICATION
+#endif
+#if defined MBEDTLS_SSL_SESSION_TICKETS
+#define POLARSSL_SSL_SESSION_TICKETS MBEDTLS_SSL_SESSION_TICKETS
+#endif
+#if defined MBEDTLS_SSL_SRV_C
+#define POLARSSL_SSL_SRV_C MBEDTLS_SSL_SRV_C
+#endif
+#if defined MBEDTLS_SSL_SRV_RESPECT_CLIENT_PREFERENCE
+#define POLARSSL_SSL_SRV_RESPECT_CLIENT_PREFERENCE MBEDTLS_SSL_SRV_RESPECT_CLIENT_PREFERENCE
+#endif
+#if defined MBEDTLS_SSL_SRV_SUPPORT_SSLV2_CLIENT_HELLO
+#define POLARSSL_SSL_SRV_SUPPORT_SSLV2_CLIENT_HELLO MBEDTLS_SSL_SRV_SUPPORT_SSLV2_CLIENT_HELLO
+#endif
+#if defined MBEDTLS_SSL_TLS_C
+#define POLARSSL_SSL_TLS_C MBEDTLS_SSL_TLS_C
+#endif
+#if defined MBEDTLS_SSL_TRUNCATED_HMAC
+#define POLARSSL_SSL_TRUNCATED_HMAC MBEDTLS_SSL_TRUNCATED_HMAC
+#endif
+#if defined MBEDTLS_THREADING_ALT
+#define POLARSSL_THREADING_ALT MBEDTLS_THREADING_ALT
+#endif
+#if defined MBEDTLS_THREADING_C
+#define POLARSSL_THREADING_C MBEDTLS_THREADING_C
+#endif
+#if defined MBEDTLS_THREADING_PTHREAD
+#define POLARSSL_THREADING_PTHREAD MBEDTLS_THREADING_PTHREAD
+#endif
+#if defined MBEDTLS_TIMING_ALT
+#define POLARSSL_TIMING_ALT MBEDTLS_TIMING_ALT
+#endif
+#if defined MBEDTLS_TIMING_C
+#define POLARSSL_TIMING_C MBEDTLS_TIMING_C
+#endif
+#if defined MBEDTLS_VERSION_C
+#define POLARSSL_VERSION_C MBEDTLS_VERSION_C
+#endif
+#if defined MBEDTLS_VERSION_FEATURES
+#define POLARSSL_VERSION_FEATURES MBEDTLS_VERSION_FEATURES
+#endif
+#if defined MBEDTLS_X509_ALLOW_EXTENSIONS_NON_V3
+#define POLARSSL_X509_ALLOW_EXTENSIONS_NON_V3 MBEDTLS_X509_ALLOW_EXTENSIONS_NON_V3
+#endif
+#if defined MBEDTLS_X509_ALLOW_UNSUPPORTED_CRITICAL_EXTENSION
+#define POLARSSL_X509_ALLOW_UNSUPPORTED_CRITICAL_EXTENSION MBEDTLS_X509_ALLOW_UNSUPPORTED_CRITICAL_EXTENSION
+#endif
+#if defined MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE
+#define POLARSSL_X509_CHECK_EXTENDED_KEY_USAGE MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE
+#endif
+#if defined MBEDTLS_X509_CHECK_KEY_USAGE
+#define POLARSSL_X509_CHECK_KEY_USAGE MBEDTLS_X509_CHECK_KEY_USAGE
+#endif
+#if defined MBEDTLS_X509_CREATE_C
+#define POLARSSL_X509_CREATE_C MBEDTLS_X509_CREATE_C
+#endif
+#if defined MBEDTLS_X509_CRL_PARSE_C
+#define POLARSSL_X509_CRL_PARSE_C MBEDTLS_X509_CRL_PARSE_C
+#endif
+#if defined MBEDTLS_X509_CRT_PARSE_C
+#define POLARSSL_X509_CRT_PARSE_C MBEDTLS_X509_CRT_PARSE_C
+#endif
+#if defined MBEDTLS_X509_CRT_WRITE_C
+#define POLARSSL_X509_CRT_WRITE_C MBEDTLS_X509_CRT_WRITE_C
+#endif
+#if defined MBEDTLS_X509_CSR_PARSE_C
+#define POLARSSL_X509_CSR_PARSE_C MBEDTLS_X509_CSR_PARSE_C
+#endif
+#if defined MBEDTLS_X509_CSR_WRITE_C
+#define POLARSSL_X509_CSR_WRITE_C MBEDTLS_X509_CSR_WRITE_C
+#endif
+#if defined MBEDTLS_X509_MAX_INTERMEDIATE_CA
+#define POLARSSL_X509_MAX_INTERMEDIATE_CA MBEDTLS_X509_MAX_INTERMEDIATE_CA
+#endif
+#if defined MBEDTLS_X509_RSASSA_PSS_SUPPORT
+#define POLARSSL_X509_RSASSA_PSS_SUPPORT MBEDTLS_X509_RSASSA_PSS_SUPPORT
+#endif
+#if defined MBEDTLS_X509_USE_C
+#define POLARSSL_X509_USE_C MBEDTLS_X509_USE_C
+#endif
+#if defined MBEDTLS_XTEA_ALT
+#define POLARSSL_XTEA_ALT MBEDTLS_XTEA_ALT
+#endif
+#if defined MBEDTLS_XTEA_C
+#define POLARSSL_XTEA_C MBEDTLS_XTEA_C
+#endif
+#if defined MBEDTLS_ZLIB_SUPPORT
+#define POLARSSL_ZLIB_SUPPORT MBEDTLS_ZLIB_SUPPORT
+#endif
+
+/*
+ * Misc names (macros, types, functions, enum constants...)
+ */
+#define AES_DECRYPT MBEDTLS_AES_DECRYPT
+#define AES_ENCRYPT MBEDTLS_AES_ENCRYPT
+#define ASN1_BIT_STRING MBEDTLS_ASN1_BIT_STRING
+#define ASN1_BMP_STRING MBEDTLS_ASN1_BMP_STRING
+#define ASN1_BOOLEAN MBEDTLS_ASN1_BOOLEAN
+#define ASN1_CHK_ADD MBEDTLS_ASN1_CHK_ADD
+#define ASN1_CONSTRUCTED MBEDTLS_ASN1_CONSTRUCTED
+#define ASN1_CONTEXT_SPECIFIC MBEDTLS_ASN1_CONTEXT_SPECIFIC
+#define ASN1_GENERALIZED_TIME MBEDTLS_ASN1_GENERALIZED_TIME
+#define ASN1_IA5_STRING MBEDTLS_ASN1_IA5_STRING
+#define ASN1_INTEGER MBEDTLS_ASN1_INTEGER
+#define ASN1_NULL MBEDTLS_ASN1_NULL
+#define ASN1_OCTET_STRING MBEDTLS_ASN1_OCTET_STRING
+#define ASN1_OID MBEDTLS_ASN1_OID
+#define ASN1_PRIMITIVE MBEDTLS_ASN1_PRIMITIVE
+#define ASN1_PRINTABLE_STRING MBEDTLS_ASN1_PRINTABLE_STRING
+#define ASN1_SEQUENCE MBEDTLS_ASN1_SEQUENCE
+#define ASN1_SET MBEDTLS_ASN1_SET
+#define ASN1_T61_STRING MBEDTLS_ASN1_T61_STRING
+#define ASN1_UNIVERSAL_STRING MBEDTLS_ASN1_UNIVERSAL_STRING
+#define ASN1_UTC_TIME MBEDTLS_ASN1_UTC_TIME
+#define ASN1_UTF8_STRING MBEDTLS_ASN1_UTF8_STRING
+#define BADCERT_CN_MISMATCH MBEDTLS_X509_BADCERT_CN_MISMATCH
+#define BADCERT_EXPIRED MBEDTLS_X509_BADCERT_EXPIRED
+#define BADCERT_FUTURE MBEDTLS_X509_BADCERT_FUTURE
+#define BADCERT_MISSING MBEDTLS_X509_BADCERT_MISSING
+#define BADCERT_NOT_TRUSTED MBEDTLS_X509_BADCERT_NOT_TRUSTED
+#define BADCERT_OTHER MBEDTLS_X509_BADCERT_OTHER
+#define BADCERT_REVOKED MBEDTLS_X509_BADCERT_REVOKED
+#define BADCERT_SKIP_VERIFY MBEDTLS_X509_BADCERT_SKIP_VERIFY
+#define BADCRL_EXPIRED MBEDTLS_X509_BADCRL_EXPIRED
+#define BADCRL_FUTURE MBEDTLS_X509_BADCRL_FUTURE
+#define BADCRL_NOT_TRUSTED MBEDTLS_X509_BADCRL_NOT_TRUSTED
+#define BLOWFISH_BLOCKSIZE MBEDTLS_BLOWFISH_BLOCKSIZE
+#define BLOWFISH_DECRYPT MBEDTLS_BLOWFISH_DECRYPT
+#define BLOWFISH_ENCRYPT MBEDTLS_BLOWFISH_ENCRYPT
+#define BLOWFISH_MAX_KEY MBEDTLS_BLOWFISH_MAX_KEY_BITS
+#define BLOWFISH_MIN_KEY MBEDTLS_BLOWFISH_MIN_KEY_BITS
+#define BLOWFISH_ROUNDS MBEDTLS_BLOWFISH_ROUNDS
+#define CAMELLIA_DECRYPT MBEDTLS_CAMELLIA_DECRYPT
+#define CAMELLIA_ENCRYPT MBEDTLS_CAMELLIA_ENCRYPT
+#define COLLECT_SIZE MBEDTLS_HAVEGE_COLLECT_SIZE
+#define CTR_DRBG_BLOCKSIZE MBEDTLS_CTR_DRBG_BLOCKSIZE
+#define CTR_DRBG_ENTROPY_LEN MBEDTLS_CTR_DRBG_ENTROPY_LEN
+#define CTR_DRBG_KEYBITS MBEDTLS_CTR_DRBG_KEYBITS
+#define CTR_DRBG_KEYSIZE MBEDTLS_CTR_DRBG_KEYSIZE
+#define CTR_DRBG_MAX_INPUT MBEDTLS_CTR_DRBG_MAX_INPUT
+#define CTR_DRBG_MAX_REQUEST MBEDTLS_CTR_DRBG_MAX_REQUEST
+#define CTR_DRBG_MAX_SEED_INPUT MBEDTLS_CTR_DRBG_MAX_SEED_INPUT
+#define CTR_DRBG_PR_OFF MBEDTLS_CTR_DRBG_PR_OFF
+#define CTR_DRBG_PR_ON MBEDTLS_CTR_DRBG_PR_ON
+#define CTR_DRBG_RESEED_INTERVAL MBEDTLS_CTR_DRBG_RESEED_INTERVAL
+#define CTR_DRBG_SEEDLEN MBEDTLS_CTR_DRBG_SEEDLEN
+#define DEPRECATED MBEDTLS_DEPRECATED
+#define DES_DECRYPT MBEDTLS_DES_DECRYPT
+#define DES_ENCRYPT MBEDTLS_DES_ENCRYPT
+#define DES_KEY_SIZE MBEDTLS_DES_KEY_SIZE
+#define ENTROPY_BLOCK_SIZE MBEDTLS_ENTROPY_BLOCK_SIZE
+#define ENTROPY_MAX_GATHER MBEDTLS_ENTROPY_MAX_GATHER
+#define ENTROPY_MAX_SEED_SIZE MBEDTLS_ENTROPY_MAX_SEED_SIZE
+#define ENTROPY_MAX_SOURCES MBEDTLS_ENTROPY_MAX_SOURCES
+#define ENTROPY_MIN_HARDCLOCK MBEDTLS_ENTROPY_MIN_HARDCLOCK
+#define ENTROPY_MIN_HAVEGE MBEDTLS_ENTROPY_MIN_HAVEGE
+#define ENTROPY_MIN_PLATFORM MBEDTLS_ENTROPY_MIN_PLATFORM
+#define ENTROPY_SOURCE_MANUAL MBEDTLS_ENTROPY_SOURCE_MANUAL
+#define EXT_AUTHORITY_KEY_IDENTIFIER MBEDTLS_X509_EXT_AUTHORITY_KEY_IDENTIFIER
+#define EXT_BASIC_CONSTRAINTS MBEDTLS_X509_EXT_BASIC_CONSTRAINTS
+#define EXT_CERTIFICATE_POLICIES MBEDTLS_X509_EXT_CERTIFICATE_POLICIES
+#define EXT_CRL_DISTRIBUTION_POINTS MBEDTLS_X509_EXT_CRL_DISTRIBUTION_POINTS
+#define EXT_EXTENDED_KEY_USAGE MBEDTLS_X509_EXT_EXTENDED_KEY_USAGE
+#define EXT_FRESHEST_CRL MBEDTLS_X509_EXT_FRESHEST_CRL
+#define EXT_INIHIBIT_ANYPOLICY MBEDTLS_X509_EXT_INIHIBIT_ANYPOLICY
+#define EXT_ISSUER_ALT_NAME MBEDTLS_X509_EXT_ISSUER_ALT_NAME
+#define EXT_KEY_USAGE MBEDTLS_X509_EXT_KEY_USAGE
+#define EXT_NAME_CONSTRAINTS MBEDTLS_X509_EXT_NAME_CONSTRAINTS
+#define EXT_NS_CERT_TYPE MBEDTLS_X509_EXT_NS_CERT_TYPE
+#define EXT_POLICY_CONSTRAINTS MBEDTLS_X509_EXT_POLICY_CONSTRAINTS
+#define EXT_POLICY_MAPPINGS MBEDTLS_X509_EXT_POLICY_MAPPINGS
+#define EXT_SUBJECT_ALT_NAME MBEDTLS_X509_EXT_SUBJECT_ALT_NAME
+#define EXT_SUBJECT_DIRECTORY_ATTRS MBEDTLS_X509_EXT_SUBJECT_DIRECTORY_ATTRS
+#define EXT_SUBJECT_KEY_IDENTIFIER MBEDTLS_X509_EXT_SUBJECT_KEY_IDENTIFIER
+#define GCM_DECRYPT MBEDTLS_GCM_DECRYPT
+#define GCM_ENCRYPT MBEDTLS_GCM_ENCRYPT
+#define KU_CRL_SIGN MBEDTLS_X509_KU_CRL_SIGN
+#define KU_DATA_ENCIPHERMENT MBEDTLS_X509_KU_DATA_ENCIPHERMENT
+#define KU_DIGITAL_SIGNATURE MBEDTLS_X509_KU_DIGITAL_SIGNATURE
+#define KU_KEY_AGREEMENT MBEDTLS_X509_KU_KEY_AGREEMENT
+#define KU_KEY_CERT_SIGN MBEDTLS_X509_KU_KEY_CERT_SIGN
+#define KU_KEY_ENCIPHERMENT MBEDTLS_X509_KU_KEY_ENCIPHERMENT
+#define KU_NON_REPUDIATION MBEDTLS_X509_KU_NON_REPUDIATION
+#define LN_2_DIV_LN_10_SCALE100 MBEDTLS_LN_2_DIV_LN_10_SCALE100
+#define MD_CONTEXT_T_INIT MBEDTLS_MD_CONTEXT_T_INIT
+#define MEMORY_VERIFY_ALLOC MBEDTLS_MEMORY_VERIFY_ALLOC
+#define MEMORY_VERIFY_ALWAYS MBEDTLS_MEMORY_VERIFY_ALWAYS
+#define MEMORY_VERIFY_FREE MBEDTLS_MEMORY_VERIFY_FREE
+#define MEMORY_VERIFY_NONE MBEDTLS_MEMORY_VERIFY_NONE
+#define MPI_CHK MBEDTLS_MPI_CHK
+#define NET_PROTO_TCP MBEDTLS_NET_PROTO_TCP
+#define NET_PROTO_UDP MBEDTLS_NET_PROTO_UDP
+#define NS_CERT_TYPE_EMAIL MBEDTLS_X509_NS_CERT_TYPE_EMAIL
+#define NS_CERT_TYPE_EMAIL_CA MBEDTLS_X509_NS_CERT_TYPE_EMAIL_CA
+#define NS_CERT_TYPE_OBJECT_SIGNING MBEDTLS_X509_NS_CERT_TYPE_OBJECT_SIGNING
+#define NS_CERT_TYPE_OBJECT_SIGNING_CA MBEDTLS_X509_NS_CERT_TYPE_OBJECT_SIGNING_CA
+#define NS_CERT_TYPE_RESERVED MBEDTLS_X509_NS_CERT_TYPE_RESERVED
+#define NS_CERT_TYPE_SSL_CA MBEDTLS_X509_NS_CERT_TYPE_SSL_CA
+#define NS_CERT_TYPE_SSL_CLIENT MBEDTLS_X509_NS_CERT_TYPE_SSL_CLIENT
+#define NS_CERT_TYPE_SSL_SERVER MBEDTLS_X509_NS_CERT_TYPE_SSL_SERVER
+#define OID_ANSI_X9_62 MBEDTLS_OID_ANSI_X9_62
+#define OID_ANSI_X9_62_FIELD_TYPE MBEDTLS_OID_ANSI_X9_62_FIELD_TYPE
+#define OID_ANSI_X9_62_PRIME_FIELD MBEDTLS_OID_ANSI_X9_62_PRIME_FIELD
+#define OID_ANSI_X9_62_SIG MBEDTLS_OID_ANSI_X9_62_SIG
+#define OID_ANSI_X9_62_SIG_SHA2 MBEDTLS_OID_ANSI_X9_62_SIG_SHA2
+#define OID_ANY_EXTENDED_KEY_USAGE MBEDTLS_OID_ANY_EXTENDED_KEY_USAGE
+#define OID_AT MBEDTLS_OID_AT
+#define OID_AT_CN MBEDTLS_OID_AT_CN
+#define OID_AT_COUNTRY MBEDTLS_OID_AT_COUNTRY
+#define OID_AT_DN_QUALIFIER MBEDTLS_OID_AT_DN_QUALIFIER
+#define OID_AT_GENERATION_QUALIFIER MBEDTLS_OID_AT_GENERATION_QUALIFIER
+#define OID_AT_GIVEN_NAME MBEDTLS_OID_AT_GIVEN_NAME
+#define OID_AT_INITIALS MBEDTLS_OID_AT_INITIALS
+#define OID_AT_LOCALITY MBEDTLS_OID_AT_LOCALITY
+#define OID_AT_ORGANIZATION MBEDTLS_OID_AT_ORGANIZATION
+#define OID_AT_ORG_UNIT MBEDTLS_OID_AT_ORG_UNIT
+#define OID_AT_POSTAL_ADDRESS MBEDTLS_OID_AT_POSTAL_ADDRESS
+#define OID_AT_POSTAL_CODE MBEDTLS_OID_AT_POSTAL_CODE
+#define OID_AT_PSEUDONYM MBEDTLS_OID_AT_PSEUDONYM
+#define OID_AT_SERIAL_NUMBER MBEDTLS_OID_AT_SERIAL_NUMBER
+#define OID_AT_STATE MBEDTLS_OID_AT_STATE
+#define OID_AT_SUR_NAME MBEDTLS_OID_AT_SUR_NAME
+#define OID_AT_TITLE MBEDTLS_OID_AT_TITLE
+#define OID_AT_UNIQUE_IDENTIFIER MBEDTLS_OID_AT_UNIQUE_IDENTIFIER
+#define OID_AUTHORITY_KEY_IDENTIFIER MBEDTLS_OID_AUTHORITY_KEY_IDENTIFIER
+#define OID_BASIC_CONSTRAINTS MBEDTLS_OID_BASIC_CONSTRAINTS
+#define OID_CERTICOM MBEDTLS_OID_CERTICOM
+#define OID_CERTIFICATE_POLICIES MBEDTLS_OID_CERTIFICATE_POLICIES
+#define OID_CLIENT_AUTH MBEDTLS_OID_CLIENT_AUTH
+#define OID_CMP MBEDTLS_OID_CMP
+#define OID_CODE_SIGNING MBEDTLS_OID_CODE_SIGNING
+#define OID_COUNTRY_US MBEDTLS_OID_COUNTRY_US
+#define OID_CRL_DISTRIBUTION_POINTS MBEDTLS_OID_CRL_DISTRIBUTION_POINTS
+#define OID_CRL_NUMBER MBEDTLS_OID_CRL_NUMBER
+#define OID_DES_CBC MBEDTLS_OID_DES_CBC
+#define OID_DES_EDE3_CBC MBEDTLS_OID_DES_EDE3_CBC
+#define OID_DIGEST_ALG_MD2 MBEDTLS_OID_DIGEST_ALG_MD2
+#define OID_DIGEST_ALG_MD4 MBEDTLS_OID_DIGEST_ALG_MD4
+#define OID_DIGEST_ALG_MD5 MBEDTLS_OID_DIGEST_ALG_MD5
+#define OID_DIGEST_ALG_SHA1 MBEDTLS_OID_DIGEST_ALG_SHA1
+#define OID_DIGEST_ALG_SHA224 MBEDTLS_OID_DIGEST_ALG_SHA224
+#define OID_DIGEST_ALG_SHA256 MBEDTLS_OID_DIGEST_ALG_SHA256
+#define OID_DIGEST_ALG_SHA384 MBEDTLS_OID_DIGEST_ALG_SHA384
+#define OID_DIGEST_ALG_SHA512 MBEDTLS_OID_DIGEST_ALG_SHA512
+#define OID_DOMAIN_COMPONENT MBEDTLS_OID_DOMAIN_COMPONENT
+#define OID_ECDSA_SHA1 MBEDTLS_OID_ECDSA_SHA1
+#define OID_ECDSA_SHA224 MBEDTLS_OID_ECDSA_SHA224
+#define OID_ECDSA_SHA256 MBEDTLS_OID_ECDSA_SHA256
+#define OID_ECDSA_SHA384 MBEDTLS_OID_ECDSA_SHA384
+#define OID_ECDSA_SHA512 MBEDTLS_OID_ECDSA_SHA512
+#define OID_EC_ALG_ECDH MBEDTLS_OID_EC_ALG_ECDH
+#define OID_EC_ALG_UNRESTRICTED MBEDTLS_OID_EC_ALG_UNRESTRICTED
+#define OID_EC_BRAINPOOL_V1 MBEDTLS_OID_EC_BRAINPOOL_V1
+#define OID_EC_GRP_BP256R1 MBEDTLS_OID_EC_GRP_BP256R1
+#define OID_EC_GRP_BP384R1 MBEDTLS_OID_EC_GRP_BP384R1
+#define OID_EC_GRP_BP512R1 MBEDTLS_OID_EC_GRP_BP512R1
+#define OID_EC_GRP_SECP192K1 MBEDTLS_OID_EC_GRP_SECP192K1
+#define OID_EC_GRP_SECP192R1 MBEDTLS_OID_EC_GRP_SECP192R1
+#define OID_EC_GRP_SECP224K1 MBEDTLS_OID_EC_GRP_SECP224K1
+#define OID_EC_GRP_SECP224R1 MBEDTLS_OID_EC_GRP_SECP224R1
+#define OID_EC_GRP_SECP256K1 MBEDTLS_OID_EC_GRP_SECP256K1
+#define OID_EC_GRP_SECP256R1 MBEDTLS_OID_EC_GRP_SECP256R1
+#define OID_EC_GRP_SECP384R1 MBEDTLS_OID_EC_GRP_SECP384R1
+#define OID_EC_GRP_SECP521R1 MBEDTLS_OID_EC_GRP_SECP521R1
+#define OID_EMAIL_PROTECTION MBEDTLS_OID_EMAIL_PROTECTION
+#define OID_EXTENDED_KEY_USAGE MBEDTLS_OID_EXTENDED_KEY_USAGE
+#define OID_FRESHEST_CRL MBEDTLS_OID_FRESHEST_CRL
+#define OID_GOV MBEDTLS_OID_GOV
+#define OID_HMAC_SHA1 MBEDTLS_OID_HMAC_SHA1
+#define OID_ID_CE MBEDTLS_OID_ID_CE
+#define OID_INIHIBIT_ANYPOLICY MBEDTLS_OID_INIHIBIT_ANYPOLICY
+#define OID_ISO_CCITT_DS MBEDTLS_OID_ISO_CCITT_DS
+#define OID_ISO_IDENTIFIED_ORG MBEDTLS_OID_ISO_IDENTIFIED_ORG
+#define OID_ISO_ITU_COUNTRY MBEDTLS_OID_ISO_ITU_COUNTRY
+#define OID_ISO_ITU_US_ORG MBEDTLS_OID_ISO_ITU_US_ORG
+#define OID_ISO_MEMBER_BODIES MBEDTLS_OID_ISO_MEMBER_BODIES
+#define OID_ISSUER_ALT_NAME MBEDTLS_OID_ISSUER_ALT_NAME
+#define OID_KEY_USAGE MBEDTLS_OID_KEY_USAGE
+#define OID_KP MBEDTLS_OID_KP
+#define OID_MGF1 MBEDTLS_OID_MGF1
+#define OID_NAME_CONSTRAINTS MBEDTLS_OID_NAME_CONSTRAINTS
+#define OID_NETSCAPE MBEDTLS_OID_NETSCAPE
+#define OID_NS_BASE_URL MBEDTLS_OID_NS_BASE_URL
+#define OID_NS_CA_POLICY_URL MBEDTLS_OID_NS_CA_POLICY_URL
+#define OID_NS_CA_REVOCATION_URL MBEDTLS_OID_NS_CA_REVOCATION_URL
+#define OID_NS_CERT MBEDTLS_OID_NS_CERT
+#define OID_NS_CERT_SEQUENCE MBEDTLS_OID_NS_CERT_SEQUENCE
+#define OID_NS_CERT_TYPE MBEDTLS_OID_NS_CERT_TYPE
+#define OID_NS_COMMENT MBEDTLS_OID_NS_COMMENT
+#define OID_NS_DATA_TYPE MBEDTLS_OID_NS_DATA_TYPE
+#define OID_NS_RENEWAL_URL MBEDTLS_OID_NS_RENEWAL_URL
+#define OID_NS_REVOCATION_URL MBEDTLS_OID_NS_REVOCATION_URL
+#define OID_NS_SSL_SERVER_NAME MBEDTLS_OID_NS_SSL_SERVER_NAME
+#define OID_OCSP_SIGNING MBEDTLS_OID_OCSP_SIGNING
+#define OID_OIW_SECSIG MBEDTLS_OID_OIW_SECSIG
+#define OID_OIW_SECSIG_ALG MBEDTLS_OID_OIW_SECSIG_ALG
+#define OID_OIW_SECSIG_SHA1 MBEDTLS_OID_OIW_SECSIG_SHA1
+#define OID_ORGANIZATION MBEDTLS_OID_ORGANIZATION
+#define OID_ORG_ANSI_X9_62 MBEDTLS_OID_ORG_ANSI_X9_62
+#define OID_ORG_CERTICOM MBEDTLS_OID_ORG_CERTICOM
+#define OID_ORG_DOD MBEDTLS_OID_ORG_DOD
+#define OID_ORG_GOV MBEDTLS_OID_ORG_GOV
+#define OID_ORG_NETSCAPE MBEDTLS_OID_ORG_NETSCAPE
+#define OID_ORG_OIW MBEDTLS_OID_ORG_OIW
+#define OID_ORG_RSA_DATA_SECURITY MBEDTLS_OID_ORG_RSA_DATA_SECURITY
+#define OID_ORG_TELETRUST MBEDTLS_OID_ORG_TELETRUST
+#define OID_PKCS MBEDTLS_OID_PKCS
+#define OID_PKCS1 MBEDTLS_OID_PKCS1
+#define OID_PKCS12 MBEDTLS_OID_PKCS12
+#define OID_PKCS12_PBE MBEDTLS_OID_PKCS12_PBE
+#define OID_PKCS12_PBE_SHA1_DES2_EDE_CBC MBEDTLS_OID_PKCS12_PBE_SHA1_DES2_EDE_CBC
+#define OID_PKCS12_PBE_SHA1_DES3_EDE_CBC MBEDTLS_OID_PKCS12_PBE_SHA1_DES3_EDE_CBC
+#define OID_PKCS12_PBE_SHA1_RC2_128_CBC MBEDTLS_OID_PKCS12_PBE_SHA1_RC2_128_CBC
+#define OID_PKCS12_PBE_SHA1_RC2_40_CBC MBEDTLS_OID_PKCS12_PBE_SHA1_RC2_40_CBC
+#define OID_PKCS12_PBE_SHA1_RC4_128 MBEDTLS_OID_PKCS12_PBE_SHA1_RC4_128
+#define OID_PKCS12_PBE_SHA1_RC4_40 MBEDTLS_OID_PKCS12_PBE_SHA1_RC4_40
+#define OID_PKCS1_MD2 MBEDTLS_OID_PKCS1_MD2
+#define OID_PKCS1_MD4 MBEDTLS_OID_PKCS1_MD4
+#define OID_PKCS1_MD5 MBEDTLS_OID_PKCS1_MD5
+#define OID_PKCS1_RSA MBEDTLS_OID_PKCS1_RSA
+#define OID_PKCS1_SHA1 MBEDTLS_OID_PKCS1_SHA1
+#define OID_PKCS1_SHA224 MBEDTLS_OID_PKCS1_SHA224
+#define OID_PKCS1_SHA256 MBEDTLS_OID_PKCS1_SHA256
+#define OID_PKCS1_SHA384 MBEDTLS_OID_PKCS1_SHA384
+#define OID_PKCS1_SHA512 MBEDTLS_OID_PKCS1_SHA512
+#define OID_PKCS5 MBEDTLS_OID_PKCS5
+#define OID_PKCS5_PBES2 MBEDTLS_OID_PKCS5_PBES2
+#define OID_PKCS5_PBE_MD2_DES_CBC MBEDTLS_OID_PKCS5_PBE_MD2_DES_CBC
+#define OID_PKCS5_PBE_MD2_RC2_CBC MBEDTLS_OID_PKCS5_PBE_MD2_RC2_CBC
+#define OID_PKCS5_PBE_MD5_DES_CBC MBEDTLS_OID_PKCS5_PBE_MD5_DES_CBC
+#define OID_PKCS5_PBE_MD5_RC2_CBC MBEDTLS_OID_PKCS5_PBE_MD5_RC2_CBC
+#define OID_PKCS5_PBE_SHA1_DES_CBC MBEDTLS_OID_PKCS5_PBE_SHA1_DES_CBC
+#define OID_PKCS5_PBE_SHA1_RC2_CBC MBEDTLS_OID_PKCS5_PBE_SHA1_RC2_CBC
+#define OID_PKCS5_PBKDF2 MBEDTLS_OID_PKCS5_PBKDF2
+#define OID_PKCS5_PBMAC1 MBEDTLS_OID_PKCS5_PBMAC1
+#define OID_PKCS9 MBEDTLS_OID_PKCS9
+#define OID_PKCS9_CSR_EXT_REQ MBEDTLS_OID_PKCS9_CSR_EXT_REQ
+#define OID_PKCS9_EMAIL MBEDTLS_OID_PKCS9_EMAIL
+#define OID_PKIX MBEDTLS_OID_PKIX
+#define OID_POLICY_CONSTRAINTS MBEDTLS_OID_POLICY_CONSTRAINTS
+#define OID_POLICY_MAPPINGS MBEDTLS_OID_POLICY_MAPPINGS
+#define OID_PRIVATE_KEY_USAGE_PERIOD MBEDTLS_OID_PRIVATE_KEY_USAGE_PERIOD
+#define OID_RSASSA_PSS MBEDTLS_OID_RSASSA_PSS
+#define OID_RSA_COMPANY MBEDTLS_OID_RSA_COMPANY
+#define OID_RSA_SHA_OBS MBEDTLS_OID_RSA_SHA_OBS
+#define OID_SERVER_AUTH MBEDTLS_OID_SERVER_AUTH
+#define OID_SIZE MBEDTLS_OID_SIZE
+#define OID_SUBJECT_ALT_NAME MBEDTLS_OID_SUBJECT_ALT_NAME
+#define OID_SUBJECT_DIRECTORY_ATTRS MBEDTLS_OID_SUBJECT_DIRECTORY_ATTRS
+#define OID_SUBJECT_KEY_IDENTIFIER MBEDTLS_OID_SUBJECT_KEY_IDENTIFIER
+#define OID_TELETRUST MBEDTLS_OID_TELETRUST
+#define OID_TIME_STAMPING MBEDTLS_OID_TIME_STAMPING
+#define PADLOCK_ACE MBEDTLS_PADLOCK_ACE
+#define PADLOCK_ALIGN16 MBEDTLS_PADLOCK_ALIGN16
+#define PADLOCK_PHE MBEDTLS_PADLOCK_PHE
+#define PADLOCK_PMM MBEDTLS_PADLOCK_PMM
+#define PADLOCK_RNG MBEDTLS_PADLOCK_RNG
+#define PKCS12_DERIVE_IV MBEDTLS_PKCS12_DERIVE_IV
+#define PKCS12_DERIVE_KEY MBEDTLS_PKCS12_DERIVE_KEY
+#define PKCS12_DERIVE_MAC_KEY MBEDTLS_PKCS12_DERIVE_MAC_KEY
+#define PKCS12_PBE_DECRYPT MBEDTLS_PKCS12_PBE_DECRYPT
+#define PKCS12_PBE_ENCRYPT MBEDTLS_PKCS12_PBE_ENCRYPT
+#define PKCS5_DECRYPT MBEDTLS_PKCS5_DECRYPT
+#define PKCS5_ENCRYPT MBEDTLS_PKCS5_ENCRYPT
+#define POLARSSL_AESNI_AES MBEDTLS_AESNI_AES
+#define POLARSSL_AESNI_CLMUL MBEDTLS_AESNI_CLMUL
+#define POLARSSL_AESNI_H MBEDTLS_AESNI_H
+#define POLARSSL_AES_H MBEDTLS_AES_H
+#define POLARSSL_ARC4_H MBEDTLS_ARC4_H
+#define POLARSSL_ASN1_H MBEDTLS_ASN1_H
+#define POLARSSL_ASN1_WRITE_H MBEDTLS_ASN1_WRITE_H
+#define POLARSSL_BASE64_H MBEDTLS_BASE64_H
+#define POLARSSL_BIGNUM_H MBEDTLS_BIGNUM_H
+#define POLARSSL_BLOWFISH_H MBEDTLS_BLOWFISH_H
+#define POLARSSL_BN_MUL_H MBEDTLS_BN_MUL_H
+#define POLARSSL_CAMELLIA_H MBEDTLS_CAMELLIA_H
+#define POLARSSL_CCM_H MBEDTLS_CCM_H
+#define POLARSSL_CERTS_H MBEDTLS_CERTS_H
+#define POLARSSL_CHECK_CONFIG_H MBEDTLS_CHECK_CONFIG_H
+#define POLARSSL_CIPHERSUITE_NODTLS MBEDTLS_CIPHERSUITE_NODTLS
+#define POLARSSL_CIPHERSUITE_SHORT_TAG MBEDTLS_CIPHERSUITE_SHORT_TAG
+#define POLARSSL_CIPHERSUITE_WEAK MBEDTLS_CIPHERSUITE_WEAK
+#define POLARSSL_CIPHER_AES_128_CBC MBEDTLS_CIPHER_AES_128_CBC
+#define POLARSSL_CIPHER_AES_128_CCM MBEDTLS_CIPHER_AES_128_CCM
+#define POLARSSL_CIPHER_AES_128_CFB128 MBEDTLS_CIPHER_AES_128_CFB128
+#define POLARSSL_CIPHER_AES_128_CTR MBEDTLS_CIPHER_AES_128_CTR
+#define POLARSSL_CIPHER_AES_128_ECB MBEDTLS_CIPHER_AES_128_ECB
+#define POLARSSL_CIPHER_AES_128_GCM MBEDTLS_CIPHER_AES_128_GCM
+#define POLARSSL_CIPHER_AES_192_CBC MBEDTLS_CIPHER_AES_192_CBC
+#define POLARSSL_CIPHER_AES_192_CCM MBEDTLS_CIPHER_AES_192_CCM
+#define POLARSSL_CIPHER_AES_192_CFB128 MBEDTLS_CIPHER_AES_192_CFB128
+#define POLARSSL_CIPHER_AES_192_CTR MBEDTLS_CIPHER_AES_192_CTR
+#define POLARSSL_CIPHER_AES_192_ECB MBEDTLS_CIPHER_AES_192_ECB
+#define POLARSSL_CIPHER_AES_192_GCM MBEDTLS_CIPHER_AES_192_GCM
+#define POLARSSL_CIPHER_AES_256_CBC MBEDTLS_CIPHER_AES_256_CBC
+#define POLARSSL_CIPHER_AES_256_CCM MBEDTLS_CIPHER_AES_256_CCM
+#define POLARSSL_CIPHER_AES_256_CFB128 MBEDTLS_CIPHER_AES_256_CFB128
+#define POLARSSL_CIPHER_AES_256_CTR MBEDTLS_CIPHER_AES_256_CTR
+#define POLARSSL_CIPHER_AES_256_ECB MBEDTLS_CIPHER_AES_256_ECB
+#define POLARSSL_CIPHER_AES_256_GCM MBEDTLS_CIPHER_AES_256_GCM
+#define POLARSSL_CIPHER_ARC4_128 MBEDTLS_CIPHER_ARC4_128
+#define POLARSSL_CIPHER_BLOWFISH_CBC MBEDTLS_CIPHER_BLOWFISH_CBC
+#define POLARSSL_CIPHER_BLOWFISH_CFB64 MBEDTLS_CIPHER_BLOWFISH_CFB64
+#define POLARSSL_CIPHER_BLOWFISH_CTR MBEDTLS_CIPHER_BLOWFISH_CTR
+#define POLARSSL_CIPHER_BLOWFISH_ECB MBEDTLS_CIPHER_BLOWFISH_ECB
+#define POLARSSL_CIPHER_CAMELLIA_128_CBC MBEDTLS_CIPHER_CAMELLIA_128_CBC
+#define POLARSSL_CIPHER_CAMELLIA_128_CCM MBEDTLS_CIPHER_CAMELLIA_128_CCM
+#define POLARSSL_CIPHER_CAMELLIA_128_CFB128 MBEDTLS_CIPHER_CAMELLIA_128_CFB128
+#define POLARSSL_CIPHER_CAMELLIA_128_CTR MBEDTLS_CIPHER_CAMELLIA_128_CTR
+#define POLARSSL_CIPHER_CAMELLIA_128_ECB MBEDTLS_CIPHER_CAMELLIA_128_ECB
+#define POLARSSL_CIPHER_CAMELLIA_128_GCM MBEDTLS_CIPHER_CAMELLIA_128_GCM
+#define POLARSSL_CIPHER_CAMELLIA_192_CBC MBEDTLS_CIPHER_CAMELLIA_192_CBC
+#define POLARSSL_CIPHER_CAMELLIA_192_CCM MBEDTLS_CIPHER_CAMELLIA_192_CCM
+#define POLARSSL_CIPHER_CAMELLIA_192_CFB128 MBEDTLS_CIPHER_CAMELLIA_192_CFB128
+#define POLARSSL_CIPHER_CAMELLIA_192_CTR MBEDTLS_CIPHER_CAMELLIA_192_CTR
+#define POLARSSL_CIPHER_CAMELLIA_192_ECB MBEDTLS_CIPHER_CAMELLIA_192_ECB
+#define POLARSSL_CIPHER_CAMELLIA_192_GCM MBEDTLS_CIPHER_CAMELLIA_192_GCM
+#define POLARSSL_CIPHER_CAMELLIA_256_CBC MBEDTLS_CIPHER_CAMELLIA_256_CBC
+#define POLARSSL_CIPHER_CAMELLIA_256_CCM MBEDTLS_CIPHER_CAMELLIA_256_CCM
+#define POLARSSL_CIPHER_CAMELLIA_256_CFB128 MBEDTLS_CIPHER_CAMELLIA_256_CFB128
+#define POLARSSL_CIPHER_CAMELLIA_256_CTR MBEDTLS_CIPHER_CAMELLIA_256_CTR
+#define POLARSSL_CIPHER_CAMELLIA_256_ECB MBEDTLS_CIPHER_CAMELLIA_256_ECB
+#define POLARSSL_CIPHER_CAMELLIA_256_GCM MBEDTLS_CIPHER_CAMELLIA_256_GCM
+#define POLARSSL_CIPHER_DES_CBC MBEDTLS_CIPHER_DES_CBC
+#define POLARSSL_CIPHER_DES_ECB MBEDTLS_CIPHER_DES_ECB
+#define POLARSSL_CIPHER_DES_EDE3_CBC MBEDTLS_CIPHER_DES_EDE3_CBC
+#define POLARSSL_CIPHER_DES_EDE3_ECB MBEDTLS_CIPHER_DES_EDE3_ECB
+#define POLARSSL_CIPHER_DES_EDE_CBC MBEDTLS_CIPHER_DES_EDE_CBC
+#define POLARSSL_CIPHER_DES_EDE_ECB MBEDTLS_CIPHER_DES_EDE_ECB
+#define POLARSSL_CIPHER_H MBEDTLS_CIPHER_H
+#define POLARSSL_CIPHER_ID_3DES MBEDTLS_CIPHER_ID_3DES
+#define POLARSSL_CIPHER_ID_AES MBEDTLS_CIPHER_ID_AES
+#define POLARSSL_CIPHER_ID_ARC4 MBEDTLS_CIPHER_ID_ARC4
+#define POLARSSL_CIPHER_ID_BLOWFISH MBEDTLS_CIPHER_ID_BLOWFISH
+#define POLARSSL_CIPHER_ID_CAMELLIA MBEDTLS_CIPHER_ID_CAMELLIA
+#define POLARSSL_CIPHER_ID_DES MBEDTLS_CIPHER_ID_DES
+#define POLARSSL_CIPHER_ID_NONE MBEDTLS_CIPHER_ID_NONE
+#define POLARSSL_CIPHER_ID_NULL MBEDTLS_CIPHER_ID_NULL
+#define POLARSSL_CIPHER_MODE_AEAD MBEDTLS_CIPHER_MODE_AEAD
+#define POLARSSL_CIPHER_MODE_STREAM MBEDTLS_CIPHER_MODE_STREAM
+#define POLARSSL_CIPHER_MODE_WITH_PADDING MBEDTLS_CIPHER_MODE_WITH_PADDING
+#define POLARSSL_CIPHER_NONE MBEDTLS_CIPHER_NONE
+#define POLARSSL_CIPHER_NULL MBEDTLS_CIPHER_NULL
+#define POLARSSL_CIPHER_VARIABLE_IV_LEN MBEDTLS_CIPHER_VARIABLE_IV_LEN
+#define POLARSSL_CIPHER_VARIABLE_KEY_LEN MBEDTLS_CIPHER_VARIABLE_KEY_LEN
+#define POLARSSL_CIPHER_WRAP_H MBEDTLS_CIPHER_WRAP_H
+#define POLARSSL_CONFIG_H MBEDTLS_CONFIG_H
+#define POLARSSL_CTR_DRBG_H MBEDTLS_CTR_DRBG_H
+#define POLARSSL_DEBUG_H MBEDTLS_DEBUG_H
+#define POLARSSL_DEBUG_LOG_FULL MBEDTLS_DEBUG_LOG_FULL
+#define POLARSSL_DEBUG_LOG_RAW MBEDTLS_DEBUG_LOG_RAW
+#define POLARSSL_DECRYPT MBEDTLS_DECRYPT
+#define POLARSSL_DES_H MBEDTLS_DES_H
+#define POLARSSL_DHM_H MBEDTLS_DHM_H
+#define POLARSSL_DHM_RFC2409_MODP_1024_G MBEDTLS_DHM_RFC2409_MODP_1024_G
+#define POLARSSL_DHM_RFC2409_MODP_1024_P MBEDTLS_DHM_RFC2409_MODP_1024_P
+#define POLARSSL_DHM_RFC3526_MODP_2048_G MBEDTLS_DHM_RFC3526_MODP_2048_G
+#define POLARSSL_DHM_RFC3526_MODP_2048_P MBEDTLS_DHM_RFC3526_MODP_2048_P
+#define POLARSSL_DHM_RFC3526_MODP_3072_G MBEDTLS_DHM_RFC3526_MODP_3072_G
+#define POLARSSL_DHM_RFC3526_MODP_3072_P MBEDTLS_DHM_RFC3526_MODP_3072_P
+#define POLARSSL_DHM_RFC5114_MODP_1024_G MBEDTLS_DHM_RFC5114_MODP_1024_G
+#define POLARSSL_DHM_RFC5114_MODP_1024_P MBEDTLS_DHM_RFC5114_MODP_1024_P
+#define POLARSSL_DHM_RFC5114_MODP_2048_G MBEDTLS_DHM_RFC5114_MODP_2048_G
+#define POLARSSL_DHM_RFC5114_MODP_2048_P MBEDTLS_DHM_RFC5114_MODP_2048_P
+#define POLARSSL_ECDH_H MBEDTLS_ECDH_H
+#define POLARSSL_ECDH_OURS MBEDTLS_ECDH_OURS
+#define POLARSSL_ECDH_THEIRS MBEDTLS_ECDH_THEIRS
+#define POLARSSL_ECDSA_H MBEDTLS_ECDSA_H
+#define POLARSSL_ECP_DP_BP256R1 MBEDTLS_ECP_DP_BP256R1
+#define POLARSSL_ECP_DP_BP384R1 MBEDTLS_ECP_DP_BP384R1
+#define POLARSSL_ECP_DP_BP512R1 MBEDTLS_ECP_DP_BP512R1
+#define POLARSSL_ECP_DP_M255 MBEDTLS_ECP_DP_CURVE25519
+#define POLARSSL_ECP_DP_MAX MBEDTLS_ECP_DP_MAX
+#define POLARSSL_ECP_DP_NONE MBEDTLS_ECP_DP_NONE
+#define POLARSSL_ECP_DP_SECP192K1 MBEDTLS_ECP_DP_SECP192K1
+#define POLARSSL_ECP_DP_SECP192R1 MBEDTLS_ECP_DP_SECP192R1
+#define POLARSSL_ECP_DP_SECP224K1 MBEDTLS_ECP_DP_SECP224K1
+#define POLARSSL_ECP_DP_SECP224R1 MBEDTLS_ECP_DP_SECP224R1
+#define POLARSSL_ECP_DP_SECP256K1 MBEDTLS_ECP_DP_SECP256K1
+#define POLARSSL_ECP_DP_SECP256R1 MBEDTLS_ECP_DP_SECP256R1
+#define POLARSSL_ECP_DP_SECP384R1 MBEDTLS_ECP_DP_SECP384R1
+#define POLARSSL_ECP_DP_SECP521R1 MBEDTLS_ECP_DP_SECP521R1
+#define POLARSSL_ECP_H MBEDTLS_ECP_H
+#define POLARSSL_ECP_MAX_BYTES MBEDTLS_ECP_MAX_BYTES
+#define POLARSSL_ECP_MAX_PT_LEN MBEDTLS_ECP_MAX_PT_LEN
+#define POLARSSL_ECP_PF_COMPRESSED MBEDTLS_ECP_PF_COMPRESSED
+#define POLARSSL_ECP_PF_UNCOMPRESSED MBEDTLS_ECP_PF_UNCOMPRESSED
+#define POLARSSL_ECP_TLS_NAMED_CURVE MBEDTLS_ECP_TLS_NAMED_CURVE
+#define POLARSSL_ENCRYPT MBEDTLS_ENCRYPT
+#define POLARSSL_ENTROPY_H MBEDTLS_ENTROPY_H
+#define POLARSSL_ENTROPY_POLL_H MBEDTLS_ENTROPY_POLL_H
+#define POLARSSL_ENTROPY_SHA256_ACCUMULATOR MBEDTLS_ENTROPY_SHA256_ACCUMULATOR
+#define POLARSSL_ENTROPY_SHA512_ACCUMULATOR MBEDTLS_ENTROPY_SHA512_ACCUMULATOR
+#define POLARSSL_ERROR_H MBEDTLS_ERROR_H
+#define POLARSSL_ERR_AES_INVALID_INPUT_LENGTH MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH
+#define POLARSSL_ERR_AES_INVALID_KEY_LENGTH MBEDTLS_ERR_AES_INVALID_KEY_LENGTH
+#define POLARSSL_ERR_ASN1_BUF_TOO_SMALL MBEDTLS_ERR_ASN1_BUF_TOO_SMALL
+#define POLARSSL_ERR_ASN1_INVALID_DATA MBEDTLS_ERR_ASN1_INVALID_DATA
+#define POLARSSL_ERR_ASN1_INVALID_LENGTH MBEDTLS_ERR_ASN1_INVALID_LENGTH
+#define POLARSSL_ERR_ASN1_LENGTH_MISMATCH MBEDTLS_ERR_ASN1_LENGTH_MISMATCH
+#define POLARSSL_ERR_ASN1_MALLOC_FAILED MBEDTLS_ERR_ASN1_ALLOC_FAILED
+#define POLARSSL_ERR_ASN1_OUT_OF_DATA MBEDTLS_ERR_ASN1_OUT_OF_DATA
+#define POLARSSL_ERR_ASN1_UNEXPECTED_TAG MBEDTLS_ERR_ASN1_UNEXPECTED_TAG
+#define POLARSSL_ERR_BASE64_BUFFER_TOO_SMALL MBEDTLS_ERR_BASE64_BUFFER_TOO_SMALL
+#define POLARSSL_ERR_BASE64_INVALID_CHARACTER MBEDTLS_ERR_BASE64_INVALID_CHARACTER
+#define POLARSSL_ERR_BLOWFISH_INVALID_INPUT_LENGTH MBEDTLS_ERR_BLOWFISH_INVALID_INPUT_LENGTH
+#define POLARSSL_ERR_BLOWFISH_INVALID_KEY_LENGTH MBEDTLS_ERR_BLOWFISH_INVALID_KEY_LENGTH
+#define POLARSSL_ERR_CAMELLIA_INVALID_INPUT_LENGTH MBEDTLS_ERR_CAMELLIA_INVALID_INPUT_LENGTH
+#define POLARSSL_ERR_CAMELLIA_INVALID_KEY_LENGTH MBEDTLS_ERR_CAMELLIA_INVALID_KEY_LENGTH
+#define POLARSSL_ERR_CCM_AUTH_FAILED MBEDTLS_ERR_CCM_AUTH_FAILED
+#define POLARSSL_ERR_CCM_BAD_INPUT MBEDTLS_ERR_CCM_BAD_INPUT
+#define POLARSSL_ERR_CIPHER_ALLOC_FAILED MBEDTLS_ERR_CIPHER_ALLOC_FAILED
+#define POLARSSL_ERR_CIPHER_AUTH_FAILED MBEDTLS_ERR_CIPHER_AUTH_FAILED
+#define POLARSSL_ERR_CIPHER_BAD_INPUT_DATA MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA
+#define POLARSSL_ERR_CIPHER_FEATURE_UNAVAILABLE MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE
+#define POLARSSL_ERR_CIPHER_FULL_BLOCK_EXPECTED MBEDTLS_ERR_CIPHER_FULL_BLOCK_EXPECTED
+#define POLARSSL_ERR_CIPHER_INVALID_PADDING MBEDTLS_ERR_CIPHER_INVALID_PADDING
+#define POLARSSL_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED
+#define POLARSSL_ERR_CTR_DRBG_FILE_IO_ERROR MBEDTLS_ERR_CTR_DRBG_FILE_IO_ERROR
+#define POLARSSL_ERR_CTR_DRBG_INPUT_TOO_BIG MBEDTLS_ERR_CTR_DRBG_INPUT_TOO_BIG
+#define POLARSSL_ERR_CTR_DRBG_REQUEST_TOO_BIG MBEDTLS_ERR_CTR_DRBG_REQUEST_TOO_BIG
+#define POLARSSL_ERR_DES_INVALID_INPUT_LENGTH MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH
+#define POLARSSL_ERR_DHM_BAD_INPUT_DATA MBEDTLS_ERR_DHM_BAD_INPUT_DATA
+#define POLARSSL_ERR_DHM_CALC_SECRET_FAILED MBEDTLS_ERR_DHM_CALC_SECRET_FAILED
+#define POLARSSL_ERR_DHM_FILE_IO_ERROR MBEDTLS_ERR_DHM_FILE_IO_ERROR
+#define POLARSSL_ERR_DHM_INVALID_FORMAT MBEDTLS_ERR_DHM_INVALID_FORMAT
+#define POLARSSL_ERR_DHM_MAKE_PARAMS_FAILED MBEDTLS_ERR_DHM_MAKE_PARAMS_FAILED
+#define POLARSSL_ERR_DHM_MAKE_PUBLIC_FAILED MBEDTLS_ERR_DHM_MAKE_PUBLIC_FAILED
+#define POLARSSL_ERR_DHM_MALLOC_FAILED MBEDTLS_ERR_DHM_ALLOC_FAILED
+#define POLARSSL_ERR_DHM_READ_PARAMS_FAILED MBEDTLS_ERR_DHM_READ_PARAMS_FAILED
+#define POLARSSL_ERR_DHM_READ_PUBLIC_FAILED MBEDTLS_ERR_DHM_READ_PUBLIC_FAILED
+#define POLARSSL_ERR_ECP_BAD_INPUT_DATA MBEDTLS_ERR_ECP_BAD_INPUT_DATA
+#define POLARSSL_ERR_ECP_BUFFER_TOO_SMALL MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL
+#define POLARSSL_ERR_ECP_FEATURE_UNAVAILABLE MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE
+#define POLARSSL_ERR_ECP_INVALID_KEY MBEDTLS_ERR_ECP_INVALID_KEY
+#define POLARSSL_ERR_ECP_MALLOC_FAILED MBEDTLS_ERR_ECP_ALLOC_FAILED
+#define POLARSSL_ERR_ECP_RANDOM_FAILED MBEDTLS_ERR_ECP_RANDOM_FAILED
+#define POLARSSL_ERR_ECP_SIG_LEN_MISMATCH MBEDTLS_ERR_ECP_SIG_LEN_MISMATCH
+#define POLARSSL_ERR_ECP_VERIFY_FAILED MBEDTLS_ERR_ECP_VERIFY_FAILED
+#define POLARSSL_ERR_ENTROPY_FILE_IO_ERROR MBEDTLS_ERR_ENTROPY_FILE_IO_ERROR
+#define POLARSSL_ERR_ENTROPY_MAX_SOURCES MBEDTLS_ERR_ENTROPY_MAX_SOURCES
+#define POLARSSL_ERR_ENTROPY_NO_SOURCES_DEFINED MBEDTLS_ERR_ENTROPY_NO_SOURCES_DEFINED
+#define POLARSSL_ERR_ENTROPY_SOURCE_FAILED MBEDTLS_ERR_ENTROPY_SOURCE_FAILED
+#define POLARSSL_ERR_GCM_AUTH_FAILED MBEDTLS_ERR_GCM_AUTH_FAILED
+#define POLARSSL_ERR_GCM_BAD_INPUT MBEDTLS_ERR_GCM_BAD_INPUT
+#define POLARSSL_ERR_HMAC_DRBG_ENTROPY_SOURCE_FAILED MBEDTLS_ERR_HMAC_DRBG_ENTROPY_SOURCE_FAILED
+#define POLARSSL_ERR_HMAC_DRBG_FILE_IO_ERROR MBEDTLS_ERR_HMAC_DRBG_FILE_IO_ERROR
+#define POLARSSL_ERR_HMAC_DRBG_INPUT_TOO_BIG MBEDTLS_ERR_HMAC_DRBG_INPUT_TOO_BIG
+#define POLARSSL_ERR_HMAC_DRBG_REQUEST_TOO_BIG MBEDTLS_ERR_HMAC_DRBG_REQUEST_TOO_BIG
+#define POLARSSL_ERR_MD2_FILE_IO_ERROR MBEDTLS_ERR_MD2_FILE_IO_ERROR
+#define POLARSSL_ERR_MD4_FILE_IO_ERROR MBEDTLS_ERR_MD4_FILE_IO_ERROR
+#define POLARSSL_ERR_MD5_FILE_IO_ERROR MBEDTLS_ERR_MD5_FILE_IO_ERROR
+#define POLARSSL_ERR_MD_ALLOC_FAILED MBEDTLS_ERR_MD_ALLOC_FAILED
+#define POLARSSL_ERR_MD_BAD_INPUT_DATA MBEDTLS_ERR_MD_BAD_INPUT_DATA
+#define POLARSSL_ERR_MD_FEATURE_UNAVAILABLE MBEDTLS_ERR_MD_FEATURE_UNAVAILABLE
+#define POLARSSL_ERR_MD_FILE_IO_ERROR MBEDTLS_ERR_MD_FILE_IO_ERROR
+#define POLARSSL_ERR_MPI_BAD_INPUT_DATA MBEDTLS_ERR_MPI_BAD_INPUT_DATA
+#define POLARSSL_ERR_MPI_BUFFER_TOO_SMALL MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL
+#define POLARSSL_ERR_MPI_DIVISION_BY_ZERO MBEDTLS_ERR_MPI_DIVISION_BY_ZERO
+#define POLARSSL_ERR_MPI_FILE_IO_ERROR MBEDTLS_ERR_MPI_FILE_IO_ERROR
+#define POLARSSL_ERR_MPI_INVALID_CHARACTER MBEDTLS_ERR_MPI_INVALID_CHARACTER
+#define POLARSSL_ERR_MPI_MALLOC_FAILED MBEDTLS_ERR_MPI_ALLOC_FAILED
+#define POLARSSL_ERR_MPI_NEGATIVE_VALUE MBEDTLS_ERR_MPI_NEGATIVE_VALUE
+#define POLARSSL_ERR_MPI_NOT_ACCEPTABLE MBEDTLS_ERR_MPI_NOT_ACCEPTABLE
+#define POLARSSL_ERR_NET_ACCEPT_FAILED MBEDTLS_ERR_NET_ACCEPT_FAILED
+#define POLARSSL_ERR_NET_BIND_FAILED MBEDTLS_ERR_NET_BIND_FAILED
+#define POLARSSL_ERR_NET_CONNECT_FAILED MBEDTLS_ERR_NET_CONNECT_FAILED
+#define POLARSSL_ERR_NET_CONN_RESET MBEDTLS_ERR_NET_CONN_RESET
+#define POLARSSL_ERR_NET_LISTEN_FAILED MBEDTLS_ERR_NET_LISTEN_FAILED
+#define POLARSSL_ERR_NET_RECV_FAILED MBEDTLS_ERR_NET_RECV_FAILED
+#define POLARSSL_ERR_NET_SEND_FAILED MBEDTLS_ERR_NET_SEND_FAILED
+#define POLARSSL_ERR_NET_SOCKET_FAILED MBEDTLS_ERR_NET_SOCKET_FAILED
+#define POLARSSL_ERR_NET_TIMEOUT MBEDTLS_ERR_SSL_TIMEOUT
+#define POLARSSL_ERR_NET_UNKNOWN_HOST MBEDTLS_ERR_NET_UNKNOWN_HOST
+#define POLARSSL_ERR_NET_WANT_READ MBEDTLS_ERR_SSL_WANT_READ
+#define POLARSSL_ERR_NET_WANT_WRITE MBEDTLS_ERR_SSL_WANT_WRITE
+#define POLARSSL_ERR_OID_BUF_TOO_SMALL MBEDTLS_ERR_OID_BUF_TOO_SMALL
+#define POLARSSL_ERR_OID_NOT_FOUND MBEDTLS_ERR_OID_NOT_FOUND
+#define POLARSSL_ERR_PADLOCK_DATA_MISALIGNED MBEDTLS_ERR_PADLOCK_DATA_MISALIGNED
+#define POLARSSL_ERR_PBKDF2_BAD_INPUT_DATA MBEDTLS_ERR_PBKDF2_BAD_INPUT_DATA
+#define POLARSSL_ERR_PEM_BAD_INPUT_DATA MBEDTLS_ERR_PEM_BAD_INPUT_DATA
+#define POLARSSL_ERR_PEM_FEATURE_UNAVAILABLE MBEDTLS_ERR_PEM_FEATURE_UNAVAILABLE
+#define POLARSSL_ERR_PEM_INVALID_DATA MBEDTLS_ERR_PEM_INVALID_DATA
+#define POLARSSL_ERR_PEM_INVALID_ENC_IV MBEDTLS_ERR_PEM_INVALID_ENC_IV
+#define POLARSSL_ERR_PEM_MALLOC_FAILED MBEDTLS_ERR_PEM_ALLOC_FAILED
+#define POLARSSL_ERR_PEM_NO_HEADER_FOOTER_PRESENT MBEDTLS_ERR_PEM_NO_HEADER_FOOTER_PRESENT
+#define POLARSSL_ERR_PEM_PASSWORD_MISMATCH MBEDTLS_ERR_PEM_PASSWORD_MISMATCH
+#define POLARSSL_ERR_PEM_PASSWORD_REQUIRED MBEDTLS_ERR_PEM_PASSWORD_REQUIRED
+#define POLARSSL_ERR_PEM_UNKNOWN_ENC_ALG MBEDTLS_ERR_PEM_UNKNOWN_ENC_ALG
+#define POLARSSL_ERR_PKCS12_BAD_INPUT_DATA MBEDTLS_ERR_PKCS12_BAD_INPUT_DATA
+#define POLARSSL_ERR_PKCS12_FEATURE_UNAVAILABLE MBEDTLS_ERR_PKCS12_FEATURE_UNAVAILABLE
+#define POLARSSL_ERR_PKCS12_PASSWORD_MISMATCH MBEDTLS_ERR_PKCS12_PASSWORD_MISMATCH
+#define POLARSSL_ERR_PKCS12_PBE_INVALID_FORMAT MBEDTLS_ERR_PKCS12_PBE_INVALID_FORMAT
+#define POLARSSL_ERR_PKCS5_BAD_INPUT_DATA MBEDTLS_ERR_PKCS5_BAD_INPUT_DATA
+#define POLARSSL_ERR_PKCS5_FEATURE_UNAVAILABLE MBEDTLS_ERR_PKCS5_FEATURE_UNAVAILABLE
+#define POLARSSL_ERR_PKCS5_INVALID_FORMAT MBEDTLS_ERR_PKCS5_INVALID_FORMAT
+#define POLARSSL_ERR_PKCS5_PASSWORD_MISMATCH MBEDTLS_ERR_PKCS5_PASSWORD_MISMATCH
+#define POLARSSL_ERR_PK_BAD_INPUT_DATA MBEDTLS_ERR_PK_BAD_INPUT_DATA
+#define POLARSSL_ERR_PK_FEATURE_UNAVAILABLE MBEDTLS_ERR_PK_FEATURE_UNAVAILABLE
+#define POLARSSL_ERR_PK_FILE_IO_ERROR MBEDTLS_ERR_PK_FILE_IO_ERROR
+#define POLARSSL_ERR_PK_INVALID_ALG MBEDTLS_ERR_PK_INVALID_ALG
+#define POLARSSL_ERR_PK_INVALID_PUBKEY MBEDTLS_ERR_PK_INVALID_PUBKEY
+#define POLARSSL_ERR_PK_KEY_INVALID_FORMAT MBEDTLS_ERR_PK_KEY_INVALID_FORMAT
+#define POLARSSL_ERR_PK_KEY_INVALID_VERSION MBEDTLS_ERR_PK_KEY_INVALID_VERSION
+#define POLARSSL_ERR_PK_MALLOC_FAILED MBEDTLS_ERR_PK_ALLOC_FAILED
+#define POLARSSL_ERR_PK_PASSWORD_MISMATCH MBEDTLS_ERR_PK_PASSWORD_MISMATCH
+#define POLARSSL_ERR_PK_PASSWORD_REQUIRED MBEDTLS_ERR_PK_PASSWORD_REQUIRED
+#define POLARSSL_ERR_PK_SIG_LEN_MISMATCH MBEDTLS_ERR_PK_SIG_LEN_MISMATCH
+#define POLARSSL_ERR_PK_TYPE_MISMATCH MBEDTLS_ERR_PK_TYPE_MISMATCH
+#define POLARSSL_ERR_PK_UNKNOWN_NAMED_CURVE MBEDTLS_ERR_PK_UNKNOWN_NAMED_CURVE
+#define POLARSSL_ERR_PK_UNKNOWN_PK_ALG MBEDTLS_ERR_PK_UNKNOWN_PK_ALG
+#define POLARSSL_ERR_RIPEMD160_FILE_IO_ERROR MBEDTLS_ERR_RIPEMD160_FILE_IO_ERROR
+#define POLARSSL_ERR_RSA_BAD_INPUT_DATA MBEDTLS_ERR_RSA_BAD_INPUT_DATA
+#define POLARSSL_ERR_RSA_INVALID_PADDING MBEDTLS_ERR_RSA_INVALID_PADDING
+#define POLARSSL_ERR_RSA_KEY_CHECK_FAILED MBEDTLS_ERR_RSA_KEY_CHECK_FAILED
+#define POLARSSL_ERR_RSA_KEY_GEN_FAILED MBEDTLS_ERR_RSA_KEY_GEN_FAILED
+#define POLARSSL_ERR_RSA_OUTPUT_TOO_LARGE MBEDTLS_ERR_RSA_OUTPUT_TOO_LARGE
+#define POLARSSL_ERR_RSA_PRIVATE_FAILED MBEDTLS_ERR_RSA_PRIVATE_FAILED
+#define POLARSSL_ERR_RSA_PUBLIC_FAILED MBEDTLS_ERR_RSA_PUBLIC_FAILED
+#define POLARSSL_ERR_RSA_RNG_FAILED MBEDTLS_ERR_RSA_RNG_FAILED
+#define POLARSSL_ERR_RSA_VERIFY_FAILED MBEDTLS_ERR_RSA_VERIFY_FAILED
+#define POLARSSL_ERR_SHA1_FILE_IO_ERROR MBEDTLS_ERR_SHA1_FILE_IO_ERROR
+#define POLARSSL_ERR_SHA256_FILE_IO_ERROR MBEDTLS_ERR_SHA256_FILE_IO_ERROR
+#define POLARSSL_ERR_SHA512_FILE_IO_ERROR MBEDTLS_ERR_SHA512_FILE_IO_ERROR
+#define POLARSSL_ERR_SSL_BAD_HS_CERTIFICATE MBEDTLS_ERR_SSL_BAD_HS_CERTIFICATE
+#define POLARSSL_ERR_SSL_BAD_HS_CERTIFICATE_REQUEST MBEDTLS_ERR_SSL_BAD_HS_CERTIFICATE_REQUEST
+#define POLARSSL_ERR_SSL_BAD_HS_CERTIFICATE_VERIFY MBEDTLS_ERR_SSL_BAD_HS_CERTIFICATE_VERIFY
+#define POLARSSL_ERR_SSL_BAD_HS_CHANGE_CIPHER_SPEC MBEDTLS_ERR_SSL_BAD_HS_CHANGE_CIPHER_SPEC
+#define POLARSSL_ERR_SSL_BAD_HS_CLIENT_HELLO MBEDTLS_ERR_SSL_BAD_HS_CLIENT_HELLO
+#define POLARSSL_ERR_SSL_BAD_HS_CLIENT_KEY_EXCHANGE MBEDTLS_ERR_SSL_BAD_HS_CLIENT_KEY_EXCHANGE
+#define POLARSSL_ERR_SSL_BAD_HS_CLIENT_KEY_EXCHANGE_CS MBEDTLS_ERR_SSL_BAD_HS_CLIENT_KEY_EXCHANGE_CS
+#define POLARSSL_ERR_SSL_BAD_HS_CLIENT_KEY_EXCHANGE_RP MBEDTLS_ERR_SSL_BAD_HS_CLIENT_KEY_EXCHANGE_RP
+#define POLARSSL_ERR_SSL_BAD_HS_FINISHED MBEDTLS_ERR_SSL_BAD_HS_FINISHED
+#define POLARSSL_ERR_SSL_BAD_HS_NEW_SESSION_TICKET MBEDTLS_ERR_SSL_BAD_HS_NEW_SESSION_TICKET
+#define POLARSSL_ERR_SSL_BAD_HS_PROTOCOL_VERSION MBEDTLS_ERR_SSL_BAD_HS_PROTOCOL_VERSION
+#define POLARSSL_ERR_SSL_BAD_HS_SERVER_HELLO MBEDTLS_ERR_SSL_BAD_HS_SERVER_HELLO
+#define POLARSSL_ERR_SSL_BAD_HS_SERVER_HELLO_DONE MBEDTLS_ERR_SSL_BAD_HS_SERVER_HELLO_DONE
+#define POLARSSL_ERR_SSL_BAD_HS_SERVER_KEY_EXCHANGE MBEDTLS_ERR_SSL_BAD_HS_SERVER_KEY_EXCHANGE
+#define POLARSSL_ERR_SSL_BAD_INPUT_DATA MBEDTLS_ERR_SSL_BAD_INPUT_DATA
+#define POLARSSL_ERR_SSL_BUFFER_TOO_SMALL MBEDTLS_ERR_SSL_BUFFER_TOO_SMALL
+#define POLARSSL_ERR_SSL_CA_CHAIN_REQUIRED MBEDTLS_ERR_SSL_CA_CHAIN_REQUIRED
+#define POLARSSL_ERR_SSL_CERTIFICATE_REQUIRED MBEDTLS_ERR_SSL_CERTIFICATE_REQUIRED
+#define POLARSSL_ERR_SSL_CERTIFICATE_TOO_LARGE MBEDTLS_ERR_SSL_CERTIFICATE_TOO_LARGE
+#define POLARSSL_ERR_SSL_COMPRESSION_FAILED MBEDTLS_ERR_SSL_COMPRESSION_FAILED
+#define POLARSSL_ERR_SSL_CONN_EOF MBEDTLS_ERR_SSL_CONN_EOF
+#define POLARSSL_ERR_SSL_COUNTER_WRAPPING MBEDTLS_ERR_SSL_COUNTER_WRAPPING
+#define POLARSSL_ERR_SSL_FATAL_ALERT_MESSAGE MBEDTLS_ERR_SSL_FATAL_ALERT_MESSAGE
+#define POLARSSL_ERR_SSL_FEATURE_UNAVAILABLE MBEDTLS_ERR_SSL_FEATURE_UNAVAILABLE
+#define POLARSSL_ERR_SSL_HELLO_VERIFY_REQUIRED MBEDTLS_ERR_SSL_HELLO_VERIFY_REQUIRED
+#define POLARSSL_ERR_SSL_HW_ACCEL_FAILED MBEDTLS_ERR_SSL_HW_ACCEL_FAILED
+#define POLARSSL_ERR_SSL_HW_ACCEL_FALLTHROUGH MBEDTLS_ERR_SSL_HW_ACCEL_FALLTHROUGH
+#define POLARSSL_ERR_SSL_INTERNAL_ERROR MBEDTLS_ERR_SSL_INTERNAL_ERROR
+#define POLARSSL_ERR_SSL_INVALID_MAC MBEDTLS_ERR_SSL_INVALID_MAC
+#define POLARSSL_ERR_SSL_INVALID_RECORD MBEDTLS_ERR_SSL_INVALID_RECORD
+#define POLARSSL_ERR_SSL_MALLOC_FAILED MBEDTLS_ERR_SSL_ALLOC_FAILED
+#define POLARSSL_ERR_SSL_NO_CIPHER_CHOSEN MBEDTLS_ERR_SSL_NO_CIPHER_CHOSEN
+#define POLARSSL_ERR_SSL_NO_CLIENT_CERTIFICATE MBEDTLS_ERR_SSL_NO_CLIENT_CERTIFICATE
+#define POLARSSL_ERR_SSL_NO_RNG MBEDTLS_ERR_SSL_NO_RNG
+#define POLARSSL_ERR_SSL_NO_USABLE_CIPHERSUITE MBEDTLS_ERR_SSL_NO_USABLE_CIPHERSUITE
+#define POLARSSL_ERR_SSL_PEER_CLOSE_NOTIFY MBEDTLS_ERR_SSL_PEER_CLOSE_NOTIFY
+#define POLARSSL_ERR_SSL_PEER_VERIFY_FAILED MBEDTLS_ERR_SSL_PEER_VERIFY_FAILED
+#define POLARSSL_ERR_SSL_PK_TYPE_MISMATCH MBEDTLS_ERR_SSL_PK_TYPE_MISMATCH
+#define POLARSSL_ERR_SSL_PRIVATE_KEY_REQUIRED MBEDTLS_ERR_SSL_PRIVATE_KEY_REQUIRED
+#define POLARSSL_ERR_SSL_SESSION_TICKET_EXPIRED MBEDTLS_ERR_SSL_SESSION_TICKET_EXPIRED
+#define POLARSSL_ERR_SSL_UNEXPECTED_MESSAGE MBEDTLS_ERR_SSL_UNEXPECTED_MESSAGE
+#define POLARSSL_ERR_SSL_UNKNOWN_CIPHER MBEDTLS_ERR_SSL_UNKNOWN_CIPHER
+#define POLARSSL_ERR_SSL_UNKNOWN_IDENTITY MBEDTLS_ERR_SSL_UNKNOWN_IDENTITY
+#define POLARSSL_ERR_SSL_WAITING_SERVER_HELLO_RENEGO MBEDTLS_ERR_SSL_WAITING_SERVER_HELLO_RENEGO
+#define POLARSSL_ERR_THREADING_BAD_INPUT_DATA MBEDTLS_ERR_THREADING_BAD_INPUT_DATA
+#define POLARSSL_ERR_THREADING_FEATURE_UNAVAILABLE MBEDTLS_ERR_THREADING_FEATURE_UNAVAILABLE
+#define POLARSSL_ERR_THREADING_MUTEX_ERROR MBEDTLS_ERR_THREADING_MUTEX_ERROR
+#define POLARSSL_ERR_X509_BAD_INPUT_DATA MBEDTLS_ERR_X509_BAD_INPUT_DATA
+#define POLARSSL_ERR_X509_CERT_UNKNOWN_FORMAT MBEDTLS_ERR_X509_CERT_UNKNOWN_FORMAT
+#define POLARSSL_ERR_X509_CERT_VERIFY_FAILED MBEDTLS_ERR_X509_CERT_VERIFY_FAILED
+#define POLARSSL_ERR_X509_FEATURE_UNAVAILABLE MBEDTLS_ERR_X509_FEATURE_UNAVAILABLE
+#define POLARSSL_ERR_X509_FILE_IO_ERROR MBEDTLS_ERR_X509_FILE_IO_ERROR
+#define POLARSSL_ERR_X509_INVALID_ALG MBEDTLS_ERR_X509_INVALID_ALG
+#define POLARSSL_ERR_X509_INVALID_DATE MBEDTLS_ERR_X509_INVALID_DATE
+#define POLARSSL_ERR_X509_INVALID_EXTENSIONS MBEDTLS_ERR_X509_INVALID_EXTENSIONS
+#define POLARSSL_ERR_X509_INVALID_FORMAT MBEDTLS_ERR_X509_INVALID_FORMAT
+#define POLARSSL_ERR_X509_INVALID_NAME MBEDTLS_ERR_X509_INVALID_NAME
+#define POLARSSL_ERR_X509_INVALID_SERIAL MBEDTLS_ERR_X509_INVALID_SERIAL
+#define POLARSSL_ERR_X509_INVALID_SIGNATURE MBEDTLS_ERR_X509_INVALID_SIGNATURE
+#define POLARSSL_ERR_X509_INVALID_VERSION MBEDTLS_ERR_X509_INVALID_VERSION
+#define POLARSSL_ERR_X509_MALLOC_FAILED MBEDTLS_ERR_X509_ALLOC_FAILED
+#define POLARSSL_ERR_X509_SIG_MISMATCH MBEDTLS_ERR_X509_SIG_MISMATCH
+#define POLARSSL_ERR_X509_UNKNOWN_OID MBEDTLS_ERR_X509_UNKNOWN_OID
+#define POLARSSL_ERR_X509_UNKNOWN_SIG_ALG MBEDTLS_ERR_X509_UNKNOWN_SIG_ALG
+#define POLARSSL_ERR_X509_UNKNOWN_VERSION MBEDTLS_ERR_X509_UNKNOWN_VERSION
+#define POLARSSL_ERR_XTEA_INVALID_INPUT_LENGTH MBEDTLS_ERR_XTEA_INVALID_INPUT_LENGTH
+#define POLARSSL_GCM_H MBEDTLS_GCM_H
+#define POLARSSL_HAVEGE_H MBEDTLS_HAVEGE_H
+#define POLARSSL_HAVE_INT32 MBEDTLS_HAVE_INT32
+#define POLARSSL_HAVE_INT64 MBEDTLS_HAVE_INT64
+#define POLARSSL_HAVE_UDBL MBEDTLS_HAVE_UDBL
+#define POLARSSL_HAVE_X86 MBEDTLS_HAVE_X86
+#define POLARSSL_HAVE_X86_64 MBEDTLS_HAVE_X86_64
+#define POLARSSL_HMAC_DRBG_H MBEDTLS_HMAC_DRBG_H
+#define POLARSSL_HMAC_DRBG_PR_OFF MBEDTLS_HMAC_DRBG_PR_OFF
+#define POLARSSL_HMAC_DRBG_PR_ON MBEDTLS_HMAC_DRBG_PR_ON
+#define POLARSSL_KEY_EXCHANGE_DHE_PSK MBEDTLS_KEY_EXCHANGE_DHE_PSK
+#define POLARSSL_KEY_EXCHANGE_DHE_RSA MBEDTLS_KEY_EXCHANGE_DHE_RSA
+#define POLARSSL_KEY_EXCHANGE_ECDHE_ECDSA MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA
+#define POLARSSL_KEY_EXCHANGE_ECDHE_PSK MBEDTLS_KEY_EXCHANGE_ECDHE_PSK
+#define POLARSSL_KEY_EXCHANGE_ECDHE_RSA MBEDTLS_KEY_EXCHANGE_ECDHE_RSA
+#define POLARSSL_KEY_EXCHANGE_ECDH_ECDSA MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA
+#define POLARSSL_KEY_EXCHANGE_ECDH_RSA MBEDTLS_KEY_EXCHANGE_ECDH_RSA
+#define POLARSSL_KEY_EXCHANGE_NONE MBEDTLS_KEY_EXCHANGE_NONE
+#define POLARSSL_KEY_EXCHANGE_PSK MBEDTLS_KEY_EXCHANGE_PSK
+#define POLARSSL_KEY_EXCHANGE_RSA MBEDTLS_KEY_EXCHANGE_RSA
+#define POLARSSL_KEY_EXCHANGE_RSA_PSK MBEDTLS_KEY_EXCHANGE_RSA_PSK
+#define POLARSSL_KEY_EXCHANGE__SOME__ECDHE_ENABLED MBEDTLS_KEY_EXCHANGE__SOME__ECDHE_ENABLED
+#define POLARSSL_KEY_EXCHANGE__SOME__PSK_ENABLED MBEDTLS_KEY_EXCHANGE__SOME__PSK_ENABLED
+#define POLARSSL_KEY_EXCHANGE__WITH_CERT__ENABLED MBEDTLS_KEY_EXCHANGE__WITH_CERT__ENABLED
+#define POLARSSL_KEY_LENGTH_DES MBEDTLS_KEY_LENGTH_DES
+#define POLARSSL_KEY_LENGTH_DES_EDE MBEDTLS_KEY_LENGTH_DES_EDE
+#define POLARSSL_KEY_LENGTH_DES_EDE3 MBEDTLS_KEY_LENGTH_DES_EDE3
+#define POLARSSL_KEY_LENGTH_NONE MBEDTLS_KEY_LENGTH_NONE
+#define POLARSSL_MAX_BLOCK_LENGTH MBEDTLS_MAX_BLOCK_LENGTH
+#define POLARSSL_MAX_IV_LENGTH MBEDTLS_MAX_IV_LENGTH
+#define POLARSSL_MD2_H MBEDTLS_MD2_H
+#define POLARSSL_MD4_H MBEDTLS_MD4_H
+#define POLARSSL_MD5_H MBEDTLS_MD5_H
+#define POLARSSL_MD_H MBEDTLS_MD_H
+#define POLARSSL_MD_MAX_SIZE MBEDTLS_MD_MAX_SIZE
+#define POLARSSL_MD_MD2 MBEDTLS_MD_MD2
+#define POLARSSL_MD_MD4 MBEDTLS_MD_MD4
+#define POLARSSL_MD_MD5 MBEDTLS_MD_MD5
+#define POLARSSL_MD_NONE MBEDTLS_MD_NONE
+#define POLARSSL_MD_RIPEMD160 MBEDTLS_MD_RIPEMD160
+#define POLARSSL_MD_SHA1 MBEDTLS_MD_SHA1
+#define POLARSSL_MD_SHA224 MBEDTLS_MD_SHA224
+#define POLARSSL_MD_SHA256 MBEDTLS_MD_SHA256
+#define POLARSSL_MD_SHA384 MBEDTLS_MD_SHA384
+#define POLARSSL_MD_SHA512 MBEDTLS_MD_SHA512
+#define POLARSSL_MD_WRAP_H MBEDTLS_MD_WRAP_H
+#define POLARSSL_MEMORY_BUFFER_ALLOC_H MBEDTLS_MEMORY_BUFFER_ALLOC_H
+#define POLARSSL_MEMORY_H MBEDTLS_MEMORY_H
+#define POLARSSL_MODE_CBC MBEDTLS_MODE_CBC
+#define POLARSSL_MODE_CCM MBEDTLS_MODE_CCM
+#define POLARSSL_MODE_CFB MBEDTLS_MODE_CFB
+#define POLARSSL_MODE_CTR MBEDTLS_MODE_CTR
+#define POLARSSL_MODE_ECB MBEDTLS_MODE_ECB
+#define POLARSSL_MODE_GCM MBEDTLS_MODE_GCM
+#define POLARSSL_MODE_NONE MBEDTLS_MODE_NONE
+#define POLARSSL_MODE_OFB MBEDTLS_MODE_OFB
+#define POLARSSL_MODE_STREAM MBEDTLS_MODE_STREAM
+#define POLARSSL_MPI_MAX_BITS MBEDTLS_MPI_MAX_BITS
+#define POLARSSL_MPI_MAX_BITS_SCALE100 MBEDTLS_MPI_MAX_BITS_SCALE100
+#define POLARSSL_MPI_MAX_LIMBS MBEDTLS_MPI_MAX_LIMBS
+#define POLARSSL_MPI_RW_BUFFER_SIZE MBEDTLS_MPI_RW_BUFFER_SIZE
+#define POLARSSL_NET_H MBEDTLS_NET_H
+#define POLARSSL_NET_LISTEN_BACKLOG MBEDTLS_NET_LISTEN_BACKLOG
+#define POLARSSL_OID_H MBEDTLS_OID_H
+#define POLARSSL_OPERATION_NONE MBEDTLS_OPERATION_NONE
+#define POLARSSL_PADDING_NONE MBEDTLS_PADDING_NONE
+#define POLARSSL_PADDING_ONE_AND_ZEROS MBEDTLS_PADDING_ONE_AND_ZEROS
+#define POLARSSL_PADDING_PKCS7 MBEDTLS_PADDING_PKCS7
+#define POLARSSL_PADDING_ZEROS MBEDTLS_PADDING_ZEROS
+#define POLARSSL_PADDING_ZEROS_AND_LEN MBEDTLS_PADDING_ZEROS_AND_LEN
+#define POLARSSL_PADLOCK_H MBEDTLS_PADLOCK_H
+#define POLARSSL_PBKDF2_H MBEDTLS_PBKDF2_H
+#define POLARSSL_PEM_H MBEDTLS_PEM_H
+#define POLARSSL_PKCS11_H MBEDTLS_PKCS11_H
+#define POLARSSL_PKCS12_H MBEDTLS_PKCS12_H
+#define POLARSSL_PKCS5_H MBEDTLS_PKCS5_H
+#define POLARSSL_PK_DEBUG_ECP MBEDTLS_PK_DEBUG_ECP
+#define POLARSSL_PK_DEBUG_MAX_ITEMS MBEDTLS_PK_DEBUG_MAX_ITEMS
+#define POLARSSL_PK_DEBUG_MPI MBEDTLS_PK_DEBUG_MPI
+#define POLARSSL_PK_DEBUG_NONE MBEDTLS_PK_DEBUG_NONE
+#define POLARSSL_PK_ECDSA MBEDTLS_PK_ECDSA
+#define POLARSSL_PK_ECKEY MBEDTLS_PK_ECKEY
+#define POLARSSL_PK_ECKEY_DH MBEDTLS_PK_ECKEY_DH
+#define POLARSSL_PK_H MBEDTLS_PK_H
+#define POLARSSL_PK_NONE MBEDTLS_PK_NONE
+#define POLARSSL_PK_RSA MBEDTLS_PK_RSA
+#define POLARSSL_PK_RSASSA_PSS MBEDTLS_PK_RSASSA_PSS
+#define POLARSSL_PK_RSA_ALT MBEDTLS_PK_RSA_ALT
+#define POLARSSL_PK_WRAP_H MBEDTLS_PK_WRAP_H
+#define POLARSSL_PLATFORM_H MBEDTLS_PLATFORM_H
+#define POLARSSL_PREMASTER_SIZE MBEDTLS_PREMASTER_SIZE
+#define POLARSSL_RIPEMD160_H MBEDTLS_RIPEMD160_H
+#define POLARSSL_RSA_H MBEDTLS_RSA_H
+#define POLARSSL_SHA1_H MBEDTLS_SHA1_H
+#define POLARSSL_SHA256_H MBEDTLS_SHA256_H
+#define POLARSSL_SHA512_H MBEDTLS_SHA512_H
+#define POLARSSL_SSL_CACHE_H MBEDTLS_SSL_CACHE_H
+#define POLARSSL_SSL_CIPHERSUITES_H MBEDTLS_SSL_CIPHERSUITES_H
+#define POLARSSL_SSL_COOKIE_H MBEDTLS_SSL_COOKIE_H
+#define POLARSSL_SSL_H MBEDTLS_SSL_H
+#define POLARSSL_THREADING_H MBEDTLS_THREADING_H
+#define POLARSSL_THREADING_IMPL MBEDTLS_THREADING_IMPL
+#define POLARSSL_TIMING_H MBEDTLS_TIMING_H
+#define POLARSSL_VERSION_H MBEDTLS_VERSION_H
+#define POLARSSL_VERSION_MAJOR MBEDTLS_VERSION_MAJOR
+#define POLARSSL_VERSION_MINOR MBEDTLS_VERSION_MINOR
+#define POLARSSL_VERSION_NUMBER MBEDTLS_VERSION_NUMBER
+#define POLARSSL_VERSION_PATCH MBEDTLS_VERSION_PATCH
+#define POLARSSL_VERSION_STRING MBEDTLS_VERSION_STRING
+#define POLARSSL_VERSION_STRING_FULL MBEDTLS_VERSION_STRING_FULL
+#define POLARSSL_X509_CRL_H MBEDTLS_X509_CRL_H
+#define POLARSSL_X509_CRT_H MBEDTLS_X509_CRT_H
+#define POLARSSL_X509_CSR_H MBEDTLS_X509_CSR_H
+#define POLARSSL_X509_H MBEDTLS_X509_H
+#define POLARSSL_XTEA_H MBEDTLS_XTEA_H
+#define RSA_CRYPT MBEDTLS_RSA_CRYPT
+#define RSA_PKCS_V15 MBEDTLS_RSA_PKCS_V15
+#define RSA_PKCS_V21 MBEDTLS_RSA_PKCS_V21
+#define RSA_PRIVATE MBEDTLS_RSA_PRIVATE
+#define RSA_PUBLIC MBEDTLS_RSA_PUBLIC
+#define RSA_SALT_LEN_ANY MBEDTLS_RSA_SALT_LEN_ANY
+#define RSA_SIGN MBEDTLS_RSA_SIGN
+#define SSL_ALERT_LEVEL_FATAL MBEDTLS_SSL_ALERT_LEVEL_FATAL
+#define SSL_ALERT_LEVEL_WARNING MBEDTLS_SSL_ALERT_LEVEL_WARNING
+#define SSL_ALERT_MSG_ACCESS_DENIED MBEDTLS_SSL_ALERT_MSG_ACCESS_DENIED
+#define SSL_ALERT_MSG_BAD_CERT MBEDTLS_SSL_ALERT_MSG_BAD_CERT
+#define SSL_ALERT_MSG_BAD_RECORD_MAC MBEDTLS_SSL_ALERT_MSG_BAD_RECORD_MAC
+#define SSL_ALERT_MSG_CERT_EXPIRED MBEDTLS_SSL_ALERT_MSG_CERT_EXPIRED
+#define SSL_ALERT_MSG_CERT_REVOKED MBEDTLS_SSL_ALERT_MSG_CERT_REVOKED
+#define SSL_ALERT_MSG_CERT_UNKNOWN MBEDTLS_SSL_ALERT_MSG_CERT_UNKNOWN
+#define SSL_ALERT_MSG_CLOSE_NOTIFY MBEDTLS_SSL_ALERT_MSG_CLOSE_NOTIFY
+#define SSL_ALERT_MSG_DECODE_ERROR MBEDTLS_SSL_ALERT_MSG_DECODE_ERROR
+#define SSL_ALERT_MSG_DECOMPRESSION_FAILURE MBEDTLS_SSL_ALERT_MSG_DECOMPRESSION_FAILURE
+#define SSL_ALERT_MSG_DECRYPTION_FAILED MBEDTLS_SSL_ALERT_MSG_DECRYPTION_FAILED
+#define SSL_ALERT_MSG_DECRYPT_ERROR MBEDTLS_SSL_ALERT_MSG_DECRYPT_ERROR
+#define SSL_ALERT_MSG_EXPORT_RESTRICTION MBEDTLS_SSL_ALERT_MSG_EXPORT_RESTRICTION
+#define SSL_ALERT_MSG_HANDSHAKE_FAILURE MBEDTLS_SSL_ALERT_MSG_HANDSHAKE_FAILURE
+#define SSL_ALERT_MSG_ILLEGAL_PARAMETER MBEDTLS_SSL_ALERT_MSG_ILLEGAL_PARAMETER
+#define SSL_ALERT_MSG_INAPROPRIATE_FALLBACK MBEDTLS_SSL_ALERT_MSG_INAPROPRIATE_FALLBACK
+#define SSL_ALERT_MSG_INSUFFICIENT_SECURITY MBEDTLS_SSL_ALERT_MSG_INSUFFICIENT_SECURITY
+#define SSL_ALERT_MSG_INTERNAL_ERROR MBEDTLS_SSL_ALERT_MSG_INTERNAL_ERROR
+#define SSL_ALERT_MSG_NO_APPLICATION_PROTOCOL MBEDTLS_SSL_ALERT_MSG_NO_APPLICATION_PROTOCOL
+#define SSL_ALERT_MSG_NO_CERT MBEDTLS_SSL_ALERT_MSG_NO_CERT
+#define SSL_ALERT_MSG_NO_RENEGOTIATION MBEDTLS_SSL_ALERT_MSG_NO_RENEGOTIATION
+#define SSL_ALERT_MSG_PROTOCOL_VERSION MBEDTLS_SSL_ALERT_MSG_PROTOCOL_VERSION
+#define SSL_ALERT_MSG_RECORD_OVERFLOW MBEDTLS_SSL_ALERT_MSG_RECORD_OVERFLOW
+#define SSL_ALERT_MSG_UNEXPECTED_MESSAGE MBEDTLS_SSL_ALERT_MSG_UNEXPECTED_MESSAGE
+#define SSL_ALERT_MSG_UNKNOWN_CA MBEDTLS_SSL_ALERT_MSG_UNKNOWN_CA
+#define SSL_ALERT_MSG_UNKNOWN_PSK_IDENTITY MBEDTLS_SSL_ALERT_MSG_UNKNOWN_PSK_IDENTITY
+#define SSL_ALERT_MSG_UNRECOGNIZED_NAME MBEDTLS_SSL_ALERT_MSG_UNRECOGNIZED_NAME
+#define SSL_ALERT_MSG_UNSUPPORTED_CERT MBEDTLS_SSL_ALERT_MSG_UNSUPPORTED_CERT
+#define SSL_ALERT_MSG_UNSUPPORTED_EXT MBEDTLS_SSL_ALERT_MSG_UNSUPPORTED_EXT
+#define SSL_ALERT_MSG_USER_CANCELED MBEDTLS_SSL_ALERT_MSG_USER_CANCELED
+#define SSL_ANTI_REPLAY_DISABLED MBEDTLS_SSL_ANTI_REPLAY_DISABLED
+#define SSL_ANTI_REPLAY_ENABLED MBEDTLS_SSL_ANTI_REPLAY_ENABLED
+#define SSL_ARC4_DISABLED MBEDTLS_SSL_ARC4_DISABLED
+#define SSL_ARC4_ENABLED MBEDTLS_SSL_ARC4_ENABLED
+#define SSL_BUFFER_LEN MBEDTLS_SSL_BUFFER_LEN
+#define SSL_CACHE_DEFAULT_MAX_ENTRIES MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES
+#define SSL_CACHE_DEFAULT_TIMEOUT MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT
+#define SSL_CBC_RECORD_SPLITTING_DISABLED MBEDTLS_SSL_CBC_RECORD_SPLITTING_DISABLED
+#define SSL_CBC_RECORD_SPLITTING_ENABLED MBEDTLS_SSL_CBC_RECORD_SPLITTING_ENABLED
+#define SSL_CERTIFICATE_REQUEST MBEDTLS_SSL_CERTIFICATE_REQUEST
+#define SSL_CERTIFICATE_VERIFY MBEDTLS_SSL_CERTIFICATE_VERIFY
+#define SSL_CERT_TYPE_ECDSA_SIGN MBEDTLS_SSL_CERT_TYPE_ECDSA_SIGN
+#define SSL_CERT_TYPE_RSA_SIGN MBEDTLS_SSL_CERT_TYPE_RSA_SIGN
+#define SSL_CHANNEL_INBOUND MBEDTLS_SSL_CHANNEL_INBOUND
+#define SSL_CHANNEL_OUTBOUND MBEDTLS_SSL_CHANNEL_OUTBOUND
+#define SSL_CIPHERSUITES MBEDTLS_SSL_CIPHERSUITES
+#define SSL_CLIENT_CERTIFICATE MBEDTLS_SSL_CLIENT_CERTIFICATE
+#define SSL_CLIENT_CHANGE_CIPHER_SPEC MBEDTLS_SSL_CLIENT_CHANGE_CIPHER_SPEC
+#define SSL_CLIENT_FINISHED MBEDTLS_SSL_CLIENT_FINISHED
+#define SSL_CLIENT_HELLO MBEDTLS_SSL_CLIENT_HELLO
+#define SSL_CLIENT_KEY_EXCHANGE MBEDTLS_SSL_CLIENT_KEY_EXCHANGE
+#define SSL_COMPRESSION_ADD MBEDTLS_SSL_COMPRESSION_ADD
+#define SSL_COMPRESS_DEFLATE MBEDTLS_SSL_COMPRESS_DEFLATE
+#define SSL_COMPRESS_NULL MBEDTLS_SSL_COMPRESS_NULL
+#define SSL_DEBUG_BUF MBEDTLS_SSL_DEBUG_BUF
+#define SSL_DEBUG_CRT MBEDTLS_SSL_DEBUG_CRT
+#define SSL_DEBUG_ECP MBEDTLS_SSL_DEBUG_ECP
+#define SSL_DEBUG_MPI MBEDTLS_SSL_DEBUG_MPI
+#define SSL_DEBUG_MSG MBEDTLS_SSL_DEBUG_MSG
+#define SSL_DEBUG_RET MBEDTLS_SSL_DEBUG_RET
+#define SSL_DEFAULT_TICKET_LIFETIME MBEDTLS_SSL_DEFAULT_TICKET_LIFETIME
+#define SSL_DTLS_TIMEOUT_DFL_MAX MBEDTLS_SSL_DTLS_TIMEOUT_DFL_MAX
+#define SSL_DTLS_TIMEOUT_DFL_MIN MBEDTLS_SSL_DTLS_TIMEOUT_DFL_MIN
+#define SSL_EMPTY_RENEGOTIATION_INFO MBEDTLS_SSL_EMPTY_RENEGOTIATION_INFO
+#define SSL_ETM_DISABLED MBEDTLS_SSL_ETM_DISABLED
+#define SSL_ETM_ENABLED MBEDTLS_SSL_ETM_ENABLED
+#define SSL_EXTENDED_MS_DISABLED MBEDTLS_SSL_EXTENDED_MS_DISABLED
+#define SSL_EXTENDED_MS_ENABLED MBEDTLS_SSL_EXTENDED_MS_ENABLED
+#define SSL_FALLBACK_SCSV MBEDTLS_SSL_FALLBACK_SCSV
+#define SSL_FLUSH_BUFFERS MBEDTLS_SSL_FLUSH_BUFFERS
+#define SSL_HANDSHAKE_OVER MBEDTLS_SSL_HANDSHAKE_OVER
+#define SSL_HANDSHAKE_WRAPUP MBEDTLS_SSL_HANDSHAKE_WRAPUP
+#define SSL_HASH_MD5 MBEDTLS_SSL_HASH_MD5
+#define SSL_HASH_NONE MBEDTLS_SSL_HASH_NONE
+#define SSL_HASH_SHA1 MBEDTLS_SSL_HASH_SHA1
+#define SSL_HASH_SHA224 MBEDTLS_SSL_HASH_SHA224
+#define SSL_HASH_SHA256 MBEDTLS_SSL_HASH_SHA256
+#define SSL_HASH_SHA384 MBEDTLS_SSL_HASH_SHA384
+#define SSL_HASH_SHA512 MBEDTLS_SSL_HASH_SHA512
+#define SSL_HELLO_REQUEST MBEDTLS_SSL_HELLO_REQUEST
+#define SSL_HS_CERTIFICATE MBEDTLS_SSL_HS_CERTIFICATE
+#define SSL_HS_CERTIFICATE_REQUEST MBEDTLS_SSL_HS_CERTIFICATE_REQUEST
+#define SSL_HS_CERTIFICATE_VERIFY MBEDTLS_SSL_HS_CERTIFICATE_VERIFY
+#define SSL_HS_CLIENT_HELLO MBEDTLS_SSL_HS_CLIENT_HELLO
+#define SSL_HS_CLIENT_KEY_EXCHANGE MBEDTLS_SSL_HS_CLIENT_KEY_EXCHANGE
+#define SSL_HS_FINISHED MBEDTLS_SSL_HS_FINISHED
+#define SSL_HS_HELLO_REQUEST MBEDTLS_SSL_HS_HELLO_REQUEST
+#define SSL_HS_HELLO_VERIFY_REQUEST MBEDTLS_SSL_HS_HELLO_VERIFY_REQUEST
+#define SSL_HS_NEW_SESSION_TICKET MBEDTLS_SSL_HS_NEW_SESSION_TICKET
+#define SSL_HS_SERVER_HELLO MBEDTLS_SSL_HS_SERVER_HELLO
+#define SSL_HS_SERVER_HELLO_DONE MBEDTLS_SSL_HS_SERVER_HELLO_DONE
+#define SSL_HS_SERVER_KEY_EXCHANGE MBEDTLS_SSL_HS_SERVER_KEY_EXCHANGE
+#define SSL_INITIAL_HANDSHAKE MBEDTLS_SSL_INITIAL_HANDSHAKE
+#define SSL_IS_CLIENT MBEDTLS_SSL_IS_CLIENT
+#define SSL_IS_FALLBACK MBEDTLS_SSL_IS_FALLBACK
+#define SSL_IS_NOT_FALLBACK MBEDTLS_SSL_IS_NOT_FALLBACK
+#define SSL_IS_SERVER MBEDTLS_SSL_IS_SERVER
+#define SSL_LEGACY_ALLOW_RENEGOTIATION MBEDTLS_SSL_LEGACY_ALLOW_RENEGOTIATION
+#define SSL_LEGACY_BREAK_HANDSHAKE MBEDTLS_SSL_LEGACY_BREAK_HANDSHAKE
+#define SSL_LEGACY_NO_RENEGOTIATION MBEDTLS_SSL_LEGACY_NO_RENEGOTIATION
+#define SSL_LEGACY_RENEGOTIATION MBEDTLS_SSL_LEGACY_RENEGOTIATION
+#define SSL_MAC_ADD MBEDTLS_SSL_MAC_ADD
+#define SSL_MAJOR_VERSION_3 MBEDTLS_SSL_MAJOR_VERSION_3
+#define SSL_MAX_CONTENT_LEN MBEDTLS_SSL_MAX_CONTENT_LEN
+#define SSL_MAX_FRAG_LEN_1024 MBEDTLS_SSL_MAX_FRAG_LEN_1024
+#define SSL_MAX_FRAG_LEN_2048 MBEDTLS_SSL_MAX_FRAG_LEN_2048
+#define SSL_MAX_FRAG_LEN_4096 MBEDTLS_SSL_MAX_FRAG_LEN_4096
+#define SSL_MAX_FRAG_LEN_512 MBEDTLS_SSL_MAX_FRAG_LEN_512
+#define SSL_MAX_FRAG_LEN_INVALID MBEDTLS_SSL_MAX_FRAG_LEN_INVALID
+#define SSL_MAX_FRAG_LEN_NONE MBEDTLS_SSL_MAX_FRAG_LEN_NONE
+#define SSL_MAX_MAJOR_VERSION MBEDTLS_SSL_MAX_MAJOR_VERSION
+#define SSL_MAX_MINOR_VERSION MBEDTLS_SSL_MAX_MINOR_VERSION
+#define SSL_MINOR_VERSION_0 MBEDTLS_SSL_MINOR_VERSION_0
+#define SSL_MINOR_VERSION_1 MBEDTLS_SSL_MINOR_VERSION_1
+#define SSL_MINOR_VERSION_2 MBEDTLS_SSL_MINOR_VERSION_2
+#define SSL_MINOR_VERSION_3 MBEDTLS_SSL_MINOR_VERSION_3
+#define SSL_MIN_MAJOR_VERSION MBEDTLS_SSL_MIN_MAJOR_VERSION
+#define SSL_MIN_MINOR_VERSION MBEDTLS_SSL_MIN_MINOR_VERSION
+#define SSL_MSG_ALERT MBEDTLS_SSL_MSG_ALERT
+#define SSL_MSG_APPLICATION_DATA MBEDTLS_SSL_MSG_APPLICATION_DATA
+#define SSL_MSG_CHANGE_CIPHER_SPEC MBEDTLS_SSL_MSG_CHANGE_CIPHER_SPEC
+#define SSL_MSG_HANDSHAKE MBEDTLS_SSL_MSG_HANDSHAKE
+#define SSL_PADDING_ADD MBEDTLS_SSL_PADDING_ADD
+#define SSL_RENEGOTIATION MBEDTLS_SSL_RENEGOTIATION
+#define SSL_RENEGOTIATION_DISABLED MBEDTLS_SSL_RENEGOTIATION_DISABLED
+#define SSL_RENEGOTIATION_DONE MBEDTLS_SSL_RENEGOTIATION_DONE
+#define SSL_RENEGOTIATION_ENABLED MBEDTLS_SSL_RENEGOTIATION_ENABLED
+#define SSL_RENEGOTIATION_NOT_ENFORCED MBEDTLS_SSL_RENEGOTIATION_NOT_ENFORCED
+#define SSL_RENEGOTIATION_PENDING MBEDTLS_SSL_RENEGOTIATION_PENDING
+#define SSL_RENEGO_MAX_RECORDS_DEFAULT MBEDTLS_SSL_RENEGO_MAX_RECORDS_DEFAULT
+#define SSL_RETRANS_FINISHED MBEDTLS_SSL_RETRANS_FINISHED
+#define SSL_RETRANS_PREPARING MBEDTLS_SSL_RETRANS_PREPARING
+#define SSL_RETRANS_SENDING MBEDTLS_SSL_RETRANS_SENDING
+#define SSL_RETRANS_WAITING MBEDTLS_SSL_RETRANS_WAITING
+#define SSL_SECURE_RENEGOTIATION MBEDTLS_SSL_SECURE_RENEGOTIATION
+#define SSL_SERVER_CERTIFICATE MBEDTLS_SSL_SERVER_CERTIFICATE
+#define SSL_SERVER_CHANGE_CIPHER_SPEC MBEDTLS_SSL_SERVER_CHANGE_CIPHER_SPEC
+#define SSL_SERVER_FINISHED MBEDTLS_SSL_SERVER_FINISHED
+#define SSL_SERVER_HELLO MBEDTLS_SSL_SERVER_HELLO
+#define SSL_SERVER_HELLO_DONE MBEDTLS_SSL_SERVER_HELLO_DONE
+#define SSL_SERVER_HELLO_VERIFY_REQUEST_SENT MBEDTLS_SSL_SERVER_HELLO_VERIFY_REQUEST_SENT
+#define SSL_SERVER_KEY_EXCHANGE MBEDTLS_SSL_SERVER_KEY_EXCHANGE
+#define SSL_SERVER_NEW_SESSION_TICKET MBEDTLS_SSL_SERVER_NEW_SESSION_TICKET
+#define SSL_SESSION_TICKETS_DISABLED MBEDTLS_SSL_SESSION_TICKETS_DISABLED
+#define SSL_SESSION_TICKETS_ENABLED MBEDTLS_SSL_SESSION_TICKETS_ENABLED
+#define SSL_SIG_ANON MBEDTLS_SSL_SIG_ANON
+#define SSL_SIG_ECDSA MBEDTLS_SSL_SIG_ECDSA
+#define SSL_SIG_RSA MBEDTLS_SSL_SIG_RSA
+#define SSL_TRANSPORT_DATAGRAM MBEDTLS_SSL_TRANSPORT_DATAGRAM
+#define SSL_TRANSPORT_STREAM MBEDTLS_SSL_TRANSPORT_STREAM
+#define SSL_TRUNCATED_HMAC_LEN MBEDTLS_SSL_TRUNCATED_HMAC_LEN
+#define SSL_TRUNC_HMAC_DISABLED MBEDTLS_SSL_TRUNC_HMAC_DISABLED
+#define SSL_TRUNC_HMAC_ENABLED MBEDTLS_SSL_TRUNC_HMAC_ENABLED
+#define SSL_VERIFY_DATA_MAX_LEN MBEDTLS_SSL_VERIFY_DATA_MAX_LEN
+#define SSL_VERIFY_NONE MBEDTLS_SSL_VERIFY_NONE
+#define SSL_VERIFY_OPTIONAL MBEDTLS_SSL_VERIFY_OPTIONAL
+#define SSL_VERIFY_REQUIRED MBEDTLS_SSL_VERIFY_REQUIRED
+#define TLS_DHE_PSK_WITH_3DES_EDE_CBC_SHA MBEDTLS_TLS_DHE_PSK_WITH_3DES_EDE_CBC_SHA
+#define TLS_DHE_PSK_WITH_AES_128_CBC_SHA MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA
+#define TLS_DHE_PSK_WITH_AES_128_CBC_SHA256 MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA256
+#define TLS_DHE_PSK_WITH_AES_128_CCM MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CCM
+#define TLS_DHE_PSK_WITH_AES_128_CCM_8 MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CCM_8
+#define TLS_DHE_PSK_WITH_AES_128_GCM_SHA256 MBEDTLS_TLS_DHE_PSK_WITH_AES_128_GCM_SHA256
+#define TLS_DHE_PSK_WITH_AES_256_CBC_SHA MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA
+#define TLS_DHE_PSK_WITH_AES_256_CBC_SHA384 MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA384
+#define TLS_DHE_PSK_WITH_AES_256_CCM MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CCM
+#define TLS_DHE_PSK_WITH_AES_256_CCM_8 MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CCM_8
+#define TLS_DHE_PSK_WITH_AES_256_GCM_SHA384 MBEDTLS_TLS_DHE_PSK_WITH_AES_256_GCM_SHA384
+#define TLS_DHE_PSK_WITH_CAMELLIA_128_CBC_SHA256 MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_CBC_SHA256
+#define TLS_DHE_PSK_WITH_CAMELLIA_128_GCM_SHA256 MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_GCM_SHA256
+#define TLS_DHE_PSK_WITH_CAMELLIA_256_CBC_SHA384 MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_CBC_SHA384
+#define TLS_DHE_PSK_WITH_CAMELLIA_256_GCM_SHA384 MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_GCM_SHA384
+#define TLS_DHE_PSK_WITH_NULL_SHA MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA
+#define TLS_DHE_PSK_WITH_NULL_SHA256 MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA256
+#define TLS_DHE_PSK_WITH_NULL_SHA384 MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA384
+#define TLS_DHE_PSK_WITH_RC4_128_SHA MBEDTLS_TLS_DHE_PSK_WITH_RC4_128_SHA
+#define TLS_DHE_RSA_WITH_3DES_EDE_CBC_SHA MBEDTLS_TLS_DHE_RSA_WITH_3DES_EDE_CBC_SHA
+#define TLS_DHE_RSA_WITH_AES_128_CBC_SHA MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA
+#define TLS_DHE_RSA_WITH_AES_128_CBC_SHA256 MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA256
+#define TLS_DHE_RSA_WITH_AES_128_CCM MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CCM
+#define TLS_DHE_RSA_WITH_AES_128_CCM_8 MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CCM_8
+#define TLS_DHE_RSA_WITH_AES_128_GCM_SHA256 MBEDTLS_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256
+#define TLS_DHE_RSA_WITH_AES_256_CBC_SHA MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA
+#define TLS_DHE_RSA_WITH_AES_256_CBC_SHA256 MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA256
+#define TLS_DHE_RSA_WITH_AES_256_CCM MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CCM
+#define TLS_DHE_RSA_WITH_AES_256_CCM_8 MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CCM_8
+#define TLS_DHE_RSA_WITH_AES_256_GCM_SHA384 MBEDTLS_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384
+#define TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA
+#define TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256 MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256
+#define TLS_DHE_RSA_WITH_CAMELLIA_128_GCM_SHA256 MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_GCM_SHA256
+#define TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA
+#define TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256 MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256
+#define TLS_DHE_RSA_WITH_CAMELLIA_256_GCM_SHA384 MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_GCM_SHA384
+#define TLS_DHE_RSA_WITH_DES_CBC_SHA MBEDTLS_TLS_DHE_RSA_WITH_DES_CBC_SHA
+#define TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA MBEDTLS_TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA
+#define TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA
+#define TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256
+#define TLS_ECDHE_ECDSA_WITH_AES_128_CCM MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CCM
+#define TLS_ECDHE_ECDSA_WITH_AES_128_CCM_8 MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CCM_8
+#define TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256
+#define TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA
+#define TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384 MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384
+#define TLS_ECDHE_ECDSA_WITH_AES_256_CCM MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CCM
+#define TLS_ECDHE_ECDSA_WITH_AES_256_CCM_8 MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CCM_8
+#define TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384 MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384
+#define TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_CBC_SHA256 MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_CBC_SHA256
+#define TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_GCM_SHA256 MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_GCM_SHA256
+#define TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_CBC_SHA384 MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_CBC_SHA384
+#define TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_GCM_SHA384 MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_GCM_SHA384
+#define TLS_ECDHE_ECDSA_WITH_NULL_SHA MBEDTLS_TLS_ECDHE_ECDSA_WITH_NULL_SHA
+#define TLS_ECDHE_ECDSA_WITH_RC4_128_SHA MBEDTLS_TLS_ECDHE_ECDSA_WITH_RC4_128_SHA
+#define TLS_ECDHE_PSK_WITH_3DES_EDE_CBC_SHA MBEDTLS_TLS_ECDHE_PSK_WITH_3DES_EDE_CBC_SHA
+#define TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA
+#define TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA256 MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA256
+#define TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA
+#define TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA384 MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA384
+#define TLS_ECDHE_PSK_WITH_CAMELLIA_128_CBC_SHA256 MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_128_CBC_SHA256
+#define TLS_ECDHE_PSK_WITH_CAMELLIA_256_CBC_SHA384 MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_256_CBC_SHA384
+#define TLS_ECDHE_PSK_WITH_NULL_SHA MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA
+#define TLS_ECDHE_PSK_WITH_NULL_SHA256 MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA256
+#define TLS_ECDHE_PSK_WITH_NULL_SHA384 MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA384
+#define TLS_ECDHE_PSK_WITH_RC4_128_SHA MBEDTLS_TLS_ECDHE_PSK_WITH_RC4_128_SHA
+#define TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA MBEDTLS_TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA
+#define TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA
+#define TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256 MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256
+#define TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256
+#define TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA
+#define TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384 MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384
+#define TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384
+#define TLS_ECDHE_RSA_WITH_CAMELLIA_128_CBC_SHA256 MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_CBC_SHA256
+#define TLS_ECDHE_RSA_WITH_CAMELLIA_128_GCM_SHA256 MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_GCM_SHA256
+#define TLS_ECDHE_RSA_WITH_CAMELLIA_256_CBC_SHA384 MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_CBC_SHA384
+#define TLS_ECDHE_RSA_WITH_CAMELLIA_256_GCM_SHA384 MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_GCM_SHA384
+#define TLS_ECDHE_RSA_WITH_NULL_SHA MBEDTLS_TLS_ECDHE_RSA_WITH_NULL_SHA
+#define TLS_ECDHE_RSA_WITH_RC4_128_SHA MBEDTLS_TLS_ECDHE_RSA_WITH_RC4_128_SHA
+#define TLS_ECDH_ECDSA_WITH_3DES_EDE_CBC_SHA MBEDTLS_TLS_ECDH_ECDSA_WITH_3DES_EDE_CBC_SHA
+#define TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA
+#define TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256 MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256
+#define TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256 MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256
+#define TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA
+#define TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384 MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384
+#define TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384 MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384
+#define TLS_ECDH_ECDSA_WITH_CAMELLIA_128_CBC_SHA256 MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_CBC_SHA256
+#define TLS_ECDH_ECDSA_WITH_CAMELLIA_128_GCM_SHA256 MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_GCM_SHA256
+#define TLS_ECDH_ECDSA_WITH_CAMELLIA_256_CBC_SHA384 MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_CBC_SHA384
+#define TLS_ECDH_ECDSA_WITH_CAMELLIA_256_GCM_SHA384 MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_GCM_SHA384
+#define TLS_ECDH_ECDSA_WITH_NULL_SHA MBEDTLS_TLS_ECDH_ECDSA_WITH_NULL_SHA
+#define TLS_ECDH_ECDSA_WITH_RC4_128_SHA MBEDTLS_TLS_ECDH_ECDSA_WITH_RC4_128_SHA
+#define TLS_ECDH_RSA_WITH_3DES_EDE_CBC_SHA MBEDTLS_TLS_ECDH_RSA_WITH_3DES_EDE_CBC_SHA
+#define TLS_ECDH_RSA_WITH_AES_128_CBC_SHA MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA
+#define TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256 MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256
+#define TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256 MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256
+#define TLS_ECDH_RSA_WITH_AES_256_CBC_SHA MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA
+#define TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384 MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384
+#define TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384 MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384
+#define TLS_ECDH_RSA_WITH_CAMELLIA_128_CBC_SHA256 MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_CBC_SHA256
+#define TLS_ECDH_RSA_WITH_CAMELLIA_128_GCM_SHA256 MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_GCM_SHA256
+#define TLS_ECDH_RSA_WITH_CAMELLIA_256_CBC_SHA384 MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_CBC_SHA384
+#define TLS_ECDH_RSA_WITH_CAMELLIA_256_GCM_SHA384 MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_GCM_SHA384
+#define TLS_ECDH_RSA_WITH_NULL_SHA MBEDTLS_TLS_ECDH_RSA_WITH_NULL_SHA
+#define TLS_ECDH_RSA_WITH_RC4_128_SHA MBEDTLS_TLS_ECDH_RSA_WITH_RC4_128_SHA
+#define TLS_EXT_ALPN MBEDTLS_TLS_EXT_ALPN
+#define TLS_EXT_ENCRYPT_THEN_MAC MBEDTLS_TLS_EXT_ENCRYPT_THEN_MAC
+#define TLS_EXT_EXTENDED_MASTER_SECRET MBEDTLS_TLS_EXT_EXTENDED_MASTER_SECRET
+#define TLS_EXT_MAX_FRAGMENT_LENGTH MBEDTLS_TLS_EXT_MAX_FRAGMENT_LENGTH
+#define TLS_EXT_RENEGOTIATION_INFO MBEDTLS_TLS_EXT_RENEGOTIATION_INFO
+#define TLS_EXT_SERVERNAME MBEDTLS_TLS_EXT_SERVERNAME
+#define TLS_EXT_SERVERNAME_HOSTNAME MBEDTLS_TLS_EXT_SERVERNAME_HOSTNAME
+#define TLS_EXT_SESSION_TICKET MBEDTLS_TLS_EXT_SESSION_TICKET
+#define TLS_EXT_SIG_ALG MBEDTLS_TLS_EXT_SIG_ALG
+#define TLS_EXT_SUPPORTED_ELLIPTIC_CURVES MBEDTLS_TLS_EXT_SUPPORTED_ELLIPTIC_CURVES
+#define TLS_EXT_SUPPORTED_POINT_FORMATS MBEDTLS_TLS_EXT_SUPPORTED_POINT_FORMATS
+#define TLS_EXT_SUPPORTED_POINT_FORMATS_PRESENT MBEDTLS_TLS_EXT_SUPPORTED_POINT_FORMATS_PRESENT
+#define TLS_EXT_TRUNCATED_HMAC MBEDTLS_TLS_EXT_TRUNCATED_HMAC
+#define TLS_PSK_WITH_3DES_EDE_CBC_SHA MBEDTLS_TLS_PSK_WITH_3DES_EDE_CBC_SHA
+#define TLS_PSK_WITH_AES_128_CBC_SHA MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA
+#define TLS_PSK_WITH_AES_128_CBC_SHA256 MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA256
+#define TLS_PSK_WITH_AES_128_CCM MBEDTLS_TLS_PSK_WITH_AES_128_CCM
+#define TLS_PSK_WITH_AES_128_CCM_8 MBEDTLS_TLS_PSK_WITH_AES_128_CCM_8
+#define TLS_PSK_WITH_AES_128_GCM_SHA256 MBEDTLS_TLS_PSK_WITH_AES_128_GCM_SHA256
+#define TLS_PSK_WITH_AES_256_CBC_SHA MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA
+#define TLS_PSK_WITH_AES_256_CBC_SHA384 MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA384
+#define TLS_PSK_WITH_AES_256_CCM MBEDTLS_TLS_PSK_WITH_AES_256_CCM
+#define TLS_PSK_WITH_AES_256_CCM_8 MBEDTLS_TLS_PSK_WITH_AES_256_CCM_8
+#define TLS_PSK_WITH_AES_256_GCM_SHA384 MBEDTLS_TLS_PSK_WITH_AES_256_GCM_SHA384
+#define TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256 MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256
+#define TLS_PSK_WITH_CAMELLIA_128_GCM_SHA256 MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_GCM_SHA256
+#define TLS_PSK_WITH_CAMELLIA_256_CBC_SHA384 MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_CBC_SHA384
+#define TLS_PSK_WITH_CAMELLIA_256_GCM_SHA384 MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_GCM_SHA384
+#define TLS_PSK_WITH_NULL_SHA MBEDTLS_TLS_PSK_WITH_NULL_SHA
+#define TLS_PSK_WITH_NULL_SHA256 MBEDTLS_TLS_PSK_WITH_NULL_SHA256
+#define TLS_PSK_WITH_NULL_SHA384 MBEDTLS_TLS_PSK_WITH_NULL_SHA384
+#define TLS_PSK_WITH_RC4_128_SHA MBEDTLS_TLS_PSK_WITH_RC4_128_SHA
+#define TLS_RSA_PSK_WITH_3DES_EDE_CBC_SHA MBEDTLS_TLS_RSA_PSK_WITH_3DES_EDE_CBC_SHA
+#define TLS_RSA_PSK_WITH_AES_128_CBC_SHA MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA
+#define TLS_RSA_PSK_WITH_AES_128_CBC_SHA256 MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA256
+#define TLS_RSA_PSK_WITH_AES_128_GCM_SHA256 MBEDTLS_TLS_RSA_PSK_WITH_AES_128_GCM_SHA256
+#define TLS_RSA_PSK_WITH_AES_256_CBC_SHA MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA
+#define TLS_RSA_PSK_WITH_AES_256_CBC_SHA384 MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA384
+#define TLS_RSA_PSK_WITH_AES_256_GCM_SHA384 MBEDTLS_TLS_RSA_PSK_WITH_AES_256_GCM_SHA384
+#define TLS_RSA_PSK_WITH_CAMELLIA_128_CBC_SHA256 MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_CBC_SHA256
+#define TLS_RSA_PSK_WITH_CAMELLIA_128_GCM_SHA256 MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_GCM_SHA256
+#define TLS_RSA_PSK_WITH_CAMELLIA_256_CBC_SHA384 MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_CBC_SHA384
+#define TLS_RSA_PSK_WITH_CAMELLIA_256_GCM_SHA384 MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_GCM_SHA384
+#define TLS_RSA_PSK_WITH_NULL_SHA MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA
+#define TLS_RSA_PSK_WITH_NULL_SHA256 MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA256
+#define TLS_RSA_PSK_WITH_NULL_SHA384 MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA384
+#define TLS_RSA_PSK_WITH_RC4_128_SHA MBEDTLS_TLS_RSA_PSK_WITH_RC4_128_SHA
+#define TLS_RSA_WITH_3DES_EDE_CBC_SHA MBEDTLS_TLS_RSA_WITH_3DES_EDE_CBC_SHA
+#define TLS_RSA_WITH_AES_128_CBC_SHA MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA
+#define TLS_RSA_WITH_AES_128_CBC_SHA256 MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA256
+#define TLS_RSA_WITH_AES_128_CCM MBEDTLS_TLS_RSA_WITH_AES_128_CCM
+#define TLS_RSA_WITH_AES_128_CCM_8 MBEDTLS_TLS_RSA_WITH_AES_128_CCM_8
+#define TLS_RSA_WITH_AES_128_GCM_SHA256 MBEDTLS_TLS_RSA_WITH_AES_128_GCM_SHA256
+#define TLS_RSA_WITH_AES_256_CBC_SHA MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA
+#define TLS_RSA_WITH_AES_256_CBC_SHA256 MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA256
+#define TLS_RSA_WITH_AES_256_CCM MBEDTLS_TLS_RSA_WITH_AES_256_CCM
+#define TLS_RSA_WITH_AES_256_CCM_8 MBEDTLS_TLS_RSA_WITH_AES_256_CCM_8
+#define TLS_RSA_WITH_AES_256_GCM_SHA384 MBEDTLS_TLS_RSA_WITH_AES_256_GCM_SHA384
+#define TLS_RSA_WITH_CAMELLIA_128_CBC_SHA MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA
+#define TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256 MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256
+#define TLS_RSA_WITH_CAMELLIA_128_GCM_SHA256 MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_GCM_SHA256
+#define TLS_RSA_WITH_CAMELLIA_256_CBC_SHA MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA
+#define TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256 MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256
+#define TLS_RSA_WITH_CAMELLIA_256_GCM_SHA384 MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_GCM_SHA384
+#define TLS_RSA_WITH_DES_CBC_SHA MBEDTLS_TLS_RSA_WITH_DES_CBC_SHA
+#define TLS_RSA_WITH_NULL_MD5 MBEDTLS_TLS_RSA_WITH_NULL_MD5
+#define TLS_RSA_WITH_NULL_SHA MBEDTLS_TLS_RSA_WITH_NULL_SHA
+#define TLS_RSA_WITH_NULL_SHA256 MBEDTLS_TLS_RSA_WITH_NULL_SHA256
+#define TLS_RSA_WITH_RC4_128_MD5 MBEDTLS_TLS_RSA_WITH_RC4_128_MD5
+#define TLS_RSA_WITH_RC4_128_SHA MBEDTLS_TLS_RSA_WITH_RC4_128_SHA
+#define UL64 MBEDTLS_UL64
+#define X509_CRT_VERSION_1 MBEDTLS_X509_CRT_VERSION_1
+#define X509_CRT_VERSION_2 MBEDTLS_X509_CRT_VERSION_2
+#define X509_CRT_VERSION_3 MBEDTLS_X509_CRT_VERSION_3
+#define X509_FORMAT_DER MBEDTLS_X509_FORMAT_DER
+#define X509_FORMAT_PEM MBEDTLS_X509_FORMAT_PEM
+#define X509_MAX_DN_NAME_SIZE MBEDTLS_X509_MAX_DN_NAME_SIZE
+#define X509_RFC5280_MAX_SERIAL_LEN MBEDTLS_X509_RFC5280_MAX_SERIAL_LEN
+#define X509_RFC5280_UTC_TIME_LEN MBEDTLS_X509_RFC5280_UTC_TIME_LEN
+#define XTEA_DECRYPT MBEDTLS_XTEA_DECRYPT
+#define XTEA_ENCRYPT MBEDTLS_XTEA_ENCRYPT
+#define _asn1_bitstring mbedtls_asn1_bitstring
+#define _asn1_buf mbedtls_asn1_buf
+#define _asn1_named_data mbedtls_asn1_named_data
+#define _asn1_sequence mbedtls_asn1_sequence
+#define _ssl_cache_context mbedtls_ssl_cache_context
+#define _ssl_cache_entry mbedtls_ssl_cache_entry
+#define _ssl_ciphersuite_t mbedtls_ssl_ciphersuite_t
+#define _ssl_context mbedtls_ssl_context
+#define _ssl_flight_item mbedtls_ssl_flight_item
+#define _ssl_handshake_params mbedtls_ssl_handshake_params
+#define _ssl_key_cert mbedtls_ssl_key_cert
+#define _ssl_premaster_secret mbedtls_ssl_premaster_secret
+#define _ssl_session mbedtls_ssl_session
+#define _ssl_ticket_keys mbedtls_ssl_ticket_keys
+#define _ssl_transform mbedtls_ssl_transform
+#define _x509_crl mbedtls_x509_crl
+#define _x509_crl_entry mbedtls_x509_crl_entry
+#define _x509_crt mbedtls_x509_crt
+#define _x509_csr mbedtls_x509_csr
+#define _x509_time mbedtls_x509_time
+#define _x509write_cert mbedtls_x509write_cert
+#define _x509write_csr mbedtls_x509write_csr
+#define aes_context mbedtls_aes_context
+#define aes_crypt_cbc mbedtls_aes_crypt_cbc
+#define aes_crypt_cfb128 mbedtls_aes_crypt_cfb128
+#define aes_crypt_cfb8 mbedtls_aes_crypt_cfb8
+#define aes_crypt_ctr mbedtls_aes_crypt_ctr
+#define aes_crypt_ecb mbedtls_aes_crypt_ecb
+#define aes_free mbedtls_aes_free
+#define aes_init mbedtls_aes_init
+#define aes_self_test mbedtls_aes_self_test
+#define aes_setkey_dec mbedtls_aes_setkey_dec
+#define aes_setkey_enc mbedtls_aes_setkey_enc
+#define aesni_crypt_ecb mbedtls_aesni_crypt_ecb
+#define aesni_gcm_mult mbedtls_aesni_gcm_mult
+#define aesni_inverse_key mbedtls_aesni_inverse_key
+#define aesni_setkey_enc mbedtls_aesni_setkey_enc
+#define aesni_supports mbedtls_aesni_has_support
+#define alarmed mbedtls_timing_alarmed
+#define arc4_context mbedtls_arc4_context
+#define arc4_crypt mbedtls_arc4_crypt
+#define arc4_free mbedtls_arc4_free
+#define arc4_init mbedtls_arc4_init
+#define arc4_self_test mbedtls_arc4_self_test
+#define arc4_setup mbedtls_arc4_setup
+#define asn1_bitstring mbedtls_asn1_bitstring
+#define asn1_buf mbedtls_asn1_buf
+#define asn1_find_named_data mbedtls_asn1_find_named_data
+#define asn1_free_named_data mbedtls_asn1_free_named_data
+#define asn1_free_named_data_list mbedtls_asn1_free_named_data_list
+#define asn1_get_alg mbedtls_asn1_get_alg
+#define asn1_get_alg_null mbedtls_asn1_get_alg_null
+#define asn1_get_bitstring mbedtls_asn1_get_bitstring
+#define asn1_get_bitstring_null mbedtls_asn1_get_bitstring_null
+#define asn1_get_bool mbedtls_asn1_get_bool
+#define asn1_get_int mbedtls_asn1_get_int
+#define asn1_get_len mbedtls_asn1_get_len
+#define asn1_get_mpi mbedtls_asn1_get_mpi
+#define asn1_get_sequence_of mbedtls_asn1_get_sequence_of
+#define asn1_get_tag mbedtls_asn1_get_tag
+#define asn1_named_data mbedtls_asn1_named_data
+#define asn1_sequence mbedtls_asn1_sequence
+#define asn1_store_named_data mbedtls_asn1_store_named_data
+#define asn1_write_algorithm_identifier mbedtls_asn1_write_algorithm_identifier
+#define asn1_write_bitstring mbedtls_asn1_write_bitstring
+#define asn1_write_bool mbedtls_asn1_write_bool
+#define asn1_write_ia5_string mbedtls_asn1_write_ia5_string
+#define asn1_write_int mbedtls_asn1_write_int
+#define asn1_write_len mbedtls_asn1_write_len
+#define asn1_write_mpi mbedtls_asn1_write_mpi
+#define asn1_write_null mbedtls_asn1_write_null
+#define asn1_write_octet_string mbedtls_asn1_write_octet_string
+#define asn1_write_oid mbedtls_asn1_write_oid
+#define asn1_write_printable_string mbedtls_asn1_write_printable_string
+#define asn1_write_raw_buffer mbedtls_asn1_write_raw_buffer
+#define asn1_write_tag mbedtls_asn1_write_tag
+#define base64_decode mbedtls_base64_decode
+#define base64_encode mbedtls_base64_encode
+#define base64_self_test mbedtls_base64_self_test
+#define blowfish_context mbedtls_blowfish_context
+#define blowfish_crypt_cbc mbedtls_blowfish_crypt_cbc
+#define blowfish_crypt_cfb64 mbedtls_blowfish_crypt_cfb64
+#define blowfish_crypt_ctr mbedtls_blowfish_crypt_ctr
+#define blowfish_crypt_ecb mbedtls_blowfish_crypt_ecb
+#define blowfish_free mbedtls_blowfish_free
+#define blowfish_init mbedtls_blowfish_init
+#define blowfish_setkey mbedtls_blowfish_setkey
+#define camellia_context mbedtls_camellia_context
+#define camellia_crypt_cbc mbedtls_camellia_crypt_cbc
+#define camellia_crypt_cfb128 mbedtls_camellia_crypt_cfb128
+#define camellia_crypt_ctr mbedtls_camellia_crypt_ctr
+#define camellia_crypt_ecb mbedtls_camellia_crypt_ecb
+#define camellia_free mbedtls_camellia_free
+#define camellia_init mbedtls_camellia_init
+#define camellia_self_test mbedtls_camellia_self_test
+#define camellia_setkey_dec mbedtls_camellia_setkey_dec
+#define camellia_setkey_enc mbedtls_camellia_setkey_enc
+#define ccm_auth_decrypt mbedtls_ccm_auth_decrypt
+#define ccm_context mbedtls_ccm_context
+#define ccm_encrypt_and_tag mbedtls_ccm_encrypt_and_tag
+#define ccm_free mbedtls_ccm_free
+#define ccm_init mbedtls_ccm_init
+#define ccm_self_test mbedtls_ccm_self_test
+#define cipher_auth_decrypt mbedtls_cipher_auth_decrypt
+#define cipher_auth_encrypt mbedtls_cipher_auth_encrypt
+#define cipher_base_t mbedtls_cipher_base_t
+#define cipher_check_tag mbedtls_cipher_check_tag
+#define cipher_context_t mbedtls_cipher_context_t
+#define cipher_crypt mbedtls_cipher_crypt
+#define cipher_definition_t mbedtls_cipher_definition_t
+#define cipher_definitions mbedtls_cipher_definitions
+#define cipher_finish mbedtls_cipher_finish
+#define cipher_free mbedtls_cipher_free
+#define cipher_free_ctx mbedtls_cipher_free_ctx
+#define cipher_get_block_size mbedtls_cipher_get_block_size
+#define cipher_get_cipher_mode mbedtls_cipher_get_cipher_mode
+#define cipher_get_iv_size mbedtls_cipher_get_iv_size
+#define cipher_get_key_size mbedtls_cipher_get_key_bitlen
+#define cipher_get_name mbedtls_cipher_get_name
+#define cipher_get_operation mbedtls_cipher_get_operation
+#define cipher_get_type mbedtls_cipher_get_type
+#define cipher_id_t mbedtls_cipher_id_t
+#define cipher_info_from_string mbedtls_cipher_info_from_string
+#define cipher_info_from_type mbedtls_cipher_info_from_type
+#define cipher_info_from_values mbedtls_cipher_info_from_values
+#define cipher_info_t mbedtls_cipher_info_t
+#define cipher_init mbedtls_cipher_init
+#define cipher_init_ctx mbedtls_cipher_setup
+#define cipher_list mbedtls_cipher_list
+#define cipher_mode_t mbedtls_cipher_mode_t
+#define cipher_padding_t mbedtls_cipher_padding_t
+#define cipher_reset mbedtls_cipher_reset
+#define cipher_self_test mbedtls_cipher_self_test
+#define cipher_set_iv mbedtls_cipher_set_iv
+#define cipher_set_padding_mode mbedtls_cipher_set_padding_mode
+#define cipher_setkey mbedtls_cipher_setkey
+#define cipher_type_t mbedtls_cipher_type_t
+#define cipher_update mbedtls_cipher_update
+#define cipher_update_ad mbedtls_cipher_update_ad
+#define cipher_write_tag mbedtls_cipher_write_tag
+#define ctr_drbg_context mbedtls_ctr_drbg_context
+#define ctr_drbg_free mbedtls_ctr_drbg_free
+#define ctr_drbg_init mbedtls_ctr_drbg_init
+#define ctr_drbg_init_entropy_len mbedtls_ctr_drbg_init_entropy_len
+#define ctr_drbg_random mbedtls_ctr_drbg_random
+#define ctr_drbg_random_with_add mbedtls_ctr_drbg_random_with_add
+#define ctr_drbg_reseed mbedtls_ctr_drbg_reseed
+#define ctr_drbg_self_test mbedtls_ctr_drbg_self_test
+#define ctr_drbg_set_entropy_len mbedtls_ctr_drbg_set_entropy_len
+#define ctr_drbg_set_prediction_resistance mbedtls_ctr_drbg_set_prediction_resistance
+#define ctr_drbg_set_reseed_interval mbedtls_ctr_drbg_set_reseed_interval
+#define ctr_drbg_update mbedtls_ctr_drbg_update
+#define ctr_drbg_update_seed_file mbedtls_ctr_drbg_update_seed_file
+#define ctr_drbg_write_seed_file mbedtls_ctr_drbg_write_seed_file
+#define debug_fmt mbedtls_debug_fmt
+#define debug_print_buf mbedtls_debug_print_buf
+#define debug_print_crt mbedtls_debug_print_crt
+#define debug_print_ecp mbedtls_debug_print_ecp
+#define debug_print_mpi mbedtls_debug_print_mpi
+#define debug_print_msg mbedtls_debug_print_msg
+#define debug_print_ret mbedtls_debug_print_ret
+#define debug_set_log_mode mbedtls_debug_set_log_mode
+#define debug_set_threshold mbedtls_debug_set_threshold
+#define des3_context mbedtls_des3_context
+#define des3_crypt_cbc mbedtls_des3_crypt_cbc
+#define des3_crypt_ecb mbedtls_des3_crypt_ecb
+#define des3_free mbedtls_des3_free
+#define des3_init mbedtls_des3_init
+#define des3_set2key_dec mbedtls_des3_set2key_dec
+#define des3_set2key_enc mbedtls_des3_set2key_enc
+#define des3_set3key_dec mbedtls_des3_set3key_dec
+#define des3_set3key_enc mbedtls_des3_set3key_enc
+#define des_context mbedtls_des_context
+#define des_crypt_cbc mbedtls_des_crypt_cbc
+#define des_crypt_ecb mbedtls_des_crypt_ecb
+#define des_free mbedtls_des_free
+#define des_init mbedtls_des_init
+#define des_key_check_key_parity mbedtls_des_key_check_key_parity
+#define des_key_check_weak mbedtls_des_key_check_weak
+#define des_key_set_parity mbedtls_des_key_set_parity
+#define des_self_test mbedtls_des_self_test
+#define des_setkey_dec mbedtls_des_setkey_dec
+#define des_setkey_enc mbedtls_des_setkey_enc
+#define dhm_calc_secret mbedtls_dhm_calc_secret
+#define dhm_context mbedtls_dhm_context
+#define dhm_free mbedtls_dhm_free
+#define dhm_init mbedtls_dhm_init
+#define dhm_make_params mbedtls_dhm_make_params
+#define dhm_make_public mbedtls_dhm_make_public
+#define dhm_parse_dhm mbedtls_dhm_parse_dhm
+#define dhm_parse_dhmfile mbedtls_dhm_parse_dhmfile
+#define dhm_read_params mbedtls_dhm_read_params
+#define dhm_read_public mbedtls_dhm_read_public
+#define dhm_self_test mbedtls_dhm_self_test
+#define ecdh_calc_secret mbedtls_ecdh_calc_secret
+#define ecdh_compute_shared mbedtls_ecdh_compute_shared
+#define ecdh_context mbedtls_ecdh_context
+#define ecdh_free mbedtls_ecdh_free
+#define ecdh_gen_public mbedtls_ecdh_gen_public
+#define ecdh_get_params mbedtls_ecdh_get_params
+#define ecdh_init mbedtls_ecdh_init
+#define ecdh_make_params mbedtls_ecdh_make_params
+#define ecdh_make_public mbedtls_ecdh_make_public
+#define ecdh_read_params mbedtls_ecdh_read_params
+#define ecdh_read_public mbedtls_ecdh_read_public
+#define ecdh_self_test mbedtls_ecdh_self_test
+#define ecdh_side mbedtls_ecdh_side
+#define ecdsa_context mbedtls_ecdsa_context
+#define ecdsa_free mbedtls_ecdsa_free
+#define ecdsa_from_keypair mbedtls_ecdsa_from_keypair
+#define ecdsa_genkey mbedtls_ecdsa_genkey
+#define ecdsa_info mbedtls_ecdsa_info
+#define ecdsa_init mbedtls_ecdsa_init
+#define ecdsa_read_signature mbedtls_ecdsa_read_signature
+#define ecdsa_self_test mbedtls_ecdsa_self_test
+#define ecdsa_sign mbedtls_ecdsa_sign
+#define ecdsa_sign_det mbedtls_ecdsa_sign_det
+#define ecdsa_verify mbedtls_ecdsa_verify
+#define ecdsa_write_signature mbedtls_ecdsa_write_signature
+#define ecdsa_write_signature_det mbedtls_ecdsa_write_signature_det
+#define eckey_info mbedtls_eckey_info
+#define eckeydh_info mbedtls_eckeydh_info
+#define ecp_add mbedtls_ecp_add
+#define ecp_check_privkey mbedtls_ecp_check_privkey
+#define ecp_check_pub_priv mbedtls_ecp_check_pub_priv
+#define ecp_check_pubkey mbedtls_ecp_check_pubkey
+#define ecp_copy mbedtls_ecp_copy
+#define ecp_curve_info mbedtls_ecp_curve_info
+#define ecp_curve_info_from_grp_id mbedtls_ecp_curve_info_from_grp_id
+#define ecp_curve_info_from_name mbedtls_ecp_curve_info_from_name
+#define ecp_curve_info_from_tls_id mbedtls_ecp_curve_info_from_tls_id
+#define ecp_curve_list mbedtls_ecp_curve_list
+#define ecp_gen_key mbedtls_ecp_gen_key
+#define ecp_gen_keypair mbedtls_ecp_gen_keypair
+#define ecp_group mbedtls_ecp_group
+#define ecp_group_copy mbedtls_ecp_group_copy
+#define ecp_group_free mbedtls_ecp_group_free
+#define ecp_group_id mbedtls_ecp_group_id
+#define ecp_group_init mbedtls_ecp_group_init
+#define ecp_group_read_string mbedtls_ecp_group_read_string
+#define ecp_grp_id_list mbedtls_ecp_grp_id_list
+#define ecp_is_zero mbedtls_ecp_is_zero
+#define ecp_keypair mbedtls_ecp_keypair
+#define ecp_keypair_free mbedtls_ecp_keypair_free
+#define ecp_keypair_init mbedtls_ecp_keypair_init
+#define ecp_mul mbedtls_ecp_mul
+#define ecp_point mbedtls_ecp_point
+#define ecp_point_free mbedtls_ecp_point_free
+#define ecp_point_init mbedtls_ecp_point_init
+#define ecp_point_read_binary mbedtls_ecp_point_read_binary
+#define ecp_point_read_string mbedtls_ecp_point_read_string
+#define ecp_point_write_binary mbedtls_ecp_point_write_binary
+#define ecp_self_test mbedtls_ecp_self_test
+#define ecp_set_zero mbedtls_ecp_set_zero
+#define ecp_sub mbedtls_ecp_sub
+#define ecp_tls_read_group mbedtls_ecp_tls_read_group
+#define ecp_tls_read_point mbedtls_ecp_tls_read_point
+#define ecp_tls_write_group mbedtls_ecp_tls_write_group
+#define ecp_tls_write_point mbedtls_ecp_tls_write_point
+#define ecp_use_known_dp mbedtls_ecp_group_load
+#define entropy_add_source mbedtls_entropy_add_source
+#define entropy_context mbedtls_entropy_context
+#define entropy_free mbedtls_entropy_free
+#define entropy_func mbedtls_entropy_func
+#define entropy_gather mbedtls_entropy_gather
+#define entropy_init mbedtls_entropy_init
+#define entropy_self_test mbedtls_entropy_self_test
+#define entropy_update_manual mbedtls_entropy_update_manual
+#define entropy_update_seed_file mbedtls_entropy_update_seed_file
+#define entropy_write_seed_file mbedtls_entropy_write_seed_file
+#define error_strerror mbedtls_strerror
+#define f_source_ptr mbedtls_entropy_f_source_ptr
+#define gcm_auth_decrypt mbedtls_gcm_auth_decrypt
+#define gcm_context mbedtls_gcm_context
+#define gcm_crypt_and_tag mbedtls_gcm_crypt_and_tag
+#define gcm_finish mbedtls_gcm_finish
+#define gcm_free mbedtls_gcm_free
+#define gcm_init mbedtls_gcm_init
+#define gcm_self_test mbedtls_gcm_self_test
+#define gcm_starts mbedtls_gcm_starts
+#define gcm_update mbedtls_gcm_update
+#define get_timer mbedtls_timing_get_timer
+#define hardclock mbedtls_timing_hardclock
+#define hardclock_poll mbedtls_hardclock_poll
+#define havege_free mbedtls_havege_free
+#define havege_init mbedtls_havege_init
+#define havege_poll mbedtls_havege_poll
+#define havege_random mbedtls_havege_random
+#define havege_state mbedtls_havege_state
+#define hmac_drbg_context mbedtls_hmac_drbg_context
+#define hmac_drbg_free mbedtls_hmac_drbg_free
+#define hmac_drbg_init mbedtls_hmac_drbg_init
+#define hmac_drbg_init_buf mbedtls_hmac_drbg_init_buf
+#define hmac_drbg_random mbedtls_hmac_drbg_random
+#define hmac_drbg_random_with_add mbedtls_hmac_drbg_random_with_add
+#define hmac_drbg_reseed mbedtls_hmac_drbg_reseed
+#define hmac_drbg_self_test mbedtls_hmac_drbg_self_test
+#define hmac_drbg_set_entropy_len mbedtls_hmac_drbg_set_entropy_len
+#define hmac_drbg_set_prediction_resistance mbedtls_hmac_drbg_set_prediction_resistance
+#define hmac_drbg_set_reseed_interval mbedtls_hmac_drbg_set_reseed_interval
+#define hmac_drbg_update mbedtls_hmac_drbg_update
+#define hmac_drbg_update_seed_file mbedtls_hmac_drbg_update_seed_file
+#define hmac_drbg_write_seed_file mbedtls_hmac_drbg_write_seed_file
+#define hr_time mbedtls_timing_hr_time
+#define key_exchange_type_t mbedtls_key_exchange_type_t
+#define md mbedtls_md
+#define md2 mbedtls_md2
+#define md2_context mbedtls_md2_context
+#define md2_file mbedtls_md2_file
+#define md2_finish mbedtls_md2_finish
+#define md2_free mbedtls_md2_free
+#define md2_hmac mbedtls_md2_hmac
+#define md2_hmac_finish mbedtls_md2_hmac_finish
+#define md2_hmac_reset mbedtls_md2_hmac_reset
+#define md2_hmac_starts mbedtls_md2_hmac_starts
+#define md2_hmac_update mbedtls_md2_hmac_update
+#define md2_info mbedtls_md2_info
+#define md2_init mbedtls_md2_init
+#define md2_process mbedtls_md2_process
+#define md2_self_test mbedtls_md2_self_test
+#define md2_starts mbedtls_md2_starts
+#define md2_update mbedtls_md2_update
+#define md4 mbedtls_md4
+#define md4_context mbedtls_md4_context
+#define md4_file mbedtls_md4_file
+#define md4_finish mbedtls_md4_finish
+#define md4_free mbedtls_md4_free
+#define md4_hmac mbedtls_md4_hmac
+#define md4_hmac_finish mbedtls_md4_hmac_finish
+#define md4_hmac_reset mbedtls_md4_hmac_reset
+#define md4_hmac_starts mbedtls_md4_hmac_starts
+#define md4_hmac_update mbedtls_md4_hmac_update
+#define md4_info mbedtls_md4_info
+#define md4_init mbedtls_md4_init
+#define md4_process mbedtls_md4_process
+#define md4_self_test mbedtls_md4_self_test
+#define md4_starts mbedtls_md4_starts
+#define md4_update mbedtls_md4_update
+#define md5 mbedtls_md5
+#define md5_context mbedtls_md5_context
+#define md5_file mbedtls_md5_file
+#define md5_finish mbedtls_md5_finish
+#define md5_free mbedtls_md5_free
+#define md5_hmac mbedtls_md5_hmac
+#define md5_hmac_finish mbedtls_md5_hmac_finish
+#define md5_hmac_reset mbedtls_md5_hmac_reset
+#define md5_hmac_starts mbedtls_md5_hmac_starts
+#define md5_hmac_update mbedtls_md5_hmac_update
+#define md5_info mbedtls_md5_info
+#define md5_init mbedtls_md5_init
+#define md5_process mbedtls_md5_process
+#define md5_self_test mbedtls_md5_self_test
+#define md5_starts mbedtls_md5_starts
+#define md5_update mbedtls_md5_update
+#define md_context_t mbedtls_md_context_t
+#define md_file mbedtls_md_file
+#define md_finish mbedtls_md_finish
+#define md_free mbedtls_md_free
+#define md_free_ctx mbedtls_md_free_ctx
+#define md_get_name mbedtls_md_get_name
+#define md_get_size mbedtls_md_get_size
+#define md_get_type mbedtls_md_get_type
+#define md_hmac mbedtls_md_hmac
+#define md_hmac_finish mbedtls_md_hmac_finish
+#define md_hmac_reset mbedtls_md_hmac_reset
+#define md_hmac_starts mbedtls_md_hmac_starts
+#define md_hmac_update mbedtls_md_hmac_update
+#define md_info_from_string mbedtls_md_info_from_string
+#define md_info_from_type mbedtls_md_info_from_type
+#define md_info_t mbedtls_md_info_t
+#define md_init mbedtls_md_init
+#define md_init_ctx mbedtls_md_init_ctx
+#define md_list mbedtls_md_list
+#define md_process mbedtls_md_process
+#define md_starts mbedtls_md_starts
+#define md_type_t mbedtls_md_type_t
+#define md_update mbedtls_md_update
+#define memory_buffer_alloc_cur_get mbedtls_memory_buffer_alloc_cur_get
+#define memory_buffer_alloc_free mbedtls_memory_buffer_alloc_free
+#define memory_buffer_alloc_init mbedtls_memory_buffer_alloc_init
+#define memory_buffer_alloc_max_get mbedtls_memory_buffer_alloc_max_get
+#define memory_buffer_alloc_max_reset mbedtls_memory_buffer_alloc_max_reset
+#define memory_buffer_alloc_self_test mbedtls_memory_buffer_alloc_self_test
+#define memory_buffer_alloc_status mbedtls_memory_buffer_alloc_status
+#define memory_buffer_alloc_verify mbedtls_memory_buffer_alloc_verify
+#define memory_buffer_set_verify mbedtls_memory_buffer_set_verify
+#define memory_set_own mbedtls_memory_set_own
+#define mpi mbedtls_mpi
+#define mpi_add_abs mbedtls_mpi_add_abs
+#define mpi_add_int mbedtls_mpi_add_int
+#define mpi_add_mpi mbedtls_mpi_add_mpi
+#define mpi_cmp_abs mbedtls_mpi_cmp_abs
+#define mpi_cmp_int mbedtls_mpi_cmp_int
+#define mpi_cmp_mpi mbedtls_mpi_cmp_mpi
+#define mpi_copy mbedtls_mpi_copy
+#define mpi_div_int mbedtls_mpi_div_int
+#define mpi_div_mpi mbedtls_mpi_div_mpi
+#define mpi_exp_mod mbedtls_mpi_exp_mod
+#define mpi_fill_random mbedtls_mpi_fill_random
+#define mpi_free mbedtls_mpi_free
+#define mpi_gcd mbedtls_mpi_gcd
+#define mpi_gen_prime mbedtls_mpi_gen_prime
+#define mpi_get_bit mbedtls_mpi_get_bit
+#define mpi_grow mbedtls_mpi_grow
+#define mpi_init mbedtls_mpi_init
+#define mpi_inv_mod mbedtls_mpi_inv_mod
+#define mpi_is_prime mbedtls_mpi_is_prime
+#define mpi_lsb mbedtls_mpi_lsb
+#define mpi_lset mbedtls_mpi_lset
+#define mpi_mod_int mbedtls_mpi_mod_int
+#define mpi_mod_mpi mbedtls_mpi_mod_mpi
+#define mpi_msb mbedtls_mpi_bitlen
+#define mpi_mul_int mbedtls_mpi_mul_int
+#define mpi_mul_mpi mbedtls_mpi_mul_mpi
+#define mpi_read_binary mbedtls_mpi_read_binary
+#define mpi_read_file mbedtls_mpi_read_file
+#define mpi_read_string mbedtls_mpi_read_string
+#define mpi_safe_cond_assign mbedtls_mpi_safe_cond_assign
+#define mpi_safe_cond_swap mbedtls_mpi_safe_cond_swap
+#define mpi_self_test mbedtls_mpi_self_test
+#define mpi_set_bit mbedtls_mpi_set_bit
+#define mpi_shift_l mbedtls_mpi_shift_l
+#define mpi_shift_r mbedtls_mpi_shift_r
+#define mpi_shrink mbedtls_mpi_shrink
+#define mpi_size mbedtls_mpi_size
+#define mpi_sub_abs mbedtls_mpi_sub_abs
+#define mpi_sub_int mbedtls_mpi_sub_int
+#define mpi_sub_mpi mbedtls_mpi_sub_mpi
+#define mpi_swap mbedtls_mpi_swap
+#define mpi_write_binary mbedtls_mpi_write_binary
+#define mpi_write_file mbedtls_mpi_write_file
+#define mpi_write_string mbedtls_mpi_write_string
+#define net_accept mbedtls_net_accept
+#define net_bind mbedtls_net_bind
+#define net_close mbedtls_net_free
+#define net_connect mbedtls_net_connect
+#define net_recv mbedtls_net_recv
+#define net_recv_timeout mbedtls_net_recv_timeout
+#define net_send mbedtls_net_send
+#define net_set_block mbedtls_net_set_block
+#define net_set_nonblock mbedtls_net_set_nonblock
+#define net_usleep mbedtls_net_usleep
+#define oid_descriptor_t mbedtls_oid_descriptor_t
+#define oid_get_attr_short_name mbedtls_oid_get_attr_short_name
+#define oid_get_cipher_alg mbedtls_oid_get_cipher_alg
+#define oid_get_ec_grp mbedtls_oid_get_ec_grp
+#define oid_get_extended_key_usage mbedtls_oid_get_extended_key_usage
+#define oid_get_md_alg mbedtls_oid_get_md_alg
+#define oid_get_numeric_string mbedtls_oid_get_numeric_string
+#define oid_get_oid_by_ec_grp mbedtls_oid_get_oid_by_ec_grp
+#define oid_get_oid_by_md mbedtls_oid_get_oid_by_md
+#define oid_get_oid_by_pk_alg mbedtls_oid_get_oid_by_pk_alg
+#define oid_get_oid_by_sig_alg mbedtls_oid_get_oid_by_sig_alg
+#define oid_get_pk_alg mbedtls_oid_get_pk_alg
+#define oid_get_pkcs12_pbe_alg mbedtls_oid_get_pkcs12_pbe_alg
+#define oid_get_sig_alg mbedtls_oid_get_sig_alg
+#define oid_get_sig_alg_desc mbedtls_oid_get_sig_alg_desc
+#define oid_get_x509_ext_type mbedtls_oid_get_x509_ext_type
+#define operation_t mbedtls_operation_t
+#define padlock_supports mbedtls_padlock_has_support
+#define padlock_xcryptcbc mbedtls_padlock_xcryptcbc
+#define padlock_xcryptecb mbedtls_padlock_xcryptecb
+#define pbkdf2_hmac mbedtls_pbkdf2_hmac
+#define pbkdf2_self_test mbedtls_pbkdf2_self_test
+#define pem_context mbedtls_pem_context
+#define pem_free mbedtls_pem_free
+#define pem_init mbedtls_pem_init
+#define pem_read_buffer mbedtls_pem_read_buffer
+#define pem_write_buffer mbedtls_pem_write_buffer
+#define pk_can_do mbedtls_pk_can_do
+#define pk_check_pair mbedtls_pk_check_pair
+#define pk_context mbedtls_pk_context
+#define pk_debug mbedtls_pk_debug
+#define pk_debug_item mbedtls_pk_debug_item
+#define pk_debug_type mbedtls_pk_debug_type
+#define pk_decrypt mbedtls_pk_decrypt
+#define pk_ec mbedtls_pk_ec
+#define pk_encrypt mbedtls_pk_encrypt
+#define pk_free mbedtls_pk_free
+#define pk_get_len mbedtls_pk_get_len
+#define pk_get_name mbedtls_pk_get_name
+#define pk_get_size mbedtls_pk_get_bitlen
+#define pk_get_type mbedtls_pk_get_type
+#define pk_info_from_type mbedtls_pk_info_from_type
+#define pk_info_t mbedtls_pk_info_t
+#define pk_init mbedtls_pk_init
+#define pk_init_ctx mbedtls_pk_setup
+#define pk_init_ctx_rsa_alt mbedtls_pk_setup_rsa_alt
+#define pk_load_file mbedtls_pk_load_file
+#define pk_parse_key mbedtls_pk_parse_key
+#define pk_parse_keyfile mbedtls_pk_parse_keyfile
+#define pk_parse_public_key mbedtls_pk_parse_public_key
+#define pk_parse_public_keyfile mbedtls_pk_parse_public_keyfile
+#define pk_parse_subpubkey mbedtls_pk_parse_subpubkey
+#define pk_rsa mbedtls_pk_rsa
+#define pk_rsa_alt_decrypt_func mbedtls_pk_rsa_alt_decrypt_func
+#define pk_rsa_alt_key_len_func mbedtls_pk_rsa_alt_key_len_func
+#define pk_rsa_alt_sign_func mbedtls_pk_rsa_alt_sign_func
+#define pk_rsassa_pss_options mbedtls_pk_rsassa_pss_options
+#define pk_sign mbedtls_pk_sign
+#define pk_type_t mbedtls_pk_type_t
+#define pk_verify mbedtls_pk_verify
+#define pk_verify_ext mbedtls_pk_verify_ext
+#define pk_write_key_der mbedtls_pk_write_key_der
+#define pk_write_key_pem mbedtls_pk_write_key_pem
+#define pk_write_pubkey mbedtls_pk_write_pubkey
+#define pk_write_pubkey_der mbedtls_pk_write_pubkey_der
+#define pk_write_pubkey_pem mbedtls_pk_write_pubkey_pem
+#define pkcs11_context mbedtls_pkcs11_context
+#define pkcs11_decrypt mbedtls_pkcs11_decrypt
+#define pkcs11_priv_key_free mbedtls_pkcs11_priv_key_free
+#define pkcs11_priv_key_init mbedtls_pkcs11_priv_key_bind
+#define pkcs11_sign mbedtls_pkcs11_sign
+#define pkcs11_x509_cert_init mbedtls_pkcs11_x509_cert_bind
+#define pkcs12_derivation mbedtls_pkcs12_derivation
+#define pkcs12_pbe mbedtls_pkcs12_pbe
+#define pkcs12_pbe_sha1_rc4_128 mbedtls_pkcs12_pbe_sha1_rc4_128
+#define pkcs5_pbes2 mbedtls_pkcs5_pbes2
+#define pkcs5_pbkdf2_hmac mbedtls_pkcs5_pbkdf2_hmac
+#define pkcs5_self_test mbedtls_pkcs5_self_test
+#define platform_entropy_poll mbedtls_platform_entropy_poll
+#define platform_set_exit mbedtls_platform_set_exit
+#define platform_set_fprintf mbedtls_platform_set_fprintf
+#define platform_set_malloc_free mbedtls_platform_set_malloc_free
+#define platform_set_printf mbedtls_platform_set_printf
+#define platform_set_snprintf mbedtls_platform_set_snprintf
+#define polarssl_exit mbedtls_exit
+#define polarssl_fprintf mbedtls_fprintf
+#define polarssl_free mbedtls_free
+#define polarssl_malloc mbedtls_malloc
+#define polarssl_mutex_free mbedtls_mutex_free
+#define polarssl_mutex_init mbedtls_mutex_init
+#define polarssl_mutex_lock mbedtls_mutex_lock
+#define polarssl_mutex_unlock mbedtls_mutex_unlock
+#define polarssl_printf mbedtls_printf
+#define polarssl_snprintf mbedtls_snprintf
+#define polarssl_strerror mbedtls_strerror
+#define ripemd160 mbedtls_ripemd160
+#define ripemd160_context mbedtls_ripemd160_context
+#define ripemd160_file mbedtls_ripemd160_file
+#define ripemd160_finish mbedtls_ripemd160_finish
+#define ripemd160_free mbedtls_ripemd160_free
+#define ripemd160_hmac mbedtls_ripemd160_hmac
+#define ripemd160_hmac_finish mbedtls_ripemd160_hmac_finish
+#define ripemd160_hmac_reset mbedtls_ripemd160_hmac_reset
+#define ripemd160_hmac_starts mbedtls_ripemd160_hmac_starts
+#define ripemd160_hmac_update mbedtls_ripemd160_hmac_update
+#define ripemd160_info mbedtls_ripemd160_info
+#define ripemd160_init mbedtls_ripemd160_init
+#define ripemd160_process mbedtls_ripemd160_process
+#define ripemd160_self_test mbedtls_ripemd160_self_test
+#define ripemd160_starts mbedtls_ripemd160_starts
+#define ripemd160_update mbedtls_ripemd160_update
+#define rsa_alt_context mbedtls_rsa_alt_context
+#define rsa_alt_info mbedtls_rsa_alt_info
+#define rsa_check_privkey mbedtls_rsa_check_privkey
+#define rsa_check_pub_priv mbedtls_rsa_check_pub_priv
+#define rsa_check_pubkey mbedtls_rsa_check_pubkey
+#define rsa_context mbedtls_rsa_context
+#define rsa_copy mbedtls_rsa_copy
+#define rsa_decrypt_func mbedtls_rsa_decrypt_func
+#define rsa_free mbedtls_rsa_free
+#define rsa_gen_key mbedtls_rsa_gen_key
+#define rsa_info mbedtls_rsa_info
+#define rsa_init mbedtls_rsa_init
+#define rsa_key_len_func mbedtls_rsa_key_len_func
+#define rsa_pkcs1_decrypt mbedtls_rsa_pkcs1_decrypt
+#define rsa_pkcs1_encrypt mbedtls_rsa_pkcs1_encrypt
+#define rsa_pkcs1_sign mbedtls_rsa_pkcs1_sign
+#define rsa_pkcs1_verify mbedtls_rsa_pkcs1_verify
+#define rsa_private mbedtls_rsa_private
+#define rsa_public mbedtls_rsa_public
+#define rsa_rsaes_oaep_decrypt mbedtls_rsa_rsaes_oaep_decrypt
+#define rsa_rsaes_oaep_encrypt mbedtls_rsa_rsaes_oaep_encrypt
+#define rsa_rsaes_pkcs1_v15_decrypt mbedtls_rsa_rsaes_pkcs1_v15_decrypt
+#define rsa_rsaes_pkcs1_v15_encrypt mbedtls_rsa_rsaes_pkcs1_v15_encrypt
+#define rsa_rsassa_pkcs1_v15_sign mbedtls_rsa_rsassa_pkcs1_v15_sign
+#define rsa_rsassa_pkcs1_v15_verify mbedtls_rsa_rsassa_pkcs1_v15_verify
+#define rsa_rsassa_pss_sign mbedtls_rsa_rsassa_pss_sign
+#define rsa_rsassa_pss_verify mbedtls_rsa_rsassa_pss_verify
+#define rsa_rsassa_pss_verify_ext mbedtls_rsa_rsassa_pss_verify_ext
+#define rsa_self_test mbedtls_rsa_self_test
+#define rsa_set_padding mbedtls_rsa_set_padding
+#define rsa_sign_func mbedtls_rsa_sign_func
+#define safer_memcmp mbedtls_ssl_safer_memcmp
+#define set_alarm mbedtls_set_alarm
+#define sha1 mbedtls_sha1
+#define sha1_context mbedtls_sha1_context
+#define sha1_file mbedtls_sha1_file
+#define sha1_finish mbedtls_sha1_finish
+#define sha1_free mbedtls_sha1_free
+#define sha1_hmac mbedtls_sha1_hmac
+#define sha1_hmac_finish mbedtls_sha1_hmac_finish
+#define sha1_hmac_reset mbedtls_sha1_hmac_reset
+#define sha1_hmac_starts mbedtls_sha1_hmac_starts
+#define sha1_hmac_update mbedtls_sha1_hmac_update
+#define sha1_info mbedtls_sha1_info
+#define sha1_init mbedtls_sha1_init
+#define sha1_process mbedtls_sha1_process
+#define sha1_self_test mbedtls_sha1_self_test
+#define sha1_starts mbedtls_sha1_starts
+#define sha1_update mbedtls_sha1_update
+#define sha224_info mbedtls_sha224_info
+#define sha256 mbedtls_sha256
+#define sha256_context mbedtls_sha256_context
+#define sha256_file mbedtls_sha256_file
+#define sha256_finish mbedtls_sha256_finish
+#define sha256_free mbedtls_sha256_free
+#define sha256_hmac mbedtls_sha256_hmac
+#define sha256_hmac_finish mbedtls_sha256_hmac_finish
+#define sha256_hmac_reset mbedtls_sha256_hmac_reset
+#define sha256_hmac_starts mbedtls_sha256_hmac_starts
+#define sha256_hmac_update mbedtls_sha256_hmac_update
+#define sha256_info mbedtls_sha256_info
+#define sha256_init mbedtls_sha256_init
+#define sha256_process mbedtls_sha256_process
+#define sha256_self_test mbedtls_sha256_self_test
+#define sha256_starts mbedtls_sha256_starts
+#define sha256_update mbedtls_sha256_update
+#define sha384_info mbedtls_sha384_info
+#define sha512 mbedtls_sha512
+#define sha512_context mbedtls_sha512_context
+#define sha512_file mbedtls_sha512_file
+#define sha512_finish mbedtls_sha512_finish
+#define sha512_free mbedtls_sha512_free
+#define sha512_hmac mbedtls_sha512_hmac
+#define sha512_hmac_finish mbedtls_sha512_hmac_finish
+#define sha512_hmac_reset mbedtls_sha512_hmac_reset
+#define sha512_hmac_starts mbedtls_sha512_hmac_starts
+#define sha512_hmac_update mbedtls_sha512_hmac_update
+#define sha512_info mbedtls_sha512_info
+#define sha512_init mbedtls_sha512_init
+#define sha512_process mbedtls_sha512_process
+#define sha512_self_test mbedtls_sha512_self_test
+#define sha512_starts mbedtls_sha512_starts
+#define sha512_update mbedtls_sha512_update
+#define source_state mbedtls_entropy_source_state
+#define ssl_cache_context mbedtls_ssl_cache_context
+#define ssl_cache_entry mbedtls_ssl_cache_entry
+#define ssl_cache_free mbedtls_ssl_cache_free
+#define ssl_cache_get mbedtls_ssl_cache_get
+#define ssl_cache_init mbedtls_ssl_cache_init
+#define ssl_cache_set mbedtls_ssl_cache_set
+#define ssl_cache_set_max_entries mbedtls_ssl_cache_set_max_entries
+#define ssl_cache_set_timeout mbedtls_ssl_cache_set_timeout
+#define ssl_check_cert_usage mbedtls_ssl_check_cert_usage
+#define ssl_ciphersuite_from_id mbedtls_ssl_ciphersuite_from_id
+#define ssl_ciphersuite_from_string mbedtls_ssl_ciphersuite_from_string
+#define ssl_ciphersuite_t mbedtls_ssl_ciphersuite_t
+#define ssl_ciphersuite_uses_ec mbedtls_ssl_ciphersuite_uses_ec
+#define ssl_ciphersuite_uses_psk mbedtls_ssl_ciphersuite_uses_psk
+#define ssl_close_notify mbedtls_ssl_close_notify
+#define ssl_context mbedtls_ssl_context
+#define ssl_cookie_check mbedtls_ssl_cookie_check
+#define ssl_cookie_check_t mbedtls_ssl_cookie_check_t
+#define ssl_cookie_ctx mbedtls_ssl_cookie_ctx
+#define ssl_cookie_free mbedtls_ssl_cookie_free
+#define ssl_cookie_init mbedtls_ssl_cookie_init
+#define ssl_cookie_set_timeout mbedtls_ssl_cookie_set_timeout
+#define ssl_cookie_setup mbedtls_ssl_cookie_setup
+#define ssl_cookie_write mbedtls_ssl_cookie_write
+#define ssl_cookie_write_t mbedtls_ssl_cookie_write_t
+#define ssl_curve_is_acceptable mbedtls_ssl_curve_is_acceptable
+#define ssl_derive_keys mbedtls_ssl_derive_keys
+#define ssl_dtls_replay_check mbedtls_ssl_dtls_replay_check
+#define ssl_dtls_replay_update mbedtls_ssl_dtls_replay_update
+#define ssl_fetch_input mbedtls_ssl_fetch_input
+#define ssl_flight_item mbedtls_ssl_flight_item
+#define ssl_flush_output mbedtls_ssl_flush_output
+#define ssl_free mbedtls_ssl_free
+#define ssl_get_alpn_protocol mbedtls_ssl_get_alpn_protocol
+#define ssl_get_bytes_avail mbedtls_ssl_get_bytes_avail
+#define ssl_get_ciphersuite mbedtls_ssl_get_ciphersuite
+#define ssl_get_ciphersuite_id mbedtls_ssl_get_ciphersuite_id
+#define ssl_get_ciphersuite_name mbedtls_ssl_get_ciphersuite_name
+#define ssl_get_ciphersuite_sig_pk_alg mbedtls_ssl_get_ciphersuite_sig_pk_alg
+#define ssl_get_peer_cert mbedtls_ssl_get_peer_cert
+#define ssl_get_record_expansion mbedtls_ssl_get_record_expansion
+#define ssl_get_session mbedtls_ssl_get_session
+#define ssl_get_verify_result mbedtls_ssl_get_verify_result
+#define ssl_get_version mbedtls_ssl_get_version
+#define ssl_handshake mbedtls_ssl_handshake
+#define ssl_handshake_client_step mbedtls_ssl_handshake_client_step
+#define ssl_handshake_free mbedtls_ssl_handshake_free
+#define ssl_handshake_params mbedtls_ssl_handshake_params
+#define ssl_handshake_server_step mbedtls_ssl_handshake_server_step
+#define ssl_handshake_step mbedtls_ssl_handshake_step
+#define ssl_handshake_wrapup mbedtls_ssl_handshake_wrapup
+#define ssl_hdr_len mbedtls_ssl_hdr_len
+#define ssl_hs_hdr_len mbedtls_ssl_hs_hdr_len
+#define ssl_hw_record_activate mbedtls_ssl_hw_record_activate
+#define ssl_hw_record_finish mbedtls_ssl_hw_record_finish
+#define ssl_hw_record_init mbedtls_ssl_hw_record_init
+#define ssl_hw_record_read mbedtls_ssl_hw_record_read
+#define ssl_hw_record_reset mbedtls_ssl_hw_record_reset
+#define ssl_hw_record_write mbedtls_ssl_hw_record_write
+#define ssl_init mbedtls_ssl_init
+#define ssl_key_cert mbedtls_ssl_key_cert
+#define ssl_legacy_renegotiation mbedtls_ssl_conf_legacy_renegotiation
+#define ssl_list_ciphersuites mbedtls_ssl_list_ciphersuites
+#define ssl_md_alg_from_hash mbedtls_ssl_md_alg_from_hash
+#define ssl_optimize_checksum mbedtls_ssl_optimize_checksum
+#define ssl_own_cert mbedtls_ssl_own_cert
+#define ssl_own_key mbedtls_ssl_own_key
+#define ssl_parse_certificate mbedtls_ssl_parse_certificate
+#define ssl_parse_change_cipher_spec mbedtls_ssl_parse_change_cipher_spec
+#define ssl_parse_finished mbedtls_ssl_parse_finished
+#define ssl_pk_alg_from_sig mbedtls_ssl_pk_alg_from_sig
+#define ssl_pkcs11_decrypt mbedtls_ssl_pkcs11_decrypt
+#define ssl_pkcs11_key_len mbedtls_ssl_pkcs11_key_len
+#define ssl_pkcs11_sign mbedtls_ssl_pkcs11_sign
+#define ssl_psk_derive_premaster mbedtls_ssl_psk_derive_premaster
+#define ssl_read mbedtls_ssl_read
+#define ssl_read_record mbedtls_ssl_read_record
+#define ssl_read_version mbedtls_ssl_read_version
+#define ssl_recv_flight_completed mbedtls_ssl_recv_flight_completed
+#define ssl_renegotiate mbedtls_ssl_renegotiate
+#define ssl_resend mbedtls_ssl_resend
+#define ssl_reset_checksum mbedtls_ssl_reset_checksum
+#define ssl_send_alert_message mbedtls_ssl_send_alert_message
+#define ssl_send_fatal_handshake_failure mbedtls_ssl_send_fatal_handshake_failure
+#define ssl_send_flight_completed mbedtls_ssl_send_flight_completed
+#define ssl_session mbedtls_ssl_session
+#define ssl_session_free mbedtls_ssl_session_free
+#define ssl_session_init mbedtls_ssl_session_init
+#define ssl_session_reset mbedtls_ssl_session_reset
+#define ssl_set_alpn_protocols mbedtls_ssl_conf_alpn_protocols
+#define ssl_set_arc4_support mbedtls_ssl_conf_arc4_support
+#define ssl_set_authmode mbedtls_ssl_conf_authmode
+#define ssl_set_bio mbedtls_ssl_set_bio
+#define ssl_set_bio mbedtls_ssl_set_bio_timeout
+#define ssl_set_ca_chain mbedtls_ssl_conf_ca_chain
+#define ssl_set_cbc_record_splitting mbedtls_ssl_conf_cbc_record_splitting
+#define ssl_set_ciphersuites mbedtls_ssl_conf_ciphersuites
+#define ssl_set_ciphersuites_for_version mbedtls_ssl_conf_ciphersuites_for_version
+#define ssl_set_client_transport_id mbedtls_ssl_set_client_transport_id
+#define ssl_set_curves mbedtls_ssl_conf_curves
+#define ssl_set_dbg mbedtls_ssl_conf_dbg
+#define ssl_set_dh_param mbedtls_ssl_conf_dh_param
+#define ssl_set_dh_param_ctx mbedtls_ssl_conf_dh_param_ctx
+#define ssl_set_dtls_anti_replay mbedtls_ssl_conf_dtls_anti_replay
+#define ssl_set_dtls_badmac_limit mbedtls_ssl_conf_dtls_badmac_limit
+#define ssl_set_dtls_cookies mbedtls_ssl_conf_dtls_cookies
+#define ssl_set_encrypt_then_mac mbedtls_ssl_conf_encrypt_then_mac
+#define ssl_set_endpoint mbedtls_ssl_conf_endpoint
+#define ssl_set_extended_master_secret mbedtls_ssl_conf_extended_master_secret
+#define ssl_set_fallback mbedtls_ssl_conf_fallback
+#define ssl_set_handshake_timeout mbedtls_ssl_conf_handshake_timeout
+#define ssl_set_hostname mbedtls_ssl_set_hostname
+#define ssl_set_max_frag_len mbedtls_ssl_conf_max_frag_len
+#define ssl_set_max_version mbedtls_ssl_conf_max_version
+#define ssl_set_min_version mbedtls_ssl_conf_min_version
+#define ssl_set_own_cert mbedtls_ssl_conf_own_cert
+#define ssl_set_own_cert_alt mbedtls_ssl_set_own_cert_alt
+#define ssl_set_own_cert_rsa mbedtls_ssl_set_own_cert_rsa
+#define ssl_set_psk mbedtls_ssl_conf_psk
+#define ssl_set_psk_cb mbedtls_ssl_conf_psk_cb
+#define ssl_set_renegotiation mbedtls_ssl_conf_renegotiation
+#define ssl_set_renegotiation_enforced mbedtls_ssl_conf_renegotiation_enforced
+#define ssl_set_renegotiation_period mbedtls_ssl_conf_renegotiation_period
+#define ssl_set_rng mbedtls_ssl_conf_rng
+#define ssl_set_session mbedtls_ssl_set_session
+#define ssl_set_session_cache mbedtls_ssl_conf_session_cache
+#define ssl_set_session_ticket_lifetime mbedtls_ssl_conf_session_ticket_lifetime
+#define ssl_set_session_tickets mbedtls_ssl_conf_session_tickets
+#define ssl_set_sni mbedtls_ssl_conf_sni
+#define ssl_set_transport mbedtls_ssl_conf_transport
+#define ssl_set_truncated_hmac mbedtls_ssl_conf_truncated_hmac
+#define ssl_set_verify mbedtls_ssl_conf_verify
+#define ssl_sig_from_pk mbedtls_ssl_sig_from_pk
+#define ssl_states mbedtls_ssl_states
+#define ssl_ticket_keys mbedtls_ssl_ticket_keys
+#define ssl_transform mbedtls_ssl_transform
+#define ssl_transform_free mbedtls_ssl_transform_free
+#define ssl_write mbedtls_ssl_write
+#define ssl_write_certificate mbedtls_ssl_write_certificate
+#define ssl_write_change_cipher_spec mbedtls_ssl_write_change_cipher_spec
+#define ssl_write_finished mbedtls_ssl_write_finished
+#define ssl_write_record mbedtls_ssl_write_record
+#define ssl_write_version mbedtls_ssl_write_version
+#define supported_ciphers mbedtls_cipher_supported
+#define t_sint mbedtls_mpi_sint
+#define t_udbl mbedtls_t_udbl
+#define t_uint mbedtls_mpi_uint
+#define test_ca_crt mbedtls_test_ca_crt
+#define test_ca_crt_ec mbedtls_test_ca_crt_ec
+#define test_ca_crt_rsa mbedtls_test_ca_crt_rsa
+#define test_ca_key mbedtls_test_ca_key
+#define test_ca_key_ec mbedtls_test_ca_key_ec
+#define test_ca_key_rsa mbedtls_test_ca_key_rsa
+#define test_ca_list mbedtls_test_cas_pem
+#define test_ca_pwd mbedtls_test_ca_pwd
+#define test_ca_pwd_ec mbedtls_test_ca_pwd_ec
+#define test_ca_pwd_rsa mbedtls_test_ca_pwd_rsa
+#define test_cli_crt mbedtls_test_cli_crt
+#define test_cli_crt_ec mbedtls_test_cli_crt_ec
+#define test_cli_crt_rsa mbedtls_test_cli_crt_rsa
+#define test_cli_key mbedtls_test_cli_key
+#define test_cli_key_ec mbedtls_test_cli_key_ec
+#define test_cli_key_rsa mbedtls_test_cli_key_rsa
+#define test_dhm_params mbedtls_test_dhm_params
+#define test_srv_crt mbedtls_test_srv_crt
+#define test_srv_crt_ec mbedtls_test_srv_crt_ec
+#define test_srv_crt_rsa mbedtls_test_srv_crt_rsa
+#define test_srv_key mbedtls_test_srv_key
+#define test_srv_key_ec mbedtls_test_srv_key_ec
+#define test_srv_key_rsa mbedtls_test_srv_key_rsa
+#define threading_mutex_t mbedtls_threading_mutex_t
+#define threading_set_alt mbedtls_threading_set_alt
+#define timing_self_test mbedtls_timing_self_test
+#define version_check_feature mbedtls_version_check_feature
+#define version_get_number mbedtls_version_get_number
+#define version_get_string mbedtls_version_get_string
+#define version_get_string_full mbedtls_version_get_string_full
+#define x509_bitstring mbedtls_x509_bitstring
+#define x509_buf mbedtls_x509_buf
+#define x509_crl mbedtls_x509_crl
+#define x509_crl_entry mbedtls_x509_crl_entry
+#define x509_crl_free mbedtls_x509_crl_free
+#define x509_crl_info mbedtls_x509_crl_info
+#define x509_crl_init mbedtls_x509_crl_init
+#define x509_crl_parse mbedtls_x509_crl_parse
+#define x509_crl_parse_der mbedtls_x509_crl_parse_der
+#define x509_crl_parse_file mbedtls_x509_crl_parse_file
+#define x509_crt mbedtls_x509_crt
+#define x509_crt_check_extended_key_usage mbedtls_x509_crt_check_extended_key_usage
+#define x509_crt_check_key_usage mbedtls_x509_crt_check_key_usage
+#define x509_crt_free mbedtls_x509_crt_free
+#define x509_crt_info mbedtls_x509_crt_info
+#define x509_crt_init mbedtls_x509_crt_init
+#define x509_crt_parse mbedtls_x509_crt_parse
+#define x509_crt_parse_der mbedtls_x509_crt_parse_der
+#define x509_crt_parse_file mbedtls_x509_crt_parse_file
+#define x509_crt_parse_path mbedtls_x509_crt_parse_path
+#define x509_crt_revoked mbedtls_x509_crt_is_revoked
+#define x509_crt_verify mbedtls_x509_crt_verify
+#define x509_csr mbedtls_x509_csr
+#define x509_csr_free mbedtls_x509_csr_free
+#define x509_csr_info mbedtls_x509_csr_info
+#define x509_csr_init mbedtls_x509_csr_init
+#define x509_csr_parse mbedtls_x509_csr_parse
+#define x509_csr_parse_der mbedtls_x509_csr_parse_der
+#define x509_csr_parse_file mbedtls_x509_csr_parse_file
+#define x509_dn_gets mbedtls_x509_dn_gets
+#define x509_get_alg mbedtls_x509_get_alg
+#define x509_get_alg_null mbedtls_x509_get_alg_null
+#define x509_get_ext mbedtls_x509_get_ext
+#define x509_get_name mbedtls_x509_get_name
+#define x509_get_rsassa_pss_params mbedtls_x509_get_rsassa_pss_params
+#define x509_get_serial mbedtls_x509_get_serial
+#define x509_get_sig mbedtls_x509_get_sig
+#define x509_get_sig_alg mbedtls_x509_get_sig_alg
+#define x509_get_time mbedtls_x509_get_time
+#define x509_key_size_helper mbedtls_x509_key_size_helper
+#define x509_name mbedtls_x509_name
+#define x509_oid_get_description mbedtls_x509_oid_get_description
+#define x509_oid_get_numeric_string mbedtls_x509_oid_get_numeric_string
+#define x509_self_test mbedtls_x509_self_test
+#define x509_sequence mbedtls_x509_sequence
+#define x509_serial_gets mbedtls_x509_serial_gets
+#define x509_set_extension mbedtls_x509_set_extension
+#define x509_sig_alg_gets mbedtls_x509_sig_alg_gets
+#define x509_string_to_names mbedtls_x509_string_to_names
+#define x509_time mbedtls_x509_time
+#define x509_time_expired mbedtls_x509_time_is_past
+#define x509_time_future mbedtls_x509_time_is_future
+#define x509_write_extensions mbedtls_x509_write_extensions
+#define x509_write_names mbedtls_x509_write_names
+#define x509_write_sig mbedtls_x509_write_sig
+#define x509write_cert mbedtls_x509write_cert
+#define x509write_crt_der mbedtls_x509write_crt_der
+#define x509write_crt_free mbedtls_x509write_crt_free
+#define x509write_crt_init mbedtls_x509write_crt_init
+#define x509write_crt_pem mbedtls_x509write_crt_pem
+#define x509write_crt_set_authority_key_identifier mbedtls_x509write_crt_set_authority_key_identifier
+#define x509write_crt_set_basic_constraints mbedtls_x509write_crt_set_basic_constraints
+#define x509write_crt_set_extension mbedtls_x509write_crt_set_extension
+#define x509write_crt_set_issuer_key mbedtls_x509write_crt_set_issuer_key
+#define x509write_crt_set_issuer_name mbedtls_x509write_crt_set_issuer_name
+#define x509write_crt_set_key_usage mbedtls_x509write_crt_set_key_usage
+#define x509write_crt_set_md_alg mbedtls_x509write_crt_set_md_alg
+#define x509write_crt_set_ns_cert_type mbedtls_x509write_crt_set_ns_cert_type
+#define x509write_crt_set_serial mbedtls_x509write_crt_set_serial
+#define x509write_crt_set_subject_key mbedtls_x509write_crt_set_subject_key
+#define x509write_crt_set_subject_key_identifier mbedtls_x509write_crt_set_subject_key_identifier
+#define x509write_crt_set_subject_name mbedtls_x509write_crt_set_subject_name
+#define x509write_crt_set_validity mbedtls_x509write_crt_set_validity
+#define x509write_crt_set_version mbedtls_x509write_crt_set_version
+#define x509write_csr mbedtls_x509write_csr
+#define x509write_csr_der mbedtls_x509write_csr_der
+#define x509write_csr_free mbedtls_x509write_csr_free
+#define x509write_csr_init mbedtls_x509write_csr_init
+#define x509write_csr_pem mbedtls_x509write_csr_pem
+#define x509write_csr_set_extension mbedtls_x509write_csr_set_extension
+#define x509write_csr_set_key mbedtls_x509write_csr_set_key
+#define x509write_csr_set_key_usage mbedtls_x509write_csr_set_key_usage
+#define x509write_csr_set_md_alg mbedtls_x509write_csr_set_md_alg
+#define x509write_csr_set_ns_cert_type mbedtls_x509write_csr_set_ns_cert_type
+#define x509write_csr_set_subject_name mbedtls_x509write_csr_set_subject_name
+#define xtea_context mbedtls_xtea_context
+#define xtea_crypt_cbc mbedtls_xtea_crypt_cbc
+#define xtea_crypt_ecb mbedtls_xtea_crypt_ecb
+#define xtea_free mbedtls_xtea_free
+#define xtea_init mbedtls_xtea_init
+#define xtea_self_test mbedtls_xtea_self_test
+#define xtea_setup mbedtls_xtea_setup
+
+#endif /* compat-1.3.h */
+#endif /* MBEDTLS_DEPRECATED_REMOVED */
diff --git a/tools/sdk/include/mbedtls/mbedtls/config.h b/tools/sdk/include/mbedtls/mbedtls/config.h
new file mode 100644
index 00000000..3b7c85b3
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/config.h
@@ -0,0 +1,2587 @@
+/**
+ * \file config.h
+ *
+ * \brief Configuration options (set of defines)
+ *
+ *  This set of compile-time options may be used to enable
+ *  or disable features selectively, and reduce the global
+ *  memory footprint.
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+
+#ifndef MBEDTLS_CONFIG_H
+#define MBEDTLS_CONFIG_H
+
+#if defined(_MSC_VER) && !defined(_CRT_SECURE_NO_DEPRECATE)
+#define _CRT_SECURE_NO_DEPRECATE 1
+#endif
+
+/**
+ * \name SECTION: System support
+ *
+ * This section sets system specific settings.
+ * \{
+ */
+
+/**
+ * \def MBEDTLS_HAVE_ASM
+ *
+ * The compiler has support for asm().
+ *
+ * Requires support for asm() in compiler.
+ *
+ * Used in:
+ *      library/timing.c
+ *      library/padlock.c
+ *      include/mbedtls/bn_mul.h
+ *
+ * Comment to disable the use of assembly code.
+ */
+#define MBEDTLS_HAVE_ASM
+
+/**
+ * \def MBEDTLS_HAVE_SSE2
+ *
+ * CPU supports SSE2 instruction set.
+ *
+ * Uncomment if the CPU supports SSE2 (IA-32 specific).
+ */
+//#define MBEDTLS_HAVE_SSE2
+
+/**
+ * \def MBEDTLS_HAVE_TIME
+ *
+ * System has time.h and time().
+ * The time does not need to be correct, only time differences are used,
+ * by contrast with MBEDTLS_HAVE_TIME_DATE
+ *
+ * Comment if your system does not support time functions
+ */
+#define MBEDTLS_HAVE_TIME
+
+/**
+ * \def MBEDTLS_HAVE_TIME_DATE
+ *
+ * System has time.h and time(), gmtime() and the clock is correct.
+ * The time needs to be correct (not necesarily very accurate, but at least
+ * the date should be correct). This is used to verify the validity period of
+ * X.509 certificates.
+ *
+ * Comment if your system does not have a correct clock.
+ */
+#define MBEDTLS_HAVE_TIME_DATE
+
+/**
+ * \def MBEDTLS_PLATFORM_MEMORY
+ *
+ * Enable the memory allocation layer.
+ *
+ * By default mbed TLS uses the system-provided calloc() and free().
+ * This allows different allocators (self-implemented or provided) to be
+ * provided to the platform abstraction layer.
+ *
+ * Enabling MBEDTLS_PLATFORM_MEMORY without the
+ * MBEDTLS_PLATFORM_{FREE,CALLOC}_MACROs will provide
+ * "mbedtls_platform_set_calloc_free()" allowing you to set an alternative calloc() and
+ * free() function pointer at runtime.
+ *
+ * Enabling MBEDTLS_PLATFORM_MEMORY and specifying
+ * MBEDTLS_PLATFORM_{CALLOC,FREE}_MACROs will allow you to specify the
+ * alternate function at compile time.
+ *
+ * Requires: MBEDTLS_PLATFORM_C
+ *
+ * Enable this layer to allow use of alternative memory allocators.
+ */
+//#define MBEDTLS_PLATFORM_MEMORY
+
+/**
+ * \def MBEDTLS_PLATFORM_NO_STD_FUNCTIONS
+ *
+ * Do not assign standard functions in the platform layer (e.g. calloc() to
+ * MBEDTLS_PLATFORM_STD_CALLOC and printf() to MBEDTLS_PLATFORM_STD_PRINTF)
+ *
+ * This makes sure there are no linking errors on platforms that do not support
+ * these functions. You will HAVE to provide alternatives, either at runtime
+ * via the platform_set_xxx() functions or at compile time by setting
+ * the MBEDTLS_PLATFORM_STD_XXX defines, or enabling a
+ * MBEDTLS_PLATFORM_XXX_MACRO.
+ *
+ * Requires: MBEDTLS_PLATFORM_C
+ *
+ * Uncomment to prevent default assignment of standard functions in the
+ * platform layer.
+ */
+//#define MBEDTLS_PLATFORM_NO_STD_FUNCTIONS
+
+/**
+ * \def MBEDTLS_PLATFORM_EXIT_ALT
+ *
+ * MBEDTLS_PLATFORM_XXX_ALT: Uncomment a macro to let mbed TLS support the
+ * function in the platform abstraction layer.
+ *
+ * Example: In case you uncomment MBEDTLS_PLATFORM_PRINTF_ALT, mbed TLS will
+ * provide a function "mbedtls_platform_set_printf()" that allows you to set an
+ * alternative printf function pointer.
+ *
+ * All these define require MBEDTLS_PLATFORM_C to be defined!
+ *
+ * \note MBEDTLS_PLATFORM_SNPRINTF_ALT is required on Windows;
+ * it will be enabled automatically by check_config.h
+ *
+ * \warning MBEDTLS_PLATFORM_XXX_ALT cannot be defined at the same time as
+ * MBEDTLS_PLATFORM_XXX_MACRO!
+ *
+ * Uncomment a macro to enable alternate implementation of specific base
+ * platform function
+ */
+//#define MBEDTLS_PLATFORM_EXIT_ALT
+//#define MBEDTLS_PLATFORM_TIME_ALT
+//#define MBEDTLS_PLATFORM_FPRINTF_ALT
+//#define MBEDTLS_PLATFORM_PRINTF_ALT
+//#define MBEDTLS_PLATFORM_SNPRINTF_ALT
+//#define MBEDTLS_PLATFORM_NV_SEED_ALT
+
+/**
+ * \def MBEDTLS_DEPRECATED_WARNING
+ *
+ * Mark deprecated functions so that they generate a warning if used.
+ * Functions deprecated in one version will usually be removed in the next
+ * version. You can enable this to help you prepare the transition to a new
+ * major version by making sure your code is not using these functions.
+ *
+ * This only works with GCC and Clang. With other compilers, you may want to
+ * use MBEDTLS_DEPRECATED_REMOVED
+ *
+ * Uncomment to get warnings on using deprecated functions.
+ */
+//#define MBEDTLS_DEPRECATED_WARNING
+
+/**
+ * \def MBEDTLS_DEPRECATED_REMOVED
+ *
+ * Remove deprecated functions so that they generate an error if used.
+ * Functions deprecated in one version will usually be removed in the next
+ * version. You can enable this to help you prepare the transition to a new
+ * major version by making sure your code is not using these functions.
+ *
+ * Uncomment to get errors on using deprecated functions.
+ */
+//#define MBEDTLS_DEPRECATED_REMOVED
+
+/* \} name SECTION: System support */
+
+/**
+ * \name SECTION: mbed TLS feature support
+ *
+ * This section sets support for features that are or are not needed
+ * within the modules that are enabled.
+ * \{
+ */
+
+/**
+ * \def MBEDTLS_TIMING_ALT
+ *
+ * Uncomment to provide your own alternate implementation for mbedtls_timing_hardclock(),
+ * mbedtls_timing_get_timer(), mbedtls_set_alarm(), mbedtls_set/get_delay()
+ *
+ * Only works if you have MBEDTLS_TIMING_C enabled.
+ *
+ * You will need to provide a header "timing_alt.h" and an implementation at
+ * compile time.
+ */
+//#define MBEDTLS_TIMING_ALT
+
+/**
+ * \def MBEDTLS_AES_ALT
+ *
+ * MBEDTLS__MODULE_NAME__ALT: Uncomment a macro to let mbed TLS use your
+ * alternate core implementation of a symmetric crypto or hash module (e.g.
+ * platform specific assembly optimized implementations). Keep in mind that
+ * the function prototypes should remain the same.
+ *
+ * This replaces the whole module. If you only want to replace one of the
+ * functions, use one of the MBEDTLS__FUNCTION_NAME__ALT flags.
+ *
+ * Example: In case you uncomment MBEDTLS_AES_ALT, mbed TLS will no longer
+ * provide the "struct mbedtls_aes_context" definition and omit the base function
+ * declarations and implementations. "aes_alt.h" will be included from
+ * "aes.h" to include the new function definitions.
+ *
+ * Uncomment a macro to enable alternate implementation of the corresponding
+ * module.
+ */
+//#define MBEDTLS_AES_ALT
+//#define MBEDTLS_ARC4_ALT
+//#define MBEDTLS_BLOWFISH_ALT
+//#define MBEDTLS_CAMELLIA_ALT
+//#define MBEDTLS_DES_ALT
+//#define MBEDTLS_XTEA_ALT
+//#define MBEDTLS_MD2_ALT
+//#define MBEDTLS_MD4_ALT
+//#define MBEDTLS_MD5_ALT
+//#define MBEDTLS_RIPEMD160_ALT
+//#define MBEDTLS_SHA1_ALT
+//#define MBEDTLS_SHA256_ALT
+//#define MBEDTLS_SHA512_ALT
+
+/**
+ * \def MBEDTLS_MD2_PROCESS_ALT
+ *
+ * MBEDTLS__FUNCTION_NAME__ALT: Uncomment a macro to let mbed TLS use you
+ * alternate core implementation of symmetric crypto or hash function. Keep in
+ * mind that function prototypes should remain the same.
+ *
+ * This replaces only one function. The header file from mbed TLS is still
+ * used, in contrast to the MBEDTLS__MODULE_NAME__ALT flags.
+ *
+ * Example: In case you uncomment MBEDTLS_SHA256_PROCESS_ALT, mbed TLS will
+ * no longer provide the mbedtls_sha1_process() function, but it will still provide
+ * the other function (using your mbedtls_sha1_process() function) and the definition
+ * of mbedtls_sha1_context, so your implementation of mbedtls_sha1_process must be compatible
+ * with this definition.
+ *
+ * Note: if you use the AES_xxx_ALT macros, then is is recommended to also set
+ * MBEDTLS_AES_ROM_TABLES in order to help the linker garbage-collect the AES
+ * tables.
+ *
+ * Uncomment a macro to enable alternate implementation of the corresponding
+ * function.
+ */
+//#define MBEDTLS_MD2_PROCESS_ALT
+//#define MBEDTLS_MD4_PROCESS_ALT
+//#define MBEDTLS_MD5_PROCESS_ALT
+//#define MBEDTLS_RIPEMD160_PROCESS_ALT
+//#define MBEDTLS_SHA1_PROCESS_ALT
+//#define MBEDTLS_SHA256_PROCESS_ALT
+//#define MBEDTLS_SHA512_PROCESS_ALT
+//#define MBEDTLS_DES_SETKEY_ALT
+//#define MBEDTLS_DES_CRYPT_ECB_ALT
+//#define MBEDTLS_DES3_CRYPT_ECB_ALT
+//#define MBEDTLS_AES_SETKEY_ENC_ALT
+//#define MBEDTLS_AES_SETKEY_DEC_ALT
+//#define MBEDTLS_AES_ENCRYPT_ALT
+//#define MBEDTLS_AES_DECRYPT_ALT
+
+/**
+ * \def MBEDTLS_TEST_NULL_ENTROPY
+ *
+ * Enables testing and use of mbed TLS without any configured entropy sources.
+ * This permits use of the library on platforms before an entropy source has
+ * been integrated (see for example the MBEDTLS_ENTROPY_HARDWARE_ALT or the
+ * MBEDTLS_ENTROPY_NV_SEED switches).
+ *
+ * WARNING! This switch MUST be disabled in production builds, and is suitable
+ * only for development.
+ * Enabling the switch negates any security provided by the library.
+ *
+ * Requires MBEDTLS_ENTROPY_C, MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES
+ *
+ */
+//#define MBEDTLS_TEST_NULL_ENTROPY
+
+/**
+ * \def MBEDTLS_ENTROPY_HARDWARE_ALT
+ *
+ * Uncomment this macro to let mbed TLS use your own implementation of a
+ * hardware entropy collector.
+ *
+ * Your function must be called \c mbedtls_hardware_poll(), have the same
+ * prototype as declared in entropy_poll.h, and accept NULL as first argument.
+ *
+ * Uncomment to use your own hardware entropy collector.
+ */
+//#define MBEDTLS_ENTROPY_HARDWARE_ALT
+
+/**
+ * \def MBEDTLS_AES_ROM_TABLES
+ *
+ * Store the AES tables in ROM.
+ *
+ * Uncomment this macro to store the AES tables in ROM.
+ */
+//#define MBEDTLS_AES_ROM_TABLES
+
+/**
+ * \def MBEDTLS_CAMELLIA_SMALL_MEMORY
+ *
+ * Use less ROM for the Camellia implementation (saves about 768 bytes).
+ *
+ * Uncomment this macro to use less memory for Camellia.
+ */
+//#define MBEDTLS_CAMELLIA_SMALL_MEMORY
+
+/**
+ * \def MBEDTLS_CIPHER_MODE_CBC
+ *
+ * Enable Cipher Block Chaining mode (CBC) for symmetric ciphers.
+ */
+#define MBEDTLS_CIPHER_MODE_CBC
+
+/**
+ * \def MBEDTLS_CIPHER_MODE_CFB
+ *
+ * Enable Cipher Feedback mode (CFB) for symmetric ciphers.
+ */
+#define MBEDTLS_CIPHER_MODE_CFB
+
+/**
+ * \def MBEDTLS_CIPHER_MODE_CTR
+ *
+ * Enable Counter Block Cipher mode (CTR) for symmetric ciphers.
+ */
+#define MBEDTLS_CIPHER_MODE_CTR
+
+/**
+ * \def MBEDTLS_CIPHER_NULL_CIPHER
+ *
+ * Enable NULL cipher.
+ * Warning: Only do so when you know what you are doing. This allows for
+ * encryption or channels without any security!
+ *
+ * Requires MBEDTLS_ENABLE_WEAK_CIPHERSUITES as well to enable
+ * the following ciphersuites:
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_NULL_SHA
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_NULL_SHA
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_NULL_SHA
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_NULL_SHA
+ *      MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA384
+ *      MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA256
+ *      MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA
+ *      MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA384
+ *      MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA256
+ *      MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA
+ *      MBEDTLS_TLS_RSA_WITH_NULL_SHA256
+ *      MBEDTLS_TLS_RSA_WITH_NULL_SHA
+ *      MBEDTLS_TLS_RSA_WITH_NULL_MD5
+ *      MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA384
+ *      MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA256
+ *      MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA
+ *      MBEDTLS_TLS_PSK_WITH_NULL_SHA384
+ *      MBEDTLS_TLS_PSK_WITH_NULL_SHA256
+ *      MBEDTLS_TLS_PSK_WITH_NULL_SHA
+ *
+ * Uncomment this macro to enable the NULL cipher and ciphersuites
+ */
+//#define MBEDTLS_CIPHER_NULL_CIPHER
+
+/**
+ * \def MBEDTLS_CIPHER_PADDING_PKCS7
+ *
+ * MBEDTLS_CIPHER_PADDING_XXX: Uncomment or comment macros to add support for
+ * specific padding modes in the cipher layer with cipher modes that support
+ * padding (e.g. CBC)
+ *
+ * If you disable all padding modes, only full blocks can be used with CBC.
+ *
+ * Enable padding modes in the cipher layer.
+ */
+#define MBEDTLS_CIPHER_PADDING_PKCS7
+#define MBEDTLS_CIPHER_PADDING_ONE_AND_ZEROS
+#define MBEDTLS_CIPHER_PADDING_ZEROS_AND_LEN
+#define MBEDTLS_CIPHER_PADDING_ZEROS
+
+/**
+ * \def MBEDTLS_ENABLE_WEAK_CIPHERSUITES
+ *
+ * Enable weak ciphersuites in SSL / TLS.
+ * Warning: Only do so when you know what you are doing. This allows for
+ * channels with virtually no security at all!
+ *
+ * This enables the following ciphersuites:
+ *      MBEDTLS_TLS_RSA_WITH_DES_CBC_SHA
+ *      MBEDTLS_TLS_DHE_RSA_WITH_DES_CBC_SHA
+ *
+ * Uncomment this macro to enable weak ciphersuites
+ */
+//#define MBEDTLS_ENABLE_WEAK_CIPHERSUITES
+
+/**
+ * \def MBEDTLS_REMOVE_ARC4_CIPHERSUITES
+ *
+ * Remove RC4 ciphersuites by default in SSL / TLS.
+ * This flag removes the ciphersuites based on RC4 from the default list as
+ * returned by mbedtls_ssl_list_ciphersuites(). However, it is still possible to
+ * enable (some of) them with mbedtls_ssl_conf_ciphersuites() by including them
+ * explicitly.
+ *
+ * Uncomment this macro to remove RC4 ciphersuites by default.
+ */
+#define MBEDTLS_REMOVE_ARC4_CIPHERSUITES
+
+/**
+ * \def MBEDTLS_ECP_DP_SECP192R1_ENABLED
+ *
+ * MBEDTLS_ECP_XXXX_ENABLED: Enables specific curves within the Elliptic Curve
+ * module.  By default all supported curves are enabled.
+ *
+ * Comment macros to disable the curve and functions for it
+ */
+#define MBEDTLS_ECP_DP_SECP192R1_ENABLED
+#define MBEDTLS_ECP_DP_SECP224R1_ENABLED
+#define MBEDTLS_ECP_DP_SECP256R1_ENABLED
+#define MBEDTLS_ECP_DP_SECP384R1_ENABLED
+#define MBEDTLS_ECP_DP_SECP521R1_ENABLED
+#define MBEDTLS_ECP_DP_SECP192K1_ENABLED
+#define MBEDTLS_ECP_DP_SECP224K1_ENABLED
+#define MBEDTLS_ECP_DP_SECP256K1_ENABLED
+#define MBEDTLS_ECP_DP_BP256R1_ENABLED
+#define MBEDTLS_ECP_DP_BP384R1_ENABLED
+#define MBEDTLS_ECP_DP_BP512R1_ENABLED
+#define MBEDTLS_ECP_DP_CURVE25519_ENABLED
+
+/**
+ * \def MBEDTLS_ECP_NIST_OPTIM
+ *
+ * Enable specific 'modulo p' routines for each NIST prime.
+ * Depending on the prime and architecture, makes operations 4 to 8 times
+ * faster on the corresponding curve.
+ *
+ * Comment this macro to disable NIST curves optimisation.
+ */
+#define MBEDTLS_ECP_NIST_OPTIM
+
+/**
+ * \def MBEDTLS_ECDSA_DETERMINISTIC
+ *
+ * Enable deterministic ECDSA (RFC 6979).
+ * Standard ECDSA is "fragile" in the sense that lack of entropy when signing
+ * may result in a compromise of the long-term signing key. This is avoided by
+ * the deterministic variant.
+ *
+ * Requires: MBEDTLS_HMAC_DRBG_C
+ *
+ * Comment this macro to disable deterministic ECDSA.
+ */
+#define MBEDTLS_ECDSA_DETERMINISTIC
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_PSK_ENABLED
+ *
+ * Enable the PSK based ciphersuite modes in SSL / TLS.
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ *      MBEDTLS_TLS_PSK_WITH_AES_256_GCM_SHA384
+ *      MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA384
+ *      MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA
+ *      MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_GCM_SHA384
+ *      MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_CBC_SHA384
+ *      MBEDTLS_TLS_PSK_WITH_AES_128_GCM_SHA256
+ *      MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA256
+ *      MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA
+ *      MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_GCM_SHA256
+ *      MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256
+ *      MBEDTLS_TLS_PSK_WITH_3DES_EDE_CBC_SHA
+ *      MBEDTLS_TLS_PSK_WITH_RC4_128_SHA
+ */
+#define MBEDTLS_KEY_EXCHANGE_PSK_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED
+ *
+ * Enable the DHE-PSK based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_DHM_C
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ *      MBEDTLS_TLS_DHE_PSK_WITH_AES_256_GCM_SHA384
+ *      MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA384
+ *      MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA
+ *      MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_GCM_SHA384
+ *      MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_CBC_SHA384
+ *      MBEDTLS_TLS_DHE_PSK_WITH_AES_128_GCM_SHA256
+ *      MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA256
+ *      MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA
+ *      MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_GCM_SHA256
+ *      MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_CBC_SHA256
+ *      MBEDTLS_TLS_DHE_PSK_WITH_3DES_EDE_CBC_SHA
+ *      MBEDTLS_TLS_DHE_PSK_WITH_RC4_128_SHA
+ */
+#define MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED
+ *
+ * Enable the ECDHE-PSK based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_ECDH_C
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ *      MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA384
+ *      MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA
+ *      MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_256_CBC_SHA384
+ *      MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA256
+ *      MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA
+ *      MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_128_CBC_SHA256
+ *      MBEDTLS_TLS_ECDHE_PSK_WITH_3DES_EDE_CBC_SHA
+ *      MBEDTLS_TLS_ECDHE_PSK_WITH_RC4_128_SHA
+ */
+#define MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED
+ *
+ * Enable the RSA-PSK based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15,
+ *           MBEDTLS_X509_CRT_PARSE_C
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ *      MBEDTLS_TLS_RSA_PSK_WITH_AES_256_GCM_SHA384
+ *      MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA384
+ *      MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA
+ *      MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_GCM_SHA384
+ *      MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_CBC_SHA384
+ *      MBEDTLS_TLS_RSA_PSK_WITH_AES_128_GCM_SHA256
+ *      MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA256
+ *      MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA
+ *      MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_GCM_SHA256
+ *      MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_CBC_SHA256
+ *      MBEDTLS_TLS_RSA_PSK_WITH_3DES_EDE_CBC_SHA
+ *      MBEDTLS_TLS_RSA_PSK_WITH_RC4_128_SHA
+ */
+#define MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_RSA_ENABLED
+ *
+ * Enable the RSA-only based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15,
+ *           MBEDTLS_X509_CRT_PARSE_C
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ *      MBEDTLS_TLS_RSA_WITH_AES_256_GCM_SHA384
+ *      MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA256
+ *      MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA
+ *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_GCM_SHA384
+ *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256
+ *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA
+ *      MBEDTLS_TLS_RSA_WITH_AES_128_GCM_SHA256
+ *      MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA256
+ *      MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA
+ *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_GCM_SHA256
+ *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256
+ *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA
+ *      MBEDTLS_TLS_RSA_WITH_3DES_EDE_CBC_SHA
+ *      MBEDTLS_TLS_RSA_WITH_RC4_128_SHA
+ *      MBEDTLS_TLS_RSA_WITH_RC4_128_MD5
+ */
+#define MBEDTLS_KEY_EXCHANGE_RSA_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED
+ *
+ * Enable the DHE-RSA based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_DHM_C, MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15,
+ *           MBEDTLS_X509_CRT_PARSE_C
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ *      MBEDTLS_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384
+ *      MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA256
+ *      MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA
+ *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_GCM_SHA384
+ *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256
+ *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA
+ *      MBEDTLS_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256
+ *      MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA256
+ *      MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA
+ *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_GCM_SHA256
+ *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256
+ *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA
+ *      MBEDTLS_TLS_DHE_RSA_WITH_3DES_EDE_CBC_SHA
+ */
+#define MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED
+ *
+ * Enable the ECDHE-RSA based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_ECDH_C, MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15,
+ *           MBEDTLS_X509_CRT_PARSE_C
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_GCM_SHA384
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_CBC_SHA384
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_GCM_SHA256
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_CBC_SHA256
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_RC4_128_SHA
+ */
+#define MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED
+ *
+ * Enable the ECDHE-ECDSA based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_ECDH_C, MBEDTLS_ECDSA_C, MBEDTLS_X509_CRT_PARSE_C,
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_GCM_SHA384
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_CBC_SHA384
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_GCM_SHA256
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_CBC_SHA256
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_RC4_128_SHA
+ */
+#define MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED
+ *
+ * Enable the ECDH-ECDSA based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_ECDH_C, MBEDTLS_X509_CRT_PARSE_C
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_RC4_128_SHA
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_3DES_EDE_CBC_SHA
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_CBC_SHA256
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_CBC_SHA384
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_GCM_SHA256
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_GCM_SHA384
+ */
+#define MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED
+ *
+ * Enable the ECDH-RSA based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_ECDH_C, MBEDTLS_X509_CRT_PARSE_C
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_RC4_128_SHA
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_3DES_EDE_CBC_SHA
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_CBC_SHA256
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_CBC_SHA384
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_GCM_SHA256
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_GCM_SHA384
+ */
+#define MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED
+ *
+ * Enable the ECJPAKE based ciphersuite modes in SSL / TLS.
+ *
+ * \warning This is currently experimental. EC J-PAKE support is based on the
+ * Thread v1.0.0 specification; incompatible changes to the specification
+ * might still happen. For this reason, this is disabled by default.
+ *
+ * Requires: MBEDTLS_ECJPAKE_C
+ *           MBEDTLS_SHA256_C
+ *           MBEDTLS_ECP_DP_SECP256R1_ENABLED
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ *      MBEDTLS_TLS_ECJPAKE_WITH_AES_128_CCM_8
+ */
+//#define MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED
+
+/**
+ * \def MBEDTLS_PK_PARSE_EC_EXTENDED
+ *
+ * Enhance support for reading EC keys using variants of SEC1 not allowed by
+ * RFC 5915 and RFC 5480.
+ *
+ * Currently this means parsing the SpecifiedECDomain choice of EC
+ * parameters (only known groups are supported, not arbitrary domains, to
+ * avoid validation issues).
+ *
+ * Disable if you only need to support RFC 5915 + 5480 key formats.
+ */
+#define MBEDTLS_PK_PARSE_EC_EXTENDED
+
+/**
+ * \def MBEDTLS_ERROR_STRERROR_DUMMY
+ *
+ * Enable a dummy error function to make use of mbedtls_strerror() in
+ * third party libraries easier when MBEDTLS_ERROR_C is disabled
+ * (no effect when MBEDTLS_ERROR_C is enabled).
+ *
+ * You can safely disable this if MBEDTLS_ERROR_C is enabled, or if you're
+ * not using mbedtls_strerror() or error_strerror() in your application.
+ *
+ * Disable if you run into name conflicts and want to really remove the
+ * mbedtls_strerror()
+ */
+#define MBEDTLS_ERROR_STRERROR_DUMMY
+
+/**
+ * \def MBEDTLS_GENPRIME
+ *
+ * Enable the prime-number generation code.
+ *
+ * Requires: MBEDTLS_BIGNUM_C
+ */
+#define MBEDTLS_GENPRIME
+
+/**
+ * \def MBEDTLS_FS_IO
+ *
+ * Enable functions that use the filesystem.
+ */
+#define MBEDTLS_FS_IO
+
+/**
+ * \def MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES
+ *
+ * Do not add default entropy sources. These are the platform specific,
+ * mbedtls_timing_hardclock and HAVEGE based poll functions.
+ *
+ * This is useful to have more control over the added entropy sources in an
+ * application.
+ *
+ * Uncomment this macro to prevent loading of default entropy functions.
+ */
+//#define MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES
+
+/**
+ * \def MBEDTLS_NO_PLATFORM_ENTROPY
+ *
+ * Do not use built-in platform entropy functions.
+ * This is useful if your platform does not support
+ * standards like the /dev/urandom or Windows CryptoAPI.
+ *
+ * Uncomment this macro to disable the built-in platform entropy functions.
+ */
+//#define MBEDTLS_NO_PLATFORM_ENTROPY
+
+/**
+ * \def MBEDTLS_ENTROPY_FORCE_SHA256
+ *
+ * Force the entropy accumulator to use a SHA-256 accumulator instead of the
+ * default SHA-512 based one (if both are available).
+ *
+ * Requires: MBEDTLS_SHA256_C
+ *
+ * On 32-bit systems SHA-256 can be much faster than SHA-512. Use this option
+ * if you have performance concerns.
+ *
+ * This option is only useful if both MBEDTLS_SHA256_C and
+ * MBEDTLS_SHA512_C are defined. Otherwise the available hash module is used.
+ */
+//#define MBEDTLS_ENTROPY_FORCE_SHA256
+
+/**
+ * \def MBEDTLS_ENTROPY_NV_SEED
+ *
+ * Enable the non-volatile (NV) seed file-based entropy source.
+ * (Also enables the NV seed read/write functions in the platform layer)
+ *
+ * This is crucial (if not required) on systems that do not have a
+ * cryptographic entropy source (in hardware or kernel) available.
+ *
+ * Requires: MBEDTLS_ENTROPY_C, MBEDTLS_PLATFORM_C
+ *
+ * \note The read/write functions that are used by the entropy source are
+ *       determined in the platform layer, and can be modified at runtime and/or
+ *       compile-time depending on the flags (MBEDTLS_PLATFORM_NV_SEED_*) used.
+ *
+ * \note If you use the default implementation functions that read a seedfile
+ *       with regular fopen(), please make sure you make a seedfile with the
+ *       proper name (defined in MBEDTLS_PLATFORM_STD_NV_SEED_FILE) and at
+ *       least MBEDTLS_ENTROPY_BLOCK_SIZE bytes in size that can be read from
+ *       and written to or you will get an entropy source error! The default
+ *       implementation will only use the first MBEDTLS_ENTROPY_BLOCK_SIZE
+ *       bytes from the file.
+ *
+ * \note The entropy collector will write to the seed file before entropy is
+ *       given to an external source, to update it.
+ */
+//#define MBEDTLS_ENTROPY_NV_SEED
+
+/**
+ * \def MBEDTLS_MEMORY_DEBUG
+ *
+ * Enable debugging of buffer allocator memory issues. Automatically prints
+ * (to stderr) all (fatal) messages on memory allocation issues. Enables
+ * function for 'debug output' of allocated memory.
+ *
+ * Requires: MBEDTLS_MEMORY_BUFFER_ALLOC_C
+ *
+ * Uncomment this macro to let the buffer allocator print out error messages.
+ */
+//#define MBEDTLS_MEMORY_DEBUG
+
+/**
+ * \def MBEDTLS_MEMORY_BACKTRACE
+ *
+ * Include backtrace information with each allocated block.
+ *
+ * Requires: MBEDTLS_MEMORY_BUFFER_ALLOC_C
+ *           GLIBC-compatible backtrace() an backtrace_symbols() support
+ *
+ * Uncomment this macro to include backtrace information
+ */
+//#define MBEDTLS_MEMORY_BACKTRACE
+
+/**
+ * \def MBEDTLS_PK_RSA_ALT_SUPPORT
+ *
+ * Support external private RSA keys (eg from a HSM) in the PK layer.
+ *
+ * Comment this macro to disable support for external private RSA keys.
+ */
+#define MBEDTLS_PK_RSA_ALT_SUPPORT
+
+/**
+ * \def MBEDTLS_PKCS1_V15
+ *
+ * Enable support for PKCS#1 v1.5 encoding.
+ *
+ * Requires: MBEDTLS_RSA_C
+ *
+ * This enables support for PKCS#1 v1.5 operations.
+ */
+#define MBEDTLS_PKCS1_V15
+
+/**
+ * \def MBEDTLS_PKCS1_V21
+ *
+ * Enable support for PKCS#1 v2.1 encoding.
+ *
+ * Requires: MBEDTLS_MD_C, MBEDTLS_RSA_C
+ *
+ * This enables support for RSAES-OAEP and RSASSA-PSS operations.
+ */
+#define MBEDTLS_PKCS1_V21
+
+/**
+ * \def MBEDTLS_RSA_NO_CRT
+ *
+ * Do not use the Chinese Remainder Theorem for the RSA private operation.
+ *
+ * Uncomment this macro to disable the use of CRT in RSA.
+ *
+ */
+//#define MBEDTLS_RSA_NO_CRT
+
+/**
+ * \def MBEDTLS_SELF_TEST
+ *
+ * Enable the checkup functions (*_self_test).
+ */
+#define MBEDTLS_SELF_TEST
+
+/**
+ * \def MBEDTLS_SHA256_SMALLER
+ *
+ * Enable an implementation of SHA-256 that has lower ROM footprint but also
+ * lower performance.
+ *
+ * The default implementation is meant to be a reasonnable compromise between
+ * performance and size. This version optimizes more aggressively for size at
+ * the expense of performance. Eg on Cortex-M4 it reduces the size of
+ * mbedtls_sha256_process() from ~2KB to ~0.5KB for a performance hit of about
+ * 30%.
+ *
+ * Uncomment to enable the smaller implementation of SHA256.
+ */
+//#define MBEDTLS_SHA256_SMALLER
+
+/**
+ * \def MBEDTLS_SSL_AEAD_RANDOM_IV
+ *
+ * Generate a random IV rather than using the record sequence number as a
+ * nonce for ciphersuites using and AEAD algorithm (GCM or CCM).
+ *
+ * Using the sequence number is generally recommended.
+ *
+ * Uncomment this macro to always use random IVs with AEAD ciphersuites.
+ */
+//#define MBEDTLS_SSL_AEAD_RANDOM_IV
+
+/**
+ * \def MBEDTLS_SSL_ALL_ALERT_MESSAGES
+ *
+ * Enable sending of alert messages in case of encountered errors as per RFC.
+ * If you choose not to send the alert messages, mbed TLS can still communicate
+ * with other servers, only debugging of failures is harder.
+ *
+ * The advantage of not sending alert messages, is that no information is given
+ * about reasons for failures thus preventing adversaries of gaining intel.
+ *
+ * Enable sending of all alert messages
+ */
+#define MBEDTLS_SSL_ALL_ALERT_MESSAGES
+
+/**
+ * \def MBEDTLS_SSL_DEBUG_ALL
+ *
+ * Enable the debug messages in SSL module for all issues.
+ * Debug messages have been disabled in some places to prevent timing
+ * attacks due to (unbalanced) debugging function calls.
+ *
+ * If you need all error reporting you should enable this during debugging,
+ * but remove this for production servers that should log as well.
+ *
+ * Uncomment this macro to report all debug messages on errors introducing
+ * a timing side-channel.
+ *
+ */
+//#define MBEDTLS_SSL_DEBUG_ALL
+
+/** \def MBEDTLS_SSL_ENCRYPT_THEN_MAC
+ *
+ * Enable support for Encrypt-then-MAC, RFC 7366.
+ *
+ * This allows peers that both support it to use a more robust protection for
+ * ciphersuites using CBC, providing deep resistance against timing attacks
+ * on the padding or underlying cipher.
+ *
+ * This only affects CBC ciphersuites, and is useless if none is defined.
+ *
+ * Requires: MBEDTLS_SSL_PROTO_TLS1    or
+ *           MBEDTLS_SSL_PROTO_TLS1_1  or
+ *           MBEDTLS_SSL_PROTO_TLS1_2
+ *
+ * Comment this macro to disable support for Encrypt-then-MAC
+ */
+#define MBEDTLS_SSL_ENCRYPT_THEN_MAC
+
+/** \def MBEDTLS_SSL_EXTENDED_MASTER_SECRET
+ *
+ * Enable support for Extended Master Secret, aka Session Hash
+ * (draft-ietf-tls-session-hash-02).
+ *
+ * This was introduced as "the proper fix" to the Triple Handshake familiy of
+ * attacks, but it is recommended to always use it (even if you disable
+ * renegotiation), since it actually fixes a more fundamental issue in the
+ * original SSL/TLS design, and has implications beyond Triple Handshake.
+ *
+ * Requires: MBEDTLS_SSL_PROTO_TLS1    or
+ *           MBEDTLS_SSL_PROTO_TLS1_1  or
+ *           MBEDTLS_SSL_PROTO_TLS1_2
+ *
+ * Comment this macro to disable support for Extended Master Secret.
+ */
+#define MBEDTLS_SSL_EXTENDED_MASTER_SECRET
+
+/**
+ * \def MBEDTLS_SSL_FALLBACK_SCSV
+ *
+ * Enable support for FALLBACK_SCSV (draft-ietf-tls-downgrade-scsv-00).
+ *
+ * For servers, it is recommended to always enable this, unless you support
+ * only one version of TLS, or know for sure that none of your clients
+ * implements a fallback strategy.
+ *
+ * For clients, you only need this if you're using a fallback strategy, which
+ * is not recommended in the first place, unless you absolutely need it to
+ * interoperate with buggy (version-intolerant) servers.
+ *
+ * Comment this macro to disable support for FALLBACK_SCSV
+ */
+#define MBEDTLS_SSL_FALLBACK_SCSV
+
+/**
+ * \def MBEDTLS_SSL_HW_RECORD_ACCEL
+ *
+ * Enable hooking functions in SSL module for hardware acceleration of
+ * individual records.
+ *
+ * Uncomment this macro to enable hooking functions.
+ */
+//#define MBEDTLS_SSL_HW_RECORD_ACCEL
+
+/**
+ * \def MBEDTLS_SSL_CBC_RECORD_SPLITTING
+ *
+ * Enable 1/n-1 record splitting for CBC mode in SSLv3 and TLS 1.0.
+ *
+ * This is a countermeasure to the BEAST attack, which also minimizes the risk
+ * of interoperability issues compared to sending 0-length records.
+ *
+ * Comment this macro to disable 1/n-1 record splitting.
+ */
+#define MBEDTLS_SSL_CBC_RECORD_SPLITTING
+
+/**
+ * \def MBEDTLS_SSL_RENEGOTIATION
+ *
+ * Disable support for TLS renegotiation.
+ *
+ * The two main uses of renegotiation are (1) refresh keys on long-lived
+ * connections and (2) client authentication after the initial handshake.
+ * If you don't need renegotiation, it's probably better to disable it, since
+ * it has been associated with security issues in the past and is easy to
+ * misuse/misunderstand.
+ *
+ * Comment this to disable support for renegotiation.
+ */
+#define MBEDTLS_SSL_RENEGOTIATION
+
+/**
+ * \def MBEDTLS_SSL_SRV_SUPPORT_SSLV2_CLIENT_HELLO
+ *
+ * Enable support for receiving and parsing SSLv2 Client Hello messages for the
+ * SSL Server module (MBEDTLS_SSL_SRV_C).
+ *
+ * Uncomment this macro to enable support for SSLv2 Client Hello messages.
+ */
+//#define MBEDTLS_SSL_SRV_SUPPORT_SSLV2_CLIENT_HELLO
+
+/**
+ * \def MBEDTLS_SSL_SRV_RESPECT_CLIENT_PREFERENCE
+ *
+ * Pick the ciphersuite according to the client's preferences rather than ours
+ * in the SSL Server module (MBEDTLS_SSL_SRV_C).
+ *
+ * Uncomment this macro to respect client's ciphersuite order
+ */
+//#define MBEDTLS_SSL_SRV_RESPECT_CLIENT_PREFERENCE
+
+/**
+ * \def MBEDTLS_SSL_MAX_FRAGMENT_LENGTH
+ *
+ * Enable support for RFC 6066 max_fragment_length extension in SSL.
+ *
+ * Comment this macro to disable support for the max_fragment_length extension
+ */
+#define MBEDTLS_SSL_MAX_FRAGMENT_LENGTH
+
+/**
+ * \def MBEDTLS_SSL_PROTO_SSL3
+ *
+ * Enable support for SSL 3.0.
+ *
+ * Requires: MBEDTLS_MD5_C
+ *           MBEDTLS_SHA1_C
+ *
+ * Comment this macro to disable support for SSL 3.0
+ */
+//#define MBEDTLS_SSL_PROTO_SSL3
+
+/**
+ * \def MBEDTLS_SSL_PROTO_TLS1
+ *
+ * Enable support for TLS 1.0.
+ *
+ * Requires: MBEDTLS_MD5_C
+ *           MBEDTLS_SHA1_C
+ *
+ * Comment this macro to disable support for TLS 1.0
+ */
+#define MBEDTLS_SSL_PROTO_TLS1
+
+/**
+ * \def MBEDTLS_SSL_PROTO_TLS1_1
+ *
+ * Enable support for TLS 1.1 (and DTLS 1.0 if DTLS is enabled).
+ *
+ * Requires: MBEDTLS_MD5_C
+ *           MBEDTLS_SHA1_C
+ *
+ * Comment this macro to disable support for TLS 1.1 / DTLS 1.0
+ */
+#define MBEDTLS_SSL_PROTO_TLS1_1
+
+/**
+ * \def MBEDTLS_SSL_PROTO_TLS1_2
+ *
+ * Enable support for TLS 1.2 (and DTLS 1.2 if DTLS is enabled).
+ *
+ * Requires: MBEDTLS_SHA1_C or MBEDTLS_SHA256_C or MBEDTLS_SHA512_C
+ *           (Depends on ciphersuites)
+ *
+ * Comment this macro to disable support for TLS 1.2 / DTLS 1.2
+ */
+#define MBEDTLS_SSL_PROTO_TLS1_2
+
+/**
+ * \def MBEDTLS_SSL_PROTO_DTLS
+ *
+ * Enable support for DTLS (all available versions).
+ *
+ * Enable this and MBEDTLS_SSL_PROTO_TLS1_1 to enable DTLS 1.0,
+ * and/or this and MBEDTLS_SSL_PROTO_TLS1_2 to enable DTLS 1.2.
+ *
+ * Requires: MBEDTLS_SSL_PROTO_TLS1_1
+ *        or MBEDTLS_SSL_PROTO_TLS1_2
+ *
+ * Comment this macro to disable support for DTLS
+ */
+#define MBEDTLS_SSL_PROTO_DTLS
+
+/**
+ * \def MBEDTLS_SSL_ALPN
+ *
+ * Enable support for RFC 7301 Application Layer Protocol Negotiation.
+ *
+ * Comment this macro to disable support for ALPN.
+ */
+#define MBEDTLS_SSL_ALPN
+
+/**
+ * \def MBEDTLS_SSL_DTLS_ANTI_REPLAY
+ *
+ * Enable support for the anti-replay mechanism in DTLS.
+ *
+ * Requires: MBEDTLS_SSL_TLS_C
+ *           MBEDTLS_SSL_PROTO_DTLS
+ *
+ * \warning Disabling this is often a security risk!
+ * See mbedtls_ssl_conf_dtls_anti_replay() for details.
+ *
+ * Comment this to disable anti-replay in DTLS.
+ */
+#define MBEDTLS_SSL_DTLS_ANTI_REPLAY
+
+/**
+ * \def MBEDTLS_SSL_DTLS_HELLO_VERIFY
+ *
+ * Enable support for HelloVerifyRequest on DTLS servers.
+ *
+ * This feature is highly recommended to prevent DTLS servers being used as
+ * amplifiers in DoS attacks against other hosts. It should always be enabled
+ * unless you know for sure amplification cannot be a problem in the
+ * environment in which your server operates.
+ *
+ * \warning Disabling this can ba a security risk! (see above)
+ *
+ * Requires: MBEDTLS_SSL_PROTO_DTLS
+ *
+ * Comment this to disable support for HelloVerifyRequest.
+ */
+#define MBEDTLS_SSL_DTLS_HELLO_VERIFY
+
+/**
+ * \def MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE
+ *
+ * Enable server-side support for clients that reconnect from the same port.
+ *
+ * Some clients unexpectedly close the connection and try to reconnect using the
+ * same source port. This needs special support from the server to handle the
+ * new connection securely, as described in section 4.2.8 of RFC 6347. This
+ * flag enables that support.
+ *
+ * Requires: MBEDTLS_SSL_DTLS_HELLO_VERIFY
+ *
+ * Comment this to disable support for clients reusing the source port.
+ */
+#define MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE
+
+/**
+ * \def MBEDTLS_SSL_DTLS_BADMAC_LIMIT
+ *
+ * Enable support for a limit of records with bad MAC.
+ *
+ * See mbedtls_ssl_conf_dtls_badmac_limit().
+ *
+ * Requires: MBEDTLS_SSL_PROTO_DTLS
+ */
+#define MBEDTLS_SSL_DTLS_BADMAC_LIMIT
+
+/**
+ * \def MBEDTLS_SSL_SESSION_TICKETS
+ *
+ * Enable support for RFC 5077 session tickets in SSL.
+ * Client-side, provides full support for session tickets (maintainance of a
+ * session store remains the responsibility of the application, though).
+ * Server-side, you also need to provide callbacks for writing and parsing
+ * tickets, including authenticated encryption and key management. Example
+ * callbacks are provided by MBEDTLS_SSL_TICKET_C.
+ *
+ * Comment this macro to disable support for SSL session tickets
+ */
+#define MBEDTLS_SSL_SESSION_TICKETS
+
+/**
+ * \def MBEDTLS_SSL_EXPORT_KEYS
+ *
+ * Enable support for exporting key block and master secret.
+ * This is required for certain users of TLS, e.g. EAP-TLS.
+ *
+ * Comment this macro to disable support for key export
+ */
+#define MBEDTLS_SSL_EXPORT_KEYS
+
+/**
+ * \def MBEDTLS_SSL_SERVER_NAME_INDICATION
+ *
+ * Enable support for RFC 6066 server name indication (SNI) in SSL.
+ *
+ * Requires: MBEDTLS_X509_CRT_PARSE_C
+ *
+ * Comment this macro to disable support for server name indication in SSL
+ */
+#define MBEDTLS_SSL_SERVER_NAME_INDICATION
+
+/**
+ * \def MBEDTLS_SSL_TRUNCATED_HMAC
+ *
+ * Enable support for RFC 6066 truncated HMAC in SSL.
+ *
+ * Comment this macro to disable support for truncated HMAC in SSL
+ */
+#define MBEDTLS_SSL_TRUNCATED_HMAC
+
+/**
+ * \def MBEDTLS_THREADING_ALT
+ *
+ * Provide your own alternate threading implementation.
+ *
+ * Requires: MBEDTLS_THREADING_C
+ *
+ * Uncomment this to allow your own alternate threading implementation.
+ */
+//#define MBEDTLS_THREADING_ALT
+
+/**
+ * \def MBEDTLS_THREADING_PTHREAD
+ *
+ * Enable the pthread wrapper layer for the threading layer.
+ *
+ * Requires: MBEDTLS_THREADING_C
+ *
+ * Uncomment this to enable pthread mutexes.
+ */
+//#define MBEDTLS_THREADING_PTHREAD
+
+/**
+ * \def MBEDTLS_VERSION_FEATURES
+ *
+ * Allow run-time checking of compile-time enabled features. Thus allowing users
+ * to check at run-time if the library is for instance compiled with threading
+ * support via mbedtls_version_check_feature().
+ *
+ * Requires: MBEDTLS_VERSION_C
+ *
+ * Comment this to disable run-time checking and save ROM space
+ */
+#define MBEDTLS_VERSION_FEATURES
+
+/**
+ * \def MBEDTLS_X509_ALLOW_EXTENSIONS_NON_V3
+ *
+ * If set, the X509 parser will not break-off when parsing an X509 certificate
+ * and encountering an extension in a v1 or v2 certificate.
+ *
+ * Uncomment to prevent an error.
+ */
+//#define MBEDTLS_X509_ALLOW_EXTENSIONS_NON_V3
+
+/**
+ * \def MBEDTLS_X509_ALLOW_UNSUPPORTED_CRITICAL_EXTENSION
+ *
+ * If set, the X509 parser will not break-off when parsing an X509 certificate
+ * and encountering an unknown critical extension.
+ *
+ * \warning Depending on your PKI use, enabling this can be a security risk!
+ *
+ * Uncomment to prevent an error.
+ */
+//#define MBEDTLS_X509_ALLOW_UNSUPPORTED_CRITICAL_EXTENSION
+
+/**
+ * \def MBEDTLS_X509_CHECK_KEY_USAGE
+ *
+ * Enable verification of the keyUsage extension (CA and leaf certificates).
+ *
+ * Disabling this avoids problems with mis-issued and/or misused
+ * (intermediate) CA and leaf certificates.
+ *
+ * \warning Depending on your PKI use, disabling this can be a security risk!
+ *
+ * Comment to skip keyUsage checking for both CA and leaf certificates.
+ */
+#define MBEDTLS_X509_CHECK_KEY_USAGE
+
+/**
+ * \def MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE
+ *
+ * Enable verification of the extendedKeyUsage extension (leaf certificates).
+ *
+ * Disabling this avoids problems with mis-issued and/or misused certificates.
+ *
+ * \warning Depending on your PKI use, disabling this can be a security risk!
+ *
+ * Comment to skip extendedKeyUsage checking for certificates.
+ */
+#define MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE
+
+/**
+ * \def MBEDTLS_X509_RSASSA_PSS_SUPPORT
+ *
+ * Enable parsing and verification of X.509 certificates, CRLs and CSRS
+ * signed with RSASSA-PSS (aka PKCS#1 v2.1).
+ *
+ * Comment this macro to disallow using RSASSA-PSS in certificates.
+ */
+#define MBEDTLS_X509_RSASSA_PSS_SUPPORT
+
+/**
+ * \def MBEDTLS_ZLIB_SUPPORT
+ *
+ * If set, the SSL/TLS module uses ZLIB to support compression and
+ * decompression of packet data.
+ *
+ * \warning TLS-level compression MAY REDUCE SECURITY! See for example the
+ * CRIME attack. Before enabling this option, you should examine with care if
+ * CRIME or similar exploits may be a applicable to your use case.
+ *
+ * \note Currently compression can't be used with DTLS.
+ *
+ * Used in: library/ssl_tls.c
+ *          library/ssl_cli.c
+ *          library/ssl_srv.c
+ *
+ * This feature requires zlib library and headers to be present.
+ *
+ * Uncomment to enable use of ZLIB
+ */
+//#define MBEDTLS_ZLIB_SUPPORT
+/* \} name SECTION: mbed TLS feature support */
+
+/**
+ * \name SECTION: mbed TLS modules
+ *
+ * This section enables or disables entire modules in mbed TLS
+ * \{
+ */
+
+/**
+ * \def MBEDTLS_AESNI_C
+ *
+ * Enable AES-NI support on x86-64.
+ *
+ * Module:  library/aesni.c
+ * Caller:  library/aes.c
+ *
+ * Requires: MBEDTLS_HAVE_ASM
+ *
+ * This modules adds support for the AES-NI instructions on x86-64
+ */
+#define MBEDTLS_AESNI_C
+
+/**
+ * \def MBEDTLS_AES_C
+ *
+ * Enable the AES block cipher.
+ *
+ * Module:  library/aes.c
+ * Caller:  library/ssl_tls.c
+ *          library/pem.c
+ *          library/ctr_drbg.c
+ *
+ * This module enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384
+ *      MBEDTLS_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384
+ *      MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA256
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA
+ *      MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256
+ *      MBEDTLS_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256
+ *      MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA256
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA
+ *      MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA
+ *      MBEDTLS_TLS_DHE_PSK_WITH_AES_256_GCM_SHA384
+ *      MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA384
+ *      MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA384
+ *      MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA
+ *      MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA
+ *      MBEDTLS_TLS_DHE_PSK_WITH_AES_128_GCM_SHA256
+ *      MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA256
+ *      MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA256
+ *      MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA
+ *      MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA
+ *      MBEDTLS_TLS_RSA_WITH_AES_256_GCM_SHA384
+ *      MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA256
+ *      MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA
+ *      MBEDTLS_TLS_RSA_WITH_AES_128_GCM_SHA256
+ *      MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA256
+ *      MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA
+ *      MBEDTLS_TLS_RSA_PSK_WITH_AES_256_GCM_SHA384
+ *      MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA384
+ *      MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA
+ *      MBEDTLS_TLS_RSA_PSK_WITH_AES_128_GCM_SHA256
+ *      MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA256
+ *      MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA
+ *      MBEDTLS_TLS_PSK_WITH_AES_256_GCM_SHA384
+ *      MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA384
+ *      MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA
+ *      MBEDTLS_TLS_PSK_WITH_AES_128_GCM_SHA256
+ *      MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA256
+ *      MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA
+ *
+ * PEM_PARSE uses AES for decrypting encrypted keys.
+ */
+#define MBEDTLS_AES_C
+
+/**
+ * \def MBEDTLS_ARC4_C
+ *
+ * Enable the ARCFOUR stream cipher.
+ *
+ * Module:  library/arc4.c
+ * Caller:  library/ssl_tls.c
+ *
+ * This module enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_RC4_128_SHA
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_RC4_128_SHA
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_RC4_128_SHA
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_RC4_128_SHA
+ *      MBEDTLS_TLS_ECDHE_PSK_WITH_RC4_128_SHA
+ *      MBEDTLS_TLS_DHE_PSK_WITH_RC4_128_SHA
+ *      MBEDTLS_TLS_RSA_WITH_RC4_128_SHA
+ *      MBEDTLS_TLS_RSA_WITH_RC4_128_MD5
+ *      MBEDTLS_TLS_RSA_PSK_WITH_RC4_128_SHA
+ *      MBEDTLS_TLS_PSK_WITH_RC4_128_SHA
+ */
+#define MBEDTLS_ARC4_C
+
+/**
+ * \def MBEDTLS_ASN1_PARSE_C
+ *
+ * Enable the generic ASN1 parser.
+ *
+ * Module:  library/asn1.c
+ * Caller:  library/x509.c
+ *          library/dhm.c
+ *          library/pkcs12.c
+ *          library/pkcs5.c
+ *          library/pkparse.c
+ */
+#define MBEDTLS_ASN1_PARSE_C
+
+/**
+ * \def MBEDTLS_ASN1_WRITE_C
+ *
+ * Enable the generic ASN1 writer.
+ *
+ * Module:  library/asn1write.c
+ * Caller:  library/ecdsa.c
+ *          library/pkwrite.c
+ *          library/x509_create.c
+ *          library/x509write_crt.c
+ *          library/mbedtls_x509write_csr.c
+ */
+#define MBEDTLS_ASN1_WRITE_C
+
+/**
+ * \def MBEDTLS_BASE64_C
+ *
+ * Enable the Base64 module.
+ *
+ * Module:  library/base64.c
+ * Caller:  library/pem.c
+ *
+ * This module is required for PEM support (required by X.509).
+ */
+#define MBEDTLS_BASE64_C
+
+/**
+ * \def MBEDTLS_BIGNUM_C
+ *
+ * Enable the multi-precision integer library.
+ *
+ * Module:  library/bignum.c
+ * Caller:  library/dhm.c
+ *          library/ecp.c
+ *          library/ecdsa.c
+ *          library/rsa.c
+ *          library/ssl_tls.c
+ *
+ * This module is required for RSA, DHM and ECC (ECDH, ECDSA) support.
+ */
+#define MBEDTLS_BIGNUM_C
+
+/**
+ * \def MBEDTLS_BLOWFISH_C
+ *
+ * Enable the Blowfish block cipher.
+ *
+ * Module:  library/blowfish.c
+ */
+#define MBEDTLS_BLOWFISH_C
+
+/**
+ * \def MBEDTLS_CAMELLIA_C
+ *
+ * Enable the Camellia block cipher.
+ *
+ * Module:  library/camellia.c
+ * Caller:  library/ssl_tls.c
+ *
+ * This module enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_CBC_SHA256
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_CBC_SHA384
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_CBC_SHA256
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_CBC_SHA384
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_GCM_SHA256
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_GCM_SHA384
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_GCM_SHA256
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_GCM_SHA384
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_GCM_SHA384
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_GCM_SHA384
+ *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_GCM_SHA384
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_CBC_SHA384
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_CBC_SHA384
+ *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256
+ *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_GCM_SHA256
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_GCM_SHA256
+ *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_GCM_SHA256
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_CBC_SHA256
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_CBC_SHA256
+ *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256
+ *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA
+ *      MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_GCM_SHA384
+ *      MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_256_CBC_SHA384
+ *      MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_CBC_SHA384
+ *      MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_GCM_SHA256
+ *      MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_CBC_SHA256
+ *      MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_128_CBC_SHA256
+ *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_GCM_SHA384
+ *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256
+ *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA
+ *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_GCM_SHA256
+ *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256
+ *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA
+ *      MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_GCM_SHA384
+ *      MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_CBC_SHA384
+ *      MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_GCM_SHA256
+ *      MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_CBC_SHA256
+ *      MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_GCM_SHA384
+ *      MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_CBC_SHA384
+ *      MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_GCM_SHA256
+ *      MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256
+ */
+#define MBEDTLS_CAMELLIA_C
+
+/**
+ * \def MBEDTLS_CCM_C
+ *
+ * Enable the Counter with CBC-MAC (CCM) mode for 128-bit block cipher.
+ *
+ * Module:  library/ccm.c
+ *
+ * Requires: MBEDTLS_AES_C or MBEDTLS_CAMELLIA_C
+ *
+ * This module enables the AES-CCM ciphersuites, if other requisites are
+ * enabled as well.
+ */
+#define MBEDTLS_CCM_C
+
+/**
+ * \def MBEDTLS_CERTS_C
+ *
+ * Enable the test certificates.
+ *
+ * Module:  library/certs.c
+ * Caller:
+ *
+ * This module is used for testing (ssl_client/server).
+ */
+#define MBEDTLS_CERTS_C
+
+/**
+ * \def MBEDTLS_CIPHER_C
+ *
+ * Enable the generic cipher layer.
+ *
+ * Module:  library/cipher.c
+ * Caller:  library/ssl_tls.c
+ *
+ * Uncomment to enable generic cipher wrappers.
+ */
+#define MBEDTLS_CIPHER_C
+
+/**
+ * \def MBEDTLS_CTR_DRBG_C
+ *
+ * Enable the CTR_DRBG AES-256-based random generator.
+ *
+ * Module:  library/ctr_drbg.c
+ * Caller:
+ *
+ * Requires: MBEDTLS_AES_C
+ *
+ * This module provides the CTR_DRBG AES-256 random number generator.
+ */
+#define MBEDTLS_CTR_DRBG_C
+
+/**
+ * \def MBEDTLS_DEBUG_C
+ *
+ * Enable the debug functions.
+ *
+ * Module:  library/debug.c
+ * Caller:  library/ssl_cli.c
+ *          library/ssl_srv.c
+ *          library/ssl_tls.c
+ *
+ * This module provides debugging functions.
+ */
+#define MBEDTLS_DEBUG_C
+
+/**
+ * \def MBEDTLS_DES_C
+ *
+ * Enable the DES block cipher.
+ *
+ * Module:  library/des.c
+ * Caller:  library/pem.c
+ *          library/ssl_tls.c
+ *
+ * This module enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_3DES_EDE_CBC_SHA
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_3DES_EDE_CBC_SHA
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA
+ *      MBEDTLS_TLS_DHE_RSA_WITH_3DES_EDE_CBC_SHA
+ *      MBEDTLS_TLS_ECDHE_PSK_WITH_3DES_EDE_CBC_SHA
+ *      MBEDTLS_TLS_DHE_PSK_WITH_3DES_EDE_CBC_SHA
+ *      MBEDTLS_TLS_RSA_WITH_3DES_EDE_CBC_SHA
+ *      MBEDTLS_TLS_RSA_PSK_WITH_3DES_EDE_CBC_SHA
+ *      MBEDTLS_TLS_PSK_WITH_3DES_EDE_CBC_SHA
+ *
+ * PEM_PARSE uses DES/3DES for decrypting encrypted keys.
+ */
+#define MBEDTLS_DES_C
+
+/**
+ * \def MBEDTLS_DHM_C
+ *
+ * Enable the Diffie-Hellman-Merkle module.
+ *
+ * Module:  library/dhm.c
+ * Caller:  library/ssl_cli.c
+ *          library/ssl_srv.c
+ *
+ * This module is used by the following key exchanges:
+ *      DHE-RSA, DHE-PSK
+ */
+#define MBEDTLS_DHM_C
+
+/**
+ * \def MBEDTLS_ECDH_C
+ *
+ * Enable the elliptic curve Diffie-Hellman library.
+ *
+ * Module:  library/ecdh.c
+ * Caller:  library/ssl_cli.c
+ *          library/ssl_srv.c
+ *
+ * This module is used by the following key exchanges:
+ *      ECDHE-ECDSA, ECDHE-RSA, DHE-PSK
+ *
+ * Requires: MBEDTLS_ECP_C
+ */
+#define MBEDTLS_ECDH_C
+
+/**
+ * \def MBEDTLS_ECDSA_C
+ *
+ * Enable the elliptic curve DSA library.
+ *
+ * Module:  library/ecdsa.c
+ * Caller:
+ *
+ * This module is used by the following key exchanges:
+ *      ECDHE-ECDSA
+ *
+ * Requires: MBEDTLS_ECP_C, MBEDTLS_ASN1_WRITE_C, MBEDTLS_ASN1_PARSE_C
+ */
+#define MBEDTLS_ECDSA_C
+
+/**
+ * \def MBEDTLS_ECJPAKE_C
+ *
+ * Enable the elliptic curve J-PAKE library.
+ *
+ * \warning This is currently experimental. EC J-PAKE support is based on the
+ * Thread v1.0.0 specification; incompatible changes to the specification
+ * might still happen. For this reason, this is disabled by default.
+ *
+ * Module:  library/ecjpake.c
+ * Caller:
+ *
+ * This module is used by the following key exchanges:
+ *      ECJPAKE
+ *
+ * Requires: MBEDTLS_ECP_C, MBEDTLS_MD_C
+ */
+//#define MBEDTLS_ECJPAKE_C
+
+/**
+ * \def MBEDTLS_ECP_C
+ *
+ * Enable the elliptic curve over GF(p) library.
+ *
+ * Module:  library/ecp.c
+ * Caller:  library/ecdh.c
+ *          library/ecdsa.c
+ *          library/ecjpake.c
+ *
+ * Requires: MBEDTLS_BIGNUM_C and at least one MBEDTLS_ECP_DP_XXX_ENABLED
+ */
+#define MBEDTLS_ECP_C
+
+/**
+ * \def MBEDTLS_ENTROPY_C
+ *
+ * Enable the platform-specific entropy code.
+ *
+ * Module:  library/entropy.c
+ * Caller:
+ *
+ * Requires: MBEDTLS_SHA512_C or MBEDTLS_SHA256_C
+ *
+ * This module provides a generic entropy pool
+ */
+#define MBEDTLS_ENTROPY_C
+
+/**
+ * \def MBEDTLS_ERROR_C
+ *
+ * Enable error code to error string conversion.
+ *
+ * Module:  library/error.c
+ * Caller:
+ *
+ * This module enables mbedtls_strerror().
+ */
+#define MBEDTLS_ERROR_C
+
+/**
+ * \def MBEDTLS_GCM_C
+ *
+ * Enable the Galois/Counter Mode (GCM) for AES.
+ *
+ * Module:  library/gcm.c
+ *
+ * Requires: MBEDTLS_AES_C or MBEDTLS_CAMELLIA_C
+ *
+ * This module enables the AES-GCM and CAMELLIA-GCM ciphersuites, if other
+ * requisites are enabled as well.
+ */
+#define MBEDTLS_GCM_C
+
+/**
+ * \def MBEDTLS_HAVEGE_C
+ *
+ * Enable the HAVEGE random generator.
+ *
+ * Warning: the HAVEGE random generator is not suitable for virtualized
+ *          environments
+ *
+ * Warning: the HAVEGE random generator is dependent on timing and specific
+ *          processor traits. It is therefore not advised to use HAVEGE as
+ *          your applications primary random generator or primary entropy pool
+ *          input. As a secondary input to your entropy pool, it IS able add
+ *          the (limited) extra entropy it provides.
+ *
+ * Module:  library/havege.c
+ * Caller:
+ *
+ * Requires: MBEDTLS_TIMING_C
+ *
+ * Uncomment to enable the HAVEGE random generator.
+ */
+//#define MBEDTLS_HAVEGE_C
+
+/**
+ * \def MBEDTLS_HMAC_DRBG_C
+ *
+ * Enable the HMAC_DRBG random generator.
+ *
+ * Module:  library/hmac_drbg.c
+ * Caller:
+ *
+ * Requires: MBEDTLS_MD_C
+ *
+ * Uncomment to enable the HMAC_DRBG random number geerator.
+ */
+#define MBEDTLS_HMAC_DRBG_C
+
+/**
+ * \def MBEDTLS_MD_C
+ *
+ * Enable the generic message digest layer.
+ *
+ * Module:  library/mbedtls_md.c
+ * Caller:
+ *
+ * Uncomment to enable generic message digest wrappers.
+ */
+#define MBEDTLS_MD_C
+
+/**
+ * \def MBEDTLS_MD2_C
+ *
+ * Enable the MD2 hash algorithm.
+ *
+ * Module:  library/mbedtls_md2.c
+ * Caller:
+ *
+ * Uncomment to enable support for (rare) MD2-signed X.509 certs.
+ */
+//#define MBEDTLS_MD2_C
+
+/**
+ * \def MBEDTLS_MD4_C
+ *
+ * Enable the MD4 hash algorithm.
+ *
+ * Module:  library/mbedtls_md4.c
+ * Caller:
+ *
+ * Uncomment to enable support for (rare) MD4-signed X.509 certs.
+ */
+//#define MBEDTLS_MD4_C
+
+/**
+ * \def MBEDTLS_MD5_C
+ *
+ * Enable the MD5 hash algorithm.
+ *
+ * Module:  library/mbedtls_md5.c
+ * Caller:  library/mbedtls_md.c
+ *          library/pem.c
+ *          library/ssl_tls.c
+ *
+ * This module is required for SSL/TLS and X.509.
+ * PEM_PARSE uses MD5 for decrypting encrypted keys.
+ */
+#define MBEDTLS_MD5_C
+
+/**
+ * \def MBEDTLS_MEMORY_BUFFER_ALLOC_C
+ *
+ * Enable the buffer allocator implementation that makes use of a (stack)
+ * based buffer to 'allocate' dynamic memory. (replaces calloc() and free()
+ * calls)
+ *
+ * Module:  library/memory_buffer_alloc.c
+ *
+ * Requires: MBEDTLS_PLATFORM_C
+ *           MBEDTLS_PLATFORM_MEMORY (to use it within mbed TLS)
+ *
+ * Enable this module to enable the buffer memory allocator.
+ */
+//#define MBEDTLS_MEMORY_BUFFER_ALLOC_C
+
+/**
+ * \def MBEDTLS_NET_C
+ *
+ * Enable the TCP and UDP over IPv6/IPv4 networking routines.
+ *
+ * \note This module only works on POSIX/Unix (including Linux, BSD and OS X)
+ * and Windows. For other platforms, you'll want to disable it, and write your
+ * own networking callbacks to be passed to \c mbedtls_ssl_set_bio().
+ *
+ * \note See also our Knowledge Base article about porting to a new
+ * environment:
+ * https://tls.mbed.org/kb/how-to/how-do-i-port-mbed-tls-to-a-new-environment-OS
+ *
+ * Module:  library/net.c
+ *
+ * This module provides networking routines.
+ */
+#define MBEDTLS_NET_C
+
+/**
+ * \def MBEDTLS_OID_C
+ *
+ * Enable the OID database.
+ *
+ * Module:  library/oid.c
+ * Caller:  library/asn1write.c
+ *          library/pkcs5.c
+ *          library/pkparse.c
+ *          library/pkwrite.c
+ *          library/rsa.c
+ *          library/x509.c
+ *          library/x509_create.c
+ *          library/mbedtls_x509_crl.c
+ *          library/mbedtls_x509_crt.c
+ *          library/mbedtls_x509_csr.c
+ *          library/x509write_crt.c
+ *          library/mbedtls_x509write_csr.c
+ *
+ * This modules translates between OIDs and internal values.
+ */
+#define MBEDTLS_OID_C
+
+/**
+ * \def MBEDTLS_PADLOCK_C
+ *
+ * Enable VIA Padlock support on x86.
+ *
+ * Module:  library/padlock.c
+ * Caller:  library/aes.c
+ *
+ * Requires: MBEDTLS_HAVE_ASM
+ *
+ * This modules adds support for the VIA PadLock on x86.
+ */
+#define MBEDTLS_PADLOCK_C
+
+/**
+ * \def MBEDTLS_PEM_PARSE_C
+ *
+ * Enable PEM decoding / parsing.
+ *
+ * Module:  library/pem.c
+ * Caller:  library/dhm.c
+ *          library/pkparse.c
+ *          library/mbedtls_x509_crl.c
+ *          library/mbedtls_x509_crt.c
+ *          library/mbedtls_x509_csr.c
+ *
+ * Requires: MBEDTLS_BASE64_C
+ *
+ * This modules adds support for decoding / parsing PEM files.
+ */
+#define MBEDTLS_PEM_PARSE_C
+
+/**
+ * \def MBEDTLS_PEM_WRITE_C
+ *
+ * Enable PEM encoding / writing.
+ *
+ * Module:  library/pem.c
+ * Caller:  library/pkwrite.c
+ *          library/x509write_crt.c
+ *          library/mbedtls_x509write_csr.c
+ *
+ * Requires: MBEDTLS_BASE64_C
+ *
+ * This modules adds support for encoding / writing PEM files.
+ */
+#define MBEDTLS_PEM_WRITE_C
+
+/**
+ * \def MBEDTLS_PK_C
+ *
+ * Enable the generic public (asymetric) key layer.
+ *
+ * Module:  library/pk.c
+ * Caller:  library/ssl_tls.c
+ *          library/ssl_cli.c
+ *          library/ssl_srv.c
+ *
+ * Requires: MBEDTLS_RSA_C or MBEDTLS_ECP_C
+ *
+ * Uncomment to enable generic public key wrappers.
+ */
+#define MBEDTLS_PK_C
+
+/**
+ * \def MBEDTLS_PK_PARSE_C
+ *
+ * Enable the generic public (asymetric) key parser.
+ *
+ * Module:  library/pkparse.c
+ * Caller:  library/mbedtls_x509_crt.c
+ *          library/mbedtls_x509_csr.c
+ *
+ * Requires: MBEDTLS_PK_C
+ *
+ * Uncomment to enable generic public key parse functions.
+ */
+#define MBEDTLS_PK_PARSE_C
+
+/**
+ * \def MBEDTLS_PK_WRITE_C
+ *
+ * Enable the generic public (asymetric) key writer.
+ *
+ * Module:  library/pkwrite.c
+ * Caller:  library/x509write.c
+ *
+ * Requires: MBEDTLS_PK_C
+ *
+ * Uncomment to enable generic public key write functions.
+ */
+#define MBEDTLS_PK_WRITE_C
+
+/**
+ * \def MBEDTLS_PKCS5_C
+ *
+ * Enable PKCS#5 functions.
+ *
+ * Module:  library/pkcs5.c
+ *
+ * Requires: MBEDTLS_MD_C
+ *
+ * This module adds support for the PKCS#5 functions.
+ */
+#define MBEDTLS_PKCS5_C
+
+/**
+ * \def MBEDTLS_PKCS11_C
+ *
+ * Enable wrapper for PKCS#11 smartcard support.
+ *
+ * Module:  library/pkcs11.c
+ * Caller:  library/pk.c
+ *
+ * Requires: MBEDTLS_PK_C
+ *
+ * This module enables SSL/TLS PKCS #11 smartcard support.
+ * Requires the presence of the PKCS#11 helper library (libpkcs11-helper)
+ */
+//#define MBEDTLS_PKCS11_C
+
+/**
+ * \def MBEDTLS_PKCS12_C
+ *
+ * Enable PKCS#12 PBE functions.
+ * Adds algorithms for parsing PKCS#8 encrypted private keys
+ *
+ * Module:  library/pkcs12.c
+ * Caller:  library/pkparse.c
+ *
+ * Requires: MBEDTLS_ASN1_PARSE_C, MBEDTLS_CIPHER_C, MBEDTLS_MD_C
+ * Can use:  MBEDTLS_ARC4_C
+ *
+ * This module enables PKCS#12 functions.
+ */
+#define MBEDTLS_PKCS12_C
+
+/**
+ * \def MBEDTLS_PLATFORM_C
+ *
+ * Enable the platform abstraction layer that allows you to re-assign
+ * functions like calloc(), free(), snprintf(), printf(), fprintf(), exit().
+ *
+ * Enabling MBEDTLS_PLATFORM_C enables to use of MBEDTLS_PLATFORM_XXX_ALT
+ * or MBEDTLS_PLATFORM_XXX_MACRO directives, allowing the functions mentioned
+ * above to be specified at runtime or compile time respectively.
+ *
+ * \note This abstraction layer must be enabled on Windows (including MSYS2)
+ * as other module rely on it for a fixed snprintf implementation.
+ *
+ * Module:  library/platform.c
+ * Caller:  Most other .c files
+ *
+ * This module enables abstraction of common (libc) functions.
+ */
+#define MBEDTLS_PLATFORM_C
+
+/**
+ * \def MBEDTLS_RIPEMD160_C
+ *
+ * Enable the RIPEMD-160 hash algorithm.
+ *
+ * Module:  library/mbedtls_ripemd160.c
+ * Caller:  library/mbedtls_md.c
+ *
+ */
+#define MBEDTLS_RIPEMD160_C
+
+/**
+ * \def MBEDTLS_RSA_C
+ *
+ * Enable the RSA public-key cryptosystem.
+ *
+ * Module:  library/rsa.c
+ * Caller:  library/ssl_cli.c
+ *          library/ssl_srv.c
+ *          library/ssl_tls.c
+ *          library/x509.c
+ *
+ * This module is used by the following key exchanges:
+ *      RSA, DHE-RSA, ECDHE-RSA, RSA-PSK
+ *
+ * Requires: MBEDTLS_BIGNUM_C, MBEDTLS_OID_C
+ */
+#define MBEDTLS_RSA_C
+
+/**
+ * \def MBEDTLS_SHA1_C
+ *
+ * Enable the SHA1 cryptographic hash algorithm.
+ *
+ * Module:  library/mbedtls_sha1.c
+ * Caller:  library/mbedtls_md.c
+ *          library/ssl_cli.c
+ *          library/ssl_srv.c
+ *          library/ssl_tls.c
+ *          library/x509write_crt.c
+ *
+ * This module is required for SSL/TLS and SHA1-signed certificates.
+ */
+#define MBEDTLS_SHA1_C
+
+/**
+ * \def MBEDTLS_SHA256_C
+ *
+ * Enable the SHA-224 and SHA-256 cryptographic hash algorithms.
+ *
+ * Module:  library/mbedtls_sha256.c
+ * Caller:  library/entropy.c
+ *          library/mbedtls_md.c
+ *          library/ssl_cli.c
+ *          library/ssl_srv.c
+ *          library/ssl_tls.c
+ *
+ * This module adds support for SHA-224 and SHA-256.
+ * This module is required for the SSL/TLS 1.2 PRF function.
+ */
+#define MBEDTLS_SHA256_C
+
+/**
+ * \def MBEDTLS_SHA512_C
+ *
+ * Enable the SHA-384 and SHA-512 cryptographic hash algorithms.
+ *
+ * Module:  library/mbedtls_sha512.c
+ * Caller:  library/entropy.c
+ *          library/mbedtls_md.c
+ *          library/ssl_cli.c
+ *          library/ssl_srv.c
+ *
+ * This module adds support for SHA-384 and SHA-512.
+ */
+#define MBEDTLS_SHA512_C
+
+/**
+ * \def MBEDTLS_SSL_CACHE_C
+ *
+ * Enable simple SSL cache implementation.
+ *
+ * Module:  library/ssl_cache.c
+ * Caller:
+ *
+ * Requires: MBEDTLS_SSL_CACHE_C
+ */
+#define MBEDTLS_SSL_CACHE_C
+
+/**
+ * \def MBEDTLS_SSL_COOKIE_C
+ *
+ * Enable basic implementation of DTLS cookies for hello verification.
+ *
+ * Module:  library/ssl_cookie.c
+ * Caller:
+ */
+#define MBEDTLS_SSL_COOKIE_C
+
+/**
+ * \def MBEDTLS_SSL_TICKET_C
+ *
+ * Enable an implementation of TLS server-side callbacks for session tickets.
+ *
+ * Module:  library/ssl_ticket.c
+ * Caller:
+ *
+ * Requires: MBEDTLS_CIPHER_C
+ */
+#define MBEDTLS_SSL_TICKET_C
+
+/**
+ * \def MBEDTLS_SSL_CLI_C
+ *
+ * Enable the SSL/TLS client code.
+ *
+ * Module:  library/ssl_cli.c
+ * Caller:
+ *
+ * Requires: MBEDTLS_SSL_TLS_C
+ *
+ * This module is required for SSL/TLS client support.
+ */
+#define MBEDTLS_SSL_CLI_C
+
+/**
+ * \def MBEDTLS_SSL_SRV_C
+ *
+ * Enable the SSL/TLS server code.
+ *
+ * Module:  library/ssl_srv.c
+ * Caller:
+ *
+ * Requires: MBEDTLS_SSL_TLS_C
+ *
+ * This module is required for SSL/TLS server support.
+ */
+#define MBEDTLS_SSL_SRV_C
+
+/**
+ * \def MBEDTLS_SSL_TLS_C
+ *
+ * Enable the generic SSL/TLS code.
+ *
+ * Module:  library/ssl_tls.c
+ * Caller:  library/ssl_cli.c
+ *          library/ssl_srv.c
+ *
+ * Requires: MBEDTLS_CIPHER_C, MBEDTLS_MD_C
+ *           and at least one of the MBEDTLS_SSL_PROTO_XXX defines
+ *
+ * This module is required for SSL/TLS.
+ */
+#define MBEDTLS_SSL_TLS_C
+
+/**
+ * \def MBEDTLS_THREADING_C
+ *
+ * Enable the threading abstraction layer.
+ * By default mbed TLS assumes it is used in a non-threaded environment or that
+ * contexts are not shared between threads. If you do intend to use contexts
+ * between threads, you will need to enable this layer to prevent race
+ * conditions. See also our Knowledge Base article about threading:
+ * https://tls.mbed.org/kb/development/thread-safety-and-multi-threading
+ *
+ * Module:  library/threading.c
+ *
+ * This allows different threading implementations (self-implemented or
+ * provided).
+ *
+ * You will have to enable either MBEDTLS_THREADING_ALT or
+ * MBEDTLS_THREADING_PTHREAD.
+ *
+ * Enable this layer to allow use of mutexes within mbed TLS
+ */
+//#define MBEDTLS_THREADING_C
+
+/**
+ * \def MBEDTLS_TIMING_C
+ *
+ * Enable the semi-portable timing interface.
+ *
+ * \note The provided implementation only works on POSIX/Unix (including Linux,
+ * BSD and OS X) and Windows. On other platforms, you can either disable that
+ * module and provide your own implementations of the callbacks needed by
+ * \c mbedtls_ssl_set_timer_cb() for DTLS, or leave it enabled and provide
+ * your own implementation of the whole module by setting
+ * \c MBEDTLS_TIMING_ALT in the current file.
+ *
+ * \note See also our Knowledge Base article about porting to a new
+ * environment:
+ * https://tls.mbed.org/kb/how-to/how-do-i-port-mbed-tls-to-a-new-environment-OS
+ *
+ * Module:  library/timing.c
+ * Caller:  library/havege.c
+ *
+ * This module is used by the HAVEGE random number generator.
+ */
+#define MBEDTLS_TIMING_C
+
+/**
+ * \def MBEDTLS_VERSION_C
+ *
+ * Enable run-time version information.
+ *
+ * Module:  library/version.c
+ *
+ * This module provides run-time version information.
+ */
+#define MBEDTLS_VERSION_C
+
+/**
+ * \def MBEDTLS_X509_USE_C
+ *
+ * Enable X.509 core for using certificates.
+ *
+ * Module:  library/x509.c
+ * Caller:  library/mbedtls_x509_crl.c
+ *          library/mbedtls_x509_crt.c
+ *          library/mbedtls_x509_csr.c
+ *
+ * Requires: MBEDTLS_ASN1_PARSE_C, MBEDTLS_BIGNUM_C, MBEDTLS_OID_C,
+ *           MBEDTLS_PK_PARSE_C
+ *
+ * This module is required for the X.509 parsing modules.
+ */
+#define MBEDTLS_X509_USE_C
+
+/**
+ * \def MBEDTLS_X509_CRT_PARSE_C
+ *
+ * Enable X.509 certificate parsing.
+ *
+ * Module:  library/mbedtls_x509_crt.c
+ * Caller:  library/ssl_cli.c
+ *          library/ssl_srv.c
+ *          library/ssl_tls.c
+ *
+ * Requires: MBEDTLS_X509_USE_C
+ *
+ * This module is required for X.509 certificate parsing.
+ */
+#define MBEDTLS_X509_CRT_PARSE_C
+
+/**
+ * \def MBEDTLS_X509_CRL_PARSE_C
+ *
+ * Enable X.509 CRL parsing.
+ *
+ * Module:  library/mbedtls_x509_crl.c
+ * Caller:  library/mbedtls_x509_crt.c
+ *
+ * Requires: MBEDTLS_X509_USE_C
+ *
+ * This module is required for X.509 CRL parsing.
+ */
+#define MBEDTLS_X509_CRL_PARSE_C
+
+/**
+ * \def MBEDTLS_X509_CSR_PARSE_C
+ *
+ * Enable X.509 Certificate Signing Request (CSR) parsing.
+ *
+ * Module:  library/mbedtls_x509_csr.c
+ * Caller:  library/x509_crt_write.c
+ *
+ * Requires: MBEDTLS_X509_USE_C
+ *
+ * This module is used for reading X.509 certificate request.
+ */
+#define MBEDTLS_X509_CSR_PARSE_C
+
+/**
+ * \def MBEDTLS_X509_CREATE_C
+ *
+ * Enable X.509 core for creating certificates.
+ *
+ * Module:  library/x509_create.c
+ *
+ * Requires: MBEDTLS_BIGNUM_C, MBEDTLS_OID_C, MBEDTLS_PK_WRITE_C
+ *
+ * This module is the basis for creating X.509 certificates and CSRs.
+ */
+#define MBEDTLS_X509_CREATE_C
+
+/**
+ * \def MBEDTLS_X509_CRT_WRITE_C
+ *
+ * Enable creating X.509 certificates.
+ *
+ * Module:  library/x509_crt_write.c
+ *
+ * Requires: MBEDTLS_X509_CREATE_C
+ *
+ * This module is required for X.509 certificate creation.
+ */
+#define MBEDTLS_X509_CRT_WRITE_C
+
+/**
+ * \def MBEDTLS_X509_CSR_WRITE_C
+ *
+ * Enable creating X.509 Certificate Signing Requests (CSR).
+ *
+ * Module:  library/x509_csr_write.c
+ *
+ * Requires: MBEDTLS_X509_CREATE_C
+ *
+ * This module is required for X.509 certificate request writing.
+ */
+#define MBEDTLS_X509_CSR_WRITE_C
+
+/**
+ * \def MBEDTLS_XTEA_C
+ *
+ * Enable the XTEA block cipher.
+ *
+ * Module:  library/xtea.c
+ * Caller:
+ */
+#define MBEDTLS_XTEA_C
+
+/* \} name SECTION: mbed TLS modules */
+
+/**
+ * \name SECTION: Module configuration options
+ *
+ * This section allows for the setting of module specific sizes and
+ * configuration options. The default values are already present in the
+ * relevant header files and should suffice for the regular use cases.
+ *
+ * Our advice is to enable options and change their values here
+ * only if you have a good reason and know the consequences.
+ *
+ * Please check the respective header file for documentation on these
+ * parameters (to prevent duplicate documentation).
+ * \{
+ */
+
+/* MPI / BIGNUM options */
+//#define MBEDTLS_MPI_WINDOW_SIZE            6 /**< Maximum windows size used. */
+//#define MBEDTLS_MPI_MAX_SIZE            1024 /**< Maximum number of bytes for usable MPIs. */
+
+/* CTR_DRBG options */
+//#define MBEDTLS_CTR_DRBG_ENTROPY_LEN               48 /**< Amount of entropy used per seed by default (48 with SHA-512, 32 with SHA-256) */
+//#define MBEDTLS_CTR_DRBG_RESEED_INTERVAL        10000 /**< Interval before reseed is performed by default */
+//#define MBEDTLS_CTR_DRBG_MAX_INPUT                256 /**< Maximum number of additional input bytes */
+//#define MBEDTLS_CTR_DRBG_MAX_REQUEST             1024 /**< Maximum number of requested bytes per call */
+//#define MBEDTLS_CTR_DRBG_MAX_SEED_INPUT           384 /**< Maximum size of (re)seed buffer */
+
+/* HMAC_DRBG options */
+//#define MBEDTLS_HMAC_DRBG_RESEED_INTERVAL   10000 /**< Interval before reseed is performed by default */
+//#define MBEDTLS_HMAC_DRBG_MAX_INPUT           256 /**< Maximum number of additional input bytes */
+//#define MBEDTLS_HMAC_DRBG_MAX_REQUEST        1024 /**< Maximum number of requested bytes per call */
+//#define MBEDTLS_HMAC_DRBG_MAX_SEED_INPUT      384 /**< Maximum size of (re)seed buffer */
+
+/* ECP options */
+//#define MBEDTLS_ECP_MAX_BITS             521 /**< Maximum bit size of groups */
+//#define MBEDTLS_ECP_WINDOW_SIZE            6 /**< Maximum window size used */
+//#define MBEDTLS_ECP_FIXED_POINT_OPTIM      1 /**< Enable fixed-point speed-up */
+
+/* Entropy options */
+//#define MBEDTLS_ENTROPY_MAX_SOURCES                20 /**< Maximum number of sources supported */
+//#define MBEDTLS_ENTROPY_MAX_GATHER                128 /**< Maximum amount requested from entropy sources */
+
+/* Memory buffer allocator options */
+//#define MBEDTLS_MEMORY_ALIGN_MULTIPLE      4 /**< Align on multiples of this value */
+
+/* Platform options */
+//#define MBEDTLS_PLATFORM_STD_MEM_HDR    /**< Header to include if MBEDTLS_PLATFORM_NO_STD_FUNCTIONS is defined. Don't define if no header is needed. */
+//#define MBEDTLS_PLATFORM_STD_CALLOC        calloc /**< Default allocator to use, can be undefined */
+//#define MBEDTLS_PLATFORM_STD_FREE            free /**< Default free to use, can be undefined */
+//#define MBEDTLS_PLATFORM_STD_EXIT            exit /**< Default exit to use, can be undefined */
+//#define MBEDTLS_PLATFORM_STD_TIME            time /**< Default time to use, can be undefined */
+//#define MBEDTLS_PLATFORM_STD_FPRINTF      fprintf /**< Default fprintf to use, can be undefined */
+//#define MBEDTLS_PLATFORM_STD_PRINTF        printf /**< Default printf to use, can be undefined */
+/* Note: your snprintf must correclty zero-terminate the buffer! */
+//#define MBEDTLS_PLATFORM_STD_SNPRINTF    snprintf /**< Default snprintf to use, can be undefined */
+//#define MBEDTLS_PLATFORM_STD_EXIT_SUCCESS       0 /**< Default exit value to use, can be undefined */
+//#define MBEDTLS_PLATFORM_STD_EXIT_FAILURE       1 /**< Default exit value to use, can be undefined */
+//#define MBEDTLS_PLATFORM_STD_NV_SEED_READ   mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read function to use, can be undefined */
+//#define MBEDTLS_PLATFORM_STD_NV_SEED_WRITE  mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, can be undefined */
+//#define MBEDTLS_PLATFORM_STD_NV_SEED_FILE  "seedfile" /**< Seed file to read/write with default implementation */
+
+/* To Use Function Macros MBEDTLS_PLATFORM_C must be enabled */
+/* MBEDTLS_PLATFORM_XXX_MACRO and MBEDTLS_PLATFORM_XXX_ALT cannot both be defined */
+//#define MBEDTLS_PLATFORM_CALLOC_MACRO        calloc /**< Default allocator macro to use, can be undefined */
+//#define MBEDTLS_PLATFORM_FREE_MACRO            free /**< Default free macro to use, can be undefined */
+//#define MBEDTLS_PLATFORM_EXIT_MACRO            exit /**< Default exit macro to use, can be undefined */
+//#define MBEDTLS_PLATFORM_TIME_MACRO            time /**< Default time macro to use, can be undefined */
+//#define MBEDTLS_PLATFORM_TIME_TYPE_MACRO       time_t /**< Default time macro to use, can be undefined */
+//#define MBEDTLS_PLATFORM_FPRINTF_MACRO      fprintf /**< Default fprintf macro to use, can be undefined */
+//#define MBEDTLS_PLATFORM_PRINTF_MACRO        printf /**< Default printf macro to use, can be undefined */
+/* Note: your snprintf must correclty zero-terminate the buffer! */
+//#define MBEDTLS_PLATFORM_SNPRINTF_MACRO    snprintf /**< Default snprintf macro to use, can be undefined */
+//#define MBEDTLS_PLATFORM_NV_SEED_READ_MACRO   mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read function to use, can be undefined */
+//#define MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO  mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, can be undefined */
+
+/* SSL Cache options */
+//#define MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT       86400 /**< 1 day  */
+//#define MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES      50 /**< Maximum entries in cache */
+
+/* SSL options */
+//#define MBEDTLS_SSL_MAX_CONTENT_LEN             16384 /**< Maxium fragment length in bytes, determines the size of each of the two internal I/O buffers */
+//#define MBEDTLS_SSL_DEFAULT_TICKET_LIFETIME     86400 /**< Lifetime of session tickets (if enabled) */
+//#define MBEDTLS_PSK_MAX_LEN               32 /**< Max size of TLS pre-shared keys, in bytes (default 256 bits) */
+//#define MBEDTLS_SSL_COOKIE_TIMEOUT        60 /**< Default expiration delay of DTLS cookies, in seconds if HAVE_TIME, or in number of cookies issued */
+
+/**
+ * Complete list of ciphersuites to use, in order of preference.
+ *
+ * \warning No dependency checking is done on that field! This option can only
+ * be used to restrict the set of available ciphersuites. It is your
+ * responsibility to make sure the needed modules are active.
+ *
+ * Use this to save a few hundred bytes of ROM (default ordering of all
+ * available ciphersuites) and a few to a few hundred bytes of RAM.
+ *
+ * The value below is only an example, not the default.
+ */
+//#define MBEDTLS_SSL_CIPHERSUITES MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384,MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256
+
+/* X509 options */
+//#define MBEDTLS_X509_MAX_INTERMEDIATE_CA   8   /**< Maximum number of intermediate CAs in a verification chain. */
+
+/* \} name SECTION: Customisation configuration options */
+
+/* Target and application specific configurations */
+//#define YOTTA_CFG_MBEDTLS_USER_CONFIG_FILE "target_config.h"
+
+/*
+ * Allow user to override any previous default.
+ *
+ * Use two macro names for that, as:
+ * - with yotta the prefix YOTTA_CFG_ is forced
+ * - without yotta is looks weird to have a YOTTA prefix.
+ */
+#if defined(YOTTA_CFG_MBEDTLS_USER_CONFIG_FILE)
+#include YOTTA_CFG_MBEDTLS_USER_CONFIG_FILE
+#elif defined(MBEDTLS_USER_CONFIG_FILE)
+#include MBEDTLS_USER_CONFIG_FILE
+#endif
+
+#include "check_config.h"
+
+#endif /* MBEDTLS_CONFIG_H */
diff --git a/tools/sdk/include/mbedtls/mbedtls/ctr_drbg.h b/tools/sdk/include/mbedtls/mbedtls/ctr_drbg.h
new file mode 100644
index 00000000..059d3c5c
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/ctr_drbg.h
@@ -0,0 +1,290 @@
+/**
+ * \file ctr_drbg.h
+ *
+ * \brief CTR_DRBG based on AES-256 (NIST SP 800-90)
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_CTR_DRBG_H
+#define MBEDTLS_CTR_DRBG_H
+
+#include "aes.h"
+
+#if defined(MBEDTLS_THREADING_C)
+#include "mbedtls/threading.h"
+#endif
+
+#define MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED        -0x0034  /**< The entropy source failed. */
+#define MBEDTLS_ERR_CTR_DRBG_REQUEST_TOO_BIG              -0x0036  /**< Too many random requested in single call. */
+#define MBEDTLS_ERR_CTR_DRBG_INPUT_TOO_BIG                -0x0038  /**< Input too large (Entropy + additional). */
+#define MBEDTLS_ERR_CTR_DRBG_FILE_IO_ERROR                -0x003A  /**< Read/write error in file. */
+
+#define MBEDTLS_CTR_DRBG_BLOCKSIZE          16      /**< Block size used by the cipher                  */
+#define MBEDTLS_CTR_DRBG_KEYSIZE            32      /**< Key size used by the cipher                    */
+#define MBEDTLS_CTR_DRBG_KEYBITS            ( MBEDTLS_CTR_DRBG_KEYSIZE * 8 )
+#define MBEDTLS_CTR_DRBG_SEEDLEN            ( MBEDTLS_CTR_DRBG_KEYSIZE + MBEDTLS_CTR_DRBG_BLOCKSIZE )
+                                            /**< The seed length (counter + AES key)            */
+
+/**
+ * \name SECTION: Module settings
+ *
+ * The configuration options you can set for this module are in this section.
+ * Either change them in config.h or define them on the compiler command line.
+ * \{
+ */
+
+#if !defined(MBEDTLS_CTR_DRBG_ENTROPY_LEN)
+#if defined(MBEDTLS_SHA512_C) && !defined(MBEDTLS_ENTROPY_FORCE_SHA256)
+#define MBEDTLS_CTR_DRBG_ENTROPY_LEN        48      /**< Amount of entropy used per seed by default (48 with SHA-512, 32 with SHA-256) */
+#else
+#define MBEDTLS_CTR_DRBG_ENTROPY_LEN        32      /**< Amount of entropy used per seed by default (48 with SHA-512, 32 with SHA-256) */
+#endif
+#endif
+
+#if !defined(MBEDTLS_CTR_DRBG_RESEED_INTERVAL)
+#define MBEDTLS_CTR_DRBG_RESEED_INTERVAL    10000   /**< Interval before reseed is performed by default */
+#endif
+
+#if !defined(MBEDTLS_CTR_DRBG_MAX_INPUT)
+#define MBEDTLS_CTR_DRBG_MAX_INPUT          256     /**< Maximum number of additional input bytes */
+#endif
+
+#if !defined(MBEDTLS_CTR_DRBG_MAX_REQUEST)
+#define MBEDTLS_CTR_DRBG_MAX_REQUEST        1024    /**< Maximum number of requested bytes per call */
+#endif
+
+#if !defined(MBEDTLS_CTR_DRBG_MAX_SEED_INPUT)
+#define MBEDTLS_CTR_DRBG_MAX_SEED_INPUT     384     /**< Maximum size of (re)seed buffer */
+#endif
+
+/* \} name SECTION: Module settings */
+
+#define MBEDTLS_CTR_DRBG_PR_OFF             0       /**< No prediction resistance       */
+#define MBEDTLS_CTR_DRBG_PR_ON              1       /**< Prediction resistance enabled  */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          CTR_DRBG context structure
+ */
+typedef struct
+{
+    unsigned char counter[16];  /*!<  counter (V)       */
+    int reseed_counter;         /*!<  reseed counter    */
+    int prediction_resistance;  /*!<  enable prediction resistance (Automatic
+                                      reseed before every random generation)  */
+    size_t entropy_len;         /*!<  amount of entropy grabbed on each
+                                      (re)seed          */
+    int reseed_interval;        /*!<  reseed interval   */
+
+    mbedtls_aes_context aes_ctx;        /*!<  AES context       */
+
+    /*
+     * Callbacks (Entropy)
+     */
+    int (*f_entropy)(void *, unsigned char *, size_t);
+
+    void *p_entropy;            /*!<  context for the entropy function */
+
+#if defined(MBEDTLS_THREADING_C)
+    mbedtls_threading_mutex_t mutex;
+#endif
+}
+mbedtls_ctr_drbg_context;
+
+/**
+ * \brief               CTR_DRBG context initialization
+ *                      Makes the context ready for mbedtls_ctr_drbg_seed() or
+ *                      mbedtls_ctr_drbg_free().
+ *
+ * \param ctx           CTR_DRBG context to be initialized
+ */
+void mbedtls_ctr_drbg_init( mbedtls_ctr_drbg_context *ctx );
+
+/**
+ * \brief               CTR_DRBG initial seeding
+ *                      Seed and setup entropy source for future reseeds.
+ *
+ * Note: Personalization data can be provided in addition to the more generic
+ *       entropy source to make this instantiation as unique as possible.
+ *
+ * \param ctx           CTR_DRBG context to be seeded
+ * \param f_entropy     Entropy callback (p_entropy, buffer to fill, buffer
+ *                      length)
+ * \param p_entropy     Entropy context
+ * \param custom        Personalization data (Device specific identifiers)
+ *                      (Can be NULL)
+ * \param len           Length of personalization data
+ *
+ * \return              0 if successful, or
+ *                      MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED
+ */
+int mbedtls_ctr_drbg_seed( mbedtls_ctr_drbg_context *ctx,
+                   int (*f_entropy)(void *, unsigned char *, size_t),
+                   void *p_entropy,
+                   const unsigned char *custom,
+                   size_t len );
+
+/**
+ * \brief               Clear CTR_CRBG context data
+ *
+ * \param ctx           CTR_DRBG context to clear
+ */
+void mbedtls_ctr_drbg_free( mbedtls_ctr_drbg_context *ctx );
+
+/**
+ * \brief               Enable / disable prediction resistance (Default: Off)
+ *
+ * Note: If enabled, entropy is used for ctx->entropy_len before each call!
+ *       Only use this if you have ample supply of good entropy!
+ *
+ * \param ctx           CTR_DRBG context
+ * \param resistance    MBEDTLS_CTR_DRBG_PR_ON or MBEDTLS_CTR_DRBG_PR_OFF
+ */
+void mbedtls_ctr_drbg_set_prediction_resistance( mbedtls_ctr_drbg_context *ctx,
+                                         int resistance );
+
+/**
+ * \brief               Set the amount of entropy grabbed on each (re)seed
+ *                      (Default: MBEDTLS_CTR_DRBG_ENTROPY_LEN)
+ *
+ * \param ctx           CTR_DRBG context
+ * \param len           Amount of entropy to grab
+ */
+void mbedtls_ctr_drbg_set_entropy_len( mbedtls_ctr_drbg_context *ctx,
+                               size_t len );
+
+/**
+ * \brief               Set the reseed interval
+ *                      (Default: MBEDTLS_CTR_DRBG_RESEED_INTERVAL)
+ *
+ * \param ctx           CTR_DRBG context
+ * \param interval      Reseed interval
+ */
+void mbedtls_ctr_drbg_set_reseed_interval( mbedtls_ctr_drbg_context *ctx,
+                                   int interval );
+
+/**
+ * \brief               CTR_DRBG reseeding (extracts data from entropy source)
+ *
+ * \param ctx           CTR_DRBG context
+ * \param additional    Additional data to add to state (Can be NULL)
+ * \param len           Length of additional data
+ *
+ * \return              0 if successful, or
+ *                      MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED
+ */
+int mbedtls_ctr_drbg_reseed( mbedtls_ctr_drbg_context *ctx,
+                     const unsigned char *additional, size_t len );
+
+/**
+ * \brief               CTR_DRBG update state
+ *
+ * \param ctx           CTR_DRBG context
+ * \param additional    Additional data to update state with
+ * \param add_len       Length of additional data
+ *
+ * \note                If add_len is greater than MBEDTLS_CTR_DRBG_MAX_SEED_INPUT,
+ *                      only the first MBEDTLS_CTR_DRBG_MAX_SEED_INPUT bytes are used,
+ *                      the remaining ones are silently discarded.
+ */
+void mbedtls_ctr_drbg_update( mbedtls_ctr_drbg_context *ctx,
+                      const unsigned char *additional, size_t add_len );
+
+/**
+ * \brief               CTR_DRBG generate random with additional update input
+ *
+ * Note: Automatically reseeds if reseed_counter is reached.
+ *
+ * \param p_rng         CTR_DRBG context
+ * \param output        Buffer to fill
+ * \param output_len    Length of the buffer
+ * \param additional    Additional data to update with (Can be NULL)
+ * \param add_len       Length of additional data
+ *
+ * \return              0 if successful, or
+ *                      MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED, or
+ *                      MBEDTLS_ERR_CTR_DRBG_REQUEST_TOO_BIG
+ */
+int mbedtls_ctr_drbg_random_with_add( void *p_rng,
+                              unsigned char *output, size_t output_len,
+                              const unsigned char *additional, size_t add_len );
+
+/**
+ * \brief               CTR_DRBG generate random
+ *
+ * Note: Automatically reseeds if reseed_counter is reached.
+ *
+ * \param p_rng         CTR_DRBG context
+ * \param output        Buffer to fill
+ * \param output_len    Length of the buffer
+ *
+ * \return              0 if successful, or
+ *                      MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED, or
+ *                      MBEDTLS_ERR_CTR_DRBG_REQUEST_TOO_BIG
+ */
+int mbedtls_ctr_drbg_random( void *p_rng,
+                     unsigned char *output, size_t output_len );
+
+#if defined(MBEDTLS_FS_IO)
+/**
+ * \brief               Write a seed file
+ *
+ * \param ctx           CTR_DRBG context
+ * \param path          Name of the file
+ *
+ * \return              0 if successful,
+ *                      MBEDTLS_ERR_CTR_DRBG_FILE_IO_ERROR on file error, or
+ *                      MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED
+ */
+int mbedtls_ctr_drbg_write_seed_file( mbedtls_ctr_drbg_context *ctx, const char *path );
+
+/**
+ * \brief               Read and update a seed file. Seed is added to this
+ *                      instance
+ *
+ * \param ctx           CTR_DRBG context
+ * \param path          Name of the file
+ *
+ * \return              0 if successful,
+ *                      MBEDTLS_ERR_CTR_DRBG_FILE_IO_ERROR on file error,
+ *                      MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED or
+ *                      MBEDTLS_ERR_CTR_DRBG_INPUT_TOO_BIG
+ */
+int mbedtls_ctr_drbg_update_seed_file( mbedtls_ctr_drbg_context *ctx, const char *path );
+#endif /* MBEDTLS_FS_IO */
+
+/**
+ * \brief               Checkup routine
+ *
+ * \return              0 if successful, or 1 if the test failed
+ */
+int mbedtls_ctr_drbg_self_test( int verbose );
+
+/* Internal functions (do not call directly) */
+int mbedtls_ctr_drbg_seed_entropy_len( mbedtls_ctr_drbg_context *,
+                               int (*)(void *, unsigned char *, size_t), void *,
+                               const unsigned char *, size_t, size_t );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ctr_drbg.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/debug.h b/tools/sdk/include/mbedtls/mbedtls/debug.h
new file mode 100644
index 00000000..29579964
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/debug.h
@@ -0,0 +1,228 @@
+/**
+ * \file debug.h
+ *
+ * \brief Functions for controlling and providing debug output from the library.
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_DEBUG_H
+#define MBEDTLS_DEBUG_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#include "ssl.h"
+
+#if defined(MBEDTLS_ECP_C)
+#include "ecp.h"
+#endif
+
+#if defined(MBEDTLS_DEBUG_C)
+
+#define MBEDTLS_DEBUG_STRIP_PARENS( ... )   __VA_ARGS__
+
+#define MBEDTLS_SSL_DEBUG_MSG( level, args )                    \
+    mbedtls_debug_print_msg( ssl, level, __FILE__, __LINE__,    \
+                             MBEDTLS_DEBUG_STRIP_PARENS args )
+
+#define MBEDTLS_SSL_DEBUG_RET( level, text, ret )                \
+    mbedtls_debug_print_ret( ssl, level, __FILE__, __LINE__, text, ret )
+
+#define MBEDTLS_SSL_DEBUG_BUF( level, text, buf, len )           \
+    mbedtls_debug_print_buf( ssl, level, __FILE__, __LINE__, text, buf, len )
+
+#if defined(MBEDTLS_BIGNUM_C)
+#define MBEDTLS_SSL_DEBUG_MPI( level, text, X )                  \
+    mbedtls_debug_print_mpi( ssl, level, __FILE__, __LINE__, text, X )
+#endif
+
+#if defined(MBEDTLS_ECP_C)
+#define MBEDTLS_SSL_DEBUG_ECP( level, text, X )                  \
+    mbedtls_debug_print_ecp( ssl, level, __FILE__, __LINE__, text, X )
+#endif
+
+#if defined(MBEDTLS_X509_CRT_PARSE_C)
+#define MBEDTLS_SSL_DEBUG_CRT( level, text, crt )                \
+    mbedtls_debug_print_crt( ssl, level, __FILE__, __LINE__, text, crt )
+#endif
+
+#else /* MBEDTLS_DEBUG_C */
+
+#define MBEDTLS_SSL_DEBUG_MSG( level, args )            do { } while( 0 )
+#define MBEDTLS_SSL_DEBUG_RET( level, text, ret )       do { } while( 0 )
+#define MBEDTLS_SSL_DEBUG_BUF( level, text, buf, len )  do { } while( 0 )
+#define MBEDTLS_SSL_DEBUG_MPI( level, text, X )         do { } while( 0 )
+#define MBEDTLS_SSL_DEBUG_ECP( level, text, X )         do { } while( 0 )
+#define MBEDTLS_SSL_DEBUG_CRT( level, text, crt )       do { } while( 0 )
+
+#endif /* MBEDTLS_DEBUG_C */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief   Set the threshold error level to handle globally all debug output.
+ *          Debug messages that have a level over the threshold value are
+ *          discarded.
+ *          (Default value: 0 = No debug )
+ *
+ * \param threshold     theshold level of messages to filter on. Messages at a
+ *                      higher level will be discarded.
+ *                          - Debug levels
+ *                              - 0 No debug
+ *                              - 1 Error
+ *                              - 2 State change
+ *                              - 3 Informational
+ *                              - 4 Verbose
+ */
+void mbedtls_debug_set_threshold( int threshold );
+
+/**
+ * \brief    Print a message to the debug output. This function is always used
+ *          through the MBEDTLS_SSL_DEBUG_MSG() macro, which supplies the ssl
+ *          context, file and line number parameters.
+ *
+ * \param ssl       SSL context
+ * \param level     error level of the debug message
+ * \param file      file the message has occurred in
+ * \param line      line number the message has occurred at
+ * \param format    format specifier, in printf format
+ * \param ...       variables used by the format specifier
+ *
+ * \attention       This function is intended for INTERNAL usage within the
+ *                  library only.
+ */
+void mbedtls_debug_print_msg( const mbedtls_ssl_context *ssl, int level,
+                              const char *file, int line,
+                              const char *format, ... );
+
+/**
+ * \brief   Print the return value of a function to the debug output. This
+ *          function is always used through the MBEDTLS_SSL_DEBUG_RET() macro,
+ *          which supplies the ssl context, file and line number parameters.
+ *
+ * \param ssl       SSL context
+ * \param level     error level of the debug message
+ * \param file      file the error has occurred in
+ * \param line      line number the error has occurred in
+ * \param text      the name of the function that returned the error
+ * \param ret       the return code value
+ *
+ * \attention       This function is intended for INTERNAL usage within the
+ *                  library only.
+ */
+void mbedtls_debug_print_ret( const mbedtls_ssl_context *ssl, int level,
+                      const char *file, int line,
+                      const char *text, int ret );
+
+/**
+ * \brief   Output a buffer of size len bytes to the debug output. This function
+ *          is always used through the MBEDTLS_SSL_DEBUG_BUF() macro,
+ *          which supplies the ssl context, file and line number parameters.
+ *
+ * \param ssl       SSL context
+ * \param level     error level of the debug message
+ * \param file      file the error has occurred in
+ * \param line      line number the error has occurred in
+ * \param text      a name or label for the buffer being dumped. Normally the
+ *                  variable or buffer name
+ * \param buf       the buffer to be outputted
+ * \param len       length of the buffer
+ *
+ * \attention       This function is intended for INTERNAL usage within the
+ *                  library only.
+ */
+void mbedtls_debug_print_buf( const mbedtls_ssl_context *ssl, int level,
+                      const char *file, int line, const char *text,
+                      const unsigned char *buf, size_t len );
+
+#if defined(MBEDTLS_BIGNUM_C)
+/**
+ * \brief   Print a MPI variable to the debug output. This function is always
+ *          used through the MBEDTLS_SSL_DEBUG_MPI() macro, which supplies the
+ *          ssl context, file and line number parameters.
+ *
+ * \param ssl       SSL context
+ * \param level     error level of the debug message
+ * \param file      file the error has occurred in
+ * \param line      line number the error has occurred in
+ * \param text      a name or label for the MPI being output. Normally the
+ *                  variable name
+ * \param X         the MPI variable
+ *
+ * \attention       This function is intended for INTERNAL usage within the
+ *                  library only.
+ */
+void mbedtls_debug_print_mpi( const mbedtls_ssl_context *ssl, int level,
+                      const char *file, int line,
+                      const char *text, const mbedtls_mpi *X );
+#endif
+
+#if defined(MBEDTLS_ECP_C)
+/**
+ * \brief   Print an ECP point to the debug output. This function is always
+ *          used through the MBEDTLS_SSL_DEBUG_ECP() macro, which supplies the
+ *          ssl context, file and line number parameters.
+ *
+ * \param ssl       SSL context
+ * \param level     error level of the debug message
+ * \param file      file the error has occurred in
+ * \param line      line number the error has occurred in
+ * \param text      a name or label for the ECP point being output. Normally the
+ *                  variable name
+ * \param X         the ECP point
+ *
+ * \attention       This function is intended for INTERNAL usage within the
+ *                  library only.
+ */
+void mbedtls_debug_print_ecp( const mbedtls_ssl_context *ssl, int level,
+                      const char *file, int line,
+                      const char *text, const mbedtls_ecp_point *X );
+#endif
+
+#if defined(MBEDTLS_X509_CRT_PARSE_C)
+/**
+ * \brief   Print a X.509 certificate structure to the debug output. This
+ *          function is always used through the MBEDTLS_SSL_DEBUG_CRT() macro,
+ *          which supplies the ssl context, file and line number parameters.
+ *
+ * \param ssl       SSL context
+ * \param level     error level of the debug message
+ * \param file      file the error has occurred in
+ * \param line      line number the error has occurred in
+ * \param text      a name or label for the certificate being output
+ * \param crt       X.509 certificate structure
+ *
+ * \attention       This function is intended for INTERNAL usage within the
+ *                  library only.
+ */
+void mbedtls_debug_print_crt( const mbedtls_ssl_context *ssl, int level,
+                      const char *file, int line,
+                      const char *text, const mbedtls_x509_crt *crt );
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* debug.h */
+
diff --git a/tools/sdk/include/mbedtls/mbedtls/des.h b/tools/sdk/include/mbedtls/mbedtls/des.h
new file mode 100644
index 00000000..5ca2ecf2
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/des.h
@@ -0,0 +1,306 @@
+/**
+ * \file des.h
+ *
+ * \brief DES block cipher
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_DES_H
+#define MBEDTLS_DES_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#include 
+#include 
+
+#define MBEDTLS_DES_ENCRYPT     1
+#define MBEDTLS_DES_DECRYPT     0
+
+#define MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH              -0x0032  /**< The data input has an invalid length. */
+
+#define MBEDTLS_DES_KEY_SIZE    8
+
+#if !defined(MBEDTLS_DES_ALT)
+// Regular implementation
+//
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          DES context structure
+ */
+typedef struct
+{
+    uint32_t sk[32];            /*!<  DES subkeys       */
+}
+mbedtls_des_context;
+
+/**
+ * \brief          Triple-DES context structure
+ */
+typedef struct
+{
+    uint32_t sk[96];            /*!<  3DES subkeys      */
+}
+mbedtls_des3_context;
+
+/**
+ * \brief          Initialize DES context
+ *
+ * \param ctx      DES context to be initialized
+ */
+void mbedtls_des_init( mbedtls_des_context *ctx );
+
+/**
+ * \brief          Clear DES context
+ *
+ * \param ctx      DES context to be cleared
+ */
+void mbedtls_des_free( mbedtls_des_context *ctx );
+
+/**
+ * \brief          Initialize Triple-DES context
+ *
+ * \param ctx      DES3 context to be initialized
+ */
+void mbedtls_des3_init( mbedtls_des3_context *ctx );
+
+/**
+ * \brief          Clear Triple-DES context
+ *
+ * \param ctx      DES3 context to be cleared
+ */
+void mbedtls_des3_free( mbedtls_des3_context *ctx );
+
+/**
+ * \brief          Set key parity on the given key to odd.
+ *
+ *                 DES keys are 56 bits long, but each byte is padded with
+ *                 a parity bit to allow verification.
+ *
+ * \param key      8-byte secret key
+ */
+void mbedtls_des_key_set_parity( unsigned char key[MBEDTLS_DES_KEY_SIZE] );
+
+/**
+ * \brief          Check that key parity on the given key is odd.
+ *
+ *                 DES keys are 56 bits long, but each byte is padded with
+ *                 a parity bit to allow verification.
+ *
+ * \param key      8-byte secret key
+ *
+ * \return         0 is parity was ok, 1 if parity was not correct.
+ */
+int mbedtls_des_key_check_key_parity( const unsigned char key[MBEDTLS_DES_KEY_SIZE] );
+
+/**
+ * \brief          Check that key is not a weak or semi-weak DES key
+ *
+ * \param key      8-byte secret key
+ *
+ * \return         0 if no weak key was found, 1 if a weak key was identified.
+ */
+int mbedtls_des_key_check_weak( const unsigned char key[MBEDTLS_DES_KEY_SIZE] );
+
+/**
+ * \brief          DES key schedule (56-bit, encryption)
+ *
+ * \param ctx      DES context to be initialized
+ * \param key      8-byte secret key
+ *
+ * \return         0
+ */
+int mbedtls_des_setkey_enc( mbedtls_des_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] );
+
+/**
+ * \brief          DES key schedule (56-bit, decryption)
+ *
+ * \param ctx      DES context to be initialized
+ * \param key      8-byte secret key
+ *
+ * \return         0
+ */
+int mbedtls_des_setkey_dec( mbedtls_des_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] );
+
+/**
+ * \brief          Triple-DES key schedule (112-bit, encryption)
+ *
+ * \param ctx      3DES context to be initialized
+ * \param key      16-byte secret key
+ *
+ * \return         0
+ */
+int mbedtls_des3_set2key_enc( mbedtls_des3_context *ctx,
+                      const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] );
+
+/**
+ * \brief          Triple-DES key schedule (112-bit, decryption)
+ *
+ * \param ctx      3DES context to be initialized
+ * \param key      16-byte secret key
+ *
+ * \return         0
+ */
+int mbedtls_des3_set2key_dec( mbedtls_des3_context *ctx,
+                      const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] );
+
+/**
+ * \brief          Triple-DES key schedule (168-bit, encryption)
+ *
+ * \param ctx      3DES context to be initialized
+ * \param key      24-byte secret key
+ *
+ * \return         0
+ */
+int mbedtls_des3_set3key_enc( mbedtls_des3_context *ctx,
+                      const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] );
+
+/**
+ * \brief          Triple-DES key schedule (168-bit, decryption)
+ *
+ * \param ctx      3DES context to be initialized
+ * \param key      24-byte secret key
+ *
+ * \return         0
+ */
+int mbedtls_des3_set3key_dec( mbedtls_des3_context *ctx,
+                      const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] );
+
+/**
+ * \brief          DES-ECB block encryption/decryption
+ *
+ * \param ctx      DES context
+ * \param input    64-bit input block
+ * \param output   64-bit output block
+ *
+ * \return         0 if successful
+ */
+int mbedtls_des_crypt_ecb( mbedtls_des_context *ctx,
+                    const unsigned char input[8],
+                    unsigned char output[8] );
+
+#if defined(MBEDTLS_CIPHER_MODE_CBC)
+/**
+ * \brief          DES-CBC buffer encryption/decryption
+ *
+ * \note           Upon exit, the content of the IV is updated so that you can
+ *                 call the function same function again on the following
+ *                 block(s) of data and get the same result as if it was
+ *                 encrypted in one call. This allows a "streaming" usage.
+ *                 If on the other hand you need to retain the contents of the
+ *                 IV, you should either save it manually or use the cipher
+ *                 module instead.
+ *
+ * \param ctx      DES context
+ * \param mode     MBEDTLS_DES_ENCRYPT or MBEDTLS_DES_DECRYPT
+ * \param length   length of the input data
+ * \param iv       initialization vector (updated after use)
+ * \param input    buffer holding the input data
+ * \param output   buffer holding the output data
+ */
+int mbedtls_des_crypt_cbc( mbedtls_des_context *ctx,
+                    int mode,
+                    size_t length,
+                    unsigned char iv[8],
+                    const unsigned char *input,
+                    unsigned char *output );
+#endif /* MBEDTLS_CIPHER_MODE_CBC */
+
+/**
+ * \brief          3DES-ECB block encryption/decryption
+ *
+ * \param ctx      3DES context
+ * \param input    64-bit input block
+ * \param output   64-bit output block
+ *
+ * \return         0 if successful
+ */
+int mbedtls_des3_crypt_ecb( mbedtls_des3_context *ctx,
+                     const unsigned char input[8],
+                     unsigned char output[8] );
+
+#if defined(MBEDTLS_CIPHER_MODE_CBC)
+/**
+ * \brief          3DES-CBC buffer encryption/decryption
+ *
+ * \note           Upon exit, the content of the IV is updated so that you can
+ *                 call the function same function again on the following
+ *                 block(s) of data and get the same result as if it was
+ *                 encrypted in one call. This allows a "streaming" usage.
+ *                 If on the other hand you need to retain the contents of the
+ *                 IV, you should either save it manually or use the cipher
+ *                 module instead.
+ *
+ * \param ctx      3DES context
+ * \param mode     MBEDTLS_DES_ENCRYPT or MBEDTLS_DES_DECRYPT
+ * \param length   length of the input data
+ * \param iv       initialization vector (updated after use)
+ * \param input    buffer holding the input data
+ * \param output   buffer holding the output data
+ *
+ * \return         0 if successful, or MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH
+ */
+int mbedtls_des3_crypt_cbc( mbedtls_des3_context *ctx,
+                     int mode,
+                     size_t length,
+                     unsigned char iv[8],
+                     const unsigned char *input,
+                     unsigned char *output );
+#endif /* MBEDTLS_CIPHER_MODE_CBC */
+
+/**
+ * \brief          Internal function for key expansion.
+ *                 (Only exposed to allow overriding it,
+ *                 see MBEDTLS_DES_SETKEY_ALT)
+ *
+ * \param SK       Round keys
+ * \param key      Base key
+ */
+void mbedtls_des_setkey( uint32_t SK[32],
+                         const unsigned char key[MBEDTLS_DES_KEY_SIZE] );
+#ifdef __cplusplus
+}
+#endif
+
+#else  /* MBEDTLS_DES_ALT */
+#include "des_alt.h"
+#endif /* MBEDTLS_DES_ALT */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          Checkup routine
+ *
+ * \return         0 if successful, or 1 if the test failed
+ */
+int mbedtls_des_self_test( int verbose );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* des.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/dhm.h b/tools/sdk/include/mbedtls/mbedtls/dhm.h
new file mode 100644
index 00000000..d7ab1522
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/dhm.h
@@ -0,0 +1,305 @@
+/**
+ * \file dhm.h
+ *
+ * \brief Diffie-Hellman-Merkle key exchange
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_DHM_H
+#define MBEDTLS_DHM_H
+
+#include "bignum.h"
+
+/*
+ * DHM Error codes
+ */
+#define MBEDTLS_ERR_DHM_BAD_INPUT_DATA                    -0x3080  /**< Bad input parameters to function. */
+#define MBEDTLS_ERR_DHM_READ_PARAMS_FAILED                -0x3100  /**< Reading of the DHM parameters failed. */
+#define MBEDTLS_ERR_DHM_MAKE_PARAMS_FAILED                -0x3180  /**< Making of the DHM parameters failed. */
+#define MBEDTLS_ERR_DHM_READ_PUBLIC_FAILED                -0x3200  /**< Reading of the public values failed. */
+#define MBEDTLS_ERR_DHM_MAKE_PUBLIC_FAILED                -0x3280  /**< Making of the public value failed. */
+#define MBEDTLS_ERR_DHM_CALC_SECRET_FAILED                -0x3300  /**< Calculation of the DHM secret failed. */
+#define MBEDTLS_ERR_DHM_INVALID_FORMAT                    -0x3380  /**< The ASN.1 data is not formatted correctly. */
+#define MBEDTLS_ERR_DHM_ALLOC_FAILED                      -0x3400  /**< Allocation of memory failed. */
+#define MBEDTLS_ERR_DHM_FILE_IO_ERROR                     -0x3480  /**< Read/write of file failed. */
+
+/**
+ * RFC 3526 defines a number of standardized Diffie-Hellman groups
+ * for IKE.
+ * RFC 5114 defines a number of standardized Diffie-Hellman groups
+ * that can be used.
+ *
+ * Some are included here for convenience.
+ *
+ * Included are:
+ *  RFC 3526 3.    2048-bit MODP Group
+ *  RFC 3526 4.    3072-bit MODP Group
+ *  RFC 3526 5.    4096-bit MODP Group
+ *  RFC 5114 2.2.  2048-bit MODP Group with 224-bit Prime Order Subgroup
+ */
+#define MBEDTLS_DHM_RFC3526_MODP_2048_P               \
+    "FFFFFFFFFFFFFFFFC90FDAA22168C234C4C6628B80DC1CD1" \
+    "29024E088A67CC74020BBEA63B139B22514A08798E3404DD" \
+    "EF9519B3CD3A431B302B0A6DF25F14374FE1356D6D51C245" \
+    "E485B576625E7EC6F44C42E9A637ED6B0BFF5CB6F406B7ED" \
+    "EE386BFB5A899FA5AE9F24117C4B1FE649286651ECE45B3D" \
+    "C2007CB8A163BF0598DA48361C55D39A69163FA8FD24CF5F" \
+    "83655D23DCA3AD961C62F356208552BB9ED529077096966D" \
+    "670C354E4ABC9804F1746C08CA18217C32905E462E36CE3B" \
+    "E39E772C180E86039B2783A2EC07A28FB5C55DF06F4C52C9" \
+    "DE2BCBF6955817183995497CEA956AE515D2261898FA0510" \
+    "15728E5A8AACAA68FFFFFFFFFFFFFFFF"
+
+#define MBEDTLS_DHM_RFC3526_MODP_2048_G          "02"
+
+#define MBEDTLS_DHM_RFC3526_MODP_3072_P               \
+    "FFFFFFFFFFFFFFFFC90FDAA22168C234C4C6628B80DC1CD1" \
+    "29024E088A67CC74020BBEA63B139B22514A08798E3404DD" \
+    "EF9519B3CD3A431B302B0A6DF25F14374FE1356D6D51C245" \
+    "E485B576625E7EC6F44C42E9A637ED6B0BFF5CB6F406B7ED" \
+    "EE386BFB5A899FA5AE9F24117C4B1FE649286651ECE45B3D" \
+    "C2007CB8A163BF0598DA48361C55D39A69163FA8FD24CF5F" \
+    "83655D23DCA3AD961C62F356208552BB9ED529077096966D" \
+    "670C354E4ABC9804F1746C08CA18217C32905E462E36CE3B" \
+    "E39E772C180E86039B2783A2EC07A28FB5C55DF06F4C52C9" \
+    "DE2BCBF6955817183995497CEA956AE515D2261898FA0510" \
+    "15728E5A8AAAC42DAD33170D04507A33A85521ABDF1CBA64" \
+    "ECFB850458DBEF0A8AEA71575D060C7DB3970F85A6E1E4C7" \
+    "ABF5AE8CDB0933D71E8C94E04A25619DCEE3D2261AD2EE6B" \
+    "F12FFA06D98A0864D87602733EC86A64521F2B18177B200C" \
+    "BBE117577A615D6C770988C0BAD946E208E24FA074E5AB31" \
+    "43DB5BFCE0FD108E4B82D120A93AD2CAFFFFFFFFFFFFFFFF"
+
+#define MBEDTLS_DHM_RFC3526_MODP_3072_G          "02"
+
+#define MBEDTLS_DHM_RFC3526_MODP_4096_P                \
+    "FFFFFFFFFFFFFFFFC90FDAA22168C234C4C6628B80DC1CD1" \
+    "29024E088A67CC74020BBEA63B139B22514A08798E3404DD" \
+    "EF9519B3CD3A431B302B0A6DF25F14374FE1356D6D51C245" \
+    "E485B576625E7EC6F44C42E9A637ED6B0BFF5CB6F406B7ED" \
+    "EE386BFB5A899FA5AE9F24117C4B1FE649286651ECE45B3D" \
+    "C2007CB8A163BF0598DA48361C55D39A69163FA8FD24CF5F" \
+    "83655D23DCA3AD961C62F356208552BB9ED529077096966D" \
+    "670C354E4ABC9804F1746C08CA18217C32905E462E36CE3B" \
+    "E39E772C180E86039B2783A2EC07A28FB5C55DF06F4C52C9" \
+    "DE2BCBF6955817183995497CEA956AE515D2261898FA0510" \
+    "15728E5A8AAAC42DAD33170D04507A33A85521ABDF1CBA64" \
+    "ECFB850458DBEF0A8AEA71575D060C7DB3970F85A6E1E4C7" \
+    "ABF5AE8CDB0933D71E8C94E04A25619DCEE3D2261AD2EE6B" \
+    "F12FFA06D98A0864D87602733EC86A64521F2B18177B200C" \
+    "BBE117577A615D6C770988C0BAD946E208E24FA074E5AB31" \
+    "43DB5BFCE0FD108E4B82D120A92108011A723C12A787E6D7" \
+    "88719A10BDBA5B2699C327186AF4E23C1A946834B6150BDA" \
+    "2583E9CA2AD44CE8DBBBC2DB04DE8EF92E8EFC141FBECAA6" \
+    "287C59474E6BC05D99B2964FA090C3A2233BA186515BE7ED" \
+    "1F612970CEE2D7AFB81BDD762170481CD0069127D5B05AA9" \
+    "93B4EA988D8FDDC186FFB7DC90A6C08F4DF435C934063199" \
+    "FFFFFFFFFFFFFFFF"
+
+#define MBEDTLS_DHM_RFC3526_MODP_4096_G          "02"
+
+#define MBEDTLS_DHM_RFC5114_MODP_2048_P               \
+    "AD107E1E9123A9D0D660FAA79559C51FA20D64E5683B9FD1" \
+    "B54B1597B61D0A75E6FA141DF95A56DBAF9A3C407BA1DF15" \
+    "EB3D688A309C180E1DE6B85A1274A0A66D3F8152AD6AC212" \
+    "9037C9EDEFDA4DF8D91E8FEF55B7394B7AD5B7D0B6C12207" \
+    "C9F98D11ED34DBF6C6BA0B2C8BBC27BE6A00E0A0B9C49708" \
+    "B3BF8A317091883681286130BC8985DB1602E714415D9330" \
+    "278273C7DE31EFDC7310F7121FD5A07415987D9ADC0A486D" \
+    "CDF93ACC44328387315D75E198C641A480CD86A1B9E587E8" \
+    "BE60E69CC928B2B9C52172E413042E9B23F10B0E16E79763" \
+    "C9B53DCF4BA80A29E3FB73C16B8E75B97EF363E2FFA31F71" \
+    "CF9DE5384E71B81C0AC4DFFE0C10E64F"
+
+#define MBEDTLS_DHM_RFC5114_MODP_2048_G              \
+    "AC4032EF4F2D9AE39DF30B5C8FFDAC506CDEBE7B89998CAF"\
+    "74866A08CFE4FFE3A6824A4E10B9A6F0DD921F01A70C4AFA"\
+    "AB739D7700C29F52C57DB17C620A8652BE5E9001A8D66AD7"\
+    "C17669101999024AF4D027275AC1348BB8A762D0521BC98A"\
+    "E247150422EA1ED409939D54DA7460CDB5F6C6B250717CBE"\
+    "F180EB34118E98D119529A45D6F834566E3025E316A330EF"\
+    "BB77A86F0C1AB15B051AE3D428C8F8ACB70A8137150B8EEB"\
+    "10E183EDD19963DDD9E263E4770589EF6AA21E7F5F2FF381"\
+    "B539CCE3409D13CD566AFBB48D6C019181E1BCFE94B30269"\
+    "EDFE72FE9B6AA4BD7B5A0F1C71CFFF4C19C418E1F6EC0179"\
+    "81BC087F2A7065B384B890D3191F2BFA"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          DHM context structure
+ */
+typedef struct
+{
+    size_t len; /*!<  size(P) in chars  */
+    mbedtls_mpi P;      /*!<  prime modulus     */
+    mbedtls_mpi G;      /*!<  generator         */
+    mbedtls_mpi X;      /*!<  secret value      */
+    mbedtls_mpi GX;     /*!<  self = G^X mod P  */
+    mbedtls_mpi GY;     /*!<  peer = G^Y mod P  */
+    mbedtls_mpi K;      /*!<  key = GY^X mod P  */
+    mbedtls_mpi RP;     /*!<  cached R^2 mod P  */
+    mbedtls_mpi Vi;     /*!<  blinding value    */
+    mbedtls_mpi Vf;     /*!<  un-blinding value */
+    mbedtls_mpi pX;     /*!<  previous X        */
+}
+mbedtls_dhm_context;
+
+/**
+ * \brief          Initialize DHM context
+ *
+ * \param ctx      DHM context to be initialized
+ */
+void mbedtls_dhm_init( mbedtls_dhm_context *ctx );
+
+/**
+ * \brief          Parse the ServerKeyExchange parameters
+ *
+ * \param ctx      DHM context
+ * \param p        &(start of input buffer)
+ * \param end      end of buffer
+ *
+ * \return         0 if successful, or an MBEDTLS_ERR_DHM_XXX error code
+ */
+int mbedtls_dhm_read_params( mbedtls_dhm_context *ctx,
+                     unsigned char **p,
+                     const unsigned char *end );
+
+/**
+ * \brief          Setup and write the ServerKeyExchange parameters
+ *
+ * \param ctx      DHM context
+ * \param x_size   private value size in bytes
+ * \param output   destination buffer
+ * \param olen     number of chars written
+ * \param f_rng    RNG function
+ * \param p_rng    RNG parameter
+ *
+ * \note           This function assumes that ctx->P and ctx->G
+ *                 have already been properly set (for example
+ *                 using mbedtls_mpi_read_string or mbedtls_mpi_read_binary).
+ *
+ * \return         0 if successful, or an MBEDTLS_ERR_DHM_XXX error code
+ */
+int mbedtls_dhm_make_params( mbedtls_dhm_context *ctx, int x_size,
+                     unsigned char *output, size_t *olen,
+                     int (*f_rng)(void *, unsigned char *, size_t),
+                     void *p_rng );
+
+/**
+ * \brief          Import the peer's public value G^Y
+ *
+ * \param ctx      DHM context
+ * \param input    input buffer
+ * \param ilen     size of buffer
+ *
+ * \return         0 if successful, or an MBEDTLS_ERR_DHM_XXX error code
+ */
+int mbedtls_dhm_read_public( mbedtls_dhm_context *ctx,
+                     const unsigned char *input, size_t ilen );
+
+/**
+ * \brief          Create own private value X and export G^X
+ *
+ * \param ctx      DHM context
+ * \param x_size   private value size in bytes
+ * \param output   destination buffer
+ * \param olen     must be at least equal to the size of P, ctx->len
+ * \param f_rng    RNG function
+ * \param p_rng    RNG parameter
+ *
+ * \return         0 if successful, or an MBEDTLS_ERR_DHM_XXX error code
+ */
+int mbedtls_dhm_make_public( mbedtls_dhm_context *ctx, int x_size,
+                     unsigned char *output, size_t olen,
+                     int (*f_rng)(void *, unsigned char *, size_t),
+                     void *p_rng );
+
+/**
+ * \brief          Derive and export the shared secret (G^Y)^X mod P
+ *
+ * \param ctx      DHM context
+ * \param output   destination buffer
+ * \param output_size   size of the destination buffer
+ * \param olen     on exit, holds the actual number of bytes written
+ * \param f_rng    RNG function, for blinding purposes
+ * \param p_rng    RNG parameter
+ *
+ * \return         0 if successful, or an MBEDTLS_ERR_DHM_XXX error code
+ *
+ * \note           If non-NULL, f_rng is used to blind the input as
+ *                 countermeasure against timing attacks. Blinding is
+ *                 automatically used if and only if our secret value X is
+ *                 re-used and costs nothing otherwise, so it is recommended
+ *                 to always pass a non-NULL f_rng argument.
+ */
+int mbedtls_dhm_calc_secret( mbedtls_dhm_context *ctx,
+                     unsigned char *output, size_t output_size, size_t *olen,
+                     int (*f_rng)(void *, unsigned char *, size_t),
+                     void *p_rng );
+
+/**
+ * \brief          Free and clear the components of a DHM key
+ *
+ * \param ctx      DHM context to free and clear
+ */
+void mbedtls_dhm_free( mbedtls_dhm_context *ctx );
+
+#if defined(MBEDTLS_ASN1_PARSE_C)
+/** \ingroup x509_module */
+/**
+ * \brief          Parse DHM parameters in PEM or DER format
+ *
+ * \param dhm      DHM context to be initialized
+ * \param dhmin    input buffer
+ * \param dhminlen size of the buffer
+ *                 (including the terminating null byte for PEM data)
+ *
+ * \return         0 if successful, or a specific DHM or PEM error code
+ */
+int mbedtls_dhm_parse_dhm( mbedtls_dhm_context *dhm, const unsigned char *dhmin,
+                   size_t dhminlen );
+
+#if defined(MBEDTLS_FS_IO)
+/** \ingroup x509_module */
+/**
+ * \brief          Load and parse DHM parameters
+ *
+ * \param dhm      DHM context to be initialized
+ * \param path     filename to read the DHM Parameters from
+ *
+ * \return         0 if successful, or a specific DHM or PEM error code
+ */
+int mbedtls_dhm_parse_dhmfile( mbedtls_dhm_context *dhm, const char *path );
+#endif /* MBEDTLS_FS_IO */
+#endif /* MBEDTLS_ASN1_PARSE_C */
+
+/**
+ * \brief          Checkup routine
+ *
+ * \return         0 if successful, or 1 if the test failed
+ */
+int mbedtls_dhm_self_test( int verbose );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* dhm.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/ecdh.h b/tools/sdk/include/mbedtls/mbedtls/ecdh.h
new file mode 100644
index 00000000..625a2819
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/ecdh.h
@@ -0,0 +1,214 @@
+/**
+ * \file ecdh.h
+ *
+ * \brief Elliptic curve Diffie-Hellman
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_ECDH_H
+#define MBEDTLS_ECDH_H
+
+#include "ecp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * When importing from an EC key, select if it is our key or the peer's key
+ */
+typedef enum
+{
+    MBEDTLS_ECDH_OURS,
+    MBEDTLS_ECDH_THEIRS,
+} mbedtls_ecdh_side;
+
+/**
+ * \brief           ECDH context structure
+ */
+typedef struct
+{
+    mbedtls_ecp_group grp;      /*!<  elliptic curve used                           */
+    mbedtls_mpi d;              /*!<  our secret value (private key)                */
+    mbedtls_ecp_point Q;        /*!<  our public value (public key)                 */
+    mbedtls_ecp_point Qp;       /*!<  peer's public value (public key)              */
+    mbedtls_mpi z;              /*!<  shared secret                                 */
+    int point_format;   /*!<  format for point export in TLS messages       */
+    mbedtls_ecp_point Vi;       /*!<  blinding value (for later)                    */
+    mbedtls_ecp_point Vf;       /*!<  un-blinding value (for later)                 */
+    mbedtls_mpi _d;             /*!<  previous d (for later)                        */
+}
+mbedtls_ecdh_context;
+
+/**
+ * \brief           Generate a public key.
+ *                  Raw function that only does the core computation.
+ *
+ * \param grp       ECP group
+ * \param d         Destination MPI (secret exponent, aka private key)
+ * \param Q         Destination point (public key)
+ * \param f_rng     RNG function
+ * \param p_rng     RNG parameter
+ *
+ * \return          0 if successful,
+ *                  or a MBEDTLS_ERR_ECP_XXX or MBEDTLS_MPI_XXX error code
+ */
+int mbedtls_ecdh_gen_public( mbedtls_ecp_group *grp, mbedtls_mpi *d, mbedtls_ecp_point *Q,
+                     int (*f_rng)(void *, unsigned char *, size_t),
+                     void *p_rng );
+
+/**
+ * \brief           Compute shared secret
+ *                  Raw function that only does the core computation.
+ *
+ * \param grp       ECP group
+ * \param z         Destination MPI (shared secret)
+ * \param Q         Public key from other party
+ * \param d         Our secret exponent (private key)
+ * \param f_rng     RNG function (see notes)
+ * \param p_rng     RNG parameter
+ *
+ * \return          0 if successful,
+ *                  or a MBEDTLS_ERR_ECP_XXX or MBEDTLS_MPI_XXX error code
+ *
+ * \note            If f_rng is not NULL, it is used to implement
+ *                  countermeasures against potential elaborate timing
+ *                  attacks, see \c mbedtls_ecp_mul() for details.
+ */
+int mbedtls_ecdh_compute_shared( mbedtls_ecp_group *grp, mbedtls_mpi *z,
+                         const mbedtls_ecp_point *Q, const mbedtls_mpi *d,
+                         int (*f_rng)(void *, unsigned char *, size_t),
+                         void *p_rng );
+
+/**
+ * \brief           Initialize context
+ *
+ * \param ctx       Context to initialize
+ */
+void mbedtls_ecdh_init( mbedtls_ecdh_context *ctx );
+
+/**
+ * \brief           Free context
+ *
+ * \param ctx       Context to free
+ */
+void mbedtls_ecdh_free( mbedtls_ecdh_context *ctx );
+
+/**
+ * \brief           Generate a public key and a TLS ServerKeyExchange payload.
+ *                  (First function used by a TLS server for ECDHE.)
+ *
+ * \param ctx       ECDH context
+ * \param olen      number of chars written
+ * \param buf       destination buffer
+ * \param blen      length of buffer
+ * \param f_rng     RNG function
+ * \param p_rng     RNG parameter
+ *
+ * \note            This function assumes that ctx->grp has already been
+ *                  properly set (for example using mbedtls_ecp_group_load).
+ *
+ * \return          0 if successful, or an MBEDTLS_ERR_ECP_XXX error code
+ */
+int mbedtls_ecdh_make_params( mbedtls_ecdh_context *ctx, size_t *olen,
+                      unsigned char *buf, size_t blen,
+                      int (*f_rng)(void *, unsigned char *, size_t),
+                      void *p_rng );
+
+/**
+ * \brief           Parse and procress a TLS ServerKeyExhange payload.
+ *                  (First function used by a TLS client for ECDHE.)
+ *
+ * \param ctx       ECDH context
+ * \param buf       pointer to start of input buffer
+ * \param end       one past end of buffer
+ *
+ * \return          0 if successful, or an MBEDTLS_ERR_ECP_XXX error code
+ */
+int mbedtls_ecdh_read_params( mbedtls_ecdh_context *ctx,
+                      const unsigned char **buf, const unsigned char *end );
+
+/**
+ * \brief           Setup an ECDH context from an EC key.
+ *                  (Used by clients and servers in place of the
+ *                  ServerKeyEchange for static ECDH: import ECDH parameters
+ *                  from a certificate's EC key information.)
+ *
+ * \param ctx       ECDH constext to set
+ * \param key       EC key to use
+ * \param side      Is it our key (1) or the peer's key (0) ?
+ *
+ * \return          0 if successful, or an MBEDTLS_ERR_ECP_XXX error code
+ */
+int mbedtls_ecdh_get_params( mbedtls_ecdh_context *ctx, const mbedtls_ecp_keypair *key,
+                     mbedtls_ecdh_side side );
+
+/**
+ * \brief           Generate a public key and a TLS ClientKeyExchange payload.
+ *                  (Second function used by a TLS client for ECDH(E).)
+ *
+ * \param ctx       ECDH context
+ * \param olen      number of bytes actually written
+ * \param buf       destination buffer
+ * \param blen      size of destination buffer
+ * \param f_rng     RNG function
+ * \param p_rng     RNG parameter
+ *
+ * \return          0 if successful, or an MBEDTLS_ERR_ECP_XXX error code
+ */
+int mbedtls_ecdh_make_public( mbedtls_ecdh_context *ctx, size_t *olen,
+                      unsigned char *buf, size_t blen,
+                      int (*f_rng)(void *, unsigned char *, size_t),
+                      void *p_rng );
+
+/**
+ * \brief           Parse and process a TLS ClientKeyExchange payload.
+ *                  (Second function used by a TLS server for ECDH(E).)
+ *
+ * \param ctx       ECDH context
+ * \param buf       start of input buffer
+ * \param blen      length of input buffer
+ *
+ * \return          0 if successful, or an MBEDTLS_ERR_ECP_XXX error code
+ */
+int mbedtls_ecdh_read_public( mbedtls_ecdh_context *ctx,
+                      const unsigned char *buf, size_t blen );
+
+/**
+ * \brief           Derive and export the shared secret.
+ *                  (Last function used by both TLS client en servers.)
+ *
+ * \param ctx       ECDH context
+ * \param olen      number of bytes written
+ * \param buf       destination buffer
+ * \param blen      buffer length
+ * \param f_rng     RNG function, see notes for \c mbedtls_ecdh_compute_shared()
+ * \param p_rng     RNG parameter
+ *
+ * \return          0 if successful, or an MBEDTLS_ERR_ECP_XXX error code
+ */
+int mbedtls_ecdh_calc_secret( mbedtls_ecdh_context *ctx, size_t *olen,
+                      unsigned char *buf, size_t blen,
+                      int (*f_rng)(void *, unsigned char *, size_t),
+                      void *p_rng );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ecdh.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/ecdsa.h b/tools/sdk/include/mbedtls/mbedtls/ecdsa.h
new file mode 100644
index 00000000..52827d8d
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/ecdsa.h
@@ -0,0 +1,248 @@
+/**
+ * \file ecdsa.h
+ *
+ * \brief Elliptic curve DSA
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_ECDSA_H
+#define MBEDTLS_ECDSA_H
+
+#include "ecp.h"
+#include "md.h"
+
+/*
+ * RFC 4492 page 20:
+ *
+ *     Ecdsa-Sig-Value ::= SEQUENCE {
+ *         r       INTEGER,
+ *         s       INTEGER
+ *     }
+ *
+ * Size is at most
+ *    1 (tag) + 1 (len) + 1 (initial 0) + ECP_MAX_BYTES for each of r and s,
+ *    twice that + 1 (tag) + 2 (len) for the sequence
+ * (assuming ECP_MAX_BYTES is less than 126 for r and s,
+ * and less than 124 (total len <= 255) for the sequence)
+ */
+#if MBEDTLS_ECP_MAX_BYTES > 124
+#error "MBEDTLS_ECP_MAX_BYTES bigger than expected, please fix MBEDTLS_ECDSA_MAX_LEN"
+#endif
+/** Maximum size of an ECDSA signature in bytes */
+#define MBEDTLS_ECDSA_MAX_LEN  ( 3 + 2 * ( 3 + MBEDTLS_ECP_MAX_BYTES ) )
+
+/**
+ * \brief           ECDSA context structure
+ */
+typedef mbedtls_ecp_keypair mbedtls_ecdsa_context;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief           Compute ECDSA signature of a previously hashed message
+ *
+ * \note            The deterministic version is usually prefered.
+ *
+ * \param grp       ECP group
+ * \param r         First output integer
+ * \param s         Second output integer
+ * \param d         Private signing key
+ * \param buf       Message hash
+ * \param blen      Length of buf
+ * \param f_rng     RNG function
+ * \param p_rng     RNG parameter
+ *
+ * \return          0 if successful,
+ *                  or a MBEDTLS_ERR_ECP_XXX or MBEDTLS_MPI_XXX error code
+ */
+int mbedtls_ecdsa_sign( mbedtls_ecp_group *grp, mbedtls_mpi *r, mbedtls_mpi *s,
+                const mbedtls_mpi *d, const unsigned char *buf, size_t blen,
+                int (*f_rng)(void *, unsigned char *, size_t), void *p_rng );
+
+#if defined(MBEDTLS_ECDSA_DETERMINISTIC)
+/**
+ * \brief           Compute ECDSA signature of a previously hashed message,
+ *                  deterministic version (RFC 6979).
+ *
+ * \param grp       ECP group
+ * \param r         First output integer
+ * \param s         Second output integer
+ * \param d         Private signing key
+ * \param buf       Message hash
+ * \param blen      Length of buf
+ * \param md_alg    MD algorithm used to hash the message
+ *
+ * \return          0 if successful,
+ *                  or a MBEDTLS_ERR_ECP_XXX or MBEDTLS_MPI_XXX error code
+ */
+int mbedtls_ecdsa_sign_det( mbedtls_ecp_group *grp, mbedtls_mpi *r, mbedtls_mpi *s,
+                    const mbedtls_mpi *d, const unsigned char *buf, size_t blen,
+                    mbedtls_md_type_t md_alg );
+#endif /* MBEDTLS_ECDSA_DETERMINISTIC */
+
+/**
+ * \brief           Verify ECDSA signature of a previously hashed message
+ *
+ * \param grp       ECP group
+ * \param buf       Message hash
+ * \param blen      Length of buf
+ * \param Q         Public key to use for verification
+ * \param r         First integer of the signature
+ * \param s         Second integer of the signature
+ *
+ * \return          0 if successful,
+ *                  MBEDTLS_ERR_ECP_BAD_INPUT_DATA if signature is invalid
+ *                  or a MBEDTLS_ERR_ECP_XXX or MBEDTLS_MPI_XXX error code
+ */
+int mbedtls_ecdsa_verify( mbedtls_ecp_group *grp,
+                  const unsigned char *buf, size_t blen,
+                  const mbedtls_ecp_point *Q, const mbedtls_mpi *r, const mbedtls_mpi *s);
+
+/**
+ * \brief           Compute ECDSA signature and write it to buffer,
+ *                  serialized as defined in RFC 4492 page 20.
+ *                  (Not thread-safe to use same context in multiple threads)
+ *
+ * \note            The deterministice version (RFC 6979) is used if
+ *                  MBEDTLS_ECDSA_DETERMINISTIC is defined.
+ *
+ * \param ctx       ECDSA context
+ * \param md_alg    Algorithm that was used to hash the message
+ * \param hash      Message hash
+ * \param hlen      Length of hash
+ * \param sig       Buffer that will hold the signature
+ * \param slen      Length of the signature written
+ * \param f_rng     RNG function
+ * \param p_rng     RNG parameter
+ *
+ * \note            The "sig" buffer must be at least as large as twice the
+ *                  size of the curve used, plus 9 (eg. 73 bytes if a 256-bit
+ *                  curve is used). MBEDTLS_ECDSA_MAX_LEN is always safe.
+ *
+ * \return          0 if successful,
+ *                  or a MBEDTLS_ERR_ECP_XXX, MBEDTLS_ERR_MPI_XXX or
+ *                  MBEDTLS_ERR_ASN1_XXX error code
+ */
+int mbedtls_ecdsa_write_signature( mbedtls_ecdsa_context *ctx, mbedtls_md_type_t md_alg,
+                           const unsigned char *hash, size_t hlen,
+                           unsigned char *sig, size_t *slen,
+                           int (*f_rng)(void *, unsigned char *, size_t),
+                           void *p_rng );
+
+#if defined(MBEDTLS_ECDSA_DETERMINISTIC)
+#if ! defined(MBEDTLS_DEPRECATED_REMOVED)
+#if defined(MBEDTLS_DEPRECATED_WARNING)
+#define MBEDTLS_DEPRECATED    __attribute__((deprecated))
+#else
+#define MBEDTLS_DEPRECATED
+#endif
+/**
+ * \brief           Compute ECDSA signature and write it to buffer,
+ *                  serialized as defined in RFC 4492 page 20.
+ *                  Deterministic version, RFC 6979.
+ *                  (Not thread-safe to use same context in multiple threads)
+ *
+ * \deprecated      Superseded by mbedtls_ecdsa_write_signature() in 2.0.0
+ *
+ * \param ctx       ECDSA context
+ * \param hash      Message hash
+ * \param hlen      Length of hash
+ * \param sig       Buffer that will hold the signature
+ * \param slen      Length of the signature written
+ * \param md_alg    MD algorithm used to hash the message
+ *
+ * \note            The "sig" buffer must be at least as large as twice the
+ *                  size of the curve used, plus 9 (eg. 73 bytes if a 256-bit
+ *                  curve is used). MBEDTLS_ECDSA_MAX_LEN is always safe.
+ *
+ * \return          0 if successful,
+ *                  or a MBEDTLS_ERR_ECP_XXX, MBEDTLS_ERR_MPI_XXX or
+ *                  MBEDTLS_ERR_ASN1_XXX error code
+ */
+int mbedtls_ecdsa_write_signature_det( mbedtls_ecdsa_context *ctx,
+                               const unsigned char *hash, size_t hlen,
+                               unsigned char *sig, size_t *slen,
+                               mbedtls_md_type_t md_alg ) MBEDTLS_DEPRECATED;
+#undef MBEDTLS_DEPRECATED
+#endif /* MBEDTLS_DEPRECATED_REMOVED */
+#endif /* MBEDTLS_ECDSA_DETERMINISTIC */
+
+/**
+ * \brief           Read and verify an ECDSA signature
+ *
+ * \param ctx       ECDSA context
+ * \param hash      Message hash
+ * \param hlen      Size of hash
+ * \param sig       Signature to read and verify
+ * \param slen      Size of sig
+ *
+ * \return          0 if successful,
+ *                  MBEDTLS_ERR_ECP_BAD_INPUT_DATA if signature is invalid,
+ *                  MBEDTLS_ERR_ECP_SIG_LEN_MISMATCH if the signature is
+ *                  valid but its actual length is less than siglen,
+ *                  or a MBEDTLS_ERR_ECP_XXX or MBEDTLS_ERR_MPI_XXX error code
+ */
+int mbedtls_ecdsa_read_signature( mbedtls_ecdsa_context *ctx,
+                          const unsigned char *hash, size_t hlen,
+                          const unsigned char *sig, size_t slen );
+
+/**
+ * \brief           Generate an ECDSA keypair on the given curve
+ *
+ * \param ctx       ECDSA context in which the keypair should be stored
+ * \param gid       Group (elliptic curve) to use. One of the various
+ *                  MBEDTLS_ECP_DP_XXX macros depending on configuration.
+ * \param f_rng     RNG function
+ * \param p_rng     RNG parameter
+ *
+ * \return          0 on success, or a MBEDTLS_ERR_ECP_XXX code.
+ */
+int mbedtls_ecdsa_genkey( mbedtls_ecdsa_context *ctx, mbedtls_ecp_group_id gid,
+                  int (*f_rng)(void *, unsigned char *, size_t), void *p_rng );
+
+/**
+ * \brief           Set an ECDSA context from an EC key pair
+ *
+ * \param ctx       ECDSA context to set
+ * \param key       EC key to use
+ *
+ * \return          0 on success, or a MBEDTLS_ERR_ECP_XXX code.
+ */
+int mbedtls_ecdsa_from_keypair( mbedtls_ecdsa_context *ctx, const mbedtls_ecp_keypair *key );
+
+/**
+ * \brief           Initialize context
+ *
+ * \param ctx       Context to initialize
+ */
+void mbedtls_ecdsa_init( mbedtls_ecdsa_context *ctx );
+
+/**
+ * \brief           Free context
+ *
+ * \param ctx       Context to free
+ */
+void mbedtls_ecdsa_free( mbedtls_ecdsa_context *ctx );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ecdsa.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/ecjpake.h b/tools/sdk/include/mbedtls/mbedtls/ecjpake.h
new file mode 100644
index 00000000..b7b61604
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/ecjpake.h
@@ -0,0 +1,238 @@
+/**
+ * \file ecjpake.h
+ *
+ * \brief Elliptic curve J-PAKE
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_ECJPAKE_H
+#define MBEDTLS_ECJPAKE_H
+
+/*
+ * J-PAKE is a password-authenticated key exchange that allows deriving a
+ * strong shared secret from a (potentially low entropy) pre-shared
+ * passphrase, with forward secrecy and mutual authentication.
+ * https://en.wikipedia.org/wiki/Password_Authenticated_Key_Exchange_by_Juggling
+ *
+ * This file implements the Elliptic Curve variant of J-PAKE,
+ * as defined in Chapter 7.4 of the Thread v1.0 Specification,
+ * available to members of the Thread Group http://threadgroup.org/
+ *
+ * As the J-PAKE algorithm is inherently symmetric, so is our API.
+ * Each party needs to send its first round message, in any order, to the
+ * other party, then each sends its second round message, in any order.
+ * The payloads are serialized in a way suitable for use in TLS, but could
+ * also be use outside TLS.
+ */
+
+#include "ecp.h"
+#include "md.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Roles in the EC J-PAKE exchange
+ */
+typedef enum {
+    MBEDTLS_ECJPAKE_CLIENT = 0,         /**< Client                         */
+    MBEDTLS_ECJPAKE_SERVER,             /**< Server                         */
+} mbedtls_ecjpake_role;
+
+/**
+ * EC J-PAKE context structure.
+ *
+ * J-PAKE is a symmetric protocol, except for the identifiers used in
+ * Zero-Knowledge Proofs, and the serialization of the second message
+ * (KeyExchange) as defined by the Thread spec.
+ *
+ * In order to benefit from this symmetry, we choose a different naming
+ * convetion from the Thread v1.0 spec. Correspondance is indicated in the
+ * description as a pair C: client name, S: server name
+ */
+typedef struct
+{
+    const mbedtls_md_info_t *md_info;   /**< Hash to use                    */
+    mbedtls_ecp_group grp;              /**< Elliptic curve                 */
+    mbedtls_ecjpake_role role;          /**< Are we client or server?       */
+    int point_format;                   /**< Format for point export        */
+
+    mbedtls_ecp_point Xm1;              /**< My public key 1   C: X1, S: X3 */
+    mbedtls_ecp_point Xm2;              /**< My public key 2   C: X2, S: X4 */
+    mbedtls_ecp_point Xp1;              /**< Peer public key 1 C: X3, S: X1 */
+    mbedtls_ecp_point Xp2;              /**< Peer public key 2 C: X4, S: X2 */
+    mbedtls_ecp_point Xp;               /**< Peer public key   C: Xs, S: Xc */
+
+    mbedtls_mpi xm1;                    /**< My private key 1  C: x1, S: x3 */
+    mbedtls_mpi xm2;                    /**< My private key 2  C: x2, S: x4 */
+
+    mbedtls_mpi s;                      /**< Pre-shared secret (passphrase) */
+} mbedtls_ecjpake_context;
+
+/**
+ * \brief           Initialize a context
+ *                  (just makes it ready for setup() or free()).
+ *
+ * \param ctx       context to initialize
+ */
+void mbedtls_ecjpake_init( mbedtls_ecjpake_context *ctx );
+
+/**
+ * \brief           Set up a context for use
+ *
+ * \note            Currently the only values for hash/curve allowed by the
+ *                  standard are MBEDTLS_MD_SHA256/MBEDTLS_ECP_DP_SECP256R1.
+ *
+ * \param ctx       context to set up
+ * \param role      Our role: client or server
+ * \param hash      hash function to use (MBEDTLS_MD_XXX)
+ * \param curve     elliptic curve identifier (MBEDTLS_ECP_DP_XXX)
+ * \param secret    pre-shared secret (passphrase)
+ * \param len       length of the shared secret
+ *
+ * \return          0 if successfull,
+ *                  a negative error code otherwise
+ */
+int mbedtls_ecjpake_setup( mbedtls_ecjpake_context *ctx,
+                           mbedtls_ecjpake_role role,
+                           mbedtls_md_type_t hash,
+                           mbedtls_ecp_group_id curve,
+                           const unsigned char *secret,
+                           size_t len );
+
+/*
+ * \brief           Check if a context is ready for use
+ *
+ * \param ctx       Context to check
+ *
+ * \return          0 if the context is ready for use,
+ *                  MBEDTLS_ERR_ECP_BAD_INPUT_DATA otherwise
+ */
+int mbedtls_ecjpake_check( const mbedtls_ecjpake_context *ctx );
+
+/**
+ * \brief           Generate and write the first round message
+ *                  (TLS: contents of the Client/ServerHello extension,
+ *                  excluding extension type and length bytes)
+ *
+ * \param ctx       Context to use
+ * \param buf       Buffer to write the contents to
+ * \param len       Buffer size
+ * \param olen      Will be updated with the number of bytes written
+ * \param f_rng     RNG function
+ * \param p_rng     RNG parameter
+ *
+ * \return          0 if successfull,
+ *                  a negative error code otherwise
+ */
+int mbedtls_ecjpake_write_round_one( mbedtls_ecjpake_context *ctx,
+                            unsigned char *buf, size_t len, size_t *olen,
+                            int (*f_rng)(void *, unsigned char *, size_t),
+                            void *p_rng );
+
+/**
+ * \brief           Read and process the first round message
+ *                  (TLS: contents of the Client/ServerHello extension,
+ *                  excluding extension type and length bytes)
+ *
+ * \param ctx       Context to use
+ * \param buf       Pointer to extension contents
+ * \param len       Extension length
+ *
+ * \return          0 if successfull,
+ *                  a negative error code otherwise
+ */
+int mbedtls_ecjpake_read_round_one( mbedtls_ecjpake_context *ctx,
+                                    const unsigned char *buf,
+                                    size_t len );
+
+/**
+ * \brief           Generate and write the second round message
+ *                  (TLS: contents of the Client/ServerKeyExchange)
+ *
+ * \param ctx       Context to use
+ * \param buf       Buffer to write the contents to
+ * \param len       Buffer size
+ * \param olen      Will be updated with the number of bytes written
+ * \param f_rng     RNG function
+ * \param p_rng     RNG parameter
+ *
+ * \return          0 if successfull,
+ *                  a negative error code otherwise
+ */
+int mbedtls_ecjpake_write_round_two( mbedtls_ecjpake_context *ctx,
+                            unsigned char *buf, size_t len, size_t *olen,
+                            int (*f_rng)(void *, unsigned char *, size_t),
+                            void *p_rng );
+
+/**
+ * \brief           Read and process the second round message
+ *                  (TLS: contents of the Client/ServerKeyExchange)
+ *
+ * \param ctx       Context to use
+ * \param buf       Pointer to the message
+ * \param len       Message length
+ *
+ * \return          0 if successfull,
+ *                  a negative error code otherwise
+ */
+int mbedtls_ecjpake_read_round_two( mbedtls_ecjpake_context *ctx,
+                                    const unsigned char *buf,
+                                    size_t len );
+
+/**
+ * \brief           Derive the shared secret
+ *                  (TLS: Pre-Master Secret)
+ *
+ * \param ctx       Context to use
+ * \param buf       Buffer to write the contents to
+ * \param len       Buffer size
+ * \param olen      Will be updated with the number of bytes written
+ * \param f_rng     RNG function
+ * \param p_rng     RNG parameter
+ *
+ * \return          0 if successfull,
+ *                  a negative error code otherwise
+ */
+int mbedtls_ecjpake_derive_secret( mbedtls_ecjpake_context *ctx,
+                            unsigned char *buf, size_t len, size_t *olen,
+                            int (*f_rng)(void *, unsigned char *, size_t),
+                            void *p_rng );
+
+/**
+ * \brief           Free a context's content
+ *
+ * \param ctx       context to free
+ */
+void mbedtls_ecjpake_free( mbedtls_ecjpake_context *ctx );
+
+#if defined(MBEDTLS_SELF_TEST)
+/**
+ * \brief          Checkup routine
+ *
+ * \return         0 if successful, or 1 if a test failed
+ */
+int mbedtls_ecjpake_self_test( int verbose );
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ecjpake.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/ecp.h b/tools/sdk/include/mbedtls/mbedtls/ecp.h
new file mode 100644
index 00000000..5246c789
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/ecp.h
@@ -0,0 +1,669 @@
+/**
+ * \file ecp.h
+ *
+ * \brief Elliptic curves over GF(p)
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_ECP_H
+#define MBEDTLS_ECP_H
+
+#include "bignum.h"
+
+/*
+ * ECP error codes
+ */
+#define MBEDTLS_ERR_ECP_BAD_INPUT_DATA                    -0x4F80  /**< Bad input parameters to function. */
+#define MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL                  -0x4F00  /**< The buffer is too small to write to. */
+#define MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE               -0x4E80  /**< Requested curve not available. */
+#define MBEDTLS_ERR_ECP_VERIFY_FAILED                     -0x4E00  /**< The signature is not valid. */
+#define MBEDTLS_ERR_ECP_ALLOC_FAILED                      -0x4D80  /**< Memory allocation failed. */
+#define MBEDTLS_ERR_ECP_RANDOM_FAILED                     -0x4D00  /**< Generation of random value, such as (ephemeral) key, failed. */
+#define MBEDTLS_ERR_ECP_INVALID_KEY                       -0x4C80  /**< Invalid private or public key. */
+#define MBEDTLS_ERR_ECP_SIG_LEN_MISMATCH                  -0x4C00  /**< Signature is valid but shorter than the user-supplied length. */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Domain parameters (curve, subgroup and generator) identifiers.
+ *
+ * Only curves over prime fields are supported.
+ *
+ * \warning This library does not support validation of arbitrary domain
+ * parameters. Therefore, only well-known domain parameters from trusted
+ * sources should be used. See mbedtls_ecp_group_load().
+ */
+typedef enum
+{
+    MBEDTLS_ECP_DP_NONE = 0,
+    MBEDTLS_ECP_DP_SECP192R1,      /*!< 192-bits NIST curve  */
+    MBEDTLS_ECP_DP_SECP224R1,      /*!< 224-bits NIST curve  */
+    MBEDTLS_ECP_DP_SECP256R1,      /*!< 256-bits NIST curve  */
+    MBEDTLS_ECP_DP_SECP384R1,      /*!< 384-bits NIST curve  */
+    MBEDTLS_ECP_DP_SECP521R1,      /*!< 521-bits NIST curve  */
+    MBEDTLS_ECP_DP_BP256R1,        /*!< 256-bits Brainpool curve */
+    MBEDTLS_ECP_DP_BP384R1,        /*!< 384-bits Brainpool curve */
+    MBEDTLS_ECP_DP_BP512R1,        /*!< 512-bits Brainpool curve */
+    MBEDTLS_ECP_DP_CURVE25519,           /*!< Curve25519               */
+    MBEDTLS_ECP_DP_SECP192K1,      /*!< 192-bits "Koblitz" curve */
+    MBEDTLS_ECP_DP_SECP224K1,      /*!< 224-bits "Koblitz" curve */
+    MBEDTLS_ECP_DP_SECP256K1,      /*!< 256-bits "Koblitz" curve */
+} mbedtls_ecp_group_id;
+
+/**
+ * Number of supported curves (plus one for NONE).
+ *
+ * (Montgomery curves excluded for now.)
+ */
+#define MBEDTLS_ECP_DP_MAX     12
+
+/**
+ * Curve information for use by other modules
+ */
+typedef struct
+{
+    mbedtls_ecp_group_id grp_id;    /*!< Internal identifier        */
+    uint16_t tls_id;                /*!< TLS NamedCurve identifier  */
+    uint16_t bit_size;              /*!< Curve size in bits         */
+    const char *name;               /*!< Human-friendly name        */
+} mbedtls_ecp_curve_info;
+
+/**
+ * \brief           ECP point structure (jacobian coordinates)
+ *
+ * \note            All functions expect and return points satisfying
+ *                  the following condition: Z == 0 or Z == 1. (Other
+ *                  values of Z are used by internal functions only.)
+ *                  The point is zero, or "at infinity", if Z == 0.
+ *                  Otherwise, X and Y are its standard (affine) coordinates.
+ */
+typedef struct
+{
+    mbedtls_mpi X;          /*!<  the point's X coordinate  */
+    mbedtls_mpi Y;          /*!<  the point's Y coordinate  */
+    mbedtls_mpi Z;          /*!<  the point's Z coordinate  */
+}
+mbedtls_ecp_point;
+
+/**
+ * \brief           ECP group structure
+ *
+ * We consider two types of curves equations:
+ * 1. Short Weierstrass y^2 = x^3 + A x + B     mod P   (SEC1 + RFC 4492)
+ * 2. Montgomery,       y^2 = x^3 + A x^2 + x   mod P   (Curve25519 + draft)
+ * In both cases, a generator G for a prime-order subgroup is fixed. In the
+ * short weierstrass, this subgroup is actually the whole curve, and its
+ * cardinal is denoted by N.
+ *
+ * In the case of Short Weierstrass curves, our code requires that N is an odd
+ * prime. (Use odd in mbedtls_ecp_mul() and prime in mbedtls_ecdsa_sign() for blinding.)
+ *
+ * In the case of Montgomery curves, we don't store A but (A + 2) / 4 which is
+ * the quantity actually used in the formulas. Also, nbits is not the size of N
+ * but the required size for private keys.
+ *
+ * If modp is NULL, reduction modulo P is done using a generic algorithm.
+ * Otherwise, it must point to a function that takes an mbedtls_mpi in the range
+ * 0..2^(2*pbits)-1 and transforms it in-place in an integer of little more
+ * than pbits, so that the integer may be efficiently brought in the 0..P-1
+ * range by a few additions or substractions. It must return 0 on success and
+ * non-zero on failure.
+ */
+typedef struct
+{
+    mbedtls_ecp_group_id id;    /*!<  internal group identifier                     */
+    mbedtls_mpi P;              /*!<  prime modulus of the base field               */
+    mbedtls_mpi A;              /*!<  1. A in the equation, or 2. (A + 2) / 4       */
+    mbedtls_mpi B;              /*!<  1. B in the equation, or 2. unused            */
+    mbedtls_ecp_point G;        /*!<  generator of the (sub)group used              */
+    mbedtls_mpi N;              /*!<  1. the order of G, or 2. unused               */
+    size_t pbits;       /*!<  number of bits in P                           */
+    size_t nbits;       /*!<  number of bits in 1. P, or 2. private keys    */
+    unsigned int h;     /*!<  internal: 1 if the constants are static       */
+    int (*modp)(mbedtls_mpi *); /*!<  function for fast reduction mod P             */
+    int (*t_pre)(mbedtls_ecp_point *, void *);  /*!< unused                         */
+    int (*t_post)(mbedtls_ecp_point *, void *); /*!< unused                         */
+    void *t_data;                       /*!< unused                         */
+    mbedtls_ecp_point *T;       /*!<  pre-computed points for ecp_mul_comb()        */
+    size_t T_size;      /*!<  number for pre-computed points                */
+}
+mbedtls_ecp_group;
+
+/**
+ * \brief           ECP key pair structure
+ *
+ * A generic key pair that could be used for ECDSA, fixed ECDH, etc.
+ *
+ * \note Members purposefully in the same order as struc mbedtls_ecdsa_context.
+ */
+typedef struct
+{
+    mbedtls_ecp_group grp;      /*!<  Elliptic curve and base point     */
+    mbedtls_mpi d;              /*!<  our secret value                  */
+    mbedtls_ecp_point Q;        /*!<  our public value                  */
+}
+mbedtls_ecp_keypair;
+
+/**
+ * \name SECTION: Module settings
+ *
+ * The configuration options you can set for this module are in this section.
+ * Either change them in config.h or define them on the compiler command line.
+ * \{
+ */
+
+#if !defined(MBEDTLS_ECP_MAX_BITS)
+/**
+ * Maximum size of the groups (that is, of N and P)
+ */
+#define MBEDTLS_ECP_MAX_BITS     521   /**< Maximum bit size of groups */
+#endif
+
+#define MBEDTLS_ECP_MAX_BYTES    ( ( MBEDTLS_ECP_MAX_BITS + 7 ) / 8 )
+#define MBEDTLS_ECP_MAX_PT_LEN   ( 2 * MBEDTLS_ECP_MAX_BYTES + 1 )
+
+#if !defined(MBEDTLS_ECP_WINDOW_SIZE)
+/*
+ * Maximum "window" size used for point multiplication.
+ * Default: 6.
+ * Minimum value: 2. Maximum value: 7.
+ *
+ * Result is an array of at most ( 1 << ( MBEDTLS_ECP_WINDOW_SIZE - 1 ) )
+ * points used for point multiplication. This value is directly tied to EC
+ * peak memory usage, so decreasing it by one should roughly cut memory usage
+ * by two (if large curves are in use).
+ *
+ * Reduction in size may reduce speed, but larger curves are impacted first.
+ * Sample performances (in ECDHE handshakes/s, with FIXED_POINT_OPTIM = 1):
+ *      w-size:     6       5       4       3       2
+ *      521       145     141     135     120      97
+ *      384       214     209     198     177     146
+ *      256       320     320     303     262     226
+
+ *      224       475     475     453     398     342
+ *      192       640     640     633     587     476
+ */
+#define MBEDTLS_ECP_WINDOW_SIZE    6   /**< Maximum window size used */
+#endif /* MBEDTLS_ECP_WINDOW_SIZE */
+
+#if !defined(MBEDTLS_ECP_FIXED_POINT_OPTIM)
+/*
+ * Trade memory for speed on fixed-point multiplication.
+ *
+ * This speeds up repeated multiplication of the generator (that is, the
+ * multiplication in ECDSA signatures, and half of the multiplications in
+ * ECDSA verification and ECDHE) by a factor roughly 3 to 4.
+ *
+ * The cost is increasing EC peak memory usage by a factor roughly 2.
+ *
+ * Change this value to 0 to reduce peak memory usage.
+ */
+#define MBEDTLS_ECP_FIXED_POINT_OPTIM  1   /**< Enable fixed-point speed-up */
+#endif /* MBEDTLS_ECP_FIXED_POINT_OPTIM */
+
+/* \} name SECTION: Module settings */
+
+/*
+ * Point formats, from RFC 4492's enum ECPointFormat
+ */
+#define MBEDTLS_ECP_PF_UNCOMPRESSED    0   /**< Uncompressed point format */
+#define MBEDTLS_ECP_PF_COMPRESSED      1   /**< Compressed point format */
+
+/*
+ * Some other constants from RFC 4492
+ */
+#define MBEDTLS_ECP_TLS_NAMED_CURVE    3   /**< ECCurveType's named_curve */
+
+/**
+ * \brief           Get the list of supported curves in order of preferrence
+ *                  (full information)
+ *
+ * \return          A statically allocated array, the last entry is 0.
+ */
+const mbedtls_ecp_curve_info *mbedtls_ecp_curve_list( void );
+
+/**
+ * \brief           Get the list of supported curves in order of preferrence
+ *                  (grp_id only)
+ *
+ * \return          A statically allocated array,
+ *                  terminated with MBEDTLS_ECP_DP_NONE.
+ */
+const mbedtls_ecp_group_id *mbedtls_ecp_grp_id_list( void );
+
+/**
+ * \brief           Get curve information from an internal group identifier
+ *
+ * \param grp_id    A MBEDTLS_ECP_DP_XXX value
+ *
+ * \return          The associated curve information or NULL
+ */
+const mbedtls_ecp_curve_info *mbedtls_ecp_curve_info_from_grp_id( mbedtls_ecp_group_id grp_id );
+
+/**
+ * \brief           Get curve information from a TLS NamedCurve value
+ *
+ * \param tls_id    A MBEDTLS_ECP_DP_XXX value
+ *
+ * \return          The associated curve information or NULL
+ */
+const mbedtls_ecp_curve_info *mbedtls_ecp_curve_info_from_tls_id( uint16_t tls_id );
+
+/**
+ * \brief           Get curve information from a human-readable name
+ *
+ * \param name      The name
+ *
+ * \return          The associated curve information or NULL
+ */
+const mbedtls_ecp_curve_info *mbedtls_ecp_curve_info_from_name( const char *name );
+
+/**
+ * \brief           Initialize a point (as zero)
+ */
+void mbedtls_ecp_point_init( mbedtls_ecp_point *pt );
+
+/**
+ * \brief           Initialize a group (to something meaningless)
+ */
+void mbedtls_ecp_group_init( mbedtls_ecp_group *grp );
+
+/**
+ * \brief           Initialize a key pair (as an invalid one)
+ */
+void mbedtls_ecp_keypair_init( mbedtls_ecp_keypair *key );
+
+/**
+ * \brief           Free the components of a point
+ */
+void mbedtls_ecp_point_free( mbedtls_ecp_point *pt );
+
+/**
+ * \brief           Free the components of an ECP group
+ */
+void mbedtls_ecp_group_free( mbedtls_ecp_group *grp );
+
+/**
+ * \brief           Free the components of a key pair
+ */
+void mbedtls_ecp_keypair_free( mbedtls_ecp_keypair *key );
+
+/**
+ * \brief           Copy the contents of point Q into P
+ *
+ * \param P         Destination point
+ * \param Q         Source point
+ *
+ * \return          0 if successful,
+ *                  MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed
+ */
+int mbedtls_ecp_copy( mbedtls_ecp_point *P, const mbedtls_ecp_point *Q );
+
+/**
+ * \brief           Copy the contents of a group object
+ *
+ * \param dst       Destination group
+ * \param src       Source group
+ *
+ * \return          0 if successful,
+ *                  MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed
+ */
+int mbedtls_ecp_group_copy( mbedtls_ecp_group *dst, const mbedtls_ecp_group *src );
+
+/**
+ * \brief           Set a point to zero
+ *
+ * \param pt        Destination point
+ *
+ * \return          0 if successful,
+ *                  MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed
+ */
+int mbedtls_ecp_set_zero( mbedtls_ecp_point *pt );
+
+/**
+ * \brief           Tell if a point is zero
+ *
+ * \param pt        Point to test
+ *
+ * \return          1 if point is zero, 0 otherwise
+ */
+int mbedtls_ecp_is_zero( mbedtls_ecp_point *pt );
+
+/**
+ * \brief           Compare two points
+ *
+ * \note            This assumes the points are normalized. Otherwise,
+ *                  they may compare as "not equal" even if they are.
+ *
+ * \param P         First point to compare
+ * \param Q         Second point to compare
+ *
+ * \return          0 if the points are equal,
+ *                  MBEDTLS_ERR_ECP_BAD_INPUT_DATA otherwise
+ */
+int mbedtls_ecp_point_cmp( const mbedtls_ecp_point *P,
+                           const mbedtls_ecp_point *Q );
+
+/**
+ * \brief           Import a non-zero point from two ASCII strings
+ *
+ * \param P         Destination point
+ * \param radix     Input numeric base
+ * \param x         First affine coordinate as a null-terminated string
+ * \param y         Second affine coordinate as a null-terminated string
+ *
+ * \return          0 if successful, or a MBEDTLS_ERR_MPI_XXX error code
+ */
+int mbedtls_ecp_point_read_string( mbedtls_ecp_point *P, int radix,
+                           const char *x, const char *y );
+
+/**
+ * \brief           Export a point into unsigned binary data
+ *
+ * \param grp       Group to which the point should belong
+ * \param P         Point to export
+ * \param format    Point format, should be a MBEDTLS_ECP_PF_XXX macro
+ * \param olen      Length of the actual output
+ * \param buf       Output buffer
+ * \param buflen    Length of the output buffer
+ *
+ * \return          0 if successful,
+ *                  or MBEDTLS_ERR_ECP_BAD_INPUT_DATA
+ *                  or MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL
+ */
+int mbedtls_ecp_point_write_binary( const mbedtls_ecp_group *grp, const mbedtls_ecp_point *P,
+                            int format, size_t *olen,
+                            unsigned char *buf, size_t buflen );
+
+/**
+ * \brief           Import a point from unsigned binary data
+ *
+ * \param grp       Group to which the point should belong
+ * \param P         Point to import
+ * \param buf       Input buffer
+ * \param ilen      Actual length of input
+ *
+ * \return          0 if successful,
+ *                  MBEDTLS_ERR_ECP_BAD_INPUT_DATA if input is invalid,
+ *                  MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed,
+ *                  MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE if the point format
+ *                  is not implemented.
+ *
+ * \note            This function does NOT check that the point actually
+ *                  belongs to the given group, see mbedtls_ecp_check_pubkey() for
+ *                  that.
+ */
+int mbedtls_ecp_point_read_binary( const mbedtls_ecp_group *grp, mbedtls_ecp_point *P,
+                           const unsigned char *buf, size_t ilen );
+
+/**
+ * \brief           Import a point from a TLS ECPoint record
+ *
+ * \param grp       ECP group used
+ * \param pt        Destination point
+ * \param buf       $(Start of input buffer)
+ * \param len       Buffer length
+ *
+ * \note            buf is updated to point right after the ECPoint on exit
+ *
+ * \return          0 if successful,
+ *                  MBEDTLS_ERR_MPI_XXX if initialization failed
+ *                  MBEDTLS_ERR_ECP_BAD_INPUT_DATA if input is invalid
+ */
+int mbedtls_ecp_tls_read_point( const mbedtls_ecp_group *grp, mbedtls_ecp_point *pt,
+                        const unsigned char **buf, size_t len );
+
+/**
+ * \brief           Export a point as a TLS ECPoint record
+ *
+ * \param grp       ECP group used
+ * \param pt        Point to export
+ * \param format    Export format
+ * \param olen      length of data written
+ * \param buf       Buffer to write to
+ * \param blen      Buffer length
+ *
+ * \return          0 if successful,
+ *                  or MBEDTLS_ERR_ECP_BAD_INPUT_DATA
+ *                  or MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL
+ */
+int mbedtls_ecp_tls_write_point( const mbedtls_ecp_group *grp, const mbedtls_ecp_point *pt,
+                         int format, size_t *olen,
+                         unsigned char *buf, size_t blen );
+
+/**
+ * \brief           Set a group using well-known domain parameters
+ *
+ * \param grp       Destination group
+ * \param index     Index in the list of well-known domain parameters
+ *
+ * \return          0 if successful,
+ *                  MBEDTLS_ERR_MPI_XXX if initialization failed
+ *                  MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE for unkownn groups
+ *
+ * \note            Index should be a value of RFC 4492's enum NamedCurve,
+ *                  usually in the form of a MBEDTLS_ECP_DP_XXX macro.
+ */
+int mbedtls_ecp_group_load( mbedtls_ecp_group *grp, mbedtls_ecp_group_id index );
+
+/**
+ * \brief           Set a group from a TLS ECParameters record
+ *
+ * \param grp       Destination group
+ * \param buf       &(Start of input buffer)
+ * \param len       Buffer length
+ *
+ * \note            buf is updated to point right after ECParameters on exit
+ *
+ * \return          0 if successful,
+ *                  MBEDTLS_ERR_MPI_XXX if initialization failed
+ *                  MBEDTLS_ERR_ECP_BAD_INPUT_DATA if input is invalid
+ */
+int mbedtls_ecp_tls_read_group( mbedtls_ecp_group *grp, const unsigned char **buf, size_t len );
+
+/**
+ * \brief           Write the TLS ECParameters record for a group
+ *
+ * \param grp       ECP group used
+ * \param olen      Number of bytes actually written
+ * \param buf       Buffer to write to
+ * \param blen      Buffer length
+ *
+ * \return          0 if successful,
+ *                  or MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL
+ */
+int mbedtls_ecp_tls_write_group( const mbedtls_ecp_group *grp, size_t *olen,
+                         unsigned char *buf, size_t blen );
+
+/**
+ * \brief           Multiplication by an integer: R = m * P
+ *                  (Not thread-safe to use same group in multiple threads)
+ *
+ * \note            In order to prevent timing attacks, this function
+ *                  executes the exact same sequence of (base field)
+ *                  operations for any valid m. It avoids any if-branch or
+ *                  array index depending on the value of m.
+ *
+ * \note            If f_rng is not NULL, it is used to randomize intermediate
+ *                  results in order to prevent potential timing attacks
+ *                  targeting these results. It is recommended to always
+ *                  provide a non-NULL f_rng (the overhead is negligible).
+ *
+ * \param grp       ECP group
+ * \param R         Destination point
+ * \param m         Integer by which to multiply
+ * \param P         Point to multiply
+ * \param f_rng     RNG function (see notes)
+ * \param p_rng     RNG parameter
+ *
+ * \return          0 if successful,
+ *                  MBEDTLS_ERR_ECP_INVALID_KEY if m is not a valid privkey
+ *                  or P is not a valid pubkey,
+ *                  MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed
+ */
+int mbedtls_ecp_mul( mbedtls_ecp_group *grp, mbedtls_ecp_point *R,
+             const mbedtls_mpi *m, const mbedtls_ecp_point *P,
+             int (*f_rng)(void *, unsigned char *, size_t), void *p_rng );
+
+/**
+ * \brief           Multiplication and addition of two points by integers:
+ *                  R = m * P + n * Q
+ *                  (Not thread-safe to use same group in multiple threads)
+ *
+ * \note            In contrast to mbedtls_ecp_mul(), this function does not guarantee
+ *                  a constant execution flow and timing.
+ *
+ * \param grp       ECP group
+ * \param R         Destination point
+ * \param m         Integer by which to multiply P
+ * \param P         Point to multiply by m
+ * \param n         Integer by which to multiply Q
+ * \param Q         Point to be multiplied by n
+ *
+ * \return          0 if successful,
+ *                  MBEDTLS_ERR_ECP_INVALID_KEY if m or n is not a valid privkey
+ *                  or P or Q is not a valid pubkey,
+ *                  MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed
+ */
+int mbedtls_ecp_muladd( mbedtls_ecp_group *grp, mbedtls_ecp_point *R,
+             const mbedtls_mpi *m, const mbedtls_ecp_point *P,
+             const mbedtls_mpi *n, const mbedtls_ecp_point *Q );
+
+/**
+ * \brief           Check that a point is a valid public key on this curve
+ *
+ * \param grp       Curve/group the point should belong to
+ * \param pt        Point to check
+ *
+ * \return          0 if point is a valid public key,
+ *                  MBEDTLS_ERR_ECP_INVALID_KEY otherwise.
+ *
+ * \note            This function only checks the point is non-zero, has valid
+ *                  coordinates and lies on the curve, but not that it is
+ *                  indeed a multiple of G. This is additional check is more
+ *                  expensive, isn't required by standards, and shouldn't be
+ *                  necessary if the group used has a small cofactor. In
+ *                  particular, it is useless for the NIST groups which all
+ *                  have a cofactor of 1.
+ *
+ * \note            Uses bare components rather than an mbedtls_ecp_keypair structure
+ *                  in order to ease use with other structures such as
+ *                  mbedtls_ecdh_context of mbedtls_ecdsa_context.
+ */
+int mbedtls_ecp_check_pubkey( const mbedtls_ecp_group *grp, const mbedtls_ecp_point *pt );
+
+/**
+ * \brief           Check that an mbedtls_mpi is a valid private key for this curve
+ *
+ * \param grp       Group used
+ * \param d         Integer to check
+ *
+ * \return          0 if point is a valid private key,
+ *                  MBEDTLS_ERR_ECP_INVALID_KEY otherwise.
+ *
+ * \note            Uses bare components rather than an mbedtls_ecp_keypair structure
+ *                  in order to ease use with other structures such as
+ *                  mbedtls_ecdh_context of mbedtls_ecdsa_context.
+ */
+int mbedtls_ecp_check_privkey( const mbedtls_ecp_group *grp, const mbedtls_mpi *d );
+
+/**
+ * \brief           Generate a keypair with configurable base point
+ *
+ * \param grp       ECP group
+ * \param G         Chosen base point
+ * \param d         Destination MPI (secret part)
+ * \param Q         Destination point (public part)
+ * \param f_rng     RNG function
+ * \param p_rng     RNG parameter
+ *
+ * \return          0 if successful,
+ *                  or a MBEDTLS_ERR_ECP_XXX or MBEDTLS_MPI_XXX error code
+ *
+ * \note            Uses bare components rather than an mbedtls_ecp_keypair structure
+ *                  in order to ease use with other structures such as
+ *                  mbedtls_ecdh_context of mbedtls_ecdsa_context.
+ */
+int mbedtls_ecp_gen_keypair_base( mbedtls_ecp_group *grp,
+                     const mbedtls_ecp_point *G,
+                     mbedtls_mpi *d, mbedtls_ecp_point *Q,
+                     int (*f_rng)(void *, unsigned char *, size_t),
+                     void *p_rng );
+
+/**
+ * \brief           Generate a keypair
+ *
+ * \param grp       ECP group
+ * \param d         Destination MPI (secret part)
+ * \param Q         Destination point (public part)
+ * \param f_rng     RNG function
+ * \param p_rng     RNG parameter
+ *
+ * \return          0 if successful,
+ *                  or a MBEDTLS_ERR_ECP_XXX or MBEDTLS_MPI_XXX error code
+ *
+ * \note            Uses bare components rather than an mbedtls_ecp_keypair structure
+ *                  in order to ease use with other structures such as
+ *                  mbedtls_ecdh_context of mbedtls_ecdsa_context.
+ */
+int mbedtls_ecp_gen_keypair( mbedtls_ecp_group *grp, mbedtls_mpi *d, mbedtls_ecp_point *Q,
+                     int (*f_rng)(void *, unsigned char *, size_t),
+                     void *p_rng );
+
+/**
+ * \brief           Generate a keypair
+ *
+ * \param grp_id    ECP group identifier
+ * \param key       Destination keypair
+ * \param f_rng     RNG function
+ * \param p_rng     RNG parameter
+ *
+ * \return          0 if successful,
+ *                  or a MBEDTLS_ERR_ECP_XXX or MBEDTLS_MPI_XXX error code
+ */
+int mbedtls_ecp_gen_key( mbedtls_ecp_group_id grp_id, mbedtls_ecp_keypair *key,
+                int (*f_rng)(void *, unsigned char *, size_t), void *p_rng );
+
+/**
+ * \brief           Check a public-private key pair
+ *
+ * \param pub       Keypair structure holding a public key
+ * \param prv       Keypair structure holding a private (plus public) key
+ *
+ * \return          0 if successful (keys are valid and match), or
+ *                  MBEDTLS_ERR_ECP_BAD_INPUT_DATA, or
+ *                  a MBEDTLS_ERR_ECP_XXX or MBEDTLS_ERR_MPI_XXX code.
+ */
+int mbedtls_ecp_check_pub_priv( const mbedtls_ecp_keypair *pub, const mbedtls_ecp_keypair *prv );
+
+#if defined(MBEDTLS_SELF_TEST)
+/**
+ * \brief          Checkup routine
+ *
+ * \return         0 if successful, or 1 if a test failed
+ */
+int mbedtls_ecp_self_test( int verbose );
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ecp.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/entropy.h b/tools/sdk/include/mbedtls/mbedtls/entropy.h
new file mode 100644
index 00000000..fed0494e
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/entropy.h
@@ -0,0 +1,267 @@
+/**
+ * \file entropy.h
+ *
+ * \brief Entropy accumulator implementation
+ *
+ *  Copyright (C) 2006-2016, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_ENTROPY_H
+#define MBEDTLS_ENTROPY_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#include 
+
+#if defined(MBEDTLS_SHA512_C) && !defined(MBEDTLS_ENTROPY_FORCE_SHA256)
+#include "sha512.h"
+#define MBEDTLS_ENTROPY_SHA512_ACCUMULATOR
+#else
+#if defined(MBEDTLS_SHA256_C)
+#define MBEDTLS_ENTROPY_SHA256_ACCUMULATOR
+#include "sha256.h"
+#endif
+#endif
+
+#if defined(MBEDTLS_THREADING_C)
+#include "threading.h"
+#endif
+
+#if defined(MBEDTLS_HAVEGE_C)
+#include "havege.h"
+#endif
+
+#define MBEDTLS_ERR_ENTROPY_SOURCE_FAILED                 -0x003C  /**< Critical entropy source failure. */
+#define MBEDTLS_ERR_ENTROPY_MAX_SOURCES                   -0x003E  /**< No more sources can be added. */
+#define MBEDTLS_ERR_ENTROPY_NO_SOURCES_DEFINED            -0x0040  /**< No sources have been added to poll. */
+#define MBEDTLS_ERR_ENTROPY_NO_STRONG_SOURCE              -0x003D  /**< No strong sources have been added to poll. */
+#define MBEDTLS_ERR_ENTROPY_FILE_IO_ERROR                 -0x003F  /**< Read/write error in file. */
+
+/**
+ * \name SECTION: Module settings
+ *
+ * The configuration options you can set for this module are in this section.
+ * Either change them in config.h or define them on the compiler command line.
+ * \{
+ */
+
+#if !defined(MBEDTLS_ENTROPY_MAX_SOURCES)
+#define MBEDTLS_ENTROPY_MAX_SOURCES     20      /**< Maximum number of sources supported */
+#endif
+
+#if !defined(MBEDTLS_ENTROPY_MAX_GATHER)
+#define MBEDTLS_ENTROPY_MAX_GATHER      128     /**< Maximum amount requested from entropy sources */
+#endif
+
+/* \} name SECTION: Module settings */
+
+#if defined(MBEDTLS_ENTROPY_SHA512_ACCUMULATOR)
+#define MBEDTLS_ENTROPY_BLOCK_SIZE      64      /**< Block size of entropy accumulator (SHA-512) */
+#else
+#define MBEDTLS_ENTROPY_BLOCK_SIZE      32      /**< Block size of entropy accumulator (SHA-256) */
+#endif
+
+#define MBEDTLS_ENTROPY_MAX_SEED_SIZE   1024    /**< Maximum size of seed we read from seed file */
+#define MBEDTLS_ENTROPY_SOURCE_MANUAL   MBEDTLS_ENTROPY_MAX_SOURCES
+
+#define MBEDTLS_ENTROPY_SOURCE_STRONG   1       /**< Entropy source is strong   */
+#define MBEDTLS_ENTROPY_SOURCE_WEAK     0       /**< Entropy source is weak     */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief           Entropy poll callback pointer
+ *
+ * \param data      Callback-specific data pointer
+ * \param output    Data to fill
+ * \param len       Maximum size to provide
+ * \param olen      The actual amount of bytes put into the buffer (Can be 0)
+ *
+ * \return          0 if no critical failures occurred,
+ *                  MBEDTLS_ERR_ENTROPY_SOURCE_FAILED otherwise
+ */
+typedef int (*mbedtls_entropy_f_source_ptr)(void *data, unsigned char *output, size_t len,
+                            size_t *olen);
+
+/**
+ * \brief           Entropy source state
+ */
+typedef struct
+{
+    mbedtls_entropy_f_source_ptr    f_source;   /**< The entropy source callback */
+    void *          p_source;   /**< The callback data pointer */
+    size_t          size;       /**< Amount received in bytes */
+    size_t          threshold;  /**< Minimum bytes required before release */
+    int             strong;     /**< Is the source strong? */
+}
+mbedtls_entropy_source_state;
+
+/**
+ * \brief           Entropy context structure
+ */
+typedef struct
+{
+#if defined(MBEDTLS_ENTROPY_SHA512_ACCUMULATOR)
+    mbedtls_sha512_context  accumulator;
+#else
+    mbedtls_sha256_context  accumulator;
+#endif
+    int             source_count;
+    mbedtls_entropy_source_state    source[MBEDTLS_ENTROPY_MAX_SOURCES];
+#if defined(MBEDTLS_HAVEGE_C)
+    mbedtls_havege_state    havege_data;
+#endif
+#if defined(MBEDTLS_THREADING_C)
+    mbedtls_threading_mutex_t mutex;    /*!< mutex                  */
+#endif
+#if defined(MBEDTLS_ENTROPY_NV_SEED)
+    int initial_entropy_run;
+#endif
+}
+mbedtls_entropy_context;
+
+/**
+ * \brief           Initialize the context
+ *
+ * \param ctx       Entropy context to initialize
+ */
+void mbedtls_entropy_init( mbedtls_entropy_context *ctx );
+
+/**
+ * \brief           Free the data in the context
+ *
+ * \param ctx       Entropy context to free
+ */
+void mbedtls_entropy_free( mbedtls_entropy_context *ctx );
+
+/**
+ * \brief           Adds an entropy source to poll
+ *                  (Thread-safe if MBEDTLS_THREADING_C is enabled)
+ *
+ * \param ctx       Entropy context
+ * \param f_source  Entropy function
+ * \param p_source  Function data
+ * \param threshold Minimum required from source before entropy is released
+ *                  ( with mbedtls_entropy_func() ) (in bytes)
+ * \param strong    MBEDTLS_ENTROPY_SOURCE_STRONG or
+ *                  MBEDTSL_ENTROPY_SOURCE_WEAK.
+ *                  At least one strong source needs to be added.
+ *                  Weaker sources (such as the cycle counter) can be used as
+ *                  a complement.
+ *
+ * \return          0 if successful or MBEDTLS_ERR_ENTROPY_MAX_SOURCES
+ */
+int mbedtls_entropy_add_source( mbedtls_entropy_context *ctx,
+                        mbedtls_entropy_f_source_ptr f_source, void *p_source,
+                        size_t threshold, int strong );
+
+/**
+ * \brief           Trigger an extra gather poll for the accumulator
+ *                  (Thread-safe if MBEDTLS_THREADING_C is enabled)
+ *
+ * \param ctx       Entropy context
+ *
+ * \return          0 if successful, or MBEDTLS_ERR_ENTROPY_SOURCE_FAILED
+ */
+int mbedtls_entropy_gather( mbedtls_entropy_context *ctx );
+
+/**
+ * \brief           Retrieve entropy from the accumulator
+ *                  (Maximum length: MBEDTLS_ENTROPY_BLOCK_SIZE)
+ *                  (Thread-safe if MBEDTLS_THREADING_C is enabled)
+ *
+ * \param data      Entropy context
+ * \param output    Buffer to fill
+ * \param len       Number of bytes desired, must be at most MBEDTLS_ENTROPY_BLOCK_SIZE
+ *
+ * \return          0 if successful, or MBEDTLS_ERR_ENTROPY_SOURCE_FAILED
+ */
+int mbedtls_entropy_func( void *data, unsigned char *output, size_t len );
+
+/**
+ * \brief           Add data to the accumulator manually
+ *                  (Thread-safe if MBEDTLS_THREADING_C is enabled)
+ *
+ * \param ctx       Entropy context
+ * \param data      Data to add
+ * \param len       Length of data
+ *
+ * \return          0 if successful
+ */
+int mbedtls_entropy_update_manual( mbedtls_entropy_context *ctx,
+                           const unsigned char *data, size_t len );
+
+#if defined(MBEDTLS_ENTROPY_NV_SEED)
+/**
+ * \brief           Trigger an update of the seed file in NV by using the
+ *                  current entropy pool.
+ *
+ * \param ctx       Entropy context
+ *
+ * \return          0 if successful
+ */
+int mbedtls_entropy_update_nv_seed( mbedtls_entropy_context *ctx );
+#endif /* MBEDTLS_ENTROPY_NV_SEED */
+
+#if defined(MBEDTLS_FS_IO)
+/**
+ * \brief               Write a seed file
+ *
+ * \param ctx           Entropy context
+ * \param path          Name of the file
+ *
+ * \return              0 if successful,
+ *                      MBEDTLS_ERR_ENTROPY_FILE_IO_ERROR on file error, or
+ *                      MBEDTLS_ERR_ENTROPY_SOURCE_FAILED
+ */
+int mbedtls_entropy_write_seed_file( mbedtls_entropy_context *ctx, const char *path );
+
+/**
+ * \brief               Read and update a seed file. Seed is added to this
+ *                      instance. No more than MBEDTLS_ENTROPY_MAX_SEED_SIZE bytes are
+ *                      read from the seed file. The rest is ignored.
+ *
+ * \param ctx           Entropy context
+ * \param path          Name of the file
+ *
+ * \return              0 if successful,
+ *                      MBEDTLS_ERR_ENTROPY_FILE_IO_ERROR on file error,
+ *                      MBEDTLS_ERR_ENTROPY_SOURCE_FAILED
+ */
+int mbedtls_entropy_update_seed_file( mbedtls_entropy_context *ctx, const char *path );
+#endif /* MBEDTLS_FS_IO */
+
+#if defined(MBEDTLS_SELF_TEST)
+/**
+ * \brief          Checkup routine
+ *
+ * \return         0 if successful, or 1 if a test failed
+ */
+int mbedtls_entropy_self_test( int verbose );
+#endif /* MBEDTLS_SELF_TEST */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* entropy.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/entropy_poll.h b/tools/sdk/include/mbedtls/mbedtls/entropy_poll.h
new file mode 100644
index 00000000..430e8651
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/entropy_poll.h
@@ -0,0 +1,107 @@
+/**
+ * \file entropy_poll.h
+ *
+ * \brief Platform-specific and custom entropy polling functions
+ *
+ *  Copyright (C) 2006-2016, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_ENTROPY_POLL_H
+#define MBEDTLS_ENTROPY_POLL_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Default thresholds for built-in sources, in bytes
+ */
+#define MBEDTLS_ENTROPY_MIN_PLATFORM     32     /**< Minimum for platform source    */
+#define MBEDTLS_ENTROPY_MIN_HAVEGE       32     /**< Minimum for HAVEGE             */
+#define MBEDTLS_ENTROPY_MIN_HARDCLOCK     4     /**< Minimum for mbedtls_timing_hardclock()        */
+#define MBEDTLS_ENTROPY_MIN_HARDWARE     32     /**< Minimum for the hardware source */
+
+/**
+ * \brief           Entropy poll callback that provides 0 entropy.
+ */
+#if defined(MBEDTLS_TEST_NULL_ENTROPY)
+    int mbedtls_null_entropy_poll( void *data,
+                                unsigned char *output, size_t len, size_t *olen );
+#endif
+
+#if !defined(MBEDTLS_NO_PLATFORM_ENTROPY)
+/**
+ * \brief           Platform-specific entropy poll callback
+ */
+int mbedtls_platform_entropy_poll( void *data,
+                           unsigned char *output, size_t len, size_t *olen );
+#endif
+
+#if defined(MBEDTLS_HAVEGE_C)
+/**
+ * \brief           HAVEGE based entropy poll callback
+ *
+ * Requires an HAVEGE state as its data pointer.
+ */
+int mbedtls_havege_poll( void *data,
+                 unsigned char *output, size_t len, size_t *olen );
+#endif
+
+#if defined(MBEDTLS_TIMING_C)
+/**
+ * \brief           mbedtls_timing_hardclock-based entropy poll callback
+ */
+int mbedtls_hardclock_poll( void *data,
+                    unsigned char *output, size_t len, size_t *olen );
+#endif
+
+#if defined(MBEDTLS_ENTROPY_HARDWARE_ALT)
+/**
+ * \brief           Entropy poll callback for a hardware source
+ *
+ * \warning         This is not provided by mbed TLS!
+ *                  See \c MBEDTLS_ENTROPY_HARDWARE_ALT in config.h.
+ *
+ * \note            This must accept NULL as its first argument.
+ */
+int mbedtls_hardware_poll( void *data,
+                           unsigned char *output, size_t len, size_t *olen );
+#endif
+
+#if defined(MBEDTLS_ENTROPY_NV_SEED)
+/**
+ * \brief           Entropy poll callback for a non-volatile seed file
+ *
+ * \note            This must accept NULL as its first argument.
+ */
+int mbedtls_nv_seed_poll( void *data,
+                          unsigned char *output, size_t len, size_t *olen );
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* entropy_poll.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/error.h b/tools/sdk/include/mbedtls/mbedtls/error.h
new file mode 100644
index 00000000..5e549f6b
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/error.h
@@ -0,0 +1,107 @@
+/**
+ * \file error.h
+ *
+ * \brief Error to string translation
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_ERROR_H
+#define MBEDTLS_ERROR_H
+
+#include 
+
+/**
+ * Error code layout.
+ *
+ * Currently we try to keep all error codes within the negative space of 16
+ * bits signed integers to support all platforms (-0x0001 - -0x7FFF). In
+ * addition we'd like to give two layers of information on the error if
+ * possible.
+ *
+ * For that purpose the error codes are segmented in the following manner:
+ *
+ * 16 bit error code bit-segmentation
+ *
+ * 1 bit  - Unused (sign bit)
+ * 3 bits - High level module ID
+ * 5 bits - Module-dependent error code
+ * 7 bits - Low level module errors
+ *
+ * For historical reasons, low-level error codes are divided in even and odd,
+ * even codes were assigned first, and -1 is reserved for other errors.
+ *
+ * Low-level module errors (0x0002-0x007E, 0x0003-0x007F)
+ *
+ * Module   Nr  Codes assigned
+ * MPI       7  0x0002-0x0010
+ * GCM       2  0x0012-0x0014
+ * BLOWFISH  2  0x0016-0x0018
+ * THREADING 3  0x001A-0x001E
+ * AES       2  0x0020-0x0022
+ * CAMELLIA  2  0x0024-0x0026
+ * XTEA      1  0x0028-0x0028
+ * BASE64    2  0x002A-0x002C
+ * OID       1  0x002E-0x002E   0x000B-0x000B
+ * PADLOCK   1  0x0030-0x0030
+ * DES       1  0x0032-0x0032
+ * CTR_DBRG  4  0x0034-0x003A
+ * ENTROPY   3  0x003C-0x0040   0x003D-0x003F
+ * NET      11  0x0042-0x0052   0x0043-0x0045
+ * ASN1      7  0x0060-0x006C
+ * PBKDF2    1  0x007C-0x007C
+ * HMAC_DRBG 4  0x0003-0x0009
+ * CCM       2                  0x000D-0x000F
+ *
+ * High-level module nr (3 bits - 0x0...-0x7...)
+ * Name      ID  Nr of Errors
+ * PEM       1   9
+ * PKCS#12   1   4 (Started from top)
+ * X509      2   19
+ * PKCS5     2   4 (Started from top)
+ * DHM       3   9
+ * PK        3   14 (Started from top)
+ * RSA       4   9
+ * ECP       4   8 (Started from top)
+ * MD        5   4
+ * CIPHER    6   6
+ * SSL       6   17 (Started from top)
+ * SSL       7   31
+ *
+ * Module dependent error code (5 bits 0x.00.-0x.F8.)
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief Translate a mbed TLS error code into a string representation,
+ *        Result is truncated if necessary and always includes a terminating
+ *        null byte.
+ *
+ * \param errnum    error code
+ * \param buffer    buffer to place representation in
+ * \param buflen    length of the buffer
+ */
+void mbedtls_strerror( int errnum, char *buffer, size_t buflen );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* error.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/esp_config.h b/tools/sdk/include/mbedtls/mbedtls/esp_config.h
new file mode 100644
index 00000000..5a69ff78
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/esp_config.h
@@ -0,0 +1,2531 @@
+/**
+ *
+ * \brief Default mbedTLS configuration options for esp-idf
+ *
+ *  This set of compile-time options may be used to enable
+ *  or disable features selectively, and reduce the global
+ *  memory footprint.
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+
+#ifndef MBEDTLS_CONFIG_H
+#define MBEDTLS_CONFIG_H
+
+#include "sdkconfig.h"
+
+#if defined(_MSC_VER) && !defined(_CRT_SECURE_NO_DEPRECATE)
+#define _CRT_SECURE_NO_DEPRECATE 1
+#endif
+
+/**
+ * \name SECTION: System support
+ *
+ * This section sets system specific settings.
+ * \{
+ */
+
+/**
+ * \def MBEDTLS_HAVE_ASM
+ *
+ * The compiler has support for asm().
+ *
+ * Requires support for asm() in compiler.
+ *
+ * Used in:
+ *      library/timing.c
+ *      library/padlock.c
+ *      include/mbedtls/bn_mul.h
+ *
+ * Comment to disable the use of assembly code.
+ */
+#define MBEDTLS_HAVE_ASM
+
+/**
+ * \def MBEDTLS_HAVE_SSE2
+ *
+ * CPU supports SSE2 instruction set.
+ *
+ * Uncomment if the CPU supports SSE2 (IA-32 specific).
+ */
+//#define MBEDTLS_HAVE_SSE2
+
+/**
+ * \def MBEDTLS_HAVE_TIME
+ *
+ * System has time.h and time().
+ * The time does not need to be correct, only time differences are used,
+ * by contrast with MBEDTLS_HAVE_TIME_DATE
+ *
+ * Comment if your system does not support time functions
+ */
+//#define MBEDTLS_HAVE_TIME
+
+/**
+ * \def MBEDTLS_HAVE_TIME_DATE
+ *
+ * System has time.h and time(), gmtime() and the clock is correct.
+ * The time needs to be correct (not necesarily very accurate, but at least
+ * the date should be correct). This is used to verify the validity period of
+ * X.509 certificates.
+ *
+ * Comment if your system does not have a correct clock.
+ */
+//#define MBEDTLS_HAVE_TIME_DATE
+
+/**
+ * \def MBEDTLS_PLATFORM_MEMORY
+ *
+ * Enable the memory allocation layer.
+ *
+ * By default mbed TLS uses the system-provided calloc() and free().
+ * This allows different allocators (self-implemented or provided) to be
+ * provided to the platform abstraction layer.
+ *
+ * Enabling MBEDTLS_PLATFORM_MEMORY without the
+ * MBEDTLS_PLATFORM_{FREE,CALLOC}_MACROs will provide
+ * "mbedtls_platform_set_calloc_free()" allowing you to set an alternative calloc() and
+ * free() function pointer at runtime.
+ *
+ * Enabling MBEDTLS_PLATFORM_MEMORY and specifying
+ * MBEDTLS_PLATFORM_{CALLOC,FREE}_MACROs will allow you to specify the
+ * alternate function at compile time.
+ *
+ * Requires: MBEDTLS_PLATFORM_C
+ *
+ * Enable this layer to allow use of alternative memory allocators.
+ */
+//#define MBEDTLS_PLATFORM_MEMORY
+
+/**
+ * \def MBEDTLS_PLATFORM_NO_STD_FUNCTIONS
+ *
+ * Do not assign standard functions in the platform layer (e.g. calloc() to
+ * MBEDTLS_PLATFORM_STD_CALLOC and printf() to MBEDTLS_PLATFORM_STD_PRINTF)
+ *
+ * This makes sure there are no linking errors on platforms that do not support
+ * these functions. You will HAVE to provide alternatives, either at runtime
+ * via the platform_set_xxx() functions or at compile time by setting
+ * the MBEDTLS_PLATFORM_STD_XXX defines, or enabling a
+ * MBEDTLS_PLATFORM_XXX_MACRO.
+ *
+ * Requires: MBEDTLS_PLATFORM_C
+ *
+ * Uncomment to prevent default assignment of standard functions in the
+ * platform layer.
+ */
+//#define MBEDTLS_PLATFORM_NO_STD_FUNCTIONS
+
+/**
+ * \def MBEDTLS_PLATFORM_EXIT_ALT
+ *
+ * MBEDTLS_PLATFORM_XXX_ALT: Uncomment a macro to let mbed TLS support the
+ * function in the platform abstraction layer.
+ *
+ * Example: In case you uncomment MBEDTLS_PLATFORM_PRINTF_ALT, mbed TLS will
+ * provide a function "mbedtls_platform_set_printf()" that allows you to set an
+ * alternative printf function pointer.
+ *
+ * All these define require MBEDTLS_PLATFORM_C to be defined!
+ *
+ * \note MBEDTLS_PLATFORM_SNPRINTF_ALT is required on Windows;
+ * it will be enabled automatically by check_config.h
+ *
+ * \warning MBEDTLS_PLATFORM_XXX_ALT cannot be defined at the same time as
+ * MBEDTLS_PLATFORM_XXX_MACRO!
+ *
+ * Uncomment a macro to enable alternate implementation of specific base
+ * platform function
+ */
+//#define MBEDTLS_PLATFORM_EXIT_ALT
+//#define MBEDTLS_PLATFORM_FPRINTF_ALT
+//#define MBEDTLS_PLATFORM_PRINTF_ALT
+//#define MBEDTLS_PLATFORM_SNPRINTF_ALT
+
+/**
+ * \def MBEDTLS_DEPRECATED_WARNING
+ *
+ * Mark deprecated functions so that they generate a warning if used.
+ * Functions deprecated in one version will usually be removed in the next
+ * version. You can enable this to help you prepare the transition to a new
+ * major version by making sure your code is not using these functions.
+ *
+ * This only works with GCC and Clang. With other compilers, you may want to
+ * use MBEDTLS_DEPRECATED_REMOVED
+ *
+ * Uncomment to get warnings on using deprecated functions.
+ */
+//#define MBEDTLS_DEPRECATED_WARNING
+
+/**
+ * \def MBEDTLS_DEPRECATED_REMOVED
+ *
+ * Remove deprecated functions so that they generate an error if used.
+ * Functions deprecated in one version will usually be removed in the next
+ * version. You can enable this to help you prepare the transition to a new
+ * major version by making sure your code is not using these functions.
+ *
+ * Uncomment to get errors on using deprecated functions.
+ */
+//#define MBEDTLS_DEPRECATED_REMOVED
+
+/* \} name SECTION: System support */
+
+/**
+ * \name SECTION: mbed TLS feature support
+ *
+ * This section sets support for features that are or are not needed
+ * within the modules that are enabled.
+ * \{
+ */
+
+/**
+ * \def MBEDTLS_TIMING_ALT
+ *
+ * Uncomment to provide your own alternate implementation for mbedtls_timing_hardclock(),
+ * mbedtls_timing_get_timer(), mbedtls_set_alarm(), mbedtls_set/get_delay()
+ *
+ * Only works if you have MBEDTLS_TIMING_C enabled.
+ *
+ * You will need to provide a header "timing_alt.h" and an implementation at
+ * compile time.
+ */
+//#define MBEDTLS_TIMING_ALT
+
+/**
+ * \def MBEDTLS_AES_ALT
+ *
+ * MBEDTLS__MODULE_NAME__ALT: Uncomment a macro to let mbed TLS use your
+ * alternate core implementation of a symmetric crypto or hash module (e.g.
+ * platform specific assembly optimized implementations). Keep in mind that
+ * the function prototypes should remain the same.
+ *
+ * This replaces the whole module. If you only want to replace one of the
+ * functions, use one of the MBEDTLS__FUNCTION_NAME__ALT flags.
+ *
+ * Example: In case you uncomment MBEDTLS_AES_ALT, mbed TLS will no longer
+ * provide the "struct mbedtls_aes_context" definition and omit the base function
+ * declarations and implementations. "aes_alt.h" will be included from
+ * "aes.h" to include the new function definitions.
+ *
+ * Uncomment a macro to enable alternate implementation of the corresponding
+ * module.
+ */
+//#define MBEDTLS_ARC4_ALT
+//#define MBEDTLS_BLOWFISH_ALT
+//#define MBEDTLS_CAMELLIA_ALT
+//#define MBEDTLS_DES_ALT
+//#define MBEDTLS_XTEA_ALT
+//#define MBEDTLS_MD2_ALT
+//#define MBEDTLS_MD4_ALT
+//#define MBEDTLS_MD5_ALT
+//#define MBEDTLS_RIPEMD160_ALT
+
+/* The following units have ESP32 hardware support,
+   uncommenting each _ALT macro will use the
+   hardware-accelerated implementation. */
+#define MBEDTLS_AES_ALT
+
+/* Currently hardware SHA does not work with TLS handshake,
+   due to concurrency issue. Internal TW#7111. */
+//#define MBEDTLS_SHA1_ALT
+//#define MBEDTLS_SHA256_ALT
+//#define MBEDTLS_SHA512_ALT
+
+/* The following MPI (bignum) functions have ESP32 hardware support,
+   Uncommenting these macros will use the hardware-accelerated
+   implementations.
+
+   Disabled as number of limbs limited by bug. Internal TW#7112.
+*/
+//#define MBEDTLS_MPI_EXP_MOD_ALT
+//#define MBEDTLS_MPI_MUL_MPI_ALT
+
+/**
+ * \def MBEDTLS_MD2_PROCESS_ALT
+ *
+ * MBEDTLS__FUNCTION_NAME__ALT: Uncomment a macro to let mbed TLS use you
+ * alternate core implementation of symmetric crypto or hash function. Keep in
+ * mind that function prototypes should remain the same.
+ *
+ * This replaces only one function. The header file from mbed TLS is still
+ * used, in contrast to the MBEDTLS__MODULE_NAME__ALT flags.
+ *
+ * Example: In case you uncomment MBEDTLS_SHA256_PROCESS_ALT, mbed TLS will
+ * no longer provide the mbedtls_sha1_process() function, but it will still provide
+ * the other function (using your mbedtls_sha1_process() function) and the definition
+ * of mbedtls_sha1_context, so your implementation of mbedtls_sha1_process must be compatible
+ * with this definition.
+ *
+ * Note: if you use the AES_xxx_ALT macros, then is is recommended to also set
+ * MBEDTLS_AES_ROM_TABLES in order to help the linker garbage-collect the AES
+ * tables.
+ *
+ * Uncomment a macro to enable alternate implementation of the corresponding
+ * function.
+ */
+//#define MBEDTLS_MD2_PROCESS_ALT
+//#define MBEDTLS_MD4_PROCESS_ALT
+//#define MBEDTLS_MD5_PROCESS_ALT
+//#define MBEDTLS_RIPEMD160_PROCESS_ALT
+//#define MBEDTLS_SHA1_PROCESS_ALT
+//#define MBEDTLS_SHA256_PROCESS_ALT
+//#define MBEDTLS_SHA512_PROCESS_ALT
+//#define MBEDTLS_DES_SETKEY_ALT
+//#define MBEDTLS_DES_CRYPT_ECB_ALT
+//#define MBEDTLS_DES3_CRYPT_ECB_ALT
+//#define MBEDTLS_AES_SETKEY_ENC_ALT
+//#define MBEDTLS_AES_SETKEY_DEC_ALT
+//#define MBEDTLS_AES_ENCRYPT_ALT
+//#define MBEDTLS_AES_DECRYPT_ALT
+
+/**
+ * \def MBEDTLS_ENTROPY_HARDWARE_ALT
+ *
+ * Uncomment this macro to let mbed TLS use your own implementation of a
+ * hardware entropy collector.
+ *
+ * Your function must be called \c mbedtls_hardware_poll(), have the same
+ * prototype as declared in entropy_poll.h, and accept NULL as first argument.
+ *
+ * Uncomment to use your own hardware entropy collector.
+ */
+#define MBEDTLS_ENTROPY_HARDWARE_ALT
+
+/**
+ * \def MBEDTLS_AES_ROM_TABLES
+ *
+ * Store the AES tables in ROM.
+ *
+ * Uncomment this macro to store the AES tables in ROM.
+ */
+#define MBEDTLS_AES_ROM_TABLES
+
+/**
+ * \def MBEDTLS_CAMELLIA_SMALL_MEMORY
+ *
+ * Use less ROM for the Camellia implementation (saves about 768 bytes).
+ *
+ * Uncomment this macro to use less memory for Camellia.
+ */
+//#define MBEDTLS_CAMELLIA_SMALL_MEMORY
+
+/**
+ * \def MBEDTLS_CIPHER_MODE_CBC
+ *
+ * Enable Cipher Block Chaining mode (CBC) for symmetric ciphers.
+ */
+#define MBEDTLS_CIPHER_MODE_CBC
+
+/**
+ * \def MBEDTLS_CIPHER_MODE_CFB
+ *
+ * Enable Cipher Feedback mode (CFB) for symmetric ciphers.
+ */
+#define MBEDTLS_CIPHER_MODE_CFB
+
+/**
+ * \def MBEDTLS_CIPHER_MODE_CTR
+ *
+ * Enable Counter Block Cipher mode (CTR) for symmetric ciphers.
+ */
+#define MBEDTLS_CIPHER_MODE_CTR
+
+/**
+ * \def MBEDTLS_CIPHER_NULL_CIPHER
+ *
+ * Enable NULL cipher.
+ * Warning: Only do so when you know what you are doing. This allows for
+ * encryption or channels without any security!
+ *
+ * Requires MBEDTLS_ENABLE_WEAK_CIPHERSUITES as well to enable
+ * the following ciphersuites:
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_NULL_SHA
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_NULL_SHA
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_NULL_SHA
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_NULL_SHA
+ *      MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA384
+ *      MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA256
+ *      MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA
+ *      MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA384
+ *      MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA256
+ *      MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA
+ *      MBEDTLS_TLS_RSA_WITH_NULL_SHA256
+ *      MBEDTLS_TLS_RSA_WITH_NULL_SHA
+ *      MBEDTLS_TLS_RSA_WITH_NULL_MD5
+ *      MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA384
+ *      MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA256
+ *      MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA
+ *      MBEDTLS_TLS_PSK_WITH_NULL_SHA384
+ *      MBEDTLS_TLS_PSK_WITH_NULL_SHA256
+ *      MBEDTLS_TLS_PSK_WITH_NULL_SHA
+ *
+ * Uncomment this macro to enable the NULL cipher and ciphersuites
+ */
+//#define MBEDTLS_CIPHER_NULL_CIPHER
+
+/**
+ * \def MBEDTLS_CIPHER_PADDING_PKCS7
+ *
+ * MBEDTLS_CIPHER_PADDING_XXX: Uncomment or comment macros to add support for
+ * specific padding modes in the cipher layer with cipher modes that support
+ * padding (e.g. CBC)
+ *
+ * If you disable all padding modes, only full blocks can be used with CBC.
+ *
+ * Enable padding modes in the cipher layer.
+ */
+#define MBEDTLS_CIPHER_PADDING_PKCS7
+#define MBEDTLS_CIPHER_PADDING_ONE_AND_ZEROS
+#define MBEDTLS_CIPHER_PADDING_ZEROS_AND_LEN
+#define MBEDTLS_CIPHER_PADDING_ZEROS
+
+/**
+ * \def MBEDTLS_ENABLE_WEAK_CIPHERSUITES
+ *
+ * Enable weak ciphersuites in SSL / TLS.
+ * Warning: Only do so when you know what you are doing. This allows for
+ * channels with virtually no security at all!
+ *
+ * This enables the following ciphersuites:
+ *      MBEDTLS_TLS_RSA_WITH_DES_CBC_SHA
+ *      MBEDTLS_TLS_DHE_RSA_WITH_DES_CBC_SHA
+ *
+ * Uncomment this macro to enable weak ciphersuites
+ */
+//#define MBEDTLS_ENABLE_WEAK_CIPHERSUITES
+
+/**
+ * \def MBEDTLS_REMOVE_ARC4_CIPHERSUITES
+ *
+ * Remove RC4 ciphersuites by default in SSL / TLS.
+ * This flag removes the ciphersuites based on RC4 from the default list as
+ * returned by mbedtls_ssl_list_ciphersuites(). However, it is still possible to
+ * enable (some of) them with mbedtls_ssl_conf_ciphersuites() by including them
+ * explicitly.
+ *
+ * Uncomment this macro to remove RC4 ciphersuites by default.
+ */
+#define MBEDTLS_REMOVE_ARC4_CIPHERSUITES
+
+/**
+ * \def MBEDTLS_ECP_DP_SECP192R1_ENABLED
+ *
+ * MBEDTLS_ECP_XXXX_ENABLED: Enables specific curves within the Elliptic Curve
+ * module.  By default all supported curves are enabled.
+ *
+ * Comment macros to disable the curve and functions for it
+ */
+#define MBEDTLS_ECP_DP_SECP192R1_ENABLED
+#define MBEDTLS_ECP_DP_SECP224R1_ENABLED
+#define MBEDTLS_ECP_DP_SECP256R1_ENABLED
+#define MBEDTLS_ECP_DP_SECP384R1_ENABLED
+#define MBEDTLS_ECP_DP_SECP521R1_ENABLED
+#define MBEDTLS_ECP_DP_SECP192K1_ENABLED
+#define MBEDTLS_ECP_DP_SECP224K1_ENABLED
+#define MBEDTLS_ECP_DP_SECP256K1_ENABLED
+#define MBEDTLS_ECP_DP_BP256R1_ENABLED
+#define MBEDTLS_ECP_DP_BP384R1_ENABLED
+#define MBEDTLS_ECP_DP_BP512R1_ENABLED
+#define MBEDTLS_ECP_DP_CURVE25519_ENABLED
+
+/**
+ * \def MBEDTLS_ECP_NIST_OPTIM
+ *
+ * Enable specific 'modulo p' routines for each NIST prime.
+ * Depending on the prime and architecture, makes operations 4 to 8 times
+ * faster on the corresponding curve.
+ *
+ * Comment this macro to disable NIST curves optimisation.
+ */
+#define MBEDTLS_ECP_NIST_OPTIM
+
+/**
+ * \def MBEDTLS_ECDSA_DETERMINISTIC
+ *
+ * Enable deterministic ECDSA (RFC 6979).
+ * Standard ECDSA is "fragile" in the sense that lack of entropy when signing
+ * may result in a compromise of the long-term signing key. This is avoided by
+ * the deterministic variant.
+ *
+ * Requires: MBEDTLS_HMAC_DRBG_C
+ *
+ * Comment this macro to disable deterministic ECDSA.
+ */
+#define MBEDTLS_ECDSA_DETERMINISTIC
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_PSK_ENABLED
+ *
+ * Enable the PSK based ciphersuite modes in SSL / TLS.
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ *      MBEDTLS_TLS_PSK_WITH_AES_256_GCM_SHA384
+ *      MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA384
+ *      MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA
+ *      MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_GCM_SHA384
+ *      MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_CBC_SHA384
+ *      MBEDTLS_TLS_PSK_WITH_AES_128_GCM_SHA256
+ *      MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA256
+ *      MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA
+ *      MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_GCM_SHA256
+ *      MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256
+ *      MBEDTLS_TLS_PSK_WITH_3DES_EDE_CBC_SHA
+ *      MBEDTLS_TLS_PSK_WITH_RC4_128_SHA
+ */
+#define MBEDTLS_KEY_EXCHANGE_PSK_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED
+ *
+ * Enable the DHE-PSK based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_DHM_C
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ *      MBEDTLS_TLS_DHE_PSK_WITH_AES_256_GCM_SHA384
+ *      MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA384
+ *      MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA
+ *      MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_GCM_SHA384
+ *      MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_CBC_SHA384
+ *      MBEDTLS_TLS_DHE_PSK_WITH_AES_128_GCM_SHA256
+ *      MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA256
+ *      MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA
+ *      MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_GCM_SHA256
+ *      MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_CBC_SHA256
+ *      MBEDTLS_TLS_DHE_PSK_WITH_3DES_EDE_CBC_SHA
+ *      MBEDTLS_TLS_DHE_PSK_WITH_RC4_128_SHA
+ */
+#define MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED
+ *
+ * Enable the ECDHE-PSK based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_ECDH_C
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ *      MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA384
+ *      MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA
+ *      MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_256_CBC_SHA384
+ *      MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA256
+ *      MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA
+ *      MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_128_CBC_SHA256
+ *      MBEDTLS_TLS_ECDHE_PSK_WITH_3DES_EDE_CBC_SHA
+ *      MBEDTLS_TLS_ECDHE_PSK_WITH_RC4_128_SHA
+ */
+#define MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED
+ *
+ * Enable the RSA-PSK based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15,
+ *           MBEDTLS_X509_CRT_PARSE_C
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ *      MBEDTLS_TLS_RSA_PSK_WITH_AES_256_GCM_SHA384
+ *      MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA384
+ *      MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA
+ *      MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_GCM_SHA384
+ *      MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_CBC_SHA384
+ *      MBEDTLS_TLS_RSA_PSK_WITH_AES_128_GCM_SHA256
+ *      MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA256
+ *      MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA
+ *      MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_GCM_SHA256
+ *      MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_CBC_SHA256
+ *      MBEDTLS_TLS_RSA_PSK_WITH_3DES_EDE_CBC_SHA
+ *      MBEDTLS_TLS_RSA_PSK_WITH_RC4_128_SHA
+ */
+#define MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_RSA_ENABLED
+ *
+ * Enable the RSA-only based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15,
+ *           MBEDTLS_X509_CRT_PARSE_C
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ *      MBEDTLS_TLS_RSA_WITH_AES_256_GCM_SHA384
+ *      MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA256
+ *      MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA
+ *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_GCM_SHA384
+ *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256
+ *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA
+ *      MBEDTLS_TLS_RSA_WITH_AES_128_GCM_SHA256
+ *      MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA256
+ *      MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA
+ *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_GCM_SHA256
+ *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256
+ *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA
+ *      MBEDTLS_TLS_RSA_WITH_3DES_EDE_CBC_SHA
+ *      MBEDTLS_TLS_RSA_WITH_RC4_128_SHA
+ *      MBEDTLS_TLS_RSA_WITH_RC4_128_MD5
+ */
+#define MBEDTLS_KEY_EXCHANGE_RSA_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED
+ *
+ * Enable the DHE-RSA based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_DHM_C, MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15,
+ *           MBEDTLS_X509_CRT_PARSE_C
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ *      MBEDTLS_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384
+ *      MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA256
+ *      MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA
+ *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_GCM_SHA384
+ *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256
+ *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA
+ *      MBEDTLS_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256
+ *      MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA256
+ *      MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA
+ *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_GCM_SHA256
+ *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256
+ *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA
+ *      MBEDTLS_TLS_DHE_RSA_WITH_3DES_EDE_CBC_SHA
+ */
+#define MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED
+ *
+ * Enable the ECDHE-RSA based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_ECDH_C, MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15,
+ *           MBEDTLS_X509_CRT_PARSE_C
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_GCM_SHA384
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_CBC_SHA384
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_GCM_SHA256
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_CBC_SHA256
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_RC4_128_SHA
+ */
+#define MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED
+ *
+ * Enable the ECDHE-ECDSA based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_ECDH_C, MBEDTLS_ECDSA_C, MBEDTLS_X509_CRT_PARSE_C,
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_GCM_SHA384
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_CBC_SHA384
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_GCM_SHA256
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_CBC_SHA256
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_RC4_128_SHA
+ */
+#define MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED
+ *
+ * Enable the ECDH-ECDSA based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_ECDH_C, MBEDTLS_X509_CRT_PARSE_C
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_RC4_128_SHA
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_3DES_EDE_CBC_SHA
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_CBC_SHA256
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_CBC_SHA384
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_GCM_SHA256
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_GCM_SHA384
+ */
+#define MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED
+ *
+ * Enable the ECDH-RSA based ciphersuite modes in SSL / TLS.
+ *
+ * Requires: MBEDTLS_ECDH_C, MBEDTLS_X509_CRT_PARSE_C
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_RC4_128_SHA
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_3DES_EDE_CBC_SHA
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_CBC_SHA256
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_CBC_SHA384
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_GCM_SHA256
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_GCM_SHA384
+ */
+#define MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED
+
+/**
+ * \def MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED
+ *
+ * Enable the ECJPAKE based ciphersuite modes in SSL / TLS.
+ *
+ * \warning This is currently experimental. EC J-PAKE support is based on the
+ * Thread v1.0.0 specification; incompatible changes to the specification
+ * might still happen. For this reason, this is disabled by default.
+ *
+ * Requires: MBEDTLS_ECJPAKE_C
+ *           MBEDTLS_SHA256_C
+ *           MBEDTLS_ECP_DP_SECP256R1_ENABLED
+ *
+ * This enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ *      MBEDTLS_TLS_ECJPAKE_WITH_AES_128_CCM_8
+ */
+//#define MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED
+
+/**
+ * \def MBEDTLS_PK_PARSE_EC_EXTENDED
+ *
+ * Enhance support for reading EC keys using variants of SEC1 not allowed by
+ * RFC 5915 and RFC 5480.
+ *
+ * Currently this means parsing the SpecifiedECDomain choice of EC
+ * parameters (only known groups are supported, not arbitrary domains, to
+ * avoid validation issues).
+ *
+ * Disable if you only need to support RFC 5915 + 5480 key formats.
+ */
+#define MBEDTLS_PK_PARSE_EC_EXTENDED
+
+/**
+ * \def MBEDTLS_ERROR_STRERROR_DUMMY
+ *
+ * Enable a dummy error function to make use of mbedtls_strerror() in
+ * third party libraries easier when MBEDTLS_ERROR_C is disabled
+ * (no effect when MBEDTLS_ERROR_C is enabled).
+ *
+ * You can safely disable this if MBEDTLS_ERROR_C is enabled, or if you're
+ * not using mbedtls_strerror() or error_strerror() in your application.
+ *
+ * Disable if you run into name conflicts and want to really remove the
+ * mbedtls_strerror()
+ */
+#define MBEDTLS_ERROR_STRERROR_DUMMY
+
+/**
+ * \def MBEDTLS_GENPRIME
+ *
+ * Enable the prime-number generation code.
+ *
+ * Requires: MBEDTLS_BIGNUM_C
+ */
+#define MBEDTLS_GENPRIME
+
+/**
+ * \def MBEDTLS_FS_IO
+ *
+ * Enable functions that use the filesystem.
+ */
+//#define MBEDTLS_FS_IO
+
+/**
+ * \def MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES
+ *
+ * Do not add default entropy sources. These are the platform specific,
+ * mbedtls_timing_hardclock and HAVEGE based poll functions.
+ *
+ * This is useful to have more control over the added entropy sources in an
+ * application.
+ *
+ * Uncomment this macro to prevent loading of default entropy functions.
+ */
+//#define MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES
+
+/**
+ * \def MBEDTLS_NO_PLATFORM_ENTROPY
+ *
+ * Do not use built-in platform entropy functions.
+ * This is useful if your platform does not support
+ * standards like the /dev/urandom or Windows CryptoAPI.
+ *
+ * Uncomment this macro to disable the built-in platform entropy functions.
+ */
+#define MBEDTLS_NO_PLATFORM_ENTROPY
+
+/**
+ * \def MBEDTLS_ENTROPY_FORCE_SHA256
+ *
+ * Force the entropy accumulator to use a SHA-256 accumulator instead of the
+ * default SHA-512 based one (if both are available).
+ *
+ * Requires: MBEDTLS_SHA256_C
+ *
+ * On 32-bit systems SHA-256 can be much faster than SHA-512. Use this option
+ * if you have performance concerns.
+ *
+ * This option is only useful if both MBEDTLS_SHA256_C and
+ * MBEDTLS_SHA512_C are defined. Otherwise the available hash module is used.
+ */
+//#define MBEDTLS_ENTROPY_FORCE_SHA256
+
+/**
+ * \def MBEDTLS_MEMORY_DEBUG
+ *
+ * Enable debugging of buffer allocator memory issues. Automatically prints
+ * (to stderr) all (fatal) messages on memory allocation issues. Enables
+ * function for 'debug output' of allocated memory.
+ *
+ * Requires: MBEDTLS_MEMORY_BUFFER_ALLOC_C
+ *
+ * Uncomment this macro to let the buffer allocator print out error messages.
+ */
+//#define MBEDTLS_MEMORY_DEBUG
+
+/**
+ * \def MBEDTLS_MEMORY_BACKTRACE
+ *
+ * Include backtrace information with each allocated block.
+ *
+ * Requires: MBEDTLS_MEMORY_BUFFER_ALLOC_C
+ *           GLIBC-compatible backtrace() an backtrace_symbols() support
+ *
+ * Uncomment this macro to include backtrace information
+ */
+//#define MBEDTLS_MEMORY_BACKTRACE
+
+/**
+ * \def MBEDTLS_PK_RSA_ALT_SUPPORT
+ *
+ * Support external private RSA keys (eg from a HSM) in the PK layer.
+ *
+ * Comment this macro to disable support for external private RSA keys.
+ */
+#define MBEDTLS_PK_RSA_ALT_SUPPORT
+
+/**
+ * \def MBEDTLS_PKCS1_V15
+ *
+ * Enable support for PKCS#1 v1.5 encoding.
+ *
+ * Requires: MBEDTLS_RSA_C
+ *
+ * This enables support for PKCS#1 v1.5 operations.
+ */
+#define MBEDTLS_PKCS1_V15
+
+/**
+ * \def MBEDTLS_PKCS1_V21
+ *
+ * Enable support for PKCS#1 v2.1 encoding.
+ *
+ * Requires: MBEDTLS_MD_C, MBEDTLS_RSA_C
+ *
+ * This enables support for RSAES-OAEP and RSASSA-PSS operations.
+ */
+#define MBEDTLS_PKCS1_V21
+
+/**
+ * \def MBEDTLS_RSA_NO_CRT
+ *
+ * Do not use the Chinese Remainder Theorem for the RSA private operation.
+ *
+ * Uncomment this macro to disable the use of CRT in RSA.
+ *
+ */
+//#define MBEDTLS_RSA_NO_CRT
+
+/**
+ * \def MBEDTLS_SELF_TEST
+ *
+ * Enable the checkup functions (*_self_test).
+ */
+#define MBEDTLS_SELF_TEST
+
+/**
+ * \def MBEDTLS_SHA256_SMALLER
+ *
+ * Enable an implementation of SHA-256 that has lower ROM footprint but also
+ * lower performance.
+ *
+ * The default implementation is meant to be a reasonnable compromise between
+ * performance and size. This version optimizes more aggressively for size at
+ * the expense of performance. Eg on Cortex-M4 it reduces the size of
+ * mbedtls_sha256_process() from ~2KB to ~0.5KB for a performance hit of about
+ * 30%.
+ *
+ * Uncomment to enable the smaller implementation of SHA256.
+ */
+//#define MBEDTLS_SHA256_SMALLER
+
+/**
+ * \def MBEDTLS_SSL_AEAD_RANDOM_IV
+ *
+ * Generate a random IV rather than using the record sequence number as a
+ * nonce for ciphersuites using and AEAD algorithm (GCM or CCM).
+ *
+ * Using the sequence number is generally recommended.
+ *
+ * Uncomment this macro to always use random IVs with AEAD ciphersuites.
+ */
+//#define MBEDTLS_SSL_AEAD_RANDOM_IV
+
+/**
+ * \def MBEDTLS_SSL_ALL_ALERT_MESSAGES
+ *
+ * Enable sending of alert messages in case of encountered errors as per RFC.
+ * If you choose not to send the alert messages, mbed TLS can still communicate
+ * with other servers, only debugging of failures is harder.
+ *
+ * The advantage of not sending alert messages, is that no information is given
+ * about reasons for failures thus preventing adversaries of gaining intel.
+ *
+ * Enable sending of all alert messages
+ */
+#define MBEDTLS_SSL_ALL_ALERT_MESSAGES
+
+/**
+ * \def MBEDTLS_SSL_DEBUG_ALL
+ *
+ * Enable the debug messages in SSL module for all issues.
+ * Debug messages have been disabled in some places to prevent timing
+ * attacks due to (unbalanced) debugging function calls.
+ *
+ * If you need all error reporting you should enable this during debugging,
+ * but remove this for production servers that should log as well.
+ *
+ * Uncomment this macro to report all debug messages on errors introducing
+ * a timing side-channel.
+ *
+ */
+//#define MBEDTLS_SSL_DEBUG_ALL
+
+/** \def MBEDTLS_SSL_ENCRYPT_THEN_MAC
+ *
+ * Enable support for Encrypt-then-MAC, RFC 7366.
+ *
+ * This allows peers that both support it to use a more robust protection for
+ * ciphersuites using CBC, providing deep resistance against timing attacks
+ * on the padding or underlying cipher.
+ *
+ * This only affects CBC ciphersuites, and is useless if none is defined.
+ *
+ * Requires: MBEDTLS_SSL_PROTO_TLS1    or
+ *           MBEDTLS_SSL_PROTO_TLS1_1  or
+ *           MBEDTLS_SSL_PROTO_TLS1_2
+ *
+ * Comment this macro to disable support for Encrypt-then-MAC
+ */
+#define MBEDTLS_SSL_ENCRYPT_THEN_MAC
+
+/** \def MBEDTLS_SSL_EXTENDED_MASTER_SECRET
+ *
+ * Enable support for Extended Master Secret, aka Session Hash
+ * (draft-ietf-tls-session-hash-02).
+ *
+ * This was introduced as "the proper fix" to the Triple Handshake familiy of
+ * attacks, but it is recommended to always use it (even if you disable
+ * renegotiation), since it actually fixes a more fundamental issue in the
+ * original SSL/TLS design, and has implications beyond Triple Handshake.
+ *
+ * Requires: MBEDTLS_SSL_PROTO_TLS1    or
+ *           MBEDTLS_SSL_PROTO_TLS1_1  or
+ *           MBEDTLS_SSL_PROTO_TLS1_2
+ *
+ * Comment this macro to disable support for Extended Master Secret.
+ */
+#define MBEDTLS_SSL_EXTENDED_MASTER_SECRET
+
+/**
+ * \def MBEDTLS_SSL_FALLBACK_SCSV
+ *
+ * Enable support for FALLBACK_SCSV (draft-ietf-tls-downgrade-scsv-00).
+ *
+ * For servers, it is recommended to always enable this, unless you support
+ * only one version of TLS, or know for sure that none of your clients
+ * implements a fallback strategy.
+ *
+ * For clients, you only need this if you're using a fallback strategy, which
+ * is not recommended in the first place, unless you absolutely need it to
+ * interoperate with buggy (version-intolerant) servers.
+ *
+ * Comment this macro to disable support for FALLBACK_SCSV
+ */
+#define MBEDTLS_SSL_FALLBACK_SCSV
+
+/**
+ * \def MBEDTLS_SSL_HW_RECORD_ACCEL
+ *
+ * Enable hooking functions in SSL module for hardware acceleration of
+ * individual records.
+ *
+ * Uncomment this macro to enable hooking functions.
+ */
+//#define MBEDTLS_SSL_HW_RECORD_ACCEL
+
+/**
+ * \def MBEDTLS_SSL_CBC_RECORD_SPLITTING
+ *
+ * Enable 1/n-1 record splitting for CBC mode in SSLv3 and TLS 1.0.
+ *
+ * This is a countermeasure to the BEAST attack, which also minimizes the risk
+ * of interoperability issues compared to sending 0-length records.
+ *
+ * Comment this macro to disable 1/n-1 record splitting.
+ */
+#define MBEDTLS_SSL_CBC_RECORD_SPLITTING
+
+/**
+ * \def MBEDTLS_SSL_RENEGOTIATION
+ *
+ * Disable support for TLS renegotiation.
+ *
+ * The two main uses of renegotiation are (1) refresh keys on long-lived
+ * connections and (2) client authentication after the initial handshake.
+ * If you don't need renegotiation, it's probably better to disable it, since
+ * it has been associated with security issues in the past and is easy to
+ * misuse/misunderstand.
+ *
+ * Comment this to disable support for renegotiation.
+ */
+#define MBEDTLS_SSL_RENEGOTIATION
+
+/**
+ * \def MBEDTLS_SSL_SRV_SUPPORT_SSLV2_CLIENT_HELLO
+ *
+ * Enable support for receiving and parsing SSLv2 Client Hello messages for the
+ * SSL Server module (MBEDTLS_SSL_SRV_C).
+ *
+ * Uncomment this macro to enable support for SSLv2 Client Hello messages.
+ */
+//#define MBEDTLS_SSL_SRV_SUPPORT_SSLV2_CLIENT_HELLO
+
+/**
+ * \def MBEDTLS_SSL_SRV_RESPECT_CLIENT_PREFERENCE
+ *
+ * Pick the ciphersuite according to the client's preferences rather than ours
+ * in the SSL Server module (MBEDTLS_SSL_SRV_C).
+ *
+ * Uncomment this macro to respect client's ciphersuite order
+ */
+//#define MBEDTLS_SSL_SRV_RESPECT_CLIENT_PREFERENCE
+
+/**
+ * \def MBEDTLS_SSL_MAX_FRAGMENT_LENGTH
+ *
+ * Enable support for RFC 6066 max_fragment_length extension in SSL.
+ *
+ * Comment this macro to disable support for the max_fragment_length extension
+ */
+#define MBEDTLS_SSL_MAX_FRAGMENT_LENGTH
+
+/**
+ * \def MBEDTLS_SSL_PROTO_SSL3
+ *
+ * Enable support for SSL 3.0.
+ *
+ * Requires: MBEDTLS_MD5_C
+ *           MBEDTLS_SHA1_C
+ *
+ * Comment this macro to disable support for SSL 3.0
+ */
+#define MBEDTLS_SSL_PROTO_SSL3
+
+/**
+ * \def MBEDTLS_SSL_PROTO_TLS1
+ *
+ * Enable support for TLS 1.0.
+ *
+ * Requires: MBEDTLS_MD5_C
+ *           MBEDTLS_SHA1_C
+ *
+ * Comment this macro to disable support for TLS 1.0
+ */
+#define MBEDTLS_SSL_PROTO_TLS1
+
+/**
+ * \def MBEDTLS_SSL_PROTO_TLS1_1
+ *
+ * Enable support for TLS 1.1 (and DTLS 1.0 if DTLS is enabled).
+ *
+ * Requires: MBEDTLS_MD5_C
+ *           MBEDTLS_SHA1_C
+ *
+ * Comment this macro to disable support for TLS 1.1 / DTLS 1.0
+ */
+#define MBEDTLS_SSL_PROTO_TLS1_1
+
+/**
+ * \def MBEDTLS_SSL_PROTO_TLS1_2
+ *
+ * Enable support for TLS 1.2 (and DTLS 1.2 if DTLS is enabled).
+ *
+ * Requires: MBEDTLS_SHA1_C or MBEDTLS_SHA256_C or MBEDTLS_SHA512_C
+ *           (Depends on ciphersuites)
+ *
+ * Comment this macro to disable support for TLS 1.2 / DTLS 1.2
+ */
+#define MBEDTLS_SSL_PROTO_TLS1_2
+
+/**
+ * \def MBEDTLS_SSL_PROTO_DTLS
+ *
+ * Enable support for DTLS (all available versions).
+ *
+ * Enable this and MBEDTLS_SSL_PROTO_TLS1_1 to enable DTLS 1.0,
+ * and/or this and MBEDTLS_SSL_PROTO_TLS1_2 to enable DTLS 1.2.
+ *
+ * Requires: MBEDTLS_SSL_PROTO_TLS1_1
+ *        or MBEDTLS_SSL_PROTO_TLS1_2
+ *
+ * Comment this macro to disable support for DTLS
+ */
+#define MBEDTLS_SSL_PROTO_DTLS
+
+/**
+ * \def MBEDTLS_SSL_ALPN
+ *
+ * Enable support for RFC 7301 Application Layer Protocol Negotiation.
+ *
+ * Comment this macro to disable support for ALPN.
+ */
+#define MBEDTLS_SSL_ALPN
+
+/**
+ * \def MBEDTLS_SSL_DTLS_ANTI_REPLAY
+ *
+ * Enable support for the anti-replay mechanism in DTLS.
+ *
+ * Requires: MBEDTLS_SSL_TLS_C
+ *           MBEDTLS_SSL_PROTO_DTLS
+ *
+ * \warning Disabling this is often a security risk!
+ * See mbedtls_ssl_conf_dtls_anti_replay() for details.
+ *
+ * Comment this to disable anti-replay in DTLS.
+ */
+#define MBEDTLS_SSL_DTLS_ANTI_REPLAY
+
+/**
+ * \def MBEDTLS_SSL_DTLS_HELLO_VERIFY
+ *
+ * Enable support for HelloVerifyRequest on DTLS servers.
+ *
+ * This feature is highly recommended to prevent DTLS servers being used as
+ * amplifiers in DoS attacks against other hosts. It should always be enabled
+ * unless you know for sure amplification cannot be a problem in the
+ * environment in which your server operates.
+ *
+ * \warning Disabling this can ba a security risk! (see above)
+ *
+ * Requires: MBEDTLS_SSL_PROTO_DTLS
+ *
+ * Comment this to disable support for HelloVerifyRequest.
+ */
+#define MBEDTLS_SSL_DTLS_HELLO_VERIFY
+
+/**
+ * \def MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE
+ *
+ * Enable server-side support for clients that reconnect from the same port.
+ *
+ * Some clients unexpectedly close the connection and try to reconnect using the
+ * same source port. This needs special support from the server to handle the
+ * new connection securely, as described in section 4.2.8 of RFC 6347. This
+ * flag enables that support.
+ *
+ * Requires: MBEDTLS_SSL_DTLS_HELLO_VERIFY
+ *
+ * Comment this to disable support for clients reusing the source port.
+ */
+#define MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE
+
+/**
+ * \def MBEDTLS_SSL_DTLS_BADMAC_LIMIT
+ *
+ * Enable support for a limit of records with bad MAC.
+ *
+ * See mbedtls_ssl_conf_dtls_badmac_limit().
+ *
+ * Requires: MBEDTLS_SSL_PROTO_DTLS
+ */
+#define MBEDTLS_SSL_DTLS_BADMAC_LIMIT
+
+/**
+ * \def MBEDTLS_SSL_SESSION_TICKETS
+ *
+ * Enable support for RFC 5077 session tickets in SSL.
+ * Client-side, provides full support for session tickets (maintainance of a
+ * session store remains the responsibility of the application, though).
+ * Server-side, you also need to provide callbacks for writing and parsing
+ * tickets, including authenticated encryption and key management. Example
+ * callbacks are provided by MBEDTLS_SSL_TICKET_C.
+ *
+ * Comment this macro to disable support for SSL session tickets
+ */
+#define MBEDTLS_SSL_SESSION_TICKETS
+
+/**
+ * \def MBEDTLS_SSL_EXPORT_KEYS
+ *
+ * Enable support for exporting key block and master secret.
+ * This is required for certain users of TLS, e.g. EAP-TLS.
+ *
+ * Comment this macro to disable support for key export
+ */
+#define MBEDTLS_SSL_EXPORT_KEYS
+
+/**
+ * \def MBEDTLS_SSL_SERVER_NAME_INDICATION
+ *
+ * Enable support for RFC 6066 server name indication (SNI) in SSL.
+ *
+ * Requires: MBEDTLS_X509_CRT_PARSE_C
+ *
+ * Comment this macro to disable support for server name indication in SSL
+ */
+#define MBEDTLS_SSL_SERVER_NAME_INDICATION
+
+/**
+ * \def MBEDTLS_SSL_TRUNCATED_HMAC
+ *
+ * Enable support for RFC 6066 truncated HMAC in SSL.
+ *
+ * Comment this macro to disable support for truncated HMAC in SSL
+ */
+#define MBEDTLS_SSL_TRUNCATED_HMAC
+
+/**
+ * \def MBEDTLS_THREADING_ALT
+ *
+ * Provide your own alternate threading implementation.
+ *
+ * Requires: MBEDTLS_THREADING_C
+ *
+ * Uncomment this to allow your own alternate threading implementation.
+ */
+//#define MBEDTLS_THREADING_ALT
+
+/**
+ * \def MBEDTLS_THREADING_PTHREAD
+ *
+ * Enable the pthread wrapper layer for the threading layer.
+ *
+ * Requires: MBEDTLS_THREADING_C
+ *
+ * Uncomment this to enable pthread mutexes.
+ */
+//#define MBEDTLS_THREADING_PTHREAD
+
+/**
+ * \def MBEDTLS_VERSION_FEATURES
+ *
+ * Allow run-time checking of compile-time enabled features. Thus allowing users
+ * to check at run-time if the library is for instance compiled with threading
+ * support via mbedtls_version_check_feature().
+ *
+ * Requires: MBEDTLS_VERSION_C
+ *
+ * Comment this to disable run-time checking and save ROM space
+ */
+#define MBEDTLS_VERSION_FEATURES
+
+/**
+ * \def MBEDTLS_X509_ALLOW_EXTENSIONS_NON_V3
+ *
+ * If set, the X509 parser will not break-off when parsing an X509 certificate
+ * and encountering an extension in a v1 or v2 certificate.
+ *
+ * Uncomment to prevent an error.
+ */
+//#define MBEDTLS_X509_ALLOW_EXTENSIONS_NON_V3
+
+/**
+ * \def MBEDTLS_X509_ALLOW_UNSUPPORTED_CRITICAL_EXTENSION
+ *
+ * If set, the X509 parser will not break-off when parsing an X509 certificate
+ * and encountering an unknown critical extension.
+ *
+ * \warning Depending on your PKI use, enabling this can be a security risk!
+ *
+ * Uncomment to prevent an error.
+ */
+//#define MBEDTLS_X509_ALLOW_UNSUPPORTED_CRITICAL_EXTENSION
+
+/**
+ * \def MBEDTLS_X509_CHECK_KEY_USAGE
+ *
+ * Enable verification of the keyUsage extension (CA and leaf certificates).
+ *
+ * Disabling this avoids problems with mis-issued and/or misused
+ * (intermediate) CA and leaf certificates.
+ *
+ * \warning Depending on your PKI use, disabling this can be a security risk!
+ *
+ * Comment to skip keyUsage checking for both CA and leaf certificates.
+ */
+#define MBEDTLS_X509_CHECK_KEY_USAGE
+
+/**
+ * \def MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE
+ *
+ * Enable verification of the extendedKeyUsage extension (leaf certificates).
+ *
+ * Disabling this avoids problems with mis-issued and/or misused certificates.
+ *
+ * \warning Depending on your PKI use, disabling this can be a security risk!
+ *
+ * Comment to skip extendedKeyUsage checking for certificates.
+ */
+#define MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE
+
+/**
+ * \def MBEDTLS_X509_RSASSA_PSS_SUPPORT
+ *
+ * Enable parsing and verification of X.509 certificates, CRLs and CSRS
+ * signed with RSASSA-PSS (aka PKCS#1 v2.1).
+ *
+ * Comment this macro to disallow using RSASSA-PSS in certificates.
+ */
+#define MBEDTLS_X509_RSASSA_PSS_SUPPORT
+
+/**
+ * \def MBEDTLS_ZLIB_SUPPORT
+ *
+ * If set, the SSL/TLS module uses ZLIB to support compression and
+ * decompression of packet data.
+ *
+ * \warning TLS-level compression MAY REDUCE SECURITY! See for example the
+ * CRIME attack. Before enabling this option, you should examine with care if
+ * CRIME or similar exploits may be a applicable to your use case.
+ *
+ * \note Currently compression can't be used with DTLS.
+ *
+ * Used in: library/ssl_tls.c
+ *          library/ssl_cli.c
+ *          library/ssl_srv.c
+ *
+ * This feature requires zlib library and headers to be present.
+ *
+ * Uncomment to enable use of ZLIB
+ */
+//#define MBEDTLS_ZLIB_SUPPORT
+/* \} name SECTION: mbed TLS feature support */
+
+/**
+ * \name SECTION: mbed TLS modules
+ *
+ * This section enables or disables entire modules in mbed TLS
+ * \{
+ */
+
+/**
+ * \def MBEDTLS_AESNI_C
+ *
+ * Enable AES-NI support on x86-64.
+ *
+ * Module:  library/aesni.c
+ * Caller:  library/aes.c
+ *
+ * Requires: MBEDTLS_HAVE_ASM
+ *
+ * This modules adds support for the AES-NI instructions on x86-64
+ */
+#define MBEDTLS_AESNI_C
+
+/**
+ * \def MBEDTLS_AES_C
+ *
+ * Enable the AES block cipher.
+ *
+ * Module:  library/aes.c
+ * Caller:  library/ssl_tls.c
+ *          library/pem.c
+ *          library/ctr_drbg.c
+ *
+ * This module enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384
+ *      MBEDTLS_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384
+ *      MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA256
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA
+ *      MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256
+ *      MBEDTLS_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256
+ *      MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA256
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA
+ *      MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA
+ *      MBEDTLS_TLS_DHE_PSK_WITH_AES_256_GCM_SHA384
+ *      MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA384
+ *      MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA384
+ *      MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA
+ *      MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA
+ *      MBEDTLS_TLS_DHE_PSK_WITH_AES_128_GCM_SHA256
+ *      MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA256
+ *      MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA256
+ *      MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA
+ *      MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA
+ *      MBEDTLS_TLS_RSA_WITH_AES_256_GCM_SHA384
+ *      MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA256
+ *      MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA
+ *      MBEDTLS_TLS_RSA_WITH_AES_128_GCM_SHA256
+ *      MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA256
+ *      MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA
+ *      MBEDTLS_TLS_RSA_PSK_WITH_AES_256_GCM_SHA384
+ *      MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA384
+ *      MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA
+ *      MBEDTLS_TLS_RSA_PSK_WITH_AES_128_GCM_SHA256
+ *      MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA256
+ *      MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA
+ *      MBEDTLS_TLS_PSK_WITH_AES_256_GCM_SHA384
+ *      MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA384
+ *      MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA
+ *      MBEDTLS_TLS_PSK_WITH_AES_128_GCM_SHA256
+ *      MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA256
+ *      MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA
+ *
+ * PEM_PARSE uses AES for decrypting encrypted keys.
+ */
+#define MBEDTLS_AES_C
+
+/**
+ * \def MBEDTLS_ARC4_C
+ *
+ * Enable the ARCFOUR stream cipher.
+ *
+ * Module:  library/arc4.c
+ * Caller:  library/ssl_tls.c
+ *
+ * This module enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_RC4_128_SHA
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_RC4_128_SHA
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_RC4_128_SHA
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_RC4_128_SHA
+ *      MBEDTLS_TLS_ECDHE_PSK_WITH_RC4_128_SHA
+ *      MBEDTLS_TLS_DHE_PSK_WITH_RC4_128_SHA
+ *      MBEDTLS_TLS_RSA_WITH_RC4_128_SHA
+ *      MBEDTLS_TLS_RSA_WITH_RC4_128_MD5
+ *      MBEDTLS_TLS_RSA_PSK_WITH_RC4_128_SHA
+ *      MBEDTLS_TLS_PSK_WITH_RC4_128_SHA
+ */
+#define MBEDTLS_ARC4_C
+
+/**
+ * \def MBEDTLS_ASN1_PARSE_C
+ *
+ * Enable the generic ASN1 parser.
+ *
+ * Module:  library/asn1.c
+ * Caller:  library/x509.c
+ *          library/dhm.c
+ *          library/pkcs12.c
+ *          library/pkcs5.c
+ *          library/pkparse.c
+ */
+#define MBEDTLS_ASN1_PARSE_C
+
+/**
+ * \def MBEDTLS_ASN1_WRITE_C
+ *
+ * Enable the generic ASN1 writer.
+ *
+ * Module:  library/asn1write.c
+ * Caller:  library/ecdsa.c
+ *          library/pkwrite.c
+ *          library/x509_create.c
+ *          library/x509write_crt.c
+ *          library/mbedtls_x509write_csr.c
+ */
+#define MBEDTLS_ASN1_WRITE_C
+
+/**
+ * \def MBEDTLS_BASE64_C
+ *
+ * Enable the Base64 module.
+ *
+ * Module:  library/base64.c
+ * Caller:  library/pem.c
+ *
+ * This module is required for PEM support (required by X.509).
+ */
+#define MBEDTLS_BASE64_C
+
+/**
+ * \def MBEDTLS_BIGNUM_C
+ *
+ * Enable the multi-precision integer library.
+ *
+ * Module:  library/bignum.c
+ * Caller:  library/dhm.c
+ *          library/ecp.c
+ *          library/ecdsa.c
+ *          library/rsa.c
+ *          library/ssl_tls.c
+ *
+ * This module is required for RSA, DHM and ECC (ECDH, ECDSA) support.
+ */
+#define MBEDTLS_BIGNUM_C
+
+/**
+ * \def MBEDTLS_BLOWFISH_C
+ *
+ * Enable the Blowfish block cipher.
+ *
+ * Module:  library/blowfish.c
+ */
+#define MBEDTLS_BLOWFISH_C
+
+/**
+ * \def MBEDTLS_CAMELLIA_C
+ *
+ * Enable the Camellia block cipher.
+ *
+ * Module:  library/camellia.c
+ * Caller:  library/ssl_tls.c
+ *
+ * This module enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_CBC_SHA256
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_CBC_SHA384
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_CBC_SHA256
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_CBC_SHA384
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_GCM_SHA256
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_GCM_SHA384
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_GCM_SHA256
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_GCM_SHA384
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_GCM_SHA384
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_GCM_SHA384
+ *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_GCM_SHA384
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_CBC_SHA384
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_CBC_SHA384
+ *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256
+ *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_GCM_SHA256
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_GCM_SHA256
+ *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_GCM_SHA256
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_CBC_SHA256
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_CBC_SHA256
+ *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256
+ *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA
+ *      MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_GCM_SHA384
+ *      MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_256_CBC_SHA384
+ *      MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_CBC_SHA384
+ *      MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_GCM_SHA256
+ *      MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_CBC_SHA256
+ *      MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_128_CBC_SHA256
+ *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_GCM_SHA384
+ *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256
+ *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA
+ *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_GCM_SHA256
+ *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256
+ *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA
+ *      MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_GCM_SHA384
+ *      MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_CBC_SHA384
+ *      MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_GCM_SHA256
+ *      MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_CBC_SHA256
+ *      MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_GCM_SHA384
+ *      MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_CBC_SHA384
+ *      MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_GCM_SHA256
+ *      MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256
+ */
+#define MBEDTLS_CAMELLIA_C
+
+/**
+ * \def MBEDTLS_CCM_C
+ *
+ * Enable the Counter with CBC-MAC (CCM) mode for 128-bit block cipher.
+ *
+ * Module:  library/ccm.c
+ *
+ * Requires: MBEDTLS_AES_C or MBEDTLS_CAMELLIA_C
+ *
+ * This module enables the AES-CCM ciphersuites, if other requisites are
+ * enabled as well.
+ */
+#define MBEDTLS_CCM_C
+
+/**
+ * \def MBEDTLS_CERTS_C
+ *
+ * Enable the test certificates.
+ *
+ * Module:  library/certs.c
+ * Caller:
+ *
+ * This module is used for testing (ssl_client/server).
+ */
+#define MBEDTLS_CERTS_C
+
+/**
+ * \def MBEDTLS_CIPHER_C
+ *
+ * Enable the generic cipher layer.
+ *
+ * Module:  library/cipher.c
+ * Caller:  library/ssl_tls.c
+ *
+ * Uncomment to enable generic cipher wrappers.
+ */
+#define MBEDTLS_CIPHER_C
+
+/**
+ * \def MBEDTLS_CTR_DRBG_C
+ *
+ * Enable the CTR_DRBG AES-256-based random generator.
+ *
+ * Module:  library/ctr_drbg.c
+ * Caller:
+ *
+ * Requires: MBEDTLS_AES_C
+ *
+ * This module provides the CTR_DRBG AES-256 random number generator.
+ */
+#define MBEDTLS_CTR_DRBG_C
+
+/**
+ * \def MBEDTLS_DEBUG_C
+ *
+ * Enable the debug functions.
+ *
+ * Module:  library/debug.c
+ * Caller:  library/ssl_cli.c
+ *          library/ssl_srv.c
+ *          library/ssl_tls.c
+ *
+ * This module provides debugging functions.
+ */
+#if CONFIG_MBEDTLS_DEBUG
+#define MBEDTLS_DEBUG_C
+#endif
+
+/**
+ * \def MBEDTLS_DES_C
+ *
+ * Enable the DES block cipher.
+ *
+ * Module:  library/des.c
+ * Caller:  library/pem.c
+ *          library/ssl_tls.c
+ *
+ * This module enables the following ciphersuites (if other requisites are
+ * enabled as well):
+ *      MBEDTLS_TLS_ECDH_ECDSA_WITH_3DES_EDE_CBC_SHA
+ *      MBEDTLS_TLS_ECDH_RSA_WITH_3DES_EDE_CBC_SHA
+ *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA
+ *      MBEDTLS_TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA
+ *      MBEDTLS_TLS_DHE_RSA_WITH_3DES_EDE_CBC_SHA
+ *      MBEDTLS_TLS_ECDHE_PSK_WITH_3DES_EDE_CBC_SHA
+ *      MBEDTLS_TLS_DHE_PSK_WITH_3DES_EDE_CBC_SHA
+ *      MBEDTLS_TLS_RSA_WITH_3DES_EDE_CBC_SHA
+ *      MBEDTLS_TLS_RSA_PSK_WITH_3DES_EDE_CBC_SHA
+ *      MBEDTLS_TLS_PSK_WITH_3DES_EDE_CBC_SHA
+ *
+ * PEM_PARSE uses DES/3DES for decrypting encrypted keys.
+ */
+#define MBEDTLS_DES_C
+
+/**
+ * \def MBEDTLS_DHM_C
+ *
+ * Enable the Diffie-Hellman-Merkle module.
+ *
+ * Module:  library/dhm.c
+ * Caller:  library/ssl_cli.c
+ *          library/ssl_srv.c
+ *
+ * This module is used by the following key exchanges:
+ *      DHE-RSA, DHE-PSK
+ */
+#define MBEDTLS_DHM_C
+
+/**
+ * \def MBEDTLS_ECDH_C
+ *
+ * Enable the elliptic curve Diffie-Hellman library.
+ *
+ * Module:  library/ecdh.c
+ * Caller:  library/ssl_cli.c
+ *          library/ssl_srv.c
+ *
+ * This module is used by the following key exchanges:
+ *      ECDHE-ECDSA, ECDHE-RSA, DHE-PSK
+ *
+ * Requires: MBEDTLS_ECP_C
+ */
+#define MBEDTLS_ECDH_C
+
+/**
+ * \def MBEDTLS_ECDSA_C
+ *
+ * Enable the elliptic curve DSA library.
+ *
+ * Module:  library/ecdsa.c
+ * Caller:
+ *
+ * This module is used by the following key exchanges:
+ *      ECDHE-ECDSA
+ *
+ * Requires: MBEDTLS_ECP_C, MBEDTLS_ASN1_WRITE_C, MBEDTLS_ASN1_PARSE_C
+ */
+#define MBEDTLS_ECDSA_C
+
+/**
+ * \def MBEDTLS_ECJPAKE_C
+ *
+ * Enable the elliptic curve J-PAKE library.
+ *
+ * \warning This is currently experimental. EC J-PAKE support is based on the
+ * Thread v1.0.0 specification; incompatible changes to the specification
+ * might still happen. For this reason, this is disabled by default.
+ *
+ * Module:  library/ecjpake.c
+ * Caller:
+ *
+ * This module is used by the following key exchanges:
+ *      ECJPAKE
+ *
+ * Requires: MBEDTLS_ECP_C, MBEDTLS_MD_C
+ */
+//#define MBEDTLS_ECJPAKE_C
+
+/**
+ * \def MBEDTLS_ECP_C
+ *
+ * Enable the elliptic curve over GF(p) library.
+ *
+ * Module:  library/ecp.c
+ * Caller:  library/ecdh.c
+ *          library/ecdsa.c
+ *          library/ecjpake.c
+ *
+ * Requires: MBEDTLS_BIGNUM_C and at least one MBEDTLS_ECP_DP_XXX_ENABLED
+ */
+#define MBEDTLS_ECP_C
+
+/**
+ * \def MBEDTLS_ENTROPY_C
+ *
+ * Enable the platform-specific entropy code.
+ *
+ * Module:  library/entropy.c
+ * Caller:
+ *
+ * Requires: MBEDTLS_SHA512_C or MBEDTLS_SHA256_C
+ *
+ * This module provides a generic entropy pool
+ */
+#define MBEDTLS_ENTROPY_C
+
+/**
+ * \def MBEDTLS_ERROR_C
+ *
+ * Enable error code to error string conversion.
+ *
+ * Module:  library/error.c
+ * Caller:
+ *
+ * This module enables mbedtls_strerror().
+ */
+#define MBEDTLS_ERROR_C
+
+/**
+ * \def MBEDTLS_GCM_C
+ *
+ * Enable the Galois/Counter Mode (GCM) for AES.
+ *
+ * Module:  library/gcm.c
+ *
+ * Requires: MBEDTLS_AES_C or MBEDTLS_CAMELLIA_C
+ *
+ * This module enables the AES-GCM and CAMELLIA-GCM ciphersuites, if other
+ * requisites are enabled as well.
+ */
+#define MBEDTLS_GCM_C
+
+/**
+ * \def MBEDTLS_HAVEGE_C
+ *
+ * Enable the HAVEGE random generator.
+ *
+ * Warning: the HAVEGE random generator is not suitable for virtualized
+ *          environments
+ *
+ * Warning: the HAVEGE random generator is dependent on timing and specific
+ *          processor traits. It is therefore not advised to use HAVEGE as
+ *          your applications primary random generator or primary entropy pool
+ *          input. As a secondary input to your entropy pool, it IS able add
+ *          the (limited) extra entropy it provides.
+ *
+ * Module:  library/havege.c
+ * Caller:
+ *
+ * Requires: MBEDTLS_TIMING_C
+ *
+ * Uncomment to enable the HAVEGE random generator.
+ */
+//#define MBEDTLS_HAVEGE_C
+
+/**
+ * \def MBEDTLS_HMAC_DRBG_C
+ *
+ * Enable the HMAC_DRBG random generator.
+ *
+ * Module:  library/hmac_drbg.c
+ * Caller:
+ *
+ * Requires: MBEDTLS_MD_C
+ *
+ * Uncomment to enable the HMAC_DRBG random number geerator.
+ */
+#define MBEDTLS_HMAC_DRBG_C
+
+/**
+ * \def MBEDTLS_MD_C
+ *
+ * Enable the generic message digest layer.
+ *
+ * Module:  library/mbedtls_md.c
+ * Caller:
+ *
+ * Uncomment to enable generic message digest wrappers.
+ */
+#define MBEDTLS_MD_C
+
+/**
+ * \def MBEDTLS_MD2_C
+ *
+ * Enable the MD2 hash algorithm.
+ *
+ * Module:  library/mbedtls_md2.c
+ * Caller:
+ *
+ * Uncomment to enable support for (rare) MD2-signed X.509 certs.
+ */
+//#define MBEDTLS_MD2_C
+
+/**
+ * \def MBEDTLS_MD4_C
+ *
+ * Enable the MD4 hash algorithm.
+ *
+ * Module:  library/mbedtls_md4.c
+ * Caller:
+ *
+ * Uncomment to enable support for (rare) MD4-signed X.509 certs.
+ */
+//#define MBEDTLS_MD4_C
+
+/**
+ * \def MBEDTLS_MD5_C
+ *
+ * Enable the MD5 hash algorithm.
+ *
+ * Module:  library/mbedtls_md5.c
+ * Caller:  library/mbedtls_md.c
+ *          library/pem.c
+ *          library/ssl_tls.c
+ *
+ * This module is required for SSL/TLS and X.509.
+ * PEM_PARSE uses MD5 for decrypting encrypted keys.
+ */
+#define MBEDTLS_MD5_C
+
+/**
+ * \def MBEDTLS_MEMORY_BUFFER_ALLOC_C
+ *
+ * Enable the buffer allocator implementation that makes use of a (stack)
+ * based buffer to 'allocate' dynamic memory. (replaces calloc() and free()
+ * calls)
+ *
+ * Module:  library/memory_buffer_alloc.c
+ *
+ * Requires: MBEDTLS_PLATFORM_C
+ *           MBEDTLS_PLATFORM_MEMORY (to use it within mbed TLS)
+ *
+ * Enable this module to enable the buffer memory allocator.
+ */
+//#define MBEDTLS_MEMORY_BUFFER_ALLOC_C
+
+/**
+ * \def MBEDTLS_NET_C
+ *
+ * Enable the TCP/IP networking routines.
+ *
+ * Module:  library/net.c
+ *
+ * This module provides TCP/IP networking routines.
+ */
+//#define MBEDTLS_NET_C
+
+/**
+ * \def MBEDTLS_OID_C
+ *
+ * Enable the OID database.
+ *
+ * Module:  library/oid.c
+ * Caller:  library/asn1write.c
+ *          library/pkcs5.c
+ *          library/pkparse.c
+ *          library/pkwrite.c
+ *          library/rsa.c
+ *          library/x509.c
+ *          library/x509_create.c
+ *          library/mbedtls_x509_crl.c
+ *          library/mbedtls_x509_crt.c
+ *          library/mbedtls_x509_csr.c
+ *          library/x509write_crt.c
+ *          library/mbedtls_x509write_csr.c
+ *
+ * This modules translates between OIDs and internal values.
+ */
+#define MBEDTLS_OID_C
+
+/**
+ * \def MBEDTLS_PADLOCK_C
+ *
+ * Enable VIA Padlock support on x86.
+ *
+ * Module:  library/padlock.c
+ * Caller:  library/aes.c
+ *
+ * Requires: MBEDTLS_HAVE_ASM
+ *
+ * This modules adds support for the VIA PadLock on x86.
+ */
+#define MBEDTLS_PADLOCK_C
+
+/**
+ * \def MBEDTLS_PEM_PARSE_C
+ *
+ * Enable PEM decoding / parsing.
+ *
+ * Module:  library/pem.c
+ * Caller:  library/dhm.c
+ *          library/pkparse.c
+ *          library/mbedtls_x509_crl.c
+ *          library/mbedtls_x509_crt.c
+ *          library/mbedtls_x509_csr.c
+ *
+ * Requires: MBEDTLS_BASE64_C
+ *
+ * This modules adds support for decoding / parsing PEM files.
+ */
+#define MBEDTLS_PEM_PARSE_C
+
+/**
+ * \def MBEDTLS_PEM_WRITE_C
+ *
+ * Enable PEM encoding / writing.
+ *
+ * Module:  library/pem.c
+ * Caller:  library/pkwrite.c
+ *          library/x509write_crt.c
+ *          library/mbedtls_x509write_csr.c
+ *
+ * Requires: MBEDTLS_BASE64_C
+ *
+ * This modules adds support for encoding / writing PEM files.
+ */
+#define MBEDTLS_PEM_WRITE_C
+
+/**
+ * \def MBEDTLS_PK_C
+ *
+ * Enable the generic public (asymetric) key layer.
+ *
+ * Module:  library/pk.c
+ * Caller:  library/ssl_tls.c
+ *          library/ssl_cli.c
+ *          library/ssl_srv.c
+ *
+ * Requires: MBEDTLS_RSA_C or MBEDTLS_ECP_C
+ *
+ * Uncomment to enable generic public key wrappers.
+ */
+#define MBEDTLS_PK_C
+
+/**
+ * \def MBEDTLS_PK_PARSE_C
+ *
+ * Enable the generic public (asymetric) key parser.
+ *
+ * Module:  library/pkparse.c
+ * Caller:  library/mbedtls_x509_crt.c
+ *          library/mbedtls_x509_csr.c
+ *
+ * Requires: MBEDTLS_PK_C
+ *
+ * Uncomment to enable generic public key parse functions.
+ */
+#define MBEDTLS_PK_PARSE_C
+
+/**
+ * \def MBEDTLS_PK_WRITE_C
+ *
+ * Enable the generic public (asymetric) key writer.
+ *
+ * Module:  library/pkwrite.c
+ * Caller:  library/x509write.c
+ *
+ * Requires: MBEDTLS_PK_C
+ *
+ * Uncomment to enable generic public key write functions.
+ */
+#define MBEDTLS_PK_WRITE_C
+
+/**
+ * \def MBEDTLS_PKCS5_C
+ *
+ * Enable PKCS#5 functions.
+ *
+ * Module:  library/pkcs5.c
+ *
+ * Requires: MBEDTLS_MD_C
+ *
+ * This module adds support for the PKCS#5 functions.
+ */
+#define MBEDTLS_PKCS5_C
+
+/**
+ * \def MBEDTLS_PKCS11_C
+ *
+ * Enable wrapper for PKCS#11 smartcard support.
+ *
+ * Module:  library/pkcs11.c
+ * Caller:  library/pk.c
+ *
+ * Requires: MBEDTLS_PK_C
+ *
+ * This module enables SSL/TLS PKCS #11 smartcard support.
+ * Requires the presence of the PKCS#11 helper library (libpkcs11-helper)
+ */
+//#define MBEDTLS_PKCS11_C
+
+/**
+ * \def MBEDTLS_PKCS12_C
+ *
+ * Enable PKCS#12 PBE functions.
+ * Adds algorithms for parsing PKCS#8 encrypted private keys
+ *
+ * Module:  library/pkcs12.c
+ * Caller:  library/pkparse.c
+ *
+ * Requires: MBEDTLS_ASN1_PARSE_C, MBEDTLS_CIPHER_C, MBEDTLS_MD_C
+ * Can use:  MBEDTLS_ARC4_C
+ *
+ * This module enables PKCS#12 functions.
+ */
+#define MBEDTLS_PKCS12_C
+
+/**
+ * \def MBEDTLS_PLATFORM_C
+ *
+ * Enable the platform abstraction layer that allows you to re-assign
+ * functions like calloc(), free(), snprintf(), printf(), fprintf(), exit().
+ *
+ * Enabling MBEDTLS_PLATFORM_C enables to use of MBEDTLS_PLATFORM_XXX_ALT
+ * or MBEDTLS_PLATFORM_XXX_MACRO directives, allowing the functions mentioned
+ * above to be specified at runtime or compile time respectively.
+ *
+ * \note This abstraction layer must be enabled on Windows (including MSYS2)
+ * as other module rely on it for a fixed snprintf implementation.
+ *
+ * Module:  library/platform.c
+ * Caller:  Most other .c files
+ *
+ * This module enables abstraction of common (libc) functions.
+ */
+#define MBEDTLS_PLATFORM_C
+
+/**
+ * \def MBEDTLS_RIPEMD160_C
+ *
+ * Enable the RIPEMD-160 hash algorithm.
+ *
+ * Module:  library/mbedtls_ripemd160.c
+ * Caller:  library/mbedtls_md.c
+ *
+ */
+#define MBEDTLS_RIPEMD160_C
+
+/**
+ * \def MBEDTLS_RSA_C
+ *
+ * Enable the RSA public-key cryptosystem.
+ *
+ * Module:  library/rsa.c
+ * Caller:  library/ssl_cli.c
+ *          library/ssl_srv.c
+ *          library/ssl_tls.c
+ *          library/x509.c
+ *
+ * This module is used by the following key exchanges:
+ *      RSA, DHE-RSA, ECDHE-RSA, RSA-PSK
+ *
+ * Requires: MBEDTLS_BIGNUM_C, MBEDTLS_OID_C
+ */
+#define MBEDTLS_RSA_C
+
+/**
+ * \def MBEDTLS_SHA1_C
+ *
+ * Enable the SHA1 cryptographic hash algorithm.
+ *
+ * Module:  library/mbedtls_sha1.c
+ * Caller:  library/mbedtls_md.c
+ *          library/ssl_cli.c
+ *          library/ssl_srv.c
+ *          library/ssl_tls.c
+ *          library/x509write_crt.c
+ *
+ * This module is required for SSL/TLS and SHA1-signed certificates.
+ */
+#define MBEDTLS_SHA1_C
+
+/**
+ * \def MBEDTLS_SHA256_C
+ *
+ * Enable the SHA-224 and SHA-256 cryptographic hash algorithms.
+ *
+ * Module:  library/mbedtls_sha256.c
+ * Caller:  library/entropy.c
+ *          library/mbedtls_md.c
+ *          library/ssl_cli.c
+ *          library/ssl_srv.c
+ *          library/ssl_tls.c
+ *
+ * This module adds support for SHA-224 and SHA-256.
+ * This module is required for the SSL/TLS 1.2 PRF function.
+ */
+#define MBEDTLS_SHA256_C
+
+/**
+ * \def MBEDTLS_SHA512_C
+ *
+ * Enable the SHA-384 and SHA-512 cryptographic hash algorithms.
+ *
+ * Module:  library/mbedtls_sha512.c
+ * Caller:  library/entropy.c
+ *          library/mbedtls_md.c
+ *          library/ssl_cli.c
+ *          library/ssl_srv.c
+ *
+ * This module adds support for SHA-384 and SHA-512.
+ */
+#define MBEDTLS_SHA512_C
+
+/**
+ * \def MBEDTLS_SSL_CACHE_C
+ *
+ * Enable simple SSL cache implementation.
+ *
+ * Module:  library/ssl_cache.c
+ * Caller:
+ *
+ * Requires: MBEDTLS_SSL_CACHE_C
+ */
+#define MBEDTLS_SSL_CACHE_C
+
+/**
+ * \def MBEDTLS_SSL_COOKIE_C
+ *
+ * Enable basic implementation of DTLS cookies for hello verification.
+ *
+ * Module:  library/ssl_cookie.c
+ * Caller:
+ */
+#define MBEDTLS_SSL_COOKIE_C
+
+/**
+ * \def MBEDTLS_SSL_TICKET_C
+ *
+ * Enable an implementation of TLS server-side callbacks for session tickets.
+ *
+ * Module:  library/ssl_ticket.c
+ * Caller:
+ *
+ * Requires: MBEDTLS_CIPHER_C
+ */
+#define MBEDTLS_SSL_TICKET_C
+
+/**
+ * \def MBEDTLS_SSL_CLI_C
+ *
+ * Enable the SSL/TLS client code.
+ *
+ * Module:  library/ssl_cli.c
+ * Caller:
+ *
+ * Requires: MBEDTLS_SSL_TLS_C
+ *
+ * This module is required for SSL/TLS client support.
+ */
+#define MBEDTLS_SSL_CLI_C
+
+/**
+ * \def MBEDTLS_SSL_SRV_C
+ *
+ * Enable the SSL/TLS server code.
+ *
+ * Module:  library/ssl_srv.c
+ * Caller:
+ *
+ * Requires: MBEDTLS_SSL_TLS_C
+ *
+ * This module is required for SSL/TLS server support.
+ */
+#define MBEDTLS_SSL_SRV_C
+
+/**
+ * \def MBEDTLS_SSL_TLS_C
+ *
+ * Enable the generic SSL/TLS code.
+ *
+ * Module:  library/ssl_tls.c
+ * Caller:  library/ssl_cli.c
+ *          library/ssl_srv.c
+ *
+ * Requires: MBEDTLS_CIPHER_C, MBEDTLS_MD_C
+ *           and at least one of the MBEDTLS_SSL_PROTO_XXX defines
+ *
+ * This module is required for SSL/TLS.
+ */
+#define MBEDTLS_SSL_TLS_C
+
+/**
+ * \def MBEDTLS_THREADING_C
+ *
+ * Enable the threading abstraction layer.
+ * By default mbed TLS assumes it is used in a non-threaded environment or that
+ * contexts are not shared between threads. If you do intend to use contexts
+ * between threads, you will need to enable this layer to prevent race
+ * conditions.
+ *
+ * Module:  library/threading.c
+ *
+ * This allows different threading implementations (self-implemented or
+ * provided).
+ *
+ * You will have to enable either MBEDTLS_THREADING_ALT or
+ * MBEDTLS_THREADING_PTHREAD.
+ *
+ * Enable this layer to allow use of mutexes within mbed TLS
+ */
+//#define MBEDTLS_THREADING_C
+
+/**
+ * \def MBEDTLS_TIMING_C
+ *
+ * Enable the portable timing interface.
+ *
+ * Module:  library/timing.c
+ * Caller:  library/havege.c
+ *
+ * This module is used by the HAVEGE random number generator.
+ */
+//#define MBEDTLS_TIMING_C
+
+/**
+ * \def MBEDTLS_VERSION_C
+ *
+ * Enable run-time version information.
+ *
+ * Module:  library/version.c
+ *
+ * This module provides run-time version information.
+ */
+#define MBEDTLS_VERSION_C
+
+/**
+ * \def MBEDTLS_X509_USE_C
+ *
+ * Enable X.509 core for using certificates.
+ *
+ * Module:  library/x509.c
+ * Caller:  library/mbedtls_x509_crl.c
+ *          library/mbedtls_x509_crt.c
+ *          library/mbedtls_x509_csr.c
+ *
+ * Requires: MBEDTLS_ASN1_PARSE_C, MBEDTLS_BIGNUM_C, MBEDTLS_OID_C,
+ *           MBEDTLS_PK_PARSE_C
+ *
+ * This module is required for the X.509 parsing modules.
+ */
+#define MBEDTLS_X509_USE_C
+
+/**
+ * \def MBEDTLS_X509_CRT_PARSE_C
+ *
+ * Enable X.509 certificate parsing.
+ *
+ * Module:  library/mbedtls_x509_crt.c
+ * Caller:  library/ssl_cli.c
+ *          library/ssl_srv.c
+ *          library/ssl_tls.c
+ *
+ * Requires: MBEDTLS_X509_USE_C
+ *
+ * This module is required for X.509 certificate parsing.
+ */
+#define MBEDTLS_X509_CRT_PARSE_C
+
+/**
+ * \def MBEDTLS_X509_CRL_PARSE_C
+ *
+ * Enable X.509 CRL parsing.
+ *
+ * Module:  library/mbedtls_x509_crl.c
+ * Caller:  library/mbedtls_x509_crt.c
+ *
+ * Requires: MBEDTLS_X509_USE_C
+ *
+ * This module is required for X.509 CRL parsing.
+ */
+#define MBEDTLS_X509_CRL_PARSE_C
+
+/**
+ * \def MBEDTLS_X509_CSR_PARSE_C
+ *
+ * Enable X.509 Certificate Signing Request (CSR) parsing.
+ *
+ * Module:  library/mbedtls_x509_csr.c
+ * Caller:  library/x509_crt_write.c
+ *
+ * Requires: MBEDTLS_X509_USE_C
+ *
+ * This module is used for reading X.509 certificate request.
+ */
+#define MBEDTLS_X509_CSR_PARSE_C
+
+/**
+ * \def MBEDTLS_X509_CREATE_C
+ *
+ * Enable X.509 core for creating certificates.
+ *
+ * Module:  library/x509_create.c
+ *
+ * Requires: MBEDTLS_BIGNUM_C, MBEDTLS_OID_C, MBEDTLS_PK_WRITE_C
+ *
+ * This module is the basis for creating X.509 certificates and CSRs.
+ */
+#define MBEDTLS_X509_CREATE_C
+
+/**
+ * \def MBEDTLS_X509_CRT_WRITE_C
+ *
+ * Enable creating X.509 certificates.
+ *
+ * Module:  library/x509_crt_write.c
+ *
+ * Requires: MBEDTLS_X509_CREATE_C
+ *
+ * This module is required for X.509 certificate creation.
+ */
+#define MBEDTLS_X509_CRT_WRITE_C
+
+/**
+ * \def MBEDTLS_X509_CSR_WRITE_C
+ *
+ * Enable creating X.509 Certificate Signing Requests (CSR).
+ *
+ * Module:  library/x509_csr_write.c
+ *
+ * Requires: MBEDTLS_X509_CREATE_C
+ *
+ * This module is required for X.509 certificate request writing.
+ */
+#define MBEDTLS_X509_CSR_WRITE_C
+
+/**
+ * \def MBEDTLS_XTEA_C
+ *
+ * Enable the XTEA block cipher.
+ *
+ * Module:  library/xtea.c
+ * Caller:
+ */
+#define MBEDTLS_XTEA_C
+
+/* \} name SECTION: mbed TLS modules */
+
+/**
+ * \name SECTION: Module configuration options
+ *
+ * This section allows for the setting of module specific sizes and
+ * configuration options. The default values are already present in the
+ * relevant header files and should suffice for the regular use cases.
+ *
+ * Our advice is to enable options and change their values here
+ * only if you have a good reason and know the consequences.
+ *
+ * Please check the respective header file for documentation on these
+ * parameters (to prevent duplicate documentation).
+ * \{
+ */
+
+/* MPI / BIGNUM options */
+//#define MBEDTLS_MPI_WINDOW_SIZE            6 /**< Maximum windows size used. */
+//#define MBEDTLS_MPI_MAX_SIZE            1024 /**< Maximum number of bytes for usable MPIs. */
+
+/* CTR_DRBG options */
+//#define MBEDTLS_CTR_DRBG_ENTROPY_LEN               48 /**< Amount of entropy used per seed by default (48 with SHA-512, 32 with SHA-256) */
+//#define MBEDTLS_CTR_DRBG_RESEED_INTERVAL        10000 /**< Interval before reseed is performed by default */
+//#define MBEDTLS_CTR_DRBG_MAX_INPUT                256 /**< Maximum number of additional input bytes */
+//#define MBEDTLS_CTR_DRBG_MAX_REQUEST             1024 /**< Maximum number of requested bytes per call */
+//#define MBEDTLS_CTR_DRBG_MAX_SEED_INPUT           384 /**< Maximum size of (re)seed buffer */
+
+/* HMAC_DRBG options */
+//#define MBEDTLS_HMAC_DRBG_RESEED_INTERVAL   10000 /**< Interval before reseed is performed by default */
+//#define MBEDTLS_HMAC_DRBG_MAX_INPUT           256 /**< Maximum number of additional input bytes */
+//#define MBEDTLS_HMAC_DRBG_MAX_REQUEST        1024 /**< Maximum number of requested bytes per call */
+//#define MBEDTLS_HMAC_DRBG_MAX_SEED_INPUT      384 /**< Maximum size of (re)seed buffer */
+
+/* ECP options */
+//#define MBEDTLS_ECP_MAX_BITS             521 /**< Maximum bit size of groups */
+//#define MBEDTLS_ECP_WINDOW_SIZE            6 /**< Maximum window size used */
+//#define MBEDTLS_ECP_FIXED_POINT_OPTIM      1 /**< Enable fixed-point speed-up */
+
+/* Entropy options */
+//#define MBEDTLS_ENTROPY_MAX_SOURCES                20 /**< Maximum number of sources supported */
+//#define MBEDTLS_ENTROPY_MAX_GATHER                128 /**< Maximum amount requested from entropy sources */
+
+/* Memory buffer allocator options */
+//#define MBEDTLS_MEMORY_ALIGN_MULTIPLE      4 /**< Align on multiples of this value */
+
+/* Platform options */
+//#define MBEDTLS_PLATFORM_STD_MEM_HDR    /**< Header to include if MBEDTLS_PLATFORM_NO_STD_FUNCTIONS is defined. Don't define if no header is needed. */
+//#define MBEDTLS_PLATFORM_STD_CALLOC        calloc /**< Default allocator to use, can be undefined */
+//#define MBEDTLS_PLATFORM_STD_FREE            free /**< Default free to use, can be undefined */
+//#define MBEDTLS_PLATFORM_STD_EXIT            exit /**< Default exit to use, can be undefined */
+//#define MBEDTLS_PLATFORM_STD_FPRINTF      fprintf /**< Default fprintf to use, can be undefined */
+//#define MBEDTLS_PLATFORM_STD_PRINTF        printf /**< Default printf to use, can be undefined */
+/* Note: your snprintf must correclty zero-terminate the buffer! */
+//#define MBEDTLS_PLATFORM_STD_SNPRINTF    snprintf /**< Default snprintf to use, can be undefined */
+
+/* To Use Function Macros MBEDTLS_PLATFORM_C must be enabled */
+/* MBEDTLS_PLATFORM_XXX_MACRO and MBEDTLS_PLATFORM_XXX_ALT cannot both be defined */
+//#define MBEDTLS_PLATFORM_CALLOC_MACRO        calloc /**< Default allocator macro to use, can be undefined */
+//#define MBEDTLS_PLATFORM_FREE_MACRO            free /**< Default free macro to use, can be undefined */
+//#define MBEDTLS_PLATFORM_EXIT_MACRO            exit /**< Default exit macro to use, can be undefined */
+//#define MBEDTLS_PLATFORM_FPRINTF_MACRO      fprintf /**< Default fprintf macro to use, can be undefined */
+//#define MBEDTLS_PLATFORM_PRINTF_MACRO        printf /**< Default printf macro to use, can be undefined */
+/* Note: your snprintf must correclty zero-terminate the buffer! */
+//#define MBEDTLS_PLATFORM_SNPRINTF_MACRO    snprintf /**< Default snprintf macro to use, can be undefined */
+
+/* SSL Cache options */
+//#define MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT       86400 /**< 1 day  */
+//#define MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES      50 /**< Maximum entries in cache */
+
+/* SSL options */
+
+#define MBEDTLS_SSL_MAX_CONTENT_LEN             CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN /**< Maxium fragment length in bytes, determines the size of each of the two internal I/O buffers */
+//#define MBEDTLS_SSL_DEFAULT_TICKET_LIFETIME     86400 /**< Lifetime of session tickets (if enabled) */
+//#define MBEDTLS_PSK_MAX_LEN               32 /**< Max size of TLS pre-shared keys, in bytes (default 256 bits) */
+//#define MBEDTLS_SSL_COOKIE_TIMEOUT        60 /**< Default expiration delay of DTLS cookies, in seconds if HAVE_TIME, or in number of cookies issued */
+
+/**
+ * Complete list of ciphersuites to use, in order of preference.
+ *
+ * \warning No dependency checking is done on that field! This option can only
+ * be used to restrict the set of available ciphersuites. It is your
+ * responsibility to make sure the needed modules are active.
+ *
+ * Use this to save a few hundred bytes of ROM (default ordering of all
+ * available ciphersuites) and a few to a few hundred bytes of RAM.
+ *
+ * The value below is only an example, not the default.
+ */
+//#define MBEDTLS_SSL_CIPHERSUITES MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384,MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256
+
+/* X509 options */
+//#define MBEDTLS_X509_MAX_INTERMEDIATE_CA   8   /**< Maximum number of intermediate CAs in a verification chain. */
+
+/* \} name SECTION: Module configuration options */
+
+#if defined(TARGET_LIKE_MBED)
+#include "mbedtls/target_config.h"
+#endif
+
+/*
+ * Allow user to override any previous default.
+ *
+ * Use two macro names for that, as:
+ * - with yotta the prefix YOTTA_CFG_ is forced
+ * - without yotta is looks weird to have a YOTTA prefix.
+ */
+#if defined(YOTTA_CFG_MBEDTLS_USER_CONFIG_FILE)
+#include YOTTA_CFG_MBEDTLS_USER_CONFIG_FILE
+#elif defined(MBEDTLS_USER_CONFIG_FILE)
+#include MBEDTLS_USER_CONFIG_FILE
+#endif
+
+#include "mbedtls/check_config.h"
+
+#endif /* MBEDTLS_CONFIG_H */
diff --git a/tools/sdk/include/mbedtls/mbedtls/gcm.h b/tools/sdk/include/mbedtls/mbedtls/gcm.h
new file mode 100644
index 00000000..6743ac9a
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/gcm.h
@@ -0,0 +1,220 @@
+/**
+ * \file gcm.h
+ *
+ * \brief Galois/Counter mode for 128-bit block ciphers
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_GCM_H
+#define MBEDTLS_GCM_H
+
+#include "cipher.h"
+
+#include 
+
+#define MBEDTLS_GCM_ENCRYPT     1
+#define MBEDTLS_GCM_DECRYPT     0
+
+#define MBEDTLS_ERR_GCM_AUTH_FAILED                       -0x0012  /**< Authenticated decryption failed. */
+#define MBEDTLS_ERR_GCM_BAD_INPUT                         -0x0014  /**< Bad input parameters to function. */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          GCM context structure
+ */
+typedef struct {
+    mbedtls_cipher_context_t cipher_ctx;/*!< cipher context used */
+    uint64_t HL[16];            /*!< Precalculated HTable */
+    uint64_t HH[16];            /*!< Precalculated HTable */
+    uint64_t len;               /*!< Total data length */
+    uint64_t add_len;           /*!< Total add length */
+    unsigned char base_ectr[16];/*!< First ECTR for tag */
+    unsigned char y[16];        /*!< Y working value */
+    unsigned char buf[16];      /*!< buf working value */
+    int mode;                   /*!< Encrypt or Decrypt */
+}
+mbedtls_gcm_context;
+
+/**
+ * \brief           Initialize GCM context (just makes references valid)
+ *                  Makes the context ready for mbedtls_gcm_setkey() or
+ *                  mbedtls_gcm_free().
+ *
+ * \param ctx       GCM context to initialize
+ */
+void mbedtls_gcm_init( mbedtls_gcm_context *ctx );
+
+/**
+ * \brief           GCM initialization (encryption)
+ *
+ * \param ctx       GCM context to be initialized
+ * \param cipher    cipher to use (a 128-bit block cipher)
+ * \param key       encryption key
+ * \param keybits   must be 128, 192 or 256
+ *
+ * \return          0 if successful, or a cipher specific error code
+ */
+int mbedtls_gcm_setkey( mbedtls_gcm_context *ctx,
+                        mbedtls_cipher_id_t cipher,
+                        const unsigned char *key,
+                        unsigned int keybits );
+
+/**
+ * \brief           GCM buffer encryption/decryption using a block cipher
+ *
+ * \note On encryption, the output buffer can be the same as the input buffer.
+ *       On decryption, the output buffer cannot be the same as input buffer.
+ *       If buffers overlap, the output buffer must trail at least 8 bytes
+ *       behind the input buffer.
+ *
+ * \param ctx       GCM context
+ * \param mode      MBEDTLS_GCM_ENCRYPT or MBEDTLS_GCM_DECRYPT
+ * \param length    length of the input data
+ * \param iv        initialization vector
+ * \param iv_len    length of IV
+ * \param add       additional data
+ * \param add_len   length of additional data
+ * \param input     buffer holding the input data
+ * \param output    buffer for holding the output data
+ * \param tag_len   length of the tag to generate
+ * \param tag       buffer for holding the tag
+ *
+ * \return         0 if successful
+ */
+int mbedtls_gcm_crypt_and_tag( mbedtls_gcm_context *ctx,
+                       int mode,
+                       size_t length,
+                       const unsigned char *iv,
+                       size_t iv_len,
+                       const unsigned char *add,
+                       size_t add_len,
+                       const unsigned char *input,
+                       unsigned char *output,
+                       size_t tag_len,
+                       unsigned char *tag );
+
+/**
+ * \brief           GCM buffer authenticated decryption using a block cipher
+ *
+ * \note On decryption, the output buffer cannot be the same as input buffer.
+ *       If buffers overlap, the output buffer must trail at least 8 bytes
+ *       behind the input buffer.
+ *
+ * \param ctx       GCM context
+ * \param length    length of the input data
+ * \param iv        initialization vector
+ * \param iv_len    length of IV
+ * \param add       additional data
+ * \param add_len   length of additional data
+ * \param tag       buffer holding the tag
+ * \param tag_len   length of the tag
+ * \param input     buffer holding the input data
+ * \param output    buffer for holding the output data
+ *
+ * \return         0 if successful and authenticated,
+ *                 MBEDTLS_ERR_GCM_AUTH_FAILED if tag does not match
+ */
+int mbedtls_gcm_auth_decrypt( mbedtls_gcm_context *ctx,
+                      size_t length,
+                      const unsigned char *iv,
+                      size_t iv_len,
+                      const unsigned char *add,
+                      size_t add_len,
+                      const unsigned char *tag,
+                      size_t tag_len,
+                      const unsigned char *input,
+                      unsigned char *output );
+
+/**
+ * \brief           Generic GCM stream start function
+ *
+ * \param ctx       GCM context
+ * \param mode      MBEDTLS_GCM_ENCRYPT or MBEDTLS_GCM_DECRYPT
+ * \param iv        initialization vector
+ * \param iv_len    length of IV
+ * \param add       additional data (or NULL if length is 0)
+ * \param add_len   length of additional data
+ *
+ * \return         0 if successful
+ */
+int mbedtls_gcm_starts( mbedtls_gcm_context *ctx,
+                int mode,
+                const unsigned char *iv,
+                size_t iv_len,
+                const unsigned char *add,
+                size_t add_len );
+
+/**
+ * \brief           Generic GCM update function. Encrypts/decrypts using the
+ *                  given GCM context. Expects input to be a multiple of 16
+ *                  bytes! Only the last call before mbedtls_gcm_finish() can be less
+ *                  than 16 bytes!
+ *
+ * \note On decryption, the output buffer cannot be the same as input buffer.
+ *       If buffers overlap, the output buffer must trail at least 8 bytes
+ *       behind the input buffer.
+ *
+ * \param ctx       GCM context
+ * \param length    length of the input data
+ * \param input     buffer holding the input data
+ * \param output    buffer for holding the output data
+ *
+ * \return         0 if successful or MBEDTLS_ERR_GCM_BAD_INPUT
+ */
+int mbedtls_gcm_update( mbedtls_gcm_context *ctx,
+                size_t length,
+                const unsigned char *input,
+                unsigned char *output );
+
+/**
+ * \brief           Generic GCM finalisation function. Wraps up the GCM stream
+ *                  and generates the tag. The tag can have a maximum length of
+ *                  16 bytes.
+ *
+ * \param ctx       GCM context
+ * \param tag       buffer for holding the tag (may be NULL if tag_len is 0)
+ * \param tag_len   length of the tag to generate
+ *
+ * \return          0 if successful or MBEDTLS_ERR_GCM_BAD_INPUT
+ */
+int mbedtls_gcm_finish( mbedtls_gcm_context *ctx,
+                unsigned char *tag,
+                size_t tag_len );
+
+/**
+ * \brief           Free a GCM context and underlying cipher sub-context
+ *
+ * \param ctx       GCM context to free
+ */
+void mbedtls_gcm_free( mbedtls_gcm_context *ctx );
+
+/**
+ * \brief          Checkup routine
+ *
+ * \return         0 if successful, or 1 if the test failed
+ */
+int mbedtls_gcm_self_test( int verbose );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* gcm.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/havege.h b/tools/sdk/include/mbedtls/mbedtls/havege.h
new file mode 100644
index 00000000..dac5d311
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/havege.h
@@ -0,0 +1,74 @@
+/**
+ * \file havege.h
+ *
+ * \brief HAVEGE: HArdware Volatile Entropy Gathering and Expansion
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_HAVEGE_H
+#define MBEDTLS_HAVEGE_H
+
+#include 
+
+#define MBEDTLS_HAVEGE_COLLECT_SIZE 1024
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          HAVEGE state structure
+ */
+typedef struct
+{
+    int PT1, PT2, offset[2];
+    int pool[MBEDTLS_HAVEGE_COLLECT_SIZE];
+    int WALK[8192];
+}
+mbedtls_havege_state;
+
+/**
+ * \brief          HAVEGE initialization
+ *
+ * \param hs       HAVEGE state to be initialized
+ */
+void mbedtls_havege_init( mbedtls_havege_state *hs );
+
+/**
+ * \brief          Clear HAVEGE state
+ *
+ * \param hs       HAVEGE state to be cleared
+ */
+void mbedtls_havege_free( mbedtls_havege_state *hs );
+
+/**
+ * \brief          HAVEGE rand function
+ *
+ * \param p_rng    A HAVEGE state
+ * \param output   Buffer to fill
+ * \param len      Length of buffer
+ *
+ * \return         0
+ */
+int mbedtls_havege_random( void *p_rng, unsigned char *output, size_t len );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* havege.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/hmac_drbg.h b/tools/sdk/include/mbedtls/mbedtls/hmac_drbg.h
new file mode 100644
index 00000000..e0105580
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/hmac_drbg.h
@@ -0,0 +1,299 @@
+/**
+ * \file hmac_drbg.h
+ *
+ * \brief HMAC_DRBG (NIST SP 800-90A)
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_HMAC_DRBG_H
+#define MBEDTLS_HMAC_DRBG_H
+
+#include "md.h"
+
+#if defined(MBEDTLS_THREADING_C)
+#include "mbedtls/threading.h"
+#endif
+
+/*
+ * Error codes
+ */
+#define MBEDTLS_ERR_HMAC_DRBG_REQUEST_TOO_BIG              -0x0003  /**< Too many random requested in single call. */
+#define MBEDTLS_ERR_HMAC_DRBG_INPUT_TOO_BIG                -0x0005  /**< Input too large (Entropy + additional). */
+#define MBEDTLS_ERR_HMAC_DRBG_FILE_IO_ERROR                -0x0007  /**< Read/write error in file. */
+#define MBEDTLS_ERR_HMAC_DRBG_ENTROPY_SOURCE_FAILED        -0x0009  /**< The entropy source failed. */
+
+/**
+ * \name SECTION: Module settings
+ *
+ * The configuration options you can set for this module are in this section.
+ * Either change them in config.h or define them on the compiler command line.
+ * \{
+ */
+
+#if !defined(MBEDTLS_HMAC_DRBG_RESEED_INTERVAL)
+#define MBEDTLS_HMAC_DRBG_RESEED_INTERVAL   10000   /**< Interval before reseed is performed by default */
+#endif
+
+#if !defined(MBEDTLS_HMAC_DRBG_MAX_INPUT)
+#define MBEDTLS_HMAC_DRBG_MAX_INPUT         256     /**< Maximum number of additional input bytes */
+#endif
+
+#if !defined(MBEDTLS_HMAC_DRBG_MAX_REQUEST)
+#define MBEDTLS_HMAC_DRBG_MAX_REQUEST       1024    /**< Maximum number of requested bytes per call */
+#endif
+
+#if !defined(MBEDTLS_HMAC_DRBG_MAX_SEED_INPUT)
+#define MBEDTLS_HMAC_DRBG_MAX_SEED_INPUT    384     /**< Maximum size of (re)seed buffer */
+#endif
+
+/* \} name SECTION: Module settings */
+
+#define MBEDTLS_HMAC_DRBG_PR_OFF   0   /**< No prediction resistance       */
+#define MBEDTLS_HMAC_DRBG_PR_ON    1   /**< Prediction resistance enabled  */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * HMAC_DRBG context.
+ */
+typedef struct
+{
+    /* Working state: the key K is not stored explicitely,
+     * but is implied by the HMAC context */
+    mbedtls_md_context_t md_ctx;                    /*!< HMAC context (inc. K)  */
+    unsigned char V[MBEDTLS_MD_MAX_SIZE];  /*!< V in the spec          */
+    int reseed_counter;                     /*!< reseed counter         */
+
+    /* Administrative state */
+    size_t entropy_len;         /*!< entropy bytes grabbed on each (re)seed */
+    int prediction_resistance;  /*!< enable prediction resistance (Automatic
+                                     reseed before every random generation) */
+    int reseed_interval;        /*!< reseed interval   */
+
+    /* Callbacks */
+    int (*f_entropy)(void *, unsigned char *, size_t); /*!< entropy function */
+    void *p_entropy;            /*!< context for the entropy function        */
+
+#if defined(MBEDTLS_THREADING_C)
+    mbedtls_threading_mutex_t mutex;
+#endif
+} mbedtls_hmac_drbg_context;
+
+/**
+ * \brief               HMAC_DRBG context initialization
+ *                      Makes the context ready for mbedtls_hmac_drbg_seed(),
+ *                      mbedtls_hmac_drbg_seed_buf() or
+ *                      mbedtls_hmac_drbg_free().
+ *
+ * \param ctx           HMAC_DRBG context to be initialized
+ */
+void mbedtls_hmac_drbg_init( mbedtls_hmac_drbg_context *ctx );
+
+/**
+ * \brief               HMAC_DRBG initial seeding
+ *                      Seed and setup entropy source for future reseeds.
+ *
+ * \param ctx           HMAC_DRBG context to be seeded
+ * \param md_info       MD algorithm to use for HMAC_DRBG
+ * \param f_entropy     Entropy callback (p_entropy, buffer to fill, buffer
+ *                      length)
+ * \param p_entropy     Entropy context
+ * \param custom        Personalization data (Device specific identifiers)
+ *                      (Can be NULL)
+ * \param len           Length of personalization data
+ *
+ * \note                The "security strength" as defined by NIST is set to:
+ *                      128 bits if md_alg is SHA-1,
+ *                      192 bits if md_alg is SHA-224,
+ *                      256 bits if md_alg is SHA-256 or higher.
+ *                      Note that SHA-256 is just as efficient as SHA-224.
+ *
+ * \return              0 if successful, or
+ *                      MBEDTLS_ERR_MD_BAD_INPUT_DATA, or
+ *                      MBEDTLS_ERR_MD_ALLOC_FAILED, or
+ *                      MBEDTLS_ERR_HMAC_DRBG_ENTROPY_SOURCE_FAILED.
+ */
+int mbedtls_hmac_drbg_seed( mbedtls_hmac_drbg_context *ctx,
+                    const mbedtls_md_info_t * md_info,
+                    int (*f_entropy)(void *, unsigned char *, size_t),
+                    void *p_entropy,
+                    const unsigned char *custom,
+                    size_t len );
+
+/**
+ * \brief               Initilisation of simpified HMAC_DRBG (never reseeds).
+ *                      (For use with deterministic ECDSA.)
+ *
+ * \param ctx           HMAC_DRBG context to be initialised
+ * \param md_info       MD algorithm to use for HMAC_DRBG
+ * \param data          Concatenation of entropy string and additional data
+ * \param data_len      Length of data in bytes
+ *
+ * \return              0 if successful, or
+ *                      MBEDTLS_ERR_MD_BAD_INPUT_DATA, or
+ *                      MBEDTLS_ERR_MD_ALLOC_FAILED.
+ */
+int mbedtls_hmac_drbg_seed_buf( mbedtls_hmac_drbg_context *ctx,
+                        const mbedtls_md_info_t * md_info,
+                        const unsigned char *data, size_t data_len );
+
+/**
+ * \brief               Enable / disable prediction resistance (Default: Off)
+ *
+ * Note: If enabled, entropy is used for ctx->entropy_len before each call!
+ *       Only use this if you have ample supply of good entropy!
+ *
+ * \param ctx           HMAC_DRBG context
+ * \param resistance    MBEDTLS_HMAC_DRBG_PR_ON or MBEDTLS_HMAC_DRBG_PR_OFF
+ */
+void mbedtls_hmac_drbg_set_prediction_resistance( mbedtls_hmac_drbg_context *ctx,
+                                          int resistance );
+
+/**
+ * \brief               Set the amount of entropy grabbed on each reseed
+ *                      (Default: given by the security strength, which
+ *                      depends on the hash used, see \c mbedtls_hmac_drbg_init() )
+ *
+ * \param ctx           HMAC_DRBG context
+ * \param len           Amount of entropy to grab, in bytes
+ */
+void mbedtls_hmac_drbg_set_entropy_len( mbedtls_hmac_drbg_context *ctx,
+                                size_t len );
+
+/**
+ * \brief               Set the reseed interval
+ *                      (Default: MBEDTLS_HMAC_DRBG_RESEED_INTERVAL)
+ *
+ * \param ctx           HMAC_DRBG context
+ * \param interval      Reseed interval
+ */
+void mbedtls_hmac_drbg_set_reseed_interval( mbedtls_hmac_drbg_context *ctx,
+                                    int interval );
+
+/**
+ * \brief               HMAC_DRBG update state
+ *
+ * \param ctx           HMAC_DRBG context
+ * \param additional    Additional data to update state with, or NULL
+ * \param add_len       Length of additional data, or 0
+ *
+ * \note                Additional data is optional, pass NULL and 0 as second
+ *                      third argument if no additional data is being used.
+ */
+void mbedtls_hmac_drbg_update( mbedtls_hmac_drbg_context *ctx,
+                       const unsigned char *additional, size_t add_len );
+
+/**
+ * \brief               HMAC_DRBG reseeding (extracts data from entropy source)
+ *
+ * \param ctx           HMAC_DRBG context
+ * \param additional    Additional data to add to state (Can be NULL)
+ * \param len           Length of additional data
+ *
+ * \return              0 if successful, or
+ *                      MBEDTLS_ERR_HMAC_DRBG_ENTROPY_SOURCE_FAILED
+ */
+int mbedtls_hmac_drbg_reseed( mbedtls_hmac_drbg_context *ctx,
+                      const unsigned char *additional, size_t len );
+
+/**
+ * \brief               HMAC_DRBG generate random with additional update input
+ *
+ * Note: Automatically reseeds if reseed_counter is reached or PR is enabled.
+ *
+ * \param p_rng         HMAC_DRBG context
+ * \param output        Buffer to fill
+ * \param output_len    Length of the buffer
+ * \param additional    Additional data to update with (can be NULL)
+ * \param add_len       Length of additional data (can be 0)
+ *
+ * \return              0 if successful, or
+ *                      MBEDTLS_ERR_HMAC_DRBG_ENTROPY_SOURCE_FAILED, or
+ *                      MBEDTLS_ERR_HMAC_DRBG_REQUEST_TOO_BIG, or
+ *                      MBEDTLS_ERR_HMAC_DRBG_INPUT_TOO_BIG.
+ */
+int mbedtls_hmac_drbg_random_with_add( void *p_rng,
+                               unsigned char *output, size_t output_len,
+                               const unsigned char *additional,
+                               size_t add_len );
+
+/**
+ * \brief               HMAC_DRBG generate random
+ *
+ * Note: Automatically reseeds if reseed_counter is reached or PR is enabled.
+ *
+ * \param p_rng         HMAC_DRBG context
+ * \param output        Buffer to fill
+ * \param out_len       Length of the buffer
+ *
+ * \return              0 if successful, or
+ *                      MBEDTLS_ERR_HMAC_DRBG_ENTROPY_SOURCE_FAILED, or
+ *                      MBEDTLS_ERR_HMAC_DRBG_REQUEST_TOO_BIG
+ */
+int mbedtls_hmac_drbg_random( void *p_rng, unsigned char *output, size_t out_len );
+
+/**
+ * \brief               Free an HMAC_DRBG context
+ *
+ * \param ctx           HMAC_DRBG context to free.
+ */
+void mbedtls_hmac_drbg_free( mbedtls_hmac_drbg_context *ctx );
+
+#if defined(MBEDTLS_FS_IO)
+/**
+ * \brief               Write a seed file
+ *
+ * \param ctx           HMAC_DRBG context
+ * \param path          Name of the file
+ *
+ * \return              0 if successful, 1 on file error, or
+ *                      MBEDTLS_ERR_HMAC_DRBG_ENTROPY_SOURCE_FAILED
+ */
+int mbedtls_hmac_drbg_write_seed_file( mbedtls_hmac_drbg_context *ctx, const char *path );
+
+/**
+ * \brief               Read and update a seed file. Seed is added to this
+ *                      instance
+ *
+ * \param ctx           HMAC_DRBG context
+ * \param path          Name of the file
+ *
+ * \return              0 if successful, 1 on file error,
+ *                      MBEDTLS_ERR_HMAC_DRBG_ENTROPY_SOURCE_FAILED or
+ *                      MBEDTLS_ERR_HMAC_DRBG_INPUT_TOO_BIG
+ */
+int mbedtls_hmac_drbg_update_seed_file( mbedtls_hmac_drbg_context *ctx, const char *path );
+#endif /* MBEDTLS_FS_IO */
+
+
+#if defined(MBEDTLS_SELF_TEST)
+/**
+ * \brief               Checkup routine
+ *
+ * \return              0 if successful, or 1 if the test failed
+ */
+int mbedtls_hmac_drbg_self_test( int verbose );
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* hmac_drbg.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/md.h b/tools/sdk/include/mbedtls/mbedtls/md.h
new file mode 100644
index 00000000..b9023553
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/md.h
@@ -0,0 +1,353 @@
+/**
+ * \file md.h
+ *
+ * \brief Generic message digest wrapper
+ *
+ * \author Adriaan de Jong 
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_MD_H
+#define MBEDTLS_MD_H
+
+#include 
+
+#define MBEDTLS_ERR_MD_FEATURE_UNAVAILABLE                -0x5080  /**< The selected feature is not available. */
+#define MBEDTLS_ERR_MD_BAD_INPUT_DATA                     -0x5100  /**< Bad input parameters to function. */
+#define MBEDTLS_ERR_MD_ALLOC_FAILED                       -0x5180  /**< Failed to allocate memory. */
+#define MBEDTLS_ERR_MD_FILE_IO_ERROR                      -0x5200  /**< Opening or reading of file failed. */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    MBEDTLS_MD_NONE=0,
+    MBEDTLS_MD_MD2,
+    MBEDTLS_MD_MD4,
+    MBEDTLS_MD_MD5,
+    MBEDTLS_MD_SHA1,
+    MBEDTLS_MD_SHA224,
+    MBEDTLS_MD_SHA256,
+    MBEDTLS_MD_SHA384,
+    MBEDTLS_MD_SHA512,
+    MBEDTLS_MD_RIPEMD160,
+} mbedtls_md_type_t;
+
+#if defined(MBEDTLS_SHA512_C)
+#define MBEDTLS_MD_MAX_SIZE         64  /* longest known is SHA512 */
+#else
+#define MBEDTLS_MD_MAX_SIZE         32  /* longest known is SHA256 or less */
+#endif
+
+/**
+ * Opaque struct defined in md_internal.h
+ */
+typedef struct mbedtls_md_info_t mbedtls_md_info_t;
+
+/**
+ * Generic message digest context.
+ */
+typedef struct {
+    /** Information about the associated message digest */
+    const mbedtls_md_info_t *md_info;
+
+    /** Digest-specific context */
+    void *md_ctx;
+
+    /** HMAC part of the context */
+    void *hmac_ctx;
+} mbedtls_md_context_t;
+
+/**
+ * \brief Returns the list of digests supported by the generic digest module.
+ *
+ * \return          a statically allocated array of digests, the last entry
+ *                  is 0.
+ */
+const int *mbedtls_md_list( void );
+
+/**
+ * \brief           Returns the message digest information associated with the
+ *                  given digest name.
+ *
+ * \param md_name   Name of the digest to search for.
+ *
+ * \return          The message digest information associated with md_name or
+ *                  NULL if not found.
+ */
+const mbedtls_md_info_t *mbedtls_md_info_from_string( const char *md_name );
+
+/**
+ * \brief           Returns the message digest information associated with the
+ *                  given digest type.
+ *
+ * \param md_type   type of digest to search for.
+ *
+ * \return          The message digest information associated with md_type or
+ *                  NULL if not found.
+ */
+const mbedtls_md_info_t *mbedtls_md_info_from_type( mbedtls_md_type_t md_type );
+
+/**
+ * \brief           Initialize a md_context (as NONE)
+ *                  This should always be called first.
+ *                  Prepares the context for mbedtls_md_setup() or mbedtls_md_free().
+ */
+void mbedtls_md_init( mbedtls_md_context_t *ctx );
+
+/**
+ * \brief           Free and clear the internal structures of ctx.
+ *                  Can be called at any time after mbedtls_md_init().
+ *                  Mandatory once mbedtls_md_setup() has been called.
+ */
+void mbedtls_md_free( mbedtls_md_context_t *ctx );
+
+#if ! defined(MBEDTLS_DEPRECATED_REMOVED)
+#if defined(MBEDTLS_DEPRECATED_WARNING)
+#define MBEDTLS_DEPRECATED    __attribute__((deprecated))
+#else
+#define MBEDTLS_DEPRECATED
+#endif
+/**
+ * \brief           Select MD to use and allocate internal structures.
+ *                  Should be called after mbedtls_md_init() or mbedtls_md_free().
+ *                  Makes it necessary to call mbedtls_md_free() later.
+ *
+ * \deprecated      Superseded by mbedtls_md_setup() in 2.0.0
+ *
+ * \param ctx       Context to set up.
+ * \param md_info   Message digest to use.
+ *
+ * \returns         \c 0 on success,
+ *                  \c MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter failure,
+ *                  \c MBEDTLS_ERR_MD_ALLOC_FAILED memory allocation failure.
+ */
+int mbedtls_md_init_ctx( mbedtls_md_context_t *ctx, const mbedtls_md_info_t *md_info ) MBEDTLS_DEPRECATED;
+#undef MBEDTLS_DEPRECATED
+#endif /* MBEDTLS_DEPRECATED_REMOVED */
+
+/**
+ * \brief           Select MD to use and allocate internal structures.
+ *                  Should be called after mbedtls_md_init() or mbedtls_md_free().
+ *                  Makes it necessary to call mbedtls_md_free() later.
+ *
+ * \param ctx       Context to set up.
+ * \param md_info   Message digest to use.
+ * \param hmac      0 to save some memory if HMAC will not be used,
+ *                  non-zero is HMAC is going to be used with this context.
+ *
+ * \returns         \c 0 on success,
+ *                  \c MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter failure,
+ *                  \c MBEDTLS_ERR_MD_ALLOC_FAILED memory allocation failure.
+ */
+int mbedtls_md_setup( mbedtls_md_context_t *ctx, const mbedtls_md_info_t *md_info, int hmac );
+
+/**
+ * \brief           Clone the state of an MD context
+ *
+ * \note            The two contexts must have been setup to the same type
+ *                  (cloning from SHA-256 to SHA-512 make no sense).
+ *
+ * \warning         Only clones the MD state, not the HMAC state! (for now)
+ *
+ * \param dst       The destination context
+ * \param src       The context to be cloned
+ *
+ * \return          \c 0 on success,
+ *                  \c MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter failure.
+ */
+int mbedtls_md_clone( mbedtls_md_context_t *dst,
+                      const mbedtls_md_context_t *src );
+
+/**
+ * \brief           Returns the size of the message digest output.
+ *
+ * \param md_info   message digest info
+ *
+ * \return          size of the message digest output in bytes.
+ */
+unsigned char mbedtls_md_get_size( const mbedtls_md_info_t *md_info );
+
+/**
+ * \brief           Returns the type of the message digest output.
+ *
+ * \param md_info   message digest info
+ *
+ * \return          type of the message digest output.
+ */
+mbedtls_md_type_t mbedtls_md_get_type( const mbedtls_md_info_t *md_info );
+
+/**
+ * \brief           Returns the name of the message digest output.
+ *
+ * \param md_info   message digest info
+ *
+ * \return          name of the message digest output.
+ */
+const char *mbedtls_md_get_name( const mbedtls_md_info_t *md_info );
+
+/**
+ * \brief           Prepare the context to digest a new message.
+ *                  Generally called after mbedtls_md_setup() or mbedtls_md_finish().
+ *                  Followed by mbedtls_md_update().
+ *
+ * \param ctx       generic message digest context.
+ *
+ * \returns         0 on success, MBEDTLS_ERR_MD_BAD_INPUT_DATA if parameter
+ *                  verification fails.
+ */
+int mbedtls_md_starts( mbedtls_md_context_t *ctx );
+
+/**
+ * \brief           Generic message digest process buffer
+ *                  Called between mbedtls_md_starts() and mbedtls_md_finish().
+ *                  May be called repeatedly.
+ *
+ * \param ctx       Generic message digest context
+ * \param input     buffer holding the  datal
+ * \param ilen      length of the input data
+ *
+ * \returns         0 on success, MBEDTLS_ERR_MD_BAD_INPUT_DATA if parameter
+ *                  verification fails.
+ */
+int mbedtls_md_update( mbedtls_md_context_t *ctx, const unsigned char *input, size_t ilen );
+
+/**
+ * \brief           Generic message digest final digest
+ *                  Called after mbedtls_md_update().
+ *                  Usually followed by mbedtls_md_free() or mbedtls_md_starts().
+ *
+ * \param ctx       Generic message digest context
+ * \param output    Generic message digest checksum result
+ *
+ * \returns         0 on success, MBEDTLS_ERR_MD_BAD_INPUT_DATA if parameter
+ *                  verification fails.
+ */
+int mbedtls_md_finish( mbedtls_md_context_t *ctx, unsigned char *output );
+
+/**
+ * \brief          Output = message_digest( input buffer )
+ *
+ * \param md_info  message digest info
+ * \param input    buffer holding the  data
+ * \param ilen     length of the input data
+ * \param output   Generic message digest checksum result
+ *
+ * \returns        0 on success, MBEDTLS_ERR_MD_BAD_INPUT_DATA if parameter
+ *                 verification fails.
+ */
+int mbedtls_md( const mbedtls_md_info_t *md_info, const unsigned char *input, size_t ilen,
+        unsigned char *output );
+
+#if defined(MBEDTLS_FS_IO)
+/**
+ * \brief          Output = message_digest( file contents )
+ *
+ * \param md_info  message digest info
+ * \param path     input file name
+ * \param output   generic message digest checksum result
+ *
+ * \return         0 if successful,
+ *                 MBEDTLS_ERR_MD_FILE_IO_ERROR if file input failed,
+ *                 MBEDTLS_ERR_MD_BAD_INPUT_DATA if md_info was NULL.
+ */
+int mbedtls_md_file( const mbedtls_md_info_t *md_info, const char *path,
+                     unsigned char *output );
+#endif /* MBEDTLS_FS_IO */
+
+/**
+ * \brief           Set HMAC key and prepare to authenticate a new message.
+ *                  Usually called after mbedtls_md_setup() or mbedtls_md_hmac_finish().
+ *
+ * \param ctx       HMAC context
+ * \param key       HMAC secret key
+ * \param keylen    length of the HMAC key in bytes
+ *
+ * \returns         0 on success, MBEDTLS_ERR_MD_BAD_INPUT_DATA if parameter
+ *                  verification fails.
+ */
+int mbedtls_md_hmac_starts( mbedtls_md_context_t *ctx, const unsigned char *key,
+                    size_t keylen );
+
+/**
+ * \brief           Generic HMAC process buffer.
+ *                  Called between mbedtls_md_hmac_starts() or mbedtls_md_hmac_reset()
+ *                  and mbedtls_md_hmac_finish().
+ *                  May be called repeatedly.
+ *
+ * \param ctx       HMAC context
+ * \param input     buffer holding the  data
+ * \param ilen      length of the input data
+ *
+ * \returns         0 on success, MBEDTLS_ERR_MD_BAD_INPUT_DATA if parameter
+ *                  verification fails.
+ */
+int mbedtls_md_hmac_update( mbedtls_md_context_t *ctx, const unsigned char *input,
+                    size_t ilen );
+
+/**
+ * \brief           Output HMAC.
+ *                  Called after mbedtls_md_hmac_update().
+ *                  Usually followed my mbedtls_md_hmac_reset(), mbedtls_md_hmac_starts(),
+ *                  or mbedtls_md_free().
+ *
+ * \param ctx       HMAC context
+ * \param output    Generic HMAC checksum result
+ *
+ * \returns         0 on success, MBEDTLS_ERR_MD_BAD_INPUT_DATA if parameter
+ *                  verification fails.
+ */
+int mbedtls_md_hmac_finish( mbedtls_md_context_t *ctx, unsigned char *output);
+
+/**
+ * \brief           Prepare to authenticate a new message with the same key.
+ *                  Called after mbedtls_md_hmac_finish() and before mbedtls_md_hmac_update().
+ *
+ * \param ctx       HMAC context to be reset
+ *
+ * \returns         0 on success, MBEDTLS_ERR_MD_BAD_INPUT_DATA if parameter
+ *                  verification fails.
+ */
+int mbedtls_md_hmac_reset( mbedtls_md_context_t *ctx );
+
+/**
+ * \brief          Output = Generic_HMAC( hmac key, input buffer )
+ *
+ * \param md_info  message digest info
+ * \param key      HMAC secret key
+ * \param keylen   length of the HMAC key in bytes
+ * \param input    buffer holding the  data
+ * \param ilen     length of the input data
+ * \param output   Generic HMAC-result
+ *
+ * \returns        0 on success, MBEDTLS_ERR_MD_BAD_INPUT_DATA if parameter
+ *                 verification fails.
+ */
+int mbedtls_md_hmac( const mbedtls_md_info_t *md_info, const unsigned char *key, size_t keylen,
+                const unsigned char *input, size_t ilen,
+                unsigned char *output );
+
+/* Internal use */
+int mbedtls_md_process( mbedtls_md_context_t *ctx, const unsigned char *data );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MBEDTLS_MD_H */
diff --git a/tools/sdk/include/mbedtls/mbedtls/md2.h b/tools/sdk/include/mbedtls/mbedtls/md2.h
new file mode 100644
index 00000000..0f93fbf4
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/md2.h
@@ -0,0 +1,136 @@
+/**
+ * \file md2.h
+ *
+ * \brief MD2 message digest algorithm (hash function)
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_MD2_H
+#define MBEDTLS_MD2_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#include 
+
+#if !defined(MBEDTLS_MD2_ALT)
+// Regular implementation
+//
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          MD2 context structure
+ */
+typedef struct
+{
+    unsigned char cksum[16];    /*!< checksum of the data block */
+    unsigned char state[48];    /*!< intermediate digest state  */
+    unsigned char buffer[16];   /*!< data block being processed */
+    size_t left;                /*!< amount of data in buffer   */
+}
+mbedtls_md2_context;
+
+/**
+ * \brief          Initialize MD2 context
+ *
+ * \param ctx      MD2 context to be initialized
+ */
+void mbedtls_md2_init( mbedtls_md2_context *ctx );
+
+/**
+ * \brief          Clear MD2 context
+ *
+ * \param ctx      MD2 context to be cleared
+ */
+void mbedtls_md2_free( mbedtls_md2_context *ctx );
+
+/**
+ * \brief          Clone (the state of) an MD2 context
+ *
+ * \param dst      The destination context
+ * \param src      The context to be cloned
+ */
+void mbedtls_md2_clone( mbedtls_md2_context *dst,
+                        const mbedtls_md2_context *src );
+
+/**
+ * \brief          MD2 context setup
+ *
+ * \param ctx      context to be initialized
+ */
+void mbedtls_md2_starts( mbedtls_md2_context *ctx );
+
+/**
+ * \brief          MD2 process buffer
+ *
+ * \param ctx      MD2 context
+ * \param input    buffer holding the  data
+ * \param ilen     length of the input data
+ */
+void mbedtls_md2_update( mbedtls_md2_context *ctx, const unsigned char *input, size_t ilen );
+
+/**
+ * \brief          MD2 final digest
+ *
+ * \param ctx      MD2 context
+ * \param output   MD2 checksum result
+ */
+void mbedtls_md2_finish( mbedtls_md2_context *ctx, unsigned char output[16] );
+
+#ifdef __cplusplus
+}
+#endif
+
+#else  /* MBEDTLS_MD2_ALT */
+#include "md2_alt.h"
+#endif /* MBEDTLS_MD2_ALT */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          Output = MD2( input buffer )
+ *
+ * \param input    buffer holding the  data
+ * \param ilen     length of the input data
+ * \param output   MD2 checksum result
+ */
+void mbedtls_md2( const unsigned char *input, size_t ilen, unsigned char output[16] );
+
+/**
+ * \brief          Checkup routine
+ *
+ * \return         0 if successful, or 1 if the test failed
+ */
+int mbedtls_md2_self_test( int verbose );
+
+/* Internal use */
+void mbedtls_md2_process( mbedtls_md2_context *ctx );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* mbedtls_md2.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/md4.h b/tools/sdk/include/mbedtls/mbedtls/md4.h
new file mode 100644
index 00000000..45214d41
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/md4.h
@@ -0,0 +1,136 @@
+/**
+ * \file md4.h
+ *
+ * \brief MD4 message digest algorithm (hash function)
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_MD4_H
+#define MBEDTLS_MD4_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#include 
+#include 
+
+#if !defined(MBEDTLS_MD4_ALT)
+// Regular implementation
+//
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          MD4 context structure
+ */
+typedef struct
+{
+    uint32_t total[2];          /*!< number of bytes processed  */
+    uint32_t state[4];          /*!< intermediate digest state  */
+    unsigned char buffer[64];   /*!< data block being processed */
+}
+mbedtls_md4_context;
+
+/**
+ * \brief          Initialize MD4 context
+ *
+ * \param ctx      MD4 context to be initialized
+ */
+void mbedtls_md4_init( mbedtls_md4_context *ctx );
+
+/**
+ * \brief          Clear MD4 context
+ *
+ * \param ctx      MD4 context to be cleared
+ */
+void mbedtls_md4_free( mbedtls_md4_context *ctx );
+
+/**
+ * \brief          Clone (the state of) an MD4 context
+ *
+ * \param dst      The destination context
+ * \param src      The context to be cloned
+ */
+void mbedtls_md4_clone( mbedtls_md4_context *dst,
+                        const mbedtls_md4_context *src );
+
+/**
+ * \brief          MD4 context setup
+ *
+ * \param ctx      context to be initialized
+ */
+void mbedtls_md4_starts( mbedtls_md4_context *ctx );
+
+/**
+ * \brief          MD4 process buffer
+ *
+ * \param ctx      MD4 context
+ * \param input    buffer holding the  data
+ * \param ilen     length of the input data
+ */
+void mbedtls_md4_update( mbedtls_md4_context *ctx, const unsigned char *input, size_t ilen );
+
+/**
+ * \brief          MD4 final digest
+ *
+ * \param ctx      MD4 context
+ * \param output   MD4 checksum result
+ */
+void mbedtls_md4_finish( mbedtls_md4_context *ctx, unsigned char output[16] );
+
+#ifdef __cplusplus
+}
+#endif
+
+#else  /* MBEDTLS_MD4_ALT */
+#include "md4_alt.h"
+#endif /* MBEDTLS_MD4_ALT */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          Output = MD4( input buffer )
+ *
+ * \param input    buffer holding the  data
+ * \param ilen     length of the input data
+ * \param output   MD4 checksum result
+ */
+void mbedtls_md4( const unsigned char *input, size_t ilen, unsigned char output[16] );
+
+/**
+ * \brief          Checkup routine
+ *
+ * \return         0 if successful, or 1 if the test failed
+ */
+int mbedtls_md4_self_test( int verbose );
+
+/* Internal use */
+void mbedtls_md4_process( mbedtls_md4_context *ctx, const unsigned char data[64] );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* mbedtls_md4.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/md5.h b/tools/sdk/include/mbedtls/mbedtls/md5.h
new file mode 100644
index 00000000..5a64061a
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/md5.h
@@ -0,0 +1,136 @@
+/**
+ * \file md5.h
+ *
+ * \brief MD5 message digest algorithm (hash function)
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_MD5_H
+#define MBEDTLS_MD5_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#include 
+#include 
+
+#if !defined(MBEDTLS_MD5_ALT)
+// Regular implementation
+//
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          MD5 context structure
+ */
+typedef struct
+{
+    uint32_t total[2];          /*!< number of bytes processed  */
+    uint32_t state[4];          /*!< intermediate digest state  */
+    unsigned char buffer[64];   /*!< data block being processed */
+}
+mbedtls_md5_context;
+
+/**
+ * \brief          Initialize MD5 context
+ *
+ * \param ctx      MD5 context to be initialized
+ */
+void mbedtls_md5_init( mbedtls_md5_context *ctx );
+
+/**
+ * \brief          Clear MD5 context
+ *
+ * \param ctx      MD5 context to be cleared
+ */
+void mbedtls_md5_free( mbedtls_md5_context *ctx );
+
+/**
+ * \brief          Clone (the state of) an MD5 context
+ *
+ * \param dst      The destination context
+ * \param src      The context to be cloned
+ */
+void mbedtls_md5_clone( mbedtls_md5_context *dst,
+                        const mbedtls_md5_context *src );
+
+/**
+ * \brief          MD5 context setup
+ *
+ * \param ctx      context to be initialized
+ */
+void mbedtls_md5_starts( mbedtls_md5_context *ctx );
+
+/**
+ * \brief          MD5 process buffer
+ *
+ * \param ctx      MD5 context
+ * \param input    buffer holding the  data
+ * \param ilen     length of the input data
+ */
+void mbedtls_md5_update( mbedtls_md5_context *ctx, const unsigned char *input, size_t ilen );
+
+/**
+ * \brief          MD5 final digest
+ *
+ * \param ctx      MD5 context
+ * \param output   MD5 checksum result
+ */
+void mbedtls_md5_finish( mbedtls_md5_context *ctx, unsigned char output[16] );
+
+/* Internal use */
+void mbedtls_md5_process( mbedtls_md5_context *ctx, const unsigned char data[64] );
+
+#ifdef __cplusplus
+}
+#endif
+
+#else  /* MBEDTLS_MD5_ALT */
+#include "md5_alt.h"
+#endif /* MBEDTLS_MD5_ALT */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          Output = MD5( input buffer )
+ *
+ * \param input    buffer holding the  data
+ * \param ilen     length of the input data
+ * \param output   MD5 checksum result
+ */
+void mbedtls_md5( const unsigned char *input, size_t ilen, unsigned char output[16] );
+
+/**
+ * \brief          Checkup routine
+ *
+ * \return         0 if successful, or 1 if the test failed
+ */
+int mbedtls_md5_self_test( int verbose );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* mbedtls_md5.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/md_internal.h b/tools/sdk/include/mbedtls/mbedtls/md_internal.h
new file mode 100644
index 00000000..e2441bbc
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/md_internal.h
@@ -0,0 +1,114 @@
+/**
+ * \file md_internal.h
+ *
+ * \brief Message digest wrappers.
+ *
+ * \warning This in an internal header. Do not include directly.
+ *
+ * \author Adriaan de Jong 
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_MD_WRAP_H
+#define MBEDTLS_MD_WRAP_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#include "md.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Message digest information.
+ * Allows message digest functions to be called in a generic way.
+ */
+struct mbedtls_md_info_t
+{
+    /** Digest identifier */
+    mbedtls_md_type_t type;
+
+    /** Name of the message digest */
+    const char * name;
+
+    /** Output length of the digest function in bytes */
+    int size;
+
+    /** Block length of the digest function in bytes */
+    int block_size;
+
+    /** Digest initialisation function */
+    void (*starts_func)( void *ctx );
+
+    /** Digest update function */
+    void (*update_func)( void *ctx, const unsigned char *input, size_t ilen );
+
+    /** Digest finalisation function */
+    void (*finish_func)( void *ctx, unsigned char *output );
+
+    /** Generic digest function */
+    void (*digest_func)( const unsigned char *input, size_t ilen,
+                         unsigned char *output );
+
+    /** Allocate a new context */
+    void * (*ctx_alloc_func)( void );
+
+    /** Free the given context */
+    void (*ctx_free_func)( void *ctx );
+
+    /** Clone state from a context */
+    void (*clone_func)( void *dst, const void *src );
+
+    /** Internal use only */
+    void (*process_func)( void *ctx, const unsigned char *input );
+};
+
+#if defined(MBEDTLS_MD2_C)
+extern const mbedtls_md_info_t mbedtls_md2_info;
+#endif
+#if defined(MBEDTLS_MD4_C)
+extern const mbedtls_md_info_t mbedtls_md4_info;
+#endif
+#if defined(MBEDTLS_MD5_C)
+extern const mbedtls_md_info_t mbedtls_md5_info;
+#endif
+#if defined(MBEDTLS_RIPEMD160_C)
+extern const mbedtls_md_info_t mbedtls_ripemd160_info;
+#endif
+#if defined(MBEDTLS_SHA1_C)
+extern const mbedtls_md_info_t mbedtls_sha1_info;
+#endif
+#if defined(MBEDTLS_SHA256_C)
+extern const mbedtls_md_info_t mbedtls_sha224_info;
+extern const mbedtls_md_info_t mbedtls_sha256_info;
+#endif
+#if defined(MBEDTLS_SHA512_C)
+extern const mbedtls_md_info_t mbedtls_sha384_info;
+extern const mbedtls_md_info_t mbedtls_sha512_info;
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MBEDTLS_MD_WRAP_H */
diff --git a/tools/sdk/include/mbedtls/mbedtls/memory_buffer_alloc.h b/tools/sdk/include/mbedtls/mbedtls/memory_buffer_alloc.h
new file mode 100644
index 00000000..d5df316f
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/memory_buffer_alloc.h
@@ -0,0 +1,150 @@
+/**
+ * \file memory_buffer_alloc.h
+ *
+ * \brief Buffer-based memory allocator
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_MEMORY_BUFFER_ALLOC_H
+#define MBEDTLS_MEMORY_BUFFER_ALLOC_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#include 
+
+/**
+ * \name SECTION: Module settings
+ *
+ * The configuration options you can set for this module are in this section.
+ * Either change them in config.h or define them on the compiler command line.
+ * \{
+ */
+
+#if !defined(MBEDTLS_MEMORY_ALIGN_MULTIPLE)
+#define MBEDTLS_MEMORY_ALIGN_MULTIPLE       4 /**< Align on multiples of this value */
+#endif
+
+/* \} name SECTION: Module settings */
+
+#define MBEDTLS_MEMORY_VERIFY_NONE         0
+#define MBEDTLS_MEMORY_VERIFY_ALLOC        (1 << 0)
+#define MBEDTLS_MEMORY_VERIFY_FREE         (1 << 1)
+#define MBEDTLS_MEMORY_VERIFY_ALWAYS       (MBEDTLS_MEMORY_VERIFY_ALLOC | MBEDTLS_MEMORY_VERIFY_FREE)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief   Initialize use of stack-based memory allocator.
+ *          The stack-based allocator does memory management inside the
+ *          presented buffer and does not call calloc() and free().
+ *          It sets the global mbedtls_calloc() and mbedtls_free() pointers
+ *          to its own functions.
+ *          (Provided mbedtls_calloc() and mbedtls_free() are thread-safe if
+ *           MBEDTLS_THREADING_C is defined)
+ *
+ * \note    This code is not optimized and provides a straight-forward
+ *          implementation of a stack-based memory allocator.
+ *
+ * \param buf   buffer to use as heap
+ * \param len   size of the buffer
+ */
+void mbedtls_memory_buffer_alloc_init( unsigned char *buf, size_t len );
+
+/**
+ * \brief   Free the mutex for thread-safety and clear remaining memory
+ */
+void mbedtls_memory_buffer_alloc_free( void );
+
+/**
+ * \brief   Determine when the allocator should automatically verify the state
+ *          of the entire chain of headers / meta-data.
+ *          (Default: MBEDTLS_MEMORY_VERIFY_NONE)
+ *
+ * \param verify    One of MBEDTLS_MEMORY_VERIFY_NONE, MBEDTLS_MEMORY_VERIFY_ALLOC,
+ *                  MBEDTLS_MEMORY_VERIFY_FREE or MBEDTLS_MEMORY_VERIFY_ALWAYS
+ */
+void mbedtls_memory_buffer_set_verify( int verify );
+
+#if defined(MBEDTLS_MEMORY_DEBUG)
+/**
+ * \brief   Print out the status of the allocated memory (primarily for use
+ *          after a program should have de-allocated all memory)
+ *          Prints out a list of 'still allocated' blocks and their stack
+ *          trace if MBEDTLS_MEMORY_BACKTRACE is defined.
+ */
+void mbedtls_memory_buffer_alloc_status( void );
+
+/**
+ * \brief   Get the peak heap usage so far
+ *
+ * \param max_used      Peak number of bytes in use or committed. This
+ *                      includes bytes in allocated blocks too small to split
+ *                      into smaller blocks but larger than the requested size.
+ * \param max_blocks    Peak number of blocks in use, including free and used
+ */
+void mbedtls_memory_buffer_alloc_max_get( size_t *max_used, size_t *max_blocks );
+
+/**
+ * \brief   Reset peak statistics
+ */
+void mbedtls_memory_buffer_alloc_max_reset( void );
+
+/**
+ * \brief   Get the current heap usage
+ *
+ * \param cur_used      Current number of bytes in use or committed. This
+ *                      includes bytes in allocated blocks too small to split
+ *                      into smaller blocks but larger than the requested size.
+ * \param cur_blocks    Current number of blocks in use, including free and used
+ */
+void mbedtls_memory_buffer_alloc_cur_get( size_t *cur_used, size_t *cur_blocks );
+#endif /* MBEDTLS_MEMORY_DEBUG */
+
+/**
+ * \brief   Verifies that all headers in the memory buffer are correct
+ *          and contain sane values. Helps debug buffer-overflow errors.
+ *
+ *          Prints out first failure if MBEDTLS_MEMORY_DEBUG is defined.
+ *          Prints out full header information if MBEDTLS_MEMORY_DEBUG
+ *          is defined. (Includes stack trace information for each block if
+ *          MBEDTLS_MEMORY_BACKTRACE is defined as well).
+ *
+ * \return             0 if verified, 1 otherwise
+ */
+int mbedtls_memory_buffer_alloc_verify( void );
+
+#if defined(MBEDTLS_SELF_TEST)
+/**
+ * \brief          Checkup routine
+ *
+ * \return         0 if successful, or 1 if a test failed
+ */
+int mbedtls_memory_buffer_alloc_self_test( int verbose );
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* memory_buffer_alloc.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/net.h b/tools/sdk/include/mbedtls/mbedtls/net.h
new file mode 100644
index 00000000..8c6534cf
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/net.h
@@ -0,0 +1,225 @@
+/**
+ * \file net.h
+ *
+ * \brief Network communication functions
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_NET_H
+#define MBEDTLS_NET_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#include "ssl.h"
+
+#include 
+#include 
+
+#define MBEDTLS_ERR_NET_SOCKET_FAILED                     -0x0042  /**< Failed to open a socket. */
+#define MBEDTLS_ERR_NET_CONNECT_FAILED                    -0x0044  /**< The connection to the given server / port failed. */
+#define MBEDTLS_ERR_NET_BIND_FAILED                       -0x0046  /**< Binding of the socket failed. */
+#define MBEDTLS_ERR_NET_LISTEN_FAILED                     -0x0048  /**< Could not listen on the socket. */
+#define MBEDTLS_ERR_NET_ACCEPT_FAILED                     -0x004A  /**< Could not accept the incoming connection. */
+#define MBEDTLS_ERR_NET_RECV_FAILED                       -0x004C  /**< Reading information from the socket failed. */
+#define MBEDTLS_ERR_NET_SEND_FAILED                       -0x004E  /**< Sending information through the socket failed. */
+#define MBEDTLS_ERR_NET_CONN_RESET                        -0x0050  /**< Connection was reset by peer. */
+#define MBEDTLS_ERR_NET_UNKNOWN_HOST                      -0x0052  /**< Failed to get an IP address for the given hostname. */
+#define MBEDTLS_ERR_NET_BUFFER_TOO_SMALL                  -0x0043  /**< Buffer is too small to hold the data. */
+#define MBEDTLS_ERR_NET_INVALID_CONTEXT                   -0x0045  /**< The context is invalid, eg because it was free()ed. */
+
+#define MBEDTLS_NET_LISTEN_BACKLOG         10 /**< The backlog that listen() should use. */
+
+#define MBEDTLS_NET_PROTO_TCP 0 /**< The TCP transport protocol */
+#define MBEDTLS_NET_PROTO_UDP 1 /**< The UDP transport protocol */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Wrapper type for sockets.
+ *
+ * Currently backed by just a file descriptor, but might be more in the future
+ * (eg two file descriptors for combined IPv4 + IPv6 support, or additional
+ * structures for hand-made UDP demultiplexing).
+ */
+typedef struct
+{
+    int fd;             /**< The underlying file descriptor                 */
+}
+mbedtls_net_context;
+
+/**
+ * \brief          Initialize a context
+ *                 Just makes the context ready to be used or freed safely.
+ *
+ * \param ctx      Context to initialize
+ */
+void mbedtls_net_init( mbedtls_net_context *ctx );
+
+/**
+ * \brief          Initiate a connection with host:port in the given protocol
+ *
+ * \param ctx      Socket to use
+ * \param host     Host to connect to
+ * \param port     Port to connect to
+ * \param proto    Protocol: MBEDTLS_NET_PROTO_TCP or MBEDTLS_NET_PROTO_UDP
+ *
+ * \return         0 if successful, or one of:
+ *                      MBEDTLS_ERR_NET_SOCKET_FAILED,
+ *                      MBEDTLS_ERR_NET_UNKNOWN_HOST,
+ *                      MBEDTLS_ERR_NET_CONNECT_FAILED
+ *
+ * \note           Sets the socket in connected mode even with UDP.
+ */
+int mbedtls_net_connect( mbedtls_net_context *ctx, const char *host, const char *port, int proto );
+
+/**
+ * \brief          Create a receiving socket on bind_ip:port in the chosen
+ *                 protocol. If bind_ip == NULL, all interfaces are bound.
+ *
+ * \param ctx      Socket to use
+ * \param bind_ip  IP to bind to, can be NULL
+ * \param port     Port number to use
+ * \param proto    Protocol: MBEDTLS_NET_PROTO_TCP or MBEDTLS_NET_PROTO_UDP
+ *
+ * \return         0 if successful, or one of:
+ *                      MBEDTLS_ERR_NET_SOCKET_FAILED,
+ *                      MBEDTLS_ERR_NET_BIND_FAILED,
+ *                      MBEDTLS_ERR_NET_LISTEN_FAILED
+ *
+ * \note           Regardless of the protocol, opens the sockets and binds it.
+ *                 In addition, make the socket listening if protocol is TCP.
+ */
+int mbedtls_net_bind( mbedtls_net_context *ctx, const char *bind_ip, const char *port, int proto );
+
+/**
+ * \brief           Accept a connection from a remote client
+ *
+ * \param bind_ctx  Relevant socket
+ * \param client_ctx Will contain the connected client socket
+ * \param client_ip Will contain the client IP address
+ * \param buf_size  Size of the client_ip buffer
+ * \param ip_len    Will receive the size of the client IP written
+ *
+ * \return          0 if successful, or
+ *                  MBEDTLS_ERR_NET_ACCEPT_FAILED, or
+ *                  MBEDTLS_ERR_NET_BUFFER_TOO_SMALL if buf_size is too small,
+ *                  MBEDTLS_ERR_SSL_WANT_READ if bind_fd was set to
+ *                  non-blocking and accept() would block.
+ */
+int mbedtls_net_accept( mbedtls_net_context *bind_ctx,
+                        mbedtls_net_context *client_ctx,
+                        void *client_ip, size_t buf_size, size_t *ip_len );
+
+/**
+ * \brief          Set the socket blocking
+ *
+ * \param ctx      Socket to set
+ *
+ * \return         0 if successful, or a non-zero error code
+ */
+int mbedtls_net_set_block( mbedtls_net_context *ctx );
+
+/**
+ * \brief          Set the socket non-blocking
+ *
+ * \param ctx      Socket to set
+ *
+ * \return         0 if successful, or a non-zero error code
+ */
+int mbedtls_net_set_nonblock( mbedtls_net_context *ctx );
+
+/**
+ * \brief          Portable usleep helper
+ *
+ * \param usec     Amount of microseconds to sleep
+ *
+ * \note           Real amount of time slept will not be less than
+ *                 select()'s timeout granularity (typically, 10ms).
+ */
+void mbedtls_net_usleep( unsigned long usec );
+
+/**
+ * \brief          Read at most 'len' characters. If no error occurs,
+ *                 the actual amount read is returned.
+ *
+ * \param ctx      Socket
+ * \param buf      The buffer to write to
+ * \param len      Maximum length of the buffer
+ *
+ * \return         the number of bytes received,
+ *                 or a non-zero error code; with a non-blocking socket,
+ *                 MBEDTLS_ERR_SSL_WANT_READ indicates read() would block.
+ */
+int mbedtls_net_recv( void *ctx, unsigned char *buf, size_t len );
+
+/**
+ * \brief          Write at most 'len' characters. If no error occurs,
+ *                 the actual amount read is returned.
+ *
+ * \param ctx      Socket
+ * \param buf      The buffer to read from
+ * \param len      The length of the buffer
+ *
+ * \return         the number of bytes sent,
+ *                 or a non-zero error code; with a non-blocking socket,
+ *                 MBEDTLS_ERR_SSL_WANT_WRITE indicates write() would block.
+ */
+int mbedtls_net_send( void *ctx, const unsigned char *buf, size_t len );
+
+/**
+ * \brief          Read at most 'len' characters, blocking for at most
+ *                 'timeout' seconds. If no error occurs, the actual amount
+ *                 read is returned.
+ *
+ * \param ctx      Socket
+ * \param buf      The buffer to write to
+ * \param len      Maximum length of the buffer
+ * \param timeout  Maximum number of milliseconds to wait for data
+ *                 0 means no timeout (wait forever)
+ *
+ * \return         the number of bytes received,
+ *                 or a non-zero error code:
+ *                 MBEDTLS_ERR_SSL_TIMEOUT if the operation timed out,
+ *                 MBEDTLS_ERR_SSL_WANT_READ if interrupted by a signal.
+ *
+ * \note           This function will block (until data becomes available or
+ *                 timeout is reached) even if the socket is set to
+ *                 non-blocking. Handling timeouts with non-blocking reads
+ *                 requires a different strategy.
+ */
+int mbedtls_net_recv_timeout( void *ctx, unsigned char *buf, size_t len,
+                      uint32_t timeout );
+
+/**
+ * \brief          Gracefully shutdown the connection and free associated data
+ *
+ * \param ctx      The context to free
+ */
+void mbedtls_net_free( mbedtls_net_context *ctx );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* net.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/oid.h b/tools/sdk/include/mbedtls/mbedtls/oid.h
new file mode 100644
index 00000000..fcecdafd
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/oid.h
@@ -0,0 +1,570 @@
+/**
+ * \file oid.h
+ *
+ * \brief Object Identifier (OID) database
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_OID_H
+#define MBEDTLS_OID_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#include "asn1.h"
+#include "pk.h"
+
+#include 
+
+#if defined(MBEDTLS_CIPHER_C)
+#include "cipher.h"
+#endif
+
+#if defined(MBEDTLS_MD_C)
+#include "md.h"
+#endif
+
+#if defined(MBEDTLS_X509_USE_C) || defined(MBEDTLS_X509_CREATE_C)
+#include "x509.h"
+#endif
+
+#define MBEDTLS_ERR_OID_NOT_FOUND                         -0x002E  /**< OID is not found. */
+#define MBEDTLS_ERR_OID_BUF_TOO_SMALL                     -0x000B  /**< output buffer is too small */
+
+/*
+ * Top level OID tuples
+ */
+#define MBEDTLS_OID_ISO_MEMBER_BODIES           "\x2a"          /* {iso(1) member-body(2)} */
+#define MBEDTLS_OID_ISO_IDENTIFIED_ORG          "\x2b"          /* {iso(1) identified-organization(3)} */
+#define MBEDTLS_OID_ISO_CCITT_DS                "\x55"          /* {joint-iso-ccitt(2) ds(5)} */
+#define MBEDTLS_OID_ISO_ITU_COUNTRY             "\x60"          /* {joint-iso-itu-t(2) country(16)} */
+
+/*
+ * ISO Member bodies OID parts
+ */
+#define MBEDTLS_OID_COUNTRY_US                  "\x86\x48"      /* {us(840)} */
+#define MBEDTLS_OID_ORG_RSA_DATA_SECURITY       "\x86\xf7\x0d"  /* {rsadsi(113549)} */
+#define MBEDTLS_OID_RSA_COMPANY                 MBEDTLS_OID_ISO_MEMBER_BODIES MBEDTLS_OID_COUNTRY_US \
+                                        MBEDTLS_OID_ORG_RSA_DATA_SECURITY /* {iso(1) member-body(2) us(840) rsadsi(113549)} */
+#define MBEDTLS_OID_ORG_ANSI_X9_62              "\xce\x3d" /* ansi-X9-62(10045) */
+#define MBEDTLS_OID_ANSI_X9_62                  MBEDTLS_OID_ISO_MEMBER_BODIES MBEDTLS_OID_COUNTRY_US \
+                                        MBEDTLS_OID_ORG_ANSI_X9_62
+
+/*
+ * ISO Identified organization OID parts
+ */
+#define MBEDTLS_OID_ORG_DOD                     "\x06"          /* {dod(6)} */
+#define MBEDTLS_OID_ORG_OIW                     "\x0e"
+#define MBEDTLS_OID_OIW_SECSIG                  MBEDTLS_OID_ORG_OIW "\x03"
+#define MBEDTLS_OID_OIW_SECSIG_ALG              MBEDTLS_OID_OIW_SECSIG "\x02"
+#define MBEDTLS_OID_OIW_SECSIG_SHA1             MBEDTLS_OID_OIW_SECSIG_ALG "\x1a"
+#define MBEDTLS_OID_ORG_CERTICOM                "\x81\x04"  /* certicom(132) */
+#define MBEDTLS_OID_CERTICOM                    MBEDTLS_OID_ISO_IDENTIFIED_ORG MBEDTLS_OID_ORG_CERTICOM
+#define MBEDTLS_OID_ORG_TELETRUST               "\x24" /* teletrust(36) */
+#define MBEDTLS_OID_TELETRUST                   MBEDTLS_OID_ISO_IDENTIFIED_ORG MBEDTLS_OID_ORG_TELETRUST
+
+/*
+ * ISO ITU OID parts
+ */
+#define MBEDTLS_OID_ORGANIZATION                "\x01"          /* {organization(1)} */
+#define MBEDTLS_OID_ISO_ITU_US_ORG              MBEDTLS_OID_ISO_ITU_COUNTRY MBEDTLS_OID_COUNTRY_US MBEDTLS_OID_ORGANIZATION /* {joint-iso-itu-t(2) country(16) us(840) organization(1)} */
+
+#define MBEDTLS_OID_ORG_GOV                     "\x65"          /* {gov(101)} */
+#define MBEDTLS_OID_GOV                         MBEDTLS_OID_ISO_ITU_US_ORG MBEDTLS_OID_ORG_GOV /* {joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101)} */
+
+#define MBEDTLS_OID_ORG_NETSCAPE                "\x86\xF8\x42"  /* {netscape(113730)} */
+#define MBEDTLS_OID_NETSCAPE                    MBEDTLS_OID_ISO_ITU_US_ORG MBEDTLS_OID_ORG_NETSCAPE /* Netscape OID {joint-iso-itu-t(2) country(16) us(840) organization(1) netscape(113730)} */
+
+/* ISO arc for standard certificate and CRL extensions */
+#define MBEDTLS_OID_ID_CE                       MBEDTLS_OID_ISO_CCITT_DS "\x1D" /**< id-ce OBJECT IDENTIFIER  ::=  {joint-iso-ccitt(2) ds(5) 29} */
+
+/**
+ * Private Internet Extensions
+ * { iso(1) identified-organization(3) dod(6) internet(1)
+ *                      security(5) mechanisms(5) pkix(7) }
+ */
+#define MBEDTLS_OID_PKIX                        MBEDTLS_OID_ISO_IDENTIFIED_ORG MBEDTLS_OID_ORG_DOD "\x01\x05\x05\x07"
+
+/*
+ * Arc for standard naming attributes
+ */
+#define MBEDTLS_OID_AT                          MBEDTLS_OID_ISO_CCITT_DS "\x04" /**< id-at OBJECT IDENTIFIER ::= {joint-iso-ccitt(2) ds(5) 4} */
+#define MBEDTLS_OID_AT_CN                       MBEDTLS_OID_AT "\x03" /**< id-at-commonName AttributeType:= {id-at 3} */
+#define MBEDTLS_OID_AT_SUR_NAME                 MBEDTLS_OID_AT "\x04" /**< id-at-surName AttributeType:= {id-at 4} */
+#define MBEDTLS_OID_AT_SERIAL_NUMBER            MBEDTLS_OID_AT "\x05" /**< id-at-serialNumber AttributeType:= {id-at 5} */
+#define MBEDTLS_OID_AT_COUNTRY                  MBEDTLS_OID_AT "\x06" /**< id-at-countryName AttributeType:= {id-at 6} */
+#define MBEDTLS_OID_AT_LOCALITY                 MBEDTLS_OID_AT "\x07" /**< id-at-locality AttributeType:= {id-at 7} */
+#define MBEDTLS_OID_AT_STATE                    MBEDTLS_OID_AT "\x08" /**< id-at-state AttributeType:= {id-at 8} */
+#define MBEDTLS_OID_AT_ORGANIZATION             MBEDTLS_OID_AT "\x0A" /**< id-at-organizationName AttributeType:= {id-at 10} */
+#define MBEDTLS_OID_AT_ORG_UNIT                 MBEDTLS_OID_AT "\x0B" /**< id-at-organizationalUnitName AttributeType:= {id-at 11} */
+#define MBEDTLS_OID_AT_TITLE                    MBEDTLS_OID_AT "\x0C" /**< id-at-title AttributeType:= {id-at 12} */
+#define MBEDTLS_OID_AT_POSTAL_ADDRESS           MBEDTLS_OID_AT "\x10" /**< id-at-postalAddress AttributeType:= {id-at 16} */
+#define MBEDTLS_OID_AT_POSTAL_CODE              MBEDTLS_OID_AT "\x11" /**< id-at-postalCode AttributeType:= {id-at 17} */
+#define MBEDTLS_OID_AT_GIVEN_NAME               MBEDTLS_OID_AT "\x2A" /**< id-at-givenName AttributeType:= {id-at 42} */
+#define MBEDTLS_OID_AT_INITIALS                 MBEDTLS_OID_AT "\x2B" /**< id-at-initials AttributeType:= {id-at 43} */
+#define MBEDTLS_OID_AT_GENERATION_QUALIFIER     MBEDTLS_OID_AT "\x2C" /**< id-at-generationQualifier AttributeType:= {id-at 44} */
+#define MBEDTLS_OID_AT_UNIQUE_IDENTIFIER        MBEDTLS_OID_AT "\x2D" /**< id-at-uniqueIdentifier AttributType:= {id-at 45} */
+#define MBEDTLS_OID_AT_DN_QUALIFIER             MBEDTLS_OID_AT "\x2E" /**< id-at-dnQualifier AttributeType:= {id-at 46} */
+#define MBEDTLS_OID_AT_PSEUDONYM                MBEDTLS_OID_AT "\x41" /**< id-at-pseudonym AttributeType:= {id-at 65} */
+
+#define MBEDTLS_OID_DOMAIN_COMPONENT            "\x09\x92\x26\x89\x93\xF2\x2C\x64\x01\x19" /** id-domainComponent AttributeType:= {itu-t(0) data(9) pss(2342) ucl(19200300) pilot(100) pilotAttributeType(1) domainComponent(25)} */
+
+/*
+ * OIDs for standard certificate extensions
+ */
+#define MBEDTLS_OID_AUTHORITY_KEY_IDENTIFIER    MBEDTLS_OID_ID_CE "\x23" /**< id-ce-authorityKeyIdentifier OBJECT IDENTIFIER ::=  { id-ce 35 } */
+#define MBEDTLS_OID_SUBJECT_KEY_IDENTIFIER      MBEDTLS_OID_ID_CE "\x0E" /**< id-ce-subjectKeyIdentifier OBJECT IDENTIFIER ::=  { id-ce 14 } */
+#define MBEDTLS_OID_KEY_USAGE                   MBEDTLS_OID_ID_CE "\x0F" /**< id-ce-keyUsage OBJECT IDENTIFIER ::=  { id-ce 15 } */
+#define MBEDTLS_OID_CERTIFICATE_POLICIES        MBEDTLS_OID_ID_CE "\x20" /**< id-ce-certificatePolicies OBJECT IDENTIFIER ::=  { id-ce 32 } */
+#define MBEDTLS_OID_POLICY_MAPPINGS             MBEDTLS_OID_ID_CE "\x21" /**< id-ce-policyMappings OBJECT IDENTIFIER ::=  { id-ce 33 } */
+#define MBEDTLS_OID_SUBJECT_ALT_NAME            MBEDTLS_OID_ID_CE "\x11" /**< id-ce-subjectAltName OBJECT IDENTIFIER ::=  { id-ce 17 } */
+#define MBEDTLS_OID_ISSUER_ALT_NAME             MBEDTLS_OID_ID_CE "\x12" /**< id-ce-issuerAltName OBJECT IDENTIFIER ::=  { id-ce 18 } */
+#define MBEDTLS_OID_SUBJECT_DIRECTORY_ATTRS     MBEDTLS_OID_ID_CE "\x09" /**< id-ce-subjectDirectoryAttributes OBJECT IDENTIFIER ::=  { id-ce 9 } */
+#define MBEDTLS_OID_BASIC_CONSTRAINTS           MBEDTLS_OID_ID_CE "\x13" /**< id-ce-basicConstraints OBJECT IDENTIFIER ::=  { id-ce 19 } */
+#define MBEDTLS_OID_NAME_CONSTRAINTS            MBEDTLS_OID_ID_CE "\x1E" /**< id-ce-nameConstraints OBJECT IDENTIFIER ::=  { id-ce 30 } */
+#define MBEDTLS_OID_POLICY_CONSTRAINTS          MBEDTLS_OID_ID_CE "\x24" /**< id-ce-policyConstraints OBJECT IDENTIFIER ::=  { id-ce 36 } */
+#define MBEDTLS_OID_EXTENDED_KEY_USAGE          MBEDTLS_OID_ID_CE "\x25" /**< id-ce-extKeyUsage OBJECT IDENTIFIER ::= { id-ce 37 } */
+#define MBEDTLS_OID_CRL_DISTRIBUTION_POINTS     MBEDTLS_OID_ID_CE "\x1F" /**< id-ce-cRLDistributionPoints OBJECT IDENTIFIER ::=  { id-ce 31 } */
+#define MBEDTLS_OID_INIHIBIT_ANYPOLICY          MBEDTLS_OID_ID_CE "\x36" /**< id-ce-inhibitAnyPolicy OBJECT IDENTIFIER ::=  { id-ce 54 } */
+#define MBEDTLS_OID_FRESHEST_CRL                MBEDTLS_OID_ID_CE "\x2E" /**< id-ce-freshestCRL OBJECT IDENTIFIER ::=  { id-ce 46 } */
+
+/*
+ * Netscape certificate extensions
+ */
+#define MBEDTLS_OID_NS_CERT                 MBEDTLS_OID_NETSCAPE "\x01"
+#define MBEDTLS_OID_NS_CERT_TYPE            MBEDTLS_OID_NS_CERT  "\x01"
+#define MBEDTLS_OID_NS_BASE_URL             MBEDTLS_OID_NS_CERT  "\x02"
+#define MBEDTLS_OID_NS_REVOCATION_URL       MBEDTLS_OID_NS_CERT  "\x03"
+#define MBEDTLS_OID_NS_CA_REVOCATION_URL    MBEDTLS_OID_NS_CERT  "\x04"
+#define MBEDTLS_OID_NS_RENEWAL_URL          MBEDTLS_OID_NS_CERT  "\x07"
+#define MBEDTLS_OID_NS_CA_POLICY_URL        MBEDTLS_OID_NS_CERT  "\x08"
+#define MBEDTLS_OID_NS_SSL_SERVER_NAME      MBEDTLS_OID_NS_CERT  "\x0C"
+#define MBEDTLS_OID_NS_COMMENT              MBEDTLS_OID_NS_CERT  "\x0D"
+#define MBEDTLS_OID_NS_DATA_TYPE            MBEDTLS_OID_NETSCAPE "\x02"
+#define MBEDTLS_OID_NS_CERT_SEQUENCE        MBEDTLS_OID_NS_DATA_TYPE "\x05"
+
+/*
+ * OIDs for CRL extensions
+ */
+#define MBEDTLS_OID_PRIVATE_KEY_USAGE_PERIOD    MBEDTLS_OID_ID_CE "\x10"
+#define MBEDTLS_OID_CRL_NUMBER                  MBEDTLS_OID_ID_CE "\x14" /**< id-ce-cRLNumber OBJECT IDENTIFIER ::= { id-ce 20 } */
+
+/*
+ * X.509 v3 Extended key usage OIDs
+ */
+#define MBEDTLS_OID_ANY_EXTENDED_KEY_USAGE      MBEDTLS_OID_EXTENDED_KEY_USAGE "\x00" /**< anyExtendedKeyUsage OBJECT IDENTIFIER ::= { id-ce-extKeyUsage 0 } */
+
+#define MBEDTLS_OID_KP                          MBEDTLS_OID_PKIX "\x03" /**< id-kp OBJECT IDENTIFIER ::= { id-pkix 3 } */
+#define MBEDTLS_OID_SERVER_AUTH                 MBEDTLS_OID_KP "\x01" /**< id-kp-serverAuth OBJECT IDENTIFIER ::= { id-kp 1 } */
+#define MBEDTLS_OID_CLIENT_AUTH                 MBEDTLS_OID_KP "\x02" /**< id-kp-clientAuth OBJECT IDENTIFIER ::= { id-kp 2 } */
+#define MBEDTLS_OID_CODE_SIGNING                MBEDTLS_OID_KP "\x03" /**< id-kp-codeSigning OBJECT IDENTIFIER ::= { id-kp 3 } */
+#define MBEDTLS_OID_EMAIL_PROTECTION            MBEDTLS_OID_KP "\x04" /**< id-kp-emailProtection OBJECT IDENTIFIER ::= { id-kp 4 } */
+#define MBEDTLS_OID_TIME_STAMPING               MBEDTLS_OID_KP "\x08" /**< id-kp-timeStamping OBJECT IDENTIFIER ::= { id-kp 8 } */
+#define MBEDTLS_OID_OCSP_SIGNING                MBEDTLS_OID_KP "\x09" /**< id-kp-OCSPSigning OBJECT IDENTIFIER ::= { id-kp 9 } */
+
+/*
+ * PKCS definition OIDs
+ */
+
+#define MBEDTLS_OID_PKCS                MBEDTLS_OID_RSA_COMPANY "\x01" /**< pkcs OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) 1 } */
+#define MBEDTLS_OID_PKCS1               MBEDTLS_OID_PKCS "\x01" /**< pkcs-1 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) pkcs(1) 1 } */
+#define MBEDTLS_OID_PKCS5               MBEDTLS_OID_PKCS "\x05" /**< pkcs-5 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) pkcs(1) 5 } */
+#define MBEDTLS_OID_PKCS9               MBEDTLS_OID_PKCS "\x09" /**< pkcs-9 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) pkcs(1) 9 } */
+#define MBEDTLS_OID_PKCS12              MBEDTLS_OID_PKCS "\x0c" /**< pkcs-12 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) pkcs(1) 12 } */
+
+/*
+ * PKCS#1 OIDs
+ */
+#define MBEDTLS_OID_PKCS1_RSA           MBEDTLS_OID_PKCS1 "\x01" /**< rsaEncryption OBJECT IDENTIFIER ::= { pkcs-1 1 } */
+#define MBEDTLS_OID_PKCS1_MD2           MBEDTLS_OID_PKCS1 "\x02" /**< md2WithRSAEncryption ::= { pkcs-1 2 } */
+#define MBEDTLS_OID_PKCS1_MD4           MBEDTLS_OID_PKCS1 "\x03" /**< md4WithRSAEncryption ::= { pkcs-1 3 } */
+#define MBEDTLS_OID_PKCS1_MD5           MBEDTLS_OID_PKCS1 "\x04" /**< md5WithRSAEncryption ::= { pkcs-1 4 } */
+#define MBEDTLS_OID_PKCS1_SHA1          MBEDTLS_OID_PKCS1 "\x05" /**< sha1WithRSAEncryption ::= { pkcs-1 5 } */
+#define MBEDTLS_OID_PKCS1_SHA224        MBEDTLS_OID_PKCS1 "\x0e" /**< sha224WithRSAEncryption ::= { pkcs-1 14 } */
+#define MBEDTLS_OID_PKCS1_SHA256        MBEDTLS_OID_PKCS1 "\x0b" /**< sha256WithRSAEncryption ::= { pkcs-1 11 } */
+#define MBEDTLS_OID_PKCS1_SHA384        MBEDTLS_OID_PKCS1 "\x0c" /**< sha384WithRSAEncryption ::= { pkcs-1 12 } */
+#define MBEDTLS_OID_PKCS1_SHA512        MBEDTLS_OID_PKCS1 "\x0d" /**< sha512WithRSAEncryption ::= { pkcs-1 13 } */
+
+#define MBEDTLS_OID_RSA_SHA_OBS         "\x2B\x0E\x03\x02\x1D"
+
+#define MBEDTLS_OID_PKCS9_EMAIL         MBEDTLS_OID_PKCS9 "\x01" /**< emailAddress AttributeType ::= { pkcs-9 1 } */
+
+/* RFC 4055 */
+#define MBEDTLS_OID_RSASSA_PSS          MBEDTLS_OID_PKCS1 "\x0a" /**< id-RSASSA-PSS ::= { pkcs-1 10 } */
+#define MBEDTLS_OID_MGF1                MBEDTLS_OID_PKCS1 "\x08" /**< id-mgf1 ::= { pkcs-1 8 } */
+
+/*
+ * Digest algorithms
+ */
+#define MBEDTLS_OID_DIGEST_ALG_MD2              MBEDTLS_OID_RSA_COMPANY "\x02\x02" /**< id-mbedtls_md2 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) digestAlgorithm(2) 2 } */
+#define MBEDTLS_OID_DIGEST_ALG_MD4              MBEDTLS_OID_RSA_COMPANY "\x02\x04" /**< id-mbedtls_md4 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) digestAlgorithm(2) 4 } */
+#define MBEDTLS_OID_DIGEST_ALG_MD5              MBEDTLS_OID_RSA_COMPANY "\x02\x05" /**< id-mbedtls_md5 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) digestAlgorithm(2) 5 } */
+#define MBEDTLS_OID_DIGEST_ALG_SHA1             MBEDTLS_OID_ISO_IDENTIFIED_ORG MBEDTLS_OID_OIW_SECSIG_SHA1 /**< id-mbedtls_sha1 OBJECT IDENTIFIER ::= { iso(1) identified-organization(3) oiw(14) secsig(3) algorithms(2) 26 } */
+#define MBEDTLS_OID_DIGEST_ALG_SHA224           MBEDTLS_OID_GOV "\x03\x04\x02\x04" /**< id-sha224 OBJECT IDENTIFIER ::= { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistalgorithm(4) hashalgs(2) 4 } */
+#define MBEDTLS_OID_DIGEST_ALG_SHA256           MBEDTLS_OID_GOV "\x03\x04\x02\x01" /**< id-mbedtls_sha256 OBJECT IDENTIFIER ::= { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistalgorithm(4) hashalgs(2) 1 } */
+
+#define MBEDTLS_OID_DIGEST_ALG_SHA384           MBEDTLS_OID_GOV "\x03\x04\x02\x02" /**< id-sha384 OBJECT IDENTIFIER ::= { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistalgorithm(4) hashalgs(2) 2 } */
+
+#define MBEDTLS_OID_DIGEST_ALG_SHA512           MBEDTLS_OID_GOV "\x03\x04\x02\x03" /**< id-mbedtls_sha512 OBJECT IDENTIFIER ::= { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistalgorithm(4) hashalgs(2) 3 } */
+
+#define MBEDTLS_OID_HMAC_SHA1                   MBEDTLS_OID_RSA_COMPANY "\x02\x07" /**< id-hmacWithSHA1 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) digestAlgorithm(2) 7 } */
+
+/*
+ * Encryption algorithms
+ */
+#define MBEDTLS_OID_DES_CBC                     MBEDTLS_OID_ISO_IDENTIFIED_ORG MBEDTLS_OID_OIW_SECSIG_ALG "\x07" /**< desCBC OBJECT IDENTIFIER ::= { iso(1) identified-organization(3) oiw(14) secsig(3) algorithms(2) 7 } */
+#define MBEDTLS_OID_DES_EDE3_CBC                MBEDTLS_OID_RSA_COMPANY "\x03\x07" /**< des-ede3-cbc OBJECT IDENTIFIER ::= { iso(1) member-body(2) -- us(840) rsadsi(113549) encryptionAlgorithm(3) 7 } */
+
+/*
+ * PKCS#5 OIDs
+ */
+#define MBEDTLS_OID_PKCS5_PBKDF2                MBEDTLS_OID_PKCS5 "\x0c" /**< id-PBKDF2 OBJECT IDENTIFIER ::= {pkcs-5 12} */
+#define MBEDTLS_OID_PKCS5_PBES2                 MBEDTLS_OID_PKCS5 "\x0d" /**< id-PBES2 OBJECT IDENTIFIER ::= {pkcs-5 13} */
+#define MBEDTLS_OID_PKCS5_PBMAC1                MBEDTLS_OID_PKCS5 "\x0e" /**< id-PBMAC1 OBJECT IDENTIFIER ::= {pkcs-5 14} */
+
+/*
+ * PKCS#5 PBES1 algorithms
+ */
+#define MBEDTLS_OID_PKCS5_PBE_MD2_DES_CBC       MBEDTLS_OID_PKCS5 "\x01" /**< pbeWithMD2AndDES-CBC OBJECT IDENTIFIER ::= {pkcs-5 1} */
+#define MBEDTLS_OID_PKCS5_PBE_MD2_RC2_CBC       MBEDTLS_OID_PKCS5 "\x04" /**< pbeWithMD2AndRC2-CBC OBJECT IDENTIFIER ::= {pkcs-5 4} */
+#define MBEDTLS_OID_PKCS5_PBE_MD5_DES_CBC       MBEDTLS_OID_PKCS5 "\x03" /**< pbeWithMD5AndDES-CBC OBJECT IDENTIFIER ::= {pkcs-5 3} */
+#define MBEDTLS_OID_PKCS5_PBE_MD5_RC2_CBC       MBEDTLS_OID_PKCS5 "\x06" /**< pbeWithMD5AndRC2-CBC OBJECT IDENTIFIER ::= {pkcs-5 6} */
+#define MBEDTLS_OID_PKCS5_PBE_SHA1_DES_CBC      MBEDTLS_OID_PKCS5 "\x0a" /**< pbeWithSHA1AndDES-CBC OBJECT IDENTIFIER ::= {pkcs-5 10} */
+#define MBEDTLS_OID_PKCS5_PBE_SHA1_RC2_CBC      MBEDTLS_OID_PKCS5 "\x0b" /**< pbeWithSHA1AndRC2-CBC OBJECT IDENTIFIER ::= {pkcs-5 11} */
+
+/*
+ * PKCS#8 OIDs
+ */
+#define MBEDTLS_OID_PKCS9_CSR_EXT_REQ           MBEDTLS_OID_PKCS9 "\x0e" /**< extensionRequest OBJECT IDENTIFIER ::= {pkcs-9 14} */
+
+/*
+ * PKCS#12 PBE OIDs
+ */
+#define MBEDTLS_OID_PKCS12_PBE                      MBEDTLS_OID_PKCS12 "\x01" /**< pkcs-12PbeIds OBJECT IDENTIFIER ::= {pkcs-12 1} */
+
+#define MBEDTLS_OID_PKCS12_PBE_SHA1_RC4_128         MBEDTLS_OID_PKCS12_PBE "\x01" /**< pbeWithSHAAnd128BitRC4 OBJECT IDENTIFIER ::= {pkcs-12PbeIds 1} */
+#define MBEDTLS_OID_PKCS12_PBE_SHA1_RC4_40          MBEDTLS_OID_PKCS12_PBE "\x02" /**< pbeWithSHAAnd40BitRC4 OBJECT IDENTIFIER ::= {pkcs-12PbeIds 2} */
+#define MBEDTLS_OID_PKCS12_PBE_SHA1_DES3_EDE_CBC    MBEDTLS_OID_PKCS12_PBE "\x03" /**< pbeWithSHAAnd3-KeyTripleDES-CBC OBJECT IDENTIFIER ::= {pkcs-12PbeIds 3} */
+#define MBEDTLS_OID_PKCS12_PBE_SHA1_DES2_EDE_CBC    MBEDTLS_OID_PKCS12_PBE "\x04" /**< pbeWithSHAAnd2-KeyTripleDES-CBC OBJECT IDENTIFIER ::= {pkcs-12PbeIds 4} */
+#define MBEDTLS_OID_PKCS12_PBE_SHA1_RC2_128_CBC     MBEDTLS_OID_PKCS12_PBE "\x05" /**< pbeWithSHAAnd128BitRC2-CBC OBJECT IDENTIFIER ::= {pkcs-12PbeIds 5} */
+#define MBEDTLS_OID_PKCS12_PBE_SHA1_RC2_40_CBC      MBEDTLS_OID_PKCS12_PBE "\x06" /**< pbeWithSHAAnd40BitRC2-CBC OBJECT IDENTIFIER ::= {pkcs-12PbeIds 6} */
+
+/*
+ * EC key algorithms from RFC 5480
+ */
+
+/* id-ecPublicKey OBJECT IDENTIFIER ::= {
+ *       iso(1) member-body(2) us(840) ansi-X9-62(10045) keyType(2) 1 } */
+#define MBEDTLS_OID_EC_ALG_UNRESTRICTED         MBEDTLS_OID_ANSI_X9_62 "\x02\01"
+
+/*   id-ecDH OBJECT IDENTIFIER ::= {
+ *     iso(1) identified-organization(3) certicom(132)
+ *     schemes(1) ecdh(12) } */
+#define MBEDTLS_OID_EC_ALG_ECDH                 MBEDTLS_OID_CERTICOM "\x01\x0c"
+
+/*
+ * ECParameters namedCurve identifiers, from RFC 5480, RFC 5639, and SEC2
+ */
+
+/* secp192r1 OBJECT IDENTIFIER ::= {
+ *   iso(1) member-body(2) us(840) ansi-X9-62(10045) curves(3) prime(1) 1 } */
+#define MBEDTLS_OID_EC_GRP_SECP192R1        MBEDTLS_OID_ANSI_X9_62 "\x03\x01\x01"
+
+/* secp224r1 OBJECT IDENTIFIER ::= {
+ *   iso(1) identified-organization(3) certicom(132) curve(0) 33 } */
+#define MBEDTLS_OID_EC_GRP_SECP224R1        MBEDTLS_OID_CERTICOM "\x00\x21"
+
+/* secp256r1 OBJECT IDENTIFIER ::= {
+ *   iso(1) member-body(2) us(840) ansi-X9-62(10045) curves(3) prime(1) 7 } */
+#define MBEDTLS_OID_EC_GRP_SECP256R1        MBEDTLS_OID_ANSI_X9_62 "\x03\x01\x07"
+
+/* secp384r1 OBJECT IDENTIFIER ::= {
+ *   iso(1) identified-organization(3) certicom(132) curve(0) 34 } */
+#define MBEDTLS_OID_EC_GRP_SECP384R1        MBEDTLS_OID_CERTICOM "\x00\x22"
+
+/* secp521r1 OBJECT IDENTIFIER ::= {
+ *   iso(1) identified-organization(3) certicom(132) curve(0) 35 } */
+#define MBEDTLS_OID_EC_GRP_SECP521R1        MBEDTLS_OID_CERTICOM "\x00\x23"
+
+/* secp192k1 OBJECT IDENTIFIER ::= {
+ *   iso(1) identified-organization(3) certicom(132) curve(0) 31 } */
+#define MBEDTLS_OID_EC_GRP_SECP192K1        MBEDTLS_OID_CERTICOM "\x00\x1f"
+
+/* secp224k1 OBJECT IDENTIFIER ::= {
+ *   iso(1) identified-organization(3) certicom(132) curve(0) 32 } */
+#define MBEDTLS_OID_EC_GRP_SECP224K1        MBEDTLS_OID_CERTICOM "\x00\x20"
+
+/* secp256k1 OBJECT IDENTIFIER ::= {
+ *   iso(1) identified-organization(3) certicom(132) curve(0) 10 } */
+#define MBEDTLS_OID_EC_GRP_SECP256K1        MBEDTLS_OID_CERTICOM "\x00\x0a"
+
+/* RFC 5639 4.1
+ * ecStdCurvesAndGeneration OBJECT IDENTIFIER::= {iso(1)
+ * identified-organization(3) teletrust(36) algorithm(3) signature-
+ * algorithm(3) ecSign(2) 8}
+ * ellipticCurve OBJECT IDENTIFIER ::= {ecStdCurvesAndGeneration 1}
+ * versionOne OBJECT IDENTIFIER ::= {ellipticCurve 1} */
+#define MBEDTLS_OID_EC_BRAINPOOL_V1         MBEDTLS_OID_TELETRUST "\x03\x03\x02\x08\x01\x01"
+
+/* brainpoolP256r1 OBJECT IDENTIFIER ::= {versionOne 7} */
+#define MBEDTLS_OID_EC_GRP_BP256R1          MBEDTLS_OID_EC_BRAINPOOL_V1 "\x07"
+
+/* brainpoolP384r1 OBJECT IDENTIFIER ::= {versionOne 11} */
+#define MBEDTLS_OID_EC_GRP_BP384R1          MBEDTLS_OID_EC_BRAINPOOL_V1 "\x0B"
+
+/* brainpoolP512r1 OBJECT IDENTIFIER ::= {versionOne 13} */
+#define MBEDTLS_OID_EC_GRP_BP512R1          MBEDTLS_OID_EC_BRAINPOOL_V1 "\x0D"
+
+/*
+ * SEC1 C.1
+ *
+ * prime-field OBJECT IDENTIFIER ::= { id-fieldType 1 }
+ * id-fieldType OBJECT IDENTIFIER ::= { ansi-X9-62 fieldType(1)}
+ */
+#define MBEDTLS_OID_ANSI_X9_62_FIELD_TYPE   MBEDTLS_OID_ANSI_X9_62 "\x01"
+#define MBEDTLS_OID_ANSI_X9_62_PRIME_FIELD  MBEDTLS_OID_ANSI_X9_62_FIELD_TYPE "\x01"
+
+/*
+ * ECDSA signature identifiers, from RFC 5480
+ */
+#define MBEDTLS_OID_ANSI_X9_62_SIG          MBEDTLS_OID_ANSI_X9_62 "\x04" /* signatures(4) */
+#define MBEDTLS_OID_ANSI_X9_62_SIG_SHA2     MBEDTLS_OID_ANSI_X9_62_SIG "\x03" /* ecdsa-with-SHA2(3) */
+
+/* ecdsa-with-SHA1 OBJECT IDENTIFIER ::= {
+ *   iso(1) member-body(2) us(840) ansi-X9-62(10045) signatures(4) 1 } */
+#define MBEDTLS_OID_ECDSA_SHA1              MBEDTLS_OID_ANSI_X9_62_SIG "\x01"
+
+/* ecdsa-with-SHA224 OBJECT IDENTIFIER ::= {
+ *   iso(1) member-body(2) us(840) ansi-X9-62(10045) signatures(4)
+ *   ecdsa-with-SHA2(3) 1 } */
+#define MBEDTLS_OID_ECDSA_SHA224            MBEDTLS_OID_ANSI_X9_62_SIG_SHA2 "\x01"
+
+/* ecdsa-with-SHA256 OBJECT IDENTIFIER ::= {
+ *   iso(1) member-body(2) us(840) ansi-X9-62(10045) signatures(4)
+ *   ecdsa-with-SHA2(3) 2 } */
+#define MBEDTLS_OID_ECDSA_SHA256            MBEDTLS_OID_ANSI_X9_62_SIG_SHA2 "\x02"
+
+/* ecdsa-with-SHA384 OBJECT IDENTIFIER ::= {
+ *   iso(1) member-body(2) us(840) ansi-X9-62(10045) signatures(4)
+ *   ecdsa-with-SHA2(3) 3 } */
+#define MBEDTLS_OID_ECDSA_SHA384            MBEDTLS_OID_ANSI_X9_62_SIG_SHA2 "\x03"
+
+/* ecdsa-with-SHA512 OBJECT IDENTIFIER ::= {
+ *   iso(1) member-body(2) us(840) ansi-X9-62(10045) signatures(4)
+ *   ecdsa-with-SHA2(3) 4 } */
+#define MBEDTLS_OID_ECDSA_SHA512            MBEDTLS_OID_ANSI_X9_62_SIG_SHA2 "\x04"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief Base OID descriptor structure
+ */
+typedef struct {
+    const char *asn1;               /*!< OID ASN.1 representation       */
+    size_t asn1_len;                /*!< length of asn1                 */
+    const char *name;               /*!< official name (e.g. from RFC)  */
+    const char *description;        /*!< human friendly description     */
+} mbedtls_oid_descriptor_t;
+
+/**
+ * \brief           Translate an ASN.1 OID into its numeric representation
+ *                  (e.g. "\x2A\x86\x48\x86\xF7\x0D" into "1.2.840.113549")
+ *
+ * \param buf       buffer to put representation in
+ * \param size      size of the buffer
+ * \param oid       OID to translate
+ *
+ * \return          Length of the string written (excluding final NULL) or
+ *                  MBEDTLS_ERR_OID_BUF_TOO_SMALL in case of error
+ */
+int mbedtls_oid_get_numeric_string( char *buf, size_t size, const mbedtls_asn1_buf *oid );
+
+#if defined(MBEDTLS_X509_USE_C) || defined(MBEDTLS_X509_CREATE_C)
+/**
+ * \brief          Translate an X.509 extension OID into local values
+ *
+ * \param oid      OID to use
+ * \param ext_type place to store the extension type
+ *
+ * \return         0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND
+ */
+int mbedtls_oid_get_x509_ext_type( const mbedtls_asn1_buf *oid, int *ext_type );
+#endif
+
+/**
+ * \brief          Translate an X.509 attribute type OID into the short name
+ *                 (e.g. the OID for an X520 Common Name into "CN")
+ *
+ * \param oid      OID to use
+ * \param short_name    place to store the string pointer
+ *
+ * \return         0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND
+ */
+int mbedtls_oid_get_attr_short_name( const mbedtls_asn1_buf *oid, const char **short_name );
+
+/**
+ * \brief          Translate PublicKeyAlgorithm OID into pk_type
+ *
+ * \param oid      OID to use
+ * \param pk_alg   place to store public key algorithm
+ *
+ * \return         0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND
+ */
+int mbedtls_oid_get_pk_alg( const mbedtls_asn1_buf *oid, mbedtls_pk_type_t *pk_alg );
+
+/**
+ * \brief          Translate pk_type into PublicKeyAlgorithm OID
+ *
+ * \param pk_alg   Public key type to look for
+ * \param oid      place to store ASN.1 OID string pointer
+ * \param olen     length of the OID
+ *
+ * \return         0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND
+ */
+int mbedtls_oid_get_oid_by_pk_alg( mbedtls_pk_type_t pk_alg,
+                           const char **oid, size_t *olen );
+
+#if defined(MBEDTLS_ECP_C)
+/**
+ * \brief          Translate NamedCurve OID into an EC group identifier
+ *
+ * \param oid      OID to use
+ * \param grp_id   place to store group id
+ *
+ * \return         0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND
+ */
+int mbedtls_oid_get_ec_grp( const mbedtls_asn1_buf *oid, mbedtls_ecp_group_id *grp_id );
+
+/**
+ * \brief          Translate EC group identifier into NamedCurve OID
+ *
+ * \param grp_id   EC group identifier
+ * \param oid      place to store ASN.1 OID string pointer
+ * \param olen     length of the OID
+ *
+ * \return         0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND
+ */
+int mbedtls_oid_get_oid_by_ec_grp( mbedtls_ecp_group_id grp_id,
+                           const char **oid, size_t *olen );
+#endif /* MBEDTLS_ECP_C */
+
+#if defined(MBEDTLS_MD_C)
+/**
+ * \brief          Translate SignatureAlgorithm OID into md_type and pk_type
+ *
+ * \param oid      OID to use
+ * \param md_alg   place to store message digest algorithm
+ * \param pk_alg   place to store public key algorithm
+ *
+ * \return         0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND
+ */
+int mbedtls_oid_get_sig_alg( const mbedtls_asn1_buf *oid,
+                     mbedtls_md_type_t *md_alg, mbedtls_pk_type_t *pk_alg );
+
+/**
+ * \brief          Translate SignatureAlgorithm OID into description
+ *
+ * \param oid      OID to use
+ * \param desc     place to store string pointer
+ *
+ * \return         0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND
+ */
+int mbedtls_oid_get_sig_alg_desc( const mbedtls_asn1_buf *oid, const char **desc );
+
+/**
+ * \brief          Translate md_type and pk_type into SignatureAlgorithm OID
+ *
+ * \param md_alg   message digest algorithm
+ * \param pk_alg   public key algorithm
+ * \param oid      place to store ASN.1 OID string pointer
+ * \param olen     length of the OID
+ *
+ * \return         0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND
+ */
+int mbedtls_oid_get_oid_by_sig_alg( mbedtls_pk_type_t pk_alg, mbedtls_md_type_t md_alg,
+                            const char **oid, size_t *olen );
+
+/**
+ * \brief          Translate hash algorithm OID into md_type
+ *
+ * \param oid      OID to use
+ * \param md_alg   place to store message digest algorithm
+ *
+ * \return         0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND
+ */
+int mbedtls_oid_get_md_alg( const mbedtls_asn1_buf *oid, mbedtls_md_type_t *md_alg );
+#endif /* MBEDTLS_MD_C */
+
+/**
+ * \brief          Translate Extended Key Usage OID into description
+ *
+ * \param oid      OID to use
+ * \param desc     place to store string pointer
+ *
+ * \return         0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND
+ */
+int mbedtls_oid_get_extended_key_usage( const mbedtls_asn1_buf *oid, const char **desc );
+
+/**
+ * \brief          Translate md_type into hash algorithm OID
+ *
+ * \param md_alg   message digest algorithm
+ * \param oid      place to store ASN.1 OID string pointer
+ * \param olen     length of the OID
+ *
+ * \return         0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND
+ */
+int mbedtls_oid_get_oid_by_md( mbedtls_md_type_t md_alg, const char **oid, size_t *olen );
+
+#if defined(MBEDTLS_CIPHER_C)
+/**
+ * \brief          Translate encryption algorithm OID into cipher_type
+ *
+ * \param oid           OID to use
+ * \param cipher_alg    place to store cipher algorithm
+ *
+ * \return         0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND
+ */
+int mbedtls_oid_get_cipher_alg( const mbedtls_asn1_buf *oid, mbedtls_cipher_type_t *cipher_alg );
+#endif /* MBEDTLS_CIPHER_C */
+
+#if defined(MBEDTLS_PKCS12_C)
+/**
+ * \brief          Translate PKCS#12 PBE algorithm OID into md_type and
+ *                 cipher_type
+ *
+ * \param oid           OID to use
+ * \param md_alg        place to store message digest algorithm
+ * \param cipher_alg    place to store cipher algorithm
+ *
+ * \return         0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND
+ */
+int mbedtls_oid_get_pkcs12_pbe_alg( const mbedtls_asn1_buf *oid, mbedtls_md_type_t *md_alg,
+                            mbedtls_cipher_type_t *cipher_alg );
+#endif /* MBEDTLS_PKCS12_C */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* oid.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/padlock.h b/tools/sdk/include/mbedtls/mbedtls/padlock.h
new file mode 100644
index 00000000..2045a5ab
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/padlock.h
@@ -0,0 +1,107 @@
+/**
+ * \file padlock.h
+ *
+ * \brief VIA PadLock ACE for HW encryption/decryption supported by some
+ *        processors
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_PADLOCK_H
+#define MBEDTLS_PADLOCK_H
+
+#include "aes.h"
+
+#define MBEDTLS_ERR_PADLOCK_DATA_MISALIGNED               -0x0030  /**< Input data should be aligned. */
+
+#if defined(__has_feature)
+#if __has_feature(address_sanitizer)
+#define MBEDTLS_HAVE_ASAN
+#endif
+#endif
+
+/* Some versions of ASan result in errors about not enough registers */
+#if defined(MBEDTLS_HAVE_ASM) && defined(__GNUC__) && defined(__i386__) && \
+    !defined(MBEDTLS_HAVE_ASAN)
+
+#ifndef MBEDTLS_HAVE_X86
+#define MBEDTLS_HAVE_X86
+#endif
+
+#include 
+
+#define MBEDTLS_PADLOCK_RNG 0x000C
+#define MBEDTLS_PADLOCK_ACE 0x00C0
+#define MBEDTLS_PADLOCK_PHE 0x0C00
+#define MBEDTLS_PADLOCK_PMM 0x3000
+
+#define MBEDTLS_PADLOCK_ALIGN16(x) (uint32_t *) (16 + ((int32_t) x & ~15))
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          PadLock detection routine
+ *
+ * \param feature  The feature to detect
+ *
+ * \return         1 if CPU has support for the feature, 0 otherwise
+ */
+int mbedtls_padlock_has_support( int feature );
+
+/**
+ * \brief          PadLock AES-ECB block en(de)cryption
+ *
+ * \param ctx      AES context
+ * \param mode     MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT
+ * \param input    16-byte input block
+ * \param output   16-byte output block
+ *
+ * \return         0 if success, 1 if operation failed
+ */
+int mbedtls_padlock_xcryptecb( mbedtls_aes_context *ctx,
+                       int mode,
+                       const unsigned char input[16],
+                       unsigned char output[16] );
+
+/**
+ * \brief          PadLock AES-CBC buffer en(de)cryption
+ *
+ * \param ctx      AES context
+ * \param mode     MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT
+ * \param length   length of the input data
+ * \param iv       initialization vector (updated after use)
+ * \param input    buffer holding the input data
+ * \param output   buffer holding the output data
+ *
+ * \return         0 if success, 1 if operation failed
+ */
+int mbedtls_padlock_xcryptcbc( mbedtls_aes_context *ctx,
+                       int mode,
+                       size_t length,
+                       unsigned char iv[16],
+                       const unsigned char *input,
+                       unsigned char *output );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAVE_X86  */
+
+#endif /* padlock.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/pem.h b/tools/sdk/include/mbedtls/mbedtls/pem.h
new file mode 100644
index 00000000..54dc02d7
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/pem.h
@@ -0,0 +1,129 @@
+/**
+ * \file pem.h
+ *
+ * \brief Privacy Enhanced Mail (PEM) decoding
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_PEM_H
+#define MBEDTLS_PEM_H
+
+#include 
+
+/**
+ * \name PEM Error codes
+ * These error codes are returned in case of errors reading the
+ * PEM data.
+ * \{
+ */
+#define MBEDTLS_ERR_PEM_NO_HEADER_FOOTER_PRESENT          -0x1080  /**< No PEM header or footer found. */
+#define MBEDTLS_ERR_PEM_INVALID_DATA                      -0x1100  /**< PEM string is not as expected. */
+#define MBEDTLS_ERR_PEM_ALLOC_FAILED                      -0x1180  /**< Failed to allocate memory. */
+#define MBEDTLS_ERR_PEM_INVALID_ENC_IV                    -0x1200  /**< RSA IV is not in hex-format. */
+#define MBEDTLS_ERR_PEM_UNKNOWN_ENC_ALG                   -0x1280  /**< Unsupported key encryption algorithm. */
+#define MBEDTLS_ERR_PEM_PASSWORD_REQUIRED                 -0x1300  /**< Private key password can't be empty. */
+#define MBEDTLS_ERR_PEM_PASSWORD_MISMATCH                 -0x1380  /**< Given private key password does not allow for correct decryption. */
+#define MBEDTLS_ERR_PEM_FEATURE_UNAVAILABLE               -0x1400  /**< Unavailable feature, e.g. hashing/encryption combination. */
+#define MBEDTLS_ERR_PEM_BAD_INPUT_DATA                    -0x1480  /**< Bad input parameters to function. */
+/* \} name */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(MBEDTLS_PEM_PARSE_C)
+/**
+ * \brief       PEM context structure
+ */
+typedef struct
+{
+    unsigned char *buf;     /*!< buffer for decoded data             */
+    size_t buflen;          /*!< length of the buffer                */
+    unsigned char *info;    /*!< buffer for extra header information */
+}
+mbedtls_pem_context;
+
+/**
+ * \brief       PEM context setup
+ *
+ * \param ctx   context to be initialized
+ */
+void mbedtls_pem_init( mbedtls_pem_context *ctx );
+
+/**
+ * \brief       Read a buffer for PEM information and store the resulting
+ *              data into the specified context buffers.
+ *
+ * \param ctx       context to use
+ * \param header    header string to seek and expect
+ * \param footer    footer string to seek and expect
+ * \param data      source data to look in (must be nul-terminated)
+ * \param pwd       password for decryption (can be NULL)
+ * \param pwdlen    length of password
+ * \param use_len   destination for total length used (set after header is
+ *                  correctly read, so unless you get
+ *                  MBEDTLS_ERR_PEM_BAD_INPUT_DATA or
+ *                  MBEDTLS_ERR_PEM_NO_HEADER_FOOTER_PRESENT, use_len is
+ *                  the length to skip)
+ *
+ * \note            Attempts to check password correctness by verifying if
+ *                  the decrypted text starts with an ASN.1 sequence of
+ *                  appropriate length
+ *
+ * \return          0 on success, or a specific PEM error code
+ */
+int mbedtls_pem_read_buffer( mbedtls_pem_context *ctx, const char *header, const char *footer,
+                     const unsigned char *data,
+                     const unsigned char *pwd,
+                     size_t pwdlen, size_t *use_len );
+
+/**
+ * \brief       PEM context memory freeing
+ *
+ * \param ctx   context to be freed
+ */
+void mbedtls_pem_free( mbedtls_pem_context *ctx );
+#endif /* MBEDTLS_PEM_PARSE_C */
+
+#if defined(MBEDTLS_PEM_WRITE_C)
+/**
+ * \brief           Write a buffer of PEM information from a DER encoded
+ *                  buffer.
+ *
+ * \param header    header string to write
+ * \param footer    footer string to write
+ * \param der_data  DER data to write
+ * \param der_len   length of the DER data
+ * \param buf       buffer to write to
+ * \param buf_len   length of output buffer
+ * \param olen      total length written / required (if buf_len is not enough)
+ *
+ * \return          0 on success, or a specific PEM or BASE64 error code. On
+ *                  MBEDTLS_ERR_BASE64_BUFFER_TOO_SMALL olen is the required
+ *                  size.
+ */
+int mbedtls_pem_write_buffer( const char *header, const char *footer,
+                      const unsigned char *der_data, size_t der_len,
+                      unsigned char *buf, size_t buf_len, size_t *olen );
+#endif /* MBEDTLS_PEM_WRITE_C */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* pem.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/pk.h b/tools/sdk/include/mbedtls/mbedtls/pk.h
new file mode 100644
index 00000000..f9f9b9bb
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/pk.h
@@ -0,0 +1,616 @@
+/**
+ * \file pk.h
+ *
+ * \brief Public Key abstraction layer
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+
+#ifndef MBEDTLS_PK_H
+#define MBEDTLS_PK_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#include "md.h"
+
+#if defined(MBEDTLS_RSA_C)
+#include "rsa.h"
+#endif
+
+#if defined(MBEDTLS_ECP_C)
+#include "ecp.h"
+#endif
+
+#if defined(MBEDTLS_ECDSA_C)
+#include "ecdsa.h"
+#endif
+
+#if ( defined(__ARMCC_VERSION) || defined(_MSC_VER) ) && \
+    !defined(inline) && !defined(__cplusplus)
+#define inline __inline
+#endif
+
+#define MBEDTLS_ERR_PK_ALLOC_FAILED        -0x3F80  /**< Memory allocation failed. */
+#define MBEDTLS_ERR_PK_TYPE_MISMATCH       -0x3F00  /**< Type mismatch, eg attempt to encrypt with an ECDSA key */
+#define MBEDTLS_ERR_PK_BAD_INPUT_DATA      -0x3E80  /**< Bad input parameters to function. */
+#define MBEDTLS_ERR_PK_FILE_IO_ERROR       -0x3E00  /**< Read/write of file failed. */
+#define MBEDTLS_ERR_PK_KEY_INVALID_VERSION -0x3D80  /**< Unsupported key version */
+#define MBEDTLS_ERR_PK_KEY_INVALID_FORMAT  -0x3D00  /**< Invalid key tag or value. */
+#define MBEDTLS_ERR_PK_UNKNOWN_PK_ALG      -0x3C80  /**< Key algorithm is unsupported (only RSA and EC are supported). */
+#define MBEDTLS_ERR_PK_PASSWORD_REQUIRED   -0x3C00  /**< Private key password can't be empty. */
+#define MBEDTLS_ERR_PK_PASSWORD_MISMATCH   -0x3B80  /**< Given private key password does not allow for correct decryption. */
+#define MBEDTLS_ERR_PK_INVALID_PUBKEY      -0x3B00  /**< The pubkey tag or value is invalid (only RSA and EC are supported). */
+#define MBEDTLS_ERR_PK_INVALID_ALG         -0x3A80  /**< The algorithm tag or value is invalid. */
+#define MBEDTLS_ERR_PK_UNKNOWN_NAMED_CURVE -0x3A00  /**< Elliptic curve is unsupported (only NIST curves are supported). */
+#define MBEDTLS_ERR_PK_FEATURE_UNAVAILABLE -0x3980  /**< Unavailable feature, e.g. RSA disabled for RSA key. */
+#define MBEDTLS_ERR_PK_SIG_LEN_MISMATCH    -0x3900  /**< The signature is valid but its length is less than expected. */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          Public key types
+ */
+typedef enum {
+    MBEDTLS_PK_NONE=0,
+    MBEDTLS_PK_RSA,
+    MBEDTLS_PK_ECKEY,
+    MBEDTLS_PK_ECKEY_DH,
+    MBEDTLS_PK_ECDSA,
+    MBEDTLS_PK_RSA_ALT,
+    MBEDTLS_PK_RSASSA_PSS,
+} mbedtls_pk_type_t;
+
+/**
+ * \brief           Options for RSASSA-PSS signature verification.
+ *                  See \c mbedtls_rsa_rsassa_pss_verify_ext()
+ */
+typedef struct
+{
+    mbedtls_md_type_t mgf1_hash_id;
+    int expected_salt_len;
+
+} mbedtls_pk_rsassa_pss_options;
+
+/**
+ * \brief           Types for interfacing with the debug module
+ */
+typedef enum
+{
+    MBEDTLS_PK_DEBUG_NONE = 0,
+    MBEDTLS_PK_DEBUG_MPI,
+    MBEDTLS_PK_DEBUG_ECP,
+} mbedtls_pk_debug_type;
+
+/**
+ * \brief           Item to send to the debug module
+ */
+typedef struct
+{
+    mbedtls_pk_debug_type type;
+    const char *name;
+    void *value;
+} mbedtls_pk_debug_item;
+
+/** Maximum number of item send for debugging, plus 1 */
+#define MBEDTLS_PK_DEBUG_MAX_ITEMS 3
+
+/**
+ * \brief           Public key information and operations
+ */
+typedef struct mbedtls_pk_info_t mbedtls_pk_info_t;
+
+/**
+ * \brief           Public key container
+ */
+typedef struct
+{
+    const mbedtls_pk_info_t *   pk_info; /**< Public key informations        */
+    void *                      pk_ctx;  /**< Underlying public key context  */
+} mbedtls_pk_context;
+
+#if defined(MBEDTLS_RSA_C)
+/**
+ * Quick access to an RSA context inside a PK context.
+ *
+ * \warning You must make sure the PK context actually holds an RSA context
+ * before using this function!
+ */
+static inline mbedtls_rsa_context *mbedtls_pk_rsa( const mbedtls_pk_context pk )
+{
+    return( (mbedtls_rsa_context *) (pk).pk_ctx );
+}
+#endif /* MBEDTLS_RSA_C */
+
+#if defined(MBEDTLS_ECP_C)
+/**
+ * Quick access to an EC context inside a PK context.
+ *
+ * \warning You must make sure the PK context actually holds an EC context
+ * before using this function!
+ */
+static inline mbedtls_ecp_keypair *mbedtls_pk_ec( const mbedtls_pk_context pk )
+{
+    return( (mbedtls_ecp_keypair *) (pk).pk_ctx );
+}
+#endif /* MBEDTLS_ECP_C */
+
+#if defined(MBEDTLS_PK_RSA_ALT_SUPPORT)
+/**
+ * \brief           Types for RSA-alt abstraction
+ */
+typedef int (*mbedtls_pk_rsa_alt_decrypt_func)( void *ctx, int mode, size_t *olen,
+                    const unsigned char *input, unsigned char *output,
+                    size_t output_max_len );
+typedef int (*mbedtls_pk_rsa_alt_sign_func)( void *ctx,
+                    int (*f_rng)(void *, unsigned char *, size_t), void *p_rng,
+                    int mode, mbedtls_md_type_t md_alg, unsigned int hashlen,
+                    const unsigned char *hash, unsigned char *sig );
+typedef size_t (*mbedtls_pk_rsa_alt_key_len_func)( void *ctx );
+#endif /* MBEDTLS_PK_RSA_ALT_SUPPORT */
+
+/**
+ * \brief           Return information associated with the given PK type
+ *
+ * \param pk_type   PK type to search for.
+ *
+ * \return          The PK info associated with the type or NULL if not found.
+ */
+const mbedtls_pk_info_t *mbedtls_pk_info_from_type( mbedtls_pk_type_t pk_type );
+
+/**
+ * \brief           Initialize a mbedtls_pk_context (as NONE)
+ */
+void mbedtls_pk_init( mbedtls_pk_context *ctx );
+
+/**
+ * \brief           Free a mbedtls_pk_context
+ */
+void mbedtls_pk_free( mbedtls_pk_context *ctx );
+
+/**
+ * \brief           Initialize a PK context with the information given
+ *                  and allocates the type-specific PK subcontext.
+ *
+ * \param ctx       Context to initialize. Must be empty (type NONE).
+ * \param info      Information to use
+ *
+ * \return          0 on success,
+ *                  MBEDTLS_ERR_PK_BAD_INPUT_DATA on invalid input,
+ *                  MBEDTLS_ERR_PK_ALLOC_FAILED on allocation failure.
+ *
+ * \note            For contexts holding an RSA-alt key, use
+ *                  \c mbedtls_pk_setup_rsa_alt() instead.
+ */
+int mbedtls_pk_setup( mbedtls_pk_context *ctx, const mbedtls_pk_info_t *info );
+
+#if defined(MBEDTLS_PK_RSA_ALT_SUPPORT)
+/**
+ * \brief           Initialize an RSA-alt context
+ *
+ * \param ctx       Context to initialize. Must be empty (type NONE).
+ * \param key       RSA key pointer
+ * \param decrypt_func  Decryption function
+ * \param sign_func     Signing function
+ * \param key_len_func  Function returning key length in bytes
+ *
+ * \return          0 on success, or MBEDTLS_ERR_PK_BAD_INPUT_DATA if the
+ *                  context wasn't already initialized as RSA_ALT.
+ *
+ * \note            This function replaces \c mbedtls_pk_setup() for RSA-alt.
+ */
+int mbedtls_pk_setup_rsa_alt( mbedtls_pk_context *ctx, void * key,
+                         mbedtls_pk_rsa_alt_decrypt_func decrypt_func,
+                         mbedtls_pk_rsa_alt_sign_func sign_func,
+                         mbedtls_pk_rsa_alt_key_len_func key_len_func );
+#endif /* MBEDTLS_PK_RSA_ALT_SUPPORT */
+
+/**
+ * \brief           Get the size in bits of the underlying key
+ *
+ * \param ctx       Context to use
+ *
+ * \return          Key size in bits, or 0 on error
+ */
+size_t mbedtls_pk_get_bitlen( const mbedtls_pk_context *ctx );
+
+/**
+ * \brief           Get the length in bytes of the underlying key
+ * \param ctx       Context to use
+ *
+ * \return          Key length in bytes, or 0 on error
+ */
+static inline size_t mbedtls_pk_get_len( const mbedtls_pk_context *ctx )
+{
+    return( ( mbedtls_pk_get_bitlen( ctx ) + 7 ) / 8 );
+}
+
+/**
+ * \brief           Tell if a context can do the operation given by type
+ *
+ * \param ctx       Context to test
+ * \param type      Target type
+ *
+ * \return          0 if context can't do the operations,
+ *                  1 otherwise.
+ */
+int mbedtls_pk_can_do( const mbedtls_pk_context *ctx, mbedtls_pk_type_t type );
+
+/**
+ * \brief           Verify signature (including padding if relevant).
+ *
+ * \param ctx       PK context to use
+ * \param md_alg    Hash algorithm used (see notes)
+ * \param hash      Hash of the message to sign
+ * \param hash_len  Hash length or 0 (see notes)
+ * \param sig       Signature to verify
+ * \param sig_len   Signature length
+ *
+ * \return          0 on success (signature is valid),
+ *                  MBEDTLS_ERR_PK_SIG_LEN_MISMATCH if the signature is
+ *                  valid but its actual length is less than sig_len,
+ *                  or a specific error code.
+ *
+ * \note            For RSA keys, the default padding type is PKCS#1 v1.5.
+ *                  Use \c mbedtls_pk_verify_ext( MBEDTLS_PK_RSASSA_PSS, ... )
+ *                  to verify RSASSA_PSS signatures.
+ *
+ * \note            If hash_len is 0, then the length associated with md_alg
+ *                  is used instead, or an error returned if it is invalid.
+ *
+ * \note            md_alg may be MBEDTLS_MD_NONE, only if hash_len != 0
+ */
+int mbedtls_pk_verify( mbedtls_pk_context *ctx, mbedtls_md_type_t md_alg,
+               const unsigned char *hash, size_t hash_len,
+               const unsigned char *sig, size_t sig_len );
+
+/**
+ * \brief           Verify signature, with options.
+ *                  (Includes verification of the padding depending on type.)
+ *
+ * \param type      Signature type (inc. possible padding type) to verify
+ * \param options   Pointer to type-specific options, or NULL
+ * \param ctx       PK context to use
+ * \param md_alg    Hash algorithm used (see notes)
+ * \param hash      Hash of the message to sign
+ * \param hash_len  Hash length or 0 (see notes)
+ * \param sig       Signature to verify
+ * \param sig_len   Signature length
+ *
+ * \return          0 on success (signature is valid),
+ *                  MBEDTLS_ERR_PK_TYPE_MISMATCH if the PK context can't be
+ *                  used for this type of signatures,
+ *                  MBEDTLS_ERR_PK_SIG_LEN_MISMATCH if the signature is
+ *                  valid but its actual length is less than sig_len,
+ *                  or a specific error code.
+ *
+ * \note            If hash_len is 0, then the length associated with md_alg
+ *                  is used instead, or an error returned if it is invalid.
+ *
+ * \note            md_alg may be MBEDTLS_MD_NONE, only if hash_len != 0
+ *
+ * \note            If type is MBEDTLS_PK_RSASSA_PSS, then options must point
+ *                  to a mbedtls_pk_rsassa_pss_options structure,
+ *                  otherwise it must be NULL.
+ */
+int mbedtls_pk_verify_ext( mbedtls_pk_type_t type, const void *options,
+                   mbedtls_pk_context *ctx, mbedtls_md_type_t md_alg,
+                   const unsigned char *hash, size_t hash_len,
+                   const unsigned char *sig, size_t sig_len );
+
+/**
+ * \brief           Make signature, including padding if relevant.
+ *
+ * \param ctx       PK context to use - must hold a private key
+ * \param md_alg    Hash algorithm used (see notes)
+ * \param hash      Hash of the message to sign
+ * \param hash_len  Hash length or 0 (see notes)
+ * \param sig       Place to write the signature
+ * \param sig_len   Number of bytes written
+ * \param f_rng     RNG function
+ * \param p_rng     RNG parameter
+ *
+ * \return          0 on success, or a specific error code.
+ *
+ * \note            For RSA keys, the default padding type is PKCS#1 v1.5.
+ *                  There is no interface in the PK module to make RSASSA-PSS
+ *                  signatures yet.
+ *
+ * \note            If hash_len is 0, then the length associated with md_alg
+ *                  is used instead, or an error returned if it is invalid.
+ *
+ * \note            For RSA, md_alg may be MBEDTLS_MD_NONE if hash_len != 0.
+ *                  For ECDSA, md_alg may never be MBEDTLS_MD_NONE.
+ */
+int mbedtls_pk_sign( mbedtls_pk_context *ctx, mbedtls_md_type_t md_alg,
+             const unsigned char *hash, size_t hash_len,
+             unsigned char *sig, size_t *sig_len,
+             int (*f_rng)(void *, unsigned char *, size_t), void *p_rng );
+
+/**
+ * \brief           Decrypt message (including padding if relevant).
+ *
+ * \param ctx       PK context to use - must hold a private key
+ * \param input     Input to decrypt
+ * \param ilen      Input size
+ * \param output    Decrypted output
+ * \param olen      Decrypted message length
+ * \param osize     Size of the output buffer
+ * \param f_rng     RNG function
+ * \param p_rng     RNG parameter
+ *
+ * \note            For RSA keys, the default padding type is PKCS#1 v1.5.
+ *
+ * \return          0 on success, or a specific error code.
+ */
+int mbedtls_pk_decrypt( mbedtls_pk_context *ctx,
+                const unsigned char *input, size_t ilen,
+                unsigned char *output, size_t *olen, size_t osize,
+                int (*f_rng)(void *, unsigned char *, size_t), void *p_rng );
+
+/**
+ * \brief           Encrypt message (including padding if relevant).
+ *
+ * \param ctx       PK context to use
+ * \param input     Message to encrypt
+ * \param ilen      Message size
+ * \param output    Encrypted output
+ * \param olen      Encrypted output length
+ * \param osize     Size of the output buffer
+ * \param f_rng     RNG function
+ * \param p_rng     RNG parameter
+ *
+ * \note            For RSA keys, the default padding type is PKCS#1 v1.5.
+ *
+ * \return          0 on success, or a specific error code.
+ */
+int mbedtls_pk_encrypt( mbedtls_pk_context *ctx,
+                const unsigned char *input, size_t ilen,
+                unsigned char *output, size_t *olen, size_t osize,
+                int (*f_rng)(void *, unsigned char *, size_t), void *p_rng );
+
+/**
+ * \brief           Check if a public-private pair of keys matches.
+ *
+ * \param pub       Context holding a public key.
+ * \param prv       Context holding a private (and public) key.
+ *
+ * \return          0 on success or MBEDTLS_ERR_PK_BAD_INPUT_DATA
+ */
+int mbedtls_pk_check_pair( const mbedtls_pk_context *pub, const mbedtls_pk_context *prv );
+
+/**
+ * \brief           Export debug information
+ *
+ * \param ctx       Context to use
+ * \param items     Place to write debug items
+ *
+ * \return          0 on success or MBEDTLS_ERR_PK_BAD_INPUT_DATA
+ */
+int mbedtls_pk_debug( const mbedtls_pk_context *ctx, mbedtls_pk_debug_item *items );
+
+/**
+ * \brief           Access the type name
+ *
+ * \param ctx       Context to use
+ *
+ * \return          Type name on success, or "invalid PK"
+ */
+const char * mbedtls_pk_get_name( const mbedtls_pk_context *ctx );
+
+/**
+ * \brief           Get the key type
+ *
+ * \param ctx       Context to use
+ *
+ * \return          Type on success, or MBEDTLS_PK_NONE
+ */
+mbedtls_pk_type_t mbedtls_pk_get_type( const mbedtls_pk_context *ctx );
+
+#if defined(MBEDTLS_PK_PARSE_C)
+/** \ingroup pk_module */
+/**
+ * \brief           Parse a private key in PEM or DER format
+ *
+ * \param ctx       key to be initialized
+ * \param key       input buffer
+ * \param keylen    size of the buffer
+ *                  (including the terminating null byte for PEM data)
+ * \param pwd       password for decryption (optional)
+ * \param pwdlen    size of the password
+ *
+ * \note            On entry, ctx must be empty, either freshly initialised
+ *                  with mbedtls_pk_init() or reset with mbedtls_pk_free(). If you need a
+ *                  specific key type, check the result with mbedtls_pk_can_do().
+ *
+ * \note            The key is also checked for correctness.
+ *
+ * \return          0 if successful, or a specific PK or PEM error code
+ */
+int mbedtls_pk_parse_key( mbedtls_pk_context *ctx,
+                  const unsigned char *key, size_t keylen,
+                  const unsigned char *pwd, size_t pwdlen );
+
+/** \ingroup pk_module */
+/**
+ * \brief           Parse a public key in PEM or DER format
+ *
+ * \param ctx       key to be initialized
+ * \param key       input buffer
+ * \param keylen    size of the buffer
+ *                  (including the terminating null byte for PEM data)
+ *
+ * \note            On entry, ctx must be empty, either freshly initialised
+ *                  with mbedtls_pk_init() or reset with mbedtls_pk_free(). If you need a
+ *                  specific key type, check the result with mbedtls_pk_can_do().
+ *
+ * \note            The key is also checked for correctness.
+ *
+ * \return          0 if successful, or a specific PK or PEM error code
+ */
+int mbedtls_pk_parse_public_key( mbedtls_pk_context *ctx,
+                         const unsigned char *key, size_t keylen );
+
+#if defined(MBEDTLS_FS_IO)
+/** \ingroup pk_module */
+/**
+ * \brief           Load and parse a private key
+ *
+ * \param ctx       key to be initialized
+ * \param path      filename to read the private key from
+ * \param password  password to decrypt the file (can be NULL)
+ *
+ * \note            On entry, ctx must be empty, either freshly initialised
+ *                  with mbedtls_pk_init() or reset with mbedtls_pk_free(). If you need a
+ *                  specific key type, check the result with mbedtls_pk_can_do().
+ *
+ * \note            The key is also checked for correctness.
+ *
+ * \return          0 if successful, or a specific PK or PEM error code
+ */
+int mbedtls_pk_parse_keyfile( mbedtls_pk_context *ctx,
+                      const char *path, const char *password );
+
+/** \ingroup pk_module */
+/**
+ * \brief           Load and parse a public key
+ *
+ * \param ctx       key to be initialized
+ * \param path      filename to read the public key from
+ *
+ * \note            On entry, ctx must be empty, either freshly initialised
+ *                  with mbedtls_pk_init() or reset with mbedtls_pk_free(). If
+ *                  you need a specific key type, check the result with
+ *                  mbedtls_pk_can_do().
+ *
+ * \note            The key is also checked for correctness.
+ *
+ * \return          0 if successful, or a specific PK or PEM error code
+ */
+int mbedtls_pk_parse_public_keyfile( mbedtls_pk_context *ctx, const char *path );
+#endif /* MBEDTLS_FS_IO */
+#endif /* MBEDTLS_PK_PARSE_C */
+
+#if defined(MBEDTLS_PK_WRITE_C)
+/**
+ * \brief           Write a private key to a PKCS#1 or SEC1 DER structure
+ *                  Note: data is written at the end of the buffer! Use the
+ *                        return value to determine where you should start
+ *                        using the buffer
+ *
+ * \param ctx       private to write away
+ * \param buf       buffer to write to
+ * \param size      size of the buffer
+ *
+ * \return          length of data written if successful, or a specific
+ *                  error code
+ */
+int mbedtls_pk_write_key_der( mbedtls_pk_context *ctx, unsigned char *buf, size_t size );
+
+/**
+ * \brief           Write a public key to a SubjectPublicKeyInfo DER structure
+ *                  Note: data is written at the end of the buffer! Use the
+ *                        return value to determine where you should start
+ *                        using the buffer
+ *
+ * \param ctx       public key to write away
+ * \param buf       buffer to write to
+ * \param size      size of the buffer
+ *
+ * \return          length of data written if successful, or a specific
+ *                  error code
+ */
+int mbedtls_pk_write_pubkey_der( mbedtls_pk_context *ctx, unsigned char *buf, size_t size );
+
+#if defined(MBEDTLS_PEM_WRITE_C)
+/**
+ * \brief           Write a public key to a PEM string
+ *
+ * \param ctx       public key to write away
+ * \param buf       buffer to write to
+ * \param size      size of the buffer
+ *
+ * \return          0 if successful, or a specific error code
+ */
+int mbedtls_pk_write_pubkey_pem( mbedtls_pk_context *ctx, unsigned char *buf, size_t size );
+
+/**
+ * \brief           Write a private key to a PKCS#1 or SEC1 PEM string
+ *
+ * \param ctx       private to write away
+ * \param buf       buffer to write to
+ * \param size      size of the buffer
+ *
+ * \return          0 if successful, or a specific error code
+ */
+int mbedtls_pk_write_key_pem( mbedtls_pk_context *ctx, unsigned char *buf, size_t size );
+#endif /* MBEDTLS_PEM_WRITE_C */
+#endif /* MBEDTLS_PK_WRITE_C */
+
+/*
+ * WARNING: Low-level functions. You probably do not want to use these unless
+ *          you are certain you do ;)
+ */
+
+#if defined(MBEDTLS_PK_PARSE_C)
+/**
+ * \brief           Parse a SubjectPublicKeyInfo DER structure
+ *
+ * \param p         the position in the ASN.1 data
+ * \param end       end of the buffer
+ * \param pk        the key to fill
+ *
+ * \return          0 if successful, or a specific PK error code
+ */
+int mbedtls_pk_parse_subpubkey( unsigned char **p, const unsigned char *end,
+                        mbedtls_pk_context *pk );
+#endif /* MBEDTLS_PK_PARSE_C */
+
+#if defined(MBEDTLS_PK_WRITE_C)
+/**
+ * \brief           Write a subjectPublicKey to ASN.1 data
+ *                  Note: function works backwards in data buffer
+ *
+ * \param p         reference to current position pointer
+ * \param start     start of the buffer (for bounds-checking)
+ * \param key       public key to write away
+ *
+ * \return          the length written or a negative error code
+ */
+int mbedtls_pk_write_pubkey( unsigned char **p, unsigned char *start,
+                     const mbedtls_pk_context *key );
+#endif /* MBEDTLS_PK_WRITE_C */
+
+/*
+ * Internal module functions. You probably do not want to use these unless you
+ * know you do.
+ */
+#if defined(MBEDTLS_FS_IO)
+int mbedtls_pk_load_file( const char *path, unsigned char **buf, size_t *n );
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MBEDTLS_PK_H */
diff --git a/tools/sdk/include/mbedtls/mbedtls/pk_internal.h b/tools/sdk/include/mbedtls/mbedtls/pk_internal.h
new file mode 100644
index 00000000..01d0f214
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/pk_internal.h
@@ -0,0 +1,114 @@
+/**
+ * \file pk.h
+ *
+ * \brief Public Key abstraction layer: wrapper functions
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+
+#ifndef MBEDTLS_PK_WRAP_H
+#define MBEDTLS_PK_WRAP_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#include "pk.h"
+
+struct mbedtls_pk_info_t
+{
+    /** Public key type */
+    mbedtls_pk_type_t type;
+
+    /** Type name */
+    const char *name;
+
+    /** Get key size in bits */
+    size_t (*get_bitlen)( const void * );
+
+    /** Tell if the context implements this type (e.g. ECKEY can do ECDSA) */
+    int (*can_do)( mbedtls_pk_type_t type );
+
+    /** Verify signature */
+    int (*verify_func)( void *ctx, mbedtls_md_type_t md_alg,
+                        const unsigned char *hash, size_t hash_len,
+                        const unsigned char *sig, size_t sig_len );
+
+    /** Make signature */
+    int (*sign_func)( void *ctx, mbedtls_md_type_t md_alg,
+                      const unsigned char *hash, size_t hash_len,
+                      unsigned char *sig, size_t *sig_len,
+                      int (*f_rng)(void *, unsigned char *, size_t),
+                      void *p_rng );
+
+    /** Decrypt message */
+    int (*decrypt_func)( void *ctx, const unsigned char *input, size_t ilen,
+                         unsigned char *output, size_t *olen, size_t osize,
+                         int (*f_rng)(void *, unsigned char *, size_t),
+                         void *p_rng );
+
+    /** Encrypt message */
+    int (*encrypt_func)( void *ctx, const unsigned char *input, size_t ilen,
+                         unsigned char *output, size_t *olen, size_t osize,
+                         int (*f_rng)(void *, unsigned char *, size_t),
+                         void *p_rng );
+
+    /** Check public-private key pair */
+    int (*check_pair_func)( const void *pub, const void *prv );
+
+    /** Allocate a new context */
+    void * (*ctx_alloc_func)( void );
+
+    /** Free the given context */
+    void (*ctx_free_func)( void *ctx );
+
+    /** Interface with the debug module */
+    void (*debug_func)( const void *ctx, mbedtls_pk_debug_item *items );
+
+};
+#if defined(MBEDTLS_PK_RSA_ALT_SUPPORT)
+/* Container for RSA-alt */
+typedef struct
+{
+    void *key;
+    mbedtls_pk_rsa_alt_decrypt_func decrypt_func;
+    mbedtls_pk_rsa_alt_sign_func sign_func;
+    mbedtls_pk_rsa_alt_key_len_func key_len_func;
+} mbedtls_rsa_alt_context;
+#endif
+
+#if defined(MBEDTLS_RSA_C)
+extern const mbedtls_pk_info_t mbedtls_rsa_info;
+#endif
+
+#if defined(MBEDTLS_ECP_C)
+extern const mbedtls_pk_info_t mbedtls_eckey_info;
+extern const mbedtls_pk_info_t mbedtls_eckeydh_info;
+#endif
+
+#if defined(MBEDTLS_ECDSA_C)
+extern const mbedtls_pk_info_t mbedtls_ecdsa_info;
+#endif
+
+#if defined(MBEDTLS_PK_RSA_ALT_SUPPORT)
+extern const mbedtls_pk_info_t mbedtls_rsa_alt_info;
+#endif
+
+#endif /* MBEDTLS_PK_WRAP_H */
diff --git a/tools/sdk/include/mbedtls/mbedtls/pkcs11.h b/tools/sdk/include/mbedtls/mbedtls/pkcs11.h
new file mode 100644
index 00000000..2e889281
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/pkcs11.h
@@ -0,0 +1,173 @@
+/**
+ * \file pkcs11.h
+ *
+ * \brief Wrapper for PKCS#11 library libpkcs11-helper
+ *
+ * \author Adriaan de Jong 
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_PKCS11_H
+#define MBEDTLS_PKCS11_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#if defined(MBEDTLS_PKCS11_C)
+
+#include "x509_crt.h"
+
+#include 
+
+#if ( defined(__ARMCC_VERSION) || defined(_MSC_VER) ) && \
+    !defined(inline) && !defined(__cplusplus)
+#define inline __inline
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Context for PKCS #11 private keys.
+ */
+typedef struct {
+        pkcs11h_certificate_t pkcs11h_cert;
+        int len;
+} mbedtls_pkcs11_context;
+
+/**
+ * Initialize a mbedtls_pkcs11_context.
+ * (Just making memory references valid.)
+ */
+void mbedtls_pkcs11_init( mbedtls_pkcs11_context *ctx );
+
+/**
+ * Fill in a mbed TLS certificate, based on the given PKCS11 helper certificate.
+ *
+ * \param cert          X.509 certificate to fill
+ * \param pkcs11h_cert  PKCS #11 helper certificate
+ *
+ * \return              0 on success.
+ */
+int mbedtls_pkcs11_x509_cert_bind( mbedtls_x509_crt *cert, pkcs11h_certificate_t pkcs11h_cert );
+
+/**
+ * Set up a mbedtls_pkcs11_context storing the given certificate. Note that the
+ * mbedtls_pkcs11_context will take over control of the certificate, freeing it when
+ * done.
+ *
+ * \param priv_key      Private key structure to fill.
+ * \param pkcs11_cert   PKCS #11 helper certificate
+ *
+ * \return              0 on success
+ */
+int mbedtls_pkcs11_priv_key_bind( mbedtls_pkcs11_context *priv_key,
+        pkcs11h_certificate_t pkcs11_cert );
+
+/**
+ * Free the contents of the given private key context. Note that the structure
+ * itself is not freed.
+ *
+ * \param priv_key      Private key structure to cleanup
+ */
+void mbedtls_pkcs11_priv_key_free( mbedtls_pkcs11_context *priv_key );
+
+/**
+ * \brief          Do an RSA private key decrypt, then remove the message
+ *                 padding
+ *
+ * \param ctx      PKCS #11 context
+ * \param mode     must be MBEDTLS_RSA_PRIVATE, for compatibility with rsa.c's signature
+ * \param input    buffer holding the encrypted data
+ * \param output   buffer that will hold the plaintext
+ * \param olen     will contain the plaintext length
+ * \param output_max_len    maximum length of the output buffer
+ *
+ * \return         0 if successful, or an MBEDTLS_ERR_RSA_XXX error code
+ *
+ * \note           The output buffer must be as large as the size
+ *                 of ctx->N (eg. 128 bytes if RSA-1024 is used) otherwise
+ *                 an error is thrown.
+ */
+int mbedtls_pkcs11_decrypt( mbedtls_pkcs11_context *ctx,
+                       int mode, size_t *olen,
+                       const unsigned char *input,
+                       unsigned char *output,
+                       size_t output_max_len );
+
+/**
+ * \brief          Do a private RSA to sign a message digest
+ *
+ * \param ctx      PKCS #11 context
+ * \param mode     must be MBEDTLS_RSA_PRIVATE, for compatibility with rsa.c's signature
+ * \param md_alg   a MBEDTLS_MD_XXX (use MBEDTLS_MD_NONE for signing raw data)
+ * \param hashlen  message digest length (for MBEDTLS_MD_NONE only)
+ * \param hash     buffer holding the message digest
+ * \param sig      buffer that will hold the ciphertext
+ *
+ * \return         0 if the signing operation was successful,
+ *                 or an MBEDTLS_ERR_RSA_XXX error code
+ *
+ * \note           The "sig" buffer must be as large as the size
+ *                 of ctx->N (eg. 128 bytes if RSA-1024 is used).
+ */
+int mbedtls_pkcs11_sign( mbedtls_pkcs11_context *ctx,
+                    int mode,
+                    mbedtls_md_type_t md_alg,
+                    unsigned int hashlen,
+                    const unsigned char *hash,
+                    unsigned char *sig );
+
+/**
+ * SSL/TLS wrappers for PKCS#11 functions
+ */
+static inline int mbedtls_ssl_pkcs11_decrypt( void *ctx, int mode, size_t *olen,
+                        const unsigned char *input, unsigned char *output,
+                        size_t output_max_len )
+{
+    return mbedtls_pkcs11_decrypt( (mbedtls_pkcs11_context *) ctx, mode, olen, input, output,
+                           output_max_len );
+}
+
+static inline int mbedtls_ssl_pkcs11_sign( void *ctx,
+                     int (*f_rng)(void *, unsigned char *, size_t), void *p_rng,
+                     int mode, mbedtls_md_type_t md_alg, unsigned int hashlen,
+                     const unsigned char *hash, unsigned char *sig )
+{
+    ((void) f_rng);
+    ((void) p_rng);
+    return mbedtls_pkcs11_sign( (mbedtls_pkcs11_context *) ctx, mode, md_alg,
+                        hashlen, hash, sig );
+}
+
+static inline size_t mbedtls_ssl_pkcs11_key_len( void *ctx )
+{
+    return ( (mbedtls_pkcs11_context *) ctx )->len;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MBEDTLS_PKCS11_C */
+
+#endif /* MBEDTLS_PKCS11_H */
diff --git a/tools/sdk/include/mbedtls/mbedtls/pkcs12.h b/tools/sdk/include/mbedtls/mbedtls/pkcs12.h
new file mode 100644
index 00000000..9b2d9045
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/pkcs12.h
@@ -0,0 +1,119 @@
+/**
+ * \file pkcs12.h
+ *
+ * \brief PKCS#12 Personal Information Exchange Syntax
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_PKCS12_H
+#define MBEDTLS_PKCS12_H
+
+#include "md.h"
+#include "cipher.h"
+#include "asn1.h"
+
+#include 
+
+#define MBEDTLS_ERR_PKCS12_BAD_INPUT_DATA                 -0x1F80  /**< Bad input parameters to function. */
+#define MBEDTLS_ERR_PKCS12_FEATURE_UNAVAILABLE            -0x1F00  /**< Feature not available, e.g. unsupported encryption scheme. */
+#define MBEDTLS_ERR_PKCS12_PBE_INVALID_FORMAT             -0x1E80  /**< PBE ASN.1 data not as expected. */
+#define MBEDTLS_ERR_PKCS12_PASSWORD_MISMATCH              -0x1E00  /**< Given private key password does not allow for correct decryption. */
+
+#define MBEDTLS_PKCS12_DERIVE_KEY       1   /**< encryption/decryption key */
+#define MBEDTLS_PKCS12_DERIVE_IV        2   /**< initialization vector     */
+#define MBEDTLS_PKCS12_DERIVE_MAC_KEY   3   /**< integrity / MAC key       */
+
+#define MBEDTLS_PKCS12_PBE_DECRYPT      0
+#define MBEDTLS_PKCS12_PBE_ENCRYPT      1
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief            PKCS12 Password Based function (encryption / decryption)
+ *                   for pbeWithSHAAnd128BitRC4
+ *
+ * \param pbe_params an ASN1 buffer containing the pkcs-12PbeParams structure
+ * \param mode       either MBEDTLS_PKCS12_PBE_ENCRYPT or MBEDTLS_PKCS12_PBE_DECRYPT
+ * \param pwd        the password used (may be NULL if no password is used)
+ * \param pwdlen     length of the password (may be 0)
+ * \param input      the input data
+ * \param len        data length
+ * \param output     the output buffer
+ *
+ * \return           0 if successful, or a MBEDTLS_ERR_XXX code
+ */
+int mbedtls_pkcs12_pbe_sha1_rc4_128( mbedtls_asn1_buf *pbe_params, int mode,
+                             const unsigned char *pwd,  size_t pwdlen,
+                             const unsigned char *input, size_t len,
+                             unsigned char *output );
+
+/**
+ * \brief            PKCS12 Password Based function (encryption / decryption)
+ *                   for cipher-based and mbedtls_md-based PBE's
+ *
+ * \param pbe_params an ASN1 buffer containing the pkcs-12PbeParams structure
+ * \param mode       either MBEDTLS_PKCS12_PBE_ENCRYPT or MBEDTLS_PKCS12_PBE_DECRYPT
+ * \param cipher_type the cipher used
+ * \param md_type     the mbedtls_md used
+ * \param pwd        the password used (may be NULL if no password is used)
+ * \param pwdlen     length of the password (may be 0)
+ * \param input      the input data
+ * \param len        data length
+ * \param output     the output buffer
+ *
+ * \return           0 if successful, or a MBEDTLS_ERR_XXX code
+ */
+int mbedtls_pkcs12_pbe( mbedtls_asn1_buf *pbe_params, int mode,
+                mbedtls_cipher_type_t cipher_type, mbedtls_md_type_t md_type,
+                const unsigned char *pwd,  size_t pwdlen,
+                const unsigned char *input, size_t len,
+                unsigned char *output );
+
+/**
+ * \brief            The PKCS#12 derivation function uses a password and a salt
+ *                   to produce pseudo-random bits for a particular "purpose".
+ *
+ *                   Depending on the given id, this function can produce an
+ *                   encryption/decryption key, an nitialization vector or an
+ *                   integrity key.
+ *
+ * \param data       buffer to store the derived data in
+ * \param datalen    length to fill
+ * \param pwd        password to use (may be NULL if no password is used)
+ * \param pwdlen     length of the password (may be 0)
+ * \param salt       salt buffer to use
+ * \param saltlen    length of the salt
+ * \param mbedtls_md         mbedtls_md type to use during the derivation
+ * \param id         id that describes the purpose (can be MBEDTLS_PKCS12_DERIVE_KEY,
+ *                   MBEDTLS_PKCS12_DERIVE_IV or MBEDTLS_PKCS12_DERIVE_MAC_KEY)
+ * \param iterations number of iterations
+ *
+ * \return          0 if successful, or a MD, BIGNUM type error.
+ */
+int mbedtls_pkcs12_derivation( unsigned char *data, size_t datalen,
+                       const unsigned char *pwd, size_t pwdlen,
+                       const unsigned char *salt, size_t saltlen,
+                       mbedtls_md_type_t mbedtls_md, int id, int iterations );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* pkcs12.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/pkcs5.h b/tools/sdk/include/mbedtls/mbedtls/pkcs5.h
new file mode 100644
index 00000000..ec5cb9e7
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/pkcs5.h
@@ -0,0 +1,94 @@
+/**
+ * \file pkcs5.h
+ *
+ * \brief PKCS#5 functions
+ *
+ * \author Mathias Olsson 
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_PKCS5_H
+#define MBEDTLS_PKCS5_H
+
+#include "asn1.h"
+#include "md.h"
+
+#include 
+#include 
+
+#define MBEDTLS_ERR_PKCS5_BAD_INPUT_DATA                  -0x2f80  /**< Bad input parameters to function. */
+#define MBEDTLS_ERR_PKCS5_INVALID_FORMAT                  -0x2f00  /**< Unexpected ASN.1 data. */
+#define MBEDTLS_ERR_PKCS5_FEATURE_UNAVAILABLE             -0x2e80  /**< Requested encryption or digest alg not available. */
+#define MBEDTLS_ERR_PKCS5_PASSWORD_MISMATCH               -0x2e00  /**< Given private key password does not allow for correct decryption. */
+
+#define MBEDTLS_PKCS5_DECRYPT      0
+#define MBEDTLS_PKCS5_ENCRYPT      1
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          PKCS#5 PBES2 function
+ *
+ * \param pbe_params the ASN.1 algorithm parameters
+ * \param mode       either MBEDTLS_PKCS5_DECRYPT or MBEDTLS_PKCS5_ENCRYPT
+ * \param pwd        password to use when generating key
+ * \param pwdlen     length of password
+ * \param data       data to process
+ * \param datalen    length of data
+ * \param output     output buffer
+ *
+ * \returns        0 on success, or a MBEDTLS_ERR_XXX code if verification fails.
+ */
+int mbedtls_pkcs5_pbes2( const mbedtls_asn1_buf *pbe_params, int mode,
+                 const unsigned char *pwd,  size_t pwdlen,
+                 const unsigned char *data, size_t datalen,
+                 unsigned char *output );
+
+/**
+ * \brief          PKCS#5 PBKDF2 using HMAC
+ *
+ * \param ctx      Generic HMAC context
+ * \param password Password to use when generating key
+ * \param plen     Length of password
+ * \param salt     Salt to use when generating key
+ * \param slen     Length of salt
+ * \param iteration_count       Iteration count
+ * \param key_length            Length of generated key in bytes
+ * \param output   Generated key. Must be at least as big as key_length
+ *
+ * \returns        0 on success, or a MBEDTLS_ERR_XXX code if verification fails.
+ */
+int mbedtls_pkcs5_pbkdf2_hmac( mbedtls_md_context_t *ctx, const unsigned char *password,
+                       size_t plen, const unsigned char *salt, size_t slen,
+                       unsigned int iteration_count,
+                       uint32_t key_length, unsigned char *output );
+
+/**
+ * \brief          Checkup routine
+ *
+ * \return         0 if successful, or 1 if the test failed
+ */
+int mbedtls_pkcs5_self_test( int verbose );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* pkcs5.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/platform.h b/tools/sdk/include/mbedtls/mbedtls/platform.h
new file mode 100644
index 00000000..caf8f252
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/platform.h
@@ -0,0 +1,324 @@
+/**
+ * \file platform.h
+ *
+ * \brief mbed TLS Platform abstraction layer
+ *
+ *  Copyright (C) 2006-2016, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_PLATFORM_H
+#define MBEDTLS_PLATFORM_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \name SECTION: Module settings
+ *
+ * The configuration options you can set for this module are in this section.
+ * Either change them in config.h or define them on the compiler command line.
+ * \{
+ */
+
+#if !defined(MBEDTLS_PLATFORM_NO_STD_FUNCTIONS)
+#include 
+#include 
+#include 
+#if !defined(MBEDTLS_PLATFORM_STD_SNPRINTF)
+#if defined(_WIN32)
+#define MBEDTLS_PLATFORM_STD_SNPRINTF   mbedtls_platform_win32_snprintf /**< Default snprintf to use  */
+#else
+#define MBEDTLS_PLATFORM_STD_SNPRINTF   snprintf /**< Default snprintf to use  */
+#endif
+#endif
+#if !defined(MBEDTLS_PLATFORM_STD_PRINTF)
+#define MBEDTLS_PLATFORM_STD_PRINTF   printf /**< Default printf to use  */
+#endif
+#if !defined(MBEDTLS_PLATFORM_STD_FPRINTF)
+#define MBEDTLS_PLATFORM_STD_FPRINTF fprintf /**< Default fprintf to use */
+#endif
+#if !defined(MBEDTLS_PLATFORM_STD_CALLOC)
+#define MBEDTLS_PLATFORM_STD_CALLOC   calloc /**< Default allocator to use */
+#endif
+#if !defined(MBEDTLS_PLATFORM_STD_FREE)
+#define MBEDTLS_PLATFORM_STD_FREE       free /**< Default free to use */
+#endif
+#if !defined(MBEDTLS_PLATFORM_STD_EXIT)
+#define MBEDTLS_PLATFORM_STD_EXIT      exit /**< Default exit to use */
+#endif
+#if !defined(MBEDTLS_PLATFORM_STD_TIME)
+#define MBEDTLS_PLATFORM_STD_TIME       time    /**< Default time to use */
+#endif
+#if !defined(MBEDTLS_PLATFORM_STD_EXIT_SUCCESS)
+#define MBEDTLS_PLATFORM_STD_EXIT_SUCCESS  EXIT_SUCCESS /**< Default exit value to use */
+#endif
+#if !defined(MBEDTLS_PLATFORM_STD_EXIT_FAILURE)
+#define MBEDTLS_PLATFORM_STD_EXIT_FAILURE  EXIT_FAILURE /**< Default exit value to use */
+#endif
+#if defined(MBEDTLS_FS_IO)
+#if !defined(MBEDTLS_PLATFORM_STD_NV_SEED_READ)
+#define MBEDTLS_PLATFORM_STD_NV_SEED_READ   mbedtls_platform_std_nv_seed_read
+#endif
+#if !defined(MBEDTLS_PLATFORM_STD_NV_SEED_WRITE)
+#define MBEDTLS_PLATFORM_STD_NV_SEED_WRITE  mbedtls_platform_std_nv_seed_write
+#endif
+#if !defined(MBEDTLS_PLATFORM_STD_NV_SEED_FILE)
+#define MBEDTLS_PLATFORM_STD_NV_SEED_FILE   "seedfile"
+#endif
+#endif /* MBEDTLS_FS_IO */
+#else /* MBEDTLS_PLATFORM_NO_STD_FUNCTIONS */
+#if defined(MBEDTLS_PLATFORM_STD_MEM_HDR)
+#include MBEDTLS_PLATFORM_STD_MEM_HDR
+#endif
+#endif /* MBEDTLS_PLATFORM_NO_STD_FUNCTIONS */
+
+
+/* \} name SECTION: Module settings */
+
+/*
+ * The function pointers for calloc and free
+ */
+#if defined(MBEDTLS_PLATFORM_MEMORY)
+#if defined(MBEDTLS_PLATFORM_FREE_MACRO) && \
+    defined(MBEDTLS_PLATFORM_CALLOC_MACRO)
+#define mbedtls_free       MBEDTLS_PLATFORM_FREE_MACRO
+#define mbedtls_calloc     MBEDTLS_PLATFORM_CALLOC_MACRO
+#else
+/* For size_t */
+#include 
+extern void * (*mbedtls_calloc)( size_t n, size_t size );
+extern void (*mbedtls_free)( void *ptr );
+
+/**
+ * \brief   Set your own memory implementation function pointers
+ *
+ * \param calloc_func   the calloc function implementation
+ * \param free_func     the free function implementation
+ *
+ * \return              0 if successful
+ */
+int mbedtls_platform_set_calloc_free( void * (*calloc_func)( size_t, size_t ),
+                              void (*free_func)( void * ) );
+#endif /* MBEDTLS_PLATFORM_FREE_MACRO && MBEDTLS_PLATFORM_CALLOC_MACRO */
+#else /* !MBEDTLS_PLATFORM_MEMORY */
+#define mbedtls_free       free
+#define mbedtls_calloc     calloc
+#endif /* MBEDTLS_PLATFORM_MEMORY && !MBEDTLS_PLATFORM_{FREE,CALLOC}_MACRO */
+
+/*
+ * The function pointers for fprintf
+ */
+#if defined(MBEDTLS_PLATFORM_FPRINTF_ALT)
+/* We need FILE * */
+#include 
+extern int (*mbedtls_fprintf)( FILE *stream, const char *format, ... );
+
+/**
+ * \brief   Set your own fprintf function pointer
+ *
+ * \param fprintf_func   the fprintf function implementation
+ *
+ * \return              0
+ */
+int mbedtls_platform_set_fprintf( int (*fprintf_func)( FILE *stream, const char *,
+                                               ... ) );
+#else
+#if defined(MBEDTLS_PLATFORM_FPRINTF_MACRO)
+#define mbedtls_fprintf    MBEDTLS_PLATFORM_FPRINTF_MACRO
+#else
+#define mbedtls_fprintf    fprintf
+#endif /* MBEDTLS_PLATFORM_FPRINTF_MACRO */
+#endif /* MBEDTLS_PLATFORM_FPRINTF_ALT */
+
+/*
+ * The function pointers for printf
+ */
+#if defined(MBEDTLS_PLATFORM_PRINTF_ALT)
+extern int (*mbedtls_printf)( const char *format, ... );
+
+/**
+ * \brief   Set your own printf function pointer
+ *
+ * \param printf_func   the printf function implementation
+ *
+ * \return              0
+ */
+int mbedtls_platform_set_printf( int (*printf_func)( const char *, ... ) );
+#else /* !MBEDTLS_PLATFORM_PRINTF_ALT */
+#if defined(MBEDTLS_PLATFORM_PRINTF_MACRO)
+#define mbedtls_printf     MBEDTLS_PLATFORM_PRINTF_MACRO
+#else
+#define mbedtls_printf     printf
+#endif /* MBEDTLS_PLATFORM_PRINTF_MACRO */
+#endif /* MBEDTLS_PLATFORM_PRINTF_ALT */
+
+/*
+ * The function pointers for snprintf
+ *
+ * The snprintf implementation should conform to C99:
+ * - it *must* always correctly zero-terminate the buffer
+ *   (except when n == 0, then it must leave the buffer untouched)
+ * - however it is acceptable to return -1 instead of the required length when
+ *   the destination buffer is too short.
+ */
+#if defined(_WIN32)
+/* For Windows (inc. MSYS2), we provide our own fixed implementation */
+int mbedtls_platform_win32_snprintf( char *s, size_t n, const char *fmt, ... );
+#endif
+
+#if defined(MBEDTLS_PLATFORM_SNPRINTF_ALT)
+extern int (*mbedtls_snprintf)( char * s, size_t n, const char * format, ... );
+
+/**
+ * \brief   Set your own snprintf function pointer
+ *
+ * \param snprintf_func   the snprintf function implementation
+ *
+ * \return              0
+ */
+int mbedtls_platform_set_snprintf( int (*snprintf_func)( char * s, size_t n,
+                                                 const char * format, ... ) );
+#else /* MBEDTLS_PLATFORM_SNPRINTF_ALT */
+#if defined(MBEDTLS_PLATFORM_SNPRINTF_MACRO)
+#define mbedtls_snprintf   MBEDTLS_PLATFORM_SNPRINTF_MACRO
+#else
+#define mbedtls_snprintf   snprintf
+#endif /* MBEDTLS_PLATFORM_SNPRINTF_MACRO */
+#endif /* MBEDTLS_PLATFORM_SNPRINTF_ALT */
+
+/*
+ * The function pointers for exit
+ */
+#if defined(MBEDTLS_PLATFORM_EXIT_ALT)
+extern void (*mbedtls_exit)( int status );
+
+/**
+ * \brief   Set your own exit function pointer
+ *
+ * \param exit_func   the exit function implementation
+ *
+ * \return              0
+ */
+int mbedtls_platform_set_exit( void (*exit_func)( int status ) );
+#else
+#if defined(MBEDTLS_PLATFORM_EXIT_MACRO)
+#define mbedtls_exit   MBEDTLS_PLATFORM_EXIT_MACRO
+#else
+#define mbedtls_exit   exit
+#endif /* MBEDTLS_PLATFORM_EXIT_MACRO */
+#endif /* MBEDTLS_PLATFORM_EXIT_ALT */
+
+/*
+ * The default exit values
+ */
+#if defined(MBEDTLS_PLATFORM_STD_EXIT_SUCCESS)
+#define MBEDTLS_EXIT_SUCCESS MBEDTLS_PLATFORM_STD_EXIT_SUCCESS
+#else
+#define MBEDTLS_EXIT_SUCCESS 0
+#endif
+#if defined(MBEDTLS_PLATFORM_STD_EXIT_FAILURE)
+#define MBEDTLS_EXIT_FAILURE MBEDTLS_PLATFORM_STD_EXIT_FAILURE
+#else
+#define MBEDTLS_EXIT_FAILURE 1
+#endif
+
+/*
+ * The time_t datatype
+ */
+#if defined(MBEDTLS_PLATFORM_TIME_TYPE_MACRO)
+typedef MBEDTLS_PLATFORM_TIME_TYPE_MACRO mbedtls_time_t;
+#else
+/* For time_t */
+#include 
+typedef time_t mbedtls_time_t;
+#endif /* MBEDTLS_PLATFORM_TIME_TYPE_MACRO */
+
+/*
+ * The function pointers for time
+ */
+#if defined(MBEDTLS_PLATFORM_TIME_ALT)
+extern mbedtls_time_t (*mbedtls_time)( mbedtls_time_t* time );
+
+/**
+ * \brief   Set your own time function pointer
+ *
+ * \param   time_func   the time function implementation
+ *
+ * \return              0
+ */
+int mbedtls_platform_set_time( mbedtls_time_t (*time_func)( mbedtls_time_t* time ) );
+#else
+#if defined(MBEDTLS_PLATFORM_TIME_MACRO)
+#define mbedtls_time    MBEDTLS_PLATFORM_TIME_MACRO
+#else
+#define mbedtls_time   time
+#endif /* MBEDTLS_PLATFORM_TIME_MACRO */
+#endif /* MBEDTLS_PLATFORM_TIME_ALT */
+
+/*
+ * The function pointers for reading from and writing a seed file to
+ * Non-Volatile storage (NV) in a platform-independent way
+ *
+ * Only enabled when the NV seed entropy source is enabled
+ */
+#if defined(MBEDTLS_ENTROPY_NV_SEED)
+#if !defined(MBEDTLS_PLATFORM_NO_STD_FUNCTIONS) && defined(MBEDTLS_FS_IO)
+/* Internal standard platform definitions */
+int mbedtls_platform_std_nv_seed_read( unsigned char *buf, size_t buf_len );
+int mbedtls_platform_std_nv_seed_write( unsigned char *buf, size_t buf_len );
+#endif
+
+#if defined(MBEDTLS_PLATFORM_NV_SEED_ALT)
+extern int (*mbedtls_nv_seed_read)( unsigned char *buf, size_t buf_len );
+extern int (*mbedtls_nv_seed_write)( unsigned char *buf, size_t buf_len );
+
+/**
+ * \brief   Set your own seed file writing/reading functions
+ *
+ * \param   nv_seed_read_func   the seed reading function implementation
+ * \param   nv_seed_write_func  the seed writing function implementation
+ *
+ * \return              0
+ */
+int mbedtls_platform_set_nv_seed(
+            int (*nv_seed_read_func)( unsigned char *buf, size_t buf_len ),
+            int (*nv_seed_write_func)( unsigned char *buf, size_t buf_len )
+            );
+#else
+#if defined(MBEDTLS_PLATFORM_NV_SEED_READ_MACRO) && \
+    defined(MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO)
+#define mbedtls_nv_seed_read    MBEDTLS_PLATFORM_NV_SEED_READ_MACRO
+#define mbedtls_nv_seed_write   MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO
+#else
+#define mbedtls_nv_seed_read    mbedtls_platform_std_nv_seed_read
+#define mbedtls_nv_seed_write   mbedtls_platform_std_nv_seed_write
+#endif
+#endif /* MBEDTLS_PLATFORM_NV_SEED_ALT */
+#endif /* MBEDTLS_ENTROPY_NV_SEED */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* platform.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/ripemd160.h b/tools/sdk/include/mbedtls/mbedtls/ripemd160.h
new file mode 100644
index 00000000..7083fc85
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/ripemd160.h
@@ -0,0 +1,138 @@
+/**
+ * \file ripemd160.h
+ *
+ * \brief RIPE MD-160 message digest
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_RIPEMD160_H
+#define MBEDTLS_RIPEMD160_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#include 
+#include 
+
+#if !defined(MBEDTLS_RIPEMD160_ALT)
+// Regular implementation
+//
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          RIPEMD-160 context structure
+ */
+typedef struct
+{
+    uint32_t total[2];          /*!< number of bytes processed  */
+    uint32_t state[5];          /*!< intermediate digest state  */
+    unsigned char buffer[64];   /*!< data block being processed */
+}
+mbedtls_ripemd160_context;
+
+/**
+ * \brief          Initialize RIPEMD-160 context
+ *
+ * \param ctx      RIPEMD-160 context to be initialized
+ */
+void mbedtls_ripemd160_init( mbedtls_ripemd160_context *ctx );
+
+/**
+ * \brief          Clear RIPEMD-160 context
+ *
+ * \param ctx      RIPEMD-160 context to be cleared
+ */
+void mbedtls_ripemd160_free( mbedtls_ripemd160_context *ctx );
+
+/**
+ * \brief          Clone (the state of) an RIPEMD-160 context
+ *
+ * \param dst      The destination context
+ * \param src      The context to be cloned
+ */
+void mbedtls_ripemd160_clone( mbedtls_ripemd160_context *dst,
+                        const mbedtls_ripemd160_context *src );
+
+/**
+ * \brief          RIPEMD-160 context setup
+ *
+ * \param ctx      context to be initialized
+ */
+void mbedtls_ripemd160_starts( mbedtls_ripemd160_context *ctx );
+
+/**
+ * \brief          RIPEMD-160 process buffer
+ *
+ * \param ctx      RIPEMD-160 context
+ * \param input    buffer holding the  data
+ * \param ilen     length of the input data
+ */
+void mbedtls_ripemd160_update( mbedtls_ripemd160_context *ctx,
+                       const unsigned char *input, size_t ilen );
+
+/**
+ * \brief          RIPEMD-160 final digest
+ *
+ * \param ctx      RIPEMD-160 context
+ * \param output   RIPEMD-160 checksum result
+ */
+void mbedtls_ripemd160_finish( mbedtls_ripemd160_context *ctx, unsigned char output[20] );
+
+/* Internal use */
+void mbedtls_ripemd160_process( mbedtls_ripemd160_context *ctx, const unsigned char data[64] );
+
+#ifdef __cplusplus
+}
+#endif
+
+#else  /* MBEDTLS_RIPEMD160_ALT */
+#include "ripemd160.h"
+#endif /* MBEDTLS_RIPEMD160_ALT */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          Output = RIPEMD-160( input buffer )
+ *
+ * \param input    buffer holding the  data
+ * \param ilen     length of the input data
+ * \param output   RIPEMD-160 checksum result
+ */
+void mbedtls_ripemd160( const unsigned char *input, size_t ilen,
+                unsigned char output[20] );
+
+/**
+ * \brief          Checkup routine
+ *
+ * \return         0 if successful, or 1 if the test failed
+ */
+int mbedtls_ripemd160_self_test( int verbose );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* mbedtls_ripemd160.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/rsa.h b/tools/sdk/include/mbedtls/mbedtls/rsa.h
new file mode 100644
index 00000000..9c8645df
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/rsa.h
@@ -0,0 +1,652 @@
+/**
+ * \file rsa.h
+ *
+ * \brief The RSA public-key cryptosystem
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_RSA_H
+#define MBEDTLS_RSA_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#include "bignum.h"
+#include "md.h"
+
+#if defined(MBEDTLS_THREADING_C)
+#include "threading.h"
+#endif
+
+/*
+ * RSA Error codes
+ */
+#define MBEDTLS_ERR_RSA_BAD_INPUT_DATA                    -0x4080  /**< Bad input parameters to function. */
+#define MBEDTLS_ERR_RSA_INVALID_PADDING                   -0x4100  /**< Input data contains invalid padding and is rejected. */
+#define MBEDTLS_ERR_RSA_KEY_GEN_FAILED                    -0x4180  /**< Something failed during generation of a key. */
+#define MBEDTLS_ERR_RSA_KEY_CHECK_FAILED                  -0x4200  /**< Key failed to pass the library's validity check. */
+#define MBEDTLS_ERR_RSA_PUBLIC_FAILED                     -0x4280  /**< The public key operation failed. */
+#define MBEDTLS_ERR_RSA_PRIVATE_FAILED                    -0x4300  /**< The private key operation failed. */
+#define MBEDTLS_ERR_RSA_VERIFY_FAILED                     -0x4380  /**< The PKCS#1 verification failed. */
+#define MBEDTLS_ERR_RSA_OUTPUT_TOO_LARGE                  -0x4400  /**< The output buffer for decryption is not large enough. */
+#define MBEDTLS_ERR_RSA_RNG_FAILED                        -0x4480  /**< The random generator failed to generate non-zeros. */
+
+/*
+ * RSA constants
+ */
+#define MBEDTLS_RSA_PUBLIC      0
+#define MBEDTLS_RSA_PRIVATE     1
+
+#define MBEDTLS_RSA_PKCS_V15    0
+#define MBEDTLS_RSA_PKCS_V21    1
+
+#define MBEDTLS_RSA_SIGN        1
+#define MBEDTLS_RSA_CRYPT       2
+
+#define MBEDTLS_RSA_SALT_LEN_ANY    -1
+
+/*
+ * The above constants may be used even if the RSA module is compile out,
+ * eg for alternative (PKCS#11) RSA implemenations in the PK layers.
+ */
+#if defined(MBEDTLS_RSA_C)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          RSA context structure
+ */
+typedef struct
+{
+    int ver;                    /*!<  always 0          */
+    size_t len;                 /*!<  size(N) in chars  */
+
+    mbedtls_mpi N;                      /*!<  public modulus    */
+    mbedtls_mpi E;                      /*!<  public exponent   */
+
+    mbedtls_mpi D;                      /*!<  private exponent  */
+    mbedtls_mpi P;                      /*!<  1st prime factor  */
+    mbedtls_mpi Q;                      /*!<  2nd prime factor  */
+    mbedtls_mpi DP;                     /*!<  D % (P - 1)       */
+    mbedtls_mpi DQ;                     /*!<  D % (Q - 1)       */
+    mbedtls_mpi QP;                     /*!<  1 / (Q % P)       */
+
+    mbedtls_mpi RN;                     /*!<  cached R^2 mod N  */
+    mbedtls_mpi RP;                     /*!<  cached R^2 mod P  */
+    mbedtls_mpi RQ;                     /*!<  cached R^2 mod Q  */
+
+    mbedtls_mpi Vi;                     /*!<  cached blinding value     */
+    mbedtls_mpi Vf;                     /*!<  cached un-blinding value  */
+
+    int padding;                /*!<  MBEDTLS_RSA_PKCS_V15 for 1.5 padding and
+                                      RSA_PKCS_v21 for OAEP/PSS         */
+    int hash_id;                /*!<  Hash identifier of mbedtls_md_type_t as
+                                      specified in the mbedtls_md.h header file
+                                      for the EME-OAEP and EMSA-PSS
+                                      encoding                          */
+#if defined(MBEDTLS_THREADING_C)
+    mbedtls_threading_mutex_t mutex;    /*!<  Thread-safety mutex       */
+#endif
+}
+mbedtls_rsa_context;
+
+/**
+ * \brief          Initialize an RSA context
+ *
+ *                 Note: Set padding to MBEDTLS_RSA_PKCS_V21 for the RSAES-OAEP
+ *                 encryption scheme and the RSASSA-PSS signature scheme.
+ *
+ * \param ctx      RSA context to be initialized
+ * \param padding  MBEDTLS_RSA_PKCS_V15 or MBEDTLS_RSA_PKCS_V21
+ * \param hash_id  MBEDTLS_RSA_PKCS_V21 hash identifier
+ *
+ * \note           The hash_id parameter is actually ignored
+ *                 when using MBEDTLS_RSA_PKCS_V15 padding.
+ *
+ * \note           Choice of padding mode is strictly enforced for private key
+ *                 operations, since there might be security concerns in
+ *                 mixing padding modes. For public key operations it's merely
+ *                 a default value, which can be overriden by calling specific
+ *                 rsa_rsaes_xxx or rsa_rsassa_xxx functions.
+ *
+ * \note           The chosen hash is always used for OEAP encryption.
+ *                 For PSS signatures, it's always used for making signatures,
+ *                 but can be overriden (and always is, if set to
+ *                 MBEDTLS_MD_NONE) for verifying them.
+ */
+void mbedtls_rsa_init( mbedtls_rsa_context *ctx,
+               int padding,
+               int hash_id);
+
+/**
+ * \brief          Set padding for an already initialized RSA context
+ *                 See \c mbedtls_rsa_init() for details.
+ *
+ * \param ctx      RSA context to be set
+ * \param padding  MBEDTLS_RSA_PKCS_V15 or MBEDTLS_RSA_PKCS_V21
+ * \param hash_id  MBEDTLS_RSA_PKCS_V21 hash identifier
+ */
+void mbedtls_rsa_set_padding( mbedtls_rsa_context *ctx, int padding, int hash_id);
+
+/**
+ * \brief          Generate an RSA keypair
+ *
+ * \param ctx      RSA context that will hold the key
+ * \param f_rng    RNG function
+ * \param p_rng    RNG parameter
+ * \param nbits    size of the public key in bits
+ * \param exponent public exponent (e.g., 65537)
+ *
+ * \note           mbedtls_rsa_init() must be called beforehand to setup
+ *                 the RSA context.
+ *
+ * \return         0 if successful, or an MBEDTLS_ERR_RSA_XXX error code
+ */
+int mbedtls_rsa_gen_key( mbedtls_rsa_context *ctx,
+                 int (*f_rng)(void *, unsigned char *, size_t),
+                 void *p_rng,
+                 unsigned int nbits, int exponent );
+
+/**
+ * \brief          Check a public RSA key
+ *
+ * \param ctx      RSA context to be checked
+ *
+ * \return         0 if successful, or an MBEDTLS_ERR_RSA_XXX error code
+ */
+int mbedtls_rsa_check_pubkey( const mbedtls_rsa_context *ctx );
+
+/**
+ * \brief          Check a private RSA key
+ *
+ * \param ctx      RSA context to be checked
+ *
+ * \return         0 if successful, or an MBEDTLS_ERR_RSA_XXX error code
+ */
+int mbedtls_rsa_check_privkey( const mbedtls_rsa_context *ctx );
+
+/**
+ * \brief          Check a public-private RSA key pair.
+ *                 Check each of the contexts, and make sure they match.
+ *
+ * \param pub      RSA context holding the public key
+ * \param prv      RSA context holding the private key
+ *
+ * \return         0 if successful, or an MBEDTLS_ERR_RSA_XXX error code
+ */
+int mbedtls_rsa_check_pub_priv( const mbedtls_rsa_context *pub, const mbedtls_rsa_context *prv );
+
+/**
+ * \brief          Do an RSA public key operation
+ *
+ * \param ctx      RSA context
+ * \param input    input buffer
+ * \param output   output buffer
+ *
+ * \return         0 if successful, or an MBEDTLS_ERR_RSA_XXX error code
+ *
+ * \note           This function does NOT take care of message
+ *                 padding. Also, be sure to set input[0] = 0 or assure that
+ *                 input is smaller than N.
+ *
+ * \note           The input and output buffers must be large
+ *                 enough (eg. 128 bytes if RSA-1024 is used).
+ */
+int mbedtls_rsa_public( mbedtls_rsa_context *ctx,
+                const unsigned char *input,
+                unsigned char *output );
+
+/**
+ * \brief          Do an RSA private key operation
+ *
+ * \param ctx      RSA context
+ * \param f_rng    RNG function (Needed for blinding)
+ * \param p_rng    RNG parameter
+ * \param input    input buffer
+ * \param output   output buffer
+ *
+ * \return         0 if successful, or an MBEDTLS_ERR_RSA_XXX error code
+ *
+ * \note           The input and output buffers must be large
+ *                 enough (eg. 128 bytes if RSA-1024 is used).
+ */
+int mbedtls_rsa_private( mbedtls_rsa_context *ctx,
+                 int (*f_rng)(void *, unsigned char *, size_t),
+                 void *p_rng,
+                 const unsigned char *input,
+                 unsigned char *output );
+
+/**
+ * \brief          Generic wrapper to perform a PKCS#1 encryption using the
+ *                 mode from the context. Add the message padding, then do an
+ *                 RSA operation.
+ *
+ * \param ctx      RSA context
+ * \param f_rng    RNG function (Needed for padding and PKCS#1 v2.1 encoding
+ *                               and MBEDTLS_RSA_PRIVATE)
+ * \param p_rng    RNG parameter
+ * \param mode     MBEDTLS_RSA_PUBLIC or MBEDTLS_RSA_PRIVATE
+ * \param ilen     contains the plaintext length
+ * \param input    buffer holding the data to be encrypted
+ * \param output   buffer that will hold the ciphertext
+ *
+ * \return         0 if successful, or an MBEDTLS_ERR_RSA_XXX error code
+ *
+ * \note           The output buffer must be as large as the size
+ *                 of ctx->N (eg. 128 bytes if RSA-1024 is used).
+ */
+int mbedtls_rsa_pkcs1_encrypt( mbedtls_rsa_context *ctx,
+                       int (*f_rng)(void *, unsigned char *, size_t),
+                       void *p_rng,
+                       int mode, size_t ilen,
+                       const unsigned char *input,
+                       unsigned char *output );
+
+/**
+ * \brief          Perform a PKCS#1 v1.5 encryption (RSAES-PKCS1-v1_5-ENCRYPT)
+ *
+ * \param ctx      RSA context
+ * \param f_rng    RNG function (Needed for padding and MBEDTLS_RSA_PRIVATE)
+ * \param p_rng    RNG parameter
+ * \param mode     MBEDTLS_RSA_PUBLIC or MBEDTLS_RSA_PRIVATE
+ * \param ilen     contains the plaintext length
+ * \param input    buffer holding the data to be encrypted
+ * \param output   buffer that will hold the ciphertext
+ *
+ * \return         0 if successful, or an MBEDTLS_ERR_RSA_XXX error code
+ *
+ * \note           The output buffer must be as large as the size
+ *                 of ctx->N (eg. 128 bytes if RSA-1024 is used).
+ */
+int mbedtls_rsa_rsaes_pkcs1_v15_encrypt( mbedtls_rsa_context *ctx,
+                                 int (*f_rng)(void *, unsigned char *, size_t),
+                                 void *p_rng,
+                                 int mode, size_t ilen,
+                                 const unsigned char *input,
+                                 unsigned char *output );
+
+/**
+ * \brief          Perform a PKCS#1 v2.1 OAEP encryption (RSAES-OAEP-ENCRYPT)
+ *
+ * \param ctx      RSA context
+ * \param f_rng    RNG function (Needed for padding and PKCS#1 v2.1 encoding
+ *                               and MBEDTLS_RSA_PRIVATE)
+ * \param p_rng    RNG parameter
+ * \param mode     MBEDTLS_RSA_PUBLIC or MBEDTLS_RSA_PRIVATE
+ * \param label    buffer holding the custom label to use
+ * \param label_len contains the label length
+ * \param ilen     contains the plaintext length
+ * \param input    buffer holding the data to be encrypted
+ * \param output   buffer that will hold the ciphertext
+ *
+ * \return         0 if successful, or an MBEDTLS_ERR_RSA_XXX error code
+ *
+ * \note           The output buffer must be as large as the size
+ *                 of ctx->N (eg. 128 bytes if RSA-1024 is used).
+ */
+int mbedtls_rsa_rsaes_oaep_encrypt( mbedtls_rsa_context *ctx,
+                            int (*f_rng)(void *, unsigned char *, size_t),
+                            void *p_rng,
+                            int mode,
+                            const unsigned char *label, size_t label_len,
+                            size_t ilen,
+                            const unsigned char *input,
+                            unsigned char *output );
+
+/**
+ * \brief          Generic wrapper to perform a PKCS#1 decryption using the
+ *                 mode from the context. Do an RSA operation, then remove
+ *                 the message padding
+ *
+ * \param ctx      RSA context
+ * \param f_rng    RNG function (Only needed for MBEDTLS_RSA_PRIVATE)
+ * \param p_rng    RNG parameter
+ * \param mode     MBEDTLS_RSA_PUBLIC or MBEDTLS_RSA_PRIVATE
+ * \param olen     will contain the plaintext length
+ * \param input    buffer holding the encrypted data
+ * \param output   buffer that will hold the plaintext
+ * \param output_max_len    maximum length of the output buffer
+ *
+ * \return         0 if successful, or an MBEDTLS_ERR_RSA_XXX error code
+ *
+ * \note           The output buffer must be as large as the size
+ *                 of ctx->N (eg. 128 bytes if RSA-1024 is used) otherwise
+ *                 an error is thrown.
+ */
+int mbedtls_rsa_pkcs1_decrypt( mbedtls_rsa_context *ctx,
+                       int (*f_rng)(void *, unsigned char *, size_t),
+                       void *p_rng,
+                       int mode, size_t *olen,
+                       const unsigned char *input,
+                       unsigned char *output,
+                       size_t output_max_len );
+
+/**
+ * \brief          Perform a PKCS#1 v1.5 decryption (RSAES-PKCS1-v1_5-DECRYPT)
+ *
+ * \param ctx      RSA context
+ * \param f_rng    RNG function (Only needed for MBEDTLS_RSA_PRIVATE)
+ * \param p_rng    RNG parameter
+ * \param mode     MBEDTLS_RSA_PUBLIC or MBEDTLS_RSA_PRIVATE
+ * \param olen     will contain the plaintext length
+ * \param input    buffer holding the encrypted data
+ * \param output   buffer that will hold the plaintext
+ * \param output_max_len    maximum length of the output buffer
+ *
+ * \return         0 if successful, or an MBEDTLS_ERR_RSA_XXX error code
+ *
+ * \note           The output buffer must be as large as the size
+ *                 of ctx->N (eg. 128 bytes if RSA-1024 is used) otherwise
+ *                 an error is thrown.
+ */
+int mbedtls_rsa_rsaes_pkcs1_v15_decrypt( mbedtls_rsa_context *ctx,
+                                 int (*f_rng)(void *, unsigned char *, size_t),
+                                 void *p_rng,
+                                 int mode, size_t *olen,
+                                 const unsigned char *input,
+                                 unsigned char *output,
+                                 size_t output_max_len );
+
+/**
+ * \brief          Perform a PKCS#1 v2.1 OAEP decryption (RSAES-OAEP-DECRYPT)
+ *
+ * \param ctx      RSA context
+ * \param f_rng    RNG function (Only needed for MBEDTLS_RSA_PRIVATE)
+ * \param p_rng    RNG parameter
+ * \param mode     MBEDTLS_RSA_PUBLIC or MBEDTLS_RSA_PRIVATE
+ * \param label    buffer holding the custom label to use
+ * \param label_len contains the label length
+ * \param olen     will contain the plaintext length
+ * \param input    buffer holding the encrypted data
+ * \param output   buffer that will hold the plaintext
+ * \param output_max_len    maximum length of the output buffer
+ *
+ * \return         0 if successful, or an MBEDTLS_ERR_RSA_XXX error code
+ *
+ * \note           The output buffer must be as large as the size
+ *                 of ctx->N (eg. 128 bytes if RSA-1024 is used) otherwise
+ *                 an error is thrown.
+ */
+int mbedtls_rsa_rsaes_oaep_decrypt( mbedtls_rsa_context *ctx,
+                            int (*f_rng)(void *, unsigned char *, size_t),
+                            void *p_rng,
+                            int mode,
+                            const unsigned char *label, size_t label_len,
+                            size_t *olen,
+                            const unsigned char *input,
+                            unsigned char *output,
+                            size_t output_max_len );
+
+/**
+ * \brief          Generic wrapper to perform a PKCS#1 signature using the
+ *                 mode from the context. Do a private RSA operation to sign
+ *                 a message digest
+ *
+ * \param ctx      RSA context
+ * \param f_rng    RNG function (Needed for PKCS#1 v2.1 encoding and for
+ *                               MBEDTLS_RSA_PRIVATE)
+ * \param p_rng    RNG parameter
+ * \param mode     MBEDTLS_RSA_PUBLIC or MBEDTLS_RSA_PRIVATE
+ * \param md_alg   a MBEDTLS_MD_XXX (use MBEDTLS_MD_NONE for signing raw data)
+ * \param hashlen  message digest length (for MBEDTLS_MD_NONE only)
+ * \param hash     buffer holding the message digest
+ * \param sig      buffer that will hold the ciphertext
+ *
+ * \return         0 if the signing operation was successful,
+ *                 or an MBEDTLS_ERR_RSA_XXX error code
+ *
+ * \note           The "sig" buffer must be as large as the size
+ *                 of ctx->N (eg. 128 bytes if RSA-1024 is used).
+ *
+ * \note           In case of PKCS#1 v2.1 encoding, see comments on
+ * \note           \c mbedtls_rsa_rsassa_pss_sign() for details on md_alg and hash_id.
+ */
+int mbedtls_rsa_pkcs1_sign( mbedtls_rsa_context *ctx,
+                    int (*f_rng)(void *, unsigned char *, size_t),
+                    void *p_rng,
+                    int mode,
+                    mbedtls_md_type_t md_alg,
+                    unsigned int hashlen,
+                    const unsigned char *hash,
+                    unsigned char *sig );
+
+/**
+ * \brief          Perform a PKCS#1 v1.5 signature (RSASSA-PKCS1-v1_5-SIGN)
+ *
+ * \param ctx      RSA context
+ * \param f_rng    RNG function (Only needed for MBEDTLS_RSA_PRIVATE)
+ * \param p_rng    RNG parameter
+ * \param mode     MBEDTLS_RSA_PUBLIC or MBEDTLS_RSA_PRIVATE
+ * \param md_alg   a MBEDTLS_MD_XXX (use MBEDTLS_MD_NONE for signing raw data)
+ * \param hashlen  message digest length (for MBEDTLS_MD_NONE only)
+ * \param hash     buffer holding the message digest
+ * \param sig      buffer that will hold the ciphertext
+ *
+ * \return         0 if the signing operation was successful,
+ *                 or an MBEDTLS_ERR_RSA_XXX error code
+ *
+ * \note           The "sig" buffer must be as large as the size
+ *                 of ctx->N (eg. 128 bytes if RSA-1024 is used).
+ */
+int mbedtls_rsa_rsassa_pkcs1_v15_sign( mbedtls_rsa_context *ctx,
+                               int (*f_rng)(void *, unsigned char *, size_t),
+                               void *p_rng,
+                               int mode,
+                               mbedtls_md_type_t md_alg,
+                               unsigned int hashlen,
+                               const unsigned char *hash,
+                               unsigned char *sig );
+
+/**
+ * \brief          Perform a PKCS#1 v2.1 PSS signature (RSASSA-PSS-SIGN)
+ *
+ * \param ctx      RSA context
+ * \param f_rng    RNG function (Needed for PKCS#1 v2.1 encoding and for
+ *                               MBEDTLS_RSA_PRIVATE)
+ * \param p_rng    RNG parameter
+ * \param mode     MBEDTLS_RSA_PUBLIC or MBEDTLS_RSA_PRIVATE
+ * \param md_alg   a MBEDTLS_MD_XXX (use MBEDTLS_MD_NONE for signing raw data)
+ * \param hashlen  message digest length (for MBEDTLS_MD_NONE only)
+ * \param hash     buffer holding the message digest
+ * \param sig      buffer that will hold the ciphertext
+ *
+ * \return         0 if the signing operation was successful,
+ *                 or an MBEDTLS_ERR_RSA_XXX error code
+ *
+ * \note           The "sig" buffer must be as large as the size
+ *                 of ctx->N (eg. 128 bytes if RSA-1024 is used).
+ *
+ * \note           The hash_id in the RSA context is the one used for the
+ *                 encoding. md_alg in the function call is the type of hash
+ *                 that is encoded. According to RFC 3447 it is advised to
+ *                 keep both hashes the same.
+ */
+int mbedtls_rsa_rsassa_pss_sign( mbedtls_rsa_context *ctx,
+                         int (*f_rng)(void *, unsigned char *, size_t),
+                         void *p_rng,
+                         int mode,
+                         mbedtls_md_type_t md_alg,
+                         unsigned int hashlen,
+                         const unsigned char *hash,
+                         unsigned char *sig );
+
+/**
+ * \brief          Generic wrapper to perform a PKCS#1 verification using the
+ *                 mode from the context. Do a public RSA operation and check
+ *                 the message digest
+ *
+ * \param ctx      points to an RSA public key
+ * \param f_rng    RNG function (Only needed for MBEDTLS_RSA_PRIVATE)
+ * \param p_rng    RNG parameter
+ * \param mode     MBEDTLS_RSA_PUBLIC or MBEDTLS_RSA_PRIVATE
+ * \param md_alg   a MBEDTLS_MD_XXX (use MBEDTLS_MD_NONE for signing raw data)
+ * \param hashlen  message digest length (for MBEDTLS_MD_NONE only)
+ * \param hash     buffer holding the message digest
+ * \param sig      buffer holding the ciphertext
+ *
+ * \return         0 if the verify operation was successful,
+ *                 or an MBEDTLS_ERR_RSA_XXX error code
+ *
+ * \note           The "sig" buffer must be as large as the size
+ *                 of ctx->N (eg. 128 bytes if RSA-1024 is used).
+ *
+ * \note           In case of PKCS#1 v2.1 encoding, see comments on
+ *                 \c mbedtls_rsa_rsassa_pss_verify() about md_alg and hash_id.
+ */
+int mbedtls_rsa_pkcs1_verify( mbedtls_rsa_context *ctx,
+                      int (*f_rng)(void *, unsigned char *, size_t),
+                      void *p_rng,
+                      int mode,
+                      mbedtls_md_type_t md_alg,
+                      unsigned int hashlen,
+                      const unsigned char *hash,
+                      const unsigned char *sig );
+
+/**
+ * \brief          Perform a PKCS#1 v1.5 verification (RSASSA-PKCS1-v1_5-VERIFY)
+ *
+ * \param ctx      points to an RSA public key
+ * \param f_rng    RNG function (Only needed for MBEDTLS_RSA_PRIVATE)
+ * \param p_rng    RNG parameter
+ * \param mode     MBEDTLS_RSA_PUBLIC or MBEDTLS_RSA_PRIVATE
+ * \param md_alg   a MBEDTLS_MD_XXX (use MBEDTLS_MD_NONE for signing raw data)
+ * \param hashlen  message digest length (for MBEDTLS_MD_NONE only)
+ * \param hash     buffer holding the message digest
+ * \param sig      buffer holding the ciphertext
+ *
+ * \return         0 if the verify operation was successful,
+ *                 or an MBEDTLS_ERR_RSA_XXX error code
+ *
+ * \note           The "sig" buffer must be as large as the size
+ *                 of ctx->N (eg. 128 bytes if RSA-1024 is used).
+ */
+int mbedtls_rsa_rsassa_pkcs1_v15_verify( mbedtls_rsa_context *ctx,
+                                 int (*f_rng)(void *, unsigned char *, size_t),
+                                 void *p_rng,
+                                 int mode,
+                                 mbedtls_md_type_t md_alg,
+                                 unsigned int hashlen,
+                                 const unsigned char *hash,
+                                 const unsigned char *sig );
+
+/**
+ * \brief          Perform a PKCS#1 v2.1 PSS verification (RSASSA-PSS-VERIFY)
+ *                 (This is the "simple" version.)
+ *
+ * \param ctx      points to an RSA public key
+ * \param f_rng    RNG function (Only needed for MBEDTLS_RSA_PRIVATE)
+ * \param p_rng    RNG parameter
+ * \param mode     MBEDTLS_RSA_PUBLIC or MBEDTLS_RSA_PRIVATE
+ * \param md_alg   a MBEDTLS_MD_XXX (use MBEDTLS_MD_NONE for signing raw data)
+ * \param hashlen  message digest length (for MBEDTLS_MD_NONE only)
+ * \param hash     buffer holding the message digest
+ * \param sig      buffer holding the ciphertext
+ *
+ * \return         0 if the verify operation was successful,
+ *                 or an MBEDTLS_ERR_RSA_XXX error code
+ *
+ * \note           The "sig" buffer must be as large as the size
+ *                 of ctx->N (eg. 128 bytes if RSA-1024 is used).
+ *
+ * \note           The hash_id in the RSA context is the one used for the
+ *                 verification. md_alg in the function call is the type of
+ *                 hash that is verified. According to RFC 3447 it is advised to
+ *                 keep both hashes the same. If hash_id in the RSA context is
+ *                 unset, the md_alg from the function call is used.
+ */
+int mbedtls_rsa_rsassa_pss_verify( mbedtls_rsa_context *ctx,
+                           int (*f_rng)(void *, unsigned char *, size_t),
+                           void *p_rng,
+                           int mode,
+                           mbedtls_md_type_t md_alg,
+                           unsigned int hashlen,
+                           const unsigned char *hash,
+                           const unsigned char *sig );
+
+/**
+ * \brief          Perform a PKCS#1 v2.1 PSS verification (RSASSA-PSS-VERIFY)
+ *                 (This is the version with "full" options.)
+ *
+ * \param ctx      points to an RSA public key
+ * \param f_rng    RNG function (Only needed for MBEDTLS_RSA_PRIVATE)
+ * \param p_rng    RNG parameter
+ * \param mode     MBEDTLS_RSA_PUBLIC or MBEDTLS_RSA_PRIVATE
+ * \param md_alg   a MBEDTLS_MD_XXX (use MBEDTLS_MD_NONE for signing raw data)
+ * \param hashlen  message digest length (for MBEDTLS_MD_NONE only)
+ * \param hash     buffer holding the message digest
+ * \param mgf1_hash_id message digest used for mask generation
+ * \param expected_salt_len Length of the salt used in padding, use
+ *                 MBEDTLS_RSA_SALT_LEN_ANY to accept any salt length
+ * \param sig      buffer holding the ciphertext
+ *
+ * \return         0 if the verify operation was successful,
+ *                 or an MBEDTLS_ERR_RSA_XXX error code
+ *
+ * \note           The "sig" buffer must be as large as the size
+ *                 of ctx->N (eg. 128 bytes if RSA-1024 is used).
+ *
+ * \note           The hash_id in the RSA context is ignored.
+ */
+int mbedtls_rsa_rsassa_pss_verify_ext( mbedtls_rsa_context *ctx,
+                               int (*f_rng)(void *, unsigned char *, size_t),
+                               void *p_rng,
+                               int mode,
+                               mbedtls_md_type_t md_alg,
+                               unsigned int hashlen,
+                               const unsigned char *hash,
+                               mbedtls_md_type_t mgf1_hash_id,
+                               int expected_salt_len,
+                               const unsigned char *sig );
+
+/**
+ * \brief          Copy the components of an RSA context
+ *
+ * \param dst      Destination context
+ * \param src      Source context
+ *
+ * \return         0 on success,
+ *                 MBEDTLS_ERR_MPI_ALLOC_FAILED on memory allocation failure
+ */
+int mbedtls_rsa_copy( mbedtls_rsa_context *dst, const mbedtls_rsa_context *src );
+
+/**
+ * \brief          Free the components of an RSA key
+ *
+ * \param ctx      RSA Context to free
+ */
+void mbedtls_rsa_free( mbedtls_rsa_context *ctx );
+
+/**
+ * \brief          Checkup routine
+ *
+ * \return         0 if successful, or 1 if the test failed
+ */
+int mbedtls_rsa_self_test( int verbose );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MBEDTLS_RSA_C */
+
+#endif /* rsa.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/sha1.h b/tools/sdk/include/mbedtls/mbedtls/sha1.h
new file mode 100644
index 00000000..7a67c6c1
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/sha1.h
@@ -0,0 +1,136 @@
+/**
+ * \file sha1.h
+ *
+ * \brief SHA-1 cryptographic hash function
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_SHA1_H
+#define MBEDTLS_SHA1_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#include 
+#include 
+
+#if !defined(MBEDTLS_SHA1_ALT)
+// Regular implementation
+//
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          SHA-1 context structure
+ */
+typedef struct
+{
+    uint32_t total[2];          /*!< number of bytes processed  */
+    uint32_t state[5];          /*!< intermediate digest state  */
+    unsigned char buffer[64];   /*!< data block being processed */
+}
+mbedtls_sha1_context;
+
+/**
+ * \brief          Initialize SHA-1 context
+ *
+ * \param ctx      SHA-1 context to be initialized
+ */
+void mbedtls_sha1_init( mbedtls_sha1_context *ctx );
+
+/**
+ * \brief          Clear SHA-1 context
+ *
+ * \param ctx      SHA-1 context to be cleared
+ */
+void mbedtls_sha1_free( mbedtls_sha1_context *ctx );
+
+/**
+ * \brief          Clone (the state of) a SHA-1 context
+ *
+ * \param dst      The destination context
+ * \param src      The context to be cloned
+ */
+void mbedtls_sha1_clone( mbedtls_sha1_context *dst,
+                         const mbedtls_sha1_context *src );
+
+/**
+ * \brief          SHA-1 context setup
+ *
+ * \param ctx      context to be initialized
+ */
+void mbedtls_sha1_starts( mbedtls_sha1_context *ctx );
+
+/**
+ * \brief          SHA-1 process buffer
+ *
+ * \param ctx      SHA-1 context
+ * \param input    buffer holding the  data
+ * \param ilen     length of the input data
+ */
+void mbedtls_sha1_update( mbedtls_sha1_context *ctx, const unsigned char *input, size_t ilen );
+
+/**
+ * \brief          SHA-1 final digest
+ *
+ * \param ctx      SHA-1 context
+ * \param output   SHA-1 checksum result
+ */
+void mbedtls_sha1_finish( mbedtls_sha1_context *ctx, unsigned char output[20] );
+
+/* Internal use */
+void mbedtls_sha1_process( mbedtls_sha1_context *ctx, const unsigned char data[64] );
+
+#ifdef __cplusplus
+}
+#endif
+
+#else  /* MBEDTLS_SHA1_ALT */
+#include "sha1_alt.h"
+#endif /* MBEDTLS_SHA1_ALT */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          Output = SHA-1( input buffer )
+ *
+ * \param input    buffer holding the  data
+ * \param ilen     length of the input data
+ * \param output   SHA-1 checksum result
+ */
+void mbedtls_sha1( const unsigned char *input, size_t ilen, unsigned char output[20] );
+
+/**
+ * \brief          Checkup routine
+ *
+ * \return         0 if successful, or 1 if the test failed
+ */
+int mbedtls_sha1_self_test( int verbose );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* mbedtls_sha1.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/sha256.h b/tools/sdk/include/mbedtls/mbedtls/sha256.h
new file mode 100644
index 00000000..f8041adf
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/sha256.h
@@ -0,0 +1,141 @@
+/**
+ * \file sha256.h
+ *
+ * \brief SHA-224 and SHA-256 cryptographic hash function
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_SHA256_H
+#define MBEDTLS_SHA256_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#include 
+#include 
+
+#if !defined(MBEDTLS_SHA256_ALT)
+// Regular implementation
+//
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          SHA-256 context structure
+ */
+typedef struct
+{
+    uint32_t total[2];          /*!< number of bytes processed  */
+    uint32_t state[8];          /*!< intermediate digest state  */
+    unsigned char buffer[64];   /*!< data block being processed */
+    int is224;                  /*!< 0 => SHA-256, else SHA-224 */
+}
+mbedtls_sha256_context;
+
+/**
+ * \brief          Initialize SHA-256 context
+ *
+ * \param ctx      SHA-256 context to be initialized
+ */
+void mbedtls_sha256_init( mbedtls_sha256_context *ctx );
+
+/**
+ * \brief          Clear SHA-256 context
+ *
+ * \param ctx      SHA-256 context to be cleared
+ */
+void mbedtls_sha256_free( mbedtls_sha256_context *ctx );
+
+/**
+ * \brief          Clone (the state of) a SHA-256 context
+ *
+ * \param dst      The destination context
+ * \param src      The context to be cloned
+ */
+void mbedtls_sha256_clone( mbedtls_sha256_context *dst,
+                           const mbedtls_sha256_context *src );
+
+/**
+ * \brief          SHA-256 context setup
+ *
+ * \param ctx      context to be initialized
+ * \param is224    0 = use SHA256, 1 = use SHA224
+ */
+void mbedtls_sha256_starts( mbedtls_sha256_context *ctx, int is224 );
+
+/**
+ * \brief          SHA-256 process buffer
+ *
+ * \param ctx      SHA-256 context
+ * \param input    buffer holding the  data
+ * \param ilen     length of the input data
+ */
+void mbedtls_sha256_update( mbedtls_sha256_context *ctx, const unsigned char *input,
+                    size_t ilen );
+
+/**
+ * \brief          SHA-256 final digest
+ *
+ * \param ctx      SHA-256 context
+ * \param output   SHA-224/256 checksum result
+ */
+void mbedtls_sha256_finish( mbedtls_sha256_context *ctx, unsigned char output[32] );
+
+/* Internal use */
+void mbedtls_sha256_process( mbedtls_sha256_context *ctx, const unsigned char data[64] );
+
+#ifdef __cplusplus
+}
+#endif
+
+#else  /* MBEDTLS_SHA256_ALT */
+#include "sha256_alt.h"
+#endif /* MBEDTLS_SHA256_ALT */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          Output = SHA-256( input buffer )
+ *
+ * \param input    buffer holding the  data
+ * \param ilen     length of the input data
+ * \param output   SHA-224/256 checksum result
+ * \param is224    0 = use SHA256, 1 = use SHA224
+ */
+void mbedtls_sha256( const unsigned char *input, size_t ilen,
+           unsigned char output[32], int is224 );
+
+/**
+ * \brief          Checkup routine
+ *
+ * \return         0 if successful, or 1 if the test failed
+ */
+int mbedtls_sha256_self_test( int verbose );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* mbedtls_sha256.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/sha512.h b/tools/sdk/include/mbedtls/mbedtls/sha512.h
new file mode 100644
index 00000000..12f4fab4
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/sha512.h
@@ -0,0 +1,141 @@
+/**
+ * \file sha512.h
+ *
+ * \brief SHA-384 and SHA-512 cryptographic hash function
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_SHA512_H
+#define MBEDTLS_SHA512_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#include 
+#include 
+
+#if !defined(MBEDTLS_SHA512_ALT)
+// Regular implementation
+//
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          SHA-512 context structure
+ */
+typedef struct
+{
+    uint64_t total[2];          /*!< number of bytes processed  */
+    uint64_t state[8];          /*!< intermediate digest state  */
+    unsigned char buffer[128];  /*!< data block being processed */
+    int is384;                  /*!< 0 => SHA-512, else SHA-384 */
+}
+mbedtls_sha512_context;
+
+/**
+ * \brief          Initialize SHA-512 context
+ *
+ * \param ctx      SHA-512 context to be initialized
+ */
+void mbedtls_sha512_init( mbedtls_sha512_context *ctx );
+
+/**
+ * \brief          Clear SHA-512 context
+ *
+ * \param ctx      SHA-512 context to be cleared
+ */
+void mbedtls_sha512_free( mbedtls_sha512_context *ctx );
+
+/**
+ * \brief          Clone (the state of) a SHA-512 context
+ *
+ * \param dst      The destination context
+ * \param src      The context to be cloned
+ */
+void mbedtls_sha512_clone( mbedtls_sha512_context *dst,
+                           const mbedtls_sha512_context *src );
+
+/**
+ * \brief          SHA-512 context setup
+ *
+ * \param ctx      context to be initialized
+ * \param is384    0 = use SHA512, 1 = use SHA384
+ */
+void mbedtls_sha512_starts( mbedtls_sha512_context *ctx, int is384 );
+
+/**
+ * \brief          SHA-512 process buffer
+ *
+ * \param ctx      SHA-512 context
+ * \param input    buffer holding the  data
+ * \param ilen     length of the input data
+ */
+void mbedtls_sha512_update( mbedtls_sha512_context *ctx, const unsigned char *input,
+                    size_t ilen );
+
+/**
+ * \brief          SHA-512 final digest
+ *
+ * \param ctx      SHA-512 context
+ * \param output   SHA-384/512 checksum result
+ */
+void mbedtls_sha512_finish( mbedtls_sha512_context *ctx, unsigned char output[64] );
+
+/* Internal use */
+void mbedtls_sha512_process( mbedtls_sha512_context *ctx, const unsigned char data[128] );
+
+#ifdef __cplusplus
+}
+#endif
+
+#else  /* MBEDTLS_SHA512_ALT */
+#include "sha512_alt.h"
+#endif /* MBEDTLS_SHA512_ALT */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          Output = SHA-512( input buffer )
+ *
+ * \param input    buffer holding the  data
+ * \param ilen     length of the input data
+ * \param output   SHA-384/512 checksum result
+ * \param is384    0 = use SHA512, 1 = use SHA384
+ */
+void mbedtls_sha512( const unsigned char *input, size_t ilen,
+             unsigned char output[64], int is384 );
+
+/**
+ * \brief          Checkup routine
+ *
+ * \return         0 if successful, or 1 if the test failed
+ */
+int mbedtls_sha512_self_test( int verbose );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* mbedtls_sha512.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/ssl.h b/tools/sdk/include/mbedtls/mbedtls/ssl.h
new file mode 100644
index 00000000..82c07607
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/ssl.h
@@ -0,0 +1,2549 @@
+/**
+ * \file ssl.h
+ *
+ * \brief SSL/TLS functions.
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_SSL_H
+#define MBEDTLS_SSL_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#include "bignum.h"
+#include "ecp.h"
+
+#include "ssl_ciphersuites.h"
+
+#if defined(MBEDTLS_X509_CRT_PARSE_C)
+#include "x509_crt.h"
+#include "x509_crl.h"
+#endif
+
+#if defined(MBEDTLS_DHM_C)
+#include "dhm.h"
+#endif
+
+#if defined(MBEDTLS_ECDH_C)
+#include "ecdh.h"
+#endif
+
+#if defined(MBEDTLS_ZLIB_SUPPORT)
+#include "zlib.h"
+#endif
+
+#if defined(MBEDTLS_HAVE_TIME)
+#include 
+#endif
+
+/*
+ * SSL Error codes
+ */
+#define MBEDTLS_ERR_SSL_FEATURE_UNAVAILABLE               -0x7080  /**< The requested feature is not available. */
+#define MBEDTLS_ERR_SSL_BAD_INPUT_DATA                    -0x7100  /**< Bad input parameters to function. */
+#define MBEDTLS_ERR_SSL_INVALID_MAC                       -0x7180  /**< Verification of the message MAC failed. */
+#define MBEDTLS_ERR_SSL_INVALID_RECORD                    -0x7200  /**< An invalid SSL record was received. */
+#define MBEDTLS_ERR_SSL_CONN_EOF                          -0x7280  /**< The connection indicated an EOF. */
+#define MBEDTLS_ERR_SSL_UNKNOWN_CIPHER                    -0x7300  /**< An unknown cipher was received. */
+#define MBEDTLS_ERR_SSL_NO_CIPHER_CHOSEN                  -0x7380  /**< The server has no ciphersuites in common with the client. */
+#define MBEDTLS_ERR_SSL_NO_RNG                            -0x7400  /**< No RNG was provided to the SSL module. */
+#define MBEDTLS_ERR_SSL_NO_CLIENT_CERTIFICATE             -0x7480  /**< No client certification received from the client, but required by the authentication mode. */
+#define MBEDTLS_ERR_SSL_CERTIFICATE_TOO_LARGE             -0x7500  /**< Our own certificate(s) is/are too large to send in an SSL message. */
+#define MBEDTLS_ERR_SSL_CERTIFICATE_REQUIRED              -0x7580  /**< The own certificate is not set, but needed by the server. */
+#define MBEDTLS_ERR_SSL_PRIVATE_KEY_REQUIRED              -0x7600  /**< The own private key or pre-shared key is not set, but needed. */
+#define MBEDTLS_ERR_SSL_CA_CHAIN_REQUIRED                 -0x7680  /**< No CA Chain is set, but required to operate. */
+#define MBEDTLS_ERR_SSL_UNEXPECTED_MESSAGE                -0x7700  /**< An unexpected message was received from our peer. */
+#define MBEDTLS_ERR_SSL_FATAL_ALERT_MESSAGE               -0x7780  /**< A fatal alert message was received from our peer. */
+#define MBEDTLS_ERR_SSL_PEER_VERIFY_FAILED                -0x7800  /**< Verification of our peer failed. */
+#define MBEDTLS_ERR_SSL_PEER_CLOSE_NOTIFY                 -0x7880  /**< The peer notified us that the connection is going to be closed. */
+#define MBEDTLS_ERR_SSL_BAD_HS_CLIENT_HELLO               -0x7900  /**< Processing of the ClientHello handshake message failed. */
+#define MBEDTLS_ERR_SSL_BAD_HS_SERVER_HELLO               -0x7980  /**< Processing of the ServerHello handshake message failed. */
+#define MBEDTLS_ERR_SSL_BAD_HS_CERTIFICATE                -0x7A00  /**< Processing of the Certificate handshake message failed. */
+#define MBEDTLS_ERR_SSL_BAD_HS_CERTIFICATE_REQUEST        -0x7A80  /**< Processing of the CertificateRequest handshake message failed. */
+#define MBEDTLS_ERR_SSL_BAD_HS_SERVER_KEY_EXCHANGE        -0x7B00  /**< Processing of the ServerKeyExchange handshake message failed. */
+#define MBEDTLS_ERR_SSL_BAD_HS_SERVER_HELLO_DONE          -0x7B80  /**< Processing of the ServerHelloDone handshake message failed. */
+#define MBEDTLS_ERR_SSL_BAD_HS_CLIENT_KEY_EXCHANGE        -0x7C00  /**< Processing of the ClientKeyExchange handshake message failed. */
+#define MBEDTLS_ERR_SSL_BAD_HS_CLIENT_KEY_EXCHANGE_RP     -0x7C80  /**< Processing of the ClientKeyExchange handshake message failed in DHM / ECDH Read Public. */
+#define MBEDTLS_ERR_SSL_BAD_HS_CLIENT_KEY_EXCHANGE_CS     -0x7D00  /**< Processing of the ClientKeyExchange handshake message failed in DHM / ECDH Calculate Secret. */
+#define MBEDTLS_ERR_SSL_BAD_HS_CERTIFICATE_VERIFY         -0x7D80  /**< Processing of the CertificateVerify handshake message failed. */
+#define MBEDTLS_ERR_SSL_BAD_HS_CHANGE_CIPHER_SPEC         -0x7E00  /**< Processing of the ChangeCipherSpec handshake message failed. */
+#define MBEDTLS_ERR_SSL_BAD_HS_FINISHED                   -0x7E80  /**< Processing of the Finished handshake message failed. */
+#define MBEDTLS_ERR_SSL_ALLOC_FAILED                      -0x7F00  /**< Memory allocation failed */
+#define MBEDTLS_ERR_SSL_HW_ACCEL_FAILED                   -0x7F80  /**< Hardware acceleration function returned with error */
+#define MBEDTLS_ERR_SSL_HW_ACCEL_FALLTHROUGH              -0x6F80  /**< Hardware acceleration function skipped / left alone data */
+#define MBEDTLS_ERR_SSL_COMPRESSION_FAILED                -0x6F00  /**< Processing of the compression / decompression failed */
+#define MBEDTLS_ERR_SSL_BAD_HS_PROTOCOL_VERSION           -0x6E80  /**< Handshake protocol not within min/max boundaries */
+#define MBEDTLS_ERR_SSL_BAD_HS_NEW_SESSION_TICKET         -0x6E00  /**< Processing of the NewSessionTicket handshake message failed. */
+#define MBEDTLS_ERR_SSL_SESSION_TICKET_EXPIRED            -0x6D80  /**< Session ticket has expired. */
+#define MBEDTLS_ERR_SSL_PK_TYPE_MISMATCH                  -0x6D00  /**< Public key type mismatch (eg, asked for RSA key exchange and presented EC key) */
+#define MBEDTLS_ERR_SSL_UNKNOWN_IDENTITY                  -0x6C80  /**< Unknown identity received (eg, PSK identity) */
+#define MBEDTLS_ERR_SSL_INTERNAL_ERROR                    -0x6C00  /**< Internal error (eg, unexpected failure in lower-level module) */
+#define MBEDTLS_ERR_SSL_COUNTER_WRAPPING                  -0x6B80  /**< A counter would wrap (eg, too many messages exchanged). */
+#define MBEDTLS_ERR_SSL_WAITING_SERVER_HELLO_RENEGO       -0x6B00  /**< Unexpected message at ServerHello in renegotiation. */
+#define MBEDTLS_ERR_SSL_HELLO_VERIFY_REQUIRED             -0x6A80  /**< DTLS client must retry for hello verification */
+#define MBEDTLS_ERR_SSL_BUFFER_TOO_SMALL                  -0x6A00  /**< A buffer is too small to receive or write a message */
+#define MBEDTLS_ERR_SSL_NO_USABLE_CIPHERSUITE             -0x6980  /**< None of the common ciphersuites is usable (eg, no suitable certificate, see debug messages). */
+#define MBEDTLS_ERR_SSL_WANT_READ                         -0x6900  /**< Connection requires a read call. */
+#define MBEDTLS_ERR_SSL_WANT_WRITE                        -0x6880  /**< Connection requires a write call. */
+#define MBEDTLS_ERR_SSL_TIMEOUT                           -0x6800  /**< The operation timed out. */
+#define MBEDTLS_ERR_SSL_CLIENT_RECONNECT                  -0x6780  /**< The client initiated a reconnect from the same port. */
+#define MBEDTLS_ERR_SSL_UNEXPECTED_RECORD                 -0x6700  /**< Record header looks valid but is not expected. */
+
+/*
+ * Various constants
+ */
+#define MBEDTLS_SSL_MAJOR_VERSION_3             3
+#define MBEDTLS_SSL_MINOR_VERSION_0             0   /*!< SSL v3.0 */
+#define MBEDTLS_SSL_MINOR_VERSION_1             1   /*!< TLS v1.0 */
+#define MBEDTLS_SSL_MINOR_VERSION_2             2   /*!< TLS v1.1 */
+#define MBEDTLS_SSL_MINOR_VERSION_3             3   /*!< TLS v1.2 */
+
+#define MBEDTLS_SSL_TRANSPORT_STREAM            0   /*!< TLS      */
+#define MBEDTLS_SSL_TRANSPORT_DATAGRAM          1   /*!< DTLS     */
+
+#define MBEDTLS_SSL_MAX_HOST_NAME_LEN           255 /*!< Maximum host name defined in RFC 1035 */
+
+/* RFC 6066 section 4, see also mfl_code_to_length in ssl_tls.c
+ * NONE must be zero so that memset()ing structure to zero works */
+#define MBEDTLS_SSL_MAX_FRAG_LEN_NONE           0   /*!< don't use this extension   */
+#define MBEDTLS_SSL_MAX_FRAG_LEN_512            1   /*!< MaxFragmentLength 2^9      */
+#define MBEDTLS_SSL_MAX_FRAG_LEN_1024           2   /*!< MaxFragmentLength 2^10     */
+#define MBEDTLS_SSL_MAX_FRAG_LEN_2048           3   /*!< MaxFragmentLength 2^11     */
+#define MBEDTLS_SSL_MAX_FRAG_LEN_4096           4   /*!< MaxFragmentLength 2^12     */
+#define MBEDTLS_SSL_MAX_FRAG_LEN_INVALID        5   /*!< first invalid value        */
+
+#define MBEDTLS_SSL_IS_CLIENT                   0
+#define MBEDTLS_SSL_IS_SERVER                   1
+
+#define MBEDTLS_SSL_IS_NOT_FALLBACK             0
+#define MBEDTLS_SSL_IS_FALLBACK                 1
+
+#define MBEDTLS_SSL_EXTENDED_MS_DISABLED        0
+#define MBEDTLS_SSL_EXTENDED_MS_ENABLED         1
+
+#define MBEDTLS_SSL_ETM_DISABLED                0
+#define MBEDTLS_SSL_ETM_ENABLED                 1
+
+#define MBEDTLS_SSL_COMPRESS_NULL               0
+#define MBEDTLS_SSL_COMPRESS_DEFLATE            1
+
+#define MBEDTLS_SSL_VERIFY_NONE                 0
+#define MBEDTLS_SSL_VERIFY_OPTIONAL             1
+#define MBEDTLS_SSL_VERIFY_REQUIRED             2
+#define MBEDTLS_SSL_VERIFY_UNSET                3 /* Used only for sni_authmode */
+
+#define MBEDTLS_SSL_LEGACY_RENEGOTIATION        0
+#define MBEDTLS_SSL_SECURE_RENEGOTIATION        1
+
+#define MBEDTLS_SSL_RENEGOTIATION_DISABLED      0
+#define MBEDTLS_SSL_RENEGOTIATION_ENABLED       1
+
+#define MBEDTLS_SSL_ANTI_REPLAY_DISABLED        0
+#define MBEDTLS_SSL_ANTI_REPLAY_ENABLED         1
+
+#define MBEDTLS_SSL_RENEGOTIATION_NOT_ENFORCED  -1
+#define MBEDTLS_SSL_RENEGO_MAX_RECORDS_DEFAULT  16
+
+#define MBEDTLS_SSL_LEGACY_NO_RENEGOTIATION     0
+#define MBEDTLS_SSL_LEGACY_ALLOW_RENEGOTIATION  1
+#define MBEDTLS_SSL_LEGACY_BREAK_HANDSHAKE      2
+
+#define MBEDTLS_SSL_TRUNC_HMAC_DISABLED         0
+#define MBEDTLS_SSL_TRUNC_HMAC_ENABLED          1
+#define MBEDTLS_SSL_TRUNCATED_HMAC_LEN          10  /* 80 bits, rfc 6066 section 7 */
+
+#define MBEDTLS_SSL_SESSION_TICKETS_DISABLED     0
+#define MBEDTLS_SSL_SESSION_TICKETS_ENABLED      1
+
+#define MBEDTLS_SSL_CBC_RECORD_SPLITTING_DISABLED    0
+#define MBEDTLS_SSL_CBC_RECORD_SPLITTING_ENABLED     1
+
+#define MBEDTLS_SSL_ARC4_ENABLED                0
+#define MBEDTLS_SSL_ARC4_DISABLED               1
+
+#define MBEDTLS_SSL_PRESET_DEFAULT              0
+#define MBEDTLS_SSL_PRESET_SUITEB               2
+
+/*
+ * Default range for DTLS retransmission timer value, in milliseconds.
+ * RFC 6347 4.2.4.1 says from 1 second to 60 seconds.
+ */
+#define MBEDTLS_SSL_DTLS_TIMEOUT_DFL_MIN    1000
+#define MBEDTLS_SSL_DTLS_TIMEOUT_DFL_MAX   60000
+
+/**
+ * \name SECTION: Module settings
+ *
+ * The configuration options you can set for this module are in this section.
+ * Either change them in config.h or define them on the compiler command line.
+ * \{
+ */
+
+#if !defined(MBEDTLS_SSL_DEFAULT_TICKET_LIFETIME)
+#define MBEDTLS_SSL_DEFAULT_TICKET_LIFETIME     86400 /**< Lifetime of session tickets (if enabled) */
+#endif
+
+/*
+ * Maxium fragment length in bytes,
+ * determines the size of each of the two internal I/O buffers.
+ *
+ * Note: the RFC defines the default size of SSL / TLS messages. If you
+ * change the value here, other clients / servers may not be able to
+ * communicate with you anymore. Only change this value if you control
+ * both sides of the connection and have it reduced at both sides, or
+ * if you're using the Max Fragment Length extension and you know all your
+ * peers are using it too!
+ */
+#if !defined(MBEDTLS_SSL_MAX_CONTENT_LEN)
+#define MBEDTLS_SSL_MAX_CONTENT_LEN         16384   /**< Size of the input / output buffer */
+#endif
+
+/* \} name SECTION: Module settings */
+
+/*
+ * Length of the verify data for secure renegotiation
+ */
+#if defined(MBEDTLS_SSL_PROTO_SSL3)
+#define MBEDTLS_SSL_VERIFY_DATA_MAX_LEN 36
+#else
+#define MBEDTLS_SSL_VERIFY_DATA_MAX_LEN 12
+#endif
+
+/*
+ * Signaling ciphersuite values (SCSV)
+ */
+#define MBEDTLS_SSL_EMPTY_RENEGOTIATION_INFO    0xFF   /**< renegotiation info ext */
+#define MBEDTLS_SSL_FALLBACK_SCSV_VALUE         0x5600 /**< RFC 7507 section 2 */
+
+/*
+ * Supported Signature and Hash algorithms (For TLS 1.2)
+ * RFC 5246 section 7.4.1.4.1
+ */
+#define MBEDTLS_SSL_HASH_NONE                0
+#define MBEDTLS_SSL_HASH_MD5                 1
+#define MBEDTLS_SSL_HASH_SHA1                2
+#define MBEDTLS_SSL_HASH_SHA224              3
+#define MBEDTLS_SSL_HASH_SHA256              4
+#define MBEDTLS_SSL_HASH_SHA384              5
+#define MBEDTLS_SSL_HASH_SHA512              6
+
+#define MBEDTLS_SSL_SIG_ANON                 0
+#define MBEDTLS_SSL_SIG_RSA                  1
+#define MBEDTLS_SSL_SIG_ECDSA                3
+
+/*
+ * Client Certificate Types
+ * RFC 5246 section 7.4.4 plus RFC 4492 section 5.5
+ */
+#define MBEDTLS_SSL_CERT_TYPE_RSA_SIGN       1
+#define MBEDTLS_SSL_CERT_TYPE_ECDSA_SIGN    64
+
+/*
+ * Message, alert and handshake types
+ */
+#define MBEDTLS_SSL_MSG_CHANGE_CIPHER_SPEC     20
+#define MBEDTLS_SSL_MSG_ALERT                  21
+#define MBEDTLS_SSL_MSG_HANDSHAKE              22
+#define MBEDTLS_SSL_MSG_APPLICATION_DATA       23
+
+#define MBEDTLS_SSL_ALERT_LEVEL_WARNING         1
+#define MBEDTLS_SSL_ALERT_LEVEL_FATAL           2
+
+#define MBEDTLS_SSL_ALERT_MSG_CLOSE_NOTIFY           0  /* 0x00 */
+#define MBEDTLS_SSL_ALERT_MSG_UNEXPECTED_MESSAGE    10  /* 0x0A */
+#define MBEDTLS_SSL_ALERT_MSG_BAD_RECORD_MAC        20  /* 0x14 */
+#define MBEDTLS_SSL_ALERT_MSG_DECRYPTION_FAILED     21  /* 0x15 */
+#define MBEDTLS_SSL_ALERT_MSG_RECORD_OVERFLOW       22  /* 0x16 */
+#define MBEDTLS_SSL_ALERT_MSG_DECOMPRESSION_FAILURE 30  /* 0x1E */
+#define MBEDTLS_SSL_ALERT_MSG_HANDSHAKE_FAILURE     40  /* 0x28 */
+#define MBEDTLS_SSL_ALERT_MSG_NO_CERT               41  /* 0x29 */
+#define MBEDTLS_SSL_ALERT_MSG_BAD_CERT              42  /* 0x2A */
+#define MBEDTLS_SSL_ALERT_MSG_UNSUPPORTED_CERT      43  /* 0x2B */
+#define MBEDTLS_SSL_ALERT_MSG_CERT_REVOKED          44  /* 0x2C */
+#define MBEDTLS_SSL_ALERT_MSG_CERT_EXPIRED          45  /* 0x2D */
+#define MBEDTLS_SSL_ALERT_MSG_CERT_UNKNOWN          46  /* 0x2E */
+#define MBEDTLS_SSL_ALERT_MSG_ILLEGAL_PARAMETER     47  /* 0x2F */
+#define MBEDTLS_SSL_ALERT_MSG_UNKNOWN_CA            48  /* 0x30 */
+#define MBEDTLS_SSL_ALERT_MSG_ACCESS_DENIED         49  /* 0x31 */
+#define MBEDTLS_SSL_ALERT_MSG_DECODE_ERROR          50  /* 0x32 */
+#define MBEDTLS_SSL_ALERT_MSG_DECRYPT_ERROR         51  /* 0x33 */
+#define MBEDTLS_SSL_ALERT_MSG_EXPORT_RESTRICTION    60  /* 0x3C */
+#define MBEDTLS_SSL_ALERT_MSG_PROTOCOL_VERSION      70  /* 0x46 */
+#define MBEDTLS_SSL_ALERT_MSG_INSUFFICIENT_SECURITY 71  /* 0x47 */
+#define MBEDTLS_SSL_ALERT_MSG_INTERNAL_ERROR        80  /* 0x50 */
+#define MBEDTLS_SSL_ALERT_MSG_INAPROPRIATE_FALLBACK 86  /* 0x56 */
+#define MBEDTLS_SSL_ALERT_MSG_USER_CANCELED         90  /* 0x5A */
+#define MBEDTLS_SSL_ALERT_MSG_NO_RENEGOTIATION     100  /* 0x64 */
+#define MBEDTLS_SSL_ALERT_MSG_UNSUPPORTED_EXT      110  /* 0x6E */
+#define MBEDTLS_SSL_ALERT_MSG_UNRECOGNIZED_NAME    112  /* 0x70 */
+#define MBEDTLS_SSL_ALERT_MSG_UNKNOWN_PSK_IDENTITY 115  /* 0x73 */
+#define MBEDTLS_SSL_ALERT_MSG_NO_APPLICATION_PROTOCOL 120 /* 0x78 */
+
+#define MBEDTLS_SSL_HS_HELLO_REQUEST            0
+#define MBEDTLS_SSL_HS_CLIENT_HELLO             1
+#define MBEDTLS_SSL_HS_SERVER_HELLO             2
+#define MBEDTLS_SSL_HS_HELLO_VERIFY_REQUEST     3
+#define MBEDTLS_SSL_HS_NEW_SESSION_TICKET       4
+#define MBEDTLS_SSL_HS_CERTIFICATE             11
+#define MBEDTLS_SSL_HS_SERVER_KEY_EXCHANGE     12
+#define MBEDTLS_SSL_HS_CERTIFICATE_REQUEST     13
+#define MBEDTLS_SSL_HS_SERVER_HELLO_DONE       14
+#define MBEDTLS_SSL_HS_CERTIFICATE_VERIFY      15
+#define MBEDTLS_SSL_HS_CLIENT_KEY_EXCHANGE     16
+#define MBEDTLS_SSL_HS_FINISHED                20
+
+/*
+ * TLS extensions
+ */
+#define MBEDTLS_TLS_EXT_SERVERNAME                   0
+#define MBEDTLS_TLS_EXT_SERVERNAME_HOSTNAME          0
+
+#define MBEDTLS_TLS_EXT_MAX_FRAGMENT_LENGTH          1
+
+#define MBEDTLS_TLS_EXT_TRUNCATED_HMAC               4
+
+#define MBEDTLS_TLS_EXT_SUPPORTED_ELLIPTIC_CURVES   10
+#define MBEDTLS_TLS_EXT_SUPPORTED_POINT_FORMATS     11
+
+#define MBEDTLS_TLS_EXT_SIG_ALG                     13
+
+#define MBEDTLS_TLS_EXT_ALPN                        16
+
+#define MBEDTLS_TLS_EXT_ENCRYPT_THEN_MAC            22 /* 0x16 */
+#define MBEDTLS_TLS_EXT_EXTENDED_MASTER_SECRET  0x0017 /* 23 */
+
+#define MBEDTLS_TLS_EXT_SESSION_TICKET              35
+
+#define MBEDTLS_TLS_EXT_ECJPAKE_KKPP               256 /* experimental */
+
+#define MBEDTLS_TLS_EXT_RENEGOTIATION_INFO      0xFF01
+
+/*
+ * Size defines
+ */
+#if !defined(MBEDTLS_PSK_MAX_LEN)
+#define MBEDTLS_PSK_MAX_LEN            32 /* 256 bits */
+#endif
+
+/* Dummy type used only for its size */
+union mbedtls_ssl_premaster_secret
+{
+#if defined(MBEDTLS_KEY_EXCHANGE_RSA_ENABLED)
+    unsigned char _pms_rsa[48];                         /* RFC 5246 8.1.1 */
+#endif
+#if defined(MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED)
+    unsigned char _pms_dhm[MBEDTLS_MPI_MAX_SIZE];      /* RFC 5246 8.1.2 */
+#endif
+#if defined(MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED)    || \
+    defined(MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED)  || \
+    defined(MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED)     || \
+    defined(MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED)
+    unsigned char _pms_ecdh[MBEDTLS_ECP_MAX_BYTES];    /* RFC 4492 5.10 */
+#endif
+#if defined(MBEDTLS_KEY_EXCHANGE_PSK_ENABLED)
+    unsigned char _pms_psk[4 + 2 * MBEDTLS_PSK_MAX_LEN];       /* RFC 4279 2 */
+#endif
+#if defined(MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED)
+    unsigned char _pms_dhe_psk[4 + MBEDTLS_MPI_MAX_SIZE
+                                 + MBEDTLS_PSK_MAX_LEN];       /* RFC 4279 3 */
+#endif
+#if defined(MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED)
+    unsigned char _pms_rsa_psk[52 + MBEDTLS_PSK_MAX_LEN];      /* RFC 4279 4 */
+#endif
+#if defined(MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED)
+    unsigned char _pms_ecdhe_psk[4 + MBEDTLS_ECP_MAX_BYTES
+                                   + MBEDTLS_PSK_MAX_LEN];     /* RFC 5489 2 */
+#endif
+#if defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED)
+    unsigned char _pms_ecjpake[32];     /* Thread spec: SHA-256 output */
+#endif
+};
+
+#define MBEDTLS_PREMASTER_SIZE     sizeof( union mbedtls_ssl_premaster_secret )
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * SSL state machine
+ */
+typedef enum
+{
+    MBEDTLS_SSL_HELLO_REQUEST,
+    MBEDTLS_SSL_CLIENT_HELLO,
+    MBEDTLS_SSL_SERVER_HELLO,
+    MBEDTLS_SSL_SERVER_CERTIFICATE,
+    MBEDTLS_SSL_SERVER_KEY_EXCHANGE,
+    MBEDTLS_SSL_CERTIFICATE_REQUEST,
+    MBEDTLS_SSL_SERVER_HELLO_DONE,
+    MBEDTLS_SSL_CLIENT_CERTIFICATE,
+    MBEDTLS_SSL_CLIENT_KEY_EXCHANGE,
+    MBEDTLS_SSL_CERTIFICATE_VERIFY,
+    MBEDTLS_SSL_CLIENT_CHANGE_CIPHER_SPEC,
+    MBEDTLS_SSL_CLIENT_FINISHED,
+    MBEDTLS_SSL_SERVER_CHANGE_CIPHER_SPEC,
+    MBEDTLS_SSL_SERVER_FINISHED,
+    MBEDTLS_SSL_FLUSH_BUFFERS,
+    MBEDTLS_SSL_HANDSHAKE_WRAPUP,
+    MBEDTLS_SSL_HANDSHAKE_OVER,
+    MBEDTLS_SSL_SERVER_NEW_SESSION_TICKET,
+    MBEDTLS_SSL_SERVER_HELLO_VERIFY_REQUEST_SENT,
+}
+mbedtls_ssl_states;
+
+/**
+ * \brief          Callback type: send data on the network.
+ *
+ * \note           That callback may be either blocking or non-blocking.
+ *
+ * \param ctx      Context for the send callback (typically a file descriptor)
+ * \param buf      Buffer holding the data to send
+ * \param len      Length of the data to send
+ *
+ * \return         The callback must return the number of bytes sent if any,
+ *                 or a non-zero error code.
+ *                 If performing non-blocking I/O, \c MBEDTLS_ERR_SSL_WANT_WRITE
+ *                 must be returned when the operation would block.
+ *
+ * \note           The callback is allowed to send fewer bytes than requested.
+ *                 It must always return the number of bytes actually sent.
+ */
+typedef int mbedtls_ssl_send_t( void *ctx,
+                                const unsigned char *buf,
+                                size_t len );
+
+/**
+ * \brief          Callback type: receive data from the network.
+ *
+ * \note           That callback may be either blocking or non-blocking.
+ *
+ * \param ctx      Context for the receive callback (typically a file
+ *                 descriptor)
+ * \param buf      Buffer to write the received data to
+ * \param len      Length of the receive buffer
+ *
+ * \return         The callback must return the number of bytes received,
+ *                 or a non-zero error code.
+ *                 If performing non-blocking I/O, \c MBEDTLS_ERR_SSL_WANT_READ
+ *                 must be returned when the operation would block.
+ *
+ * \note           The callback may receive fewer bytes than the length of the
+ *                 buffer. It must always return the number of bytes actually
+ *                 received and written to the buffer.
+ */
+typedef int mbedtls_ssl_recv_t( void *ctx,
+                                unsigned char *buf,
+                                size_t len );
+
+/**
+ * \brief          Callback type: receive data from the network, with timeout
+ *
+ * \note           That callback must block until data is received, or the
+ *                 timeout delay expires, or the operation is interrupted by a
+ *                 signal.
+ *
+ * \param ctx      Context for the receive callback (typically a file descriptor)
+ * \param buf      Buffer to write the received data to
+ * \param len      Length of the receive buffer
+ * \param timeout  Maximum nomber of millisecondes to wait for data
+ *                 0 means no timeout (potentially waiting forever)
+ *
+ * \return         The callback must return the number of bytes received,
+ *                 or a non-zero error code:
+ *                 \c MBEDTLS_ERR_SSL_TIMEOUT if the operation timed out,
+ *                 \c MBEDTLS_ERR_SSL_WANT_READ if interrupted by a signal.
+ *
+ * \note           The callback may receive fewer bytes than the length of the
+ *                 buffer. It must always return the number of bytes actually
+ *                 received and written to the buffer.
+ */
+typedef int mbedtls_ssl_recv_timeout_t( void *ctx,
+                                        unsigned char *buf,
+                                        size_t len,
+                                        uint32_t timeout );
+/**
+ * \brief          Callback type: set a pair of timers/delays to watch
+ *
+ * \param ctx      Context pointer
+ * \param int_ms   Intermediate delay in milliseconds
+ * \param fin_ms   Final delay in milliseconds
+ *                 0 cancels the current timer.
+ *
+ * \note           This callback must at least store the necessary information
+ *                 for the associated \c mbedtls_ssl_get_timer_t callback to
+ *                 return correct information.
+ *
+ * \note           If using a event-driven style of programming, an event must
+ *                 be generated when the final delay is passed. The event must
+ *                 cause a call to \c mbedtls_ssl_handshake() with the proper
+ *                 SSL context to be scheduled. Care must be taken to ensure
+ *                 that at most one such call happens at a time.
+ *
+ * \note           Only one timer at a time must be running. Calling this
+ *                 function while a timer is running must cancel it. Cancelled
+ *                 timers must not generate any event.
+ */
+typedef void mbedtls_ssl_set_timer_t( void * ctx,
+                                      uint32_t int_ms,
+                                      uint32_t fin_ms );
+
+/**
+ * \brief          Callback type: get status of timers/delays
+ *
+ * \param ctx      Context pointer
+ *
+ * \return         This callback must return:
+ *                 -1 if cancelled (fin_ms == 0),
+ *                  0 if none of the delays have passed,
+ *                  1 if only the intermediate delay has passed,
+ *                  2 if the final delay has passed.
+ */
+typedef int mbedtls_ssl_get_timer_t( void * ctx );
+
+
+/* Defined below */
+typedef struct mbedtls_ssl_session mbedtls_ssl_session;
+typedef struct mbedtls_ssl_context mbedtls_ssl_context;
+typedef struct mbedtls_ssl_config  mbedtls_ssl_config;
+
+/* Defined in ssl_internal.h */
+typedef struct mbedtls_ssl_transform mbedtls_ssl_transform;
+typedef struct mbedtls_ssl_handshake_params mbedtls_ssl_handshake_params;
+#if defined(MBEDTLS_X509_CRT_PARSE_C)
+typedef struct mbedtls_ssl_key_cert mbedtls_ssl_key_cert;
+#endif
+#if defined(MBEDTLS_SSL_PROTO_DTLS)
+typedef struct mbedtls_ssl_flight_item mbedtls_ssl_flight_item;
+#endif
+
+/*
+ * This structure is used for storing current session data.
+ */
+struct mbedtls_ssl_session
+{
+#if defined(MBEDTLS_HAVE_TIME)
+    mbedtls_time_t start;       /*!< starting time      */
+#endif
+    int ciphersuite;            /*!< chosen ciphersuite */
+    int compression;            /*!< chosen compression */
+    size_t id_len;              /*!< session id length  */
+    unsigned char id[32];       /*!< session identifier */
+    unsigned char master[48];   /*!< the master secret  */
+
+#if defined(MBEDTLS_X509_CRT_PARSE_C)
+    mbedtls_x509_crt *peer_cert;        /*!< peer X.509 cert chain */
+#endif /* MBEDTLS_X509_CRT_PARSE_C */
+    uint32_t verify_result;          /*!<  verification result     */
+
+#if defined(MBEDTLS_SSL_SESSION_TICKETS) && defined(MBEDTLS_SSL_CLI_C)
+    unsigned char *ticket;      /*!< RFC 5077 session ticket */
+    size_t ticket_len;          /*!< session ticket length   */
+    uint32_t ticket_lifetime;   /*!< ticket lifetime hint    */
+#endif /* MBEDTLS_SSL_SESSION_TICKETS && MBEDTLS_SSL_CLI_C */
+
+#if defined(MBEDTLS_SSL_MAX_FRAGMENT_LENGTH)
+    unsigned char mfl_code;     /*!< MaxFragmentLength negotiated by peer */
+#endif /* MBEDTLS_SSL_MAX_FRAGMENT_LENGTH */
+
+#if defined(MBEDTLS_SSL_TRUNCATED_HMAC)
+    int trunc_hmac;             /*!< flag for truncated hmac activation   */
+#endif /* MBEDTLS_SSL_TRUNCATED_HMAC */
+
+#if defined(MBEDTLS_SSL_ENCRYPT_THEN_MAC)
+    int encrypt_then_mac;       /*!< flag for EtM activation                */
+#endif
+};
+
+/**
+ * SSL/TLS configuration to be shared between mbedtls_ssl_context structures.
+ */
+struct mbedtls_ssl_config
+{
+    /* Group items by size (largest first) to minimize padding overhead */
+
+    /*
+     * Pointers
+     */
+
+    const int *ciphersuite_list[4]; /*!< allowed ciphersuites per version   */
+
+    /** Callback for printing debug output                                  */
+    void (*f_dbg)(void *, int, const char *, int, const char *);
+    void *p_dbg;                    /*!< context for the debug function     */
+
+    /** Callback for getting (pseudo-)random numbers                        */
+    int  (*f_rng)(void *, unsigned char *, size_t);
+    void *p_rng;                    /*!< context for the RNG function       */
+
+    /** Callback to retrieve a session from the cache                       */
+    int (*f_get_cache)(void *, mbedtls_ssl_session *);
+    /** Callback to store a session into the cache                          */
+    int (*f_set_cache)(void *, const mbedtls_ssl_session *);
+    void *p_cache;                  /*!< context for cache callbacks        */
+
+#if defined(MBEDTLS_SSL_SERVER_NAME_INDICATION)
+    /** Callback for setting cert according to SNI extension                */
+    int (*f_sni)(void *, mbedtls_ssl_context *, const unsigned char *, size_t);
+    void *p_sni;                    /*!< context for SNI callback           */
+#endif
+
+#if defined(MBEDTLS_X509_CRT_PARSE_C)
+    /** Callback to customize X.509 certificate chain verification          */
+    int (*f_vrfy)(void *, mbedtls_x509_crt *, int, uint32_t *);
+    void *p_vrfy;                   /*!< context for X.509 verify calllback */
+#endif
+
+#if defined(MBEDTLS_KEY_EXCHANGE__SOME__PSK_ENABLED)
+    /** Callback to retrieve PSK key from identity                          */
+    int (*f_psk)(void *, mbedtls_ssl_context *, const unsigned char *, size_t);
+    void *p_psk;                    /*!< context for PSK callback           */
+#endif
+
+#if defined(MBEDTLS_SSL_DTLS_HELLO_VERIFY) && defined(MBEDTLS_SSL_SRV_C)
+    /** Callback to create & write a cookie for ClientHello veirifcation    */
+    int (*f_cookie_write)( void *, unsigned char **, unsigned char *,
+                           const unsigned char *, size_t );
+    /** Callback to verify validity of a ClientHello cookie                 */
+    int (*f_cookie_check)( void *, const unsigned char *, size_t,
+                           const unsigned char *, size_t );
+    void *p_cookie;                 /*!< context for the cookie callbacks   */
+#endif
+
+#if defined(MBEDTLS_SSL_SESSION_TICKETS) && defined(MBEDTLS_SSL_SRV_C)
+    /** Callback to create & write a session ticket                         */
+    int (*f_ticket_write)( void *, const mbedtls_ssl_session *,
+            unsigned char *, const unsigned char *, size_t *, uint32_t * );
+    /** Callback to parse a session ticket into a session structure         */
+    int (*f_ticket_parse)( void *, mbedtls_ssl_session *, unsigned char *, size_t);
+    void *p_ticket;                 /*!< context for the ticket callbacks   */
+#endif /* MBEDTLS_SSL_SESSION_TICKETS && MBEDTLS_SSL_SRV_C */
+
+#if defined(MBEDTLS_SSL_EXPORT_KEYS)
+    /** Callback to export key block and master secret                      */
+    int (*f_export_keys)( void *, const unsigned char *,
+            const unsigned char *, size_t, size_t, size_t );
+    void *p_export_keys;            /*!< context for key export callback    */
+#endif
+
+#if defined(MBEDTLS_X509_CRT_PARSE_C)
+    const mbedtls_x509_crt_profile *cert_profile; /*!< verification profile */
+    mbedtls_ssl_key_cert *key_cert; /*!< own certificate/key pair(s)        */
+    mbedtls_x509_crt *ca_chain;     /*!< trusted CAs                        */
+    mbedtls_x509_crl *ca_crl;       /*!< trusted CAs CRLs                   */
+#endif /* MBEDTLS_X509_CRT_PARSE_C */
+
+#if defined(MBEDTLS_KEY_EXCHANGE__WITH_CERT__ENABLED)
+    const int *sig_hashes;          /*!< allowed signature hashes           */
+#endif
+
+#if defined(MBEDTLS_ECP_C)
+    const mbedtls_ecp_group_id *curve_list; /*!< allowed curves             */
+#endif
+
+#if defined(MBEDTLS_DHM_C)
+    mbedtls_mpi dhm_P;              /*!< prime modulus for DHM              */
+    mbedtls_mpi dhm_G;              /*!< generator for DHM                  */
+#endif
+
+#if defined(MBEDTLS_KEY_EXCHANGE__SOME__PSK_ENABLED)
+    unsigned char *psk;             /*!< pre-shared key                     */
+    size_t         psk_len;         /*!< length of the pre-shared key       */
+    unsigned char *psk_identity;    /*!< identity for PSK negotiation       */
+    size_t         psk_identity_len;/*!< length of identity                 */
+#endif
+
+#if defined(MBEDTLS_SSL_ALPN)
+    const char **alpn_list;         /*!< ordered list of protocols          */
+#endif
+
+    /*
+     * Numerical settings (int then char)
+     */
+
+    uint32_t read_timeout;          /*!< timeout for mbedtls_ssl_read (ms)  */
+
+#if defined(MBEDTLS_SSL_PROTO_DTLS)
+    uint32_t hs_timeout_min;        /*!< initial value of the handshake
+                                         retransmission timeout (ms)        */
+    uint32_t hs_timeout_max;        /*!< maximum value of the handshake
+                                         retransmission timeout (ms)        */
+#endif
+
+#if defined(MBEDTLS_SSL_RENEGOTIATION)
+    int renego_max_records;         /*!< grace period for renegotiation     */
+    unsigned char renego_period[8]; /*!< value of the record counters
+                                         that triggers renegotiation        */
+#endif
+
+#if defined(MBEDTLS_SSL_DTLS_BADMAC_LIMIT)
+    unsigned int badmac_limit;      /*!< limit of records with a bad MAC    */
+#endif
+
+#if defined(MBEDTLS_DHM_C) && defined(MBEDTLS_SSL_CLI_C)
+    unsigned int dhm_min_bitlen;    /*!< min. bit length of the DHM prime   */
+#endif
+
+    unsigned char max_major_ver;    /*!< max. major version used            */
+    unsigned char max_minor_ver;    /*!< max. minor version used            */
+    unsigned char min_major_ver;    /*!< min. major version used            */
+    unsigned char min_minor_ver;    /*!< min. minor version used            */
+
+    /*
+     * Flags (bitfields)
+     */
+
+    unsigned int endpoint : 1;      /*!< 0: client, 1: server               */
+    unsigned int transport : 1;     /*!< stream (TLS) or datagram (DTLS)    */
+    unsigned int authmode : 2;      /*!< MBEDTLS_SSL_VERIFY_XXX             */
+    /* needed even with renego disabled for LEGACY_BREAK_HANDSHAKE          */
+    unsigned int allow_legacy_renegotiation : 2 ; /*!< MBEDTLS_LEGACY_XXX   */
+#if defined(MBEDTLS_ARC4_C)
+    unsigned int arc4_disabled : 1; /*!< blacklist RC4 ciphersuites?        */
+#endif
+#if defined(MBEDTLS_SSL_MAX_FRAGMENT_LENGTH)
+    unsigned int mfl_code : 3;      /*!< desired fragment length            */
+#endif
+#if defined(MBEDTLS_SSL_ENCRYPT_THEN_MAC)
+    unsigned int encrypt_then_mac : 1 ; /*!< negotiate encrypt-then-mac?    */
+#endif
+#if defined(MBEDTLS_SSL_EXTENDED_MASTER_SECRET)
+    unsigned int extended_ms : 1;   /*!< negotiate extended master secret?  */
+#endif
+#if defined(MBEDTLS_SSL_DTLS_ANTI_REPLAY)
+    unsigned int anti_replay : 1;   /*!< detect and prevent replay?         */
+#endif
+#if defined(MBEDTLS_SSL_CBC_RECORD_SPLITTING)
+    unsigned int cbc_record_splitting : 1;  /*!< do cbc record splitting    */
+#endif
+#if defined(MBEDTLS_SSL_RENEGOTIATION)
+    unsigned int disable_renegotiation : 1; /*!< disable renegotiation?     */
+#endif
+#if defined(MBEDTLS_SSL_TRUNCATED_HMAC)
+    unsigned int trunc_hmac : 1;    /*!< negotiate truncated hmac?          */
+#endif
+#if defined(MBEDTLS_SSL_SESSION_TICKETS)
+    unsigned int session_tickets : 1;   /*!< use session tickets?           */
+#endif
+#if defined(MBEDTLS_SSL_FALLBACK_SCSV) && defined(MBEDTLS_SSL_CLI_C)
+    unsigned int fallback : 1;      /*!< is this a fallback?                */
+#endif
+};
+
+
+struct mbedtls_ssl_context
+{
+    const mbedtls_ssl_config *conf; /*!< configuration information          */
+
+    /*
+     * Miscellaneous
+     */
+    int state;                  /*!< SSL handshake: current state     */
+#if defined(MBEDTLS_SSL_RENEGOTIATION)
+    int renego_status;          /*!< Initial, in progress, pending?   */
+    int renego_records_seen;    /*!< Records since renego request, or with DTLS,
+                                  number of retransmissions of request if
+                                  renego_max_records is < 0           */
+#endif
+
+    int major_ver;              /*!< equal to  MBEDTLS_SSL_MAJOR_VERSION_3    */
+    int minor_ver;              /*!< either 0 (SSL3) or 1 (TLS1.0)    */
+
+#if defined(MBEDTLS_SSL_DTLS_BADMAC_LIMIT)
+    unsigned badmac_seen;       /*!< records with a bad MAC received    */
+#endif
+
+    mbedtls_ssl_send_t *f_send; /*!< Callback for network send */
+    mbedtls_ssl_recv_t *f_recv; /*!< Callback for network receive */
+    mbedtls_ssl_recv_timeout_t *f_recv_timeout;
+                                /*!< Callback for network receive with timeout */
+
+    void *p_bio;                /*!< context for I/O operations   */
+
+    /*
+     * Session layer
+     */
+    mbedtls_ssl_session *session_in;            /*!<  current session data (in)   */
+    mbedtls_ssl_session *session_out;           /*!<  current session data (out)  */
+    mbedtls_ssl_session *session;               /*!<  negotiated session data     */
+    mbedtls_ssl_session *session_negotiate;     /*!<  session data in negotiation */
+
+    mbedtls_ssl_handshake_params *handshake;    /*!<  params required only during
+                                              the handshake process        */
+
+    /*
+     * Record layer transformations
+     */
+    mbedtls_ssl_transform *transform_in;        /*!<  current transform params (in)   */
+    mbedtls_ssl_transform *transform_out;       /*!<  current transform params (in)   */
+    mbedtls_ssl_transform *transform;           /*!<  negotiated transform params     */
+    mbedtls_ssl_transform *transform_negotiate; /*!<  transform params in negotiation */
+
+    /*
+     * Timers
+     */
+    void *p_timer;              /*!< context for the timer callbacks */
+
+    mbedtls_ssl_set_timer_t *f_set_timer;       /*!< set timer callback */
+    mbedtls_ssl_get_timer_t *f_get_timer;       /*!< get timer callback */
+
+    /*
+     * Record layer (incoming data)
+     */
+    unsigned char *in_buf;      /*!< input buffer                     */
+    unsigned char *in_ctr;      /*!< 64-bit incoming message counter
+                                     TLS: maintained by us
+                                     DTLS: read from peer             */
+    unsigned char *in_hdr;      /*!< start of record header           */
+    unsigned char *in_len;      /*!< two-bytes message length field   */
+    unsigned char *in_iv;       /*!< ivlen-byte IV                    */
+    unsigned char *in_msg;      /*!< message contents (in_iv+ivlen)   */
+    unsigned char *in_offt;     /*!< read offset in application data  */
+
+    int in_msgtype;             /*!< record header: message type      */
+    size_t in_msglen;           /*!< record header: message length    */
+    size_t in_left;             /*!< amount of data read so far       */
+#if defined(MBEDTLS_SSL_PROTO_DTLS)
+    uint16_t in_epoch;          /*!< DTLS epoch for incoming records  */
+    size_t next_record_offset;  /*!< offset of the next record in datagram
+                                     (equal to in_left if none)       */
+#endif
+#if defined(MBEDTLS_SSL_DTLS_ANTI_REPLAY)
+    uint64_t in_window_top;     /*!< last validated record seq_num    */
+    uint64_t in_window;         /*!< bitmask for replay detection     */
+#endif
+
+    size_t in_hslen;            /*!< current handshake message length,
+                                     including the handshake header   */
+    int nb_zero;                /*!< # of 0-length encrypted messages */
+    int record_read;            /*!< record is already present        */
+
+    /*
+     * Record layer (outgoing data)
+     */
+    unsigned char *out_buf;     /*!< output buffer                    */
+    unsigned char *out_ctr;     /*!< 64-bit outgoing message counter  */
+    unsigned char *out_hdr;     /*!< start of record header           */
+    unsigned char *out_len;     /*!< two-bytes message length field   */
+    unsigned char *out_iv;      /*!< ivlen-byte IV                    */
+    unsigned char *out_msg;     /*!< message contents (out_iv+ivlen)  */
+
+    int out_msgtype;            /*!< record header: message type      */
+    size_t out_msglen;          /*!< record header: message length    */
+    size_t out_left;            /*!< amount of data not yet written   */
+
+#if defined(MBEDTLS_ZLIB_SUPPORT)
+    unsigned char *compress_buf;        /*!<  zlib data buffer        */
+#endif
+#if defined(MBEDTLS_SSL_CBC_RECORD_SPLITTING)
+    signed char split_done;     /*!< current record already splitted? */
+#endif
+
+    /*
+     * PKI layer
+     */
+    int client_auth;                    /*!<  flag for client auth.   */
+
+    /*
+     * User settings
+     */
+#if defined(MBEDTLS_X509_CRT_PARSE_C)
+    char *hostname;             /*!< expected peer CN for verification
+                                     (and SNI if available)                 */
+#endif
+
+#if defined(MBEDTLS_SSL_ALPN)
+    const char *alpn_chosen;    /*!<  negotiated protocol                   */
+#endif
+
+    /*
+     * Information for DTLS hello verify
+     */
+#if defined(MBEDTLS_SSL_DTLS_HELLO_VERIFY) && defined(MBEDTLS_SSL_SRV_C)
+    unsigned char  *cli_id;         /*!<  transport-level ID of the client  */
+    size_t          cli_id_len;     /*!<  length of cli_id                  */
+#endif
+
+    /*
+     * Secure renegotiation
+     */
+    /* needed to know when to send extension on server */
+    int secure_renegotiation;           /*!<  does peer support legacy or
+                                              secure renegotiation           */
+#if defined(MBEDTLS_SSL_RENEGOTIATION)
+    size_t verify_data_len;             /*!<  length of verify data stored   */
+    char own_verify_data[MBEDTLS_SSL_VERIFY_DATA_MAX_LEN]; /*!<  previous handshake verify data */
+    char peer_verify_data[MBEDTLS_SSL_VERIFY_DATA_MAX_LEN]; /*!<  previous handshake verify data */
+#endif
+};
+
+#if defined(MBEDTLS_SSL_HW_RECORD_ACCEL)
+
+#define MBEDTLS_SSL_CHANNEL_OUTBOUND    0
+#define MBEDTLS_SSL_CHANNEL_INBOUND     1
+
+extern int (*mbedtls_ssl_hw_record_init)(mbedtls_ssl_context *ssl,
+                const unsigned char *key_enc, const unsigned char *key_dec,
+                size_t keylen,
+                const unsigned char *iv_enc,  const unsigned char *iv_dec,
+                size_t ivlen,
+                const unsigned char *mac_enc, const unsigned char *mac_dec,
+                size_t maclen);
+extern int (*mbedtls_ssl_hw_record_activate)(mbedtls_ssl_context *ssl, int direction);
+extern int (*mbedtls_ssl_hw_record_reset)(mbedtls_ssl_context *ssl);
+extern int (*mbedtls_ssl_hw_record_write)(mbedtls_ssl_context *ssl);
+extern int (*mbedtls_ssl_hw_record_read)(mbedtls_ssl_context *ssl);
+extern int (*mbedtls_ssl_hw_record_finish)(mbedtls_ssl_context *ssl);
+#endif /* MBEDTLS_SSL_HW_RECORD_ACCEL */
+
+/**
+ * \brief Returns the list of ciphersuites supported by the SSL/TLS module.
+ *
+ * \return              a statically allocated array of ciphersuites, the last
+ *                      entry is 0.
+ */
+const int *mbedtls_ssl_list_ciphersuites( void );
+
+/**
+ * \brief               Return the name of the ciphersuite associated with the
+ *                      given ID
+ *
+ * \param ciphersuite_id SSL ciphersuite ID
+ *
+ * \return              a string containing the ciphersuite name
+ */
+const char *mbedtls_ssl_get_ciphersuite_name( const int ciphersuite_id );
+
+/**
+ * \brief               Return the ID of the ciphersuite associated with the
+ *                      given name
+ *
+ * \param ciphersuite_name SSL ciphersuite name
+ *
+ * \return              the ID with the ciphersuite or 0 if not found
+ */
+int mbedtls_ssl_get_ciphersuite_id( const char *ciphersuite_name );
+
+/**
+ * \brief          Initialize an SSL context
+ *                 Just makes the context ready for mbedtls_ssl_setup() or
+ *                 mbedtls_ssl_free()
+ *
+ * \param ssl      SSL context
+ */
+void mbedtls_ssl_init( mbedtls_ssl_context *ssl );
+
+/**
+ * \brief          Set up an SSL context for use
+ *
+ * \note           No copy of the configuration context is made, it can be
+ *                 shared by many mbedtls_ssl_context structures.
+ *
+ * \warning        Modifying the conf structure after it has been used in this
+ *                 function is unsupported!
+ *
+ * \param ssl      SSL context
+ * \param conf     SSL configuration to use
+ *
+ * \return         0 if successful, or MBEDTLS_ERR_SSL_ALLOC_FAILED if
+ *                 memory allocation failed
+ */
+int mbedtls_ssl_setup( mbedtls_ssl_context *ssl,
+                       const mbedtls_ssl_config *conf );
+
+/**
+ * \brief          Reset an already initialized SSL context for re-use
+ *                 while retaining application-set variables, function
+ *                 pointers and data.
+ *
+ * \param ssl      SSL context
+ * \return         0 if successful, or MBEDTLS_ERR_SSL_ALLOC_FAILED,
+                   MBEDTLS_ERR_SSL_HW_ACCEL_FAILED or
+ *                 MBEDTLS_ERR_SSL_COMPRESSION_FAILED
+ */
+int mbedtls_ssl_session_reset( mbedtls_ssl_context *ssl );
+
+/**
+ * \brief          Set the current endpoint type
+ *
+ * \param conf     SSL configuration
+ * \param endpoint must be MBEDTLS_SSL_IS_CLIENT or MBEDTLS_SSL_IS_SERVER
+ */
+void mbedtls_ssl_conf_endpoint( mbedtls_ssl_config *conf, int endpoint );
+
+/**
+ * \brief           Set the transport type (TLS or DTLS).
+ *                  Default: TLS
+ *
+ * \note            For DTLS, you must either provide a recv callback that
+ *                  doesn't block, or one that handles timeouts, see
+ *                  \c mbedtls_ssl_set_bio(). You also need to provide timer
+ *                  callbacks with \c mbedtls_ssl_set_timer_cb().
+ *
+ * \param conf      SSL configuration
+ * \param transport transport type:
+ *                  MBEDTLS_SSL_TRANSPORT_STREAM for TLS,
+ *                  MBEDTLS_SSL_TRANSPORT_DATAGRAM for DTLS.
+ */
+void mbedtls_ssl_conf_transport( mbedtls_ssl_config *conf, int transport );
+
+/**
+ * \brief          Set the certificate verification mode
+ *                 Default: NONE on server, REQUIRED on client
+ *
+ * \param conf     SSL configuration
+ * \param authmode can be:
+ *
+ *  MBEDTLS_SSL_VERIFY_NONE:      peer certificate is not checked
+ *                        (default on server)
+ *                        (insecure on client)
+ *
+ *  MBEDTLS_SSL_VERIFY_OPTIONAL:  peer certificate is checked, however the
+ *                        handshake continues even if verification failed;
+ *                        mbedtls_ssl_get_verify_result() can be called after the
+ *                        handshake is complete.
+ *
+ *  MBEDTLS_SSL_VERIFY_REQUIRED:  peer *must* present a valid certificate,
+ *                        handshake is aborted if verification failed.
+ *                        (default on client)
+ *
+ * \note On client, MBEDTLS_SSL_VERIFY_REQUIRED is the recommended mode.
+ * With MBEDTLS_SSL_VERIFY_OPTIONAL, the user needs to call mbedtls_ssl_get_verify_result() at
+ * the right time(s), which may not be obvious, while REQUIRED always perform
+ * the verification as soon as possible. For example, REQUIRED was protecting
+ * against the "triple handshake" attack even before it was found.
+ */
+void mbedtls_ssl_conf_authmode( mbedtls_ssl_config *conf, int authmode );
+
+#if defined(MBEDTLS_X509_CRT_PARSE_C)
+/**
+ * \brief          Set the verification callback (Optional).
+ *
+ *                 If set, the verify callback is called for each
+ *                 certificate in the chain. For implementation
+ *                 information, please see \c x509parse_verify()
+ *
+ * \param conf     SSL configuration
+ * \param f_vrfy   verification function
+ * \param p_vrfy   verification parameter
+ */
+void mbedtls_ssl_conf_verify( mbedtls_ssl_config *conf,
+                     int (*f_vrfy)(void *, mbedtls_x509_crt *, int, uint32_t *),
+                     void *p_vrfy );
+#endif /* MBEDTLS_X509_CRT_PARSE_C */
+
+/**
+ * \brief          Set the random number generator callback
+ *
+ * \param conf     SSL configuration
+ * \param f_rng    RNG function
+ * \param p_rng    RNG parameter
+ */
+void mbedtls_ssl_conf_rng( mbedtls_ssl_config *conf,
+                  int (*f_rng)(void *, unsigned char *, size_t),
+                  void *p_rng );
+
+/**
+ * \brief          Set the debug callback
+ *
+ *                 The callback has the following argument:
+ *                 void *           opaque context for the callback
+ *                 int              debug level
+ *                 const char *     file name
+ *                 int              line number
+ *                 const char *     message
+ *
+ * \param conf     SSL configuration
+ * \param f_dbg    debug function
+ * \param p_dbg    debug parameter
+ */
+void mbedtls_ssl_conf_dbg( mbedtls_ssl_config *conf,
+                  void (*f_dbg)(void *, int, const char *, int, const char *),
+                  void  *p_dbg );
+
+/**
+ * \brief          Set the underlying BIO callbacks for write, read and
+ *                 read-with-timeout.
+ *
+ * \param ssl      SSL context
+ * \param p_bio    parameter (context) shared by BIO callbacks
+ * \param f_send   write callback
+ * \param f_recv   read callback
+ * \param f_recv_timeout blocking read callback with timeout.
+ *
+ * \note           One of f_recv or f_recv_timeout can be NULL, in which case
+ *                 the other is used. If both are non-NULL, f_recv_timeout is
+ *                 used and f_recv is ignored (as if it were NULL).
+ *
+ * \note           The two most common use cases are:
+ *                 - non-blocking I/O, f_recv != NULL, f_recv_timeout == NULL
+ *                 - blocking I/O, f_recv == NULL, f_recv_timout != NULL
+ *
+ * \note           For DTLS, you need to provide either a non-NULL
+ *                 f_recv_timeout callback, or a f_recv that doesn't block.
+ *
+ * \note           See the documentations of \c mbedtls_ssl_sent_t,
+ *                 \c mbedtls_ssl_recv_t and \c mbedtls_ssl_recv_timeout_t for
+ *                 the conventions those callbacks must follow.
+ *
+ * \note           On some platforms, net.c provides \c mbedtls_net_send(),
+ *                 \c mbedtls_net_recv() and \c mbedtls_net_recv_timeout()
+ *                 that are suitable to be used here.
+ */
+void mbedtls_ssl_set_bio( mbedtls_ssl_context *ssl,
+                          void *p_bio,
+                          mbedtls_ssl_send_t *f_send,
+                          mbedtls_ssl_recv_t *f_recv,
+                          mbedtls_ssl_recv_timeout_t *f_recv_timeout );
+
+/**
+ * \brief          Set the timeout period for mbedtls_ssl_read()
+ *                 (Default: no timeout.)
+ *
+ * \param conf     SSL configuration context
+ * \param timeout  Timeout value in milliseconds.
+ *                 Use 0 for no timeout (default).
+ *
+ * \note           With blocking I/O, this will only work if a non-NULL
+ *                 \c f_recv_timeout was set with \c mbedtls_ssl_set_bio().
+ *                 With non-blocking I/O, this will only work if timer
+ *                 callbacks were set with \c mbedtls_ssl_set_timer_cb().
+ *
+ * \note           With non-blocking I/O, you may also skip this function
+ *                 altogether and handle timeouts at the application layer.
+ */
+void mbedtls_ssl_conf_read_timeout( mbedtls_ssl_config *conf, uint32_t timeout );
+
+/**
+ * \brief          Set the timer callbacks (Mandatory for DTLS.)
+ *
+ * \param ssl      SSL context
+ * \param p_timer  parameter (context) shared by timer callbacks
+ * \param f_set_timer   set timer callback
+ * \param f_get_timer   get timer callback. Must return:
+ *
+ * \note           See the documentation of \c mbedtls_ssl_set_timer_t and
+ *                 \c mbedtls_ssl_get_timer_t for the conventions this pair of
+ *                 callbacks must fallow.
+ *
+ * \note           On some platforms, timing.c provides
+ *                 \c mbedtls_timing_set_delay() and
+ *                 \c mbedtls_timing_get_delay() that are suitable for using
+ *                 here, except if using an event-driven style.
+ *
+ * \note           See also the "DTLS tutorial" article in our knowledge base.
+ *                 https://tls.mbed.org/kb/how-to/dtls-tutorial
+ */
+void mbedtls_ssl_set_timer_cb( mbedtls_ssl_context *ssl,
+                               void *p_timer,
+                               mbedtls_ssl_set_timer_t *f_set_timer,
+                               mbedtls_ssl_get_timer_t *f_get_timer );
+
+/**
+ * \brief           Callback type: generate and write session ticket
+ *
+ * \note            This describes what a callback implementation should do.
+ *                  This callback should generate an encrypted and
+ *                  authenticated ticket for the session and write it to the
+ *                  output buffer. Here, ticket means the opaque ticket part
+ *                  of the NewSessionTicket structure of RFC 5077.
+ *
+ * \param p_ticket  Context for the callback
+ * \param session   SSL session to be written in the ticket
+ * \param start     Start of the output buffer
+ * \param end       End of the output buffer
+ * \param tlen      On exit, holds the length written
+ * \param lifetime  On exit, holds the lifetime of the ticket in seconds
+ *
+ * \return          0 if successful, or
+ *                  a specific MBEDTLS_ERR_XXX code.
+ */
+typedef int mbedtls_ssl_ticket_write_t( void *p_ticket,
+                                        const mbedtls_ssl_session *session,
+                                        unsigned char *start,
+                                        const unsigned char *end,
+                                        size_t *tlen,
+                                        uint32_t *lifetime );
+
+#if defined(MBEDTLS_SSL_EXPORT_KEYS)
+/**
+ * \brief           Callback type: Export key block and master secret
+ *
+ * \note            This is required for certain uses of TLS, e.g. EAP-TLS
+ *                  (RFC 5216) and Thread. The key pointers are ephemeral and
+ *                  therefore must not be stored. The master secret and keys
+ *                  should not be used directly except as an input to a key
+ *                  derivation function.
+ *
+ * \param p_expkey  Context for the callback
+ * \param ms        Pointer to master secret (fixed length: 48 bytes)
+ * \param kb        Pointer to key block, see RFC 5246 section 6.3
+ *                  (variable length: 2 * maclen + 2 * keylen + 2 * ivlen).
+ * \param maclen    MAC length
+ * \param keylen    Key length
+ * \param ivlen     IV length
+ *
+ * \return          0 if successful, or
+ *                  a specific MBEDTLS_ERR_XXX code.
+ */
+typedef int mbedtls_ssl_export_keys_t( void *p_expkey,
+                                const unsigned char *ms,
+                                const unsigned char *kb,
+                                size_t maclen,
+                                size_t keylen,
+                                size_t ivlen );
+#endif /* MBEDTLS_SSL_EXPORT_KEYS */
+
+/**
+ * \brief           Callback type: parse and load session ticket
+ *
+ * \note            This describes what a callback implementation should do.
+ *                  This callback should parse a session ticket as generated
+ *                  by the corresponding mbedtls_ssl_ticket_write_t function,
+ *                  and, if the ticket is authentic and valid, load the
+ *                  session.
+ *
+ * \note            The implementation is allowed to modify the first len
+ *                  bytes of the input buffer, eg to use it as a temporary
+ *                  area for the decrypted ticket contents.
+ *
+ * \param p_ticket  Context for the callback
+ * \param session   SSL session to be loaded
+ * \param buf       Start of the buffer containing the ticket
+ * \param len       Length of the ticket.
+ *
+ * \return          0 if successful, or
+ *                  MBEDTLS_ERR_SSL_INVALID_MAC if not authentic, or
+ *                  MBEDTLS_ERR_SSL_SESSION_TICKET_EXPIRED if expired, or
+ *                  any other non-zero code for other failures.
+ */
+typedef int mbedtls_ssl_ticket_parse_t( void *p_ticket,
+                                        mbedtls_ssl_session *session,
+                                        unsigned char *buf,
+                                        size_t len );
+
+#if defined(MBEDTLS_SSL_SESSION_TICKETS) && defined(MBEDTLS_SSL_SRV_C)
+/**
+ * \brief           Configure SSL session ticket callbacks (server only).
+ *                  (Default: none.)
+ *
+ * \note            On server, session tickets are enabled by providing
+ *                  non-NULL callbacks.
+ *
+ * \note            On client, use \c mbedtls_ssl_conf_session_tickets().
+ *
+ * \param conf      SSL configuration context
+ * \param f_ticket_write    Callback for writing a ticket
+ * \param f_ticket_parse    Callback for parsing a ticket
+ * \param p_ticket          Context shared by the two callbacks
+ */
+void mbedtls_ssl_conf_session_tickets_cb( mbedtls_ssl_config *conf,
+        mbedtls_ssl_ticket_write_t *f_ticket_write,
+        mbedtls_ssl_ticket_parse_t *f_ticket_parse,
+        void *p_ticket );
+#endif /* MBEDTLS_SSL_SESSION_TICKETS && MBEDTLS_SSL_SRV_C */
+
+#if defined(MBEDTLS_SSL_EXPORT_KEYS)
+/**
+ * \brief           Configure key export callback.
+ *                  (Default: none.)
+ *
+ * \note            See \c mbedtls_ssl_export_keys_t.
+ *
+ * \param conf      SSL configuration context
+ * \param f_export_keys     Callback for exporting keys
+ * \param p_export_keys     Context for the callback
+ */
+void mbedtls_ssl_conf_export_keys_cb( mbedtls_ssl_config *conf,
+        mbedtls_ssl_export_keys_t *f_export_keys,
+        void *p_export_keys );
+#endif /* MBEDTLS_SSL_EXPORT_KEYS */
+
+/**
+ * \brief          Callback type: generate a cookie
+ *
+ * \param ctx      Context for the callback
+ * \param p        Buffer to write to,
+ *                 must be updated to point right after the cookie
+ * \param end      Pointer to one past the end of the output buffer
+ * \param info     Client ID info that was passed to
+ *                 \c mbedtls_ssl_set_client_transport_id()
+ * \param ilen     Length of info in bytes
+ *
+ * \return         The callback must return 0 on success,
+ *                 or a negative error code.
+ */
+typedef int mbedtls_ssl_cookie_write_t( void *ctx,
+                                unsigned char **p, unsigned char *end,
+                                const unsigned char *info, size_t ilen );
+
+/**
+ * \brief          Callback type: verify a cookie
+ *
+ * \param ctx      Context for the callback
+ * \param cookie   Cookie to verify
+ * \param clen     Length of cookie
+ * \param info     Client ID info that was passed to
+ *                 \c mbedtls_ssl_set_client_transport_id()
+ * \param ilen     Length of info in bytes
+ *
+ * \return         The callback must return 0 if cookie is valid,
+ *                 or a negative error code.
+ */
+typedef int mbedtls_ssl_cookie_check_t( void *ctx,
+                                const unsigned char *cookie, size_t clen,
+                                const unsigned char *info, size_t ilen );
+
+#if defined(MBEDTLS_SSL_DTLS_HELLO_VERIFY) && defined(MBEDTLS_SSL_SRV_C)
+/**
+ * \brief           Register callbacks for DTLS cookies
+ *                  (Server only. DTLS only.)
+ *
+ *                  Default: dummy callbacks that fail, in order to force you to
+ *                  register working callbacks (and initialize their context).
+ *
+ *                  To disable HelloVerifyRequest, register NULL callbacks.
+ *
+ * \warning         Disabling hello verification allows your server to be used
+ *                  for amplification in DoS attacks against other hosts.
+ *                  Only disable if you known this can't happen in your
+ *                  particular environment.
+ *
+ * \note            See comments on \c mbedtls_ssl_handshake() about handling
+ *                  the MBEDTLS_ERR_SSL_HELLO_VERIFY_REQUIRED that is expected
+ *                  on the first handshake attempt when this is enabled.
+ *
+ * \note            This is also necessary to handle client reconnection from
+ *                  the same port as described in RFC 6347 section 4.2.8 (only
+ *                  the variant with cookies is supported currently). See
+ *                  comments on \c mbedtls_ssl_read() for details.
+ *
+ * \param conf              SSL configuration
+ * \param f_cookie_write    Cookie write callback
+ * \param f_cookie_check    Cookie check callback
+ * \param p_cookie          Context for both callbacks
+ */
+void mbedtls_ssl_conf_dtls_cookies( mbedtls_ssl_config *conf,
+                           mbedtls_ssl_cookie_write_t *f_cookie_write,
+                           mbedtls_ssl_cookie_check_t *f_cookie_check,
+                           void *p_cookie );
+
+/**
+ * \brief          Set client's transport-level identification info.
+ *                 (Server only. DTLS only.)
+ *
+ *                 This is usually the IP address (and port), but could be
+ *                 anything identify the client depending on the underlying
+ *                 network stack. Used for HelloVerifyRequest with DTLS.
+ *                 This is *not* used to route the actual packets.
+ *
+ * \param ssl      SSL context
+ * \param info     Transport-level info identifying the client (eg IP + port)
+ * \param ilen     Length of info in bytes
+ *
+ * \note           An internal copy is made, so the info buffer can be reused.
+ *
+ * \return         0 on success,
+ *                 MBEDTLS_ERR_SSL_BAD_INPUT_DATA if used on client,
+ *                 MBEDTLS_ERR_SSL_ALLOC_FAILED if out of memory.
+ */
+int mbedtls_ssl_set_client_transport_id( mbedtls_ssl_context *ssl,
+                                 const unsigned char *info,
+                                 size_t ilen );
+
+#endif /* MBEDTLS_SSL_DTLS_HELLO_VERIFY && MBEDTLS_SSL_SRV_C */
+
+#if defined(MBEDTLS_SSL_DTLS_ANTI_REPLAY)
+/**
+ * \brief          Enable or disable anti-replay protection for DTLS.
+ *                 (DTLS only, no effect on TLS.)
+ *                 Default: enabled.
+ *
+ * \param conf     SSL configuration
+ * \param mode     MBEDTLS_SSL_ANTI_REPLAY_ENABLED or MBEDTLS_SSL_ANTI_REPLAY_DISABLED.
+ *
+ * \warning        Disabling this is a security risk unless the application
+ *                 protocol handles duplicated packets in a safe way. You
+ *                 should not disable this without careful consideration.
+ *                 However, if your application already detects duplicated
+ *                 packets and needs information about them to adjust its
+ *                 transmission strategy, then you'll want to disable this.
+ */
+void mbedtls_ssl_conf_dtls_anti_replay( mbedtls_ssl_config *conf, char mode );
+#endif /* MBEDTLS_SSL_DTLS_ANTI_REPLAY */
+
+#if defined(MBEDTLS_SSL_DTLS_BADMAC_LIMIT)
+/**
+ * \brief          Set a limit on the number of records with a bad MAC
+ *                 before terminating the connection.
+ *                 (DTLS only, no effect on TLS.)
+ *                 Default: 0 (disabled).
+ *
+ * \param conf     SSL configuration
+ * \param limit    Limit, or 0 to disable.
+ *
+ * \note           If the limit is N, then the connection is terminated when
+ *                 the Nth non-authentic record is seen.
+ *
+ * \note           Records with an invalid header are not counted, only the
+ *                 ones going through the authentication-decryption phase.
+ *
+ * \note           This is a security trade-off related to the fact that it's
+ *                 often relatively easy for an active attacker ot inject UDP
+ *                 datagrams. On one hand, setting a low limit here makes it
+ *                 easier for such an attacker to forcibly terminated a
+ *                 connection. On the other hand, a high limit or no limit
+ *                 might make us waste resources checking authentication on
+ *                 many bogus packets.
+ */
+void mbedtls_ssl_conf_dtls_badmac_limit( mbedtls_ssl_config *conf, unsigned limit );
+#endif /* MBEDTLS_SSL_DTLS_BADMAC_LIMIT */
+
+#if defined(MBEDTLS_SSL_PROTO_DTLS)
+/**
+ * \brief          Set retransmit timeout values for the DTLS handshake.
+ *                 (DTLS only, no effect on TLS.)
+ *
+ * \param conf     SSL configuration
+ * \param min      Initial timeout value in milliseconds.
+ *                 Default: 1000 (1 second).
+ * \param max      Maximum timeout value in milliseconds.
+ *                 Default: 60000 (60 seconds).
+ *
+ * \note           Default values are from RFC 6347 section 4.2.4.1.
+ *
+ * \note           The 'min' value should typically be slightly above the
+ *                 expected round-trip time to your peer, plus whatever time
+ *                 it takes for the peer to process the message. For example,
+ *                 if your RTT is about 600ms and you peer needs up to 1s to
+ *                 do the cryptographic operations in the handshake, then you
+ *                 should set 'min' slightly above 1600. Lower values of 'min'
+ *                 might cause spurious resends which waste network resources,
+ *                 while larger value of 'min' will increase overall latency
+ *                 on unreliable network links.
+ *
+ * \note           The more unreliable your network connection is, the larger
+ *                 your max / min ratio needs to be in order to achieve
+ *                 reliable handshakes.
+ *
+ * \note           Messages are retransmitted up to log2(ceil(max/min)) times.
+ *                 For example, if min = 1s and max = 5s, the retransmit plan
+ *                 goes: send ... 1s -> resend ... 2s -> resend ... 4s ->
+ *                 resend ... 5s -> give up and return a timeout error.
+ */
+void mbedtls_ssl_conf_handshake_timeout( mbedtls_ssl_config *conf, uint32_t min, uint32_t max );
+#endif /* MBEDTLS_SSL_PROTO_DTLS */
+
+#if defined(MBEDTLS_SSL_SRV_C)
+/**
+ * \brief          Set the session cache callbacks (server-side only)
+ *                 If not set, no session resuming is done (except if session
+ *                 tickets are enabled too).
+ *
+ *                 The session cache has the responsibility to check for stale
+ *                 entries based on timeout. See RFC 5246 for recommendations.
+ *
+ *                 Warning: session.peer_cert is cleared by the SSL/TLS layer on
+ *                 connection shutdown, so do not cache the pointer! Either set
+ *                 it to NULL or make a full copy of the certificate.
+ *
+ *                 The get callback is called once during the initial handshake
+ *                 to enable session resuming. The get function has the
+ *                 following parameters: (void *parameter, mbedtls_ssl_session *session)
+ *                 If a valid entry is found, it should fill the master of
+ *                 the session object with the cached values and return 0,
+ *                 return 1 otherwise. Optionally peer_cert can be set as well
+ *                 if it is properly present in cache entry.
+ *
+ *                 The set callback is called once during the initial handshake
+ *                 to enable session resuming after the entire handshake has
+ *                 been finished. The set function has the following parameters:
+ *                 (void *parameter, const mbedtls_ssl_session *session). The function
+ *                 should create a cache entry for future retrieval based on
+ *                 the data in the session structure and should keep in mind
+ *                 that the mbedtls_ssl_session object presented (and all its referenced
+ *                 data) is cleared by the SSL/TLS layer when the connection is
+ *                 terminated. It is recommended to add metadata to determine if
+ *                 an entry is still valid in the future. Return 0 if
+ *                 successfully cached, return 1 otherwise.
+ *
+ * \param conf           SSL configuration
+ * \param p_cache        parmater (context) for both callbacks
+ * \param f_get_cache    session get callback
+ * \param f_set_cache    session set callback
+ */
+void mbedtls_ssl_conf_session_cache( mbedtls_ssl_config *conf,
+        void *p_cache,
+        int (*f_get_cache)(void *, mbedtls_ssl_session *),
+        int (*f_set_cache)(void *, const mbedtls_ssl_session *) );
+#endif /* MBEDTLS_SSL_SRV_C */
+
+#if defined(MBEDTLS_SSL_CLI_C)
+/**
+ * \brief          Request resumption of session (client-side only)
+ *                 Session data is copied from presented session structure.
+ *
+ * \param ssl      SSL context
+ * \param session  session context
+ *
+ * \return         0 if successful,
+ *                 MBEDTLS_ERR_SSL_ALLOC_FAILED if memory allocation failed,
+ *                 MBEDTLS_ERR_SSL_BAD_INPUT_DATA if used server-side or
+ *                 arguments are otherwise invalid
+ *
+ * \sa             mbedtls_ssl_get_session()
+ */
+int mbedtls_ssl_set_session( mbedtls_ssl_context *ssl, const mbedtls_ssl_session *session );
+#endif /* MBEDTLS_SSL_CLI_C */
+
+/**
+ * \brief               Set the list of allowed ciphersuites and the preference
+ *                      order. First in the list has the highest preference.
+ *                      (Overrides all version-specific lists)
+ *
+ *                      The ciphersuites array is not copied, and must remain
+ *                      valid for the lifetime of the ssl_config.
+ *
+ *                      Note: The server uses its own preferences
+ *                      over the preference of the client unless
+ *                      MBEDTLS_SSL_SRV_RESPECT_CLIENT_PREFERENCE is defined!
+ *
+ * \param conf          SSL configuration
+ * \param ciphersuites  0-terminated list of allowed ciphersuites
+ */
+void mbedtls_ssl_conf_ciphersuites( mbedtls_ssl_config *conf,
+                                   const int *ciphersuites );
+
+/**
+ * \brief               Set the list of allowed ciphersuites and the
+ *                      preference order for a specific version of the protocol.
+ *                      (Only useful on the server side)
+ *
+ *                      The ciphersuites array is not copied, and must remain
+ *                      valid for the lifetime of the ssl_config.
+ *
+ * \param conf          SSL configuration
+ * \param ciphersuites  0-terminated list of allowed ciphersuites
+ * \param major         Major version number (only MBEDTLS_SSL_MAJOR_VERSION_3
+ *                      supported)
+ * \param minor         Minor version number (MBEDTLS_SSL_MINOR_VERSION_0,
+ *                      MBEDTLS_SSL_MINOR_VERSION_1 and MBEDTLS_SSL_MINOR_VERSION_2,
+ *                      MBEDTLS_SSL_MINOR_VERSION_3 supported)
+ *
+ * \note                With DTLS, use MBEDTLS_SSL_MINOR_VERSION_2 for DTLS 1.0
+ *                      and MBEDTLS_SSL_MINOR_VERSION_3 for DTLS 1.2
+ */
+void mbedtls_ssl_conf_ciphersuites_for_version( mbedtls_ssl_config *conf,
+                                       const int *ciphersuites,
+                                       int major, int minor );
+
+#if defined(MBEDTLS_X509_CRT_PARSE_C)
+/**
+ * \brief          Set the X.509 security profile used for verification
+ *
+ * \note           The restrictions are enforced for all certificates in the
+ *                 chain. However, signatures in the handshake are not covered
+ *                 by this setting but by \b mbedtls_ssl_conf_sig_hashes().
+ *
+ * \param conf     SSL configuration
+ * \param profile  Profile to use
+ */
+void mbedtls_ssl_conf_cert_profile( mbedtls_ssl_config *conf,
+                                    const mbedtls_x509_crt_profile *profile );
+
+/**
+ * \brief          Set the data required to verify peer certificate
+ *
+ * \param conf     SSL configuration
+ * \param ca_chain trusted CA chain (meaning all fully trusted top-level CAs)
+ * \param ca_crl   trusted CA CRLs
+ */
+void mbedtls_ssl_conf_ca_chain( mbedtls_ssl_config *conf,
+                               mbedtls_x509_crt *ca_chain,
+                               mbedtls_x509_crl *ca_crl );
+
+/**
+ * \brief          Set own certificate chain and private key
+ *
+ * \note           own_cert should contain in order from the bottom up your
+ *                 certificate chain. The top certificate (self-signed)
+ *                 can be omitted.
+ *
+ * \note           On server, this function can be called multiple times to
+ *                 provision more than one cert/key pair (eg one ECDSA, one
+ *                 RSA with SHA-256, one RSA with SHA-1). An adequate
+ *                 certificate will be selected according to the client's
+ *                 advertised capabilities. In case mutliple certificates are
+ *                 adequate, preference is given to the one set by the first
+ *                 call to this function, then second, etc.
+ *
+ * \note           On client, only the first call has any effect. That is,
+ *                 only one client certificate can be provisioned. The
+ *                 server's preferences in its CertficateRequest message will
+ *                 be ignored and our only cert will be sent regardless of
+ *                 whether it matches those preferences - the server can then
+ *                 decide what it wants to do with it.
+ *
+ * \param conf     SSL configuration
+ * \param own_cert own public certificate chain
+ * \param pk_key   own private key
+ *
+ * \return         0 on success or MBEDTLS_ERR_SSL_ALLOC_FAILED
+ */
+int mbedtls_ssl_conf_own_cert( mbedtls_ssl_config *conf,
+                              mbedtls_x509_crt *own_cert,
+                              mbedtls_pk_context *pk_key );
+#endif /* MBEDTLS_X509_CRT_PARSE_C */
+
+#if defined(MBEDTLS_KEY_EXCHANGE__SOME__PSK_ENABLED)
+/**
+ * \brief          Set the Pre Shared Key (PSK) and the expected identity name
+ *
+ * \note           This is mainly useful for clients. Servers will usually
+ *                 want to use \c mbedtls_ssl_conf_psk_cb() instead.
+ *
+ * \note           Currently clients can only register one pre-shared key.
+ *                 In other words, the servers' identity hint is ignored.
+ *                 Support for setting multiple PSKs on clients and selecting
+ *                 one based on the identity hint is not a planned feature but
+ *                 feedback is welcomed.
+ *
+ * \param conf     SSL configuration
+ * \param psk      pointer to the pre-shared key
+ * \param psk_len  pre-shared key length
+ * \param psk_identity      pointer to the pre-shared key identity
+ * \param psk_identity_len  identity key length
+ *
+ * \return         0 if successful or MBEDTLS_ERR_SSL_ALLOC_FAILED
+ */
+int mbedtls_ssl_conf_psk( mbedtls_ssl_config *conf,
+                const unsigned char *psk, size_t psk_len,
+                const unsigned char *psk_identity, size_t psk_identity_len );
+
+
+/**
+ * \brief          Set the Pre Shared Key (PSK) for the current handshake
+ *
+ * \note           This should only be called inside the PSK callback,
+ *                 ie the function passed to \c mbedtls_ssl_conf_psk_cb().
+ *
+ * \param ssl      SSL context
+ * \param psk      pointer to the pre-shared key
+ * \param psk_len  pre-shared key length
+ *
+ * \return         0 if successful or MBEDTLS_ERR_SSL_ALLOC_FAILED
+ */
+int mbedtls_ssl_set_hs_psk( mbedtls_ssl_context *ssl,
+                            const unsigned char *psk, size_t psk_len );
+
+/**
+ * \brief          Set the PSK callback (server-side only).
+ *
+ *                 If set, the PSK callback is called for each
+ *                 handshake where a PSK ciphersuite was negotiated.
+ *                 The caller provides the identity received and wants to
+ *                 receive the actual PSK data and length.
+ *
+ *                 The callback has the following parameters: (void *parameter,
+ *                 mbedtls_ssl_context *ssl, const unsigned char *psk_identity,
+ *                 size_t identity_len)
+ *                 If a valid PSK identity is found, the callback should use
+ *                 \c mbedtls_ssl_set_hs_psk() on the ssl context to set the
+ *                 correct PSK and return 0.
+ *                 Any other return value will result in a denied PSK identity.
+ *
+ * \note           If you set a PSK callback using this function, then you
+ *                 don't need to set a PSK key and identity using
+ *                 \c mbedtls_ssl_conf_psk().
+ *
+ * \param conf     SSL configuration
+ * \param f_psk    PSK identity function
+ * \param p_psk    PSK identity parameter
+ */
+void mbedtls_ssl_conf_psk_cb( mbedtls_ssl_config *conf,
+                     int (*f_psk)(void *, mbedtls_ssl_context *, const unsigned char *,
+                                  size_t),
+                     void *p_psk );
+#endif /* MBEDTLS_KEY_EXCHANGE__SOME__PSK_ENABLED */
+
+#if defined(MBEDTLS_DHM_C) && defined(MBEDTLS_SSL_SRV_C)
+/**
+ * \brief          Set the Diffie-Hellman public P and G values,
+ *                 read as hexadecimal strings (server-side only)
+ *                 (Default: MBEDTLS_DHM_RFC5114_MODP_2048_[PG])
+ *
+ * \param conf     SSL configuration
+ * \param dhm_P    Diffie-Hellman-Merkle modulus
+ * \param dhm_G    Diffie-Hellman-Merkle generator
+ *
+ * \return         0 if successful
+ */
+int mbedtls_ssl_conf_dh_param( mbedtls_ssl_config *conf, const char *dhm_P, const char *dhm_G );
+
+/**
+ * \brief          Set the Diffie-Hellman public P and G values,
+ *                 read from existing context (server-side only)
+ *
+ * \param conf     SSL configuration
+ * \param dhm_ctx  Diffie-Hellman-Merkle context
+ *
+ * \return         0 if successful
+ */
+int mbedtls_ssl_conf_dh_param_ctx( mbedtls_ssl_config *conf, mbedtls_dhm_context *dhm_ctx );
+#endif /* MBEDTLS_DHM_C && defined(MBEDTLS_SSL_SRV_C) */
+
+#if defined(MBEDTLS_DHM_C) && defined(MBEDTLS_SSL_CLI_C)
+/**
+ * \brief          Set the minimum length for Diffie-Hellman parameters.
+ *                 (Client-side only.)
+ *                 (Default: 1024 bits.)
+ *
+ * \param conf     SSL configuration
+ * \param bitlen   Minimum bit length of the DHM prime
+ */
+void mbedtls_ssl_conf_dhm_min_bitlen( mbedtls_ssl_config *conf,
+                                      unsigned int bitlen );
+#endif /* MBEDTLS_DHM_C && MBEDTLS_SSL_CLI_C */
+
+#if defined(MBEDTLS_ECP_C)
+/**
+ * \brief          Set the allowed curves in order of preference.
+ *                 (Default: all defined curves.)
+ *
+ *                 On server: this only affects selection of the ECDHE curve;
+ *                 the curves used for ECDH and ECDSA are determined by the
+ *                 list of available certificates instead.
+ *
+ *                 On client: this affects the list of curves offered for any
+ *                 use. The server can override our preference order.
+ *
+ *                 Both sides: limits the set of curves accepted for use in
+ *                 ECDHE and in the peer's end-entity certificate.
+ *
+ * \note           This has no influence on which curves are allowed inside the
+ *                 certificate chains, see \c mbedtls_ssl_conf_cert_profile()
+ *                 for that. For the end-entity certificate however, the key
+ *                 will be accepted only if it is allowed both by this list
+ *                 and by the cert profile.
+ *
+ * \note           This list should be ordered by decreasing preference
+ *                 (preferred curve first).
+ *
+ * \param conf     SSL configuration
+ * \param curves   Ordered list of allowed curves,
+ *                 terminated by MBEDTLS_ECP_DP_NONE.
+ */
+void mbedtls_ssl_conf_curves( mbedtls_ssl_config *conf,
+                              const mbedtls_ecp_group_id *curves );
+#endif /* MBEDTLS_ECP_C */
+
+#if defined(MBEDTLS_KEY_EXCHANGE__WITH_CERT__ENABLED)
+/**
+ * \brief          Set the allowed hashes for signatures during the handshake.
+ *                 (Default: all available hashes except MD5.)
+ *
+ * \note           This only affects which hashes are offered and can be used
+ *                 for signatures during the handshake. Hashes for message
+ *                 authentication and the TLS PRF are controlled by the
+ *                 ciphersuite, see \c mbedtls_ssl_conf_ciphersuites(). Hashes
+ *                 used for certificate signature are controlled by the
+ *                 verification profile, see \c mbedtls_ssl_conf_cert_profile().
+ *
+ * \note           This list should be ordered by decreasing preference
+ *                 (preferred hash first).
+ *
+ * \param conf     SSL configuration
+ * \param hashes   Ordered list of allowed signature hashes,
+ *                 terminated by \c MBEDTLS_MD_NONE.
+ */
+void mbedtls_ssl_conf_sig_hashes( mbedtls_ssl_config *conf,
+                                  const int *hashes );
+#endif /* MBEDTLS_KEY_EXCHANGE__WITH_CERT__ENABLED */
+
+#if defined(MBEDTLS_X509_CRT_PARSE_C)
+/**
+ * \brief          Set the hostname to check against the received server
+ *                 certificate. It sets the ServerName TLS extension too,
+ *                 if the extension is enabled.
+ *                 (client-side only)
+ *
+ * \param ssl      SSL context
+ * \param hostname the server hostname
+ *
+ * \return         0 if successful or MBEDTLS_ERR_SSL_ALLOC_FAILED
+ */
+int mbedtls_ssl_set_hostname( mbedtls_ssl_context *ssl, const char *hostname );
+#endif /* MBEDTLS_X509_CRT_PARSE_C */
+
+#if defined(MBEDTLS_SSL_SERVER_NAME_INDICATION)
+/**
+ * \brief          Set own certificate and key for the current handshake
+ *
+ * \note           Same as \c mbedtls_ssl_conf_own_cert() but for use within
+ *                 the SNI callback.
+ *
+ * \param ssl      SSL context
+ * \param own_cert own public certificate chain
+ * \param pk_key   own private key
+ *
+ * \return         0 on success or MBEDTLS_ERR_SSL_ALLOC_FAILED
+ */
+int mbedtls_ssl_set_hs_own_cert( mbedtls_ssl_context *ssl,
+                                 mbedtls_x509_crt *own_cert,
+                                 mbedtls_pk_context *pk_key );
+
+/**
+ * \brief          Set the data required to verify peer certificate for the
+ *                 current handshake
+ *
+ * \note           Same as \c mbedtls_ssl_conf_ca_chain() but for use within
+ *                 the SNI callback.
+ *
+ * \param ssl      SSL context
+ * \param ca_chain trusted CA chain (meaning all fully trusted top-level CAs)
+ * \param ca_crl   trusted CA CRLs
+ */
+void mbedtls_ssl_set_hs_ca_chain( mbedtls_ssl_context *ssl,
+                                  mbedtls_x509_crt *ca_chain,
+                                  mbedtls_x509_crl *ca_crl );
+
+/**
+ * \brief          Set authmode for the current handshake.
+ *
+ * \note           Same as \c mbedtls_ssl_conf_authmode() but for use within
+ *                 the SNI callback.
+ *
+ * \param ssl      SSL context
+ * \param authmode MBEDTLS_SSL_VERIFY_NONE, MBEDTLS_SSL_VERIFY_OPTIONAL or
+ *                 MBEDTLS_SSL_VERIFY_REQUIRED
+ */
+void mbedtls_ssl_set_hs_authmode( mbedtls_ssl_context *ssl,
+                                  int authmode );
+
+/**
+ * \brief          Set server side ServerName TLS extension callback
+ *                 (optional, server-side only).
+ *
+ *                 If set, the ServerName callback is called whenever the
+ *                 server receives a ServerName TLS extension from the client
+ *                 during a handshake. The ServerName callback has the
+ *                 following parameters: (void *parameter, mbedtls_ssl_context *ssl,
+ *                 const unsigned char *hostname, size_t len). If a suitable
+ *                 certificate is found, the callback must set the
+ *                 certificate(s) and key(s) to use with \c
+ *                 mbedtls_ssl_set_hs_own_cert() (can be called repeatedly),
+ *                 and may optionally adjust the CA and associated CRL with \c
+ *                 mbedtls_ssl_set_hs_ca_chain() as well as the client
+ *                 authentication mode with \c mbedtls_ssl_set_hs_authmode(),
+ *                 then must return 0. If no matching name is found, the
+ *                 callback must either set a default cert, or
+ *                 return non-zero to abort the handshake at this point.
+ *
+ * \param conf     SSL configuration
+ * \param f_sni    verification function
+ * \param p_sni    verification parameter
+ */
+void mbedtls_ssl_conf_sni( mbedtls_ssl_config *conf,
+                  int (*f_sni)(void *, mbedtls_ssl_context *, const unsigned char *,
+                               size_t),
+                  void *p_sni );
+#endif /* MBEDTLS_SSL_SERVER_NAME_INDICATION */
+
+#if defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED)
+/**
+ * \brief          Set the EC J-PAKE password for current handshake.
+ *
+ * \note           An internal copy is made, and destroyed as soon as the
+ *                 handshake is completed, or when the SSL context is reset or
+ *                 freed.
+ *
+ * \note           The SSL context needs to be already set up. The right place
+ *                 to call this function is between \c mbedtls_ssl_setup() or
+ *                 \c mbedtls_ssl_reset() and \c mbedtls_ssl_handshake().
+ *
+ * \param ssl      SSL context
+ * \param pw       EC J-PAKE password (pre-shared secret)
+ * \param pw_len   length of pw in bytes
+ *
+ * \return         0 on success, or a negative error code.
+ */
+int mbedtls_ssl_set_hs_ecjpake_password( mbedtls_ssl_context *ssl,
+                                         const unsigned char *pw,
+                                         size_t pw_len );
+#endif /*MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED */
+
+#if defined(MBEDTLS_SSL_ALPN)
+/**
+ * \brief          Set the supported Application Layer Protocols.
+ *
+ * \param conf     SSL configuration
+ * \param protos   Pointer to a NULL-terminated list of supported protocols,
+ *                 in decreasing preference order. The pointer to the list is
+ *                 recorded by the library for later reference as required, so
+ *                 the lifetime of the table must be atleast as long as the
+ *                 lifetime of the SSL configuration structure.
+ *
+ * \return         0 on success, or MBEDTLS_ERR_SSL_BAD_INPUT_DATA.
+ */
+int mbedtls_ssl_conf_alpn_protocols( mbedtls_ssl_config *conf, const char **protos );
+
+/**
+ * \brief          Get the name of the negotiated Application Layer Protocol.
+ *                 This function should be called after the handshake is
+ *                 completed.
+ *
+ * \param ssl      SSL context
+ *
+ * \return         Protcol name, or NULL if no protocol was negotiated.
+ */
+const char *mbedtls_ssl_get_alpn_protocol( const mbedtls_ssl_context *ssl );
+#endif /* MBEDTLS_SSL_ALPN */
+
+/**
+ * \brief          Set the maximum supported version sent from the client side
+ *                 and/or accepted at the server side
+ *                 (Default: MBEDTLS_SSL_MAX_MAJOR_VERSION, MBEDTLS_SSL_MAX_MINOR_VERSION)
+ *
+ * \note           This ignores ciphersuites from higher versions.
+ *
+ * \note           With DTLS, use MBEDTLS_SSL_MINOR_VERSION_2 for DTLS 1.0 and
+ *                 MBEDTLS_SSL_MINOR_VERSION_3 for DTLS 1.2
+ *
+ * \param conf     SSL configuration
+ * \param major    Major version number (only MBEDTLS_SSL_MAJOR_VERSION_3 supported)
+ * \param minor    Minor version number (MBEDTLS_SSL_MINOR_VERSION_0,
+ *                 MBEDTLS_SSL_MINOR_VERSION_1 and MBEDTLS_SSL_MINOR_VERSION_2,
+ *                 MBEDTLS_SSL_MINOR_VERSION_3 supported)
+ */
+void mbedtls_ssl_conf_max_version( mbedtls_ssl_config *conf, int major, int minor );
+
+/**
+ * \brief          Set the minimum accepted SSL/TLS protocol version
+ *                 (Default: TLS 1.0)
+ *
+ * \note           Input outside of the SSL_MAX_XXXXX_VERSION and
+ *                 SSL_MIN_XXXXX_VERSION range is ignored.
+ *
+ * \note           MBEDTLS_SSL_MINOR_VERSION_0 (SSL v3) should be avoided.
+ *
+ * \note           With DTLS, use MBEDTLS_SSL_MINOR_VERSION_2 for DTLS 1.0 and
+ *                 MBEDTLS_SSL_MINOR_VERSION_3 for DTLS 1.2
+ *
+ * \param conf     SSL configuration
+ * \param major    Major version number (only MBEDTLS_SSL_MAJOR_VERSION_3 supported)
+ * \param minor    Minor version number (MBEDTLS_SSL_MINOR_VERSION_0,
+ *                 MBEDTLS_SSL_MINOR_VERSION_1 and MBEDTLS_SSL_MINOR_VERSION_2,
+ *                 MBEDTLS_SSL_MINOR_VERSION_3 supported)
+ */
+void mbedtls_ssl_conf_min_version( mbedtls_ssl_config *conf, int major, int minor );
+
+#if defined(MBEDTLS_SSL_FALLBACK_SCSV) && defined(MBEDTLS_SSL_CLI_C)
+/**
+ * \brief          Set the fallback flag (client-side only).
+ *                 (Default: MBEDTLS_SSL_IS_NOT_FALLBACK).
+ *
+ * \note           Set to MBEDTLS_SSL_IS_FALLBACK when preparing a fallback
+ *                 connection, that is a connection with max_version set to a
+ *                 lower value than the value you're willing to use. Such
+ *                 fallback connections are not recommended but are sometimes
+ *                 necessary to interoperate with buggy (version-intolerant)
+ *                 servers.
+ *
+ * \warning        You should NOT set this to MBEDTLS_SSL_IS_FALLBACK for
+ *                 non-fallback connections! This would appear to work for a
+ *                 while, then cause failures when the server is upgraded to
+ *                 support a newer TLS version.
+ *
+ * \param conf     SSL configuration
+ * \param fallback MBEDTLS_SSL_IS_NOT_FALLBACK or MBEDTLS_SSL_IS_FALLBACK
+ */
+void mbedtls_ssl_conf_fallback( mbedtls_ssl_config *conf, char fallback );
+#endif /* MBEDTLS_SSL_FALLBACK_SCSV && MBEDTLS_SSL_CLI_C */
+
+#if defined(MBEDTLS_SSL_ENCRYPT_THEN_MAC)
+/**
+ * \brief           Enable or disable Encrypt-then-MAC
+ *                  (Default: MBEDTLS_SSL_ETM_ENABLED)
+ *
+ * \note            This should always be enabled, it is a security
+ *                  improvement, and should not cause any interoperability
+ *                  issue (used only if the peer supports it too).
+ *
+ * \param conf      SSL configuration
+ * \param etm       MBEDTLS_SSL_ETM_ENABLED or MBEDTLS_SSL_ETM_DISABLED
+ */
+void mbedtls_ssl_conf_encrypt_then_mac( mbedtls_ssl_config *conf, char etm );
+#endif /* MBEDTLS_SSL_ENCRYPT_THEN_MAC */
+
+#if defined(MBEDTLS_SSL_EXTENDED_MASTER_SECRET)
+/**
+ * \brief           Enable or disable Extended Master Secret negotiation.
+ *                  (Default: MBEDTLS_SSL_EXTENDED_MS_ENABLED)
+ *
+ * \note            This should always be enabled, it is a security fix to the
+ *                  protocol, and should not cause any interoperability issue
+ *                  (used only if the peer supports it too).
+ *
+ * \param conf      SSL configuration
+ * \param ems       MBEDTLS_SSL_EXTENDED_MS_ENABLED or MBEDTLS_SSL_EXTENDED_MS_DISABLED
+ */
+void mbedtls_ssl_conf_extended_master_secret( mbedtls_ssl_config *conf, char ems );
+#endif /* MBEDTLS_SSL_EXTENDED_MASTER_SECRET */
+
+#if defined(MBEDTLS_ARC4_C)
+/**
+ * \brief          Disable or enable support for RC4
+ *                 (Default: MBEDTLS_SSL_ARC4_DISABLED)
+ *
+ * \warning        Use of RC4 in DTLS/TLS has been prohibited by RFC 7465
+ *                 for security reasons. Use at your own risk.
+ *
+ * \note           This function is deprecated and will likely be removed in
+ *                 a future version of the library.
+ *                 RC4 is disabled by default at compile time and needs to be
+ *                 actively enabled for use with legacy systems.
+ *
+ * \param conf     SSL configuration
+ * \param arc4     MBEDTLS_SSL_ARC4_ENABLED or MBEDTLS_SSL_ARC4_DISABLED
+ */
+void mbedtls_ssl_conf_arc4_support( mbedtls_ssl_config *conf, char arc4 );
+#endif /* MBEDTLS_ARC4_C */
+
+#if defined(MBEDTLS_SSL_MAX_FRAGMENT_LENGTH)
+/**
+ * \brief          Set the maximum fragment length to emit and/or negotiate
+ *                 (Default: MBEDTLS_SSL_MAX_CONTENT_LEN, usually 2^14 bytes)
+ *                 (Server: set maximum fragment length to emit,
+ *                 usually negotiated by the client during handshake
+ *                 (Client: set maximum fragment length to emit *and*
+ *                 negotiate with the server during handshake)
+ *
+ * \param conf     SSL configuration
+ * \param mfl_code Code for maximum fragment length (allowed values:
+ *                 MBEDTLS_SSL_MAX_FRAG_LEN_512,  MBEDTLS_SSL_MAX_FRAG_LEN_1024,
+ *                 MBEDTLS_SSL_MAX_FRAG_LEN_2048, MBEDTLS_SSL_MAX_FRAG_LEN_4096)
+ *
+ * \return         0 if successful or MBEDTLS_ERR_SSL_BAD_INPUT_DATA
+ */
+int mbedtls_ssl_conf_max_frag_len( mbedtls_ssl_config *conf, unsigned char mfl_code );
+#endif /* MBEDTLS_SSL_MAX_FRAGMENT_LENGTH */
+
+#if defined(MBEDTLS_SSL_TRUNCATED_HMAC)
+/**
+ * \brief          Activate negotiation of truncated HMAC
+ *                 (Default: MBEDTLS_SSL_TRUNC_HMAC_DISABLED)
+ *
+ * \param conf     SSL configuration
+ * \param truncate Enable or disable (MBEDTLS_SSL_TRUNC_HMAC_ENABLED or
+ *                                    MBEDTLS_SSL_TRUNC_HMAC_DISABLED)
+ */
+void mbedtls_ssl_conf_truncated_hmac( mbedtls_ssl_config *conf, int truncate );
+#endif /* MBEDTLS_SSL_TRUNCATED_HMAC */
+
+#if defined(MBEDTLS_SSL_CBC_RECORD_SPLITTING)
+/**
+ * \brief          Enable / Disable 1/n-1 record splitting
+ *                 (Default: MBEDTLS_SSL_CBC_RECORD_SPLITTING_ENABLED)
+ *
+ * \note           Only affects SSLv3 and TLS 1.0, not higher versions.
+ *                 Does not affect non-CBC ciphersuites in any version.
+ *
+ * \param conf     SSL configuration
+ * \param split    MBEDTLS_SSL_CBC_RECORD_SPLITTING_ENABLED or
+ *                 MBEDTLS_SSL_CBC_RECORD_SPLITTING_DISABLED
+ */
+void mbedtls_ssl_conf_cbc_record_splitting( mbedtls_ssl_config *conf, char split );
+#endif /* MBEDTLS_SSL_CBC_RECORD_SPLITTING */
+
+#if defined(MBEDTLS_SSL_SESSION_TICKETS) && defined(MBEDTLS_SSL_CLI_C)
+/**
+ * \brief          Enable / Disable session tickets (client only).
+ *                 (Default: MBEDTLS_SSL_SESSION_TICKETS_ENABLED.)
+ *
+ * \note           On server, use \c mbedtls_ssl_conf_session_tickets_cb().
+ *
+ * \param conf     SSL configuration
+ * \param use_tickets   Enable or disable (MBEDTLS_SSL_SESSION_TICKETS_ENABLED or
+ *                                         MBEDTLS_SSL_SESSION_TICKETS_DISABLED)
+ */
+void mbedtls_ssl_conf_session_tickets( mbedtls_ssl_config *conf, int use_tickets );
+#endif /* MBEDTLS_SSL_SESSION_TICKETS && MBEDTLS_SSL_CLI_C */
+
+#if defined(MBEDTLS_SSL_RENEGOTIATION)
+/**
+ * \brief          Enable / Disable renegotiation support for connection when
+ *                 initiated by peer
+ *                 (Default: MBEDTLS_SSL_RENEGOTIATION_DISABLED)
+ *
+ * \warning        It is recommended to always disable renegotation unless you
+ *                 know you need it and you know what you're doing. In the
+ *                 past, there have been several issues associated with
+ *                 renegotiation or a poor understanding of its properties.
+ *
+ * \note           Server-side, enabling renegotiation also makes the server
+ *                 susceptible to a resource DoS by a malicious client.
+ *
+ * \param conf    SSL configuration
+ * \param renegotiation     Enable or disable (MBEDTLS_SSL_RENEGOTIATION_ENABLED or
+ *                                             MBEDTLS_SSL_RENEGOTIATION_DISABLED)
+ */
+void mbedtls_ssl_conf_renegotiation( mbedtls_ssl_config *conf, int renegotiation );
+#endif /* MBEDTLS_SSL_RENEGOTIATION */
+
+/**
+ * \brief          Prevent or allow legacy renegotiation.
+ *                 (Default: MBEDTLS_SSL_LEGACY_NO_RENEGOTIATION)
+ *
+ *                 MBEDTLS_SSL_LEGACY_NO_RENEGOTIATION allows connections to
+ *                 be established even if the peer does not support
+ *                 secure renegotiation, but does not allow renegotiation
+ *                 to take place if not secure.
+ *                 (Interoperable and secure option)
+ *
+ *                 MBEDTLS_SSL_LEGACY_ALLOW_RENEGOTIATION allows renegotiations
+ *                 with non-upgraded peers. Allowing legacy renegotiation
+ *                 makes the connection vulnerable to specific man in the
+ *                 middle attacks. (See RFC 5746)
+ *                 (Most interoperable and least secure option)
+ *
+ *                 MBEDTLS_SSL_LEGACY_BREAK_HANDSHAKE breaks off connections
+ *                 if peer does not support secure renegotiation. Results
+ *                 in interoperability issues with non-upgraded peers
+ *                 that do not support renegotiation altogether.
+ *                 (Most secure option, interoperability issues)
+ *
+ * \param conf     SSL configuration
+ * \param allow_legacy  Prevent or allow (SSL_NO_LEGACY_RENEGOTIATION,
+ *                                        SSL_ALLOW_LEGACY_RENEGOTIATION or
+ *                                        MBEDTLS_SSL_LEGACY_BREAK_HANDSHAKE)
+ */
+void mbedtls_ssl_conf_legacy_renegotiation( mbedtls_ssl_config *conf, int allow_legacy );
+
+#if defined(MBEDTLS_SSL_RENEGOTIATION)
+/**
+ * \brief          Enforce renegotiation requests.
+ *                 (Default: enforced, max_records = 16)
+ *
+ *                 When we request a renegotiation, the peer can comply or
+ *                 ignore the request. This function allows us to decide
+ *                 whether to enforce our renegotiation requests by closing
+ *                 the connection if the peer doesn't comply.
+ *
+ *                 However, records could already be in transit from the peer
+ *                 when the request is emitted. In order to increase
+ *                 reliability, we can accept a number of records before the
+ *                 expected handshake records.
+ *
+ *                 The optimal value is highly dependent on the specific usage
+ *                 scenario.
+ *
+ * \note           With DTLS and server-initiated renegotiation, the
+ *                 HelloRequest is retransmited every time mbedtls_ssl_read() times
+ *                 out or receives Application Data, until:
+ *                 - max_records records have beens seen, if it is >= 0, or
+ *                 - the number of retransmits that would happen during an
+ *                 actual handshake has been reached.
+ *                 Please remember the request might be lost a few times
+ *                 if you consider setting max_records to a really low value.
+ *
+ * \warning        On client, the grace period can only happen during
+ *                 mbedtls_ssl_read(), as opposed to mbedtls_ssl_write() and mbedtls_ssl_renegotiate()
+ *                 which always behave as if max_record was 0. The reason is,
+ *                 if we receive application data from the server, we need a
+ *                 place to write it, which only happens during mbedtls_ssl_read().
+ *
+ * \param conf     SSL configuration
+ * \param max_records Use MBEDTLS_SSL_RENEGOTIATION_NOT_ENFORCED if you don't want to
+ *                 enforce renegotiation, or a non-negative value to enforce
+ *                 it but allow for a grace period of max_records records.
+ */
+void mbedtls_ssl_conf_renegotiation_enforced( mbedtls_ssl_config *conf, int max_records );
+
+/**
+ * \brief          Set record counter threshold for periodic renegotiation.
+ *                 (Default: 2^64 - 256.)
+ *
+ *                 Renegotiation is automatically triggered when a record
+ *                 counter (outgoing or ingoing) crosses the defined
+ *                 threshold. The default value is meant to prevent the
+ *                 connection from being closed when the counter is about to
+ *                 reached its maximal value (it is not allowed to wrap).
+ *
+ *                 Lower values can be used to enforce policies such as "keys
+ *                 must be refreshed every N packets with cipher X".
+ *
+ * \param conf     SSL configuration
+ * \param period   The threshold value: a big-endian 64-bit number.
+ *                 Set to 2^64 - 1 to disable periodic renegotiation
+ */
+void mbedtls_ssl_conf_renegotiation_period( mbedtls_ssl_config *conf,
+                                   const unsigned char period[8] );
+#endif /* MBEDTLS_SSL_RENEGOTIATION */
+
+/**
+ * \brief          Return the number of data bytes available to read
+ *
+ * \param ssl      SSL context
+ *
+ * \return         how many bytes are available in the read buffer
+ */
+size_t mbedtls_ssl_get_bytes_avail( const mbedtls_ssl_context *ssl );
+
+/**
+ * \brief          Return the result of the certificate verification
+ *
+ * \param ssl      SSL context
+ *
+ * \return         0 if successful,
+ *                 -1 if result is not available (eg because the handshake was
+ *                 aborted too early), or
+ *                 a combination of BADCERT_xxx and BADCRL_xxx flags, see
+ *                 x509.h
+ */
+uint32_t mbedtls_ssl_get_verify_result( const mbedtls_ssl_context *ssl );
+
+/**
+ * \brief          Return the name of the current ciphersuite
+ *
+ * \param ssl      SSL context
+ *
+ * \return         a string containing the ciphersuite name
+ */
+const char *mbedtls_ssl_get_ciphersuite( const mbedtls_ssl_context *ssl );
+
+/**
+ * \brief          Return the current SSL version (SSLv3/TLSv1/etc)
+ *
+ * \param ssl      SSL context
+ *
+ * \return         a string containing the SSL version
+ */
+const char *mbedtls_ssl_get_version( const mbedtls_ssl_context *ssl );
+
+/**
+ * \brief          Return the (maximum) number of bytes added by the record
+ *                 layer: header + encryption/MAC overhead (inc. padding)
+ *
+ * \param ssl      SSL context
+ *
+ * \return         Current maximum record expansion in bytes, or
+ *                 MBEDTLS_ERR_SSL_FEATURE_UNAVAILABLE if compression is
+ *                 enabled, which makes expansion much less predictable
+ */
+int mbedtls_ssl_get_record_expansion( const mbedtls_ssl_context *ssl );
+
+#if defined(MBEDTLS_SSL_MAX_FRAGMENT_LENGTH)
+/**
+ * \brief          Return the maximum fragment length (payload, in bytes).
+ *                 This is the value negotiated with peer if any,
+ *                 or the locally configured value.
+ *
+ * \note           With DTLS, \c mbedtls_ssl_write() will return an error if
+ *                 called with a larger length value.
+ *                 With TLS, \c mbedtls_ssl_write() will fragment the input if
+ *                 necessary and return the number of bytes written; it is up
+ *                 to the caller to call \c mbedtls_ssl_write() again in
+ *                 order to send the remaining bytes if any.
+ *
+ * \param ssl      SSL context
+ *
+ * \return         Current maximum fragment length.
+ */
+size_t mbedtls_ssl_get_max_frag_len( const mbedtls_ssl_context *ssl );
+#endif /* MBEDTLS_SSL_MAX_FRAGMENT_LENGTH */
+
+#if defined(MBEDTLS_X509_CRT_PARSE_C)
+/**
+ * \brief          Return the peer certificate from the current connection
+ *
+ *                 Note: Can be NULL in case no certificate was sent during
+ *                 the handshake. Different calls for the same connection can
+ *                 return the same or different pointers for the same
+ *                 certificate and even a different certificate altogether.
+ *                 The peer cert CAN change in a single connection if
+ *                 renegotiation is performed.
+ *
+ * \param ssl      SSL context
+ *
+ * \return         the current peer certificate
+ */
+const mbedtls_x509_crt *mbedtls_ssl_get_peer_cert( const mbedtls_ssl_context *ssl );
+#endif /* MBEDTLS_X509_CRT_PARSE_C */
+
+#if defined(MBEDTLS_SSL_CLI_C)
+/**
+ * \brief          Save session in order to resume it later (client-side only)
+ *                 Session data is copied to presented session structure.
+ *
+ * \warning        Currently, peer certificate is lost in the operation.
+ *
+ * \param ssl      SSL context
+ * \param session  session context
+ *
+ * \return         0 if successful,
+ *                 MBEDTLS_ERR_SSL_ALLOC_FAILED if memory allocation failed,
+ *                 MBEDTLS_ERR_SSL_BAD_INPUT_DATA if used server-side or
+ *                 arguments are otherwise invalid
+ *
+ * \sa             mbedtls_ssl_set_session()
+ */
+int mbedtls_ssl_get_session( const mbedtls_ssl_context *ssl, mbedtls_ssl_session *session );
+#endif /* MBEDTLS_SSL_CLI_C */
+
+/**
+ * \brief          Perform the SSL handshake
+ *
+ * \param ssl      SSL context
+ *
+ * \return         0 if successful, or
+ *                 MBEDTLS_ERR_SSL_WANT_READ or MBEDTLS_ERR_SSL_WANT_WRITE, or
+ *                 MBEDTLS_ERR_SSL_HELLO_VERIFY_REQUIRED (see below), or
+ *                 a specific SSL error code.
+ *
+ * \note           If this function returns something other than 0 or
+ *                 MBEDTLS_ERR_SSL_WANT_READ/WRITE, then the ssl context
+ *                 becomes unusable, and you should either free it or call
+ *                 \c mbedtls_ssl_session_reset() on it before re-using it for
+ *                 a new connection; the current connection must be closed.
+ *
+ * \note           If DTLS is in use, then you may choose to handle
+ *                 MBEDTLS_ERR_SSL_HELLO_VERIFY_REQUIRED specially for logging
+ *                 purposes, as it is an expected return value rather than an
+ *                 actual error, but you still need to reset/free the context.
+ */
+int mbedtls_ssl_handshake( mbedtls_ssl_context *ssl );
+
+/**
+ * \brief          Perform a single step of the SSL handshake
+ *
+ * \note           The state of the context (ssl->state) will be at
+ *                 the next state after execution of this function. Do not
+ *                 call this function if state is MBEDTLS_SSL_HANDSHAKE_OVER.
+ *
+ * \note           If this function returns something other than 0 or
+ *                 MBEDTLS_ERR_SSL_WANT_READ/WRITE, then the ssl context
+ *                 becomes unusable, and you should either free it or call
+ *                 \c mbedtls_ssl_session_reset() on it before re-using it for
+ *                 a new connection; the current connection must be closed.
+ *
+ * \param ssl      SSL context
+ *
+ * \return         0 if successful, or
+ *                 MBEDTLS_ERR_SSL_WANT_READ or MBEDTLS_ERR_SSL_WANT_WRITE, or
+ *                 a specific SSL error code.
+ */
+int mbedtls_ssl_handshake_step( mbedtls_ssl_context *ssl );
+
+#if defined(MBEDTLS_SSL_RENEGOTIATION)
+/**
+ * \brief          Initiate an SSL renegotiation on the running connection.
+ *                 Client: perform the renegotiation right now.
+ *                 Server: request renegotiation, which will be performed
+ *                 during the next call to mbedtls_ssl_read() if honored by
+ *                 client.
+ *
+ * \param ssl      SSL context
+ *
+ * \return         0 if successful, or any mbedtls_ssl_handshake() return
+ *                 value.
+ *
+ * \note           If this function returns something other than 0 or
+ *                 MBEDTLS_ERR_SSL_WANT_READ/WRITE, then the ssl context
+ *                 becomes unusable, and you should either free it or call
+ *                 \c mbedtls_ssl_session_reset() on it before re-using it for
+ *                 a new connection; the current connection must be closed.
+ */
+int mbedtls_ssl_renegotiate( mbedtls_ssl_context *ssl );
+#endif /* MBEDTLS_SSL_RENEGOTIATION */
+
+/**
+ * \brief          Read at most 'len' application data bytes
+ *
+ * \param ssl      SSL context
+ * \param buf      buffer that will hold the data
+ * \param len      maximum number of bytes to read
+ *
+ * \return         the number of bytes read, or
+ *                 0 for EOF, or
+ *                 MBEDTLS_ERR_SSL_WANT_READ or MBEDTLS_ERR_SSL_WANT_WRITE, or
+ *                 MBEDTLS_ERR_SSL_CLIENT_RECONNECT (see below), or
+ *                 another negative error code.
+ *
+ * \note           If this function returns something other than a positive
+ *                 value or MBEDTLS_ERR_SSL_WANT_READ/WRITE or
+ *                 MBEDTLS_ERR_SSL_CLIENT_RECONNECT, then the ssl context
+ *                 becomes unusable, and you should either free it or call
+ *                 \c mbedtls_ssl_session_reset() on it before re-using it for
+ *                 a new connection; the current connection must be closed.
+ *
+ * \note           When this function return MBEDTLS_ERR_SSL_CLIENT_RECONNECT
+ *                 (which can only happen server-side), it means that a client
+ *                 is initiating a new connection using the same source port.
+ *                 You can either treat that as a connection close and wait
+ *                 for the client to resend a ClientHello, or directly
+ *                 continue with \c mbedtls_ssl_handshake() with the same
+ *                 context (as it has beeen reset internally). Either way, you
+ *                 should make sure this is seen by the application as a new
+ *                 connection: application state, if any, should be reset, and
+ *                 most importantly the identity of the client must be checked
+ *                 again. WARNING: not validating the identity of the client
+ *                 again, or not transmitting the new identity to the
+ *                 application layer, would allow authentication bypass!
+ */
+int mbedtls_ssl_read( mbedtls_ssl_context *ssl, unsigned char *buf, size_t len );
+
+/**
+ * \brief          Try to write exactly 'len' application data bytes
+ *
+ * \warning        This function will do partial writes in some cases. If the
+ *                 return value is non-negative but less than length, the
+ *                 function must be called again with updated arguments:
+ *                 buf + ret, len - ret (if ret is the return value) until
+ *                 it returns a value equal to the last 'len' argument.
+ *
+ * \param ssl      SSL context
+ * \param buf      buffer holding the data
+ * \param len      how many bytes must be written
+ *
+ * \return         the number of bytes actually written (may be less than len),
+ *                 or MBEDTLS_ERR_SSL_WANT_WRITE of MBEDTLS_ERR_SSL_WANT_READ,
+ *                 or another negative error code.
+ *
+ * \note           If this function returns something other than a positive
+ *                 value or MBEDTLS_ERR_SSL_WANT_READ/WRITE, the ssl context
+ *                 becomes unusable, and you should either free it or call
+ *                 \c mbedtls_ssl_session_reset() on it before re-using it for
+ *                 a new connection; the current connection must be closed.
+ *
+ * \note           When this function returns MBEDTLS_ERR_SSL_WANT_WRITE/READ,
+ *                 it must be called later with the *same* arguments,
+ *                 until it returns a positive value.
+ *
+ * \note           If the requested length is greater than the maximum
+ *                 fragment length (either the built-in limit or the one set
+ *                 or negotiated with the peer), then:
+ *                 - with TLS, less bytes than requested are written.
+ *                 - with DTLS, MBEDTLS_ERR_SSL_BAD_INPUT_DATA is returned.
+ *                 \c mbedtls_ssl_get_max_frag_len() may be used to query the
+ *                 active maximum fragment length.
+ */
+int mbedtls_ssl_write( mbedtls_ssl_context *ssl, const unsigned char *buf, size_t len );
+
+/**
+ * \brief           Send an alert message
+ *
+ * \param ssl       SSL context
+ * \param level     The alert level of the message
+ *                  (MBEDTLS_SSL_ALERT_LEVEL_WARNING or MBEDTLS_SSL_ALERT_LEVEL_FATAL)
+ * \param message   The alert message (SSL_ALERT_MSG_*)
+ *
+ * \return          0 if successful, or a specific SSL error code.
+ *
+ * \note           If this function returns something other than 0 or
+ *                 MBEDTLS_ERR_SSL_WANT_READ/WRITE, then the ssl context
+ *                 becomes unusable, and you should either free it or call
+ *                 \c mbedtls_ssl_session_reset() on it before re-using it for
+ *                 a new connection; the current connection must be closed.
+ */
+int mbedtls_ssl_send_alert_message( mbedtls_ssl_context *ssl,
+                            unsigned char level,
+                            unsigned char message );
+/**
+ * \brief          Notify the peer that the connection is being closed
+ *
+ * \param ssl      SSL context
+ *
+ * \return          0 if successful, or a specific SSL error code.
+ *
+ * \note           If this function returns something other than 0 or
+ *                 MBEDTLS_ERR_SSL_WANT_READ/WRITE, then the ssl context
+ *                 becomes unusable, and you should either free it or call
+ *                 \c mbedtls_ssl_session_reset() on it before re-using it for
+ *                 a new connection; the current connection must be closed.
+ */
+int mbedtls_ssl_close_notify( mbedtls_ssl_context *ssl );
+
+/**
+ * \brief          Free referenced items in an SSL context and clear memory
+ *
+ * \param ssl      SSL context
+ */
+void mbedtls_ssl_free( mbedtls_ssl_context *ssl );
+
+/**
+ * \brief          Initialize an SSL configuration context
+ *                 Just makes the context ready for
+ *                 mbedtls_ssl_config_defaults() or mbedtls_ssl_config_free().
+ *
+ * \note           You need to call mbedtls_ssl_config_defaults() unless you
+ *                 manually set all of the relevent fields yourself.
+ *
+ * \param conf     SSL configuration context
+ */
+void mbedtls_ssl_config_init( mbedtls_ssl_config *conf );
+
+/**
+ * \brief          Load reasonnable default SSL configuration values.
+ *                 (You need to call mbedtls_ssl_config_init() first.)
+ *
+ * \param conf     SSL configuration context
+ * \param endpoint MBEDTLS_SSL_IS_CLIENT or MBEDTLS_SSL_IS_SERVER
+ * \param transport MBEDTLS_SSL_TRANSPORT_STREAM for TLS, or
+ *                  MBEDTLS_SSL_TRANSPORT_DATAGRAM for DTLS
+ * \param preset   a MBEDTLS_SSL_PRESET_XXX value
+ *                 (currently unused).
+ *
+ * \note           See \c mbedtls_ssl_conf_transport() for notes on DTLS.
+ *
+ * \return         0 if successful, or
+ *                 MBEDTLS_ERR_XXX_ALLOC_FAILED on memory allocation error.
+ */
+int mbedtls_ssl_config_defaults( mbedtls_ssl_config *conf,
+                                 int endpoint, int transport, int preset );
+
+/**
+ * \brief          Free an SSL configuration context
+ *
+ * \param conf     SSL configuration context
+ */
+void mbedtls_ssl_config_free( mbedtls_ssl_config *conf );
+
+/**
+ * \brief          Initialize SSL session structure
+ *
+ * \param session  SSL session
+ */
+void mbedtls_ssl_session_init( mbedtls_ssl_session *session );
+
+/**
+ * \brief          Free referenced items in an SSL session including the
+ *                 peer certificate and clear memory
+ *
+ * \param session  SSL session
+ */
+void mbedtls_ssl_session_free( mbedtls_ssl_session *session );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ssl.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/ssl_cache.h b/tools/sdk/include/mbedtls/mbedtls/ssl_cache.h
new file mode 100644
index 00000000..3734bb72
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/ssl_cache.h
@@ -0,0 +1,143 @@
+/**
+ * \file ssl_cache.h
+ *
+ * \brief SSL session cache implementation
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_SSL_CACHE_H
+#define MBEDTLS_SSL_CACHE_H
+
+#include "ssl.h"
+
+#if defined(MBEDTLS_THREADING_C)
+#include "threading.h"
+#endif
+
+/**
+ * \name SECTION: Module settings
+ *
+ * The configuration options you can set for this module are in this section.
+ * Either change them in config.h or define them on the compiler command line.
+ * \{
+ */
+
+#if !defined(MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT)
+#define MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT       86400   /*!< 1 day  */
+#endif
+
+#if !defined(MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES)
+#define MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES      50   /*!< Maximum entries in cache */
+#endif
+
+/* \} name SECTION: Module settings */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct mbedtls_ssl_cache_context mbedtls_ssl_cache_context;
+typedef struct mbedtls_ssl_cache_entry mbedtls_ssl_cache_entry;
+
+/**
+ * \brief   This structure is used for storing cache entries
+ */
+struct mbedtls_ssl_cache_entry
+{
+#if defined(MBEDTLS_HAVE_TIME)
+    mbedtls_time_t timestamp;           /*!< entry timestamp    */
+#endif
+    mbedtls_ssl_session session;        /*!< entry session      */
+#if defined(MBEDTLS_X509_CRT_PARSE_C)
+    mbedtls_x509_buf peer_cert;         /*!< entry peer_cert    */
+#endif
+    mbedtls_ssl_cache_entry *next;      /*!< chain pointer      */
+};
+
+/**
+ * \brief Cache context
+ */
+struct mbedtls_ssl_cache_context
+{
+    mbedtls_ssl_cache_entry *chain;     /*!< start of the chain     */
+    int timeout;                /*!< cache entry timeout    */
+    int max_entries;            /*!< maximum entries        */
+#if defined(MBEDTLS_THREADING_C)
+    mbedtls_threading_mutex_t mutex;    /*!< mutex                  */
+#endif
+};
+
+/**
+ * \brief          Initialize an SSL cache context
+ *
+ * \param cache    SSL cache context
+ */
+void mbedtls_ssl_cache_init( mbedtls_ssl_cache_context *cache );
+
+/**
+ * \brief          Cache get callback implementation
+ *                 (Thread-safe if MBEDTLS_THREADING_C is enabled)
+ *
+ * \param data     SSL cache context
+ * \param session  session to retrieve entry for
+ */
+int mbedtls_ssl_cache_get( void *data, mbedtls_ssl_session *session );
+
+/**
+ * \brief          Cache set callback implementation
+ *                 (Thread-safe if MBEDTLS_THREADING_C is enabled)
+ *
+ * \param data     SSL cache context
+ * \param session  session to store entry for
+ */
+int mbedtls_ssl_cache_set( void *data, const mbedtls_ssl_session *session );
+
+#if defined(MBEDTLS_HAVE_TIME)
+/**
+ * \brief          Set the cache timeout
+ *                 (Default: MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT (1 day))
+ *
+ *                 A timeout of 0 indicates no timeout.
+ *
+ * \param cache    SSL cache context
+ * \param timeout  cache entry timeout in seconds
+ */
+void mbedtls_ssl_cache_set_timeout( mbedtls_ssl_cache_context *cache, int timeout );
+#endif /* MBEDTLS_HAVE_TIME */
+
+/**
+ * \brief          Set the maximum number of cache entries
+ *                 (Default: MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES (50))
+ *
+ * \param cache    SSL cache context
+ * \param max      cache entry maximum
+ */
+void mbedtls_ssl_cache_set_max_entries( mbedtls_ssl_cache_context *cache, int max );
+
+/**
+ * \brief          Free referenced items in a cache context and clear memory
+ *
+ * \param cache    SSL cache context
+ */
+void mbedtls_ssl_cache_free( mbedtls_ssl_cache_context *cache );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ssl_cache.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/ssl_ciphersuites.h b/tools/sdk/include/mbedtls/mbedtls/ssl_ciphersuites.h
new file mode 100644
index 00000000..deaaa375
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/ssl_ciphersuites.h
@@ -0,0 +1,321 @@
+/**
+ * \file ssl_ciphersuites.h
+ *
+ * \brief SSL Ciphersuites for mbed TLS
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_SSL_CIPHERSUITES_H
+#define MBEDTLS_SSL_CIPHERSUITES_H
+
+#include "pk.h"
+#include "cipher.h"
+#include "md.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Supported ciphersuites (Official IANA names)
+ */
+#define MBEDTLS_TLS_RSA_WITH_NULL_MD5                    0x01   /**< Weak! */
+#define MBEDTLS_TLS_RSA_WITH_NULL_SHA                    0x02   /**< Weak! */
+
+#define MBEDTLS_TLS_RSA_WITH_RC4_128_MD5                 0x04
+#define MBEDTLS_TLS_RSA_WITH_RC4_128_SHA                 0x05
+#define MBEDTLS_TLS_RSA_WITH_DES_CBC_SHA                 0x09   /**< Weak! Not in TLS 1.2 */
+
+#define MBEDTLS_TLS_RSA_WITH_3DES_EDE_CBC_SHA            0x0A
+
+#define MBEDTLS_TLS_DHE_RSA_WITH_DES_CBC_SHA             0x15   /**< Weak! Not in TLS 1.2 */
+#define MBEDTLS_TLS_DHE_RSA_WITH_3DES_EDE_CBC_SHA        0x16
+
+#define MBEDTLS_TLS_PSK_WITH_NULL_SHA                    0x2C   /**< Weak! */
+#define MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA                0x2D   /**< Weak! */
+#define MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA                0x2E   /**< Weak! */
+#define MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA             0x2F
+
+#define MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA         0x33
+#define MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA             0x35
+#define MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA         0x39
+
+#define MBEDTLS_TLS_RSA_WITH_NULL_SHA256                 0x3B   /**< Weak! */
+#define MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA256          0x3C   /**< TLS 1.2 */
+#define MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA256          0x3D   /**< TLS 1.2 */
+
+#define MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA        0x41
+#define MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA    0x45
+
+#define MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA256      0x67   /**< TLS 1.2 */
+#define MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA256      0x6B   /**< TLS 1.2 */
+
+#define MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA        0x84
+#define MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA    0x88
+
+#define MBEDTLS_TLS_PSK_WITH_RC4_128_SHA                 0x8A
+#define MBEDTLS_TLS_PSK_WITH_3DES_EDE_CBC_SHA            0x8B
+#define MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA             0x8C
+#define MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA             0x8D
+
+#define MBEDTLS_TLS_DHE_PSK_WITH_RC4_128_SHA             0x8E
+#define MBEDTLS_TLS_DHE_PSK_WITH_3DES_EDE_CBC_SHA        0x8F
+#define MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA         0x90
+#define MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA         0x91
+
+#define MBEDTLS_TLS_RSA_PSK_WITH_RC4_128_SHA             0x92
+#define MBEDTLS_TLS_RSA_PSK_WITH_3DES_EDE_CBC_SHA        0x93
+#define MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA         0x94
+#define MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA         0x95
+
+#define MBEDTLS_TLS_RSA_WITH_AES_128_GCM_SHA256          0x9C   /**< TLS 1.2 */
+#define MBEDTLS_TLS_RSA_WITH_AES_256_GCM_SHA384          0x9D   /**< TLS 1.2 */
+#define MBEDTLS_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256      0x9E   /**< TLS 1.2 */
+#define MBEDTLS_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384      0x9F   /**< TLS 1.2 */
+
+#define MBEDTLS_TLS_PSK_WITH_AES_128_GCM_SHA256          0xA8   /**< TLS 1.2 */
+#define MBEDTLS_TLS_PSK_WITH_AES_256_GCM_SHA384          0xA9   /**< TLS 1.2 */
+#define MBEDTLS_TLS_DHE_PSK_WITH_AES_128_GCM_SHA256      0xAA   /**< TLS 1.2 */
+#define MBEDTLS_TLS_DHE_PSK_WITH_AES_256_GCM_SHA384      0xAB   /**< TLS 1.2 */
+#define MBEDTLS_TLS_RSA_PSK_WITH_AES_128_GCM_SHA256      0xAC   /**< TLS 1.2 */
+#define MBEDTLS_TLS_RSA_PSK_WITH_AES_256_GCM_SHA384      0xAD   /**< TLS 1.2 */
+
+#define MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA256          0xAE
+#define MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA384          0xAF
+#define MBEDTLS_TLS_PSK_WITH_NULL_SHA256                 0xB0   /**< Weak! */
+#define MBEDTLS_TLS_PSK_WITH_NULL_SHA384                 0xB1   /**< Weak! */
+
+#define MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA256      0xB2
+#define MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA384      0xB3
+#define MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA256             0xB4   /**< Weak! */
+#define MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA384             0xB5   /**< Weak! */
+
+#define MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA256      0xB6
+#define MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA384      0xB7
+#define MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA256             0xB8   /**< Weak! */
+#define MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA384             0xB9   /**< Weak! */
+
+#define MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256     0xBA   /**< TLS 1.2 */
+#define MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256 0xBE   /**< TLS 1.2 */
+
+#define MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256     0xC0   /**< TLS 1.2 */
+#define MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256 0xC4   /**< TLS 1.2 */
+
+#define MBEDTLS_TLS_ECDH_ECDSA_WITH_NULL_SHA             0xC001 /**< Weak! */
+#define MBEDTLS_TLS_ECDH_ECDSA_WITH_RC4_128_SHA          0xC002 /**< Not in SSL3! */
+#define MBEDTLS_TLS_ECDH_ECDSA_WITH_3DES_EDE_CBC_SHA     0xC003 /**< Not in SSL3! */
+#define MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA      0xC004 /**< Not in SSL3! */
+#define MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA      0xC005 /**< Not in SSL3! */
+
+#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_NULL_SHA            0xC006 /**< Weak! */
+#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_RC4_128_SHA         0xC007 /**< Not in SSL3! */
+#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA    0xC008 /**< Not in SSL3! */
+#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA     0xC009 /**< Not in SSL3! */
+#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA     0xC00A /**< Not in SSL3! */
+
+#define MBEDTLS_TLS_ECDH_RSA_WITH_NULL_SHA               0xC00B /**< Weak! */
+#define MBEDTLS_TLS_ECDH_RSA_WITH_RC4_128_SHA            0xC00C /**< Not in SSL3! */
+#define MBEDTLS_TLS_ECDH_RSA_WITH_3DES_EDE_CBC_SHA       0xC00D /**< Not in SSL3! */
+#define MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA        0xC00E /**< Not in SSL3! */
+#define MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA        0xC00F /**< Not in SSL3! */
+
+#define MBEDTLS_TLS_ECDHE_RSA_WITH_NULL_SHA              0xC010 /**< Weak! */
+#define MBEDTLS_TLS_ECDHE_RSA_WITH_RC4_128_SHA           0xC011 /**< Not in SSL3! */
+#define MBEDTLS_TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA      0xC012 /**< Not in SSL3! */
+#define MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA       0xC013 /**< Not in SSL3! */
+#define MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA       0xC014 /**< Not in SSL3! */
+
+#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256  0xC023 /**< TLS 1.2 */
+#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384  0xC024 /**< TLS 1.2 */
+#define MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256   0xC025 /**< TLS 1.2 */
+#define MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384   0xC026 /**< TLS 1.2 */
+#define MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256    0xC027 /**< TLS 1.2 */
+#define MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384    0xC028 /**< TLS 1.2 */
+#define MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256     0xC029 /**< TLS 1.2 */
+#define MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384     0xC02A /**< TLS 1.2 */
+
+#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256  0xC02B /**< TLS 1.2 */
+#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384  0xC02C /**< TLS 1.2 */
+#define MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256   0xC02D /**< TLS 1.2 */
+#define MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384   0xC02E /**< TLS 1.2 */
+#define MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256    0xC02F /**< TLS 1.2 */
+#define MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384    0xC030 /**< TLS 1.2 */
+#define MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256     0xC031 /**< TLS 1.2 */
+#define MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384     0xC032 /**< TLS 1.2 */
+
+#define MBEDTLS_TLS_ECDHE_PSK_WITH_RC4_128_SHA           0xC033 /**< Not in SSL3! */
+#define MBEDTLS_TLS_ECDHE_PSK_WITH_3DES_EDE_CBC_SHA      0xC034 /**< Not in SSL3! */
+#define MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA       0xC035 /**< Not in SSL3! */
+#define MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA       0xC036 /**< Not in SSL3! */
+#define MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA256    0xC037 /**< Not in SSL3! */
+#define MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA384    0xC038 /**< Not in SSL3! */
+#define MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA              0xC039 /**< Weak! No SSL3! */
+#define MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA256           0xC03A /**< Weak! No SSL3! */
+#define MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA384           0xC03B /**< Weak! No SSL3! */
+
+#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_CBC_SHA256 0xC072 /**< Not in SSL3! */
+#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_CBC_SHA384 0xC073 /**< Not in SSL3! */
+#define MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_CBC_SHA256  0xC074 /**< Not in SSL3! */
+#define MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_CBC_SHA384  0xC075 /**< Not in SSL3! */
+#define MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_CBC_SHA256   0xC076 /**< Not in SSL3! */
+#define MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_CBC_SHA384   0xC077 /**< Not in SSL3! */
+#define MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_CBC_SHA256    0xC078 /**< Not in SSL3! */
+#define MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_CBC_SHA384    0xC079 /**< Not in SSL3! */
+
+#define MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_GCM_SHA256         0xC07A /**< TLS 1.2 */
+#define MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_GCM_SHA384         0xC07B /**< TLS 1.2 */
+#define MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_GCM_SHA256     0xC07C /**< TLS 1.2 */
+#define MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_GCM_SHA384     0xC07D /**< TLS 1.2 */
+#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_GCM_SHA256 0xC086 /**< TLS 1.2 */
+#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_GCM_SHA384 0xC087 /**< TLS 1.2 */
+#define MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_GCM_SHA256  0xC088 /**< TLS 1.2 */
+#define MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_GCM_SHA384  0xC089 /**< TLS 1.2 */
+#define MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_GCM_SHA256   0xC08A /**< TLS 1.2 */
+#define MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_GCM_SHA384   0xC08B /**< TLS 1.2 */
+#define MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_GCM_SHA256    0xC08C /**< TLS 1.2 */
+#define MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_GCM_SHA384    0xC08D /**< TLS 1.2 */
+
+#define MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_GCM_SHA256       0xC08E /**< TLS 1.2 */
+#define MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_GCM_SHA384       0xC08F /**< TLS 1.2 */
+#define MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_GCM_SHA256   0xC090 /**< TLS 1.2 */
+#define MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_GCM_SHA384   0xC091 /**< TLS 1.2 */
+#define MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_GCM_SHA256   0xC092 /**< TLS 1.2 */
+#define MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_GCM_SHA384   0xC093 /**< TLS 1.2 */
+
+#define MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256       0xC094
+#define MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_CBC_SHA384       0xC095
+#define MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_CBC_SHA256   0xC096
+#define MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_CBC_SHA384   0xC097
+#define MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_CBC_SHA256   0xC098
+#define MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_CBC_SHA384   0xC099
+#define MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_128_CBC_SHA256 0xC09A /**< Not in SSL3! */
+#define MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_256_CBC_SHA384 0xC09B /**< Not in SSL3! */
+
+#define MBEDTLS_TLS_RSA_WITH_AES_128_CCM                0xC09C  /**< TLS 1.2 */
+#define MBEDTLS_TLS_RSA_WITH_AES_256_CCM                0xC09D  /**< TLS 1.2 */
+#define MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CCM            0xC09E  /**< TLS 1.2 */
+#define MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CCM            0xC09F  /**< TLS 1.2 */
+#define MBEDTLS_TLS_RSA_WITH_AES_128_CCM_8              0xC0A0  /**< TLS 1.2 */
+#define MBEDTLS_TLS_RSA_WITH_AES_256_CCM_8              0xC0A1  /**< TLS 1.2 */
+#define MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CCM_8          0xC0A2  /**< TLS 1.2 */
+#define MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CCM_8          0xC0A3  /**< TLS 1.2 */
+#define MBEDTLS_TLS_PSK_WITH_AES_128_CCM                0xC0A4  /**< TLS 1.2 */
+#define MBEDTLS_TLS_PSK_WITH_AES_256_CCM                0xC0A5  /**< TLS 1.2 */
+#define MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CCM            0xC0A6  /**< TLS 1.2 */
+#define MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CCM            0xC0A7  /**< TLS 1.2 */
+#define MBEDTLS_TLS_PSK_WITH_AES_128_CCM_8              0xC0A8  /**< TLS 1.2 */
+#define MBEDTLS_TLS_PSK_WITH_AES_256_CCM_8              0xC0A9  /**< TLS 1.2 */
+#define MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CCM_8          0xC0AA  /**< TLS 1.2 */
+#define MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CCM_8          0xC0AB  /**< TLS 1.2 */
+/* The last two are named with PSK_DHE in the RFC, which looks like a typo */
+
+#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CCM        0xC0AC  /**< TLS 1.2 */
+#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CCM        0xC0AD  /**< TLS 1.2 */
+#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CCM_8      0xC0AE  /**< TLS 1.2 */
+#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CCM_8      0xC0AF  /**< TLS 1.2 */
+
+#define MBEDTLS_TLS_ECJPAKE_WITH_AES_128_CCM_8          0xC0FF  /**< experimental */
+
+/* Reminder: update mbedtls_ssl_premaster_secret when adding a new key exchange.
+ * Reminder: update MBEDTLS_KEY_EXCHANGE__xxx below
+ */
+typedef enum {
+    MBEDTLS_KEY_EXCHANGE_NONE = 0,
+    MBEDTLS_KEY_EXCHANGE_RSA,
+    MBEDTLS_KEY_EXCHANGE_DHE_RSA,
+    MBEDTLS_KEY_EXCHANGE_ECDHE_RSA,
+    MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA,
+    MBEDTLS_KEY_EXCHANGE_PSK,
+    MBEDTLS_KEY_EXCHANGE_DHE_PSK,
+    MBEDTLS_KEY_EXCHANGE_RSA_PSK,
+    MBEDTLS_KEY_EXCHANGE_ECDHE_PSK,
+    MBEDTLS_KEY_EXCHANGE_ECDH_RSA,
+    MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA,
+    MBEDTLS_KEY_EXCHANGE_ECJPAKE,
+} mbedtls_key_exchange_type_t;
+
+/* Key exchanges using a certificate */
+#if defined(MBEDTLS_KEY_EXCHANGE_RSA_ENABLED)           || \
+    defined(MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED)       || \
+    defined(MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED)     || \
+    defined(MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED)   || \
+    defined(MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED)       || \
+    defined(MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED)      || \
+    defined(MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED)
+#define MBEDTLS_KEY_EXCHANGE__WITH_CERT__ENABLED
+#endif
+
+/* Key exchanges using a PSK */
+#if defined(MBEDTLS_KEY_EXCHANGE_PSK_ENABLED)           || \
+    defined(MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED)       || \
+    defined(MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED)       || \
+    defined(MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED)
+#define MBEDTLS_KEY_EXCHANGE__SOME__PSK_ENABLED
+#endif
+
+/* Key exchanges using a ECDHE */
+#if defined(MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED)     || \
+    defined(MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED)   || \
+    defined(MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED)
+#define MBEDTLS_KEY_EXCHANGE__SOME__ECDHE_ENABLED
+#endif
+
+typedef struct mbedtls_ssl_ciphersuite_t mbedtls_ssl_ciphersuite_t;
+
+#define MBEDTLS_CIPHERSUITE_WEAK       0x01    /**< Weak ciphersuite flag  */
+#define MBEDTLS_CIPHERSUITE_SHORT_TAG  0x02    /**< Short authentication tag,
+                                                     eg for CCM_8 */
+#define MBEDTLS_CIPHERSUITE_NODTLS     0x04    /**< Can't be used with DTLS */
+
+/**
+ * \brief   This structure is used for storing ciphersuite information
+ */
+struct mbedtls_ssl_ciphersuite_t
+{
+    int id;
+    const char * name;
+
+    mbedtls_cipher_type_t cipher;
+    mbedtls_md_type_t mac;
+    mbedtls_key_exchange_type_t key_exchange;
+
+    int min_major_ver;
+    int min_minor_ver;
+    int max_major_ver;
+    int max_minor_ver;
+
+    unsigned char flags;
+};
+
+const int *mbedtls_ssl_list_ciphersuites( void );
+
+const mbedtls_ssl_ciphersuite_t *mbedtls_ssl_ciphersuite_from_string( const char *ciphersuite_name );
+const mbedtls_ssl_ciphersuite_t *mbedtls_ssl_ciphersuite_from_id( int ciphersuite_id );
+
+#if defined(MBEDTLS_PK_C)
+mbedtls_pk_type_t mbedtls_ssl_get_ciphersuite_sig_pk_alg( const mbedtls_ssl_ciphersuite_t *info );
+#endif
+
+int mbedtls_ssl_ciphersuite_uses_ec( const mbedtls_ssl_ciphersuite_t *info );
+int mbedtls_ssl_ciphersuite_uses_psk( const mbedtls_ssl_ciphersuite_t *info );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ssl_ciphersuites.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/ssl_cookie.h b/tools/sdk/include/mbedtls/mbedtls/ssl_cookie.h
new file mode 100644
index 00000000..037e1c31
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/ssl_cookie.h
@@ -0,0 +1,108 @@
+/**
+ * \file ssl_cookie.h
+ *
+ * \brief DTLS cookie callbacks implementation
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_SSL_COOKIE_H
+#define MBEDTLS_SSL_COOKIE_H
+
+#include "ssl.h"
+
+#if defined(MBEDTLS_THREADING_C)
+#include "threading.h"
+#endif
+
+/**
+ * \name SECTION: Module settings
+ *
+ * The configuration options you can set for this module are in this section.
+ * Either change them in config.h or define them on the compiler command line.
+ * \{
+ */
+#ifndef MBEDTLS_SSL_COOKIE_TIMEOUT
+#define MBEDTLS_SSL_COOKIE_TIMEOUT     60 /**< Default expiration delay of DTLS cookies, in seconds if HAVE_TIME, or in number of cookies issued */
+#endif
+
+/* \} name SECTION: Module settings */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          Context for the default cookie functions.
+ */
+typedef struct
+{
+    mbedtls_md_context_t    hmac_ctx;   /*!< context for the HMAC portion   */
+#if !defined(MBEDTLS_HAVE_TIME)
+    unsigned long   serial;     /*!< serial number for expiration   */
+#endif
+    unsigned long   timeout;    /*!< timeout delay, in seconds if HAVE_TIME,
+                                     or in number of tickets issued */
+
+#if defined(MBEDTLS_THREADING_C)
+    mbedtls_threading_mutex_t mutex;
+#endif
+} mbedtls_ssl_cookie_ctx;
+
+/**
+ * \brief          Initialize cookie context
+ */
+void mbedtls_ssl_cookie_init( mbedtls_ssl_cookie_ctx *ctx );
+
+/**
+ * \brief          Setup cookie context (generate keys)
+ */
+int mbedtls_ssl_cookie_setup( mbedtls_ssl_cookie_ctx *ctx,
+                      int (*f_rng)(void *, unsigned char *, size_t),
+                      void *p_rng );
+
+/**
+ * \brief          Set expiration delay for cookies
+ *                 (Default MBEDTLS_SSL_COOKIE_TIMEOUT)
+ *
+ * \param ctx      Cookie contex
+ * \param delay    Delay, in seconds if HAVE_TIME, or in number of cookies
+ *                 issued in the meantime.
+ *                 0 to disable expiration (NOT recommended)
+ */
+void mbedtls_ssl_cookie_set_timeout( mbedtls_ssl_cookie_ctx *ctx, unsigned long delay );
+
+/**
+ * \brief          Free cookie context
+ */
+void mbedtls_ssl_cookie_free( mbedtls_ssl_cookie_ctx *ctx );
+
+/**
+ * \brief          Generate cookie, see \c mbedtls_ssl_cookie_write_t
+ */
+mbedtls_ssl_cookie_write_t mbedtls_ssl_cookie_write;
+
+/**
+ * \brief          Verify cookie, see \c mbedtls_ssl_cookie_write_t
+ */
+mbedtls_ssl_cookie_check_t mbedtls_ssl_cookie_check;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ssl_cookie.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/ssl_internal.h b/tools/sdk/include/mbedtls/mbedtls/ssl_internal.h
new file mode 100644
index 00000000..d63d7d4e
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/ssl_internal.h
@@ -0,0 +1,494 @@
+/**
+ * \file ssl_ticket.h
+ *
+ * \brief Internal functions shared by the SSL modules
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_SSL_INTERNAL_H
+#define MBEDTLS_SSL_INTERNAL_H
+
+#include "ssl.h"
+
+#if defined(MBEDTLS_MD5_C)
+#include "md5.h"
+#endif
+
+#if defined(MBEDTLS_SHA1_C)
+#include "sha1.h"
+#endif
+
+#if defined(MBEDTLS_SHA256_C)
+#include "sha256.h"
+#endif
+
+#if defined(MBEDTLS_SHA512_C)
+#include "sha512.h"
+#endif
+
+#if defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED)
+#include "ecjpake.h"
+#endif
+
+#if ( defined(__ARMCC_VERSION) || defined(_MSC_VER) ) && \
+    !defined(inline) && !defined(__cplusplus)
+#define inline __inline
+#endif
+
+/* Determine minimum supported version */
+#define MBEDTLS_SSL_MIN_MAJOR_VERSION           MBEDTLS_SSL_MAJOR_VERSION_3
+
+#if defined(MBEDTLS_SSL_PROTO_SSL3)
+#define MBEDTLS_SSL_MIN_MINOR_VERSION           MBEDTLS_SSL_MINOR_VERSION_0
+#else
+#if defined(MBEDTLS_SSL_PROTO_TLS1)
+#define MBEDTLS_SSL_MIN_MINOR_VERSION           MBEDTLS_SSL_MINOR_VERSION_1
+#else
+#if defined(MBEDTLS_SSL_PROTO_TLS1_1)
+#define MBEDTLS_SSL_MIN_MINOR_VERSION           MBEDTLS_SSL_MINOR_VERSION_2
+#else
+#if defined(MBEDTLS_SSL_PROTO_TLS1_2)
+#define MBEDTLS_SSL_MIN_MINOR_VERSION           MBEDTLS_SSL_MINOR_VERSION_3
+#endif /* MBEDTLS_SSL_PROTO_TLS1_2 */
+#endif /* MBEDTLS_SSL_PROTO_TLS1_1 */
+#endif /* MBEDTLS_SSL_PROTO_TLS1   */
+#endif /* MBEDTLS_SSL_PROTO_SSL3   */
+
+/* Determine maximum supported version */
+#define MBEDTLS_SSL_MAX_MAJOR_VERSION           MBEDTLS_SSL_MAJOR_VERSION_3
+
+#if defined(MBEDTLS_SSL_PROTO_TLS1_2)
+#define MBEDTLS_SSL_MAX_MINOR_VERSION           MBEDTLS_SSL_MINOR_VERSION_3
+#else
+#if defined(MBEDTLS_SSL_PROTO_TLS1_1)
+#define MBEDTLS_SSL_MAX_MINOR_VERSION           MBEDTLS_SSL_MINOR_VERSION_2
+#else
+#if defined(MBEDTLS_SSL_PROTO_TLS1)
+#define MBEDTLS_SSL_MAX_MINOR_VERSION           MBEDTLS_SSL_MINOR_VERSION_1
+#else
+#if defined(MBEDTLS_SSL_PROTO_SSL3)
+#define MBEDTLS_SSL_MAX_MINOR_VERSION           MBEDTLS_SSL_MINOR_VERSION_0
+#endif /* MBEDTLS_SSL_PROTO_SSL3   */
+#endif /* MBEDTLS_SSL_PROTO_TLS1   */
+#endif /* MBEDTLS_SSL_PROTO_TLS1_1 */
+#endif /* MBEDTLS_SSL_PROTO_TLS1_2 */
+
+#define MBEDTLS_SSL_INITIAL_HANDSHAKE           0
+#define MBEDTLS_SSL_RENEGOTIATION_IN_PROGRESS   1   /* In progress */
+#define MBEDTLS_SSL_RENEGOTIATION_DONE          2   /* Done or aborted */
+#define MBEDTLS_SSL_RENEGOTIATION_PENDING       3   /* Requested (server only) */
+
+/*
+ * DTLS retransmission states, see RFC 6347 4.2.4
+ *
+ * The SENDING state is merged in PREPARING for initial sends,
+ * but is distinct for resends.
+ *
+ * Note: initial state is wrong for server, but is not used anyway.
+ */
+#define MBEDTLS_SSL_RETRANS_PREPARING       0
+#define MBEDTLS_SSL_RETRANS_SENDING         1
+#define MBEDTLS_SSL_RETRANS_WAITING         2
+#define MBEDTLS_SSL_RETRANS_FINISHED        3
+
+/*
+ * Allow extra bytes for record, authentication and encryption overhead:
+ * counter (8) + header (5) + IV(16) + MAC (16-48) + padding (0-256)
+ * and allow for a maximum of 1024 of compression expansion if
+ * enabled.
+ */
+#if defined(MBEDTLS_ZLIB_SUPPORT)
+#define MBEDTLS_SSL_COMPRESSION_ADD          1024
+#else
+#define MBEDTLS_SSL_COMPRESSION_ADD             0
+#endif
+
+#if defined(MBEDTLS_ARC4_C) || defined(MBEDTLS_CIPHER_MODE_CBC)
+/* Ciphersuites using HMAC */
+#if defined(MBEDTLS_SHA512_C)
+#define MBEDTLS_SSL_MAC_ADD                 48  /* SHA-384 used for HMAC */
+#elif defined(MBEDTLS_SHA256_C)
+#define MBEDTLS_SSL_MAC_ADD                 32  /* SHA-256 used for HMAC */
+#else
+#define MBEDTLS_SSL_MAC_ADD                 20  /* SHA-1   used for HMAC */
+#endif
+#else
+/* AEAD ciphersuites: GCM and CCM use a 128 bits tag */
+#define MBEDTLS_SSL_MAC_ADD                 16
+#endif
+
+#if defined(MBEDTLS_CIPHER_MODE_CBC)
+#define MBEDTLS_SSL_PADDING_ADD            256
+#else
+#define MBEDTLS_SSL_PADDING_ADD              0
+#endif
+
+#define MBEDTLS_SSL_BUFFER_LEN  ( MBEDTLS_SSL_MAX_CONTENT_LEN               \
+                        + MBEDTLS_SSL_COMPRESSION_ADD               \
+                        + 29 /* counter + header + IV */    \
+                        + MBEDTLS_SSL_MAC_ADD                       \
+                        + MBEDTLS_SSL_PADDING_ADD                   \
+                        )
+
+/*
+ * TLS extension flags (for extensions with outgoing ServerHello content
+ * that need it (e.g. for RENEGOTIATION_INFO the server already knows because
+ * of state of the renegotiation flag, so no indicator is required)
+ */
+#define MBEDTLS_TLS_EXT_SUPPORTED_POINT_FORMATS_PRESENT (1 << 0)
+#define MBEDTLS_TLS_EXT_ECJPAKE_KKPP_OK                 (1 << 1)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * This structure contains the parameters only needed during handshake.
+ */
+struct mbedtls_ssl_handshake_params
+{
+    /*
+     * Handshake specific crypto variables
+     */
+    int sig_alg;                        /*!<  Hash algorithm for signature   */
+    int verify_sig_alg;                 /*!<  Signature algorithm for verify */
+#if defined(MBEDTLS_DHM_C)
+    mbedtls_dhm_context dhm_ctx;                /*!<  DHM key exchange        */
+#endif
+#if defined(MBEDTLS_ECDH_C)
+    mbedtls_ecdh_context ecdh_ctx;              /*!<  ECDH key exchange       */
+#endif
+#if defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED)
+    mbedtls_ecjpake_context ecjpake_ctx;        /*!< EC J-PAKE key exchange */
+#if defined(MBEDTLS_SSL_CLI_C)
+    unsigned char *ecjpake_cache;               /*!< Cache for ClientHello ext */
+    size_t ecjpake_cache_len;                   /*!< Length of cached data */
+#endif
+#endif
+#if defined(MBEDTLS_ECDH_C) || defined(MBEDTLS_ECDSA_C) || \
+    defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED)
+    const mbedtls_ecp_curve_info **curves;      /*!<  Supported elliptic curves */
+#endif
+#if defined(MBEDTLS_KEY_EXCHANGE__SOME__PSK_ENABLED)
+    unsigned char *psk;                 /*!<  PSK from the callback         */
+    size_t psk_len;                     /*!<  Length of PSK from callback   */
+#endif
+#if defined(MBEDTLS_X509_CRT_PARSE_C)
+    mbedtls_ssl_key_cert *key_cert;     /*!< chosen key/cert pair (server)  */
+#if defined(MBEDTLS_SSL_SERVER_NAME_INDICATION)
+    int sni_authmode;                   /*!< authmode from SNI callback     */
+    mbedtls_ssl_key_cert *sni_key_cert; /*!< key/cert list from SNI         */
+    mbedtls_x509_crt *sni_ca_chain;     /*!< trusted CAs from SNI callback  */
+    mbedtls_x509_crl *sni_ca_crl;       /*!< trusted CAs CRLs from SNI      */
+#endif
+#endif /* MBEDTLS_X509_CRT_PARSE_C */
+#if defined(MBEDTLS_SSL_PROTO_DTLS)
+    unsigned int out_msg_seq;           /*!<  Outgoing handshake sequence number */
+    unsigned int in_msg_seq;            /*!<  Incoming handshake sequence number */
+
+    unsigned char *verify_cookie;       /*!<  Cli: HelloVerifyRequest cookie
+                                              Srv: unused                    */
+    unsigned char verify_cookie_len;    /*!<  Cli: cookie length
+                                              Srv: flag for sending a cookie */
+
+    unsigned char *hs_msg;              /*!<  Reassembled handshake message  */
+
+    uint32_t retransmit_timeout;        /*!<  Current value of timeout       */
+    unsigned char retransmit_state;     /*!<  Retransmission state           */
+    mbedtls_ssl_flight_item *flight;            /*!<  Current outgoing flight        */
+    mbedtls_ssl_flight_item *cur_msg;           /*!<  Current message in flight      */
+    unsigned int in_flight_start_seq;   /*!<  Minimum message sequence in the
+                                              flight being received          */
+    mbedtls_ssl_transform *alt_transform_out;   /*!<  Alternative transform for
+                                              resending messages             */
+    unsigned char alt_out_ctr[8];       /*!<  Alternative record epoch/counter
+                                              for resending messages         */
+#endif
+
+    /*
+     * Checksum contexts
+     */
+#if defined(MBEDTLS_SSL_PROTO_SSL3) || defined(MBEDTLS_SSL_PROTO_TLS1) || \
+    defined(MBEDTLS_SSL_PROTO_TLS1_1)
+       mbedtls_md5_context fin_md5;
+      mbedtls_sha1_context fin_sha1;
+#endif
+#if defined(MBEDTLS_SSL_PROTO_TLS1_2)
+#if defined(MBEDTLS_SHA256_C)
+    mbedtls_sha256_context fin_sha256;
+#endif
+#if defined(MBEDTLS_SHA512_C)
+    mbedtls_sha512_context fin_sha512;
+#endif
+#endif /* MBEDTLS_SSL_PROTO_TLS1_2 */
+
+    void (*update_checksum)(mbedtls_ssl_context *, const unsigned char *, size_t);
+    void (*calc_verify)(mbedtls_ssl_context *, unsigned char *);
+    void (*calc_finished)(mbedtls_ssl_context *, unsigned char *, int);
+    int  (*tls_prf)(const unsigned char *, size_t, const char *,
+                    const unsigned char *, size_t,
+                    unsigned char *, size_t);
+
+    size_t pmslen;                      /*!<  premaster length        */
+
+    unsigned char randbytes[64];        /*!<  random bytes            */
+    unsigned char premaster[MBEDTLS_PREMASTER_SIZE];
+                                        /*!<  premaster secret        */
+
+    int resume;                         /*!<  session resume indicator*/
+    int max_major_ver;                  /*!< max. major version client*/
+    int max_minor_ver;                  /*!< max. minor version client*/
+    int cli_exts;                       /*!< client extension presence*/
+
+#if defined(MBEDTLS_SSL_SESSION_TICKETS)
+    int new_session_ticket;             /*!< use NewSessionTicket?    */
+#endif /* MBEDTLS_SSL_SESSION_TICKETS */
+#if defined(MBEDTLS_SSL_EXTENDED_MASTER_SECRET)
+    int extended_ms;                    /*!< use Extended Master Secret? */
+#endif
+};
+
+/*
+ * This structure contains a full set of runtime transform parameters
+ * either in negotiation or active.
+ */
+struct mbedtls_ssl_transform
+{
+    /*
+     * Session specific crypto layer
+     */
+    const mbedtls_ssl_ciphersuite_t *ciphersuite_info;
+                                        /*!<  Chosen cipersuite_info  */
+    unsigned int keylen;                /*!<  symmetric key length (bytes)  */
+    size_t minlen;                      /*!<  min. ciphertext length  */
+    size_t ivlen;                       /*!<  IV length               */
+    size_t fixed_ivlen;                 /*!<  Fixed part of IV (AEAD) */
+    size_t maclen;                      /*!<  MAC length              */
+
+    unsigned char iv_enc[16];           /*!<  IV (encryption)         */
+    unsigned char iv_dec[16];           /*!<  IV (decryption)         */
+
+#if defined(MBEDTLS_SSL_PROTO_SSL3)
+    /* Needed only for SSL v3.0 secret */
+    unsigned char mac_enc[20];          /*!<  SSL v3.0 secret (enc)   */
+    unsigned char mac_dec[20];          /*!<  SSL v3.0 secret (dec)   */
+#endif /* MBEDTLS_SSL_PROTO_SSL3 */
+
+    mbedtls_md_context_t md_ctx_enc;            /*!<  MAC (encryption)        */
+    mbedtls_md_context_t md_ctx_dec;            /*!<  MAC (decryption)        */
+
+    mbedtls_cipher_context_t cipher_ctx_enc;    /*!<  encryption context      */
+    mbedtls_cipher_context_t cipher_ctx_dec;    /*!<  decryption context      */
+
+    /*
+     * Session specific compression layer
+     */
+#if defined(MBEDTLS_ZLIB_SUPPORT)
+    z_stream ctx_deflate;               /*!<  compression context     */
+    z_stream ctx_inflate;               /*!<  decompression context   */
+#endif
+};
+
+#if defined(MBEDTLS_X509_CRT_PARSE_C)
+/*
+ * List of certificate + private key pairs
+ */
+struct mbedtls_ssl_key_cert
+{
+    mbedtls_x509_crt *cert;                 /*!< cert                       */
+    mbedtls_pk_context *key;                /*!< private key                */
+    mbedtls_ssl_key_cert *next;             /*!< next key/cert pair         */
+};
+#endif /* MBEDTLS_X509_CRT_PARSE_C */
+
+#if defined(MBEDTLS_SSL_PROTO_DTLS)
+/*
+ * List of handshake messages kept around for resending
+ */
+struct mbedtls_ssl_flight_item
+{
+    unsigned char *p;       /*!< message, including handshake headers   */
+    size_t len;             /*!< length of p                            */
+    unsigned char type;     /*!< type of the message: handshake or CCS  */
+    mbedtls_ssl_flight_item *next;  /*!< next handshake message(s)              */
+};
+#endif /* MBEDTLS_SSL_PROTO_DTLS */
+
+
+/**
+ * \brief           Free referenced items in an SSL transform context and clear
+ *                  memory
+ *
+ * \param transform SSL transform context
+ */
+void mbedtls_ssl_transform_free( mbedtls_ssl_transform *transform );
+
+/**
+ * \brief           Free referenced items in an SSL handshake context and clear
+ *                  memory
+ *
+ * \param handshake SSL handshake context
+ */
+void mbedtls_ssl_handshake_free( mbedtls_ssl_handshake_params *handshake );
+
+int mbedtls_ssl_handshake_client_step( mbedtls_ssl_context *ssl );
+int mbedtls_ssl_handshake_server_step( mbedtls_ssl_context *ssl );
+void mbedtls_ssl_handshake_wrapup( mbedtls_ssl_context *ssl );
+
+int mbedtls_ssl_send_fatal_handshake_failure( mbedtls_ssl_context *ssl );
+
+void mbedtls_ssl_reset_checksum( mbedtls_ssl_context *ssl );
+int mbedtls_ssl_derive_keys( mbedtls_ssl_context *ssl );
+
+int mbedtls_ssl_read_record( mbedtls_ssl_context *ssl );
+int mbedtls_ssl_fetch_input( mbedtls_ssl_context *ssl, size_t nb_want );
+
+int mbedtls_ssl_write_record( mbedtls_ssl_context *ssl );
+int mbedtls_ssl_flush_output( mbedtls_ssl_context *ssl );
+
+int mbedtls_ssl_parse_certificate( mbedtls_ssl_context *ssl );
+int mbedtls_ssl_write_certificate( mbedtls_ssl_context *ssl );
+
+int mbedtls_ssl_parse_change_cipher_spec( mbedtls_ssl_context *ssl );
+int mbedtls_ssl_write_change_cipher_spec( mbedtls_ssl_context *ssl );
+
+int mbedtls_ssl_parse_finished( mbedtls_ssl_context *ssl );
+int mbedtls_ssl_write_finished( mbedtls_ssl_context *ssl );
+
+void mbedtls_ssl_optimize_checksum( mbedtls_ssl_context *ssl,
+                            const mbedtls_ssl_ciphersuite_t *ciphersuite_info );
+
+#if defined(MBEDTLS_KEY_EXCHANGE__SOME__PSK_ENABLED)
+int mbedtls_ssl_psk_derive_premaster( mbedtls_ssl_context *ssl, mbedtls_key_exchange_type_t key_ex );
+#endif
+
+#if defined(MBEDTLS_PK_C)
+unsigned char mbedtls_ssl_sig_from_pk( mbedtls_pk_context *pk );
+mbedtls_pk_type_t mbedtls_ssl_pk_alg_from_sig( unsigned char sig );
+#endif
+
+mbedtls_md_type_t mbedtls_ssl_md_alg_from_hash( unsigned char hash );
+unsigned char mbedtls_ssl_hash_from_md_alg( int md );
+
+#if defined(MBEDTLS_ECP_C)
+int mbedtls_ssl_check_curve( const mbedtls_ssl_context *ssl, mbedtls_ecp_group_id grp_id );
+#endif
+
+#if defined(MBEDTLS_KEY_EXCHANGE__WITH_CERT__ENABLED)
+int mbedtls_ssl_check_sig_hash( const mbedtls_ssl_context *ssl,
+                                mbedtls_md_type_t md );
+#endif
+
+#if defined(MBEDTLS_X509_CRT_PARSE_C)
+static inline mbedtls_pk_context *mbedtls_ssl_own_key( mbedtls_ssl_context *ssl )
+{
+    mbedtls_ssl_key_cert *key_cert;
+
+    if( ssl->handshake != NULL && ssl->handshake->key_cert != NULL )
+        key_cert = ssl->handshake->key_cert;
+    else
+        key_cert = ssl->conf->key_cert;
+
+    return( key_cert == NULL ? NULL : key_cert->key );
+}
+
+static inline mbedtls_x509_crt *mbedtls_ssl_own_cert( mbedtls_ssl_context *ssl )
+{
+    mbedtls_ssl_key_cert *key_cert;
+
+    if( ssl->handshake != NULL && ssl->handshake->key_cert != NULL )
+        key_cert = ssl->handshake->key_cert;
+    else
+        key_cert = ssl->conf->key_cert;
+
+    return( key_cert == NULL ? NULL : key_cert->cert );
+}
+
+/*
+ * Check usage of a certificate wrt extensions:
+ * keyUsage, extendedKeyUsage (later), and nSCertType (later).
+ *
+ * Warning: cert_endpoint is the endpoint of the cert (ie, of our peer when we
+ * check a cert we received from them)!
+ *
+ * Return 0 if everything is OK, -1 if not.
+ */
+int mbedtls_ssl_check_cert_usage( const mbedtls_x509_crt *cert,
+                          const mbedtls_ssl_ciphersuite_t *ciphersuite,
+                          int cert_endpoint,
+                          uint32_t *flags );
+#endif /* MBEDTLS_X509_CRT_PARSE_C */
+
+void mbedtls_ssl_write_version( int major, int minor, int transport,
+                        unsigned char ver[2] );
+void mbedtls_ssl_read_version( int *major, int *minor, int transport,
+                       const unsigned char ver[2] );
+
+static inline size_t mbedtls_ssl_hdr_len( const mbedtls_ssl_context *ssl )
+{
+#if defined(MBEDTLS_SSL_PROTO_DTLS)
+    if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM )
+        return( 13 );
+#else
+    ((void) ssl);
+#endif
+    return( 5 );
+}
+
+static inline size_t mbedtls_ssl_hs_hdr_len( const mbedtls_ssl_context *ssl )
+{
+#if defined(MBEDTLS_SSL_PROTO_DTLS)
+    if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM )
+        return( 12 );
+#else
+    ((void) ssl);
+#endif
+    return( 4 );
+}
+
+#if defined(MBEDTLS_SSL_PROTO_DTLS)
+void mbedtls_ssl_send_flight_completed( mbedtls_ssl_context *ssl );
+void mbedtls_ssl_recv_flight_completed( mbedtls_ssl_context *ssl );
+int mbedtls_ssl_resend( mbedtls_ssl_context *ssl );
+#endif
+
+/* Visible for testing purposes only */
+#if defined(MBEDTLS_SSL_DTLS_ANTI_REPLAY)
+int mbedtls_ssl_dtls_replay_check( mbedtls_ssl_context *ssl );
+void mbedtls_ssl_dtls_replay_update( mbedtls_ssl_context *ssl );
+#endif
+
+/* constant-time buffer comparison */
+static inline int mbedtls_ssl_safer_memcmp( const void *a, const void *b, size_t n )
+{
+    size_t i;
+    const unsigned char *A = (const unsigned char *) a;
+    const unsigned char *B = (const unsigned char *) b;
+    unsigned char diff = 0;
+
+    for( i = 0; i < n; i++ )
+        diff |= A[i] ^ B[i];
+
+    return( diff );
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ssl_internal.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/ssl_ticket.h b/tools/sdk/include/mbedtls/mbedtls/ssl_ticket.h
new file mode 100644
index 00000000..7c6bc61b
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/ssl_ticket.h
@@ -0,0 +1,135 @@
+/**
+ * \file ssl_ticket.h
+ *
+ * \brief TLS server ticket callbacks implementation
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_SSL_TICKET_H
+#define MBEDTLS_SSL_TICKET_H
+
+/*
+ * This implementation of the session ticket callbacks includes key
+ * management, rotating the keys periodically in order to preserve forward
+ * secrecy, when MBEDTLS_HAVE_TIME is defined.
+ */
+
+#include "ssl.h"
+#include "cipher.h"
+
+#if defined(MBEDTLS_THREADING_C)
+#include "threading.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief   Information for session ticket protection
+ */
+typedef struct
+{
+    unsigned char name[4];          /*!< random key identifier              */
+    uint32_t generation_time;       /*!< key generation timestamp (seconds) */
+    mbedtls_cipher_context_t ctx;   /*!< context for auth enc/decryption    */
+}
+mbedtls_ssl_ticket_key;
+
+/**
+ * \brief   Context for session ticket handling functions
+ */
+typedef struct
+{
+    mbedtls_ssl_ticket_key keys[2]; /*!< ticket protection keys             */
+    unsigned char active;           /*!< index of the currently active key  */
+
+    uint32_t ticket_lifetime;       /*!< lifetime of tickets in seconds     */
+
+    /** Callback for getting (pseudo-)random numbers                        */
+    int  (*f_rng)(void *, unsigned char *, size_t);
+    void *p_rng;                    /*!< context for the RNG function       */
+
+#if defined(MBEDTLS_THREADING_C)
+    mbedtls_threading_mutex_t mutex;
+#endif
+}
+mbedtls_ssl_ticket_context;
+
+/**
+ * \brief           Initialize a ticket context.
+ *                  (Just make it ready for mbedtls_ssl_ticket_setup()
+ *                  or mbedtls_ssl_ticket_free().)
+ *
+ * \param ctx       Context to be initialized
+ */
+void mbedtls_ssl_ticket_init( mbedtls_ssl_ticket_context *ctx );
+
+/**
+ * \brief           Prepare context to be actually used
+ *
+ * \param ctx       Context to be set up
+ * \param f_rng     RNG callback function
+ * \param p_rng     RNG callback context
+ * \param cipher    AEAD cipher to use for ticket protection.
+ *                  Recommended value: MBEDTLS_CIPHER_AES_256_GCM.
+ * \param lifetime  Tickets lifetime in seconds
+ *                  Recommended value: 86400 (one day).
+ *
+ * \note            It is highly recommended to select a cipher that is at
+ *                  least as strong as the the strongest ciphersuite
+ *                  supported. Usually that means a 256-bit key.
+ *
+ * \note            The lifetime of the keys is twice the lifetime of tickets.
+ *                  It is recommended to pick a reasonnable lifetime so as not
+ *                  to negate the benefits of forward secrecy.
+ *
+ * \return          0 if successful,
+ *                  or a specific MBEDTLS_ERR_XXX error code
+ */
+int mbedtls_ssl_ticket_setup( mbedtls_ssl_ticket_context *ctx,
+    int (*f_rng)(void *, unsigned char *, size_t), void *p_rng,
+    mbedtls_cipher_type_t cipher,
+    uint32_t lifetime );
+
+/**
+ * \brief           Implementation of the ticket write callback
+ *
+ * \note            See \c mbedlts_ssl_ticket_write_t for description
+ */
+mbedtls_ssl_ticket_write_t mbedtls_ssl_ticket_write;
+
+/**
+ * \brief           Implementation of the ticket parse callback
+ *
+ * \note            See \c mbedlts_ssl_ticket_parse_t for description
+ */
+mbedtls_ssl_ticket_parse_t mbedtls_ssl_ticket_parse;
+
+/**
+ * \brief           Free a context's content and zeroize it.
+ *
+ * \param ctx       Context to be cleaned up
+ */
+void mbedtls_ssl_ticket_free( mbedtls_ssl_ticket_context *ctx );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ssl_ticket.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/threading.h b/tools/sdk/include/mbedtls/mbedtls/threading.h
new file mode 100644
index 00000000..b0c34ecc
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/threading.h
@@ -0,0 +1,106 @@
+/**
+ * \file threading.h
+ *
+ * \brief Threading abstraction layer
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_THREADING_H
+#define MBEDTLS_THREADING_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define MBEDTLS_ERR_THREADING_FEATURE_UNAVAILABLE         -0x001A  /**< The selected feature is not available. */
+#define MBEDTLS_ERR_THREADING_BAD_INPUT_DATA              -0x001C  /**< Bad input parameters to function. */
+#define MBEDTLS_ERR_THREADING_MUTEX_ERROR                 -0x001E  /**< Locking / unlocking / free failed with error code. */
+
+#if defined(MBEDTLS_THREADING_PTHREAD)
+#include 
+typedef struct
+{
+    pthread_mutex_t mutex;
+    char is_valid;
+} mbedtls_threading_mutex_t;
+#endif
+
+#if defined(MBEDTLS_THREADING_ALT)
+/* You should define the mbedtls_threading_mutex_t type in your header */
+#include "threading_alt.h"
+
+/**
+ * \brief           Set your alternate threading implementation function
+ *                  pointers and initialize global mutexes. If used, this
+ *                  function must be called once in the main thread before any
+ *                  other mbed TLS function is called, and
+ *                  mbedtls_threading_free_alt() must be called once in the main
+ *                  thread after all other mbed TLS functions.
+ *
+ * \note            mutex_init() and mutex_free() don't return a status code.
+ *                  If mutex_init() fails, it should leave its argument (the
+ *                  mutex) in a state such that mutex_lock() will fail when
+ *                  called with this argument.
+ *
+ * \param mutex_init    the init function implementation
+ * \param mutex_free    the free function implementation
+ * \param mutex_lock    the lock function implementation
+ * \param mutex_unlock  the unlock function implementation
+ */
+void mbedtls_threading_set_alt( void (*mutex_init)( mbedtls_threading_mutex_t * ),
+                       void (*mutex_free)( mbedtls_threading_mutex_t * ),
+                       int (*mutex_lock)( mbedtls_threading_mutex_t * ),
+                       int (*mutex_unlock)( mbedtls_threading_mutex_t * ) );
+
+/**
+ * \brief               Free global mutexes.
+ */
+void mbedtls_threading_free_alt( void );
+#endif /* MBEDTLS_THREADING_ALT */
+
+#if defined(MBEDTLS_THREADING_C)
+/*
+ * The function pointers for mutex_init, mutex_free, mutex_ and mutex_unlock
+ *
+ * All these functions are expected to work or the result will be undefined.
+ */
+extern void (*mbedtls_mutex_init)( mbedtls_threading_mutex_t *mutex );
+extern void (*mbedtls_mutex_free)( mbedtls_threading_mutex_t *mutex );
+extern int (*mbedtls_mutex_lock)( mbedtls_threading_mutex_t *mutex );
+extern int (*mbedtls_mutex_unlock)( mbedtls_threading_mutex_t *mutex );
+
+/*
+ * Global mutexes
+ */
+extern mbedtls_threading_mutex_t mbedtls_threading_readdir_mutex;
+extern mbedtls_threading_mutex_t mbedtls_threading_gmtime_mutex;
+#endif /* MBEDTLS_THREADING_C */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* threading.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/timing.h b/tools/sdk/include/mbedtls/mbedtls/timing.h
new file mode 100644
index 00000000..ae7a713e
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/timing.h
@@ -0,0 +1,141 @@
+/**
+ * \file timing.h
+ *
+ * \brief Portable interface to the CPU cycle counter
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_TIMING_H
+#define MBEDTLS_TIMING_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#if !defined(MBEDTLS_TIMING_ALT)
+// Regular implementation
+//
+
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          timer structure
+ */
+struct mbedtls_timing_hr_time
+{
+    unsigned char opaque[32];
+};
+
+/**
+ * \brief          Context for mbedtls_timing_set/get_delay()
+ */
+typedef struct
+{
+    struct mbedtls_timing_hr_time   timer;
+    uint32_t                        int_ms;
+    uint32_t                        fin_ms;
+} mbedtls_timing_delay_context;
+
+extern volatile int mbedtls_timing_alarmed;
+
+/**
+ * \brief          Return the CPU cycle counter value
+ *
+ * \warning        This is only a best effort! Do not rely on this!
+ *                 In particular, it is known to be unreliable on virtual
+ *                 machines.
+ */
+unsigned long mbedtls_timing_hardclock( void );
+
+/**
+ * \brief          Return the elapsed time in milliseconds
+ *
+ * \param val      points to a timer structure
+ * \param reset    if set to 1, the timer is restarted
+ */
+unsigned long mbedtls_timing_get_timer( struct mbedtls_timing_hr_time *val, int reset );
+
+/**
+ * \brief          Setup an alarm clock
+ *
+ * \param seconds  delay before the "mbedtls_timing_alarmed" flag is set
+ *
+ * \warning        Only one alarm at a time  is supported. In a threaded
+ *                 context, this means one for the whole process, not one per
+ *                 thread.
+ */
+void mbedtls_set_alarm( int seconds );
+
+/**
+ * \brief          Set a pair of delays to watch
+ *                 (See \c mbedtls_timing_get_delay().)
+ *
+ * \param data     Pointer to timing data
+ *                 Must point to a valid \c mbedtls_timing_delay_context struct.
+ * \param int_ms   First (intermediate) delay in milliseconds.
+ * \param fin_ms   Second (final) delay in milliseconds.
+ *                 Pass 0 to cancel the current delay.
+ */
+void mbedtls_timing_set_delay( void *data, uint32_t int_ms, uint32_t fin_ms );
+
+/**
+ * \brief          Get the status of delays
+ *                 (Memory helper: number of delays passed.)
+ *
+ * \param data     Pointer to timing data
+ *                 Must point to a valid \c mbedtls_timing_delay_context struct.
+ *
+ * \return         -1 if cancelled (fin_ms = 0)
+ *                  0 if none of the delays are passed,
+ *                  1 if only the intermediate delay is passed,
+ *                  2 if the final delay is passed.
+ */
+int mbedtls_timing_get_delay( void *data );
+
+#ifdef __cplusplus
+}
+#endif
+
+#else  /* MBEDTLS_TIMING_ALT */
+#include "timing_alt.h"
+#endif /* MBEDTLS_TIMING_ALT */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(MBEDTLS_SELF_TEST)
+/**
+ * \brief          Checkup routine
+ *
+ * \return         0 if successful, or 1 if a test failed
+ */
+int mbedtls_timing_self_test( int verbose );
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* timing.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/version.h b/tools/sdk/include/mbedtls/mbedtls/version.h
new file mode 100644
index 00000000..b40aa510
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/version.h
@@ -0,0 +1,111 @@
+/**
+ * \file version.h
+ *
+ * \brief Run-time version information
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+/*
+ * This set of compile-time defines and run-time variables can be used to
+ * determine the version number of the mbed TLS library used.
+ */
+#ifndef MBEDTLS_VERSION_H
+#define MBEDTLS_VERSION_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+/**
+ * The version number x.y.z is split into three parts.
+ * Major, Minor, Patchlevel
+ */
+#define MBEDTLS_VERSION_MAJOR  2
+#define MBEDTLS_VERSION_MINOR  3
+#define MBEDTLS_VERSION_PATCH  0
+
+/**
+ * The single version number has the following structure:
+ *    MMNNPP00
+ *    Major version | Minor version | Patch version
+ */
+#define MBEDTLS_VERSION_NUMBER         0x02030000
+#define MBEDTLS_VERSION_STRING         "2.3.0"
+#define MBEDTLS_VERSION_STRING_FULL    "mbed TLS 2.3.0"
+
+#if defined(MBEDTLS_VERSION_C)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Get the version number.
+ *
+ * \return          The constructed version number in the format
+ *                  MMNNPP00 (Major, Minor, Patch).
+ */
+unsigned int mbedtls_version_get_number( void );
+
+/**
+ * Get the version string ("x.y.z").
+ *
+ * \param string    The string that will receive the value.
+ *                  (Should be at least 9 bytes in size)
+ */
+void mbedtls_version_get_string( char *string );
+
+/**
+ * Get the full version string ("mbed TLS x.y.z").
+ *
+ * \param string    The string that will receive the value. The mbed TLS version
+ *                  string will use 18 bytes AT MOST including a terminating
+ *                  null byte.
+ *                  (So the buffer should be at least 18 bytes to receive this
+ *                  version string).
+ */
+void mbedtls_version_get_string_full( char *string );
+
+/**
+ * \brief           Check if support for a feature was compiled into this
+ *                  mbed TLS binary. This allows you to see at runtime if the
+ *                  library was for instance compiled with or without
+ *                  Multi-threading support.
+ *
+ * \note            only checks against defines in the sections "System
+ *                  support", "mbed TLS modules" and "mbed TLS feature
+ *                  support" in config.h
+ *
+ * \param feature   The string for the define to check (e.g. "MBEDTLS_AES_C")
+ *
+ * \return          0 if the feature is present,
+ *                  -1 if the feature is not present and
+ *                  -2 if support for feature checking as a whole was not
+ *                  compiled in.
+ */
+int mbedtls_version_check_feature( const char *feature );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MBEDTLS_VERSION_C */
+
+#endif /* version.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/x509.h b/tools/sdk/include/mbedtls/mbedtls/x509.h
new file mode 100644
index 00000000..54dac166
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/x509.h
@@ -0,0 +1,331 @@
+/**
+ * \file x509.h
+ *
+ * \brief X.509 generic defines and structures
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_X509_H
+#define MBEDTLS_X509_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#include "asn1.h"
+#include "pk.h"
+
+#if defined(MBEDTLS_RSA_C)
+#include "rsa.h"
+#endif
+
+/**
+ * \addtogroup x509_module
+ * \{
+ */
+
+#if !defined(MBEDTLS_X509_MAX_INTERMEDIATE_CA)
+/**
+ * Maximum number of intermediate CAs in a verification chain.
+ * That is, maximum length of the chain, excluding the end-entity certificate
+ * and the trusted root certificate.
+ *
+ * Set this to a low value to prevent an adversary from making you waste
+ * resources verifying an overlong certificate chain.
+ */
+#define MBEDTLS_X509_MAX_INTERMEDIATE_CA   8
+#endif
+
+/**
+ * \name X509 Error codes
+ * \{
+ */
+#define MBEDTLS_ERR_X509_FEATURE_UNAVAILABLE              -0x2080  /**< Unavailable feature, e.g. RSA hashing/encryption combination. */
+#define MBEDTLS_ERR_X509_UNKNOWN_OID                      -0x2100  /**< Requested OID is unknown. */
+#define MBEDTLS_ERR_X509_INVALID_FORMAT                   -0x2180  /**< The CRT/CRL/CSR format is invalid, e.g. different type expected. */
+#define MBEDTLS_ERR_X509_INVALID_VERSION                  -0x2200  /**< The CRT/CRL/CSR version element is invalid. */
+#define MBEDTLS_ERR_X509_INVALID_SERIAL                   -0x2280  /**< The serial tag or value is invalid. */
+#define MBEDTLS_ERR_X509_INVALID_ALG                      -0x2300  /**< The algorithm tag or value is invalid. */
+#define MBEDTLS_ERR_X509_INVALID_NAME                     -0x2380  /**< The name tag or value is invalid. */
+#define MBEDTLS_ERR_X509_INVALID_DATE                     -0x2400  /**< The date tag or value is invalid. */
+#define MBEDTLS_ERR_X509_INVALID_SIGNATURE                -0x2480  /**< The signature tag or value invalid. */
+#define MBEDTLS_ERR_X509_INVALID_EXTENSIONS               -0x2500  /**< The extension tag or value is invalid. */
+#define MBEDTLS_ERR_X509_UNKNOWN_VERSION                  -0x2580  /**< CRT/CRL/CSR has an unsupported version number. */
+#define MBEDTLS_ERR_X509_UNKNOWN_SIG_ALG                  -0x2600  /**< Signature algorithm (oid) is unsupported. */
+#define MBEDTLS_ERR_X509_SIG_MISMATCH                     -0x2680  /**< Signature algorithms do not match. (see \c ::mbedtls_x509_crt sig_oid) */
+#define MBEDTLS_ERR_X509_CERT_VERIFY_FAILED               -0x2700  /**< Certificate verification failed, e.g. CRL, CA or signature check failed. */
+#define MBEDTLS_ERR_X509_CERT_UNKNOWN_FORMAT              -0x2780  /**< Format not recognized as DER or PEM. */
+#define MBEDTLS_ERR_X509_BAD_INPUT_DATA                   -0x2800  /**< Input invalid. */
+#define MBEDTLS_ERR_X509_ALLOC_FAILED                     -0x2880  /**< Allocation of memory failed. */
+#define MBEDTLS_ERR_X509_FILE_IO_ERROR                    -0x2900  /**< Read/write of file failed. */
+#define MBEDTLS_ERR_X509_BUFFER_TOO_SMALL                 -0x2980  /**< Destination buffer is too small. */
+/* \} name */
+
+/**
+ * \name X509 Verify codes
+ * \{
+ */
+/* Reminder: update x509_crt_verify_strings[] in library/x509_crt.c */
+#define MBEDTLS_X509_BADCERT_EXPIRED             0x01  /**< The certificate validity has expired. */
+#define MBEDTLS_X509_BADCERT_REVOKED             0x02  /**< The certificate has been revoked (is on a CRL). */
+#define MBEDTLS_X509_BADCERT_CN_MISMATCH         0x04  /**< The certificate Common Name (CN) does not match with the expected CN. */
+#define MBEDTLS_X509_BADCERT_NOT_TRUSTED         0x08  /**< The certificate is not correctly signed by the trusted CA. */
+#define MBEDTLS_X509_BADCRL_NOT_TRUSTED          0x10  /**< The CRL is not correctly signed by the trusted CA. */
+#define MBEDTLS_X509_BADCRL_EXPIRED              0x20  /**< The CRL is expired. */
+#define MBEDTLS_X509_BADCERT_MISSING             0x40  /**< Certificate was missing. */
+#define MBEDTLS_X509_BADCERT_SKIP_VERIFY         0x80  /**< Certificate verification was skipped. */
+#define MBEDTLS_X509_BADCERT_OTHER             0x0100  /**< Other reason (can be used by verify callback) */
+#define MBEDTLS_X509_BADCERT_FUTURE            0x0200  /**< The certificate validity starts in the future. */
+#define MBEDTLS_X509_BADCRL_FUTURE             0x0400  /**< The CRL is from the future */
+#define MBEDTLS_X509_BADCERT_KEY_USAGE         0x0800  /**< Usage does not match the keyUsage extension. */
+#define MBEDTLS_X509_BADCERT_EXT_KEY_USAGE     0x1000  /**< Usage does not match the extendedKeyUsage extension. */
+#define MBEDTLS_X509_BADCERT_NS_CERT_TYPE      0x2000  /**< Usage does not match the nsCertType extension. */
+#define MBEDTLS_X509_BADCERT_BAD_MD            0x4000  /**< The certificate is signed with an unacceptable hash. */
+#define MBEDTLS_X509_BADCERT_BAD_PK            0x8000  /**< The certificate is signed with an unacceptable PK alg (eg RSA vs ECDSA). */
+#define MBEDTLS_X509_BADCERT_BAD_KEY         0x010000  /**< The certificate is signed with an unacceptable key (eg bad curve, RSA too short). */
+#define MBEDTLS_X509_BADCRL_BAD_MD           0x020000  /**< The CRL is signed with an unacceptable hash. */
+#define MBEDTLS_X509_BADCRL_BAD_PK           0x040000  /**< The CRL is signed with an unacceptable PK alg (eg RSA vs ECDSA). */
+#define MBEDTLS_X509_BADCRL_BAD_KEY          0x080000  /**< The CRL is signed with an unacceptable key (eg bad curve, RSA too short). */
+
+/* \} name */
+/* \} addtogroup x509_module */
+
+/*
+ * X.509 v3 Key Usage Extension flags
+ * Reminder: update x509_info_key_usage() when adding new flags.
+ */
+#define MBEDTLS_X509_KU_DIGITAL_SIGNATURE            (0x80)  /* bit 0 */
+#define MBEDTLS_X509_KU_NON_REPUDIATION              (0x40)  /* bit 1 */
+#define MBEDTLS_X509_KU_KEY_ENCIPHERMENT             (0x20)  /* bit 2 */
+#define MBEDTLS_X509_KU_DATA_ENCIPHERMENT            (0x10)  /* bit 3 */
+#define MBEDTLS_X509_KU_KEY_AGREEMENT                (0x08)  /* bit 4 */
+#define MBEDTLS_X509_KU_KEY_CERT_SIGN                (0x04)  /* bit 5 */
+#define MBEDTLS_X509_KU_CRL_SIGN                     (0x02)  /* bit 6 */
+#define MBEDTLS_X509_KU_ENCIPHER_ONLY                (0x01)  /* bit 7 */
+#define MBEDTLS_X509_KU_DECIPHER_ONLY              (0x8000)  /* bit 8 */
+
+/*
+ * Netscape certificate types
+ * (http://www.mozilla.org/projects/security/pki/nss/tech-notes/tn3.html)
+ */
+
+#define MBEDTLS_X509_NS_CERT_TYPE_SSL_CLIENT         (0x80)  /* bit 0 */
+#define MBEDTLS_X509_NS_CERT_TYPE_SSL_SERVER         (0x40)  /* bit 1 */
+#define MBEDTLS_X509_NS_CERT_TYPE_EMAIL              (0x20)  /* bit 2 */
+#define MBEDTLS_X509_NS_CERT_TYPE_OBJECT_SIGNING     (0x10)  /* bit 3 */
+#define MBEDTLS_X509_NS_CERT_TYPE_RESERVED           (0x08)  /* bit 4 */
+#define MBEDTLS_X509_NS_CERT_TYPE_SSL_CA             (0x04)  /* bit 5 */
+#define MBEDTLS_X509_NS_CERT_TYPE_EMAIL_CA           (0x02)  /* bit 6 */
+#define MBEDTLS_X509_NS_CERT_TYPE_OBJECT_SIGNING_CA  (0x01)  /* bit 7 */
+
+/*
+ * X.509 extension types
+ *
+ * Comments refer to the status for using certificates. Status can be
+ * different for writing certificates or reading CRLs or CSRs.
+ */
+#define MBEDTLS_X509_EXT_AUTHORITY_KEY_IDENTIFIER    (1 << 0)
+#define MBEDTLS_X509_EXT_SUBJECT_KEY_IDENTIFIER      (1 << 1)
+#define MBEDTLS_X509_EXT_KEY_USAGE                   (1 << 2)
+#define MBEDTLS_X509_EXT_CERTIFICATE_POLICIES        (1 << 3)
+#define MBEDTLS_X509_EXT_POLICY_MAPPINGS             (1 << 4)
+#define MBEDTLS_X509_EXT_SUBJECT_ALT_NAME            (1 << 5)    /* Supported (DNS) */
+#define MBEDTLS_X509_EXT_ISSUER_ALT_NAME             (1 << 6)
+#define MBEDTLS_X509_EXT_SUBJECT_DIRECTORY_ATTRS     (1 << 7)
+#define MBEDTLS_X509_EXT_BASIC_CONSTRAINTS           (1 << 8)    /* Supported */
+#define MBEDTLS_X509_EXT_NAME_CONSTRAINTS            (1 << 9)
+#define MBEDTLS_X509_EXT_POLICY_CONSTRAINTS          (1 << 10)
+#define MBEDTLS_X509_EXT_EXTENDED_KEY_USAGE          (1 << 11)
+#define MBEDTLS_X509_EXT_CRL_DISTRIBUTION_POINTS     (1 << 12)
+#define MBEDTLS_X509_EXT_INIHIBIT_ANYPOLICY          (1 << 13)
+#define MBEDTLS_X509_EXT_FRESHEST_CRL                (1 << 14)
+
+#define MBEDTLS_X509_EXT_NS_CERT_TYPE                (1 << 16)   /* Parsed (and then ?) */
+
+/*
+ * Storage format identifiers
+ * Recognized formats: PEM and DER
+ */
+#define MBEDTLS_X509_FORMAT_DER                 1
+#define MBEDTLS_X509_FORMAT_PEM                 2
+
+#define MBEDTLS_X509_MAX_DN_NAME_SIZE         256 /**< Maximum value size of a DN entry */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup x509_module
+ * \{ */
+
+/**
+ * \name Structures for parsing X.509 certificates, CRLs and CSRs
+ * \{
+ */
+
+/**
+ * Type-length-value structure that allows for ASN1 using DER.
+ */
+typedef mbedtls_asn1_buf mbedtls_x509_buf;
+
+/**
+ * Container for ASN1 bit strings.
+ */
+typedef mbedtls_asn1_bitstring mbedtls_x509_bitstring;
+
+/**
+ * Container for ASN1 named information objects.
+ * It allows for Relative Distinguished Names (e.g. cn=localhost,ou=code,etc.).
+ */
+typedef mbedtls_asn1_named_data mbedtls_x509_name;
+
+/**
+ * Container for a sequence of ASN.1 items
+ */
+typedef mbedtls_asn1_sequence mbedtls_x509_sequence;
+
+/** Container for date and time (precision in seconds). */
+typedef struct mbedtls_x509_time
+{
+    int year, mon, day;         /**< Date. */
+    int hour, min, sec;         /**< Time. */
+}
+mbedtls_x509_time;
+
+/** \} name Structures for parsing X.509 certificates, CRLs and CSRs */
+/** \} addtogroup x509_module */
+
+/**
+ * \brief          Store the certificate DN in printable form into buf;
+ *                 no more than size characters will be written.
+ *
+ * \param buf      Buffer to write to
+ * \param size     Maximum size of buffer
+ * \param dn       The X509 name to represent
+ *
+ * \return         The length of the string written (not including the
+ *                 terminated nul byte), or a negative error code.
+ */
+int mbedtls_x509_dn_gets( char *buf, size_t size, const mbedtls_x509_name *dn );
+
+/**
+ * \brief          Store the certificate serial in printable form into buf;
+ *                 no more than size characters will be written.
+ *
+ * \param buf      Buffer to write to
+ * \param size     Maximum size of buffer
+ * \param serial   The X509 serial to represent
+ *
+ * \return         The length of the string written (not including the
+ *                 terminated nul byte), or a negative error code.
+ */
+int mbedtls_x509_serial_gets( char *buf, size_t size, const mbedtls_x509_buf *serial );
+
+/**
+ * \brief          Check a given mbedtls_x509_time against the system time
+ *                 and tell if it's in the past.
+ *
+ * \note           Intended usage is "if( is_past( valid_to ) ) ERROR".
+ *                 Hence the return value of 1 if on internal errors.
+ *
+ * \param time     mbedtls_x509_time to check
+ *
+ * \return         1 if the given time is in the past or an error occured,
+ *                 0 otherwise.
+ */
+int mbedtls_x509_time_is_past( const mbedtls_x509_time *time );
+
+/**
+ * \brief          Check a given mbedtls_x509_time against the system time
+ *                 and tell if it's in the future.
+ *
+ * \note           Intended usage is "if( is_future( valid_from ) ) ERROR".
+ *                 Hence the return value of 1 if on internal errors.
+ *
+ * \param time     mbedtls_x509_time to check
+ *
+ * \return         1 if the given time is in the future or an error occured,
+ *                 0 otherwise.
+ */
+int mbedtls_x509_time_is_future( const mbedtls_x509_time *time );
+
+/**
+ * \brief          Checkup routine
+ *
+ * \return         0 if successful, or 1 if the test failed
+ */
+int mbedtls_x509_self_test( int verbose );
+
+/*
+ * Internal module functions. You probably do not want to use these unless you
+ * know you do.
+ */
+int mbedtls_x509_get_name( unsigned char **p, const unsigned char *end,
+                   mbedtls_x509_name *cur );
+int mbedtls_x509_get_alg_null( unsigned char **p, const unsigned char *end,
+                       mbedtls_x509_buf *alg );
+int mbedtls_x509_get_alg( unsigned char **p, const unsigned char *end,
+                  mbedtls_x509_buf *alg, mbedtls_x509_buf *params );
+#if defined(MBEDTLS_X509_RSASSA_PSS_SUPPORT)
+int mbedtls_x509_get_rsassa_pss_params( const mbedtls_x509_buf *params,
+                                mbedtls_md_type_t *md_alg, mbedtls_md_type_t *mgf_md,
+                                int *salt_len );
+#endif
+int mbedtls_x509_get_sig( unsigned char **p, const unsigned char *end, mbedtls_x509_buf *sig );
+int mbedtls_x509_get_sig_alg( const mbedtls_x509_buf *sig_oid, const mbedtls_x509_buf *sig_params,
+                      mbedtls_md_type_t *md_alg, mbedtls_pk_type_t *pk_alg,
+                      void **sig_opts );
+int mbedtls_x509_get_time( unsigned char **p, const unsigned char *end,
+                   mbedtls_x509_time *time );
+int mbedtls_x509_get_serial( unsigned char **p, const unsigned char *end,
+                     mbedtls_x509_buf *serial );
+int mbedtls_x509_get_ext( unsigned char **p, const unsigned char *end,
+                  mbedtls_x509_buf *ext, int tag );
+int mbedtls_x509_sig_alg_gets( char *buf, size_t size, const mbedtls_x509_buf *sig_oid,
+                       mbedtls_pk_type_t pk_alg, mbedtls_md_type_t md_alg,
+                       const void *sig_opts );
+int mbedtls_x509_key_size_helper( char *buf, size_t buf_size, const char *name );
+int mbedtls_x509_string_to_names( mbedtls_asn1_named_data **head, const char *name );
+int mbedtls_x509_set_extension( mbedtls_asn1_named_data **head, const char *oid, size_t oid_len,
+                        int critical, const unsigned char *val,
+                        size_t val_len );
+int mbedtls_x509_write_extensions( unsigned char **p, unsigned char *start,
+                           mbedtls_asn1_named_data *first );
+int mbedtls_x509_write_names( unsigned char **p, unsigned char *start,
+                      mbedtls_asn1_named_data *first );
+int mbedtls_x509_write_sig( unsigned char **p, unsigned char *start,
+                    const char *oid, size_t oid_len,
+                    unsigned char *sig, size_t size );
+
+#define MBEDTLS_X509_SAFE_SNPRINTF                          \
+    do {                                                    \
+        if( ret < 0 || (size_t) ret >= n )                  \
+            return( MBEDTLS_ERR_X509_BUFFER_TOO_SMALL );    \
+                                                            \
+        n -= (size_t) ret;                                  \
+        p += (size_t) ret;                                  \
+    } while( 0 )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* x509.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/x509_crl.h b/tools/sdk/include/mbedtls/mbedtls/x509_crl.h
new file mode 100644
index 00000000..79884399
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/x509_crl.h
@@ -0,0 +1,173 @@
+/**
+ * \file x509_crl.h
+ *
+ * \brief X.509 certificate revocation list parsing
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_X509_CRL_H
+#define MBEDTLS_X509_CRL_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#include "x509.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup x509_module
+ * \{ */
+
+/**
+ * \name Structures and functions for parsing CRLs
+ * \{
+ */
+
+/**
+ * Certificate revocation list entry.
+ * Contains the CA-specific serial numbers and revocation dates.
+ */
+typedef struct mbedtls_x509_crl_entry
+{
+    mbedtls_x509_buf raw;
+
+    mbedtls_x509_buf serial;
+
+    mbedtls_x509_time revocation_date;
+
+    mbedtls_x509_buf entry_ext;
+
+    struct mbedtls_x509_crl_entry *next;
+}
+mbedtls_x509_crl_entry;
+
+/**
+ * Certificate revocation list structure.
+ * Every CRL may have multiple entries.
+ */
+typedef struct mbedtls_x509_crl
+{
+    mbedtls_x509_buf raw;           /**< The raw certificate data (DER). */
+    mbedtls_x509_buf tbs;           /**< The raw certificate body (DER). The part that is To Be Signed. */
+
+    int version;            /**< CRL version (1=v1, 2=v2) */
+    mbedtls_x509_buf sig_oid;       /**< CRL signature type identifier */
+
+    mbedtls_x509_buf issuer_raw;    /**< The raw issuer data (DER). */
+
+    mbedtls_x509_name issuer;       /**< The parsed issuer data (named information object). */
+
+    mbedtls_x509_time this_update;
+    mbedtls_x509_time next_update;
+
+    mbedtls_x509_crl_entry entry;   /**< The CRL entries containing the certificate revocation times for this CA. */
+
+    mbedtls_x509_buf crl_ext;
+
+    mbedtls_x509_buf sig_oid2;
+    mbedtls_x509_buf sig;
+    mbedtls_md_type_t sig_md;           /**< Internal representation of the MD algorithm of the signature algorithm, e.g. MBEDTLS_MD_SHA256 */
+    mbedtls_pk_type_t sig_pk;           /**< Internal representation of the Public Key algorithm of the signature algorithm, e.g. MBEDTLS_PK_RSA */
+    void *sig_opts;             /**< Signature options to be passed to mbedtls_pk_verify_ext(), e.g. for RSASSA-PSS */
+
+    struct mbedtls_x509_crl *next;
+}
+mbedtls_x509_crl;
+
+/**
+ * \brief          Parse a DER-encoded CRL and append it to the chained list
+ *
+ * \param chain    points to the start of the chain
+ * \param buf      buffer holding the CRL data in DER format
+ * \param buflen   size of the buffer
+ *                 (including the terminating null byte for PEM data)
+ *
+ * \return         0 if successful, or a specific X509 or PEM error code
+ */
+int mbedtls_x509_crl_parse_der( mbedtls_x509_crl *chain,
+                        const unsigned char *buf, size_t buflen );
+/**
+ * \brief          Parse one or more CRLs and append them to the chained list
+ *
+ * \note           Mutliple CRLs are accepted only if using PEM format
+ *
+ * \param chain    points to the start of the chain
+ * \param buf      buffer holding the CRL data in PEM or DER format
+ * \param buflen   size of the buffer
+ *                 (including the terminating null byte for PEM data)
+ *
+ * \return         0 if successful, or a specific X509 or PEM error code
+ */
+int mbedtls_x509_crl_parse( mbedtls_x509_crl *chain, const unsigned char *buf, size_t buflen );
+
+#if defined(MBEDTLS_FS_IO)
+/**
+ * \brief          Load one or more CRLs and append them to the chained list
+ *
+ * \note           Mutliple CRLs are accepted only if using PEM format
+ *
+ * \param chain    points to the start of the chain
+ * \param path     filename to read the CRLs from (in PEM or DER encoding)
+ *
+ * \return         0 if successful, or a specific X509 or PEM error code
+ */
+int mbedtls_x509_crl_parse_file( mbedtls_x509_crl *chain, const char *path );
+#endif /* MBEDTLS_FS_IO */
+
+/**
+ * \brief          Returns an informational string about the CRL.
+ *
+ * \param buf      Buffer to write to
+ * \param size     Maximum size of buffer
+ * \param prefix   A line prefix
+ * \param crl      The X509 CRL to represent
+ *
+ * \return         The length of the string written (not including the
+ *                 terminated nul byte), or a negative error code.
+ */
+int mbedtls_x509_crl_info( char *buf, size_t size, const char *prefix,
+                   const mbedtls_x509_crl *crl );
+
+/**
+ * \brief          Initialize a CRL (chain)
+ *
+ * \param crl      CRL chain to initialize
+ */
+void mbedtls_x509_crl_init( mbedtls_x509_crl *crl );
+
+/**
+ * \brief          Unallocate all CRL data
+ *
+ * \param crl      CRL chain to free
+ */
+void mbedtls_x509_crl_free( mbedtls_x509_crl *crl );
+
+/* \} name */
+/* \} addtogroup x509_module */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* mbedtls_x509_crl.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/x509_crt.h b/tools/sdk/include/mbedtls/mbedtls/x509_crt.h
new file mode 100644
index 00000000..41b6bfe5
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/x509_crt.h
@@ -0,0 +1,650 @@
+/**
+ * \file x509_crt.h
+ *
+ * \brief X.509 certificate parsing and writing
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_X509_CRT_H
+#define MBEDTLS_X509_CRT_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#include "x509.h"
+#include "x509_crl.h"
+
+/**
+ * \addtogroup x509_module
+ * \{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \name Structures and functions for parsing and writing X.509 certificates
+ * \{
+ */
+
+/**
+ * Container for an X.509 certificate. The certificate may be chained.
+ */
+typedef struct mbedtls_x509_crt
+{
+    mbedtls_x509_buf raw;               /**< The raw certificate data (DER). */
+    mbedtls_x509_buf tbs;               /**< The raw certificate body (DER). The part that is To Be Signed. */
+
+    int version;                /**< The X.509 version. (1=v1, 2=v2, 3=v3) */
+    mbedtls_x509_buf serial;            /**< Unique id for certificate issued by a specific CA. */
+    mbedtls_x509_buf sig_oid;           /**< Signature algorithm, e.g. sha1RSA */
+
+    mbedtls_x509_buf issuer_raw;        /**< The raw issuer data (DER). Used for quick comparison. */
+    mbedtls_x509_buf subject_raw;       /**< The raw subject data (DER). Used for quick comparison. */
+
+    mbedtls_x509_name issuer;           /**< The parsed issuer data (named information object). */
+    mbedtls_x509_name subject;          /**< The parsed subject data (named information object). */
+
+    mbedtls_x509_time valid_from;       /**< Start time of certificate validity. */
+    mbedtls_x509_time valid_to;         /**< End time of certificate validity. */
+
+    mbedtls_pk_context pk;              /**< Container for the public key context. */
+
+    mbedtls_x509_buf issuer_id;         /**< Optional X.509 v2/v3 issuer unique identifier. */
+    mbedtls_x509_buf subject_id;        /**< Optional X.509 v2/v3 subject unique identifier. */
+    mbedtls_x509_buf v3_ext;            /**< Optional X.509 v3 extensions.  */
+    mbedtls_x509_sequence subject_alt_names;    /**< Optional list of Subject Alternative Names (Only dNSName supported). */
+
+    int ext_types;              /**< Bit string containing detected and parsed extensions */
+    int ca_istrue;              /**< Optional Basic Constraint extension value: 1 if this certificate belongs to a CA, 0 otherwise. */
+    int max_pathlen;            /**< Optional Basic Constraint extension value: The maximum path length to the root certificate. Path length is 1 higher than RFC 5280 'meaning', so 1+ */
+
+    unsigned int key_usage;     /**< Optional key usage extension value: See the values in x509.h */
+
+    mbedtls_x509_sequence ext_key_usage; /**< Optional list of extended key usage OIDs. */
+
+    unsigned char ns_cert_type; /**< Optional Netscape certificate type extension value: See the values in x509.h */
+
+    mbedtls_x509_buf sig;               /**< Signature: hash of the tbs part signed with the private key. */
+    mbedtls_md_type_t sig_md;           /**< Internal representation of the MD algorithm of the signature algorithm, e.g. MBEDTLS_MD_SHA256 */
+    mbedtls_pk_type_t sig_pk;           /**< Internal representation of the Public Key algorithm of the signature algorithm, e.g. MBEDTLS_PK_RSA */
+    void *sig_opts;             /**< Signature options to be passed to mbedtls_pk_verify_ext(), e.g. for RSASSA-PSS */
+
+    struct mbedtls_x509_crt *next;     /**< Next certificate in the CA-chain. */
+}
+mbedtls_x509_crt;
+
+/**
+ * Build flag from an algorithm/curve identifier (pk, md, ecp)
+ * Since 0 is always XXX_NONE, ignore it.
+ */
+#define MBEDTLS_X509_ID_FLAG( id )   ( 1 << ( id - 1 ) )
+
+/**
+ * Security profile for certificate verification.
+ *
+ * All lists are bitfields, built by ORing flags from MBEDTLS_X509_ID_FLAG().
+ */
+typedef struct
+{
+    uint32_t allowed_mds;       /**< MDs for signatures         */
+    uint32_t allowed_pks;       /**< PK algs for signatures     */
+    uint32_t allowed_curves;    /**< Elliptic curves for ECDSA  */
+    uint32_t rsa_min_bitlen;    /**< Minimum size for RSA keys  */
+}
+mbedtls_x509_crt_profile;
+
+#define MBEDTLS_X509_CRT_VERSION_1              0
+#define MBEDTLS_X509_CRT_VERSION_2              1
+#define MBEDTLS_X509_CRT_VERSION_3              2
+
+#define MBEDTLS_X509_RFC5280_MAX_SERIAL_LEN 32
+#define MBEDTLS_X509_RFC5280_UTC_TIME_LEN   15
+
+/**
+ * Container for writing a certificate (CRT)
+ */
+typedef struct mbedtls_x509write_cert
+{
+    int version;
+    mbedtls_mpi serial;
+    mbedtls_pk_context *subject_key;
+    mbedtls_pk_context *issuer_key;
+    mbedtls_asn1_named_data *subject;
+    mbedtls_asn1_named_data *issuer;
+    mbedtls_md_type_t md_alg;
+    char not_before[MBEDTLS_X509_RFC5280_UTC_TIME_LEN + 1];
+    char not_after[MBEDTLS_X509_RFC5280_UTC_TIME_LEN + 1];
+    mbedtls_asn1_named_data *extensions;
+}
+mbedtls_x509write_cert;
+
+#if defined(MBEDTLS_X509_CRT_PARSE_C)
+/**
+ * Default security profile. Should provide a good balance between security
+ * and compatibility with current deployments.
+ */
+extern const mbedtls_x509_crt_profile mbedtls_x509_crt_profile_default;
+
+/**
+ * Expected next default profile. Recommended for new deployments.
+ * Currently targets a 128-bit security level, except for RSA-2048.
+ */
+extern const mbedtls_x509_crt_profile mbedtls_x509_crt_profile_next;
+
+/**
+ * NSA Suite B profile.
+ */
+extern const mbedtls_x509_crt_profile mbedtls_x509_crt_profile_suiteb;
+
+/**
+ * \brief          Parse a single DER formatted certificate and add it
+ *                 to the chained list.
+ *
+ * \param chain    points to the start of the chain
+ * \param buf      buffer holding the certificate DER data
+ * \param buflen   size of the buffer
+ *
+ * \return         0 if successful, or a specific X509 or PEM error code
+ */
+int mbedtls_x509_crt_parse_der( mbedtls_x509_crt *chain, const unsigned char *buf,
+                        size_t buflen );
+
+/**
+ * \brief          Parse one or more certificates and add them
+ *                 to the chained list. Parses permissively. If some
+ *                 certificates can be parsed, the result is the number
+ *                 of failed certificates it encountered. If none complete
+ *                 correctly, the first error is returned.
+ *
+ * \param chain    points to the start of the chain
+ * \param buf      buffer holding the certificate data in PEM or DER format
+ * \param buflen   size of the buffer
+ *                 (including the terminating null byte for PEM data)
+ *
+ * \return         0 if all certificates parsed successfully, a positive number
+ *                 if partly successful or a specific X509 or PEM error code
+ */
+int mbedtls_x509_crt_parse( mbedtls_x509_crt *chain, const unsigned char *buf, size_t buflen );
+
+#if defined(MBEDTLS_FS_IO)
+/**
+ * \brief          Load one or more certificates and add them
+ *                 to the chained list. Parses permissively. If some
+ *                 certificates can be parsed, the result is the number
+ *                 of failed certificates it encountered. If none complete
+ *                 correctly, the first error is returned.
+ *
+ * \param chain    points to the start of the chain
+ * \param path     filename to read the certificates from
+ *
+ * \return         0 if all certificates parsed successfully, a positive number
+ *                 if partly successful or a specific X509 or PEM error code
+ */
+int mbedtls_x509_crt_parse_file( mbedtls_x509_crt *chain, const char *path );
+
+/**
+ * \brief          Load one or more certificate files from a path and add them
+ *                 to the chained list. Parses permissively. If some
+ *                 certificates can be parsed, the result is the number
+ *                 of failed certificates it encountered. If none complete
+ *                 correctly, the first error is returned.
+ *
+ * \param chain    points to the start of the chain
+ * \param path     directory / folder to read the certificate files from
+ *
+ * \return         0 if all certificates parsed successfully, a positive number
+ *                 if partly successful or a specific X509 or PEM error code
+ */
+int mbedtls_x509_crt_parse_path( mbedtls_x509_crt *chain, const char *path );
+#endif /* MBEDTLS_FS_IO */
+
+/**
+ * \brief          Returns an informational string about the
+ *                 certificate.
+ *
+ * \param buf      Buffer to write to
+ * \param size     Maximum size of buffer
+ * \param prefix   A line prefix
+ * \param crt      The X509 certificate to represent
+ *
+ * \return         The length of the string written (not including the
+ *                 terminated nul byte), or a negative error code.
+ */
+int mbedtls_x509_crt_info( char *buf, size_t size, const char *prefix,
+                   const mbedtls_x509_crt *crt );
+
+/**
+ * \brief          Returns an informational string about the
+ *                 verification status of a certificate.
+ *
+ * \param buf      Buffer to write to
+ * \param size     Maximum size of buffer
+ * \param prefix   A line prefix
+ * \param flags    Verification flags created by mbedtls_x509_crt_verify()
+ *
+ * \return         The length of the string written (not including the
+ *                 terminated nul byte), or a negative error code.
+ */
+int mbedtls_x509_crt_verify_info( char *buf, size_t size, const char *prefix,
+                          uint32_t flags );
+
+/**
+ * \brief          Verify the certificate signature
+ *
+ *                 The verify callback is a user-supplied callback that
+ *                 can clear / modify / add flags for a certificate. If set,
+ *                 the verification callback is called for each
+ *                 certificate in the chain (from the trust-ca down to the
+ *                 presented crt). The parameters for the callback are:
+ *                 (void *parameter, mbedtls_x509_crt *crt, int certificate_depth,
+ *                 int *flags). With the flags representing current flags for
+ *                 that specific certificate and the certificate depth from
+ *                 the bottom (Peer cert depth = 0).
+ *
+ *                 All flags left after returning from the callback
+ *                 are also returned to the application. The function should
+ *                 return 0 for anything but a fatal error.
+ *
+ * \note           In case verification failed, the results can be displayed
+ *                 using \c mbedtls_x509_crt_verify_info()
+ *
+ * \note           Same as \c mbedtls_x509_crt_verify_with_profile() with the
+ *                 default security profile.
+ *
+ * \note           It is your responsibility to provide up-to-date CRLs for
+ *                 all trusted CAs. If no CRL is provided for the CA that was
+ *                 used to sign the certificate, CRL verification is skipped
+ *                 silently, that is *without* setting any flag.
+ *
+ * \param crt      a certificate (chain) to be verified
+ * \param trust_ca the list of trusted CAs
+ * \param ca_crl   the list of CRLs for trusted CAs (see note above)
+ * \param cn       expected Common Name (can be set to
+ *                 NULL if the CN must not be verified)
+ * \param flags    result of the verification
+ * \param f_vrfy   verification function
+ * \param p_vrfy   verification parameter
+ *
+ * \return         0 if successful or MBEDTLS_ERR_X509_CERT_VERIFY_FAILED
+ *                 in which case *flags will have one or more
+ *                 MBEDTLS_X509_BADCERT_XXX or MBEDTLS_X509_BADCRL_XXX flags
+ *                 set,
+ *                 or another error in case of a fatal error encountered
+ *                 during the verification process.
+ */
+int mbedtls_x509_crt_verify( mbedtls_x509_crt *crt,
+                     mbedtls_x509_crt *trust_ca,
+                     mbedtls_x509_crl *ca_crl,
+                     const char *cn, uint32_t *flags,
+                     int (*f_vrfy)(void *, mbedtls_x509_crt *, int, uint32_t *),
+                     void *p_vrfy );
+
+/**
+ * \brief          Verify the certificate signature according to profile
+ *
+ * \note           Same as \c mbedtls_x509_crt_verify(), but with explicit
+ *                 security profile.
+ *
+ * \note           The restrictions on keys (RSA minimum size, allowed curves
+ *                 for ECDSA) apply to all certificates: trusted root,
+ *                 intermediate CAs if any, and end entity certificate.
+ *
+ * \param crt      a certificate (chain) to be verified
+ * \param trust_ca the list of trusted CAs
+ * \param ca_crl   the list of CRLs for trusted CAs
+ * \param profile  security profile for verification
+ * \param cn       expected Common Name (can be set to
+ *                 NULL if the CN must not be verified)
+ * \param flags    result of the verification
+ * \param f_vrfy   verification function
+ * \param p_vrfy   verification parameter
+ *
+ * \return         0 if successful or MBEDTLS_ERR_X509_CERT_VERIFY_FAILED
+ *                 in which case *flags will have one or more
+ *                 MBEDTLS_X509_BADCERT_XXX or MBEDTLS_X509_BADCRL_XXX flags
+ *                 set,
+ *                 or another error in case of a fatal error encountered
+ *                 during the verification process.
+ */
+int mbedtls_x509_crt_verify_with_profile( mbedtls_x509_crt *crt,
+                     mbedtls_x509_crt *trust_ca,
+                     mbedtls_x509_crl *ca_crl,
+                     const mbedtls_x509_crt_profile *profile,
+                     const char *cn, uint32_t *flags,
+                     int (*f_vrfy)(void *, mbedtls_x509_crt *, int, uint32_t *),
+                     void *p_vrfy );
+
+#if defined(MBEDTLS_X509_CHECK_KEY_USAGE)
+/**
+ * \brief          Check usage of certificate against keyUsage extension.
+ *
+ * \param crt      Leaf certificate used.
+ * \param usage    Intended usage(s) (eg MBEDTLS_X509_KU_KEY_ENCIPHERMENT
+ *                 before using the certificate to perform an RSA key
+ *                 exchange).
+ *
+ * \note           Except for decipherOnly and encipherOnly, a bit set in the
+ *                 usage argument means this bit MUST be set in the
+ *                 certificate. For decipherOnly and encipherOnly, it means
+ *                 that bit MAY be set.
+ *
+ * \return         0 is these uses of the certificate are allowed,
+ *                 MBEDTLS_ERR_X509_BAD_INPUT_DATA if the keyUsage extension
+ *                 is present but does not match the usage argument.
+ *
+ * \note           You should only call this function on leaf certificates, on
+ *                 (intermediate) CAs the keyUsage extension is automatically
+ *                 checked by \c mbedtls_x509_crt_verify().
+ */
+int mbedtls_x509_crt_check_key_usage( const mbedtls_x509_crt *crt,
+                                      unsigned int usage );
+#endif /* MBEDTLS_X509_CHECK_KEY_USAGE) */
+
+#if defined(MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE)
+/**
+ * \brief          Check usage of certificate against extentedJeyUsage.
+ *
+ * \param crt      Leaf certificate used.
+ * \param usage_oid Intended usage (eg MBEDTLS_OID_SERVER_AUTH or MBEDTLS_OID_CLIENT_AUTH).
+ * \param usage_len Length of usage_oid (eg given by MBEDTLS_OID_SIZE()).
+ *
+ * \return         0 if this use of the certificate is allowed,
+ *                 MBEDTLS_ERR_X509_BAD_INPUT_DATA if not.
+ *
+ * \note           Usually only makes sense on leaf certificates.
+ */
+int mbedtls_x509_crt_check_extended_key_usage( const mbedtls_x509_crt *crt,
+                                       const char *usage_oid,
+                                       size_t usage_len );
+#endif /* MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE) */
+
+#if defined(MBEDTLS_X509_CRL_PARSE_C)
+/**
+ * \brief          Verify the certificate revocation status
+ *
+ * \param crt      a certificate to be verified
+ * \param crl      the CRL to verify against
+ *
+ * \return         1 if the certificate is revoked, 0 otherwise
+ *
+ */
+int mbedtls_x509_crt_is_revoked( const mbedtls_x509_crt *crt, const mbedtls_x509_crl *crl );
+#endif /* MBEDTLS_X509_CRL_PARSE_C */
+
+/**
+ * \brief          Initialize a certificate (chain)
+ *
+ * \param crt      Certificate chain to initialize
+ */
+void mbedtls_x509_crt_init( mbedtls_x509_crt *crt );
+
+/**
+ * \brief          Unallocate all certificate data
+ *
+ * \param crt      Certificate chain to free
+ */
+void mbedtls_x509_crt_free( mbedtls_x509_crt *crt );
+#endif /* MBEDTLS_X509_CRT_PARSE_C */
+
+/* \} name */
+/* \} addtogroup x509_module */
+
+#if defined(MBEDTLS_X509_CRT_WRITE_C)
+/**
+ * \brief           Initialize a CRT writing context
+ *
+ * \param ctx       CRT context to initialize
+ */
+void mbedtls_x509write_crt_init( mbedtls_x509write_cert *ctx );
+
+/**
+ * \brief           Set the verion for a Certificate
+ *                  Default: MBEDTLS_X509_CRT_VERSION_3
+ *
+ * \param ctx       CRT context to use
+ * \param version   version to set (MBEDTLS_X509_CRT_VERSION_1, MBEDTLS_X509_CRT_VERSION_2 or
+ *                                  MBEDTLS_X509_CRT_VERSION_3)
+ */
+void mbedtls_x509write_crt_set_version( mbedtls_x509write_cert *ctx, int version );
+
+/**
+ * \brief           Set the serial number for a Certificate.
+ *
+ * \param ctx       CRT context to use
+ * \param serial    serial number to set
+ *
+ * \return          0 if successful
+ */
+int mbedtls_x509write_crt_set_serial( mbedtls_x509write_cert *ctx, const mbedtls_mpi *serial );
+
+/**
+ * \brief           Set the validity period for a Certificate
+ *                  Timestamps should be in string format for UTC timezone
+ *                  i.e. "YYYYMMDDhhmmss"
+ *                  e.g. "20131231235959" for December 31st 2013
+ *                       at 23:59:59
+ *
+ * \param ctx       CRT context to use
+ * \param not_before    not_before timestamp
+ * \param not_after     not_after timestamp
+ *
+ * \return          0 if timestamp was parsed successfully, or
+ *                  a specific error code
+ */
+int mbedtls_x509write_crt_set_validity( mbedtls_x509write_cert *ctx, const char *not_before,
+                                const char *not_after );
+
+/**
+ * \brief           Set the issuer name for a Certificate
+ *                  Issuer names should contain a comma-separated list
+ *                  of OID types and values:
+ *                  e.g. "C=UK,O=ARM,CN=mbed TLS CA"
+ *
+ * \param ctx           CRT context to use
+ * \param issuer_name   issuer name to set
+ *
+ * \return          0 if issuer name was parsed successfully, or
+ *                  a specific error code
+ */
+int mbedtls_x509write_crt_set_issuer_name( mbedtls_x509write_cert *ctx,
+                                   const char *issuer_name );
+
+/**
+ * \brief           Set the subject name for a Certificate
+ *                  Subject names should contain a comma-separated list
+ *                  of OID types and values:
+ *                  e.g. "C=UK,O=ARM,CN=mbed TLS Server 1"
+ *
+ * \param ctx           CRT context to use
+ * \param subject_name  subject name to set
+ *
+ * \return          0 if subject name was parsed successfully, or
+ *                  a specific error code
+ */
+int mbedtls_x509write_crt_set_subject_name( mbedtls_x509write_cert *ctx,
+                                    const char *subject_name );
+
+/**
+ * \brief           Set the subject public key for the certificate
+ *
+ * \param ctx       CRT context to use
+ * \param key       public key to include
+ */
+void mbedtls_x509write_crt_set_subject_key( mbedtls_x509write_cert *ctx, mbedtls_pk_context *key );
+
+/**
+ * \brief           Set the issuer key used for signing the certificate
+ *
+ * \param ctx       CRT context to use
+ * \param key       private key to sign with
+ */
+void mbedtls_x509write_crt_set_issuer_key( mbedtls_x509write_cert *ctx, mbedtls_pk_context *key );
+
+/**
+ * \brief           Set the MD algorithm to use for the signature
+ *                  (e.g. MBEDTLS_MD_SHA1)
+ *
+ * \param ctx       CRT context to use
+ * \param md_alg    MD algorithm to use
+ */
+void mbedtls_x509write_crt_set_md_alg( mbedtls_x509write_cert *ctx, mbedtls_md_type_t md_alg );
+
+/**
+ * \brief           Generic function to add to or replace an extension in the
+ *                  CRT
+ *
+ * \param ctx       CRT context to use
+ * \param oid       OID of the extension
+ * \param oid_len   length of the OID
+ * \param critical  if the extension is critical (per the RFC's definition)
+ * \param val       value of the extension OCTET STRING
+ * \param val_len   length of the value data
+ *
+ * \return          0 if successful, or a MBEDTLS_ERR_X509_ALLOC_FAILED
+ */
+int mbedtls_x509write_crt_set_extension( mbedtls_x509write_cert *ctx,
+                                 const char *oid, size_t oid_len,
+                                 int critical,
+                                 const unsigned char *val, size_t val_len );
+
+/**
+ * \brief           Set the basicConstraints extension for a CRT
+ *
+ * \param ctx       CRT context to use
+ * \param is_ca     is this a CA certificate
+ * \param max_pathlen   maximum length of certificate chains below this
+ *                      certificate (only for CA certificates, -1 is
+ *                      inlimited)
+ *
+ * \return          0 if successful, or a MBEDTLS_ERR_X509_ALLOC_FAILED
+ */
+int mbedtls_x509write_crt_set_basic_constraints( mbedtls_x509write_cert *ctx,
+                                         int is_ca, int max_pathlen );
+
+#if defined(MBEDTLS_SHA1_C)
+/**
+ * \brief           Set the subjectKeyIdentifier extension for a CRT
+ *                  Requires that mbedtls_x509write_crt_set_subject_key() has been
+ *                  called before
+ *
+ * \param ctx       CRT context to use
+ *
+ * \return          0 if successful, or a MBEDTLS_ERR_X509_ALLOC_FAILED
+ */
+int mbedtls_x509write_crt_set_subject_key_identifier( mbedtls_x509write_cert *ctx );
+
+/**
+ * \brief           Set the authorityKeyIdentifier extension for a CRT
+ *                  Requires that mbedtls_x509write_crt_set_issuer_key() has been
+ *                  called before
+ *
+ * \param ctx       CRT context to use
+ *
+ * \return          0 if successful, or a MBEDTLS_ERR_X509_ALLOC_FAILED
+ */
+int mbedtls_x509write_crt_set_authority_key_identifier( mbedtls_x509write_cert *ctx );
+#endif /* MBEDTLS_SHA1_C */
+
+/**
+ * \brief           Set the Key Usage Extension flags
+ *                  (e.g. MBEDTLS_X509_KU_DIGITAL_SIGNATURE | MBEDTLS_X509_KU_KEY_CERT_SIGN)
+ *
+ * \param ctx       CRT context to use
+ * \param key_usage key usage flags to set
+ *
+ * \return          0 if successful, or MBEDTLS_ERR_X509_ALLOC_FAILED
+ */
+int mbedtls_x509write_crt_set_key_usage( mbedtls_x509write_cert *ctx,
+                                         unsigned int key_usage );
+
+/**
+ * \brief           Set the Netscape Cert Type flags
+ *                  (e.g. MBEDTLS_X509_NS_CERT_TYPE_SSL_CLIENT | MBEDTLS_X509_NS_CERT_TYPE_EMAIL)
+ *
+ * \param ctx           CRT context to use
+ * \param ns_cert_type  Netscape Cert Type flags to set
+ *
+ * \return          0 if successful, or MBEDTLS_ERR_X509_ALLOC_FAILED
+ */
+int mbedtls_x509write_crt_set_ns_cert_type( mbedtls_x509write_cert *ctx,
+                                    unsigned char ns_cert_type );
+
+/**
+ * \brief           Free the contents of a CRT write context
+ *
+ * \param ctx       CRT context to free
+ */
+void mbedtls_x509write_crt_free( mbedtls_x509write_cert *ctx );
+
+/**
+ * \brief           Write a built up certificate to a X509 DER structure
+ *                  Note: data is written at the end of the buffer! Use the
+ *                        return value to determine where you should start
+ *                        using the buffer
+ *
+ * \param ctx       certificate to write away
+ * \param buf       buffer to write to
+ * \param size      size of the buffer
+ * \param f_rng     RNG function (for signature, see note)
+ * \param p_rng     RNG parameter
+ *
+ * \return          length of data written if successful, or a specific
+ *                  error code
+ *
+ * \note            f_rng may be NULL if RSA is used for signature and the
+ *                  signature is made offline (otherwise f_rng is desirable
+ *                  for countermeasures against timing attacks).
+ *                  ECDSA signatures always require a non-NULL f_rng.
+ */
+int mbedtls_x509write_crt_der( mbedtls_x509write_cert *ctx, unsigned char *buf, size_t size,
+                       int (*f_rng)(void *, unsigned char *, size_t),
+                       void *p_rng );
+
+#if defined(MBEDTLS_PEM_WRITE_C)
+/**
+ * \brief           Write a built up certificate to a X509 PEM string
+ *
+ * \param ctx       certificate to write away
+ * \param buf       buffer to write to
+ * \param size      size of the buffer
+ * \param f_rng     RNG function (for signature, see note)
+ * \param p_rng     RNG parameter
+ *
+ * \return          0 if successful, or a specific error code
+ *
+ * \note            f_rng may be NULL if RSA is used for signature and the
+ *                  signature is made offline (otherwise f_rng is desirable
+ *                  for countermeasures against timing attacks).
+ *                  ECDSA signatures always require a non-NULL f_rng.
+ */
+int mbedtls_x509write_crt_pem( mbedtls_x509write_cert *ctx, unsigned char *buf, size_t size,
+                       int (*f_rng)(void *, unsigned char *, size_t),
+                       void *p_rng );
+#endif /* MBEDTLS_PEM_WRITE_C */
+#endif /* MBEDTLS_X509_CRT_WRITE_C */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* mbedtls_x509_crt.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/x509_csr.h b/tools/sdk/include/mbedtls/mbedtls/x509_csr.h
new file mode 100644
index 00000000..7a9c2e05
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/x509_csr.h
@@ -0,0 +1,298 @@
+/**
+ * \file x509_csr.h
+ *
+ * \brief X.509 certificate signing request parsing and writing
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_X509_CSR_H
+#define MBEDTLS_X509_CSR_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#include "x509.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup x509_module
+ * \{ */
+
+/**
+ * \name Structures and functions for X.509 Certificate Signing Requests (CSR)
+ * \{
+ */
+
+/**
+ * Certificate Signing Request (CSR) structure.
+ */
+typedef struct mbedtls_x509_csr
+{
+    mbedtls_x509_buf raw;           /**< The raw CSR data (DER). */
+    mbedtls_x509_buf cri;           /**< The raw CertificateRequestInfo body (DER). */
+
+    int version;            /**< CSR version (1=v1). */
+
+    mbedtls_x509_buf  subject_raw;  /**< The raw subject data (DER). */
+    mbedtls_x509_name subject;      /**< The parsed subject data (named information object). */
+
+    mbedtls_pk_context pk;          /**< Container for the public key context. */
+
+    mbedtls_x509_buf sig_oid;
+    mbedtls_x509_buf sig;
+    mbedtls_md_type_t sig_md;       /**< Internal representation of the MD algorithm of the signature algorithm, e.g. MBEDTLS_MD_SHA256 */
+    mbedtls_pk_type_t sig_pk;       /**< Internal representation of the Public Key algorithm of the signature algorithm, e.g. MBEDTLS_PK_RSA */
+    void *sig_opts;         /**< Signature options to be passed to mbedtls_pk_verify_ext(), e.g. for RSASSA-PSS */
+}
+mbedtls_x509_csr;
+
+/**
+ * Container for writing a CSR
+ */
+typedef struct mbedtls_x509write_csr
+{
+    mbedtls_pk_context *key;
+    mbedtls_asn1_named_data *subject;
+    mbedtls_md_type_t md_alg;
+    mbedtls_asn1_named_data *extensions;
+}
+mbedtls_x509write_csr;
+
+#if defined(MBEDTLS_X509_CSR_PARSE_C)
+/**
+ * \brief          Load a Certificate Signing Request (CSR) in DER format
+ *
+ * \note           CSR attributes (if any) are currently silently ignored.
+ *
+ * \param csr      CSR context to fill
+ * \param buf      buffer holding the CRL data
+ * \param buflen   size of the buffer
+ *
+ * \return         0 if successful, or a specific X509 error code
+ */
+int mbedtls_x509_csr_parse_der( mbedtls_x509_csr *csr,
+                        const unsigned char *buf, size_t buflen );
+
+/**
+ * \brief          Load a Certificate Signing Request (CSR), DER or PEM format
+ *
+ * \note           See notes for \c mbedtls_x509_csr_parse_der()
+ *
+ * \param csr      CSR context to fill
+ * \param buf      buffer holding the CRL data
+ * \param buflen   size of the buffer
+ *                 (including the terminating null byte for PEM data)
+ *
+ * \return         0 if successful, or a specific X509 or PEM error code
+ */
+int mbedtls_x509_csr_parse( mbedtls_x509_csr *csr, const unsigned char *buf, size_t buflen );
+
+#if defined(MBEDTLS_FS_IO)
+/**
+ * \brief          Load a Certificate Signing Request (CSR)
+ *
+ * \note           See notes for \c mbedtls_x509_csr_parse()
+ *
+ * \param csr      CSR context to fill
+ * \param path     filename to read the CSR from
+ *
+ * \return         0 if successful, or a specific X509 or PEM error code
+ */
+int mbedtls_x509_csr_parse_file( mbedtls_x509_csr *csr, const char *path );
+#endif /* MBEDTLS_FS_IO */
+
+/**
+ * \brief          Returns an informational string about the
+ *                 CSR.
+ *
+ * \param buf      Buffer to write to
+ * \param size     Maximum size of buffer
+ * \param prefix   A line prefix
+ * \param csr      The X509 CSR to represent
+ *
+ * \return         The length of the string written (not including the
+ *                 terminated nul byte), or a negative error code.
+ */
+int mbedtls_x509_csr_info( char *buf, size_t size, const char *prefix,
+                   const mbedtls_x509_csr *csr );
+
+/**
+ * \brief          Initialize a CSR
+ *
+ * \param csr      CSR to initialize
+ */
+void mbedtls_x509_csr_init( mbedtls_x509_csr *csr );
+
+/**
+ * \brief          Unallocate all CSR data
+ *
+ * \param csr      CSR to free
+ */
+void mbedtls_x509_csr_free( mbedtls_x509_csr *csr );
+#endif /* MBEDTLS_X509_CSR_PARSE_C */
+
+/* \} name */
+/* \} addtogroup x509_module */
+
+#if defined(MBEDTLS_X509_CSR_WRITE_C)
+/**
+ * \brief           Initialize a CSR context
+ *
+ * \param ctx       CSR context to initialize
+ */
+void mbedtls_x509write_csr_init( mbedtls_x509write_csr *ctx );
+
+/**
+ * \brief           Set the subject name for a CSR
+ *                  Subject names should contain a comma-separated list
+ *                  of OID types and values:
+ *                  e.g. "C=UK,O=ARM,CN=mbed TLS Server 1"
+ *
+ * \param ctx           CSR context to use
+ * \param subject_name  subject name to set
+ *
+ * \return          0 if subject name was parsed successfully, or
+ *                  a specific error code
+ */
+int mbedtls_x509write_csr_set_subject_name( mbedtls_x509write_csr *ctx,
+                                    const char *subject_name );
+
+/**
+ * \brief           Set the key for a CSR (public key will be included,
+ *                  private key used to sign the CSR when writing it)
+ *
+ * \param ctx       CSR context to use
+ * \param key       Asymetric key to include
+ */
+void mbedtls_x509write_csr_set_key( mbedtls_x509write_csr *ctx, mbedtls_pk_context *key );
+
+/**
+ * \brief           Set the MD algorithm to use for the signature
+ *                  (e.g. MBEDTLS_MD_SHA1)
+ *
+ * \param ctx       CSR context to use
+ * \param md_alg    MD algorithm to use
+ */
+void mbedtls_x509write_csr_set_md_alg( mbedtls_x509write_csr *ctx, mbedtls_md_type_t md_alg );
+
+/**
+ * \brief           Set the Key Usage Extension flags
+ *                  (e.g. MBEDTLS_X509_KU_DIGITAL_SIGNATURE | MBEDTLS_X509_KU_KEY_CERT_SIGN)
+ *
+ * \param ctx       CSR context to use
+ * \param key_usage key usage flags to set
+ *
+ * \return          0 if successful, or MBEDTLS_ERR_X509_ALLOC_FAILED
+ */
+int mbedtls_x509write_csr_set_key_usage( mbedtls_x509write_csr *ctx, unsigned char key_usage );
+
+/**
+ * \brief           Set the Netscape Cert Type flags
+ *                  (e.g. MBEDTLS_X509_NS_CERT_TYPE_SSL_CLIENT | MBEDTLS_X509_NS_CERT_TYPE_EMAIL)
+ *
+ * \param ctx           CSR context to use
+ * \param ns_cert_type  Netscape Cert Type flags to set
+ *
+ * \return          0 if successful, or MBEDTLS_ERR_X509_ALLOC_FAILED
+ */
+int mbedtls_x509write_csr_set_ns_cert_type( mbedtls_x509write_csr *ctx,
+                                    unsigned char ns_cert_type );
+
+/**
+ * \brief           Generic function to add to or replace an extension in the
+ *                  CSR
+ *
+ * \param ctx       CSR context to use
+ * \param oid       OID of the extension
+ * \param oid_len   length of the OID
+ * \param val       value of the extension OCTET STRING
+ * \param val_len   length of the value data
+ *
+ * \return          0 if successful, or a MBEDTLS_ERR_X509_ALLOC_FAILED
+ */
+int mbedtls_x509write_csr_set_extension( mbedtls_x509write_csr *ctx,
+                                 const char *oid, size_t oid_len,
+                                 const unsigned char *val, size_t val_len );
+
+/**
+ * \brief           Free the contents of a CSR context
+ *
+ * \param ctx       CSR context to free
+ */
+void mbedtls_x509write_csr_free( mbedtls_x509write_csr *ctx );
+
+/**
+ * \brief           Write a CSR (Certificate Signing Request) to a
+ *                  DER structure
+ *                  Note: data is written at the end of the buffer! Use the
+ *                        return value to determine where you should start
+ *                        using the buffer
+ *
+ * \param ctx       CSR to write away
+ * \param buf       buffer to write to
+ * \param size      size of the buffer
+ * \param f_rng     RNG function (for signature, see note)
+ * \param p_rng     RNG parameter
+ *
+ * \return          length of data written if successful, or a specific
+ *                  error code
+ *
+ * \note            f_rng may be NULL if RSA is used for signature and the
+ *                  signature is made offline (otherwise f_rng is desirable
+ *                  for countermeasures against timing attacks).
+ *                  ECDSA signatures always require a non-NULL f_rng.
+ */
+int mbedtls_x509write_csr_der( mbedtls_x509write_csr *ctx, unsigned char *buf, size_t size,
+                       int (*f_rng)(void *, unsigned char *, size_t),
+                       void *p_rng );
+
+#if defined(MBEDTLS_PEM_WRITE_C)
+/**
+ * \brief           Write a CSR (Certificate Signing Request) to a
+ *                  PEM string
+ *
+ * \param ctx       CSR to write away
+ * \param buf       buffer to write to
+ * \param size      size of the buffer
+ * \param f_rng     RNG function (for signature, see note)
+ * \param p_rng     RNG parameter
+ *
+ * \return          0 if successful, or a specific error code
+ *
+ * \note            f_rng may be NULL if RSA is used for signature and the
+ *                  signature is made offline (otherwise f_rng is desirable
+ *                  for couermeasures against timing attacks).
+ *                  ECDSA signatures always require a non-NULL f_rng.
+ */
+int mbedtls_x509write_csr_pem( mbedtls_x509write_csr *ctx, unsigned char *buf, size_t size,
+                       int (*f_rng)(void *, unsigned char *, size_t),
+                       void *p_rng );
+#endif /* MBEDTLS_PEM_WRITE_C */
+#endif /* MBEDTLS_X509_CSR_WRITE_C */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* mbedtls_x509_csr.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/xtea.h b/tools/sdk/include/mbedtls/mbedtls/xtea.h
new file mode 100644
index 00000000..b073f84e
--- /dev/null
+++ b/tools/sdk/include/mbedtls/mbedtls/xtea.h
@@ -0,0 +1,139 @@
+/**
+ * \file xtea.h
+ *
+ * \brief XTEA block cipher (32-bit)
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_XTEA_H
+#define MBEDTLS_XTEA_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#include 
+#include 
+
+#define MBEDTLS_XTEA_ENCRYPT     1
+#define MBEDTLS_XTEA_DECRYPT     0
+
+#define MBEDTLS_ERR_XTEA_INVALID_INPUT_LENGTH             -0x0028  /**< The data input has an invalid length. */
+
+#if !defined(MBEDTLS_XTEA_ALT)
+// Regular implementation
+//
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          XTEA context structure
+ */
+typedef struct
+{
+    uint32_t k[4];       /*!< key */
+}
+mbedtls_xtea_context;
+
+/**
+ * \brief          Initialize XTEA context
+ *
+ * \param ctx      XTEA context to be initialized
+ */
+void mbedtls_xtea_init( mbedtls_xtea_context *ctx );
+
+/**
+ * \brief          Clear XTEA context
+ *
+ * \param ctx      XTEA context to be cleared
+ */
+void mbedtls_xtea_free( mbedtls_xtea_context *ctx );
+
+/**
+ * \brief          XTEA key schedule
+ *
+ * \param ctx      XTEA context to be initialized
+ * \param key      the secret key
+ */
+void mbedtls_xtea_setup( mbedtls_xtea_context *ctx, const unsigned char key[16] );
+
+/**
+ * \brief          XTEA cipher function
+ *
+ * \param ctx      XTEA context
+ * \param mode     MBEDTLS_XTEA_ENCRYPT or MBEDTLS_XTEA_DECRYPT
+ * \param input    8-byte input block
+ * \param output   8-byte output block
+ *
+ * \return         0 if successful
+ */
+int mbedtls_xtea_crypt_ecb( mbedtls_xtea_context *ctx,
+                    int mode,
+                    const unsigned char input[8],
+                    unsigned char output[8] );
+
+#if defined(MBEDTLS_CIPHER_MODE_CBC)
+/**
+ * \brief          XTEA CBC cipher function
+ *
+ * \param ctx      XTEA context
+ * \param mode     MBEDTLS_XTEA_ENCRYPT or MBEDTLS_XTEA_DECRYPT
+ * \param length   the length of input, multiple of 8
+ * \param iv       initialization vector for CBC mode
+ * \param input    input block
+ * \param output   output block
+ *
+ * \return         0 if successful,
+ *                 MBEDTLS_ERR_XTEA_INVALID_INPUT_LENGTH if the length % 8 != 0
+ */
+int mbedtls_xtea_crypt_cbc( mbedtls_xtea_context *ctx,
+                    int mode,
+                    size_t length,
+                    unsigned char iv[8],
+                    const unsigned char *input,
+                    unsigned char *output);
+#endif /* MBEDTLS_CIPHER_MODE_CBC */
+
+#ifdef __cplusplus
+}
+#endif
+
+#else  /* MBEDTLS_XTEA_ALT */
+#include "xtea_alt.h"
+#endif /* MBEDTLS_XTEA_ALT */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          Checkup routine
+ *
+ * \return         0 if successful, or 1 if the test failed
+ */
+int mbedtls_xtea_self_test( int verbose );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* xtea.h */
diff --git a/tools/sdk/include/mbedtls/sha1_alt.h b/tools/sdk/include/mbedtls/sha1_alt.h
new file mode 100644
index 00000000..60297b9f
--- /dev/null
+++ b/tools/sdk/include/mbedtls/sha1_alt.h
@@ -0,0 +1,33 @@
+/*
+ * copyright (c) 2010 - 2012 Espressif System
+ *
+ */
+#ifndef _SHA1_ALT_H_
+#define _SHA1_ALT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(MBEDTLS_SHA1_ALT)
+
+#include "hwcrypto/sha.h"
+
+typedef esp_sha_context mbedtls_sha1_context;
+
+#define mbedtls_sha1_init       esp_sha1_init
+#define mbedtls_sha1_starts     esp_sha1_start
+#define mbedtls_sha1_clone      esp_sha1_clone
+#define mbedtls_sha1_update     esp_sha1_update
+#define mbedtls_sha1_finish     esp_sha1_finish
+#define mbedtls_sha1_free       esp_sha1_free
+#define mbedtls_sha1_process(...)
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/tools/sdk/include/mbedtls/sha256_alt.h b/tools/sdk/include/mbedtls/sha256_alt.h
new file mode 100644
index 00000000..6d9986b3
--- /dev/null
+++ b/tools/sdk/include/mbedtls/sha256_alt.h
@@ -0,0 +1,33 @@
+/*
+ * copyright (c) 2010 - 2012 Espressif System
+ *
+ */
+
+#ifndef _SHA256_ALT_H_
+#define _SHA256_ALT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(MBEDTLS_SHA256_ALT)
+
+#include "hwcrypto/sha.h"
+
+typedef esp_sha_context mbedtls_sha256_context;
+
+#define mbedtls_sha256_init     esp_sha256_init
+#define mbedtls_sha256_clone    esp_sha256_clone
+#define mbedtls_sha256_starts   esp_sha256_start
+#define mbedtls_sha256_update   esp_sha256_update
+#define mbedtls_sha256_finish   esp_sha256_finish
+#define mbedtls_sha256_free     esp_sha256_free
+#define mbedtls_sha256_process(...)
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* sha256.h */
diff --git a/tools/sdk/include/mbedtls/sha512_alt.h b/tools/sdk/include/mbedtls/sha512_alt.h
new file mode 100644
index 00000000..241f2be3
--- /dev/null
+++ b/tools/sdk/include/mbedtls/sha512_alt.h
@@ -0,0 +1,33 @@
+/*
+ * copyright (c) 2010 - 2012 Espressif System
+ *
+ * esf Link List Descriptor
+ */
+
+#ifndef _SHA512_ALT_H_
+#define _SHA512_ALT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(MBEDTLS_SHA512_ALT)
+#include "hwcrypto/sha.h"
+
+typedef esp_sha_context  mbedtls_sha512_context;
+
+#define mbedtls_sha512_init     esp_sha512_init
+#define mbedtls_sha512_clone    esp_sha512_clone
+#define mbedtls_sha512_starts   esp_sha512_start
+#define mbedtls_sha512_update   esp_sha512_update
+#define mbedtls_sha512_finish   esp_sha512_finish
+#define mbedtls_sha512_free     esp_sha512_free
+#define mbedtls_sha512_process(...)
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* sha512.h */
diff --git a/tools/sdk/include/newlib/_ansi.h b/tools/sdk/include/newlib/_ansi.h
new file mode 100644
index 00000000..5fb99070
--- /dev/null
+++ b/tools/sdk/include/newlib/_ansi.h
@@ -0,0 +1,140 @@
+/* Provide support for both ANSI and non-ANSI environments.  */
+
+/* Some ANSI environments are "broken" in the sense that __STDC__ cannot be
+   relied upon to have it's intended meaning.  Therefore we must use our own
+   concoction: _HAVE_STDC.  Always use _HAVE_STDC instead of __STDC__ in newlib
+   sources!
+
+   To get a strict ANSI C environment, define macro __STRICT_ANSI__.  This will
+   "comment out" the non-ANSI parts of the ANSI header files (non-ANSI header
+   files aren't affected).  */
+
+#ifndef	_ANSIDECL_H_
+#define	_ANSIDECL_H_
+
+#include 
+#include 
+
+/* First try to figure out whether we really are in an ANSI C environment.  */
+/* FIXME: This probably needs some work.  Perhaps sys/config.h can be
+   prevailed upon to give us a clue.  */
+
+#ifdef __STDC__
+#define _HAVE_STDC
+#endif
+
+/*  ISO C++.  */
+
+#ifdef __cplusplus
+#if !(defined(_BEGIN_STD_C) && defined(_END_STD_C))
+#ifdef _HAVE_STD_CXX
+#define _BEGIN_STD_C namespace std { extern "C" {
+#define _END_STD_C  } }
+#else
+#define _BEGIN_STD_C extern "C" {
+#define _END_STD_C  }
+#endif
+#if __GNUC_PREREQ (3, 3)
+#define _NOTHROW __attribute__ ((__nothrow__))
+#else
+#define _NOTHROW throw()
+#endif
+#endif
+#else
+#define _BEGIN_STD_C
+#define _END_STD_C
+#define _NOTHROW
+#endif
+
+#ifdef _HAVE_STDC
+#define	_PTR		void *
+#define	_AND		,
+#define	_NOARGS		void
+#define	_CONST		const
+#define	_VOLATILE	volatile
+#define	_SIGNED		signed
+#define	_DOTS		, ...
+#define _VOID void
+#ifdef __CYGWIN__
+#define	_EXFUN_NOTHROW(name, proto)	__cdecl name proto _NOTHROW
+#define	_EXFUN(name, proto)		__cdecl name proto
+#define	_EXPARM(name, proto)		(* __cdecl name) proto
+#define	_EXFNPTR(name, proto)		(__cdecl * name) proto
+#else
+#define	_EXFUN_NOTHROW(name, proto)	name proto _NOTHROW
+#define	_EXFUN(name, proto)		name proto
+#define _EXPARM(name, proto)		(* name) proto
+#define _EXFNPTR(name, proto)		(* name) proto
+#endif
+#define	_DEFUN(name, arglist, args)	name(args)
+#define	_DEFUN_VOID(name)		name(_NOARGS)
+#define _CAST_VOID (void)
+#ifndef _LONG_DOUBLE
+#define _LONG_DOUBLE long double
+#endif
+#ifndef _PARAMS
+#define _PARAMS(paramlist)		paramlist
+#endif
+#else	
+#define	_PTR		char *
+#define	_AND		;
+#define	_NOARGS
+#define	_CONST
+#define	_VOLATILE
+#define	_SIGNED
+#define	_DOTS
+#define _VOID void
+#define	_EXFUN(name, proto)		name()
+#define	_EXFUN_NOTHROW(name, proto)	name()
+#define	_DEFUN(name, arglist, args)	name arglist args;
+#define	_DEFUN_VOID(name)		name()
+#define _CAST_VOID
+#define _LONG_DOUBLE double
+#ifndef _PARAMS
+#define _PARAMS(paramlist)		()
+#endif
+#endif
+
+/* Support gcc's __attribute__ facility.  */
+
+#ifdef __GNUC__
+#define _ATTRIBUTE(attrs) __attribute__ (attrs)
+#else
+#define _ATTRIBUTE(attrs)
+#endif
+
+/*  The traditional meaning of 'extern inline' for GCC is not
+  to emit the function body unless the address is explicitly
+  taken.  However this behaviour is changing to match the C99
+  standard, which uses 'extern inline' to indicate that the
+  function body *must* be emitted.  Likewise, a function declared
+  without either 'extern' or 'static' defaults to extern linkage
+  (C99 6.2.2p5), and the compiler may choose whether to use the
+  inline version or call the extern linkage version (6.7.4p6).
+  If we are using GCC, but do not have the new behaviour, we need
+  to use extern inline; if we are using a new GCC with the
+  C99-compatible behaviour, or a non-GCC compiler (which we will
+  have to hope is C99, since there is no other way to achieve the
+  effect of omitting the function if it isn't referenced) we use
+  'static inline', which c99 defines to mean more-or-less the same
+  as the Gnu C 'extern inline'.  */
+#if defined(__GNUC__) && !defined(__GNUC_STDC_INLINE__)
+/* We're using GCC, but without the new C99-compatible behaviour.  */
+#define _ELIDABLE_INLINE extern __inline__ _ATTRIBUTE ((__always_inline__))
+#else
+/* We're using GCC in C99 mode, or an unknown compiler which
+  we just have to hope obeys the C99 semantics of inline.  */
+#define _ELIDABLE_INLINE static __inline__
+#endif
+
+#if __GNUC_PREREQ (3, 1)
+#define _NOINLINE		__attribute__ ((__noinline__))
+#define _NOINLINE_STATIC	_NOINLINE static
+#else
+/* On non-GNU compilers and GCC prior to version 3.1 the compiler can't be
+   trusted not to inline if it is static. */
+#define _NOINLINE
+#define _NOINLINE_STATIC
+#endif
+
+#endif /* _ANSIDECL_H_ */
diff --git a/tools/sdk/include/newlib/_syslist.h b/tools/sdk/include/newlib/_syslist.h
new file mode 100644
index 00000000..271644ef
--- /dev/null
+++ b/tools/sdk/include/newlib/_syslist.h
@@ -0,0 +1,40 @@
+/* internal use only -- mapping of "system calls" for libraries that lose
+   and only provide C names, so that we end up in violation of ANSI */
+#ifndef __SYSLIST_H
+#define __SYSLIST_H
+
+#ifdef MISSING_SYSCALL_NAMES
+#define _close close
+#define _execve execve
+#define _fcntl fcntl
+#define _fork fork
+#define _fstat fstat
+#define _getpid getpid
+#define _gettimeofday gettimeofday
+#define _isatty isatty
+#define _kill kill
+#define _link link
+#define _lseek lseek
+#define _mkdir mkdir
+#define _open open
+#define _read read
+#define _sbrk sbrk
+#define _stat stat
+#define _times times
+#define _unlink unlink
+#define _wait wait
+#define _write write
+#endif /* MISSING_SYSCALL_NAMES */
+
+#if defined MISSING_SYSCALL_NAMES || !defined HAVE_OPENDIR
+/* If the system call interface is missing opendir, readdir, and
+   closedir, there is an implementation of these functions in
+   libc/posix that is implemented using open, getdents, and close. 
+   Note, these functions are currently not in the libc/syscalls
+   directory.  */
+#define _opendir opendir
+#define _readdir readdir
+#define _closedir closedir
+#endif /* MISSING_SYSCALL_NAMES || !HAVE_OPENDIR */
+
+#endif /* !__SYSLIST_H_ */
diff --git a/tools/sdk/include/newlib/alloca.h b/tools/sdk/include/newlib/alloca.h
new file mode 100644
index 00000000..2ea0fd9b
--- /dev/null
+++ b/tools/sdk/include/newlib/alloca.h
@@ -0,0 +1,21 @@
+/* libc/include/alloca.h - Allocate memory on stack */
+
+/* Written 2000 by Werner Almesberger */
+/* Rearranged for general inclusion by stdlib.h.
+   2001, Corinna Vinschen  */
+
+#ifndef _NEWLIB_ALLOCA_H
+#define _NEWLIB_ALLOCA_H
+
+#include "_ansi.h"
+#include 
+
+#undef alloca
+
+#ifdef __GNUC__
+#define alloca(size) __builtin_alloca(size)
+#else
+void * _EXFUN(alloca,(size_t));
+#endif
+
+#endif
diff --git a/tools/sdk/include/newlib/ar.h b/tools/sdk/include/newlib/ar.h
new file mode 100644
index 00000000..ac2e4ca9
--- /dev/null
+++ b/tools/sdk/include/newlib/ar.h
@@ -0,0 +1,69 @@
+/*	$NetBSD: ar.h,v 1.4 1994/10/26 00:55:43 cgd Exp $	*/
+
+/*-
+ * Copyright (c) 1991, 1993
+ *	The Regents of the University of California.  All rights reserved.
+ * (c) UNIX System Laboratories, Inc.
+ * All or some portions of this file are derived from material licensed
+ * to the University of California by American Telephone and Telegraph
+ * Co. or Unix System Laboratories, Inc. and are reproduced herein with
+ * the permission of UNIX System Laboratories, Inc.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * Hugh Smith at The University of Guelph.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the University of
+ *	California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)ar.h	8.2 (Berkeley) 1/21/94
+ */
+
+#ifndef _AR_H_
+#define	_AR_H_
+
+/* Pre-4BSD archives had these magic numbers in them. */
+#define	OARMAG1	0177555
+#define	OARMAG2	0177545
+
+#define	ARMAG		"!\n"	/* ar "magic number" */
+#define	SARMAG		8		/* strlen(ARMAG); */
+
+#define	AR_EFMT1	"#1/"		/* extended format #1 */
+
+struct ar_hdr {
+	char ar_name[16];		/* name */
+	char ar_date[12];		/* modification time */
+	char ar_uid[6];			/* user id */
+	char ar_gid[6];			/* group id */
+	char ar_mode[8];		/* octal file permissions */
+	char ar_size[10];		/* size in bytes */
+#define	ARFMAG	"`\n"
+	char ar_fmag[2];		/* consistency check */
+};
+
+#endif /* !_AR_H_ */
diff --git a/tools/sdk/include/newlib/argz.h b/tools/sdk/include/newlib/argz.h
new file mode 100644
index 00000000..02c9adbf
--- /dev/null
+++ b/tools/sdk/include/newlib/argz.h
@@ -0,0 +1,33 @@
+/* Copyright (C) 2002 by  Red Hat, Incorporated. All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software
+ * is freely granted, provided that this notice is preserved.
+ */
+
+#ifndef _ARGZ_H_
+#define _ARGZ_H_
+
+#include 
+#include 
+
+#include "_ansi.h"
+
+_BEGIN_STD_C
+
+/* The newlib implementation of these functions assumes that sizeof(char) == 1. */
+error_t argz_create (char *const argv[], char **argz, size_t *argz_len);
+error_t argz_create_sep (const char *string, int sep, char **argz, size_t *argz_len);
+size_t argz_count (const char *argz, size_t argz_len);
+void argz_extract (char *argz, size_t argz_len, char **argv);
+void argz_stringify (char *argz, size_t argz_len, int sep);
+error_t argz_add (char **argz, size_t *argz_len, const char *str);
+error_t argz_add_sep (char **argz, size_t *argz_len, const char *str, int sep);
+error_t argz_append (char **argz, size_t *argz_len, const char *buf, size_t buf_len);
+error_t argz_delete (char **argz, size_t *argz_len, char *entry);
+error_t argz_insert (char **argz, size_t *argz_len, char *before, const char *entry);
+char * argz_next (char *argz, size_t argz_len, const char *entry);
+error_t argz_replace (char **argz, size_t *argz_len, const char *str, const char *with, unsigned *replace_count);
+
+_END_STD_C
+
+#endif /* _ARGZ_H_ */
diff --git a/tools/sdk/include/newlib/assert.h b/tools/sdk/include/newlib/assert.h
new file mode 100644
index 00000000..91bb040c
--- /dev/null
+++ b/tools/sdk/include/newlib/assert.h
@@ -0,0 +1,50 @@
+/*
+	assert.h
+*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "_ansi.h"
+
+#undef assert
+
+#ifdef NDEBUG           /* required by ANSI standard */
+# define assert(__e) ((void)0)
+#else
+# define assert(__e) ((__e) ? (void)0 : __assert_func (__FILE__, __LINE__, \
+						       __ASSERT_FUNC, #__e))
+
+# ifndef __ASSERT_FUNC
+  /* Use g++'s demangled names in C++.  */
+#  if defined __cplusplus && defined __GNUC__
+#   define __ASSERT_FUNC __PRETTY_FUNCTION__
+
+  /* C99 requires the use of __func__.  */
+#  elif __STDC_VERSION__ >= 199901L
+#   define __ASSERT_FUNC __func__
+
+  /* Older versions of gcc don't have __func__ but can use __FUNCTION__.  */
+#  elif __GNUC__ >= 2
+#   define __ASSERT_FUNC __FUNCTION__
+
+  /* failed to detect __func__ support.  */
+#  else
+#   define __ASSERT_FUNC ((char *) 0)
+#  endif
+# endif /* !__ASSERT_FUNC */
+#endif /* !NDEBUG */
+
+void _EXFUN(__assert, (const char *, int, const char *)
+	    _ATTRIBUTE ((__noreturn__)));
+void _EXFUN(__assert_func, (const char *, int, const char *, const char *)
+	    _ATTRIBUTE ((__noreturn__)));
+
+#if __STDC_VERSION__ >= 201112L && !defined __cplusplus
+# define static_assert _Static_assert
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tools/sdk/include/newlib/complex.h b/tools/sdk/include/newlib/complex.h
new file mode 100644
index 00000000..969b20e5
--- /dev/null
+++ b/tools/sdk/include/newlib/complex.h
@@ -0,0 +1,124 @@
+/* $NetBSD: complex.h,v 1.3 2010/09/15 16:11:30 christos Exp $ */
+
+/*
+ * Written by Matthias Drochner.
+ * Public domain.
+ */
+
+#ifndef	_COMPLEX_H
+#define	_COMPLEX_H
+
+#define complex _Complex
+#define _Complex_I 1.0fi
+#define I _Complex_I
+
+#include 
+
+__BEGIN_DECLS
+
+/* 7.3.5 Trigonometric functions */
+/* 7.3.5.1 The cacos functions */
+double complex cacos(double complex);
+float complex cacosf(float complex);
+
+/* 7.3.5.2 The casin functions */
+double complex casin(double complex);
+float complex casinf(float complex);
+
+/* 7.3.5.1 The catan functions */
+double complex catan(double complex);
+float complex catanf(float complex);
+
+/* 7.3.5.1 The ccos functions */
+double complex ccos(double complex);
+float complex ccosf(float complex);
+
+/* 7.3.5.1 The csin functions */
+double complex csin(double complex);
+float complex csinf(float complex);
+
+/* 7.3.5.1 The ctan functions */
+double complex ctan(double complex);
+float complex ctanf(float complex);
+
+/* 7.3.6 Hyperbolic functions */
+/* 7.3.6.1 The cacosh functions */
+double complex cacosh(double complex);
+float complex cacoshf(float complex);
+
+/* 7.3.6.2 The casinh functions */
+double complex casinh(double complex);
+float complex casinhf(float complex);
+
+/* 7.3.6.3 The catanh functions */
+double complex catanh(double complex);
+float complex catanhf(float complex);
+
+/* 7.3.6.4 The ccosh functions */
+double complex ccosh(double complex);
+float complex ccoshf(float complex);
+
+/* 7.3.6.5 The csinh functions */
+double complex csinh(double complex);
+float complex csinhf(float complex);
+
+/* 7.3.6.6 The ctanh functions */
+double complex ctanh(double complex);
+float complex ctanhf(float complex);
+
+/* 7.3.7 Exponential and logarithmic functions */
+/* 7.3.7.1 The cexp functions */
+double complex cexp(double complex);
+float complex cexpf(float complex);
+
+/* 7.3.7.2 The clog functions */
+double complex clog(double complex);
+float complex clogf(float complex);
+
+/* 7.3.8 Power and absolute-value functions */
+/* 7.3.8.1 The cabs functions */
+/*#ifndef __LIBM0_SOURCE__ */
+/* avoid conflict with historical cabs(struct complex) */
+/* double cabs(double complex) __RENAME(__c99_cabs);
+   float cabsf(float complex) __RENAME(__c99_cabsf);
+   #endif
+*/
+double cabs(double complex) ;
+float cabsf(float complex) ;
+
+/* 7.3.8.2 The cpow functions */
+double complex cpow(double complex, double complex);
+float complex cpowf(float complex, float complex);
+
+/* 7.3.8.3 The csqrt functions */
+double complex csqrt(double complex);
+float complex csqrtf(float complex);
+
+/* 7.3.9 Manipulation functions */
+/* 7.3.9.1 The carg functions */ 
+double carg(double complex);
+float cargf(float complex);
+
+/* 7.3.9.2 The cimag functions */
+double cimag(double complex);
+float cimagf(float complex);
+/*long double cimagl(long double complex); */
+
+/* 7.3.9.3 The conj functions */
+double complex conj(double complex);
+float complex conjf(float complex);
+/*long double complex conjl(long double complex); */
+
+/* 7.3.9.4 The cproj functions */
+double complex cproj(double complex);
+float complex cprojf(float complex);
+/*long double complex cprojl(long double complex); */
+
+/* 7.3.9.5 The creal functions */
+double creal(double complex);
+float crealf(float complex);
+/*long double creall(long double complex); */
+
+__END_DECLS
+
+#endif	/* ! _COMPLEX_H */
diff --git a/tools/sdk/include/newlib/config.h b/tools/sdk/include/newlib/config.h
new file mode 100644
index 00000000..69d49adf
--- /dev/null
+++ b/tools/sdk/include/newlib/config.h
@@ -0,0 +1,28 @@
+#ifndef __SYS_CONFIG_H__
+#define __SYS_CONFIG_H__
+
+#include   /* floating point macros */
+#include 	/* POSIX defs */
+
+#ifndef __EXPORT
+#define __EXPORT
+#endif
+
+#ifndef __IMPORT
+#define __IMPORT
+#endif
+
+/* Define return type of read/write routines.  In POSIX, the return type
+   for read()/write() is "ssize_t" but legacy newlib code has been using
+   "int" for some time.  If not specified, "int" is defaulted.  */
+#ifndef _READ_WRITE_RETURN_TYPE
+#define _READ_WRITE_RETURN_TYPE int
+#endif
+/* Define `count' parameter of read/write routines.  In POSIX, the `count'
+   parameter is "size_t" but legacy newlib code has been using "int" for some
+   time.  If not specified, "int" is defaulted.  */
+#ifndef _READ_WRITE_BUFSIZE_TYPE
+#define _READ_WRITE_BUFSIZE_TYPE int
+#endif
+
+#endif /* __SYS_CONFIG_H__ */
diff --git a/tools/sdk/include/newlib/ctype.h b/tools/sdk/include/newlib/ctype.h
new file mode 100644
index 00000000..1eb3f787
--- /dev/null
+++ b/tools/sdk/include/newlib/ctype.h
@@ -0,0 +1,113 @@
+#ifndef _CTYPE_H_
+#define _CTYPE_H_
+
+#include "_ansi.h"
+
+_BEGIN_STD_C
+
+int _EXFUN(isalnum, (int __c));
+int _EXFUN(isalpha, (int __c));
+int _EXFUN(iscntrl, (int __c));
+int _EXFUN(isdigit, (int __c));
+int _EXFUN(isgraph, (int __c));
+int _EXFUN(islower, (int __c));
+int _EXFUN(isprint, (int __c));
+int _EXFUN(ispunct, (int __c));
+int _EXFUN(isspace, (int __c));
+int _EXFUN(isupper, (int __c));
+int _EXFUN(isxdigit,(int __c));
+int _EXFUN(tolower, (int __c));
+int _EXFUN(toupper, (int __c));
+
+#if !defined(__STRICT_ANSI__) || defined(__cplusplus) || __STDC_VERSION__ >= 199901L
+int _EXFUN(isblank, (int __c));
+#endif
+
+#ifndef __STRICT_ANSI__
+int _EXFUN(isascii, (int __c));
+int _EXFUN(toascii, (int __c));
+#define _tolower(__c) ((unsigned char)(__c) - 'A' + 'a')
+#define _toupper(__c) ((unsigned char)(__c) - 'a' + 'A')
+#endif
+
+#define	_U	01
+#define	_L	02
+#define	_N	04
+#define	_S	010
+#define _P	020
+#define _C	040
+#define _X	0100
+#define	_B	0200
+
+#ifndef _MB_CAPABLE
+_CONST
+#endif
+extern	__IMPORT char	* _CONST __ctype_ptr__;
+
+#ifndef __cplusplus
+/* These macros are intentionally written in a manner that will trigger
+   a gcc -Wall warning if the user mistakenly passes a 'char' instead
+   of an int containing an 'unsigned char'.  Note that the sizeof will
+   always be 1, which is what we want for mapping EOF to __ctype_ptr__[0];
+   the use of a raw index inside the sizeof triggers the gcc warning if
+   __c was of type char, and sizeof masks side effects of the extra __c.
+   Meanwhile, the real index to __ctype_ptr__+1 must be cast to int,
+   since isalpha(0x100000001LL) must equal isalpha(1), rather than being
+   an out-of-bounds reference on a 64-bit machine.  */
+#define __ctype_lookup(__c) ((__ctype_ptr__+sizeof(""[__c]))[(int)(__c)])
+
+#define	isalpha(__c)	(__ctype_lookup(__c)&(_U|_L))
+#define	isupper(__c)	((__ctype_lookup(__c)&(_U|_L))==_U)
+#define	islower(__c)	((__ctype_lookup(__c)&(_U|_L))==_L)
+#define	isdigit(__c)	(__ctype_lookup(__c)&_N)
+#define	isxdigit(__c)	(__ctype_lookup(__c)&(_X|_N))
+#define	isspace(__c)	(__ctype_lookup(__c)&_S)
+#define ispunct(__c)	(__ctype_lookup(__c)&_P)
+#define isalnum(__c)	(__ctype_lookup(__c)&(_U|_L|_N))
+#define isprint(__c)	(__ctype_lookup(__c)&(_P|_U|_L|_N|_B))
+#define	isgraph(__c)	(__ctype_lookup(__c)&(_P|_U|_L|_N))
+#define iscntrl(__c)	(__ctype_lookup(__c)&_C)
+
+#if defined(__GNUC__) && \
+    (!defined(__STRICT_ANSI__) || __STDC_VERSION__ >= 199901L)
+#define isblank(__c) \
+  __extension__ ({ __typeof__ (__c) __x = (__c);		\
+        (__ctype_lookup(__x)&_B) || (int) (__x) == '\t';})
+#endif
+
+
+/* Non-gcc versions will get the library versions, and will be
+   slightly slower.  These macros are not NLS-aware so they are
+   disabled if the system supports the extended character sets. */
+# if defined(__GNUC__)
+#  if !defined (_MB_EXTENDED_CHARSETS_ISO) && !defined (_MB_EXTENDED_CHARSETS_WINDOWS)
+#   define toupper(__c) \
+  __extension__ ({ __typeof__ (__c) __x = (__c);	\
+      islower (__x) ? (int) __x - 'a' + 'A' : (int) __x;})
+#   define tolower(__c) \
+  __extension__ ({ __typeof__ (__c) __x = (__c);	\
+      isupper (__x) ? (int) __x - 'A' + 'a' : (int) __x;})
+#  else /* _MB_EXTENDED_CHARSETS* */
+/* Allow a gcc warning if the user passed 'char', but defer to the
+   function.  */
+#   define toupper(__c) \
+  __extension__ ({ __typeof__ (__c) __x = (__c);	\
+      (void) __ctype_ptr__[__x]; (toupper) (__x);})
+#   define tolower(__c) \
+  __extension__ ({ __typeof__ (__c) __x = (__c);	\
+      (void) __ctype_ptr__[__x]; (tolower) (__x);})
+#  endif /* _MB_EXTENDED_CHARSETS* */
+# endif /* __GNUC__ */
+#endif /* !__cplusplus */
+
+#ifndef __STRICT_ANSI__
+#define isascii(__c)	((unsigned)(__c)<=0177)
+#define toascii(__c)	((__c)&0177)
+#endif
+
+/* For C++ backward-compatibility only.  */
+extern	__IMPORT _CONST char	_ctype_[];
+
+_END_STD_C
+
+#endif /* _CTYPE_H_ */
diff --git a/tools/sdk/include/newlib/dirent.h b/tools/sdk/include/newlib/dirent.h
new file mode 100644
index 00000000..6fefc03c
--- /dev/null
+++ b/tools/sdk/include/newlib/dirent.h
@@ -0,0 +1,15 @@
+#ifndef _DIRENT_H_
+#define _DIRENT_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include 
+
+#if !defined(MAXNAMLEN) && !defined(_POSIX_SOURCE)
+#define MAXNAMLEN 1024
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*_DIRENT_H_*/
diff --git a/tools/sdk/include/newlib/envlock.h b/tools/sdk/include/newlib/envlock.h
new file mode 100644
index 00000000..9bb6a813
--- /dev/null
+++ b/tools/sdk/include/newlib/envlock.h
@@ -0,0 +1,15 @@
+/* envlock.h -- header file for env routines.  */
+
+#ifndef _INCLUDE_ENVLOCK_H_
+#define _INCLUDE_ENVLOCK_H_
+
+#include <_ansi.h>
+#include 
+
+#define ENV_LOCK __env_lock(reent_ptr)
+#define ENV_UNLOCK __env_unlock(reent_ptr)
+
+void _EXFUN(__env_lock,(struct _reent *reent));
+void _EXFUN(__env_unlock,(struct _reent *reent));
+
+#endif /* _INCLUDE_ENVLOCK_H_ */
diff --git a/tools/sdk/include/newlib/envz.h b/tools/sdk/include/newlib/envz.h
new file mode 100644
index 00000000..e6a31c31
--- /dev/null
+++ b/tools/sdk/include/newlib/envz.h
@@ -0,0 +1,16 @@
+/* Copyright (C) 2002 by  Red Hat, Incorporated. All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software
+ * is freely granted, provided that this notice is preserved.
+ */
+
+#include 
+#include 
+
+/* The newlib implementation of these functions assumes that sizeof(char) == 1. */
+char * envz_entry (const char *envz, size_t envz_len, const char *name);
+char * envz_get (const char *envz, size_t envz_len, const char *name);
+error_t envz_add (char **envz, size_t *envz_len, const char *name, const char *value);
+error_t envz_merge (char **envz, size_t *envz_len, const char *envz2, size_t envz2_len, int override);
+void envz_remove(char **envz, size_t *envz_len, const char *name);
+void envz_strip (char **envz, size_t *envz_len);
diff --git a/tools/sdk/include/newlib/errno.h b/tools/sdk/include/newlib/errno.h
new file mode 100644
index 00000000..7cc2ca86
--- /dev/null
+++ b/tools/sdk/include/newlib/errno.h
@@ -0,0 +1,11 @@
+#ifndef __ERRNO_H__
+#define __ERRNO_H__
+
+#ifndef __error_t_defined
+typedef int error_t;
+#define __error_t_defined 1
+#endif
+
+#include 
+
+#endif /* !__ERRNO_H__ */
diff --git a/tools/sdk/include/newlib/fastmath.h b/tools/sdk/include/newlib/fastmath.h
new file mode 100644
index 00000000..95eea5f3
--- /dev/null
+++ b/tools/sdk/include/newlib/fastmath.h
@@ -0,0 +1,13 @@
+#ifndef _FASTMATH_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+#define _FASTMATH_H_
+
+#include 
+#include 
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FASTMATH_H_ */
diff --git a/tools/sdk/include/newlib/fcntl.h b/tools/sdk/include/newlib/fcntl.h
new file mode 100644
index 00000000..86a91677
--- /dev/null
+++ b/tools/sdk/include/newlib/fcntl.h
@@ -0,0 +1 @@
+#include 
diff --git a/tools/sdk/include/newlib/fenv.h b/tools/sdk/include/newlib/fenv.h
new file mode 100644
index 00000000..2fa76f75
--- /dev/null
+++ b/tools/sdk/include/newlib/fenv.h
@@ -0,0 +1,88 @@
+/* Copyright (c) 2011 Tensilica Inc.  ALL RIGHTS RESERVED.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+   1. Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+
+   2. Redistributions in binary form must reproduce the above
+      copyright notice, this list of conditions and the following
+      disclaimer in the documentation and/or other materials provided
+      with the distribution.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+   FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+   TENSILICA INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT,
+   INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+   SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+   STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+   OF THE POSSIBILITY OF SUCH DAMAGE.  */
+
+
+#ifndef _FENV_H
+#define _FENV_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef unsigned long fenv_t;
+typedef unsigned long fexcept_t;
+
+#define FE_DIVBYZERO   0x08
+#define FE_INEXACT     0x01
+#define FE_INVALID     0x10
+#define FE_OVERFLOW    0x04
+#define FE_UNDERFLOW   0x02
+
+#define FE_ALL_EXCEPT \
+  (FE_DIVBYZERO  |		      \
+   FE_INEXACT    |		      \
+   FE_INVALID    |		      \
+   FE_OVERFLOW   |		      \
+   FE_UNDERFLOW)
+
+#define FE_DOWNWARD   0x3
+#define FE_TONEAREST  0x0
+#define FE_TOWARDZERO 0x1
+#define FE_UPWARD     0x2
+
+#define FE_DFL_ENV ((const fenv_t *) 0)
+
+int  feclearexcept(int);
+int  fegetexceptflag(fexcept_t *, int);
+int  feraiseexcept(int);
+int  fesetexceptflag(const fexcept_t *, int);
+int  fetestexcept(int);
+int  fegetround(void);
+int  fesetround(int);
+int  fegetenv(fenv_t *);
+int  feholdexcept(fenv_t *);
+int  fesetenv(const fenv_t *);
+int  feupdateenv(const fenv_t *);
+
+/* glibc extensions  */
+int feenableexcept(int excepts);
+int fedisableexcept(int excepts);
+int fegetexcept(void);
+
+#define _FE_EXCEPTION_FLAGS_OFFSET 7
+#define _FE_EXCEPTION_FLAG_MASK (FE_ALL_EXCEPT << _FE_EXCEPTION_FLAGS_OFFSET)
+#define _FE_EXCEPTION_ENABLE_OFFSET 2
+#define _FE_EXCEPTION_ENABLE_MASK (FE_ALL_EXCEPT << _FE_EXCEPTION_ENABLE_OFFSET)
+#define _FE_ROUND_MODE_OFFSET 0
+#define _FE_ROUND_MODE_MASK (0x3 << _FE_ROUND_MODE_OFFSET)
+#define _FE_FLOATING_ENV_MASK (_FE_EXCEPTION_FLAG_MASK | _FE_EXCEPTION_ENABLE_MASK | _FE_ROUND_MODE_MASK)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tools/sdk/include/newlib/fnmatch.h b/tools/sdk/include/newlib/fnmatch.h
new file mode 100644
index 00000000..06311fc4
--- /dev/null
+++ b/tools/sdk/include/newlib/fnmatch.h
@@ -0,0 +1,55 @@
+/*-
+ * Copyright (c) 1992, 1993
+ *	The Regents of the University of California.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: src/include/fnmatch.h,v 1.10 2002/03/23 17:24:53 imp Exp $
+ *	@(#)fnmatch.h	8.1 (Berkeley) 6/2/93
+ */
+
+#ifndef	_FNMATCH_H_
+#define	_FNMATCH_H_
+
+#define	FNM_NOMATCH	1	/* Match failed. */
+
+#define	FNM_NOESCAPE	0x01	/* Disable backslash escaping. */
+#define	FNM_PATHNAME	0x02	/* Slash must be matched by slash. */
+#define	FNM_PERIOD	0x04	/* Period must be matched by period. */
+
+#if defined(_GNU_SOURCE) || !defined(_ANSI_SOURCE) && !defined(_POSIX_SOURCE)
+#define	FNM_LEADING_DIR	0x08	/* Ignore / after Imatch. */
+#define	FNM_CASEFOLD	0x10	/* Case insensitive search. */
+#define	FNM_IGNORECASE	FNM_CASEFOLD
+#define	FNM_FILE_NAME	FNM_PATHNAME
+#endif
+
+#include 
+
+__BEGIN_DECLS
+int	 fnmatch(const char *, const char *, int);
+__END_DECLS
+
+#endif /* !_FNMATCH_H_ */
diff --git a/tools/sdk/include/newlib/getopt.h b/tools/sdk/include/newlib/getopt.h
new file mode 100644
index 00000000..e12d253d
--- /dev/null
+++ b/tools/sdk/include/newlib/getopt.h
@@ -0,0 +1,190 @@
+/****************************************************************************
+
+getopt.h - Read command line options
+
+AUTHOR: Gregory Pietsch
+CREATED Thu Jan 09 22:37:00 1997
+
+DESCRIPTION:
+
+The getopt() function parses the command line arguments.  Its arguments argc
+and argv are the argument count and array as passed to the main() function
+on program invocation.  The argument optstring is a list of available option
+characters.  If such a character is followed by a colon (`:'), the option
+takes an argument, which is placed in optarg.  If such a character is
+followed by two colons, the option takes an optional argument, which is
+placed in optarg.  If the option does not take an argument, optarg is NULL.
+
+The external variable optind is the index of the next array element of argv
+to be processed; it communicates from one call to the next which element to
+process.
+
+The getopt_long() function works like getopt() except that it also accepts
+long options started by two dashes `--'.  If these take values, it is either
+in the form
+
+--arg=value
+
+ or
+
+--arg value
+
+It takes the additional arguments longopts which is a pointer to the first
+element of an array of type GETOPT_LONG_OPTION_T, defined below.  The last
+element of the array has to be filled with NULL for the name field.
+
+The longind pointer points to the index of the current long option relative
+to longopts if it is non-NULL.
+
+The getopt() function returns the option character if the option was found
+successfully, `:' if there was a missing parameter for one of the options,
+`?' for an unknown option character, and EOF for the end of the option list.
+
+The getopt_long() function's return value is described below.
+
+The function getopt_long_only() is identical to getopt_long(), except that a
+plus sign `+' can introduce long options as well as `--'.
+
+Describe how to deal with options that follow non-option ARGV-elements.
+
+If the caller did not specify anything, the default is REQUIRE_ORDER if the
+environment variable POSIXLY_CORRECT is defined, PERMUTE otherwise.
+
+REQUIRE_ORDER means don't recognize them as options; stop option processing
+when the first non-option is seen.  This is what Unix does.  This mode of
+operation is selected by either setting the environment variable
+POSIXLY_CORRECT, or using `+' as the first character of the optstring
+parameter.
+
+PERMUTE is the default.  We permute the contents of ARGV as we scan, so that
+eventually all the non-options are at the end.  This allows options to be
+given in any order, even with programs that were not written to expect this.
+
+RETURN_IN_ORDER is an option available to programs that were written to
+expect options and other ARGV-elements in any order and that care about the
+ordering of the two.  We describe each non-option ARGV-element as if it were
+the argument of an option with character code 1.  Using `-' as the first
+character of the optstring parameter selects this mode of operation.
+
+The special argument `--' forces an end of option-scanning regardless of the
+value of `ordering'.  In the case of RETURN_IN_ORDER, only `--' can cause
+getopt() and friends to return EOF with optind != argc.
+
+COPYRIGHT NOTICE AND DISCLAIMER:
+
+Copyright (C) 1997 Gregory Pietsch
+
+This file and the accompanying getopt.c implementation file are hereby 
+placed in the public domain without restrictions.  Just give the author 
+credit, don't claim you wrote it or prevent anyone else from using it.
+
+Gregory Pietsch's current e-mail address:
+gpietsch@comcast.net
+****************************************************************************/
+
+/* This is a glibc-extension header file. */
+
+#ifndef GETOPT_H
+#define GETOPT_H
+
+#include <_ansi.h>
+
+/* include files needed by this include file */
+
+#define no_argument		0
+#define required_argument	1
+#define optional_argument	2
+
+#ifdef __cplusplus
+extern "C"
+{
+
+#endif				/* __cplusplus */
+
+/* types defined by this include file */
+  struct option
+  {
+    const char *name;		/* the name of the long option */
+    int has_arg;		/* one of the above macros */
+    int *flag;			/* determines if getopt_long() returns a
+				 * value for a long option; if it is
+				 * non-NULL, 0 is returned as a function
+				 * value and the value of val is stored in
+				 * the area pointed to by flag.  Otherwise,
+				 * val is returned. */
+    int val;			/* determines the value to return if flag is
+				 * NULL. */
+
+  };
+
+/* While getopt.h is a glibc extension, the following are newlib extensions.
+ * They are optionally included via the __need_getopt_newlib flag.  */
+
+#ifdef __need_getopt_newlib
+
+  /* macros defined by this include file */
+  #define NO_ARG          	no_argument
+  #define REQUIRED_ARG    	required_argument
+  #define OPTIONAL_ARG    	optional_argument
+
+  /* The GETOPT_DATA_INITIALIZER macro is used to initialize a statically-
+     allocated variable of type struct getopt_data.  */
+  #define GETOPT_DATA_INITIALIZER	{0,0,0,0,0}
+
+  /* These #defines are to make accessing the reentrant functions easier.  */
+  #define getopt_r		__getopt_r
+  #define getopt_long_r		__getopt_long_r
+  #define getopt_long_only_r	__getopt_long_only_r
+
+  /* The getopt_data structure is for reentrancy. Its members are similar to
+     the externally-defined variables.  */
+  typedef struct getopt_data
+  {
+    char *optarg;
+    int optind, opterr, optopt, optwhere;
+  } getopt_data;
+
+#endif /* __need_getopt_newlib */
+
+  /* externally-defined variables */
+  extern char *optarg;
+  extern int optind;
+  extern int opterr;
+  extern int optopt;
+
+  /* function prototypes */
+  int _EXFUN (getopt,
+	      (int __argc, char *const __argv[], const char *__optstring));
+
+  int _EXFUN (getopt_long,
+	      (int __argc, char *const __argv[], const char *__shortopts,
+	       const struct option * __longopts, int *__longind));
+
+  int _EXFUN (getopt_long_only,
+	      (int __argc, char *const __argv[], const char *__shortopts,
+	       const struct option * __longopts, int *__longind));
+
+#ifdef __need_getopt_newlib
+  int _EXFUN (__getopt_r,
+	      (int __argc, char *const __argv[], const char *__optstring,
+	       struct getopt_data * __data));
+
+  int _EXFUN (__getopt_long_r,
+	      (int __argc, char *const __argv[], const char *__shortopts,
+	       const struct option * __longopts, int *__longind,
+	       struct getopt_data * __data));
+
+  int _EXFUN (__getopt_long_only_r,
+	      (int __argc, char *const __argv[], const char *__shortopts,
+	       const struct option * __longopts, int *__longind,
+	       struct getopt_data * __data));
+#endif /* __need_getopt_newlib */
+
+#ifdef __cplusplus
+};
+
+#endif /* __cplusplus  */
+
+#endif /* GETOPT_H */
+
+/* END OF FILE getopt.h */
diff --git a/tools/sdk/include/newlib/glob.h b/tools/sdk/include/newlib/glob.h
new file mode 100644
index 00000000..7a300e69
--- /dev/null
+++ b/tools/sdk/include/newlib/glob.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 1989, 1993
+ *	The Regents of the University of California.  All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * Guido van Rossum.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)glob.h	8.1 (Berkeley) 6/2/93
+ * $FreeBSD: src/include/glob.h,v 1.6 2002/03/23 17:24:53 imp Exp $
+ */
+
+#ifndef _GLOB_H_
+#define	_GLOB_H_
+
+#include 
+
+struct stat;
+typedef struct {
+	int gl_pathc;		/* Count of total paths so far. */
+	int gl_matchc;		/* Count of paths matching pattern. */
+	int gl_offs;		/* Reserved at beginning of gl_pathv. */
+	int gl_flags;		/* Copy of flags parameter to glob. */
+	char **gl_pathv;	/* List of paths matching pattern. */
+				/* Copy of errfunc parameter to glob. */
+	int (*gl_errfunc)(const char *, int);
+
+	/*
+	 * Alternate filesystem access methods for glob; replacement
+	 * versions of closedir(3), readdir(3), opendir(3), stat(2)
+	 * and lstat(2).
+	 */
+	void (*gl_closedir)(void *);
+	struct dirent *(*gl_readdir)(void *);
+	void *(*gl_opendir)(const char *);
+	int (*gl_lstat)(const char *, struct stat *);
+	int (*gl_stat)(const char *, struct stat *);
+} glob_t;
+
+#define	GLOB_APPEND	0x0001	/* Append to output from previous call. */
+#define	GLOB_DOOFFS	0x0002	/* Use gl_offs. */
+#define	GLOB_ERR	0x0004	/* Return on error. */
+#define	GLOB_MARK	0x0008	/* Append / to matching directories. */
+#define	GLOB_NOCHECK	0x0010	/* Return pattern itself if nothing matches. */
+#define	GLOB_NOSORT	0x0020	/* Don't sort. */
+
+#define	GLOB_ALTDIRFUNC	0x0040	/* Use alternately specified directory funcs. */
+#define	GLOB_BRACE	0x0080	/* Expand braces ala csh. */
+#define	GLOB_MAGCHAR	0x0100	/* Pattern had globbing characters. */
+#define	GLOB_NOMAGIC	0x0200	/* GLOB_NOCHECK without magic chars (csh). */
+#define	GLOB_QUOTE	0x0400	/* Quote special chars with \. */
+#define	GLOB_TILDE	0x0800	/* Expand tilde names from the passwd file. */
+#define	GLOB_LIMIT	0x1000	/* limit number of returned paths */
+
+/* backwards compatibility, this is the old name for this option */
+#define GLOB_MAXPATH	GLOB_LIMIT
+
+#define	GLOB_NOSPACE	(-1)	/* Malloc call failed. */
+#define	GLOB_ABEND	(-2)	/* Unignored error. */
+
+__BEGIN_DECLS
+int	glob(const char *__restrict, int, int (*)(const char *, int), 
+		glob_t *__restrict);
+void	globfree(glob_t *);
+__END_DECLS
+
+#endif /* !_GLOB_H_ */
diff --git a/tools/sdk/include/newlib/grp.h b/tools/sdk/include/newlib/grp.h
new file mode 100644
index 00000000..c3a5a676
--- /dev/null
+++ b/tools/sdk/include/newlib/grp.h
@@ -0,0 +1,95 @@
+/*	$NetBSD: grp.h,v 1.7 1995/04/29 05:30:40 cgd Exp $	*/
+
+/*-
+ * Copyright (c) 1989, 1993
+ *	The Regents of the University of California.  All rights reserved.
+ * (c) UNIX System Laboratories, Inc.
+ * All or some portions of this file are derived from material licensed
+ * to the University of California by American Telephone and Telegraph
+ * Co. or Unix System Laboratories, Inc. and are reproduced herein with
+ * the permission of UNIX System Laboratories, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the University of
+ *	California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)grp.h	8.2 (Berkeley) 1/21/94
+ */
+
+#ifndef _GRP_H_
+#define	_GRP_H_
+
+#include 
+#include 
+#ifdef __CYGWIN__
+#include 
+#endif
+
+#if !defined(_POSIX_SOURCE) && !defined(_XOPEN_SOURCE)
+#define	_PATH_GROUP		"/etc/group"
+#endif
+
+struct group {
+	char	*gr_name;		/* group name */
+	char	*gr_passwd;		/* group password */
+	gid_t	gr_gid;			/* group id */
+	char	**gr_mem;		/* group members */
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef __INSIDE_CYGWIN__
+struct group	*getgrgid (gid_t);
+struct group	*getgrnam (const char *);
+int		 getgrnam_r (const char *, struct group *,
+			char *, size_t, struct group **);
+int		 getgrgid_r (gid_t, struct group *,
+			char *, size_t, struct group **);
+#ifndef _POSIX_SOURCE
+struct group	*getgrent (void);
+void		 setgrent (void);
+void		 endgrent (void);
+#ifndef __CYGWIN__
+void		 setgrfile (const char *);
+#endif /* !__CYGWIN__ */
+#ifndef _XOPEN_SOURCE
+#ifndef __CYGWIN__
+char		*group_from_gid (gid_t, int);
+int		 setgroupent (int);
+#endif /* !__CYGWIN__ */
+int		 initgroups (const char *, gid_t);
+#endif /* !_XOPEN_SOURCE */
+#endif /* !_POSIX_SOURCE */
+#endif /* !__INSIDE_CYGWIN__ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !_GRP_H_ */
diff --git a/tools/sdk/include/newlib/iconv.h b/tools/sdk/include/newlib/iconv.h
new file mode 100644
index 00000000..4c023e9d
--- /dev/null
+++ b/tools/sdk/include/newlib/iconv.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2003-2004, Artem B. Bityuckiy, SoftMine Corporation.
+ * Rights transferred to Franklin Electronic Publishers.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+#ifndef _ICONV_H_
+#define _ICONV_H_
+
+#include <_ansi.h>
+#include 
+#include 
+#include 
+
+/* iconv_t: charset conversion descriptor type */
+typedef _iconv_t iconv_t;
+
+_BEGIN_STD_C
+
+#ifndef _REENT_ONLY
+iconv_t
+_EXFUN(iconv_open, (_CONST char *, _CONST char *));
+
+size_t
+_EXFUN(iconv, (iconv_t, char **__restrict, size_t *__restrict, 
+               char **__restrict, size_t *__restrict));
+
+int
+_EXFUN(iconv_close, (iconv_t));
+#endif
+
+iconv_t
+_EXFUN(_iconv_open_r, (struct _reent *, _CONST char *, _CONST char *));
+
+size_t
+_EXFUN(_iconv_r, (struct _reent *, iconv_t, _CONST char **,
+                  size_t *, char **, size_t *));
+
+int
+_EXFUN(_iconv_close_r, (struct _reent *, iconv_t));
+
+_END_STD_C
+
+#endif /* #ifndef _ICONV_H_ */
diff --git a/tools/sdk/include/newlib/ieeefp.h b/tools/sdk/include/newlib/ieeefp.h
new file mode 100644
index 00000000..0b06fb78
--- /dev/null
+++ b/tools/sdk/include/newlib/ieeefp.h
@@ -0,0 +1,256 @@
+#ifndef _IEEE_FP_H_
+#define _IEEE_FP_H_
+
+#include "_ansi.h"
+
+#include 
+
+_BEGIN_STD_C
+
+/* FIXME FIXME FIXME:
+   Neither of __ieee_{float,double}_shape_tape seem to be used anywhere
+   except in libm/test.  If that is the case, please delete these from here.
+   If that is not the case, please insert documentation here describing why
+   they're needed.  */
+
+#ifdef __IEEE_BIG_ENDIAN
+
+typedef union 
+{
+  double value;
+  struct 
+  {
+    unsigned int sign : 1;
+    unsigned int exponent: 11;
+    unsigned int fraction0:4;
+    unsigned int fraction1:16;
+    unsigned int fraction2:16;
+    unsigned int fraction3:16;
+    
+  } number;
+  struct 
+  {
+    unsigned int sign : 1;
+    unsigned int exponent: 11;
+    unsigned int quiet:1;
+    unsigned int function0:3;
+    unsigned int function1:16;
+    unsigned int function2:16;
+    unsigned int function3:16;
+  } nan;
+  struct 
+  {
+    unsigned long msw;
+    unsigned long lsw;
+  } parts;
+    long aslong[2];
+} __ieee_double_shape_type;
+
+#endif
+
+#ifdef __IEEE_LITTLE_ENDIAN
+
+typedef union 
+{
+  double value;
+  struct 
+  {
+#ifdef __SMALL_BITFIELDS
+    unsigned int fraction3:16;
+    unsigned int fraction2:16;
+    unsigned int fraction1:16;
+    unsigned int fraction0: 4;
+#else
+    unsigned int fraction1:32;
+    unsigned int fraction0:20;
+#endif
+    unsigned int exponent :11;
+    unsigned int sign     : 1;
+  } number;
+  struct 
+  {
+#ifdef __SMALL_BITFIELDS
+    unsigned int function3:16;
+    unsigned int function2:16;
+    unsigned int function1:16;
+    unsigned int function0:3;
+#else
+    unsigned int function1:32;
+    unsigned int function0:19;
+#endif
+    unsigned int quiet:1;
+    unsigned int exponent: 11;
+    unsigned int sign : 1;
+  } nan;
+  struct 
+  {
+    unsigned long lsw;
+    unsigned long msw;
+  } parts;
+
+  long aslong[2];
+
+} __ieee_double_shape_type;
+
+#endif
+
+#ifdef __IEEE_BIG_ENDIAN
+
+typedef union
+{
+  float value;
+  struct 
+  {
+    unsigned int sign : 1;
+    unsigned int exponent: 8;
+    unsigned int fraction0: 7;
+    unsigned int fraction1: 16;
+  } number;
+  struct 
+  {
+    unsigned int sign:1;
+    unsigned int exponent:8;
+    unsigned int quiet:1;
+    unsigned int function0:6;
+    unsigned int function1:16;
+  } nan;
+  long p1;
+  
+} __ieee_float_shape_type;
+
+#endif
+
+#ifdef __IEEE_LITTLE_ENDIAN
+
+typedef union
+{
+  float value;
+  struct 
+  {
+    unsigned int fraction0: 7;
+    unsigned int fraction1: 16;
+    unsigned int exponent: 8;
+    unsigned int sign : 1;
+  } number;
+  struct 
+  {
+    unsigned int function1:16;
+    unsigned int function0:6;
+    unsigned int quiet:1;
+    unsigned int exponent:8;
+    unsigned int sign:1;
+  } nan;
+  long p1;
+  
+} __ieee_float_shape_type;
+
+#endif
+
+
+
+
+
+/* FLOATING ROUNDING */
+
+typedef int fp_rnd;
+#define FP_RN 0 	/* Round to nearest 		*/
+#define FP_RM 1		/* Round down 			*/
+#define FP_RP 2		/* Round up 			*/
+#define FP_RZ 3		/* Round to zero (trunate) 	*/
+
+fp_rnd _EXFUN(fpgetround,(void));
+fp_rnd _EXFUN(fpsetround, (fp_rnd));
+
+/* EXCEPTIONS */
+
+typedef int fp_except;
+#define FP_X_INV 0x10	/* Invalid operation 		*/
+#define FP_X_DX  0x80	/* Divide by zero		*/
+#define FP_X_OFL 0x04	/* Overflow exception		*/
+#define FP_X_UFL 0x02	/* Underflow exception		*/
+#define FP_X_IMP 0x01	/* imprecise exception		*/
+
+fp_except _EXFUN(fpgetmask,(void));
+fp_except _EXFUN(fpsetmask,(fp_except));
+fp_except _EXFUN(fpgetsticky,(void));
+fp_except _EXFUN(fpsetsticky, (fp_except));
+
+/* INTEGER ROUNDING */
+
+typedef int fp_rdi;
+#define FP_RDI_TOZ 0	/* Round to Zero 		*/
+#define FP_RDI_RD  1	/* Follow float mode		*/
+
+fp_rdi _EXFUN(fpgetroundtoi,(void));
+fp_rdi _EXFUN(fpsetroundtoi,(fp_rdi));
+
+#undef isnan
+#undef isinf
+
+int _EXFUN(isnan, (double));
+int _EXFUN(isinf, (double));
+int _EXFUN(finite, (double));
+
+
+
+int _EXFUN(isnanf, (float));
+int _EXFUN(isinff, (float));
+int _EXFUN(finitef, (float));
+
+#define __IEEE_DBL_EXPBIAS 1023
+#define __IEEE_FLT_EXPBIAS 127
+
+#define __IEEE_DBL_EXPLEN 11
+#define __IEEE_FLT_EXPLEN 8
+
+
+#define __IEEE_DBL_FRACLEN (64 - (__IEEE_DBL_EXPLEN + 1))
+#define __IEEE_FLT_FRACLEN (32 - (__IEEE_FLT_EXPLEN + 1))
+
+#define __IEEE_DBL_MAXPOWTWO	((double)(1L << 32 - 2) * (1L << (32-11) - 32 + 1))
+#define __IEEE_FLT_MAXPOWTWO	((float)(1L << (32-8) - 1))
+
+#define __IEEE_DBL_NAN_EXP 0x7ff
+#define __IEEE_FLT_NAN_EXP 0xff
+
+#ifndef __ieeefp_isnanf
+#define __ieeefp_isnanf(x) (((*(long *)&(x) & 0x7f800000L)==0x7f800000L) && \
+			    ((*(long *)&(x) & 0x007fffffL)!=0000000000L))
+#endif
+#define isnanf(x)	__ieeefp_isnanf(x)
+
+#ifndef __ieeefp_isinff
+#define __ieeefp_isinff(x) (((*(long *)&(x) & 0x7f800000L)==0x7f800000L) && \
+			    ((*(long *)&(x) & 0x007fffffL)==0000000000L))
+#endif
+#define isinff(x)	__ieeefp_isinff(x)
+
+#ifndef __ieeefp_finitef
+#define __ieeefp_finitef(x) (((*(long *)&(x) & 0x7f800000L)!=0x7f800000L))
+#endif
+#define finitef(x)	__ieeefp_finitef(x)
+
+#ifdef _DOUBLE_IS_32BITS
+#undef __IEEE_DBL_EXPBIAS
+#define __IEEE_DBL_EXPBIAS __IEEE_FLT_EXPBIAS
+
+#undef __IEEE_DBL_EXPLEN
+#define __IEEE_DBL_EXPLEN __IEEE_FLT_EXPLEN
+
+#undef __IEEE_DBL_FRACLEN
+#define __IEEE_DBL_FRACLEN __IEEE_FLT_FRACLEN
+
+#undef __IEEE_DBL_MAXPOWTWO
+#define __IEEE_DBL_MAXPOWTWO __IEEE_FLT_MAXPOWTWO
+
+#undef __IEEE_DBL_NAN_EXP
+#define __IEEE_DBL_NAN_EXP __IEEE_FLT_NAN_EXP
+
+#undef __ieee_double_shape_type
+#define __ieee_double_shape_type __ieee_float_shape_type
+
+#endif /* _DOUBLE_IS_32BITS */
+
+_END_STD_C
+
+#endif /* _IEEE_FP_H_ */
diff --git a/tools/sdk/include/newlib/inttypes.h b/tools/sdk/include/newlib/inttypes.h
new file mode 100644
index 00000000..39bf1351
--- /dev/null
+++ b/tools/sdk/include/newlib/inttypes.h
@@ -0,0 +1,319 @@
+/*
+ * Copyright (c) 2004, 2005 by
+ * Ralf Corsepius, Ulm/Germany. All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software
+ * is freely granted, provided that this notice is preserved.
+ */
+
+/**
+ *  @file  inttypes.h
+ */
+
+#ifndef _INTTYPES_H
+#define _INTTYPES_H
+
+#include 
+#include 
+#include 
+#define __need_wchar_t
+#include 
+
+#define __STRINGIFY(a) #a
+
+/* 8-bit types */
+#define __PRI8(x) __STRINGIFY(x)
+
+/* NOTICE: scanning 8-bit types requires use of the hh specifier
+ * which is only supported on newlib platforms that
+ * are built with C99 I/O format support enabled.  If the flag in
+ * newlib.h hasn't been set during configuration to indicate this, the 8-bit
+ * scanning format macros are disabled here as they result in undefined
+ * behaviour which can include memory overwrite.  Overriding the flag after the
+ * library has been built is not recommended as it will expose the underlying
+ * undefined behaviour.
+ */
+
+#if defined(_WANT_IO_C99_FORMATS)
+  #define __SCN8(x) __STRINGIFY(hh##x)
+#endif /* _WANT_IO_C99_FORMATS */
+
+
+#define PRId8		__PRI8(d)
+#define PRIi8		__PRI8(i)
+#define PRIo8		__PRI8(o)
+#define PRIu8		__PRI8(u)
+#define PRIx8		__PRI8(x)
+#define PRIX8		__PRI8(X)
+
+/* Macros below are only enabled for a newlib built with C99 I/O format support. */
+#if defined(_WANT_IO_C99_FORMATS)
+
+#define SCNd8		__SCN8(d)
+#define SCNi8		__SCN8(i)
+#define SCNo8		__SCN8(o)
+#define SCNu8		__SCN8(u)
+#define SCNx8		__SCN8(x)
+
+#endif /* _WANT_IO_C99_FORMATS */
+
+
+#define PRIdLEAST8	__PRI8(d)
+#define PRIiLEAST8	__PRI8(i)
+#define PRIoLEAST8	__PRI8(o)
+#define PRIuLEAST8	__PRI8(u)
+#define PRIxLEAST8	__PRI8(x)
+#define PRIXLEAST8	__PRI8(X)
+
+/* Macros below are only enabled for a newlib built with C99 I/O format support. */
+#if defined(_WANT_IO_C99_FORMATS)
+
+  #define SCNdLEAST8	__SCN8(d)
+  #define SCNiLEAST8	__SCN8(i)
+  #define SCNoLEAST8	__SCN8(o)
+  #define SCNuLEAST8	__SCN8(u)
+  #define SCNxLEAST8	__SCN8(x)
+
+#endif /* _WANT_IO_C99_FORMATS */
+
+#define PRIdFAST8	__PRI8(d)
+#define PRIiFAST8	__PRI8(i)
+#define PRIoFAST8	__PRI8(o)
+#define PRIuFAST8	__PRI8(u)
+#define PRIxFAST8	__PRI8(x)
+#define PRIXFAST8	__PRI8(X)
+
+/* Macros below are only enabled for a newlib built with C99 I/O format support. */
+#if defined(_WANT_IO_C99_FORMATS)
+
+  #define SCNdFAST8	__SCN8(d)
+  #define SCNiFAST8	__SCN8(i)
+  #define SCNoFAST8	__SCN8(o)
+  #define SCNuFAST8	__SCN8(u)
+  #define SCNxFAST8	__SCN8(x)
+
+#endif /* _WANT_IO_C99_FORMATS */
+
+/* 16-bit types */
+#define __PRI16(x) __STRINGIFY(x)
+#define __SCN16(x) __STRINGIFY(h##x)
+
+
+#define PRId16		__PRI16(d)
+#define PRIi16		__PRI16(i)
+#define PRIo16		__PRI16(o)
+#define PRIu16		__PRI16(u)
+#define PRIx16		__PRI16(x)
+#define PRIX16		__PRI16(X)
+
+#define SCNd16		__SCN16(d)
+#define SCNi16		__SCN16(i)
+#define SCNo16		__SCN16(o)
+#define SCNu16		__SCN16(u)
+#define SCNx16		__SCN16(x)
+
+
+#define PRIdLEAST16	__PRI16(d)
+#define PRIiLEAST16	__PRI16(i)
+#define PRIoLEAST16	__PRI16(o)
+#define PRIuLEAST16	__PRI16(u)
+#define PRIxLEAST16	__PRI16(x)
+#define PRIXLEAST16	__PRI16(X)
+
+#define SCNdLEAST16	__SCN16(d)
+#define SCNiLEAST16	__SCN16(i)
+#define SCNoLEAST16	__SCN16(o)
+#define SCNuLEAST16	__SCN16(u)
+#define SCNxLEAST16	__SCN16(x)
+
+
+#define PRIdFAST16	__PRI16(d)
+#define PRIiFAST16	__PRI16(i)
+#define PRIoFAST16	__PRI16(o)
+#define PRIuFAST16	__PRI16(u)
+#define PRIxFAST16	__PRI16(x)
+#define PRIXFAST16	__PRI16(X)
+
+#define SCNdFAST16	__SCN16(d)
+#define SCNiFAST16	__SCN16(i)
+#define SCNoFAST16	__SCN16(o)
+#define SCNuFAST16	__SCN16(u)
+#define SCNxFAST16	__SCN16(x)
+
+/* 32-bit types */
+#if __have_long32
+#define __PRI32(x) __STRINGIFY(l##x)
+#define __SCN32(x) __STRINGIFY(l##x)
+#else
+#define __PRI32(x) __STRINGIFY(x)
+#define __SCN32(x) __STRINGIFY(x)
+#endif
+
+#define PRId32		__PRI32(d)
+#define PRIi32		__PRI32(i)
+#define PRIo32		__PRI32(o)
+#define PRIu32		__PRI32(u)
+#define PRIx32		__PRI32(x)
+#define PRIX32		__PRI32(X)
+
+#define SCNd32		__SCN32(d)
+#define SCNi32		__SCN32(i)
+#define SCNo32		__SCN32(o)
+#define SCNu32		__SCN32(u)
+#define SCNx32		__SCN32(x)
+
+
+#define PRIdLEAST32	__PRI32(d)
+#define PRIiLEAST32	__PRI32(i)
+#define PRIoLEAST32	__PRI32(o)
+#define PRIuLEAST32	__PRI32(u)
+#define PRIxLEAST32	__PRI32(x)
+#define PRIXLEAST32	__PRI32(X)
+
+#define SCNdLEAST32	__SCN32(d)
+#define SCNiLEAST32	__SCN32(i)
+#define SCNoLEAST32	__SCN32(o)
+#define SCNuLEAST32	__SCN32(u)
+#define SCNxLEAST32	__SCN32(x)
+
+
+#define PRIdFAST32	__PRI32(d)
+#define PRIiFAST32	__PRI32(i)
+#define PRIoFAST32	__PRI32(o)
+#define PRIuFAST32	__PRI32(u)
+#define PRIxFAST32	__PRI32(x)
+#define PRIXFAST32	__PRI32(X)
+
+#define SCNdFAST32	__SCN32(d)
+#define SCNiFAST32	__SCN32(i)
+#define SCNoFAST32	__SCN32(o)
+#define SCNuFAST32	__SCN32(u)
+#define SCNxFAST32	__SCN32(x)
+
+
+/* 64-bit types */
+#if __have_long64
+#define __PRI64(x) __STRINGIFY(l##x)
+#define __SCN64(x) __STRINGIFY(l##x)
+#elif __have_longlong64
+#define __PRI64(x) __STRINGIFY(ll##x)
+#define __SCN64(x) __STRINGIFY(ll##x)
+#else
+#define __PRI64(x) __STRINGIFY(x)
+#define __SCN64(x) __STRINGIFY(x)
+#endif
+
+#define PRId64		__PRI64(d)
+#define PRIi64		__PRI64(i)
+#define PRIo64		__PRI64(o)
+#define PRIu64		__PRI64(u)
+#define PRIx64		__PRI64(x)
+#define PRIX64		__PRI64(X)
+
+#define SCNd64		__SCN64(d)
+#define SCNi64		__SCN64(i)
+#define SCNo64		__SCN64(o)
+#define SCNu64		__SCN64(u)
+#define SCNx64		__SCN64(x)
+
+#if __int64_t_defined
+#define PRIdLEAST64	__PRI64(d)
+#define PRIiLEAST64	__PRI64(i)
+#define PRIoLEAST64	__PRI64(o)
+#define PRIuLEAST64	__PRI64(u)
+#define PRIxLEAST64	__PRI64(x)
+#define PRIXLEAST64	__PRI64(X)
+
+#define SCNdLEAST64	__SCN64(d)
+#define SCNiLEAST64	__SCN64(i)
+#define SCNoLEAST64	__SCN64(o)
+#define SCNuLEAST64	__SCN64(u)
+#define SCNxLEAST64	__SCN64(x)
+
+
+#define PRIdFAST64	__PRI64(d)
+#define PRIiFAST64	__PRI64(i)
+#define PRIoFAST64	__PRI64(o)
+#define PRIuFAST64	__PRI64(u)
+#define PRIxFAST64	__PRI64(x)
+#define PRIXFAST64	__PRI64(X)
+
+#define SCNdFAST64	__SCN64(d)
+#define SCNiFAST64	__SCN64(i)
+#define SCNoFAST64	__SCN64(o)
+#define SCNuFAST64	__SCN64(u)
+#define SCNxFAST64	__SCN64(x)
+#endif
+
+/* max-bit types */
+#if __have_long64
+#define __PRIMAX(x) __STRINGIFY(l##x)
+#define __SCNMAX(x) __STRINGIFY(l##x)
+#elif __have_longlong64
+#define __PRIMAX(x) __STRINGIFY(ll##x)
+#define __SCNMAX(x) __STRINGIFY(ll##x)
+#else
+#define __PRIMAX(x) __STRINGIFY(x)
+#define __SCNMAX(x) __STRINGIFY(x)
+#endif
+
+#define PRIdMAX		__PRIMAX(d)
+#define PRIiMAX		__PRIMAX(i)
+#define PRIoMAX		__PRIMAX(o)
+#define PRIuMAX		__PRIMAX(u)
+#define PRIxMAX		__PRIMAX(x)
+#define PRIXMAX		__PRIMAX(X)
+
+#define SCNdMAX		__SCNMAX(d)
+#define SCNiMAX		__SCNMAX(i)
+#define SCNoMAX		__SCNMAX(o)
+#define SCNuMAX		__SCNMAX(u)
+#define SCNxMAX		__SCNMAX(x)
+
+/* ptr types */
+#if defined(_UINTPTR_EQ_ULONGLONG)
+# define __PRIPTR(x) __STRINGIFY(ll##x)
+# define __SCNPTR(x) __STRINGIFY(ll##x)
+#elif defined(_UINTPTR_EQ_ULONG)
+# define __PRIPTR(x) __STRINGIFY(l##x)
+# define __SCNPTR(x) __STRINGIFY(l##x)
+#else
+# define __PRIPTR(x) __STRINGIFY(x)
+# define __SCNPTR(x) __STRINGIFY(x)
+#endif
+
+#define PRIdPTR		__PRIPTR(d)
+#define PRIiPTR		__PRIPTR(i)
+#define PRIoPTR		__PRIPTR(o)
+#define PRIuPTR		__PRIPTR(u)
+#define PRIxPTR		__PRIPTR(x)
+#define PRIXPTR		__PRIPTR(X)
+
+#define SCNdPTR		__SCNPTR(d)
+#define SCNiPTR		__SCNPTR(i)
+#define SCNoPTR		__SCNPTR(o)
+#define SCNuPTR		__SCNPTR(u)
+#define SCNxPTR		__SCNPTR(x)
+
+
+typedef struct {
+  intmax_t	quot;
+  intmax_t	rem;
+} imaxdiv_t;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern intmax_t  imaxabs(intmax_t j);
+extern imaxdiv_t imaxdiv(intmax_t numer, intmax_t denomer);
+extern intmax_t  strtoimax(const char *__restrict, char **__restrict, int);
+extern uintmax_t strtoumax(const char *__restrict, char **__restrict, int);
+extern intmax_t  wcstoimax(const wchar_t *__restrict, wchar_t **__restrict, int);
+extern uintmax_t wcstoumax(const wchar_t *__restrict, wchar_t **__restrict, int);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tools/sdk/include/newlib/langinfo.h b/tools/sdk/include/newlib/langinfo.h
new file mode 100644
index 00000000..9040adef
--- /dev/null
+++ b/tools/sdk/include/newlib/langinfo.h
@@ -0,0 +1,316 @@
+/*-
+ * Copyright (c) 2001 Alexey Zelkin 
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: src/include/langinfo.h,v 1.5 2002/03/23 17:24:53 imp Exp $
+ */
+
+#ifndef _LANGINFO_H_
+#define	_LANGINFO_H_
+
+#include 
+#include 
+#include 
+
+typedef int nl_item;
+
+enum __nl_item
+{
+  /* POSIX and BSD defined items have to stick to the original values
+     to maintain backward compatibility. */
+  _NL_CTYPE_CODESET_NAME = 0,	/* codeset name */
+#define CODESET _NL_CTYPE_CODESET_NAME
+  D_T_FMT,			/* string for formatting date and time */
+#define D_T_FMT D_T_FMT
+  D_FMT,			/* date format string */
+#define D_FMT D_FMT
+  T_FMT,			/* time format string */
+#define T_FMT T_FMT
+  T_FMT_AMPM,			/* a.m. or p.m. time formatting string */
+#define T_FMT_AMPM T_FMT_AMPM
+  AM_STR,			/* Ante Meridian affix */
+#define AM_STR AM_STR
+  PM_STR,			/* Post Meridian affix */
+#define PM_STR PM_STR
+
+/* week day names */
+  DAY_1,
+#define DAY_1 DAY_1
+  DAY_2,
+#define DAY_2 DAY_2
+  DAY_3,
+#define DAY_3 DAY_3
+  DAY_4,
+#define DAY_4 DAY_4
+  DAY_5,
+#define DAY_5 DAY_5
+  DAY_6,
+#define DAY_6 DAY_6
+  DAY_7,
+#define DAY_7 DAY_7
+
+/* abbreviated week day names */
+  ABDAY_1,
+#define ABDAY_1 ABDAY_1
+  ABDAY_2,
+#define ABDAY_2 ABDAY_2
+  ABDAY_3,
+#define ABDAY_3 ABDAY_3
+  ABDAY_4,
+#define ABDAY_4 ABDAY_4
+  ABDAY_5,
+#define ABDAY_5 ABDAY_5
+  ABDAY_6,
+#define ABDAY_6 ABDAY_6
+  ABDAY_7,
+#define ABDAY_7 ABDAY_7
+
+/* month names */
+  MON_1,
+#define MON_1 MON_1
+  MON_2,
+#define MON_2 MON_2
+  MON_3,
+#define MON_3 MON_3
+  MON_4,
+#define MON_4 MON_4
+  MON_5,
+#define MON_5 MON_5
+  MON_6,
+#define MON_6 MON_6
+  MON_7,
+#define MON_7 MON_7
+  MON_8,
+#define MON_8 MON_8
+  MON_9,
+#define MON_9 MON_9
+  MON_10,
+#define MON_10 MON_10
+  MON_11,
+#define MON_11 MON_11
+  MON_12,
+#define MON_12 MON_12
+
+/* abbreviated month names */
+  ABMON_1,
+#define ABMON_1 ABMON_1
+  ABMON_2,
+#define ABMON_2 ABMON_2
+  ABMON_3,
+#define ABMON_3 ABMON_3
+  ABMON_4,
+#define ABMON_4 ABMON_4
+  ABMON_5,
+#define ABMON_5 ABMON_5
+  ABMON_6,
+#define ABMON_6 ABMON_6
+  ABMON_7,
+#define ABMON_7 ABMON_7
+  ABMON_8,
+#define ABMON_8 ABMON_8
+  ABMON_9,
+#define ABMON_9 ABMON_9
+  ABMON_10,
+#define ABMON_10 ABMON_10
+  ABMON_11,
+#define ABMON_11 ABMON_11
+  ABMON_12,
+#define ABMON_12 ABMON_12
+
+  ERA,				/* era description segments */
+#define ERA ERA
+  ERA_D_FMT,			/* era date format string */
+#define ERA_D_FMT ERA_D_FMT
+  ERA_D_T_FMT,			/* era date and time format string */
+#define ERA_D_T_FMT ERA_D_T_FMT
+  ERA_T_FMT,			/* era time format string */
+#define ERA_T_FMT ERA_T_FMT
+  ALT_DIGITS,			/* alternative symbols for digits */
+#define ALT_DIGITS ALT_DIGITS
+
+  RADIXCHAR,			/* radix char */
+#define RADIXCHAR RADIXCHAR
+  THOUSEP,			/* separator for thousands */
+#define THOUSEP THOUSEP
+
+  YESEXPR,			/* affirmative response expression */
+#define YESEXPR YESEXPR
+  NOEXPR,			/* negative response expression */
+#define NOEXPR NOEXPR
+  YESSTR,			/* affirmative response for yes/no queries */
+#define YESSTR YESSTR
+  NOSTR,			/* negative response for yes/no queries */
+#define NOSTR NOSTR
+
+  CRNCYSTR,			/* currency symbol */
+#define CRNCYSTR CRNCYSTR
+
+  D_MD_ORDER,			/* month/day order (BSD extension) */
+#define D_MD_ORDER D_MD_ORDER
+
+  _NL_TIME_DATE_FMT = 84,	/* date fmt used by date(1) (GNU extension) */
+#define _DATE_FMT _NL_TIME_DATE_FMT
+
+#ifdef __HAVE_LOCALE_INFO__
+  _NL_CTYPE_MB_CUR_MAX,
+  _NL_MESSAGES_CODESET,
+
+#ifdef __HAVE_LOCALE_INFO_EXTENDED__
+
+  /* NOTE:
+  
+     Always maintain the order and position of existing entries!
+     Always append new entry to the list, prior to the definition
+     of _NL_LOCALE_EXTENDED_LAST_ENTRY. */
+
+  _NL_LOCALE_EXTENDED_FIRST_ENTRY,
+
+  _NL_CTYPE_OUTDIGITS0_MB,
+  _NL_CTYPE_OUTDIGITS1_MB,
+  _NL_CTYPE_OUTDIGITS2_MB,
+  _NL_CTYPE_OUTDIGITS3_MB,
+  _NL_CTYPE_OUTDIGITS4_MB,
+  _NL_CTYPE_OUTDIGITS5_MB,
+  _NL_CTYPE_OUTDIGITS6_MB,
+  _NL_CTYPE_OUTDIGITS7_MB,
+  _NL_CTYPE_OUTDIGITS8_MB,
+  _NL_CTYPE_OUTDIGITS9_MB,
+  _NL_CTYPE_OUTDIGITS0_WC,
+  _NL_CTYPE_OUTDIGITS1_WC,
+  _NL_CTYPE_OUTDIGITS2_WC,
+  _NL_CTYPE_OUTDIGITS3_WC,
+  _NL_CTYPE_OUTDIGITS4_WC,
+  _NL_CTYPE_OUTDIGITS5_WC,
+  _NL_CTYPE_OUTDIGITS6_WC,
+  _NL_CTYPE_OUTDIGITS7_WC,
+  _NL_CTYPE_OUTDIGITS8_WC,
+  _NL_CTYPE_OUTDIGITS9_WC,
+
+  _NL_TIME_CODESET,
+  _NL_TIME_WMON_1,
+  _NL_TIME_WMON_2,
+  _NL_TIME_WMON_3,
+  _NL_TIME_WMON_4,
+  _NL_TIME_WMON_5,
+  _NL_TIME_WMON_6,
+  _NL_TIME_WMON_7,
+  _NL_TIME_WMON_8,
+  _NL_TIME_WMON_9,
+  _NL_TIME_WMON_10,
+  _NL_TIME_WMON_11,
+  _NL_TIME_WMON_12,
+  _NL_TIME_WMONTH_1,
+  _NL_TIME_WMONTH_2,
+  _NL_TIME_WMONTH_3,
+  _NL_TIME_WMONTH_4,
+  _NL_TIME_WMONTH_5,
+  _NL_TIME_WMONTH_6,
+  _NL_TIME_WMONTH_7,
+  _NL_TIME_WMONTH_8,
+  _NL_TIME_WMONTH_9,
+  _NL_TIME_WMONTH_10,
+  _NL_TIME_WMONTH_11,
+  _NL_TIME_WMONTH_12,
+  _NL_TIME_WWDAY_1,
+  _NL_TIME_WWDAY_2,
+  _NL_TIME_WWDAY_3,
+  _NL_TIME_WWDAY_4,
+  _NL_TIME_WWDAY_5,
+  _NL_TIME_WWDAY_6,
+  _NL_TIME_WWDAY_7,
+  _NL_TIME_WWEEKDAY_1,
+  _NL_TIME_WWEEKDAY_2,
+  _NL_TIME_WWEEKDAY_3,
+  _NL_TIME_WWEEKDAY_4,
+  _NL_TIME_WWEEKDAY_5,
+  _NL_TIME_WWEEKDAY_6,
+  _NL_TIME_WWEEKDAY_7,
+  _NL_TIME_WT_FMT,
+  _NL_TIME_WD_FMT,
+  _NL_TIME_WD_T_FMT,
+  _NL_TIME_WAM_STR,
+  _NL_TIME_WPM_STR,
+  _NL_TIME_WDATE_FMT,
+  _NL_TIME_WT_FMT_AMPM,
+  _NL_TIME_WERA,
+  _NL_TIME_WERA_D_FMT,
+  _NL_TIME_WERA_D_T_FMT,
+  _NL_TIME_WERA_T_FMT,
+  _NL_TIME_WALT_DIGITS,
+
+  _NL_NUMERIC_CODESET,
+  _NL_NUMERIC_GROUPING,
+  _NL_NUMERIC_DECIMAL_POINT_WC,
+  _NL_NUMERIC_THOUSANDS_SEP_WC,
+
+  _NL_MONETARY_INT_CURR_SYMBOL,
+  _NL_MONETARY_CURRENCY_SYMBOL,
+  _NL_MONETARY_MON_DECIMAL_POINT,
+  _NL_MONETARY_MON_THOUSANDS_SEP,
+  _NL_MONETARY_MON_GROUPING,
+  _NL_MONETARY_POSITIVE_SIGN,
+  _NL_MONETARY_NEGATIVE_SIGN,
+  _NL_MONETARY_INT_FRAC_DIGITS,
+  _NL_MONETARY_FRAC_DIGITS,
+  _NL_MONETARY_P_CS_PRECEDES,
+  _NL_MONETARY_P_SEP_BY_SPACE,
+  _NL_MONETARY_N_CS_PRECEDES,
+  _NL_MONETARY_N_SEP_BY_SPACE,
+  _NL_MONETARY_P_SIGN_POSN,
+  _NL_MONETARY_N_SIGN_POSN,
+  _NL_MONETARY_INT_P_CS_PRECEDES,
+  _NL_MONETARY_INT_P_SEP_BY_SPACE,
+  _NL_MONETARY_INT_N_CS_PRECEDES,
+  _NL_MONETARY_INT_N_SEP_BY_SPACE,
+  _NL_MONETARY_INT_P_SIGN_POSN,
+  _NL_MONETARY_INT_N_SIGN_POSN,
+  _NL_MONETARY_CODESET,
+  _NL_MONETARY_WINT_CURR_SYMBOL,
+  _NL_MONETARY_WCURRENCY_SYMBOL,
+  _NL_MONETARY_WMON_DECIMAL_POINT,
+  _NL_MONETARY_WMON_THOUSANDS_SEP,
+  _NL_MONETARY_WPOSITIVE_SIGN,
+  _NL_MONETARY_WNEGATIVE_SIGN,
+
+  _NL_MESSAGES_WYESEXPR,
+  _NL_MESSAGES_WNOEXPR,
+  _NL_MESSAGES_WYESSTR,
+  _NL_MESSAGES_WNOSTR,
+
+  _NL_COLLATE_CODESET,
+
+  /* This MUST be the last entry since it's used to check for an array
+     index in nl_langinfo(). */
+  _NL_LOCALE_EXTENDED_LAST_ENTRY
+
+#endif /* __HAVE_LOCALE_INFO_EXTENDED__ */
+#endif /* __HAVE_LOCALE_INFO__ */
+
+};
+
+__BEGIN_DECLS
+char	*nl_langinfo(nl_item);
+__END_DECLS
+
+#endif /* !_LANGINFO_H_ */
diff --git a/tools/sdk/include/newlib/libgen.h b/tools/sdk/include/newlib/libgen.h
new file mode 100644
index 00000000..abfab0e5
--- /dev/null
+++ b/tools/sdk/include/newlib/libgen.h
@@ -0,0 +1,23 @@
+/*
+ * libgen.h - defined by XPG4
+ */
+
+#ifndef _LIBGEN_H_
+#define _LIBGEN_H_
+
+#include "_ansi.h"
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+char      *_EXFUN(basename,     (char *));
+char      *_EXFUN(dirname,     (char *));
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _LIBGEN_H_ */
+
diff --git a/tools/sdk/include/newlib/limits.h b/tools/sdk/include/newlib/limits.h
new file mode 100644
index 00000000..190f1f78
--- /dev/null
+++ b/tools/sdk/include/newlib/limits.h
@@ -0,0 +1,146 @@
+#ifndef _LIBC_LIMITS_H_
+# define _LIBC_LIMITS_H_	1
+
+#include 
+
+# ifdef _MB_LEN_MAX
+#  define MB_LEN_MAX	_MB_LEN_MAX
+# else
+#  define MB_LEN_MAX    1
+# endif
+
+/* Maximum number of positional arguments, if _WANT_IO_POS_ARGS.  */
+# ifndef NL_ARGMAX
+#  define NL_ARGMAX 32
+# endif
+
+/* if do not have #include_next support, then we
+   have to define the limits here. */
+# if !defined __GNUC__ || __GNUC__ < 2
+
+#  ifndef _LIMITS_H
+#   define _LIMITS_H	1
+
+#   include 
+
+/* Number of bits in a `char'.  */
+#   undef CHAR_BIT
+#   define CHAR_BIT 8
+
+/* Minimum and maximum values a `signed char' can hold.  */
+#   undef SCHAR_MIN
+#   define SCHAR_MIN (-128)
+#   undef SCHAR_MAX
+#   define SCHAR_MAX 127
+
+/* Maximum value an `unsigned char' can hold.  (Minimum is 0).  */
+#   undef UCHAR_MAX
+#   define UCHAR_MAX 255
+
+/* Minimum and maximum values a `char' can hold.  */
+#   ifdef __CHAR_UNSIGNED__
+#    undef CHAR_MIN
+#    define CHAR_MIN 0
+#    undef CHAR_MAX
+#    define CHAR_MAX 255
+#   else
+#    undef CHAR_MIN
+#    define CHAR_MIN (-128)
+#    undef CHAR_MAX
+#    define CHAR_MAX 127
+#   endif
+
+/* Minimum and maximum values a `signed short int' can hold.  */
+#   undef SHRT_MIN
+/* For the sake of 16 bit hosts, we may not use -32768 */
+#   define SHRT_MIN (-32767-1)
+#   undef SHRT_MAX
+#   define SHRT_MAX 32767
+
+/* Maximum value an `unsigned short int' can hold.  (Minimum is 0).  */
+#   undef USHRT_MAX
+#   define USHRT_MAX 65535
+
+/* Minimum and maximum values a `signed int' can hold.  */
+#   ifndef __INT_MAX__
+#    define __INT_MAX__ 2147483647
+#   endif
+#   undef INT_MIN
+#   define INT_MIN (-INT_MAX-1)
+#   undef INT_MAX
+#   define INT_MAX __INT_MAX__
+
+/* Maximum value an `unsigned int' can hold.  (Minimum is 0).  */
+#   undef UINT_MAX
+#   define UINT_MAX (INT_MAX * 2U + 1)
+
+/* Minimum and maximum values a `signed long int' can hold.
+   (Same as `int').  */
+#   ifndef __LONG_MAX__
+#    if defined (__alpha__) || (defined (__sparc__) && defined(__arch64__)) || defined (__sparcv9)
+#     define __LONG_MAX__ 9223372036854775807L
+#    else
+#     define __LONG_MAX__ 2147483647L
+#    endif /* __alpha__ || sparc64 */
+#   endif
+#   undef LONG_MIN
+#   define LONG_MIN (-LONG_MAX-1)
+#   undef LONG_MAX
+#   define LONG_MAX __LONG_MAX__
+
+/* Maximum value an `unsigned long int' can hold.  (Minimum is 0).  */
+#   undef ULONG_MAX
+#   define ULONG_MAX (LONG_MAX * 2UL + 1)
+
+#   ifndef __LONG_LONG_MAX__
+#    define __LONG_LONG_MAX__ 9223372036854775807LL
+#   endif
+
+#   if (defined (__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) ||   \
+  (defined(__cplusplus) && __cplusplus >= 201103L)
+/* Minimum and maximum values a `signed long long int' can hold.  */
+#    undef LLONG_MIN
+#    define LLONG_MIN (-LLONG_MAX-1)
+#    undef LLONG_MAX
+#    define LLONG_MAX __LONG_LONG_MAX__
+
+/* Maximum value an `unsigned long long int' can hold.  (Minimum is 0).  */
+#    undef ULLONG_MAX
+#    define ULLONG_MAX (LLONG_MAX * 2ULL + 1)
+#   endif
+
+#  if defined (__GNU_LIBRARY__) ? defined (__USE_GNU) : !defined (__STRICT_ANSI__)
+/* Minimum and maximum values a `signed long long int' can hold.  */
+#    undef LONG_LONG_MIN
+#    define LONG_LONG_MIN (-LONG_LONG_MAX-1)
+#    undef LONG_LONG_MAX
+#    define LONG_LONG_MAX __LONG_LONG_MAX__
+
+/* Maximum value an `unsigned long long int' can hold.  (Minimum is 0).  */
+#    undef ULONG_LONG_MAX
+#    define ULONG_LONG_MAX (LONG_LONG_MAX * 2ULL + 1)
+#   endif
+
+#  endif /* _LIMITS_H  */
+# endif	 /* GCC 2.  */
+
+#endif	 /* !_LIBC_LIMITS_H_ */
+
+#if defined __GNUC__ && !defined _GCC_LIMITS_H_
+/* `_GCC_LIMITS_H_' is what GCC's file defines.  */
+# include_next 
+#endif /* __GNUC__ && !_GCC_LIMITS_H_ */
+
+#ifndef _POSIX2_RE_DUP_MAX
+/* The maximum number of repeated occurrences of a regular expression
+ *    permitted when using the interval notation `\{M,N\}'.  */
+#define _POSIX2_RE_DUP_MAX              255
+#endif /* _POSIX2_RE_DUP_MAX  */
+
+#ifndef ARG_MAX
+#define ARG_MAX		4096
+#endif
+
+#ifndef PATH_MAX
+#define PATH_MAX	4096
+#endif
diff --git a/tools/sdk/include/newlib/locale.h b/tools/sdk/include/newlib/locale.h
new file mode 100644
index 00000000..cbd658e4
--- /dev/null
+++ b/tools/sdk/include/newlib/locale.h
@@ -0,0 +1,64 @@
+/*
+	locale.h
+	Values appropriate for the formatting of monetary and other
+	numberic quantities.
+*/
+
+#ifndef _LOCALE_H_
+#define _LOCALE_H_
+
+#include "_ansi.h"
+
+#define __need_NULL
+#include 
+
+#define LC_ALL	    0
+#define LC_COLLATE  1
+#define LC_CTYPE    2
+#define LC_MONETARY 3
+#define LC_NUMERIC  4
+#define LC_TIME     5
+#define LC_MESSAGES 6
+
+_BEGIN_STD_C
+
+struct lconv
+{
+  char *decimal_point;
+  char *thousands_sep;
+  char *grouping;
+  char *int_curr_symbol;
+  char *currency_symbol;
+  char *mon_decimal_point;
+  char *mon_thousands_sep;
+  char *mon_grouping;
+  char *positive_sign;
+  char *negative_sign;
+  char int_frac_digits;
+  char frac_digits;
+  char p_cs_precedes;
+  char p_sep_by_space;
+  char n_cs_precedes;
+  char n_sep_by_space;
+  char p_sign_posn;
+  char n_sign_posn;
+  char int_n_cs_precedes;
+  char int_n_sep_by_space;
+  char int_n_sign_posn;
+  char int_p_cs_precedes;
+  char int_p_sep_by_space;
+  char int_p_sign_posn;
+};
+
+#ifndef _REENT_ONLY
+char *_EXFUN(setlocale,(int category, const char *locale));
+struct lconv *_EXFUN(localeconv,(void));
+#endif
+
+struct _reent;
+char *_EXFUN(_setlocale_r,(struct _reent *, int category, const char *locale));
+struct lconv *_EXFUN(_localeconv_r,(struct _reent *));
+
+_END_STD_C
+
+#endif /* _LOCALE_H_ */
diff --git a/tools/sdk/include/newlib/machine/_default_types.h b/tools/sdk/include/newlib/machine/_default_types.h
new file mode 100644
index 00000000..03bdc523
--- /dev/null
+++ b/tools/sdk/include/newlib/machine/_default_types.h
@@ -0,0 +1,56 @@
+/*
+ * _default_types implementation for xtensa lx106 arch
+ *
+ * Simplified version of generic _default_types.h, ignores gcc
+ * built-in standard types.
+ */
+
+#ifndef _MACHINE__DEFAULT_TYPES_H
+#define _MACHINE__DEFAULT_TYPES_H
+
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef signed char __int8_t ;
+typedef unsigned char __uint8_t ;
+#define ___int8_t_defined 1
+
+typedef signed short __int16_t;
+typedef unsigned short __uint16_t;
+#define ___int16_t_defined 1
+
+typedef signed int __int32_t;
+typedef unsigned int __uint32_t;
+#define ___int32_t_defined 1
+
+typedef signed long long __int64_t;
+typedef unsigned long long __uint64_t;
+#define ___int64_t_defined 1
+
+typedef __int8_t __int_least8_t;
+typedef __uint8_t __uint_least8_t;
+#define ___int_least8_t_defined
+
+typedef __int16_t __int_least16_t;
+typedef __uint16_t __uint_least16_t;
+#define ___int_least16_t_defined
+
+typedef __int32_t __int_least32_t;
+typedef __uint32_t __uint_least32_t;
+#define ___int_least32_t_defined
+
+typedef __int64_t __int_least64_t;
+typedef __uint64_t __uint_least64_t;
+#define ___int_least64_t_defined
+
+typedef __INTPTR_TYPE__ __intptr_t;
+typedef __UINTPTR_TYPE__ __uintptr_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MACHINE__DEFAULT_TYPES_H */
diff --git a/tools/sdk/include/newlib/machine/_types.h b/tools/sdk/include/newlib/machine/_types.h
new file mode 100644
index 00000000..17e6d51e
--- /dev/null
+++ b/tools/sdk/include/newlib/machine/_types.h
@@ -0,0 +1,8 @@
+/*
+ *  $Id$
+ */
+
+#ifndef _MACHINE__TYPES_H
+#define _MACHINE__TYPES_H
+#include 
+#endif
diff --git a/tools/sdk/include/newlib/machine/ansi.h b/tools/sdk/include/newlib/machine/ansi.h
new file mode 100644
index 00000000..737b6d06
--- /dev/null
+++ b/tools/sdk/include/newlib/machine/ansi.h
@@ -0,0 +1 @@
+/* dummy header file to support BSD compiler */
diff --git a/tools/sdk/include/newlib/machine/endian.h b/tools/sdk/include/newlib/machine/endian.h
new file mode 100644
index 00000000..07ebc8f6
--- /dev/null
+++ b/tools/sdk/include/newlib/machine/endian.h
@@ -0,0 +1,20 @@
+#ifndef __MACHINE_ENDIAN_H__
+
+#include 
+
+#ifndef BIG_ENDIAN
+#define BIG_ENDIAN 4321
+#endif
+#ifndef LITTLE_ENDIAN
+#define LITTLE_ENDIAN 1234
+#endif
+
+#ifndef BYTE_ORDER
+#if defined(__IEEE_LITTLE_ENDIAN) || defined(__IEEE_BYTES_LITTLE_ENDIAN)
+#define BYTE_ORDER LITTLE_ENDIAN
+#else
+#define BYTE_ORDER BIG_ENDIAN
+#endif
+#endif
+
+#endif /* __MACHINE_ENDIAN_H__ */
diff --git a/tools/sdk/include/newlib/machine/fastmath.h b/tools/sdk/include/newlib/machine/fastmath.h
new file mode 100644
index 00000000..b13befa2
--- /dev/null
+++ b/tools/sdk/include/newlib/machine/fastmath.h
@@ -0,0 +1,100 @@
+#ifdef __sysvnecv70_target
+double EXFUN(fast_sin,(double));
+double EXFUN(fast_cos,(double));
+double EXFUN(fast_tan,(double));
+
+double EXFUN(fast_asin,(double));
+double EXFUN(fast_acos,(double));
+double EXFUN(fast_atan,(double));
+
+double EXFUN(fast_sinh,(double));
+double EXFUN(fast_cosh,(double));
+double EXFUN(fast_tanh,(double));
+
+double EXFUN(fast_asinh,(double));
+double EXFUN(fast_acosh,(double));
+double EXFUN(fast_atanh,(double));
+
+double EXFUN(fast_abs,(double));
+double EXFUN(fast_sqrt,(double));
+double EXFUN(fast_exp2,(double));
+double EXFUN(fast_exp10,(double));
+double EXFUN(fast_expe,(double));
+double EXFUN(fast_log10,(double));
+double EXFUN(fast_log2,(double));
+double EXFUN(fast_loge,(double));
+
+
+#define	sin(x)		fast_sin(x)
+#define	cos(x)		fast_cos(x)
+#define	tan(x)		fast_tan(x)
+#define	asin(x)		fast_asin(x)
+#define	acos(x)		fast_acos(x)
+#define	atan(x)		fast_atan(x)
+#define	sinh(x)		fast_sinh(x)
+#define	cosh(x)		fast_cosh(x)
+#define	tanh(x)		fast_tanh(x)
+#define	asinh(x)	fast_asinh(x)
+#define	acosh(x)	fast_acosh(x)
+#define	atanh(x)	fast_atanh(x)
+#define	abs(x)		fast_abs(x)
+#define	sqrt(x)		fast_sqrt(x)
+#define	exp2(x)		fast_exp2(x)
+#define	exp10(x)	fast_exp10(x)
+#define	expe(x)		fast_expe(x)
+#define	log10(x)	fast_log10(x)
+#define	log2(x)		fast_log2(x)
+#define	loge(x)		fast_loge(x)
+
+#ifdef _HAVE_STDC
+/* These functions are in assembler, they really do take floats. This
+   can only be used with a real ANSI compiler */
+
+float EXFUN(fast_sinf,(float));
+float EXFUN(fast_cosf,(float));
+float EXFUN(fast_tanf,(float));
+
+float EXFUN(fast_asinf,(float));
+float EXFUN(fast_acosf,(float));
+float EXFUN(fast_atanf,(float));
+
+float EXFUN(fast_sinhf,(float));
+float EXFUN(fast_coshf,(float));
+float EXFUN(fast_tanhf,(float));
+
+float EXFUN(fast_asinhf,(float));
+float EXFUN(fast_acoshf,(float));
+float EXFUN(fast_atanhf,(float));
+
+float EXFUN(fast_absf,(float));
+float EXFUN(fast_sqrtf,(float));
+float EXFUN(fast_exp2f,(float));
+float EXFUN(fast_exp10f,(float));
+float EXFUN(fast_expef,(float));
+float EXFUN(fast_log10f,(float));
+float EXFUN(fast_log2f,(float));
+float EXFUN(fast_logef,(float));
+#define	sinf(x)		fast_sinf(x)
+#define	cosf(x)		fast_cosf(x)
+#define	tanf(x)		fast_tanf(x)
+#define	asinf(x)	fast_asinf(x)
+#define	acosf(x)	fast_acosf(x)
+#define	atanf(x)	fast_atanf(x)
+#define	sinhf(x)	fast_sinhf(x)
+#define	coshf(x)	fast_coshf(x)
+#define	tanhf(x)	fast_tanhf(x)
+#define	asinhf(x)	fast_asinhf(x)
+#define	acoshf(x)	fast_acoshf(x)
+#define	atanhf(x)	fast_atanhf(x)
+#define	absf(x)		fast_absf(x)
+#define	sqrtf(x)	fast_sqrtf(x)
+#define	exp2f(x)	fast_exp2f(x)
+#define	exp10f(x)	fast_exp10f(x)
+#define	expef(x)	fast_expef(x)
+#define	log10f(x)	fast_log10f(x)
+#define	log2f(x)	fast_log2f(x)
+#define	logef(x)	fast_logef(x)
+#endif
+/* Override the functions defined in math.h */
+#endif /* __sysvnecv70_target */
+
diff --git a/tools/sdk/include/newlib/machine/ieeefp.h b/tools/sdk/include/newlib/machine/ieeefp.h
new file mode 100644
index 00000000..f11dc053
--- /dev/null
+++ b/tools/sdk/include/newlib/machine/ieeefp.h
@@ -0,0 +1,434 @@
+#ifndef __IEEE_BIG_ENDIAN
+#ifndef __IEEE_LITTLE_ENDIAN
+
+/* This file can define macros to choose variations of the IEEE float
+   format:
+
+   _FLT_LARGEST_EXPONENT_IS_NORMAL
+
+	Defined if the float format uses the largest exponent for finite
+	numbers rather than NaN and infinity representations.  Such a
+	format cannot represent NaNs or infinities at all, but it's FLT_MAX
+	is twice the IEEE value.
+
+   _FLT_NO_DENORMALS
+
+	Defined if the float format does not support IEEE denormals.  Every
+	float with a zero exponent is taken to be a zero representation.
+ 
+   ??? At the moment, there are no equivalent macros above for doubles and
+   the macros are not fully supported by --enable-newlib-hw-fp.
+
+   __IEEE_BIG_ENDIAN
+
+        Defined if the float format is big endian.  This is mutually exclusive
+        with __IEEE_LITTLE_ENDIAN.
+
+   __IEEE_LITTLE_ENDIAN
+ 
+        Defined if the float format is little endian.  This is mutually exclusive
+        with __IEEE_BIG_ENDIAN.
+
+   Note that one of __IEEE_BIG_ENDIAN or __IEEE_LITTLE_ENDIAN must be specified for a
+   platform or error will occur.
+
+   __IEEE_BYTES_LITTLE_ENDIAN
+
+        This flag is used in conjunction with __IEEE_BIG_ENDIAN to describe a situation 
+	whereby multiple words of an IEEE floating point are in big endian order, but the
+	words themselves are little endian with respect to the bytes.
+
+   _DOUBLE_IS_32BITS 
+
+        This is used on platforms that support double by using the 32-bit IEEE
+        float type.
+
+   _FLOAT_ARG
+
+        This represents what type a float arg is passed as.  It is used when the type is
+        not promoted to double.
+	
+*/
+
+#if (defined(__arm__) || defined(__thumb__)) && !defined(__MAVERICK__)
+/* ARM traditionally used big-endian words; and within those words the
+   byte ordering was big or little endian depending upon the target.
+   Modern floating-point formats are naturally ordered; in this case
+   __VFP_FP__ will be defined, even if soft-float.  */
+#ifdef __VFP_FP__
+# ifdef __ARMEL__
+#  define __IEEE_LITTLE_ENDIAN
+# else
+#  define __IEEE_BIG_ENDIAN
+# endif
+#else
+# define __IEEE_BIG_ENDIAN
+# ifdef __ARMEL__
+#  define __IEEE_BYTES_LITTLE_ENDIAN
+# endif
+#endif
+#endif
+
+#if defined (__aarch64__)
+#if defined (__AARCH64EL__)
+#define __IEEE_LITTLE_ENDIAN
+#else
+#define __IEEE_BIG_ENDIAN
+#endif
+#endif
+
+#ifdef __epiphany__
+#define __IEEE_LITTLE_ENDIAN
+#define Sudden_Underflow 1
+#endif
+
+#ifdef __hppa__
+#define __IEEE_BIG_ENDIAN
+#endif
+
+#ifdef __nds32__
+#ifdef __big_endian__
+#define __IEEE_BIG_ENDIAN
+#else
+#define __IEEE_LITTLE_ENDIAN
+#endif
+#endif
+
+#ifdef __SPU__
+#define __IEEE_BIG_ENDIAN
+
+#define isfinite(__y) \
+	(__extension__ ({int __cy; \
+		(sizeof (__y) == sizeof (float))  ? (1) : \
+		(__cy = fpclassify(__y)) != FP_INFINITE && __cy != FP_NAN;}))
+
+#define isinf(__x) ((sizeof (__x) == sizeof (float))  ?  (0) : __isinfd(__x))
+#define isnan(__x) ((sizeof (__x) == sizeof (float))  ?  (0) : __isnand(__x))
+
+/*
+ * Macros for use in ieeefp.h. We can't just define the real ones here
+ * (like those above) as we have name space issues when this is *not*
+ * included via generic the ieeefp.h.
+ */
+#define __ieeefp_isnanf(x)	0
+#define __ieeefp_isinff(x)	0
+#define __ieeefp_finitef(x)	1
+#endif
+
+#ifdef __sparc__
+#ifdef __LITTLE_ENDIAN_DATA__
+#define __IEEE_LITTLE_ENDIAN
+#else
+#define __IEEE_BIG_ENDIAN
+#endif
+#endif
+
+#if defined(__m68k__) || defined(__mc68000__)
+#define __IEEE_BIG_ENDIAN
+#endif
+
+#if defined(__mc68hc11__) || defined(__mc68hc12__) || defined(__mc68hc1x__)
+#define __IEEE_BIG_ENDIAN
+#ifdef __HAVE_SHORT_DOUBLE__
+# define _DOUBLE_IS_32BITS
+#endif
+#endif
+
+#if defined (__H8300__) || defined (__H8300H__) || defined (__H8300S__) || defined (__H8500__) || defined (__H8300SX__)
+#define __IEEE_BIG_ENDIAN
+#define _FLOAT_ARG float
+#define _DOUBLE_IS_32BITS
+#endif
+
+#if defined (__xc16x__) || defined (__xc16xL__) || defined (__xc16xS__)
+#define __IEEE_LITTLE_ENDIAN
+#define _FLOAT_ARG float
+#define _DOUBLE_IS_32BITS
+#endif
+
+
+#ifdef __sh__
+#ifdef __LITTLE_ENDIAN__
+#define __IEEE_LITTLE_ENDIAN
+#else
+#define __IEEE_BIG_ENDIAN
+#endif
+#if defined(__SH2E__) || defined(__SH3E__) || defined(__SH4_SINGLE_ONLY__) || defined(__SH2A_SINGLE_ONLY__)
+#define _DOUBLE_IS_32BITS
+#endif
+#endif
+
+#ifdef _AM29K
+#define __IEEE_BIG_ENDIAN
+#endif
+
+#ifdef _WIN32
+#define __IEEE_LITTLE_ENDIAN
+#endif
+
+#ifdef __i386__
+#define __IEEE_LITTLE_ENDIAN
+#endif
+
+#ifdef __i960__
+#define __IEEE_LITTLE_ENDIAN
+#endif
+
+#ifdef __lm32__
+#define __IEEE_BIG_ENDIAN
+#endif
+
+#ifdef __M32R__
+#define __IEEE_BIG_ENDIAN
+#endif
+
+#if defined(_C4x) || defined(_C3x)
+#define __IEEE_BIG_ENDIAN
+#define _DOUBLE_IS_32BITS
+#endif
+
+#ifdef __TMS320C6X__
+#ifdef _BIG_ENDIAN
+#define __IEEE_BIG_ENDIAN
+#else
+#define __IEEE_LITTLE_ENDIAN
+#endif
+#endif
+
+#ifdef __TIC80__
+#define __IEEE_LITTLE_ENDIAN
+#endif
+
+#ifdef __MIPSEL__
+#define __IEEE_LITTLE_ENDIAN
+#endif
+#ifdef __MIPSEB__
+#define __IEEE_BIG_ENDIAN
+#endif
+
+#ifdef __MMIX__
+#define __IEEE_BIG_ENDIAN
+#endif
+
+#ifdef __D30V__
+#define __IEEE_BIG_ENDIAN
+#endif
+
+/* necv70 was __IEEE_LITTLE_ENDIAN. */
+
+#ifdef __W65__
+#define __IEEE_LITTLE_ENDIAN
+#define _DOUBLE_IS_32BITS
+#endif
+
+#if defined(__Z8001__) || defined(__Z8002__)
+#define __IEEE_BIG_ENDIAN
+#endif
+
+#ifdef __m88k__
+#define __IEEE_BIG_ENDIAN
+#endif
+
+#ifdef __mn10300__
+#define __IEEE_LITTLE_ENDIAN
+#endif
+
+#ifdef __mn10200__
+#define __IEEE_LITTLE_ENDIAN
+#define _DOUBLE_IS_32BITS
+#endif
+
+#ifdef __v800
+#define __IEEE_LITTLE_ENDIAN
+#endif
+
+#ifdef __v850
+#define __IEEE_LITTLE_ENDIAN
+#endif
+
+#ifdef __D10V__
+#define __IEEE_BIG_ENDIAN
+#if __DOUBLE__ == 32
+#define _DOUBLE_IS_32BITS
+#endif
+#endif
+
+#ifdef __PPC__
+#if (defined(_BIG_ENDIAN) && _BIG_ENDIAN) || (defined(_AIX) && _AIX)
+#define __IEEE_BIG_ENDIAN
+#else
+#if (defined(_LITTLE_ENDIAN) && _LITTLE_ENDIAN) || (defined(__sun__) && __sun__) || (defined(_WIN32) && _WIN32)
+#define __IEEE_LITTLE_ENDIAN
+#endif
+#endif
+#endif
+
+#ifdef __xstormy16__
+#define __IEEE_LITTLE_ENDIAN
+#endif
+
+#ifdef __arc__
+#ifdef __big_endian__
+#define __IEEE_BIG_ENDIAN
+#else
+#define __IEEE_LITTLE_ENDIAN
+#endif
+#endif
+
+#ifdef __CRX__
+#define __IEEE_LITTLE_ENDIAN
+#endif
+
+#ifdef __fr30__
+#define __IEEE_BIG_ENDIAN
+#endif
+
+#ifdef __mcore__
+#define __IEEE_BIG_ENDIAN
+#endif
+
+#ifdef __mt__
+#define __IEEE_BIG_ENDIAN
+#endif
+
+#ifdef __frv__
+#define __IEEE_BIG_ENDIAN
+#endif
+
+#ifdef __moxie__
+#ifdef __MOXIE_BIG_ENDIAN__
+#define __IEEE_BIG_ENDIAN
+#else
+#define __IEEE_LITTLE_ENDIAN
+#endif
+#endif
+
+#ifdef __ia64__
+#ifdef __BIG_ENDIAN__
+#define __IEEE_BIG_ENDIAN
+#else
+#define __IEEE_LITTLE_ENDIAN
+#endif
+#endif
+
+#ifdef __AVR__
+#define __IEEE_LITTLE_ENDIAN
+#define _DOUBLE_IS_32BITS
+#endif
+
+#if defined(__or1k__) || defined(__OR1K__) || defined(__OR1KND__)
+#define __IEEE_BIG_ENDIAN
+#endif
+
+#ifdef __IP2K__
+#define __IEEE_BIG_ENDIAN
+#define __SMALL_BITFIELDS
+#define _DOUBLE_IS_32BITS
+#endif
+
+#ifdef __iq2000__
+#define __IEEE_BIG_ENDIAN
+#endif
+
+#ifdef __MAVERICK__
+#ifdef __ARMEL__
+#  define __IEEE_LITTLE_ENDIAN
+#else  /* must be __ARMEB__ */
+#  define __IEEE_BIG_ENDIAN
+#endif /* __ARMEL__ */
+#endif /* __MAVERICK__ */
+
+#ifdef __m32c__
+#define __IEEE_LITTLE_ENDIAN
+#define __SMALL_BITFIELDS
+#endif
+
+#ifdef __CRIS__
+#define __IEEE_LITTLE_ENDIAN
+#endif
+
+#ifdef __BFIN__
+#define __IEEE_LITTLE_ENDIAN
+#endif
+
+#ifdef __x86_64__
+#define __IEEE_LITTLE_ENDIAN
+#endif
+
+#ifdef __mep__
+#ifdef __LITTLE_ENDIAN__
+#define __IEEE_LITTLE_ENDIAN
+#else
+#define __IEEE_BIG_ENDIAN
+#endif
+#endif
+
+#ifdef __MICROBLAZE__
+#ifndef __MICROBLAZEEL__
+#define __IEEE_BIG_ENDIAN
+#else
+#define __IEEE_LITTLE_ENDIAN
+#endif
+#endif
+
+#ifdef __MSP430__
+#define __IEEE_LITTLE_ENDIAN
+#define __SMALL_BITFIELDS	/* 16 Bit INT */
+#endif
+
+#ifdef __RL78__
+#define __IEEE_LITTLE_ENDIAN
+#define __SMALL_BITFIELDS	/* 16 Bit INT */
+#ifndef __RL78_64BIT_DOUBLES__
+#define _DOUBLE_IS_32BITS
+#endif
+#endif
+
+#ifdef __RX__
+
+#ifdef __RX_BIG_ENDIAN__
+#define __IEEE_BIG_ENDIAN
+#else
+#define __IEEE_LITTLE_ENDIAN
+#endif
+
+#ifndef __RX_64BIT_DOUBLES__
+#define _DOUBLE_IS_32BITS
+#endif
+
+#ifdef __RX_16BIT_INTS__
+#define __SMALL_BITFIELDS
+#endif
+
+#endif
+
+#if (defined(__CR16__) || defined(__CR16C__) ||defined(__CR16CP__))
+#define __IEEE_LITTLE_ENDIAN
+#define __SMALL_BITFIELDS	/* 16 Bit INT */
+#endif
+
+#ifdef __NIOS2__
+# ifdef __nios2_big_endian__
+#  define __IEEE_BIG_ENDIAN
+# else
+#  define __IEEE_LITTLE_ENDIAN
+# endif
+#endif
+
+#if (defined(__XTENSA__))
+# ifdef __XTENSA_EB__
+#  define __IEEE_BIG_ENDIAN
+# else
+#  define __IEEE_LITTLE_ENDIAN
+# endif
+#endif
+
+#ifndef __IEEE_BIG_ENDIAN
+#ifndef __IEEE_LITTLE_ENDIAN
+#error Endianess not declared!!
+#endif /* not __IEEE_LITTLE_ENDIAN */
+#endif /* not __IEEE_BIG_ENDIAN */
+
+#endif /* not __IEEE_LITTLE_ENDIAN */
+#endif /* not __IEEE_BIG_ENDIAN */
+
diff --git a/tools/sdk/include/newlib/machine/malloc.h b/tools/sdk/include/newlib/machine/malloc.h
new file mode 100644
index 00000000..fdada9ed
--- /dev/null
+++ b/tools/sdk/include/newlib/machine/malloc.h
@@ -0,0 +1,8 @@
+#ifndef	_MACHMALLOC_H_
+#define	_MACHMALLOC_H_
+
+/* place holder so platforms may add malloc.h extensions */
+
+#endif	/* _MACHMALLOC_H_ */
+
+
diff --git a/tools/sdk/include/newlib/machine/param.h b/tools/sdk/include/newlib/machine/param.h
new file mode 100644
index 00000000..bdf8bf70
--- /dev/null
+++ b/tools/sdk/include/newlib/machine/param.h
@@ -0,0 +1 @@
+/* Place holder for machine-specific param.h.  */
diff --git a/tools/sdk/include/newlib/machine/setjmp-dj.h b/tools/sdk/include/newlib/machine/setjmp-dj.h
new file mode 100644
index 00000000..6ca5e652
--- /dev/null
+++ b/tools/sdk/include/newlib/machine/setjmp-dj.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 1991 DJ Delorie
+ * All rights reserved.
+ *
+ * Redistribution, modification, and use in source and binary forms is permitted
+ * provided that the above copyright notice and following paragraph are
+ * duplicated in all such forms.
+ *
+ * This file is distributed WITHOUT ANY WARRANTY; without even the implied
+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+/* Modified to use SETJMP_DJ_H rather than SETJMP_H to avoid
+   conflicting with setjmp.h.  Ian Taylor, Cygnus support, April,
+   1993.  */
+
+#ifndef _SETJMP_DJ_H_
+#define _SETJMP_DJ_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+  unsigned long eax;
+  unsigned long ebx;
+  unsigned long ecx;
+  unsigned long edx;
+  unsigned long esi;
+  unsigned long edi;
+  unsigned long ebp;
+  unsigned long esp;
+  unsigned long eip;
+} jmp_buf[1];
+
+extern int setjmp(jmp_buf);
+extern void longjmp(jmp_buf, int);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tools/sdk/include/newlib/machine/setjmp.h b/tools/sdk/include/newlib/machine/setjmp.h
new file mode 100644
index 00000000..9f9d9e49
--- /dev/null
+++ b/tools/sdk/include/newlib/machine/setjmp.h
@@ -0,0 +1,453 @@
+
+_BEGIN_STD_C
+
+#if defined(__or1k__) || defined(__or1knd__)
+#define _JBLEN 31 /* 32 GPRs - r0 */
+#define _JBTYPE unsigned long
+#endif
+
+#if defined(__arm__) || defined(__thumb__)
+/*
+ * All callee preserved registers:
+ * v1 - v7, fp, ip, sp, lr, f4, f5, f6, f7
+ */
+#define _JBLEN 23
+#endif
+
+#if defined(__aarch64__)
+#define _JBLEN 22
+#define _JBTYPE long long
+#endif
+
+#if defined(__AVR__)
+#define _JBLEN 24
+#endif
+
+#ifdef __sparc__
+/*
+ * onsstack,sigmask,sp,pc,npc,psr,g1,o0,wbcnt (sigcontext).
+ * All else recovered by under/over(flow) handling.
+ */
+#define	_JBLEN	13
+#endif
+
+#ifdef __BFIN__
+#define _JBLEN  40
+#endif
+
+#ifdef __epiphany__
+/* All callee preserved registers: r4-r10,fp, sp, lr,r15, r32-r39  */
+#define _JBTYPE long long
+#define _JBLEN 10
+#endif
+
+/* necv70 was 9 as well. */
+
+#if defined(__m68k__) || defined(__mc68000__)
+/*
+ * onsstack,sigmask,sp,pc,psl,d2-d7,a2-a6,
+ * fp2-fp7	for 68881.
+ * All else recovered by under/over(flow) handling.
+ */
+#define	_JBLEN	34
+#endif
+
+#if defined(__mc68hc11__) || defined(__mc68hc12__) || defined(__mc68hc1x__)
+/*
+ * D, X, Y are not saved.
+ * Only take into account the pseudo soft registers (max 32).
+ */
+#define _JBLEN  32
+#endif
+
+#ifdef __nds32__
+/* 17 words for GPRs,
+   1 word for $fpcfg.freg and 30 words for FPUs
+   Reserved 2 words for aligement-adjustment. When storeing double-precision
+   floating-point register into memory, the address has to be
+   double-word-aligned.
+   Check libc/machine/nds32/setjmp.S for more information.  */
+#if __NDS32_EXT_FPU_SP__ || __NDS32_EXT_FPU_DP__
+#define	_JBLEN 50
+#else
+#define _JBLEN 18
+#endif
+#endif
+
+#if defined(__Z8001__) || defined(__Z8002__)
+/* 16 regs + pc */
+#define _JBLEN 20
+#endif
+
+#ifdef _AM29K
+/*
+ * onsstack,sigmask,sp,pc,npc,psr,g1,o0,wbcnt (sigcontext).
+ * All else recovered by under/over(flow) handling.
+ */
+#define	_JBLEN	9
+#endif
+
+#ifdef __i386__
+# if defined(__CYGWIN__) && !defined (_JBLEN)
+#  define _JBLEN (13 * 4)
+# elif defined(__unix__) || defined(__rtems__)
+#  define _JBLEN	9
+# else
+#  include "setjmp-dj.h"
+# endif
+#endif
+
+#ifdef __x86_64__
+# ifdef __CYGWIN__
+#  define _JBTYPE long
+#  define _JBLEN  32
+# else
+#  define _JBTYPE long long
+#  define _JBLEN  8
+# endif
+#endif
+
+#ifdef __i960__
+#define _JBLEN 35
+#endif
+
+#ifdef __M32R__
+/* Only 8 words are currently needed.  10 gives us some slop if we need
+   to expand.  */
+#define _JBLEN 10
+#endif
+
+#ifdef __mips__
+# if defined(__mips64)
+#  define _JBTYPE long long
+# endif
+# ifdef __mips_soft_float
+#  define _JBLEN 11
+# else
+#  define _JBLEN 23
+# endif
+#endif
+
+#ifdef __m88000__
+#define _JBLEN 21
+#endif
+
+#ifdef __H8300__
+#define _JBLEN 5
+#define _JBTYPE int
+#endif
+
+#ifdef __H8300H__
+/* same as H8/300 but registers are twice as big */
+#define _JBLEN 5
+#define _JBTYPE long
+#endif
+
+#if defined (__H8300S__) || defined (__H8300SX__)
+/* same as H8/300 but registers are twice as big */
+#define _JBLEN 5
+#define _JBTYPE long
+#endif
+
+#ifdef __H8500__
+#define _JBLEN 4
+#endif
+
+#ifdef  __sh__
+#if __SH5__
+#define _JBLEN 50
+#define _JBTYPE long long
+#else
+#define _JBLEN 20
+#endif /* __SH5__ */
+#endif
+
+#ifdef  __v800
+#define _JBLEN 28
+#endif
+
+#ifdef __PPC__
+#ifdef __ALTIVEC__
+#define _JBLEN 64
+#else
+#define _JBLEN 32
+#endif
+#define _JBTYPE double
+#endif
+
+#ifdef __MICROBLAZE__
+#define _JBLEN  20
+#define _JBTYPE unsigned int
+#endif
+
+#ifdef __hppa__
+/* %r30, %r2-%r18, %r27, pad, %fr12-%fr15.
+   Note space exists for the FP registers, but they are not
+   saved.  */
+#define _JBLEN 28
+#endif
+
+#if defined(__mn10300__) || defined(__mn10200__)
+#ifdef __AM33_2__
+#define _JBLEN 26
+#else
+/* A guess */
+#define _JBLEN 10
+#endif
+#endif
+
+#ifdef __v850
+/* I think our setjmp is saving 15 regs at the moment.  Gives us one word
+   slop if we need to expand.  */
+#define _JBLEN 16
+#endif
+
+#if defined(_C4x)
+#define _JBLEN 10
+#endif
+#if defined(_C3x)
+#define _JBLEN 9
+#endif
+
+#ifdef __TMS320C6X__
+#define _JBLEN 13
+#endif
+
+#ifdef __TIC80__
+#define _JBLEN 13
+#endif
+
+#ifdef __D10V__
+#define _JBLEN 8
+#endif
+
+#ifdef __D30V__
+#define _JBLEN ((64 /* GPR */ + (2*2) /* ACs */ + 18 /* CRs */) / 2)
+#define _JBTYPE double
+#endif
+
+#ifdef __frv__
+#define _JBLEN (68/2)  /* room for 68 32-bit regs */
+#define _JBTYPE double
+#endif
+
+#ifdef __moxie__
+#define _JBLEN 16
+#endif
+
+#ifdef __CRX__
+#define _JBLEN 9
+#endif
+
+#if (defined(__CR16__) || defined(__CR16C__) ||defined(__CR16CP__))
+/* r6, r7, r8, r9, r10, r11, r12 (r12L, r12H), 
+ * r13 (r13L, r13H), ra(raL, raH), sp(spL, spH) */
+#define _JBLEN 14
+#define _JBTYPE unsigned short
+#endif
+
+#ifdef __fr30__
+#define _JBLEN 10
+#endif
+
+#ifdef __iq2000__
+#define _JBLEN 32
+#endif
+
+#ifdef __mcore__
+#define _JBLEN 16
+#endif
+
+#ifdef __MMIX__
+/* Using a layout compatible with GCC's built-in.  */
+#define _JBLEN 5
+#define _JBTYPE unsigned long
+#endif
+
+#ifdef __mt__
+#define _JBLEN 16
+#endif
+
+#ifdef __SPU__
+#define _JBLEN 50 
+#define _JBTYPE __vector signed int
+#endif
+
+#ifdef __xstormy16__
+/* 4 GPRs plus SP plus PC. */
+#define _JBLEN 8
+#endif
+
+#ifdef __XTENSA__
+#if __XTENSA_WINDOWED_ABI__
+
+/* The jmp_buf structure for Xtensa windowed ABI holds the following
+   (where "proc" is the procedure that calls setjmp): 4-12 registers
+   from the window of proc, the 4 words from the save area at proc's $sp
+   (in case a subsequent alloca in proc moves $sp), and the return
+   address within proc.  Everything else is saved on the stack in the
+   normal save areas.  The jmp_buf structure is:
+  
+  	struct jmp_buf {
+  	    int regs[12];
+  	    int save[4];
+  	    void *return_address;
+  	}
+  
+   See the setjmp code for details.  */
+
+#define _JBLEN		17	/* 12 + 4 + 1 */
+
+#else /* __XTENSA_CALL0_ABI__ */
+
+#define _JBLEN		6	/* a0, a1, a12, a13, a14, a15 */
+
+#endif /* __XTENSA_CALL0_ABI__ */
+#endif /* __XTENSA__ */
+
+#ifdef __mep__
+/* 16 GPRs, pc, hi, lo */
+#define _JBLEN 19
+#endif
+
+#ifdef __CRIS__
+#define _JBLEN 18
+#endif
+
+#ifdef __lm32__
+#define _JBLEN 19
+#endif
+
+#ifdef __m32c__
+#if defined(__r8c_cpu__) || defined(__m16c_cpu__)
+#define _JBLEN (22/2)
+#else
+#define _JBLEN (34/2)
+#endif
+#define _JBTYPE unsigned short
+#endif /* __m32c__ */
+
+#ifdef __MSP430__
+#define _JBLEN 9
+
+#ifdef __MSP430X_LARGE__
+#define _JBTYPE unsigned long
+#else
+#define _JBTYPE unsigned short
+#endif
+#endif
+
+#ifdef __RL78__
+/* Three banks of registers, SP, CS, ES, PC */
+#define _JBLEN (8*3+8)
+#define _JBTYPE unsigned char
+#endif
+
+/*
+ * There are two versions of setjmp()/longjmp():
+ *   1) Compiler (gcc) built-in versions.
+ *   2) Function-call versions.
+ *
+ * The built-in versions are used most of the time.  When used, gcc replaces
+ * calls to setjmp()/longjmp() with inline assembly code.  The built-in 
+ * versions save/restore a variable number of registers.
+
+ * _JBLEN is set to 40 to be ultra-safe with the built-in versions.
+ * It only needs to be 12 for the function-call versions
+ * but this data structure is used by both versions.
+ */
+#ifdef __NIOS2__
+#define _JBLEN 40
+#define _JBTYPE unsigned long
+#endif
+
+#ifdef __RX__
+#define _JBLEN 0x44
+#endif
+
+#ifdef _JBLEN
+#ifdef _JBTYPE
+typedef	_JBTYPE jmp_buf[_JBLEN];
+#else
+typedef	int jmp_buf[_JBLEN];
+#endif
+#endif
+
+_END_STD_C
+
+#if defined(__CYGWIN__) || defined(__rtems__)
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* POSIX sigsetjmp/siglongjmp macros */
+#ifdef _JBTYPE
+typedef _JBTYPE sigjmp_buf[_JBLEN+1+((sizeof (_JBTYPE) + sizeof (sigset_t) - 1)
+				     /sizeof (_JBTYPE))];
+#else
+typedef int sigjmp_buf[_JBLEN+1+(sizeof (sigset_t)/sizeof (int))];
+#endif
+
+#define _SAVEMASK	_JBLEN
+#define _SIGMASK	(_JBLEN+1)
+
+#ifdef __CYGWIN__
+# define _CYGWIN_WORKING_SIGSETJMP
+#endif
+
+#ifdef _POSIX_THREADS
+#define __SIGMASK_FUNC pthread_sigmask
+#else
+#define __SIGMASK_FUNC sigprocmask
+#endif
+
+#if defined(__GNUC__)
+
+#define sigsetjmp(env, savemask) \
+            __extension__ \
+            ({ \
+              sigjmp_buf *_sjbuf = &(env); \
+              ((*_sjbuf)[_SAVEMASK] = savemask,\
+              __SIGMASK_FUNC (SIG_SETMASK, 0, (sigset_t *)((*_sjbuf) + _SIGMASK)),\
+              setjmp (*_sjbuf)); \
+            })
+
+#define siglongjmp(env, val) \
+            __extension__ \
+            ({ \
+              sigjmp_buf *_sjbuf = &(env); \
+              ((((*_sjbuf)[_SAVEMASK]) ? \
+               __SIGMASK_FUNC (SIG_SETMASK, (sigset_t *)((*_sjbuf) + _SIGMASK), 0)\
+               : 0), \
+               longjmp (*_sjbuf, val)); \
+            })
+
+#else /* !__GNUC__ */
+
+#define sigsetjmp(env, savemask) ((env)[_SAVEMASK] = savemask,\
+               __SIGMASK_FUNC (SIG_SETMASK, 0, (sigset_t *) ((env) + _SIGMASK)),\
+               setjmp (env))
+
+#define siglongjmp(env, val) ((((env)[_SAVEMASK])?\
+               __SIGMASK_FUNC (SIG_SETMASK, (sigset_t *) ((env) + _SIGMASK), 0):0),\
+               longjmp (env, val))
+
+#endif
+
+/* POSIX _setjmp/_longjmp, maintained for XSI compatibility.  These
+   are equivalent to sigsetjmp/siglongjmp when not saving the signal mask.
+   New applications should use sigsetjmp/siglongjmp instead. */
+#ifdef __CYGWIN__
+extern void _longjmp(jmp_buf, int);
+extern int _setjmp(jmp_buf);
+#else
+#define _setjmp(env)		sigsetjmp ((env), 0)
+#define _longjmp(env, val)	siglongjmp ((env), (val))
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __CYGWIN__ or __rtems__ */
diff --git a/tools/sdk/include/newlib/machine/stdlib.h b/tools/sdk/include/newlib/machine/stdlib.h
new file mode 100644
index 00000000..fa3f3a13
--- /dev/null
+++ b/tools/sdk/include/newlib/machine/stdlib.h
@@ -0,0 +1,8 @@
+#ifndef	_MACHSTDLIB_H_
+#define	_MACHSTDLIB_H_
+
+/* place holder so platforms may add stdlib.h extensions */
+
+#endif	/* _MACHSTDLIB_H_ */
+
+
diff --git a/tools/sdk/include/newlib/machine/termios.h b/tools/sdk/include/newlib/machine/termios.h
new file mode 100644
index 00000000..41fd4593
--- /dev/null
+++ b/tools/sdk/include/newlib/machine/termios.h
@@ -0,0 +1 @@
+#define __MAX_BAUD  B4000000
diff --git a/tools/sdk/include/newlib/machine/time.h b/tools/sdk/include/newlib/machine/time.h
new file mode 100644
index 00000000..06e2ccff
--- /dev/null
+++ b/tools/sdk/include/newlib/machine/time.h
@@ -0,0 +1,19 @@
+#ifndef	_MACHTIME_H_
+#define	_MACHTIME_H_
+
+#if defined(__rtems__)
+#define _CLOCKS_PER_SEC_  sysconf(_SC_CLK_TCK)
+#else  /* !__rtems__ */
+#if defined(__aarch64__) || defined(__arm__) || defined(__thumb__)
+#define _CLOCKS_PER_SEC_ 100
+#endif
+#endif /* !__rtems__ */
+
+#ifdef __SPU__
+#include 
+int nanosleep (const struct timespec *, struct timespec *);
+#endif
+
+#endif	/* _MACHTIME_H_ */
+
+
diff --git a/tools/sdk/include/newlib/machine/types.h b/tools/sdk/include/newlib/machine/types.h
new file mode 100644
index 00000000..40a75faa
--- /dev/null
+++ b/tools/sdk/include/newlib/machine/types.h
@@ -0,0 +1,30 @@
+#ifndef	_MACHTYPES_H_
+#define	_MACHTYPES_H_
+
+/*
+ *  The following section is RTEMS specific and is needed to more
+ *  closely match the types defined in the BSD machine/types.h.
+ *  This is needed to let the RTEMS/BSD TCP/IP stack compile.
+ */
+#if defined(__rtems__)
+#include 
+#endif
+
+#define	_CLOCK_T_	unsigned long		/* clock() */
+#define	_TIME_T_	long			/* time() */
+#define _CLOCKID_T_ 	unsigned long
+#define _TIMER_T_   	unsigned long
+
+#ifndef _HAVE_SYSTYPES
+typedef long int __off_t;
+typedef int __pid_t;
+#ifdef __GNUC__
+__extension__ typedef long long int __loff_t;
+#else
+typedef long int __loff_t;
+#endif
+#endif
+
+#endif	/* _MACHTYPES_H_ */
+
+
diff --git a/tools/sdk/include/newlib/malloc.h b/tools/sdk/include/newlib/malloc.h
new file mode 100644
index 00000000..41b5efdc
--- /dev/null
+++ b/tools/sdk/include/newlib/malloc.h
@@ -0,0 +1,169 @@
+/* malloc.h -- header file for memory routines.  */
+
+#ifndef _INCLUDE_MALLOC_H_
+#define _INCLUDE_MALLOC_H_
+
+#include <_ansi.h>
+#include 
+
+#define __need_size_t
+#include 
+
+/* include any machine-specific extensions */
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* This version of struct mallinfo must match the one in
+   libc/stdlib/mallocr.c.  */
+
+struct mallinfo {
+  size_t arena;    /* total space allocated from system */
+  size_t ordblks;  /* number of non-inuse chunks */
+  size_t smblks;   /* unused -- always zero */
+  size_t hblks;    /* number of mmapped regions */
+  size_t hblkhd;   /* total space in mmapped regions */
+  size_t usmblks;  /* unused -- always zero */
+  size_t fsmblks;  /* unused -- always zero */
+  size_t uordblks; /* total allocated space */
+  size_t fordblks; /* total non-inuse space */
+  size_t keepcost; /* top-most, releasable (via malloc_trim) space */
+};	
+
+/* The routines.  */
+
+extern _PTR malloc _PARAMS ((size_t));
+#ifdef __CYGWIN__
+#undef _malloc_r
+#define _malloc_r(r, s) malloc (s)
+#else
+extern _PTR _malloc_r _PARAMS ((struct _reent *, size_t));
+#endif
+
+extern _VOID free _PARAMS ((_PTR));
+#ifdef __CYGWIN__
+#undef _free_r
+#define _free_r(r, p) free (p)
+#else
+extern _VOID _free_r _PARAMS ((struct _reent *, _PTR));
+#endif
+
+extern _PTR realloc _PARAMS ((_PTR, size_t));
+#ifdef __CYGWIN__
+#undef _realloc_r
+#define _realloc_r(r, p, s) realloc (p, s)
+#else
+extern _PTR _realloc_r _PARAMS ((struct _reent *, _PTR, size_t));
+#endif
+
+extern _PTR calloc _PARAMS ((size_t, size_t));
+#ifdef __CYGWIN__
+#undef _calloc_r
+#define _calloc_r(r, s1, s2) calloc (s1, s2);
+#else
+extern _PTR _calloc_r _PARAMS ((struct _reent *, size_t, size_t));
+#endif
+
+extern _PTR memalign _PARAMS ((size_t, size_t));
+#ifdef __CYGWIN__
+#undef _memalign_r
+#define _memalign_r(r, s1, s2) memalign (s1, s2);
+#else
+extern _PTR _memalign_r _PARAMS ((struct _reent *, size_t, size_t));
+#endif
+
+extern struct mallinfo mallinfo _PARAMS ((void));
+#ifdef __CYGWIN__
+#undef _mallinfo_r
+#define _mallinfo_r(r) mallinfo ()
+#else
+extern struct mallinfo _mallinfo_r _PARAMS ((struct _reent *));
+#endif
+
+extern void malloc_stats _PARAMS ((void));
+#ifdef __CYGWIN__
+#undef _malloc_stats_r
+#define _malloc_stats_r(r) malloc_stats ()
+#else
+extern void _malloc_stats_r _PARAMS ((struct _reent *));
+#endif
+
+extern int mallopt _PARAMS ((int, int));
+#ifdef __CYGWIN__
+#undef _mallopt_r
+#define _mallopt_r(i1, i2) mallopt (i1, i2)
+#else
+extern int _mallopt_r _PARAMS ((struct _reent *, int, int));
+#endif
+
+extern size_t malloc_usable_size _PARAMS ((_PTR));
+#ifdef __CYGWIN__
+#undef _malloc_usable_size_r
+#define _malloc_usable_size_r(r, p) malloc_usable_size (p)
+#else
+extern size_t _malloc_usable_size_r _PARAMS ((struct _reent *, _PTR));
+#endif
+
+/* These aren't too useful on an embedded system, but we define them
+   anyhow.  */
+
+extern _PTR valloc _PARAMS ((size_t));
+#ifdef __CYGWIN__
+#undef _valloc_r
+#define _valloc_r(r, s) valloc (s)
+#else
+extern _PTR _valloc_r _PARAMS ((struct _reent *, size_t));
+#endif
+
+extern _PTR pvalloc _PARAMS ((size_t));
+#ifdef __CYGWIN__
+#undef _pvalloc_r
+#define _pvalloc_r(r, s) pvalloc (s)
+#else
+extern _PTR _pvalloc_r _PARAMS ((struct _reent *, size_t));
+#endif
+
+extern int malloc_trim _PARAMS ((size_t));
+#ifdef __CYGWIN__
+#undef _malloc_trim_r
+#define _malloc_trim_r(r, s) malloc_trim (s)
+#else
+extern int _malloc_trim_r _PARAMS ((struct _reent *, size_t));
+#endif
+
+/* A compatibility routine for an earlier version of the allocator.  */
+
+extern _VOID mstats _PARAMS ((char *));
+#ifdef __CYGWIN__
+#undef _mstats_r
+#define _mstats_r(r, p) mstats (p)
+#else
+extern _VOID _mstats_r _PARAMS ((struct _reent *, char *));
+#endif
+
+/* SVID2/XPG mallopt options */
+
+#define M_MXFAST  1    /* UNUSED in this malloc */
+#define M_NLBLKS  2    /* UNUSED in this malloc */
+#define M_GRAIN   3    /* UNUSED in this malloc */
+#define M_KEEP    4    /* UNUSED in this malloc */
+
+/* mallopt options that actually do something */
+  
+#define M_TRIM_THRESHOLD    -1
+#define M_TOP_PAD           -2
+#define M_MMAP_THRESHOLD    -3 
+#define M_MMAP_MAX          -4
+
+#ifndef __CYGWIN__
+/* Some systems provide this, so do too for compatibility.  */
+extern void cfree _PARAMS ((_PTR));
+#endif /* __CYGWIN__ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _INCLUDE_MALLOC_H_ */
diff --git a/tools/sdk/include/newlib/math.h b/tools/sdk/include/newlib/math.h
new file mode 100644
index 00000000..d16ce307
--- /dev/null
+++ b/tools/sdk/include/newlib/math.h
@@ -0,0 +1,615 @@
+#ifndef  _MATH_H_
+
+#define  _MATH_H_
+
+#include 
+#include 
+#include "_ansi.h"
+
+_BEGIN_STD_C
+
+/* __dmath, __fmath, and __ldmath are only here for backwards compatibility
+ * in case any code used them.  They are no longer used by Newlib, itself,
+ * other than legacy.  */
+union __dmath
+{
+  double d;
+  __ULong i[2];
+};
+
+union __fmath
+{
+  float f;
+  __ULong i[1];
+};
+
+#if defined(_HAVE_LONG_DOUBLE)
+union __ldmath
+{
+  long double ld;
+  __ULong i[4];
+};
+#endif
+
+/* Natural log of 2 */
+#define _M_LN2        0.693147180559945309417
+
+#if __GNUC_PREREQ (3, 3)
+ /* gcc >= 3.3 implicitly defines builtins for HUGE_VALx values.  */
+
+# ifndef HUGE_VAL
+#  define HUGE_VAL (__builtin_huge_val())
+# endif
+
+# ifndef HUGE_VALF
+#  define HUGE_VALF (__builtin_huge_valf())
+# endif
+
+# ifndef HUGE_VALL
+#  define HUGE_VALL (__builtin_huge_vall())
+# endif
+
+# ifndef INFINITY
+#  define INFINITY (__builtin_inff())
+# endif
+
+# ifndef NAN
+#  define NAN (__builtin_nanf(""))
+# endif
+
+#else /* !gcc >= 3.3  */
+
+ /*      No builtins.  Use fixed defines instead.  (All 3 HUGE plus the INFINITY
+  * and NAN macros are required to be constant expressions.  Using a variable--
+  * even a static const--does not meet this requirement, as it cannot be
+  * evaluated at translation time.)
+  *      The infinities are done using numbers that are far in excess of
+  * something that would be expected to be encountered in a floating-point
+  * implementation.  (A more certain way uses values from float.h, but that is
+  * avoided because system includes are not supposed to include each other.)
+  *      This method might produce warnings from some compilers.  (It does in
+  * newer GCCs, but not for ones that would hit this #else.)  If this happens,
+  * please report details to the Newlib mailing list.  */
+
+ #ifndef HUGE_VAL
+  #define HUGE_VAL (1.0e999999999)
+ #endif
+
+ #ifndef HUGE_VALF
+  #define HUGE_VALF (1.0e999999999F)
+ #endif
+
+ #if !defined(HUGE_VALL)  &&  defined(_HAVE_LONG_DOUBLE)
+  #define HUGE_VALL (1.0e999999999L)
+ #endif
+
+ #if !defined(INFINITY)
+  #define INFINITY (HUGE_VALF)
+ #endif
+
+ #if !defined(NAN)
+  #if defined(__GNUC__)  &&  defined(__cplusplus)
+    /* Exception:  older g++ versions warn about the divide by 0 used in the
+     * normal case (even though older gccs do not).  This trick suppresses the
+     * warning, but causes errors for plain gcc, so is only used in the one
+     * special case.  */
+    static const union { __ULong __i[1]; float __d; } __Nanf = {0x7FC00000};
+    #define NAN (__Nanf.__d)
+  #else
+    #define NAN (0.0F/0.0F)
+  #endif
+ #endif
+
+#endif /* !gcc >= 3.3  */
+
+/* Reentrant ANSI C functions.  */
+
+#ifndef __math_68881
+extern double atan _PARAMS((double));
+extern double cos _PARAMS((double));
+extern double sin _PARAMS((double));
+extern double tan _PARAMS((double));
+extern double tanh _PARAMS((double));
+extern double frexp _PARAMS((double, int *));
+extern double modf _PARAMS((double, double *));
+extern double ceil _PARAMS((double));
+extern double fabs _PARAMS((double));
+extern double floor _PARAMS((double));
+#endif /* ! defined (__math_68881) */
+
+/* Non reentrant ANSI C functions.  */
+
+#ifndef _REENT_ONLY
+#ifndef __math_68881
+extern double acos _PARAMS((double));
+extern double asin _PARAMS((double));
+extern double atan2 _PARAMS((double, double));
+extern double cosh _PARAMS((double));
+extern double sinh _PARAMS((double));
+extern double exp _PARAMS((double));
+extern double ldexp _PARAMS((double, int));
+extern double log _PARAMS((double));
+extern double log10 _PARAMS((double));
+extern double pow _PARAMS((double, double));
+extern double sqrt _PARAMS((double));
+extern double fmod _PARAMS((double, double));
+#endif /* ! defined (__math_68881) */
+#endif /* ! defined (_REENT_ONLY) */
+
+#if !defined(__STRICT_ANSI__) || defined(__cplusplus) || \
+  (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L)
+
+/* ISO C99 types and macros. */
+
+/* FIXME:  FLT_EVAL_METHOD should somehow be gotten from float.h (which is hard,
+ * considering that the standard says the includes it defines should not
+ * include other includes that it defines) and that value used.  (This can be
+ * solved, but autoconf has a bug which makes the solution more difficult, so
+ * it has been skipped for now.)  */
+#if !defined(FLT_EVAL_METHOD) && defined(__FLT_EVAL_METHOD__)
+  #define FLT_EVAL_METHOD __FLT_EVAL_METHOD__
+  #define __TMP_FLT_EVAL_METHOD
+#endif /* FLT_EVAL_METHOD */
+#if defined FLT_EVAL_METHOD
+  #if FLT_EVAL_METHOD == 0
+    typedef float  float_t;
+    typedef double double_t;
+   #elif FLT_EVAL_METHOD == 1
+    typedef double float_t;
+    typedef double double_t;
+   #elif FLT_EVAL_METHOD == 2
+    typedef long double float_t;
+    typedef long double double_t;
+   #else
+    /* Implementation-defined.  Assume float_t and double_t have been
+     * defined previously for this configuration (e.g. config.h). */
+  #endif
+#else
+    /* Assume basic definitions.  */
+    typedef float  float_t;
+    typedef double double_t;
+#endif
+#if defined(__TMP_FLT_EVAL_METHOD)
+  #undef FLT_EVAL_METHOD
+#endif
+
+#define FP_NAN         0
+#define FP_INFINITE    1
+#define FP_ZERO        2
+#define FP_SUBNORMAL   3
+#define FP_NORMAL      4
+
+#ifndef FP_ILOGB0
+# define FP_ILOGB0 (-INT_MAX)
+#endif
+#ifndef FP_ILOGBNAN
+# define FP_ILOGBNAN INT_MAX
+#endif
+
+#ifndef MATH_ERRNO
+# define MATH_ERRNO 1
+#endif
+#ifndef MATH_ERREXCEPT
+# define MATH_ERREXCEPT 2
+#endif
+#ifndef math_errhandling
+# define math_errhandling MATH_ERRNO
+#endif
+
+extern int __isinff (float x);
+extern int __isinfd (double x);
+extern int __isnanf (float x);
+extern int __isnand (double x);
+extern int __fpclassifyf (float x);
+extern int __fpclassifyd (double x);
+extern int __signbitf (float x);
+extern int __signbitd (double x);
+
+#define fpclassify(__x) \
+	((sizeof(__x) == sizeof(float))  ? __fpclassifyf(__x) : \
+	__fpclassifyd(__x))
+
+#ifndef isfinite
+  #define isfinite(__y) \
+          (__extension__ ({int __cy = fpclassify(__y); \
+                           __cy != FP_INFINITE && __cy != FP_NAN;}))
+#endif
+
+/* Note: isinf and isnan were once functions in newlib that took double
+ *       arguments.  C99 specifies that these names are reserved for macros
+ *       supporting multiple floating point types.  Thus, they are
+ *       now defined as macros.  Implementations of the old functions
+ *       taking double arguments still exist for compatibility purposes
+ *       (prototypes for them are in ).  */
+#ifndef isinf
+  #define isinf(y) (fpclassify(y) == FP_INFINITE)
+#endif
+
+#ifndef isnan
+  #define isnan(y) (fpclassify(y) == FP_NAN)
+#endif
+
+#define isnormal(y) (fpclassify(y) == FP_NORMAL)
+#define signbit(__x) \
+	((sizeof(__x) == sizeof(float))  ?  __signbitf(__x) : \
+		__signbitd(__x))
+
+#define isgreater(x,y) \
+          (__extension__ ({__typeof__(x) __x = (x); __typeof__(y) __y = (y); \
+                           !isunordered(__x,__y) && (__x > __y);}))
+#define isgreaterequal(x,y) \
+          (__extension__ ({__typeof__(x) __x = (x); __typeof__(y) __y = (y); \
+                           !isunordered(__x,__y) && (__x >= __y);}))
+#define isless(x,y) \
+          (__extension__ ({__typeof__(x) __x = (x); __typeof__(y) __y = (y); \
+                           !isunordered(__x,__y) && (__x < __y);}))
+#define islessequal(x,y) \
+          (__extension__ ({__typeof__(x) __x = (x); __typeof__(y) __y = (y); \
+                           !isunordered(__x,__y) && (__x <= __y);}))
+#define islessgreater(x,y) \
+          (__extension__ ({__typeof__(x) __x = (x); __typeof__(y) __y = (y); \
+                           !isunordered(__x,__y) && (__x < __y || __x > __y);}))
+
+#define isunordered(a,b) \
+          (__extension__ ({__typeof__(a) __a = (a); __typeof__(b) __b = (b); \
+                           fpclassify(__a) == FP_NAN || fpclassify(__b) == FP_NAN;}))
+
+/* Non ANSI double precision functions.  */
+
+extern double infinity _PARAMS((void));
+extern double nan _PARAMS((const char *));
+extern int finite _PARAMS((double));
+extern double copysign _PARAMS((double, double));
+extern double logb _PARAMS((double));
+extern int ilogb _PARAMS((double));
+
+extern double asinh _PARAMS((double));
+extern double cbrt _PARAMS((double));
+extern double nextafter _PARAMS((double, double));
+extern double rint _PARAMS((double));
+extern double scalbn _PARAMS((double, int));
+
+extern double exp2 _PARAMS((double));
+extern double scalbln _PARAMS((double, long int));
+extern double tgamma _PARAMS((double));
+extern double nearbyint _PARAMS((double));
+extern long int lrint _PARAMS((double));
+extern long long int llrint _PARAMS((double));
+extern double round _PARAMS((double));
+extern long int lround _PARAMS((double));
+extern long long int llround _PARAMS((double));
+extern double trunc _PARAMS((double));
+extern double remquo _PARAMS((double, double, int *));
+extern double fdim _PARAMS((double, double));
+extern double fmax _PARAMS((double, double));
+extern double fmin _PARAMS((double, double));
+extern double fma _PARAMS((double, double, double));
+
+#ifndef __math_68881
+extern double log1p _PARAMS((double));
+extern double expm1 _PARAMS((double));
+#endif /* ! defined (__math_68881) */
+
+#ifndef _REENT_ONLY
+extern double acosh _PARAMS((double));
+extern double atanh _PARAMS((double));
+extern double remainder _PARAMS((double, double));
+extern double gamma _PARAMS((double));
+extern double lgamma _PARAMS((double));
+extern double erf _PARAMS((double));
+extern double erfc _PARAMS((double));
+extern double log2 _PARAMS((double));
+#if !defined(__cplusplus)
+#define log2(x) (log (x) / _M_LN2)
+#endif
+
+#ifndef __math_68881
+extern double hypot _PARAMS((double, double));
+#endif
+
+#endif /* ! defined (_REENT_ONLY) */
+
+/* Single precision versions of ANSI functions.  */
+
+extern float atanf _PARAMS((float));
+extern float cosf _PARAMS((float));
+extern float sinf _PARAMS((float));
+extern float tanf _PARAMS((float));
+extern float tanhf _PARAMS((float));
+extern float frexpf _PARAMS((float, int *));
+extern float modff _PARAMS((float, float *));
+extern float ceilf _PARAMS((float));
+extern float fabsf _PARAMS((float));
+extern float floorf _PARAMS((float));
+
+#ifndef _REENT_ONLY
+extern float acosf _PARAMS((float));
+extern float asinf _PARAMS((float));
+extern float atan2f _PARAMS((float, float));
+extern float coshf _PARAMS((float));
+extern float sinhf _PARAMS((float));
+extern float expf _PARAMS((float));
+extern float ldexpf _PARAMS((float, int));
+extern float logf _PARAMS((float));
+extern float log10f _PARAMS((float));
+extern float powf _PARAMS((float, float));
+extern float sqrtf _PARAMS((float));
+extern float fmodf _PARAMS((float, float));
+#endif /* ! defined (_REENT_ONLY) */
+
+/* Other single precision functions.  */
+
+extern float exp2f _PARAMS((float));
+extern float scalblnf _PARAMS((float, long int));
+extern float tgammaf _PARAMS((float));
+extern float nearbyintf _PARAMS((float));
+extern long int lrintf _PARAMS((float));
+extern long long int llrintf _PARAMS((float));
+extern float roundf _PARAMS((float));
+extern long int lroundf _PARAMS((float));
+extern long long int llroundf _PARAMS((float));
+extern float truncf _PARAMS((float));
+extern float remquof _PARAMS((float, float, int *));
+extern float fdimf _PARAMS((float, float));
+extern float fmaxf _PARAMS((float, float));
+extern float fminf _PARAMS((float, float));
+extern float fmaf _PARAMS((float, float, float));
+
+extern float infinityf _PARAMS((void));
+extern float nanf _PARAMS((const char *));
+extern int finitef _PARAMS((float));
+extern float copysignf _PARAMS((float, float));
+extern float logbf _PARAMS((float));
+extern int ilogbf _PARAMS((float));
+
+extern float asinhf _PARAMS((float));
+extern float cbrtf _PARAMS((float));
+extern float nextafterf _PARAMS((float, float));
+extern float rintf _PARAMS((float));
+extern float scalbnf _PARAMS((float, int));
+extern float log1pf _PARAMS((float));
+extern float expm1f _PARAMS((float));
+
+#ifndef _REENT_ONLY
+extern float acoshf _PARAMS((float));
+extern float atanhf _PARAMS((float));
+extern float remainderf _PARAMS((float, float));
+extern float gammaf _PARAMS((float));
+extern float lgammaf _PARAMS((float));
+extern float erff _PARAMS((float));
+extern float erfcf _PARAMS((float));
+extern float log2f _PARAMS((float));
+extern float hypotf _PARAMS((float, float));
+#endif /* ! defined (_REENT_ONLY) */
+
+/* On platforms where long double equals double.  */
+#ifdef _LDBL_EQ_DBL
+/* Reentrant ANSI C functions.  */
+#ifndef __math_68881
+extern long double atanl _PARAMS((long double));
+extern long double cosl _PARAMS((long double));
+extern long double sinl _PARAMS((long double));
+extern long double tanl _PARAMS((long double));
+extern long double tanhl _PARAMS((long double));
+extern long double frexpl _PARAMS((long double, int *));
+extern long double modfl _PARAMS((long double, long double *));
+extern long double ceill _PARAMS((long double));
+extern long double fabsl _PARAMS((long double));
+extern long double floorl _PARAMS((long double));
+extern long double log1pl _PARAMS((long double));
+extern long double expm1l _PARAMS((long double));
+#endif /* ! defined (__math_68881) */
+/* Non reentrant ANSI C functions.  */
+#ifndef _REENT_ONLY
+#ifndef __math_68881
+extern long double acosl _PARAMS((long double));
+extern long double asinl _PARAMS((long double));
+extern long double atan2l _PARAMS((long double, long double));
+extern long double coshl _PARAMS((long double));
+extern long double sinhl _PARAMS((long double));
+extern long double expl _PARAMS((long double));
+extern long double ldexpl _PARAMS((long double, int));
+extern long double logl _PARAMS((long double));
+extern long double log10l _PARAMS((long double));
+extern long double powl _PARAMS((long double, long double));
+extern long double sqrtl _PARAMS((long double));
+extern long double fmodl _PARAMS((long double, long double));
+extern long double hypotl _PARAMS((long double, long double));
+#endif /* ! defined (__math_68881) */
+#endif /* ! defined (_REENT_ONLY) */
+extern long double copysignl _PARAMS((long double, long double));
+extern long double nanl _PARAMS((const char *));
+extern int ilogbl _PARAMS((long double));
+extern long double asinhl _PARAMS((long double));
+extern long double cbrtl _PARAMS((long double));
+extern long double nextafterl _PARAMS((long double, long double));
+extern float nexttowardf _PARAMS((float, long double));
+extern double nexttoward _PARAMS((double, long double));
+extern long double nexttowardl _PARAMS((long double, long double));
+extern long double logbl _PARAMS((long double));
+extern long double log2l _PARAMS((long double));
+extern long double rintl _PARAMS((long double));
+extern long double scalbnl _PARAMS((long double, int));
+extern long double exp2l _PARAMS((long double));
+extern long double scalblnl _PARAMS((long double, long));
+extern long double tgammal _PARAMS((long double));
+extern long double nearbyintl _PARAMS((long double));
+extern long int lrintl _PARAMS((long double));
+extern long long int llrintl _PARAMS((long double));
+extern long double roundl _PARAMS((long double));
+extern long lroundl _PARAMS((long double));
+extern long long int llroundl _PARAMS((long double));
+extern long double truncl _PARAMS((long double));
+extern long double remquol _PARAMS((long double, long double, int *));
+extern long double fdiml _PARAMS((long double, long double));
+extern long double fmaxl _PARAMS((long double, long double));
+extern long double fminl _PARAMS((long double, long double));
+extern long double fmal _PARAMS((long double, long double, long double));
+#ifndef _REENT_ONLY
+extern long double acoshl _PARAMS((long double));
+extern long double atanhl _PARAMS((long double));
+extern long double remainderl _PARAMS((long double, long double));
+extern long double lgammal _PARAMS((long double));
+extern long double erfl _PARAMS((long double));
+extern long double erfcl _PARAMS((long double));
+#endif /* ! defined (_REENT_ONLY) */
+#else /* !_LDBL_EQ_DBL */
+#ifdef __i386__
+/* Other long double precision functions.  */
+extern _LONG_DOUBLE rintl _PARAMS((_LONG_DOUBLE));
+extern long int lrintl _PARAMS((_LONG_DOUBLE));
+extern long long int llrintl _PARAMS((_LONG_DOUBLE));
+#endif /* __i386__ */
+#endif /* !_LDBL_EQ_DBL */
+
+#endif /* !defined (__STRICT_ANSI__) || defined(__cplusplus) || (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) */
+
+#if !defined (__STRICT_ANSI__) || defined(__cplusplus)
+
+extern double drem _PARAMS((double, double));
+extern void sincos _PARAMS((double, double *, double *));
+extern double gamma_r _PARAMS((double, int *));
+extern double lgamma_r _PARAMS((double, int *));
+
+extern double y0 _PARAMS((double));
+extern double y1 _PARAMS((double));
+extern double yn _PARAMS((int, double));
+extern double j0 _PARAMS((double));
+extern double j1 _PARAMS((double));
+extern double jn _PARAMS((int, double));
+
+extern float dremf _PARAMS((float, float));
+extern void sincosf _PARAMS((float, float *, float *));
+extern float gammaf_r _PARAMS((float, int *));
+extern float lgammaf_r _PARAMS((float, int *));
+
+extern float y0f _PARAMS((float));
+extern float y1f _PARAMS((float));
+extern float ynf _PARAMS((int, float));
+extern float j0f _PARAMS((float));
+extern float j1f _PARAMS((float));
+extern float jnf _PARAMS((int, float));
+
+/* GNU extensions */
+# ifndef exp10
+extern double exp10 _PARAMS((double));
+# endif
+# ifndef pow10
+extern double pow10 _PARAMS((double));
+# endif
+# ifndef exp10f
+extern float exp10f _PARAMS((float));
+# endif
+# ifndef pow10f
+extern float pow10f _PARAMS((float));
+# endif
+
+#endif /* !defined (__STRICT_ANSI__) || defined(__cplusplus) */
+
+#ifndef __STRICT_ANSI__
+
+/* The gamma functions use a global variable, signgam.  */
+#ifndef _REENT_ONLY
+#define signgam (*__signgam())
+extern int *__signgam _PARAMS((void));
+#endif /* ! defined (_REENT_ONLY) */
+
+#define __signgam_r(ptr) _REENT_SIGNGAM(ptr)
+
+/* The exception structure passed to the matherr routine.  */
+/* We have a problem when using C++ since `exception' is a reserved
+   name in C++.  */
+#ifdef __cplusplus
+struct __exception
+#else
+struct exception
+#endif
+{
+  int type;
+  char *name;
+  double arg1;
+  double arg2;
+  double retval;
+  int err;
+};
+
+#ifdef __cplusplus
+extern int matherr _PARAMS((struct __exception *e));
+#else
+extern int matherr _PARAMS((struct exception *e));
+#endif
+
+/* Values for the type field of struct exception.  */
+
+#define DOMAIN 1
+#define SING 2
+#define OVERFLOW 3
+#define UNDERFLOW 4
+#define TLOSS 5
+#define PLOSS 6
+
+#endif /* ! defined (__STRICT_ANSI__) */
+
+/* Useful constants.  */
+
+#if !defined(__STRICT_ANSI__) || ((_XOPEN_SOURCE - 0) >= 500)
+
+#define MAXFLOAT	3.40282347e+38F
+
+#define M_E		2.7182818284590452354
+#define M_LOG2E		1.4426950408889634074
+#define M_LOG10E	0.43429448190325182765
+#define M_LN2		_M_LN2
+#define M_LN10		2.30258509299404568402
+#define M_PI		3.14159265358979323846
+#define M_PI_2		1.57079632679489661923
+#define M_PI_4		0.78539816339744830962
+#define M_1_PI		0.31830988618379067154
+#define M_2_PI		0.63661977236758134308
+#define M_2_SQRTPI	1.12837916709551257390
+#define M_SQRT2		1.41421356237309504880
+#define M_SQRT1_2	0.70710678118654752440
+
+#endif
+
+#ifndef __STRICT_ANSI__
+
+#define M_TWOPI         (M_PI * 2.0)
+#define M_3PI_4		2.3561944901923448370E0
+#define M_SQRTPI        1.77245385090551602792981
+#define M_LN2LO         1.9082149292705877000E-10
+#define M_LN2HI         6.9314718036912381649E-1
+#define M_SQRT3	1.73205080756887719000
+#define M_IVLN10        0.43429448190325182765 /* 1 / log(10) */
+#define M_LOG2_E        _M_LN2
+#define M_INVLN2        1.4426950408889633870E0  /* 1 / log(2) */
+
+/* Global control over fdlibm error handling.  */
+
+enum __fdlibm_version
+{
+  __fdlibm_ieee = -1,
+  __fdlibm_svid,
+  __fdlibm_xopen,
+  __fdlibm_posix
+};
+
+#define _LIB_VERSION_TYPE enum __fdlibm_version
+#define _LIB_VERSION __fdlib_version
+
+extern __IMPORT _LIB_VERSION_TYPE _LIB_VERSION;
+
+#define _IEEE_  __fdlibm_ieee
+#define _SVID_  __fdlibm_svid
+#define _XOPEN_ __fdlibm_xopen
+#define _POSIX_ __fdlibm_posix
+
+#endif /* ! defined (__STRICT_ANSI__) */
+
+_END_STD_C
+
+#ifdef __FAST_MATH__
+#include 
+#endif
+
+#endif /* _MATH_H_ */
diff --git a/tools/sdk/include/newlib/newlib.h b/tools/sdk/include/newlib/newlib.h
new file mode 100644
index 00000000..e9bf5664
--- /dev/null
+++ b/tools/sdk/include/newlib/newlib.h
@@ -0,0 +1,201 @@
+/* newlib.h.  Generated from newlib.hin by configure.  */
+/* newlib.hin.  Manually edited from the output of autoheader to
+   remove all PACKAGE_ macros which will collide with any user
+   package using newlib header files and having its own package name,
+   version, etc...  */
+#ifndef __NEWLIB_H__
+
+#define __NEWLIB_H__ 1
+
+/* EL/IX level */
+/* #undef _ELIX_LEVEL */
+
+/* Newlib version */
+#define _NEWLIB_VERSION "2.2.0"
+
+/* C99 formats support (such as %a, %zu, ...) in IO functions like
+ * printf/scanf enabled */
+/* #undef _WANT_IO_C99_FORMATS */
+
+/* long long type support in IO functions like printf/scanf enabled */
+/* #undef _WANT_IO_LONG_LONG */
+
+/* Register application finalization function using atexit. */
+/* #undef _WANT_REGISTER_FINI */
+
+/* long double type support in IO functions like printf/scanf enabled */
+/* #undef _WANT_IO_LONG_DOUBLE */
+
+/* Positional argument support in printf functions enabled.  */
+/* #undef _WANT_IO_POS_ARGS */
+
+/* Optional reentrant struct support.  Used mostly on platforms with
+   very restricted storage.  */
+#define _WANT_REENT_SMALL 1
+
+/* Multibyte supported */
+/* #undef _MB_CAPABLE */
+
+/* MB_LEN_MAX */
+#define _MB_LEN_MAX 1
+
+/* ICONV enabled */
+/* #undef _ICONV_ENABLED */
+
+/* Enable ICONV external CCS files loading capabilities */
+/* #undef _ICONV_ENABLE_EXTERNAL_CCS */
+
+/* Define if the linker supports .preinit_array/.init_array/.fini_array
+ * sections.  */
+#define HAVE_INITFINI_ARRAY 1
+
+/* True if atexit() may dynamically allocate space for cleanup
+   functions.  */
+#define _ATEXIT_DYNAMIC_ALLOC 1
+
+/* True if long double supported.  */
+#define _HAVE_LONG_DOUBLE 1
+
+/* Define if compiler supports -fno-tree-loop-distribute-patterns. */
+#define _HAVE_CC_INHIBIT_LOOP_TO_LIBCALL 1
+
+/* True if long double supported and it is equal to double.  */
+#define _LDBL_EQ_DBL 1
+ 
+/* Define if uintptr_t is unsigned long on this architecture */
+/* #undef _UINTPTR_EQ_ULONG */
+
+/* Define if uintptr_t is unsigned long long on this architecture */
+/* #undef _UINTPTR_EQ_ULONGLONG */
+
+/* Define if ivo supported in streamio.  */
+#define _FVWRITE_IN_STREAMIO 1
+
+/* Define if fseek functions support seek optimization.  */
+#define _FSEEK_OPTIMIZATION 1
+
+/* Define if wide char orientation is supported.  */
+#define _WIDE_ORIENT 1
+
+/* Define if unbuffered stream file optimization is supported.  */
+#define _UNBUF_STREAM_OPT 1
+
+/* Define if lite version of exit supported.  */
+/* #undef _LITE_EXIT */
+
+/* Define if declare atexit data as global.  */
+/* #undef _REENT_GLOBAL_ATEXIT */
+
+/* Define if small footprint nano-formatted-IO implementation used.  */
+#define _NANO_FORMATTED_IO 1
+
+/*
+ * Iconv encodings enabled ("to" direction)
+ */
+/* #undef _ICONV_TO_ENCODING_BIG5 */
+/* #undef _ICONV_TO_ENCODING_CP775 */
+/* #undef _ICONV_TO_ENCODING_CP850 */
+/* #undef _ICONV_TO_ENCODING_CP852 */
+/* #undef _ICONV_TO_ENCODING_CP855 */
+/* #undef _ICONV_TO_ENCODING_CP866 */
+/* #undef _ICONV_TO_ENCODING_EUC_JP */
+/* #undef _ICONV_TO_ENCODING_EUC_TW */
+/* #undef _ICONV_TO_ENCODING_EUC_KR */
+/* #undef _ICONV_TO_ENCODING_ISO_8859_1 */
+/* #undef _ICONV_TO_ENCODING_ISO_8859_10 */
+/* #undef _ICONV_TO_ENCODING_ISO_8859_11 */
+/* #undef _ICONV_TO_ENCODING_ISO_8859_13 */
+/* #undef _ICONV_TO_ENCODING_ISO_8859_14 */
+/* #undef _ICONV_TO_ENCODING_ISO_8859_15 */
+/* #undef _ICONV_TO_ENCODING_ISO_8859_2 */
+/* #undef _ICONV_TO_ENCODING_ISO_8859_3 */
+/* #undef _ICONV_TO_ENCODING_ISO_8859_4 */
+/* #undef _ICONV_TO_ENCODING_ISO_8859_5 */
+/* #undef _ICONV_TO_ENCODING_ISO_8859_6 */
+/* #undef _ICONV_TO_ENCODING_ISO_8859_7 */
+/* #undef _ICONV_TO_ENCODING_ISO_8859_8 */
+/* #undef _ICONV_TO_ENCODING_ISO_8859_9 */
+/* #undef _ICONV_TO_ENCODING_ISO_IR_111 */
+/* #undef _ICONV_TO_ENCODING_KOI8_R */
+/* #undef _ICONV_TO_ENCODING_KOI8_RU */
+/* #undef _ICONV_TO_ENCODING_KOI8_U */
+/* #undef _ICONV_TO_ENCODING_KOI8_UNI */
+/* #undef _ICONV_TO_ENCODING_UCS_2 */
+/* #undef _ICONV_TO_ENCODING_UCS_2_INTERNAL */
+/* #undef _ICONV_TO_ENCODING_UCS_2BE */
+/* #undef _ICONV_TO_ENCODING_UCS_2LE */
+/* #undef _ICONV_TO_ENCODING_UCS_4 */
+/* #undef _ICONV_TO_ENCODING_UCS_4_INTERNAL */
+/* #undef _ICONV_TO_ENCODING_UCS_4BE */
+/* #undef _ICONV_TO_ENCODING_UCS_4LE */
+/* #undef _ICONV_TO_ENCODING_US_ASCII */
+/* #undef _ICONV_TO_ENCODING_UTF_16 */
+/* #undef _ICONV_TO_ENCODING_UTF_16BE */
+/* #undef _ICONV_TO_ENCODING_UTF_16LE */
+/* #undef _ICONV_TO_ENCODING_UTF_8 */
+/* #undef _ICONV_TO_ENCODING_WIN_1250 */
+/* #undef _ICONV_TO_ENCODING_WIN_1251 */
+/* #undef _ICONV_TO_ENCODING_WIN_1252 */
+/* #undef _ICONV_TO_ENCODING_WIN_1253 */
+/* #undef _ICONV_TO_ENCODING_WIN_1254 */
+/* #undef _ICONV_TO_ENCODING_WIN_1255 */
+/* #undef _ICONV_TO_ENCODING_WIN_1256 */
+/* #undef _ICONV_TO_ENCODING_WIN_1257 */
+/* #undef _ICONV_TO_ENCODING_WIN_1258 */
+
+/*
+ * Iconv encodings enabled ("from" direction)
+ */
+/* #undef _ICONV_FROM_ENCODING_BIG5 */
+/* #undef _ICONV_FROM_ENCODING_CP775 */
+/* #undef _ICONV_FROM_ENCODING_CP850 */
+/* #undef _ICONV_FROM_ENCODING_CP852 */
+/* #undef _ICONV_FROM_ENCODING_CP855 */
+/* #undef _ICONV_FROM_ENCODING_CP866 */
+/* #undef _ICONV_FROM_ENCODING_EUC_JP */
+/* #undef _ICONV_FROM_ENCODING_EUC_TW */
+/* #undef _ICONV_FROM_ENCODING_EUC_KR */
+/* #undef _ICONV_FROM_ENCODING_ISO_8859_1 */
+/* #undef _ICONV_FROM_ENCODING_ISO_8859_10 */
+/* #undef _ICONV_FROM_ENCODING_ISO_8859_11 */
+/* #undef _ICONV_FROM_ENCODING_ISO_8859_13 */
+/* #undef _ICONV_FROM_ENCODING_ISO_8859_14 */
+/* #undef _ICONV_FROM_ENCODING_ISO_8859_15 */
+/* #undef _ICONV_FROM_ENCODING_ISO_8859_2 */
+/* #undef _ICONV_FROM_ENCODING_ISO_8859_3 */
+/* #undef _ICONV_FROM_ENCODING_ISO_8859_4 */
+/* #undef _ICONV_FROM_ENCODING_ISO_8859_5 */
+/* #undef _ICONV_FROM_ENCODING_ISO_8859_6 */
+/* #undef _ICONV_FROM_ENCODING_ISO_8859_7 */
+/* #undef _ICONV_FROM_ENCODING_ISO_8859_8 */
+/* #undef _ICONV_FROM_ENCODING_ISO_8859_9 */
+/* #undef _ICONV_FROM_ENCODING_ISO_IR_111 */
+/* #undef _ICONV_FROM_ENCODING_KOI8_R */
+/* #undef _ICONV_FROM_ENCODING_KOI8_RU */
+/* #undef _ICONV_FROM_ENCODING_KOI8_U */
+/* #undef _ICONV_FROM_ENCODING_KOI8_UNI */
+/* #undef _ICONV_FROM_ENCODING_UCS_2 */
+/* #undef _ICONV_FROM_ENCODING_UCS_2_INTERNAL */
+/* #undef _ICONV_FROM_ENCODING_UCS_2BE */
+/* #undef _ICONV_FROM_ENCODING_UCS_2LE */
+/* #undef _ICONV_FROM_ENCODING_UCS_4 */
+/* #undef _ICONV_FROM_ENCODING_UCS_4_INTERNAL */
+/* #undef _ICONV_FROM_ENCODING_UCS_4BE */
+/* #undef _ICONV_FROM_ENCODING_UCS_4LE */
+/* #undef _ICONV_FROM_ENCODING_US_ASCII */
+/* #undef _ICONV_FROM_ENCODING_UTF_16 */
+/* #undef _ICONV_FROM_ENCODING_UTF_16BE */
+/* #undef _ICONV_FROM_ENCODING_UTF_16LE */
+/* #undef _ICONV_FROM_ENCODING_UTF_8 */
+/* #undef _ICONV_FROM_ENCODING_WIN_1250 */
+/* #undef _ICONV_FROM_ENCODING_WIN_1251 */
+/* #undef _ICONV_FROM_ENCODING_WIN_1252 */
+/* #undef _ICONV_FROM_ENCODING_WIN_1253 */
+/* #undef _ICONV_FROM_ENCODING_WIN_1254 */
+/* #undef _ICONV_FROM_ENCODING_WIN_1255 */
+/* #undef _ICONV_FROM_ENCODING_WIN_1256 */
+/* #undef _ICONV_FROM_ENCODING_WIN_1257 */
+/* #undef _ICONV_FROM_ENCODING_WIN_1258 */
+
+#endif /* !__NEWLIB_H__ */
+
diff --git a/tools/sdk/include/newlib/paths.h b/tools/sdk/include/newlib/paths.h
new file mode 100644
index 00000000..b1c70f58
--- /dev/null
+++ b/tools/sdk/include/newlib/paths.h
@@ -0,0 +1,9 @@
+#ifndef	_PATHS_H_
+#define _PATHS_H_
+
+#define _PATH_DEV	"/dev/"
+#define _PATH_DEVNULL   "/dev/null"
+#define _PATH_DEVZERO   "/dev/zero"
+#define _PATH_BSHELL    "/bin/sh"
+
+#endif /* _PATHS_H_ */
diff --git a/tools/sdk/include/newlib/pthread.h b/tools/sdk/include/newlib/pthread.h
new file mode 100644
index 00000000..db1f9c1c
--- /dev/null
+++ b/tools/sdk/include/newlib/pthread.h
@@ -0,0 +1,431 @@
+/*  pthread.h
+ *
+ *  Written by Joel Sherrill .
+ *
+ *  COPYRIGHT (c) 1989-2013.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  Permission to use, copy, modify, and distribute this software for any
+ *  purpose without fee is hereby granted, provided that this entire notice
+ *  is included in all copies of any software which is or includes a copy
+ *  or modification of this software.
+ *
+ *  THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY.  IN PARTICULAR,  THE AUTHOR MAKES NO REPRESENTATION
+ *  OR WARRANTY OF ANY KIND CONCERNING THE MERCHANTABILITY OF THIS
+ *  SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR PURPOSE.
+ *
+ *  $Id$
+ */
+
+#ifndef __PTHREAD_h
+#define __PTHREAD_h
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include 
+
+#if defined(_POSIX_THREADS)
+
+#include 
+#include 
+#include 
+#include 
+
+struct _pthread_cleanup_context {
+  void (*_routine)(void *);
+  void *_arg;
+  int _canceltype;
+  struct _pthread_cleanup_context *_previous;
+};
+
+/* Register Fork Handlers */
+int	_EXFUN(pthread_atfork,(void (*prepare)(void), void (*parent)(void),
+                   void (*child)(void)));
+          
+/* Mutex Initialization Attributes, P1003.1c/Draft 10, p. 81 */
+
+int	_EXFUN(pthread_mutexattr_init, (pthread_mutexattr_t *__attr));
+int	_EXFUN(pthread_mutexattr_destroy, (pthread_mutexattr_t *__attr));
+int	_EXFUN(pthread_mutexattr_getpshared,
+		(_CONST pthread_mutexattr_t *__attr, int  *__pshared));
+int	_EXFUN(pthread_mutexattr_setpshared,
+		(pthread_mutexattr_t *__attr, int __pshared));
+
+#if defined(_UNIX98_THREAD_MUTEX_ATTRIBUTES)
+
+/* Single UNIX Specification 2 Mutex Attributes types */
+
+int _EXFUN(pthread_mutexattr_gettype,
+		(_CONST pthread_mutexattr_t *__attr, int *__kind));
+int _EXFUN(pthread_mutexattr_settype,
+		(pthread_mutexattr_t *__attr, int __kind));
+
+#endif
+
+/* Initializing and Destroying a Mutex, P1003.1c/Draft 10, p. 87 */
+
+int	_EXFUN(pthread_mutex_init,
+	(pthread_mutex_t *__mutex, _CONST pthread_mutexattr_t *__attr));
+int	_EXFUN(pthread_mutex_destroy, (pthread_mutex_t *__mutex));
+
+/* This is used to statically initialize a pthread_mutex_t. Example:
+  
+    pthread_mutex_t mutex = PTHREAD_MUTEX_INITIALIZER;
+ */
+
+#define PTHREAD_MUTEX_INITIALIZER  ((pthread_mutex_t) 0xFFFFFFFF)
+
+/*  Locking and Unlocking a Mutex, P1003.1c/Draft 10, p. 93
+    NOTE: P1003.4b/D8 adds pthread_mutex_timedlock(), p. 29 */
+
+int	_EXFUN(pthread_mutex_lock, (pthread_mutex_t *__mutex));
+int	_EXFUN(pthread_mutex_trylock, (pthread_mutex_t *__mutex));
+int	_EXFUN(pthread_mutex_unlock, (pthread_mutex_t *__mutex));
+
+#if defined(_POSIX_TIMEOUTS)
+
+int	_EXFUN(pthread_mutex_timedlock,
+	(pthread_mutex_t *__mutex, _CONST struct timespec *__timeout));
+
+#endif /* _POSIX_TIMEOUTS */
+
+/* Condition Variable Initialization Attributes, P1003.1c/Draft 10, p. 96 */
+ 
+int	_EXFUN(pthread_condattr_init, (pthread_condattr_t *__attr));
+int	_EXFUN(pthread_condattr_destroy, (pthread_condattr_t *__attr));
+int	_EXFUN(pthread_condattr_getpshared,
+		(_CONST pthread_condattr_t *__attr, int *__pshared));
+int	_EXFUN(pthread_condattr_setpshared,
+		(pthread_condattr_t *__attr, int __pshared));
+ 
+/* Initializing and Destroying a Condition Variable, P1003.1c/Draft 10, p. 87 */
+ 
+int	_EXFUN(pthread_cond_init,
+	(pthread_cond_t *__cond, _CONST pthread_condattr_t *__attr));
+int	_EXFUN(pthread_cond_destroy, (pthread_cond_t *__mutex));
+ 
+/* This is used to statically initialize a pthread_cond_t. Example:
+  
+    pthread_cond_t cond = PTHREAD_COND_INITIALIZER;
+ */
+ 
+#define PTHREAD_COND_INITIALIZER  ((pthread_cond_t) 0xFFFFFFFF)
+ 
+/* Broadcasting and Signaling a Condition, P1003.1c/Draft 10, p. 101 */
+ 
+int	_EXFUN(pthread_cond_signal, (pthread_cond_t *__cond));
+int	_EXFUN(pthread_cond_broadcast, (pthread_cond_t *__cond));
+ 
+/* Waiting on a Condition, P1003.1c/Draft 10, p. 105 */
+ 
+int	_EXFUN(pthread_cond_wait,
+	(pthread_cond_t *__cond, pthread_mutex_t *__mutex));
+ 
+int	_EXFUN(pthread_cond_timedwait,
+		(pthread_cond_t *__cond, pthread_mutex_t *__mutex,
+		_CONST struct timespec *__abstime));
+ 
+#if defined(_POSIX_THREAD_PRIORITY_SCHEDULING)
+
+/* Thread Creation Scheduling Attributes, P1003.1c/Draft 10, p. 120 */
+
+int	_EXFUN(pthread_attr_setscope,
+		(pthread_attr_t *__attr, int __contentionscope));
+int	_EXFUN(pthread_attr_getscope,
+	(_CONST pthread_attr_t *__attr, int *__contentionscope));
+int	_EXFUN(pthread_attr_setinheritsched,
+	(pthread_attr_t *__attr, int __inheritsched));
+int	_EXFUN(pthread_attr_getinheritsched,
+	(_CONST pthread_attr_t *__attr, int *__inheritsched));
+int	_EXFUN(pthread_attr_setschedpolicy,
+	(pthread_attr_t *__attr, int __policy));
+int	_EXFUN(pthread_attr_getschedpolicy,
+	(_CONST pthread_attr_t *__attr, int *__policy));
+
+#endif /* defined(_POSIX_THREAD_PRIORITY_SCHEDULING) */
+
+int	_EXFUN(pthread_attr_setschedparam,
+	(pthread_attr_t *__attr, _CONST struct sched_param *__param));
+int	_EXFUN(pthread_attr_getschedparam,
+	(_CONST pthread_attr_t *__attr, struct sched_param *__param));
+
+#if defined(_POSIX_THREAD_PRIORITY_SCHEDULING)
+
+/* Dynamic Thread Scheduling Parameters Access, P1003.1c/Draft 10, p. 124 */
+
+int	_EXFUN(pthread_getschedparam,
+	(pthread_t __pthread, int *__policy, struct sched_param *__param));
+int	_EXFUN(pthread_setschedparam,
+	(pthread_t __pthread, int __policy, struct sched_param *__param));
+
+#endif /* defined(_POSIX_THREAD_PRIORITY_SCHEDULING) */
+
+#if defined(_POSIX_THREAD_PRIO_INHERIT) || defined(_POSIX_THREAD_PRIO_PROTECT)
+
+/* Mutex Initialization Scheduling Attributes, P1003.1c/Draft 10, p. 128 */
+ 
+int	_EXFUN(pthread_mutexattr_setprotocol,
+	(pthread_mutexattr_t *__attr, int __protocol));
+int	_EXFUN(pthread_mutexattr_getprotocol,
+	(_CONST pthread_mutexattr_t *__attr, int *__protocol));
+int	_EXFUN(pthread_mutexattr_setprioceiling,
+	(pthread_mutexattr_t *__attr, int __prioceiling));
+int	_EXFUN(pthread_mutexattr_getprioceiling,
+	(_CONST pthread_mutexattr_t *__attr, int *__prioceiling));
+
+#endif /* _POSIX_THREAD_PRIO_INHERIT || _POSIX_THREAD_PRIO_PROTECT */
+
+#if defined(_POSIX_THREAD_PRIO_PROTECT)
+
+/* Change the Priority Ceiling of a Mutex, P1003.1c/Draft 10, p. 131 */
+
+int	_EXFUN(pthread_mutex_setprioceiling,
+	(pthread_mutex_t *__mutex, int __prioceiling, int *__old_ceiling));
+int	_EXFUN(pthread_mutex_getprioceiling,
+	(pthread_mutex_t *__mutex, int *__prioceiling));
+
+#endif /* _POSIX_THREAD_PRIO_PROTECT */
+
+/* Thread Creation Attributes, P1003.1c/Draft 10, p, 140 */
+
+int	_EXFUN(pthread_attr_init, (pthread_attr_t *__attr));
+int	_EXFUN(pthread_attr_destroy, (pthread_attr_t *__attr));
+int	_EXFUN(pthread_attr_setstack, (pthread_attr_t *attr,
+	void *__stackaddr, size_t __stacksize));
+int	_EXFUN(pthread_attr_getstack, (_CONST pthread_attr_t *attr,
+	void **__stackaddr, size_t *__stacksize));
+int	_EXFUN(pthread_attr_getstacksize,
+	(_CONST pthread_attr_t *__attr, size_t *__stacksize));
+int	_EXFUN(pthread_attr_setstacksize,
+	(pthread_attr_t *__attr, size_t __stacksize));
+int	_EXFUN(pthread_attr_getstackaddr,
+	(_CONST pthread_attr_t *__attr, void **__stackaddr));
+int	_EXFUN(pthread_attr_setstackaddr,
+	(pthread_attr_t  *__attr, void *__stackaddr));
+int	_EXFUN(pthread_attr_getdetachstate,
+	(_CONST pthread_attr_t *__attr, int *__detachstate));
+int	_EXFUN(pthread_attr_setdetachstate,
+	(pthread_attr_t *__attr, int __detachstate));
+int	_EXFUN(pthread_attr_getguardsize,
+	(_CONST pthread_attr_t *__attr, size_t *__guardsize));
+int	_EXFUN(pthread_attr_setguardsize,
+	(pthread_attr_t *__attr, size_t __guardsize));
+
+/* POSIX thread APIs beyond the POSIX standard but provided 
+ * in GNU/Linux. They may be provided by other OSes for
+ * compatibility.
+ */
+#if defined(__GNU_VISIBLE)
+#if defined(__rtems__) 
+int	_EXFUN(pthread_attr_setaffinity_np,
+	(pthread_attr_t *__attr, size_t __cpusetsize, 
+	const cpu_set_t *__cpuset));
+int 	_EXFUN(pthread_attr_getaffinity_np,
+	(const pthread_attr_t *__attr, size_t __cpusetsize,
+	cpu_set_t *__cpuset));
+
+int	_EXFUN(pthread_setaffinity_np,
+	(pthread_t __id, size_t __cpusetsize, const cpu_set_t *__cpuset));
+int	_EXFUN(pthread_getaffinity_np,
+	(const pthread_t __id, size_t __cpusetsize, cpu_set_t *__cpuset));
+
+int	_EXFUN(pthread_getattr_np,
+	(pthread_t __id, pthread_attr_t *__attr));
+#endif /* defined(__rtems__) */
+#endif /* defined(__GNU_VISIBLE) */
+
+/* Thread Creation, P1003.1c/Draft 10, p. 144 */
+
+int	_EXFUN(pthread_create,
+	(pthread_t *__pthread, _CONST pthread_attr_t  *__attr,
+	void *(*__start_routine)( void * ), void *__arg));
+
+/* Wait for Thread Termination, P1003.1c/Draft 10, p. 147 */
+
+int	_EXFUN(pthread_join, (pthread_t __pthread, void **__value_ptr));
+
+/* Detaching a Thread, P1003.1c/Draft 10, p. 149 */
+
+int	_EXFUN(pthread_detach, (pthread_t __pthread));
+
+/* Thread Termination, p1003.1c/Draft 10, p. 150 */
+
+void	_EXFUN(pthread_exit, (void *__value_ptr));
+
+/* Get Calling Thread's ID, p1003.1c/Draft 10, p. XXX */
+
+pthread_t	_EXFUN(pthread_self, (void));
+
+/* Compare Thread IDs, p1003.1c/Draft 10, p. 153 */
+
+int	_EXFUN(pthread_equal, (pthread_t __t1, pthread_t __t2));
+
+/* Dynamic Package Initialization */
+
+/* This is used to statically initialize a pthread_once_t. Example:
+  
+    pthread_once_t once = PTHREAD_ONCE_INIT;
+  
+    NOTE:  This is named inconsistently -- it should be INITIALIZER.  */
+ 
+#define PTHREAD_ONCE_INIT  { 1, 0 }  /* is initialized and not run */
+ 
+int	_EXFUN(pthread_once,
+	(pthread_once_t *__once_control, void (*__init_routine)(void)));
+
+/* Thread-Specific Data Key Create, P1003.1c/Draft 10, p. 163 */
+
+int	_EXFUN(pthread_key_create,
+	(pthread_key_t *__key, void (*__destructor)( void * )));
+
+/* Thread-Specific Data Management, P1003.1c/Draft 10, p. 165 */
+
+int	_EXFUN(pthread_setspecific,
+	(pthread_key_t __key, _CONST void *__value));
+void *	_EXFUN(pthread_getspecific, (pthread_key_t __key));
+
+/* Thread-Specific Data Key Deletion, P1003.1c/Draft 10, p. 167 */
+
+int	_EXFUN(pthread_key_delete, (pthread_key_t __key));
+
+/* Execution of a Thread, P1003.1c/Draft 10, p. 181 */
+
+#define PTHREAD_CANCEL_ENABLE  0
+#define PTHREAD_CANCEL_DISABLE 1
+
+#define PTHREAD_CANCEL_DEFERRED 0
+#define PTHREAD_CANCEL_ASYNCHRONOUS 1
+
+#define PTHREAD_CANCELED ((void *) -1)
+
+int	_EXFUN(pthread_cancel, (pthread_t __pthread));
+
+/* Setting Cancelability State, P1003.1c/Draft 10, p. 183 */
+
+int	_EXFUN(pthread_setcancelstate, (int __state, int *__oldstate));
+int	_EXFUN(pthread_setcanceltype, (int __type, int *__oldtype));
+void 	_EXFUN(pthread_testcancel, (void));
+
+/* Establishing Cancellation Handlers, P1003.1c/Draft 10, p. 184 */
+
+void	_EXFUN(_pthread_cleanup_push,
+	(struct _pthread_cleanup_context *_context,
+	void (*_routine)(void *), void *_arg));
+
+void	_EXFUN(_pthread_cleanup_pop,
+	(struct _pthread_cleanup_context *_context,
+	int _execute));
+
+/* It is intentional to open and close the scope in two different macros */
+#define pthread_cleanup_push(_routine, _arg) \
+  do { \
+    struct _pthread_cleanup_context _pthread_clup_ctx; \
+    _pthread_cleanup_push(&_pthread_clup_ctx, (_routine), (_arg))
+
+#define pthread_cleanup_pop(_execute) \
+    _pthread_cleanup_pop(&_pthread_clup_ctx, (_execute)); \
+  } while (0)
+
+#if defined(_GNU_SOURCE)
+void	_EXFUN(_pthread_cleanup_push_defer,
+	(struct _pthread_cleanup_context *_context,
+	void (*_routine)(void *), void *_arg));
+
+void	_EXFUN(_pthread_cleanup_pop_restore,
+	(struct _pthread_cleanup_context *_context,
+	int _execute));
+
+/* It is intentional to open and close the scope in two different macros */
+#define pthread_cleanup_push_defer_np(_routine, _arg) \
+  do { \
+    struct _pthread_cleanup_context _pthread_clup_ctx; \
+    _pthread_cleanup_push_defer(&_pthread_clup_ctx, (_routine), (_arg))
+
+#define pthread_cleanup_pop_restore_np(_execute) \
+    _pthread_cleanup_pop_restore(&_pthread_clup_ctx, (_execute)); \
+  } while (0)
+#endif /* defined(_GNU_SOURCE) */
+
+#if defined(_POSIX_THREAD_CPUTIME)
+ 
+/* Accessing a Thread CPU-time Clock, P1003.4b/D8, p. 58 */
+ 
+int	_EXFUN(pthread_getcpuclockid,
+	(pthread_t __pthread_id, clockid_t *__clock_id));
+ 
+#endif /* defined(_POSIX_THREAD_CPUTIME) */
+
+
+#endif /* defined(_POSIX_THREADS) */
+
+#if defined(_POSIX_BARRIERS)
+
+int	_EXFUN(pthread_barrierattr_init, (pthread_barrierattr_t *__attr));
+int	_EXFUN(pthread_barrierattr_destroy, (pthread_barrierattr_t *__attr));
+int	_EXFUN(pthread_barrierattr_getpshared,
+	(_CONST pthread_barrierattr_t *__attr, int *__pshared));
+int	_EXFUN(pthread_barrierattr_setpshared,
+	(pthread_barrierattr_t *__attr, int __pshared));
+
+#define PTHREAD_BARRIER_SERIAL_THREAD -1
+
+int	_EXFUN(pthread_barrier_init,
+	(pthread_barrier_t *__barrier,
+	_CONST pthread_barrierattr_t *__attr, unsigned __count));
+int	_EXFUN(pthread_barrier_destroy, (pthread_barrier_t *__barrier));
+int	_EXFUN(pthread_barrier_wait,(pthread_barrier_t *__barrier));
+
+#endif /* defined(_POSIX_BARRIERS) */
+
+#if defined(_POSIX_SPIN_LOCKS)
+
+int	_EXFUN(pthread_spin_init,
+	(pthread_spinlock_t *__spinlock, int __pshared));
+int	_EXFUN(pthread_spin_destroy, (pthread_spinlock_t *__spinlock));
+int	_EXFUN(pthread_spin_lock, (pthread_spinlock_t *__spinlock));
+int	_EXFUN(pthread_spin_trylock, (pthread_spinlock_t *__spinlock));
+int	_EXFUN(pthread_spin_unlock, (pthread_spinlock_t *__spinlock));
+
+#endif /* defined(_POSIX_SPIN_LOCKS) */
+
+#if defined(_POSIX_READER_WRITER_LOCKS)
+
+/* This is used to statically initialize a pthread_rwlock_t. Example:
+  
+    pthread_mutex_t mutex = PTHREAD_RWLOCK_INITIALIZER;
+ */
+
+#define PTHREAD_RWLOCK_INITIALIZER  ((pthread_rwlock_t) 0xFFFFFFFF)
+
+int	_EXFUN(pthread_rwlockattr_init, (pthread_rwlockattr_t *__attr));
+int	_EXFUN(pthread_rwlockattr_destroy, (pthread_rwlockattr_t *__attr));
+int	_EXFUN(pthread_rwlockattr_getpshared,
+	(_CONST pthread_rwlockattr_t *__attr, int *__pshared));
+int	_EXFUN(pthread_rwlockattr_setpshared,
+	(pthread_rwlockattr_t *__attr, int __pshared));
+
+int	_EXFUN(pthread_rwlock_init,
+	(pthread_rwlock_t *__rwlock, _CONST pthread_rwlockattr_t *__attr));
+int	_EXFUN(pthread_rwlock_destroy, (pthread_rwlock_t *__rwlock));
+int	_EXFUN(pthread_rwlock_rdlock,(pthread_rwlock_t *__rwlock));
+int	_EXFUN(pthread_rwlock_tryrdlock,(pthread_rwlock_t *__rwlock));
+int	_EXFUN(pthread_rwlock_timedrdlock,
+        (pthread_rwlock_t *__rwlock, _CONST struct timespec *__abstime));
+int	_EXFUN(pthread_rwlock_unlock,(pthread_rwlock_t *__rwlock));
+int	_EXFUN(pthread_rwlock_wrlock,(pthread_rwlock_t *__rwlock));
+int	_EXFUN(pthread_rwlock_trywrlock,(pthread_rwlock_t *__rwlock));
+int	_EXFUN(pthread_rwlock_timedwrlock,
+        (pthread_rwlock_t *__rwlock, _CONST struct timespec *__abstime));
+
+#endif /* defined(_POSIX_READER_WRITER_LOCKS) */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/* end of include file */
diff --git a/tools/sdk/include/newlib/pwd.h b/tools/sdk/include/newlib/pwd.h
new file mode 100644
index 00000000..3dea4ee2
--- /dev/null
+++ b/tools/sdk/include/newlib/pwd.h
@@ -0,0 +1,87 @@
+/*-
+ * Copyright (c) 1989 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the University of
+ *	California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)pwd.h	5.13 (Berkeley) 5/28/91
+ */
+
+#ifndef _PWD_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+#define	_PWD_H_
+
+#include 
+#include 
+
+#if __BSD_VISIBLE
+#define	_PATH_PASSWD		"/etc/passwd"
+
+#define	_PASSWORD_LEN		128	/* max length, not counting NULL */
+#endif
+
+struct passwd {
+	char	*pw_name;		/* user name */
+	char	*pw_passwd;		/* encrypted password */
+	uid_t	pw_uid;			/* user uid */
+	gid_t	pw_gid;			/* user gid */
+	char	*pw_comment;		/* comment */
+	char	*pw_gecos;		/* Honeywell login info */
+	char	*pw_dir;		/* home directory */
+	char	*pw_shell;		/* default shell */
+};
+
+#ifndef __INSIDE_CYGWIN__
+struct passwd	*getpwuid (uid_t);
+struct passwd	*getpwnam (const char *);
+
+#if __POSIX_VISIBLE >= 200112 || __XSI_VISIBLE >= 500
+int 		 getpwnam_r (const char *, struct passwd *,
+			char *, size_t , struct passwd **);
+int		 getpwuid_r (uid_t, struct passwd *, char *,
+			size_t, struct passwd **);
+#endif
+
+#if __XSI_VISIBLE >= 500
+struct passwd	*getpwent (void);
+void		 setpwent (void);
+void		 endpwent (void);
+#endif
+
+#if __BSD_VISIBLE
+int		 setpassent (int);
+#endif
+#endif /*!__INSIDE_CYGWIN__*/
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _PWD_H_ */
diff --git a/tools/sdk/include/newlib/reent.h b/tools/sdk/include/newlib/reent.h
new file mode 100644
index 00000000..861be71d
--- /dev/null
+++ b/tools/sdk/include/newlib/reent.h
@@ -0,0 +1,189 @@
+/* This header file provides the reentrancy.  */
+
+/* The reentrant system calls here serve two purposes:
+
+   1) Provide reentrant versions of the system calls the ANSI C library
+      requires.
+   2) Provide these system calls in a namespace clean way.
+
+   It is intended that *all* system calls that the ANSI C library needs
+   be declared here.  It documents them all in one place.  All library access
+   to the system is via some form of these functions.
+
+   The target may provide the needed syscalls by any of the following:
+
+   1) Define the reentrant versions of the syscalls directly.
+      (eg: _open_r, _close_r, etc.).  Please keep the namespace clean.
+      When you do this, set "syscall_dir" to "syscalls" and add
+      -DREENTRANT_SYSCALLS_PROVIDED to newlib_cflags in configure.host.
+
+   2) Define namespace clean versions of the system calls by prefixing
+      them with '_' (eg: _open, _close, etc.).  Technically, there won't be
+      true reentrancy at the syscall level, but the library will be namespace
+      clean.
+      When you do this, set "syscall_dir" to "syscalls" in configure.host.
+
+   3) Define or otherwise provide the regular versions of the syscalls
+      (eg: open, close, etc.).  The library won't be reentrant nor namespace
+      clean, but at least it will work.
+      When you do this, add -DMISSING_SYSCALL_NAMES to newlib_cflags in
+      configure.host.
+
+   4) Define or otherwise provide the regular versions of the syscalls,
+      and do not supply functional interfaces for any of the reentrant
+      calls. With this method, the reentrant syscalls are redefined to
+      directly call the regular system call without the reentrancy argument.
+      When you do this, specify both -DREENTRANT_SYSCALLS_PROVIDED and 
+      -DMISSING_SYSCALL_NAMES via newlib_cflags in configure.host and do
+      not specify "syscall_dir".
+
+   Stubs of the reentrant versions of the syscalls exist in the libc/reent
+   source directory and are provided if REENTRANT_SYSCALLS_PROVIDED isn't 
+   defined.  These stubs call the native system calls: _open, _close, etc. 
+   if MISSING_SYSCALL_NAMES is *not* defined, otherwise they call the
+   non-underscored versions: open, close, etc. when MISSING_SYSCALL_NAMES
+   *is* defined.
+
+   By default, newlib functions call the reentrant syscalls internally,
+   passing a reentrancy structure as an argument.  This reentrancy structure
+   contains data that is thread-specific.  For example, the errno value is
+   kept in the reentrancy structure.  If multiple threads exist, each will
+   keep a separate errno value which is intuitive since the application flow
+   cannot check for failure reliably otherwise.
+
+   The reentrant syscalls are either provided by the platform, by the 
+   libc/reent stubs, or in the case of both MISSING_SYSCALL_NAMES and 
+   REENTRANT_SYSCALLS_PROVIDED being defined, the calls are redefined to
+   simply call the regular syscalls with no reentrancy struct argument.
+
+   A single-threaded application does not need to worry about the reentrancy
+   structure.  It is used internally.  
+
+   A multi-threaded application needs either to manually manage reentrancy 
+   structures or use dynamic reentrancy.
+   
+   Manually managing reentrancy structures entails calling special reentrant
+   versions of newlib functions that have an additional reentrancy argument.
+   For example, _printf_r.  By convention, the first argument is the
+   reentrancy structure.  By default, the normal version of the function
+   uses the default reentrancy structure: _REENT.  The reentrancy structure
+   is passed internally, eventually to the reentrant syscalls themselves.
+   How the structures are stored and accessed in this model is up to the
+   application.
+
+   Dynamic reentrancy is specified by the __DYNAMIC_REENT__ flag.  This
+   flag denotes setting up a macro to replace _REENT with a function call
+   to __getreent().  This function needs to be implemented by the platform
+   and it is meant to return the reentrancy structure for the current
+   thread.  When the regular C functions (e.g. printf) go to call internal
+   routines with the default _REENT structure, they end up calling with 
+   the reentrancy structure for the thread.  Thus, application code does not
+   need to call the _r routines nor worry about reentrancy structures.  */
+
+/* WARNING: All identifiers here must begin with an underscore.  This file is
+   included by stdio.h and others and we therefore must only use identifiers
+   in the namespace allotted to us.  */
+
+#ifndef _REENT_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+#define _REENT_H_
+
+#include 
+#include 
+#include 
+
+#define __need_size_t
+#define __need_ptrdiff_t
+#include 
+
+/* FIXME: not namespace clean */
+struct stat;
+struct tms;
+struct timeval;
+struct timezone;
+
+#if defined(REENTRANT_SYSCALLS_PROVIDED) && defined(MISSING_SYSCALL_NAMES)
+
+#define _close_r(__reent, __fd)                   close(__fd)
+#define _execve_r(__reent, __f, __arg, __env)     execve(__f, __arg, __env)
+#define _fcntl_r(__reent, __fd, __cmd, __arg)     fcntl(__fd, __cmd, __arg)
+#define _fork_r(__reent)                          fork()
+#define _fstat_r(__reent, __fdes, __stat)         fstat(__fdes, __stat)
+#define _getpid_r(__reent)                        getpid()
+#define _isatty_r(__reent, __desc)                isatty(__desc)
+#define _kill_r(__reent, __pid, __signal)         kill(__pid, __signal)
+#define _link_r(__reent, __oldpath, __newpath)    link(__oldpath, __newpath)
+#define _lseek_r(__reent, __fdes, __off, __w)     lseek(__fdes, __off, __w)
+#define _mkdir_r(__reent, __path, __m)		  mkdir(__path, __m)
+#define _open_r(__reent, __path, __flag, __m)     open(__path, __flag, __m)
+#define _read_r(__reent, __fd, __buff, __cnt)     read(__fd, __buff, __cnt)
+#define _rename_r(__reent, __old, __new)	  rename(__old, __new)
+#define _sbrk_r(__reent, __incr)                  sbrk(__incr)
+#define _stat_r(__reent, __path, __buff)          stat(__path, __buff)
+#define _times_r(__reent, __time)                 times(__time)
+#define _unlink_r(__reent, __path)                unlink(__path)
+#define _wait_r(__reent, __status)                wait(__status)
+#define _write_r(__reent, __fd, __buff, __cnt)    write(__fd, __buff, __cnt)
+#define _gettimeofday_r(__reent, __tp, __tzp)     gettimeofday(__tp, __tzp)
+
+#ifdef __LARGE64_FILES
+#define _lseek64_r(__reent, __fd, __off, __w)     lseek64(__fd, __off, __w)
+#define _fstat64_r(__reent, __fd, __buff)         fstat64(__fd, __buff)
+#define _open64_r(__reent, __path, __flag, __m)   open64(__path, __flag, __m)
+#endif
+
+#else
+/* Reentrant versions of system calls.  */
+
+extern int _close_r _PARAMS ((struct _reent *, int));
+extern int _execve_r _PARAMS ((struct _reent *, const char *, char *const *, char *const *));
+extern int _fcntl_r _PARAMS ((struct _reent *, int, int, int));
+extern int _fork_r _PARAMS ((struct _reent *));
+extern int _fstat_r _PARAMS ((struct _reent *, int, struct stat *));
+extern int _getpid_r _PARAMS ((struct _reent *));
+extern int _isatty_r _PARAMS ((struct _reent *, int));
+extern int _kill_r _PARAMS ((struct _reent *, int, int));
+extern int _link_r _PARAMS ((struct _reent *, const char *, const char *));
+extern _off_t _lseek_r _PARAMS ((struct _reent *, int, _off_t, int));
+extern int _mkdir_r _PARAMS ((struct _reent *, const char *, int));
+extern int _open_r _PARAMS ((struct _reent *, const char *, int, int));
+extern _ssize_t _read_r _PARAMS ((struct _reent *, int, void *, size_t));
+extern int _rename_r _PARAMS ((struct _reent *, const char *, const char *));
+extern void *_sbrk_r _PARAMS ((struct _reent *, ptrdiff_t));
+extern int _stat_r _PARAMS ((struct _reent *, const char *, struct stat *));
+extern _CLOCK_T_ _times_r _PARAMS ((struct _reent *, struct tms *));
+extern int _unlink_r _PARAMS ((struct _reent *, const char *));
+extern int _wait_r _PARAMS ((struct _reent *, int *));
+extern _ssize_t _write_r _PARAMS ((struct _reent *, int, const void *, size_t));
+
+/* This one is not guaranteed to be available on all targets.  */
+extern int _gettimeofday_r _PARAMS ((struct _reent *, struct timeval *__tp, void *__tzp));
+
+#ifdef __LARGE64_FILES
+
+
+#if defined(__CYGWIN__)
+#define stat64 stat
+#endif
+struct stat64;
+
+extern _off64_t _lseek64_r _PARAMS ((struct _reent *, int, _off64_t, int));
+extern int _fstat64_r _PARAMS ((struct _reent *, int, struct stat64 *));
+extern int _open64_r _PARAMS ((struct _reent *, const char *, int, int));
+extern int _stat64_r _PARAMS ((struct _reent *, const char *, struct stat64 *));
+
+/* Don't pollute namespace if not building newlib. */
+#if defined (__CYGWIN__) && !defined (_COMPILING_NEWLIB)
+#undef stat64
+#endif
+
+#endif
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _REENT_H_ */
diff --git a/tools/sdk/include/newlib/regdef.h b/tools/sdk/include/newlib/regdef.h
new file mode 100644
index 00000000..8cf144b8
--- /dev/null
+++ b/tools/sdk/include/newlib/regdef.h
@@ -0,0 +1,7 @@
+/* regdef.h -- define register names.  */
+
+/* This is a standard include file for MIPS targets.  Other target
+   probably don't define it, and attempts to include this file will
+   fail.  */
+
+#include 
diff --git a/tools/sdk/include/newlib/regex.h b/tools/sdk/include/newlib/regex.h
new file mode 100644
index 00000000..fa3e2687
--- /dev/null
+++ b/tools/sdk/include/newlib/regex.h
@@ -0,0 +1,103 @@
+/*-
+ * Copyright (c) 1992 Henry Spencer.
+ * Copyright (c) 1992, 1993
+ *	The Regents of the University of California.  All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * Henry Spencer of the University of Toronto.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)regex.h	8.2 (Berkeley) 1/3/94
+ * $FreeBSD: src/include/regex.h,v 1.4 2002/03/23 17:24:53 imp Exp $
+ */
+
+#ifndef _REGEX_H_
+#define	_REGEX_H_
+
+#include 
+
+/* types */
+typedef off_t regoff_t;
+
+typedef struct {
+	int re_magic;
+	size_t re_nsub;		/* number of parenthesized subexpressions */
+	__const char *re_endp;	/* end pointer for REG_PEND */
+	struct re_guts *re_g;	/* none of your business :-) */
+} regex_t;
+
+typedef struct {
+	regoff_t rm_so;		/* start of match */
+	regoff_t rm_eo;		/* end of match */
+} regmatch_t;
+
+/* regcomp() flags */
+#define	REG_BASIC	0000
+#define	REG_EXTENDED	0001
+#define	REG_ICASE	0002
+#define	REG_NOSUB	0004
+#define	REG_NEWLINE	0010
+#define	REG_NOSPEC	0020
+#define	REG_PEND	0040
+#define	REG_DUMP	0200
+
+/* regerror() flags */
+#define	REG_NOMATCH	 1
+#define	REG_BADPAT	 2
+#define	REG_ECOLLATE	 3
+#define	REG_ECTYPE	 4
+#define	REG_EESCAPE	 5
+#define	REG_ESUBREG	 6
+#define	REG_EBRACK	 7
+#define	REG_EPAREN	 8
+#define	REG_EBRACE	 9
+#define	REG_BADBR	10
+#define	REG_ERANGE	11
+#define	REG_ESPACE	12
+#define	REG_BADRPT	13
+#define	REG_EMPTY	14
+#define	REG_ASSERT	15
+#define	REG_INVARG	16
+#define	REG_ATOI	255	/* convert name to number (!) */
+#define	REG_ITOA	0400	/* convert number to name (!) */
+
+/* regexec() flags */
+#define	REG_NOTBOL	00001
+#define	REG_NOTEOL	00002
+#define	REG_STARTEND	00004
+#define	REG_TRACE	00400	/* tracing of execution */
+#define	REG_LARGE	01000	/* force large representation */
+#define	REG_BACKR	02000	/* force use of backref code */
+
+__BEGIN_DECLS
+int	regcomp(regex_t *__restrict, const char *__restrict, int);
+size_t	regerror(int, const regex_t *__restrict, char *__restrict, size_t);
+int	regexec(const regex_t *__restrict, const char *__restrict,
+			size_t, regmatch_t [__restrict], int);
+void	regfree(regex_t *);
+__END_DECLS
+
+#endif /* !_REGEX_H_ */
diff --git a/tools/sdk/include/newlib/sched.h b/tools/sdk/include/newlib/sched.h
new file mode 100644
index 00000000..504ad527
--- /dev/null
+++ b/tools/sdk/include/newlib/sched.h
@@ -0,0 +1,97 @@
+/*
+ *  Written by Joel Sherrill .
+ *
+ *  COPYRIGHT (c) 1989-2010.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  Permission to use, copy, modify, and distribute this software for any
+ *  purpose without fee is hereby granted, provided that this entire notice
+ *  is included in all copies of any software which is or includes a copy
+ *  or modification of this software.
+ *
+ *  THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY.  IN PARTICULAR,  THE AUTHOR MAKES NO REPRESENTATION
+ *  OR WARRANTY OF ANY KIND CONCERNING THE MERCHANTABILITY OF THIS
+ *  SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR PURPOSE.
+ *
+ *  $Id$
+ */
+
+#ifndef _SCHED_H_
+#define _SCHED_H_
+
+#include 
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(_POSIX_PRIORITY_SCHEDULING)
+/*
+ *  XBD 13 - Set Scheduling Parameters, P1003.1b-2008, p. 1803
+ */
+int sched_setparam(
+  pid_t                     __pid,
+  const struct sched_param *__param
+);
+
+/*
+ *  XBD 13 - Set Scheduling Parameters, P1003.1b-2008, p. 1800
+ */
+int sched_getparam(
+  pid_t                     __pid,
+  struct sched_param       *__param
+);
+
+/*
+ *  XBD 13 - Set Scheduling Policy and Scheduling Parameters,
+ *         P1003.1b-2008, p. 1805
+ */
+int sched_setscheduler(
+  pid_t                     __pid,
+  int                       __policy,
+  const struct sched_param *__param
+);
+
+/*
+ *  XBD 13 - Get Scheduling Policy, P1003.1b-2008, p. 1801
+ */
+int sched_getscheduler(
+  pid_t                     __pid
+);
+
+/*
+ *  XBD 13 - Get Scheduling Parameter Limits, P1003.1b-2008, p. 1799
+ */
+int sched_get_priority_max(
+  int __policy
+);
+
+int sched_get_priority_min(
+  int  __policy
+);
+
+/*
+ *  XBD 13 - Get Scheduling Parameter Limits, P1003.1b-2008, p. 1802
+ */
+int sched_rr_get_interval(
+  pid_t             __pid,
+  struct timespec  *__interval
+);
+#endif /* _POSIX_PRIORITY_SCHEDULING */
+
+#if defined(_POSIX_THREADS) || defined(_POSIX_PRIORITY_SCHEDULING)
+
+/*
+ *  XBD 13 - Yield Processor, P1003.1b-2008, p. 1807
+ */
+int sched_yield( void );
+
+#endif /* _POSIX_THREADS or _POSIX_PRIORITY_SCHEDULING */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SCHED_H_ */
diff --git a/tools/sdk/include/newlib/search.h b/tools/sdk/include/newlib/search.h
new file mode 100644
index 00000000..ed321b0f
--- /dev/null
+++ b/tools/sdk/include/newlib/search.h
@@ -0,0 +1,64 @@
+/*	$NetBSD: search.h,v 1.12 1999/02/22 10:34:28 christos Exp $	*/
+/* $FreeBSD: src/include/search.h,v 1.4 2002/03/23 17:24:53 imp Exp $ */
+
+/*
+ * Written by J.T. Conklin 
+ * Public domain.
+ */
+
+#ifndef _SEARCH_H_
+#define _SEARCH_H_
+
+#include 
+#include 
+#include 
+
+typedef struct entry {
+	char *key;
+	void *data;
+} ENTRY;
+
+typedef enum {
+	FIND, ENTER
+} ACTION;
+
+typedef enum {
+	preorder,
+	postorder,
+	endorder,
+	leaf
+} VISIT;
+
+#ifdef _SEARCH_PRIVATE
+typedef struct node {
+	char         *key;
+	struct node  *llink, *rlink;
+} node_t;
+#endif
+
+struct hsearch_data
+{
+  struct internal_head *htable;
+  size_t htablesize;
+};
+
+#ifndef __compar_fn_t_defined
+#define __compar_fn_t_defined
+typedef int (*__compar_fn_t) (const void *, const void *);
+#endif
+
+__BEGIN_DECLS
+int	 hcreate(size_t);
+void	 hdestroy(void);
+ENTRY	*hsearch(ENTRY, ACTION);
+int	 hcreate_r(size_t, struct hsearch_data *);
+void	 hdestroy_r(struct hsearch_data *);
+int	hsearch_r(ENTRY, ACTION, ENTRY **, struct hsearch_data *);
+void	*tdelete(const void *__restrict, void **__restrict, __compar_fn_t);
+void	tdestroy (void *, void (*)(void *));
+void	*tfind(const void *, void **, __compar_fn_t);
+void	*tsearch(const void *, void **, __compar_fn_t);
+void      twalk(const void *, void (*)(const void *, VISIT, int));
+__END_DECLS
+
+#endif /* !_SEARCH_H_ */
diff --git a/tools/sdk/include/newlib/setjmp.h b/tools/sdk/include/newlib/setjmp.h
new file mode 100644
index 00000000..3d815d9b
--- /dev/null
+++ b/tools/sdk/include/newlib/setjmp.h
@@ -0,0 +1,27 @@
+/*
+	setjmp.h
+	stubs for future use.
+*/
+
+#ifndef _SETJMP_H_
+#define _SETJMP_H_
+
+#include "_ansi.h"
+#include 
+
+_BEGIN_STD_C
+
+#ifdef __GNUC__
+void	_EXFUN(longjmp,(jmp_buf __jmpb, int __retval))
+			__attribute__ ((__noreturn__));
+#else
+void	_EXFUN(longjmp,(jmp_buf __jmpb, int __retval));
+#endif
+int	_EXFUN(setjmp,(jmp_buf __jmpb));
+#define setjmp(env) setjmp(env)
+
+
+_END_STD_C
+
+#endif /* _SETJMP_H_ */
+
diff --git a/tools/sdk/include/newlib/signal.h b/tools/sdk/include/newlib/signal.h
new file mode 100644
index 00000000..8c50a2eb
--- /dev/null
+++ b/tools/sdk/include/newlib/signal.h
@@ -0,0 +1,32 @@
+#ifndef _SIGNAL_H_
+#define _SIGNAL_H_
+
+#include "_ansi.h"
+#include 
+
+_BEGIN_STD_C
+
+typedef int	sig_atomic_t;		/* Atomic entity type (ANSI) */
+#ifndef _POSIX_SOURCE
+typedef _sig_func_ptr sig_t;		/* BSD naming */
+typedef _sig_func_ptr sighandler_t;	/* glibc naming */
+#endif /* !_POSIX_SOURCE */
+
+#define SIG_DFL ((_sig_func_ptr)0)	/* Default action */
+#define SIG_IGN ((_sig_func_ptr)1)	/* Ignore action */
+#define SIG_ERR ((_sig_func_ptr)-1)	/* Error return */
+
+struct _reent;
+
+_sig_func_ptr _EXFUN(_signal_r, (struct _reent *, int, _sig_func_ptr));
+int	_EXFUN(_raise_r, (struct _reent *, int));
+
+#ifndef _REENT_ONLY
+_sig_func_ptr _EXFUN(signal, (int, _sig_func_ptr));
+int	_EXFUN(raise, (int));
+void	_EXFUN(psignal, (int, const char *));
+#endif
+
+_END_STD_C
+
+#endif /* _SIGNAL_H_ */
diff --git a/tools/sdk/include/newlib/spawn.h b/tools/sdk/include/newlib/spawn.h
new file mode 100644
index 00000000..5a6692f1
--- /dev/null
+++ b/tools/sdk/include/newlib/spawn.h
@@ -0,0 +1,119 @@
+/*-
+ * Copyright (c) 2008 Ed Schouten 
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _SPAWN_H_
+#define _SPAWN_H_
+
+#include <_ansi.h>
+#include 
+#include 
+#include 
+#define __need_sigset_t
+#include 
+
+struct sched_param;
+
+typedef struct __posix_spawnattr		*posix_spawnattr_t;
+typedef struct __posix_spawn_file_actions	*posix_spawn_file_actions_t;
+
+#define POSIX_SPAWN_RESETIDS		0x01
+#define POSIX_SPAWN_SETPGROUP		0x02
+#define POSIX_SPAWN_SETSCHEDPARAM	0x04
+#define POSIX_SPAWN_SETSCHEDULER	0x08
+#define POSIX_SPAWN_SETSIGDEF		0x10
+#define POSIX_SPAWN_SETSIGMASK		0x20
+
+_BEGIN_STD_C
+/*
+ * Spawn routines
+ *
+ * XXX both arrays should be __restrict, but this does not work when GCC
+ * is invoked with -std=c99.
+ */
+int _EXFUN(posix_spawn, (pid_t *  __restrict, const char * __restrict,
+	const posix_spawn_file_actions_t *, const posix_spawnattr_t * __restrict,
+	char * const [], char * const [])
+);
+int _EXFUN(posix_spawnp, (pid_t * __restrict, const char * __restrict,
+	const posix_spawn_file_actions_t *, const posix_spawnattr_t * __restrict,
+	char * const [], char * const [])
+);
+
+/*
+ * File descriptor actions
+ */
+int _EXFUN(posix_spawn_file_actions_init, (posix_spawn_file_actions_t *));
+int _EXFUN(posix_spawn_file_actions_destroy, (posix_spawn_file_actions_t *));
+
+int _EXFUN(posix_spawn_file_actions_addopen,
+	(posix_spawn_file_actions_t * __restrict, int, const char * __restrict, int, mode_t)
+);
+int _EXFUN(posix_spawn_file_actions_adddup2,
+	(posix_spawn_file_actions_t *, int, int)
+);
+int _EXFUN(posix_spawn_file_actions_addclose,
+	(posix_spawn_file_actions_t *, int)
+);
+
+/*
+ * Spawn attributes
+ */
+int _EXFUN(posix_spawnattr_init, (posix_spawnattr_t *));
+int _EXFUN(posix_spawnattr_destroy, (posix_spawnattr_t *));
+
+int _EXFUN(posix_spawnattr_getflags,
+	(const posix_spawnattr_t * __restrict, short * __restrict)
+);
+int _EXFUN(posix_spawnattr_getpgroup,
+	(const posix_spawnattr_t * __restrict, pid_t * __restrict));
+int _EXFUN(posix_spawnattr_getschedparam,
+	(const posix_spawnattr_t * __restrict, struct sched_param * __restrict)
+);
+int _EXFUN(posix_spawnattr_getschedpolicy,
+	(const posix_spawnattr_t * __restrict, int * __restrict)
+);
+int _EXFUN(posix_spawnattr_getsigdefault,
+	(const posix_spawnattr_t * __restrict, sigset_t * __restrict)
+);
+int _EXFUN(posix_spawnattr_getsigmask,
+	(const posix_spawnattr_t * __restrict, sigset_t * __restrict)
+);
+
+int _EXFUN(posix_spawnattr_setflags, (posix_spawnattr_t *, short));
+int _EXFUN(posix_spawnattr_setpgroup, (posix_spawnattr_t *, pid_t));
+int _EXFUN(posix_spawnattr_setschedparam,
+	(posix_spawnattr_t * __restrict, const struct sched_param * __restrict)
+);
+int _EXFUN(posix_spawnattr_setschedpolicy, (posix_spawnattr_t *, int));
+int _EXFUN(posix_spawnattr_setsigdefault,
+	(posix_spawnattr_t * __restrict, const sigset_t * __restrict)
+);
+int _EXFUN(posix_spawnattr_setsigmask,
+	(posix_spawnattr_t * __restrict, const sigset_t * __restrict)
+);
+_END_STD_C
+
+#endif /* !_SPAWN_H_ */
diff --git a/tools/sdk/include/newlib/stdatomic.h b/tools/sdk/include/newlib/stdatomic.h
new file mode 100644
index 00000000..09c0cf73
--- /dev/null
+++ b/tools/sdk/include/newlib/stdatomic.h
@@ -0,0 +1,413 @@
+/*-
+ * Copyright (c) 2011 Ed Schouten 
+ *                    David Chisnall 
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _STDATOMIC_H_
+#define	_STDATOMIC_H_
+
+#include 
+#include 
+
+#if __has_extension(c_atomic) || __has_extension(cxx_atomic)
+#define	__CLANG_ATOMICS
+#elif __GNUC_PREREQ__(4, 7)
+#define	__GNUC_ATOMICS
+#elif defined(__GNUC__)
+#define	__SYNC_ATOMICS
+#else
+#error "stdatomic.h does not support your compiler"
+#endif
+
+/*
+ * 7.17.1 Atomic lock-free macros.
+ */
+
+#ifdef __GCC_ATOMIC_BOOL_LOCK_FREE
+#define	ATOMIC_BOOL_LOCK_FREE		__GCC_ATOMIC_BOOL_LOCK_FREE
+#endif
+#ifdef __GCC_ATOMIC_CHAR_LOCK_FREE
+#define	ATOMIC_CHAR_LOCK_FREE		__GCC_ATOMIC_CHAR_LOCK_FREE
+#endif
+#ifdef __GCC_ATOMIC_CHAR16_T_LOCK_FREE
+#define	ATOMIC_CHAR16_T_LOCK_FREE	__GCC_ATOMIC_CHAR16_T_LOCK_FREE
+#endif
+#ifdef __GCC_ATOMIC_CHAR32_T_LOCK_FREE
+#define	ATOMIC_CHAR32_T_LOCK_FREE	__GCC_ATOMIC_CHAR32_T_LOCK_FREE
+#endif
+#ifdef __GCC_ATOMIC_WCHAR_T_LOCK_FREE
+#define	ATOMIC_WCHAR_T_LOCK_FREE	__GCC_ATOMIC_WCHAR_T_LOCK_FREE
+#endif
+#ifdef __GCC_ATOMIC_SHORT_LOCK_FREE
+#define	ATOMIC_SHORT_LOCK_FREE		__GCC_ATOMIC_SHORT_LOCK_FREE
+#endif
+#ifdef __GCC_ATOMIC_INT_LOCK_FREE
+#define	ATOMIC_INT_LOCK_FREE		__GCC_ATOMIC_INT_LOCK_FREE
+#endif
+#ifdef __GCC_ATOMIC_LONG_LOCK_FREE
+#define	ATOMIC_LONG_LOCK_FREE		__GCC_ATOMIC_LONG_LOCK_FREE
+#endif
+#ifdef __GCC_ATOMIC_LLONG_LOCK_FREE
+#define	ATOMIC_LLONG_LOCK_FREE		__GCC_ATOMIC_LLONG_LOCK_FREE
+#endif
+#ifdef __GCC_ATOMIC_POINTER_LOCK_FREE
+#define	ATOMIC_POINTER_LOCK_FREE	__GCC_ATOMIC_POINTER_LOCK_FREE
+#endif
+
+/*
+ * 7.17.2 Initialization.
+ */
+
+#if defined(__CLANG_ATOMICS)
+#define	ATOMIC_VAR_INIT(value)		(value)
+#define	atomic_init(obj, value)		__c11_atomic_init(obj, value)
+#else
+#define	ATOMIC_VAR_INIT(value)		{ .__val = (value) }
+#define	atomic_init(obj, value)		((void)((obj)->__val = (value)))
+#endif
+
+/*
+ * Clang and recent GCC both provide predefined macros for the memory
+ * orderings.  If we are using a compiler that doesn't define them, use the
+ * clang values - these will be ignored in the fallback path.
+ */
+
+#ifndef __ATOMIC_RELAXED
+#define __ATOMIC_RELAXED		0
+#endif
+#ifndef __ATOMIC_CONSUME
+#define __ATOMIC_CONSUME		1
+#endif
+#ifndef __ATOMIC_ACQUIRE
+#define __ATOMIC_ACQUIRE		2
+#endif
+#ifndef __ATOMIC_RELEASE
+#define __ATOMIC_RELEASE		3
+#endif
+#ifndef __ATOMIC_ACQ_REL
+#define __ATOMIC_ACQ_REL		4
+#endif
+#ifndef __ATOMIC_SEQ_CST
+#define __ATOMIC_SEQ_CST		5
+#endif
+
+/*
+ * 7.17.3 Order and consistency.
+ *
+ * The memory_order_* constants that denote the barrier behaviour of the
+ * atomic operations.
+ */
+
+typedef enum {
+	memory_order_relaxed = __ATOMIC_RELAXED,
+	memory_order_consume = __ATOMIC_CONSUME,
+	memory_order_acquire = __ATOMIC_ACQUIRE,
+	memory_order_release = __ATOMIC_RELEASE,
+	memory_order_acq_rel = __ATOMIC_ACQ_REL,
+	memory_order_seq_cst = __ATOMIC_SEQ_CST
+} memory_order;
+
+/*
+ * 7.17.4 Fences.
+ */
+
+static __inline void
+atomic_thread_fence(memory_order __order __unused)
+{
+
+#ifdef __CLANG_ATOMICS
+	__c11_atomic_thread_fence(__order);
+#elif defined(__GNUC_ATOMICS)
+	__atomic_thread_fence(__order);
+#else
+	__sync_synchronize();
+#endif
+}
+
+static __inline void
+atomic_signal_fence(memory_order __order __unused)
+{
+
+#ifdef __CLANG_ATOMICS
+	__c11_atomic_signal_fence(__order);
+#elif defined(__GNUC_ATOMICS)
+	__atomic_signal_fence(__order);
+#else
+	__asm volatile ("" ::: "memory");
+#endif
+}
+
+/*
+ * 7.17.5 Lock-free property.
+ */
+
+#if defined(_KERNEL)
+/* Atomics in kernelspace are always lock-free. */
+#define	atomic_is_lock_free(obj) \
+	((void)(obj), (_Bool)1)
+#elif defined(__CLANG_ATOMICS)
+#define	atomic_is_lock_free(obj) \
+	__atomic_is_lock_free(sizeof(*(obj)), obj)
+#elif defined(__GNUC_ATOMICS)
+#define	atomic_is_lock_free(obj) \
+	__atomic_is_lock_free(sizeof((obj)->__val), &(obj)->__val)
+#else
+#define	atomic_is_lock_free(obj) \
+	((void)(obj), sizeof((obj)->__val) <= sizeof(void *))
+#endif
+
+/*
+ * 7.17.6 Atomic integer types.
+ */
+
+typedef _Atomic(_Bool)			atomic_bool;
+typedef _Atomic(char)			atomic_char;
+typedef _Atomic(signed char)		atomic_schar;
+typedef _Atomic(unsigned char)		atomic_uchar;
+typedef _Atomic(short)			atomic_short;
+typedef _Atomic(unsigned short)		atomic_ushort;
+typedef _Atomic(int)			atomic_int;
+typedef _Atomic(unsigned int)		atomic_uint;
+typedef _Atomic(long)			atomic_long;
+typedef _Atomic(unsigned long)		atomic_ulong;
+typedef _Atomic(long long)		atomic_llong;
+typedef _Atomic(unsigned long long)	atomic_ullong;
+#if 0
+typedef _Atomic(__char16_t)		atomic_char16_t;
+typedef _Atomic(__char32_t)		atomic_char32_t;
+#endif
+typedef _Atomic(wchar_t)		atomic_wchar_t;
+typedef _Atomic(int_least8_t)		atomic_int_least8_t;
+typedef _Atomic(uint_least8_t)		atomic_uint_least8_t;
+typedef _Atomic(int_least16_t)		atomic_int_least16_t;
+typedef _Atomic(uint_least16_t)		atomic_uint_least16_t;
+typedef _Atomic(int_least32_t)		atomic_int_least32_t;
+typedef _Atomic(uint_least32_t)		atomic_uint_least32_t;
+typedef _Atomic(int_least64_t)		atomic_int_least64_t;
+typedef _Atomic(uint_least64_t)		atomic_uint_least64_t;
+typedef _Atomic(int_fast8_t)		atomic_int_fast8_t;
+typedef _Atomic(uint_fast8_t)		atomic_uint_fast8_t;
+typedef _Atomic(int_fast16_t)		atomic_int_fast16_t;
+typedef _Atomic(uint_fast16_t)		atomic_uint_fast16_t;
+typedef _Atomic(int_fast32_t)		atomic_int_fast32_t;
+typedef _Atomic(uint_fast32_t)		atomic_uint_fast32_t;
+typedef _Atomic(int_fast64_t)		atomic_int_fast64_t;
+typedef _Atomic(uint_fast64_t)		atomic_uint_fast64_t;
+typedef _Atomic(intptr_t)		atomic_intptr_t;
+typedef _Atomic(uintptr_t)		atomic_uintptr_t;
+typedef _Atomic(size_t)			atomic_size_t;
+typedef _Atomic(ptrdiff_t)		atomic_ptrdiff_t;
+typedef _Atomic(intmax_t)		atomic_intmax_t;
+typedef _Atomic(uintmax_t)		atomic_uintmax_t;
+
+/*
+ * 7.17.7 Operations on atomic types.
+ */
+
+/*
+ * Compiler-specific operations.
+ */
+
+#if defined(__CLANG_ATOMICS)
+#define	atomic_compare_exchange_strong_explicit(object, expected,	\
+    desired, success, failure)						\
+	__c11_atomic_compare_exchange_strong(object, expected, desired,	\
+	    success, failure)
+#define	atomic_compare_exchange_weak_explicit(object, expected,		\
+    desired, success, failure)						\
+	__c11_atomic_compare_exchange_weak(object, expected, desired,	\
+	    success, failure)
+#define	atomic_exchange_explicit(object, desired, order)		\
+	__c11_atomic_exchange(object, desired, order)
+#define	atomic_fetch_add_explicit(object, operand, order)		\
+	__c11_atomic_fetch_add(object, operand, order)
+#define	atomic_fetch_and_explicit(object, operand, order)		\
+	__c11_atomic_fetch_and(object, operand, order)
+#define	atomic_fetch_or_explicit(object, operand, order)		\
+	__c11_atomic_fetch_or(object, operand, order)
+#define	atomic_fetch_sub_explicit(object, operand, order)		\
+	__c11_atomic_fetch_sub(object, operand, order)
+#define	atomic_fetch_xor_explicit(object, operand, order)		\
+	__c11_atomic_fetch_xor(object, operand, order)
+#define	atomic_load_explicit(object, order)				\
+	__c11_atomic_load(object, order)
+#define	atomic_store_explicit(object, desired, order)			\
+	__c11_atomic_store(object, desired, order)
+#elif defined(__GNUC_ATOMICS)
+#define	atomic_compare_exchange_strong_explicit(object, expected,	\
+    desired, success, failure)						\
+	__atomic_compare_exchange_n(&(object)->__val, expected,		\
+	    desired, 0, success, failure)
+#define	atomic_compare_exchange_weak_explicit(object, expected,		\
+    desired, success, failure)						\
+	__atomic_compare_exchange_n(&(object)->__val, expected,		\
+	    desired, 1, success, failure)
+#define	atomic_exchange_explicit(object, desired, order)		\
+	__atomic_exchange_n(&(object)->__val, desired, order)
+#define	atomic_fetch_add_explicit(object, operand, order)		\
+	__atomic_fetch_add(&(object)->__val, operand, order)
+#define	atomic_fetch_and_explicit(object, operand, order)		\
+	__atomic_fetch_and(&(object)->__val, operand, order)
+#define	atomic_fetch_or_explicit(object, operand, order)		\
+	__atomic_fetch_or(&(object)->__val, operand, order)
+#define	atomic_fetch_sub_explicit(object, operand, order)		\
+	__atomic_fetch_sub(&(object)->__val, operand, order)
+#define	atomic_fetch_xor_explicit(object, operand, order)		\
+	__atomic_fetch_xor(&(object)->__val, operand, order)
+#define	atomic_load_explicit(object, order)				\
+	__atomic_load_n(&(object)->__val, order)
+#define	atomic_store_explicit(object, desired, order)			\
+	__atomic_store_n(&(object)->__val, desired, order)
+#else
+#define	__atomic_apply_stride(object, operand) \
+	(((__typeof__((object)->__val))0) + (operand))
+#define	atomic_compare_exchange_strong_explicit(object, expected,	\
+    desired, success, failure)	__extension__ ({			\
+	__typeof__(expected) __ep = (expected);				\
+	__typeof__(*__ep) __e = *__ep;					\
+	(void)(success); (void)(failure);				\
+	(_Bool)((*__ep = __sync_val_compare_and_swap(&(object)->__val,	\
+	    __e, desired)) == __e);					\
+})
+#define	atomic_compare_exchange_weak_explicit(object, expected,		\
+    desired, success, failure)						\
+	atomic_compare_exchange_strong_explicit(object, expected,	\
+		desired, success, failure)
+#if __has_builtin(__sync_swap)
+/* Clang provides a full-barrier atomic exchange - use it if available. */
+#define	atomic_exchange_explicit(object, desired, order)		\
+	((void)(order), __sync_swap(&(object)->__val, desired))
+#else
+/*
+ * __sync_lock_test_and_set() is only an acquire barrier in theory (although in
+ * practice it is usually a full barrier) so we need an explicit barrier before
+ * it.
+ */
+#define	atomic_exchange_explicit(object, desired, order)		\
+__extension__ ({							\
+	__typeof__(object) __o = (object);				\
+	__typeof__(desired) __d = (desired);				\
+	(void)(order);							\
+	__sync_synchronize();						\
+	__sync_lock_test_and_set(&(__o)->__val, __d);			\
+})
+#endif
+#define	atomic_fetch_add_explicit(object, operand, order)		\
+	((void)(order), __sync_fetch_and_add(&(object)->__val,		\
+	    __atomic_apply_stride(object, operand)))
+#define	atomic_fetch_and_explicit(object, operand, order)		\
+	((void)(order), __sync_fetch_and_and(&(object)->__val, operand))
+#define	atomic_fetch_or_explicit(object, operand, order)		\
+	((void)(order), __sync_fetch_and_or(&(object)->__val, operand))
+#define	atomic_fetch_sub_explicit(object, operand, order)		\
+	((void)(order), __sync_fetch_and_sub(&(object)->__val,		\
+	    __atomic_apply_stride(object, operand)))
+#define	atomic_fetch_xor_explicit(object, operand, order)		\
+	((void)(order), __sync_fetch_and_xor(&(object)->__val, operand))
+#define	atomic_load_explicit(object, order)				\
+	((void)(order), __sync_fetch_and_add(&(object)->__val, 0))
+#define	atomic_store_explicit(object, desired, order)			\
+	((void)atomic_exchange_explicit(object, desired, order))
+#endif
+
+/*
+ * Convenience functions.
+ *
+ * Don't provide these in kernel space. In kernel space, we should be
+ * disciplined enough to always provide explicit barriers.
+ */
+
+#ifndef _KERNEL
+#define	atomic_compare_exchange_strong(object, expected, desired)	\
+	atomic_compare_exchange_strong_explicit(object, expected,	\
+	    desired, memory_order_seq_cst, memory_order_seq_cst)
+#define	atomic_compare_exchange_weak(object, expected, desired)		\
+	atomic_compare_exchange_weak_explicit(object, expected,		\
+	    desired, memory_order_seq_cst, memory_order_seq_cst)
+#define	atomic_exchange(object, desired)				\
+	atomic_exchange_explicit(object, desired, memory_order_seq_cst)
+#define	atomic_fetch_add(object, operand)				\
+	atomic_fetch_add_explicit(object, operand, memory_order_seq_cst)
+#define	atomic_fetch_and(object, operand)				\
+	atomic_fetch_and_explicit(object, operand, memory_order_seq_cst)
+#define	atomic_fetch_or(object, operand)				\
+	atomic_fetch_or_explicit(object, operand, memory_order_seq_cst)
+#define	atomic_fetch_sub(object, operand)				\
+	atomic_fetch_sub_explicit(object, operand, memory_order_seq_cst)
+#define	atomic_fetch_xor(object, operand)				\
+	atomic_fetch_xor_explicit(object, operand, memory_order_seq_cst)
+#define	atomic_load(object)						\
+	atomic_load_explicit(object, memory_order_seq_cst)
+#define	atomic_store(object, desired)					\
+	atomic_store_explicit(object, desired, memory_order_seq_cst)
+#endif /* !_KERNEL */
+
+/*
+ * 7.17.8 Atomic flag type and operations.
+ *
+ * XXX: Assume atomic_bool can be used as an atomic_flag. Is there some
+ * kind of compiler built-in type we could use?
+ */
+
+typedef struct {
+	atomic_bool	__flag;
+} atomic_flag;
+
+#define	ATOMIC_FLAG_INIT		{ ATOMIC_VAR_INIT(0) }
+
+static __inline _Bool
+atomic_flag_test_and_set_explicit(volatile atomic_flag *__object,
+    memory_order __order)
+{
+	return (atomic_exchange_explicit(&__object->__flag, 1, __order));
+}
+
+static __inline void
+atomic_flag_clear_explicit(volatile atomic_flag *__object, memory_order __order)
+{
+
+	atomic_store_explicit(&__object->__flag, 0, __order);
+}
+
+#ifndef _KERNEL
+static __inline _Bool
+atomic_flag_test_and_set(volatile atomic_flag *__object)
+{
+
+	return (atomic_flag_test_and_set_explicit(__object,
+	    memory_order_seq_cst));
+}
+
+static __inline void
+atomic_flag_clear(volatile atomic_flag *__object)
+{
+
+	atomic_flag_clear_explicit(__object, memory_order_seq_cst);
+}
+#endif /* !_KERNEL */
+
+#endif /* !_STDATOMIC_H_ */
diff --git a/tools/sdk/include/newlib/stdint.h b/tools/sdk/include/newlib/stdint.h
new file mode 100644
index 00000000..7386164b
--- /dev/null
+++ b/tools/sdk/include/newlib/stdint.h
@@ -0,0 +1,511 @@
+/*
+ * Copyright (c) 2004, 2005 by
+ * Ralf Corsepius, Ulm/Germany. All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software
+ * is freely granted, provided that this notice is preserved.
+ */
+
+#ifndef _STDINT_H
+#define _STDINT_H
+
+#include 
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef ___int8_t_defined
+typedef __int8_t int8_t ;
+typedef __uint8_t uint8_t ;
+#define __int8_t_defined 1
+#endif
+
+#ifdef ___int_least8_t_defined
+typedef __int_least8_t int_least8_t;
+typedef __uint_least8_t uint_least8_t;
+#define __int_least8_t_defined 1
+#endif
+
+#ifdef ___int16_t_defined
+typedef __int16_t int16_t ;
+typedef __uint16_t uint16_t ;
+#define __int16_t_defined 1
+#endif
+
+#ifdef ___int_least16_t_defined
+typedef __int_least16_t int_least16_t;
+typedef __uint_least16_t uint_least16_t;
+#define __int_least16_t_defined 1
+#endif
+
+#ifdef ___int32_t_defined
+typedef __int32_t int32_t ;
+typedef __uint32_t uint32_t ;
+#define __int32_t_defined 1
+#endif
+
+#ifdef ___int_least32_t_defined
+typedef __int_least32_t int_least32_t;
+typedef __uint_least32_t uint_least32_t;
+#define __int_least32_t_defined 1
+#endif
+
+#ifdef ___int64_t_defined
+typedef __int64_t int64_t ;
+typedef __uint64_t uint64_t ;
+#define __int64_t_defined 1
+#endif
+
+#ifdef ___int_least64_t_defined
+typedef __int_least64_t int_least64_t;
+typedef __uint_least64_t uint_least64_t;
+#define __int_least64_t_defined 1
+#endif
+
+/*
+ * Fastest minimum-width integer types
+ *
+ * Assume int to be the fastest type for all types with a width 
+ * less than __INT_MAX__ rsp. INT_MAX
+ */
+#ifdef __INT_FAST8_TYPE__
+  typedef __INT_FAST8_TYPE__ int_fast8_t;
+  typedef __UINT_FAST8_TYPE__ uint_fast8_t;
+#define __int_fast8_t_defined 1
+#elif __STDINT_EXP(INT_MAX) >= 0x7f
+  typedef signed int int_fast8_t;
+  typedef unsigned int uint_fast8_t;
+#define __int_fast8_t_defined 1
+#endif
+
+#ifdef __INT_FAST16_TYPE__
+  typedef __INT_FAST16_TYPE__ int_fast16_t;
+  typedef __UINT_FAST16_TYPE__ uint_fast16_t;
+#define __int_fast16_t_defined 1
+#elif __STDINT_EXP(INT_MAX) >= 0x7fff
+  typedef signed int int_fast16_t;
+  typedef unsigned int uint_fast16_t;
+#define __int_fast16_t_defined 1
+#endif
+
+#ifdef __INT_FAST32_TYPE__
+  typedef __INT_FAST32_TYPE__ int_fast32_t;
+  typedef __UINT_FAST32_TYPE__ uint_fast32_t;
+#define __int_fast32_t_defined 1
+#elif __STDINT_EXP(INT_MAX) >= 0x7fffffff
+  typedef signed int int_fast32_t;
+  typedef unsigned int uint_fast32_t;
+#define __int_fast32_t_defined 1
+#endif
+
+#ifdef __INT_FAST64_TYPE__
+  typedef __INT_FAST64_TYPE__ int_fast64_t;
+  typedef __UINT_FAST64_TYPE__ uint_fast64_t;
+#define __int_fast64_t_defined 1
+#elif __STDINT_EXP(INT_MAX) > 0x7fffffff
+  typedef signed int int_fast64_t;
+  typedef unsigned int uint_fast64_t;
+#define __int_fast64_t_defined 1
+#endif
+
+/*
+ * Fall back to [u]int_least_t for [u]int_fast_t types
+ * not having been defined, yet.
+ * Leave undefined, if [u]int_least_t should not be available.
+ */
+#if !__int_fast8_t_defined
+#if __int_least8_t_defined
+  typedef int_least8_t int_fast8_t;
+  typedef uint_least8_t uint_fast8_t;
+#define __int_fast8_t_defined 1
+#endif
+#endif
+
+#if !__int_fast16_t_defined
+#if __int_least16_t_defined
+  typedef int_least16_t int_fast16_t;
+  typedef uint_least16_t uint_fast16_t;
+#define __int_fast16_t_defined 1
+#endif
+#endif
+
+#if !__int_fast32_t_defined
+#if __int_least32_t_defined
+  typedef int_least32_t int_fast32_t;
+  typedef uint_least32_t uint_fast32_t;
+#define __int_fast32_t_defined 1
+#endif
+#endif
+
+#if !__int_fast64_t_defined
+#if __int_least64_t_defined
+  typedef int_least64_t int_fast64_t;
+  typedef uint_least64_t uint_fast64_t;
+#define __int_fast64_t_defined 1
+#endif
+#endif
+
+/* Greatest-width integer types */
+/* Modern GCCs provide __INTMAX_TYPE__ */
+#if defined(__INTMAX_TYPE__)
+  typedef __INTMAX_TYPE__ intmax_t;
+#elif __have_longlong64
+  typedef signed long long intmax_t;
+#else
+  typedef signed long intmax_t;
+#endif
+
+/* Modern GCCs provide __UINTMAX_TYPE__ */
+#if defined(__UINTMAX_TYPE__)
+  typedef __UINTMAX_TYPE__ uintmax_t;
+#elif __have_longlong64
+  typedef unsigned long long uintmax_t;
+#else
+  typedef unsigned long uintmax_t;
+#endif
+
+typedef __intptr_t intptr_t;
+typedef __uintptr_t uintptr_t;
+
+#ifdef __INTPTR_TYPE__
+#define INTPTR_MIN (-__INTPTR_MAX__ - 1)
+#define INTPTR_MAX __INTPTR_MAX__
+#define UINTPTR_MAX __UINTPTR_MAX__
+#elif defined(__PTRDIFF_TYPE__)
+#define INTPTR_MAX PTRDIFF_MAX
+#define INTPTR_MIN PTRDIFF_MIN
+#ifdef __UINTPTR_MAX__
+#define UINTPTR_MAX __UINTPTR_MAX__
+#else
+#define UINTPTR_MAX (2UL * PTRDIFF_MAX + 1)
+#endif
+#else
+/*
+ * Fallback to hardcoded values, 
+ * should be valid on cpu's with 32bit int/32bit void*
+ */
+#define INTPTR_MAX __STDINT_EXP(LONG_MAX)
+#define INTPTR_MIN (-__STDINT_EXP(LONG_MAX) - 1)
+#define UINTPTR_MAX (__STDINT_EXP(LONG_MAX) * 2UL + 1)
+#endif
+
+/* Limits of Specified-Width Integer Types */
+
+#ifdef __INT8_MAX__
+#define INT8_MIN (-__INT8_MAX__ - 1)
+#define INT8_MAX __INT8_MAX__
+#define UINT8_MAX __UINT8_MAX__
+#elif defined(__int8_t_defined)
+#define INT8_MIN 	-128
+#define INT8_MAX 	 127
+#define UINT8_MAX 	 255
+#endif
+
+#ifdef __INT_LEAST8_MAX__
+#define INT_LEAST8_MIN (-__INT_LEAST8_MAX__ - 1)
+#define INT_LEAST8_MAX __INT_LEAST8_MAX__
+#define UINT_LEAST8_MAX __UINT_LEAST8_MAX__
+#elif defined(__int_least8_t_defined)
+#define INT_LEAST8_MIN 	-128
+#define INT_LEAST8_MAX 	 127
+#define UINT_LEAST8_MAX	 255
+#else
+#error required type int_least8_t missing
+#endif
+
+#ifdef __INT16_MAX__
+#define INT16_MIN (-__INT16_MAX__ - 1)
+#define INT16_MAX __INT16_MAX__
+#define UINT16_MAX __UINT16_MAX__
+#elif defined(__int16_t_defined)
+#define INT16_MIN 	-32768
+#define INT16_MAX 	 32767
+#define UINT16_MAX 	 65535
+#endif
+
+#ifdef __INT_LEAST16_MAX__
+#define INT_LEAST16_MIN (-__INT_LEAST16_MAX__ - 1)
+#define INT_LEAST16_MAX __INT_LEAST16_MAX__
+#define UINT_LEAST16_MAX __UINT_LEAST16_MAX__
+#elif defined(__int_least16_t_defined)
+#define INT_LEAST16_MIN	-32768
+#define INT_LEAST16_MAX	 32767
+#define UINT_LEAST16_MAX 65535
+#else
+#error required type int_least16_t missing
+#endif
+
+#ifdef __INT32_MAX__
+#define INT32_MIN (-__INT32_MAX__ - 1)
+#define INT32_MAX __INT32_MAX__
+#define UINT32_MAX __UINT32_MAX__
+#elif defined(__int32_t_defined)
+#if __have_long32
+#define INT32_MIN 	 (-2147483647L-1)
+#define INT32_MAX 	 2147483647L
+#define UINT32_MAX       4294967295UL
+#else
+#define INT32_MIN 	 (-2147483647-1)
+#define INT32_MAX 	 2147483647
+#define UINT32_MAX       4294967295U
+#endif
+#endif
+
+#ifdef __INT_LEAST32_MAX__
+#define INT_LEAST32_MIN (-__INT_LEAST32_MAX__ - 1)
+#define INT_LEAST32_MAX __INT_LEAST32_MAX__
+#define UINT_LEAST32_MAX __UINT_LEAST32_MAX__
+#elif defined(__int_least32_t_defined)
+#if __have_long32
+#define INT_LEAST32_MIN  (-2147483647L-1)
+#define INT_LEAST32_MAX  2147483647L
+#define UINT_LEAST32_MAX 4294967295UL
+#else
+#define INT_LEAST32_MIN  (-2147483647-1)
+#define INT_LEAST32_MAX  2147483647
+#define UINT_LEAST32_MAX 4294967295U
+#endif
+#else
+#error required type int_least32_t missing
+#endif
+
+#ifdef __INT64_MAX__
+#define INT64_MIN (-__INT64_MAX__ - 1)
+#define INT64_MAX __INT64_MAX__
+#define UINT64_MAX __UINT64_MAX__
+#elif defined(__int64_t_defined)
+#if __have_long64
+#define INT64_MIN 	(-9223372036854775807L-1L)
+#define INT64_MAX 	 9223372036854775807L
+#define UINT64_MAX 	18446744073709551615U
+#elif __have_longlong64
+#define INT64_MIN 	(-9223372036854775807LL-1LL)
+#define INT64_MAX 	 9223372036854775807LL
+#define UINT64_MAX 	18446744073709551615ULL
+#endif
+#endif
+
+#ifdef __INT_LEAST64_MAX__
+#define INT_LEAST64_MIN (-__INT_LEAST64_MAX__ - 1)
+#define INT_LEAST64_MAX __INT_LEAST64_MAX__
+#define UINT_LEAST64_MAX __UINT_LEAST64_MAX__
+#elif defined(__int_least64_t_defined)
+#if __have_long64
+#define INT_LEAST64_MIN  (-9223372036854775807L-1L)
+#define INT_LEAST64_MAX  9223372036854775807L
+#define UINT_LEAST64_MAX 18446744073709551615U
+#elif __have_longlong64
+#define INT_LEAST64_MIN  (-9223372036854775807LL-1LL)
+#define INT_LEAST64_MAX  9223372036854775807LL
+#define UINT_LEAST64_MAX 18446744073709551615ULL
+#endif
+#endif
+
+#ifdef __INT_FAST8_MAX__
+#define INT_FAST8_MIN (-__INT_FAST8_MAX__ - 1)
+#define INT_FAST8_MAX __INT_FAST8_MAX__
+#define UINT_FAST8_MAX __UINT_FAST8_MAX__
+#elif defined(__int_fast8_t_defined)
+#if __STDINT_EXP(INT_MAX) >= 0x7f
+#define INT_FAST8_MIN	(-__STDINT_EXP(INT_MAX)-1)
+#define INT_FAST8_MAX	__STDINT_EXP(INT_MAX)
+#define UINT_FAST8_MAX	(__STDINT_EXP(INT_MAX)*2U+1U)
+#else
+#define INT_FAST8_MIN	INT_LEAST8_MIN
+#define INT_FAST8_MAX	INT_LEAST8_MAX
+#define UINT_FAST8_MAX	UINT_LEAST8_MAX
+#endif
+#endif
+
+#ifdef __INT_FAST16_MAX__
+#define INT_FAST16_MIN (-__INT_FAST16_MAX__ - 1)
+#define INT_FAST16_MAX __INT_FAST16_MAX__
+#define UINT_FAST16_MAX __UINT_FAST16_MAX__
+#elif defined(__int_fast16_t_defined)
+#if __STDINT_EXP(INT_MAX) >= 0x7fff
+#define INT_FAST16_MIN	(-__STDINT_EXP(INT_MAX)-1)
+#define INT_FAST16_MAX	__STDINT_EXP(INT_MAX)
+#define UINT_FAST16_MAX	(__STDINT_EXP(INT_MAX)*2U+1U)
+#else
+#define INT_FAST16_MIN	INT_LEAST16_MIN
+#define INT_FAST16_MAX	INT_LEAST16_MAX
+#define UINT_FAST16_MAX	UINT_LEAST16_MAX
+#endif
+#endif
+
+#ifdef __INT_FAST32_MAX__
+#define INT_FAST32_MIN (-__INT_FAST32_MAX__ - 1)
+#define INT_FAST32_MAX __INT_FAST32_MAX__
+#define UINT_FAST32_MAX __UINT_FAST32_MAX__
+#elif defined(__int_fast32_t_defined)
+#if __STDINT_EXP(INT_MAX) >= 0x7fffffff
+#define INT_FAST32_MIN	(-__STDINT_EXP(INT_MAX)-1)
+#define INT_FAST32_MAX	__STDINT_EXP(INT_MAX)
+#define UINT_FAST32_MAX	(__STDINT_EXP(INT_MAX)*2U+1U)
+#else
+#define INT_FAST32_MIN	INT_LEAST32_MIN
+#define INT_FAST32_MAX	INT_LEAST32_MAX
+#define UINT_FAST32_MAX	UINT_LEAST32_MAX
+#endif
+#endif
+
+#ifdef __INT_FAST64_MAX__
+#define INT_FAST64_MIN (-__INT_FAST64_MAX__ - 1)
+#define INT_FAST64_MAX __INT_FAST64_MAX__
+#define UINT_FAST64_MAX __UINT_FAST64_MAX__
+#elif defined(__int_fast64_t_defined)
+#if __STDINT_EXP(INT_MAX) > 0x7fffffff
+#define INT_FAST64_MIN	(-__STDINT_EXP(INT_MAX)-1)
+#define INT_FAST64_MAX	__STDINT_EXP(INT_MAX)
+#define UINT_FAST64_MAX	(__STDINT_EXP(INT_MAX)*2U+1U)
+#else
+#define INT_FAST64_MIN	INT_LEAST64_MIN
+#define INT_FAST64_MAX	INT_LEAST64_MAX
+#define UINT_FAST64_MAX	UINT_LEAST64_MAX
+#endif
+#endif
+
+#ifdef __INTMAX_MAX__
+#define INTMAX_MAX __INTMAX_MAX__
+#define INTMAX_MIN (-INTMAX_MAX - 1)
+#elif defined(__INTMAX_TYPE__)
+/* All relevant GCC versions prefer long to long long for intmax_t.  */
+#define INTMAX_MAX INT64_MAX
+#define INTMAX_MIN INT64_MIN
+#endif
+
+#ifdef __UINTMAX_MAX__
+#define UINTMAX_MAX __UINTMAX_MAX__
+#elif defined(__UINTMAX_TYPE__)
+/* All relevant GCC versions prefer long to long long for intmax_t.  */
+#define UINTMAX_MAX UINT64_MAX
+#endif
+
+/* This must match size_t in stddef.h, currently long unsigned int */
+#ifdef __SIZE_MAX__
+#define SIZE_MAX __SIZE_MAX__
+#else
+#define SIZE_MAX (__STDINT_EXP(LONG_MAX) * 2UL + 1)
+#endif
+
+/* This must match sig_atomic_t in  (currently int) */
+#define SIG_ATOMIC_MIN (-__STDINT_EXP(INT_MAX) - 1)
+#define SIG_ATOMIC_MAX __STDINT_EXP(INT_MAX)
+
+/* This must match ptrdiff_t  in  (currently long int) */
+#ifdef __PTRDIFF_MAX__
+#define PTRDIFF_MAX __PTRDIFF_MAX__
+#else
+#define PTRDIFF_MAX __STDINT_EXP(LONG_MAX)
+#endif
+#define PTRDIFF_MIN (-PTRDIFF_MAX - 1)
+
+/* This must match definition in  */
+#ifndef WCHAR_MIN
+#ifdef __WCHAR_MIN__
+#define WCHAR_MIN __WCHAR_MIN__
+#elif defined(__WCHAR_UNSIGNED__) || (L'\0' - 1 > 0)
+#define WCHAR_MIN (0 + L'\0')
+#else
+#define WCHAR_MIN (-0x7fffffff - 1 + L'\0')
+#endif
+#endif
+
+/* This must match definition in  */
+#ifndef WCHAR_MAX
+#ifdef __WCHAR_MAX__
+#define WCHAR_MAX __WCHAR_MAX__
+#elif defined(__WCHAR_UNSIGNED__) || (L'\0' - 1 > 0)
+#define WCHAR_MAX (0xffffffffu + L'\0')
+#else
+#define WCHAR_MAX (0x7fffffff + L'\0')
+#endif
+#endif
+
+/* wint_t is unsigned int on almost all GCC targets.  */
+#ifdef __WINT_MAX__
+#define WINT_MAX __WINT_MAX__
+#else
+#define WINT_MAX (__STDINT_EXP(INT_MAX) * 2U + 1U)
+#endif
+#ifdef __WINT_MIN__
+#define WINT_MIN __WINT_MIN__
+#else
+#define WINT_MIN 0U
+#endif
+
+/** Macros for minimum-width integer constant expressions */
+#ifdef __INT8_C
+#define INT8_C(x) __INT8_C(x)
+#define UINT8_C(x) __UINT8_C(x)
+#else
+#define INT8_C(x)	x
+#if __STDINT_EXP(INT_MAX) > 0x7f
+#define UINT8_C(x)	x
+#else
+#define UINT8_C(x)	x##U
+#endif
+#endif
+
+#ifdef __INT16_C
+#define INT16_C(x) __INT16_C(x)
+#define UINT16_C(x) __UINT16_C(x)
+#else
+#define INT16_C(x)	x
+#if __STDINT_EXP(INT_MAX) > 0x7fff
+#define UINT16_C(x)	x
+#else
+#define UINT16_C(x)	x##U
+#endif
+#endif
+
+#ifdef __INT32_C
+#define INT32_C(x) __INT32_C(x)
+#define UINT32_C(x) __UINT32_C(x)
+#else
+#if __have_long32
+#define INT32_C(x)	x##L
+#define UINT32_C(x)	x##UL
+#else
+#define INT32_C(x)	x
+#define UINT32_C(x)	x##U
+#endif
+#endif
+
+#ifdef __INT64_C
+#define INT64_C(x) __INT64_C(x)
+#define UINT64_C(x) __UINT64_C(x)
+#else
+#if __int64_t_defined
+#if __have_long64
+#define INT64_C(x)	x##L
+#define UINT64_C(x)	x##UL
+#else
+#define INT64_C(x)	x##LL
+#define UINT64_C(x)	x##ULL
+#endif
+#endif
+#endif
+
+/** Macros for greatest-width integer constant expression */
+#ifdef __INTMAX_C
+#define INTMAX_C(x) __INTMAX_C(x)
+#define UINTMAX_C(x) __UINTMAX_C(x)
+#else
+#if __have_long64
+#define INTMAX_C(x)	x##L
+#define UINTMAX_C(x)	x##UL
+#else
+#define INTMAX_C(x)	x##LL
+#define UINTMAX_C(x)	x##ULL
+#endif
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _STDINT_H */
diff --git a/tools/sdk/include/newlib/stdio.h b/tools/sdk/include/newlib/stdio.h
new file mode 100644
index 00000000..e336ee6e
--- /dev/null
+++ b/tools/sdk/include/newlib/stdio.h
@@ -0,0 +1,727 @@
+/*
+ * Copyright (c) 1990 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the University of California, Berkeley.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *	@(#)stdio.h	5.3 (Berkeley) 3/15/86
+ */
+
+/*
+ * NB: to fit things in six character monocase externals, the
+ * stdio code uses the prefix `__s' for stdio objects, typically
+ * followed by a three-character attempt at a mnemonic.
+ */
+
+#ifndef _STDIO_H_
+#define	_STDIO_H_
+
+#include "_ansi.h"
+
+#define	_FSTDIO			/* ``function stdio'' */
+
+#define __need_size_t
+#define __need_NULL
+#include 
+#include 
+
+#define __need___va_list
+#include 
+
+/*
+ *  defines __FILE, _fpos_t.
+ * They must be defined there because struct _reent needs them (and we don't
+ * want reent.h to include this file.
+ */
+
+#include 
+#include 
+
+_BEGIN_STD_C
+
+typedef __FILE FILE;
+
+#ifdef __CYGWIN__
+typedef _fpos64_t fpos_t;
+#else
+typedef _fpos_t fpos_t;
+#ifdef __LARGE64_FILES
+typedef _fpos64_t fpos64_t;
+#endif
+#endif /* !__CYGWIN__ */
+
+#include 
+
+#define	__SLBF	0x0001		/* line buffered */
+#define	__SNBF	0x0002		/* unbuffered */
+#define	__SRD	0x0004		/* OK to read */
+#define	__SWR	0x0008		/* OK to write */
+	/* RD and WR are never simultaneously asserted */
+#define	__SRW	0x0010		/* open for reading & writing */
+#define	__SEOF	0x0020		/* found EOF */
+#define	__SERR	0x0040		/* found error */
+#define	__SMBF	0x0080		/* _buf is from malloc */
+#define	__SAPP	0x0100		/* fdopen()ed in append mode - so must  write to end */
+#define	__SSTR	0x0200		/* this is an sprintf/snprintf string */
+#define	__SOPT	0x0400		/* do fseek() optimisation */
+#define	__SNPT	0x0800		/* do not do fseek() optimisation */
+#define	__SOFF	0x1000		/* set iff _offset is in fact correct */
+#define	__SORD	0x2000		/* true => stream orientation (byte/wide) decided */
+#if defined(__CYGWIN__)
+#  define __SCLE  0x4000        /* convert line endings CR/LF <-> NL */
+#endif
+#define	__SL64	0x8000		/* is 64-bit offset large file */
+
+/* _flags2 flags */
+#define	__SNLK  0x0001		/* stdio functions do not lock streams themselves */
+#define	__SWID	0x2000		/* true => stream orientation wide, false => byte, only valid if __SORD in _flags is true */
+
+/*
+ * The following three definitions are for ANSI C, which took them
+ * from System V, which stupidly took internal interface macros and
+ * made them official arguments to setvbuf(), without renaming them.
+ * Hence, these ugly _IOxxx names are *supposed* to appear in user code.
+ *
+ * Although these happen to match their counterparts above, the
+ * implementation does not rely on that (so these could be renumbered).
+ */
+#define	_IOFBF	0		/* setvbuf should set fully buffered */
+#define	_IOLBF	1		/* setvbuf should set line buffered */
+#define	_IONBF	2		/* setvbuf should set unbuffered */
+
+#define	EOF	(-1)
+
+#ifdef __BUFSIZ__
+#define	BUFSIZ		__BUFSIZ__
+#else
+#define	BUFSIZ		1024
+#endif
+
+#ifdef __FOPEN_MAX__
+#define FOPEN_MAX	__FOPEN_MAX__
+#else
+#define	FOPEN_MAX	20
+#endif
+
+#ifdef __FILENAME_MAX__
+#define FILENAME_MAX    __FILENAME_MAX__
+#else
+#define	FILENAME_MAX	1024
+#endif
+
+#ifdef __L_tmpnam__
+#define L_tmpnam	__L_tmpnam__
+#else
+#define	L_tmpnam	FILENAME_MAX
+#endif
+
+#ifndef __STRICT_ANSI__
+#define P_tmpdir        "/tmp"
+#endif
+
+#ifndef SEEK_SET
+#define	SEEK_SET	0	/* set file offset to offset */
+#endif
+#ifndef SEEK_CUR
+#define	SEEK_CUR	1	/* set file offset to current plus offset */
+#endif
+#ifndef SEEK_END
+#define	SEEK_END	2	/* set file offset to EOF plus offset */
+#endif
+
+#define	TMP_MAX		26
+
+#define	stdin	(_REENT->_stdin)
+#define	stdout	(_REENT->_stdout)
+#define	stderr	(_REENT->_stderr)
+
+#define _stdin_r(x)	((x)->_stdin)
+#define _stdout_r(x)	((x)->_stdout)
+#define _stderr_r(x)	((x)->_stderr)
+
+/*
+ * Functions defined in ANSI C standard.
+ */
+
+#ifndef __VALIST
+#ifdef __GNUC__
+#define __VALIST __gnuc_va_list
+#else
+#define __VALIST char*
+#endif
+#endif
+
+FILE *	_EXFUN(tmpfile, (void));
+char *	_EXFUN(tmpnam, (char *));
+#if __BSD_VISIBLE || __XSI_VISIBLE || __POSIX_VISIBLE >= 200112
+char *	_EXFUN(tempnam, (const char *, const char *));
+#endif
+int	_EXFUN(fclose, (FILE *));
+int	_EXFUN(fflush, (FILE *));
+FILE *	_EXFUN(freopen, (const char *__restrict, const char *__restrict, FILE *__restrict));
+void	_EXFUN(setbuf, (FILE *__restrict, char *__restrict));
+int	_EXFUN(setvbuf, (FILE *__restrict, char *__restrict, int, size_t));
+int	_EXFUN(fprintf, (FILE *__restrict, const char *__restrict, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 2, 3))));
+int	_EXFUN(fscanf, (FILE *__restrict, const char *__restrict, ...)
+               _ATTRIBUTE ((__format__ (__scanf__, 2, 3))));
+int	_EXFUN(printf, (const char *__restrict, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 1, 2))));
+int	_EXFUN(scanf, (const char *__restrict, ...)
+               _ATTRIBUTE ((__format__ (__scanf__, 1, 2))));
+int	_EXFUN(sscanf, (const char *__restrict, const char *__restrict, ...)
+               _ATTRIBUTE ((__format__ (__scanf__, 2, 3))));
+int	_EXFUN(vfprintf, (FILE *__restrict, const char *__restrict, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 2, 0))));
+int	_EXFUN(vprintf, (const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 1, 0))));
+int	_EXFUN(vsprintf, (char *__restrict, const char *__restrict, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 2, 0))));
+int	_EXFUN(fgetc, (FILE *));
+char *  _EXFUN(fgets, (char *__restrict, int, FILE *__restrict));
+int	_EXFUN(fputc, (int, FILE *));
+int	_EXFUN(fputs, (const char *__restrict, FILE *__restrict));
+int	_EXFUN(getc, (FILE *));
+int	_EXFUN(getchar, (void));
+char *  _EXFUN(gets, (char *));
+int	_EXFUN(putc, (int, FILE *));
+int	_EXFUN(putchar, (int));
+int	_EXFUN(puts, (const char *));
+int	_EXFUN(ungetc, (int, FILE *));
+size_t	_EXFUN(fread, (_PTR __restrict, size_t _size, size_t _n, FILE *__restrict));
+size_t	_EXFUN(fwrite, (const _PTR __restrict , size_t _size, size_t _n, FILE *));
+#ifdef _COMPILING_NEWLIB
+int	_EXFUN(fgetpos, (FILE *, _fpos_t *));
+#else
+int	_EXFUN(fgetpos, (FILE *__restrict, fpos_t *__restrict));
+#endif
+int	_EXFUN(fseek, (FILE *, long, int));
+#ifdef _COMPILING_NEWLIB
+int	_EXFUN(fsetpos, (FILE *, const _fpos_t *));
+#else
+int	_EXFUN(fsetpos, (FILE *, const fpos_t *));
+#endif
+long	_EXFUN(ftell, ( FILE *));
+void	_EXFUN(rewind, (FILE *));
+void	_EXFUN(clearerr, (FILE *));
+int	_EXFUN(feof, (FILE *));
+int	_EXFUN(ferror, (FILE *));
+void    _EXFUN(perror, (const char *));
+#ifndef _REENT_ONLY
+FILE *	_EXFUN(fopen, (const char *__restrict _name, const char *__restrict _type));
+int	_EXFUN(sprintf, (char *__restrict, const char *__restrict, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 2, 3))));
+int	_EXFUN(remove, (const char *));
+int	_EXFUN(rename, (const char *, const char *));
+#ifdef _COMPILING_NEWLIB
+int	_EXFUN(_rename, (const char *, const char *));
+#endif
+#endif
+#if !defined(__STRICT_ANSI__) || defined(__USE_XOPEN2K)
+#ifdef _COMPILING_NEWLIB
+int	_EXFUN(fseeko, (FILE *, _off_t, int));
+_off_t	_EXFUN(ftello, ( FILE *));
+#else
+int	_EXFUN(fseeko, (FILE *, off_t, int));
+off_t	_EXFUN(ftello, ( FILE *));
+#endif
+#endif
+#if __GNU_VISIBLE
+int	_EXFUN(fcloseall, (_VOID));
+#endif
+#if !defined(__STRICT_ANSI__) || (__STDC_VERSION__ >= 199901L) || (__cplusplus >= 201103L)
+#ifndef _REENT_ONLY
+int	_EXFUN(asiprintf, (char **, const char *, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 2, 3))));
+char *	_EXFUN(asniprintf, (char *, size_t *, const char *, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 4))));
+char *	_EXFUN(asnprintf, (char *__restrict, size_t *__restrict, const char *__restrict, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 4))));
+int	_EXFUN(asprintf, (char **__restrict, const char *__restrict, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 2, 3))));
+#ifndef diprintf
+int	_EXFUN(diprintf, (int, const char *, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 2, 3))));
+#endif
+int	_EXFUN(fiprintf, (FILE *, const char *, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 2, 3))));
+int	_EXFUN(fiscanf, (FILE *, const char *, ...)
+               _ATTRIBUTE ((__format__ (__scanf__, 2, 3))));
+int	_EXFUN(iprintf, (const char *, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 1, 2))));
+int	_EXFUN(iscanf, (const char *, ...)
+               _ATTRIBUTE ((__format__ (__scanf__, 1, 2))));
+int	_EXFUN(siprintf, (char *, const char *, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 2, 3))));
+int	_EXFUN(siscanf, (const char *, const char *, ...)
+               _ATTRIBUTE ((__format__ (__scanf__, 2, 3))));
+int	_EXFUN(snprintf, (char *__restrict, size_t, const char *__restrict, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 4))));
+int	_EXFUN(sniprintf, (char *, size_t, const char *, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 4))));
+int	_EXFUN(vasiprintf, (char **, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 2, 0))));
+char *	_EXFUN(vasniprintf, (char *, size_t *, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 0))));
+char *	_EXFUN(vasnprintf, (char *, size_t *, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 0))));
+int	_EXFUN(vasprintf, (char **, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 2, 0))));
+int	_EXFUN(vdiprintf, (int, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 2, 0))));
+int	_EXFUN(vfiprintf, (FILE *, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 2, 0))));
+int	_EXFUN(vfiscanf, (FILE *, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__scanf__, 2, 0))));
+int	_EXFUN(vfscanf, (FILE *__restrict, const char *__restrict, __VALIST)
+               _ATTRIBUTE ((__format__ (__scanf__, 2, 0))));
+int	_EXFUN(viprintf, (const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 1, 0))));
+int	_EXFUN(viscanf, (const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__scanf__, 1, 0))));
+int	_EXFUN(vscanf, (const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__scanf__, 1, 0))));
+int	_EXFUN(vsiprintf, (char *, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 2, 0))));
+int	_EXFUN(vsiscanf, (const char *, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__scanf__, 2, 0))));
+int	_EXFUN(vsniprintf, (char *, size_t, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 0))));
+int	_EXFUN(vsnprintf, (char *__restrict, size_t, const char *__restrict, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 0))));
+int	_EXFUN(vsscanf, (const char *__restrict, const char *__restrict, __VALIST)
+               _ATTRIBUTE ((__format__ (__scanf__, 2, 0))));
+#endif /* !_REENT_ONLY */
+#endif /* !__STRICT_ANSI__ */
+
+/*
+ * Routines in POSIX 1003.1:2001.
+ */
+
+#ifndef __STRICT_ANSI__
+#ifndef _REENT_ONLY
+FILE *	_EXFUN(fdopen, (int, const char *));
+#endif
+int	_EXFUN(fileno, (FILE *));
+int	_EXFUN(getw, (FILE *));
+int	_EXFUN(pclose, (FILE *));
+FILE *  _EXFUN(popen, (const char *, const char *));
+int	_EXFUN(putw, (int, FILE *));
+void    _EXFUN(setbuffer, (FILE *, char *, int));
+int	_EXFUN(setlinebuf, (FILE *));
+int	_EXFUN(getc_unlocked, (FILE *));
+int	_EXFUN(getchar_unlocked, (void));
+void	_EXFUN(flockfile, (FILE *));
+int	_EXFUN(ftrylockfile, (FILE *));
+void	_EXFUN(funlockfile, (FILE *));
+int	_EXFUN(putc_unlocked, (int, FILE *));
+int	_EXFUN(putchar_unlocked, (int));
+#endif /* ! __STRICT_ANSI__ */
+
+/*
+ * Routines in POSIX 1003.1:200x.
+ */
+
+#ifndef __STRICT_ANSI__
+# ifndef _REENT_ONLY
+#  ifndef dprintf
+int	_EXFUN(dprintf, (int, const char *__restrict, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 2, 3))));
+#  endif
+FILE *	_EXFUN(fmemopen, (void *__restrict, size_t, const char *__restrict));
+/* getdelim - see __getdelim for now */
+/* getline - see __getline for now */
+FILE *	_EXFUN(open_memstream, (char **, size_t *));
+#if __BSD_VISIBLE || __POSIX_VISIBLE >= 200809
+int	_EXFUN(renameat, (int, const char *, int, const char *));
+#endif
+int	_EXFUN(vdprintf, (int, const char *__restrict, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 2, 0))));
+# endif
+#endif
+
+/*
+ * Recursive versions of the above.
+ */
+
+int	_EXFUN(_asiprintf_r, (struct _reent *, char **, const char *, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 4))));
+char *	_EXFUN(_asniprintf_r, (struct _reent *, char *, size_t *, const char *, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 4, 5))));
+char *	_EXFUN(_asnprintf_r, (struct _reent *, char *__restrict, size_t *__restrict, const char *__restrict, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 4, 5))));
+int	_EXFUN(_asprintf_r, (struct _reent *, char **__restrict, const char *__restrict, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 4))));
+int	_EXFUN(_diprintf_r, (struct _reent *, int, const char *, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 4))));
+int	_EXFUN(_dprintf_r, (struct _reent *, int, const char *__restrict, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 4))));
+int	_EXFUN(_fclose_r, (struct _reent *, FILE *));
+int	_EXFUN(_fcloseall_r, (struct _reent *));
+FILE *	_EXFUN(_fdopen_r, (struct _reent *, int, const char *));
+int	_EXFUN(_fflush_r, (struct _reent *, FILE *));
+int	_EXFUN(_fgetc_r, (struct _reent *, FILE *));
+int	_EXFUN(_fgetc_unlocked_r, (struct _reent *, FILE *));
+char *  _EXFUN(_fgets_r, (struct _reent *, char *__restrict, int, FILE *__restrict));
+char *  _EXFUN(_fgets_unlocked_r, (struct _reent *, char *__restrict, int, FILE *__restrict));
+#ifdef _COMPILING_NEWLIB
+int	_EXFUN(_fgetpos_r, (struct _reent *, FILE *__restrict, _fpos_t *__restrict));
+int	_EXFUN(_fsetpos_r, (struct _reent *, FILE *, const _fpos_t *));
+#else
+int	_EXFUN(_fgetpos_r, (struct _reent *, FILE *, fpos_t *));
+int	_EXFUN(_fsetpos_r, (struct _reent *, FILE *, const fpos_t *));
+#endif
+int	_EXFUN(_fiprintf_r, (struct _reent *, FILE *, const char *, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 4))));
+int	_EXFUN(_fiscanf_r, (struct _reent *, FILE *, const char *, ...)
+               _ATTRIBUTE ((__format__ (__scanf__, 3, 4))));
+FILE *	_EXFUN(_fmemopen_r, (struct _reent *, void *__restrict, size_t, const char *__restrict));
+FILE *	_EXFUN(_fopen_r, (struct _reent *, const char *__restrict, const char *__restrict));
+FILE *	_EXFUN(_freopen_r, (struct _reent *, const char *__restrict, const char *__restrict, FILE *__restrict));
+int	_EXFUN(_fprintf_r, (struct _reent *, FILE *__restrict, const char *__restrict, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 4))));
+int	_EXFUN(_fpurge_r, (struct _reent *, FILE *));
+int	_EXFUN(_fputc_r, (struct _reent *, int, FILE *));
+int	_EXFUN(_fputc_unlocked_r, (struct _reent *, int, FILE *));
+int	_EXFUN(_fputs_r, (struct _reent *, const char *__restrict, FILE *__restrict));
+int	_EXFUN(_fputs_unlocked_r, (struct _reent *, const char *__restrict, FILE *__restrict));
+size_t	_EXFUN(_fread_r, (struct _reent *, _PTR __restrict, size_t _size, size_t _n, FILE *__restrict));
+size_t	_EXFUN(_fread_unlocked_r, (struct _reent *, _PTR __restrict, size_t _size, size_t _n, FILE *__restrict));
+int	_EXFUN(_fscanf_r, (struct _reent *, FILE *__restrict, const char *__restrict, ...)
+               _ATTRIBUTE ((__format__ (__scanf__, 3, 4))));
+int	_EXFUN(_fseek_r, (struct _reent *, FILE *, long, int));
+int	_EXFUN(_fseeko_r,(struct _reent *, FILE *, _off_t, int));
+long	_EXFUN(_ftell_r, (struct _reent *, FILE *));
+_off_t	_EXFUN(_ftello_r,(struct _reent *, FILE *));
+void	_EXFUN(_rewind_r, (struct _reent *, FILE *));
+size_t	_EXFUN(_fwrite_r, (struct _reent *, const _PTR __restrict, size_t _size, size_t _n, FILE *__restrict));
+size_t	_EXFUN(_fwrite_unlocked_r, (struct _reent *, const _PTR __restrict, size_t _size, size_t _n, FILE *__restrict));
+int	_EXFUN(_getc_r, (struct _reent *, FILE *));
+int	_EXFUN(_getc_unlocked_r, (struct _reent *, FILE *));
+int	_EXFUN(_getchar_r, (struct _reent *));
+int	_EXFUN(_getchar_unlocked_r, (struct _reent *));
+char *	_EXFUN(_gets_r, (struct _reent *, char *));
+int	_EXFUN(_iprintf_r, (struct _reent *, const char *, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 2, 3))));
+int	_EXFUN(_iscanf_r, (struct _reent *, const char *, ...)
+               _ATTRIBUTE ((__format__ (__scanf__, 2, 3))));
+FILE *	_EXFUN(_open_memstream_r, (struct _reent *, char **, size_t *));
+void	_EXFUN(_perror_r, (struct _reent *, const char *));
+int	_EXFUN(_printf_r, (struct _reent *, const char *__restrict, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 2, 3))));
+int	_EXFUN(_putc_r, (struct _reent *, int, FILE *));
+int	_EXFUN(_putc_unlocked_r, (struct _reent *, int, FILE *));
+int	_EXFUN(_putchar_unlocked_r, (struct _reent *, int));
+int	_EXFUN(_putchar_r, (struct _reent *, int));
+int	_EXFUN(_puts_r, (struct _reent *, const char *));
+int	_EXFUN(_remove_r, (struct _reent *, const char *));
+int	_EXFUN(_rename_r, (struct _reent *,
+			   const char *_old, const char *_new));
+int	_EXFUN(_scanf_r, (struct _reent *, const char *__restrict, ...)
+               _ATTRIBUTE ((__format__ (__scanf__, 2, 3))));
+int	_EXFUN(_siprintf_r, (struct _reent *, char *, const char *, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 4))));
+int	_EXFUN(_siscanf_r, (struct _reent *, const char *, const char *, ...)
+               _ATTRIBUTE ((__format__ (__scanf__, 3, 4))));
+int	_EXFUN(_sniprintf_r, (struct _reent *, char *, size_t, const char *, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 4, 5))));
+int	_EXFUN(_snprintf_r, (struct _reent *, char *__restrict, size_t, const char *__restrict, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 4, 5))));
+int	_EXFUN(_sprintf_r, (struct _reent *, char *__restrict, const char *__restrict, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 4))));
+int	_EXFUN(_sscanf_r, (struct _reent *, const char *__restrict, const char *__restrict, ...)
+               _ATTRIBUTE ((__format__ (__scanf__, 3, 4))));
+char *	_EXFUN(_tempnam_r, (struct _reent *, const char *, const char *));
+FILE *	_EXFUN(_tmpfile_r, (struct _reent *));
+char *	_EXFUN(_tmpnam_r, (struct _reent *, char *));
+int	_EXFUN(_ungetc_r, (struct _reent *, int, FILE *));
+int	_EXFUN(_vasiprintf_r, (struct _reent *, char **, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 0))));
+char *	_EXFUN(_vasniprintf_r, (struct _reent*, char *, size_t *, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 4, 0))));
+char *	_EXFUN(_vasnprintf_r, (struct _reent*, char *, size_t *, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 4, 0))));
+int	_EXFUN(_vasprintf_r, (struct _reent *, char **, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 0))));
+int	_EXFUN(_vdiprintf_r, (struct _reent *, int, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 0))));
+int	_EXFUN(_vdprintf_r, (struct _reent *, int, const char *__restrict, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 0))));
+int	_EXFUN(_vfiprintf_r, (struct _reent *, FILE *, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 0))));
+int	_EXFUN(_vfiscanf_r, (struct _reent *, FILE *, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__scanf__, 3, 0))));
+int	_EXFUN(_vfprintf_r, (struct _reent *, FILE *__restrict, const char *__restrict, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 0))));
+int	_EXFUN(_vfscanf_r, (struct _reent *, FILE *__restrict, const char *__restrict, __VALIST)
+               _ATTRIBUTE ((__format__ (__scanf__, 3, 0))));
+int	_EXFUN(_viprintf_r, (struct _reent *, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 2, 0))));
+int	_EXFUN(_viscanf_r, (struct _reent *, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__scanf__, 2, 0))));
+int	_EXFUN(_vprintf_r, (struct _reent *, const char *__restrict, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 2, 0))));
+int	_EXFUN(_vscanf_r, (struct _reent *, const char *__restrict, __VALIST)
+               _ATTRIBUTE ((__format__ (__scanf__, 2, 0))));
+int	_EXFUN(_vsiprintf_r, (struct _reent *, char *, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 0))));
+int	_EXFUN(_vsiscanf_r, (struct _reent *, const char *, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__scanf__, 3, 0))));
+int	_EXFUN(_vsniprintf_r, (struct _reent *, char *, size_t, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 4, 0))));
+int	_EXFUN(_vsnprintf_r, (struct _reent *, char *__restrict, size_t, const char *__restrict, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 4, 0))));
+int	_EXFUN(_vsprintf_r, (struct _reent *, char *__restrict, const char *__restrict, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 0))));
+int	_EXFUN(_vsscanf_r, (struct _reent *, const char *__restrict, const char *__restrict, __VALIST)
+               _ATTRIBUTE ((__format__ (__scanf__, 3, 0))));
+
+/* Other extensions.  */
+
+int	_EXFUN(fpurge, (FILE *));
+ssize_t _EXFUN(__getdelim, (char **, size_t *, int, FILE *));
+ssize_t _EXFUN(__getline, (char **, size_t *, FILE *));
+
+#if __BSD_VISIBLE
+void	_EXFUN(clearerr_unlocked, (FILE *));
+int	_EXFUN(feof_unlocked, (FILE *));
+int	_EXFUN(ferror_unlocked, (FILE *));
+int	_EXFUN(fileno_unlocked, (FILE *));
+int	_EXFUN(fflush_unlocked, (FILE *));
+int	_EXFUN(fgetc_unlocked, (FILE *));
+int	_EXFUN(fputc_unlocked, (int, FILE *));
+size_t	_EXFUN(fread_unlocked, (_PTR __restrict, size_t _size, size_t _n, FILE *__restrict));
+size_t	_EXFUN(fwrite_unlocked, (const _PTR __restrict , size_t _size, size_t _n, FILE *));
+#endif
+
+#if __GNU_VISIBLE
+char *  _EXFUN(fgets_unlocked, (char *__restrict, int, FILE *__restrict));
+int	_EXFUN(fputs_unlocked, (const char *__restrict, FILE *__restrict));
+#endif
+
+#ifdef __LARGE64_FILES
+#if !defined(__CYGWIN__) || defined(_COMPILING_NEWLIB)
+FILE *	_EXFUN(fdopen64, (int, const char *));
+FILE *  _EXFUN(fopen64, (const char *, const char *));
+FILE *  _EXFUN(freopen64, (_CONST char *, _CONST char *, FILE *));
+_off64_t _EXFUN(ftello64, (FILE *));
+_off64_t _EXFUN(fseeko64, (FILE *, _off64_t, int));
+int     _EXFUN(fgetpos64, (FILE *, _fpos64_t *));
+int     _EXFUN(fsetpos64, (FILE *, const _fpos64_t *));
+FILE *  _EXFUN(tmpfile64, (void));
+
+FILE *	_EXFUN(_fdopen64_r, (struct _reent *, int, const char *));
+FILE *  _EXFUN(_fopen64_r, (struct _reent *,const char *, const char *));
+FILE *  _EXFUN(_freopen64_r, (struct _reent *, _CONST char *, _CONST char *, FILE *));
+_off64_t _EXFUN(_ftello64_r, (struct _reent *, FILE *));
+_off64_t _EXFUN(_fseeko64_r, (struct _reent *, FILE *, _off64_t, int));
+int     _EXFUN(_fgetpos64_r, (struct _reent *, FILE *, _fpos64_t *));
+int     _EXFUN(_fsetpos64_r, (struct _reent *, FILE *, const _fpos64_t *));
+FILE *  _EXFUN(_tmpfile64_r, (struct _reent *));
+#endif /* !__CYGWIN__ */
+#endif /* __LARGE64_FILES */
+
+/*
+ * Routines internal to the implementation.
+ */
+
+int	_EXFUN(__srget_r, (struct _reent *, FILE *));
+int	_EXFUN(__swbuf_r, (struct _reent *, int, FILE *));
+
+/*
+ * Stdio function-access interface.
+ */
+
+#ifndef __STRICT_ANSI__
+# ifdef __LARGE64_FILES
+FILE	*_EXFUN(funopen,(const _PTR __cookie,
+		int (*__readfn)(_PTR __c, char *__buf,
+				_READ_WRITE_BUFSIZE_TYPE __n),
+		int (*__writefn)(_PTR __c, const char *__buf,
+				 _READ_WRITE_BUFSIZE_TYPE __n),
+		_fpos64_t (*__seekfn)(_PTR __c, _fpos64_t __off, int __whence),
+		int (*__closefn)(_PTR __c)));
+FILE	*_EXFUN(_funopen_r,(struct _reent *, const _PTR __cookie,
+		int (*__readfn)(_PTR __c, char *__buf,
+				_READ_WRITE_BUFSIZE_TYPE __n),
+		int (*__writefn)(_PTR __c, const char *__buf,
+				 _READ_WRITE_BUFSIZE_TYPE __n),
+		_fpos64_t (*__seekfn)(_PTR __c, _fpos64_t __off, int __whence),
+		int (*__closefn)(_PTR __c)));
+# else
+FILE	*_EXFUN(funopen,(const _PTR __cookie,
+		int (*__readfn)(_PTR __cookie, char *__buf,
+				_READ_WRITE_BUFSIZE_TYPE __n),
+		int (*__writefn)(_PTR __cookie, const char *__buf,
+				 _READ_WRITE_BUFSIZE_TYPE __n),
+		fpos_t (*__seekfn)(_PTR __cookie, fpos_t __off, int __whence),
+		int (*__closefn)(_PTR __cookie)));
+FILE	*_EXFUN(_funopen_r,(struct _reent *, const _PTR __cookie,
+		int (*__readfn)(_PTR __cookie, char *__buf,
+				_READ_WRITE_BUFSIZE_TYPE __n),
+		int (*__writefn)(_PTR __cookie, const char *__buf,
+				 _READ_WRITE_BUFSIZE_TYPE __n),
+		fpos_t (*__seekfn)(_PTR __cookie, fpos_t __off, int __whence),
+		int (*__closefn)(_PTR __cookie)));
+# endif /* !__LARGE64_FILES */
+
+# define	fropen(__cookie, __fn) funopen(__cookie, __fn, (int (*)())0, \
+					       (fpos_t (*)())0, (int (*)())0)
+# define	fwopen(__cookie, __fn) funopen(__cookie, (int (*)())0, __fn, \
+					       (fpos_t (*)())0, (int (*)())0)
+
+typedef ssize_t cookie_read_function_t(void *__cookie, char *__buf, size_t __n);
+typedef ssize_t cookie_write_function_t(void *__cookie, const char *__buf,
+					size_t __n);
+# ifdef __LARGE64_FILES
+typedef int cookie_seek_function_t(void *__cookie, _off64_t *__off,
+				   int __whence);
+# else
+typedef int cookie_seek_function_t(void *__cookie, off_t *__off, int __whence);
+# endif /* !__LARGE64_FILES */
+typedef int cookie_close_function_t(void *__cookie);
+typedef struct
+{
+  /* These four struct member names are dictated by Linux; hopefully,
+     they don't conflict with any macros.  */
+  cookie_read_function_t  *read;
+  cookie_write_function_t *write;
+  cookie_seek_function_t  *seek;
+  cookie_close_function_t *close;
+} cookie_io_functions_t;
+FILE *_EXFUN(fopencookie,(void *__cookie,
+		const char *__mode, cookie_io_functions_t __functions));
+FILE *_EXFUN(_fopencookie_r,(struct _reent *, void *__cookie,
+		const char *__mode, cookie_io_functions_t __functions));
+#endif /* ! __STRICT_ANSI__ */
+
+#ifndef __CUSTOM_FILE_IO__
+/*
+ * The __sfoo macros are here so that we can 
+ * define function versions in the C library.
+ */
+#define       __sgetc_raw_r(__ptr, __f) (--(__f)->_r < 0 ? __srget_r(__ptr, __f) : (int)(*(__f)->_p++))
+
+#ifdef __SCLE
+/*  For a platform with CR/LF, additional logic is required by
+  __sgetc_r which would otherwise simply be a macro; therefore we
+  use an inlined function.  The function is only meant to be inlined
+  in place as used and the function body should never be emitted.  
+
+  There are two possible means to this end when compiling with GCC,
+  one when compiling with a standard C99 compiler, and for other
+  compilers we're just stuck.  At the moment, this issue only
+  affects the Cygwin target, so we'll most likely be using GCC. */
+
+_ELIDABLE_INLINE int __sgetc_r(struct _reent *__ptr, FILE *__p);
+
+_ELIDABLE_INLINE int __sgetc_r(struct _reent *__ptr, FILE *__p)
+  {
+    int __c = __sgetc_raw_r(__ptr, __p);
+    if ((__p->_flags & __SCLE) && (__c == '\r'))
+      {
+      int __c2 = __sgetc_raw_r(__ptr, __p);
+      if (__c2 == '\n')
+        __c = __c2;
+      else
+        ungetc(__c2, __p);
+      }
+    return __c;
+  }
+#else
+#define __sgetc_r(__ptr, __p) __sgetc_raw_r(__ptr, __p)
+#endif
+
+#ifdef _never /* __GNUC__ */
+/* If this inline is actually used, then systems using coff debugging
+   info get hopelessly confused.  21sept93 rich@cygnus.com.  */
+_ELIDABLE_INLINE int __sputc_r(struct _reent *_ptr, int _c, FILE *_p) {
+	if (--_p->_w >= 0 || (_p->_w >= _p->_lbfsize && (char)_c != '\n'))
+		return (*_p->_p++ = _c);
+	else
+		return (__swbuf_r(_ptr, _c, _p));
+}
+#else
+/*
+ * This has been tuned to generate reasonable code on the vax using pcc
+ */
+#define       __sputc_raw_r(__ptr, __c, __p) \
+	(--(__p)->_w < 0 ? \
+		(__p)->_w >= (__p)->_lbfsize ? \
+			(*(__p)->_p = (__c)), *(__p)->_p != '\n' ? \
+				(int)*(__p)->_p++ : \
+				__swbuf_r(__ptr, '\n', __p) : \
+			__swbuf_r(__ptr, (int)(__c), __p) : \
+		(*(__p)->_p = (__c), (int)*(__p)->_p++))
+#ifdef __SCLE
+#define __sputc_r(__ptr, __c, __p) \
+        ((((__p)->_flags & __SCLE) && ((__c) == '\n')) \
+          ? __sputc_raw_r(__ptr, '\r', (__p)) : 0 , \
+        __sputc_raw_r((__ptr), (__c), (__p)))
+#else
+#define __sputc_r(__ptr, __c, __p) __sputc_raw_r(__ptr, __c, __p)
+#endif
+#endif
+
+#define	__sfeof(p)	((int)(((p)->_flags & __SEOF) != 0))
+#define	__sferror(p)	((int)(((p)->_flags & __SERR) != 0))
+#define	__sclearerr(p)	((void)((p)->_flags &= ~(__SERR|__SEOF)))
+#define	__sfileno(p)	((p)->_file)
+
+#ifndef _REENT_SMALL
+#define	feof(p)		__sfeof(p)
+#define	ferror(p)	__sferror(p)
+#define	clearerr(p)	__sclearerr(p)
+
+#if __BSD_VISIBLE
+#define	feof_unlocked(p)	__sfeof(p)
+#define	ferror_unlocked(p)	__sferror(p)
+#define	clearerr_unlocked(p)	__sclearerr(p)
+#endif /* __BSD_VISIBLE */
+#endif /* _REENT_SMALL */
+
+#if 0 /*ndef __STRICT_ANSI__ - FIXME: must initialize stdio first, use fn */
+#define	fileno(p)	__sfileno(p)
+#endif
+
+#ifndef __CYGWIN__
+#ifndef lint
+#define	getc(fp)	__sgetc_r(_REENT, fp)
+#define putc(x, fp)	__sputc_r(_REENT, x, fp)
+#endif /* lint */
+#endif /* __CYGWIN__ */
+
+#ifndef __STRICT_ANSI__
+/* fast always-buffered version, true iff error */
+#define	fast_putc(x,p) (--(p)->_w < 0 ? \
+	__swbuf_r(_REENT, (int)(x), p) == EOF : (*(p)->_p = (x), (p)->_p++, 0))
+
+#define	L_cuserid	9		/* posix says it goes in stdio.h :( */
+#ifdef __CYGWIN__
+#define L_ctermid       16
+#endif
+#endif
+
+#endif /* !__CUSTOM_FILE_IO__ */
+
+#define	getchar()	getc(stdin)
+#define	putchar(x)	putc(x, stdout)
+
+#ifndef __STRICT_ANSI__
+#define	getchar_unlocked()	getc_unlocked(stdin)
+#define	putchar_unlocked(x)	putc_unlocked(x, stdout)
+#endif
+
+_END_STD_C
+
+#endif /* _STDIO_H_ */
diff --git a/tools/sdk/include/newlib/stdio_ext.h b/tools/sdk/include/newlib/stdio_ext.h
new file mode 100644
index 00000000..029ab025
--- /dev/null
+++ b/tools/sdk/include/newlib/stdio_ext.h
@@ -0,0 +1,79 @@
+/*
+ * stdio_ext.h
+ *
+ * Definitions for I/O internal operations, originally from Solaris.
+ */
+
+#ifndef _STDIO_EXT_H_
+#define _STDIO_EXT_H_
+
+#ifdef __rtems__
+#error " not supported"
+#endif
+
+#include 
+
+#define	FSETLOCKING_QUERY	0
+#define	FSETLOCKING_INTERNAL	1
+#define	FSETLOCKING_BYCALLER	2
+
+_BEGIN_STD_C
+
+void	 _EXFUN(__fpurge,(FILE *));
+int	 _EXFUN(__fsetlocking,(FILE *, int));
+
+/* TODO:
+
+   void _flushlbf (void);
+*/
+
+#ifdef  __GNUC__
+
+_ELIDABLE_INLINE size_t
+__fbufsize (FILE *__fp) { return (size_t) __fp->_bf._size; }
+
+_ELIDABLE_INLINE int
+__freading (FILE *__fp) { return (__fp->_flags & __SRD) != 0; }
+
+_ELIDABLE_INLINE int
+__fwriting (FILE *__fp) { return (__fp->_flags & __SWR) != 0; }
+
+_ELIDABLE_INLINE int
+__freadable (FILE *__fp) { return (__fp->_flags & (__SRD | __SRW)) != 0; }
+
+_ELIDABLE_INLINE int
+__fwritable (FILE *__fp) { return (__fp->_flags & (__SWR | __SRW)) != 0; }
+
+_ELIDABLE_INLINE int
+__flbf (FILE *__fp) { return (__fp->_flags & __SLBF) != 0; }
+
+_ELIDABLE_INLINE size_t
+__fpending (FILE *__fp) { return __fp->_p - __fp->_bf._base; }
+
+#else
+
+size_t	 _EXFUN(__fbufsize,(FILE *));
+int	 _EXFUN(__freading,(FILE *));
+int	 _EXFUN(__fwriting,(FILE *));
+int	 _EXFUN(__freadable,(FILE *));
+int	 _EXFUN(__fwritable,(FILE *));
+int	 _EXFUN(__flbf,(FILE *));
+size_t	 _EXFUN(__fpending,(FILE *));
+
+#ifndef __cplusplus
+
+#define __fbufsize(__fp) ((size_t) (__fp)->_bf._size)
+#define __freading(__fp) (((__fp)->_flags & __SRD) != 0)
+#define __fwriting(__fp) (((__fp)->_flags & __SWR) != 0)
+#define __freadable(__fp) (((__fp)->_flags & (__SRD | __SRW)) != 0)
+#define __fwritable(__fp) (((__fp)->_flags & (__SWR | __SRW)) != 0)
+#define __flbf(__fp) (((__fp)->_flags & __SLBF) != 0)
+#define __fpending(__fp) ((size_t) ((__fp)->_p - (__fp)->_bf._base))
+
+#endif /* __cplusplus */
+
+#endif /* __GNUC__ */
+
+_END_STD_C
+
+#endif /* _STDIO_EXT_H_ */
diff --git a/tools/sdk/include/newlib/stdlib.h b/tools/sdk/include/newlib/stdlib.h
new file mode 100644
index 00000000..254ddd71
--- /dev/null
+++ b/tools/sdk/include/newlib/stdlib.h
@@ -0,0 +1,297 @@
+/*
+ * stdlib.h
+ *
+ * Definitions for common types, variables, and functions.
+ */
+
+#ifndef _STDLIB_H_
+#define _STDLIB_H_
+
+#include 
+#include "_ansi.h"
+
+#define __need_size_t
+#define __need_wchar_t
+#define __need_NULL
+#include 
+
+#include 
+#include 
+#include 
+#ifndef __STRICT_ANSI__
+#include 
+#endif
+
+#ifdef __CYGWIN__
+#include 
+#endif
+
+_BEGIN_STD_C
+
+typedef struct 
+{
+  int quot; /* quotient */
+  int rem; /* remainder */
+} div_t;
+
+typedef struct 
+{
+  long quot; /* quotient */
+  long rem; /* remainder */
+} ldiv_t;
+
+#if !defined(__STRICT_ANSI__) || \
+  (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) || \
+  (defined(__cplusplus) && __cplusplus >= 201103L)
+typedef struct
+{
+  long long int quot; /* quotient */
+  long long int rem; /* remainder */
+} lldiv_t;
+#endif
+
+#ifndef __compar_fn_t_defined
+#define __compar_fn_t_defined
+typedef int (*__compar_fn_t) (const _PTR, const _PTR);
+#endif
+
+#ifndef NULL
+#define NULL 0
+#endif
+
+#define EXIT_FAILURE 1
+#define EXIT_SUCCESS 0
+
+#define RAND_MAX __RAND_MAX
+
+int	_EXFUN(__locale_mb_cur_max,(_VOID));
+
+#define MB_CUR_MAX __locale_mb_cur_max()
+
+_VOID	_EXFUN(abort,(_VOID) _ATTRIBUTE ((__noreturn__)));
+int	_EXFUN(abs,(int));
+int	_EXFUN(atexit,(_VOID (*__func)(_VOID)));
+double	_EXFUN(atof,(const char *__nptr));
+#ifndef __STRICT_ANSI__
+float	_EXFUN(atoff,(const char *__nptr));
+#endif
+int	_EXFUN(atoi,(const char *__nptr));
+int	_EXFUN(_atoi_r,(struct _reent *, const char *__nptr));
+long	_EXFUN(atol,(const char *__nptr));
+long	_EXFUN(_atol_r,(struct _reent *, const char *__nptr));
+_PTR	_EXFUN(bsearch,(const _PTR __key,
+		       const _PTR __base,
+		       size_t __nmemb,
+		       size_t __size,
+		       __compar_fn_t _compar));
+_PTR	_EXFUN_NOTHROW(calloc,(size_t __nmemb, size_t __size));
+div_t	_EXFUN(div,(int __numer, int __denom));
+_VOID	_EXFUN(exit,(int __status) _ATTRIBUTE ((__noreturn__)));
+_VOID	_EXFUN_NOTHROW(free,(_PTR));
+char *  _EXFUN(getenv,(const char *__string));
+char *	_EXFUN(_getenv_r,(struct _reent *, const char *__string));
+char *	_EXFUN(_findenv,(_CONST char *, int *));
+char *	_EXFUN(_findenv_r,(struct _reent *, _CONST char *, int *));
+#ifndef __STRICT_ANSI__
+extern char *suboptarg;			/* getsubopt(3) external variable */
+int	_EXFUN(getsubopt,(char **, char * const *, char **));
+#endif
+long	_EXFUN(labs,(long));
+ldiv_t	_EXFUN(ldiv,(long __numer, long __denom));
+_PTR	_EXFUN_NOTHROW(malloc,(size_t __size));
+int	_EXFUN(mblen,(const char *, size_t));
+int	_EXFUN(_mblen_r,(struct _reent *, const char *, size_t, _mbstate_t *));
+int	_EXFUN(mbtowc,(wchar_t *__restrict, const char *__restrict, size_t));
+int	_EXFUN(_mbtowc_r,(struct _reent *, wchar_t *__restrict, const char *__restrict, size_t, _mbstate_t *));
+int	_EXFUN(wctomb,(char *, wchar_t));
+int	_EXFUN(_wctomb_r,(struct _reent *, char *, wchar_t, _mbstate_t *));
+size_t	_EXFUN(mbstowcs,(wchar_t *__restrict, const char *__restrict, size_t));
+size_t	_EXFUN(_mbstowcs_r,(struct _reent *, wchar_t *__restrict, const char *__restrict, size_t, _mbstate_t *));
+size_t	_EXFUN(wcstombs,(char *__restrict, const wchar_t *__restrict, size_t));
+size_t	_EXFUN(_wcstombs_r,(struct _reent *, char *__restrict, const wchar_t *__restrict, size_t, _mbstate_t *));
+#ifndef __STRICT_ANSI__
+#ifndef _REENT_ONLY
+char *	_EXFUN(mkdtemp,(char *));
+int	_EXFUN(mkostemp,(char *, int));
+int	_EXFUN(mkostemps,(char *, int, int));
+int	_EXFUN(mkstemp,(char *));
+int	_EXFUN(mkstemps,(char *, int));
+#if (__GNUC__ < 4) || defined(__XTENSA__)
+char *	_EXFUN(mktemp,(char *));
+#else
+char *	_EXFUN(mktemp,(char *) _ATTRIBUTE ((__warning__ ("the use of `mktemp' is dangerous; use `mkstemp' instead"))));
+#endif
+#endif
+char *	_EXFUN(_mkdtemp_r, (struct _reent *, char *));
+int	_EXFUN(_mkostemp_r, (struct _reent *, char *, int));
+int	_EXFUN(_mkostemps_r, (struct _reent *, char *, int, int));
+int	_EXFUN(_mkstemp_r, (struct _reent *, char *));
+int	_EXFUN(_mkstemps_r, (struct _reent *, char *, int));
+#if (__GNUC__ < 4) || defined(__XTENSA__)
+char *	_EXFUN(_mktemp_r, (struct _reent *, char *)); 
+#else
+char *	_EXFUN(_mktemp_r, (struct _reent *, char *) _ATTRIBUTE ((__warning__ ("the use of `mktemp' is dangerous; use `mkstemp' instead"))));
+#endif
+#endif
+_VOID	_EXFUN(qsort,(_PTR __base, size_t __nmemb, size_t __size, __compar_fn_t _compar));
+int	_EXFUN(rand,(_VOID));
+_PTR	_EXFUN_NOTHROW(realloc,(_PTR __r, size_t __size));
+#ifndef __STRICT_ANSI__
+_PTR	_EXFUN(reallocf,(_PTR __r, size_t __size));
+char *	_EXFUN(realpath, (const char *__restrict path, char *__restrict resolved_path));
+#endif
+_VOID	_EXFUN(srand,(unsigned __seed));
+double	_EXFUN(strtod,(const char *__restrict __n, char **__restrict __end_PTR));
+double	_EXFUN(_strtod_r,(struct _reent *,const char *__restrict __n, char **__restrict __end_PTR));
+#if !defined(__STRICT_ANSI__) || \
+  (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) || \
+  (defined(__cplusplus) && __cplusplus >= 201103L)
+float	_EXFUN(strtof,(const char *__restrict __n, char **__restrict __end_PTR));
+#endif
+#ifndef __STRICT_ANSI__
+/* the following strtodf interface is deprecated...use strtof instead */
+# ifndef strtodf 
+#  define strtodf strtof
+# endif
+#endif
+long	_EXFUN(strtol,(const char *__restrict __n, char **__restrict __end_PTR, int __base));
+long	_EXFUN(_strtol_r,(struct _reent *,const char *__restrict __n, char **__restrict __end_PTR, int __base));
+unsigned long _EXFUN(strtoul,(const char *__restrict __n, char **__restrict __end_PTR, int __base));
+unsigned long _EXFUN(_strtoul_r,(struct _reent *,const char *__restrict __n, char **__restrict __end_PTR, int __base));
+
+int	_EXFUN(system,(const char *__string));
+
+#ifndef __STRICT_ANSI__
+long    _EXFUN(a64l,(const char *__input));
+char *  _EXFUN(l64a,(long __input));
+char *  _EXFUN(_l64a_r,(struct _reent *,long __input));
+int	_EXFUN(on_exit,(_VOID (*__func)(int, _PTR),_PTR __arg));
+#endif /* ! __STRICT_ANSI__ */
+#if !defined(__STRICT_ANSI__) || \
+  (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) || \
+  (defined(__cplusplus) && __cplusplus >= 201103L)
+_VOID	_EXFUN(_Exit,(int __status) _ATTRIBUTE ((__noreturn__)));
+#endif
+#ifndef __STRICT_ANSI__
+int	_EXFUN(putenv,(char *__string));
+int	_EXFUN(_putenv_r,(struct _reent *, char *__string));
+_PTR	_EXFUN(_reallocf_r,(struct _reent *, _PTR, size_t));
+int	_EXFUN(setenv,(const char *__string, const char *__value, int __overwrite));
+int	_EXFUN(_setenv_r,(struct _reent *, const char *__string, const char *__value, int __overwrite));
+
+char *	_EXFUN(gcvt,(double,int,char *));
+char *	_EXFUN(gcvtf,(float,int,char *));
+char *	_EXFUN(fcvt,(double,int,int *,int *));
+char *	_EXFUN(fcvtf,(float,int,int *,int *));
+char *	_EXFUN(ecvt,(double,int,int *,int *));
+char *	_EXFUN(ecvtbuf,(double, int, int*, int*, char *));
+char *	_EXFUN(fcvtbuf,(double, int, int*, int*, char *));
+char *	_EXFUN(ecvtf,(float,int,int *,int *));
+char *	_EXFUN(dtoa,(double, int, int, int *, int*, char**));
+#endif
+char *	_EXFUN(__itoa,(int, char *, int));
+char *	_EXFUN(__utoa,(unsigned, char *, int));
+#ifndef __STRICT_ANSI__
+char *	_EXFUN(itoa,(int, char *, int));
+char *	_EXFUN(utoa,(unsigned, char *, int));
+int	_EXFUN(rand_r,(unsigned *__seed));
+
+double _EXFUN(drand48,(_VOID));
+double _EXFUN(_drand48_r,(struct _reent *));
+double _EXFUN(erand48,(unsigned short [3]));
+double _EXFUN(_erand48_r,(struct _reent *, unsigned short [3]));
+long   _EXFUN(jrand48,(unsigned short [3]));
+long   _EXFUN(_jrand48_r,(struct _reent *, unsigned short [3]));
+_VOID  _EXFUN(lcong48,(unsigned short [7]));
+_VOID  _EXFUN(_lcong48_r,(struct _reent *, unsigned short [7]));
+long   _EXFUN(lrand48,(_VOID));
+long   _EXFUN(_lrand48_r,(struct _reent *));
+long   _EXFUN(mrand48,(_VOID));
+long   _EXFUN(_mrand48_r,(struct _reent *));
+long   _EXFUN(nrand48,(unsigned short [3]));
+long   _EXFUN(_nrand48_r,(struct _reent *, unsigned short [3]));
+unsigned short *
+       _EXFUN(seed48,(unsigned short [3]));
+unsigned short *
+       _EXFUN(_seed48_r,(struct _reent *, unsigned short [3]));
+_VOID  _EXFUN(srand48,(long));
+_VOID  _EXFUN(_srand48_r,(struct _reent *, long));
+#endif /* ! __STRICT_ANSI__ */
+#if !defined(__STRICT_ANSI__) || \
+  (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) || \
+  (defined(__cplusplus) && __cplusplus >= 201103L)
+long long _EXFUN(atoll,(const char *__nptr));
+#endif
+#ifndef __STRICT_ANSI__
+long long _EXFUN(_atoll_r,(struct _reent *, const char *__nptr));
+#endif /* ! __STRICT_ANSI__ */
+#if !defined(__STRICT_ANSI__) || \
+  (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) || \
+  (defined(__cplusplus) && __cplusplus >= 201103L)
+long long _EXFUN(llabs,(long long));
+lldiv_t	_EXFUN(lldiv,(long long __numer, long long __denom));
+long long _EXFUN(strtoll,(const char *__restrict __n, char **__restrict __end_PTR, int __base));
+#endif
+#ifndef __STRICT_ANSI__
+long long _EXFUN(_strtoll_r,(struct _reent *, const char *__restrict __n, char **__restrict __end_PTR, int __base));
+#endif /* ! __STRICT_ANSI__ */
+#if !defined(__STRICT_ANSI__) || \
+  (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) || \
+  (defined(__cplusplus) && __cplusplus >= 201103L)
+unsigned long long _EXFUN(strtoull,(const char *__restrict __n, char **__restrict __end_PTR, int __base));
+#endif
+#ifndef __STRICT_ANSI__
+unsigned long long _EXFUN(_strtoull_r,(struct _reent *, const char *__restrict __n, char **__restrict __end_PTR, int __base));
+
+#ifndef __CYGWIN__
+_VOID	_EXFUN(cfree,(_PTR));
+int	_EXFUN(unsetenv,(const char *__string));
+int	_EXFUN(_unsetenv_r,(struct _reent *, const char *__string));
+#endif
+
+#ifdef __rtems__
+int _EXFUN(posix_memalign,(void **, size_t, size_t));
+#endif
+
+#endif /* ! __STRICT_ANSI__ */
+
+char *	_EXFUN(_dtoa_r,(struct _reent *, double, int, int, int *, int*, char**));
+#ifndef __CYGWIN__
+_PTR	_EXFUN_NOTHROW(_malloc_r,(struct _reent *, size_t));
+_PTR	_EXFUN_NOTHROW(_calloc_r,(struct _reent *, size_t, size_t));
+_VOID	_EXFUN_NOTHROW(_free_r,(struct _reent *, _PTR));
+_PTR	_EXFUN_NOTHROW(_realloc_r,(struct _reent *, _PTR, size_t));
+_VOID	_EXFUN(_mstats_r,(struct _reent *, char *));
+#endif
+int	_EXFUN(_system_r,(struct _reent *, const char *));
+
+_VOID	_EXFUN(__eprintf,(const char *, const char *, unsigned int, const char *));
+
+/* There are two common qsort_r variants.  If you request
+   _BSD_SOURCE, you get the BSD version; otherwise you get the GNU
+   version.  We want that #undef qsort_r will still let you
+   invoke the underlying function, but that requires gcc support. */
+#ifdef _BSD_SOURCE
+# ifdef __GNUC__
+_VOID	_EXFUN(qsort_r,(_PTR __base, size_t __nmemb, size_t __size, _PTR __thunk, int (*_compar)(_PTR, const _PTR, const _PTR)))
+             __asm__ (__ASMNAME ("__bsd_qsort_r"));
+# else
+_VOID	_EXFUN(__bsd_qsort_r,(_PTR __base, size_t __nmemb, size_t __size, _PTR __thunk, int (*_compar)(_PTR, const _PTR, const _PTR)));
+#  define qsort_r __bsd_qsort_r
+# endif
+#elif __GNU_VISIBLE
+_VOID	_EXFUN(qsort_r,(_PTR __base, size_t __nmemb, size_t __size, int (*_compar)(const _PTR, const _PTR, _PTR), _PTR __thunk));
+#endif
+
+/* On platforms where long double equals double.  */
+#ifdef _HAVE_LONG_DOUBLE
+#if !defined(__STRICT_ANSI__) || \
+  (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) || \
+  (defined(__cplusplus) && __cplusplus >= 201103L)
+extern long double strtold (const char *__restrict, char **__restrict);
+#endif
+#endif /* _HAVE_LONG_DOUBLE */
+
+_END_STD_C
+
+#endif /* _STDLIB_H_ */
diff --git a/tools/sdk/include/newlib/string.h b/tools/sdk/include/newlib/string.h
new file mode 100644
index 00000000..af5c9da4
--- /dev/null
+++ b/tools/sdk/include/newlib/string.h
@@ -0,0 +1,167 @@
+/*
+ * string.h
+ *
+ * Definitions for memory and string functions.
+ */
+
+#ifndef _STRING_H_
+#define	_STRING_H_
+
+#include "_ansi.h"
+#include 
+#include 
+#include 
+
+#define __need_size_t
+#define __need_NULL
+#include 
+
+_BEGIN_STD_C
+
+_PTR 	 _EXFUN(memchr,(const _PTR, int, size_t));
+int 	 _EXFUN(memcmp,(const _PTR, const _PTR, size_t));
+_PTR 	 _EXFUN(memcpy,(_PTR __restrict, const _PTR __restrict, size_t));
+_PTR	 _EXFUN(memmove,(_PTR, const _PTR, size_t));
+_PTR	 _EXFUN(memset,(_PTR, int, size_t));
+char 	*_EXFUN(strcat,(char *__restrict, const char *__restrict));
+char 	*_EXFUN(strchr,(const char *, int));
+int	 _EXFUN(strcmp,(const char *, const char *));
+int	 _EXFUN(strcoll,(const char *, const char *));
+char 	*_EXFUN(strcpy,(char *__restrict, const char *__restrict));
+size_t	 _EXFUN(strcspn,(const char *, const char *));
+char 	*_EXFUN(strerror,(int));
+size_t	 _EXFUN(strlen,(const char *));
+char 	*_EXFUN(strncat,(char *__restrict, const char *__restrict, size_t));
+int	 _EXFUN(strncmp,(const char *, const char *, size_t));
+char 	*_EXFUN(strncpy,(char *__restrict, const char *__restrict, size_t));
+char 	*_EXFUN(strpbrk,(const char *, const char *));
+char 	*_EXFUN(strrchr,(const char *, int));
+size_t	 _EXFUN(strspn,(const char *, const char *));
+char 	*_EXFUN(strstr,(const char *, const char *));
+#ifndef _REENT_ONLY
+char 	*_EXFUN(strtok,(char *__restrict, const char *__restrict));
+#endif
+size_t	 _EXFUN(strxfrm,(char *__restrict, const char *__restrict, size_t));
+
+#if __POSIX_VISIBLE
+char 	*_EXFUN(strtok_r,(char *__restrict, const char *__restrict, char **__restrict));
+#endif
+#if __BSD_VISIBLE
+int	 _EXFUN(bcmp,(const void *, const void *, size_t));
+void	 _EXFUN(bcopy,(const void *, void *, size_t));
+void	 _EXFUN(bzero,(void *, size_t));
+int	 _EXFUN(ffs,(int));
+char 	*_EXFUN(index,(const char *, int));
+#endif
+#if __BSD_VISIBLE || __XSI_VISIBLE
+_PTR	 _EXFUN(memccpy,(_PTR __restrict, const _PTR __restrict, int, size_t));
+#endif
+#if __GNU_VISIBLE
+_PTR	 _EXFUN(mempcpy,(_PTR, const _PTR, size_t));
+_PTR	 _EXFUN(memmem, (const _PTR, size_t, const _PTR, size_t));
+#endif
+_PTR 	 _EXFUN(memrchr,(const _PTR, int, size_t));
+#if __GNU_VISIBLE
+_PTR 	 _EXFUN(rawmemchr,(const _PTR, int));
+#endif
+#if __BSD_VISIBLE
+char 	*_EXFUN(rindex,(const char *, int));
+#endif
+char 	*_EXFUN(stpcpy,(char *__restrict, const char *__restrict));
+char 	*_EXFUN(stpncpy,(char *__restrict, const char *__restrict, size_t));
+#if __BSD_VISIBLE || __POSIX_VISIBLE
+int	 _EXFUN(strcasecmp,(const char *, const char *));
+#endif
+#if __GNU_VISIBLE
+char	*_EXFUN(strcasestr,(const char *, const char *));
+char 	*_EXFUN(strchrnul,(const char *, int));
+#endif
+#if __XSI_VISIBLE >= 500
+char 	*_EXFUN(strdup,(const char *));
+#endif
+#ifndef __STRICT_ANSI__
+char 	*_EXFUN(_strdup_r,(struct _reent *, const char *));
+#endif
+#if __XSI_VISIBLE >= 700
+char 	*_EXFUN(strndup,(const char *, size_t));
+#endif
+
+#ifndef __STRICT_ANSI__
+char 	*_EXFUN(_strndup_r,(struct _reent *, const char *, size_t));
+#endif
+
+#if __GNU_VISIBLE
+int	 _EXFUN(ffsl,(long));
+int	 _EXFUN(ffsll, (long long));
+#endif
+
+/* There are two common strerror_r variants.  If you request
+   _GNU_SOURCE, you get the GNU version; otherwise you get the POSIX
+   version.  POSIX requires that #undef strerror_r will still let you
+   invoke the underlying function, but that requires gcc support.  */
+#if __GNU_VISIBLE
+char	*_EXFUN(strerror_r,(int, char *, size_t));
+#else
+# ifdef __GNUC__
+int	_EXFUN(strerror_r,(int, char *, size_t))
+             __asm__ (__ASMNAME ("__xpg_strerror_r"));
+# else
+int	_EXFUN(__xpg_strerror_r,(int, char *, size_t));
+#  define strerror_r __xpg_strerror_r
+# endif
+#endif
+
+/* Reentrant version of strerror.  */
+char *	_EXFUN(_strerror_r, (struct _reent *, int, int, int *));
+
+#if __BSD_VISIBLE
+size_t	_EXFUN(strlcat,(char *, const char *, size_t));
+size_t	_EXFUN(strlcpy,(char *, const char *, size_t));
+#endif
+#if __BSD_VISIBLE || __POSIX_VISIBLE
+int	_EXFUN(strncasecmp,(const char *, const char *, size_t));
+#endif
+#if !defined(__STRICT_ANSI__) || __POSIX_VISIBLE >= 200809 || \
+    __XSI_VISIBLE >= 700
+size_t	 _EXFUN(strnlen,(const char *, size_t));
+#endif
+#if __BSD_VISIBLE
+char 	*_EXFUN(strsep,(char **, const char *));
+#endif
+
+/*
+ * The origin of these is unknown to me so I am conditionalizing them
+ * on __STRICT_ANSI__. Finetuning this is definitely needed. --joel
+ */
+#if !defined(__STRICT_ANSI__)
+char	*_EXFUN(strlwr,(char *));
+char	*_EXFUN(strupr,(char *));
+#endif
+
+#ifndef DEFS_H	/* Kludge to work around problem compiling in gdb */
+char	*_EXFUN(strsignal, (int __signo));
+#endif
+
+#ifdef __CYGWIN__
+int	_EXFUN(strtosigno, (const char *__name));
+#endif
+
+#if defined _GNU_SOURCE && defined __GNUC__
+#define strdupa(__s) \
+	(__extension__ ({const char *__in = (__s); \
+			 size_t __len = strlen (__in) + 1; \
+			 char * __out = (char *) __builtin_alloca (__len); \
+			 (char *) memcpy (__out, __in, __len);}))
+#define strndupa(__s, __n) \
+	(__extension__ ({const char *__in = (__s); \
+			 size_t __len = strnlen (__in, (__n)) + 1; \
+			 char *__out = (char *) __builtin_alloca (__len); \
+			 __out[__len-1] = '\0'; \
+			 (char *) memcpy (__out, __in, __len-1);}))
+#endif /* _GNU_SOURCE && __GNUC__ */
+
+#include 
+
+_END_STD_C
+
+#endif /* _STRING_H_ */
diff --git a/tools/sdk/include/newlib/strings.h b/tools/sdk/include/newlib/strings.h
new file mode 100644
index 00000000..131d81d2
--- /dev/null
+++ b/tools/sdk/include/newlib/strings.h
@@ -0,0 +1,35 @@
+/*
+ * strings.h
+ *
+ * Definitions for string operations.
+ */
+
+#ifndef _STRINGS_H_
+#define _STRINGS_H_
+
+#include "_ansi.h"
+#include 
+
+#include  /* for size_t */
+
+_BEGIN_STD_C
+
+#if !defined __STRICT_ANSI__ && _POSIX_VERSION < 200809L
+/* 
+ * Marked LEGACY in Open Group Base Specifications Issue 6/IEEE Std 1003.1-2004
+ * Removed from Open Group Base Specifications Issue 7/IEEE Std 1003.1-2008
+ */
+int	 _EXFUN(bcmp,(const void *, const void *, size_t));
+void	 _EXFUN(bcopy,(const void *, void *, size_t));
+void	 _EXFUN(bzero,(void *, size_t));
+char 	*_EXFUN(index,(const char *, int));
+char 	*_EXFUN(rindex,(const char *, int));
+#endif /* ! __STRICT_ANSI__ */
+
+int	 _EXFUN(ffs,(int));
+int	 _EXFUN(strcasecmp,(const char *, const char *));
+int	 _EXFUN(strncasecmp,(const char *, const char *, size_t));
+
+_END_STD_C
+
+#endif /* _STRINGS_H_ */
diff --git a/tools/sdk/include/newlib/sys/_default_fcntl.h b/tools/sdk/include/newlib/sys/_default_fcntl.h
new file mode 100644
index 00000000..eb674ae7
--- /dev/null
+++ b/tools/sdk/include/newlib/sys/_default_fcntl.h
@@ -0,0 +1,213 @@
+
+#ifndef	_SYS__DEFAULT_FCNTL_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+#define	_SYS__DEFAULT_FCNTL_H_
+#include <_ansi.h>
+#include 
+#define	_FOPEN		(-1)	/* from sys/file.h, kernel use only */
+#define	_FREAD		0x0001	/* read enabled */
+#define	_FWRITE		0x0002	/* write enabled */
+#define	_FAPPEND	0x0008	/* append (writes guaranteed at the end) */
+#define	_FMARK		0x0010	/* internal; mark during gc() */
+#define	_FDEFER		0x0020	/* internal; defer for next gc pass */
+#define	_FASYNC		0x0040	/* signal pgrp when data ready */
+#define	_FSHLOCK	0x0080	/* BSD flock() shared lock present */
+#define	_FEXLOCK	0x0100	/* BSD flock() exclusive lock present */
+#define	_FCREAT		0x0200	/* open with file create */
+#define	_FTRUNC		0x0400	/* open with truncation */
+#define	_FEXCL		0x0800	/* error on open if file exists */
+#define	_FNBIO		0x1000	/* non blocking I/O (sys5 style) */
+#define	_FSYNC		0x2000	/* do all writes synchronously */
+#define	_FNONBLOCK	0x4000	/* non blocking I/O (POSIX style) */
+#define	_FNDELAY	_FNONBLOCK	/* non blocking I/O (4.2 style) */
+#define	_FNOCTTY	0x8000	/* don't assign a ctty on this open */
+
+#define	O_ACCMODE	(O_RDONLY|O_WRONLY|O_RDWR)
+
+/*
+ * Flag values for open(2) and fcntl(2)
+ * The kernel adds 1 to the open modes to turn it into some
+ * combination of FREAD and FWRITE.
+ */
+#define	O_RDONLY	0		/* +1 == FREAD */
+#define	O_WRONLY	1		/* +1 == FWRITE */
+#define	O_RDWR		2		/* +1 == FREAD|FWRITE */
+#define	O_APPEND	_FAPPEND
+#define	O_CREAT		_FCREAT
+#define	O_TRUNC		_FTRUNC
+#define	O_EXCL		_FEXCL
+#define O_SYNC		_FSYNC
+/*	O_NDELAY	_FNDELAY 	set in include/fcntl.h */
+/*	O_NDELAY	_FNBIO 		set in include/fcntl.h */
+#define	O_NONBLOCK	_FNONBLOCK
+#define	O_NOCTTY	_FNOCTTY
+/* For machines which care - */
+#if defined (__CYGWIN__)
+#define _FBINARY        0x10000
+#define _FTEXT          0x20000
+#define _FNOINHERIT	0x40000
+#define _FDIRECT        0x80000
+#define _FNOFOLLOW      0x100000
+#define _FDIRECTORY     0x200000
+#define _FEXECSRCH      0x400000
+
+#define O_BINARY	_FBINARY
+#define O_TEXT		_FTEXT
+#define O_CLOEXEC	_FNOINHERIT
+#define O_DIRECT        _FDIRECT
+#define O_NOFOLLOW      _FNOFOLLOW
+#define O_DSYNC         _FSYNC
+#define O_RSYNC         _FSYNC
+#define O_DIRECTORY     _FDIRECTORY
+#define O_EXEC          _FEXECSRCH
+#define O_SEARCH        _FEXECSRCH
+#endif
+
+#ifndef	_POSIX_SOURCE
+
+/*
+ * Flags that work for fcntl(fd, F_SETFL, FXXXX)
+ */
+#define	FAPPEND		_FAPPEND
+#define	FSYNC		_FSYNC
+#define	FASYNC		_FASYNC
+#define	FNBIO		_FNBIO
+#define	FNONBIO		_FNONBLOCK	/* XXX fix to be NONBLOCK everywhere */
+#define	FNDELAY		_FNDELAY
+
+/*
+ * Flags that are disallowed for fcntl's (FCNTLCANT);
+ * used for opens, internal state, or locking.
+ */
+#define	FREAD		_FREAD
+#define	FWRITE		_FWRITE
+#define	FMARK		_FMARK
+#define	FDEFER		_FDEFER
+#define	FSHLOCK		_FSHLOCK
+#define	FEXLOCK		_FEXLOCK
+
+/*
+ * The rest of the flags, used only for opens
+ */
+#define	FOPEN		_FOPEN
+#define	FCREAT		_FCREAT
+#define	FTRUNC		_FTRUNC
+#define	FEXCL		_FEXCL
+#define	FNOCTTY		_FNOCTTY
+
+#endif	/* !_POSIX_SOURCE */
+
+/* XXX close on exec request; must match UF_EXCLOSE in user.h */
+#define	FD_CLOEXEC	1	/* posix */
+
+/* fcntl(2) requests */
+#define	F_DUPFD		0	/* Duplicate fildes */
+#define	F_GETFD		1	/* Get fildes flags (close on exec) */
+#define	F_SETFD		2	/* Set fildes flags (close on exec) */
+#define	F_GETFL		3	/* Get file flags */
+#define	F_SETFL		4	/* Set file flags */
+#ifndef	_POSIX_SOURCE
+#define	F_GETOWN 	5	/* Get owner - for ASYNC */
+#define	F_SETOWN 	6	/* Set owner - for ASYNC */
+#endif	/* !_POSIX_SOURCE */
+#define	F_GETLK  	7	/* Get record-locking information */
+#define	F_SETLK  	8	/* Set or Clear a record-lock (Non-Blocking) */
+#define	F_SETLKW 	9	/* Set or Clear a record-lock (Blocking) */
+#ifndef	_POSIX_SOURCE
+#define	F_RGETLK 	10	/* Test a remote lock to see if it is blocked */
+#define	F_RSETLK 	11	/* Set or unlock a remote lock */
+#define	F_CNVT 		12	/* Convert a fhandle to an open fd */
+#define	F_RSETLKW 	13	/* Set or Clear remote record-lock(Blocking) */
+#endif	/* !_POSIX_SOURCE */
+#ifdef __CYGWIN__
+#define	F_DUPFD_CLOEXEC	14	/* As F_DUPFD, but set close-on-exec flag */
+#endif
+
+/* fcntl(2) flags (l_type field of flock structure) */
+#define	F_RDLCK		1	/* read lock */
+#define	F_WRLCK		2	/* write lock */
+#define	F_UNLCK		3	/* remove lock(s) */
+#ifndef	_POSIX_SOURCE
+#define	F_UNLKSYS	4	/* remove remote locks for a given system */
+#endif	/* !_POSIX_SOURCE */
+
+#if __BSD_VISIBLE || __POSIX_VISIBLE >= 200809 || defined(__CYGWIN__)
+/* Special descriptor value to denote the cwd in calls to openat(2) etc. */
+#define AT_FDCWD -2
+
+/* Flag values for faccessat2) et al. */
+#define AT_EACCESS              1
+#define AT_SYMLINK_NOFOLLOW     2
+#define AT_SYMLINK_FOLLOW       4
+#define AT_REMOVEDIR            8
+#endif
+
+#if __BSD_VISIBLE
+/* lock operations for flock(2) */
+#define	LOCK_SH		0x01		/* shared file lock */
+#define	LOCK_EX		0x02		/* exclusive file lock */
+#define	LOCK_NB		0x04		/* don't block when locking */
+#define	LOCK_UN		0x08		/* unlock file */
+#endif
+
+/*#include */
+
+#ifndef __CYGWIN__
+/* file segment locking set data type - information passed to system by user */
+struct flock {
+	short	l_type;		/* F_RDLCK, F_WRLCK, or F_UNLCK */
+	short	l_whence;	/* flag to choose starting offset */
+	long	l_start;	/* relative offset, in bytes */
+	long	l_len;		/* length, in bytes; 0 means lock to EOF */
+	short	l_pid;		/* returned with F_GETLK */
+	short	l_xxx;		/* reserved for future use */
+};
+#endif /* __CYGWIN__ */
+
+#ifndef	_POSIX_SOURCE
+/* extended file segment locking set data type */
+struct eflock {
+	short	l_type;		/* F_RDLCK, F_WRLCK, or F_UNLCK */
+	short	l_whence;	/* flag to choose starting offset */
+	long	l_start;	/* relative offset, in bytes */
+	long	l_len;		/* length, in bytes; 0 means lock to EOF */
+	short	l_pid;		/* returned with F_GETLK */
+	short	l_xxx;		/* reserved for future use */
+	long	l_rpid;		/* Remote process id wanting this lock */
+	long	l_rsys;		/* Remote system id wanting this lock */
+};
+#endif	/* !_POSIX_SOURCE */
+
+#include 
+#include 		/* sigh. for the mode bits for open/creat */
+
+extern int open _PARAMS ((const char *, int, ...));
+#if __BSD_VISIBLE || __POSIX_VISIBLE >= 200809 || defined(__CYGWIN__)
+extern int openat _PARAMS ((int, const char *, int, ...));
+#endif
+extern int creat _PARAMS ((const char *, mode_t));
+extern int fcntl _PARAMS ((int, int, ...));
+#if __BSD_VISIBLE
+extern int flock _PARAMS ((int, int));
+#endif
+#ifdef __CYGWIN__
+#include 
+extern int futimesat _PARAMS ((int, const char *, const struct timeval *));
+#endif
+
+/* Provide _ prototypes for functions provided by some versions
+   of newlib.  */
+#ifdef _COMPILING_NEWLIB
+extern int _open _PARAMS ((const char *, int, ...));
+extern int _fcntl _PARAMS ((int, int, ...));
+#ifdef __LARGE64_FILES
+extern int _open64 _PARAMS ((const char *, int, ...));
+#endif
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif	/* !_SYS__DEFAULT_FCNTL_H_ */
diff --git a/tools/sdk/include/newlib/sys/_intsup.h b/tools/sdk/include/newlib/sys/_intsup.h
new file mode 100644
index 00000000..fa78426c
--- /dev/null
+++ b/tools/sdk/include/newlib/sys/_intsup.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2004, 2005 by
+ * Ralf Corsepius, Ulm/Germany. All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software
+ * is freely granted, provided that this notice is preserved.
+ *
+ * Modified for xtensa arch & non-long int32_t, removes automatic setting of __have_long32.
+ */
+
+#ifndef _SYS__INTSUP_H
+#define _SYS__INTSUP_H
+
+#include 
+
+#define __STDINT_EXP(x) __##x##__
+
+#define __have_longlong64 1
+
+#endif /* _SYS__INTSUP_H */
diff --git a/tools/sdk/include/newlib/sys/_types.h b/tools/sdk/include/newlib/sys/_types.h
new file mode 100644
index 00000000..07bc2767
--- /dev/null
+++ b/tools/sdk/include/newlib/sys/_types.h
@@ -0,0 +1,91 @@
+/* ANSI C namespace clean utility typedefs */
+
+/* This file defines various typedefs needed by the system calls that support
+   the C library.  Basically, they're just the POSIX versions with an '_'
+   prepended.  This file lives in the `sys' directory so targets can provide
+   their own if desired (or they can put target dependant conditionals here).
+*/
+
+#ifndef	_SYS__TYPES_H
+#define _SYS__TYPES_H
+
+#include 
+#include 
+
+#ifndef __off_t_defined
+typedef long _off_t;
+#endif
+
+#ifndef __dev_t_defined
+typedef short __dev_t;
+#endif
+
+#ifndef __uid_t_defined
+typedef unsigned short __uid_t;
+#endif
+#ifndef __gid_t_defined
+typedef unsigned short __gid_t;
+#endif
+
+#ifndef __off64_t_defined
+__extension__ typedef long long _off64_t;
+#endif
+
+/*
+ * We need fpos_t for the following, but it doesn't have a leading "_",
+ * so we use _fpos_t instead.
+ */
+#ifndef __fpos_t_defined
+typedef long _fpos_t;		/* XXX must match off_t in  */
+				/* (and must be `long' for now) */
+#endif
+
+#ifdef __LARGE64_FILES
+#ifndef __fpos64_t_defined
+typedef _off64_t _fpos64_t;
+#endif
+#endif
+
+#ifndef __ssize_t_defined
+#ifdef __SIZE_TYPE__
+/* If __SIZE_TYPE__ is defined (gcc) we define ssize_t based on size_t.
+   We simply change "unsigned" to "signed" for this single definition
+   to make sure ssize_t and size_t only differ by their signedness. */
+#define unsigned signed
+typedef __SIZE_TYPE__ _ssize_t;
+#undef unsigned
+#else
+#if defined(__INT_MAX__) && __INT_MAX__ == 2147483647
+typedef int _ssize_t;
+#else
+typedef long _ssize_t;
+#endif
+#endif
+#endif
+
+#define __need_wint_t
+#include 
+
+#ifndef __mbstate_t_defined
+/* Conversion state information.  */
+typedef struct
+{
+  int __count;
+  union
+  {
+    wint_t __wch;
+    unsigned char __wchb[4];
+  } __value;		/* Value so far.  */
+} _mbstate_t;
+#endif
+
+#ifndef __flock_t_defined
+typedef _LOCK_RECURSIVE_T _flock_t;
+#endif
+
+#ifndef __iconv_t_defined
+/* Iconv descriptor type */
+typedef void *_iconv_t;
+#endif
+
+#endif	/* _SYS__TYPES_H */
diff --git a/tools/sdk/include/newlib/sys/cdefs.h b/tools/sdk/include/newlib/sys/cdefs.h
new file mode 100644
index 00000000..a5e613c6
--- /dev/null
+++ b/tools/sdk/include/newlib/sys/cdefs.h
@@ -0,0 +1,710 @@
+/* libc/sys/linux/sys/cdefs.h - Helper macros for K&R vs. ANSI C compat. */
+
+/* Written 2000 by Werner Almesberger */
+
+/*-
+ * Copyright (c) 1991, 1993
+ *	The Regents of the University of California.  All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * Berkeley Software Design, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)cdefs.h	8.8 (Berkeley) 1/9/95
+ * $FreeBSD$
+ */
+
+#ifndef	_SYS_CDEFS_H_
+#define	_SYS_CDEFS_H_
+
+#include 
+#include 
+#include 
+
+#define __PMT(args)	args
+#define __DOTS    	, ...
+#define __THROW
+
+#ifdef __GNUC__
+# define __ASMNAME(cname)  __XSTRING (__USER_LABEL_PREFIX__) cname
+#endif
+
+#define __ptr_t void *
+#define __long_double_t  long double
+
+#define __attribute_malloc__
+#define __attribute_pure__
+#define __attribute_format_strfmon__(a,b)
+#define __flexarr      [0]
+
+#ifndef __BOUNDED_POINTERS__
+# define __bounded      /* nothing */
+# define __unbounded    /* nothing */
+# define __ptrvalue     /* nothing */
+#endif
+
+/*
+ * Testing against Clang-specific extensions.
+ */
+
+#ifndef	__has_extension
+#define	__has_extension		__has_feature
+#endif
+#ifndef	__has_feature
+#define	__has_feature(x)	0
+#endif
+#ifndef	__has_include
+#define	__has_include(x)	0
+#endif
+#ifndef	__has_builtin
+#define	__has_builtin(x)	0
+#endif
+
+#if defined(__cplusplus)
+#define	__BEGIN_DECLS	extern "C" {
+#define	__END_DECLS	}
+#else
+#define	__BEGIN_DECLS
+#define	__END_DECLS
+#endif
+
+/*
+ * This code has been put in place to help reduce the addition of
+ * compiler specific defines in FreeBSD code.  It helps to aid in
+ * having a compiler-agnostic source tree.
+ */
+
+#if defined(__GNUC__) || defined(__INTEL_COMPILER)
+
+#if __GNUC__ >= 3 || defined(__INTEL_COMPILER)
+#define __GNUCLIKE_ASM 3
+#define __GNUCLIKE_MATH_BUILTIN_CONSTANTS
+#else
+#define __GNUCLIKE_ASM 2
+#endif
+#define __GNUCLIKE___TYPEOF 1
+#define __GNUCLIKE___OFFSETOF 1
+#define __GNUCLIKE___SECTION 1
+
+#ifndef __INTEL_COMPILER
+# define __GNUCLIKE_CTOR_SECTION_HANDLING 1
+#endif
+
+#define __GNUCLIKE_BUILTIN_CONSTANT_P 1
+# if defined(__INTEL_COMPILER) && defined(__cplusplus) \
+    && __INTEL_COMPILER < 800
+#  undef __GNUCLIKE_BUILTIN_CONSTANT_P
+# endif
+
+#if (__GNUC_MINOR__ > 95 || __GNUC__ >= 3) && !defined(__INTEL_COMPILER)
+# define __GNUCLIKE_BUILTIN_VARARGS 1
+# define __GNUCLIKE_BUILTIN_STDARG 1
+# define __GNUCLIKE_BUILTIN_VAALIST 1
+#endif
+
+#if defined(__GNUC__)
+# define __GNUC_VA_LIST_COMPATIBILITY 1
+#endif
+
+/*
+ * Compiler memory barriers, specific to gcc and clang.
+ */
+#if defined(__GNUC__)
+#define	__compiler_membar()	__asm __volatile(" " : : : "memory")
+#endif
+
+#ifndef __INTEL_COMPILER
+# define __GNUCLIKE_BUILTIN_NEXT_ARG 1
+# define __GNUCLIKE_MATH_BUILTIN_RELOPS
+#endif
+
+#define __GNUCLIKE_BUILTIN_MEMCPY 1
+
+/* XXX: if __GNUC__ >= 2: not tested everywhere originally, where replaced */
+#define __CC_SUPPORTS_INLINE 1
+#define __CC_SUPPORTS___INLINE 1
+#define __CC_SUPPORTS___INLINE__ 1
+
+#define __CC_SUPPORTS___FUNC__ 1
+#define __CC_SUPPORTS_WARNING 1
+
+#define __CC_SUPPORTS_VARADIC_XXX 1 /* see varargs.h */
+
+#define __CC_SUPPORTS_DYNAMIC_ARRAY_INIT 1
+
+#endif /* __GNUC__ || __INTEL_COMPILER */
+
+/*
+ * The __CONCAT macro is used to concatenate parts of symbol names, e.g.
+ * with "#define OLD(foo) __CONCAT(old,foo)", OLD(foo) produces oldfoo.
+ * The __CONCAT macro is a bit tricky to use if it must work in non-ANSI
+ * mode -- there must be no spaces between its arguments, and for nested
+ * __CONCAT's, all the __CONCAT's must be at the left.  __CONCAT can also
+ * concatenate double-quoted strings produced by the __STRING macro, but
+ * this only works with ANSI C.
+ *
+ * __XSTRING is like __STRING, but it expands any macros in its argument
+ * first.  It is only available with ANSI C.
+ */
+#if defined(__STDC__) || defined(__cplusplus)
+#define	__P(protos)	protos		/* full-blown ANSI C */
+#define	__CONCAT1(x,y)	x ## y
+#define	__CONCAT(x,y)	__CONCAT1(x,y)
+#define	__STRING(x)	#x		/* stringify without expanding x */
+#define	__XSTRING(x)	__STRING(x)	/* expand x, then stringify */
+
+#define	__const		const		/* define reserved names to standard */
+#define	__signed	signed
+#define	__volatile	volatile
+#if defined(__cplusplus)
+#define	__inline	inline		/* convert to C++ keyword */
+#else
+#if !(defined(__CC_SUPPORTS___INLINE))
+#define	__inline			/* delete GCC keyword */
+#endif /* ! __CC_SUPPORTS___INLINE */
+#endif /* !__cplusplus */
+
+#else	/* !(__STDC__ || __cplusplus) */
+#define	__P(protos)	()		/* traditional C preprocessor */
+#define	__CONCAT(x,y)	x/**/y
+#define	__STRING(x)	"x"
+
+#if !defined(__CC_SUPPORTS___INLINE)
+#define	__const				/* delete pseudo-ANSI C keywords */
+#define	__inline
+#define	__signed
+#define	__volatile
+/*
+ * In non-ANSI C environments, new programs will want ANSI-only C keywords
+ * deleted from the program and old programs will want them left alone.
+ * When using a compiler other than gcc, programs using the ANSI C keywords
+ * const, inline etc. as normal identifiers should define -DNO_ANSI_KEYWORDS.
+ * When using "gcc -traditional", we assume that this is the intent; if
+ * __GNUC__ is defined but __STDC__ is not, we leave the new keywords alone.
+ */
+#ifndef	NO_ANSI_KEYWORDS
+#define	const				/* delete ANSI C keywords */
+#define	inline
+#define	signed
+#define	volatile
+#endif	/* !NO_ANSI_KEYWORDS */
+#endif	/* !__CC_SUPPORTS___INLINE */
+#endif	/* !(__STDC__ || __cplusplus) */
+
+/*
+ * Compiler-dependent macros to help declare dead (non-returning) and
+ * pure (no side effects) functions, and unused variables.  They are
+ * null except for versions of gcc that are known to support the features
+ * properly (old versions of gcc-2 supported the dead and pure features
+ * in a different (wrong) way).  If we do not provide an implementation
+ * for a given compiler, let the compile fail if it is told to use
+ * a feature that we cannot live without.
+ */
+#ifdef lint
+#define	__dead2
+#define	__pure2
+#define	__unused
+#define	__packed
+#define	__aligned(x)
+#define	__section(x)
+#else
+#if !__GNUC_PREREQ__(2, 5) && !defined(__INTEL_COMPILER)
+#define	__dead2
+#define	__pure2
+#define	__unused
+#endif
+#if __GNUC__ == 2 && __GNUC_MINOR__ >= 5 && __GNUC_MINOR__ < 7 && !defined(__INTEL_COMPILER)
+#define	__dead2		__attribute__((__noreturn__))
+#define	__pure2		__attribute__((__const__))
+#define	__unused
+/* XXX Find out what to do for __packed, __aligned and __section */
+#endif
+#if __GNUC_PREREQ__(2, 7)
+#define	__dead2		__attribute__((__noreturn__))
+#define	__pure2		__attribute__((__const__))
+#define	__unused	__attribute__((__unused__))
+#define	__used		__attribute__((__used__))
+#define	__packed	__attribute__((__packed__))
+#define	__aligned(x)	__attribute__((__aligned__(x)))
+#define	__section(x)	__attribute__((__section__(x)))
+#endif
+#if defined(__INTEL_COMPILER)
+#define __dead2		__attribute__((__noreturn__))
+#define __pure2		__attribute__((__const__))
+#define __unused	__attribute__((__unused__))
+#define __used		__attribute__((__used__))
+#define __packed	__attribute__((__packed__))
+#define __aligned(x)	__attribute__((__aligned__(x)))
+#define __section(x)	__attribute__((__section__(x)))
+#endif
+#endif
+
+#if !__GNUC_PREREQ__(2, 95)
+#define	__alignof(x)	__offsetof(struct { char __a; x __b; }, __b)
+#endif
+
+/*
+ * Keywords added in C11.
+ */
+
+#if !defined(__STDC_VERSION__) || __STDC_VERSION__ < 201112L
+
+#if !__has_extension(c_alignas)
+#if (defined(__cplusplus) && __cplusplus >= 201103L) || \
+    __has_extension(cxx_alignas)
+#define	_Alignas(x)		alignas(x)
+#else
+/* XXX: Only emulates _Alignas(constant-expression); not _Alignas(type-name). */
+#define	_Alignas(x)		__aligned(x)
+#endif
+#endif
+
+#if defined(__cplusplus) && __cplusplus >= 201103L
+#define	_Alignof(x)		alignof(x)
+#else
+#define	_Alignof(x)		__alignof(x)
+#endif
+
+#if !__has_extension(c_atomic) && !__has_extension(cxx_atomic)
+/*
+ * No native support for _Atomic(). Place object in structure to prevent
+ * most forms of direct non-atomic access.
+ */
+#define	_Atomic(T)		struct { T volatile __val; }
+#endif
+
+#if defined(__cplusplus) && __cplusplus >= 201103L
+#define	_Noreturn		[[noreturn]]
+#else
+#define	_Noreturn		__dead2
+#endif
+
+#if __GNUC_PREREQ__(4, 6) && !defined(__cplusplus)
+/*  Do nothing: _Static_assert() works as per C11 */
+#elif !__has_extension(c_static_assert)
+#if (defined(__cplusplus) && __cplusplus >= 201103L) || \
+    __has_extension(cxx_static_assert)
+#define	_Static_assert(x, y)	static_assert(x, y)
+#elif defined(__COUNTER__)
+#define	_Static_assert(x, y)	__Static_assert(x, __COUNTER__)
+#define	__Static_assert(x, y)	___Static_assert(x, y)
+#define	___Static_assert(x, y)	typedef char __assert_ ## y[(x) ? 1 : -1]
+#else
+#define	_Static_assert(x, y)	struct __hack
+#endif
+#endif
+
+#if !__has_extension(c_thread_local)
+/* XXX: Change this to test against C++11 when clang in base supports it. */
+#if /* (defined(__cplusplus) && __cplusplus >= 201103L) || */ \
+    __has_extension(cxx_thread_local)
+#define	_Thread_local		thread_local
+#else
+#define	_Thread_local		__thread
+#endif
+#endif
+
+#endif /* __STDC_VERSION__ || __STDC_VERSION__ < 201112L */
+
+/*
+ * Emulation of C11 _Generic().  Unlike the previously defined C11
+ * keywords, it is not possible to implement this using exactly the same
+ * syntax.  Therefore implement something similar under the name
+ * __generic().  Unlike _Generic(), this macro can only distinguish
+ * between a single type, so it requires nested invocations to
+ * distinguish multiple cases.
+ */
+
+#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L
+#define	__generic(expr, t, yes, no)					\
+	_Generic(expr, t: yes, default: no)
+#elif __GNUC_PREREQ__(3, 1) && !defined(__cplusplus)
+#define	__generic(expr, t, yes, no)					\
+	__builtin_choose_expr(						\
+	    __builtin_types_compatible_p(__typeof(expr), t), yes, no)
+#endif
+
+#if __GNUC_PREREQ__(2, 96)
+#define	__malloc_like	__attribute__((__malloc__))
+#define	__pure		__attribute__((__pure__))
+#else
+#define	__malloc_like
+#define	__pure
+#endif
+
+#if __GNUC_PREREQ__(3, 1) || (defined(__INTEL_COMPILER) && __INTEL_COMPILER >= 800)
+#define	__always_inline	__attribute__((__always_inline__))
+#else
+#define	__always_inline
+#endif
+
+#if __GNUC_PREREQ__(3, 1)
+#define	__noinline	__attribute__ ((__noinline__))
+#else
+#define	__noinline
+#endif
+
+#if __GNUC_PREREQ__(3, 3)
+#define __nonnull(x)	__attribute__((__nonnull__(x)))
+#else
+#define __nonnull(x)
+#endif
+
+#if __GNUC_PREREQ__(3, 4)
+#define	__fastcall	__attribute__((__fastcall__))
+#else
+#define	__fastcall
+#endif
+
+#if __GNUC_PREREQ__(4, 1)
+#define	__returns_twice	__attribute__((__returns_twice__))
+#else
+#define	__returns_twice
+#endif
+
+/* XXX: should use `#if __STDC_VERSION__ < 199901'. */
+#if !__GNUC_PREREQ__(2, 7) && !defined(__INTEL_COMPILER)
+#define	__func__	NULL
+#endif
+
+/*
+ * GCC 2.95 provides `__restrict' as an extension to C90 to support the
+ * C99-specific `restrict' type qualifier.  We happen to use `__restrict' as
+ * a way to define the `restrict' type qualifier without disturbing older
+ * software that is unaware of C99 keywords.
+ */
+#if !(__GNUC__ == 2 && __GNUC_MINOR__ == 95)
+#if !defined(__STDC_VERSION__) || __STDC_VERSION__ < 199901 || defined(lint)
+#define	__restrict
+#else
+#define	__restrict	restrict
+#endif
+#endif
+
+/*
+ * GNU C version 2.96 adds explicit branch prediction so that
+ * the CPU back-end can hint the processor and also so that
+ * code blocks can be reordered such that the predicted path
+ * sees a more linear flow, thus improving cache behavior, etc.
+ *
+ * The following two macros provide us with a way to utilize this
+ * compiler feature.  Use __predict_true() if you expect the expression
+ * to evaluate to true, and __predict_false() if you expect the
+ * expression to evaluate to false.
+ *
+ * A few notes about usage:
+ *
+ *	* Generally, __predict_false() error condition checks (unless
+ *	  you have some _strong_ reason to do otherwise, in which case
+ *	  document it), and/or __predict_true() `no-error' condition
+ *	  checks, assuming you want to optimize for the no-error case.
+ *
+ *	* Other than that, if you don't know the likelihood of a test
+ *	  succeeding from empirical or other `hard' evidence, don't
+ *	  make predictions.
+ *
+ *	* These are meant to be used in places that are run `a lot'.
+ *	  It is wasteful to make predictions in code that is run
+ *	  seldomly (e.g. at subsystem initialization time) as the
+ *	  basic block reordering that this affects can often generate
+ *	  larger code.
+ */
+#if __GNUC_PREREQ__(2, 96)
+#define __predict_true(exp)     __builtin_expect((exp), 1)
+#define __predict_false(exp)    __builtin_expect((exp), 0)
+#else
+#define __predict_true(exp)     (exp)
+#define __predict_false(exp)    (exp)
+#endif
+
+#if __GNUC_PREREQ__(4, 2)
+#define	__hidden	__attribute__((__visibility__("hidden")))
+#define	__exported	__attribute__((__visibility__("default")))
+#else
+#define	__hidden
+#define	__exported
+#endif
+
+#define __offsetof(type, field)	offsetof(type, field)
+#define	__rangeof(type, start, end) \
+	(__offsetof(type, end) - __offsetof(type, start))
+
+/*
+ * Given the pointer x to the member m of the struct s, return
+ * a pointer to the containing structure.  When using GCC, we first
+ * assign pointer x to a local variable, to check that its type is
+ * compatible with member m.
+ */
+#if __GNUC_PREREQ__(3, 1)
+#define	__containerof(x, s, m) ({					\
+	const volatile __typeof__(((s *)0)->m) *__x = (x);		\
+	__DEQUALIFY(s *, (const volatile char *)__x - __offsetof(s, m));\
+})
+#else
+#define	__containerof(x, s, m)						\
+	__DEQUALIFY(s *, (const volatile char *)(x) - __offsetof(s, m))
+#endif
+
+/*
+ * Compiler-dependent macros to declare that functions take printf-like
+ * or scanf-like arguments.  They are null except for versions of gcc
+ * that are known to support the features properly (old versions of gcc-2
+ * didn't permit keeping the keywords out of the application namespace).
+ */
+#if !__GNUC_PREREQ__(2, 7) && !defined(__INTEL_COMPILER)
+#define	__printflike(fmtarg, firstvararg)
+#define	__scanflike(fmtarg, firstvararg)
+#define	__format_arg(fmtarg)
+#define	__strfmonlike(fmtarg, firstvararg)
+#define	__strftimelike(fmtarg, firstvararg)
+#else
+#define	__printflike(fmtarg, firstvararg) \
+	    __attribute__((__format__ (__printf__, fmtarg, firstvararg)))
+#define	__scanflike(fmtarg, firstvararg) \
+	    __attribute__((__format__ (__scanf__, fmtarg, firstvararg)))
+#define	__format_arg(fmtarg)	__attribute__((__format_arg__ (fmtarg)))
+#define	__strfmonlike(fmtarg, firstvararg) \
+	    __attribute__((__format__ (__strfmon__, fmtarg, firstvararg)))
+#define	__strftimelike(fmtarg, firstvararg) \
+	    __attribute__((__format__ (__strftime__, fmtarg, firstvararg)))
+#endif
+
+/* Compiler-dependent macros that rely on FreeBSD-specific extensions. */
+#if defined(__FreeBSD_cc_version) && __FreeBSD_cc_version >= 300001 && \
+    defined(__GNUC__) && !defined(__INTEL_COMPILER)
+#define	__printf0like(fmtarg, firstvararg) \
+	    __attribute__((__format__ (__printf0__, fmtarg, firstvararg)))
+#else
+#define	__printf0like(fmtarg, firstvararg)
+#endif
+
+#if defined(__GNUC__) || defined(__INTEL_COMPILER)
+#ifndef __INTEL_COMPILER
+#define	__strong_reference(sym,aliassym)	\
+	extern __typeof (sym) aliassym __attribute__ ((__alias__ (#sym)))
+#endif
+#ifdef __ELF__
+#ifdef __STDC__
+#define	__weak_reference(sym,alias)	\
+	__asm__(".weak " #alias);	\
+	__asm__(".equ "  #alias ", " #sym)
+#define	__warn_references(sym,msg)	\
+	__asm__(".section .gnu.warning." #sym);	\
+	__asm__(".asciz \"" msg "\"");	\
+	__asm__(".previous")
+#define	__sym_compat(sym,impl,verid)	\
+	__asm__(".symver " #impl ", " #sym "@" #verid)
+#define	__sym_default(sym,impl,verid)	\
+	__asm__(".symver " #impl ", " #sym "@@" #verid)
+#else
+#define	__weak_reference(sym,alias)	\
+	__asm__(".weak alias");		\
+	__asm__(".equ alias, sym")
+#define	__warn_references(sym,msg)	\
+	__asm__(".section .gnu.warning.sym"); \
+	__asm__(".asciz \"msg\"");	\
+	__asm__(".previous")
+#define	__sym_compat(sym,impl,verid)	\
+	__asm__(".symver impl, sym@verid")
+#define	__sym_default(impl,sym,verid)	\
+	__asm__(".symver impl, sym@@verid")
+#endif	/* __STDC__ */
+#else	/* !__ELF__ */
+#ifdef __STDC__
+#define	__weak_reference(sym,alias)	\
+	__asm__(".stabs \"_" #alias "\",11,0,0,0");	\
+	__asm__(".stabs \"_" #sym "\",1,0,0,0")
+#define	__warn_references(sym,msg)	\
+	__asm__(".stabs \"" msg "\",30,0,0,0");		\
+	__asm__(".stabs \"_" #sym "\",1,0,0,0")
+#else
+#define	__weak_reference(sym,alias)	\
+	__asm__(".stabs \"_/**/alias\",11,0,0,0");	\
+	__asm__(".stabs \"_/**/sym\",1,0,0,0")
+#define	__warn_references(sym,msg)	\
+	__asm__(".stabs msg,30,0,0,0");			\
+	__asm__(".stabs \"_/**/sym\",1,0,0,0")
+#endif	/* __STDC__ */
+#endif	/* __ELF__ */
+#endif	/* __GNUC__ || __INTEL_COMPILER */
+
+#ifndef	__FBSDID
+#define	__FBSDID(s)	struct __hack
+#endif
+
+#ifndef	__RCSID
+#define	__RCSID(s)	struct __hack
+#endif
+
+#ifndef	__RCSID_SOURCE
+#define	__RCSID_SOURCE(s)	struct __hack
+#endif
+
+#ifndef	__SCCSID
+#define	__SCCSID(s)	struct __hack
+#endif
+
+#ifndef	__COPYRIGHT
+#define	__COPYRIGHT(s)	struct __hack
+#endif
+
+#ifndef	__DECONST
+#define	__DECONST(type, var)	((type)(__uintptr_t)(const void *)(var))
+#endif
+
+#ifndef	__DEVOLATILE
+#define	__DEVOLATILE(type, var)	((type)(__uintptr_t)(volatile void *)(var))
+#endif
+
+#ifndef	__DEQUALIFY
+#define	__DEQUALIFY(type, var)	((type)(__uintptr_t)(const volatile void *)(var))
+#endif
+
+/*-
+ * The following definitions are an extension of the behavior originally
+ * implemented in , but with a different level of granularity.
+ * POSIX.1 requires that the macros we test be defined before any standard
+ * header file is included.
+ *
+ * Here's a quick run-down of the versions:
+ *  defined(_POSIX_SOURCE)		1003.1-1988
+ *  _POSIX_C_SOURCE == 1		1003.1-1990
+ *  _POSIX_C_SOURCE == 2		1003.2-1992 C Language Binding Option
+ *  _POSIX_C_SOURCE == 199309		1003.1b-1993
+ *  _POSIX_C_SOURCE == 199506		1003.1c-1995, 1003.1i-1995,
+ *					and the omnibus ISO/IEC 9945-1: 1996
+ *  _POSIX_C_SOURCE == 200112		1003.1-2001
+ *  _POSIX_C_SOURCE == 200809		1003.1-2008
+ *
+ * In addition, the X/Open Portability Guide, which is now the Single UNIX
+ * Specification, defines a feature-test macro which indicates the version of
+ * that specification, and which subsumes _POSIX_C_SOURCE.
+ *
+ * Our macros begin with two underscores to avoid namespace screwage.
+ */
+
+/* Deal with IEEE Std. 1003.1-1990, in which _POSIX_C_SOURCE == 1. */
+#if defined(_POSIX_C_SOURCE) && _POSIX_C_SOURCE == 1
+#undef _POSIX_C_SOURCE		/* Probably illegal, but beyond caring now. */
+#define	_POSIX_C_SOURCE		199009
+#endif
+
+/* Deal with IEEE Std. 1003.2-1992, in which _POSIX_C_SOURCE == 2. */
+#if defined(_POSIX_C_SOURCE) && _POSIX_C_SOURCE == 2
+#undef _POSIX_C_SOURCE
+#define	_POSIX_C_SOURCE		199209
+#endif
+
+/* Deal with various X/Open Portability Guides and Single UNIX Spec. */
+#ifdef _XOPEN_SOURCE
+#if _XOPEN_SOURCE - 0 >= 700
+#define	__XSI_VISIBLE		700
+#undef _POSIX_C_SOURCE
+#define	_POSIX_C_SOURCE		200809
+#elif _XOPEN_SOURCE - 0 >= 600
+#define	__XSI_VISIBLE		600
+#undef _POSIX_C_SOURCE
+#define	_POSIX_C_SOURCE		200112
+#elif _XOPEN_SOURCE - 0 >= 500
+#define	__XSI_VISIBLE		500
+#undef _POSIX_C_SOURCE
+#define	_POSIX_C_SOURCE		199506
+#endif
+#endif
+
+/*
+ * Deal with all versions of POSIX.  The ordering relative to the tests above is
+ * important.
+ */
+#if defined(_POSIX_SOURCE) && !defined(_POSIX_C_SOURCE)
+#define	_POSIX_C_SOURCE		198808
+#endif
+#ifdef _POSIX_C_SOURCE
+#if _POSIX_C_SOURCE >= 200809
+#define	__POSIX_VISIBLE		200809
+#define	__ISO_C_VISIBLE		1999
+#elif _POSIX_C_SOURCE >= 200112
+#define	__POSIX_VISIBLE		200112
+#define	__ISO_C_VISIBLE		1999
+#elif _POSIX_C_SOURCE >= 199506
+#define	__POSIX_VISIBLE		199506
+#define	__ISO_C_VISIBLE		1990
+#elif _POSIX_C_SOURCE >= 199309
+#define	__POSIX_VISIBLE		199309
+#define	__ISO_C_VISIBLE		1990
+#elif _POSIX_C_SOURCE >= 199209
+#define	__POSIX_VISIBLE		199209
+#define	__ISO_C_VISIBLE		1990
+#elif _POSIX_C_SOURCE >= 199009
+#define	__POSIX_VISIBLE		199009
+#define	__ISO_C_VISIBLE		1990
+#else
+#define	__POSIX_VISIBLE		198808
+#define	__ISO_C_VISIBLE		0
+#endif /* _POSIX_C_SOURCE */
+#else
+/*-
+ * Deal with _ANSI_SOURCE:
+ * If it is defined, and no other compilation environment is explicitly
+ * requested, then define our internal feature-test macros to zero.  This
+ * makes no difference to the preprocessor (undefined symbols in preprocessing
+ * expressions are defined to have value zero), but makes it more convenient for
+ * a test program to print out the values.
+ *
+ * If a program mistakenly defines _ANSI_SOURCE and some other macro such as
+ * _POSIX_C_SOURCE, we will assume that it wants the broader compilation
+ * environment (and in fact we will never get here).
+ */
+#if defined(_ANSI_SOURCE)	/* Hide almost everything. */
+#define	__POSIX_VISIBLE		0
+#define	__XSI_VISIBLE		0
+#define	__BSD_VISIBLE		0
+#define	__ISO_C_VISIBLE		1990
+#elif defined(_C99_SOURCE)	/* Localism to specify strict C99 env. */
+#define	__POSIX_VISIBLE		0
+#define	__XSI_VISIBLE		0
+#define	__BSD_VISIBLE		0
+#define	__ISO_C_VISIBLE		1999
+#elif defined(_C11_SOURCE)	/* Localism to specify strict C11 env. */
+#define	__POSIX_VISIBLE		0
+#define	__XSI_VISIBLE		0
+#define	__BSD_VISIBLE		0
+#define	__ISO_C_VISIBLE		2011
+#elif defined(_GNU_SOURCE)	/* Everything and the kitchen sink. */
+#define	__POSIX_VISIBLE		200809
+#define	__XSI_VISIBLE		700
+#define	__BSD_VISIBLE		1
+#define	__ISO_C_VISIBLE		2011
+#define	__GNU_VISIBLE		1
+#else				/* Default: everything except __GNU_VISIBLE. */
+#define	__POSIX_VISIBLE		200809
+#define	__XSI_VISIBLE		700
+#define	__BSD_VISIBLE		1
+#define	__ISO_C_VISIBLE		2011
+#endif
+#endif
+
+#endif /* !_SYS_CDEFS_H_ */
diff --git a/tools/sdk/include/newlib/sys/config.h b/tools/sdk/include/newlib/sys/config.h
new file mode 100644
index 00000000..b5adfe10
--- /dev/null
+++ b/tools/sdk/include/newlib/sys/config.h
@@ -0,0 +1,300 @@
+#ifndef __SYS_CONFIG_H__
+#define __SYS_CONFIG_H__
+
+#include   /* floating point macros */
+#include 	/* POSIX defs */
+
+#ifdef __aarch64__
+#define MALLOC_ALIGNMENT 16
+#endif
+
+/* exceptions first */
+#if defined(__H8500__) || defined(__W65__)
+#define __SMALL_BITFIELDS
+/* ???  This conditional is true for the h8500 and the w65, defining H8300
+   in those cases probably isn't the right thing to do.  */
+#define H8300 1
+#endif
+
+/* 16 bit integer machines */
+#if defined(__Z8001__) || defined(__Z8002__) || defined(__H8500__) || defined(__W65__) || defined (__mn10200__) || defined (__AVR__)
+
+#undef INT_MAX
+#undef UINT_MAX
+#define INT_MAX 32767
+#define UINT_MAX 65535
+#endif
+
+#if defined (__H8300__) || defined (__H8300H__) || defined(__H8300S__) || defined (__H8300SX__)
+#define __SMALL_BITFIELDS
+#define H8300 1
+#undef INT_MAX
+#undef UINT_MAX
+#define INT_MAX __INT_MAX__
+#define UINT_MAX (__INT_MAX__ * 2U + 1)
+#endif
+
+#if (defined(__CR16__) || defined(__CR16C__) ||defined(__CR16CP__))
+#ifndef __INT32__
+#define __SMALL_BITFIELDS      
+#undef INT_MAX
+#undef UINT_MAX
+#define INT_MAX 32767
+#define UINT_MAX (__INT_MAX__ * 2U + 1)
+#else /* INT32 */
+#undef INT_MAX
+#undef UINT_MAX
+#define INT_MAX 2147483647
+#define UINT_MAX (__INT_MAX__ * 2U + 1)
+#endif /* INT32 */
+
+#endif /* CR16C */
+
+#if defined (__xc16x__) || defined (__xc16xL__) || defined (__xc16xS__)
+#define __SMALL_BITFIELDS
+#endif
+
+#ifdef __W65__
+#define __SMALL_BITFIELDS
+#endif
+
+#if defined(__D10V__)
+#define __SMALL_BITFIELDS
+#undef INT_MAX
+#undef UINT_MAX
+#define INT_MAX __INT_MAX__
+#define UINT_MAX (__INT_MAX__ * 2U + 1)
+#define _POINTER_INT short
+#endif
+
+#if defined(__mc68hc11__) || defined(__mc68hc12__) || defined(__mc68hc1x__)
+#undef INT_MAX
+#undef UINT_MAX
+#define INT_MAX __INT_MAX__
+#define UINT_MAX (__INT_MAX__ * 2U + 1)
+#define _POINTER_INT short
+#endif
+
+#if defined(__m68k__) || defined(__mc68000__)
+#define _READ_WRITE_RETURN_TYPE _ssize_t
+#endif
+
+#ifdef ___AM29K__
+#define _FLOAT_RET double
+#endif
+
+#ifdef __i386__
+#ifndef __unix__
+/* in other words, go32 */
+#define _FLOAT_RET double
+#endif
+#if defined(__linux__) || defined(__RDOS__)
+/* we want the reentrancy structure to be returned by a function */
+#define __DYNAMIC_REENT__
+#define HAVE_GETDATE
+#define _HAVE_SYSTYPES
+#define _READ_WRITE_RETURN_TYPE _ssize_t
+#define __LARGE64_FILES 1
+/* we use some glibc header files so turn on glibc large file feature */
+#define _LARGEFILE64_SOURCE 1
+#endif
+#endif
+
+#ifdef __mn10200__
+#define __SMALL_BITFIELDS
+#endif
+
+#ifdef __AVR__
+#define __SMALL_BITFIELDS
+#define _POINTER_INT short
+#endif
+
+#ifdef __v850
+#define __ATTRIBUTE_IMPURE_PTR__ __attribute__((__sda__))
+#endif
+
+/* For the PowerPC eabi, force the _impure_ptr to be in .sdata */
+#if defined(__PPC__)
+#if defined(_CALL_SYSV)
+#define __ATTRIBUTE_IMPURE_PTR__ __attribute__((__section__(".sdata")))
+#endif
+#ifdef __SPE__
+#define _LONG_DOUBLE double
+#endif
+#endif
+
+/* Configure small REENT structure for Xilinx MicroBlaze platforms */
+#if defined (__MICROBLAZE__)
+#ifndef _REENT_SMALL
+#define _REENT_SMALL
+#endif
+/* Xilinx XMK uses Unix98 mutex */
+#ifdef __XMK__
+#define _UNIX98_THREAD_MUTEX_ATTRIBUTES
+#endif
+#endif
+
+#if defined(__mips__) && !defined(__rtems__)
+#define __ATTRIBUTE_IMPURE_PTR__ __attribute__((__section__(".sdata")))
+#endif
+
+#ifdef __xstormy16__
+#define __SMALL_BITFIELDS
+#undef INT_MAX
+#undef UINT_MAX
+#define INT_MAX __INT_MAX__
+#define UINT_MAX (__INT_MAX__ * 2U + 1)
+#define MALLOC_ALIGNMENT 8
+#define _POINTER_INT short
+#define __BUFSIZ__ 16
+#define _REENT_SMALL
+#endif
+
+#if defined __MSP430__
+#ifndef _REENT_SMALL
+#define _REENT_SMALL
+#endif
+
+#define __SMALL_BITFIELDS
+
+#ifdef __MSP430X_LARGE__
+#define _POINTER_INT long
+#else
+#define _POINTER_INT int
+#endif
+#endif
+
+#ifdef __m32c__
+#define __SMALL_BITFIELDS
+#undef INT_MAX
+#undef UINT_MAX
+#define INT_MAX __INT_MAX__
+#define UINT_MAX (__INT_MAX__ * 2U + 1)
+#define MALLOC_ALIGNMENT 8
+#if defined(__r8c_cpu__) || defined(__m16c_cpu__)
+#define _POINTER_INT short
+#else
+#define _POINTER_INT long
+#endif
+#define __BUFSIZ__ 16
+#define _REENT_SMALL
+#endif /* __m32c__ */
+
+#ifdef __SPU__
+#define MALLOC_ALIGNMENT 16
+#define __CUSTOM_FILE_IO__
+#endif
+
+#ifdef __XTENSA__
+#include 
+#define MALLOC_ALIGNMENT ((XCHAL_DATA_WIDTH) < 16 ? 16 : (XCHAL_DATA_WIDTH))
+/* esp8266-specific: shrink the default fd buffer size */
+#define __BUFSIZ__ 128
+#ifndef __DYNAMIC_REENT__
+#define __DYNAMIC_REENT__
+#endif
+#ifndef _REENT_SMALL
+#define _REENT_SMALL
+#endif
+#define HAVE_GETOPT
+#endif
+
+/* This block should be kept in sync with GCC's limits.h.  The point
+   of having these definitions here is to not include limits.h, which
+   would pollute the user namespace, while still using types of the
+   the correct widths when deciding how to define __int32_t and
+   __int64_t.  */
+#ifndef __INT_MAX__
+# ifdef INT_MAX
+#  define __INT_MAX__ INT_MAX
+# else
+#  define __INT_MAX__ 2147483647
+# endif
+#endif
+
+#ifndef __LONG_MAX__
+# ifdef LONG_MAX
+#  define __LONG_MAX__ LONG_MAX
+# else
+#  if defined (__alpha__) || (defined (__sparc__) && defined(__arch64__)) \
+      || defined (__sparcv9)
+#   define __LONG_MAX__ 9223372036854775807L
+#  else
+#   define __LONG_MAX__ 2147483647L
+#  endif /* __alpha__ || sparc64 */
+# endif
+#endif
+/* End of block that should be kept in sync with GCC's limits.h.  */
+
+#ifndef _POINTER_INT
+#define _POINTER_INT long
+#endif
+
+#ifdef __frv__
+#define __ATTRIBUTE_IMPURE_PTR__ __attribute__((__section__(".sdata")))
+#endif
+#undef __RAND_MAX
+#if __INT_MAX__ == 32767
+#define __RAND_MAX 32767
+#else
+#define __RAND_MAX 0x7fffffff
+#endif
+
+#if defined(__CYGWIN__)
+#include 
+#if !defined (__STRICT_ANSI__) || (__STDC_VERSION__ >= 199901L)
+#define __USE_XOPEN2K 1
+#endif
+#endif
+
+#if defined(__rtems__)
+#define __FILENAME_MAX__ 255
+#define _READ_WRITE_RETURN_TYPE _ssize_t
+#define __DYNAMIC_REENT__
+#define _REENT_GLOBAL_ATEXIT
+#endif
+
+#ifndef __EXPORT
+#define __EXPORT
+#endif
+
+#ifndef __IMPORT
+#define __IMPORT
+#endif
+
+/* Define return type of read/write routines.  In POSIX, the return type
+   for read()/write() is "ssize_t" but legacy newlib code has been using
+   "int" for some time.  If not specified, "int" is defaulted.  */
+#ifndef _READ_WRITE_RETURN_TYPE
+#define _READ_WRITE_RETURN_TYPE int
+#endif
+/* Define `count' parameter of read/write routines.  In POSIX, the `count'
+   parameter is "size_t" but legacy newlib code has been using "int" for some
+   time.  If not specified, "int" is defaulted.  */
+#ifndef _READ_WRITE_BUFSIZE_TYPE
+#define _READ_WRITE_BUFSIZE_TYPE int
+#endif
+
+#ifndef __WCHAR_MAX__
+#if __INT_MAX__ == 32767 || defined (_WIN32)
+#define __WCHAR_MAX__ 0xffffu
+#endif
+#endif
+
+/* See if small reent asked for at configuration time and
+   is not chosen by the platform by default.  */
+#ifdef _WANT_REENT_SMALL
+#ifndef _REENT_SMALL
+#define _REENT_SMALL
+#endif
+#endif
+
+/* If _MB_EXTENDED_CHARSETS_ALL is set, we want all of the extended
+   charsets.  The extended charsets add a few functions and a couple
+   of tables of a few K each. */
+#ifdef _MB_EXTENDED_CHARSETS_ALL
+#define _MB_EXTENDED_CHARSETS_ISO 1
+#define _MB_EXTENDED_CHARSETS_WINDOWS 1
+#endif
+
+#endif /* __SYS_CONFIG_H__ */
diff --git a/tools/sdk/include/newlib/sys/custom_file.h b/tools/sdk/include/newlib/sys/custom_file.h
new file mode 100644
index 00000000..96314fb9
--- /dev/null
+++ b/tools/sdk/include/newlib/sys/custom_file.h
@@ -0,0 +1,2 @@
+#error System-specific custom_file.h is missing.
+
diff --git a/tools/sdk/include/newlib/sys/dir.h b/tools/sdk/include/newlib/sys/dir.h
new file mode 100644
index 00000000..220150dc
--- /dev/null
+++ b/tools/sdk/include/newlib/sys/dir.h
@@ -0,0 +1,10 @@
+/* BSD predecessor of POSIX.1  and struct dirent */
+
+#ifndef _SYS_DIR_H_
+#define _SYS_DIR_H_
+
+#include 
+
+#define direct dirent
+
+#endif /*_SYS_DIR_H_*/
diff --git a/tools/sdk/include/newlib/sys/dirent.h b/tools/sdk/include/newlib/sys/dirent.h
new file mode 100644
index 00000000..a3fb5c02
--- /dev/null
+++ b/tools/sdk/include/newlib/sys/dirent.h
@@ -0,0 +1,13 @@
+/*  includes , which is this file.  On a
+   system which supports , this file is overridden by
+   dirent.h in the libc/sys/.../sys directory.  On a system which does
+   not support , we will get this file which uses #error to force
+   an error.  */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#error " not supported"
+#ifdef __cplusplus
+}
+#endif
diff --git a/tools/sdk/include/newlib/sys/errno.h b/tools/sdk/include/newlib/sys/errno.h
new file mode 100644
index 00000000..a72c3732
--- /dev/null
+++ b/tools/sdk/include/newlib/sys/errno.h
@@ -0,0 +1,192 @@
+/* errno is not a global variable, because that would make using it
+   non-reentrant.  Instead, its address is returned by the function
+   __errno.  */
+
+#ifndef _SYS_ERRNO_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+#define _SYS_ERRNO_H_
+
+#include 
+
+#ifndef _REENT_ONLY
+#define errno (*__errno())
+extern int *__errno _PARAMS ((void));
+#endif
+
+/* Please don't use these variables directly.
+   Use strerror instead. */
+extern __IMPORT _CONST char * _CONST _sys_errlist[];
+extern __IMPORT int _sys_nerr;
+#ifdef __CYGWIN__
+extern __IMPORT const char * const sys_errlist[];
+extern __IMPORT int sys_nerr;
+extern __IMPORT char *program_invocation_name;
+extern __IMPORT char *program_invocation_short_name;
+#endif
+
+#define __errno_r(ptr) ((ptr)->_errno)
+
+#define	EPERM 1		/* Not owner */
+#define	ENOENT 2	/* No such file or directory */
+#define	ESRCH 3		/* No such process */
+#define	EINTR 4		/* Interrupted system call */
+#define	EIO 5		/* I/O error */
+#define	ENXIO 6		/* No such device or address */
+#define	E2BIG 7		/* Arg list too long */
+#define	ENOEXEC 8	/* Exec format error */
+#define	EBADF 9		/* Bad file number */
+#define	ECHILD 10	/* No children */
+#define	EAGAIN 11	/* No more processes */
+#define	ENOMEM 12	/* Not enough space */
+#define	EACCES 13	/* Permission denied */
+#define	EFAULT 14	/* Bad address */
+#ifdef __LINUX_ERRNO_EXTENSIONS__
+#define	ENOTBLK 15	/* Block device required */
+#endif
+#define	EBUSY 16	/* Device or resource busy */
+#define	EEXIST 17	/* File exists */
+#define	EXDEV 18	/* Cross-device link */
+#define	ENODEV 19	/* No such device */
+#define	ENOTDIR 20	/* Not a directory */
+#define	EISDIR 21	/* Is a directory */
+#define	EINVAL 22	/* Invalid argument */
+#define	ENFILE 23	/* Too many open files in system */
+#define	EMFILE 24	/* File descriptor value too large */
+#define	ENOTTY 25	/* Not a character device */
+#define	ETXTBSY 26	/* Text file busy */
+#define	EFBIG 27	/* File too large */
+#define	ENOSPC 28	/* No space left on device */
+#define	ESPIPE 29	/* Illegal seek */
+#define	EROFS 30	/* Read-only file system */
+#define	EMLINK 31	/* Too many links */
+#define	EPIPE 32	/* Broken pipe */
+#define	EDOM 33		/* Mathematics argument out of domain of function */
+#define	ERANGE 34	/* Result too large */
+#define	ENOMSG 35	/* No message of desired type */
+#define	EIDRM 36	/* Identifier removed */
+#ifdef __LINUX_ERRNO_EXTENSIONS__
+#define	ECHRNG 37	/* Channel number out of range */
+#define	EL2NSYNC 38	/* Level 2 not synchronized */
+#define	EL3HLT 39	/* Level 3 halted */
+#define	EL3RST 40	/* Level 3 reset */
+#define	ELNRNG 41	/* Link number out of range */
+#define	EUNATCH 42	/* Protocol driver not attached */
+#define	ENOCSI 43	/* No CSI structure available */
+#define	EL2HLT 44	/* Level 2 halted */
+#endif
+#define	EDEADLK 45	/* Deadlock */
+#define	ENOLCK 46	/* No lock */
+#ifdef __LINUX_ERRNO_EXTENSIONS__
+#define EBADE 50	/* Invalid exchange */
+#define EBADR 51	/* Invalid request descriptor */
+#define EXFULL 52	/* Exchange full */
+#define ENOANO 53	/* No anode */
+#define EBADRQC 54	/* Invalid request code */
+#define EBADSLT 55	/* Invalid slot */
+#define EDEADLOCK 56	/* File locking deadlock error */
+#define EBFONT 57	/* Bad font file fmt */
+#endif
+#define ENOSTR 60	/* Not a stream */
+#define ENODATA 61	/* No data (for no delay io) */
+#define ETIME 62	/* Stream ioctl timeout */
+#define ENOSR 63	/* No stream resources */
+#ifdef __LINUX_ERRNO_EXTENSIONS__
+#define ENONET 64	/* Machine is not on the network */
+#define ENOPKG 65	/* Package not installed */
+#define EREMOTE 66	/* The object is remote */
+#endif
+#define ENOLINK 67	/* Virtual circuit is gone */
+#ifdef __LINUX_ERRNO_EXTENSIONS__
+#define EADV 68		/* Advertise error */
+#define ESRMNT 69	/* Srmount error */
+#define	ECOMM 70	/* Communication error on send */
+#endif
+#define EPROTO 71	/* Protocol error */
+#define	EMULTIHOP 74	/* Multihop attempted */
+#ifdef __LINUX_ERRNO_EXTENSIONS__
+#define	ELBIN 75	/* Inode is remote (not really error) */
+#define	EDOTDOT 76	/* Cross mount point (not really error) */
+#endif
+#define EBADMSG 77	/* Bad message */
+#define EFTYPE 79	/* Inappropriate file type or format */
+#ifdef __LINUX_ERRNO_EXTENSIONS__
+#define ENOTUNIQ 80	/* Given log. name not unique */
+#define EBADFD 81	/* f.d. invalid for this operation */
+#define EREMCHG 82	/* Remote address changed */
+#define ELIBACC 83	/* Can't access a needed shared lib */
+#define ELIBBAD 84	/* Accessing a corrupted shared lib */
+#define ELIBSCN 85	/* .lib section in a.out corrupted */
+#define ELIBMAX 86	/* Attempting to link in too many libs */
+#define ELIBEXEC 87	/* Attempting to exec a shared library */
+#endif
+#define ENOSYS 88	/* Function not implemented */
+#ifdef __CYGWIN__
+#define ENMFILE 89      /* No more files */
+#endif
+#define ENOTEMPTY 90	/* Directory not empty */
+#define ENAMETOOLONG 91	/* File or path name too long */
+#define ELOOP 92	/* Too many symbolic links */
+#define EOPNOTSUPP 95	/* Operation not supported on socket */
+#define EPFNOSUPPORT 96 /* Protocol family not supported */
+#define ECONNRESET 104  /* Connection reset by peer */
+#define ENOBUFS 105	/* No buffer space available */
+#define EAFNOSUPPORT 106 /* Address family not supported by protocol family */
+#define EPROTOTYPE 107	/* Protocol wrong type for socket */
+#define ENOTSOCK 108	/* Socket operation on non-socket */
+#define ENOPROTOOPT 109	/* Protocol not available */
+#ifdef __LINUX_ERRNO_EXTENSIONS__
+#define ESHUTDOWN 110	/* Can't send after socket shutdown */
+#endif
+#define ECONNREFUSED 111	/* Connection refused */
+#define EADDRINUSE 112		/* Address already in use */
+#define ECONNABORTED 113	/* Software caused connection abort */
+#define ENETUNREACH 114		/* Network is unreachable */
+#define ENETDOWN 115		/* Network interface is not configured */
+#define ETIMEDOUT 116		/* Connection timed out */
+#define EHOSTDOWN 117		/* Host is down */
+#define EHOSTUNREACH 118	/* Host is unreachable */
+#define EINPROGRESS 119		/* Connection already in progress */
+#define EALREADY 120		/* Socket already connected */
+#define EDESTADDRREQ 121	/* Destination address required */
+#define EMSGSIZE 122		/* Message too long */
+#define EPROTONOSUPPORT 123	/* Unknown protocol */
+#ifdef __LINUX_ERRNO_EXTENSIONS__
+#define ESOCKTNOSUPPORT 124	/* Socket type not supported */
+#endif
+#define EADDRNOTAVAIL 125	/* Address not available */
+#define ENETRESET 126		/* Connection aborted by network */
+#define EISCONN 127		/* Socket is already connected */
+#define ENOTCONN 128		/* Socket is not connected */
+#define ETOOMANYREFS 129
+#ifdef __LINUX_ERRNO_EXTENSIONS__
+#define EPROCLIM 130
+#define EUSERS 131
+#endif
+#define EDQUOT 132
+#define ESTALE 133
+#define ENOTSUP 134		/* Not supported */
+#ifdef __LINUX_ERRNO_EXTENSIONS__
+#define ENOMEDIUM 135   /* No medium (in tape drive) */
+#endif
+#ifdef __CYGWIN__
+#define ENOSHARE 136    /* No such host or network path */
+#define ECASECLASH 137  /* Filename exists with different case */
+#endif
+#define EILSEQ 138		/* Illegal byte sequence */
+#define EOVERFLOW 139	/* Value too large for defined data type */
+#define ECANCELED 140	/* Operation canceled */
+#define ENOTRECOVERABLE 141	/* State not recoverable */
+#define EOWNERDEAD 142	/* Previous owner died */
+#ifdef __LINUX_ERRNO_EXTENSIONS__
+#define ESTRPIPE 143	/* Streams pipe error */
+#endif
+#define EWOULDBLOCK EAGAIN	/* Operation would block */
+
+#define __ELASTERROR 2000	/* Users can add values starting here */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _SYS_ERRNO_H */
diff --git a/tools/sdk/include/newlib/sys/fcntl.h b/tools/sdk/include/newlib/sys/fcntl.h
new file mode 100644
index 00000000..be85f40c
--- /dev/null
+++ b/tools/sdk/include/newlib/sys/fcntl.h
@@ -0,0 +1,4 @@
+#ifndef _SYS_FCNTL_H_
+#define _SYS_FCNTL_H_
+#include 
+#endif
diff --git a/tools/sdk/include/newlib/sys/features.h b/tools/sdk/include/newlib/sys/features.h
new file mode 100644
index 00000000..1d90921a
--- /dev/null
+++ b/tools/sdk/include/newlib/sys/features.h
@@ -0,0 +1,235 @@
+/*
+ *  Written by Joel Sherrill .
+ *
+ *  COPYRIGHT (c) 1989-2000.
+ *
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  Permission to use, copy, modify, and distribute this software for any
+ *  purpose without fee is hereby granted, provided that this entire notice
+ *  is included in all copies of any software which is or includes a copy
+ *  or modification of this software.
+ *
+ *  THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY.  IN PARTICULAR,  THE AUTHOR MAKES NO REPRESENTATION
+ *  OR WARRANTY OF ANY KIND CONCERNING THE MERCHANTABILITY OF THIS
+ *  SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR PURPOSE.
+ *
+ *  $Id$
+ */
+
+#ifndef _SYS_FEATURES_H
+#define _SYS_FEATURES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Macros to determine that newlib is being used.  Put in this header to 
+ * be similar to where glibc stores its version of these macros.
+ */
+#define __NEWLIB__  		2
+#define __NEWLIB_MINOR__  	1
+
+/* Macro to test version of GCC.  Returns 0 for non-GCC or too old GCC. */
+#ifndef __GNUC_PREREQ
+# if defined __GNUC__ && defined __GNUC_MINOR__
+#  define __GNUC_PREREQ(maj, min) \
+	((__GNUC__ << 16) + __GNUC_MINOR__ >= ((maj) << 16) + (min))
+# else
+#  define __GNUC_PREREQ(maj, min) 0
+# endif
+#endif /* __GNUC_PREREQ */
+/* Version with trailing underscores for BSD compatibility. */
+#define	__GNUC_PREREQ__(ma, mi)	__GNUC_PREREQ(ma, mi)
+
+/* RTEMS adheres to POSIX -- 1003.1b with some features from annexes.  */
+
+#ifdef __rtems__
+#define _POSIX_JOB_CONTROL     		1
+#define _POSIX_SAVED_IDS       		1
+#define _POSIX_VERSION			199309L
+#define _POSIX_ASYNCHRONOUS_IO		1
+#define _POSIX_FSYNC			1
+#define _POSIX_MAPPED_FILES		1
+#define _POSIX_MEMLOCK			1
+#define _POSIX_MEMLOCK_RANGE		1
+#define _POSIX_MEMORY_PROTECTION	1
+#define _POSIX_MESSAGE_PASSING		1
+#define _POSIX_MONOTONIC_CLOCK		200112L
+#define _POSIX_PRIORITIZED_IO		1
+#define _POSIX_PRIORITY_SCHEDULING	1
+#define _POSIX_REALTIME_SIGNALS		1
+#define _POSIX_SEMAPHORES		1
+/* #define _POSIX_SHARED_MEMORY_OBJECTS	1 */
+#define _POSIX_SYNCHRONIZED_IO		1
+#define _POSIX_TIMERS			1
+#define _POSIX_BARRIERS                 200112L
+#define _POSIX_READER_WRITER_LOCKS      200112L
+#define _POSIX_SPIN_LOCKS               200112L
+
+
+/* In P1003.1b but defined by drafts at least as early as P1003.1c/D10  */
+#define _POSIX_THREADS				1
+#define _POSIX_THREAD_ATTR_STACKADDR		1
+#define _POSIX_THREAD_ATTR_STACKSIZE		1
+#define _POSIX_THREAD_PRIORITY_SCHEDULING	1
+#define _POSIX_THREAD_PRIO_INHERIT		1
+#define _POSIX_THREAD_PRIO_PROTECT		1
+#define _POSIX_THREAD_PROCESS_SHARED		1
+#define _POSIX_THREAD_SAFE_FUNCTIONS		1
+
+/* P1003.4b/D8 defines the constants below this comment. */
+#define _POSIX_SPAWN				1
+#define _POSIX_TIMEOUTS				1
+#define _POSIX_CPUTIME				1
+#define _POSIX_THREAD_CPUTIME			1
+#define _POSIX_SPORADIC_SERVER			1
+#define _POSIX_THREAD_SPORADIC_SERVER		1
+#define _POSIX_DEVICE_CONTROL			1
+#define _POSIX_DEVCTL_DIRECTION			1
+#define _POSIX_INTERRUPT_CONTROL		1
+#define _POSIX_ADVISORY_INFO			1
+
+/* UNIX98 added some new pthread mutex attributes */
+#define _UNIX98_THREAD_MUTEX_ATTRIBUTES         1
+
+#endif
+
+/* XMK loosely adheres to POSIX -- 1003.1 */
+#ifdef __XMK__
+#define _POSIX_THREADS				1
+#define _POSIX_THREAD_PRIORITY_SCHEDULING	1
+#endif
+
+
+#ifdef __svr4__
+# define _POSIX_JOB_CONTROL     1
+# define _POSIX_SAVED_IDS       1
+# define _POSIX_VERSION 199009L
+#endif
+
+#ifdef __CYGWIN__
+
+#if !defined(__STRICT_ANSI__) || defined(__cplusplus) || __STDC_VERSION__ >= 199901L
+#define _POSIX_VERSION				200112L
+#define _POSIX2_VERSION				200112L
+#define _XOPEN_VERSION				   600
+
+#define _POSIX_ADVISORY_INFO			200112L
+/* #define _POSIX_ASYNCHRONOUS_IO		    -1 */
+/* #define _POSIX_BARRIERS			    -1 */
+#define _POSIX_CHOWN_RESTRICTED			     1
+#define _POSIX_CLOCK_SELECTION			200112L
+#define _POSIX_CPUTIME			    	200112L
+#define _POSIX_FSYNC				200112L
+#define _POSIX_IPV6				200112L
+#define _POSIX_JOB_CONTROL			     1
+#define _POSIX_MAPPED_FILES			200112L
+/* #define _POSIX_MEMLOCK			    -1 */
+#define _POSIX_MEMLOCK_RANGE			200112L
+#define _POSIX_MEMORY_PROTECTION		200112L
+#define _POSIX_MESSAGE_PASSING			200112L
+#define _POSIX_MONOTONIC_CLOCK			200112L
+#define _POSIX_NO_TRUNC				     1
+/* #define _POSIX_PRIORITIZED_IO		    -1 */
+#define _POSIX_PRIORITY_SCHEDULING		200112L
+#define _POSIX_RAW_SOCKETS			200112L
+#define _POSIX_READER_WRITER_LOCKS		200112L
+#define _POSIX_REALTIME_SIGNALS			200112L
+#define _POSIX_REGEXP				     1
+#define _POSIX_SAVED_IDS			     1
+#define _POSIX_SEMAPHORES			200112L
+#define _POSIX_SHARED_MEMORY_OBJECTS		200112L 
+#define _POSIX_SHELL				     1
+/* #define _POSIX_SPAWN				    -1 */
+#define _POSIX_SPIN_LOCKS			    200112L
+/* #define _POSIX_SPORADIC_SERVER		    -1 */
+#define _POSIX_SYNCHRONIZED_IO			200112L
+#define _POSIX_THREAD_ATTR_STACKADDR		200112L
+#define _POSIX_THREAD_ATTR_STACKSIZE		200112L
+#define _POSIX_THREAD_CPUTIME			200112L
+/* #define _POSIX_THREAD_PRIO_INHERIT		    -1 */
+/* #define _POSIX_THREAD_PRIO_PROTECT		    -1 */
+#define _POSIX_THREAD_PRIORITY_SCHEDULING	200112L
+#define _POSIX_THREAD_PROCESS_SHARED		200112L
+#define _POSIX_THREAD_SAFE_FUNCTIONS		200112L
+/* #define _POSIX_THREAD_SPORADIC_SERVER	    -1 */
+#define _POSIX_THREADS				200112L
+/* #define _POSIX_TIMEOUTS			    -1 */
+#define _POSIX_TIMERS				     1
+/* #define _POSIX_TRACE				    -1 */
+/* #define _POSIX_TRACE_EVENT_FILTER		    -1 */
+/* #define _POSIX_TRACE_INHERIT			    -1 */
+/* #define _POSIX_TRACE_LOG			    -1 */
+/* #define _POSIX_TYPED_MEMORY_OBJECTS		    -1 */
+#define _POSIX_VDISABLE				   '\0'
+#define _POSIX2_C_BIND				200112L
+#define _POSIX2_C_DEV				200112L
+#define _POSIX2_CHAR_TERM			200112L
+/* #define _POSIX2_FORT_DEV			    -1 */
+/* #define _POSIX2_FORT_RUN			    -1 */
+/* #define _POSIX2_LOCALEDEF			    -1 */
+/* #define _POSIX2_PBS				    -1 */
+/* #define _POSIX2_PBS_ACCOUNTING		    -1 */
+/* #define _POSIX2_PBS_CHECKPOINT		    -1 */
+/* #define _POSIX2_PBS_LOCATE			    -1 */
+/* #define _POSIX2_PBS_MESSAGE			    -1 */
+/* #define _POSIX2_PBS_TRACK			    -1 */
+#define _POSIX2_SW_DEV				200112L
+#define _POSIX2_UPE				200112L
+#define _POSIX_V6_ILP32_OFF32			    -1
+#ifdef __LP64__
+#define _POSIX_V6_ILP32_OFFBIG			    -1
+#define _POSIX_V6_LP64_OFF64			     1
+#define _POSIX_V6_LPBIG_OFFBIG			     1
+#else
+#define _POSIX_V6_ILP32_OFFBIG			     1
+#define _POSIX_V6_LP64_OFF64			    -1
+#define _POSIX_V6_LPBIG_OFFBIG			    -1
+#endif
+#define _XBS5_ILP32_OFF32			_POSIX_V6_ILP32_OFF32
+#define _XBS5_ILP32_OFFBIG			_POSIX_V6_ILP32_OFFBIG
+#define _XBS5_LP64_OFF64			_POSIX_V6_LP64_OFF64
+#define _XBS5_LPBIG_OFFBIG			_POSIX_V6_LPBIG_OFFBIG
+#define _XOPEN_CRYPT				     1
+#define _XOPEN_ENH_I18N				     1
+/* #define _XOPEN_LEGACY			    -1 */
+/* #define _XOPEN_REALTIME			    -1 */
+/* #define _XOPEN_REALTIME_THREADS		    -1 */
+#define _XOPEN_SHM				     1
+/* #define _XOPEN_STREAMS			    -1 */
+/* #define _XOPEN_UNIX				    -1 */
+
+#endif /* !__STRICT_ANSI__ || __cplusplus || __STDC_VERSION__ >= 199901L */
+
+/* The value corresponds to UNICODE version 4.0, which is the version
+   supported by XP.  Newlib supports 5.2 (2011) but so far Cygwin needs
+   the MS conversions for double-byte charsets. */
+#define __STDC_ISO_10646__ 200305L
+
+#endif /* __CYGWIN__ */
+
+/* Per the permission given in POSIX.1-2008 section 2.2.1, define
+ * _POSIX_C_SOURCE if _XOPEN_SOURCE is defined and _POSIX_C_SOURCE is not.
+ * (_XOPEN_SOURCE indicates that XSI extensions are desired by an application.)
+ * This permission is first granted in 2008, but use it for older ones, also.
+ * Allow for _XOPEN_SOURCE to be empty (from the earliest form of it, before it
+ * was required to have specific values).
+ */
+#if !defined(_POSIX_C_SOURCE)  &&  defined(_XOPEN_SOURCE) 
+  #if (_XOPEN_SOURCE - 0) == 700	/* POSIX.1-2008 */
+    #define _POSIX_C_SOURCE       200809L
+   #elif (_XOPEN_SOURCE - 0) == 600	/* POSIX.1-2001 or 2004 */
+    #define _POSIX_C_SOURCE       200112L
+   #elif (_XOPEN_SOURCE - 0) == 500	/* POSIX.1-1995 */
+    #define _POSIX_C_SOURCE       199506L
+   #elif (_XOPEN_SOURCE - 0) < 500	/* really old */
+    #define _POSIX_C_SOURCE       2
+  #endif
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _SYS_FEATURES_H */
diff --git a/tools/sdk/include/newlib/sys/file.h b/tools/sdk/include/newlib/sys/file.h
new file mode 100644
index 00000000..be88c6a5
--- /dev/null
+++ b/tools/sdk/include/newlib/sys/file.h
@@ -0,0 +1,33 @@
+/* Copyright (c) 2005-2006 Tensilica Inc.  ALL RIGHTS RESERVED.
+
+   Redistribution and use in source and binary forms, with or without 
+   modification, are permitted provided that the following conditions are met: 
+
+   1. Redistributions of source code must retain the above copyright 
+      notice, this list of conditions and the following disclaimer.
+
+   2. Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+   IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+   TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+   PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL TENSILICA
+   INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+   EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+   PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+   PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+   LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+   NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  */
+
+#include 
+
+/* Alternate names for values for the WHENCE argument to `lseek'.
+   These are the same as SEEK_SET, SEEK_CUR, and SEEK_END, respectively. */
+#ifndef L_SET
+#define L_SET   0       /* Seek from beginning of file.  */
+#define L_INCR  1       /* Seek from current position.  */
+#define L_XTND  2       /* Seek from end of file.  */
+#endif
diff --git a/tools/sdk/include/newlib/sys/iconvnls.h b/tools/sdk/include/newlib/sys/iconvnls.h
new file mode 100644
index 00000000..09ea1831
--- /dev/null
+++ b/tools/sdk/include/newlib/sys/iconvnls.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2003-2004, Artem B. Bityuckiy.
+ * Rights transferred to Franklin Electronic Publishers.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Funtions, macros, etc implimented in iconv library but used by other
+ * NLS-related subsystems too.
+ */
+#ifndef __SYS_ICONVNLS_H__
+#define __SYS_ICONVNLS_H__
+
+#include <_ansi.h>
+#include 
+#include 
+#include 
+
+/* Iconv data path environment variable name */
+#define NLS_ENVVAR_NAME  "NLSPATH"
+/* Default NLSPATH value */
+#define ICONV_DEFAULT_NLSPATH "/usr/locale"
+/* Direction markers */
+#define ICONV_NLS_FROM 0
+#define ICONV_NLS_TO   1
+
+_VOID
+_EXFUN(_iconv_nls_get_state, (iconv_t cd, mbstate_t *ps, int direction));
+
+int
+_EXFUN(_iconv_nls_set_state, (iconv_t cd, mbstate_t *ps, int direction));
+
+int
+_EXFUN(_iconv_nls_is_stateful, (iconv_t cd, int direction));
+
+int
+_EXFUN(_iconv_nls_get_mb_cur_max, (iconv_t cd, int direction));
+
+size_t
+_EXFUN(_iconv_nls_conv, (struct _reent *rptr, iconv_t cd,
+                        _CONST char **inbuf, size_t *inbytesleft,
+                        char **outbuf, size_t *outbytesleft));
+
+_CONST char *
+_EXFUN(_iconv_nls_construct_filename, (struct _reent *rptr, _CONST char *file,
+                                      _CONST char *dir, _CONST char *ext));
+
+
+int
+_EXFUN(_iconv_nls_open, (struct _reent *rptr, _CONST char *encoding,
+                        iconv_t *towc, iconv_t *fromwc, int flag));
+
+char *
+_EXFUN(_iconv_resolve_encoding_name, (struct _reent *rptr, _CONST char *ca));
+
+#endif /* __SYS_ICONVNLS_H__ */
+
diff --git a/tools/sdk/include/newlib/sys/lock.h b/tools/sdk/include/newlib/sys/lock.h
new file mode 100644
index 00000000..0ff34758
--- /dev/null
+++ b/tools/sdk/include/newlib/sys/lock.h
@@ -0,0 +1,50 @@
+#ifndef _XTENSA_LOCK_H__
+#define _XTENSA_LOCK_H__
+
+/* generic lock implementation.
+
+   Weak linked stub _lock functions in lock.c, can be
+   replaced with a lock implementation at link time.
+
+ */
+
+typedef int _lock_t;
+typedef _lock_t _LOCK_RECURSIVE_T;
+typedef _lock_t _LOCK_T;
+
+#include <_ansi.h>
+
+/* NOTE: some parts of newlib statically initialise locks via
+   __LOCK_INIT, some initialise at runtime via __lock_init. So need to
+   support possibility that a _lock_t is null during first call to
+   _lock_acquire or _lock_try_acquire.
+
+   Lock functions all take a pointer to the _lock_t entry, so the
+   value stored there can be manipulated.
+*/
+#define __LOCK_INIT(CLASS,NAME) CLASS _lock_t NAME = 0;
+#define __LOCK_INIT_RECURSIVE(CLASS,NAME) CLASS _lock_t NAME = 0;
+
+void _lock_init(_lock_t *lock);
+void _lock_init_recursive(_lock_t *lock);
+void _lock_close(_lock_t *lock);
+void _lock_close_recursive(_lock_t *lock);
+void _lock_acquire(_lock_t *lock);
+void _lock_acquire_recursive(_lock_t *lock);
+int _lock_try_acquire(_lock_t *lock);
+int _lock_try_acquire_recursive(_lock_t *lock);
+void _lock_release(_lock_t *lock);
+void _lock_release_recursive(_lock_t *lock);
+
+#define __lock_init(lock) _lock_init(&(lock))
+#define __lock_init_recursive(lock) _lock_init_recursive(&(lock))
+#define __lock_close(lock) _lock_close(&(lock))
+#define __lock_close_recursive(lock) _lock_close_recursive(&(lock))
+#define __lock_acquire(lock) _lock_acquire(&(lock))
+#define __lock_acquire_recursive(lock) _lock_acquire_recursive(&(lock))
+#define __lock_try_acquire(lock) _lock_try_acquire(&(lock))
+#define __lock_try_acquire_recursive(lock) _lock_try_acquire_recursive(&(lock))
+#define __lock_release(lock) _lock_release(&(lock))
+#define __lock_release_recursive(lock) _lock_release_recursive(&(lock))
+
+#endif /* _XTENSA_LOCK_H__ */
diff --git a/tools/sdk/include/newlib/sys/param.h b/tools/sdk/include/newlib/sys/param.h
new file mode 100644
index 00000000..ef203d3e
--- /dev/null
+++ b/tools/sdk/include/newlib/sys/param.h
@@ -0,0 +1,28 @@
+/* This is a dummy  file, not customized for any
+   particular system.  If there is a param.h in libc/sys/SYSDIR/sys,
+   it will override this one.  */
+
+#ifndef _SYS_PARAM_H
+# define _SYS_PARAM_H
+
+#include 
+#include 
+#include 
+#include 
+
+#ifndef HZ
+# define HZ (60)
+#endif
+#ifndef NOFILE
+# define NOFILE	(60)
+#endif
+#ifndef PATHSIZE
+# define PATHSIZE (1024)
+#endif
+
+#define MAXPATHLEN PATH_MAX
+
+#define MAX(a,b) ((a) > (b) ? (a) : (b))
+#define MIN(a,b) ((a) < (b) ? (a) : (b))
+
+#endif
diff --git a/tools/sdk/include/newlib/sys/queue.h b/tools/sdk/include/newlib/sys/queue.h
new file mode 100644
index 00000000..4bc7dac0
--- /dev/null
+++ b/tools/sdk/include/newlib/sys/queue.h
@@ -0,0 +1,691 @@
+/*-
+ * Copyright (c) 1991, 1993
+ *	The Regents of the University of California.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)queue.h	8.5 (Berkeley) 8/20/94
+ * $FreeBSD$
+ */
+
+#ifndef _SYS_QUEUE_H_
+#define	_SYS_QUEUE_H_
+
+#include 
+
+/*
+ * This file defines four types of data structures: singly-linked lists,
+ * singly-linked tail queues, lists and tail queues.
+ *
+ * A singly-linked list is headed by a single forward pointer. The elements
+ * are singly linked for minimum space and pointer manipulation overhead at
+ * the expense of O(n) removal for arbitrary elements. New elements can be
+ * added to the list after an existing element or at the head of the list.
+ * Elements being removed from the head of the list should use the explicit
+ * macro for this purpose for optimum efficiency. A singly-linked list may
+ * only be traversed in the forward direction.  Singly-linked lists are ideal
+ * for applications with large datasets and few or no removals or for
+ * implementing a LIFO queue.
+ *
+ * A singly-linked tail queue is headed by a pair of pointers, one to the
+ * head of the list and the other to the tail of the list. The elements are
+ * singly linked for minimum space and pointer manipulation overhead at the
+ * expense of O(n) removal for arbitrary elements. New elements can be added
+ * to the list after an existing element, at the head of the list, or at the
+ * end of the list. Elements being removed from the head of the tail queue
+ * should use the explicit macro for this purpose for optimum efficiency.
+ * A singly-linked tail queue may only be traversed in the forward direction.
+ * Singly-linked tail queues are ideal for applications with large datasets
+ * and few or no removals or for implementing a FIFO queue.
+ *
+ * A list is headed by a single forward pointer (or an array of forward
+ * pointers for a hash table header). The elements are doubly linked
+ * so that an arbitrary element can be removed without a need to
+ * traverse the list. New elements can be added to the list before
+ * or after an existing element or at the head of the list. A list
+ * may be traversed in either direction.
+ *
+ * A tail queue is headed by a pair of pointers, one to the head of the
+ * list and the other to the tail of the list. The elements are doubly
+ * linked so that an arbitrary element can be removed without a need to
+ * traverse the list. New elements can be added to the list before or
+ * after an existing element, at the head of the list, or at the end of
+ * the list. A tail queue may be traversed in either direction.
+ *
+ * For details on the use of these macros, see the queue(3) manual page.
+ *
+ *
+ *				SLIST	LIST	STAILQ	TAILQ
+ * _HEAD			+	+	+	+
+ * _HEAD_INITIALIZER		+	+	+	+
+ * _ENTRY			+	+	+	+
+ * _INIT			+	+	+	+
+ * _EMPTY			+	+	+	+
+ * _FIRST			+	+	+	+
+ * _NEXT			+	+	+	+
+ * _PREV			-	+	-	+
+ * _LAST			-	-	+	+
+ * _FOREACH			+	+	+	+
+ * _FOREACH_SAFE		+	+	+	+
+ * _FOREACH_REVERSE		-	-	-	+
+ * _FOREACH_REVERSE_SAFE	-	-	-	+
+ * _INSERT_HEAD			+	+	+	+
+ * _INSERT_BEFORE		-	+	-	+
+ * _INSERT_AFTER		+	+	+	+
+ * _INSERT_TAIL			-	-	+	+
+ * _CONCAT			-	-	+	+
+ * _REMOVE_AFTER		+	-	+	-
+ * _REMOVE_HEAD			+	-	+	-
+ * _REMOVE			+	+	+	+
+ * _SWAP			+	+	+	+
+ *
+ */
+#ifdef QUEUE_MACRO_DEBUG
+/* Store the last 2 places the queue element or head was altered */
+struct qm_trace {
+	unsigned long	 lastline;
+	unsigned long	 prevline;
+	const char	*lastfile;
+	const char	*prevfile;
+};
+
+#define	TRACEBUF	struct qm_trace trace;
+#define	TRACEBUF_INITIALIZER	{ __FILE__, __LINE__, NULL, 0 } ,
+#define	TRASHIT(x)	do {(x) = (void *)-1;} while (0)
+#define	QMD_SAVELINK(name, link)	void **name = (void *)&(link)
+
+#define	QMD_TRACE_HEAD(head) do {					\
+	(head)->trace.prevline = (head)->trace.lastline;		\
+	(head)->trace.prevfile = (head)->trace.lastfile;		\
+	(head)->trace.lastline = __LINE__;				\
+	(head)->trace.lastfile = __FILE__;				\
+} while (0)
+
+#define	QMD_TRACE_ELEM(elem) do {					\
+	(elem)->trace.prevline = (elem)->trace.lastline;		\
+	(elem)->trace.prevfile = (elem)->trace.lastfile;		\
+	(elem)->trace.lastline = __LINE__;				\
+	(elem)->trace.lastfile = __FILE__;				\
+} while (0)
+
+#else
+#define	QMD_TRACE_ELEM(elem)
+#define	QMD_TRACE_HEAD(head)
+#define	QMD_SAVELINK(name, link)
+#define	TRACEBUF
+#define	TRACEBUF_INITIALIZER
+#define	TRASHIT(x)
+#endif	/* QUEUE_MACRO_DEBUG */
+
+/*
+ * Singly-linked List declarations.
+ */
+#define	SLIST_HEAD(name, type)						\
+struct name {								\
+	struct type *slh_first;	/* first element */			\
+}
+
+#define	SLIST_HEAD_INITIALIZER(head)					\
+	{ NULL }
+
+#define	SLIST_ENTRY(type)						\
+struct {								\
+	struct type *sle_next;	/* next element */			\
+}
+
+/*
+ * Singly-linked List functions.
+ */
+#define	SLIST_EMPTY(head)	((head)->slh_first == NULL)
+
+#define	SLIST_FIRST(head)	((head)->slh_first)
+
+#define	SLIST_FOREACH(var, head, field)					\
+	for ((var) = SLIST_FIRST((head));				\
+	    (var);							\
+	    (var) = SLIST_NEXT((var), field))
+
+#define	SLIST_FOREACH_SAFE(var, head, field, tvar)			\
+	for ((var) = SLIST_FIRST((head));				\
+	    (var) && ((tvar) = SLIST_NEXT((var), field), 1);		\
+	    (var) = (tvar))
+
+#define	SLIST_FOREACH_PREVPTR(var, varp, head, field)			\
+	for ((varp) = &SLIST_FIRST((head));				\
+	    ((var) = *(varp)) != NULL;					\
+	    (varp) = &SLIST_NEXT((var), field))
+
+#define	SLIST_INIT(head) do {						\
+	SLIST_FIRST((head)) = NULL;					\
+} while (0)
+
+#define	SLIST_INSERT_AFTER(slistelm, elm, field) do {			\
+	SLIST_NEXT((elm), field) = SLIST_NEXT((slistelm), field);	\
+	SLIST_NEXT((slistelm), field) = (elm);				\
+} while (0)
+
+#define	SLIST_INSERT_HEAD(head, elm, field) do {			\
+	SLIST_NEXT((elm), field) = SLIST_FIRST((head));			\
+	SLIST_FIRST((head)) = (elm);					\
+} while (0)
+
+#define	SLIST_NEXT(elm, field)	((elm)->field.sle_next)
+
+#define	SLIST_REMOVE(head, elm, type, field) do {			\
+	QMD_SAVELINK(oldnext, (elm)->field.sle_next);			\
+	if (SLIST_FIRST((head)) == (elm)) {				\
+		SLIST_REMOVE_HEAD((head), field);			\
+	}								\
+	else {								\
+		struct type *curelm = SLIST_FIRST((head));		\
+		while (SLIST_NEXT(curelm, field) != (elm))		\
+			curelm = SLIST_NEXT(curelm, field);		\
+		SLIST_REMOVE_AFTER(curelm, field);			\
+	}								\
+	TRASHIT(*oldnext);						\
+} while (0)
+
+#define SLIST_REMOVE_AFTER(elm, field) do {				\
+	SLIST_NEXT(elm, field) =					\
+	    SLIST_NEXT(SLIST_NEXT(elm, field), field);			\
+} while (0)
+
+#define	SLIST_REMOVE_HEAD(head, field) do {				\
+	SLIST_FIRST((head)) = SLIST_NEXT(SLIST_FIRST((head)), field);	\
+} while (0)
+
+#define SLIST_SWAP(head1, head2, type) do {				\
+	struct type *swap_first = SLIST_FIRST(head1);			\
+	SLIST_FIRST(head1) = SLIST_FIRST(head2);			\
+	SLIST_FIRST(head2) = swap_first;				\
+} while (0)
+
+/*
+ * Singly-linked Tail queue declarations.
+ */
+#define	STAILQ_HEAD(name, type)						\
+struct name {								\
+	struct type *stqh_first;/* first element */			\
+	struct type **stqh_last;/* addr of last next element */		\
+}
+
+#define	STAILQ_HEAD_INITIALIZER(head)					\
+	{ NULL, &(head).stqh_first }
+
+#define	STAILQ_ENTRY(type)						\
+struct {								\
+	struct type *stqe_next;	/* next element */			\
+}
+
+/*
+ * Singly-linked Tail queue functions.
+ */
+#define	STAILQ_CONCAT(head1, head2) do {				\
+	if (!STAILQ_EMPTY((head2))) {					\
+		*(head1)->stqh_last = (head2)->stqh_first;		\
+		(head1)->stqh_last = (head2)->stqh_last;		\
+		STAILQ_INIT((head2));					\
+	}								\
+} while (0)
+
+#define	STAILQ_EMPTY(head)	((head)->stqh_first == NULL)
+
+#define	STAILQ_FIRST(head)	((head)->stqh_first)
+
+#define	STAILQ_FOREACH(var, head, field)				\
+	for((var) = STAILQ_FIRST((head));				\
+	   (var);							\
+	   (var) = STAILQ_NEXT((var), field))
+
+
+#define	STAILQ_FOREACH_SAFE(var, head, field, tvar)			\
+	for ((var) = STAILQ_FIRST((head));				\
+	    (var) && ((tvar) = STAILQ_NEXT((var), field), 1);		\
+	    (var) = (tvar))
+
+#define	STAILQ_INIT(head) do {						\
+	STAILQ_FIRST((head)) = NULL;					\
+	(head)->stqh_last = &STAILQ_FIRST((head));			\
+} while (0)
+
+#define	STAILQ_INSERT_AFTER(head, tqelm, elm, field) do {		\
+	if ((STAILQ_NEXT((elm), field) = STAILQ_NEXT((tqelm), field)) == NULL)\
+		(head)->stqh_last = &STAILQ_NEXT((elm), field);		\
+	STAILQ_NEXT((tqelm), field) = (elm);				\
+} while (0)
+
+#define	STAILQ_INSERT_HEAD(head, elm, field) do {			\
+	if ((STAILQ_NEXT((elm), field) = STAILQ_FIRST((head))) == NULL)	\
+		(head)->stqh_last = &STAILQ_NEXT((elm), field);		\
+	STAILQ_FIRST((head)) = (elm);					\
+} while (0)
+
+#define	STAILQ_INSERT_TAIL(head, elm, field) do {			\
+	STAILQ_NEXT((elm), field) = NULL;				\
+	*(head)->stqh_last = (elm);					\
+	(head)->stqh_last = &STAILQ_NEXT((elm), field);			\
+} while (0)
+
+#define	STAILQ_LAST(head, type, field)					\
+	(STAILQ_EMPTY((head)) ? NULL :					\
+	    __containerof((head)->stqh_last, struct type, field.stqe_next))
+
+#define	STAILQ_NEXT(elm, field)	((elm)->field.stqe_next)
+
+#define	STAILQ_REMOVE(head, elm, type, field) do {			\
+	QMD_SAVELINK(oldnext, (elm)->field.stqe_next);			\
+	if (STAILQ_FIRST((head)) == (elm)) {				\
+		STAILQ_REMOVE_HEAD((head), field);			\
+	}								\
+	else {								\
+		struct type *curelm = STAILQ_FIRST((head));		\
+		while (STAILQ_NEXT(curelm, field) != (elm))		\
+			curelm = STAILQ_NEXT(curelm, field);		\
+		STAILQ_REMOVE_AFTER(head, curelm, field);		\
+	}								\
+	TRASHIT(*oldnext);						\
+} while (0)
+
+#define STAILQ_REMOVE_AFTER(head, elm, field) do {			\
+	if ((STAILQ_NEXT(elm, field) =					\
+	     STAILQ_NEXT(STAILQ_NEXT(elm, field), field)) == NULL)	\
+		(head)->stqh_last = &STAILQ_NEXT((elm), field);		\
+} while (0)
+
+#define	STAILQ_REMOVE_HEAD(head, field) do {				\
+	if ((STAILQ_FIRST((head)) =					\
+	     STAILQ_NEXT(STAILQ_FIRST((head)), field)) == NULL)		\
+		(head)->stqh_last = &STAILQ_FIRST((head));		\
+} while (0)
+
+#define	STAILQ_REMOVE_HEAD_UNTIL(head, elm, field) do {			\
+	if ((STAILQ_FIRST((head)) = STAILQ_NEXT((elm), field)) == NULL)	\
+		(head)->stqh_last = &STAILQ_FIRST((head));		\
+} while (0)
+
+#define STAILQ_SWAP(head1, head2, type) do {				\
+	struct type *swap_first = STAILQ_FIRST(head1);			\
+	struct type **swap_last = (head1)->stqh_last;			\
+	STAILQ_FIRST(head1) = STAILQ_FIRST(head2);			\
+	(head1)->stqh_last = (head2)->stqh_last;			\
+	STAILQ_FIRST(head2) = swap_first;				\
+	(head2)->stqh_last = swap_last;					\
+	if (STAILQ_EMPTY(head1))					\
+		(head1)->stqh_last = &STAILQ_FIRST(head1);		\
+	if (STAILQ_EMPTY(head2))					\
+		(head2)->stqh_last = &STAILQ_FIRST(head2);		\
+} while (0)
+
+
+/*
+ * List declarations.
+ */
+#define	LIST_HEAD(name, type)						\
+struct name {								\
+	struct type *lh_first;	/* first element */			\
+}
+
+#define	LIST_HEAD_INITIALIZER(head)					\
+	{ NULL }
+
+#define	LIST_ENTRY(type)						\
+struct {								\
+	struct type *le_next;	/* next element */			\
+	struct type **le_prev;	/* address of previous next element */	\
+}
+
+/*
+ * List functions.
+ */
+
+#if (defined(_KERNEL) && defined(INVARIANTS))
+#define	QMD_LIST_CHECK_HEAD(head, field) do {				\
+	if (LIST_FIRST((head)) != NULL &&				\
+	    LIST_FIRST((head))->field.le_prev !=			\
+	     &LIST_FIRST((head)))					\
+		panic("Bad list head %p first->prev != head", (head));	\
+} while (0)
+
+#define	QMD_LIST_CHECK_NEXT(elm, field) do {				\
+	if (LIST_NEXT((elm), field) != NULL &&				\
+	    LIST_NEXT((elm), field)->field.le_prev !=			\
+	     &((elm)->field.le_next))					\
+	     	panic("Bad link elm %p next->prev != elm", (elm));	\
+} while (0)
+
+#define	QMD_LIST_CHECK_PREV(elm, field) do {				\
+	if (*(elm)->field.le_prev != (elm))				\
+		panic("Bad link elm %p prev->next != elm", (elm));	\
+} while (0)
+#else
+#define	QMD_LIST_CHECK_HEAD(head, field)
+#define	QMD_LIST_CHECK_NEXT(elm, field)
+#define	QMD_LIST_CHECK_PREV(elm, field)
+#endif /* (_KERNEL && INVARIANTS) */
+
+#define	LIST_EMPTY(head)	((head)->lh_first == NULL)
+
+#define	LIST_FIRST(head)	((head)->lh_first)
+
+#define	LIST_FOREACH(var, head, field)					\
+	for ((var) = LIST_FIRST((head));				\
+	    (var);							\
+	    (var) = LIST_NEXT((var), field))
+
+#define	LIST_FOREACH_SAFE(var, head, field, tvar)			\
+	for ((var) = LIST_FIRST((head));				\
+	    (var) && ((tvar) = LIST_NEXT((var), field), 1);		\
+	    (var) = (tvar))
+
+#define	LIST_INIT(head) do {						\
+	LIST_FIRST((head)) = NULL;					\
+} while (0)
+
+#define	LIST_INSERT_AFTER(listelm, elm, field) do {			\
+	QMD_LIST_CHECK_NEXT(listelm, field);				\
+	if ((LIST_NEXT((elm), field) = LIST_NEXT((listelm), field)) != NULL)\
+		LIST_NEXT((listelm), field)->field.le_prev =		\
+		    &LIST_NEXT((elm), field);				\
+	LIST_NEXT((listelm), field) = (elm);				\
+	(elm)->field.le_prev = &LIST_NEXT((listelm), field);		\
+} while (0)
+
+#define	LIST_INSERT_BEFORE(listelm, elm, field) do {			\
+	QMD_LIST_CHECK_PREV(listelm, field);				\
+	(elm)->field.le_prev = (listelm)->field.le_prev;		\
+	LIST_NEXT((elm), field) = (listelm);				\
+	*(listelm)->field.le_prev = (elm);				\
+	(listelm)->field.le_prev = &LIST_NEXT((elm), field);		\
+} while (0)
+
+#define	LIST_INSERT_HEAD(head, elm, field) do {				\
+	QMD_LIST_CHECK_HEAD((head), field);				\
+	if ((LIST_NEXT((elm), field) = LIST_FIRST((head))) != NULL)	\
+		LIST_FIRST((head))->field.le_prev = &LIST_NEXT((elm), field);\
+	LIST_FIRST((head)) = (elm);					\
+	(elm)->field.le_prev = &LIST_FIRST((head));			\
+} while (0)
+
+#define	LIST_NEXT(elm, field)	((elm)->field.le_next)
+
+#define	LIST_PREV(elm, head, type, field)				\
+	((elm)->field.le_prev == &LIST_FIRST((head)) ? NULL :		\
+	    __containerof((elm)->field.le_prev, struct type, field.le_next))
+
+#define	LIST_REMOVE(elm, field) do {					\
+	QMD_SAVELINK(oldnext, (elm)->field.le_next);			\
+	QMD_SAVELINK(oldprev, (elm)->field.le_prev);			\
+	QMD_LIST_CHECK_NEXT(elm, field);				\
+	QMD_LIST_CHECK_PREV(elm, field);				\
+	if (LIST_NEXT((elm), field) != NULL)				\
+		LIST_NEXT((elm), field)->field.le_prev = 		\
+		    (elm)->field.le_prev;				\
+	*(elm)->field.le_prev = LIST_NEXT((elm), field);		\
+	TRASHIT(*oldnext);						\
+	TRASHIT(*oldprev);						\
+} while (0)
+
+#define LIST_SWAP(head1, head2, type, field) do {			\
+	struct type *swap_tmp = LIST_FIRST((head1));			\
+	LIST_FIRST((head1)) = LIST_FIRST((head2));			\
+	LIST_FIRST((head2)) = swap_tmp;					\
+	if ((swap_tmp = LIST_FIRST((head1))) != NULL)			\
+		swap_tmp->field.le_prev = &LIST_FIRST((head1));		\
+	if ((swap_tmp = LIST_FIRST((head2))) != NULL)			\
+		swap_tmp->field.le_prev = &LIST_FIRST((head2));		\
+} while (0)
+
+/*
+ * Tail queue declarations.
+ */
+#define	TAILQ_HEAD(name, type)						\
+struct name {								\
+	struct type *tqh_first;	/* first element */			\
+	struct type **tqh_last;	/* addr of last next element */		\
+	TRACEBUF							\
+}
+
+#define	TAILQ_HEAD_INITIALIZER(head)					\
+	{ NULL, &(head).tqh_first, TRACEBUF_INITIALIZER }
+
+#define	TAILQ_ENTRY(type)						\
+struct {								\
+	struct type *tqe_next;	/* next element */			\
+	struct type **tqe_prev;	/* address of previous next element */	\
+	TRACEBUF							\
+}
+
+/*
+ * Tail queue functions.
+ */
+#if (defined(_KERNEL) && defined(INVARIANTS))
+#define	QMD_TAILQ_CHECK_HEAD(head, field) do {				\
+	if (!TAILQ_EMPTY(head) &&					\
+	    TAILQ_FIRST((head))->field.tqe_prev !=			\
+	     &TAILQ_FIRST((head)))					\
+		panic("Bad tailq head %p first->prev != head", (head));	\
+} while (0)
+
+#define	QMD_TAILQ_CHECK_TAIL(head, field) do {				\
+	if (*(head)->tqh_last != NULL)					\
+	    	panic("Bad tailq NEXT(%p->tqh_last) != NULL", (head)); 	\
+} while (0)
+
+#define	QMD_TAILQ_CHECK_NEXT(elm, field) do {				\
+	if (TAILQ_NEXT((elm), field) != NULL &&				\
+	    TAILQ_NEXT((elm), field)->field.tqe_prev !=			\
+	     &((elm)->field.tqe_next))					\
+		panic("Bad link elm %p next->prev != elm", (elm));	\
+} while (0)
+
+#define	QMD_TAILQ_CHECK_PREV(elm, field) do {				\
+	if (*(elm)->field.tqe_prev != (elm))				\
+		panic("Bad link elm %p prev->next != elm", (elm));	\
+} while (0)
+#else
+#define	QMD_TAILQ_CHECK_HEAD(head, field)
+#define	QMD_TAILQ_CHECK_TAIL(head, headname)
+#define	QMD_TAILQ_CHECK_NEXT(elm, field)
+#define	QMD_TAILQ_CHECK_PREV(elm, field)
+#endif /* (_KERNEL && INVARIANTS) */
+
+#define	TAILQ_CONCAT(head1, head2, field) do {				\
+	if (!TAILQ_EMPTY(head2)) {					\
+		*(head1)->tqh_last = (head2)->tqh_first;		\
+		(head2)->tqh_first->field.tqe_prev = (head1)->tqh_last;	\
+		(head1)->tqh_last = (head2)->tqh_last;			\
+		TAILQ_INIT((head2));					\
+		QMD_TRACE_HEAD(head1);					\
+		QMD_TRACE_HEAD(head2);					\
+	}								\
+} while (0)
+
+#define	TAILQ_EMPTY(head)	((head)->tqh_first == NULL)
+
+#define	TAILQ_FIRST(head)	((head)->tqh_first)
+
+#define	TAILQ_FOREACH(var, head, field)					\
+	for ((var) = TAILQ_FIRST((head));				\
+	    (var);							\
+	    (var) = TAILQ_NEXT((var), field))
+
+#define	TAILQ_FOREACH_SAFE(var, head, field, tvar)			\
+	for ((var) = TAILQ_FIRST((head));				\
+	    (var) && ((tvar) = TAILQ_NEXT((var), field), 1);		\
+	    (var) = (tvar))
+
+#define	TAILQ_FOREACH_REVERSE(var, head, headname, field)		\
+	for ((var) = TAILQ_LAST((head), headname);			\
+	    (var);							\
+	    (var) = TAILQ_PREV((var), headname, field))
+
+#define	TAILQ_FOREACH_REVERSE_SAFE(var, head, headname, field, tvar)	\
+	for ((var) = TAILQ_LAST((head), headname);			\
+	    (var) && ((tvar) = TAILQ_PREV((var), headname, field), 1);	\
+	    (var) = (tvar))
+
+#define	TAILQ_INIT(head) do {						\
+	TAILQ_FIRST((head)) = NULL;					\
+	(head)->tqh_last = &TAILQ_FIRST((head));			\
+	QMD_TRACE_HEAD(head);						\
+} while (0)
+
+#define	TAILQ_INSERT_AFTER(head, listelm, elm, field) do {		\
+	QMD_TAILQ_CHECK_NEXT(listelm, field);				\
+	if ((TAILQ_NEXT((elm), field) = TAILQ_NEXT((listelm), field)) != NULL)\
+		TAILQ_NEXT((elm), field)->field.tqe_prev = 		\
+		    &TAILQ_NEXT((elm), field);				\
+	else {								\
+		(head)->tqh_last = &TAILQ_NEXT((elm), field);		\
+		QMD_TRACE_HEAD(head);					\
+	}								\
+	TAILQ_NEXT((listelm), field) = (elm);				\
+	(elm)->field.tqe_prev = &TAILQ_NEXT((listelm), field);		\
+	QMD_TRACE_ELEM(&(elm)->field);					\
+	QMD_TRACE_ELEM(&listelm->field);				\
+} while (0)
+
+#define	TAILQ_INSERT_BEFORE(listelm, elm, field) do {			\
+	QMD_TAILQ_CHECK_PREV(listelm, field);				\
+	(elm)->field.tqe_prev = (listelm)->field.tqe_prev;		\
+	TAILQ_NEXT((elm), field) = (listelm);				\
+	*(listelm)->field.tqe_prev = (elm);				\
+	(listelm)->field.tqe_prev = &TAILQ_NEXT((elm), field);		\
+	QMD_TRACE_ELEM(&(elm)->field);					\
+	QMD_TRACE_ELEM(&listelm->field);				\
+} while (0)
+
+#define	TAILQ_INSERT_HEAD(head, elm, field) do {			\
+	QMD_TAILQ_CHECK_HEAD(head, field);				\
+	if ((TAILQ_NEXT((elm), field) = TAILQ_FIRST((head))) != NULL)	\
+		TAILQ_FIRST((head))->field.tqe_prev =			\
+		    &TAILQ_NEXT((elm), field);				\
+	else								\
+		(head)->tqh_last = &TAILQ_NEXT((elm), field);		\
+	TAILQ_FIRST((head)) = (elm);					\
+	(elm)->field.tqe_prev = &TAILQ_FIRST((head));			\
+	QMD_TRACE_HEAD(head);						\
+	QMD_TRACE_ELEM(&(elm)->field);					\
+} while (0)
+
+#define	TAILQ_INSERT_TAIL(head, elm, field) do {			\
+	QMD_TAILQ_CHECK_TAIL(head, field);				\
+	TAILQ_NEXT((elm), field) = NULL;				\
+	(elm)->field.tqe_prev = (head)->tqh_last;			\
+	*(head)->tqh_last = (elm);					\
+	(head)->tqh_last = &TAILQ_NEXT((elm), field);			\
+	QMD_TRACE_HEAD(head);						\
+	QMD_TRACE_ELEM(&(elm)->field);					\
+} while (0)
+
+#define	TAILQ_LAST(head, headname)					\
+	(*(((struct headname *)((head)->tqh_last))->tqh_last))
+
+#define	TAILQ_NEXT(elm, field) ((elm)->field.tqe_next)
+
+#define	TAILQ_PREV(elm, headname, field)				\
+	(*(((struct headname *)((elm)->field.tqe_prev))->tqh_last))
+
+#define	TAILQ_REMOVE(head, elm, field) do {				\
+	QMD_SAVELINK(oldnext, (elm)->field.tqe_next);			\
+	QMD_SAVELINK(oldprev, (elm)->field.tqe_prev);			\
+	QMD_TAILQ_CHECK_NEXT(elm, field);				\
+	QMD_TAILQ_CHECK_PREV(elm, field);				\
+	if ((TAILQ_NEXT((elm), field)) != NULL)				\
+		TAILQ_NEXT((elm), field)->field.tqe_prev = 		\
+		    (elm)->field.tqe_prev;				\
+	else {								\
+		(head)->tqh_last = (elm)->field.tqe_prev;		\
+		QMD_TRACE_HEAD(head);					\
+	}								\
+	*(elm)->field.tqe_prev = TAILQ_NEXT((elm), field);		\
+	TRASHIT(*oldnext);						\
+	TRASHIT(*oldprev);						\
+	QMD_TRACE_ELEM(&(elm)->field);					\
+} while (0)
+
+#define TAILQ_SWAP(head1, head2, type, field) do {			\
+	struct type *swap_first = (head1)->tqh_first;			\
+	struct type **swap_last = (head1)->tqh_last;			\
+	(head1)->tqh_first = (head2)->tqh_first;			\
+	(head1)->tqh_last = (head2)->tqh_last;				\
+	(head2)->tqh_first = swap_first;				\
+	(head2)->tqh_last = swap_last;					\
+	if ((swap_first = (head1)->tqh_first) != NULL)			\
+		swap_first->field.tqe_prev = &(head1)->tqh_first;	\
+	else								\
+		(head1)->tqh_last = &(head1)->tqh_first;		\
+	if ((swap_first = (head2)->tqh_first) != NULL)			\
+		swap_first->field.tqe_prev = &(head2)->tqh_first;	\
+	else								\
+		(head2)->tqh_last = &(head2)->tqh_first;		\
+} while (0)
+
+#ifdef _KERNEL
+
+/*
+ * XXX insque() and remque() are an old way of handling certain queues.
+ * They bogusly assumes that all queue heads look alike.
+ */
+
+struct quehead {
+	struct quehead *qh_link;
+	struct quehead *qh_rlink;
+};
+
+#ifdef	__GNUC__
+
+static __inline void
+insque(void *a, void *b)
+{
+	struct quehead *element = (struct quehead *)a,
+		 *head = (struct quehead *)b;
+
+	element->qh_link = head->qh_link;
+	element->qh_rlink = head;
+	head->qh_link = element;
+	element->qh_link->qh_rlink = element;
+}
+
+static __inline void
+remque(void *a)
+{
+	struct quehead *element = (struct quehead *)a;
+
+	element->qh_link->qh_rlink = element->qh_rlink;
+	element->qh_rlink->qh_link = element->qh_link;
+	element->qh_rlink = 0;
+}
+
+#else /* !__GNUC__ */
+
+void	insque(void *a, void *b);
+void	remque(void *a);
+
+#endif /* __GNUC__ */
+
+#endif /* _KERNEL */
+
+#endif /* !_SYS_QUEUE_H_ */
diff --git a/tools/sdk/include/newlib/sys/reent.h b/tools/sdk/include/newlib/sys/reent.h
new file mode 100644
index 00000000..bb52ae65
--- /dev/null
+++ b/tools/sdk/include/newlib/sys/reent.h
@@ -0,0 +1,793 @@
+/* This header file provides the reentrancy.  */
+
+/* WARNING: All identifiers here must begin with an underscore.  This file is
+   included by stdio.h and others and we therefore must only use identifiers
+   in the namespace allotted to us.  */
+
+#ifndef _SYS_REENT_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+#define _SYS_REENT_H_
+
+#include <_ansi.h>
+#include 
+#include 
+
+#define _NULL 0
+
+#ifndef __Long
+#if __LONG_MAX__ == 2147483647L
+#define __Long long
+typedef unsigned __Long __ULong;
+#elif __INT_MAX__ == 2147483647
+#define __Long int
+typedef unsigned __Long __ULong;
+#endif
+#endif
+
+#if !defined( __Long)
+#include 
+#endif
+
+#ifndef __Long
+#define __Long __int32_t
+typedef __uint32_t __ULong;
+#endif
+
+struct _reent;
+
+/*
+ * If _REENT_SMALL is defined, we make struct _reent as small as possible,
+ * by having nearly everything possible allocated at first use.
+ */
+
+struct _Bigint
+{
+  struct _Bigint *_next;
+  int _k, _maxwds, _sign, _wds;
+  __ULong _x[1];
+};
+
+/* needed by reentrant structure */
+struct __tm
+{
+  int   __tm_sec;
+  int   __tm_min;
+  int   __tm_hour;
+  int   __tm_mday;
+  int   __tm_mon;
+  int   __tm_year;
+  int   __tm_wday;
+  int   __tm_yday;
+  int   __tm_isdst;
+};
+
+/*
+ * atexit() support.
+ */
+
+#define	_ATEXIT_SIZE 32	/* must be at least 32 to guarantee ANSI conformance */
+
+struct _on_exit_args {
+	void *  _fnargs[_ATEXIT_SIZE];	        /* user fn args */
+	void *	_dso_handle[_ATEXIT_SIZE];
+	/* Bitmask is set if user function takes arguments.  */
+	__ULong _fntypes;           	        /* type of exit routine -
+				   Must have at least _ATEXIT_SIZE bits */
+	/* Bitmask is set if function was registered via __cxa_atexit.  */
+	__ULong _is_cxa;
+};
+
+#ifdef _REENT_SMALL
+struct _atexit {
+	struct	_atexit *_next;			/* next in list */
+	int	_ind;				/* next index in this table */
+	void	(*_fns[_ATEXIT_SIZE])(void);	/* the table itself */
+        struct _on_exit_args * _on_exit_args_ptr;
+};
+# define _ATEXIT_INIT {_NULL, 0, {_NULL}, _NULL}
+#else
+struct _atexit {
+	struct	_atexit *_next;			/* next in list */
+	int	_ind;				/* next index in this table */
+	/* Some entries may already have been called, and will be NULL.  */
+	void	(*_fns[_ATEXIT_SIZE])(void);	/* the table itself */
+        struct _on_exit_args _on_exit_args;
+};
+# define _ATEXIT_INIT {_NULL, 0, {_NULL}, {{_NULL}, {_NULL}, 0, 0}}
+#endif
+
+#ifdef _REENT_GLOBAL_ATEXIT
+# define _REENT_INIT_ATEXIT
+#else
+# define _REENT_INIT_ATEXIT \
+  _NULL, _ATEXIT_INIT,
+#endif
+
+/*
+ * Stdio buffers.
+ *
+ * This and __FILE are defined here because we need them for struct _reent,
+ * but we don't want stdio.h included when stdlib.h is.
+ */
+
+struct __sbuf {
+	unsigned char *_base;
+	int	_size;
+};
+
+/*
+ * Stdio state variables.
+ *
+ * The following always hold:
+ *
+ *	if (_flags&(__SLBF|__SWR)) == (__SLBF|__SWR),
+ *		_lbfsize is -_bf._size, else _lbfsize is 0
+ *	if _flags&__SRD, _w is 0
+ *	if _flags&__SWR, _r is 0
+ *
+ * This ensures that the getc and putc macros (or inline functions) never
+ * try to write or read from a file that is in `read' or `write' mode.
+ * (Moreover, they can, and do, automatically switch from read mode to
+ * write mode, and back, on "r+" and "w+" files.)
+ *
+ * _lbfsize is used only to make the inline line-buffered output stream
+ * code as compact as possible.
+ *
+ * _ub, _up, and _ur are used when ungetc() pushes back more characters
+ * than fit in the current _bf, or when ungetc() pushes back a character
+ * that does not match the previous one in _bf.  When this happens,
+ * _ub._base becomes non-nil (i.e., a stream has ungetc() data iff
+ * _ub._base!=NULL) and _up and _ur save the current values of _p and _r.
+ */
+
+#ifdef _REENT_SMALL
+/*
+ * struct __sFILE_fake is the start of a struct __sFILE, with only the
+ * minimal fields allocated.  In __sinit() we really allocate the 3
+ * standard streams, etc., and point away from this fake.
+ */
+struct __sFILE_fake {
+  unsigned char *_p;	/* current position in (some) buffer */
+  int	_r;		/* read space left for getc() */
+  int	_w;		/* write space left for putc() */
+  short	_flags;		/* flags, below; this FILE is free if 0 */
+  short	_file;		/* fileno, if Unix descriptor, else -1 */
+  struct __sbuf _bf;	/* the buffer (at least 1 byte, if !NULL) */
+  int	_lbfsize;	/* 0 or -_bf._size, for inline putc */
+
+  struct _reent *_data;
+};
+
+/* Following is needed both in libc/stdio and libc/stdlib so we put it
+ * here instead of libc/stdio/local.h where it was previously. */
+
+extern _VOID   _EXFUN(__sinit,(struct _reent *));
+
+# define _REENT_SMALL_CHECK_INIT(ptr)		\
+  do						\
+    {						\
+      if ((ptr) && !(ptr)->__sdidinit)		\
+	__sinit (ptr);				\
+    }						\
+  while (0)
+#else
+# define _REENT_SMALL_CHECK_INIT(ptr) /* nothing */
+#endif
+
+struct __sFILE {
+  unsigned char *_p;	/* current position in (some) buffer */
+  int	_r;		/* read space left for getc() */
+  int	_w;		/* write space left for putc() */
+  short	_flags;		/* flags, below; this FILE is free if 0 */
+  short	_file;		/* fileno, if Unix descriptor, else -1 */
+  struct __sbuf _bf;	/* the buffer (at least 1 byte, if !NULL) */
+  int	_lbfsize;	/* 0 or -_bf._size, for inline putc */
+
+#ifdef _REENT_SMALL
+  struct _reent *_data;
+#endif
+
+  /* operations */
+  _PTR	_cookie;	/* cookie passed to io functions */
+
+  _READ_WRITE_RETURN_TYPE _EXFNPTR(_read, (struct _reent *, _PTR,
+					   char *, _READ_WRITE_BUFSIZE_TYPE));
+  _READ_WRITE_RETURN_TYPE _EXFNPTR(_write, (struct _reent *, _PTR,
+					    const char *,
+					    _READ_WRITE_BUFSIZE_TYPE));
+  _fpos_t _EXFNPTR(_seek, (struct _reent *, _PTR, _fpos_t, int));
+  int _EXFNPTR(_close, (struct _reent *, _PTR));
+
+  /* separate buffer for long sequences of ungetc() */
+  struct __sbuf _ub;	/* ungetc buffer */
+  unsigned char *_up;	/* saved _p when _p is doing ungetc data */
+  int	_ur;		/* saved _r when _r is counting ungetc data */
+
+  /* tricks to meet minimum requirements even when malloc() fails */
+  unsigned char _ubuf[3];	/* guarantee an ungetc() buffer */
+  unsigned char _nbuf[1];	/* guarantee a getc() buffer */
+
+  /* separate buffer for fgetline() when line crosses buffer boundary */
+  struct __sbuf _lb;	/* buffer for fgetline() */
+
+  /* Unix stdio files get aligned to block boundaries on fseek() */
+  int	_blksize;	/* stat.st_blksize (may be != _bf._size) */
+  _off_t _offset;	/* current lseek offset */
+
+#ifndef _REENT_SMALL
+  struct _reent *_data;	/* Here for binary compatibility? Remove? */
+#endif
+
+#ifndef __SINGLE_THREAD__
+  _flock_t _lock;	/* for thread-safety locking */
+#endif
+  _mbstate_t _mbstate;	/* for wide char stdio functions. */
+  int   _flags2;        /* for future use */
+};
+
+#ifdef __CUSTOM_FILE_IO__
+
+/* Get custom _FILE definition.  */
+#include 
+
+#else /* !__CUSTOM_FILE_IO__ */
+#ifdef __LARGE64_FILES
+struct __sFILE64 {
+  unsigned char *_p;	/* current position in (some) buffer */
+  int	_r;		/* read space left for getc() */
+  int	_w;		/* write space left for putc() */
+  short	_flags;		/* flags, below; this FILE is free if 0 */
+  short	_file;		/* fileno, if Unix descriptor, else -1 */
+  struct __sbuf _bf;	/* the buffer (at least 1 byte, if !NULL) */
+  int	_lbfsize;	/* 0 or -_bf._size, for inline putc */
+
+  struct _reent *_data;
+
+  /* operations */
+  _PTR	_cookie;	/* cookie passed to io functions */
+
+  _READ_WRITE_RETURN_TYPE _EXFNPTR(_read, (struct _reent *, _PTR,
+					   char *, _READ_WRITE_BUFSIZE_TYPE));
+  _READ_WRITE_RETURN_TYPE _EXFNPTR(_write, (struct _reent *, _PTR,
+					    const char *,
+					    _READ_WRITE_BUFSIZE_TYPE));
+  _fpos_t _EXFNPTR(_seek, (struct _reent *, _PTR, _fpos_t, int));
+  int _EXFNPTR(_close, (struct _reent *, _PTR));
+
+  /* separate buffer for long sequences of ungetc() */
+  struct __sbuf _ub;	/* ungetc buffer */
+  unsigned char *_up;	/* saved _p when _p is doing ungetc data */
+  int	_ur;		/* saved _r when _r is counting ungetc data */
+
+  /* tricks to meet minimum requirements even when malloc() fails */
+  unsigned char _ubuf[3];	/* guarantee an ungetc() buffer */
+  unsigned char _nbuf[1];	/* guarantee a getc() buffer */
+
+  /* separate buffer for fgetline() when line crosses buffer boundary */
+  struct __sbuf _lb;	/* buffer for fgetline() */
+
+  /* Unix stdio files get aligned to block boundaries on fseek() */
+  int	_blksize;	/* stat.st_blksize (may be != _bf._size) */
+  int   _flags2;        /* for future use */
+
+  _off64_t _offset;     /* current lseek offset */
+  _fpos64_t _EXFNPTR(_seek64, (struct _reent *, _PTR, _fpos64_t, int));
+
+#ifndef __SINGLE_THREAD__
+  _flock_t _lock;	/* for thread-safety locking */
+#endif
+  _mbstate_t _mbstate;	/* for wide char stdio functions. */
+};
+typedef struct __sFILE64 __FILE;
+#else
+typedef struct __sFILE   __FILE;
+#endif /* __LARGE64_FILES */
+#endif /* !__CUSTOM_FILE_IO__ */
+
+struct _glue
+{
+  struct _glue *_next;
+  int _niobs;
+  __FILE *_iobs;
+};
+
+/*
+ * rand48 family support
+ *
+ * Copyright (c) 1993 Martin Birgmeier
+ * All rights reserved.
+ *
+ * You may redistribute unmodified or modified versions of this source
+ * code provided that the above copyright notice and this and the
+ * following conditions are retained.
+ *
+ * This software is provided ``as is'', and comes with no warranties
+ * of any kind. I shall in no event be liable for anything that happens
+ * to anyone/anything when using this software.
+ */
+#define        _RAND48_SEED_0  (0x330e)
+#define        _RAND48_SEED_1  (0xabcd)
+#define        _RAND48_SEED_2  (0x1234)
+#define        _RAND48_MULT_0  (0xe66d)
+#define        _RAND48_MULT_1  (0xdeec)
+#define        _RAND48_MULT_2  (0x0005)
+#define        _RAND48_ADD     (0x000b)
+struct _rand48 {
+  unsigned short _seed[3];
+  unsigned short _mult[3];
+  unsigned short _add;
+#ifdef _REENT_SMALL
+  /* Put this in here as well, for good luck.  */
+  __extension__ unsigned long long _rand_next;
+#endif
+};
+
+/* How big the some arrays are.  */
+#define _REENT_EMERGENCY_SIZE 25
+#define _REENT_ASCTIME_SIZE 26
+#define _REENT_SIGNAL_SIZE 24
+
+/*
+ * struct _reent
+ *
+ * This structure contains *all* globals needed by the library.
+ * It's raison d'etre is to facilitate threads by making all library routines
+ * reentrant.  IE: All state information is contained here.
+ */
+
+#ifdef _REENT_SMALL
+
+struct _mprec
+{
+  /* used by mprec routines */
+  struct _Bigint *_result;
+  int _result_k;
+  struct _Bigint *_p5s;
+  struct _Bigint **_freelist;
+};
+
+
+struct _misc_reent
+{
+  /* miscellaneous reentrant data */
+  char *_strtok_last;
+  _mbstate_t _mblen_state;
+  _mbstate_t _wctomb_state;
+  _mbstate_t _mbtowc_state;
+  char _l64a_buf[8];
+  int _getdate_err;
+  _mbstate_t _mbrlen_state;
+  _mbstate_t _mbrtowc_state;
+  _mbstate_t _mbsrtowcs_state;
+  _mbstate_t _wcrtomb_state;
+  _mbstate_t _wcsrtombs_state;
+};
+
+/* This version of _reent is laid out with "int"s in pairs, to help
+ * ports with 16-bit int's but 32-bit pointers, align nicely.  */
+struct _reent
+{
+  /* As an exception to the above put _errno first for binary
+     compatibility with non _REENT_SMALL targets.  */
+  int _errno;			/* local copy of errno */
+
+  /* FILE is a big struct and may change over time.  To try to achieve binary
+     compatibility with future versions, put stdin,stdout,stderr here.
+     These are pointers into member __sf defined below.  */
+  __FILE *_stdin, *_stdout, *_stderr;	/* XXX */
+
+  int  _inc;			/* used by tmpnam */
+
+  char *_emergency;
+
+  int __sdidinit;		/* 1 means stdio has been init'd */
+
+  int _current_category;	/* unused */
+  _CONST char *_current_locale;	/* unused */
+
+  struct _mprec *_mp;
+
+  void _EXFNPTR(__cleanup, (struct _reent *));
+
+  int _gamma_signgam;
+
+  /* used by some fp conversion routines */
+  int _cvtlen;			/* should be size_t */
+  char *_cvtbuf;
+
+  struct _rand48 *_r48;
+  struct __tm *_localtime_buf;
+  char *_asctime_buf;
+
+  /* signal info */
+  void (**(_sig_func))(int);
+
+# ifndef _REENT_GLOBAL_ATEXIT
+  /* atexit stuff */
+  struct _atexit *_atexit;
+  struct _atexit _atexit0;
+# endif
+
+  struct _glue __sglue;			/* root of glue chain */
+  __FILE *__sf;			        /* file descriptors */
+  struct _misc_reent *_misc;            /* strtok, multibyte states */
+  char *_signal_buf;                    /* strsignal */
+};
+
+extern const struct __sFILE_fake __sf_fake_stdin;
+extern const struct __sFILE_fake __sf_fake_stdout;
+extern const struct __sFILE_fake __sf_fake_stderr;
+
+# define _REENT_INIT(var) \
+  { 0, \
+    (__FILE *)&__sf_fake_stdin, \
+    (__FILE *)&__sf_fake_stdout, \
+    (__FILE *)&__sf_fake_stderr, \
+    0, \
+    _NULL, \
+    0, \
+    0, \
+    "C", \
+    _NULL, \
+    _NULL, \
+    0, \
+    0, \
+    _NULL, \
+    _NULL, \
+    _NULL, \
+    _NULL, \
+    _NULL, \
+    _REENT_INIT_ATEXIT \
+    {_NULL, 0, _NULL}, \
+    _NULL, \
+    _NULL, \
+    _NULL \
+  }
+
+#define _REENT_INIT_PTR(var) \
+  { memset((var), 0, sizeof(*(var))); \
+    (var)->_stdin = (__FILE *)&__sf_fake_stdin; \
+    (var)->_stdout = (__FILE *)&__sf_fake_stdout; \
+    (var)->_stderr = (__FILE *)&__sf_fake_stderr; \
+    (var)->_current_locale = "C"; \
+  }
+
+/* Only built the assert() calls if we are built with debugging.  */
+#if DEBUG
+#include 
+#define __reent_assert(x) assert(x)
+#else
+#define __reent_assert(x) ((void)0)
+#endif
+
+#ifdef __CUSTOM_FILE_IO__
+#error Custom FILE I/O and _REENT_SMALL not currently supported.
+#endif
+
+/* Generic _REENT check macro.  */
+#define _REENT_CHECK(var, what, type, size, init) do { \
+  struct _reent *_r = (var); \
+  if (_r->what == NULL) { \
+    _r->what = (type)malloc(size); \
+    __reent_assert(_r->what); \
+    init; \
+  } \
+} while (0)
+
+#define _REENT_CHECK_TM(var) \
+  _REENT_CHECK(var, _localtime_buf, struct __tm *, sizeof *((var)->_localtime_buf), \
+    /* nothing */)
+
+#define _REENT_CHECK_ASCTIME_BUF(var) \
+  _REENT_CHECK(var, _asctime_buf, char *, _REENT_ASCTIME_SIZE, \
+    memset((var)->_asctime_buf, 0, _REENT_ASCTIME_SIZE))
+
+/* Handle the dynamically allocated rand48 structure. */
+#define _REENT_INIT_RAND48(var) do { \
+  struct _reent *_r = (var); \
+  _r->_r48->_seed[0] = _RAND48_SEED_0; \
+  _r->_r48->_seed[1] = _RAND48_SEED_1; \
+  _r->_r48->_seed[2] = _RAND48_SEED_2; \
+  _r->_r48->_mult[0] = _RAND48_MULT_0; \
+  _r->_r48->_mult[1] = _RAND48_MULT_1; \
+  _r->_r48->_mult[2] = _RAND48_MULT_2; \
+  _r->_r48->_add = _RAND48_ADD; \
+  _r->_r48->_rand_next = 1; \
+} while (0)
+#define _REENT_CHECK_RAND48(var) \
+  _REENT_CHECK(var, _r48, struct _rand48 *, sizeof *((var)->_r48), _REENT_INIT_RAND48((var)))
+
+#define _REENT_INIT_MP(var) do { \
+  struct _reent *_r = (var); \
+  _r->_mp->_result_k = 0; \
+  _r->_mp->_result = _r->_mp->_p5s = _NULL; \
+  _r->_mp->_freelist = _NULL; \
+} while (0)
+#define _REENT_CHECK_MP(var) \
+  _REENT_CHECK(var, _mp, struct _mprec *, sizeof *((var)->_mp), _REENT_INIT_MP(var))
+
+#define _REENT_CHECK_EMERGENCY(var) \
+  _REENT_CHECK(var, _emergency, char *, _REENT_EMERGENCY_SIZE, /* nothing */)
+
+#define _REENT_INIT_MISC(var) do { \
+  struct _reent *_r = (var); \
+  _r->_misc->_strtok_last = _NULL; \
+  _r->_misc->_mblen_state.__count = 0; \
+  _r->_misc->_mblen_state.__value.__wch = 0; \
+  _r->_misc->_wctomb_state.__count = 0; \
+  _r->_misc->_wctomb_state.__value.__wch = 0; \
+  _r->_misc->_mbtowc_state.__count = 0; \
+  _r->_misc->_mbtowc_state.__value.__wch = 0; \
+  _r->_misc->_mbrlen_state.__count = 0; \
+  _r->_misc->_mbrlen_state.__value.__wch = 0; \
+  _r->_misc->_mbrtowc_state.__count = 0; \
+  _r->_misc->_mbrtowc_state.__value.__wch = 0; \
+  _r->_misc->_mbsrtowcs_state.__count = 0; \
+  _r->_misc->_mbsrtowcs_state.__value.__wch = 0; \
+  _r->_misc->_wcrtomb_state.__count = 0; \
+  _r->_misc->_wcrtomb_state.__value.__wch = 0; \
+  _r->_misc->_wcsrtombs_state.__count = 0; \
+  _r->_misc->_wcsrtombs_state.__value.__wch = 0; \
+  _r->_misc->_l64a_buf[0] = '\0'; \
+  _r->_misc->_getdate_err = 0; \
+} while (0)
+#define _REENT_CHECK_MISC(var) \
+  _REENT_CHECK(var, _misc, struct _misc_reent *, sizeof *((var)->_misc), _REENT_INIT_MISC(var))
+
+#define _REENT_CHECK_SIGNAL_BUF(var) \
+  _REENT_CHECK(var, _signal_buf, char *, _REENT_SIGNAL_SIZE, /* nothing */)
+
+#define _REENT_SIGNGAM(ptr)	((ptr)->_gamma_signgam)
+#define _REENT_RAND_NEXT(ptr)	((ptr)->_r48->_rand_next)
+#define _REENT_RAND48_SEED(ptr)	((ptr)->_r48->_seed)
+#define _REENT_RAND48_MULT(ptr)	((ptr)->_r48->_mult)
+#define _REENT_RAND48_ADD(ptr)	((ptr)->_r48->_add)
+#define _REENT_MP_RESULT(ptr)	((ptr)->_mp->_result)
+#define _REENT_MP_RESULT_K(ptr)	((ptr)->_mp->_result_k)
+#define _REENT_MP_P5S(ptr)	((ptr)->_mp->_p5s)
+#define _REENT_MP_FREELIST(ptr)	((ptr)->_mp->_freelist)
+#define _REENT_ASCTIME_BUF(ptr)	((ptr)->_asctime_buf)
+#define _REENT_TM(ptr)		((ptr)->_localtime_buf)
+#define _REENT_EMERGENCY(ptr)	((ptr)->_emergency)
+#define _REENT_STRTOK_LAST(ptr)	((ptr)->_misc->_strtok_last)
+#define _REENT_MBLEN_STATE(ptr)	((ptr)->_misc->_mblen_state)
+#define _REENT_MBTOWC_STATE(ptr)((ptr)->_misc->_mbtowc_state)
+#define _REENT_WCTOMB_STATE(ptr)((ptr)->_misc->_wctomb_state)
+#define _REENT_MBRLEN_STATE(ptr) ((ptr)->_misc->_mbrlen_state)
+#define _REENT_MBRTOWC_STATE(ptr) ((ptr)->_misc->_mbrtowc_state)
+#define _REENT_MBSRTOWCS_STATE(ptr) ((ptr)->_misc->_mbsrtowcs_state)
+#define _REENT_WCRTOMB_STATE(ptr) ((ptr)->_misc->_wcrtomb_state)
+#define _REENT_WCSRTOMBS_STATE(ptr) ((ptr)->_misc->_wcsrtombs_state)
+#define _REENT_L64A_BUF(ptr)    ((ptr)->_misc->_l64a_buf)
+#define _REENT_GETDATE_ERR_P(ptr) (&((ptr)->_misc->_getdate_err))
+#define _REENT_SIGNAL_BUF(ptr)  ((ptr)->_signal_buf)
+
+#else /* !_REENT_SMALL */
+
+struct _reent
+{
+  int _errno;			/* local copy of errno */
+
+  /* FILE is a big struct and may change over time.  To try to achieve binary
+     compatibility with future versions, put stdin,stdout,stderr here.
+     These are pointers into member __sf defined below.  */
+  __FILE *_stdin, *_stdout, *_stderr;
+
+  int  _inc;			/* used by tmpnam */
+  char _emergency[_REENT_EMERGENCY_SIZE];
+
+  int _current_category;	/* used by setlocale */
+  _CONST char *_current_locale;
+
+  int __sdidinit;		/* 1 means stdio has been init'd */
+
+  void _EXFNPTR(__cleanup, (struct _reent *));
+
+  /* used by mprec routines */
+  struct _Bigint *_result;
+  int _result_k;
+  struct _Bigint *_p5s;
+  struct _Bigint **_freelist;
+
+  /* used by some fp conversion routines */
+  int _cvtlen;			/* should be size_t */
+  char *_cvtbuf;
+
+  union
+    {
+      struct
+        {
+          unsigned int _unused_rand;
+          char * _strtok_last;
+          char _asctime_buf[_REENT_ASCTIME_SIZE];
+          struct __tm _localtime_buf;
+          int _gamma_signgam;
+          __extension__ unsigned long long _rand_next;
+          struct _rand48 _r48;
+          _mbstate_t _mblen_state;
+          _mbstate_t _mbtowc_state;
+          _mbstate_t _wctomb_state;
+          char _l64a_buf[8];
+          char _signal_buf[_REENT_SIGNAL_SIZE];
+          int _getdate_err;
+          _mbstate_t _mbrlen_state;
+          _mbstate_t _mbrtowc_state;
+          _mbstate_t _mbsrtowcs_state;
+          _mbstate_t _wcrtomb_state;
+          _mbstate_t _wcsrtombs_state;
+	  int _h_errno;
+        } _reent;
+  /* Two next two fields were once used by malloc.  They are no longer
+     used. They are used to preserve the space used before so as to
+     allow addition of new reent fields and keep binary compatibility.   */
+      struct
+        {
+#define _N_LISTS 30
+          unsigned char * _nextf[_N_LISTS];
+          unsigned int _nmalloc[_N_LISTS];
+        } _unused;
+    } _new;
+
+# ifndef _REENT_GLOBAL_ATEXIT
+  /* atexit stuff */
+  struct _atexit *_atexit;	/* points to head of LIFO stack */
+  struct _atexit _atexit0;	/* one guaranteed table, required by ANSI */
+# endif
+
+  /* signal info */
+  void (**(_sig_func))(int);
+
+  /* These are here last so that __FILE can grow without changing the offsets
+     of the above members (on the off chance that future binary compatibility
+     would be broken otherwise).  */
+  struct _glue __sglue;		/* root of glue chain */
+  __FILE __sf[3];  		/* first three file descriptors */
+};
+
+#define _REENT_INIT(var) \
+  { 0, \
+    &(var).__sf[0], \
+    &(var).__sf[1], \
+    &(var).__sf[2], \
+    0, \
+    "", \
+    0, \
+    "C", \
+    0, \
+    _NULL, \
+    _NULL, \
+    0, \
+    _NULL, \
+    _NULL, \
+    0, \
+    _NULL, \
+    { \
+      { \
+        0, \
+        _NULL, \
+        "", \
+        {0, 0, 0, 0, 0, 0, 0, 0, 0}, \
+        0, \
+        1, \
+        { \
+          {_RAND48_SEED_0, _RAND48_SEED_1, _RAND48_SEED_2}, \
+          {_RAND48_MULT_0, _RAND48_MULT_1, _RAND48_MULT_2}, \
+          _RAND48_ADD \
+        }, \
+        {0, {0}}, \
+        {0, {0}}, \
+        {0, {0}}, \
+        "", \
+        "", \
+        0, \
+        {0, {0}}, \
+        {0, {0}}, \
+        {0, {0}}, \
+        {0, {0}}, \
+        {0, {0}} \
+      } \
+    }, \
+    _REENT_INIT_ATEXIT \
+    _NULL, \
+    {_NULL, 0, _NULL} \
+  }
+
+#define _REENT_INIT_PTR(var) \
+  { memset((var), 0, sizeof(*(var))); \
+    (var)->_stdin = &(var)->__sf[0]; \
+    (var)->_stdout = &(var)->__sf[1]; \
+    (var)->_stderr = &(var)->__sf[2]; \
+    (var)->_current_locale = "C"; \
+    (var)->_new._reent._rand_next = 1; \
+    (var)->_new._reent._r48._seed[0] = _RAND48_SEED_0; \
+    (var)->_new._reent._r48._seed[1] = _RAND48_SEED_1; \
+    (var)->_new._reent._r48._seed[2] = _RAND48_SEED_2; \
+    (var)->_new._reent._r48._mult[0] = _RAND48_MULT_0; \
+    (var)->_new._reent._r48._mult[1] = _RAND48_MULT_1; \
+    (var)->_new._reent._r48._mult[2] = _RAND48_MULT_2; \
+    (var)->_new._reent._r48._add = _RAND48_ADD; \
+  }
+
+#define _REENT_CHECK_RAND48(ptr)	/* nothing */
+#define _REENT_CHECK_MP(ptr)		/* nothing */
+#define _REENT_CHECK_TM(ptr)		/* nothing */
+#define _REENT_CHECK_ASCTIME_BUF(ptr)	/* nothing */
+#define _REENT_CHECK_EMERGENCY(ptr)	/* nothing */
+#define _REENT_CHECK_MISC(ptr)	        /* nothing */
+#define _REENT_CHECK_SIGNAL_BUF(ptr)	/* nothing */
+
+#define _REENT_SIGNGAM(ptr)	((ptr)->_new._reent._gamma_signgam)
+#define _REENT_RAND_NEXT(ptr)	((ptr)->_new._reent._rand_next)
+#define _REENT_RAND48_SEED(ptr)	((ptr)->_new._reent._r48._seed)
+#define _REENT_RAND48_MULT(ptr)	((ptr)->_new._reent._r48._mult)
+#define _REENT_RAND48_ADD(ptr)	((ptr)->_new._reent._r48._add)
+#define _REENT_MP_RESULT(ptr)	((ptr)->_result)
+#define _REENT_MP_RESULT_K(ptr)	((ptr)->_result_k)
+#define _REENT_MP_P5S(ptr)	((ptr)->_p5s)
+#define _REENT_MP_FREELIST(ptr)	((ptr)->_freelist)
+#define _REENT_ASCTIME_BUF(ptr)	((ptr)->_new._reent._asctime_buf)
+#define _REENT_TM(ptr)		(&(ptr)->_new._reent._localtime_buf)
+#define _REENT_EMERGENCY(ptr)	((ptr)->_emergency)
+#define _REENT_STRTOK_LAST(ptr)	((ptr)->_new._reent._strtok_last)
+#define _REENT_MBLEN_STATE(ptr)	((ptr)->_new._reent._mblen_state)
+#define _REENT_MBTOWC_STATE(ptr)((ptr)->_new._reent._mbtowc_state)
+#define _REENT_WCTOMB_STATE(ptr)((ptr)->_new._reent._wctomb_state)
+#define _REENT_MBRLEN_STATE(ptr)((ptr)->_new._reent._mbrlen_state)
+#define _REENT_MBRTOWC_STATE(ptr)((ptr)->_new._reent._mbrtowc_state)
+#define _REENT_MBSRTOWCS_STATE(ptr)((ptr)->_new._reent._mbsrtowcs_state)
+#define _REENT_WCRTOMB_STATE(ptr)((ptr)->_new._reent._wcrtomb_state)
+#define _REENT_WCSRTOMBS_STATE(ptr)((ptr)->_new._reent._wcsrtombs_state)
+#define _REENT_L64A_BUF(ptr)    ((ptr)->_new._reent._l64a_buf)
+#define _REENT_SIGNAL_BUF(ptr)  ((ptr)->_new._reent._signal_buf)
+#define _REENT_GETDATE_ERR_P(ptr) (&((ptr)->_new._reent._getdate_err))
+
+#endif /* !_REENT_SMALL */
+
+/* This value is used in stdlib/misc.c.  reent/reent.c has to know it
+   as well to make sure the freelist is correctly free'd.  Therefore
+   we define it here, rather than in stdlib/misc.c, as before. */
+#define _Kmax (sizeof (size_t) << 3)
+
+/*
+ * All references to struct _reent are via this pointer.
+ * Internally, newlib routines that need to reference it should use _REENT.
+ */
+
+#ifndef __ATTRIBUTE_IMPURE_PTR__
+#define __ATTRIBUTE_IMPURE_PTR__
+#endif
+
+#if !defined(__DYNAMIC_REENT__) || defined(__SINGLE_THREAD__)
+extern struct _reent *_impure_ptr __ATTRIBUTE_IMPURE_PTR__;
+#endif
+
+extern struct _reent *_global_impure_ptr __ATTRIBUTE_IMPURE_PTR__;
+
+void _reclaim_reent _PARAMS ((struct _reent *));
+
+/* #define _REENT_ONLY define this to get only reentrant routines */
+
+#if defined(__DYNAMIC_REENT__) && !defined(__SINGLE_THREAD__)
+#ifndef __getreent
+  struct _reent * _EXFUN(__getreent, (void));
+#endif
+# define _REENT (__getreent())
+#else /* __SINGLE_THREAD__ || !__DYNAMIC_REENT__ */
+# define _REENT _impure_ptr
+#endif /* __SINGLE_THREAD__ || !__DYNAMIC_REENT__ */
+
+#define _GLOBAL_REENT _global_impure_ptr
+
+#ifdef _REENT_GLOBAL_ATEXIT
+extern struct _atexit *_global_atexit; /* points to head of LIFO stack */
+# define _GLOBAL_ATEXIT _global_atexit
+#else
+# define _GLOBAL_ATEXIT (_GLOBAL_REENT->_atexit)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _SYS_REENT_H_ */
diff --git a/tools/sdk/include/newlib/sys/resource.h b/tools/sdk/include/newlib/sys/resource.h
new file mode 100644
index 00000000..c35ac2a4
--- /dev/null
+++ b/tools/sdk/include/newlib/sys/resource.h
@@ -0,0 +1,17 @@
+#ifndef _SYS_RESOURCE_H_
+#define _SYS_RESOURCE_H_
+
+#include 
+
+#define	RUSAGE_SELF	0		/* calling process */
+#define	RUSAGE_CHILDREN	-1		/* terminated child processes */
+
+struct rusage {
+  	struct timeval ru_utime;	/* user time used */
+	struct timeval ru_stime;	/* system time used */
+};
+
+int	_EXFUN(getrusage, (int, struct rusage*));
+
+#endif
+
diff --git a/tools/sdk/include/newlib/sys/sched.h b/tools/sdk/include/newlib/sys/sched.h
new file mode 100644
index 00000000..58f99d68
--- /dev/null
+++ b/tools/sdk/include/newlib/sys/sched.h
@@ -0,0 +1,67 @@
+/*
+ *  Written by Joel Sherrill .
+ *
+ *  COPYRIGHT (c) 1989-2010.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  Permission to use, copy, modify, and distribute this software for any
+ *  purpose without fee is hereby granted, provided that this entire notice
+ *  is included in all copies of any software which is or includes a copy
+ *  or modification of this software.
+ *
+ *  THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY.  IN PARTICULAR,  THE AUTHOR MAKES NO REPRESENTATION
+ *  OR WARRANTY OF ANY KIND CONCERNING THE MERCHANTABILITY OF THIS
+ *  SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR PURPOSE.
+ *
+ *  $Id$
+ */
+
+
+#ifndef _SYS_SCHED_H_
+#define _SYS_SCHED_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Scheduling Policies */
+/* Open Group Specifications Issue 6 */
+#if defined(__CYGWIN__)
+#define SCHED_OTHER    3
+#else
+#define SCHED_OTHER    0
+#endif
+
+#define SCHED_FIFO     1
+#define SCHED_RR       2
+
+#if defined(_POSIX_SPORADIC_SERVER)
+#define SCHED_SPORADIC 4
+#endif
+
+/* Scheduling Parameters */
+/* Open Group Specifications Issue 6 */
+
+struct sched_param {
+  int sched_priority;           /* Process execution scheduling priority */
+
+#if defined(_POSIX_SPORADIC_SERVER) || defined(_POSIX_THREAD_SPORADIC_SERVER)
+  int sched_ss_low_priority;    /* Low scheduling priority for sporadic */
+                                /*   server */
+  struct timespec sched_ss_repl_period;
+                                /* Replenishment period for sporadic server */
+  struct timespec sched_ss_init_budget;
+                               /* Initial budget for sporadic server */
+  int sched_ss_max_repl;       /* Maximum pending replenishments for */
+                               /* sporadic server */
+#endif
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/* end of include file */
+
diff --git a/tools/sdk/include/newlib/sys/signal.h b/tools/sdk/include/newlib/sys/signal.h
new file mode 100644
index 00000000..a29f525c
--- /dev/null
+++ b/tools/sdk/include/newlib/sys/signal.h
@@ -0,0 +1,357 @@
+/* sys/signal.h */
+
+#ifndef _SYS_SIGNAL_H
+#define _SYS_SIGNAL_H
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "_ansi.h"
+#include 
+#include 
+
+/* #ifndef __STRICT_ANSI__*/
+
+/* Cygwin defines it's own sigset_t in include/cygwin/signal.h */
+#ifndef __CYGWIN__
+typedef unsigned long sigset_t;
+#endif
+
+#if defined(__rtems__)
+
+#if defined(_POSIX_REALTIME_SIGNALS)
+
+/* sigev_notify values
+   NOTE: P1003.1c/D10, p. 34 adds SIGEV_THREAD.  */
+
+#define SIGEV_NONE   1  /* No asynchronous notification shall be delivered */
+                        /*   when the event of interest occurs. */
+#define SIGEV_SIGNAL 2  /* A queued signal, with an application defined */
+                        /*  value, shall be delivered when the event of */
+                        /*  interest occurs. */
+#define SIGEV_THREAD 3  /* A notification function shall be called to */
+                        /*   perform notification. */
+
+/*  Signal Generation and Delivery, P1003.1b-1993, p. 63
+    NOTE: P1003.1c/D10, p. 34 adds sigev_notify_function and
+          sigev_notify_attributes to the sigevent structure.  */
+
+union sigval {
+  int    sival_int;    /* Integer signal value */
+  void  *sival_ptr;    /* Pointer signal value */
+};
+
+struct sigevent {
+  int              sigev_notify;               /* Notification type */
+  int              sigev_signo;                /* Signal number */
+  union sigval     sigev_value;                /* Signal value */
+
+#if defined(_POSIX_THREADS)
+  void           (*sigev_notify_function)( union sigval );
+                                               /* Notification function */
+  pthread_attr_t  *sigev_notify_attributes;    /* Notification Attributes */
+#endif
+};
+
+/* Signal Actions, P1003.1b-1993, p. 64 */
+/* si_code values, p. 66 */
+
+#define SI_USER    1    /* Sent by a user. kill(), abort(), etc */
+#define SI_QUEUE   2    /* Sent by sigqueue() */
+#define SI_TIMER   3    /* Sent by expiration of a timer_settime() timer */
+#define SI_ASYNCIO 4    /* Indicates completion of asycnhronous IO */
+#define SI_MESGQ   5    /* Indicates arrival of a message at an empty queue */
+
+typedef struct {
+  int          si_signo;    /* Signal number */
+  int          si_code;     /* Cause of the signal */
+  union sigval si_value;    /* Signal value */
+} siginfo_t;
+#endif
+
+/*  3.3.8 Synchronously Accept a Signal, P1003.1b-1993, p. 76 */
+
+#define SA_NOCLDSTOP 0x1   /* Do not generate SIGCHLD when children stop */
+#define SA_SIGINFO   0x2   /* Invoke the signal catching function with */
+                           /*   three arguments instead of one. */
+#if __BSD_VISIBLE || __XSI_VISIBLE || __POSIX_VISIBLE >= 200112
+#define SA_ONSTACK   0x4   /* Signal delivery will be on a separate stack. */
+#endif
+
+/* struct sigaction notes from POSIX:
+ *
+ *  (1) Routines stored in sa_handler should take a single int as
+ *      their argument although the POSIX standard does not require this.
+ *      This is not longer true since at least POSIX.1-2008
+ *  (2) The fields sa_handler and sa_sigaction may overlap, and a conforming
+ *      application should not use both simultaneously.
+ */
+
+typedef void (*_sig_func_ptr)(int);
+
+struct sigaction {
+  int         sa_flags;       /* Special flags to affect behavior of signal */
+  sigset_t    sa_mask;        /* Additional set of signals to be blocked */
+                              /*   during execution of signal-catching */
+                              /*   function. */
+  union {
+    _sig_func_ptr _handler;  /* SIG_DFL, SIG_IGN, or pointer to a function */
+#if defined(_POSIX_REALTIME_SIGNALS)
+    void      (*_sigaction)( int, siginfo_t *, void * );
+#endif
+  } _signal_handlers;
+};
+
+#define sa_handler    _signal_handlers._handler
+#if defined(_POSIX_REALTIME_SIGNALS)
+#define sa_sigaction  _signal_handlers._sigaction
+#endif
+
+#if __BSD_VISIBLE || __XSI_VISIBLE || __POSIX_VISIBLE >= 200112
+/*
+ * Minimum and default signal stack constants. Allow for target overrides
+ * from .
+ */
+#ifndef	MINSIGSTKSZ
+#define	MINSIGSTKSZ	2048
+#endif
+#ifndef	SIGSTKSZ
+#define	SIGSTKSZ	8192
+#endif
+
+/*
+ * Possible values for ss_flags in stack_t below.
+ */
+#define	SS_ONSTACK	0x1
+#define	SS_DISABLE	0x2
+
+/*
+ * Structure used in sigaltstack call.
+ */
+typedef struct sigaltstack {
+  void     *ss_sp;    /* Stack base or pointer.  */
+  int       ss_flags; /* Flags.  */
+  size_t    ss_size;  /* Stack size.  */
+} stack_t;
+#endif
+
+#elif defined(__CYGWIN__)
+#include 
+#else
+#define SA_NOCLDSTOP 1  /* only value supported now for sa_flags */
+
+typedef void (*_sig_func_ptr)(int);
+
+struct sigaction 
+{
+	_sig_func_ptr sa_handler;
+	sigset_t sa_mask;
+	int sa_flags;
+};
+#endif /* defined(__rtems__) */
+
+#define SIG_SETMASK 0	/* set mask with sigprocmask() */
+#define SIG_BLOCK 1	/* set of signals to block */
+#define SIG_UNBLOCK 2	/* set of signals to, well, unblock */
+
+/* These depend upon the type of sigset_t, which right now 
+   is always a long.. They're in the POSIX namespace, but
+   are not ANSI. */
+#define sigaddset(what,sig) (*(what) |= (1<<(sig)), 0)
+#define sigdelset(what,sig) (*(what) &= ~(1<<(sig)), 0)
+#define sigemptyset(what)   (*(what) = 0, 0)
+#define sigfillset(what)    (*(what) = ~(0), 0)
+#define sigismember(what,sig) (((*(what)) & (1<<(sig))) != 0)
+
+int _EXFUN(sigprocmask, (int how, const sigset_t *set, sigset_t *oset));
+
+#if defined(_POSIX_THREADS)
+int _EXFUN(pthread_sigmask, (int how, const sigset_t *set, sigset_t *oset));
+#endif
+
+#if defined(__CYGWIN__) || defined(__rtems__)
+#undef sigaddset
+#undef sigdelset
+#undef sigemptyset
+#undef sigfillset
+#undef sigismember
+
+#ifdef _COMPILING_NEWLIB
+int _EXFUN(_kill, (pid_t, int));
+#endif /* _COMPILING_NEWLIB */
+#endif /* __CYGWIN__ || __rtems__ */
+#if defined(__CYGWIN__) || defined(__rtems__) || defined(__SPU__)
+int _EXFUN(kill, (pid_t, int));
+#endif /* __CYGWIN__ || __rtems__ || __SPU__ */
+#if defined(__CYGWIN__) || defined(__rtems__)
+int _EXFUN(killpg, (pid_t, int));
+int _EXFUN(sigaction, (int, const struct sigaction *, struct sigaction *));
+int _EXFUN(sigaddset, (sigset_t *, const int));
+int _EXFUN(sigdelset, (sigset_t *, const int));
+int _EXFUN(sigismember, (const sigset_t *, int));
+int _EXFUN(sigfillset, (sigset_t *));
+int _EXFUN(sigemptyset, (sigset_t *));
+int _EXFUN(sigpending, (sigset_t *));
+int _EXFUN(sigsuspend, (const sigset_t *));
+int _EXFUN(sigpause, (int));
+
+#ifdef __rtems__
+#if __BSD_VISIBLE || __XSI_VISIBLE || __POSIX_VISIBLE >= 200112
+int _EXFUN(sigaltstack, (const stack_t *__restrict, stack_t *__restrict));
+#endif
+#endif
+
+#if defined(_POSIX_THREADS)
+#ifdef __CYGWIN__
+#  ifndef _CYGWIN_TYPES_H
+#    error You need the winsup sources or a cygwin installation to compile the cygwin version of newlib.
+#  endif
+#endif
+int _EXFUN(pthread_kill, (pthread_t thread, int sig));
+#endif
+
+#if defined(_POSIX_REALTIME_SIGNALS)
+
+/*  3.3.8 Synchronously Accept a Signal, P1003.1b-1993, p. 76
+    NOTE: P1003.1c/D10, p. 39 adds sigwait().  */
+
+int _EXFUN(sigwaitinfo, (const sigset_t *set, siginfo_t *info));
+int _EXFUN(sigtimedwait,
+  (const sigset_t *set, siginfo_t *info, const struct timespec  *timeout)
+);
+int _EXFUN(sigwait, (const sigset_t *set, int *sig));
+
+/*  3.3.9 Queue a Signal to a Process, P1003.1b-1993, p. 78 */
+int _EXFUN(sigqueue, (pid_t pid, int signo, const union sigval value));
+
+#endif /* defined(_POSIX_REALTIME_SIGNALS) */
+
+#endif /* defined(__CYGWIN__) || defined(__rtems__) */
+
+/* #endif __STRICT_ANSI__ */
+
+#if defined(___AM29K__)
+/* These all need to be defined for ANSI C, but I don't think they are
+   meaningful.  */
+#define SIGABRT 1
+#define SIGFPE 1
+#define SIGILL 1
+#define SIGINT 1
+#define SIGSEGV 1
+#define SIGTERM 1
+/* These need to be defined for POSIX, and some others do too.  */
+#define SIGHUP 1
+#define SIGQUIT 1
+#define NSIG 2
+#elif defined(__GO32__)
+#define SIGINT  1
+#define SIGKILL 2
+#define SIGPIPE 3
+#define SIGFPE  4
+#define SIGHUP  5
+#define SIGTERM 6
+#define SIGSEGV 7
+#define SIGTSTP 8
+#define SIGQUIT 9
+#define SIGTRAP 10
+#define SIGILL  11
+#define SIGEMT  12
+#define SIGALRM 13
+#define SIGBUS  14
+#define SIGLOST 15
+#define SIGSTOP 16
+#define SIGABRT 17
+#define SIGUSR1	18
+#define SIGUSR2	19
+#define NSIG    20
+#elif !defined(SIGTRAP)
+#define	SIGHUP	1	/* hangup */
+#define	SIGINT	2	/* interrupt */
+#define	SIGQUIT	3	/* quit */
+#define	SIGILL	4	/* illegal instruction (not reset when caught) */
+#define	SIGTRAP	5	/* trace trap (not reset when caught) */
+#define	SIGIOT	6	/* IOT instruction */
+#define	SIGABRT 6	/* used by abort, replace SIGIOT in the future */
+#define	SIGEMT	7	/* EMT instruction */
+#define	SIGFPE	8	/* floating point exception */
+#define	SIGKILL	9	/* kill (cannot be caught or ignored) */
+#define	SIGBUS	10	/* bus error */
+#define	SIGSEGV	11	/* segmentation violation */
+#define	SIGSYS	12	/* bad argument to system call */
+#define	SIGPIPE	13	/* write on a pipe with no one to read it */
+#define	SIGALRM	14	/* alarm clock */
+#define	SIGTERM	15	/* software termination signal from kill */
+
+#if defined(__rtems__)
+#define	SIGURG	16	/* urgent condition on IO channel */
+#define	SIGSTOP	17	/* sendable stop signal not from tty */
+#define	SIGTSTP	18	/* stop signal from tty */
+#define	SIGCONT	19	/* continue a stopped process */
+#define	SIGCHLD	20	/* to parent on child stop or exit */
+#define	SIGCLD	20	/* System V name for SIGCHLD */
+#define	SIGTTIN	21	/* to readers pgrp upon background tty read */
+#define	SIGTTOU	22	/* like TTIN for output if (tp->t_local<OSTOP) */
+#define	SIGIO	23	/* input/output possible signal */
+#define	SIGPOLL	SIGIO	/* System V name for SIGIO */
+#define	SIGWINCH 24	/* window changed */
+#define	SIGUSR1 25	/* user defined signal 1 */
+#define	SIGUSR2 26	/* user defined signal 2 */
+
+/* Real-Time Signals Range, P1003.1b-1993, p. 61
+   NOTE: By P1003.1b-1993, this should be at least RTSIG_MAX
+         (which is a minimum of 8) signals.
+ */
+#define SIGRTMIN 27
+#define SIGRTMAX 31
+#define __SIGFIRSTNOTRT SIGHUP
+#define __SIGLASTNOTRT  SIGUSR2
+
+#define NSIG	32      /* signal 0 implied */
+
+#elif defined(__svr4__)
+/* svr4 specifics. different signals above 15, and sigaction. */
+#define	SIGUSR1	16
+#define SIGUSR2	17
+#define SIGCLD	18
+#define	SIGPWR	19
+#define SIGWINCH 20
+#define	SIGPOLL	22	/* 20 for x.out binaries!!!! */
+#define	SIGSTOP	23	/* sendable stop signal not from tty */
+#define	SIGTSTP	24	/* stop signal from tty */
+#define	SIGCONT	25	/* continue a stopped process */
+#define	SIGTTIN	26	/* to readers pgrp upon background tty read */
+#define	SIGTTOU	27	/* like TTIN for output if (tp->t_local<OSTOP) */
+#define NSIG	28	
+#else
+#define	SIGURG	16	/* urgent condition on IO channel */
+#define	SIGSTOP	17	/* sendable stop signal not from tty */
+#define	SIGTSTP	18	/* stop signal from tty */
+#define	SIGCONT	19	/* continue a stopped process */
+#define	SIGCHLD	20	/* to parent on child stop or exit */
+#define	SIGCLD	20	/* System V name for SIGCHLD */
+#define	SIGTTIN	21	/* to readers pgrp upon background tty read */
+#define	SIGTTOU	22	/* like TTIN for output if (tp->t_local<OSTOP) */
+#define	SIGIO	23	/* input/output possible signal */
+#define	SIGPOLL	SIGIO	/* System V name for SIGIO */
+#define	SIGXCPU	24	/* exceeded CPU time limit */
+#define	SIGXFSZ	25	/* exceeded file size limit */
+#define	SIGVTALRM 26	/* virtual time alarm */
+#define	SIGPROF	27	/* profiling time alarm */
+#define	SIGWINCH 28	/* window changed */
+#define	SIGLOST 29	/* resource lost (eg, record-lock lost) */
+#define	SIGUSR1 30	/* user defined signal 1 */
+#define	SIGUSR2 31	/* user defined signal 2 */
+#define NSIG	32      /* signal 0 implied */
+#endif
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#ifndef _SIGNAL_H_
+/* Some applications take advantage of the fact that 
+ * and  are equivalent in glibc.  Allow for that here.  */
+#include 
+#endif
+#endif /* _SYS_SIGNAL_H */
diff --git a/tools/sdk/include/newlib/sys/stat.h b/tools/sdk/include/newlib/sys/stat.h
new file mode 100644
index 00000000..11b9d808
--- /dev/null
+++ b/tools/sdk/include/newlib/sys/stat.h
@@ -0,0 +1,192 @@
+#ifndef	_SYS_STAT_H
+#define	_SYS_STAT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <_ansi.h>
+#include 
+#include 
+#include 
+
+/* dj's stat defines _STAT_H_ */
+#ifndef _STAT_H_
+
+/* It is intended that the layout of this structure not change when the
+   sizes of any of the basic types change (short, int, long) [via a compile
+   time option].  */
+
+#ifdef __CYGWIN__
+#include 
+#ifdef _COMPILING_NEWLIB
+#define stat64 stat
+#endif
+#else
+struct	stat 
+{
+  dev_t		st_dev;
+  ino_t		st_ino;
+  mode_t	st_mode;
+  nlink_t	st_nlink;
+  uid_t		st_uid;
+  gid_t		st_gid;
+  dev_t		st_rdev;
+  off_t		st_size;
+#if defined(__rtems__)
+  struct timespec st_atim;
+  struct timespec st_mtim;
+  struct timespec st_ctim;
+  blksize_t     st_blksize;
+  blkcnt_t	st_blocks;
+#else
+  /* SysV/sco doesn't have the rest... But Solaris, eabi does.  */
+#if defined(__svr4__) && !defined(__PPC__) && !defined(__sun__)
+  time_t	st_atime;
+  time_t	st_mtime;
+  time_t	st_ctime;
+#else
+  time_t	st_atime;
+  long		st_spare1;
+  time_t	st_mtime;
+  long		st_spare2;
+  time_t	st_ctime;
+  long		st_spare3;
+  long		st_blksize;
+  long		st_blocks;
+  long	st_spare4[2];
+#endif
+#endif
+};
+
+#if defined(__rtems__)
+#define st_atime st_atim.tv_sec
+#define st_ctime st_ctim.tv_sec
+#define st_mtime st_mtim.tv_sec
+#endif
+
+#endif
+
+#define	_IFMT		0170000	/* type of file */
+#define		_IFDIR	0040000	/* directory */
+#define		_IFCHR	0020000	/* character special */
+#define		_IFBLK	0060000	/* block special */
+#define		_IFREG	0100000	/* regular */
+#define		_IFLNK	0120000	/* symbolic link */
+#define		_IFSOCK	0140000	/* socket */
+#define		_IFIFO	0010000	/* fifo */
+
+#define 	S_BLKSIZE  1024 /* size of a block */
+
+#define	S_ISUID		0004000	/* set user id on execution */
+#define	S_ISGID		0002000	/* set group id on execution */
+#define	S_ISVTX		0001000	/* save swapped text even after use */
+#ifndef	_POSIX_SOURCE
+#define	S_IREAD		0000400	/* read permission, owner */
+#define	S_IWRITE 	0000200	/* write permission, owner */
+#define	S_IEXEC		0000100	/* execute/search permission, owner */
+#define	S_ENFMT 	0002000	/* enforcement-mode locking */
+#endif	/* !_POSIX_SOURCE */
+
+#define	S_IFMT		_IFMT
+#define	S_IFDIR		_IFDIR
+#define	S_IFCHR		_IFCHR
+#define	S_IFBLK		_IFBLK
+#define	S_IFREG		_IFREG
+#define	S_IFLNK		_IFLNK
+#define	S_IFSOCK	_IFSOCK
+#define	S_IFIFO		_IFIFO
+
+#ifdef _WIN32
+/* The Windows header files define _S_ forms of these, so we do too
+   for easier portability.  */
+#define _S_IFMT		_IFMT
+#define _S_IFDIR	_IFDIR
+#define _S_IFCHR	_IFCHR
+#define _S_IFIFO	_IFIFO
+#define _S_IFREG	_IFREG
+#define _S_IREAD	0000400
+#define _S_IWRITE	0000200
+#define _S_IEXEC	0000100
+#endif
+
+#define	S_IRWXU 	(S_IRUSR | S_IWUSR | S_IXUSR)
+#define		S_IRUSR	0000400	/* read permission, owner */
+#define		S_IWUSR	0000200	/* write permission, owner */
+#define		S_IXUSR 0000100/* execute/search permission, owner */
+#define	S_IRWXG		(S_IRGRP | S_IWGRP | S_IXGRP)
+#define		S_IRGRP	0000040	/* read permission, group */
+#define		S_IWGRP	0000020	/* write permission, grougroup */
+#define		S_IXGRP 0000010/* execute/search permission, group */
+#define	S_IRWXO		(S_IROTH | S_IWOTH | S_IXOTH)
+#define		S_IROTH	0000004	/* read permission, other */
+#define		S_IWOTH	0000002	/* write permission, other */
+#define		S_IXOTH 0000001/* execute/search permission, other */
+
+#ifndef _POSIX_SOURCE
+#define ACCESSPERMS (S_IRWXU | S_IRWXG | S_IRWXO) /* 0777 */
+#define ALLPERMS (S_ISUID | S_ISGID | S_ISVTX | S_IRWXU | S_IRWXG | S_IRWXO) /* 07777 */
+#define DEFFILEMODE (S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP | S_IROTH | S_IWOTH) /* 0666 */
+#endif
+
+#define	S_ISBLK(m)	(((m)&_IFMT) == _IFBLK)
+#define	S_ISCHR(m)	(((m)&_IFMT) == _IFCHR)
+#define	S_ISDIR(m)	(((m)&_IFMT) == _IFDIR)
+#define	S_ISFIFO(m)	(((m)&_IFMT) == _IFIFO)
+#define	S_ISREG(m)	(((m)&_IFMT) == _IFREG)
+#define	S_ISLNK(m)	(((m)&_IFMT) == _IFLNK)
+#define	S_ISSOCK(m)	(((m)&_IFMT) == _IFSOCK)
+
+#if defined(__CYGWIN__)
+/* Special tv_nsec values for futimens(2) and utimensat(2). */
+#define UTIME_NOW	-2L
+#define UTIME_OMIT	-1L
+#endif
+
+int	_EXFUN(chmod,( const char *__path, mode_t __mode ));
+int     _EXFUN(fchmod,(int __fd, mode_t __mode));
+int	_EXFUN(fstat,( int __fd, struct stat *__sbuf ));
+int	_EXFUN(mkdir,( const char *_path, mode_t __mode ));
+int	_EXFUN(mkfifo,( const char *__path, mode_t __mode ));
+int	_EXFUN(stat,( const char *__restrict __path, struct stat *__restrict __sbuf ));
+mode_t	_EXFUN(umask,( mode_t __mask ));
+
+#if defined (__SPU__) || defined(__rtems__) || defined(__CYGWIN__) && !defined(__INSIDE_CYGWIN__)
+int	_EXFUN(lstat,( const char *__restrict __path, struct stat *__restrict __buf ));
+int	_EXFUN(mknod,( const char *__path, mode_t __mode, dev_t __dev ));
+#endif
+
+#if (__POSIX_VISIBLE >= 200809 || defined (__CYGWIN__)) && !defined(__INSIDE_CYGWIN__)
+int	_EXFUN(fchmodat, (int, const char *, mode_t, int));
+#endif
+#if (__BSD_VISIBLE || __POSIX_VISIBLE >= 200809 || defined (__CYGWIN__)) && !defined(__INSIDE_CYGWIN__)
+int	_EXFUN(fstatat, (int, const char *__restrict , struct stat *__restrict, int));
+int	_EXFUN(mkdirat, (int, const char *, mode_t));
+int	_EXFUN(mkfifoat, (int, const char *, mode_t));
+#endif
+#if (__BSD_VISIBLE || __XSI_VISIBLE >= 700 || defined (__CYGWIN__)) && !defined(__INSIDE_CYGWIN__)
+int	_EXFUN(mknodat, (int, const char *, mode_t, dev_t));
+#endif
+#if (__BSD_VISIBLE || __POSIX_VISIBLE >= 200809 || defined (__CYGWIN__)) && !defined(__INSIDE_CYGWIN__)
+int	_EXFUN(utimensat, (int, const char *, const struct timespec *, int));
+int	_EXFUN(futimens, (int, const struct timespec *));
+#endif
+
+/* Provide prototypes for most of the _ names that are
+   provided in newlib for some compilers.  */
+#ifdef _COMPILING_NEWLIB
+int	_EXFUN(_fstat,( int __fd, struct stat *__sbuf ));
+int	_EXFUN(_stat,( const char *__restrict __path, struct stat *__restrict __sbuf ));
+int	_EXFUN(_mkdir,( const char *_path, mode_t __mode ));
+#ifdef __LARGE64_FILES
+struct stat64;
+int	_EXFUN(_stat64,( const char *__restrict __path, struct stat64 *__restrict __sbuf ));
+int	_EXFUN(_fstat64,( int __fd, struct stat64 *__sbuf ));
+#endif
+#endif
+
+#endif /* !_STAT_H_ */
+#ifdef __cplusplus
+}
+#endif
+#endif /* _SYS_STAT_H */
diff --git a/tools/sdk/include/newlib/sys/stdio.h b/tools/sdk/include/newlib/sys/stdio.h
new file mode 100644
index 00000000..0918fe15
--- /dev/null
+++ b/tools/sdk/include/newlib/sys/stdio.h
@@ -0,0 +1,27 @@
+#ifndef _NEWLIB_STDIO_H
+#define _NEWLIB_STDIO_H
+
+#include 
+#include 
+
+/* Internal locking macros, used to protect stdio functions.  In the
+   general case, expand to nothing. Use __SSTR flag in FILE _flags to
+   detect if FILE is private to sprintf/sscanf class of functions; if
+   set then do nothing as lock is not initialised. */
+#if !defined(_flockfile)
+#ifndef __SINGLE_THREAD__
+#  define _flockfile(fp) (((fp)->_flags & __SSTR) ? 0 : __lock_acquire_recursive((fp)->_lock))
+#else
+#  define _flockfile(fp)	(_CAST_VOID 0)
+#endif
+#endif
+
+#if !defined(_funlockfile)
+#ifndef __SINGLE_THREAD__
+#  define _funlockfile(fp) (((fp)->_flags & __SSTR) ? 0 : __lock_release_recursive((fp)->_lock))
+#else
+#  define _funlockfile(fp)	(_CAST_VOID 0)
+#endif
+#endif
+
+#endif /* _NEWLIB_STDIO_H */
diff --git a/tools/sdk/include/newlib/sys/string.h b/tools/sdk/include/newlib/sys/string.h
new file mode 100644
index 00000000..ceedf4be
--- /dev/null
+++ b/tools/sdk/include/newlib/sys/string.h
@@ -0,0 +1,2 @@
+/* This is a dummy  used as a placeholder for
+   systems that need to have a special header file.  */
diff --git a/tools/sdk/include/newlib/sys/syslimits.h b/tools/sdk/include/newlib/sys/syslimits.h
new file mode 100644
index 00000000..ba9dbd66
--- /dev/null
+++ b/tools/sdk/include/newlib/sys/syslimits.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 1988, 1993
+ *	The Regents of the University of California.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the University of
+ *	California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)syslimits.h	8.1 (Berkeley) 6/2/93
+ * $FreeBSD: src/sys/sys/syslimits.h,v 1.10 2001/06/18 20:24:54 wollman Exp $
+ */
+
+#ifndef _SYS_SYSLIMITS_H_
+#define _SYS_SYSLIMITS_H_
+
+#define	ARG_MAX			65536	/* max bytes for an exec function */
+#ifndef CHILD_MAX
+#define	CHILD_MAX		   40	/* max simultaneous processes */
+#endif
+#define	LINK_MAX		32767	/* max file link count */
+#define	MAX_CANON		  255	/* max bytes in term canon input line */
+#define	MAX_INPUT		  255	/* max bytes in terminal input */
+#define	NAME_MAX		  255	/* max bytes in a file name */
+#define	NGROUPS_MAX		   16	/* max supplemental group id's */
+#ifndef OPEN_MAX
+#define	OPEN_MAX		   64	/* max open files per process */
+#endif
+#define	PATH_MAX		 1024	/* max bytes in pathname */
+#define	PIPE_BUF		  512	/* max bytes for atomic pipe writes */
+#define	IOV_MAX			 1024	/* max elements in i/o vector */
+
+#define	BC_BASE_MAX		   99	/* max ibase/obase values in bc(1) */
+#define	BC_DIM_MAX		 2048	/* max array elements in bc(1) */
+#define	BC_SCALE_MAX		   99	/* max scale value in bc(1) */
+#define	BC_STRING_MAX		 1000	/* max const string length in bc(1) */
+#define	COLL_WEIGHTS_MAX	    0	/* max weights for order keyword */
+#define	EXPR_NEST_MAX		   32	/* max expressions nested in expr(1) */
+#define	LINE_MAX		 2048	/* max bytes in an input line */
+#define	RE_DUP_MAX		  255	/* max RE's in interval notation */
+
+#endif
diff --git a/tools/sdk/include/newlib/sys/time.h b/tools/sdk/include/newlib/sys/time.h
new file mode 100644
index 00000000..be16497f
--- /dev/null
+++ b/tools/sdk/include/newlib/sys/time.h
@@ -0,0 +1,91 @@
+/* time.h -- An implementation of the standard Unix  file.
+   Written by Geoffrey Noer 
+   Public domain; no rights reserved. */
+
+#ifndef _SYS_TIME_H_
+#define _SYS_TIME_H_
+
+#include <_ansi.h>
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef _TIMEVAL_DEFINED
+#define _TIMEVAL_DEFINED
+struct timeval {
+  time_t      tv_sec;
+  suseconds_t tv_usec;
+};
+
+/* BSD time macros used by RTEMS code */
+#if defined (__rtems__) || defined (__CYGWIN__)
+
+/* Convenience macros for operations on timevals.
+   NOTE: `timercmp' does not work for >= or <=.  */
+#define	timerisset(tvp)		((tvp)->tv_sec || (tvp)->tv_usec)
+#define	timerclear(tvp)		((tvp)->tv_sec = (tvp)->tv_usec = 0)
+#define	timercmp(a, b, CMP) 						      \
+  (((a)->tv_sec == (b)->tv_sec) ? 					      \
+   ((a)->tv_usec CMP (b)->tv_usec) : 					      \
+   ((a)->tv_sec CMP (b)->tv_sec))
+#define	timeradd(a, b, result)						      \
+  do {									      \
+    (result)->tv_sec = (a)->tv_sec + (b)->tv_sec;			      \
+    (result)->tv_usec = (a)->tv_usec + (b)->tv_usec;			      \
+    if ((result)->tv_usec >= 1000000)					      \
+      {									      \
+	++(result)->tv_sec;						      \
+	(result)->tv_usec -= 1000000;					      \
+      }									      \
+  } while (0)
+#define	timersub(a, b, result)						      \
+  do {									      \
+    (result)->tv_sec = (a)->tv_sec - (b)->tv_sec;			      \
+    (result)->tv_usec = (a)->tv_usec - (b)->tv_usec;			      \
+    if ((result)->tv_usec < 0) {					      \
+      --(result)->tv_sec;						      \
+      (result)->tv_usec += 1000000;					      \
+    }									      \
+  } while (0)
+#endif /* defined (__rtems__) || defined (__CYGWIN__) */
+#endif /* !_TIMEVAL_DEFINED */
+
+struct timezone {
+  int tz_minuteswest;
+  int tz_dsttime;
+};
+
+#ifdef __CYGWIN__
+#include 
+#endif /* __CYGWIN__ */
+
+#define ITIMER_REAL     0
+#define ITIMER_VIRTUAL  1
+#define ITIMER_PROF     2
+
+struct  itimerval {
+  struct  timeval it_interval;
+  struct  timeval it_value;
+};
+
+#ifdef _COMPILING_NEWLIB
+int _EXFUN(_gettimeofday, (struct timeval *__p, void *__tz));
+#endif
+
+int _EXFUN(gettimeofday, (struct timeval *__restrict __p,
+			  void *__restrict __tz));
+#if __BSD_VISIBLE
+int _EXFUN(settimeofday, (const struct timeval *, const struct timezone *));
+int _EXFUN(adjtime, (const struct timeval *, struct timeval *));
+#endif
+int _EXFUN(utimes, (const char *__path, const struct timeval *__tvp));
+int _EXFUN(getitimer, (int __which, struct itimerval *__value));
+int _EXFUN(setitimer, (int __which, const struct itimerval *__restrict __value,
+					struct itimerval *__restrict __ovalue));
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _SYS_TIME_H_ */
diff --git a/tools/sdk/include/newlib/sys/timeb.h b/tools/sdk/include/newlib/sys/timeb.h
new file mode 100644
index 00000000..0a2c3de8
--- /dev/null
+++ b/tools/sdk/include/newlib/sys/timeb.h
@@ -0,0 +1,39 @@
+/* timeb.h -- An implementation of the standard Unix  file.
+   Written by Ian Lance Taylor 
+   Public domain; no rights reserved.
+
+    declares the structure used by the ftime function, as
+   well as the ftime function itself.  Newlib does not provide an
+   implementation of ftime.  */
+
+#ifndef _SYS_TIMEB_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define _SYS_TIMEB_H
+
+#include <_ansi.h>
+#include 
+
+#ifndef __time_t_defined
+typedef _TIME_T_ time_t;
+#define __time_t_defined
+#endif
+
+struct timeb
+{
+  time_t time;
+  unsigned short millitm;
+  short timezone;
+  short dstflag;
+};
+
+extern int ftime _PARAMS ((struct timeb *));
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! defined (_SYS_TIMEB_H) */
diff --git a/tools/sdk/include/newlib/sys/times.h b/tools/sdk/include/newlib/sys/times.h
new file mode 100644
index 00000000..927812cb
--- /dev/null
+++ b/tools/sdk/include/newlib/sys/times.h
@@ -0,0 +1,31 @@
+#ifndef	_SYS_TIMES_H
+#ifdef __cplusplus
+extern "C" {
+#endif
+#define	_SYS_TIMES_H
+
+#include <_ansi.h>
+#include 
+
+#ifndef __clock_t_defined
+typedef _CLOCK_T_ clock_t;
+#define __clock_t_defined
+#endif
+
+/*  Get Process Times, P1003.1b-1993, p. 92 */
+struct tms {
+	clock_t	tms_utime;		/* user time */
+	clock_t	tms_stime;		/* system time */
+	clock_t	tms_cutime;		/* user time, children */
+	clock_t	tms_cstime;		/* system time, children */
+};
+
+clock_t _EXFUN(times,(struct tms *));
+#ifdef _COMPILING_NEWLIB
+clock_t _EXFUN(_times,(struct tms *));
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif	/* !_SYS_TIMES_H */
diff --git a/tools/sdk/include/newlib/sys/types.h b/tools/sdk/include/newlib/sys/types.h
new file mode 100644
index 00000000..ed33e0a6
--- /dev/null
+++ b/tools/sdk/include/newlib/sys/types.h
@@ -0,0 +1,521 @@
+/* unified sys/types.h: 
+   start with sef's sysvi386 version.
+   merge go32 version -- a few ifdefs.
+   h8300hms, h8300xray, and sysvnecv70 disagree on the following types:
+
+   typedef int gid_t;
+   typedef int uid_t;
+   typedef int dev_t;
+   typedef int ino_t;
+   typedef int mode_t;
+   typedef int caddr_t;
+
+   however, these aren't "reasonable" values, the sysvi386 ones make far 
+   more sense, and should work sufficiently well (in particular, h8300 
+   doesn't have a stat, and the necv70 doesn't matter.) -- eichin
+ */
+
+#ifndef _SYS_TYPES_H
+
+#include <_ansi.h>
+
+#ifndef __INTTYPES_DEFINED__
+#define __INTTYPES_DEFINED__
+
+#include 
+
+#if defined(__rtems__) || defined(__XMK__)
+/*
+ *  The following section is RTEMS specific and is needed to more
+ *  closely match the types defined in the BSD sys/types.h.
+ *  This is needed to let the RTEMS/BSD TCP/IP stack compile.
+ */
+
+/* deprecated */
+#if ___int8_t_defined
+typedef __uint8_t	u_int8_t;
+#endif
+#if ___int16_t_defined
+typedef __uint16_t	u_int16_t;
+#endif 
+#if ___int32_t_defined
+typedef __uint32_t	u_int32_t;
+#endif
+
+#if ___int64_t_defined
+typedef __uint64_t	u_int64_t;
+
+/* deprecated */
+typedef	__uint64_t	u_quad_t;
+typedef	__int64_t	quad_t;
+typedef	quad_t *	qaddr_t;
+#endif
+
+#endif
+
+#endif /* ! __INTTYPES_DEFINED */
+
+#ifndef __need_inttypes
+
+#define _SYS_TYPES_H
+#include 
+
+#ifdef __i386__
+#if defined (GO32) || defined (__MSDOS__)
+#define __MS_types__
+#endif
+#endif
+
+# include 
+# include 
+
+/* To ensure the stat struct's layout doesn't change when sizeof(int), etc.
+   changes, we assume sizeof short and long never change and have all types
+   used to define struct stat use them and not int where possible.
+   Where not possible, _ST_INTxx are used.  It would be preferable to not have
+   such assumptions, but until the extra fluff is necessary, it's avoided.
+   No 64 bit targets use stat yet.  What to do about them is postponed
+   until necessary.  */
+#ifdef __GNUC__
+#define _ST_INT32 __attribute__ ((__mode__ (__SI__)))
+#else
+#define _ST_INT32
+#endif
+
+# ifndef	_POSIX_SOURCE
+
+#  define	physadr		physadr_t
+#  define	quad		quad_t
+
+#ifndef _BSDTYPES_DEFINED
+/* also defined in mingw/gmon.h and in w32api/winsock[2].h */
+#ifndef __u_char_defined
+typedef	unsigned char	u_char;
+#define __u_char_defined
+#endif
+#ifndef __u_short_defined
+typedef	unsigned short	u_short;
+#define __u_short_defined
+#endif
+#ifndef __u_int_defined
+typedef	unsigned int	u_int;
+#define __u_int_defined
+#endif
+#ifndef __u_long_defined
+typedef	unsigned long	u_long;
+#define __u_long_defined
+#endif
+#define _BSDTYPES_DEFINED
+#endif
+
+typedef	unsigned short	ushort;		/* System V compatibility */
+typedef	unsigned int	uint;		/* System V compatibility */
+typedef	unsigned long	ulong;		/* System V compatibility */
+# endif	/*!_POSIX_SOURCE */
+
+#ifndef __clock_t_defined
+typedef _CLOCK_T_ clock_t;
+#define __clock_t_defined
+#endif
+
+#ifndef __time_t_defined
+typedef _TIME_T_ time_t;
+#define __time_t_defined
+#endif
+
+#ifndef __timespec_defined
+#define __timespec_defined
+/* Time Value Specification Structures, P1003.1b-1993, p. 261 */
+
+struct timespec {
+  time_t  tv_sec;   /* Seconds */
+  long    tv_nsec;  /* Nanoseconds */
+};
+#endif
+
+struct itimerspec {
+  struct timespec  it_interval;  /* Timer period */
+  struct timespec  it_value;     /* Timer expiration */
+};
+
+#ifndef __daddr_t_defined
+typedef	long	daddr_t;
+#define __daddr_t_defined
+#endif
+#ifndef __caddr_t_defined
+typedef	char *	caddr_t;
+#define __caddr_t_defined
+#endif
+
+#ifndef __CYGWIN__
+#if defined(__MS_types__) || defined(__rtems__) || \
+    defined(__sparc__) || defined(__SPU__)
+typedef	unsigned long	ino_t;
+#else
+typedef	unsigned short	ino_t;
+#endif
+#endif /*__CYGWIN__*/
+
+#ifdef __MS_types__
+typedef unsigned long vm_offset_t;
+typedef unsigned long vm_size_t;
+
+#define __BIT_TYPES_DEFINED__
+
+typedef signed char int8_t;
+typedef unsigned char u_int8_t;
+typedef short int16_t;
+typedef unsigned short u_int16_t;
+typedef int int32_t;
+typedef unsigned int u_int32_t;
+typedef long long int64_t;
+typedef unsigned long long u_int64_t;
+typedef int32_t register_t;
+#endif /* __MS_types__ */
+
+/*
+ * All these should be machine specific - right now they are all broken.
+ * However, for all of Cygnus' embedded targets, we want them to all be
+ * the same.  Otherwise things like sizeof (struct stat) might depend on
+ * how the file was compiled (e.g. -mint16 vs -mint32, etc.).
+ */
+
+#ifndef __CYGWIN__	/* which defines these types in it's own types.h. */
+typedef _off_t	off_t;
+typedef __dev_t dev_t;
+typedef __uid_t uid_t;
+typedef __gid_t gid_t;
+#endif
+
+#if defined(__XMK__)
+typedef signed char pid_t;
+#else
+typedef int pid_t;
+#endif
+
+#if defined(__rtems__)
+typedef _mode_t mode_t;
+#endif
+
+#ifndef __CYGWIN__
+typedef	long key_t;
+#endif
+typedef _ssize_t ssize_t;
+
+#if !defined(__CYGWIN__) && !defined(__rtems__)
+#ifdef __MS_types__
+typedef	char *	addr_t;
+typedef int mode_t;
+#else
+#if defined (__sparc__) && !defined (__sparc_v9__)
+#ifdef __svr4__
+typedef unsigned long mode_t;
+#else
+typedef unsigned short mode_t;
+#endif
+#else
+typedef unsigned int mode_t _ST_INT32;
+#endif
+#endif /* ! __MS_types__ */
+#endif /*__CYGWIN__*/
+
+typedef unsigned short nlink_t;
+
+/* We don't define fd_set and friends if we are compiling POSIX
+   source, or if we have included (or may include as indicated
+   by __USE_W32_SOCKETS) the W32api winsock[2].h header which
+   defines Windows versions of them.   Note that a program which
+   includes the W32api winsock[2].h header must know what it is doing;
+   it must not call the cygwin32 select function.
+*/
+# if !(defined (_POSIX_SOURCE) || defined (_WINSOCK_H) || defined (_WINSOCKAPI_) || defined (__USE_W32_SOCKETS)) 
+#  define _SYS_TYPES_FD_SET
+#  define	NBBY	8		/* number of bits in a byte */
+/*
+ * Select uses bit masks of file descriptors in longs.
+ * These macros manipulate such bit fields (the filesystem macros use chars).
+ * FD_SETSIZE may be defined by the user, but the default here
+ * should be >= NOFILE (param.h).
+ */
+#  ifndef	FD_SETSIZE
+#	define	FD_SETSIZE	64
+#  endif
+
+typedef	long	fd_mask;
+#  define	NFDBITS	(sizeof (fd_mask) * NBBY)	/* bits per mask */
+#  ifndef	howmany
+#	define	howmany(x,y)	(((x)+((y)-1))/(y))
+#  endif
+
+/* We use a macro for fd_set so that including Sockets.h afterwards
+   can work.  */
+typedef	struct _types_fd_set {
+	fd_mask	fds_bits[howmany(FD_SETSIZE, NFDBITS)];
+} _types_fd_set;
+
+#define fd_set _types_fd_set
+
+#  define	FD_SET(n, p)	((p)->fds_bits[(n)/NFDBITS] |= (1L << ((n) % NFDBITS)))
+#  define	FD_CLR(n, p)	((p)->fds_bits[(n)/NFDBITS] &= ~(1L << ((n) % NFDBITS)))
+#  define	FD_ISSET(n, p)	((p)->fds_bits[(n)/NFDBITS] & (1L << ((n) % NFDBITS)))
+#  define	FD_ZERO(p)	(__extension__ (void)({ \
+     size_t __i; \
+     char *__tmp = (char *)p; \
+     for (__i = 0; __i < sizeof (*(p)); ++__i) \
+       *__tmp++ = 0; \
+}))
+
+# endif	/* !(defined (_POSIX_SOURCE) || defined (_WINSOCK_H) || defined (_WINSOCKAPI_) || defined (__USE_W32_SOCKETS)) */
+
+#undef __MS_types__
+#undef _ST_INT32
+
+
+#ifndef __clockid_t_defined
+typedef _CLOCKID_T_ clockid_t;
+#define __clockid_t_defined
+#endif
+
+#ifndef __timer_t_defined
+typedef _TIMER_T_ timer_t;
+#define __timer_t_defined
+#endif
+
+typedef unsigned long useconds_t;
+typedef long suseconds_t;
+
+#include 
+
+
+/* Cygwin will probably never have full posix compliance due to little things
+ * like an inability to set the stackaddress. Cygwin is also using void *  
+ * pointers rather than structs to ensure maximum binary compatability with
+ * previous releases.
+ * This means that we don't use the types defined here, but rather in
+ * 
+ */
+#if defined(_POSIX_THREADS) && !defined(__CYGWIN__)
+
+#include 
+
+/*
+ *  2.5 Primitive System Data Types,  P1003.1c/D10, p. 19.
+ */
+
+#if defined(__XMK__)
+typedef unsigned int pthread_t;          /* identify a thread */
+#else
+typedef __uint32_t pthread_t;            /* identify a thread */
+#endif
+
+/* P1003.1c/D10, p. 118-119 */
+#define PTHREAD_SCOPE_PROCESS 0
+#define PTHREAD_SCOPE_SYSTEM  1
+
+/* P1003.1c/D10, p. 111 */
+#define PTHREAD_INHERIT_SCHED  1      /* scheduling policy and associated */
+                                      /*   attributes are inherited from */
+                                      /*   the calling thread. */
+#define PTHREAD_EXPLICIT_SCHED 2      /* set from provided attribute object */
+
+/* P1003.1c/D10, p. 141 */
+#define PTHREAD_CREATE_DETACHED 0
+#define PTHREAD_CREATE_JOINABLE  1
+
+#if defined(__rtems__)
+  #include 
+#endif
+
+#if defined(__XMK__)
+typedef struct pthread_attr_s {
+  int contentionscope;
+  struct sched_param schedparam;
+  int  detachstate;
+  void *stackaddr;
+  size_t stacksize;
+} pthread_attr_t;
+
+#define PTHREAD_STACK_MIN       200
+
+#else /* !defined(__XMK__) */
+typedef struct {
+  int is_initialized;
+  void *stackaddr;
+  int stacksize;
+  int contentionscope;
+  int inheritsched;
+  int schedpolicy;
+  struct sched_param schedparam;
+#if defined(__rtems__)
+  size_t guardsize;
+#endif
+
+  /* P1003.4b/D8, p. 54 adds cputime_clock_allowed attribute.  */
+#if defined(_POSIX_THREAD_CPUTIME)
+  int  cputime_clock_allowed;  /* see time.h */
+#endif
+  int  detachstate;
+#if defined(__rtems__)
+  size_t affinitysetsize;
+  cpu_set_t *affinityset;
+  cpu_set_t affinitysetpreallocated;
+#endif
+} pthread_attr_t;
+
+#endif /* !defined(__XMK__) */
+
+#if defined(_POSIX_THREAD_PROCESS_SHARED)
+/* NOTE: P1003.1c/D10, p. 81 defines following values for process_shared.  */
+
+#define PTHREAD_PROCESS_PRIVATE 0 /* visible within only the creating process */
+#define PTHREAD_PROCESS_SHARED  1 /* visible too all processes with access to */
+                                  /*   the memory where the resource is */
+                                  /*   located */
+#endif
+
+#if defined(_POSIX_THREAD_PRIO_PROTECT)
+/* Mutexes */
+
+/* Values for blocking protocol. */
+
+#define PTHREAD_PRIO_NONE    0
+#define PTHREAD_PRIO_INHERIT 1
+#define PTHREAD_PRIO_PROTECT 2
+#endif
+
+#if defined(_UNIX98_THREAD_MUTEX_ATTRIBUTES)
+
+/* Values for mutex type */
+
+/* The following defines are part of the X/Open System Interface (XSI). */
+
+/*
+ * This type of mutex does not detect deadlock. A thread attempting to
+ * relock this mutex without first unlocking it shall deadlock. Attempting
+ * to unlock a mutex locked by a different thread results in undefined
+ * behavior.  Attempting to unlock an unlocked mutex results in undefined
+ * behavior.
+ */
+#define PTHREAD_MUTEX_NORMAL     0
+
+/*
+ * A thread attempting to relock this mutex without first unlocking
+ * it shall succeed in locking the mutex.  The relocking deadlock which
+ * can occur with mutexes of type PTHREAD_MUTEX_NORMAL cannot occur with
+ * this type of mutex.  Multiple locks of this mutex shall require the
+ * same number of unlocks to release the mutex before another thread can
+ * acquire the mutex. A thread attempting to unlock a mutex which another
+ * thread has locked shall return with an error.  A thread attempting to
+ * unlock an unlocked mutex shall return with an error.
+ */
+#define PTHREAD_MUTEX_RECURSIVE  1
+
+/* 
+ * This type of mutex provides error checking. A thread attempting
+ * to relock this mutex without first unlocking it shall return with an
+ * error. A thread attempting to unlock a mutex which another thread has
+ * locked shall return with an error. A thread attempting to unlock an
+ * unlocked mutex shall return with an error.
+ */
+#define PTHREAD_MUTEX_ERRORCHECK 2
+
+/*
+ * Attempting to recursively lock a mutex of this type results
+ * in undefined behavior. Attempting to unlock a mutex of this type
+ * which was not locked by the calling thread results in undefined
+ * behavior. Attempting to unlock a mutex of this type which is not locked
+ * results in undefined behavior. An implementation may map this mutex to
+ * one of the other mutex types.
+ */
+#define PTHREAD_MUTEX_DEFAULT    3
+
+#endif /* !defined(_UNIX98_THREAD_MUTEX_ATTRIBUTES) */
+
+#if defined(__XMK__)
+typedef unsigned int pthread_mutex_t;    /* identify a mutex */
+
+typedef struct {
+  int type;
+} pthread_mutexattr_t;
+
+#else /* !defined(__XMK__) */
+typedef __uint32_t pthread_mutex_t;      /* identify a mutex */
+
+typedef struct {
+  int   is_initialized;
+#if defined(_POSIX_THREAD_PROCESS_SHARED)
+  int   process_shared;  /* allow mutex to be shared amongst processes */
+#endif
+#if defined(_POSIX_THREAD_PRIO_PROTECT)
+  int   prio_ceiling;
+  int   protocol;
+#endif
+#if defined(_UNIX98_THREAD_MUTEX_ATTRIBUTES)
+  int type;
+#endif
+  int   recursive;
+} pthread_mutexattr_t;
+#endif /* !defined(__XMK__) */
+
+/* Condition Variables */
+
+typedef __uint32_t pthread_cond_t;       /* identify a condition variable */
+
+typedef struct {
+  int   is_initialized;
+#if defined(_POSIX_THREAD_PROCESS_SHARED)
+  int   process_shared;       /* allow this to be shared amongst processes */
+#endif
+} pthread_condattr_t;         /* a condition attribute object */
+
+/* Keys */
+
+typedef __uint32_t pthread_key_t;        /* thread-specific data keys */
+
+typedef struct {
+  int   is_initialized;  /* is this structure initialized? */
+  int   init_executed;   /* has the initialization routine been run? */
+} pthread_once_t;       /* dynamic package initialization */
+#else
+#if defined (__CYGWIN__)
+#include 
+#endif
+#endif /* defined(_POSIX_THREADS) */
+
+/* POSIX Barrier Types */
+
+#if defined(_POSIX_BARRIERS)
+typedef __uint32_t pthread_barrier_t;        /* POSIX Barrier Object */
+typedef struct {
+  int   is_initialized;  /* is this structure initialized? */
+#if defined(_POSIX_THREAD_PROCESS_SHARED)
+  int   process_shared;       /* allow this to be shared amongst processes */
+#endif
+} pthread_barrierattr_t;
+#endif /* defined(_POSIX_BARRIERS) */
+
+/* POSIX Spin Lock Types */
+
+#if !defined (__CYGWIN__)
+#if defined(_POSIX_SPIN_LOCKS)
+typedef __uint32_t pthread_spinlock_t;        /* POSIX Spin Lock Object */
+#endif /* defined(_POSIX_SPIN_LOCKS) */
+
+/* POSIX Reader/Writer Lock Types */
+
+#if defined(_POSIX_READER_WRITER_LOCKS)
+typedef __uint32_t pthread_rwlock_t;         /* POSIX RWLock Object */
+typedef struct {
+  int   is_initialized;       /* is this structure initialized? */
+#if defined(_POSIX_THREAD_PROCESS_SHARED)
+  int   process_shared;       /* allow this to be shared amongst processes */
+#endif
+} pthread_rwlockattr_t;
+#endif /* defined(_POSIX_READER_WRITER_LOCKS) */
+#endif /* __CYGWIN__ */
+
+#endif  /* !__need_inttypes */
+
+#undef __need_inttypes
+
+#endif	/* _SYS_TYPES_H */
diff --git a/tools/sdk/include/newlib/sys/unistd.h b/tools/sdk/include/newlib/sys/unistd.h
new file mode 100644
index 00000000..a741383d
--- /dev/null
+++ b/tools/sdk/include/newlib/sys/unistd.h
@@ -0,0 +1,516 @@
+#ifndef _SYS_UNISTD_H
+#define _SYS_UNISTD_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <_ansi.h>
+#define __need_size_t
+#define __need_ptrdiff_t
+#include 
+#include 
+#include 
+#include 
+
+extern char **environ;
+
+void	_EXFUN(_exit, (int __status ) _ATTRIBUTE ((__noreturn__)));
+
+int	_EXFUN(access,(const char *__path, int __amode ));
+unsigned  _EXFUN(alarm, (unsigned __secs ));
+int     _EXFUN(chdir, (const char *__path ));
+int     _EXFUN(chmod, (const char *__path, mode_t __mode ));
+#if !defined(__INSIDE_CYGWIN__)
+int     _EXFUN(chown, (const char *__path, uid_t __owner, gid_t __group ));
+#endif
+#if defined(__CYGWIN__) || defined(__rtems__)
+int     _EXFUN(chroot, (const char *__path ));
+#endif
+int     _EXFUN(close, (int __fildes ));
+#if defined(__CYGWIN__)
+size_t	_EXFUN(confstr, (int __name, char *__buf, size_t __len));
+#endif
+char *  _EXFUN(ctermid, (char *__s ));
+char *  _EXFUN(cuserid, (char *__s ));
+#if defined(__CYGWIN__)
+int	_EXFUN(daemon, (int nochdir, int noclose));
+#endif
+int     _EXFUN(dup, (int __fildes ));
+int     _EXFUN(dup2, (int __fildes, int __fildes2 ));
+#if defined(__CYGWIN__)
+int     _EXFUN(dup3, (int __fildes, int __fildes2, int flags));
+int	_EXFUN(eaccess, (const char *__path, int __mode));
+void	_EXFUN(endusershell, (void));
+int	_EXFUN(euidaccess, (const char *__path, int __mode));
+#endif
+int     _EXFUN(execl, (const char *__path, const char *, ... ));
+int     _EXFUN(execle, (const char *__path, const char *, ... ));
+int     _EXFUN(execlp, (const char *__file, const char *, ... ));
+#if defined(__CYGWIN__)
+int     _EXFUN(execlpe, (const char *__file, const char *, ... ));
+#endif
+int     _EXFUN(execv, (const char *__path, char * const __argv[] ));
+int     _EXFUN(execve, (const char *__path, char * const __argv[], char * const __envp[] ));
+int     _EXFUN(execvp, (const char *__file, char * const __argv[] ));
+#if defined(__CYGWIN__)
+int     _EXFUN(execvpe, (const char *__file, char * const __argv[], char * const __envp[] ));
+#endif
+#if __POSIX_VISIBLE >= 200809 || __BSD_VISIBLE || defined(__CYGWIN__)
+int	_EXFUN(faccessat, (int __dirfd, const char *__path, int __mode, int __flags));
+#endif
+#if defined(__CYGWIN__) || defined(__rtems__) || defined(__SPU__)
+int     _EXFUN(fchdir, (int __fildes));
+#endif
+int     _EXFUN(fchmod, (int __fildes, mode_t __mode ));
+#if !defined(__INSIDE_CYGWIN__)
+int     _EXFUN(fchown, (int __fildes, uid_t __owner, gid_t __group ));
+#endif
+#if __POSIX_VISIBLE >= 200809 || __BSD_VISIBLE || defined(__CYGWIN__)
+int	_EXFUN(fchownat, (int __dirfd, const char *__path, uid_t __owner, gid_t __group, int __flags));
+#endif
+#if defined(__CYGWIN__)
+int	_EXFUN(fexecve, (int __fd, char * const __argv[], char * const __envp[] ));
+#endif
+pid_t   _EXFUN(fork, (void ));
+long    _EXFUN(fpathconf, (int __fd, int __name ));
+int     _EXFUN(fsync, (int __fd));
+int     _EXFUN(fdatasync, (int __fd));
+#if defined(__CYGWIN__)
+char *  _EXFUN(get_current_dir_name, (void));
+#endif
+char *  _EXFUN(getcwd, (char *__buf, size_t __size ));
+#if defined(__CYGWIN__)
+int	_EXFUN(getdomainname ,(char *__name, size_t __len));
+#endif
+#if !defined(__INSIDE_CYGWIN__)
+gid_t   _EXFUN(getegid, (void ));
+uid_t   _EXFUN(geteuid, (void ));
+gid_t   _EXFUN(getgid, (void ));
+#endif
+int     _EXFUN(getgroups, (int __gidsetsize, gid_t __grouplist[] ));
+#if defined(__CYGWIN__)
+long    _EXFUN(gethostid, (void));
+#endif
+char *  _EXFUN(getlogin, (void ));
+#if defined(_POSIX_THREAD_SAFE_FUNCTIONS)
+int _EXFUN(getlogin_r, (char *name, size_t namesize) );
+#endif
+char *  _EXFUN(getpass, (const char *__prompt));
+int	_EXFUN(getpagesize, (void));
+#if defined(__CYGWIN__)
+int    _EXFUN(getpeereid, (int, uid_t *, gid_t *));
+#endif
+pid_t   _EXFUN(getpgid, (pid_t));
+pid_t   _EXFUN(getpgrp, (void ));
+pid_t   _EXFUN(getpid, (void ));
+pid_t   _EXFUN(getppid, (void ));
+#if defined(__CYGWIN__) || defined(__rtems__)
+pid_t   _EXFUN(getsid, (pid_t));
+#endif
+#if !defined(__INSIDE_CYGWIN__)
+uid_t   _EXFUN(getuid, (void ));
+#endif
+#ifdef __CYGWIN__
+char *	_EXFUN(getusershell, (void));
+char *  _EXFUN(getwd, (char *__buf ));
+int	_EXFUN(iruserok, (unsigned long raddr, int superuser, const char *ruser, const char *luser));
+#endif
+int     _EXFUN(isatty, (int __fildes ));
+#if !defined(__INSIDE_CYGWIN__)
+int     _EXFUN(lchown, (const char *__path, uid_t __owner, gid_t __group ));
+#endif
+int     _EXFUN(link, (const char *__path1, const char *__path2 ));
+#if __POSIX_VISIBLE >= 200809 || __BSD_VISIBLE || defined(__CYGWIN__)
+int     _EXFUN(linkat, (int __dirfd1, const char *__path1, int __dirfd2, const char *__path2, int __flags ));
+#endif
+int	_EXFUN(nice, (int __nice_value ));
+#if !defined(__INSIDE_CYGWIN__)
+off_t   _EXFUN(lseek, (int __fildes, off_t __offset, int __whence ));
+#endif
+#if defined(__SPU__) || defined(__CYGWIN__)
+#define F_ULOCK	0
+#define F_LOCK	1
+#define F_TLOCK	2
+#define F_TEST	3
+int     _EXFUN(lockf, (int __fd, int __cmd, off_t __len));
+#endif
+long    _EXFUN(pathconf, (const char *__path, int __name ));
+int     _EXFUN(pause, (void ));
+#ifdef __CYGWIN__
+int	_EXFUN(pthread_atfork, (void (*)(void), void (*)(void), void (*)(void)));
+#endif
+int     _EXFUN(pipe, (int __fildes[2] ));
+#ifdef __CYGWIN__
+int     _EXFUN(pipe2, (int __fildes[2], int flags));
+#endif
+ssize_t _EXFUN(pread, (int __fd, void *__buf, size_t __nbytes, off_t __offset));
+ssize_t _EXFUN(pwrite, (int __fd, const void *__buf, size_t __nbytes, off_t __offset));
+_READ_WRITE_RETURN_TYPE _EXFUN(read, (int __fd, void *__buf, size_t __nbyte ));
+#if defined(__CYGWIN__)
+int	_EXFUN(rresvport, (int *__alport));
+int	_EXFUN(revoke, (char *__path));
+#endif
+int     _EXFUN(rmdir, (const char *__path ));
+#if defined(__CYGWIN__)
+int	_EXFUN(ruserok, (const char *rhost, int superuser, const char *ruser, const char *luser));
+#endif
+void *  _EXFUN(sbrk,  (ptrdiff_t __incr));
+#if !defined(__INSIDE_CYGWIN__)
+#if defined(__CYGWIN__) || defined(__rtems__)
+int     _EXFUN(setegid, (gid_t __gid ));
+int     _EXFUN(seteuid, (uid_t __uid ));
+#endif
+int     _EXFUN(setgid, (gid_t __gid ));
+#endif
+#if defined(__CYGWIN__)
+int	_EXFUN(setgroups, (int ngroups, const gid_t *grouplist ));
+#endif
+#if __BSD_VISIBLE || (defined(_XOPEN_SOURCE) && __XSI_VISIBLE < 500)
+int	_EXFUN(sethostname, (const char *, size_t));
+#endif
+int     _EXFUN(setpgid, (pid_t __pid, pid_t __pgid ));
+int     _EXFUN(setpgrp, (void ));
+#if defined(__CYGWIN__) && !defined(__INSIDE_CYGWIN__)
+int	_EXFUN(setregid, (gid_t __rgid, gid_t __egid));
+int	_EXFUN(setreuid, (uid_t __ruid, uid_t __euid));
+#endif
+pid_t   _EXFUN(setsid, (void ));
+#if !defined(__INSIDE_CYGWIN__)
+int     _EXFUN(setuid, (uid_t __uid ));
+#endif
+#if defined(__CYGWIN__)
+void	_EXFUN(setusershell, (void));
+#endif
+unsigned _EXFUN(sleep, (unsigned int __seconds ));
+void    _EXFUN(swab, (const void *__restrict, void *__restrict, ssize_t));
+long    _EXFUN(sysconf, (int __name ));
+pid_t   _EXFUN(tcgetpgrp, (int __fildes ));
+int     _EXFUN(tcsetpgrp, (int __fildes, pid_t __pgrp_id ));
+char *  _EXFUN(ttyname, (int __fildes ));
+#if defined(__CYGWIN__) || defined(__rtems__)
+int     _EXFUN(ttyname_r, (int, char *, size_t)); 
+#endif
+int     _EXFUN(unlink, (const char *__path ));
+int 	_EXFUN(usleep, (useconds_t __useconds));
+int     _EXFUN(vhangup, (void ));
+_READ_WRITE_RETURN_TYPE _EXFUN(write, (int __fd, const void *__buf, size_t __nbyte ));
+
+#ifdef __CYGWIN__
+# define __UNISTD_GETOPT__
+# include 
+# undef __UNISTD_GETOPT__
+#else
+extern char *optarg;			/* getopt(3) external variables */
+extern int optind, opterr, optopt;
+int	 getopt(int, char * const [], const char *);
+extern int optreset;			/* getopt(3) external variable */
+#endif
+
+#ifndef        _POSIX_SOURCE
+pid_t   _EXFUN(vfork, (void ));
+#endif /* _POSIX_SOURCE */
+
+#ifdef _COMPILING_NEWLIB
+/* Provide prototypes for most of the _ names that are
+   provided in newlib for some compilers.  */
+int     _EXFUN(_close, (int __fildes ));
+pid_t   _EXFUN(_fork, (void ));
+pid_t   _EXFUN(_getpid, (void ));
+int	_EXFUN(_isatty, (int __fildes ));
+int     _EXFUN(_link, (const char *__path1, const char *__path2 ));
+_off_t   _EXFUN(_lseek, (int __fildes, _off_t __offset, int __whence ));
+#ifdef __LARGE64_FILES
+_off64_t _EXFUN(_lseek64, (int __filedes, _off64_t __offset, int __whence ));
+#endif
+_READ_WRITE_RETURN_TYPE _EXFUN(_read, (int __fd, void *__buf, size_t __nbyte ));
+void *  _EXFUN(_sbrk,  (ptrdiff_t __incr));
+int     _EXFUN(_unlink, (const char *__path ));
+_READ_WRITE_RETURN_TYPE _EXFUN(_write, (int __fd, const void *__buf, size_t __nbyte ));
+int     _EXFUN(_execve, (const char *__path, char * const __argv[], char * const __envp[] ));
+#endif
+
+#if defined(__CYGWIN__) || defined(__rtems__) || defined(__aarch64__) || defined (__arm__) || defined(__sh__) || defined(__SPU__)
+#if !defined(__INSIDE_CYGWIN__)
+int     _EXFUN(ftruncate, (int __fd, off_t __length));
+int     _EXFUN(truncate, (const char *, off_t __length));
+#endif
+#endif
+
+#if defined(__CYGWIN__) || defined(__rtems__)
+int	_EXFUN(getdtablesize, (void));
+int	_EXFUN(setdtablesize, (int));
+useconds_t _EXFUN(ualarm, (useconds_t __useconds, useconds_t __interval));
+#if !(defined  (_WINSOCK_H) || defined (_WINSOCKAPI_) || defined (__USE_W32_SOCKETS))
+/* winsock[2].h defines as __stdcall, and with int as 2nd arg */
+ int	_EXFUN(gethostname, (char *__name, size_t __len));
+#endif
+char *	_EXFUN(mktemp, (char *));
+#endif
+
+#if defined(__CYGWIN__) || defined(__SPU__) || defined(__rtems__)
+void    _EXFUN(sync, (void));
+#endif
+
+ssize_t _EXFUN(readlink, (const char *__restrict __path,
+                          char *__restrict __buf, size_t __buflen));
+#if __POSIX_VISIBLE >= 200809 || __BSD_VISIBLE || defined(__CYGWIN__)
+ssize_t        _EXFUN(readlinkat, (int __dirfd1, const char *__restrict __path,
+                            char *__restrict __buf, size_t __buflen));
+#endif
+int     _EXFUN(symlink, (const char *__name1, const char *__name2));
+#if __POSIX_VISIBLE >= 200809 || __BSD_VISIBLE || defined(__CYGWIN__)
+int	_EXFUN(symlinkat, (const char *, int, const char *));
+int	_EXFUN(unlinkat, (int, const char *, int));
+#endif
+
+#define	F_OK	0
+#define	R_OK	4
+#define	W_OK	2
+#define	X_OK	1
+
+# define	SEEK_SET	0
+# define	SEEK_CUR	1
+# define	SEEK_END	2
+
+#include 
+
+#define STDIN_FILENO    0       /* standard input file descriptor */
+#define STDOUT_FILENO   1       /* standard output file descriptor */
+#define STDERR_FILENO   2       /* standard error file descriptor */
+
+/*
+ *  sysconf values per IEEE Std 1003.1, 2008 Edition
+ */
+
+#define _SC_ARG_MAX                       0
+#define _SC_CHILD_MAX                     1
+#define _SC_CLK_TCK                       2
+#define _SC_NGROUPS_MAX                   3
+#define _SC_OPEN_MAX                      4
+#define _SC_JOB_CONTROL                   5
+#define _SC_SAVED_IDS                     6
+#define _SC_VERSION                       7
+#define _SC_PAGESIZE                      8
+#define _SC_PAGE_SIZE                     _SC_PAGESIZE
+/* These are non-POSIX values we accidentally introduced in 2000 without
+   guarding them.  Keeping them unguarded for backward compatibility. */
+#define _SC_NPROCESSORS_CONF              9
+#define _SC_NPROCESSORS_ONLN             10
+#define _SC_PHYS_PAGES                   11
+#define _SC_AVPHYS_PAGES                 12
+/* End of non-POSIX values. */
+#define _SC_MQ_OPEN_MAX                  13
+#define _SC_MQ_PRIO_MAX                  14
+#define _SC_RTSIG_MAX                    15
+#define _SC_SEM_NSEMS_MAX                16
+#define _SC_SEM_VALUE_MAX                17
+#define _SC_SIGQUEUE_MAX                 18
+#define _SC_TIMER_MAX                    19
+#define _SC_TZNAME_MAX                   20
+#define _SC_ASYNCHRONOUS_IO              21
+#define _SC_FSYNC                        22
+#define _SC_MAPPED_FILES                 23
+#define _SC_MEMLOCK                      24
+#define _SC_MEMLOCK_RANGE                25
+#define _SC_MEMORY_PROTECTION            26
+#define _SC_MESSAGE_PASSING              27
+#define _SC_PRIORITIZED_IO               28
+#define _SC_REALTIME_SIGNALS             29
+#define _SC_SEMAPHORES                   30
+#define _SC_SHARED_MEMORY_OBJECTS        31
+#define _SC_SYNCHRONIZED_IO              32
+#define _SC_TIMERS                       33
+#define _SC_AIO_LISTIO_MAX               34
+#define _SC_AIO_MAX                      35
+#define _SC_AIO_PRIO_DELTA_MAX           36
+#define _SC_DELAYTIMER_MAX               37
+#define _SC_THREAD_KEYS_MAX              38
+#define _SC_THREAD_STACK_MIN             39
+#define _SC_THREAD_THREADS_MAX           40
+#define _SC_TTY_NAME_MAX                 41
+#define _SC_THREADS                      42
+#define _SC_THREAD_ATTR_STACKADDR        43
+#define _SC_THREAD_ATTR_STACKSIZE        44
+#define _SC_THREAD_PRIORITY_SCHEDULING   45
+#define _SC_THREAD_PRIO_INHERIT          46
+/* _SC_THREAD_PRIO_PROTECT was _SC_THREAD_PRIO_CEILING in early drafts */
+#define _SC_THREAD_PRIO_PROTECT          47
+#define _SC_THREAD_PRIO_CEILING          _SC_THREAD_PRIO_PROTECT
+#define _SC_THREAD_PROCESS_SHARED        48
+#define _SC_THREAD_SAFE_FUNCTIONS        49
+#define _SC_GETGR_R_SIZE_MAX             50
+#define _SC_GETPW_R_SIZE_MAX             51
+#define _SC_LOGIN_NAME_MAX               52
+#define _SC_THREAD_DESTRUCTOR_ITERATIONS 53
+#define _SC_ADVISORY_INFO                54
+#define _SC_ATEXIT_MAX                   55
+#define _SC_BARRIERS                     56
+#define _SC_BC_BASE_MAX                  57
+#define _SC_BC_DIM_MAX                   58
+#define _SC_BC_SCALE_MAX                 59
+#define _SC_BC_STRING_MAX                60
+#define _SC_CLOCK_SELECTION              61
+#define _SC_COLL_WEIGHTS_MAX             62
+#define _SC_CPUTIME                      63
+#define _SC_EXPR_NEST_MAX                64
+#define _SC_HOST_NAME_MAX                65
+#define _SC_IOV_MAX                      66
+#define _SC_IPV6                         67
+#define _SC_LINE_MAX                     68
+#define _SC_MONOTONIC_CLOCK              69
+#define _SC_RAW_SOCKETS                  70
+#define _SC_READER_WRITER_LOCKS          71
+#define _SC_REGEXP                       72
+#define _SC_RE_DUP_MAX                   73
+#define _SC_SHELL                        74
+#define _SC_SPAWN                        75
+#define _SC_SPIN_LOCKS                   76
+#define _SC_SPORADIC_SERVER              77
+#define _SC_SS_REPL_MAX                  78
+#define _SC_SYMLOOP_MAX                  79
+#define _SC_THREAD_CPUTIME               80
+#define _SC_THREAD_SPORADIC_SERVER       81
+#define _SC_TIMEOUTS                     82
+#define _SC_TRACE                        83
+#define _SC_TRACE_EVENT_FILTER           84
+#define _SC_TRACE_EVENT_NAME_MAX         85
+#define _SC_TRACE_INHERIT                86
+#define _SC_TRACE_LOG                    87
+#define _SC_TRACE_NAME_MAX               88
+#define _SC_TRACE_SYS_MAX                89
+#define _SC_TRACE_USER_EVENT_MAX         90
+#define _SC_TYPED_MEMORY_OBJECTS         91
+#define _SC_V7_ILP32_OFF32               92
+#define _SC_V6_ILP32_OFF32               _SC_V7_ILP32_OFF32
+#define _SC_XBS5_ILP32_OFF32             _SC_V7_ILP32_OFF32
+#define _SC_V7_ILP32_OFFBIG              93
+#define _SC_V6_ILP32_OFFBIG              _SC_V7_ILP32_OFFBIG
+#define _SC_XBS5_ILP32_OFFBIG            _SC_V7_ILP32_OFFBIG
+#define _SC_V7_LP64_OFF64                94
+#define _SC_V6_LP64_OFF64                _SC_V7_LP64_OFF64
+#define _SC_XBS5_LP64_OFF64              _SC_V7_LP64_OFF64
+#define _SC_V7_LPBIG_OFFBIG              95
+#define _SC_V6_LPBIG_OFFBIG              _SC_V7_LPBIG_OFFBIG
+#define _SC_XBS5_LPBIG_OFFBIG            _SC_V7_LPBIG_OFFBIG
+#define _SC_XOPEN_CRYPT                  96
+#define _SC_XOPEN_ENH_I18N               97
+#define _SC_XOPEN_LEGACY                 98
+#define _SC_XOPEN_REALTIME               99
+#define _SC_STREAM_MAX                  100
+#define _SC_PRIORITY_SCHEDULING         101
+#define _SC_XOPEN_REALTIME_THREADS      102
+#define _SC_XOPEN_SHM                   103
+#define _SC_XOPEN_STREAMS               104
+#define _SC_XOPEN_UNIX                  105
+#define _SC_XOPEN_VERSION               106
+#define _SC_2_CHAR_TERM                 107
+#define _SC_2_C_BIND                    108
+#define _SC_2_C_DEV                     109
+#define _SC_2_FORT_DEV                  110
+#define _SC_2_FORT_RUN                  111
+#define _SC_2_LOCALEDEF                 112
+#define _SC_2_PBS                       113
+#define _SC_2_PBS_ACCOUNTING            114
+#define _SC_2_PBS_CHECKPOINT            115
+#define _SC_2_PBS_LOCATE                116
+#define _SC_2_PBS_MESSAGE               117
+#define _SC_2_PBS_TRACK                 118
+#define _SC_2_SW_DEV                    119
+#define _SC_2_UPE                       120
+#define _SC_2_VERSION                   121
+#define _SC_THREAD_ROBUST_PRIO_INHERIT  122
+#define _SC_THREAD_ROBUST_PRIO_PROTECT  123
+#define _SC_XOPEN_UUCP                  124
+
+/*
+ *  pathconf values per IEEE Std 1003.1, 2008 Edition
+ */
+
+#define _PC_LINK_MAX                      0
+#define _PC_MAX_CANON                     1
+#define _PC_MAX_INPUT                     2
+#define _PC_NAME_MAX                      3
+#define _PC_PATH_MAX                      4
+#define _PC_PIPE_BUF                      5
+#define _PC_CHOWN_RESTRICTED              6
+#define _PC_NO_TRUNC                      7
+#define _PC_VDISABLE                      8
+#define _PC_ASYNC_IO                      9
+#define _PC_PRIO_IO                      10
+#define _PC_SYNC_IO                      11
+#define _PC_FILESIZEBITS                 12
+#define _PC_2_SYMLINKS                   13
+#define _PC_SYMLINK_MAX                  14
+#define _PC_ALLOC_SIZE_MIN               15
+#define _PC_REC_INCR_XFER_SIZE           16
+#define _PC_REC_MAX_XFER_SIZE            17
+#define _PC_REC_MIN_XFER_SIZE            18
+#define _PC_REC_XFER_ALIGN               19
+#define _PC_TIMESTAMP_RESOLUTION         20
+#ifdef __CYGWIN__
+/* Ask for POSIX permission bits support. */
+#define _PC_POSIX_PERMISSIONS            90
+/* Ask for full POSIX permission support including uid/gid settings. */
+#define _PC_POSIX_SECURITY               91
+#endif
+
+/*
+ *  confstr values per IEEE Std 1003.1, 2004 Edition
+ */
+
+#ifdef __CYGWIN__	/* Only defined on Cygwin for now. */
+#define _CS_PATH                               0
+#define _CS_POSIX_V7_ILP32_OFF32_CFLAGS        1
+#define _CS_POSIX_V6_ILP32_OFF32_CFLAGS       _CS_POSIX_V7_ILP32_OFF32_CFLAGS
+#define _CS_XBS5_ILP32_OFF32_CFLAGS           _CS_POSIX_V7_ILP32_OFF32_CFLAGS
+#define _CS_POSIX_V7_ILP32_OFF32_LDFLAGS       2
+#define _CS_POSIX_V6_ILP32_OFF32_LDFLAGS      _CS_POSIX_V7_ILP32_OFF32_LDFLAGS
+#define _CS_XBS5_ILP32_OFF32_LDFLAGS          _CS_POSIX_V7_ILP32_OFF32_LDFLAGS
+#define _CS_POSIX_V7_ILP32_OFF32_LIBS          3
+#define _CS_POSIX_V6_ILP32_OFF32_LIBS         _CS_POSIX_V7_ILP32_OFF32_LIBS
+#define _CS_XBS5_ILP32_OFF32_LIBS             _CS_POSIX_V7_ILP32_OFF32_LIBS
+#define _CS_XBS5_ILP32_OFF32_LINTFLAGS         4
+#define _CS_POSIX_V7_ILP32_OFFBIG_CFLAGS       5
+#define _CS_POSIX_V6_ILP32_OFFBIG_CFLAGS      _CS_POSIX_V7_ILP32_OFFBIG_CFLAGS
+#define _CS_XBS5_ILP32_OFFBIG_CFLAGS          _CS_POSIX_V7_ILP32_OFFBIG_CFLAGS
+#define _CS_POSIX_V7_ILP32_OFFBIG_LDFLAGS      6
+#define _CS_POSIX_V6_ILP32_OFFBIG_LDFLAGS     _CS_POSIX_V7_ILP32_OFFBIG_LDFLAGS
+#define _CS_XBS5_ILP32_OFFBIG_LDFLAGS         _CS_POSIX_V7_ILP32_OFFBIG_LDFLAGS
+#define _CS_POSIX_V7_ILP32_OFFBIG_LIBS         7
+#define _CS_POSIX_V6_ILP32_OFFBIG_LIBS        _CS_POSIX_V7_ILP32_OFFBIG_LIBS
+#define _CS_XBS5_ILP32_OFFBIG_LIBS            _CS_POSIX_V7_ILP32_OFFBIG_LIBS
+#define _CS_XBS5_ILP32_OFFBIG_LINTFLAGS        8
+#define _CS_POSIX_V7_LP64_OFF64_CFLAGS         9
+#define _CS_POSIX_V6_LP64_OFF64_CFLAGS        _CS_POSIX_V7_LP64_OFF64_CFLAGS
+#define _CS_XBS5_LP64_OFF64_CFLAGS            _CS_POSIX_V7_LP64_OFF64_CFLAGS
+#define _CS_POSIX_V7_LP64_OFF64_LDFLAGS       10
+#define _CS_POSIX_V6_LP64_OFF64_LDFLAGS       _CS_POSIX_V7_LP64_OFF64_LDFLAGS
+#define _CS_XBS5_LP64_OFF64_LDFLAGS           _CS_POSIX_V7_LP64_OFF64_LDFLAGS
+#define _CS_POSIX_V7_LP64_OFF64_LIBS          11
+#define _CS_POSIX_V6_LP64_OFF64_LIBS          _CS_POSIX_V7_LP64_OFF64_LIBS
+#define _CS_XBS5_LP64_OFF64_LIBS              _CS_POSIX_V7_LP64_OFF64_LIBS
+#define _CS_XBS5_LP64_OFF64_LINTFLAGS         12
+#define _CS_POSIX_V7_LPBIG_OFFBIG_CFLAGS      13
+#define _CS_POSIX_V6_LPBIG_OFFBIG_CFLAGS      _CS_POSIX_V7_LPBIG_OFFBIG_CFLAGS
+#define _CS_XBS5_LPBIG_OFFBIG_CFLAGS          _CS_POSIX_V7_LPBIG_OFFBIG_CFLAGS
+#define _CS_POSIX_V7_LPBIG_OFFBIG_LDFLAGS     14
+#define _CS_POSIX_V6_LPBIG_OFFBIG_LDFLAGS     _CS_POSIX_V7_LPBIG_OFFBIG_LDFLAGS
+#define _CS_XBS5_LPBIG_OFFBIG_LDFLAGS         _CS_POSIX_V7_LPBIG_OFFBIG_LDFLAGS
+#define _CS_POSIX_V7_LPBIG_OFFBIG_LIBS        15
+#define _CS_POSIX_V6_LPBIG_OFFBIG_LIBS        _CS_POSIX_V7_LPBIG_OFFBIG_LIBS
+#define _CS_XBS5_LPBIG_OFFBIG_LIBS            _CS_POSIX_V7_LPBIG_OFFBIG_LIBS
+#define _CS_XBS5_LPBIG_OFFBIG_LINTFLAGS       16
+#define _CS_POSIX_V7_WIDTH_RESTRICTED_ENVS    17
+#define _CS_POSIX_V6_WIDTH_RESTRICTED_ENVS    _CS_POSIX_V7_WIDTH_RESTRICTED_ENVS
+#define _CS_XBS5_WIDTH_RESTRICTED_ENVS        _CS_POSIX_V7_WIDTH_RESTRICTED_ENVS
+#define _CS_POSIX_V7_THREADS_CFLAGS           18
+#define _CS_POSIX_V7_THREADS_LDFLAGS          19
+#define _CS_V7_ENV                            20
+#define _CS_V6_ENV                            _CS_V7_ENV
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _SYS_UNISTD_H */
diff --git a/tools/sdk/include/newlib/sys/utime.h b/tools/sdk/include/newlib/sys/utime.h
new file mode 100644
index 00000000..5e937f10
--- /dev/null
+++ b/tools/sdk/include/newlib/sys/utime.h
@@ -0,0 +1,22 @@
+#ifndef _SYS_UTIME_H
+#define _SYS_UTIME_H
+
+/* This is a dummy  file, not customized for any
+   particular system.  If there is a utime.h in libc/sys/SYSDIR/sys,
+   it will override this one.  */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct utimbuf 
+{
+  time_t actime;
+  time_t modtime; 
+};
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif /* _SYS_UTIME_H */
diff --git a/tools/sdk/include/newlib/sys/wait.h b/tools/sdk/include/newlib/sys/wait.h
new file mode 100644
index 00000000..73fe3720
--- /dev/null
+++ b/tools/sdk/include/newlib/sys/wait.h
@@ -0,0 +1,44 @@
+#ifndef _SYS_WAIT_H
+#define _SYS_WAIT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include 
+
+#define WNOHANG 1
+#define WUNTRACED 2
+
+/* A status looks like:
+      <2 bytes info> <2 bytes code>
+
+       == 0, child has exited, info is the exit value
+       == 1..7e, child has exited, info is the signal number.
+       == 7f, child has stopped, info was the signal number.
+       == 80, there was a core dump.
+*/
+   
+#define WIFEXITED(w)	(((w) & 0xff) == 0)
+#define WIFSIGNALED(w)	(((w) & 0x7f) > 0 && (((w) & 0x7f) < 0x7f))
+#define WIFSTOPPED(w)	(((w) & 0xff) == 0x7f)
+#define WEXITSTATUS(w)	(((w) >> 8) & 0xff)
+#define WTERMSIG(w)	((w) & 0x7f)
+#define WSTOPSIG	WEXITSTATUS
+
+pid_t wait (int *);
+pid_t waitpid (pid_t, int *, int);
+
+#ifdef _COMPILING_NEWLIB
+pid_t _wait (int *);
+#endif
+
+/* Provide prototypes for most of the _ names that are
+   provided in newlib for some compilers.  */
+pid_t _wait (int *);
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif
diff --git a/tools/sdk/include/newlib/tar.h b/tools/sdk/include/newlib/tar.h
new file mode 100644
index 00000000..07b06dd7
--- /dev/null
+++ b/tools/sdk/include/newlib/tar.h
@@ -0,0 +1,39 @@
+/*
+ * tar.h
+ */
+
+#ifndef _TAR_H
+#define _TAR_H
+
+/* General definitions */
+#define TMAGIC 		"ustar" /* ustar plus null byte. */
+#define TMAGLEN 	6 	/* Length of the above. */
+#define TVERSION 	"00"	/* 00 without a null byte. */
+#define TVERSLEN	2	/* Length of the above. */
+
+/* Typeflag field definitions */
+#define REGTYPE 	'0'	/* Regular file. */
+#define AREGTYPE	'\0'	/* Regular file. */
+#define LNKTYPE		'1'	/* Link. */
+#define SYMTYPE		'2'	/* Symbolic link. */
+#define CHRTYPE		'3'	/* Character special. */
+#define BLKTYPE		'4'	/* Block special. */
+#define DIRTYPE		'5'	/* Directory. */
+#define FIFOTYPE	'6'	/* FIFO special. */
+#define CONTTYPE	'7'	/* Reserved. */
+
+/* Mode field bit definitions (octal) */
+#define	TSUID		04000	/* Set UID on execution. */
+#define	TSGID		02000	/* Set GID on execution. */
+#define	TSVTX		01000	/* On directories, restricted deletion flag. */
+#define	TUREAD		00400	/* Read by owner. */
+#define	TUWRITE		00200	/* Write by owner. */
+#define	TUEXEC		00100	/* Execute/search by owner. */
+#define	TGREAD		00040	/* Read by group. */
+#define	TGWRITE		00020	/* Write by group. */
+#define	TGEXEC		00010	/* Execute/search by group. */
+#define	TOREAD		00004	/* Read by other. */
+#define	TOWRITE		00002	/* Write by other. */
+#define	TOEXEC		00001	/* Execute/search by other. */
+
+#endif
diff --git a/tools/sdk/include/newlib/termios.h b/tools/sdk/include/newlib/termios.h
new file mode 100644
index 00000000..ee1820ce
--- /dev/null
+++ b/tools/sdk/include/newlib/termios.h
@@ -0,0 +1,7 @@
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include 
+#ifdef __cplusplus
+}
+#endif
diff --git a/tools/sdk/include/newlib/tgmath.h b/tools/sdk/include/newlib/tgmath.h
new file mode 100644
index 00000000..f9c8311c
--- /dev/null
+++ b/tools/sdk/include/newlib/tgmath.h
@@ -0,0 +1,184 @@
+/* http://pubs.opengroup.org/onlinepubs/9699919799/basedefs/tgmath.h.html */
+/*-
+ * Copyright (c) 2004 Stefan Farfeleder.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _TGMATH_H_
+#define	_TGMATH_H_
+
+#include 
+#include 
+
+#ifdef log2
+#undef log2
+#endif
+
+/*
+ * This implementation of  requires two implementation-dependent
+ * macros to be defined:
+ * __tg_impl_simple(x, y, z, fn, fnf, fnl, ...)
+ *	Invokes fnl() if the corresponding real type of x, y or z is long
+ *	double, fn() if it is double or any has an integer type, and fnf()
+ *	otherwise.
+ * __tg_impl_full(x, y, z, fn, fnf, fnl, cfn, cfnf, cfnl, ...)
+ *	Invokes [c]fnl() if the corresponding real type of x, y or z is long
+ *	double, [c]fn() if it is double or any has an integer type, and
+ *	[c]fnf() otherwise.  The function with the 'c' prefix is called if
+ *	any of x, y or z is a complex number.
+ * Both macros call the chosen function with all additional arguments passed
+ * to them, as given by __VA_ARGS__.
+ *
+ * Note that these macros cannot be implemented with C's ?: operator,
+ * because the return type of the whole expression would incorrectly be long
+ * double complex regardless of the argument types.
+ */
+
+/* requires GCC >= 3.1 */
+#if !__GNUC_PREREQ (3, 1)
+#error " not implemented for this compiler"
+#endif
+
+#define	__tg_type(__e, __t)						\
+	__builtin_types_compatible_p(__typeof__(__e), __t)
+#define	__tg_type3(__e1, __e2, __e3, __t)				\
+	(__tg_type(__e1, __t) || __tg_type(__e2, __t) || 		\
+	 __tg_type(__e3, __t))
+#define	__tg_type_corr(__e1, __e2, __e3, __t)				\
+	(__tg_type3(__e1, __e2, __e3, __t) || 				\
+	 __tg_type3(__e1, __e2, __e3, __t _Complex))
+#define	__tg_integer(__e1, __e2, __e3)					\
+	(((__typeof__(__e1))1.5 == 1) || ((__typeof__(__e2))1.5 == 1) ||	\
+	 ((__typeof__(__e3))1.5 == 1))
+#define	__tg_is_complex(__e1, __e2, __e3)				\
+	(__tg_type3(__e1, __e2, __e3, float _Complex) ||		\
+	 __tg_type3(__e1, __e2, __e3, double _Complex) ||		\
+	 __tg_type3(__e1, __e2, __e3, long double _Complex) ||		\
+	 __tg_type3(__e1, __e2, __e3, __typeof__(_Complex_I)))
+
+#ifdef _LDBL_EQ_DBL
+#define	__tg_impl_simple(x, y, z, fn, fnf, fnl, ...)			\
+	__builtin_choose_expr(__tg_type_corr(x, y, z, long double),	\
+	    fnl(__VA_ARGS__), __builtin_choose_expr(			\
+		__tg_type_corr(x, y, z, double) || __tg_integer(x, y, z),\
+		fn(__VA_ARGS__), fnf(__VA_ARGS__)))
+#else
+#define	__tg_impl_simple(__x, __y, __z, __fn, __fnf, __fnl, ...)	\
+	(__tg_type_corr(__x, __y, __z, double) || __tg_integer(__x, __y, __z)) \
+		? __fn(__VA_ARGS__) : __fnf(__VA_ARGS__)
+#endif
+
+#define	__tg_impl_full(__x, __y, __z, __fn, __fnf, __fnl, __cfn, __cfnf, __cfnl, ...)	\
+	__builtin_choose_expr(__tg_is_complex(__x, __y, __z),		\
+	    __tg_impl_simple(__x, __y, __z, __cfn, __cfnf, __cfnl, __VA_ARGS__),	\
+	    __tg_impl_simple(__x, __y, __z, __fn, __fnf, __fnl, __VA_ARGS__))
+
+/* Macros to save lots of repetition below */
+#define	__tg_simple(__x, __fn)						\
+	__tg_impl_simple(__x, __x, __x, __fn, __fn##f, __fn##l, __x)
+#define	__tg_simple2(__x, __y, __fn)					\
+	__tg_impl_simple(__x, __x, __y, __fn, __fn##f, __fn##l, __x, __y)
+#define	__tg_simplev(__x, __fn, ...)					\
+	__tg_impl_simple(__x, __x, __x, __fn, __fn##f, __fn##l, __VA_ARGS__)
+#define	__tg_full(__x, __fn)						\
+	__tg_impl_full(__x, __x, __x, __fn, __fn##f, __fn##l, c##__fn, c##__fn##f, c##__fn##l, __x)
+
+/* 7.22#4 -- These macros expand to real or complex functions, depending on
+ * the type of their arguments. */
+#define	acos(__x)		__tg_full(__x, acos)
+#define	asin(__x)		__tg_full(__x, asin)
+#define	atan(__x)		__tg_full(__x, atan)
+#define	acosh(__x)		__tg_full(__x, acosh)
+#define	asinh(__x)		__tg_full(__x, asinh)
+#define	atanh(__x)		__tg_full(__x, atanh)
+#define	cos(__x)		__tg_full(__x, cos)
+#define	sin(__x)		__tg_full(__x, sin)
+#define	tan(__x)		__tg_full(__x, tan)
+#define	cosh(__x)		__tg_full(__x, cosh)
+#define	sinh(__x)		__tg_full(__x, sinh)
+#define	tanh(__x)		__tg_full(__x, tanh)
+#define	exp(__x)		__tg_full(__x, exp)
+#define	log(__x)		__tg_full(__x, log)
+#define	pow(__x, __y)		__tg_impl_full(__x, __x, __y, pow, powf, powl,	\
+						cpow, cpowf, cpowl, __x, __y)
+#define	sqrt(__x)		__tg_full(__x, sqrt)
+
+/* "The corresponding type-generic macro for fabs and cabs is fabs." */
+#define	fabs(__x)		__tg_impl_full(__x, __x, __x, fabs, fabsf, fabsl,	\
+						cabs, cabsf, cabsl, __x)
+
+/* 7.22#5 -- These macros are only defined for arguments with real type. */
+#define	atan2(__x, __y)		__tg_simple2(__x, __y, atan2)
+#define	cbrt(__x)		__tg_simple(__x, cbrt)
+#define	ceil(__x)		__tg_simple(__x, ceil)
+#define	copysign(__x, __y)	__tg_simple2(__x, __y, copysign)
+#define	erf(__x)		__tg_simple(__x, erf)
+#define	erfc(__x)		__tg_simple(__x, erfc)
+#define	exp2(__x)		__tg_simple(__x, exp2)
+#define	expm1(__x)		__tg_simple(__x, expm1)
+#define	fdim(__x, __y)		__tg_simple2(__x, __y, fdim)
+#define	floor(__x)		__tg_simple(__x, floor)
+#define	fma(__x, __y, __z)	__tg_impl_simple(__x, __y, __z, fma, fmaf, fmal, \
+						 __x, __y, __z)
+#define	fmax(__x, __y)		__tg_simple2(__x, __y, fmax)
+#define	fmin(__x, __y)		__tg_simple2(__x, __y, fmin)
+#define	fmod(__x, __y)		__tg_simple2(__x, __y, fmod)
+#define	frexp(__x, __y)		__tg_simplev(__x, frexp, __x, __y)
+#define	hypot(__x, __y)		__tg_simple2(__x, __y, hypot)
+#define	ilogb(__x)		__tg_simple(__x, ilogb)
+#define	ldexp(__x, __y)		__tg_simplev(__x, ldexp, __x, __y)
+#define	lgamma(__x)		__tg_simple(__x, lgamma)
+#define	llrint(__x)		__tg_simple(__x, llrint)
+#define	llround(__x)		__tg_simple(__x, llround)
+#define	log10(__x)		__tg_simple(__x, log10)
+#define	log1p(__x)		__tg_simple(__x, log1p)
+#define	log2(__x)		__tg_simple(__x, log2)
+#define	logb(__x)		__tg_simple(__x, logb)
+#define	lrint(__x)		__tg_simple(__x, lrint)
+#define	lround(__x)		__tg_simple(__x, lround)
+#define	nearbyint(__x)		__tg_simple(__x, nearbyint)
+#define	nextafter(__x, __y)	__tg_simple2(__x, __y, nextafter)
+/* not yet implemented even for _LDBL_EQ_DBL platforms
+#define	nexttoward(__x, __y)	__tg_simplev(__x, nexttoward, __x, __y)
+*/
+#define	remainder(__x, __y)	__tg_simple2(__x, __y, remainder)
+#define	remquo(__x, __y, __z)	__tg_impl_simple(__x, __x, __y, remquo, remquof,	\
+						 remquol, __x, __y, __z)
+#define	rint(__x)		__tg_simple(__x, rint)
+#define	round(__x)		__tg_simple(__x, round)
+#define	scalbn(__x, __y)	__tg_simplev(__x, scalbn, __x, __y)
+#define	scalbln(__x, __y)	__tg_simplev(__x, scalbln, __x, __y)
+#define	tgamma(__x)		__tg_simple(__x, tgamma)
+#define	trunc(__x)		__tg_simple(__x, trunc)
+
+/* 7.22#6 -- These macros always expand to complex functions. */
+#define	carg(__x)		__tg_simple(__x, carg)
+#define	cimag(__x)		__tg_simple(__x, cimag)
+#define	conj(__x)		__tg_simple(__x, conj)
+#define	cproj(__x)		__tg_simple(__x, cproj)
+#define	creal(__x)		__tg_simple(__x, creal)
+
+#endif /* !_TGMATH_H_ */
diff --git a/tools/sdk/include/newlib/time.h b/tools/sdk/include/newlib/time.h
new file mode 100644
index 00000000..d7b6612d
--- /dev/null
+++ b/tools/sdk/include/newlib/time.h
@@ -0,0 +1,291 @@
+/*
+ * time.h
+ * 
+ * Struct and function declarations for dealing with time.
+ */
+
+#ifndef _TIME_H_
+#define _TIME_H_
+
+#include "_ansi.h"
+#include 
+
+#define __need_size_t
+#define __need_NULL
+#include 
+
+/* Get _CLOCKS_PER_SEC_ */
+#include 
+
+#ifndef _CLOCKS_PER_SEC_
+#define _CLOCKS_PER_SEC_ 1000
+#endif
+
+#define CLOCKS_PER_SEC _CLOCKS_PER_SEC_
+#define CLK_TCK CLOCKS_PER_SEC
+
+#include 
+
+_BEGIN_STD_C
+
+struct tm
+{
+  int	tm_sec;
+  int	tm_min;
+  int	tm_hour;
+  int	tm_mday;
+  int	tm_mon;
+  int	tm_year;
+  int	tm_wday;
+  int	tm_yday;
+  int	tm_isdst;
+#ifdef __TM_GMTOFF
+  long	__TM_GMTOFF;
+#endif
+#ifdef __TM_ZONE
+  const char *__TM_ZONE;
+#endif
+};
+
+clock_t	   _EXFUN(clock,    (void));
+double	   _EXFUN(difftime, (time_t _time2, time_t _time1));
+time_t	   _EXFUN(mktime,   (struct tm *_timeptr));
+time_t	   _EXFUN(time,     (time_t *_timer));
+#ifndef _REENT_ONLY
+char	  *_EXFUN(asctime,  (const struct tm *_tblock));
+char	  *_EXFUN(ctime,    (const time_t *_time));
+struct tm *_EXFUN(gmtime,   (const time_t *_timer));
+struct tm *_EXFUN(localtime,(const time_t *_timer));
+#endif
+size_t	   _EXFUN(strftime, (char *__restrict _s,
+			     size_t _maxsize, const char *__restrict _fmt,
+			     const struct tm *__restrict _t));
+
+char	  *_EXFUN(asctime_r,	(const struct tm *__restrict,
+				 char *__restrict));
+char	  *_EXFUN(ctime_r,	(const time_t *, char *));
+struct tm *_EXFUN(gmtime_r,	(const time_t *__restrict,
+				 struct tm *__restrict));
+struct tm *_EXFUN(localtime_r,	(const time_t *__restrict,
+				 struct tm *__restrict));
+
+_END_STD_C
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef __STRICT_ANSI__
+char      *_EXFUN(strptime,     (const char *__restrict,
+				 const char *__restrict,
+				 struct tm *__restrict));
+_VOID      _EXFUN(tzset,	(_VOID));
+_VOID      _EXFUN(_tzset_r,	(struct _reent *));
+
+typedef struct __tzrule_struct
+{
+  char ch;
+  int m;
+  int n;
+  int d;
+  int s;
+  time_t change;
+  long offset; /* Match type of _timezone. */
+} __tzrule_type;
+
+typedef struct __tzinfo_struct
+{
+  int __tznorth;
+  int __tzyear;
+  __tzrule_type __tzrule[2];
+} __tzinfo_type;
+
+__tzinfo_type *_EXFUN (__gettzinfo, (_VOID));
+
+/* getdate functions */
+
+#ifdef HAVE_GETDATE
+#ifndef _REENT_ONLY
+#define getdate_err (*__getdate_err())
+int *_EXFUN(__getdate_err,(_VOID));
+
+struct tm *	_EXFUN(getdate, (const char *));
+/* getdate_err is set to one of the following values to indicate the error.
+     1  the DATEMSK environment variable is null or undefined,
+     2  the template file cannot be opened for reading,
+     3  failed to get file status information,
+     4  the template file is not a regular file,
+     5  an error is encountered while reading the template file,
+     6  memory allication failed (not enough memory available),
+     7  there is no line in the template that matches the input,
+     8  invalid input specification  */
+#endif /* !_REENT_ONLY */
+
+/* getdate_r returns the error code as above */
+int		_EXFUN(getdate_r, (const char *, struct tm *));
+#endif /* HAVE_GETDATE */
+
+/* defines for the opengroup specifications Derived from Issue 1 of the SVID.  */
+extern __IMPORT long _timezone;
+extern __IMPORT int _daylight;
+extern __IMPORT char *_tzname[2];
+
+/* POSIX defines the external tzname being defined in time.h */
+#ifndef tzname
+#define tzname _tzname
+#endif
+#endif /* !__STRICT_ANSI__ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#include 
+
+#ifdef __CYGWIN__
+#include 
+#endif /*__CYGWIN__*/
+
+#if defined(_POSIX_TIMERS)
+
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Clocks, P1003.1b-1993, p. 263 */
+
+int _EXFUN(clock_settime, (clockid_t clock_id, const struct timespec *tp));
+int _EXFUN(clock_gettime, (clockid_t clock_id, struct timespec *tp));
+int _EXFUN(clock_getres,  (clockid_t clock_id, struct timespec *res));
+
+/* Create a Per-Process Timer, P1003.1b-1993, p. 264 */
+
+int _EXFUN(timer_create,
+  	(clockid_t clock_id,
+ 	struct sigevent *__restrict evp,
+	timer_t *__restrict timerid));
+
+/* Delete a Per_process Timer, P1003.1b-1993, p. 266 */
+
+int _EXFUN(timer_delete, (timer_t timerid));
+
+/* Per-Process Timers, P1003.1b-1993, p. 267 */
+
+int _EXFUN(timer_settime,
+	(timer_t timerid, int flags,
+	const struct itimerspec *__restrict value,
+	struct itimerspec *__restrict ovalue));
+int _EXFUN(timer_gettime, (timer_t timerid, struct itimerspec *value));
+int _EXFUN(timer_getoverrun, (timer_t timerid));
+
+/* High Resolution Sleep, P1003.1b-1993, p. 269 */
+
+int _EXFUN(nanosleep, (const struct timespec  *rqtp, struct timespec *rmtp));
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _POSIX_TIMERS */
+
+#if defined(_POSIX_CLOCK_SELECTION)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int _EXFUN(clock_nanosleep,
+  (clockid_t clock_id, int flags, const struct timespec *rqtp,
+   struct timespec *rmtp));
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _POSIX_CLOCK_SELECTION */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* CPU-time Clock Attributes, P1003.4b/D8, p. 54 */
+
+/* values for the clock enable attribute */
+
+#define CLOCK_ENABLED  1  /* clock is enabled, i.e. counting execution time */
+#define CLOCK_DISABLED 0  /* clock is disabled */
+
+/* values for the pthread cputime_clock_allowed attribute */
+
+#define CLOCK_ALLOWED    1 /* If a thread is created with this value a */
+                           /*   CPU-time clock attached to that thread */
+                           /*   shall be accessible. */
+#define CLOCK_DISALLOWED 0 /* If a thread is created with this value, the */
+                           /*   thread shall not have a CPU-time clock */
+                           /*   accessible. */
+
+/* Manifest Constants, P1003.1b-1993, p. 262 */
+
+#define CLOCK_REALTIME (clockid_t)1
+
+/* Flag indicating time is "absolute" with respect to the clock
+   associated with a time.  */
+
+#define TIMER_ABSTIME	4
+
+/* Manifest Constants, P1003.4b/D8, p. 55 */
+
+#if defined(_POSIX_CPUTIME)
+
+/* When used in a clock or timer function call, this is interpreted as
+   the identifier of the CPU_time clock associated with the PROCESS
+   making the function call.  */
+
+#define CLOCK_PROCESS_CPUTIME_ID (clockid_t)2
+
+#endif
+
+#if defined(_POSIX_THREAD_CPUTIME)
+
+/*  When used in a clock or timer function call, this is interpreted as
+    the identifier of the CPU_time clock associated with the THREAD
+    making the function call.  */
+
+#define CLOCK_THREAD_CPUTIME_ID (clockid_t)3
+
+#endif
+
+#if defined(_POSIX_MONOTONIC_CLOCK)
+
+/*  The identifier for the system-wide monotonic clock, which is defined
+ *      as a clock whose value cannot be set via clock_settime() and which 
+ *          cannot have backward clock jumps. */
+
+#define CLOCK_MONOTONIC (clockid_t)4
+
+#endif
+
+#if defined(_POSIX_CPUTIME)
+
+/* Accessing a Process CPU-time CLock, P1003.4b/D8, p. 55 */
+
+int _EXFUN(clock_getcpuclockid, (pid_t pid, clockid_t *clock_id));
+
+#endif /* _POSIX_CPUTIME */
+
+#if defined(_POSIX_CPUTIME) || defined(_POSIX_THREAD_CPUTIME)
+
+/* CPU-time Clock Attribute Access, P1003.4b/D8, p. 56 */
+
+int _EXFUN(clock_setenable_attr, (clockid_t clock_id, int attr));
+int _EXFUN(clock_getenable_attr, (clockid_t clock_id, int *attr));
+
+#endif /* _POSIX_CPUTIME or _POSIX_THREAD_CPUTIME */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _TIME_H_ */
+
diff --git a/tools/sdk/include/newlib/unctrl.h b/tools/sdk/include/newlib/unctrl.h
new file mode 100644
index 00000000..00407523
--- /dev/null
+++ b/tools/sdk/include/newlib/unctrl.h
@@ -0,0 +1,46 @@
+/* From curses.h.  */
+/*
+ * Copyright (c) 1981, 1993
+ *	The Regents of the University of California.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the University of
+ *	California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _UNCTRL_H_
+#define _UNCTRL_H_
+
+#include <_ansi.h>
+
+#define unctrl(c)		__unctrl[(c) & 0xff]
+#define unctrllen(ch)		__unctrllen[(ch) & 0xff]
+
+extern __IMPORT _CONST char * _CONST __unctrl[256];	/* Control strings. */
+extern __IMPORT _CONST char __unctrllen[256];	/* Control strings length. */
+
+#endif /* _UNCTRL_H_ */
diff --git a/tools/sdk/include/newlib/unistd.h b/tools/sdk/include/newlib/unistd.h
new file mode 100644
index 00000000..4f6fd29a
--- /dev/null
+++ b/tools/sdk/include/newlib/unistd.h
@@ -0,0 +1,13 @@
+#ifndef _UNISTD_H_
+#define _UNISTD_H_
+
+# include 
+
+#ifndef L_SET
+/* Old BSD names for the same constants; just for compatibility.  */
+#define		L_SET		SEEK_SET
+#define		L_INCR		SEEK_CUR
+#define		L_XTND		SEEK_END
+#endif
+
+#endif /* _UNISTD_H_ */
diff --git a/tools/sdk/include/newlib/utime.h b/tools/sdk/include/newlib/utime.h
new file mode 100644
index 00000000..652891aa
--- /dev/null
+++ b/tools/sdk/include/newlib/utime.h
@@ -0,0 +1,12 @@
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <_ansi.h>
+
+/* The utime function is defined in libc/sys//sys if it exists. */
+#include 
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tools/sdk/include/newlib/utmp.h b/tools/sdk/include/newlib/utmp.h
new file mode 100644
index 00000000..88cf6f85
--- /dev/null
+++ b/tools/sdk/include/newlib/utmp.h
@@ -0,0 +1,8 @@
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include 
+#ifdef __cplusplus
+}
+#endif
+
diff --git a/tools/sdk/include/newlib/wchar.h b/tools/sdk/include/newlib/wchar.h
new file mode 100644
index 00000000..810a6c0e
--- /dev/null
+++ b/tools/sdk/include/newlib/wchar.h
@@ -0,0 +1,254 @@
+#ifndef _WCHAR_H_
+#define _WCHAR_H_
+
+#include <_ansi.h>
+
+#include 
+
+#define __need_size_t
+#define __need_wchar_t
+#define __need_wint_t
+#define __need_NULL
+#include 
+
+#define __need___va_list
+#include 
+
+/* For _mbstate_t definition. */
+#include 
+#include 
+/* For __STDC_ISO_10646__ */
+#include 
+
+#ifndef WEOF
+# define WEOF ((wint_t)-1)
+#endif
+
+/* This must match definition in  */
+#ifndef WCHAR_MIN
+#ifdef __WCHAR_MIN__
+#define WCHAR_MIN __WCHAR_MIN__
+#elif defined(__WCHAR_UNSIGNED__) || (L'\0' - 1 > 0)
+#define WCHAR_MIN (0 + L'\0')
+#else
+#define WCHAR_MIN (-0x7fffffff - 1 + L'\0')
+#endif
+#endif
+
+/* This must match definition in  */
+#ifndef WCHAR_MAX
+#ifdef __WCHAR_MAX__
+#define WCHAR_MAX __WCHAR_MAX__
+#elif defined(__WCHAR_UNSIGNED__) || (L'\0' - 1 > 0)
+#define WCHAR_MAX (0xffffffffu + L'\0')
+#else
+#define WCHAR_MAX (0x7fffffff + L'\0')
+#endif
+#endif
+
+_BEGIN_STD_C
+
+/* As in stdio.h,  defines __FILE. */
+typedef __FILE FILE;
+
+/* As required by POSIX.1-2008, declare tm as incomplete type.
+   The actual definition is in time.h. */
+struct tm;
+
+#ifndef _MBSTATE_T
+#define _MBSTATE_T
+typedef _mbstate_t mbstate_t;
+#endif /* _MBSTATE_T */
+
+wint_t	_EXFUN(btowc, (int));
+int	_EXFUN(wctob, (wint_t));
+size_t	_EXFUN(mbrlen, (const char *__restrict, size_t, mbstate_t *__restrict));
+size_t	_EXFUN(mbrtowc, (wchar_t *__restrict, const char *__restrict, size_t,
+						mbstate_t *__restrict));
+size_t	_EXFUN(_mbrtowc_r, (struct _reent *, wchar_t * , const char * , 
+			size_t, mbstate_t *));
+int	_EXFUN(mbsinit, (const mbstate_t *));
+size_t	_EXFUN(mbsnrtowcs, (wchar_t *__restrict, const char **__restrict,
+				size_t, size_t, mbstate_t *__restrict));
+size_t	_EXFUN(_mbsnrtowcs_r, (struct _reent *, wchar_t * , const char ** ,
+			size_t, size_t, mbstate_t *));
+size_t	_EXFUN(mbsrtowcs, (wchar_t *__restrict, const char **__restrict, size_t,
+				mbstate_t *__restrict));
+size_t	_EXFUN(_mbsrtowcs_r, (struct _reent *, wchar_t * , const char ** , size_t, mbstate_t *));
+size_t	_EXFUN(wcrtomb, (char *__restrict, wchar_t, mbstate_t *__restrict));
+size_t	_EXFUN(_wcrtomb_r, (struct _reent *, char * , wchar_t, mbstate_t *));
+size_t	_EXFUN(wcsnrtombs, (char *__restrict, const wchar_t **__restrict,
+				size_t, size_t, mbstate_t *__restrict));
+size_t	_EXFUN(_wcsnrtombs_r, (struct _reent *, char * , const wchar_t ** , 
+			size_t, size_t, mbstate_t *));
+size_t	_EXFUN(wcsrtombs, (char *__restrict, const wchar_t **__restrict,
+				size_t, mbstate_t *__restrict));
+size_t	_EXFUN(_wcsrtombs_r, (struct _reent *, char * , const wchar_t ** , 
+			size_t, mbstate_t *));
+int	_EXFUN(wcscasecmp, (const wchar_t *, const wchar_t *));
+wchar_t	*_EXFUN(wcscat, (wchar_t *__restrict, const wchar_t *__restrict));
+wchar_t	*_EXFUN(wcschr, (const wchar_t *, wchar_t));
+int	_EXFUN(wcscmp, (const wchar_t *, const wchar_t *));
+int	_EXFUN(wcscoll, (const wchar_t *, const wchar_t *));
+wchar_t	*_EXFUN(wcscpy, (wchar_t *__restrict, const wchar_t *__restrict));
+wchar_t	*_EXFUN(wcpcpy, (wchar_t *__restrict,
+				 const wchar_t *__restrict));
+wchar_t	*_EXFUN(wcsdup, (const wchar_t *));
+wchar_t	*_EXFUN(_wcsdup_r, (struct _reent *, const wchar_t * ));
+size_t	_EXFUN(wcscspn, (const wchar_t *, const wchar_t *));
+size_t  _EXFUN(wcsftime, (wchar_t *__restrict, size_t,
+				const wchar_t *__restrict, const struct tm *__restrict));
+size_t	_EXFUN(wcslcat, (wchar_t *, const wchar_t *, size_t));
+size_t	_EXFUN(wcslcpy, (wchar_t *, const wchar_t *, size_t));
+size_t	_EXFUN(wcslen, (const wchar_t *));
+int	_EXFUN(wcsncasecmp, (const wchar_t *, const wchar_t *, size_t));
+wchar_t	*_EXFUN(wcsncat, (wchar_t *__restrict,
+				 const wchar_t *__restrict, size_t));
+int	_EXFUN(wcsncmp, (const wchar_t *, const wchar_t *, size_t));
+wchar_t	*_EXFUN(wcsncpy, (wchar_t *__restrict,
+				 const wchar_t *__restrict, size_t));
+wchar_t	*_EXFUN(wcpncpy, (wchar_t *__restrict,
+				 const wchar_t *__restrict, size_t));
+size_t	_EXFUN(wcsnlen, (const wchar_t *, size_t));
+wchar_t	*_EXFUN(wcspbrk, (const wchar_t *, const wchar_t *));
+wchar_t	*_EXFUN(wcsrchr, (const wchar_t *, wchar_t));
+size_t	_EXFUN(wcsspn, (const wchar_t *, const wchar_t *));
+wchar_t	*_EXFUN(wcsstr, (const wchar_t *__restrict,
+				 const wchar_t *__restrict));
+wchar_t	*_EXFUN(wcstok, (wchar_t *__restrict, const wchar_t *__restrict,
+				 wchar_t **__restrict));
+double _EXFUN(wcstod, (const wchar_t *__restrict, wchar_t **__restrict));
+double _EXFUN(_wcstod_r, (struct _reent *, const wchar_t *, wchar_t **));
+float _EXFUN(wcstof, (const wchar_t *__restrict, wchar_t **__restrict));
+float _EXFUN(_wcstof_r, (struct _reent *, const wchar_t *, wchar_t **));
+#ifdef _LDBL_EQ_DBL
+long double _EXFUN(wcstold, (const wchar_t *, wchar_t **));
+#endif /* _LDBL_EQ_DBL */
+int	_EXFUN(wcswidth, (const wchar_t *, size_t));
+size_t	_EXFUN(wcsxfrm, (wchar_t *__restrict, const wchar_t *__restrict,
+				size_t));
+int	_EXFUN(wcwidth, (const wchar_t));
+wchar_t	*_EXFUN(wmemchr, (const wchar_t *, wchar_t, size_t));
+int	_EXFUN(wmemcmp, (const wchar_t *, const wchar_t *, size_t));
+wchar_t	*_EXFUN(wmemcpy, (wchar_t *__restrict, const wchar_t *__restrict,
+				 size_t));
+wchar_t	*_EXFUN(wmemmove, (wchar_t *, const wchar_t *, size_t));
+wchar_t	*_EXFUN(wmemset, (wchar_t *, wchar_t, size_t));
+
+long    _EXFUN(wcstol, (const wchar_t *__restrict, wchar_t **__restrict, int));
+long long _EXFUN(wcstoll, (const wchar_t *__restrict, wchar_t **__restrict,
+				  int));
+unsigned long _EXFUN(wcstoul, (const wchar_t *__restrict, wchar_t **__restrict,
+					  int));
+unsigned long long _EXFUN(wcstoull, (const wchar_t *__restrict,
+						   wchar_t **__restrict, int));
+long    _EXFUN(_wcstol_r, (struct _reent *, const wchar_t *, wchar_t **, int));
+long long _EXFUN(_wcstoll_r, (struct _reent *, const wchar_t *, wchar_t **, int));
+unsigned long _EXFUN(_wcstoul_r, (struct _reent *, const wchar_t *, wchar_t **, int));
+unsigned long long _EXFUN(_wcstoull_r, (struct _reent *, const wchar_t *, wchar_t **, int));
+/* On platforms where long double equals double.  */
+#ifdef _LDBL_EQ_DBL
+long double _EXFUN(wcstold, (const wchar_t *, wchar_t **));
+#endif /* _LDBL_EQ_DBL */
+
+wint_t _EXFUN(fgetwc, (__FILE *));
+wchar_t *_EXFUN(fgetws, (wchar_t *__restrict, int, __FILE *__restrict));
+wint_t _EXFUN(fputwc, (wchar_t, __FILE *));
+int _EXFUN(fputws, (const wchar_t *__restrict, __FILE *__restrict));
+int _EXFUN (fwide, (__FILE *, int));
+wint_t _EXFUN (getwc, (__FILE *));
+wint_t _EXFUN (getwchar, (void));
+wint_t _EXFUN(putwc, (wchar_t, __FILE *));
+wint_t _EXFUN(putwchar, (wchar_t));
+wint_t _EXFUN (ungetwc, (wint_t wc, __FILE *));
+
+wint_t _EXFUN(_fgetwc_r, (struct _reent *, __FILE *));
+wint_t _EXFUN(_fgetwc_unlocked_r, (struct _reent *, __FILE *));
+wchar_t *_EXFUN(_fgetws_r, (struct _reent *, wchar_t *, int, __FILE *));
+wchar_t *_EXFUN(_fgetws_unlocked_r, (struct _reent *, wchar_t *, int, __FILE *));
+wint_t _EXFUN(_fputwc_r, (struct _reent *, wchar_t, __FILE *));
+wint_t _EXFUN(_fputwc_unlocked_r, (struct _reent *, wchar_t, __FILE *));
+int _EXFUN(_fputws_r, (struct _reent *, const wchar_t *, __FILE *));
+int _EXFUN(_fputws_unlocked_r, (struct _reent *, const wchar_t *, __FILE *));
+int _EXFUN (_fwide_r, (struct _reent *, __FILE *, int));
+wint_t _EXFUN (_getwc_r, (struct _reent *, __FILE *));
+wint_t _EXFUN (_getwc_unlocked_r, (struct _reent *, __FILE *));
+wint_t _EXFUN (_getwchar_r, (struct _reent *ptr));
+wint_t _EXFUN (_getwchar_unlocked_r, (struct _reent *ptr));
+wint_t _EXFUN(_putwc_r, (struct _reent *, wchar_t, __FILE *));
+wint_t _EXFUN(_putwc_unlocked_r, (struct _reent *, wchar_t, __FILE *));
+wint_t _EXFUN(_putwchar_r, (struct _reent *, wchar_t));
+wint_t _EXFUN(_putwchar_unlocked_r, (struct _reent *, wchar_t));
+wint_t _EXFUN (_ungetwc_r, (struct _reent *, wint_t wc, __FILE *));
+
+#if __GNU_VISIBLE
+wint_t _EXFUN(fgetwc_unlocked, (__FILE *));
+wchar_t *_EXFUN(fgetws_unlocked, (wchar_t *__restrict, int, __FILE *__restrict));
+wint_t _EXFUN(fputwc_unlocked, (wchar_t, __FILE *));
+int _EXFUN(fputws_unlocked, (const wchar_t *__restrict, __FILE *__restrict));
+wint_t _EXFUN(getwc_unlocked, (__FILE *));
+wint_t _EXFUN(getwchar_unlocked, (void));
+wint_t _EXFUN(putwc_unlocked, (wchar_t, __FILE *));
+wint_t _EXFUN(putwchar_unlocked, (wchar_t));
+#endif
+
+__FILE *_EXFUN (open_wmemstream, (wchar_t **, size_t *));
+__FILE *_EXFUN (_open_wmemstream_r, (struct _reent *, wchar_t **, size_t *));
+
+#ifndef __VALIST
+#ifdef __GNUC__
+#define __VALIST __gnuc_va_list
+#else
+#define __VALIST char*
+#endif
+#endif
+
+int	_EXFUN(fwprintf, (__FILE *__restrict, const wchar_t *__restrict, ...));
+int	_EXFUN(swprintf, (wchar_t *__restrict, size_t,
+			const wchar_t *__restrict, ...));
+int	_EXFUN(vfwprintf, (__FILE *__restrict, const wchar_t *__restrict,
+			__VALIST));
+int	_EXFUN(vswprintf, (wchar_t *__restrict, size_t,
+			const wchar_t *__restrict, __VALIST));
+int	_EXFUN(vwprintf, (const wchar_t *__restrict, __VALIST));
+int	_EXFUN(wprintf, (const wchar_t *__restrict, ...));
+
+int	_EXFUN(_fwprintf_r, (struct _reent *, __FILE *, const wchar_t *, ...));
+int	_EXFUN(_swprintf_r, (struct _reent *, wchar_t *, size_t, const wchar_t *, ...));
+int	_EXFUN(_vfwprintf_r, (struct _reent *, __FILE *, const wchar_t *, __VALIST));
+int	_EXFUN(_vswprintf_r, (struct _reent *, wchar_t *, size_t, const wchar_t *, __VALIST));
+int	_EXFUN(_vwprintf_r, (struct _reent *, const wchar_t *, __VALIST));
+int	_EXFUN(_wprintf_r, (struct _reent *, const wchar_t *, ...));
+
+int	_EXFUN(fwscanf, (__FILE *__restrict, const wchar_t *__restrict, ...));
+int	_EXFUN(swscanf, (const wchar_t *__restrict,
+			const wchar_t *__restrict, ...));
+int	_EXFUN(vfwscanf, (__FILE *__restrict, const wchar_t *__restrict,
+			__VALIST));
+int	_EXFUN(vswscanf, (const wchar_t *__restrict, const wchar_t *__restrict,
+			__VALIST));
+int	_EXFUN(vwscanf, (const wchar_t *__restrict, __VALIST));
+int	_EXFUN(wscanf, (const wchar_t *__restrict, ...));
+
+int	_EXFUN(_fwscanf_r, (struct _reent *, __FILE *, const wchar_t *, ...));
+int	_EXFUN(_swscanf_r, (struct _reent *, const wchar_t *, const wchar_t *, ...));
+int	_EXFUN(_vfwscanf_r, (struct _reent *, __FILE *, const wchar_t *, __VALIST));
+int	_EXFUN(_vswscanf_r, (struct _reent *, const wchar_t *, const wchar_t *, __VALIST));
+int	_EXFUN(_vwscanf_r, (struct _reent *, const wchar_t *, __VALIST));
+int	_EXFUN(_wscanf_r, (struct _reent *, const wchar_t *, ...));
+
+#define getwc(fp)	fgetwc(fp)
+#define putwc(wc,fp)	fputwc((wc), (fp))
+#define getwchar()	fgetwc(_REENT->_stdin)
+#define putwchar(wc)	fputwc((wc), _REENT->_stdout)
+
+#if __GNU_VISIBLE
+#define getwc_unlocked(fp)	fgetwc_unlocked(fp)
+#define putwc_unlocked(wc,fp)	fputwc_unlocked((wc), (fp))
+#define getwchar_unlocked()	fgetwc_unlocked(_REENT->_stdin)
+#define putwchar_unlocked(wc)	fputwc_unlocked((wc), _REENT->_stdout)
+#endif
+
+_END_STD_C
+
+#endif /* _WCHAR_H_ */
diff --git a/tools/sdk/include/newlib/wctype.h b/tools/sdk/include/newlib/wctype.h
new file mode 100644
index 00000000..c72c9dec
--- /dev/null
+++ b/tools/sdk/include/newlib/wctype.h
@@ -0,0 +1,47 @@
+#ifndef _WCTYPE_H_
+#define _WCTYPE_H_
+
+#include <_ansi.h>
+#include 
+
+#define __need_wint_t
+#include 
+
+#ifndef WEOF
+# define WEOF ((wint_t)-1)
+#endif
+
+_BEGIN_STD_C
+
+#ifndef _WCTYPE_T
+#define _WCTYPE_T
+typedef int wctype_t;
+#endif
+
+#ifndef _WCTRANS_T
+#define _WCTRANS_T
+typedef int wctrans_t;
+#endif
+
+int	_EXFUN(iswalpha, (wint_t));
+int	_EXFUN(iswalnum, (wint_t));
+int	_EXFUN(iswblank, (wint_t));
+int	_EXFUN(iswcntrl, (wint_t));
+int	_EXFUN(iswctype, (wint_t, wctype_t));
+int	_EXFUN(iswdigit, (wint_t));
+int	_EXFUN(iswgraph, (wint_t));
+int	_EXFUN(iswlower, (wint_t));
+int	_EXFUN(iswprint, (wint_t));
+int	_EXFUN(iswpunct, (wint_t));
+int	_EXFUN(iswspace, (wint_t));
+int	_EXFUN(iswupper, (wint_t));
+int	_EXFUN(iswxdigit, (wint_t));
+wint_t	_EXFUN(towctrans, (wint_t, wctrans_t));
+wint_t	_EXFUN(towupper, (wint_t));
+wint_t	_EXFUN(towlower, (wint_t));
+wctrans_t _EXFUN(wctrans, (const char *));
+wctype_t _EXFUN(wctype, (const char *));
+
+_END_STD_C
+
+#endif /* _WCTYPE_H_ */
diff --git a/tools/sdk/include/newlib/wordexp.h b/tools/sdk/include/newlib/wordexp.h
new file mode 100644
index 00000000..1f09a64c
--- /dev/null
+++ b/tools/sdk/include/newlib/wordexp.h
@@ -0,0 +1,53 @@
+/* Copyright (C) 2002, 2010 by  Red Hat, Incorporated. All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software
+ * is freely granted, provided that this notice is preserved.
+ */
+
+#ifndef _WORDEXP_H_
+#define _WORDEXP_H_
+
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct _wordexp_t
+{
+  size_t we_wordc;	/* Count of words matched by words. */
+  char **we_wordv;	/* Pointer to list of expanded words. */
+  size_t we_offs;	/* Slots to reserve at the beginning of we_wordv. */
+};
+
+typedef struct _wordexp_t wordexp_t;
+
+#define	WRDE_DOOFFS	0x0001	/* Use we_offs. */
+#define	WRDE_APPEND	0x0002	/* Append to output from previous call. */
+#define	WRDE_NOCMD	0x0004	/* Don't perform command substitution. */
+#define	WRDE_REUSE	0x0008	/* pwordexp points to a wordexp_t struct returned from
+                                   a previous successful call to wordexp. */
+#define	WRDE_SHOWERR	0x0010	/* Print error messages to stderr. */
+#define	WRDE_UNDEF	0x0020	/* Report attempt to expand undefined shell variable. */
+
+enum {
+  WRDE_SUCCESS,
+  WRDE_NOSPACE,
+  WRDE_BADCHAR,
+  WRDE_BADVAL,
+  WRDE_CMDSUB,
+  WRDE_SYNTAX,
+  WRDE_NOSYS
+};
+
+/* Note: This implementation of wordexp requires a version of bash
+   that supports the --wordexp and --protected arguments to be present
+   on the system.  It does not support the WRDE_UNDEF flag. */
+int wordexp(const char *__restrict, wordexp_t *__restrict, int);
+void wordfree(wordexp_t *);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _WORDEXP_H_  */
diff --git a/tools/sdk/include/newlib/xtensa/config/core-isa.h b/tools/sdk/include/newlib/xtensa/config/core-isa.h
new file mode 100644
index 00000000..f3f4e45f
--- /dev/null
+++ b/tools/sdk/include/newlib/xtensa/config/core-isa.h
@@ -0,0 +1,655 @@
+/* 
+ * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
+ *				processor CORE configuration
+ *
+ *  See , which includes this file, for more details.
+ */
+
+/* Xtensa processor core configuration information.
+
+   Copyright (c) 1999-2016 Tensilica Inc.
+
+   Permission is hereby granted, free of charge, to any person obtaining
+   a copy of this software and associated documentation files (the
+   "Software"), to deal in the Software without restriction, including
+   without limitation the rights to use, copy, modify, merge, publish,
+   distribute, sublicense, and/or sell copies of the Software, and to
+   permit persons to whom the Software is furnished to do so, subject to
+   the following conditions:
+
+   The above copyright notice and this permission notice shall be included
+   in all copies or substantial portions of the Software.
+
+   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
+
+#ifndef _XTENSA_CORE_CONFIGURATION_H
+#define _XTENSA_CORE_CONFIGURATION_H
+
+
+/****************************************************************************
+	    Parameters Useful for Any Code, USER or PRIVILEGED
+ ****************************************************************************/
+
+/*
+ *  Note:  Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
+ *  configured, and a value of 0 otherwise.  These macros are always defined.
+ */
+
+
+/*----------------------------------------------------------------------
+				ISA
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_BE			0	/* big-endian byte ordering */
+#define XCHAL_HAVE_WINDOWED		1	/* windowed registers option */
+#define XCHAL_NUM_AREGS			64	/* num of physical addr regs */
+#define XCHAL_NUM_AREGS_LOG2		6	/* log2(XCHAL_NUM_AREGS) */
+#define XCHAL_MAX_INSTRUCTION_SIZE	3	/* max instr bytes (3..8) */
+#define XCHAL_HAVE_DEBUG		1	/* debug option */
+#define XCHAL_HAVE_DENSITY		1	/* 16-bit instructions */
+#define XCHAL_HAVE_LOOPS		1	/* zero-overhead loops */
+#define XCHAL_LOOP_BUFFER_SIZE		256	/* zero-ov. loop instr buffer size */
+#define XCHAL_HAVE_NSA			1	/* NSA/NSAU instructions */
+#define XCHAL_HAVE_MINMAX		1	/* MIN/MAX instructions */
+#define XCHAL_HAVE_SEXT			1	/* SEXT instruction */
+#define XCHAL_HAVE_DEPBITS		0	/* DEPBITS instruction */
+#define XCHAL_HAVE_CLAMPS		1	/* CLAMPS instruction */
+#define XCHAL_HAVE_MUL16		1	/* MUL16S/MUL16U instructions */
+#define XCHAL_HAVE_MUL32		1	/* MULL instruction */
+#define XCHAL_HAVE_MUL32_HIGH		1	/* MULUH/MULSH instructions */
+#define XCHAL_HAVE_DIV32		1	/* QUOS/QUOU/REMS/REMU instructions */
+#define XCHAL_HAVE_L32R			1	/* L32R instruction */
+#define XCHAL_HAVE_ABSOLUTE_LITERALS	0	/* non-PC-rel (extended) L32R */
+#define XCHAL_HAVE_CONST16		0	/* CONST16 instruction */
+#define XCHAL_HAVE_ADDX			1	/* ADDX#/SUBX# instructions */
+#define XCHAL_HAVE_WIDE_BRANCHES	0	/* B*.W18 or B*.W15 instr's */
+#define XCHAL_HAVE_PREDICTED_BRANCHES	0	/* B[EQ/EQZ/NE/NEZ]T instr's */
+#define XCHAL_HAVE_CALL4AND12		1	/* (obsolete option) */
+#define XCHAL_HAVE_ABS			1	/* ABS instruction */
+/*#define XCHAL_HAVE_POPC		0*/	/* POPC instruction */
+/*#define XCHAL_HAVE_CRC		0*/	/* CRC instruction */
+#define XCHAL_HAVE_RELEASE_SYNC		1	/* L32AI/S32RI instructions */
+#define XCHAL_HAVE_S32C1I		1	/* S32C1I instruction */
+#define XCHAL_HAVE_SPECULATION		0	/* speculation */
+#define XCHAL_HAVE_FULL_RESET		1	/* all regs/state reset */
+#define XCHAL_NUM_CONTEXTS		1	/* */
+#define XCHAL_NUM_MISC_REGS		4	/* num of scratch regs (0..4) */
+#define XCHAL_HAVE_TAP_MASTER		0	/* JTAG TAP control instr's */
+#define XCHAL_HAVE_PRID			1	/* processor ID register */
+#define XCHAL_HAVE_EXTERN_REGS		1	/* WER/RER instructions */
+#define XCHAL_HAVE_MX			0	/* MX core (Tensilica internal) */
+#define XCHAL_HAVE_MP_INTERRUPTS	0	/* interrupt distributor port */
+#define XCHAL_HAVE_MP_RUNSTALL		0	/* core RunStall control port */
+#define XCHAL_HAVE_PSO			0	/* Power Shut-Off */
+#define XCHAL_HAVE_PSO_CDM		0	/* core/debug/mem pwr domains */
+#define XCHAL_HAVE_PSO_FULL_RETENTION	0	/* all regs preserved on PSO */
+#define XCHAL_HAVE_THREADPTR		1	/* THREADPTR register */
+#define XCHAL_HAVE_BOOLEANS		1	/* boolean registers */
+#define XCHAL_HAVE_CP			1	/* CPENABLE reg (coprocessor) */
+#define XCHAL_CP_MAXCFG			8	/* max allowed cp id plus one */
+#define XCHAL_HAVE_MAC16		1	/* MAC16 package */
+
+#define XCHAL_HAVE_FUSION		 0	/* Fusion*/
+#define XCHAL_HAVE_FUSION_FP	 0	        /* Fusion FP option */
+#define XCHAL_HAVE_FUSION_LOW_POWER 0	/* Fusion Low Power option */
+#define XCHAL_HAVE_FUSION_AES	 0	        /* Fusion BLE/Wifi AES-128 CCM option */
+#define XCHAL_HAVE_FUSION_CONVENC	 0       /* Fusion Conv Encode option */
+#define XCHAL_HAVE_FUSION_LFSR_CRC	 0	/* Fusion LFSR-CRC option */
+#define XCHAL_HAVE_FUSION_BITOPS	 0	/* Fusion Bit Operations Support option */
+#define XCHAL_HAVE_FUSION_AVS	 0	/* Fusion AVS option */
+#define XCHAL_HAVE_FUSION_16BIT_BASEBAND	 0	/* Fusion 16-bit Baseband option */
+#define XCHAL_HAVE_FUSION_VITERBI        0     /* Fusion Viterbi option */
+#define XCHAL_HAVE_FUSION_SOFTDEMAP      0   /* Fusion Soft Bit Demap option */
+#define XCHAL_HAVE_HIFIPRO		0	/* HiFiPro Audio Engine pkg */
+#define XCHAL_HAVE_HIFI4		0	/* HiFi4 Audio Engine pkg */
+#define XCHAL_HAVE_HIFI4_VFPU		0	/* HiFi4 Audio Engine VFPU option */
+#define XCHAL_HAVE_HIFI3		0	/* HiFi3 Audio Engine pkg */
+#define XCHAL_HAVE_HIFI3_VFPU		0	/* HiFi3 Audio Engine VFPU option */
+#define XCHAL_HAVE_HIFI2		0	/* HiFi2 Audio Engine pkg */
+#define XCHAL_HAVE_HIFI2EP		0	/* HiFi2EP */
+#define XCHAL_HAVE_HIFI_MINI		0	
+
+
+#define XCHAL_HAVE_VECTORFPU2005	0	/* vector or user floating-point pkg */
+#define XCHAL_HAVE_USER_DPFPU         0       /* user DP floating-point pkg */
+#define XCHAL_HAVE_USER_SPFPU         0       /* user DP floating-point pkg */
+#define XCHAL_HAVE_FP                 1      /* single prec floating point */
+#define XCHAL_HAVE_FP_DIV             1  /* FP with DIV instructions */
+#define XCHAL_HAVE_FP_RECIP           1        /* FP with RECIP instructions */
+#define XCHAL_HAVE_FP_SQRT            1 /* FP with SQRT instructions */
+#define XCHAL_HAVE_FP_RSQRT           1        /* FP with RSQRT instructions */
+#define XCHAL_HAVE_DFP                        0     /* double precision FP pkg */
+#define XCHAL_HAVE_DFP_DIV            0 /* DFP with DIV instructions */
+#define XCHAL_HAVE_DFP_RECIP          0       /* DFP with RECIP instructions*/
+#define XCHAL_HAVE_DFP_SQRT           0        /* DFP with SQRT instructions */
+#define XCHAL_HAVE_DFP_RSQRT          0       /* DFP with RSQRT instructions*/
+#define XCHAL_HAVE_DFP_ACCEL		1	/* double precision FP acceleration pkg */
+#define XCHAL_HAVE_DFP_accel		XCHAL_HAVE_DFP_ACCEL				/* for backward compatibility */
+
+#define XCHAL_HAVE_DFPU_SINGLE_ONLY    1                 	/* DFPU Coprocessor, single precision only */
+#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE  0               	/* DFPU Coprocessor, single and double precision */
+#define XCHAL_HAVE_VECTRA1		0	/* Vectra I  pkg */
+#define XCHAL_HAVE_VECTRALX		0	/* Vectra LX pkg */
+#define XCHAL_HAVE_PDX4		        0	/* PDX4 */
+#define XCHAL_HAVE_CONNXD2		0	/* ConnX D2 pkg */
+#define XCHAL_HAVE_CONNXD2_DUALLSFLIX   0	/* ConnX D2 & Dual LoadStore Flix */
+#define XCHAL_HAVE_BBE16		0	/* ConnX BBE16 pkg */
+#define XCHAL_HAVE_BBE16_RSQRT		0	/* BBE16 & vector recip sqrt */
+#define XCHAL_HAVE_BBE16_VECDIV		0	/* BBE16 & vector divide */
+#define XCHAL_HAVE_BBE16_DESPREAD	0	/* BBE16 & despread */
+#define XCHAL_HAVE_BBENEP		0	/* ConnX BBENEP pkgs */
+#define XCHAL_HAVE_BSP3			0	/* ConnX BSP3 pkg */
+#define XCHAL_HAVE_BSP3_TRANSPOSE	0	/* BSP3 & transpose32x32 */
+#define XCHAL_HAVE_SSP16		0	/* ConnX SSP16 pkg */
+#define XCHAL_HAVE_SSP16_VITERBI	0	/* SSP16 & viterbi */
+#define XCHAL_HAVE_TURBO16		0	/* ConnX Turbo16 pkg */
+#define XCHAL_HAVE_BBP16		0	/* ConnX BBP16 pkg */
+#define XCHAL_HAVE_FLIX3		0	/* basic 3-way FLIX option */
+#define XCHAL_HAVE_GRIVPEP              0   /*  GRIVPEP is General Release of IVPEP */
+#define XCHAL_HAVE_GRIVPEP_HISTOGRAM    0   /* Histogram option on GRIVPEP */
+
+
+/*----------------------------------------------------------------------
+				MISC
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_NUM_LOADSTORE_UNITS	1	/* load/store units */
+#define XCHAL_NUM_WRITEBUFFER_ENTRIES	4	/* size of write buffer */
+#define XCHAL_INST_FETCH_WIDTH		4	/* instr-fetch width in bytes */
+#define XCHAL_DATA_WIDTH		4	/* data width in bytes */
+#define XCHAL_DATA_PIPE_DELAY		2	/* d-side pipeline delay
+						   (1 = 5-stage, 2 = 7-stage) */
+#define XCHAL_CLOCK_GATING_GLOBAL	1	/* global clock gating */
+#define XCHAL_CLOCK_GATING_FUNCUNIT	1	/* funct. unit clock gating */
+/*  In T1050, applies to selected core load and store instructions (see ISA): */
+#define XCHAL_UNALIGNED_LOAD_EXCEPTION	0	/* unaligned loads cause exc. */
+#define XCHAL_UNALIGNED_STORE_EXCEPTION	0	/* unaligned stores cause exc.*/
+#define XCHAL_UNALIGNED_LOAD_HW		1	/* unaligned loads work in hw */
+#define XCHAL_UNALIGNED_STORE_HW	1	/* unaligned stores work in hw*/
+
+#define XCHAL_SW_VERSION		1100003	/* sw version of this header */
+
+#define XCHAL_CORE_ID			"esp32_v3_49_prod"	/* alphanum core name
+						   (CoreID) set in the Xtensa
+						   Processor Generator */
+
+#define XCHAL_BUILD_UNIQUE_ID		0x0005FE96	/* 22-bit sw build ID */
+
+/*
+ *  These definitions describe the hardware targeted by this software.
+ */
+#define XCHAL_HW_CONFIGID0		0xC2BCFFFE	/* ConfigID hi 32 bits*/
+#define XCHAL_HW_CONFIGID1		0x1CC5FE96	/* ConfigID lo 32 bits*/
+#define XCHAL_HW_VERSION_NAME		"LX6.0.3"	/* full version name */
+#define XCHAL_HW_VERSION_MAJOR		2600	/* major ver# of targeted hw */
+#define XCHAL_HW_VERSION_MINOR		3	/* minor ver# of targeted hw */
+#define XCHAL_HW_VERSION		260003	/* major*100+minor */
+#define XCHAL_HW_REL_LX6		1
+#define XCHAL_HW_REL_LX6_0		1
+#define XCHAL_HW_REL_LX6_0_3		1
+#define XCHAL_HW_CONFIGID_RELIABLE	1
+/*  If software targets a *range* of hardware versions, these are the bounds: */
+#define XCHAL_HW_MIN_VERSION_MAJOR	2600	/* major v of earliest tgt hw */
+#define XCHAL_HW_MIN_VERSION_MINOR	3	/* minor v of earliest tgt hw */
+#define XCHAL_HW_MIN_VERSION		260003	/* earliest targeted hw */
+#define XCHAL_HW_MAX_VERSION_MAJOR	2600	/* major v of latest tgt hw */
+#define XCHAL_HW_MAX_VERSION_MINOR	3	/* minor v of latest tgt hw */
+#define XCHAL_HW_MAX_VERSION		260003	/* latest targeted hw */
+
+
+/*----------------------------------------------------------------------
+				CACHE
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_ICACHE_LINESIZE		4	/* I-cache line size in bytes */
+#define XCHAL_DCACHE_LINESIZE		4	/* D-cache line size in bytes */
+#define XCHAL_ICACHE_LINEWIDTH		2	/* log2(I line size in bytes) */
+#define XCHAL_DCACHE_LINEWIDTH		2	/* log2(D line size in bytes) */
+
+#define XCHAL_ICACHE_SIZE		0	/* I-cache size in bytes or 0 */
+#define XCHAL_DCACHE_SIZE		0	/* D-cache size in bytes or 0 */
+
+#define XCHAL_DCACHE_IS_WRITEBACK	0	/* writeback feature */
+#define XCHAL_DCACHE_IS_COHERENT	0	/* MP coherence feature */
+
+#define XCHAL_HAVE_PREFETCH		0	/* PREFCTL register */
+#define XCHAL_HAVE_PREFETCH_L1		0	/* prefetch to L1 dcache */
+#define XCHAL_PREFETCH_CASTOUT_LINES	0	/* dcache pref. castout bufsz */
+#define XCHAL_PREFETCH_ENTRIES		0	/* cache prefetch entries */
+#define XCHAL_PREFETCH_BLOCK_ENTRIES	0	/* prefetch block streams */
+#define XCHAL_HAVE_CACHE_BLOCKOPS	0	/* block prefetch for caches */
+#define XCHAL_HAVE_ICACHE_TEST		0	/* Icache test instructions */
+#define XCHAL_HAVE_DCACHE_TEST		0	/* Dcache test instructions */
+#define XCHAL_HAVE_ICACHE_DYN_WAYS	0	/* Icache dynamic way support */
+#define XCHAL_HAVE_DCACHE_DYN_WAYS	0	/* Dcache dynamic way support */
+
+
+
+
+/****************************************************************************
+    Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
+ ****************************************************************************/
+
+
+#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
+
+/*----------------------------------------------------------------------
+				CACHE
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_PIF			1	/* any outbound PIF present */
+#define XCHAL_HAVE_AXI			0	/* AXI bus */
+
+#define XCHAL_HAVE_PIF_WR_RESP			0	/* pif write response */
+#define XCHAL_HAVE_PIF_REQ_ATTR			0	/* pif attribute */
+
+/*  If present, cache size in bytes == (ways * 2^(linewidth + setwidth)).  */
+
+/*  Number of cache sets in log2(lines per way):  */
+#define XCHAL_ICACHE_SETWIDTH		0
+#define XCHAL_DCACHE_SETWIDTH		0
+
+/*  Cache set associativity (number of ways):  */
+#define XCHAL_ICACHE_WAYS		1
+#define XCHAL_DCACHE_WAYS		1
+
+/*  Cache features:  */
+#define XCHAL_ICACHE_LINE_LOCKABLE	0
+#define XCHAL_DCACHE_LINE_LOCKABLE	0
+#define XCHAL_ICACHE_ECC_PARITY		0
+#define XCHAL_DCACHE_ECC_PARITY		0
+
+/*  Cache access size in bytes (affects operation of SICW instruction):  */
+#define XCHAL_ICACHE_ACCESS_SIZE	1
+#define XCHAL_DCACHE_ACCESS_SIZE	1
+
+#define XCHAL_DCACHE_BANKS		0	/* number of banks */
+
+/*  Number of encoded cache attr bits (see  for decoded bits):  */
+#define XCHAL_CA_BITS			4
+
+
+/*----------------------------------------------------------------------
+			INTERNAL I/D RAM/ROMs and XLMI
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_NUM_INSTROM		1	/* number of core instr. ROMs */
+#define XCHAL_NUM_INSTRAM		2	/* number of core instr. RAMs */
+#define XCHAL_NUM_DATAROM		1	/* number of core data ROMs */
+#define XCHAL_NUM_DATARAM		2	/* number of core data RAMs */
+#define XCHAL_NUM_URAM			0	/* number of core unified RAMs*/
+#define XCHAL_NUM_XLMI			1	/* number of core XLMI ports */
+
+/*  Instruction ROM 0:  */
+#define XCHAL_INSTROM0_VADDR		0x40800000	/* virtual address */
+#define XCHAL_INSTROM0_PADDR		0x40800000	/* physical address */
+#define XCHAL_INSTROM0_SIZE		4194304	/* size in bytes */
+#define XCHAL_INSTROM0_ECC_PARITY	0	/* ECC/parity type, 0=none */
+
+/*  Instruction RAM 0:  */
+#define XCHAL_INSTRAM0_VADDR		0x40000000	/* virtual address */
+#define XCHAL_INSTRAM0_PADDR		0x40000000	/* physical address */
+#define XCHAL_INSTRAM0_SIZE		4194304	/* size in bytes */
+#define XCHAL_INSTRAM0_ECC_PARITY	0	/* ECC/parity type, 0=none */
+
+/*  Instruction RAM 1:  */
+#define XCHAL_INSTRAM1_VADDR		0x40400000	/* virtual address */
+#define XCHAL_INSTRAM1_PADDR		0x40400000	/* physical address */
+#define XCHAL_INSTRAM1_SIZE		4194304	/* size in bytes */
+#define XCHAL_INSTRAM1_ECC_PARITY	0	/* ECC/parity type, 0=none */
+
+/*  Data ROM 0:  */
+#define XCHAL_DATAROM0_VADDR		0x3F400000	/* virtual address */
+#define XCHAL_DATAROM0_PADDR		0x3F400000	/* physical address */
+#define XCHAL_DATAROM0_SIZE		4194304	/* size in bytes */
+#define XCHAL_DATAROM0_ECC_PARITY	0	/* ECC/parity type, 0=none */
+#define XCHAL_DATAROM0_BANKS		1	/* number of banks */
+
+/*  Data RAM 0:  */
+#define XCHAL_DATARAM0_VADDR		0x3FF80000	/* virtual address */
+#define XCHAL_DATARAM0_PADDR		0x3FF80000	/* physical address */
+#define XCHAL_DATARAM0_SIZE		524288	/* size in bytes */
+#define XCHAL_DATARAM0_ECC_PARITY	0	/* ECC/parity type, 0=none */
+#define XCHAL_DATARAM0_BANKS		1	/* number of banks */
+
+/*  Data RAM 1:  */
+#define XCHAL_DATARAM1_VADDR		0x3F800000	/* virtual address */
+#define XCHAL_DATARAM1_PADDR		0x3F800000	/* physical address */
+#define XCHAL_DATARAM1_SIZE		4194304	/* size in bytes */
+#define XCHAL_DATARAM1_ECC_PARITY	0	/* ECC/parity type, 0=none */
+#define XCHAL_DATARAM1_BANKS		1	/* number of banks */
+
+/*  XLMI Port 0:  */
+#define XCHAL_XLMI0_VADDR		0x3FF00000	/* virtual address */
+#define XCHAL_XLMI0_PADDR		0x3FF00000	/* physical address */
+#define XCHAL_XLMI0_SIZE		524288	/* size in bytes */
+#define XCHAL_XLMI0_ECC_PARITY	0	/* ECC/parity type, 0=none */
+
+#define XCHAL_HAVE_IMEM_LOADSTORE	1	/* can load/store to IROM/IRAM*/
+
+
+/*----------------------------------------------------------------------
+			INTERRUPTS and TIMERS
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_INTERRUPTS		1	/* interrupt option */
+#define XCHAL_HAVE_HIGHPRI_INTERRUPTS	1	/* med/high-pri. interrupts */
+#define XCHAL_HAVE_NMI			1	/* non-maskable interrupt */
+#define XCHAL_HAVE_CCOUNT		1	/* CCOUNT reg. (timer option) */
+#define XCHAL_NUM_TIMERS		3	/* number of CCOMPAREn regs */
+#define XCHAL_NUM_INTERRUPTS		32	/* number of interrupts */
+#define XCHAL_NUM_INTERRUPTS_LOG2	5	/* ceil(log2(NUM_INTERRUPTS)) */
+#define XCHAL_NUM_EXTINTERRUPTS		26	/* num of external interrupts */
+#define XCHAL_NUM_INTLEVELS		6	/* number of interrupt levels
+						   (not including level zero) */
+#define XCHAL_EXCM_LEVEL		3	/* level masked by PS.EXCM */
+	/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
+
+/*  Masks of interrupts at each interrupt level:  */
+#define XCHAL_INTLEVEL1_MASK		0x000637FF
+#define XCHAL_INTLEVEL2_MASK		0x00380000
+#define XCHAL_INTLEVEL3_MASK		0x28C08800
+#define XCHAL_INTLEVEL4_MASK		0x53000000
+#define XCHAL_INTLEVEL5_MASK		0x84010000
+#define XCHAL_INTLEVEL6_MASK		0x00000000
+#define XCHAL_INTLEVEL7_MASK		0x00004000
+
+/*  Masks of interrupts at each range 1..n of interrupt levels:  */
+#define XCHAL_INTLEVEL1_ANDBELOW_MASK	0x000637FF
+#define XCHAL_INTLEVEL2_ANDBELOW_MASK	0x003E37FF
+#define XCHAL_INTLEVEL3_ANDBELOW_MASK	0x28FEBFFF
+#define XCHAL_INTLEVEL4_ANDBELOW_MASK	0x7BFEBFFF
+#define XCHAL_INTLEVEL5_ANDBELOW_MASK	0xFFFFBFFF
+#define XCHAL_INTLEVEL6_ANDBELOW_MASK	0xFFFFBFFF
+#define XCHAL_INTLEVEL7_ANDBELOW_MASK	0xFFFFFFFF
+
+/*  Level of each interrupt:  */
+#define XCHAL_INT0_LEVEL		1
+#define XCHAL_INT1_LEVEL		1
+#define XCHAL_INT2_LEVEL		1
+#define XCHAL_INT3_LEVEL		1
+#define XCHAL_INT4_LEVEL		1
+#define XCHAL_INT5_LEVEL		1
+#define XCHAL_INT6_LEVEL		1
+#define XCHAL_INT7_LEVEL		1
+#define XCHAL_INT8_LEVEL		1
+#define XCHAL_INT9_LEVEL		1
+#define XCHAL_INT10_LEVEL		1
+#define XCHAL_INT11_LEVEL		3
+#define XCHAL_INT12_LEVEL		1
+#define XCHAL_INT13_LEVEL		1
+#define XCHAL_INT14_LEVEL		7
+#define XCHAL_INT15_LEVEL		3
+#define XCHAL_INT16_LEVEL		5
+#define XCHAL_INT17_LEVEL		1
+#define XCHAL_INT18_LEVEL		1
+#define XCHAL_INT19_LEVEL		2
+#define XCHAL_INT20_LEVEL		2
+#define XCHAL_INT21_LEVEL		2
+#define XCHAL_INT22_LEVEL		3
+#define XCHAL_INT23_LEVEL		3
+#define XCHAL_INT24_LEVEL		4
+#define XCHAL_INT25_LEVEL		4
+#define XCHAL_INT26_LEVEL		5
+#define XCHAL_INT27_LEVEL		3
+#define XCHAL_INT28_LEVEL		4
+#define XCHAL_INT29_LEVEL		3
+#define XCHAL_INT30_LEVEL		4
+#define XCHAL_INT31_LEVEL		5
+#define XCHAL_DEBUGLEVEL		6	/* debug interrupt level */
+#define XCHAL_HAVE_DEBUG_EXTERN_INT	1	/* OCD external db interrupt */
+#define XCHAL_NMILEVEL			7	/* NMI "level" (for use with
+						   EXCSAVE/EPS/EPC_n, RFI n) */
+
+/*  Type of each interrupt:  */
+#define XCHAL_INT0_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT1_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT2_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT3_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT4_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT5_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT6_TYPE 	XTHAL_INTTYPE_TIMER
+#define XCHAL_INT7_TYPE 	XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT8_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT9_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT10_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT11_TYPE 	XTHAL_INTTYPE_PROFILING
+#define XCHAL_INT12_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT13_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT14_TYPE 	XTHAL_INTTYPE_NMI
+#define XCHAL_INT15_TYPE 	XTHAL_INTTYPE_TIMER
+#define XCHAL_INT16_TYPE 	XTHAL_INTTYPE_TIMER
+#define XCHAL_INT17_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT18_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT19_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT20_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT21_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT22_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT23_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT24_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT25_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT26_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT27_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT28_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT29_TYPE 	XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT30_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT31_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+
+/*  Masks of interrupts for each type of interrupt:  */
+#define XCHAL_INTTYPE_MASK_UNCONFIGURED	0x00000000
+#define XCHAL_INTTYPE_MASK_SOFTWARE	0x20000080
+#define XCHAL_INTTYPE_MASK_EXTERN_EDGE	0x50400400
+#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL	0x8FBE333F
+#define XCHAL_INTTYPE_MASK_TIMER	0x00018040
+#define XCHAL_INTTYPE_MASK_NMI		0x00004000
+#define XCHAL_INTTYPE_MASK_WRITE_ERROR	0x00000000
+#define XCHAL_INTTYPE_MASK_PROFILING	0x00000800
+
+/*  Interrupt numbers assigned to specific interrupt sources:  */
+#define XCHAL_TIMER0_INTERRUPT		6	/* CCOMPARE0 */
+#define XCHAL_TIMER1_INTERRUPT		15	/* CCOMPARE1 */
+#define XCHAL_TIMER2_INTERRUPT		16	/* CCOMPARE2 */
+#define XCHAL_TIMER3_INTERRUPT		XTHAL_TIMER_UNCONFIGURED
+#define XCHAL_NMI_INTERRUPT		14	/* non-maskable interrupt */
+#define XCHAL_PROFILING_INTERRUPT	11	/* profiling interrupt */
+
+/*  Interrupt numbers for levels at which only one interrupt is configured:  */
+#define XCHAL_INTLEVEL7_NUM		14
+/*  (There are many interrupts each at level(s) 1, 2, 3, 4, 5.)  */
+
+
+/*
+ *  External interrupt mapping.
+ *  These macros describe how Xtensa processor interrupt numbers
+ *  (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
+ *  map to external BInterrupt pins, for those interrupts
+ *  configured as external (level-triggered, edge-triggered, or NMI).
+ *  See the Xtensa processor databook for more details.
+ */
+
+/*  Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number:  */
+#define XCHAL_EXTINT0_NUM		0	/* (intlevel 1) */
+#define XCHAL_EXTINT1_NUM		1	/* (intlevel 1) */
+#define XCHAL_EXTINT2_NUM		2	/* (intlevel 1) */
+#define XCHAL_EXTINT3_NUM		3	/* (intlevel 1) */
+#define XCHAL_EXTINT4_NUM		4	/* (intlevel 1) */
+#define XCHAL_EXTINT5_NUM		5	/* (intlevel 1) */
+#define XCHAL_EXTINT6_NUM		8	/* (intlevel 1) */
+#define XCHAL_EXTINT7_NUM		9	/* (intlevel 1) */
+#define XCHAL_EXTINT8_NUM		10	/* (intlevel 1) */
+#define XCHAL_EXTINT9_NUM		12	/* (intlevel 1) */
+#define XCHAL_EXTINT10_NUM		13	/* (intlevel 1) */
+#define XCHAL_EXTINT11_NUM		14	/* (intlevel 7) */
+#define XCHAL_EXTINT12_NUM		17	/* (intlevel 1) */
+#define XCHAL_EXTINT13_NUM		18	/* (intlevel 1) */
+#define XCHAL_EXTINT14_NUM		19	/* (intlevel 2) */
+#define XCHAL_EXTINT15_NUM		20	/* (intlevel 2) */
+#define XCHAL_EXTINT16_NUM		21	/* (intlevel 2) */
+#define XCHAL_EXTINT17_NUM		22	/* (intlevel 3) */
+#define XCHAL_EXTINT18_NUM		23	/* (intlevel 3) */
+#define XCHAL_EXTINT19_NUM		24	/* (intlevel 4) */
+#define XCHAL_EXTINT20_NUM		25	/* (intlevel 4) */
+#define XCHAL_EXTINT21_NUM		26	/* (intlevel 5) */
+#define XCHAL_EXTINT22_NUM		27	/* (intlevel 3) */
+#define XCHAL_EXTINT23_NUM		28	/* (intlevel 4) */
+#define XCHAL_EXTINT24_NUM		30	/* (intlevel 4) */
+#define XCHAL_EXTINT25_NUM		31	/* (intlevel 5) */
+/*  EXTERNAL BInterrupt pin numbers mapped to each core interrupt number:  */
+#define XCHAL_INT0_EXTNUM		0	/* (intlevel 1) */
+#define XCHAL_INT1_EXTNUM		1	/* (intlevel 1) */
+#define XCHAL_INT2_EXTNUM		2	/* (intlevel 1) */
+#define XCHAL_INT3_EXTNUM		3	/* (intlevel 1) */
+#define XCHAL_INT4_EXTNUM		4	/* (intlevel 1) */
+#define XCHAL_INT5_EXTNUM		5	/* (intlevel 1) */
+#define XCHAL_INT8_EXTNUM		6	/* (intlevel 1) */
+#define XCHAL_INT9_EXTNUM		7	/* (intlevel 1) */
+#define XCHAL_INT10_EXTNUM		8	/* (intlevel 1) */
+#define XCHAL_INT12_EXTNUM		9	/* (intlevel 1) */
+#define XCHAL_INT13_EXTNUM		10	/* (intlevel 1) */
+#define XCHAL_INT14_EXTNUM		11	/* (intlevel 7) */
+#define XCHAL_INT17_EXTNUM		12	/* (intlevel 1) */
+#define XCHAL_INT18_EXTNUM		13	/* (intlevel 1) */
+#define XCHAL_INT19_EXTNUM		14	/* (intlevel 2) */
+#define XCHAL_INT20_EXTNUM		15	/* (intlevel 2) */
+#define XCHAL_INT21_EXTNUM		16	/* (intlevel 2) */
+#define XCHAL_INT22_EXTNUM		17	/* (intlevel 3) */
+#define XCHAL_INT23_EXTNUM		18	/* (intlevel 3) */
+#define XCHAL_INT24_EXTNUM		19	/* (intlevel 4) */
+#define XCHAL_INT25_EXTNUM		20	/* (intlevel 4) */
+#define XCHAL_INT26_EXTNUM		21	/* (intlevel 5) */
+#define XCHAL_INT27_EXTNUM		22	/* (intlevel 3) */
+#define XCHAL_INT28_EXTNUM		23	/* (intlevel 4) */
+#define XCHAL_INT30_EXTNUM		24	/* (intlevel 4) */
+#define XCHAL_INT31_EXTNUM		25	/* (intlevel 5) */
+
+
+/*----------------------------------------------------------------------
+			EXCEPTIONS and VECTORS
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_XEA_VERSION		2	/* Xtensa Exception Architecture
+						   number: 1 == XEA1 (old)
+							   2 == XEA2 (new)
+							   0 == XEAX (extern) or TX */
+#define XCHAL_HAVE_XEA1			0	/* Exception Architecture 1 */
+#define XCHAL_HAVE_XEA2			1	/* Exception Architecture 2 */
+#define XCHAL_HAVE_XEAX			0	/* External Exception Arch. */
+#define XCHAL_HAVE_EXCEPTIONS		1	/* exception option */
+#define XCHAL_HAVE_HALT			0	/* halt architecture option */
+#define XCHAL_HAVE_BOOTLOADER		0	/* boot loader (for TX) */
+#define XCHAL_HAVE_MEM_ECC_PARITY	0	/* local memory ECC/parity */
+#define XCHAL_HAVE_VECTOR_SELECT	1	/* relocatable vectors */
+#define XCHAL_HAVE_VECBASE		1	/* relocatable vectors */
+#define XCHAL_VECBASE_RESET_VADDR	0x40000000  /* VECBASE reset value */
+#define XCHAL_VECBASE_RESET_PADDR	0x40000000
+#define XCHAL_RESET_VECBASE_OVERLAP	0
+
+#define XCHAL_RESET_VECTOR0_VADDR	0x50000000
+#define XCHAL_RESET_VECTOR0_PADDR	0x50000000
+#define XCHAL_RESET_VECTOR1_VADDR	0x40000400
+#define XCHAL_RESET_VECTOR1_PADDR	0x40000400
+#define XCHAL_RESET_VECTOR_VADDR	0x40000400
+#define XCHAL_RESET_VECTOR_PADDR	0x40000400
+#define XCHAL_USER_VECOFS		0x00000340
+#define XCHAL_USER_VECTOR_VADDR		0x40000340
+#define XCHAL_USER_VECTOR_PADDR		0x40000340
+#define XCHAL_KERNEL_VECOFS		0x00000300
+#define XCHAL_KERNEL_VECTOR_VADDR	0x40000300
+#define XCHAL_KERNEL_VECTOR_PADDR	0x40000300
+#define XCHAL_DOUBLEEXC_VECOFS		0x000003C0
+#define XCHAL_DOUBLEEXC_VECTOR_VADDR	0x400003C0
+#define XCHAL_DOUBLEEXC_VECTOR_PADDR	0x400003C0
+#define XCHAL_WINDOW_OF4_VECOFS		0x00000000
+#define XCHAL_WINDOW_UF4_VECOFS		0x00000040
+#define XCHAL_WINDOW_OF8_VECOFS		0x00000080
+#define XCHAL_WINDOW_UF8_VECOFS		0x000000C0
+#define XCHAL_WINDOW_OF12_VECOFS	0x00000100
+#define XCHAL_WINDOW_UF12_VECOFS	0x00000140
+#define XCHAL_WINDOW_VECTORS_VADDR	0x40000000
+#define XCHAL_WINDOW_VECTORS_PADDR	0x40000000
+#define XCHAL_INTLEVEL2_VECOFS		0x00000180
+#define XCHAL_INTLEVEL2_VECTOR_VADDR	0x40000180
+#define XCHAL_INTLEVEL2_VECTOR_PADDR	0x40000180
+#define XCHAL_INTLEVEL3_VECOFS		0x000001C0
+#define XCHAL_INTLEVEL3_VECTOR_VADDR	0x400001C0
+#define XCHAL_INTLEVEL3_VECTOR_PADDR	0x400001C0
+#define XCHAL_INTLEVEL4_VECOFS		0x00000200
+#define XCHAL_INTLEVEL4_VECTOR_VADDR	0x40000200
+#define XCHAL_INTLEVEL4_VECTOR_PADDR	0x40000200
+#define XCHAL_INTLEVEL5_VECOFS		0x00000240
+#define XCHAL_INTLEVEL5_VECTOR_VADDR	0x40000240
+#define XCHAL_INTLEVEL5_VECTOR_PADDR	0x40000240
+#define XCHAL_INTLEVEL6_VECOFS		0x00000280
+#define XCHAL_INTLEVEL6_VECTOR_VADDR	0x40000280
+#define XCHAL_INTLEVEL6_VECTOR_PADDR	0x40000280
+#define XCHAL_DEBUG_VECOFS		XCHAL_INTLEVEL6_VECOFS
+#define XCHAL_DEBUG_VECTOR_VADDR	XCHAL_INTLEVEL6_VECTOR_VADDR
+#define XCHAL_DEBUG_VECTOR_PADDR	XCHAL_INTLEVEL6_VECTOR_PADDR
+#define XCHAL_NMI_VECOFS		0x000002C0
+#define XCHAL_NMI_VECTOR_VADDR		0x400002C0
+#define XCHAL_NMI_VECTOR_PADDR		0x400002C0
+#define XCHAL_INTLEVEL7_VECOFS		XCHAL_NMI_VECOFS
+#define XCHAL_INTLEVEL7_VECTOR_VADDR	XCHAL_NMI_VECTOR_VADDR
+#define XCHAL_INTLEVEL7_VECTOR_PADDR	XCHAL_NMI_VECTOR_PADDR
+
+
+/*----------------------------------------------------------------------
+				DEBUG MODULE
+  ----------------------------------------------------------------------*/
+
+/*  Misc  */
+#define XCHAL_HAVE_DEBUG_ERI		1	/* ERI to debug module */
+#define XCHAL_HAVE_DEBUG_APB		1	/* APB to debug module */
+#define XCHAL_HAVE_DEBUG_JTAG		1	/* JTAG to debug module */
+
+/*  On-Chip Debug (OCD)  */
+#define XCHAL_HAVE_OCD			1	/* OnChipDebug option */
+#define XCHAL_NUM_IBREAK		2	/* number of IBREAKn regs */
+#define XCHAL_NUM_DBREAK		2	/* number of DBREAKn regs */
+#define XCHAL_HAVE_OCD_DIR_ARRAY	0	/* faster OCD option (to LX4) */
+#define XCHAL_HAVE_OCD_LS32DDR		1	/* L32DDR/S32DDR (faster OCD) */
+
+/*  TRAX (in core)  */
+#define XCHAL_HAVE_TRAX			1	/* TRAX in debug module */
+#define XCHAL_TRAX_MEM_SIZE		16384	/* TRAX memory size in bytes */
+#define XCHAL_TRAX_MEM_SHAREABLE	1	/* start/end regs; ready sig. */
+#define XCHAL_TRAX_ATB_WIDTH		32	/* ATB width (bits), 0=no ATB */
+#define XCHAL_TRAX_TIME_WIDTH		0	/* timestamp bitwidth, 0=none */
+
+/*  Perf counters  */
+#define XCHAL_NUM_PERF_COUNTERS		2	/* performance counters */
+
+
+/*----------------------------------------------------------------------
+				MMU
+  ----------------------------------------------------------------------*/
+
+/*  See core-matmap.h header file for more details.  */
+
+#define XCHAL_HAVE_TLBS			1	/* inverse of HAVE_CACHEATTR */
+#define XCHAL_HAVE_SPANNING_WAY		1	/* one way maps I+D 4GB vaddr */
+#define XCHAL_SPANNING_WAY		0	/* TLB spanning way number */
+#define XCHAL_HAVE_IDENTITY_MAP		1	/* vaddr == paddr always */
+#define XCHAL_HAVE_CACHEATTR		0	/* CACHEATTR register present */
+#define XCHAL_HAVE_MIMIC_CACHEATTR	1	/* region protection */
+#define XCHAL_HAVE_XLT_CACHEATTR	0	/* region prot. w/translation */
+#define XCHAL_HAVE_PTP_MMU		0	/* full MMU (with page table
+						   [autorefill] and protection)
+						   usable for an MMU-based OS */
+/*  If none of the above last 4 are set, it's a custom TLB configuration.  */
+
+#define XCHAL_MMU_ASID_BITS		0	/* number of bits in ASIDs */
+#define XCHAL_MMU_RINGS			1	/* number of rings (1..4) */
+#define XCHAL_MMU_RING_BITS		0	/* num of bits in RING field */
+
+#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
+
+
+#endif /* _XTENSA_CORE_CONFIGURATION_H */
+
diff --git a/tools/sdk/include/nghttp/config.h b/tools/sdk/include/nghttp/config.h
new file mode 100644
index 00000000..f193b0af
--- /dev/null
+++ b/tools/sdk/include/nghttp/config.h
@@ -0,0 +1,36 @@
+#ifndef __HAVE_CONFIG_H_
+#define __HAVE_CONFIG_H_
+
+#define _U_
+
+#define SIZEOF_INT_P 2
+
+//#define DEBUGBUILD
+#include "stdio.h"
+#include "stdlib.h"
+#include "string.h"
+
+#if (!defined(nghttp_unlikely))
+#define nghttp_unlikely(Expression)	!!(Expression)
+#endif
+
+#define nghttp_ASSERT(Expression) do{if (!(Expression)) printf("%d\n", __LINE__);}while(0)
+
+#define CU_ASSERT(a) nghttp_ASSERT(a)
+#define CU_ASSERT_FATAL(a) nghttp_ASSERT(a)
+
+#if 1
+#define NGHTTP2_DEBUG_INFO() printf("%s %d\n", __FILE__, __LINE__)
+#else
+#define NGHTTP2_DEBUG_INFO()
+#endif
+
+#define NGHTTP_PLATFORM_HTONS(_n)  ((uint16_t)((((_n) & 0xff) << 8) | (((_n) >> 8) & 0xff)))
+#define NGHTTP_PLATFORM_HTONL(_n)  ((uint32_t)( (((_n) & 0xff) << 24) | (((_n) & 0xff00) << 8) | (((_n) >> 8)  & 0xff00) | (((_n) >> 24) & 0xff) ))
+
+#define htons(x) NGHTTP_PLATFORM_HTONS(x)
+#define ntohs(x) NGHTTP_PLATFORM_HTONS(x)
+#define htonl(x) NGHTTP_PLATFORM_HTONL(x)
+#define ntohl(x) NGHTTP_PLATFORM_HTONL(x)
+
+#endif
diff --git a/tools/sdk/include/nghttp/http_parser.h b/tools/sdk/include/nghttp/http_parser.h
new file mode 100644
index 00000000..105ae510
--- /dev/null
+++ b/tools/sdk/include/nghttp/http_parser.h
@@ -0,0 +1,362 @@
+/* Copyright Joyent, Inc. and other Node contributors. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+#ifndef http_parser_h
+#define http_parser_h
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Also update SONAME in the Makefile whenever you change these. */
+#define HTTP_PARSER_VERSION_MAJOR 2
+#define HTTP_PARSER_VERSION_MINOR 7
+#define HTTP_PARSER_VERSION_PATCH 0
+
+#include 
+#if defined(_WIN32) && !defined(__MINGW32__) && \
+  (!defined(_MSC_VER) || _MSC_VER<1600) && !defined(__WINE__)
+#include 
+#include 
+typedef __int8 int8_t;
+typedef unsigned __int8 uint8_t;
+typedef __int16 int16_t;
+typedef unsigned __int16 uint16_t;
+typedef __int32 int32_t;
+typedef unsigned __int32 uint32_t;
+typedef __int64 int64_t;
+typedef unsigned __int64 uint64_t;
+#else
+#include 
+#endif
+
+/* Compile with -DHTTP_PARSER_STRICT=0 to make less checks, but run
+ * faster
+ */
+#ifndef HTTP_PARSER_STRICT
+# define HTTP_PARSER_STRICT 1
+#endif
+
+/* Maximium header size allowed. If the macro is not defined
+ * before including this header then the default is used. To
+ * change the maximum header size, define the macro in the build
+ * environment (e.g. -DHTTP_MAX_HEADER_SIZE=). To remove
+ * the effective limit on the size of the header, define the macro
+ * to a very large number (e.g. -DHTTP_MAX_HEADER_SIZE=0x7fffffff)
+ */
+#ifndef HTTP_MAX_HEADER_SIZE
+# define HTTP_MAX_HEADER_SIZE (80*1024)
+#endif
+
+typedef struct http_parser http_parser;
+typedef struct http_parser_settings http_parser_settings;
+
+
+/* Callbacks should return non-zero to indicate an error. The parser will
+ * then halt execution.
+ *
+ * The one exception is on_headers_complete. In a HTTP_RESPONSE parser
+ * returning '1' from on_headers_complete will tell the parser that it
+ * should not expect a body. This is used when receiving a response to a
+ * HEAD request which may contain 'Content-Length' or 'Transfer-Encoding:
+ * chunked' headers that indicate the presence of a body.
+ *
+ * Returning `2` from on_headers_complete will tell parser that it should not
+ * expect neither a body nor any futher responses on this connection. This is
+ * useful for handling responses to a CONNECT request which may not contain
+ * `Upgrade` or `Connection: upgrade` headers.
+ *
+ * http_data_cb does not return data chunks. It will be called arbitrarily
+ * many times for each string. E.G. you might get 10 callbacks for "on_url"
+ * each providing just a few characters more data.
+ */
+typedef int (*http_data_cb) (http_parser*, const char *at, size_t length);
+typedef int (*http_cb) (http_parser*);
+
+
+/* Request Methods */
+#define HTTP_METHOD_MAP(XX)         \
+  XX(0,  DELETE,      DELETE)       \
+  XX(1,  GET,         GET)          \
+  XX(2,  HEAD,        HEAD)         \
+  XX(3,  POST,        POST)         \
+  XX(4,  PUT,         PUT)          \
+  /* pathological */                \
+  XX(5,  CONNECT,     CONNECT)      \
+  XX(6,  OPTIONS,     OPTIONS)      \
+  XX(7,  TRACE,       TRACE)        \
+  /* WebDAV */                      \
+  XX(8,  COPY,        COPY)         \
+  XX(9,  LOCK,        LOCK)         \
+  XX(10, MKCOL,       MKCOL)        \
+  XX(11, MOVE,        MOVE)         \
+  XX(12, PROPFIND,    PROPFIND)     \
+  XX(13, PROPPATCH,   PROPPATCH)    \
+  XX(14, SEARCH,      SEARCH)       \
+  XX(15, UNLOCK,      UNLOCK)       \
+  XX(16, BIND,        BIND)         \
+  XX(17, REBIND,      REBIND)       \
+  XX(18, UNBIND,      UNBIND)       \
+  XX(19, ACL,         ACL)          \
+  /* subversion */                  \
+  XX(20, REPORT,      REPORT)       \
+  XX(21, MKACTIVITY,  MKACTIVITY)   \
+  XX(22, CHECKOUT,    CHECKOUT)     \
+  XX(23, MERGE,       MERGE)        \
+  /* upnp */                        \
+  XX(24, MSEARCH,     M-SEARCH)     \
+  XX(25, NOTIFY,      NOTIFY)       \
+  XX(26, SUBSCRIBE,   SUBSCRIBE)    \
+  XX(27, UNSUBSCRIBE, UNSUBSCRIBE)  \
+  /* RFC-5789 */                    \
+  XX(28, PATCH,       PATCH)        \
+  XX(29, PURGE,       PURGE)        \
+  /* CalDAV */                      \
+  XX(30, MKCALENDAR,  MKCALENDAR)   \
+  /* RFC-2068, section 19.6.1.2 */  \
+  XX(31, LINK,        LINK)         \
+  XX(32, UNLINK,      UNLINK)       \
+
+enum http_method
+  {
+#define XX(num, name, string) HTTP_##name = num,
+  HTTP_METHOD_MAP(XX)
+#undef XX
+  };
+
+
+enum http_parser_type { HTTP_REQUEST, HTTP_RESPONSE, HTTP_BOTH };
+
+
+/* Flag values for http_parser.flags field */
+enum flags
+  { F_CHUNKED               = 1 << 0
+  , F_CONNECTION_KEEP_ALIVE = 1 << 1
+  , F_CONNECTION_CLOSE      = 1 << 2
+  , F_CONNECTION_UPGRADE    = 1 << 3
+  , F_TRAILING              = 1 << 4
+  , F_UPGRADE               = 1 << 5
+  , F_SKIPBODY              = 1 << 6
+  , F_CONTENTLENGTH         = 1 << 7
+  };
+
+
+/* Map for errno-related constants
+ *
+ * The provided argument should be a macro that takes 2 arguments.
+ */
+#define HTTP_ERRNO_MAP(XX)                                           \
+  /* No error */                                                     \
+  XX(OK, "success")                                                  \
+                                                                     \
+  /* Callback-related errors */                                      \
+  XX(CB_message_begin, "the on_message_begin callback failed")       \
+  XX(CB_url, "the on_url callback failed")                           \
+  XX(CB_header_field, "the on_header_field callback failed")         \
+  XX(CB_header_value, "the on_header_value callback failed")         \
+  XX(CB_headers_complete, "the on_headers_complete callback failed") \
+  XX(CB_body, "the on_body callback failed")                         \
+  XX(CB_message_complete, "the on_message_complete callback failed") \
+  XX(CB_status, "the on_status callback failed")                     \
+  XX(CB_chunk_header, "the on_chunk_header callback failed")         \
+  XX(CB_chunk_complete, "the on_chunk_complete callback failed")     \
+                                                                     \
+  /* Parsing-related errors */                                       \
+  XX(INVALID_EOF_STATE, "stream ended at an unexpected time")        \
+  XX(HEADER_OVERFLOW,                                                \
+     "too many header bytes seen; overflow detected")                \
+  XX(CLOSED_CONNECTION,                                              \
+     "data received after completed connection: close message")      \
+  XX(INVALID_VERSION, "invalid HTTP version")                        \
+  XX(INVALID_STATUS, "invalid HTTP status code")                     \
+  XX(INVALID_METHOD, "invalid HTTP method")                          \
+  XX(INVALID_URL, "invalid URL")                                     \
+  XX(INVALID_HOST, "invalid host")                                   \
+  XX(INVALID_PORT, "invalid port")                                   \
+  XX(INVALID_PATH, "invalid path")                                   \
+  XX(INVALID_QUERY_STRING, "invalid query string")                   \
+  XX(INVALID_FRAGMENT, "invalid fragment")                           \
+  XX(LF_EXPECTED, "LF character expected")                           \
+  XX(INVALID_HEADER_TOKEN, "invalid character in header")            \
+  XX(INVALID_CONTENT_LENGTH,                                         \
+     "invalid character in content-length header")                   \
+  XX(UNEXPECTED_CONTENT_LENGTH,                                      \
+     "unexpected content-length header")                             \
+  XX(INVALID_CHUNK_SIZE,                                             \
+     "invalid character in chunk size header")                       \
+  XX(INVALID_CONSTANT, "invalid constant string")                    \
+  XX(INVALID_INTERNAL_STATE, "encountered unexpected internal state")\
+  XX(STRICT, "strict mode assertion failed")                         \
+  XX(PAUSED, "parser is paused")                                     \
+  XX(UNKNOWN, "an unknown error occurred")
+
+
+/* Define HPE_* values for each errno value above */
+#define HTTP_ERRNO_GEN(n, s) HPE_##n,
+enum http_errno {
+  HTTP_ERRNO_MAP(HTTP_ERRNO_GEN)
+};
+#undef HTTP_ERRNO_GEN
+
+
+/* Get an http_errno value from an http_parser */
+#define HTTP_PARSER_ERRNO(p)            ((enum http_errno) (p)->http_errno)
+
+
+struct http_parser {
+  /** PRIVATE **/
+  unsigned int type : 2;         /* enum http_parser_type */
+  unsigned int flags : 8;        /* F_* values from 'flags' enum; semi-public */
+  unsigned int state : 7;        /* enum state from http_parser.c */
+  unsigned int header_state : 7; /* enum header_state from http_parser.c */
+  unsigned int index : 7;        /* index into current matcher */
+  unsigned int lenient_http_headers : 1;
+
+  uint32_t nread;          /* # bytes read in various scenarios */
+  uint64_t content_length; /* # bytes in body (0 if no Content-Length header) */
+
+  /** READ-ONLY **/
+  unsigned short http_major;
+  unsigned short http_minor;
+  unsigned int status_code : 16; /* responses only */
+  unsigned int method : 8;       /* requests only */
+  unsigned int http_errno : 7;
+
+  /* 1 = Upgrade header was present and the parser has exited because of that.
+   * 0 = No upgrade header present.
+   * Should be checked when http_parser_execute() returns in addition to
+   * error checking.
+   */
+  unsigned int upgrade : 1;
+
+  /** PUBLIC **/
+  void *data; /* A pointer to get hook to the "connection" or "socket" object */
+};
+
+
+struct http_parser_settings {
+  http_cb      on_message_begin;
+  http_data_cb on_url;
+  http_data_cb on_status;
+  http_data_cb on_header_field;
+  http_data_cb on_header_value;
+  http_cb      on_headers_complete;
+  http_data_cb on_body;
+  http_cb      on_message_complete;
+  /* When on_chunk_header is called, the current chunk length is stored
+   * in parser->content_length.
+   */
+  http_cb      on_chunk_header;
+  http_cb      on_chunk_complete;
+};
+
+
+enum http_parser_url_fields
+  { UF_SCHEMA           = 0
+  , UF_HOST             = 1
+  , UF_PORT             = 2
+  , UF_PATH             = 3
+  , UF_QUERY            = 4
+  , UF_FRAGMENT         = 5
+  , UF_USERINFO         = 6
+  , UF_MAX              = 7
+  };
+
+
+/* Result structure for http_parser_parse_url().
+ *
+ * Callers should index into field_data[] with UF_* values iff field_set
+ * has the relevant (1 << UF_*) bit set. As a courtesy to clients (and
+ * because we probably have padding left over), we convert any port to
+ * a uint16_t.
+ */
+struct http_parser_url {
+  uint16_t field_set;           /* Bitmask of (1 << UF_*) values */
+  uint16_t port;                /* Converted UF_PORT string */
+
+  struct {
+    uint16_t off;               /* Offset into buffer in which field starts */
+    uint16_t len;               /* Length of run in buffer */
+  } field_data[UF_MAX];
+};
+
+
+/* Returns the library version. Bits 16-23 contain the major version number,
+ * bits 8-15 the minor version number and bits 0-7 the patch level.
+ * Usage example:
+ *
+ *   unsigned long version = http_parser_version();
+ *   unsigned major = (version >> 16) & 255;
+ *   unsigned minor = (version >> 8) & 255;
+ *   unsigned patch = version & 255;
+ *   printf("http_parser v%u.%u.%u\n", major, minor, patch);
+ */
+unsigned long http_parser_version(void);
+
+void http_parser_init(http_parser *parser, enum http_parser_type type);
+
+
+/* Initialize http_parser_settings members to 0
+ */
+void http_parser_settings_init(http_parser_settings *settings);
+
+
+/* Executes the parser. Returns number of parsed bytes. Sets
+ * `parser->http_errno` on error. */
+size_t http_parser_execute(http_parser *parser,
+                           const http_parser_settings *settings,
+                           const char *data,
+                           size_t len);
+
+
+/* If http_should_keep_alive() in the on_headers_complete or
+ * on_message_complete callback returns 0, then this should be
+ * the last message on the connection.
+ * If you are the server, respond with the "Connection: close" header.
+ * If you are the client, close the connection.
+ */
+int http_should_keep_alive(const http_parser *parser);
+
+/* Returns a string version of the HTTP method. */
+const char *http_method_str(enum http_method m);
+
+/* Return a string name of the given error */
+const char *http_errno_name(enum http_errno err);
+
+/* Return a string description of the given error */
+const char *http_errno_description(enum http_errno err);
+
+/* Initialize all http_parser_url members to 0 */
+void http_parser_url_init(struct http_parser_url *u);
+
+/* Parse a URL; return nonzero on failure */
+int http_parser_parse_url(const char *buf, size_t buflen,
+                          int is_connect,
+                          struct http_parser_url *u);
+
+/* Pause or un-pause the parser; a nonzero value pauses */
+void http_parser_pause(http_parser *parser, int paused);
+
+/* Checks if this is the final chunk of the body. */
+int http_body_is_final(const http_parser *parser);
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/tools/sdk/include/nghttp/nghttp2/nghttp2.h b/tools/sdk/include/nghttp/nghttp2/nghttp2.h
new file mode 100644
index 00000000..0ed36051
--- /dev/null
+++ b/tools/sdk/include/nghttp/nghttp2/nghttp2.h
@@ -0,0 +1,5030 @@
+/*
+ * nghttp2 - HTTP/2 C Library
+ *
+ * Copyright (c) 2013, 2014 Tatsuhiro Tsujikawa
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NGHTTP2_H
+#define NGHTTP2_H
+
+/* Define WIN32 when build target is Win32 API (borrowed from
+   libcurl) */
+#if (defined(_WIN32) || defined(__WIN32__)) && !defined(WIN32)
+#define WIN32
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include 
+#if defined(_MSC_VER) && (_MSC_VER < 1800)
+/* MSVC < 2013 does not have inttypes.h because it is not C99
+   compliant.  See compiler macros and version number in
+   https://sourceforge.net/p/predef/wiki/Compilers/ */
+#include 
+#else /* !defined(_MSC_VER) || (_MSC_VER >= 1800) */
+#include 
+#endif /* !defined(_MSC_VER) || (_MSC_VER >= 1800) */
+#include 
+
+#include 
+
+#ifdef NGHTTP2_STATICLIB
+#define NGHTTP2_EXTERN
+#elif defined(WIN32)
+#ifdef BUILDING_NGHTTP2
+#define NGHTTP2_EXTERN __declspec(dllexport)
+#else /* !BUILDING_NGHTTP2 */
+#define NGHTTP2_EXTERN __declspec(dllimport)
+#endif /* !BUILDING_NGHTTP2 */
+#else  /* !defined(WIN32) */
+#ifdef BUILDING_NGHTTP2
+#define NGHTTP2_EXTERN __attribute__((visibility("default")))
+#else /* !BUILDING_NGHTTP2 */
+#define NGHTTP2_EXTERN
+#endif /* !BUILDING_NGHTTP2 */
+#endif /* !defined(WIN32) */
+
+/**
+ * @macro
+ *
+ * The protocol version identification string of this library
+ * supports.  This identifier is used if HTTP/2 is used over TLS.
+ */
+#define NGHTTP2_PROTO_VERSION_ID "h2"
+/**
+ * @macro
+ *
+ * The length of :macro:`NGHTTP2_PROTO_VERSION_ID`.
+ */
+#define NGHTTP2_PROTO_VERSION_ID_LEN 2
+
+/**
+ * @macro
+ *
+ * The serialized form of ALPN protocol identifier this library
+ * supports.  Notice that first byte is the length of following
+ * protocol identifier.  This is the same wire format of `TLS ALPN
+ * extension `_.  This is useful
+ * to process incoming ALPN tokens in wire format.
+ */
+#define NGHTTP2_PROTO_ALPN "\x2h2"
+
+/**
+ * @macro
+ *
+ * The length of :macro:`NGHTTP2_PROTO_ALPN`.
+ */
+#define NGHTTP2_PROTO_ALPN_LEN (sizeof(NGHTTP2_PROTO_ALPN) - 1)
+
+/**
+ * @macro
+ *
+ * The protocol version identification string of this library
+ * supports.  This identifier is used if HTTP/2 is used over cleartext
+ * TCP.
+ */
+#define NGHTTP2_CLEARTEXT_PROTO_VERSION_ID "h2c"
+
+/**
+ * @macro
+ *
+ * The length of :macro:`NGHTTP2_CLEARTEXT_PROTO_VERSION_ID`.
+ */
+#define NGHTTP2_CLEARTEXT_PROTO_VERSION_ID_LEN 3
+
+struct nghttp2_session;
+/**
+ * @struct
+ *
+ * The primary structure to hold the resources needed for a HTTP/2
+ * session.  The details of this structure are intentionally hidden
+ * from the public API.
+ */
+typedef struct nghttp2_session nghttp2_session;
+
+/**
+ * @macro
+ *
+ * The age of :type:`nghttp2_info`
+ */
+#define NGHTTP2_VERSION_AGE 1
+
+/**
+ * @struct
+ *
+ * This struct is what `nghttp2_version()` returns.  It holds
+ * information about the particular nghttp2 version.
+ */
+typedef struct {
+  /**
+   * Age of this struct.  This instance of nghttp2 sets it to
+   * :macro:`NGHTTP2_VERSION_AGE` but a future version may bump it and
+   * add more struct fields at the bottom
+   */
+  int age;
+  /**
+   * the :macro:`NGHTTP2_VERSION_NUM` number (since age ==1)
+   */
+  int version_num;
+  /**
+   * points to the :macro:`NGHTTP2_VERSION` string (since age ==1)
+   */
+  const char *version_str;
+  /**
+   * points to the :macro:`NGHTTP2_PROTO_VERSION_ID` string this
+   * instance implements (since age ==1)
+   */
+  const char *proto_str;
+  /* -------- the above fields all exist when age == 1 */
+} nghttp2_info;
+
+/**
+ * @macro
+ *
+ * The default weight of stream dependency.
+ */
+#define NGHTTP2_DEFAULT_WEIGHT 16
+
+/**
+ * @macro
+ *
+ * The maximum weight of stream dependency.
+ */
+#define NGHTTP2_MAX_WEIGHT 256
+
+/**
+ * @macro
+ *
+ * The minimum weight of stream dependency.
+ */
+#define NGHTTP2_MIN_WEIGHT 1
+
+/**
+ * @macro
+ *
+ * The maximum window size
+ */
+#define NGHTTP2_MAX_WINDOW_SIZE ((int32_t)((1U << 31) - 1))
+
+/**
+ * @macro
+ *
+ * The initial window size for stream level flow control.
+ */
+#define NGHTTP2_INITIAL_WINDOW_SIZE ((1 << 16) - 1)
+/**
+ * @macro
+ *
+ * The initial window size for connection level flow control.
+ */
+#define NGHTTP2_INITIAL_CONNECTION_WINDOW_SIZE ((1 << 16) - 1)
+
+/**
+ * @macro
+ *
+ * The default header table size.
+ */
+#define NGHTTP2_DEFAULT_HEADER_TABLE_SIZE (1 << 12)
+
+/**
+ * @macro
+ *
+ * The client magic string, which is the first 24 bytes byte string of
+ * client connection preface.
+ */
+#define NGHTTP2_CLIENT_MAGIC "PRI * HTTP/2.0\r\n\r\nSM\r\n\r\n"
+
+/**
+ * @macro
+ *
+ * The length of :macro:`NGHTTP2_CLIENT_MAGIC`.
+ */
+#define NGHTTP2_CLIENT_MAGIC_LEN 24
+
+/**
+ * @enum
+ *
+ * Error codes used in this library.  The code range is [-999, -500],
+ * inclusive. The following values are defined:
+ */
+typedef enum {
+  /**
+   * Invalid argument passed.
+   */
+  NGHTTP2_ERR_INVALID_ARGUMENT = -501,
+  /**
+   * Out of buffer space.
+   */
+  NGHTTP2_ERR_BUFFER_ERROR = -502,
+  /**
+   * The specified protocol version is not supported.
+   */
+  NGHTTP2_ERR_UNSUPPORTED_VERSION = -503,
+  /**
+   * Used as a return value from :type:`nghttp2_send_callback`,
+   * :type:`nghttp2_recv_callback` and
+   * :type:`nghttp2_send_data_callback` to indicate that the operation
+   * would block.
+   */
+  NGHTTP2_ERR_WOULDBLOCK = -504,
+  /**
+   * General protocol error
+   */
+  NGHTTP2_ERR_PROTO = -505,
+  /**
+   * The frame is invalid.
+   */
+  NGHTTP2_ERR_INVALID_FRAME = -506,
+  /**
+   * The peer performed a shutdown on the connection.
+   */
+  NGHTTP2_ERR_EOF = -507,
+  /**
+   * Used as a return value from
+   * :func:`nghttp2_data_source_read_callback` to indicate that data
+   * transfer is postponed.  See
+   * :func:`nghttp2_data_source_read_callback` for details.
+   */
+  NGHTTP2_ERR_DEFERRED = -508,
+  /**
+   * Stream ID has reached the maximum value.  Therefore no stream ID
+   * is available.
+   */
+  NGHTTP2_ERR_STREAM_ID_NOT_AVAILABLE = -509,
+  /**
+   * The stream is already closed; or the stream ID is invalid.
+   */
+  NGHTTP2_ERR_STREAM_CLOSED = -510,
+  /**
+   * RST_STREAM has been added to the outbound queue.  The stream is
+   * in closing state.
+   */
+  NGHTTP2_ERR_STREAM_CLOSING = -511,
+  /**
+   * The transmission is not allowed for this stream (e.g., a frame
+   * with END_STREAM flag set has already sent).
+   */
+  NGHTTP2_ERR_STREAM_SHUT_WR = -512,
+  /**
+   * The stream ID is invalid.
+   */
+  NGHTTP2_ERR_INVALID_STREAM_ID = -513,
+  /**
+   * The state of the stream is not valid (e.g., DATA cannot be sent
+   * to the stream if response HEADERS has not been sent).
+   */
+  NGHTTP2_ERR_INVALID_STREAM_STATE = -514,
+  /**
+   * Another DATA frame has already been deferred.
+   */
+  NGHTTP2_ERR_DEFERRED_DATA_EXIST = -515,
+  /**
+   * Starting new stream is not allowed (e.g., GOAWAY has been sent
+   * and/or received).
+   */
+  NGHTTP2_ERR_START_STREAM_NOT_ALLOWED = -516,
+  /**
+   * GOAWAY has already been sent.
+   */
+  NGHTTP2_ERR_GOAWAY_ALREADY_SENT = -517,
+  /**
+   * The received frame contains the invalid header block (e.g., There
+   * are duplicate header names; or the header names are not encoded
+   * in US-ASCII character set and not lower cased; or the header name
+   * is zero-length string; or the header value contains multiple
+   * in-sequence NUL bytes).
+   */
+  NGHTTP2_ERR_INVALID_HEADER_BLOCK = -518,
+  /**
+   * Indicates that the context is not suitable to perform the
+   * requested operation.
+   */
+  NGHTTP2_ERR_INVALID_STATE = -519,
+  /**
+   * The user callback function failed due to the temporal error.
+   */
+  NGHTTP2_ERR_TEMPORAL_CALLBACK_FAILURE = -521,
+  /**
+   * The length of the frame is invalid, either too large or too small.
+   */
+  NGHTTP2_ERR_FRAME_SIZE_ERROR = -522,
+  /**
+   * Header block inflate/deflate error.
+   */
+  NGHTTP2_ERR_HEADER_COMP = -523,
+  /**
+   * Flow control error
+   */
+  NGHTTP2_ERR_FLOW_CONTROL = -524,
+  /**
+   * Insufficient buffer size given to function.
+   */
+  NGHTTP2_ERR_INSUFF_BUFSIZE = -525,
+  /**
+   * Callback was paused by the application
+   */
+  NGHTTP2_ERR_PAUSE = -526,
+  /**
+   * There are too many in-flight SETTING frame and no more
+   * transmission of SETTINGS is allowed.
+   */
+  NGHTTP2_ERR_TOO_MANY_INFLIGHT_SETTINGS = -527,
+  /**
+   * The server push is disabled.
+   */
+  NGHTTP2_ERR_PUSH_DISABLED = -528,
+  /**
+   * DATA or HEADERS frame for a given stream has been already
+   * submitted and has not been fully processed yet.  Application
+   * should wait for the transmission of the previously submitted
+   * frame before submitting another.
+   */
+  NGHTTP2_ERR_DATA_EXIST = -529,
+  /**
+   * The current session is closing due to a connection error or
+   * `nghttp2_session_terminate_session()` is called.
+   */
+  NGHTTP2_ERR_SESSION_CLOSING = -530,
+  /**
+   * Invalid HTTP header field was received and stream is going to be
+   * closed.
+   */
+  NGHTTP2_ERR_HTTP_HEADER = -531,
+  /**
+   * Violation in HTTP messaging rule.
+   */
+  NGHTTP2_ERR_HTTP_MESSAGING = -532,
+  /**
+   * Stream was refused.
+   */
+  NGHTTP2_ERR_REFUSED_STREAM = -533,
+  /**
+   * Unexpected internal error, but recovered.
+   */
+  NGHTTP2_ERR_INTERNAL = -534,
+  /**
+   * Indicates that a processing was canceled.
+   */
+  NGHTTP2_ERR_CANCEL = -535,
+  /**
+   * The errors < :enum:`NGHTTP2_ERR_FATAL` mean that the library is
+   * under unexpected condition and processing was terminated (e.g.,
+   * out of memory).  If application receives this error code, it must
+   * stop using that :type:`nghttp2_session` object and only allowed
+   * operation for that object is deallocate it using
+   * `nghttp2_session_del()`.
+   */
+  NGHTTP2_ERR_FATAL = -900,
+  /**
+   * Out of memory.  This is a fatal error.
+   */
+  NGHTTP2_ERR_NOMEM = -901,
+  /**
+   * The user callback function failed.  This is a fatal error.
+   */
+  NGHTTP2_ERR_CALLBACK_FAILURE = -902,
+  /**
+   * Invalid client magic (see :macro:`NGHTTP2_CLIENT_MAGIC`) was
+   * received and further processing is not possible.
+   */
+  NGHTTP2_ERR_BAD_CLIENT_MAGIC = -903,
+  /**
+   * Possible flooding by peer was detected in this HTTP/2 session.
+   * Flooding is measured by how many PING and SETTINGS frames with
+   * ACK flag set are queued for transmission.  These frames are
+   * response for the peer initiated frames, and peer can cause memory
+   * exhaustion on server side to send these frames forever and does
+   * not read network.
+   */
+  NGHTTP2_ERR_FLOODED = -904
+} nghttp2_error;
+
+/**
+ * @struct
+ *
+ * The object representing single contiguous buffer.
+ */
+typedef struct {
+  /**
+   * The pointer to the buffer.
+   */
+  uint8_t *base;
+  /**
+   * The length of the buffer.
+   */
+  size_t len;
+} nghttp2_vec;
+
+struct nghttp2_rcbuf;
+
+/**
+ * @struct
+ *
+ * The object representing reference counted buffer.  The details of
+ * this structure are intentionally hidden from the public API.
+ */
+typedef struct nghttp2_rcbuf nghttp2_rcbuf;
+
+/**
+ * @function
+ *
+ * Increments the reference count of |rcbuf| by 1.
+ */
+NGHTTP2_EXTERN void nghttp2_rcbuf_incref(nghttp2_rcbuf *rcbuf);
+
+/**
+ * @function
+ *
+ * Decrements the reference count of |rcbuf| by 1.  If the reference
+ * count becomes zero, the object pointed by |rcbuf| will be freed.
+ * In this case, application must not use |rcbuf| again.
+ */
+NGHTTP2_EXTERN void nghttp2_rcbuf_decref(nghttp2_rcbuf *rcbuf);
+
+/**
+ * @function
+ *
+ * Returns the underlying buffer managed by |rcbuf|.
+ */
+NGHTTP2_EXTERN nghttp2_vec nghttp2_rcbuf_get_buf(nghttp2_rcbuf *rcbuf);
+
+/**
+ * @enum
+ *
+ * The flags for header field name/value pair.
+ */
+typedef enum {
+  /**
+   * No flag set.
+   */
+  NGHTTP2_NV_FLAG_NONE = 0,
+  /**
+   * Indicates that this name/value pair must not be indexed ("Literal
+   * Header Field never Indexed" representation must be used in HPACK
+   * encoding).  Other implementation calls this bit as "sensitive".
+   */
+  NGHTTP2_NV_FLAG_NO_INDEX = 0x01,
+  /**
+   * This flag is set solely by application.  If this flag is set, the
+   * library does not make a copy of header field name.  This could
+   * improve performance.
+   */
+  NGHTTP2_NV_FLAG_NO_COPY_NAME = 0x02,
+  /**
+   * This flag is set solely by application.  If this flag is set, the
+   * library does not make a copy of header field value.  This could
+   * improve performance.
+   */
+  NGHTTP2_NV_FLAG_NO_COPY_VALUE = 0x04
+} nghttp2_nv_flag;
+
+/**
+ * @struct
+ *
+ * The name/value pair, which mainly used to represent header fields.
+ */
+typedef struct {
+  /**
+   * The |name| byte string.  If this struct is presented from library
+   * (e.g., :type:`nghttp2_on_frame_recv_callback`), |name| is
+   * guaranteed to be NULL-terminated.  For some callbacks
+   * (:type:`nghttp2_before_frame_send_callback`,
+   * :type:`nghttp2_on_frame_send_callback`, and
+   * :type:`nghttp2_on_frame_not_send_callback`), it may not be
+   * NULL-terminated if header field is passed from application with
+   * the flag :enum:`NGHTTP2_NV_FLAG_NO_COPY_NAME`).  When application
+   * is constructing this struct, |name| is not required to be
+   * NULL-terminated.
+   */
+  uint8_t *name;
+  /**
+   * The |value| byte string.  If this struct is presented from
+   * library (e.g., :type:`nghttp2_on_frame_recv_callback`), |value|
+   * is guaranteed to be NULL-terminated.  For some callbacks
+   * (:type:`nghttp2_before_frame_send_callback`,
+   * :type:`nghttp2_on_frame_send_callback`, and
+   * :type:`nghttp2_on_frame_not_send_callback`), it may not be
+   * NULL-terminated if header field is passed from application with
+   * the flag :enum:`NGHTTP2_NV_FLAG_NO_COPY_VALUE`).  When
+   * application is constructing this struct, |value| is not required
+   * to be NULL-terminated.
+   */
+  uint8_t *value;
+  /**
+   * The length of the |name|, excluding terminating NULL.
+   */
+  size_t namelen;
+  /**
+   * The length of the |value|, excluding terminating NULL.
+   */
+  size_t valuelen;
+  /**
+   * Bitwise OR of one or more of :type:`nghttp2_nv_flag`.
+   */
+  uint8_t flags;
+} nghttp2_nv;
+
+/**
+ * @enum
+ *
+ * The frame types in HTTP/2 specification.
+ */
+typedef enum {
+  /**
+   * The DATA frame.
+   */
+  NGHTTP2_DATA = 0,
+  /**
+   * The HEADERS frame.
+   */
+  NGHTTP2_HEADERS = 0x01,
+  /**
+   * The PRIORITY frame.
+   */
+  NGHTTP2_PRIORITY = 0x02,
+  /**
+   * The RST_STREAM frame.
+   */
+  NGHTTP2_RST_STREAM = 0x03,
+  /**
+   * The SETTINGS frame.
+   */
+  NGHTTP2_SETTINGS = 0x04,
+  /**
+   * The PUSH_PROMISE frame.
+   */
+  NGHTTP2_PUSH_PROMISE = 0x05,
+  /**
+   * The PING frame.
+   */
+  NGHTTP2_PING = 0x06,
+  /**
+   * The GOAWAY frame.
+   */
+  NGHTTP2_GOAWAY = 0x07,
+  /**
+   * The WINDOW_UPDATE frame.
+   */
+  NGHTTP2_WINDOW_UPDATE = 0x08,
+  /**
+   * The CONTINUATION frame.  This frame type won't be passed to any
+   * callbacks because the library processes this frame type and its
+   * preceding HEADERS/PUSH_PROMISE as a single frame.
+   */
+  NGHTTP2_CONTINUATION = 0x09,
+  /**
+   * The ALTSVC frame, which is defined in `RFC 7383
+   * `_.
+   */
+  NGHTTP2_ALTSVC = 0x0a
+} nghttp2_frame_type;
+
+/**
+ * @enum
+ *
+ * The flags for HTTP/2 frames.  This enum defines all flags for all
+ * frames.
+ */
+typedef enum {
+  /**
+   * No flag set.
+   */
+  NGHTTP2_FLAG_NONE = 0,
+  /**
+   * The END_STREAM flag.
+   */
+  NGHTTP2_FLAG_END_STREAM = 0x01,
+  /**
+   * The END_HEADERS flag.
+   */
+  NGHTTP2_FLAG_END_HEADERS = 0x04,
+  /**
+   * The ACK flag.
+   */
+  NGHTTP2_FLAG_ACK = 0x01,
+  /**
+   * The PADDED flag.
+   */
+  NGHTTP2_FLAG_PADDED = 0x08,
+  /**
+   * The PRIORITY flag.
+   */
+  NGHTTP2_FLAG_PRIORITY = 0x20
+} nghttp2_flag;
+
+/**
+ * @enum
+ * The SETTINGS ID.
+ */
+typedef enum {
+  /**
+   * SETTINGS_HEADER_TABLE_SIZE
+   */
+  NGHTTP2_SETTINGS_HEADER_TABLE_SIZE = 0x01,
+  /**
+   * SETTINGS_ENABLE_PUSH
+   */
+  NGHTTP2_SETTINGS_ENABLE_PUSH = 0x02,
+  /**
+   * SETTINGS_MAX_CONCURRENT_STREAMS
+   */
+  NGHTTP2_SETTINGS_MAX_CONCURRENT_STREAMS = 0x03,
+  /**
+   * SETTINGS_INITIAL_WINDOW_SIZE
+   */
+  NGHTTP2_SETTINGS_INITIAL_WINDOW_SIZE = 0x04,
+  /**
+   * SETTINGS_MAX_FRAME_SIZE
+   */
+  NGHTTP2_SETTINGS_MAX_FRAME_SIZE = 0x05,
+  /**
+   * SETTINGS_MAX_HEADER_LIST_SIZE
+   */
+  NGHTTP2_SETTINGS_MAX_HEADER_LIST_SIZE = 0x06
+} nghttp2_settings_id;
+/* Note: If we add SETTINGS, update the capacity of
+   NGHTTP2_INBOUND_NUM_IV as well */
+
+/**
+ * @macro
+ *
+ * .. warning::
+ *
+ *   Deprecated.  The initial max concurrent streams is 0xffffffffu.
+ *
+ * Default maximum number of incoming concurrent streams.  Use
+ * `nghttp2_submit_settings()` with
+ * :enum:`NGHTTP2_SETTINGS_MAX_CONCURRENT_STREAMS` to change the
+ * maximum number of incoming concurrent streams.
+ *
+ * .. note::
+ *
+ *   The maximum number of outgoing concurrent streams is 100 by
+ *   default.
+ */
+#define NGHTTP2_INITIAL_MAX_CONCURRENT_STREAMS ((1U << 31) - 1)
+
+/**
+ * @enum
+ * The status codes for the RST_STREAM and GOAWAY frames.
+ */
+typedef enum {
+  /**
+   * No errors.
+   */
+  NGHTTP2_NO_ERROR = 0x00,
+  /**
+   * PROTOCOL_ERROR
+   */
+  NGHTTP2_PROTOCOL_ERROR = 0x01,
+  /**
+   * INTERNAL_ERROR
+   */
+  NGHTTP2_INTERNAL_ERROR = 0x02,
+  /**
+   * FLOW_CONTROL_ERROR
+   */
+  NGHTTP2_FLOW_CONTROL_ERROR = 0x03,
+  /**
+   * SETTINGS_TIMEOUT
+   */
+  NGHTTP2_SETTINGS_TIMEOUT = 0x04,
+  /**
+   * STREAM_CLOSED
+   */
+  NGHTTP2_STREAM_CLOSED = 0x05,
+  /**
+   * FRAME_SIZE_ERROR
+   */
+  NGHTTP2_FRAME_SIZE_ERROR = 0x06,
+  /**
+   * REFUSED_STREAM
+   */
+  NGHTTP2_REFUSED_STREAM = 0x07,
+  /**
+   * CANCEL
+   */
+  NGHTTP2_CANCEL = 0x08,
+  /**
+   * COMPRESSION_ERROR
+   */
+  NGHTTP2_COMPRESSION_ERROR = 0x09,
+  /**
+   * CONNECT_ERROR
+   */
+  NGHTTP2_CONNECT_ERROR = 0x0a,
+  /**
+   * ENHANCE_YOUR_CALM
+   */
+  NGHTTP2_ENHANCE_YOUR_CALM = 0x0b,
+  /**
+   * INADEQUATE_SECURITY
+   */
+  NGHTTP2_INADEQUATE_SECURITY = 0x0c,
+  /**
+   * HTTP_1_1_REQUIRED
+   */
+  NGHTTP2_HTTP_1_1_REQUIRED = 0x0d
+} nghttp2_error_code;
+
+/**
+ * @struct
+ * The frame header.
+ */
+typedef struct {
+  /**
+   * The length field of this frame, excluding frame header.
+   */
+  size_t length;
+  /**
+   * The stream identifier (aka, stream ID)
+   */
+  int32_t stream_id;
+  /**
+   * The type of this frame.  See `nghttp2_frame_type`.
+   */
+  uint8_t type;
+  /**
+   * The flags.
+   */
+  uint8_t flags;
+  /**
+   * Reserved bit in frame header.  Currently, this is always set to 0
+   * and application should not expect something useful in here.
+   */
+  uint8_t reserved;
+} nghttp2_frame_hd;
+
+/**
+ * @union
+ *
+ * This union represents the some kind of data source passed to
+ * :type:`nghttp2_data_source_read_callback`.
+ */
+typedef union {
+  /**
+   * The integer field, suitable for a file descriptor.
+   */
+  int fd;
+  /**
+   * The pointer to an arbitrary object.
+   */
+  void *ptr;
+} nghttp2_data_source;
+
+/**
+ * @enum
+ *
+ * The flags used to set in |data_flags| output parameter in
+ * :type:`nghttp2_data_source_read_callback`.
+ */
+typedef enum {
+  /**
+   * No flag set.
+   */
+  NGHTTP2_DATA_FLAG_NONE = 0,
+  /**
+   * Indicates EOF was sensed.
+   */
+  NGHTTP2_DATA_FLAG_EOF = 0x01,
+  /**
+   * Indicates that END_STREAM flag must not be set even if
+   * NGHTTP2_DATA_FLAG_EOF is set.  Usually this flag is used to send
+   * trailer fields with `nghttp2_submit_request()` or
+   * `nghttp2_submit_response()`.
+   */
+  NGHTTP2_DATA_FLAG_NO_END_STREAM = 0x02,
+  /**
+   * Indicates that application will send complete DATA frame in
+   * :type:`nghttp2_send_data_callback`.
+   */
+  NGHTTP2_DATA_FLAG_NO_COPY = 0x04
+} nghttp2_data_flag;
+
+/**
+ * @functypedef
+ *
+ * Callback function invoked when the library wants to read data from
+ * the |source|.  The read data is sent in the stream |stream_id|.
+ * The implementation of this function must read at most |length|
+ * bytes of data from |source| (or possibly other places) and store
+ * them in |buf| and return number of data stored in |buf|.  If EOF is
+ * reached, set :enum:`NGHTTP2_DATA_FLAG_EOF` flag in |*data_flags|.
+ *
+ * Sometime it is desirable to avoid copying data into |buf| and let
+ * application to send data directly.  To achieve this, set
+ * :enum:`NGHTTP2_DATA_FLAG_NO_COPY` to |*data_flags| (and possibly
+ * other flags, just like when we do copy), and return the number of
+ * bytes to send without copying data into |buf|.  The library, seeing
+ * :enum:`NGHTTP2_DATA_FLAG_NO_COPY`, will invoke
+ * :type:`nghttp2_send_data_callback`.  The application must send
+ * complete DATA frame in that callback.
+ *
+ * If this callback is set by `nghttp2_submit_request()`,
+ * `nghttp2_submit_response()` or `nghttp2_submit_headers()` and
+ * `nghttp2_submit_data()` with flag parameter
+ * :enum:`NGHTTP2_FLAG_END_STREAM` set, and
+ * :enum:`NGHTTP2_DATA_FLAG_EOF` flag is set to |*data_flags|, DATA
+ * frame will have END_STREAM flag set.  Usually, this is expected
+ * behaviour and all are fine.  One exception is send trailer fields.
+ * You cannot send trailer fields after sending frame with END_STREAM
+ * set.  To avoid this problem, one can set
+ * :enum:`NGHTTP2_DATA_FLAG_NO_END_STREAM` along with
+ * :enum:`NGHTTP2_DATA_FLAG_EOF` to signal the library not to set
+ * END_STREAM in DATA frame.  Then application can use
+ * `nghttp2_submit_trailer()` to send trailer fields.
+ * `nghttp2_submit_trailer()` can be called inside this callback.
+ *
+ * If the application wants to postpone DATA frames (e.g.,
+ * asynchronous I/O, or reading data blocks for long time), it is
+ * achieved by returning :enum:`NGHTTP2_ERR_DEFERRED` without reading
+ * any data in this invocation.  The library removes DATA frame from
+ * the outgoing queue temporarily.  To move back deferred DATA frame
+ * to outgoing queue, call `nghttp2_session_resume_data()`.  In case
+ * of error, there are 2 choices. Returning
+ * :enum:`NGHTTP2_ERR_TEMPORAL_CALLBACK_FAILURE` will close the stream
+ * by issuing RST_STREAM with :enum:`NGHTTP2_INTERNAL_ERROR`.  If a
+ * different error code is desirable, use
+ * `nghttp2_submit_rst_stream()` with a desired error code and then
+ * return :enum:`NGHTTP2_ERR_TEMPORAL_CALLBACK_FAILURE`.  Returning
+ * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE` will signal the entire session
+ * failure.
+ */
+typedef ssize_t (*nghttp2_data_source_read_callback)(
+    nghttp2_session *session, int32_t stream_id, uint8_t *buf, size_t length,
+    uint32_t *data_flags, nghttp2_data_source *source, void *user_data);
+
+/**
+ * @struct
+ *
+ * This struct represents the data source and the way to read a chunk
+ * of data from it.
+ */
+typedef struct {
+  /**
+   * The data source.
+   */
+  nghttp2_data_source source;
+  /**
+   * The callback function to read a chunk of data from the |source|.
+   */
+  nghttp2_data_source_read_callback read_callback;
+} nghttp2_data_provider;
+
+/**
+ * @struct
+ *
+ * The DATA frame.  The received data is delivered via
+ * :type:`nghttp2_on_data_chunk_recv_callback`.
+ */
+typedef struct {
+  nghttp2_frame_hd hd;
+  /**
+   * The length of the padding in this frame.  This includes PAD_HIGH
+   * and PAD_LOW.
+   */
+  size_t padlen;
+} nghttp2_data;
+
+/**
+ * @enum
+ *
+ * The category of HEADERS, which indicates the role of the frame.  In
+ * HTTP/2 spec, request, response, push response and other arbitrary
+ * headers (e.g., trailer fields) are all called just HEADERS.  To
+ * give the application the role of incoming HEADERS frame, we define
+ * several categories.
+ */
+typedef enum {
+  /**
+   * The HEADERS frame is opening new stream, which is analogous to
+   * SYN_STREAM in SPDY.
+   */
+  NGHTTP2_HCAT_REQUEST = 0,
+  /**
+   * The HEADERS frame is the first response headers, which is
+   * analogous to SYN_REPLY in SPDY.
+   */
+  NGHTTP2_HCAT_RESPONSE = 1,
+  /**
+   * The HEADERS frame is the first headers sent against reserved
+   * stream.
+   */
+  NGHTTP2_HCAT_PUSH_RESPONSE = 2,
+  /**
+   * The HEADERS frame which does not apply for the above categories,
+   * which is analogous to HEADERS in SPDY.  If non-final response
+   * (e.g., status 1xx) is used, final response HEADERS frame will be
+   * categorized here.
+   */
+  NGHTTP2_HCAT_HEADERS = 3
+} nghttp2_headers_category;
+
+/**
+ * @struct
+ *
+ * The structure to specify stream dependency.
+ */
+typedef struct {
+  /**
+   * The stream ID of the stream to depend on.  Specifying 0 makes
+   * stream not depend any other stream.
+   */
+  int32_t stream_id;
+  /**
+   * The weight of this dependency.
+   */
+  int32_t weight;
+  /**
+   * nonzero means exclusive dependency
+   */
+  uint8_t exclusive;
+} nghttp2_priority_spec;
+
+/**
+ * @struct
+ *
+ * The HEADERS frame.  It has the following members:
+ */
+typedef struct {
+  /**
+   * The frame header.
+   */
+  nghttp2_frame_hd hd;
+  /**
+   * The length of the padding in this frame.  This includes PAD_HIGH
+   * and PAD_LOW.
+   */
+  size_t padlen;
+  /**
+   * The priority specification
+   */
+  nghttp2_priority_spec pri_spec;
+  /**
+   * The name/value pairs.
+   */
+  nghttp2_nv *nva;
+  /**
+   * The number of name/value pairs in |nva|.
+   */
+  size_t nvlen;
+  /**
+   * The category of this HEADERS frame.
+   */
+  nghttp2_headers_category cat;
+} nghttp2_headers;
+
+/**
+ * @struct
+ *
+ * The PRIORITY frame.  It has the following members:
+ */
+typedef struct {
+  /**
+   * The frame header.
+   */
+  nghttp2_frame_hd hd;
+  /**
+   * The priority specification.
+   */
+  nghttp2_priority_spec pri_spec;
+} nghttp2_priority;
+
+/**
+ * @struct
+ *
+ * The RST_STREAM frame.  It has the following members:
+ */
+typedef struct {
+  /**
+   * The frame header.
+   */
+  nghttp2_frame_hd hd;
+  /**
+   * The error code.  See :type:`nghttp2_error_code`.
+   */
+  uint32_t error_code;
+} nghttp2_rst_stream;
+
+/**
+ * @struct
+ *
+ * The SETTINGS ID/Value pair.  It has the following members:
+ */
+typedef struct {
+  /**
+   * The SETTINGS ID.  See :type:`nghttp2_settings_id`.
+   */
+  int32_t settings_id;
+  /**
+   * The value of this entry.
+   */
+  uint32_t value;
+} nghttp2_settings_entry;
+
+/**
+ * @struct
+ *
+ * The SETTINGS frame.  It has the following members:
+ */
+typedef struct {
+  /**
+   * The frame header.
+   */
+  nghttp2_frame_hd hd;
+  /**
+   * The number of SETTINGS ID/Value pairs in |iv|.
+   */
+  size_t niv;
+  /**
+   * The pointer to the array of SETTINGS ID/Value pair.
+   */
+  nghttp2_settings_entry *iv;
+} nghttp2_settings;
+
+/**
+ * @struct
+ *
+ * The PUSH_PROMISE frame.  It has the following members:
+ */
+typedef struct {
+  /**
+   * The frame header.
+   */
+  nghttp2_frame_hd hd;
+  /**
+   * The length of the padding in this frame.  This includes PAD_HIGH
+   * and PAD_LOW.
+   */
+  size_t padlen;
+  /**
+   * The name/value pairs.
+   */
+  nghttp2_nv *nva;
+  /**
+   * The number of name/value pairs in |nva|.
+   */
+  size_t nvlen;
+  /**
+   * The promised stream ID
+   */
+  int32_t promised_stream_id;
+  /**
+   * Reserved bit.  Currently this is always set to 0 and application
+   * should not expect something useful in here.
+   */
+  uint8_t reserved;
+} nghttp2_push_promise;
+
+/**
+ * @struct
+ *
+ * The PING frame.  It has the following members:
+ */
+typedef struct {
+  /**
+   * The frame header.
+   */
+  nghttp2_frame_hd hd;
+  /**
+   * The opaque data
+   */
+  uint8_t opaque_data[8];
+} nghttp2_ping;
+
+/**
+ * @struct
+ *
+ * The GOAWAY frame.  It has the following members:
+ */
+typedef struct {
+  /**
+   * The frame header.
+   */
+  nghttp2_frame_hd hd;
+  /**
+   * The last stream stream ID.
+   */
+  int32_t last_stream_id;
+  /**
+   * The error code.  See :type:`nghttp2_error_code`.
+   */
+  uint32_t error_code;
+  /**
+   * The additional debug data
+   */
+  uint8_t *opaque_data;
+  /**
+   * The length of |opaque_data| member.
+   */
+  size_t opaque_data_len;
+  /**
+   * Reserved bit.  Currently this is always set to 0 and application
+   * should not expect something useful in here.
+   */
+  uint8_t reserved;
+} nghttp2_goaway;
+
+/**
+ * @struct
+ *
+ * The WINDOW_UPDATE frame.  It has the following members:
+ */
+typedef struct {
+  /**
+   * The frame header.
+   */
+  nghttp2_frame_hd hd;
+  /**
+   * The window size increment.
+   */
+  int32_t window_size_increment;
+  /**
+   * Reserved bit.  Currently this is always set to 0 and application
+   * should not expect something useful in here.
+   */
+  uint8_t reserved;
+} nghttp2_window_update;
+
+/**
+ * @struct
+ *
+ * The extension frame.  It has following members:
+ */
+typedef struct {
+  /**
+   * The frame header.
+   */
+  nghttp2_frame_hd hd;
+  /**
+   * The pointer to extension payload.  The exact pointer type is
+   * determined by hd.type.
+   *
+   * Currently, no extension is supported.  This is a place holder for
+   * the future extensions.
+   */
+  void *payload;
+} nghttp2_extension;
+
+/**
+ * @union
+ *
+ * This union includes all frames to pass them to various function
+ * calls as nghttp2_frame type.  The CONTINUATION frame is omitted
+ * from here because the library deals with it internally.
+ */
+typedef union {
+  /**
+   * The frame header, which is convenient to inspect frame header.
+   */
+  nghttp2_frame_hd hd;
+  /**
+   * The DATA frame.
+   */
+  nghttp2_data data;
+  /**
+   * The HEADERS frame.
+   */
+  nghttp2_headers headers;
+  /**
+   * The PRIORITY frame.
+   */
+  nghttp2_priority priority;
+  /**
+   * The RST_STREAM frame.
+   */
+  nghttp2_rst_stream rst_stream;
+  /**
+   * The SETTINGS frame.
+   */
+  nghttp2_settings settings;
+  /**
+   * The PUSH_PROMISE frame.
+   */
+  nghttp2_push_promise push_promise;
+  /**
+   * The PING frame.
+   */
+  nghttp2_ping ping;
+  /**
+   * The GOAWAY frame.
+   */
+  nghttp2_goaway goaway;
+  /**
+   * The WINDOW_UPDATE frame.
+   */
+  nghttp2_window_update window_update;
+  /**
+   * The extension frame.
+   */
+  nghttp2_extension ext;
+} nghttp2_frame;
+
+/**
+ * @functypedef
+ *
+ * Callback function invoked when |session| wants to send data to the
+ * remote peer.  The implementation of this function must send at most
+ * |length| bytes of data stored in |data|.  The |flags| is currently
+ * not used and always 0. It must return the number of bytes sent if
+ * it succeeds.  If it cannot send any single byte without blocking,
+ * it must return :enum:`NGHTTP2_ERR_WOULDBLOCK`.  For other errors,
+ * it must return :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.  The
+ * |user_data| pointer is the third argument passed in to the call to
+ * `nghttp2_session_client_new()` or `nghttp2_session_server_new()`.
+ *
+ * This callback is required if the application uses
+ * `nghttp2_session_send()` to send data to the remote endpoint.  If
+ * the application uses solely `nghttp2_session_mem_send()` instead,
+ * this callback function is unnecessary.
+ *
+ * To set this callback to :type:`nghttp2_session_callbacks`, use
+ * `nghttp2_session_callbacks_set_send_callback()`.
+ *
+ * .. note::
+ *
+ *   The |length| may be very small.  If that is the case, and
+ *   application disables Nagle algorithm (``TCP_NODELAY``), then just
+ *   writing |data| to the network stack leads to very small packet,
+ *   and it is very inefficient.  An application should be responsible
+ *   to buffer up small chunks of data as necessary to avoid this
+ *   situation.
+ */
+typedef ssize_t (*nghttp2_send_callback)(nghttp2_session *session,
+                                         const uint8_t *data, size_t length,
+                                         int flags, void *user_data);
+
+/**
+ * @functypedef
+ *
+ * Callback function invoked when :enum:`NGHTTP2_DATA_FLAG_NO_COPY` is
+ * used in :type:`nghttp2_data_source_read_callback` to send complete
+ * DATA frame.
+ *
+ * The |frame| is a DATA frame to send.  The |framehd| is the
+ * serialized frame header (9 bytes). The |length| is the length of
+ * application data to send (this does not include padding).  The
+ * |source| is the same pointer passed to
+ * :type:`nghttp2_data_source_read_callback`.
+ *
+ * The application first must send frame header |framehd| of length 9
+ * bytes.  If ``frame->data.padlen > 0``, send 1 byte of value
+ * ``frame->data.padlen - 1``.  Then send exactly |length| bytes of
+ * application data.  Finally, if ``frame->data.padlen > 1``, send
+ * ``frame->data.padlen - 1`` bytes of zero as padding.
+ *
+ * The application has to send complete DATA frame in this callback.
+ * If all data were written successfully, return 0.
+ *
+ * If it cannot send any data at all, just return
+ * :enum:`NGHTTP2_ERR_WOULDBLOCK`; the library will call this callback
+ * with the same parameters later (It is recommended to send complete
+ * DATA frame at once in this function to deal with error; if partial
+ * frame data has already sent, it is impossible to send another data
+ * in that state, and all we can do is tear down connection).  When
+ * data is fully processed, but application wants to make
+ * `nghttp2_session_mem_send()` or `nghttp2_session_send()` return
+ * immediately without processing next frames, return
+ * :enum:`NGHTTP2_ERR_PAUSE`.  If application decided to reset this
+ * stream, return :enum:`NGHTTP2_ERR_TEMPORAL_CALLBACK_FAILURE`, then
+ * the library will send RST_STREAM with INTERNAL_ERROR as error code.
+ * The application can also return
+ * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`, which will result in
+ * connection closure.  Returning any other value is treated as
+ * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE` is returned.
+ */
+typedef int (*nghttp2_send_data_callback)(nghttp2_session *session,
+                                          nghttp2_frame *frame,
+                                          const uint8_t *framehd, size_t length,
+                                          nghttp2_data_source *source,
+                                          void *user_data);
+
+/**
+ * @functypedef
+ *
+ * Callback function invoked when |session| wants to receive data from
+ * the remote peer.  The implementation of this function must read at
+ * most |length| bytes of data and store it in |buf|.  The |flags| is
+ * currently not used and always 0.  It must return the number of
+ * bytes written in |buf| if it succeeds.  If it cannot read any
+ * single byte without blocking, it must return
+ * :enum:`NGHTTP2_ERR_WOULDBLOCK`.  If it gets EOF before it reads any
+ * single byte, it must return :enum:`NGHTTP2_ERR_EOF`.  For other
+ * errors, it must return :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.
+ * Returning 0 is treated as :enum:`NGHTTP2_ERR_WOULDBLOCK`.  The
+ * |user_data| pointer is the third argument passed in to the call to
+ * `nghttp2_session_client_new()` or `nghttp2_session_server_new()`.
+ *
+ * This callback is required if the application uses
+ * `nghttp2_session_recv()` to receive data from the remote endpoint.
+ * If the application uses solely `nghttp2_session_mem_recv()`
+ * instead, this callback function is unnecessary.
+ *
+ * To set this callback to :type:`nghttp2_session_callbacks`, use
+ * `nghttp2_session_callbacks_set_recv_callback()`.
+ */
+typedef ssize_t (*nghttp2_recv_callback)(nghttp2_session *session, uint8_t *buf,
+                                         size_t length, int flags,
+                                         void *user_data);
+
+/**
+ * @functypedef
+ *
+ * Callback function invoked by `nghttp2_session_recv()` and
+ * `nghttp2_session_mem_recv()` when a frame is received.  The
+ * |user_data| pointer is the third argument passed in to the call to
+ * `nghttp2_session_client_new()` or `nghttp2_session_server_new()`.
+ *
+ * If frame is HEADERS or PUSH_PROMISE, the ``nva`` and ``nvlen``
+ * member of their data structure are always ``NULL`` and 0
+ * respectively.  The header name/value pairs are emitted via
+ * :type:`nghttp2_on_header_callback`.
+ *
+ * For HEADERS, PUSH_PROMISE and DATA frames, this callback may be
+ * called after stream is closed (see
+ * :type:`nghttp2_on_stream_close_callback`).  The application should
+ * check that stream is still alive using its own stream management or
+ * :func:`nghttp2_session_get_stream_user_data()`.
+ *
+ * Only HEADERS and DATA frame can signal the end of incoming data.
+ * If ``frame->hd.flags & NGHTTP2_FLAG_END_STREAM`` is nonzero, the
+ * |frame| is the last frame from the remote peer in this stream.
+ *
+ * This callback won't be called for CONTINUATION frames.
+ * HEADERS/PUSH_PROMISE + CONTINUATIONs are treated as single frame.
+ *
+ * The implementation of this function must return 0 if it succeeds.
+ * If nonzero value is returned, it is treated as fatal error and
+ * `nghttp2_session_recv()` and `nghttp2_session_mem_recv()` functions
+ * immediately return :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.
+ *
+ * To set this callback to :type:`nghttp2_session_callbacks`, use
+ * `nghttp2_session_callbacks_set_on_frame_recv_callback()`.
+ */
+typedef int (*nghttp2_on_frame_recv_callback)(nghttp2_session *session,
+                                              const nghttp2_frame *frame,
+                                              void *user_data);
+
+/**
+ * @functypedef
+ *
+ * Callback function invoked by `nghttp2_session_recv()` and
+ * `nghttp2_session_mem_recv()` when an invalid non-DATA frame is
+ * received.  The error is indicated by the |lib_error_code|, which is
+ * one of the values defined in :type:`nghttp2_error`.  When this
+ * callback function is invoked, the library automatically submits
+ * either RST_STREAM or GOAWAY frame.  The |user_data| pointer is the
+ * third argument passed in to the call to
+ * `nghttp2_session_client_new()` or `nghttp2_session_server_new()`.
+ *
+ * If frame is HEADERS or PUSH_PROMISE, the ``nva`` and ``nvlen``
+ * member of their data structure are always ``NULL`` and 0
+ * respectively.
+ *
+ * The implementation of this function must return 0 if it succeeds.
+ * If nonzero is returned, it is treated as fatal error and
+ * `nghttp2_session_recv()` and `nghttp2_session_mem_recv()` functions
+ * immediately return :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.
+ *
+ * To set this callback to :type:`nghttp2_session_callbacks`, use
+ * `nghttp2_session_callbacks_set_on_invalid_frame_recv_callback()`.
+ */
+typedef int (*nghttp2_on_invalid_frame_recv_callback)(
+    nghttp2_session *session, const nghttp2_frame *frame, int lib_error_code,
+    void *user_data);
+
+/**
+ * @functypedef
+ *
+ * Callback function invoked when a chunk of data in DATA frame is
+ * received.  The |stream_id| is the stream ID this DATA frame belongs
+ * to.  The |flags| is the flags of DATA frame which this data chunk
+ * is contained.  ``(flags & NGHTTP2_FLAG_END_STREAM) != 0`` does not
+ * necessarily mean this chunk of data is the last one in the stream.
+ * You should use :type:`nghttp2_on_frame_recv_callback` to know all
+ * data frames are received.  The |user_data| pointer is the third
+ * argument passed in to the call to `nghttp2_session_client_new()` or
+ * `nghttp2_session_server_new()`.
+ *
+ * If the application uses `nghttp2_session_mem_recv()`, it can return
+ * :enum:`NGHTTP2_ERR_PAUSE` to make `nghttp2_session_mem_recv()`
+ * return without processing further input bytes.  The memory by
+ * pointed by the |data| is retained until
+ * `nghttp2_session_mem_recv()` or `nghttp2_session_recv()` is called.
+ * The application must retain the input bytes which was used to
+ * produce the |data| parameter, because it may refer to the memory
+ * region included in the input bytes.
+ *
+ * The implementation of this function must return 0 if it succeeds.
+ * If nonzero is returned, it is treated as fatal error, and
+ * `nghttp2_session_recv()` and `nghttp2_session_mem_recv()` functions
+ * immediately return :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.
+ *
+ * To set this callback to :type:`nghttp2_session_callbacks`, use
+ * `nghttp2_session_callbacks_set_on_data_chunk_recv_callback()`.
+ */
+typedef int (*nghttp2_on_data_chunk_recv_callback)(nghttp2_session *session,
+                                                   uint8_t flags,
+                                                   int32_t stream_id,
+                                                   const uint8_t *data,
+                                                   size_t len, void *user_data);
+
+/**
+ * @functypedef
+ *
+ * Callback function invoked just before the non-DATA frame |frame| is
+ * sent.  The |user_data| pointer is the third argument passed in to
+ * the call to `nghttp2_session_client_new()` or
+ * `nghttp2_session_server_new()`.
+ *
+ * The implementation of this function must return 0 if it succeeds.
+ * It can also return :enum:`NGHTTP2_ERR_CANCEL` to cancel the
+ * transmission of the given frame.
+ *
+ * If there is a fatal error while executing this callback, the
+ * implementation should return :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`,
+ * which makes `nghttp2_session_send()` and
+ * `nghttp2_session_mem_send()` functions immediately return
+ * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.
+ *
+ * If the other value is returned, it is treated as if
+ * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE` is returned.  But the
+ * implementation should not rely on this since the library may define
+ * new return value to extend its capability.
+ *
+ * To set this callback to :type:`nghttp2_session_callbacks`, use
+ * `nghttp2_session_callbacks_set_before_frame_send_callback()`.
+ */
+typedef int (*nghttp2_before_frame_send_callback)(nghttp2_session *session,
+                                                  const nghttp2_frame *frame,
+                                                  void *user_data);
+
+/**
+ * @functypedef
+ *
+ * Callback function invoked after the frame |frame| is sent.  The
+ * |user_data| pointer is the third argument passed in to the call to
+ * `nghttp2_session_client_new()` or `nghttp2_session_server_new()`.
+ *
+ * The implementation of this function must return 0 if it succeeds.
+ * If nonzero is returned, it is treated as fatal error and
+ * `nghttp2_session_send()` and `nghttp2_session_mem_send()` functions
+ * immediately return :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.
+ *
+ * To set this callback to :type:`nghttp2_session_callbacks`, use
+ * `nghttp2_session_callbacks_set_on_frame_send_callback()`.
+ */
+typedef int (*nghttp2_on_frame_send_callback)(nghttp2_session *session,
+                                              const nghttp2_frame *frame,
+                                              void *user_data);
+
+/**
+ * @functypedef
+ *
+ * Callback function invoked after the non-DATA frame |frame| is not
+ * sent because of the error.  The error is indicated by the
+ * |lib_error_code|, which is one of the values defined in
+ * :type:`nghttp2_error`.  The |user_data| pointer is the third
+ * argument passed in to the call to `nghttp2_session_client_new()` or
+ * `nghttp2_session_server_new()`.
+ *
+ * The implementation of this function must return 0 if it succeeds.
+ * If nonzero is returned, it is treated as fatal error and
+ * `nghttp2_session_send()` and `nghttp2_session_mem_send()` functions
+ * immediately return :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.
+ *
+ * `nghttp2_session_get_stream_user_data()` can be used to get
+ * associated data.
+ *
+ * To set this callback to :type:`nghttp2_session_callbacks`, use
+ * `nghttp2_session_callbacks_set_on_frame_not_send_callback()`.
+ */
+typedef int (*nghttp2_on_frame_not_send_callback)(nghttp2_session *session,
+                                                  const nghttp2_frame *frame,
+                                                  int lib_error_code,
+                                                  void *user_data);
+
+/**
+ * @functypedef
+ *
+ * Callback function invoked when the stream |stream_id| is closed.
+ * The reason of closure is indicated by the |error_code|.  The
+ * |error_code| is usually one of :enum:`nghttp2_error_code`, but that
+ * is not guaranteed.  The stream_user_data, which was specified in
+ * `nghttp2_submit_request()` or `nghttp2_submit_headers()`, is still
+ * available in this function.  The |user_data| pointer is the third
+ * argument passed in to the call to `nghttp2_session_client_new()` or
+ * `nghttp2_session_server_new()`.
+ *
+ * This function is also called for a stream in reserved state.
+ *
+ * The implementation of this function must return 0 if it succeeds.
+ * If nonzero is returned, it is treated as fatal error and
+ * `nghttp2_session_recv()`, `nghttp2_session_mem_recv()`,
+ * `nghttp2_session_send()`, and `nghttp2_session_mem_send()`
+ * functions immediately return :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.
+ *
+ * To set this callback to :type:`nghttp2_session_callbacks`, use
+ * `nghttp2_session_callbacks_set_on_stream_close_callback()`.
+ */
+typedef int (*nghttp2_on_stream_close_callback)(nghttp2_session *session,
+                                                int32_t stream_id,
+                                                uint32_t error_code,
+                                                void *user_data);
+
+/**
+ * @functypedef
+ *
+ * Callback function invoked when the reception of header block in
+ * HEADERS or PUSH_PROMISE is started.  Each header name/value pair
+ * will be emitted by :type:`nghttp2_on_header_callback`.
+ *
+ * The ``frame->hd.flags`` may not have
+ * :enum:`NGHTTP2_FLAG_END_HEADERS` flag set, which indicates that one
+ * or more CONTINUATION frames are involved.  But the application does
+ * not need to care about that because the header name/value pairs are
+ * emitted transparently regardless of CONTINUATION frames.
+ *
+ * The server applications probably create an object to store
+ * information about new stream if ``frame->hd.type ==
+ * NGHTTP2_HEADERS`` and ``frame->headers.cat ==
+ * NGHTTP2_HCAT_REQUEST``.  If |session| is configured as server side,
+ * ``frame->headers.cat`` is either ``NGHTTP2_HCAT_REQUEST``
+ * containing request headers or ``NGHTTP2_HCAT_HEADERS`` containing
+ * trailer fields and never get PUSH_PROMISE in this callback.
+ *
+ * For the client applications, ``frame->hd.type`` is either
+ * ``NGHTTP2_HEADERS`` or ``NGHTTP2_PUSH_PROMISE``.  In case of
+ * ``NGHTTP2_HEADERS``, ``frame->headers.cat ==
+ * NGHTTP2_HCAT_RESPONSE`` means that it is the first response
+ * headers, but it may be non-final response which is indicated by 1xx
+ * status code.  In this case, there may be zero or more HEADERS frame
+ * with ``frame->headers.cat == NGHTTP2_HCAT_HEADERS`` which has
+ * non-final response code and finally client gets exactly one HEADERS
+ * frame with ``frame->headers.cat == NGHTTP2_HCAT_HEADERS``
+ * containing final response headers (non-1xx status code).  The
+ * trailer fields also has ``frame->headers.cat ==
+ * NGHTTP2_HCAT_HEADERS`` which does not contain any status code.
+ *
+ * Returning :enum:`NGHTTP2_ERR_TEMPORAL_CALLBACK_FAILURE` will close
+ * the stream (promised stream if frame is PUSH_PROMISE) by issuing
+ * RST_STREAM with :enum:`NGHTTP2_INTERNAL_ERROR`.  In this case,
+ * :type:`nghttp2_on_header_callback` and
+ * :type:`nghttp2_on_frame_recv_callback` will not be invoked.  If a
+ * different error code is desirable, use
+ * `nghttp2_submit_rst_stream()` with a desired error code and then
+ * return :enum:`NGHTTP2_ERR_TEMPORAL_CALLBACK_FAILURE`.  Again, use
+ * ``frame->push_promise.promised_stream_id`` as stream_id parameter
+ * in `nghttp2_submit_rst_stream()` if frame is PUSH_PROMISE.
+ *
+ * The implementation of this function must return 0 if it succeeds.
+ * It can return :enum:`NGHTTP2_ERR_TEMPORAL_CALLBACK_FAILURE` to
+ * reset the stream (promised stream if frame is PUSH_PROMISE).  For
+ * critical errors, it must return
+ * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.  If the other value is
+ * returned, it is treated as if :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`
+ * is returned.  If :enum:`NGHTTP2_ERR_CALLBACK_FAILURE` is returned,
+ * `nghttp2_session_mem_recv()` function will immediately return
+ * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.
+ *
+ * To set this callback to :type:`nghttp2_session_callbacks`, use
+ * `nghttp2_session_callbacks_set_on_begin_headers_callback()`.
+ */
+typedef int (*nghttp2_on_begin_headers_callback)(nghttp2_session *session,
+                                                 const nghttp2_frame *frame,
+                                                 void *user_data);
+
+/**
+ * @functypedef
+ *
+ * Callback function invoked when a header name/value pair is received
+ * for the |frame|.  The |name| of length |namelen| is header name.
+ * The |value| of length |valuelen| is header value.  The |flags| is
+ * bitwise OR of one or more of :type:`nghttp2_nv_flag`.
+ *
+ * If :enum:`NGHTTP2_NV_FLAG_NO_INDEX` is set in |flags|, the receiver
+ * must not index this name/value pair when forwarding it to the next
+ * hop.  More specifically, "Literal Header Field never Indexed"
+ * representation must be used in HPACK encoding.
+ *
+ * When this callback is invoked, ``frame->hd.type`` is either
+ * :enum:`NGHTTP2_HEADERS` or :enum:`NGHTTP2_PUSH_PROMISE`.  After all
+ * header name/value pairs are processed with this callback, and no
+ * error has been detected, :type:`nghttp2_on_frame_recv_callback`
+ * will be invoked.  If there is an error in decompression,
+ * :type:`nghttp2_on_frame_recv_callback` for the |frame| will not be
+ * invoked.
+ *
+ * Both |name| and |value| are guaranteed to be NULL-terminated.  The
+ * |namelen| and |valuelen| do not include terminal NULL.  If
+ * `nghttp2_option_set_no_http_messaging()` is used with nonzero
+ * value, NULL character may be included in |name| or |value| before
+ * terminating NULL.
+ *
+ * Please note that unless `nghttp2_option_set_no_http_messaging()` is
+ * used, nghttp2 library does perform validation against the |name|
+ * and the |value| using `nghttp2_check_header_name()` and
+ * `nghttp2_check_header_value()`.  In addition to this, nghttp2
+ * performs validation based on HTTP Messaging rule, which is briefly
+ * explained in :ref:`http-messaging` section.
+ *
+ * If the application uses `nghttp2_session_mem_recv()`, it can return
+ * :enum:`NGHTTP2_ERR_PAUSE` to make `nghttp2_session_mem_recv()`
+ * return without processing further input bytes.  The memory pointed
+ * by |frame|, |name| and |value| parameters are retained until
+ * `nghttp2_session_mem_recv()` or `nghttp2_session_recv()` is called.
+ * The application must retain the input bytes which was used to
+ * produce these parameters, because it may refer to the memory region
+ * included in the input bytes.
+ *
+ * Returning :enum:`NGHTTP2_ERR_TEMPORAL_CALLBACK_FAILURE` will close
+ * the stream (promised stream if frame is PUSH_PROMISE) by issuing
+ * RST_STREAM with :enum:`NGHTTP2_INTERNAL_ERROR`.  In this case,
+ * :type:`nghttp2_on_header_callback` and
+ * :type:`nghttp2_on_frame_recv_callback` will not be invoked.  If a
+ * different error code is desirable, use
+ * `nghttp2_submit_rst_stream()` with a desired error code and then
+ * return :enum:`NGHTTP2_ERR_TEMPORAL_CALLBACK_FAILURE`.  Again, use
+ * ``frame->push_promise.promised_stream_id`` as stream_id parameter
+ * in `nghttp2_submit_rst_stream()` if frame is PUSH_PROMISE.
+ *
+ * The implementation of this function must return 0 if it succeeds.
+ * It may return :enum:`NGHTTP2_ERR_PAUSE` or
+ * :enum:`NGHTTP2_ERR_TEMPORAL_CALLBACK_FAILURE`.  For other critical
+ * failures, it must return :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.  If
+ * the other nonzero value is returned, it is treated as
+ * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.  If
+ * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE` is returned,
+ * `nghttp2_session_recv()` and `nghttp2_session_mem_recv()` functions
+ * immediately return :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.
+ *
+ * To set this callback to :type:`nghttp2_session_callbacks`, use
+ * `nghttp2_session_callbacks_set_on_header_callback()`.
+ *
+ * .. warning::
+ *
+ *   Application should properly limit the total buffer size to store
+ *   incoming header fields.  Without it, peer may send large number
+ *   of header fields or large header fields to cause out of memory in
+ *   local endpoint.  Due to how HPACK works, peer can do this
+ *   effectively without using much memory on their own.
+ */
+typedef int (*nghttp2_on_header_callback)(nghttp2_session *session,
+                                          const nghttp2_frame *frame,
+                                          const uint8_t *name, size_t namelen,
+                                          const uint8_t *value, size_t valuelen,
+                                          uint8_t flags, void *user_data);
+
+/**
+ * @functypedef
+ *
+ * Callback function invoked when a header name/value pair is received
+ * for the |frame|.  The |name| is header name.  The |value| is header
+ * value.  The |flags| is bitwise OR of one or more of
+ * :type:`nghttp2_nv_flag`.
+ *
+ * This callback behaves like :type:`nghttp2_on_header_callback`,
+ * except that |name| and |value| are stored in reference counted
+ * buffer.  If application wishes to keep these references without
+ * copying them, use `nghttp2_rcbuf_incref()` to increment their
+ * reference count.  It is the application's responsibility to call
+ * `nghttp2_rcbuf_decref()` if they called `nghttp2_rcbuf_incref()` so
+ * as not to leak memory.  If the |session| is created by
+ * `nghttp2_session_server_new3()` or `nghttp2_session_client_new3()`,
+ * the function to free memory is the one belongs to the mem
+ * parameter.  As long as this free function alives, |name| and
+ * |value| can live after |session| was destroyed.
+ */
+typedef int (*nghttp2_on_header_callback2)(nghttp2_session *session,
+                                           const nghttp2_frame *frame,
+                                           nghttp2_rcbuf *name,
+                                           nghttp2_rcbuf *value, uint8_t flags,
+                                           void *user_data);
+
+/**
+ * @functypedef
+ *
+ * Callback function invoked when the library asks application how
+ * many padding bytes are required for the transmission of the
+ * |frame|.  The application must choose the total length of payload
+ * including padded bytes in range [frame->hd.length, max_payloadlen],
+ * inclusive.  Choosing number not in this range will be treated as
+ * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.  Returning
+ * ``frame->hd.length`` means no padding is added.  Returning
+ * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE` will make
+ * `nghttp2_session_send()` and `nghttp2_session_mem_send()` functions
+ * immediately return :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.
+ *
+ * To set this callback to :type:`nghttp2_session_callbacks`, use
+ * `nghttp2_session_callbacks_set_select_padding_callback()`.
+ */
+typedef ssize_t (*nghttp2_select_padding_callback)(nghttp2_session *session,
+                                                   const nghttp2_frame *frame,
+                                                   size_t max_payloadlen,
+                                                   void *user_data);
+
+/**
+ * @functypedef
+ *
+ * Callback function invoked when library wants to get max length of
+ * data to send data to the remote peer.  The implementation of this
+ * function should return a value in the following range.  [1,
+ * min(|session_remote_window_size|, |stream_remote_window_size|,
+ * |remote_max_frame_size|)].  If a value greater than this range is
+ * returned than the max allow value will be used.  Returning a value
+ * smaller than this range is treated as
+ * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.  The |frame_type| is provided
+ * for future extensibility and identifies the type of frame (see
+ * :type:`nghttp2_frame_type`) for which to get the length for.
+ * Currently supported frame types are: :enum:`NGHTTP2_DATA`.
+ *
+ * This callback can be used to control the length in bytes for which
+ * :type:`nghttp2_data_source_read_callback` is allowed to send to the
+ * remote endpoint.  This callback is optional.  Returning
+ * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE` will signal the entire session
+ * failure.
+ *
+ * To set this callback to :type:`nghttp2_session_callbacks`, use
+ * `nghttp2_session_callbacks_set_data_source_read_length_callback()`.
+ */
+typedef ssize_t (*nghttp2_data_source_read_length_callback)(
+    nghttp2_session *session, uint8_t frame_type, int32_t stream_id,
+    int32_t session_remote_window_size, int32_t stream_remote_window_size,
+    uint32_t remote_max_frame_size, void *user_data);
+
+/**
+ * @functypedef
+ *
+ * Callback function invoked when a frame header is received.  The
+ * |hd| points to received frame header.
+ *
+ * Unlike :type:`nghttp2_on_frame_recv_callback`, this callback will
+ * also be called when frame header of CONTINUATION frame is received.
+ *
+ * If both :type:`nghttp2_on_begin_frame_callback` and
+ * :type:`nghttp2_on_begin_headers_callback` are set and HEADERS or
+ * PUSH_PROMISE is received, :type:`nghttp2_on_begin_frame_callback`
+ * will be called first.
+ *
+ * The implementation of this function must return 0 if it succeeds.
+ * If nonzero value is returned, it is treated as fatal error and
+ * `nghttp2_session_recv()` and `nghttp2_session_mem_recv()` functions
+ * immediately return :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.
+ *
+ * To set this callback to :type:`nghttp2_session_callbacks`, use
+ * `nghttp2_session_callbacks_set_on_begin_frame_callback()`.
+ */
+typedef int (*nghttp2_on_begin_frame_callback)(nghttp2_session *session,
+                                               const nghttp2_frame_hd *hd,
+                                               void *user_data);
+
+/**
+ * @functypedef
+ *
+ * Callback function invoked when chunk of extension frame payload is
+ * received.  The |hd| points to frame header.  The received
+ * chunk is |data| of length |len|.
+ *
+ * The implementation of this function must return 0 if it succeeds.
+ *
+ * To abort processing this extension frame, return
+ * :enum:`NGHTTP2_ERR_CANCEL`.
+ *
+ * If fatal error occurred, application should return
+ * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.  In this case,
+ * `nghttp2_session_recv()` and `nghttp2_session_mem_recv()` functions
+ * immediately return :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.  If the
+ * other values are returned, currently they are treated as
+ * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.
+ */
+typedef int (*nghttp2_on_extension_chunk_recv_callback)(
+    nghttp2_session *session, const nghttp2_frame_hd *hd, const uint8_t *data,
+    size_t len, void *user_data);
+
+/**
+ * @functypedef
+ *
+ * Callback function invoked when library asks the application to
+ * unpack extension payload from its wire format.  The extension
+ * payload has been passed to the application using
+ * :type:`nghttp2_on_extension_chunk_recv_callback`.  The frame header
+ * is already unpacked by the library and provided as |hd|.
+ *
+ * To receive extension frames, the application must tell desired
+ * extension frame type to the library using
+ * `nghttp2_option_set_user_recv_extension_type()`.
+ *
+ * The implementation of this function may store the pointer to the
+ * created object as a result of unpacking in |*payload|, and returns
+ * 0.  The pointer stored in |*payload| is opaque to the library, and
+ * the library does not own its pointer.  |*payload| is initialized as
+ * ``NULL``.  The |*payload| is available as ``frame->ext.payload`` in
+ * :type:`nghttp2_on_frame_recv_callback`.  Therefore if application
+ * can free that memory inside :type:`nghttp2_on_frame_recv_callback`
+ * callback.  Of course, application has a liberty not ot use
+ * |*payload|, and do its own mechanism to process extension frames.
+ *
+ * To abort processing this extension frame, return
+ * :enum:`NGHTTP2_ERR_CANCEL`.
+ *
+ * If fatal error occurred, application should return
+ * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.  In this case,
+ * `nghttp2_session_recv()` and `nghttp2_session_mem_recv()` functions
+ * immediately return :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.  If the
+ * other values are returned, currently they are treated as
+ * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.
+ */
+typedef int (*nghttp2_unpack_extension_callback)(nghttp2_session *session,
+                                                 void **payload,
+                                                 const nghttp2_frame_hd *hd,
+                                                 void *user_data);
+
+/**
+ * @functypedef
+ *
+ * Callback function invoked when library asks the application to pack
+ * extension payload in its wire format.  The frame header will be
+ * packed by library.  Application must pack payload only.
+ * ``frame->ext.payload`` is the object passed to
+ * `nghttp2_submit_extension()` as payload parameter.  Application
+ * must pack extension payload to the |buf| of its capacity |len|
+ * bytes.  The |len| is at least 16KiB.
+ *
+ * The implementation of this function should return the number of
+ * bytes written into |buf| when it succeeds.
+ *
+ * To abort processing this extension frame, return
+ * :enum:`NGHTTP2_ERR_CANCEL`, and
+ * :type:`nghttp2_on_frame_not_send_callback` will be invoked.
+ *
+ * If fatal error occurred, application should return
+ * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.  In this case,
+ * `nghttp2_session_send()` and `nghttp2_session_mem_send()` functions
+ * immediately return :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.  If the
+ * other values are returned, currently they are treated as
+ * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.  If the return value is
+ * strictly larger than |len|, it is treated as
+ * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.
+ */
+typedef ssize_t (*nghttp2_pack_extension_callback)(nghttp2_session *session,
+                                                   uint8_t *buf, size_t len,
+                                                   const nghttp2_frame *frame,
+                                                   void *user_data);
+
+/**
+ * @functypedef
+ *
+ * Callback function invoked when library provides the error message
+ * intended for human consumption.  This callback is solely for
+ * debugging purpose.  The |msg| is typically NULL-terminated string
+ * of length |len|.  |len| does not include the sentinel NULL
+ * character.
+ *
+ * The format of error message may change between nghttp2 library
+ * versions.  The application should not depend on the particular
+ * format.
+ *
+ * Normally, application should return 0 from this callback.  If fatal
+ * error occurred while doing something in this callback, application
+ * should return :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.  In this case,
+ * library will return immediately with return value
+ * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.  Currently, if nonzero value
+ * is returned from this callback, they are treated as
+ * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`, but application should not
+ * rely on this details.
+ */
+typedef int (*nghttp2_error_callback)(nghttp2_session *session, const char *msg,
+                                      size_t len, void *user_data);
+
+struct nghttp2_session_callbacks;
+
+/**
+ * @struct
+ *
+ * Callback functions for :type:`nghttp2_session`.  The details of
+ * this structure are intentionally hidden from the public API.
+ */
+typedef struct nghttp2_session_callbacks nghttp2_session_callbacks;
+
+/**
+ * @function
+ *
+ * Initializes |*callbacks_ptr| with NULL values.
+ *
+ * The initialized object can be used when initializing multiple
+ * :type:`nghttp2_session` objects.
+ *
+ * When the application finished using this object, it can use
+ * `nghttp2_session_callbacks_del()` to free its memory.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ */
+NGHTTP2_EXTERN int
+nghttp2_session_callbacks_new(nghttp2_session_callbacks **callbacks_ptr);
+
+/**
+ * @function
+ *
+ * Frees any resources allocated for |callbacks|.  If |callbacks| is
+ * ``NULL``, this function does nothing.
+ */
+NGHTTP2_EXTERN void
+nghttp2_session_callbacks_del(nghttp2_session_callbacks *callbacks);
+
+/**
+ * @function
+ *
+ * Sets callback function invoked when a session wants to send data to
+ * the remote peer.  This callback is not necessary if the application
+ * uses solely `nghttp2_session_mem_send()` to serialize data to
+ * transmit.
+ */
+NGHTTP2_EXTERN void nghttp2_session_callbacks_set_send_callback(
+    nghttp2_session_callbacks *cbs, nghttp2_send_callback send_callback);
+
+/**
+ * @function
+ *
+ * Sets callback function invoked when the a session wants to receive
+ * data from the remote peer.  This callback is not necessary if the
+ * application uses solely `nghttp2_session_mem_recv()` to process
+ * received data.
+ */
+NGHTTP2_EXTERN void nghttp2_session_callbacks_set_recv_callback(
+    nghttp2_session_callbacks *cbs, nghttp2_recv_callback recv_callback);
+
+/**
+ * @function
+ *
+ * Sets callback function invoked by `nghttp2_session_recv()` and
+ * `nghttp2_session_mem_recv()` when a frame is received.
+ */
+NGHTTP2_EXTERN void nghttp2_session_callbacks_set_on_frame_recv_callback(
+    nghttp2_session_callbacks *cbs,
+    nghttp2_on_frame_recv_callback on_frame_recv_callback);
+
+/**
+ * @function
+ *
+ * Sets callback function invoked by `nghttp2_session_recv()` and
+ * `nghttp2_session_mem_recv()` when an invalid non-DATA frame is
+ * received.
+ */
+NGHTTP2_EXTERN void
+nghttp2_session_callbacks_set_on_invalid_frame_recv_callback(
+    nghttp2_session_callbacks *cbs,
+    nghttp2_on_invalid_frame_recv_callback on_invalid_frame_recv_callback);
+
+/**
+ * @function
+ *
+ * Sets callback function invoked when a chunk of data in DATA frame
+ * is received.
+ */
+NGHTTP2_EXTERN void nghttp2_session_callbacks_set_on_data_chunk_recv_callback(
+    nghttp2_session_callbacks *cbs,
+    nghttp2_on_data_chunk_recv_callback on_data_chunk_recv_callback);
+
+/**
+ * @function
+ *
+ * Sets callback function invoked before a non-DATA frame is sent.
+ */
+NGHTTP2_EXTERN void nghttp2_session_callbacks_set_before_frame_send_callback(
+    nghttp2_session_callbacks *cbs,
+    nghttp2_before_frame_send_callback before_frame_send_callback);
+
+/**
+ * @function
+ *
+ * Sets callback function invoked after a frame is sent.
+ */
+NGHTTP2_EXTERN void nghttp2_session_callbacks_set_on_frame_send_callback(
+    nghttp2_session_callbacks *cbs,
+    nghttp2_on_frame_send_callback on_frame_send_callback);
+
+/**
+ * @function
+ *
+ * Sets callback function invoked when a non-DATA frame is not sent
+ * because of an error.
+ */
+NGHTTP2_EXTERN void nghttp2_session_callbacks_set_on_frame_not_send_callback(
+    nghttp2_session_callbacks *cbs,
+    nghttp2_on_frame_not_send_callback on_frame_not_send_callback);
+
+/**
+ * @function
+ *
+ * Sets callback function invoked when the stream is closed.
+ */
+NGHTTP2_EXTERN void nghttp2_session_callbacks_set_on_stream_close_callback(
+    nghttp2_session_callbacks *cbs,
+    nghttp2_on_stream_close_callback on_stream_close_callback);
+
+/**
+ * @function
+ *
+ * Sets callback function invoked when the reception of header block
+ * in HEADERS or PUSH_PROMISE is started.
+ */
+NGHTTP2_EXTERN void nghttp2_session_callbacks_set_on_begin_headers_callback(
+    nghttp2_session_callbacks *cbs,
+    nghttp2_on_begin_headers_callback on_begin_headers_callback);
+
+/**
+ * @function
+ *
+ * Sets callback function invoked when a header name/value pair is
+ * received.  If both
+ * `nghttp2_session_callbacks_set_on_header_callback()` and
+ * `nghttp2_session_callbacks_set_on_header_callback2()` are used to
+ * set callbacks, the latter has the precedence.
+ */
+NGHTTP2_EXTERN void nghttp2_session_callbacks_set_on_header_callback(
+    nghttp2_session_callbacks *cbs,
+    nghttp2_on_header_callback on_header_callback);
+
+/**
+ * @function
+ *
+ * Sets callback function invoked when a header name/value pair is
+ * received.
+ */
+NGHTTP2_EXTERN void nghttp2_session_callbacks_set_on_header_callback2(
+    nghttp2_session_callbacks *cbs,
+    nghttp2_on_header_callback2 on_header_callback2);
+
+/**
+ * @function
+ *
+ * Sets callback function invoked when the library asks application
+ * how many padding bytes are required for the transmission of the
+ * given frame.
+ */
+NGHTTP2_EXTERN void nghttp2_session_callbacks_set_select_padding_callback(
+    nghttp2_session_callbacks *cbs,
+    nghttp2_select_padding_callback select_padding_callback);
+
+/**
+ * @function
+ *
+ * Sets callback function determine the length allowed in
+ * :type:`nghttp2_data_source_read_callback`.
+ */
+NGHTTP2_EXTERN void
+nghttp2_session_callbacks_set_data_source_read_length_callback(
+    nghttp2_session_callbacks *cbs,
+    nghttp2_data_source_read_length_callback data_source_read_length_callback);
+
+/**
+ * @function
+ *
+ * Sets callback function invoked when a frame header is received.
+ */
+NGHTTP2_EXTERN void nghttp2_session_callbacks_set_on_begin_frame_callback(
+    nghttp2_session_callbacks *cbs,
+    nghttp2_on_begin_frame_callback on_begin_frame_callback);
+
+/**
+ * @function
+ *
+ * Sets callback function invoked when
+ * :enum:`NGHTTP2_DATA_FLAG_NO_COPY` is used in
+ * :type:`nghttp2_data_source_read_callback` to avoid data copy.
+ */
+NGHTTP2_EXTERN void nghttp2_session_callbacks_set_send_data_callback(
+    nghttp2_session_callbacks *cbs,
+    nghttp2_send_data_callback send_data_callback);
+
+/**
+ * @function
+ *
+ * Sets callback function invoked when the library asks the
+ * application to pack extension frame payload in wire format.
+ */
+NGHTTP2_EXTERN void nghttp2_session_callbacks_set_pack_extension_callback(
+    nghttp2_session_callbacks *cbs,
+    nghttp2_pack_extension_callback pack_extension_callback);
+
+/**
+ * @function
+ *
+ * Sets callback function invoked when the library asks the
+ * application to unpack extension frame payload from wire format.
+ */
+NGHTTP2_EXTERN void nghttp2_session_callbacks_set_unpack_extension_callback(
+    nghttp2_session_callbacks *cbs,
+    nghttp2_unpack_extension_callback unpack_extension_callback);
+
+/**
+ * @function
+ *
+ * Sets callback function invoked when chunk of extension frame
+ * payload is received.
+ */
+NGHTTP2_EXTERN void
+nghttp2_session_callbacks_set_on_extension_chunk_recv_callback(
+    nghttp2_session_callbacks *cbs,
+    nghttp2_on_extension_chunk_recv_callback on_extension_chunk_recv_callback);
+
+/**
+ * @function
+ *
+ * Sets callback function invoked when library tells error message to
+ * the application.
+ */
+NGHTTP2_EXTERN void nghttp2_session_callbacks_set_error_callback(
+    nghttp2_session_callbacks *cbs, nghttp2_error_callback error_callback);
+
+/**
+ * @functypedef
+ *
+ * Custom memory allocator to replace malloc().  The |mem_user_data|
+ * is the mem_user_data member of :type:`nghttp2_mem` structure.
+ */
+typedef void *(*nghttp2_malloc)(size_t size, void *mem_user_data);
+
+/**
+ * @functypedef
+ *
+ * Custom memory allocator to replace free().  The |mem_user_data| is
+ * the mem_user_data member of :type:`nghttp2_mem` structure.
+ */
+typedef void (*nghttp2_free)(void *ptr, void *mem_user_data);
+
+/**
+ * @functypedef
+ *
+ * Custom memory allocator to replace calloc().  The |mem_user_data|
+ * is the mem_user_data member of :type:`nghttp2_mem` structure.
+ */
+typedef void *(*nghttp2_calloc)(size_t nmemb, size_t size, void *mem_user_data);
+
+/**
+ * @functypedef
+ *
+ * Custom memory allocator to replace realloc().  The |mem_user_data|
+ * is the mem_user_data member of :type:`nghttp2_mem` structure.
+ */
+typedef void *(*nghttp2_realloc)(void *ptr, size_t size, void *mem_user_data);
+
+/**
+ * @struct
+ *
+ * Custom memory allocator functions and user defined pointer.  The
+ * |mem_user_data| member is passed to each allocator function.  This
+ * can be used, for example, to achieve per-session memory pool.
+ *
+ * In the following example code, ``my_malloc``, ``my_free``,
+ * ``my_calloc`` and ``my_realloc`` are the replacement of the
+ * standard allocators ``malloc``, ``free``, ``calloc`` and
+ * ``realloc`` respectively::
+ *
+ *     void *my_malloc_cb(size_t size, void *mem_user_data) {
+ *       return my_malloc(size);
+ *     }
+ *
+ *     void my_free_cb(void *ptr, void *mem_user_data) { my_free(ptr); }
+ *
+ *     void *my_calloc_cb(size_t nmemb, size_t size, void *mem_user_data) {
+ *       return my_calloc(nmemb, size);
+ *     }
+ *
+ *     void *my_realloc_cb(void *ptr, size_t size, void *mem_user_data) {
+ *       return my_realloc(ptr, size);
+ *     }
+ *
+ *     void session_new() {
+ *       nghttp2_session *session;
+ *       nghttp2_session_callbacks *callbacks;
+ *       nghttp2_mem mem = {NULL, my_malloc_cb, my_free_cb, my_calloc_cb,
+ *                          my_realloc_cb};
+ *
+ *       ...
+ *
+ *       nghttp2_session_client_new3(&session, callbacks, NULL, NULL, &mem);
+ *
+ *       ...
+ *     }
+ */
+typedef struct {
+  /**
+   * An arbitrary user supplied data.  This is passed to each
+   * allocator function.
+   */
+  void *mem_user_data;
+  /**
+   * Custom allocator function to replace malloc().
+   */
+  nghttp2_malloc malloc;
+  /**
+   * Custom allocator function to replace free().
+   */
+  nghttp2_free free;
+  /**
+   * Custom allocator function to replace calloc().
+   */
+  nghttp2_calloc calloc;
+  /**
+   * Custom allocator function to replace realloc().
+   */
+  nghttp2_realloc realloc;
+} nghttp2_mem;
+
+struct nghttp2_option;
+
+/**
+ * @struct
+ *
+ * Configuration options for :type:`nghttp2_session`.  The details of
+ * this structure are intentionally hidden from the public API.
+ */
+typedef struct nghttp2_option nghttp2_option;
+
+/**
+ * @function
+ *
+ * Initializes |*option_ptr| with default values.
+ *
+ * When the application finished using this object, it can use
+ * `nghttp2_option_del()` to free its memory.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ */
+NGHTTP2_EXTERN int nghttp2_option_new(nghttp2_option **option_ptr);
+
+/**
+ * @function
+ *
+ * Frees any resources allocated for |option|.  If |option| is
+ * ``NULL``, this function does nothing.
+ */
+NGHTTP2_EXTERN void nghttp2_option_del(nghttp2_option *option);
+
+/**
+ * @function
+ *
+ * This option prevents the library from sending WINDOW_UPDATE for a
+ * connection automatically.  If this option is set to nonzero, the
+ * library won't send WINDOW_UPDATE for DATA until application calls
+ * `nghttp2_session_consume()` to indicate the consumed amount of
+ * data.  Don't use `nghttp2_submit_window_update()` for this purpose.
+ * By default, this option is set to zero.
+ */
+NGHTTP2_EXTERN void
+nghttp2_option_set_no_auto_window_update(nghttp2_option *option, int val);
+
+/**
+ * @function
+ *
+ * This option sets the SETTINGS_MAX_CONCURRENT_STREAMS value of
+ * remote endpoint as if it is received in SETTINGS frame.  Without
+ * specifying this option, before the local endpoint receives
+ * SETTINGS_MAX_CONCURRENT_STREAMS in SETTINGS frame from remote
+ * endpoint, SETTINGS_MAX_CONCURRENT_STREAMS is unlimited.  This may
+ * cause problem if local endpoint submits lots of requests initially
+ * and sending them at once to the remote peer may lead to the
+ * rejection of some requests.  Specifying this option to the sensible
+ * value, say 100, may avoid this kind of issue. This value will be
+ * overwritten if the local endpoint receives
+ * SETTINGS_MAX_CONCURRENT_STREAMS from the remote endpoint.
+ */
+NGHTTP2_EXTERN void
+nghttp2_option_set_peer_max_concurrent_streams(nghttp2_option *option,
+                                               uint32_t val);
+
+/**
+ * @function
+ *
+ * By default, nghttp2 library, if configured as server, requires
+ * first 24 bytes of client magic byte string (MAGIC).  In most cases,
+ * this will simplify the implementation of server.  But sometimes
+ * server may want to detect the application protocol based on first
+ * few bytes on clear text communication.
+ *
+ * If this option is used with nonzero |val|, nghttp2 library does not
+ * handle MAGIC.  It still checks following SETTINGS frame.  This
+ * means that applications should deal with MAGIC by themselves.
+ *
+ * If this option is not used or used with zero value, if MAGIC does
+ * not match :macro:`NGHTTP2_CLIENT_MAGIC`, `nghttp2_session_recv()`
+ * and `nghttp2_session_mem_recv()` will return error
+ * :enum:`NGHTTP2_ERR_BAD_CLIENT_MAGIC`, which is fatal error.
+ */
+NGHTTP2_EXTERN void
+nghttp2_option_set_no_recv_client_magic(nghttp2_option *option, int val);
+
+/**
+ * @function
+ *
+ * By default, nghttp2 library enforces subset of HTTP Messaging rules
+ * described in `HTTP/2 specification, section 8
+ * `_.  See
+ * :ref:`http-messaging` section for details.  For those applications
+ * who use nghttp2 library as non-HTTP use, give nonzero to |val| to
+ * disable this enforcement.
+ */
+NGHTTP2_EXTERN void nghttp2_option_set_no_http_messaging(nghttp2_option *option,
+                                                         int val);
+
+/**
+ * @function
+ *
+ * RFC 7540 does not enforce any limit on the number of incoming
+ * reserved streams (in RFC 7540 terms, streams in reserved (remote)
+ * state).  This only affects client side, since only server can push
+ * streams.  Malicious server can push arbitrary number of streams,
+ * and make client's memory exhausted.  This option can set the
+ * maximum number of such incoming streams to avoid possible memory
+ * exhaustion.  If this option is set, and pushed streams are
+ * automatically closed on reception, without calling user provided
+ * callback, if they exceed the given limit.  The default value is
+ * 200.  If session is configured as server side, this option has no
+ * effect.  Server can control the number of streams to push.
+ */
+NGHTTP2_EXTERN void
+nghttp2_option_set_max_reserved_remote_streams(nghttp2_option *option,
+                                               uint32_t val);
+
+/**
+ * @function
+ *
+ * Sets extension frame type the application is willing to handle with
+ * user defined callbacks (see
+ * :type:`nghttp2_on_extension_chunk_recv_callback` and
+ * :type:`nghttp2_unpack_extension_callback`).  The |type| is
+ * extension frame type, and must be strictly greater than 0x9.
+ * Otherwise, this function does nothing.  The application can call
+ * this function multiple times to set more than one frame type to
+ * receive.  The application does not have to call this function if it
+ * just sends extension frames.
+ */
+NGHTTP2_EXTERN void
+nghttp2_option_set_user_recv_extension_type(nghttp2_option *option,
+                                            uint8_t type);
+
+/**
+ * @function
+ *
+ * Sets extension frame type the application is willing to receive
+ * using builtin handler.  The |type| is the extension frame type to
+ * receive, and must be strictly greater than 0x9.  Otherwise, this
+ * function does nothing.  The application can call this function
+ * multiple times to set more than one frame type to receive.  The
+ * application does not have to call this function if it just sends
+ * extension frames.
+ *
+ * If same frame type is passed to both
+ * `nghttp2_option_set_builtin_recv_extension_type()` and
+ * `nghttp2_option_set_user_recv_extension_type()`, the latter takes
+ * precedence.
+ */
+NGHTTP2_EXTERN void
+nghttp2_option_set_builtin_recv_extension_type(nghttp2_option *option,
+                                               uint8_t type);
+
+/**
+ * @function
+ *
+ * This option prevents the library from sending PING frame with ACK
+ * flag set automatically when PING frame without ACK flag set is
+ * received.  If this option is set to nonzero, the library won't send
+ * PING frame with ACK flag set in the response for incoming PING
+ * frame.  The application can send PING frame with ACK flag set using
+ * `nghttp2_submit_ping()` with :enum:`NGHTTP2_FLAG_ACK` as flags
+ * parameter.
+ */
+NGHTTP2_EXTERN void nghttp2_option_set_no_auto_ping_ack(nghttp2_option *option,
+                                                        int val);
+
+/**
+ * @function
+ *
+ * This option sets the maximum length of header block (a set of
+ * header fields per one HEADERS frame) to send.  The length of a
+ * given set of header fields is calculated using
+ * `nghttp2_hd_deflate_bound()`.  The default value is 64KiB.  If
+ * application attempts to send header fields larger than this limit,
+ * the transmission of the frame fails with error code
+ * :enum:`NGHTTP2_ERR_FRAME_SIZE_ERROR`.
+ */
+NGHTTP2_EXTERN void
+nghttp2_option_set_max_send_header_block_length(nghttp2_option *option,
+                                                size_t val);
+
+/**
+ * @function
+ *
+ * Initializes |*session_ptr| for client use.  The all members of
+ * |callbacks| are copied to |*session_ptr|.  Therefore |*session_ptr|
+ * does not store |callbacks|.  The |user_data| is an arbitrary user
+ * supplied data, which will be passed to the callback functions.
+ *
+ * The :type:`nghttp2_send_callback` must be specified.  If the
+ * application code uses `nghttp2_session_recv()`, the
+ * :type:`nghttp2_recv_callback` must be specified.  The other members
+ * of |callbacks| can be ``NULL``.
+ *
+ * If this function fails, |*session_ptr| is left untouched.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ */
+NGHTTP2_EXTERN int
+nghttp2_session_client_new(nghttp2_session **session_ptr,
+                           const nghttp2_session_callbacks *callbacks,
+                           void *user_data);
+
+/**
+ * @function
+ *
+ * Initializes |*session_ptr| for server use.  The all members of
+ * |callbacks| are copied to |*session_ptr|. Therefore |*session_ptr|
+ * does not store |callbacks|.  The |user_data| is an arbitrary user
+ * supplied data, which will be passed to the callback functions.
+ *
+ * The :type:`nghttp2_send_callback` must be specified.  If the
+ * application code uses `nghttp2_session_recv()`, the
+ * :type:`nghttp2_recv_callback` must be specified.  The other members
+ * of |callbacks| can be ``NULL``.
+ *
+ * If this function fails, |*session_ptr| is left untouched.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ */
+NGHTTP2_EXTERN int
+nghttp2_session_server_new(nghttp2_session **session_ptr,
+                           const nghttp2_session_callbacks *callbacks,
+                           void *user_data);
+
+/**
+ * @function
+ *
+ * Like `nghttp2_session_client_new()`, but with additional options
+ * specified in the |option|.
+ *
+ * The |option| can be ``NULL`` and the call is equivalent to
+ * `nghttp2_session_client_new()`.
+ *
+ * This function does not take ownership |option|.  The application is
+ * responsible for freeing |option| if it finishes using the object.
+ *
+ * The library code does not refer to |option| after this function
+ * returns.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ */
+NGHTTP2_EXTERN int
+nghttp2_session_client_new2(nghttp2_session **session_ptr,
+                            const nghttp2_session_callbacks *callbacks,
+                            void *user_data, const nghttp2_option *option);
+
+/**
+ * @function
+ *
+ * Like `nghttp2_session_server_new()`, but with additional options
+ * specified in the |option|.
+ *
+ * The |option| can be ``NULL`` and the call is equivalent to
+ * `nghttp2_session_server_new()`.
+ *
+ * This function does not take ownership |option|.  The application is
+ * responsible for freeing |option| if it finishes using the object.
+ *
+ * The library code does not refer to |option| after this function
+ * returns.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ */
+NGHTTP2_EXTERN int
+nghttp2_session_server_new2(nghttp2_session **session_ptr,
+                            const nghttp2_session_callbacks *callbacks,
+                            void *user_data, const nghttp2_option *option);
+
+/**
+ * @function
+ *
+ * Like `nghttp2_session_client_new2()`, but with additional custom
+ * memory allocator specified in the |mem|.
+ *
+ * The |mem| can be ``NULL`` and the call is equivalent to
+ * `nghttp2_session_client_new2()`.
+ *
+ * This function does not take ownership |mem|.  The application is
+ * responsible for freeing |mem|.
+ *
+ * The library code does not refer to |mem| pointer after this
+ * function returns, so the application can safely free it.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ */
+NGHTTP2_EXTERN int nghttp2_session_client_new3(
+    nghttp2_session **session_ptr, const nghttp2_session_callbacks *callbacks,
+    void *user_data, const nghttp2_option *option, nghttp2_mem *mem);
+
+/**
+ * @function
+ *
+ * Like `nghttp2_session_server_new2()`, but with additional custom
+ * memory allocator specified in the |mem|.
+ *
+ * The |mem| can be ``NULL`` and the call is equivalent to
+ * `nghttp2_session_server_new2()`.
+ *
+ * This function does not take ownership |mem|.  The application is
+ * responsible for freeing |mem|.
+ *
+ * The library code does not refer to |mem| pointer after this
+ * function returns, so the application can safely free it.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ */
+NGHTTP2_EXTERN int nghttp2_session_server_new3(
+    nghttp2_session **session_ptr, const nghttp2_session_callbacks *callbacks,
+    void *user_data, const nghttp2_option *option, nghttp2_mem *mem);
+
+/**
+ * @function
+ *
+ * Frees any resources allocated for |session|.  If |session| is
+ * ``NULL``, this function does nothing.
+ */
+NGHTTP2_EXTERN void nghttp2_session_del(nghttp2_session *session);
+
+/**
+ * @function
+ *
+ * Sends pending frames to the remote peer.
+ *
+ * This function retrieves the highest prioritized frame from the
+ * outbound queue and sends it to the remote peer.  It does this as
+ * many as possible until the user callback
+ * :type:`nghttp2_send_callback` returns
+ * :enum:`NGHTTP2_ERR_WOULDBLOCK` or the outbound queue becomes empty.
+ * This function calls several callback functions which are passed
+ * when initializing the |session|.  Here is the simple time chart
+ * which tells when each callback is invoked:
+ *
+ * 1. Get the next frame to send from outbound queue.
+ *
+ * 2. Prepare transmission of the frame.
+ *
+ * 3. If the control frame cannot be sent because some preconditions
+ *    are not met (e.g., request HEADERS cannot be sent after GOAWAY),
+ *    :type:`nghttp2_on_frame_not_send_callback` is invoked.  Abort
+ *    the following steps.
+ *
+ * 4. If the frame is HEADERS, PUSH_PROMISE or DATA,
+ *    :type:`nghttp2_select_padding_callback` is invoked.
+ *
+ * 5. If the frame is request HEADERS, the stream is opened here.
+ *
+ * 6. :type:`nghttp2_before_frame_send_callback` is invoked.
+ *
+ * 7. If :enum:`NGHTTP2_ERR_CANCEL` is returned from
+ *    :type:`nghttp2_before_frame_send_callback`, the current frame
+ *    transmission is canceled, and
+ *    :type:`nghttp2_on_frame_not_send_callback` is invoked.  Abort
+ *    the following steps.
+ *
+ * 8. :type:`nghttp2_send_callback` is invoked one or more times to
+ *    send the frame.
+ *
+ * 9. :type:`nghttp2_on_frame_send_callback` is invoked.
+ *
+ * 10. If the transmission of the frame triggers closure of the
+ *     stream, the stream is closed and
+ *     :type:`nghttp2_on_stream_close_callback` is invoked.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`
+ *     The callback function failed.
+ */
+NGHTTP2_EXTERN int nghttp2_session_send(nghttp2_session *session);
+
+/**
+ * @function
+ *
+ * Returns the serialized data to send.
+ *
+ * This function behaves like `nghttp2_session_send()` except that it
+ * does not use :type:`nghttp2_send_callback` to transmit data.
+ * Instead, it assigns the pointer to the serialized data to the
+ * |*data_ptr| and returns its length.  The other callbacks are called
+ * in the same way as they are in `nghttp2_session_send()`.
+ *
+ * If no data is available to send, this function returns 0.
+ *
+ * This function may not return all serialized data in one invocation.
+ * To get all data, call this function repeatedly until it returns 0
+ * or one of negative error codes.
+ *
+ * The assigned |*data_ptr| is valid until the next call of
+ * `nghttp2_session_mem_send()` or `nghttp2_session_send()`.
+ *
+ * The caller must send all data before sending the next chunk of
+ * data.
+ *
+ * This function returns the length of the data pointed by the
+ * |*data_ptr| if it succeeds, or one of the following negative error
+ * codes:
+ *
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ *
+ * .. note::
+ *
+ *   This function may produce very small byte string.  If that is the
+ *   case, and application disables Nagle algorithm (``TCP_NODELAY``),
+ *   then writing this small chunk leads to very small packet, and it
+ *   is very inefficient.  An application should be responsible to
+ *   buffer up small chunks of data as necessary to avoid this
+ *   situation.
+ */
+NGHTTP2_EXTERN ssize_t
+nghttp2_session_mem_send(nghttp2_session *session, const uint8_t **data_ptr);
+
+/**
+ * @function
+ *
+ * Receives frames from the remote peer.
+ *
+ * This function receives as many frames as possible until the user
+ * callback :type:`nghttp2_recv_callback` returns
+ * :enum:`NGHTTP2_ERR_WOULDBLOCK`.  This function calls several
+ * callback functions which are passed when initializing the
+ * |session|.  Here is the simple time chart which tells when each
+ * callback is invoked:
+ *
+ * 1. :type:`nghttp2_recv_callback` is invoked one or more times to
+ *    receive frame header.
+ *
+ * 2. When frame header is received,
+ *    :type:`nghttp2_on_begin_frame_callback` is invoked.
+ *
+ * 3. If the frame is DATA frame:
+ *
+ *    1. :type:`nghttp2_recv_callback` is invoked to receive DATA
+ *       payload. For each chunk of data,
+ *       :type:`nghttp2_on_data_chunk_recv_callback` is invoked.
+ *
+ *    2. If one DATA frame is completely received,
+ *       :type:`nghttp2_on_frame_recv_callback` is invoked.  If the
+ *       reception of the frame triggers the closure of the stream,
+ *       :type:`nghttp2_on_stream_close_callback` is invoked.
+ *
+ * 4. If the frame is the control frame:
+ *
+ *    1. :type:`nghttp2_recv_callback` is invoked one or more times to
+ *       receive whole frame.
+ *
+ *    2. If the received frame is valid, then following actions are
+ *       taken.  If the frame is either HEADERS or PUSH_PROMISE,
+ *       :type:`nghttp2_on_begin_headers_callback` is invoked.  Then
+ *       :type:`nghttp2_on_header_callback` is invoked for each header
+ *       name/value pair.  After all name/value pairs are emitted
+ *       successfully, :type:`nghttp2_on_frame_recv_callback` is
+ *       invoked.  For other frames,
+ *       :type:`nghttp2_on_frame_recv_callback` is invoked.  If the
+ *       reception of the frame triggers the closure of the stream,
+ *       :type:`nghttp2_on_stream_close_callback` is invoked.
+ *
+ *    3. If the received frame is unpacked but is interpreted as
+ *       invalid, :type:`nghttp2_on_invalid_frame_recv_callback` is
+ *       invoked.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_EOF`
+ *     The remote peer did shutdown on the connection.
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`
+ *     The callback function failed.
+ * :enum:`NGHTTP2_ERR_BAD_CLIENT_MAGIC`
+ *     Invalid client magic was detected.  This error only returns
+ *     when |session| was configured as server and
+ *     `nghttp2_option_set_no_recv_client_magic()` is not used with
+ *     nonzero value.
+ * :enum:`NGHTTP2_ERR_FLOODED`
+ *     Flooding was detected in this HTTP/2 session, and it must be
+ *     closed.  This is most likely caused by misbehaviour of peer.
+ */
+NGHTTP2_EXTERN int nghttp2_session_recv(nghttp2_session *session);
+
+/**
+ * @function
+ *
+ * Processes data |in| as an input from the remote endpoint.  The
+ * |inlen| indicates the number of bytes in the |in|.
+ *
+ * This function behaves like `nghttp2_session_recv()` except that it
+ * does not use :type:`nghttp2_recv_callback` to receive data; the
+ * |in| is the only data for the invocation of this function.  If all
+ * bytes are processed, this function returns.  The other callbacks
+ * are called in the same way as they are in `nghttp2_session_recv()`.
+ *
+ * In the current implementation, this function always tries to
+ * processes all input data unless either an error occurs or
+ * :enum:`NGHTTP2_ERR_PAUSE` is returned from
+ * :type:`nghttp2_on_header_callback` or
+ * :type:`nghttp2_on_data_chunk_recv_callback`.  If
+ * :enum:`NGHTTP2_ERR_PAUSE` is used, the return value includes the
+ * number of bytes which was used to produce the data or frame for the
+ * callback.
+ *
+ * This function returns the number of processed bytes, or one of the
+ * following negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`
+ *     The callback function failed.
+ * :enum:`NGHTTP2_ERR_BAD_CLIENT_MAGIC`
+ *     Invalid client magic was detected.  This error only returns
+ *     when |session| was configured as server and
+ *     `nghttp2_option_set_no_recv_client_magic()` is not used with
+ *     nonzero value.
+ * :enum:`NGHTTP2_ERR_FLOODED`
+ *     Flooding was detected in this HTTP/2 session, and it must be
+ *     closed.  This is most likely caused by misbehaviour of peer.
+ */
+NGHTTP2_EXTERN ssize_t nghttp2_session_mem_recv(nghttp2_session *session,
+                                                const uint8_t *in,
+                                                size_t inlen);
+
+/**
+ * @function
+ *
+ * Puts back previously deferred DATA frame in the stream |stream_id|
+ * to the outbound queue.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
+ *     The stream does not exist; or no deferred data exist.
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ */
+NGHTTP2_EXTERN int nghttp2_session_resume_data(nghttp2_session *session,
+                                               int32_t stream_id);
+
+/**
+ * @function
+ *
+ * Returns nonzero value if |session| wants to receive data from the
+ * remote peer.
+ *
+ * If both `nghttp2_session_want_read()` and
+ * `nghttp2_session_want_write()` return 0, the application should
+ * drop the connection.
+ */
+NGHTTP2_EXTERN int nghttp2_session_want_read(nghttp2_session *session);
+
+/**
+ * @function
+ *
+ * Returns nonzero value if |session| wants to send data to the remote
+ * peer.
+ *
+ * If both `nghttp2_session_want_read()` and
+ * `nghttp2_session_want_write()` return 0, the application should
+ * drop the connection.
+ */
+NGHTTP2_EXTERN int nghttp2_session_want_write(nghttp2_session *session);
+
+/**
+ * @function
+ *
+ * Returns stream_user_data for the stream |stream_id|.  The
+ * stream_user_data is provided by `nghttp2_submit_request()`,
+ * `nghttp2_submit_headers()` or
+ * `nghttp2_session_set_stream_user_data()`.  Unless it is set using
+ * `nghttp2_session_set_stream_user_data()`, if the stream is
+ * initiated by the remote endpoint, stream_user_data is always
+ * ``NULL``.  If the stream does not exist, this function returns
+ * ``NULL``.
+ */
+NGHTTP2_EXTERN void *
+nghttp2_session_get_stream_user_data(nghttp2_session *session,
+                                     int32_t stream_id);
+
+/**
+ * @function
+ *
+ * Sets the |stream_user_data| to the stream denoted by the
+ * |stream_id|.  If a stream user data is already set to the stream,
+ * it is replaced with the |stream_user_data|.  It is valid to specify
+ * ``NULL`` in the |stream_user_data|, which nullifies the associated
+ * data pointer.
+ *
+ * It is valid to set the |stream_user_data| to the stream reserved by
+ * PUSH_PROMISE frame.
+ *
+ * This function returns 0 if it succeeds, or one of following
+ * negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
+ *     The stream does not exist
+ */
+NGHTTP2_EXTERN int
+nghttp2_session_set_stream_user_data(nghttp2_session *session,
+                                     int32_t stream_id, void *stream_user_data);
+
+/**
+ * @function
+ *
+ * Returns the number of frames in the outbound queue.  This does not
+ * include the deferred DATA frames.
+ */
+NGHTTP2_EXTERN size_t
+nghttp2_session_get_outbound_queue_size(nghttp2_session *session);
+
+/**
+ * @function
+ *
+ * Returns the number of DATA payload in bytes received without
+ * WINDOW_UPDATE transmission for the stream |stream_id|.  The local
+ * (receive) window size can be adjusted by
+ * `nghttp2_submit_window_update()`.  This function takes into account
+ * that and returns effective data length.  In particular, if the
+ * local window size is reduced by submitting negative
+ * window_size_increment with `nghttp2_submit_window_update()`, this
+ * function returns the number of bytes less than actually received.
+ *
+ * This function returns -1 if it fails.
+ */
+NGHTTP2_EXTERN int32_t
+nghttp2_session_get_stream_effective_recv_data_length(nghttp2_session *session,
+                                                      int32_t stream_id);
+
+/**
+ * @function
+ *
+ * Returns the local (receive) window size for the stream |stream_id|.
+ * The local window size can be adjusted by
+ * `nghttp2_submit_window_update()`.  This function takes into account
+ * that and returns effective window size.
+ *
+ * This function returns -1 if it fails.
+ */
+NGHTTP2_EXTERN int32_t
+nghttp2_session_get_stream_effective_local_window_size(nghttp2_session *session,
+                                                       int32_t stream_id);
+
+/**
+ * @function
+ *
+ * Returns the number of DATA payload in bytes received without
+ * WINDOW_UPDATE transmission for a connection.  The local (receive)
+ * window size can be adjusted by `nghttp2_submit_window_update()`.
+ * This function takes into account that and returns effective data
+ * length.  In particular, if the local window size is reduced by
+ * submitting negative window_size_increment with
+ * `nghttp2_submit_window_update()`, this function returns the number
+ * of bytes less than actually received.
+ *
+ * This function returns -1 if it fails.
+ */
+NGHTTP2_EXTERN int32_t
+nghttp2_session_get_effective_recv_data_length(nghttp2_session *session);
+
+/**
+ * @function
+ *
+ * Returns the local (receive) window size for a connection.  The
+ * local window size can be adjusted by
+ * `nghttp2_submit_window_update()`.  This function takes into account
+ * that and returns effective window size.
+ *
+ * This function returns -1 if it fails.
+ */
+NGHTTP2_EXTERN int32_t
+nghttp2_session_get_effective_local_window_size(nghttp2_session *session);
+
+/**
+ * @function
+ *
+ * Returns the remote window size for a given stream |stream_id|.
+ *
+ * This is the amount of flow-controlled payload (e.g., DATA) that the
+ * local endpoint can send without stream level WINDOW_UPDATE.  There
+ * is also connection level flow control, so the effective size of
+ * payload that the local endpoint can actually send is
+ * min(`nghttp2_session_get_stream_remote_window_size()`,
+ * `nghttp2_session_get_remote_window_size()`).
+ *
+ * This function returns -1 if it fails.
+ */
+NGHTTP2_EXTERN int32_t
+nghttp2_session_get_stream_remote_window_size(nghttp2_session *session,
+                                              int32_t stream_id);
+
+/**
+ * @function
+ *
+ * Returns the remote window size for a connection.
+ *
+ * This function always succeeds.
+ */
+NGHTTP2_EXTERN int32_t
+nghttp2_session_get_remote_window_size(nghttp2_session *session);
+
+/**
+ * @function
+ *
+ * Returns 1 if local peer half closed the given stream |stream_id|.
+ * Returns 0 if it did not.  Returns -1 if no such stream exists.
+ */
+NGHTTP2_EXTERN int
+nghttp2_session_get_stream_local_close(nghttp2_session *session,
+                                       int32_t stream_id);
+
+/**
+ * @function
+ *
+ * Returns 1 if remote peer half closed the given stream |stream_id|.
+ * Returns 0 if it did not.  Returns -1 if no such stream exists.
+ */
+NGHTTP2_EXTERN int
+nghttp2_session_get_stream_remote_close(nghttp2_session *session,
+                                        int32_t stream_id);
+
+/**
+ * @function
+ *
+ * Signals the session so that the connection should be terminated.
+ *
+ * The last stream ID is the minimum value between the stream ID of a
+ * stream for which :type:`nghttp2_on_frame_recv_callback` was called
+ * most recently and the last stream ID we have sent to the peer
+ * previously.
+ *
+ * The |error_code| is the error code of this GOAWAY frame.  The
+ * pre-defined error code is one of :enum:`nghttp2_error_code`.
+ *
+ * After the transmission, both `nghttp2_session_want_read()` and
+ * `nghttp2_session_want_write()` return 0.
+ *
+ * This function should be called when the connection should be
+ * terminated after sending GOAWAY.  If the remaining streams should
+ * be processed after GOAWAY, use `nghttp2_submit_goaway()` instead.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ */
+NGHTTP2_EXTERN int nghttp2_session_terminate_session(nghttp2_session *session,
+                                                     uint32_t error_code);
+
+/**
+ * @function
+ *
+ * Signals the session so that the connection should be terminated.
+ *
+ * This function behaves like `nghttp2_session_terminate_session()`,
+ * but the last stream ID can be specified by the application for fine
+ * grained control of stream.  The HTTP/2 specification does not allow
+ * last_stream_id to be increased.  So the actual value sent as
+ * last_stream_id is the minimum value between the given
+ * |last_stream_id| and the last_stream_id we have previously sent to
+ * the peer.
+ *
+ * The |last_stream_id| is peer's stream ID or 0.  So if |session| is
+ * initialized as client, |last_stream_id| must be even or 0.  If
+ * |session| is initialized as server, |last_stream_id| must be odd or
+ * 0.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
+ *     The |last_stream_id| is invalid.
+ */
+NGHTTP2_EXTERN int nghttp2_session_terminate_session2(nghttp2_session *session,
+                                                      int32_t last_stream_id,
+                                                      uint32_t error_code);
+
+/**
+ * @function
+ *
+ * Signals to the client that the server started graceful shutdown
+ * procedure.
+ *
+ * This function is only usable for server.  If this function is
+ * called with client side session, this function returns
+ * :enum:`NGHTTP2_ERR_INVALID_STATE`.
+ *
+ * To gracefully shutdown HTTP/2 session, server should call this
+ * function to send GOAWAY with last_stream_id (1u << 31) - 1.  And
+ * after some delay (e.g., 1 RTT), send another GOAWAY with the stream
+ * ID that the server has some processing using
+ * `nghttp2_submit_goaway()`.  See also
+ * `nghttp2_session_get_last_proc_stream_id()`.
+ *
+ * Unlike `nghttp2_submit_goaway()`, this function just sends GOAWAY
+ * and does nothing more.  This is a mere indication to the client
+ * that session shutdown is imminent.  The application should call
+ * `nghttp2_submit_goaway()` with appropriate last_stream_id after
+ * this call.
+ *
+ * If one or more GOAWAY frame have been already sent by either
+ * `nghttp2_submit_goaway()` or `nghttp2_session_terminate_session()`,
+ * this function has no effect.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ * :enum:`NGHTTP2_ERR_INVALID_STATE`
+ *     The |session| is initialized as client.
+ */
+NGHTTP2_EXTERN int nghttp2_submit_shutdown_notice(nghttp2_session *session);
+
+/**
+ * @function
+ *
+ * Returns the value of SETTINGS |id| notified by a remote endpoint.
+ * The |id| must be one of values defined in
+ * :enum:`nghttp2_settings_id`.
+ */
+NGHTTP2_EXTERN uint32_t
+nghttp2_session_get_remote_settings(nghttp2_session *session,
+                                    nghttp2_settings_id id);
+
+/**
+ * @function
+ *
+ * Tells the |session| that next stream ID is |next_stream_id|.  The
+ * |next_stream_id| must be equal or greater than the value returned
+ * by `nghttp2_session_get_next_stream_id()`.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
+ *     The |next_stream_id| is strictly less than the value
+ *     `nghttp2_session_get_next_stream_id()` returns; or
+ *     |next_stream_id| is invalid (e.g., even integer for client, or
+ *     odd integer for server).
+ */
+NGHTTP2_EXTERN int nghttp2_session_set_next_stream_id(nghttp2_session *session,
+                                                      int32_t next_stream_id);
+
+/**
+ * @function
+ *
+ * Returns the next outgoing stream ID.  Notice that return type is
+ * uint32_t.  If we run out of stream ID for this session, this
+ * function returns 1 << 31.
+ */
+NGHTTP2_EXTERN uint32_t
+nghttp2_session_get_next_stream_id(nghttp2_session *session);
+
+/**
+ * @function
+ *
+ * Tells the |session| that |size| bytes for a stream denoted by
+ * |stream_id| were consumed by application and are ready to
+ * WINDOW_UPDATE.  The consumed bytes are counted towards both
+ * connection and stream level WINDOW_UPDATE (see
+ * `nghttp2_session_consume_connection()` and
+ * `nghttp2_session_consume_stream()` to update consumption
+ * independently).  This function is intended to be used without
+ * automatic window update (see
+ * `nghttp2_option_set_no_auto_window_update()`).
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
+ *     The |stream_id| is 0.
+ * :enum:`NGHTTP2_ERR_INVALID_STATE`
+ *     Automatic WINDOW_UPDATE is not disabled.
+ */
+NGHTTP2_EXTERN int nghttp2_session_consume(nghttp2_session *session,
+                                           int32_t stream_id, size_t size);
+
+/**
+ * @function
+ *
+ * Like `nghttp2_session_consume()`, but this only tells library that
+ * |size| bytes were consumed only for connection level.  Note that
+ * HTTP/2 maintains connection and stream level flow control windows
+ * independently.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ * :enum:`NGHTTP2_ERR_INVALID_STATE`
+ *     Automatic WINDOW_UPDATE is not disabled.
+ */
+NGHTTP2_EXTERN int nghttp2_session_consume_connection(nghttp2_session *session,
+                                                      size_t size);
+
+/**
+ * @function
+ *
+ * Like `nghttp2_session_consume()`, but this only tells library that
+ * |size| bytes were consumed only for stream denoted by |stream_id|.
+ * Note that HTTP/2 maintains connection and stream level flow control
+ * windows independently.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
+ *     The |stream_id| is 0.
+ * :enum:`NGHTTP2_ERR_INVALID_STATE`
+ *     Automatic WINDOW_UPDATE is not disabled.
+ */
+NGHTTP2_EXTERN int nghttp2_session_consume_stream(nghttp2_session *session,
+                                                  int32_t stream_id,
+                                                  size_t size);
+
+/**
+ * @function
+ *
+ * Changes priority of existing stream denoted by |stream_id|.  The
+ * new priority specification is |pri_spec|.
+ *
+ * The priority is changed silently and instantly, and no PRIORITY
+ * frame will be sent to notify the peer of this change.  This
+ * function may be useful for server to change the priority of pushed
+ * stream.
+ *
+ * If |session| is initialized as server, and ``pri_spec->stream_id``
+ * points to the idle stream, the idle stream is created if it does
+ * not exist.  The created idle stream will depend on root stream
+ * (stream 0) with weight 16.
+ *
+ * Otherwise, if stream denoted by ``pri_spec->stream_id`` is not
+ * found, we use default priority instead of given |pri_spec|.  That
+ * is make stream depend on root stream with weight 16.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
+ *     Attempted to depend on itself; or no stream exist for the given
+ *     |stream_id|; or |stream_id| is 0
+ */
+NGHTTP2_EXTERN int
+nghttp2_session_change_stream_priority(nghttp2_session *session,
+                                       int32_t stream_id,
+                                       const nghttp2_priority_spec *pri_spec);
+
+/**
+ * @function
+ *
+ * Creates idle stream with the given |stream_id|, and priority
+ * |pri_spec|.
+ *
+ * The stream creation is done without sending PRIORITY frame, which
+ * means that peer does not know about the existence of this idle
+ * stream in the local endpoint.
+ *
+ * RFC 7540 does not disallow the use of creation of idle stream with
+ * odd or even stream ID regardless of client or server.  So this
+ * function can create odd or even stream ID regardless of client or
+ * server.  But probably it is a bit safer to use the stream ID the
+ * local endpoint can initiate (in other words, use odd stream ID for
+ * client, and even stream ID for server), to avoid potential
+ * collision from peer's instruction.  Also we can use
+ * `nghttp2_session_set_next_stream_id()` to avoid to open created
+ * idle streams accidentally if we follow this recommendation.
+ *
+ * If |session| is initialized as server, and ``pri_spec->stream_id``
+ * points to the idle stream, the idle stream is created if it does
+ * not exist.  The created idle stream will depend on root stream
+ * (stream 0) with weight 16.
+ *
+ * Otherwise, if stream denoted by ``pri_spec->stream_id`` is not
+ * found, we use default priority instead of given |pri_spec|.  That
+ * is make stream depend on root stream with weight 16.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
+ *     Attempted to depend on itself; or stream denoted by |stream_id|
+ *     already exists; or |stream_id| cannot be used to create idle
+ *     stream (in other words, local endpoint has already opened
+ *     stream ID greater than or equal to the given stream ID; or
+ *     |stream_id| is 0
+ */
+NGHTTP2_EXTERN int
+nghttp2_session_create_idle_stream(nghttp2_session *session, int32_t stream_id,
+                                   const nghttp2_priority_spec *pri_spec);
+
+/**
+ * @function
+ *
+ * Performs post-process of HTTP Upgrade request.  This function can
+ * be called from both client and server, but the behavior is very
+ * different in each other.
+ *
+ * .. warning::
+ *
+ *   This function is deprecated in favor of
+ *   `nghttp2_session_upgrade2()`, because this function lacks the
+ *   parameter to tell the library the request method used in the
+ *   original HTTP request.  This information is required for client
+ *   to validate actual response body length against content-length
+ *   header field (see `nghttp2_option_set_no_http_messaging()`).  If
+ *   HEAD is used in request, the length of response body must be 0
+ *   regardless of value included in content-length header field.
+ *
+ * If called from client side, the |settings_payload| must be the
+ * value sent in ``HTTP2-Settings`` header field and must be decoded
+ * by base64url decoder.  The |settings_payloadlen| is the length of
+ * |settings_payload|.  The |settings_payload| is unpacked and its
+ * setting values will be submitted using `nghttp2_submit_settings()`.
+ * This means that the client application code does not need to submit
+ * SETTINGS by itself.  The stream with stream ID=1 is opened and the
+ * |stream_user_data| is used for its stream_user_data.  The opened
+ * stream becomes half-closed (local) state.
+ *
+ * If called from server side, the |settings_payload| must be the
+ * value received in ``HTTP2-Settings`` header field and must be
+ * decoded by base64url decoder.  The |settings_payloadlen| is the
+ * length of |settings_payload|.  It is treated as if the SETTINGS
+ * frame with that payload is received.  Thus, callback functions for
+ * the reception of SETTINGS frame will be invoked.  The stream with
+ * stream ID=1 is opened.  The |stream_user_data| is ignored.  The
+ * opened stream becomes half-closed (remote).
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
+ *     The |settings_payload| is badly formed.
+ * :enum:`NGHTTP2_ERR_PROTO`
+ *     The stream ID 1 is already used or closed; or is not available.
+ */
+NGHTTP2_EXTERN int nghttp2_session_upgrade(nghttp2_session *session,
+                                           const uint8_t *settings_payload,
+                                           size_t settings_payloadlen,
+                                           void *stream_user_data);
+
+/**
+ * @function
+ *
+ * Performs post-process of HTTP Upgrade request.  This function can
+ * be called from both client and server, but the behavior is very
+ * different in each other.
+ *
+ * If called from client side, the |settings_payload| must be the
+ * value sent in ``HTTP2-Settings`` header field and must be decoded
+ * by base64url decoder.  The |settings_payloadlen| is the length of
+ * |settings_payload|.  The |settings_payload| is unpacked and its
+ * setting values will be submitted using `nghttp2_submit_settings()`.
+ * This means that the client application code does not need to submit
+ * SETTINGS by itself.  The stream with stream ID=1 is opened and the
+ * |stream_user_data| is used for its stream_user_data.  The opened
+ * stream becomes half-closed (local) state.
+ *
+ * If called from server side, the |settings_payload| must be the
+ * value received in ``HTTP2-Settings`` header field and must be
+ * decoded by base64url decoder.  The |settings_payloadlen| is the
+ * length of |settings_payload|.  It is treated as if the SETTINGS
+ * frame with that payload is received.  Thus, callback functions for
+ * the reception of SETTINGS frame will be invoked.  The stream with
+ * stream ID=1 is opened.  The |stream_user_data| is ignored.  The
+ * opened stream becomes half-closed (remote).
+ *
+ * If the request method is HEAD, pass nonzero value to
+ * |head_request|.  Otherwise, pass 0.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
+ *     The |settings_payload| is badly formed.
+ * :enum:`NGHTTP2_ERR_PROTO`
+ *     The stream ID 1 is already used or closed; or is not available.
+ */
+NGHTTP2_EXTERN int nghttp2_session_upgrade2(nghttp2_session *session,
+                                            const uint8_t *settings_payload,
+                                            size_t settings_payloadlen,
+                                            int head_request,
+                                            void *stream_user_data);
+
+/**
+ * @function
+ *
+ * Serializes the SETTINGS values |iv| in the |buf|.  The size of the
+ * |buf| is specified by |buflen|.  The number of entries in the |iv|
+ * array is given by |niv|.  The required space in |buf| for the |niv|
+ * entries is ``8*niv`` bytes and if the given buffer is too small, an
+ * error is returned.  This function is used mainly for creating a
+ * SETTINGS payload to be sent with the ``HTTP2-Settings`` header
+ * field in an HTTP Upgrade request.  The data written in |buf| is NOT
+ * base64url encoded and the application is responsible for encoding.
+ *
+ * This function returns the number of bytes written in |buf|, or one
+ * of the following negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
+ *     The |iv| contains duplicate settings ID or invalid value.
+ *
+ * :enum:`NGHTTP2_ERR_INSUFF_BUFSIZE`
+ *     The provided |buflen| size is too small to hold the output.
+ */
+NGHTTP2_EXTERN ssize_t
+nghttp2_pack_settings_payload(uint8_t *buf, size_t buflen,
+                              const nghttp2_settings_entry *iv, size_t niv);
+
+/**
+ * @function
+ *
+ * Returns string describing the |lib_error_code|.  The
+ * |lib_error_code| must be one of the :enum:`nghttp2_error`.
+ */
+NGHTTP2_EXTERN const char *nghttp2_strerror(int lib_error_code);
+
+/**
+ * @function
+ *
+ * Returns string representation of HTTP/2 error code |error_code|
+ * (e.g., ``PROTOCOL_ERROR`` is returned if ``error_code ==
+ * NGHTTP2_PROTOCOL_ERROR``).  If string representation is unknown for
+ * given |error_code|, this function returns string ``unknown``.
+ */
+NGHTTP2_EXTERN const char *nghttp2_http2_strerror(uint32_t error_code);
+
+/**
+ * @function
+ *
+ * Initializes |pri_spec| with the |stream_id| of the stream to depend
+ * on with |weight| and its exclusive flag.  If |exclusive| is
+ * nonzero, exclusive flag is set.
+ *
+ * The |weight| must be in [:enum:`NGHTTP2_MIN_WEIGHT`,
+ * :enum:`NGHTTP2_MAX_WEIGHT`], inclusive.
+ */
+NGHTTP2_EXTERN void nghttp2_priority_spec_init(nghttp2_priority_spec *pri_spec,
+                                               int32_t stream_id,
+                                               int32_t weight, int exclusive);
+
+/**
+ * @function
+ *
+ * Initializes |pri_spec| with the default values.  The default values
+ * are: stream_id = 0, weight = :macro:`NGHTTP2_DEFAULT_WEIGHT` and
+ * exclusive = 0.
+ */
+NGHTTP2_EXTERN void
+nghttp2_priority_spec_default_init(nghttp2_priority_spec *pri_spec);
+
+/**
+ * @function
+ *
+ * Returns nonzero if the |pri_spec| is filled with default values.
+ */
+NGHTTP2_EXTERN int
+nghttp2_priority_spec_check_default(const nghttp2_priority_spec *pri_spec);
+
+/**
+ * @function
+ *
+ * Submits HEADERS frame and optionally one or more DATA frames.
+ *
+ * The |pri_spec| is priority specification of this request.  ``NULL``
+ * means the default priority (see
+ * `nghttp2_priority_spec_default_init()`).  To specify the priority,
+ * use `nghttp2_priority_spec_init()`.  If |pri_spec| is not ``NULL``,
+ * this function will copy its data members.
+ *
+ * The ``pri_spec->weight`` must be in [:enum:`NGHTTP2_MIN_WEIGHT`,
+ * :enum:`NGHTTP2_MAX_WEIGHT`], inclusive.  If ``pri_spec->weight`` is
+ * strictly less than :enum:`NGHTTP2_MIN_WEIGHT`, it becomes
+ * :enum:`NGHTTP2_MIN_WEIGHT`.  If it is strictly greater than
+ * :enum:`NGHTTP2_MAX_WEIGHT`, it becomes :enum:`NGHTTP2_MAX_WEIGHT`.
+ *
+ * The |nva| is an array of name/value pair :type:`nghttp2_nv` with
+ * |nvlen| elements.  The application is responsible to include
+ * required pseudo-header fields (header field whose name starts with
+ * ":") in |nva| and must place pseudo-headers before regular header
+ * fields.
+ *
+ * This function creates copies of all name/value pairs in |nva|.  It
+ * also lower-cases all names in |nva|.  The order of elements in
+ * |nva| is preserved.  For header fields with
+ * :enum:`NGHTTP2_NV_FLAG_NO_COPY_NAME` and
+ * :enum:`NGHTTP2_NV_FLAG_NO_COPY_VALUE` are set, header field name
+ * and value are not copied respectively.  With
+ * :enum:`NGHTTP2_NV_FLAG_NO_COPY_NAME`, application is responsible to
+ * pass header field name in lowercase.  The application should
+ * maintain the references to them until
+ * :type:`nghttp2_on_frame_send_callback` or
+ * :type:`nghttp2_on_frame_not_send_callback` is called.
+ *
+ * HTTP/2 specification has requirement about header fields in the
+ * request HEADERS.  See the specification for more details.
+ *
+ * If |data_prd| is not ``NULL``, it provides data which will be sent
+ * in subsequent DATA frames.  In this case, a method that allows
+ * request message bodies
+ * (https://tools.ietf.org/html/rfc7231#section-4) must be specified
+ * with ``:method`` key in |nva| (e.g. ``POST``).  This function does
+ * not take ownership of the |data_prd|.  The function copies the
+ * members of the |data_prd|.  If |data_prd| is ``NULL``, HEADERS have
+ * END_STREAM set.  The |stream_user_data| is data associated to the
+ * stream opened by this request and can be an arbitrary pointer,
+ * which can be retrieved later by
+ * `nghttp2_session_get_stream_user_data()`.
+ *
+ * This function returns assigned stream ID if it succeeds, or one of
+ * the following negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ * :enum:`NGHTTP2_ERR_STREAM_ID_NOT_AVAILABLE`
+ *     No stream ID is available because maximum stream ID was
+ *     reached.
+ * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
+ *     Trying to depend on itself (new stream ID equals
+ *     ``pri_spec->stream_id``).
+ * :enum:`NGHTTP2_ERR_PROTO`
+ *     The |session| is server session.
+ *
+ * .. warning::
+ *
+ *   This function returns assigned stream ID if it succeeds.  But
+ *   that stream is not opened yet.  The application must not submit
+ *   frame to that stream ID before
+ *   :type:`nghttp2_before_frame_send_callback` is called for this
+ *   frame.
+ *
+ */
+NGHTTP2_EXTERN int32_t
+nghttp2_submit_request(nghttp2_session *session,
+                       const nghttp2_priority_spec *pri_spec,
+                       const nghttp2_nv *nva, size_t nvlen,
+                       const nghttp2_data_provider *data_prd,
+                       void *stream_user_data);
+
+/**
+ * @function
+ *
+ * Submits response HEADERS frame and optionally one or more DATA
+ * frames against the stream |stream_id|.
+ *
+ * The |nva| is an array of name/value pair :type:`nghttp2_nv` with
+ * |nvlen| elements.  The application is responsible to include
+ * required pseudo-header fields (header field whose name starts with
+ * ":") in |nva| and must place pseudo-headers before regular header
+ * fields.
+ *
+ * This function creates copies of all name/value pairs in |nva|.  It
+ * also lower-cases all names in |nva|.  The order of elements in
+ * |nva| is preserved.  For header fields with
+ * :enum:`NGHTTP2_NV_FLAG_NO_COPY_NAME` and
+ * :enum:`NGHTTP2_NV_FLAG_NO_COPY_VALUE` are set, header field name
+ * and value are not copied respectively.  With
+ * :enum:`NGHTTP2_NV_FLAG_NO_COPY_NAME`, application is responsible to
+ * pass header field name in lowercase.  The application should
+ * maintain the references to them until
+ * :type:`nghttp2_on_frame_send_callback` or
+ * :type:`nghttp2_on_frame_not_send_callback` is called.
+ *
+ * HTTP/2 specification has requirement about header fields in the
+ * response HEADERS.  See the specification for more details.
+ *
+ * If |data_prd| is not ``NULL``, it provides data which will be sent
+ * in subsequent DATA frames.  This function does not take ownership
+ * of the |data_prd|.  The function copies the members of the
+ * |data_prd|.  If |data_prd| is ``NULL``, HEADERS will have
+ * END_STREAM flag set.
+ *
+ * This method can be used as normal HTTP response and push response.
+ * When pushing a resource using this function, the |session| must be
+ * configured using `nghttp2_session_server_new()` or its variants and
+ * the target stream denoted by the |stream_id| must be reserved using
+ * `nghttp2_submit_push_promise()`.
+ *
+ * To send non-final response headers (e.g., HTTP status 101), don't
+ * use this function because this function half-closes the outbound
+ * stream.  Instead, use `nghttp2_submit_headers()` for this purpose.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
+ *     The |stream_id| is 0.
+ * :enum:`NGHTTP2_ERR_DATA_EXIST`
+ *     DATA or HEADERS has been already submitted and not fully
+ *     processed yet.  Normally, this does not happen, but when
+ *     application wrongly calls `nghttp2_submit_response()` twice,
+ *     this may happen.
+ * :enum:`NGHTTP2_ERR_PROTO`
+ *     The |session| is client session.
+ *
+ * .. warning::
+ *
+ *   Calling this function twice for the same stream ID may lead to
+ *   program crash.  It is generally considered to a programming error
+ *   to commit response twice.
+ */
+NGHTTP2_EXTERN int
+nghttp2_submit_response(nghttp2_session *session, int32_t stream_id,
+                        const nghttp2_nv *nva, size_t nvlen,
+                        const nghttp2_data_provider *data_prd);
+
+/**
+ * @function
+ *
+ * Submits trailer fields HEADERS against the stream |stream_id|.
+ *
+ * The |nva| is an array of name/value pair :type:`nghttp2_nv` with
+ * |nvlen| elements.  The application is responsible not to include
+ * pseudo-header fields (header field whose name starts with ":") in
+ * |nva|.
+ *
+ * This function creates copies of all name/value pairs in |nva|.  It
+ * also lower-cases all names in |nva|.  The order of elements in
+ * |nva| is preserved.  For header fields with
+ * :enum:`NGHTTP2_NV_FLAG_NO_COPY_NAME` and
+ * :enum:`NGHTTP2_NV_FLAG_NO_COPY_VALUE` are set, header field name
+ * and value are not copied respectively.  With
+ * :enum:`NGHTTP2_NV_FLAG_NO_COPY_NAME`, application is responsible to
+ * pass header field name in lowercase.  The application should
+ * maintain the references to them until
+ * :type:`nghttp2_on_frame_send_callback` or
+ * :type:`nghttp2_on_frame_not_send_callback` is called.
+ *
+ * For server, trailer fields must follow response HEADERS or response
+ * DATA without END_STREAM flat set.  The library does not enforce
+ * this requirement, and applications should do this for themselves.
+ * If `nghttp2_submit_trailer()` is called before any response HEADERS
+ * submission (usually by `nghttp2_submit_response()`), the content of
+ * |nva| will be sent as response headers, which will result in error.
+ *
+ * This function has the same effect with `nghttp2_submit_headers()`,
+ * with flags = :enum:`NGHTTP2_FLAG_END_STREAM` and both pri_spec and
+ * stream_user_data to NULL.
+ *
+ * To submit trailer fields after `nghttp2_submit_response()` is
+ * called, the application has to specify
+ * :type:`nghttp2_data_provider` to `nghttp2_submit_response()`.
+ * Inside of :type:`nghttp2_data_source_read_callback`, when setting
+ * :enum:`NGHTTP2_DATA_FLAG_EOF`, also set
+ * :enum:`NGHTTP2_DATA_FLAG_NO_END_STREAM`.  After that, the
+ * application can send trailer fields using
+ * `nghttp2_submit_trailer()`.  `nghttp2_submit_trailer()` can be used
+ * inside :type:`nghttp2_data_source_read_callback`.
+ *
+ * This function returns 0 if it succeeds and |stream_id| is -1.
+ * Otherwise, this function returns 0 if it succeeds, or one of the
+ * following negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
+ *     The |stream_id| is 0.
+ */
+NGHTTP2_EXTERN int nghttp2_submit_trailer(nghttp2_session *session,
+                                          int32_t stream_id,
+                                          const nghttp2_nv *nva, size_t nvlen);
+
+/**
+ * @function
+ *
+ * Submits HEADERS frame. The |flags| is bitwise OR of the
+ * following values:
+ *
+ * * :enum:`NGHTTP2_FLAG_END_STREAM`
+ *
+ * If |flags| includes :enum:`NGHTTP2_FLAG_END_STREAM`, this frame has
+ * END_STREAM flag set.
+ *
+ * The library handles the CONTINUATION frame internally and it
+ * correctly sets END_HEADERS to the last sequence of the PUSH_PROMISE
+ * or CONTINUATION frame.
+ *
+ * If the |stream_id| is -1, this frame is assumed as request (i.e.,
+ * request HEADERS frame which opens new stream).  In this case, the
+ * assigned stream ID will be returned.  Otherwise, specify stream ID
+ * in |stream_id|.
+ *
+ * The |pri_spec| is priority specification of this request.  ``NULL``
+ * means the default priority (see
+ * `nghttp2_priority_spec_default_init()`).  To specify the priority,
+ * use `nghttp2_priority_spec_init()`.  If |pri_spec| is not ``NULL``,
+ * this function will copy its data members.
+ *
+ * The ``pri_spec->weight`` must be in [:enum:`NGHTTP2_MIN_WEIGHT`,
+ * :enum:`NGHTTP2_MAX_WEIGHT`], inclusive.  If ``pri_spec->weight`` is
+ * strictly less than :enum:`NGHTTP2_MIN_WEIGHT`, it becomes
+ * :enum:`NGHTTP2_MIN_WEIGHT`.  If it is strictly greater than
+ * :enum:`NGHTTP2_MAX_WEIGHT`, it becomes :enum:`NGHTTP2_MAX_WEIGHT`.
+ *
+ * The |nva| is an array of name/value pair :type:`nghttp2_nv` with
+ * |nvlen| elements.  The application is responsible to include
+ * required pseudo-header fields (header field whose name starts with
+ * ":") in |nva| and must place pseudo-headers before regular header
+ * fields.
+ *
+ * This function creates copies of all name/value pairs in |nva|.  It
+ * also lower-cases all names in |nva|.  The order of elements in
+ * |nva| is preserved.  For header fields with
+ * :enum:`NGHTTP2_NV_FLAG_NO_COPY_NAME` and
+ * :enum:`NGHTTP2_NV_FLAG_NO_COPY_VALUE` are set, header field name
+ * and value are not copied respectively.  With
+ * :enum:`NGHTTP2_NV_FLAG_NO_COPY_NAME`, application is responsible to
+ * pass header field name in lowercase.  The application should
+ * maintain the references to them until
+ * :type:`nghttp2_on_frame_send_callback` or
+ * :type:`nghttp2_on_frame_not_send_callback` is called.
+ *
+ * The |stream_user_data| is a pointer to an arbitrary data which is
+ * associated to the stream this frame will open.  Therefore it is
+ * only used if this frame opens streams, in other words, it changes
+ * stream state from idle or reserved to open.
+ *
+ * This function is low-level in a sense that the application code can
+ * specify flags directly.  For usual HTTP request,
+ * `nghttp2_submit_request()` is useful.  Likewise, for HTTP response,
+ * prefer `nghttp2_submit_response()`.
+ *
+ * This function returns newly assigned stream ID if it succeeds and
+ * |stream_id| is -1.  Otherwise, this function returns 0 if it
+ * succeeds, or one of the following negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ * :enum:`NGHTTP2_ERR_STREAM_ID_NOT_AVAILABLE`
+ *     No stream ID is available because maximum stream ID was
+ *     reached.
+ * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
+ *     The |stream_id| is 0; or trying to depend on itself (stream ID
+ *     equals ``pri_spec->stream_id``).
+ * :enum:`NGHTTP2_ERR_DATA_EXIST`
+ *     DATA or HEADERS has been already submitted and not fully
+ *     processed yet.  This happens if stream denoted by |stream_id|
+ *     is in reserved state.
+ * :enum:`NGHTTP2_ERR_PROTO`
+ *     The |stream_id| is -1, and |session| is server session.
+ *
+ * .. warning::
+ *
+ *   This function returns assigned stream ID if it succeeds and
+ *   |stream_id| is -1.  But that stream is not opened yet.  The
+ *   application must not submit frame to that stream ID before
+ *   :type:`nghttp2_before_frame_send_callback` is called for this
+ *   frame.
+ *
+ */
+NGHTTP2_EXTERN int32_t
+nghttp2_submit_headers(nghttp2_session *session, uint8_t flags,
+                       int32_t stream_id, const nghttp2_priority_spec *pri_spec,
+                       const nghttp2_nv *nva, size_t nvlen,
+                       void *stream_user_data);
+
+/**
+ * @function
+ *
+ * Submits one or more DATA frames to the stream |stream_id|.  The
+ * data to be sent are provided by |data_prd|.  If |flags| contains
+ * :enum:`NGHTTP2_FLAG_END_STREAM`, the last DATA frame has END_STREAM
+ * flag set.
+ *
+ * This function does not take ownership of the |data_prd|.  The
+ * function copies the members of the |data_prd|.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ * :enum:`NGHTTP2_ERR_DATA_EXIST`
+ *     DATA or HEADERS has been already submitted and not fully
+ *     processed yet.
+ * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
+ *     The |stream_id| is 0.
+ * :enum:`NGHTTP2_ERR_STREAM_CLOSED`
+ *     The stream was already closed; or the |stream_id| is invalid.
+ *
+ * .. note::
+ *
+ *   Currently, only one DATA or HEADERS is allowed for a stream at a
+ *   time.  Submitting these frames more than once before first DATA
+ *   or HEADERS is finished results in :enum:`NGHTTP2_ERR_DATA_EXIST`
+ *   error code.  The earliest callback which tells that previous
+ *   frame is done is :type:`nghttp2_on_frame_send_callback`.  In side
+ *   that callback, new data can be submitted using
+ *   `nghttp2_submit_data()`.  Of course, all data except for last one
+ *   must not have :enum:`NGHTTP2_FLAG_END_STREAM` flag set in
+ *   |flags|.  This sounds a bit complicated, and we recommend to use
+ *   `nghttp2_submit_request()` and `nghttp2_submit_response()` to
+ *   avoid this cascading issue.  The experience shows that for HTTP
+ *   use, these two functions are enough to implement both client and
+ *   server.
+ */
+NGHTTP2_EXTERN int nghttp2_submit_data(nghttp2_session *session, uint8_t flags,
+                                       int32_t stream_id,
+                                       const nghttp2_data_provider *data_prd);
+
+/**
+ * @function
+ *
+ * Submits PRIORITY frame to change the priority of stream |stream_id|
+ * to the priority specification |pri_spec|.
+ *
+ * The |flags| is currently ignored and should be
+ * :enum:`NGHTTP2_FLAG_NONE`.
+ *
+ * The |pri_spec| is priority specification of this request.  ``NULL``
+ * is not allowed for this function. To specify the priority, use
+ * `nghttp2_priority_spec_init()`.  This function will copy its data
+ * members.
+ *
+ * The ``pri_spec->weight`` must be in [:enum:`NGHTTP2_MIN_WEIGHT`,
+ * :enum:`NGHTTP2_MAX_WEIGHT`], inclusive.  If ``pri_spec->weight`` is
+ * strictly less than :enum:`NGHTTP2_MIN_WEIGHT`, it becomes
+ * :enum:`NGHTTP2_MIN_WEIGHT`.  If it is strictly greater than
+ * :enum:`NGHTTP2_MAX_WEIGHT`, it becomes :enum:`NGHTTP2_MAX_WEIGHT`.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
+ *     The |stream_id| is 0; or the |pri_spec| is NULL; or trying to
+ *     depend on itself.
+ */
+NGHTTP2_EXTERN int
+nghttp2_submit_priority(nghttp2_session *session, uint8_t flags,
+                        int32_t stream_id,
+                        const nghttp2_priority_spec *pri_spec);
+
+/**
+ * @function
+ *
+ * Submits RST_STREAM frame to cancel/reject the stream |stream_id|
+ * with the error code |error_code|.
+ *
+ * The pre-defined error code is one of :enum:`nghttp2_error_code`.
+ *
+ * The |flags| is currently ignored and should be
+ * :enum:`NGHTTP2_FLAG_NONE`.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
+ *     The |stream_id| is 0.
+ */
+NGHTTP2_EXTERN int nghttp2_submit_rst_stream(nghttp2_session *session,
+                                             uint8_t flags, int32_t stream_id,
+                                             uint32_t error_code);
+
+/**
+ * @function
+ *
+ * Stores local settings and submits SETTINGS frame.  The |iv| is the
+ * pointer to the array of :type:`nghttp2_settings_entry`.  The |niv|
+ * indicates the number of :type:`nghttp2_settings_entry`.
+ *
+ * The |flags| is currently ignored and should be
+ * :enum:`NGHTTP2_FLAG_NONE`.
+ *
+ * This function does not take ownership of the |iv|.  This function
+ * copies all the elements in the |iv|.
+ *
+ * While updating individual stream's local window size, if the window
+ * size becomes strictly larger than NGHTTP2_MAX_WINDOW_SIZE,
+ * RST_STREAM is issued against such a stream.
+ *
+ * SETTINGS with :enum:`NGHTTP2_FLAG_ACK` is automatically submitted
+ * by the library and application could not send it at its will.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
+ *     The |iv| contains invalid value (e.g., initial window size
+ *     strictly greater than (1 << 31) - 1.
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ */
+NGHTTP2_EXTERN int nghttp2_submit_settings(nghttp2_session *session,
+                                           uint8_t flags,
+                                           const nghttp2_settings_entry *iv,
+                                           size_t niv);
+
+/**
+ * @function
+ *
+ * Submits PUSH_PROMISE frame.
+ *
+ * The |flags| is currently ignored.  The library handles the
+ * CONTINUATION frame internally and it correctly sets END_HEADERS to
+ * the last sequence of the PUSH_PROMISE or CONTINUATION frame.
+ *
+ * The |stream_id| must be client initiated stream ID.
+ *
+ * The |nva| is an array of name/value pair :type:`nghttp2_nv` with
+ * |nvlen| elements.  The application is responsible to include
+ * required pseudo-header fields (header field whose name starts with
+ * ":") in |nva| and must place pseudo-headers before regular header
+ * fields.
+ *
+ * This function creates copies of all name/value pairs in |nva|.  It
+ * also lower-cases all names in |nva|.  The order of elements in
+ * |nva| is preserved.  For header fields with
+ * :enum:`NGHTTP2_NV_FLAG_NO_COPY_NAME` and
+ * :enum:`NGHTTP2_NV_FLAG_NO_COPY_VALUE` are set, header field name
+ * and value are not copied respectively.  With
+ * :enum:`NGHTTP2_NV_FLAG_NO_COPY_NAME`, application is responsible to
+ * pass header field name in lowercase.  The application should
+ * maintain the references to them until
+ * :type:`nghttp2_on_frame_send_callback` or
+ * :type:`nghttp2_on_frame_not_send_callback` is called.
+ *
+ * The |promised_stream_user_data| is a pointer to an arbitrary data
+ * which is associated to the promised stream this frame will open and
+ * make it in reserved state.  It is available using
+ * `nghttp2_session_get_stream_user_data()`.  The application can
+ * access it in :type:`nghttp2_before_frame_send_callback` and
+ * :type:`nghttp2_on_frame_send_callback` of this frame.
+ *
+ * The client side is not allowed to use this function.
+ *
+ * To submit response headers and data, use
+ * `nghttp2_submit_response()`.
+ *
+ * This function returns assigned promised stream ID if it succeeds,
+ * or one of the following negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ * :enum:`NGHTTP2_ERR_PROTO`
+ *     This function was invoked when |session| is initialized as
+ *     client.
+ * :enum:`NGHTTP2_ERR_STREAM_ID_NOT_AVAILABLE`
+ *     No stream ID is available because maximum stream ID was
+ *     reached.
+ * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
+ *     The |stream_id| is 0; The |stream_id| does not designate stream
+ *     that peer initiated.
+ * :enum:`NGHTTP2_ERR_STREAM_CLOSED`
+ *     The stream was already closed; or the |stream_id| is invalid.
+ *
+ * .. warning::
+ *
+ *   This function returns assigned promised stream ID if it succeeds.
+ *   As of 1.16.0, stream object for pushed resource is created when
+ *   this function succeeds.  In that case, the application can submit
+ *   push response for the promised frame.
+ *
+ *   In 1.15.0 or prior versions, pushed stream is not opened yet when
+ *   this function succeeds.  The application must not submit frame to
+ *   that stream ID before :type:`nghttp2_before_frame_send_callback`
+ *   is called for this frame.
+ *
+ */
+NGHTTP2_EXTERN int32_t
+nghttp2_submit_push_promise(nghttp2_session *session, uint8_t flags,
+                            int32_t stream_id, const nghttp2_nv *nva,
+                            size_t nvlen, void *promised_stream_user_data);
+
+/**
+ * @function
+ *
+ * Submits PING frame.  You don't have to send PING back when you
+ * received PING frame.  The library automatically submits PING frame
+ * in this case.
+ *
+ * The |flags| is bitwise OR of 0 or more of the following value.
+ *
+ * * :enum:`NGHTTP2_FLAG_ACK`
+ *
+ * Unless `nghttp2_option_set_no_auto_ping_ack()` is used, the |flags|
+ * should be :enum:`NGHTTP2_FLAG_NONE`.
+ *
+ * If the |opaque_data| is non ``NULL``, then it should point to the 8
+ * bytes array of memory to specify opaque data to send with PING
+ * frame.  If the |opaque_data| is ``NULL``, zero-cleared 8 bytes will
+ * be sent as opaque data.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ */
+NGHTTP2_EXTERN int nghttp2_submit_ping(nghttp2_session *session, uint8_t flags,
+                                       const uint8_t *opaque_data);
+
+/**
+ * @function
+ *
+ * Submits GOAWAY frame with the last stream ID |last_stream_id| and
+ * the error code |error_code|.
+ *
+ * The pre-defined error code is one of :enum:`nghttp2_error_code`.
+ *
+ * The |flags| is currently ignored and should be
+ * :enum:`NGHTTP2_FLAG_NONE`.
+ *
+ * The |last_stream_id| is peer's stream ID or 0.  So if |session| is
+ * initialized as client, |last_stream_id| must be even or 0.  If
+ * |session| is initialized as server, |last_stream_id| must be odd or
+ * 0.
+ *
+ * The HTTP/2 specification says last_stream_id must not be increased
+ * from the value previously sent.  So the actual value sent as
+ * last_stream_id is the minimum value between the given
+ * |last_stream_id| and the last_stream_id previously sent to the
+ * peer.
+ *
+ * If the |opaque_data| is not ``NULL`` and |opaque_data_len| is not
+ * zero, those data will be sent as additional debug data.  The
+ * library makes a copy of the memory region pointed by |opaque_data|
+ * with the length |opaque_data_len|, so the caller does not need to
+ * keep this memory after the return of this function.  If the
+ * |opaque_data_len| is 0, the |opaque_data| could be ``NULL``.
+ *
+ * After successful transmission of GOAWAY, following things happen.
+ * All incoming streams having strictly more than |last_stream_id| are
+ * closed.  All incoming HEADERS which starts new stream are simply
+ * ignored.  After all active streams are handled, both
+ * `nghttp2_session_want_read()` and `nghttp2_session_want_write()`
+ * return 0 and the application can close session.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
+ *     The |opaque_data_len| is too large; the |last_stream_id| is
+ *     invalid.
+ */
+NGHTTP2_EXTERN int nghttp2_submit_goaway(nghttp2_session *session,
+                                         uint8_t flags, int32_t last_stream_id,
+                                         uint32_t error_code,
+                                         const uint8_t *opaque_data,
+                                         size_t opaque_data_len);
+
+/**
+ * @function
+ *
+ * Returns the last stream ID of a stream for which
+ * :type:`nghttp2_on_frame_recv_callback` was invoked most recently.
+ * The returned value can be used as last_stream_id parameter for
+ * `nghttp2_submit_goaway()` and
+ * `nghttp2_session_terminate_session2()`.
+ *
+ * This function always succeeds.
+ */
+NGHTTP2_EXTERN int32_t
+nghttp2_session_get_last_proc_stream_id(nghttp2_session *session);
+
+/**
+ * @function
+ *
+ * Returns nonzero if new request can be sent from local endpoint.
+ *
+ * This function return 0 if request is not allowed for this session.
+ * There are several reasons why request is not allowed.  Some of the
+ * reasons are: session is server; stream ID has been spent; GOAWAY
+ * has been sent or received.
+ *
+ * The application can call `nghttp2_submit_request()` without
+ * consulting this function.  In that case, `nghttp2_submit_request()`
+ * may return error.  Or, request is failed to sent, and
+ * :type:`nghttp2_on_stream_close_callback` is called.
+ */
+NGHTTP2_EXTERN int
+nghttp2_session_check_request_allowed(nghttp2_session *session);
+
+/**
+ * @function
+ *
+ * Returns nonzero if |session| is initialized as server side session.
+ */
+NGHTTP2_EXTERN int
+nghttp2_session_check_server_session(nghttp2_session *session);
+
+/**
+ * @function
+ *
+ * Submits WINDOW_UPDATE frame.
+ *
+ * The |flags| is currently ignored and should be
+ * :enum:`NGHTTP2_FLAG_NONE`.
+ *
+ * The |stream_id| is the stream ID to send this WINDOW_UPDATE.  To
+ * send connection level WINDOW_UPDATE, specify 0 to |stream_id|.
+ *
+ * If the |window_size_increment| is positive, the WINDOW_UPDATE with
+ * that value as window_size_increment is queued.  If the
+ * |window_size_increment| is larger than the received bytes from the
+ * remote endpoint, the local window size is increased by that
+ * difference.  If the sole purpose is to increase the local window
+ * size, consider to use `nghttp2_session_set_local_window_size()`.
+ *
+ * If the |window_size_increment| is negative, the local window size
+ * is decreased by -|window_size_increment|.  If automatic
+ * WINDOW_UPDATE is enabled
+ * (`nghttp2_option_set_no_auto_window_update()`), and the library
+ * decided that the WINDOW_UPDATE should be submitted, then
+ * WINDOW_UPDATE is queued with the current received bytes count.  If
+ * the sole purpose is to decrease the local window size, consider to
+ * use `nghttp2_session_set_local_window_size()`.
+ *
+ * If the |window_size_increment| is 0, the function does nothing and
+ * returns 0.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_FLOW_CONTROL`
+ *     The local window size overflow or gets negative.
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ */
+NGHTTP2_EXTERN int nghttp2_submit_window_update(nghttp2_session *session,
+                                                uint8_t flags,
+                                                int32_t stream_id,
+                                                int32_t window_size_increment);
+
+/**
+ * @function
+ *
+ * Set local window size (local endpoints's window size) to the given
+ * |window_size| for the given stream denoted by |stream_id|.  To
+ * change connection level window size, specify 0 to |stream_id|.  To
+ * increase window size, this function may submit WINDOW_UPDATE frame
+ * to transmission queue.
+ *
+ * The |flags| is currently ignored and should be
+ * :enum:`NGHTTP2_FLAG_NONE`.
+ *
+ * This sounds similar to `nghttp2_submit_window_update()`, but there
+ * are 2 differences.  The first difference is that this function
+ * takes the absolute value of window size to set, rather than the
+ * delta.  To change the window size, this may be easier to use since
+ * the application just declares the intended window size, rather than
+ * calculating delta.  The second difference is that
+ * `nghttp2_submit_window_update()` affects the received bytes count
+ * which has not acked yet.  By the specification of
+ * `nghttp2_submit_window_update()`, to strictly increase the local
+ * window size, we have to submit delta including all received bytes
+ * count, which might not be desirable in some cases.  On the other
+ * hand, this function does not affect the received bytes count.  It
+ * just sets the local window size to the given value.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
+ *     The |stream_id| is negative.
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ */
+NGHTTP2_EXTERN int
+nghttp2_session_set_local_window_size(nghttp2_session *session, uint8_t flags,
+                                      int32_t stream_id, int32_t window_size);
+
+/**
+ * @function
+ *
+ * Submits extension frame.
+ *
+ * Application can pass arbitrary frame flags and stream ID in |flags|
+ * and |stream_id| respectively.  The |payload| is opaque pointer, and
+ * it can be accessible though ``frame->ext.payload`` in
+ * :type:`nghttp2_pack_extension_callback`.  The library will not own
+ * passed |payload| pointer.
+ *
+ * The application must set :type:`nghttp2_pack_extension_callback`
+ * using `nghttp2_session_callbacks_set_pack_extension_callback()`.
+ *
+ * The application should retain the memory pointed by |payload| until
+ * the transmission of extension frame is done (which is indicated by
+ * :type:`nghttp2_on_frame_send_callback`), or transmission fails
+ * (which is indicated by :type:`nghttp2_on_frame_not_send_callback`).
+ * If application does not touch this memory region after packing it
+ * into a wire format, application can free it inside
+ * :type:`nghttp2_pack_extension_callback`.
+ *
+ * The standard HTTP/2 frame cannot be sent with this function, so
+ * |type| must be strictly grater than 0x9.  Otherwise, this function
+ * will fail with error code :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_INVALID_STATE`
+ *     If :type:`nghttp2_pack_extension_callback` is not set.
+ * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
+ *     If  |type| specifies  standard  HTTP/2 frame  type.  The  frame
+ *     types  in the  rage [0x0,  0x9], both  inclusive, are  standard
+ *     HTTP/2 frame type, and cannot be sent using this function.
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory
+ */
+NGHTTP2_EXTERN int nghttp2_submit_extension(nghttp2_session *session,
+                                            uint8_t type, uint8_t flags,
+                                            int32_t stream_id, void *payload);
+
+/**
+ * @struct
+ *
+ * The payload of ALTSVC frame.  ALTSVC frame is a non-critical
+ * extension to HTTP/2.  If this frame is received, and
+ * `nghttp2_option_set_user_recv_extension_type()` is not set, and
+ * `nghttp2_option_set_builtin_recv_extension_type()` is set for
+ * :enum:`NGHTTP2_ALTSVC`, ``nghttp2_extension.payload`` will point to
+ * this struct.
+ *
+ * It has the following members:
+ */
+typedef struct {
+  /**
+   * The pointer to origin which this alternative service is
+   * associated with.  This is not necessarily NULL-terminated.
+   */
+  uint8_t *origin;
+  /**
+   * The length of the |origin|.
+   */
+  size_t origin_len;
+  /**
+   * The pointer to Alt-Svc field value contained in ALTSVC frame.
+   * This is not necessarily NULL-terminated.
+   */
+  uint8_t *field_value;
+  /**
+   * The length of the |field_value|.
+   */
+  size_t field_value_len;
+} nghttp2_ext_altsvc;
+
+/**
+ * @function
+ *
+ * Submits ALTSVC frame.
+ *
+ * ALTSVC frame is a non-critical extension to HTTP/2, and defined in
+ * is defined in `RFC 7383
+ * `_.
+ *
+ * The |flags| is currently ignored and should be
+ * :enum:`NGHTTP2_FLAG_NONE`.
+ *
+ * The |origin| points to the origin this alternative service is
+ * associated with.  The |origin_len| is the length of the origin.  If
+ * |stream_id| is 0, the origin must be specified.  If |stream_id| is
+ * not zero, the origin must be empty (in other words, |origin_len|
+ * must be 0).
+ *
+ * The ALTSVC frame is only usable from server side.  If this function
+ * is invoked with client side session, this function returns
+ * :enum:`NGHTTP2_ERR_INVALID_STATE`.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory
+ * :enum:`NGHTTP2_ERR_INVALID_STATE`
+ *     The function is called from client side session
+ * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
+ *     The sum of |origin_len| and |field_value_len| is larger than
+ *     16382; or |origin_len| is 0 while |stream_id| is 0; or
+ *     |origin_len| is not 0 while |stream_id| is not 0.
+ */
+NGHTTP2_EXTERN int nghttp2_submit_altsvc(nghttp2_session *session,
+                                         uint8_t flags, int32_t stream_id,
+                                         const uint8_t *origin,
+                                         size_t origin_len,
+                                         const uint8_t *field_value,
+                                         size_t field_value_len);
+
+/**
+ * @function
+ *
+ * Compares ``lhs->name`` of length ``lhs->namelen`` bytes and
+ * ``rhs->name`` of length ``rhs->namelen`` bytes.  Returns negative
+ * integer if ``lhs->name`` is found to be less than ``rhs->name``; or
+ * returns positive integer if ``lhs->name`` is found to be greater
+ * than ``rhs->name``; or returns 0 otherwise.
+ */
+NGHTTP2_EXTERN int nghttp2_nv_compare_name(const nghttp2_nv *lhs,
+                                           const nghttp2_nv *rhs);
+
+/**
+ * @function
+ *
+ * A helper function for dealing with NPN in client side or ALPN in
+ * server side.  The |in| contains peer's protocol list in preferable
+ * order.  The format of |in| is length-prefixed and not
+ * null-terminated.  For example, ``h2`` and
+ * ``http/1.1`` stored in |in| like this::
+ *
+ *     in[0] = 2
+ *     in[1..2] = "h2"
+ *     in[3] = 8
+ *     in[4..11] = "http/1.1"
+ *     inlen = 12
+ *
+ * The selection algorithm is as follows:
+ *
+ * 1. If peer's list contains HTTP/2 protocol the library supports,
+ *    it is selected and returns 1. The following step is not taken.
+ *
+ * 2. If peer's list contains ``http/1.1``, this function selects
+ *    ``http/1.1`` and returns 0.  The following step is not taken.
+ *
+ * 3. This function selects nothing and returns -1 (So called
+ *    non-overlap case).  In this case, |out| and |outlen| are left
+ *    untouched.
+ *
+ * Selecting ``h2`` means that ``h2`` is written into |*out| and its
+ * length (which is 2) is assigned to |*outlen|.
+ *
+ * For ALPN, refer to https://tools.ietf.org/html/rfc7301
+ *
+ * See http://technotes.googlecode.com/git/nextprotoneg.html for more
+ * details about NPN.
+ *
+ * For NPN, to use this method you should do something like::
+ *
+ *     static int select_next_proto_cb(SSL* ssl,
+ *                                     unsigned char **out,
+ *                                     unsigned char *outlen,
+ *                                     const unsigned char *in,
+ *                                     unsigned int inlen,
+ *                                     void *arg)
+ *     {
+ *         int rv;
+ *         rv = nghttp2_select_next_protocol(out, outlen, in, inlen);
+ *         if (rv == -1) {
+ *             return SSL_TLSEXT_ERR_NOACK;
+ *         }
+ *         if (rv == 1) {
+ *             ((MyType*)arg)->http2_selected = 1;
+ *         }
+ *         return SSL_TLSEXT_ERR_OK;
+ *     }
+ *     ...
+ *     SSL_CTX_set_next_proto_select_cb(ssl_ctx, select_next_proto_cb, my_obj);
+ *
+ */
+NGHTTP2_EXTERN int nghttp2_select_next_protocol(unsigned char **out,
+                                                unsigned char *outlen,
+                                                const unsigned char *in,
+                                                unsigned int inlen);
+
+/**
+ * @function
+ *
+ * Returns a pointer to a nghttp2_info struct with version information
+ * about the run-time library in use.  The |least_version| argument
+ * can be set to a 24 bit numerical value for the least accepted
+ * version number and if the condition is not met, this function will
+ * return a ``NULL``.  Pass in 0 to skip the version checking.
+ */
+NGHTTP2_EXTERN nghttp2_info *nghttp2_version(int least_version);
+
+/**
+ * @function
+ *
+ * Returns nonzero if the :type:`nghttp2_error` library error code
+ * |lib_error| is fatal.
+ */
+NGHTTP2_EXTERN int nghttp2_is_fatal(int lib_error_code);
+
+/**
+ * @function
+ *
+ * Returns nonzero if HTTP header field name |name| of length |len| is
+ * valid according to http://tools.ietf.org/html/rfc7230#section-3.2
+ *
+ * Because this is a header field name in HTTP2, the upper cased alphabet
+ * is treated as error.
+ */
+NGHTTP2_EXTERN int nghttp2_check_header_name(const uint8_t *name, size_t len);
+
+/**
+ * @function
+ *
+ * Returns nonzero if HTTP header field value |value| of length |len|
+ * is valid according to
+ * http://tools.ietf.org/html/rfc7230#section-3.2
+ */
+NGHTTP2_EXTERN int nghttp2_check_header_value(const uint8_t *value, size_t len);
+
+/* HPACK API */
+
+struct nghttp2_hd_deflater;
+
+/**
+ * @struct
+ *
+ * HPACK deflater object.
+ */
+typedef struct nghttp2_hd_deflater nghttp2_hd_deflater;
+
+/**
+ * @function
+ *
+ * Initializes |*deflater_ptr| for deflating name/values pairs.
+ *
+ * The |deflate_hd_table_bufsize_max| is the upper bound of header
+ * table size the deflater will use.
+ *
+ * If this function fails, |*deflater_ptr| is left untouched.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ */
+NGHTTP2_EXTERN int nghttp2_hd_deflate_new(nghttp2_hd_deflater **deflater_ptr,
+                                          size_t deflate_hd_table_bufsize_max);
+
+/**
+ * @function
+ *
+ * Like `nghttp2_hd_deflate_new()`, but with additional custom memory
+ * allocator specified in the |mem|.
+ *
+ * The |mem| can be ``NULL`` and the call is equivalent to
+ * `nghttp2_hd_deflate_new()`.
+ *
+ * This function does not take ownership |mem|.  The application is
+ * responsible for freeing |mem|.
+ *
+ * The library code does not refer to |mem| pointer after this
+ * function returns, so the application can safely free it.
+ */
+NGHTTP2_EXTERN int nghttp2_hd_deflate_new2(nghttp2_hd_deflater **deflater_ptr,
+                                           size_t deflate_hd_table_bufsize_max,
+                                           nghttp2_mem *mem);
+
+/**
+ * @function
+ *
+ * Deallocates any resources allocated for |deflater|.
+ */
+NGHTTP2_EXTERN void nghttp2_hd_deflate_del(nghttp2_hd_deflater *deflater);
+
+/**
+ * @function
+ *
+ * Changes header table size of the |deflater| to
+ * |settings_hd_table_bufsize_max| bytes.  This may trigger eviction
+ * in the dynamic table.
+ *
+ * The |settings_hd_table_bufsize_max| should be the value received in
+ * SETTINGS_HEADER_TABLE_SIZE.
+ *
+ * The deflater never uses more memory than
+ * ``deflate_hd_table_bufsize_max`` bytes specified in
+ * `nghttp2_hd_deflate_new()`.  Therefore, if
+ * |settings_hd_table_bufsize_max| > ``deflate_hd_table_bufsize_max``,
+ * resulting maximum table size becomes
+ * ``deflate_hd_table_bufsize_max``.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ */
+NGHTTP2_EXTERN int
+nghttp2_hd_deflate_change_table_size(nghttp2_hd_deflater *deflater,
+                                     size_t settings_hd_table_bufsize_max);
+
+/**
+ * @function
+ *
+ * Deflates the |nva|, which has the |nvlen| name/value pairs, into
+ * the |buf| of length |buflen|.
+ *
+ * If |buf| is not large enough to store the deflated header block,
+ * this function fails with :enum:`NGHTTP2_ERR_INSUFF_BUFSIZE`.  The
+ * caller should use `nghttp2_hd_deflate_bound()` to know the upper
+ * bound of buffer size required to deflate given header name/value
+ * pairs.
+ *
+ * Once this function fails, subsequent call of this function always
+ * returns :enum:`NGHTTP2_ERR_HEADER_COMP`.
+ *
+ * After this function returns, it is safe to delete the |nva|.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ * :enum:`NGHTTP2_ERR_HEADER_COMP`
+ *     Deflation process has failed.
+ * :enum:`NGHTTP2_ERR_INSUFF_BUFSIZE`
+ *     The provided |buflen| size is too small to hold the output.
+ */
+NGHTTP2_EXTERN ssize_t
+nghttp2_hd_deflate_hd(nghttp2_hd_deflater *deflater, uint8_t *buf,
+                      size_t buflen, const nghttp2_nv *nva, size_t nvlen);
+
+/**
+ * @function
+ *
+ * Returns an upper bound on the compressed size after deflation of
+ * |nva| of length |nvlen|.
+ */
+NGHTTP2_EXTERN size_t nghttp2_hd_deflate_bound(nghttp2_hd_deflater *deflater,
+                                               const nghttp2_nv *nva,
+                                               size_t nvlen);
+
+/**
+ * @function
+ *
+ * Returns the number of entries that header table of |deflater|
+ * contains.  This is the sum of the number of static table and
+ * dynamic table, so the return value is at least 61.
+ */
+NGHTTP2_EXTERN
+size_t nghttp2_hd_deflate_get_num_table_entries(nghttp2_hd_deflater *deflater);
+
+/**
+ * @function
+ *
+ * Returns the table entry denoted by |idx| from header table of
+ * |deflater|.  The |idx| is 1-based, and idx=1 returns first entry of
+ * static table.  idx=62 returns first entry of dynamic table if it
+ * exists.  Specifying idx=0 is error, and this function returns NULL.
+ * If |idx| is strictly greater than the number of entries the tables
+ * contain, this function returns NULL.
+ */
+NGHTTP2_EXTERN
+const nghttp2_nv *
+nghttp2_hd_deflate_get_table_entry(nghttp2_hd_deflater *deflater, size_t idx);
+
+/**
+ * @function
+ *
+ * Returns the used dynamic table size, including the overhead 32
+ * bytes per entry described in RFC 7541.
+ */
+NGHTTP2_EXTERN
+size_t nghttp2_hd_deflate_get_dynamic_table_size(nghttp2_hd_deflater *deflater);
+
+/**
+ * @function
+ *
+ * Returns the maximum dynamic table size.
+ */
+NGHTTP2_EXTERN
+size_t
+nghttp2_hd_deflate_get_max_dynamic_table_size(nghttp2_hd_deflater *deflater);
+
+struct nghttp2_hd_inflater;
+
+/**
+ * @struct
+ *
+ * HPACK inflater object.
+ */
+typedef struct nghttp2_hd_inflater nghttp2_hd_inflater;
+
+/**
+ * @function
+ *
+ * Initializes |*inflater_ptr| for inflating name/values pairs.
+ *
+ * If this function fails, |*inflater_ptr| is left untouched.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ */
+NGHTTP2_EXTERN int nghttp2_hd_inflate_new(nghttp2_hd_inflater **inflater_ptr);
+
+/**
+ * @function
+ *
+ * Like `nghttp2_hd_inflate_new()`, but with additional custom memory
+ * allocator specified in the |mem|.
+ *
+ * The |mem| can be ``NULL`` and the call is equivalent to
+ * `nghttp2_hd_inflate_new()`.
+ *
+ * This function does not take ownership |mem|.  The application is
+ * responsible for freeing |mem|.
+ *
+ * The library code does not refer to |mem| pointer after this
+ * function returns, so the application can safely free it.
+ */
+NGHTTP2_EXTERN int nghttp2_hd_inflate_new2(nghttp2_hd_inflater **inflater_ptr,
+                                           nghttp2_mem *mem);
+
+/**
+ * @function
+ *
+ * Deallocates any resources allocated for |inflater|.
+ */
+NGHTTP2_EXTERN void nghttp2_hd_inflate_del(nghttp2_hd_inflater *inflater);
+
+/**
+ * @function
+ *
+ * Changes header table size in the |inflater|.  This may trigger
+ * eviction in the dynamic table.
+ *
+ * The |settings_hd_table_bufsize_max| should be the value transmitted
+ * in SETTINGS_HEADER_TABLE_SIZE.
+ *
+ * This function must not be called while header block is being
+ * inflated.  In other words, this function must be called after
+ * initialization of |inflater|, but before calling
+ * `nghttp2_hd_inflate_hd2()`, or after
+ * `nghttp2_hd_inflate_end_headers()`.  Otherwise,
+ * `NGHTTP2_ERR_INVALID_STATE` was returned.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ * :enum:`NGHTTP2_ERR_INVALID_STATE`
+ *     The function is called while header block is being inflated.
+ *     Probably, application missed to call
+ *     `nghttp2_hd_inflate_end_headers()`.
+ */
+NGHTTP2_EXTERN int
+nghttp2_hd_inflate_change_table_size(nghttp2_hd_inflater *inflater,
+                                     size_t settings_hd_table_bufsize_max);
+
+/**
+ * @enum
+ *
+ * The flags for header inflation.
+ */
+typedef enum {
+  /**
+   * No flag set.
+   */
+  NGHTTP2_HD_INFLATE_NONE = 0,
+  /**
+   * Indicates all headers were inflated.
+   */
+  NGHTTP2_HD_INFLATE_FINAL = 0x01,
+  /**
+   * Indicates a header was emitted.
+   */
+  NGHTTP2_HD_INFLATE_EMIT = 0x02
+} nghttp2_hd_inflate_flag;
+
+/**
+ * @function
+ *
+ * .. warning::
+ *
+ *   Deprecated.  Use `nghttp2_hd_inflate_hd2()` instead.
+ *
+ * Inflates name/value block stored in |in| with length |inlen|.  This
+ * function performs decompression.  For each successful emission of
+ * header name/value pair, :enum:`NGHTTP2_HD_INFLATE_EMIT` is set in
+ * |*inflate_flags| and name/value pair is assigned to the |nv_out|
+ * and the function returns.  The caller must not free the members of
+ * |nv_out|.
+ *
+ * The |nv_out| may include pointers to the memory region in the |in|.
+ * The caller must retain the |in| while the |nv_out| is used.
+ *
+ * The application should call this function repeatedly until the
+ * ``(*inflate_flags) & NGHTTP2_HD_INFLATE_FINAL`` is nonzero and
+ * return value is non-negative.  This means the all input values are
+ * processed successfully.  Then the application must call
+ * `nghttp2_hd_inflate_end_headers()` to prepare for the next header
+ * block input.
+ *
+ * The caller can feed complete compressed header block.  It also can
+ * feed it in several chunks.  The caller must set |in_final| to
+ * nonzero if the given input is the last block of the compressed
+ * header.
+ *
+ * This function returns the number of bytes processed if it succeeds,
+ * or one of the following negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ * :enum:`NGHTTP2_ERR_HEADER_COMP`
+ *     Inflation process has failed.
+ * :enum:`NGHTTP2_ERR_BUFFER_ERROR`
+ *     The header field name or value is too large.
+ *
+ * Example follows::
+ *
+ *     int inflate_header_block(nghttp2_hd_inflater *hd_inflater,
+ *                              uint8_t *in, size_t inlen, int final)
+ *     {
+ *         ssize_t rv;
+ *
+ *         for(;;) {
+ *             nghttp2_nv nv;
+ *             int inflate_flags = 0;
+ *
+ *             rv = nghttp2_hd_inflate_hd(hd_inflater, &nv, &inflate_flags,
+ *                                        in, inlen, final);
+ *
+ *             if(rv < 0) {
+ *                 fprintf(stderr, "inflate failed with error code %zd", rv);
+ *                 return -1;
+ *             }
+ *
+ *             in += rv;
+ *             inlen -= rv;
+ *
+ *             if(inflate_flags & NGHTTP2_HD_INFLATE_EMIT) {
+ *                 fwrite(nv.name, nv.namelen, 1, stderr);
+ *                 fprintf(stderr, ": ");
+ *                 fwrite(nv.value, nv.valuelen, 1, stderr);
+ *                 fprintf(stderr, "\n");
+ *             }
+ *             if(inflate_flags & NGHTTP2_HD_INFLATE_FINAL) {
+ *                 nghttp2_hd_inflate_end_headers(hd_inflater);
+ *                 break;
+ *             }
+ *             if((inflate_flags & NGHTTP2_HD_INFLATE_EMIT) == 0 &&
+ *                inlen == 0) {
+ *                break;
+ *             }
+ *         }
+ *
+ *         return 0;
+ *     }
+ *
+ */
+NGHTTP2_EXTERN ssize_t nghttp2_hd_inflate_hd(nghttp2_hd_inflater *inflater,
+                                             nghttp2_nv *nv_out,
+                                             int *inflate_flags, uint8_t *in,
+                                             size_t inlen, int in_final);
+
+/**
+ * @function
+ *
+ * Inflates name/value block stored in |in| with length |inlen|.  This
+ * function performs decompression.  For each successful emission of
+ * header name/value pair, :enum:`NGHTTP2_HD_INFLATE_EMIT` is set in
+ * |*inflate_flags| and name/value pair is assigned to the |nv_out|
+ * and the function returns.  The caller must not free the members of
+ * |nv_out|.
+ *
+ * The |nv_out| may include pointers to the memory region in the |in|.
+ * The caller must retain the |in| while the |nv_out| is used.
+ *
+ * The application should call this function repeatedly until the
+ * ``(*inflate_flags) & NGHTTP2_HD_INFLATE_FINAL`` is nonzero and
+ * return value is non-negative.  This means the all input values are
+ * processed successfully.  Then the application must call
+ * `nghttp2_hd_inflate_end_headers()` to prepare for the next header
+ * block input.
+ *
+ * The caller can feed complete compressed header block.  It also can
+ * feed it in several chunks.  The caller must set |in_final| to
+ * nonzero if the given input is the last block of the compressed
+ * header.
+ *
+ * This function returns the number of bytes processed if it succeeds,
+ * or one of the following negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ * :enum:`NGHTTP2_ERR_HEADER_COMP`
+ *     Inflation process has failed.
+ * :enum:`NGHTTP2_ERR_BUFFER_ERROR`
+ *     The header field name or value is too large.
+ *
+ * Example follows::
+ *
+ *     int inflate_header_block(nghttp2_hd_inflater *hd_inflater,
+ *                              uint8_t *in, size_t inlen, int final)
+ *     {
+ *         ssize_t rv;
+ *
+ *         for(;;) {
+ *             nghttp2_nv nv;
+ *             int inflate_flags = 0;
+ *
+ *             rv = nghttp2_hd_inflate_hd2(hd_inflater, &nv, &inflate_flags,
+ *                                         in, inlen, final);
+ *
+ *             if(rv < 0) {
+ *                 fprintf(stderr, "inflate failed with error code %zd", rv);
+ *                 return -1;
+ *             }
+ *
+ *             in += rv;
+ *             inlen -= rv;
+ *
+ *             if(inflate_flags & NGHTTP2_HD_INFLATE_EMIT) {
+ *                 fwrite(nv.name, nv.namelen, 1, stderr);
+ *                 fprintf(stderr, ": ");
+ *                 fwrite(nv.value, nv.valuelen, 1, stderr);
+ *                 fprintf(stderr, "\n");
+ *             }
+ *             if(inflate_flags & NGHTTP2_HD_INFLATE_FINAL) {
+ *                 nghttp2_hd_inflate_end_headers(hd_inflater);
+ *                 break;
+ *             }
+ *             if((inflate_flags & NGHTTP2_HD_INFLATE_EMIT) == 0 &&
+ *                inlen == 0) {
+ *                break;
+ *             }
+ *         }
+ *
+ *         return 0;
+ *     }
+ *
+ */
+NGHTTP2_EXTERN ssize_t
+nghttp2_hd_inflate_hd2(nghttp2_hd_inflater *inflater, nghttp2_nv *nv_out,
+                       int *inflate_flags, const uint8_t *in, size_t inlen,
+                       int in_final);
+
+/**
+ * @function
+ *
+ * Signals the end of decompression for one header block.
+ *
+ * This function returns 0 if it succeeds. Currently this function
+ * always succeeds.
+ */
+NGHTTP2_EXTERN int
+nghttp2_hd_inflate_end_headers(nghttp2_hd_inflater *inflater);
+
+/**
+ * @function
+ *
+ * Returns the number of entries that header table of |inflater|
+ * contains.  This is the sum of the number of static table and
+ * dynamic table, so the return value is at least 61.
+ */
+NGHTTP2_EXTERN
+size_t nghttp2_hd_inflate_get_num_table_entries(nghttp2_hd_inflater *inflater);
+
+/**
+ * @function
+ *
+ * Returns the table entry denoted by |idx| from header table of
+ * |inflater|.  The |idx| is 1-based, and idx=1 returns first entry of
+ * static table.  idx=62 returns first entry of dynamic table if it
+ * exists.  Specifying idx=0 is error, and this function returns NULL.
+ * If |idx| is strictly greater than the number of entries the tables
+ * contain, this function returns NULL.
+ */
+NGHTTP2_EXTERN
+const nghttp2_nv *
+nghttp2_hd_inflate_get_table_entry(nghttp2_hd_inflater *inflater, size_t idx);
+
+/**
+ * @function
+ *
+ * Returns the used dynamic table size, including the overhead 32
+ * bytes per entry described in RFC 7541.
+ */
+NGHTTP2_EXTERN
+size_t nghttp2_hd_inflate_get_dynamic_table_size(nghttp2_hd_inflater *inflater);
+
+/**
+ * @function
+ *
+ * Returns the maximum dynamic table size.
+ */
+NGHTTP2_EXTERN
+size_t
+nghttp2_hd_inflate_get_max_dynamic_table_size(nghttp2_hd_inflater *inflater);
+
+struct nghttp2_stream;
+
+/**
+ * @struct
+ *
+ * The structure to represent HTTP/2 stream.  The details of this
+ * structure are intentionally hidden from the public API.
+ */
+typedef struct nghttp2_stream nghttp2_stream;
+
+/**
+ * @function
+ *
+ * Returns pointer to :type:`nghttp2_stream` object denoted by
+ * |stream_id|.  If stream was not found, returns NULL.
+ *
+ * Returns imaginary root stream (see
+ * `nghttp2_session_get_root_stream()`) if 0 is given in |stream_id|.
+ *
+ * Unless |stream_id| == 0, the returned pointer is valid until next
+ * call of `nghttp2_session_send()`, `nghttp2_session_mem_send()`,
+ * `nghttp2_session_recv()`, and `nghttp2_session_mem_recv()`.
+ */
+NGHTTP2_EXTERN nghttp2_stream *
+nghttp2_session_find_stream(nghttp2_session *session, int32_t stream_id);
+
+/**
+ * @enum
+ *
+ * State of stream as described in RFC 7540.
+ */
+typedef enum {
+  /**
+   * idle state.
+   */
+  NGHTTP2_STREAM_STATE_IDLE = 1,
+  /**
+   * open state.
+   */
+  NGHTTP2_STREAM_STATE_OPEN,
+  /**
+   * reserved (local) state.
+   */
+  NGHTTP2_STREAM_STATE_RESERVED_LOCAL,
+  /**
+   * reserved (remote) state.
+   */
+  NGHTTP2_STREAM_STATE_RESERVED_REMOTE,
+  /**
+   * half closed (local) state.
+   */
+  NGHTTP2_STREAM_STATE_HALF_CLOSED_LOCAL,
+  /**
+   * half closed (remote) state.
+   */
+  NGHTTP2_STREAM_STATE_HALF_CLOSED_REMOTE,
+  /**
+   * closed state.
+   */
+  NGHTTP2_STREAM_STATE_CLOSED
+} nghttp2_stream_proto_state;
+
+/**
+ * @function
+ *
+ * Returns state of |stream|.  The root stream retrieved by
+ * `nghttp2_session_get_root_stream()` will have stream state
+ * :enum:`NGHTTP2_STREAM_STATE_IDLE`.
+ */
+NGHTTP2_EXTERN nghttp2_stream_proto_state
+nghttp2_stream_get_state(nghttp2_stream *stream);
+
+/**
+ * @function
+ *
+ * Returns root of dependency tree, which is imaginary stream with
+ * stream ID 0.  The returned pointer is valid until |session| is
+ * freed by `nghttp2_session_del()`.
+ */
+NGHTTP2_EXTERN nghttp2_stream *
+nghttp2_session_get_root_stream(nghttp2_session *session);
+
+/**
+ * @function
+ *
+ * Returns the parent stream of |stream| in dependency tree.  Returns
+ * NULL if there is no such stream.
+ */
+NGHTTP2_EXTERN nghttp2_stream *
+nghttp2_stream_get_parent(nghttp2_stream *stream);
+
+NGHTTP2_EXTERN int32_t nghttp2_stream_get_stream_id(nghttp2_stream *stream);
+
+/**
+ * @function
+ *
+ * Returns the next sibling stream of |stream| in dependency tree.
+ * Returns NULL if there is no such stream.
+ */
+NGHTTP2_EXTERN nghttp2_stream *
+nghttp2_stream_get_next_sibling(nghttp2_stream *stream);
+
+/**
+ * @function
+ *
+ * Returns the previous sibling stream of |stream| in dependency tree.
+ * Returns NULL if there is no such stream.
+ */
+NGHTTP2_EXTERN nghttp2_stream *
+nghttp2_stream_get_previous_sibling(nghttp2_stream *stream);
+
+/**
+ * @function
+ *
+ * Returns the first child stream of |stream| in dependency tree.
+ * Returns NULL if there is no such stream.
+ */
+NGHTTP2_EXTERN nghttp2_stream *
+nghttp2_stream_get_first_child(nghttp2_stream *stream);
+
+/**
+ * @function
+ *
+ * Returns dependency weight to the parent stream of |stream|.
+ */
+NGHTTP2_EXTERN int32_t nghttp2_stream_get_weight(nghttp2_stream *stream);
+
+/**
+ * @function
+ *
+ * Returns the sum of the weight for |stream|'s children.
+ */
+NGHTTP2_EXTERN int32_t
+nghttp2_stream_get_sum_dependency_weight(nghttp2_stream *stream);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NGHTTP2_H */
diff --git a/tools/sdk/include/nghttp/nghttp2/nghttp2ver.h b/tools/sdk/include/nghttp/nghttp2/nghttp2ver.h
new file mode 100644
index 00000000..a12cb708
--- /dev/null
+++ b/tools/sdk/include/nghttp/nghttp2/nghttp2ver.h
@@ -0,0 +1,42 @@
+/*
+ * nghttp2 - HTTP/2 C Library
+ *
+ * Copyright (c) 2012, 2013 Tatsuhiro Tsujikawa
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NGHTTP2VER_H
+#define NGHTTP2VER_H
+
+/**
+ * @macro
+ * Version number of the nghttp2 library release
+ */
+#define NGHTTP2_VERSION "@PACKAGE_VERSION@"
+
+/**
+ * @macro
+ * Numerical representation of the version number of the nghttp2 library
+ * release. This is a 24 bit number with 8 bits for major number, 8 bits
+ * for minor and 8 bits for patch. Version 1.2.3 becomes 0x010203.
+ */
+#define NGHTTP2_VERSION_NUM 0x010203
+
+#endif /* NGHTTP2VER_H */
diff --git a/tools/sdk/include/nghttp/nghttp2_buf.h b/tools/sdk/include/nghttp/nghttp2_buf.h
new file mode 100644
index 00000000..6770d6f3
--- /dev/null
+++ b/tools/sdk/include/nghttp/nghttp2_buf.h
@@ -0,0 +1,388 @@
+/*
+ * nghttp2 - HTTP/2 C Library
+ *
+ * Copyright (c) 2014 Tatsuhiro Tsujikawa
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NGHTTP2_BUF_H
+#define NGHTTP2_BUF_H
+
+#ifdef HAVE_CONFIG_H
+#include 
+#endif /* HAVE_CONFIG_H */
+
+#include 
+
+#include "nghttp2_int.h"
+#include "nghttp2_mem.h"
+
+typedef struct {
+  /* This points to the beginning of the buffer. The effective range
+     of buffer is [begin, end). */
+  uint8_t *begin;
+  /* This points to the memory one byte beyond the end of the
+     buffer. */
+  uint8_t *end;
+  /* The position indicator for effective start of the buffer. pos <=
+     last must be hold. */
+  uint8_t *pos;
+  /* The position indicator for effective one beyond of the end of the
+     buffer. last <= end must be hold. */
+  uint8_t *last;
+  /* Mark arbitrary position in buffer [begin, end) */
+  uint8_t *mark;
+} nghttp2_buf;
+
+#define nghttp2_buf_len(BUF) ((size_t)((BUF)->last - (BUF)->pos))
+#define nghttp2_buf_avail(BUF) ((size_t)((BUF)->end - (BUF)->last))
+#define nghttp2_buf_mark_avail(BUF) ((size_t)((BUF)->mark - (BUF)->last))
+#define nghttp2_buf_cap(BUF) ((size_t)((BUF)->end - (BUF)->begin))
+
+#define nghttp2_buf_pos_offset(BUF) ((size_t)((BUF)->pos - (BUF)->begin))
+#define nghttp2_buf_last_offset(BUF) ((size_t)((BUF)->last - (BUF)->begin))
+
+#define nghttp2_buf_shift_right(BUF, AMT)                                      \
+  do {                                                                         \
+    (BUF)->pos += AMT;                                                         \
+    (BUF)->last += AMT;                                                        \
+  } while (0)
+
+#define nghttp2_buf_shift_left(BUF, AMT)                                       \
+  do {                                                                         \
+    (BUF)->pos -= AMT;                                                         \
+    (BUF)->last -= AMT;                                                        \
+  } while (0)
+
+/*
+ * Initializes the |buf|. No memory is allocated in this function. Use
+ * nghttp2_buf_reserve() to allocate memory.
+ */
+void nghttp2_buf_init(nghttp2_buf *buf);
+
+/*
+ * Initializes the |buf| and allocates at least |initial| bytes of
+ * memory.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory
+ */
+int nghttp2_buf_init2(nghttp2_buf *buf, size_t initial, nghttp2_mem *mem);
+
+/*
+ * Frees buffer in |buf|.
+ */
+void nghttp2_buf_free(nghttp2_buf *buf, nghttp2_mem *mem);
+
+/*
+ * Extends buffer so that nghttp2_buf_cap() returns at least
+ * |new_cap|. If extensions took place, buffer pointers in |buf| will
+ * change.
+ *
+ * This function returns 0 if it succeeds, or one of the followings
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory
+ */
+int nghttp2_buf_reserve(nghttp2_buf *buf, size_t new_cap, nghttp2_mem *mem);
+
+/*
+ * Resets pos, last, mark member of |buf| to buf->begin.
+ */
+void nghttp2_buf_reset(nghttp2_buf *buf);
+
+/*
+ * Initializes |buf| using supplied buffer |begin| of length
+ * |len|. Semantically, the application should not call *_reserve() or
+ * nghttp2_free() functions for |buf|.
+ */
+void nghttp2_buf_wrap_init(nghttp2_buf *buf, uint8_t *begin, size_t len);
+
+struct nghttp2_buf_chain;
+
+typedef struct nghttp2_buf_chain nghttp2_buf_chain;
+
+/* Chains 2 buffers */
+struct nghttp2_buf_chain {
+  /* Points to the subsequent buffer. NULL if there is no such
+     buffer. */
+  nghttp2_buf_chain *next;
+  nghttp2_buf buf;
+};
+
+typedef struct {
+  /* Points to the first buffer */
+  nghttp2_buf_chain *head;
+  /* Buffer pointer where write occurs. */
+  nghttp2_buf_chain *cur;
+  /* Memory allocator */
+  nghttp2_mem *mem;
+  /* The buffer capacity of each buf */
+  size_t chunk_length;
+  /* The maximum number of nghttp2_buf_chain */
+  size_t max_chunk;
+  /* The number of nghttp2_buf_chain allocated */
+  size_t chunk_used;
+  /* The number of nghttp2_buf_chain to keep on reset */
+  size_t chunk_keep;
+  /* pos offset from begin in each buffers. On initialization and
+     reset, buf->pos and buf->last are positioned at buf->begin +
+     offset. */
+  size_t offset;
+} nghttp2_bufs;
+
+/*
+ * This is the same as calling nghttp2_bufs_init2 with the given
+ * arguments and offset = 0.
+ */
+int nghttp2_bufs_init(nghttp2_bufs *bufs, size_t chunk_length, size_t max_chunk,
+                      nghttp2_mem *mem);
+
+/*
+ * This is the same as calling nghttp2_bufs_init3 with the given
+ * arguments and chunk_keep = max_chunk.
+ */
+int nghttp2_bufs_init2(nghttp2_bufs *bufs, size_t chunk_length,
+                       size_t max_chunk, size_t offset, nghttp2_mem *mem);
+
+/*
+ * Initializes |bufs|. Each buffer size is given in the
+ * |chunk_length|.  The maximum number of buffers is given in the
+ * |max_chunk|.  On reset, first |chunk_keep| buffers are kept and
+ * remaining buffers are deleted.  Each buffer will have bufs->pos and
+ * bufs->last shifted to left by |offset| bytes on creation and reset.
+ *
+ * This function allocates first buffer.  bufs->head and bufs->cur
+ * will point to the first buffer after this call.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory.
+ * NGHTTP2_ERR_INVALID_ARGUMENT
+ *     chunk_keep is 0; or max_chunk < chunk_keep; or offset is too
+ *     long.
+ */
+int nghttp2_bufs_init3(nghttp2_bufs *bufs, size_t chunk_length,
+                       size_t max_chunk, size_t chunk_keep, size_t offset,
+                       nghttp2_mem *mem);
+
+/*
+ * Frees any related resources to the |bufs|.
+ */
+void nghttp2_bufs_free(nghttp2_bufs *bufs);
+
+/*
+ * Initializes |bufs| using supplied buffer |begin| of length |len|.
+ * The first buffer bufs->head uses buffer |begin|.  The buffer size
+ * is fixed and no allocate extra chunk buffer is allocated.  In other
+ * words, max_chunk = chunk_keep = 1.  To free the resource allocated
+ * for |bufs|, use nghttp2_bufs_wrap_free().
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory.
+ */
+int nghttp2_bufs_wrap_init(nghttp2_bufs *bufs, uint8_t *begin, size_t len,
+                           nghttp2_mem *mem);
+
+/*
+ * Frees any related resource to the |bufs|.  This function does not
+ * free supplied buffer provided in nghttp2_bufs_wrap_init().
+ */
+void nghttp2_bufs_wrap_free(nghttp2_bufs *bufs);
+
+/*
+ * Reallocates internal buffer using |chunk_length|.  The max_chunk,
+ * chunk_keep and offset do not change.  After successful allocation
+ * of new buffer, previous buffers are deallocated without copying
+ * anything into new buffers.  chunk_used is reset to 1.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory.
+ * NGHTTP2_ERR_INVALID_ARGUMENT
+ *     chunk_length < offset
+ */
+int nghttp2_bufs_realloc(nghttp2_bufs *bufs, size_t chunk_length);
+
+/*
+ * Appends the |data| of length |len| to the |bufs|. The write starts
+ * at bufs->cur->buf.last. A new buffers will be allocated to store
+ * all data.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory.
+ * NGHTTP2_ERR_BUFFER_ERROR
+ *     Out of buffer space.
+ */
+int nghttp2_bufs_add(nghttp2_bufs *bufs, const void *data, size_t len);
+
+/*
+ * Appends a single byte |b| to the |bufs|. The write starts at
+ * bufs->cur->buf.last. A new buffers will be allocated to store all
+ * data.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory.
+ * NGHTTP2_ERR_BUFFER_ERROR
+ *     Out of buffer space.
+ */
+int nghttp2_bufs_addb(nghttp2_bufs *bufs, uint8_t b);
+
+/*
+ * Behaves like nghttp2_bufs_addb(), but this does not update
+ * buf->last pointer.
+ */
+int nghttp2_bufs_addb_hold(nghttp2_bufs *bufs, uint8_t b);
+
+#define nghttp2_bufs_fast_addb(BUFS, B)                                        \
+  do {                                                                         \
+    *(BUFS)->cur->buf.last++ = B;                                              \
+  } while (0)
+
+#define nghttp2_bufs_fast_addb_hold(BUFS, B)                                   \
+  do {                                                                         \
+    *(BUFS)->cur->buf.last = B;                                                \
+  } while (0)
+
+/*
+ * Performs bitwise-OR of |b| at bufs->cur->buf.last. A new buffers
+ * will be allocated if necessary.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory.
+ * NGHTTP2_ERR_BUFFER_ERROR
+ *     Out of buffer space.
+ */
+int nghttp2_bufs_orb(nghttp2_bufs *bufs, uint8_t b);
+
+/*
+ * Behaves like nghttp2_bufs_orb(), but does not update buf->last
+ * pointer.
+ */
+int nghttp2_bufs_orb_hold(nghttp2_bufs *bufs, uint8_t b);
+
+#define nghttp2_bufs_fast_orb(BUFS, B)                                         \
+  do {                                                                         \
+    uint8_t **p = &(BUFS)->cur->buf.last;                                      \
+    **p = (uint8_t)(**p | (B));                                                \
+    ++(*p);                                                                    \
+  } while (0)
+
+#define nghttp2_bufs_fast_orb_hold(BUFS, B)                                    \
+  do {                                                                         \
+    uint8_t *p = (BUFS)->cur->buf.last;                                        \
+    *p = (uint8_t)(*p | (B));                                                  \
+  } while (0)
+
+/*
+ * Copies all data stored in |bufs| to the contiguous buffer.  This
+ * function allocates the contiguous memory to store all data in
+ * |bufs| and assigns it to |*out|.
+ *
+ * The contents of |bufs| is left unchanged.
+ *
+ * This function returns the length of copied data and assigns the
+ * pointer to copied data to |*out| if it succeeds, or one of the
+ * following negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory
+ */
+ssize_t nghttp2_bufs_remove(nghttp2_bufs *bufs, uint8_t **out);
+
+/*
+ * Copies all data stored in |bufs| to |out|.  This function assumes
+ * that the buffer space pointed by |out| has at least
+ * nghttp2_bufs(bufs) bytes.
+ *
+ * The contents of |bufs| is left unchanged.
+ *
+ * This function returns the length of copied data.
+ */
+size_t nghttp2_bufs_remove_copy(nghttp2_bufs *bufs, uint8_t *out);
+
+/*
+ * Resets |bufs| and makes the buffers empty.
+ */
+void nghttp2_bufs_reset(nghttp2_bufs *bufs);
+
+/*
+ * Moves bufs->cur to bufs->cur->next.  If resulting bufs->cur is
+ * NULL, this function allocates new buffers and bufs->cur points to
+ * it.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory
+ * NGHTTP2_ERR_BUFFER_ERROR
+ *     Out of buffer space.
+ */
+int nghttp2_bufs_advance(nghttp2_bufs *bufs);
+
+/* Sets bufs->cur to bufs->head */
+#define nghttp2_bufs_rewind(BUFS)                                              \
+  do {                                                                         \
+    (BUFS)->cur = (BUFS)->head;                                                \
+  } while (0)
+
+/*
+ * Move bufs->cur, from the current position, using next member, to
+ * the last buf which has nghttp2_buf_len(buf) > 0 without seeing buf
+ * which satisfies nghttp2_buf_len(buf) == 0.  If
+ * nghttp2_buf_len(&bufs->cur->buf) == 0 or bufs->cur->next is NULL,
+ * bufs->cur is unchanged.
+ */
+void nghttp2_bufs_seek_last_present(nghttp2_bufs *bufs);
+
+/*
+ * Returns nonzero if bufs->cur->next is not emtpy.
+ */
+int nghttp2_bufs_next_present(nghttp2_bufs *bufs);
+
+#define nghttp2_bufs_cur_avail(BUFS) nghttp2_buf_avail(&(BUFS)->cur->buf)
+
+/*
+ * Returns the buffer length of |bufs|.
+ */
+size_t nghttp2_bufs_len(nghttp2_bufs *bufs);
+
+#endif /* NGHTTP2_BUF_H */
diff --git a/tools/sdk/include/nghttp/nghttp2_callbacks.h b/tools/sdk/include/nghttp/nghttp2_callbacks.h
new file mode 100644
index 00000000..5f08474a
--- /dev/null
+++ b/tools/sdk/include/nghttp/nghttp2_callbacks.h
@@ -0,0 +1,117 @@
+/*
+ * nghttp2 - HTTP/2 C Library
+ *
+ * Copyright (c) 2014 Tatsuhiro Tsujikawa
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NGHTTP2_CALLBACKS_H
+#define NGHTTP2_CALLBACKS_H
+
+#ifdef HAVE_CONFIG_H
+#include 
+#endif /* HAVE_CONFIG_H */
+
+#include 
+
+/*
+ * Callback functions.
+ */
+struct nghttp2_session_callbacks {
+  /**
+   * Callback function invoked when the session wants to send data to
+   * the remote peer.  This callback is not necessary if the
+   * application uses solely `nghttp2_session_mem_send()` to serialize
+   * data to transmit.
+   */
+  nghttp2_send_callback send_callback;
+  /**
+   * Callback function invoked when the session wants to receive data
+   * from the remote peer.  This callback is not necessary if the
+   * application uses solely `nghttp2_session_mem_recv()` to process
+   * received data.
+   */
+  nghttp2_recv_callback recv_callback;
+  /**
+   * Callback function invoked by `nghttp2_session_recv()` when a
+   * frame is received.
+   */
+  nghttp2_on_frame_recv_callback on_frame_recv_callback;
+  /**
+   * Callback function invoked by `nghttp2_session_recv()` when an
+   * invalid non-DATA frame is received.
+   */
+  nghttp2_on_invalid_frame_recv_callback on_invalid_frame_recv_callback;
+  /**
+   * Callback function invoked when a chunk of data in DATA frame is
+   * received.
+   */
+  nghttp2_on_data_chunk_recv_callback on_data_chunk_recv_callback;
+  /**
+   * Callback function invoked before a non-DATA frame is sent.
+   */
+  nghttp2_before_frame_send_callback before_frame_send_callback;
+  /**
+   * Callback function invoked after a frame is sent.
+   */
+  nghttp2_on_frame_send_callback on_frame_send_callback;
+  /**
+   * The callback function invoked when a non-DATA frame is not sent
+   * because of an error.
+   */
+  nghttp2_on_frame_not_send_callback on_frame_not_send_callback;
+  /**
+   * Callback function invoked when the stream is closed.
+   */
+  nghttp2_on_stream_close_callback on_stream_close_callback;
+  /**
+   * Callback function invoked when the reception of header block in
+   * HEADERS or PUSH_PROMISE is started.
+   */
+  nghttp2_on_begin_headers_callback on_begin_headers_callback;
+  /**
+   * Callback function invoked when a header name/value pair is
+   * received.
+   */
+  nghttp2_on_header_callback on_header_callback;
+  nghttp2_on_header_callback2 on_header_callback2;
+  /**
+   * Callback function invoked when the library asks application how
+   * many padding bytes are required for the transmission of the given
+   * frame.
+   */
+  nghttp2_select_padding_callback select_padding_callback;
+  /**
+   * The callback function used to determine the length allowed in
+   * `nghttp2_data_source_read_callback()`
+   */
+  nghttp2_data_source_read_length_callback read_length_callback;
+  /**
+   * Sets callback function invoked when a frame header is received.
+   */
+  nghttp2_on_begin_frame_callback on_begin_frame_callback;
+  nghttp2_send_data_callback send_data_callback;
+  nghttp2_pack_extension_callback pack_extension_callback;
+  nghttp2_unpack_extension_callback unpack_extension_callback;
+  nghttp2_on_extension_chunk_recv_callback on_extension_chunk_recv_callback;
+  nghttp2_error_callback error_callback;
+};
+
+#endif /* NGHTTP2_CALLBACKS_H */
diff --git a/tools/sdk/include/nghttp/nghttp2_frame.h b/tools/sdk/include/nghttp/nghttp2_frame.h
new file mode 100644
index 00000000..6493465a
--- /dev/null
+++ b/tools/sdk/include/nghttp/nghttp2_frame.h
@@ -0,0 +1,581 @@
+/*
+ * nghttp2 - HTTP/2 C Library
+ *
+ * Copyright (c) 2012 Tatsuhiro Tsujikawa
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NGHTTP2_FRAME_H
+#define NGHTTP2_FRAME_H
+
+#ifdef HAVE_CONFIG_H
+#include 
+#endif /* HAVE_CONFIG_H */
+
+#include 
+#include "nghttp2_hd.h"
+#include "nghttp2_buf.h"
+
+#define NGHTTP2_STREAM_ID_MASK ((1u << 31) - 1)
+#define NGHTTP2_PRI_GROUP_ID_MASK ((1u << 31) - 1)
+#define NGHTTP2_PRIORITY_MASK ((1u << 31) - 1)
+#define NGHTTP2_WINDOW_SIZE_INCREMENT_MASK ((1u << 31) - 1)
+#define NGHTTP2_SETTINGS_ID_MASK ((1 << 24) - 1)
+
+/* The number of bytes of frame header. */
+#define NGHTTP2_FRAME_HDLEN 9
+
+#define NGHTTP2_MAX_FRAME_SIZE_MAX ((1 << 24) - 1)
+#define NGHTTP2_MAX_FRAME_SIZE_MIN (1 << 14)
+
+#define NGHTTP2_MAX_PAYLOADLEN 8192//16384--LiuHan/0812
+/* The one frame buffer length for tranmission.  We may use several of
+   them to support CONTINUATION.  To account for Pad Length field, we
+   allocate extra 1 byte, which saves extra large memcopying. */
+#define NGHTTP2_FRAMEBUF_CHUNKLEN                                              \
+  (NGHTTP2_FRAME_HDLEN + 1 + NGHTTP2_MAX_PAYLOADLEN)
+
+/* The default length of DATA frame payload. */
+#define NGHTTP2_DATA_PAYLOADLEN NGHTTP2_MAX_FRAME_SIZE_MIN
+
+/* Maximum headers block size to send, calculated using
+   nghttp2_hd_deflate_bound().  This is the default value, and can be
+   overridden by nghttp2_option_set_max_send_header_block_size(). */
+#define NGHTTP2_MAX_HEADERSLEN 65536
+
+/* The number of bytes for each SETTINGS entry */
+#define NGHTTP2_FRAME_SETTINGS_ENTRY_LENGTH 6
+
+/* Length of priority related fields in HEADERS/PRIORITY frames */
+#define NGHTTP2_PRIORITY_SPECLEN 5
+
+/* Maximum length of padding in bytes. */
+#define NGHTTP2_MAX_PADLEN 256
+
+/* Union of extension frame payload */
+typedef union { nghttp2_ext_altsvc altsvc; } nghttp2_ext_frame_payload;
+
+void nghttp2_frame_pack_frame_hd(uint8_t *buf, const nghttp2_frame_hd *hd);
+
+void nghttp2_frame_unpack_frame_hd(nghttp2_frame_hd *hd, const uint8_t *buf);
+
+/**
+ * Initializes frame header |hd| with given parameters.  Reserved bit
+ * is set to 0.
+ */
+void nghttp2_frame_hd_init(nghttp2_frame_hd *hd, size_t length, uint8_t type,
+                           uint8_t flags, int32_t stream_id);
+
+/**
+ * Returns the number of priority field depending on the |flags|.  If
+ * |flags| has neither NGHTTP2_FLAG_PRIORITY_GROUP nor
+ * NGHTTP2_FLAG_PRIORITY_DEPENDENCY set, return 0.
+ */
+size_t nghttp2_frame_priority_len(uint8_t flags);
+
+/**
+ * Packs the |pri_spec| in |buf|.  This function assumes |buf| has
+ * enough space for serialization.
+ */
+void nghttp2_frame_pack_priority_spec(uint8_t *buf,
+                                      const nghttp2_priority_spec *pri_spec);
+
+/**
+ * Unpacks the priority specification from payload |payload| of length
+ * |payloadlen| to |pri_spec|.  The |flags| is used to determine what
+ * kind of priority specification is in |payload|.  This function
+ * assumes the |payload| contains whole priority specification.
+ */
+void nghttp2_frame_unpack_priority_spec(nghttp2_priority_spec *pri_spec,
+                                        uint8_t flags, const uint8_t *payload,
+                                        size_t payloadlen);
+
+/*
+ * Returns the offset from the HEADERS frame payload where the
+ * compressed header block starts. The frame payload does not include
+ * frame header.
+ */
+size_t nghttp2_frame_headers_payload_nv_offset(nghttp2_headers *frame);
+
+/*
+ * Packs HEADERS frame |frame| in wire format and store it in |bufs|.
+ * This function expands |bufs| as necessary to store frame.
+ *
+ * The caller must make sure that nghttp2_bufs_reset(bufs) is called
+ * before calling this function.
+ *
+ * frame->hd.length is assigned after length is determined during
+ * packing process.  CONTINUATION frames are also serialized in this
+ * function. This function does not handle padding.
+ *
+ * This function returns 0 if it succeeds, or returns one of the
+ * following negative error codes:
+ *
+ * NGHTTP2_ERR_HEADER_COMP
+ *     The deflate operation failed.
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory.
+ */
+int nghttp2_frame_pack_headers(nghttp2_bufs *bufs, nghttp2_headers *frame,
+                               nghttp2_hd_deflater *deflater);
+
+/*
+ * Unpacks HEADERS frame byte sequence into |frame|.  This function
+ * only unapcks bytes that come before name/value header block and
+ * after possible Pad Length field.
+ *
+ * This function always succeeds and returns 0.
+ */
+int nghttp2_frame_unpack_headers_payload(nghttp2_headers *frame,
+                                         const uint8_t *payload,
+                                         size_t payloadlen);
+
+/*
+ * Packs PRIORITY frame |frame| in wire format and store it in
+ * |bufs|.
+ *
+ * The caller must make sure that nghttp2_bufs_reset(bufs) is called
+ * before calling this function.
+ *
+ * This function always succeeds and returns 0.
+ */
+int nghttp2_frame_pack_priority(nghttp2_bufs *bufs, nghttp2_priority *frame);
+
+/*
+ * Unpacks PRIORITY wire format into |frame|.
+ */
+void nghttp2_frame_unpack_priority_payload(nghttp2_priority *frame,
+                                           const uint8_t *payload,
+                                           size_t payloadlen);
+
+/*
+ * Packs RST_STREAM frame |frame| in wire frame format and store it in
+ * |bufs|.
+ *
+ * The caller must make sure that nghttp2_bufs_reset(bufs) is called
+ * before calling this function.
+ *
+ * This function always succeeds and returns 0.
+ */
+int nghttp2_frame_pack_rst_stream(nghttp2_bufs *bufs,
+                                  nghttp2_rst_stream *frame);
+
+/*
+ * Unpacks RST_STREAM frame byte sequence into |frame|.
+ */
+void nghttp2_frame_unpack_rst_stream_payload(nghttp2_rst_stream *frame,
+                                             const uint8_t *payload,
+                                             size_t payloadlen);
+
+/*
+ * Packs SETTINGS frame |frame| in wire format and store it in
+ * |bufs|.
+ *
+ * The caller must make sure that nghttp2_bufs_reset(bufs) is called
+ * before calling this function.
+ *
+ * This function returns 0 if it succeeds, or returns one of the
+ * following negative error codes:
+ *
+ * NGHTTP2_ERR_FRAME_SIZE_ERROR
+ *     The length of the frame is too large.
+ */
+int nghttp2_frame_pack_settings(nghttp2_bufs *bufs, nghttp2_settings *frame);
+
+/*
+ * Packs the |iv|, which includes |niv| entries, in the |buf|,
+ * assuming the |buf| has at least 8 * |niv| bytes.
+ *
+ * Returns the number of bytes written into the |buf|.
+ */
+size_t nghttp2_frame_pack_settings_payload(uint8_t *buf,
+                                           const nghttp2_settings_entry *iv,
+                                           size_t niv);
+
+void nghttp2_frame_unpack_settings_entry(nghttp2_settings_entry *iv,
+                                         const uint8_t *payload);
+
+/*
+ * Initializes payload of frame->settings.  The |frame| takes
+ * ownership of |iv|.
+ */
+void nghttp2_frame_unpack_settings_payload(nghttp2_settings *frame,
+                                           nghttp2_settings_entry *iv,
+                                           size_t niv);
+
+/*
+ * Unpacks SETTINGS payload into |*iv_ptr|. The number of entries are
+ * assigned to the |*niv_ptr|. This function allocates enough memory
+ * to store the result in |*iv_ptr|. The caller is responsible to free
+ * |*iv_ptr| after its use.
+ *
+ * This function returns 0 if it succeeds or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory.
+ */
+int nghttp2_frame_unpack_settings_payload2(nghttp2_settings_entry **iv_ptr,
+                                           size_t *niv_ptr,
+                                           const uint8_t *payload,
+                                           size_t payloadlen, nghttp2_mem *mem);
+
+/*
+ * Packs PUSH_PROMISE frame |frame| in wire format and store it in
+ * |bufs|.  This function expands |bufs| as necessary to store
+ * frame.
+ *
+ * The caller must make sure that nghttp2_bufs_reset(bufs) is called
+ * before calling this function.
+ *
+ * frame->hd.length is assigned after length is determined during
+ * packing process.  CONTINUATION frames are also serialized in this
+ * function. This function does not handle padding.
+ *
+ * This function returns 0 if it succeeds, or returns one of the
+ * following negative error codes:
+ *
+ * NGHTTP2_ERR_HEADER_COMP
+ *     The deflate operation failed.
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory.
+ */
+int nghttp2_frame_pack_push_promise(nghttp2_bufs *bufs,
+                                    nghttp2_push_promise *frame,
+                                    nghttp2_hd_deflater *deflater);
+
+/*
+ * Unpacks PUSH_PROMISE frame byte sequence into |frame|.  This
+ * function only unapcks bytes that come before name/value header
+ * block and after possible Pad Length field.
+ *
+ * This function returns 0 if it succeeds or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_PROTO
+ *     TODO END_HEADERS flag is not set
+ */
+int nghttp2_frame_unpack_push_promise_payload(nghttp2_push_promise *frame,
+                                              const uint8_t *payload,
+                                              size_t payloadlen);
+
+/*
+ * Packs PING frame |frame| in wire format and store it in
+ * |bufs|.
+ *
+ * The caller must make sure that nghttp2_bufs_reset(bufs) is called
+ * before calling this function.
+ *
+ * This function always succeeds and returns 0.
+ */
+int nghttp2_frame_pack_ping(nghttp2_bufs *bufs, nghttp2_ping *frame);
+
+/*
+ * Unpacks PING wire format into |frame|.
+ */
+void nghttp2_frame_unpack_ping_payload(nghttp2_ping *frame,
+                                       const uint8_t *payload,
+                                       size_t payloadlen);
+
+/*
+ * Packs GOAWAY frame |frame| in wire format and store it in |bufs|.
+ * This function expands |bufs| as necessary to store frame.
+ *
+ * The caller must make sure that nghttp2_bufs_reset(bufs) is called
+ * before calling this function.
+ *
+ * This function returns 0 if it succeeds or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory.
+ * NGHTTP2_ERR_FRAME_SIZE_ERROR
+ *     The length of the frame is too large.
+ */
+int nghttp2_frame_pack_goaway(nghttp2_bufs *bufs, nghttp2_goaway *frame);
+
+/*
+ * Unpacks GOAWAY wire format into |frame|.  The |payload| of length
+ * |payloadlen| contains first 8 bytes of payload.  The
+ * |var_gift_payload| of length |var_gift_payloadlen| contains
+ * remaining payload and its buffer is gifted to the function and then
+ * |frame|.  The |var_gift_payloadlen| must be freed by
+ * nghttp2_frame_goaway_free().
+ */
+void nghttp2_frame_unpack_goaway_payload(nghttp2_goaway *frame,
+                                         const uint8_t *payload,
+                                         size_t payloadlen,
+                                         uint8_t *var_gift_payload,
+                                         size_t var_gift_payloadlen);
+
+/*
+ * Unpacks GOAWAY wire format into |frame|.  This function only exists
+ * for unit test.  After allocating buffer for debug data, this
+ * function internally calls nghttp2_frame_unpack_goaway_payload().
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory.
+ */
+int nghttp2_frame_unpack_goaway_payload2(nghttp2_goaway *frame,
+                                         const uint8_t *payload,
+                                         size_t payloadlen, nghttp2_mem *mem);
+
+/*
+ * Packs WINDOW_UPDATE frame |frame| in wire frame format and store it
+ * in |bufs|.
+ *
+ * The caller must make sure that nghttp2_bufs_reset(bufs) is called
+ * before calling this function.
+ *
+ * This function always succeeds and returns 0.
+ */
+int nghttp2_frame_pack_window_update(nghttp2_bufs *bufs,
+                                     nghttp2_window_update *frame);
+
+/*
+ * Unpacks WINDOW_UPDATE frame byte sequence into |frame|.
+ */
+void nghttp2_frame_unpack_window_update_payload(nghttp2_window_update *frame,
+                                                const uint8_t *payload,
+                                                size_t payloadlen);
+
+/*
+ * Packs ALTSVC frame |frame| in wire frame format and store it in
+ * |bufs|.
+ *
+ * The caller must make sure that nghttp2_bufs_reset(bufs) is called
+ * before calling this function.
+ *
+ * This function always succeeds and returns 0.
+ */
+int nghttp2_frame_pack_altsvc(nghttp2_bufs *bufs, nghttp2_extension *ext);
+
+/*
+ * Unpacks ALTSVC wire format into |frame|.  The |payload| of
+ * |payloadlen| bytes contains frame payload.  This function assumes
+ * that frame->payload points to the nghttp2_ext_altsvc object.
+ *
+ * This function always succeeds and returns 0.
+ */
+void nghttp2_frame_unpack_altsvc_payload(nghttp2_extension *frame,
+                                         size_t origin_len, uint8_t *payload,
+                                         size_t payloadlen);
+
+/*
+ * Unpacks ALTSVC wire format into |frame|.  This function only exists
+ * for unit test.  After allocating buffer for fields, this function
+ * internally calls nghttp2_frame_unpack_altsvc_payload().
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory.
+ * NGHTTP2_ERR_FRAME_SIZE_ERROR
+ *     The payload is too small.
+ */
+int nghttp2_frame_unpack_altsvc_payload2(nghttp2_extension *frame,
+                                         const uint8_t *payload,
+                                         size_t payloadlen, nghttp2_mem *mem);
+
+/*
+ * Initializes HEADERS frame |frame| with given values.  |frame| takes
+ * ownership of |nva|, so caller must not free it. If |stream_id| is
+ * not assigned yet, it must be -1.
+ */
+void nghttp2_frame_headers_init(nghttp2_headers *frame, uint8_t flags,
+                                int32_t stream_id, nghttp2_headers_category cat,
+                                const nghttp2_priority_spec *pri_spec,
+                                nghttp2_nv *nva, size_t nvlen);
+
+void nghttp2_frame_headers_free(nghttp2_headers *frame, nghttp2_mem *mem);
+
+void nghttp2_frame_priority_init(nghttp2_priority *frame, int32_t stream_id,
+                                 const nghttp2_priority_spec *pri_spec);
+
+void nghttp2_frame_priority_free(nghttp2_priority *frame);
+
+void nghttp2_frame_rst_stream_init(nghttp2_rst_stream *frame, int32_t stream_id,
+                                   uint32_t error_code);
+
+void nghttp2_frame_rst_stream_free(nghttp2_rst_stream *frame);
+
+/*
+ * Initializes PUSH_PROMISE frame |frame| with given values.  |frame|
+ * takes ownership of |nva|, so caller must not free it.
+ */
+void nghttp2_frame_push_promise_init(nghttp2_push_promise *frame, uint8_t flags,
+                                     int32_t stream_id,
+                                     int32_t promised_stream_id,
+                                     nghttp2_nv *nva, size_t nvlen);
+
+void nghttp2_frame_push_promise_free(nghttp2_push_promise *frame,
+                                     nghttp2_mem *mem);
+
+/*
+ * Initializes SETTINGS frame |frame| with given values. |frame| takes
+ * ownership of |iv|, so caller must not free it. The |flags| are
+ * bitwise-OR of one or more of nghttp2_settings_flag.
+ */
+void nghttp2_frame_settings_init(nghttp2_settings *frame, uint8_t flags,
+                                 nghttp2_settings_entry *iv, size_t niv);
+
+void nghttp2_frame_settings_free(nghttp2_settings *frame, nghttp2_mem *mem);
+
+/*
+ * Initializes PING frame |frame| with given values. If the
+ * |opqeue_data| is not NULL, it must point to 8 bytes memory region
+ * of data. The data pointed by |opaque_data| is copied. It can be
+ * NULL. In this case, 8 bytes NULL is used.
+ */
+void nghttp2_frame_ping_init(nghttp2_ping *frame, uint8_t flags,
+                             const uint8_t *opque_data);
+
+void nghttp2_frame_ping_free(nghttp2_ping *frame);
+
+/*
+ * Initializes GOAWAY frame |frame| with given values. On success,
+ * this function takes ownership of |opaque_data|, so caller must not
+ * free it. If the |opaque_data_len| is 0, opaque_data could be NULL.
+ */
+void nghttp2_frame_goaway_init(nghttp2_goaway *frame, int32_t last_stream_id,
+                               uint32_t error_code, uint8_t *opaque_data,
+                               size_t opaque_data_len);
+
+void nghttp2_frame_goaway_free(nghttp2_goaway *frame, nghttp2_mem *mem);
+
+void nghttp2_frame_window_update_init(nghttp2_window_update *frame,
+                                      uint8_t flags, int32_t stream_id,
+                                      int32_t window_size_increment);
+
+void nghttp2_frame_window_update_free(nghttp2_window_update *frame);
+
+void nghttp2_frame_extension_init(nghttp2_extension *frame, uint8_t type,
+                                  uint8_t flags, int32_t stream_id,
+                                  void *payload);
+
+void nghttp2_frame_extension_free(nghttp2_extension *frame);
+
+/*
+ * Initializes ALTSVC frame |frame| with given values.  This function
+ * assumes that frame->payload points to nghttp2_ext_altsvc object.
+ * Also |origin| and |field_value| are allocated in single buffer,
+ * starting |origin|.  On success, this function takes ownership of
+ * |origin|, so caller must not free it.
+ */
+void nghttp2_frame_altsvc_init(nghttp2_extension *frame, int32_t stream_id,
+                               uint8_t *origin, size_t origin_len,
+                               uint8_t *field_value, size_t field_value_len);
+
+/*
+ * Frees up resources under |frame|.  This function does not free
+ * nghttp2_ext_altsvc object pointed by frame->payload.  This function
+ * only frees origin pointed by nghttp2_ext_altsvc.origin.  Therefore,
+ * other fields must be allocated in the same buffer with origin.
+ */
+void nghttp2_frame_altsvc_free(nghttp2_extension *frame, nghttp2_mem *mem);
+
+/*
+ * Returns the number of padding bytes after payload.  The total
+ * padding length is given in the |padlen|.  The returned value does
+ * not include the Pad Length field.  If |padlen| is 0, this function
+ * returns 0, regardless of frame->hd.flags.
+ */
+size_t nghttp2_frame_trail_padlen(nghttp2_frame *frame, size_t padlen);
+
+void nghttp2_frame_data_init(nghttp2_data *frame, uint8_t flags,
+                             int32_t stream_id);
+
+void nghttp2_frame_data_free(nghttp2_data *frame);
+
+/*
+ * Makes copy of |iv| and return the copy. The |niv| is the number of
+ * entries in |iv|. This function returns the pointer to the copy if
+ * it succeeds, or NULL.
+ */
+nghttp2_settings_entry *nghttp2_frame_iv_copy(const nghttp2_settings_entry *iv,
+                                              size_t niv, nghttp2_mem *mem);
+
+/*
+ * Sorts the |nva| in ascending order of name and value. If names are
+ * equivalent, sort them by value.
+ */
+void nghttp2_nv_array_sort(nghttp2_nv *nva, size_t nvlen);
+
+/*
+ * Copies name/value pairs from |nva|, which contains |nvlen| pairs,
+ * to |*nva_ptr|, which is dynamically allocated so that all items can
+ * be stored.  The resultant name and value in nghttp2_nv are
+ * guaranteed to be NULL-terminated even if the input is not
+ * null-terminated.
+ *
+ * The |*nva_ptr| must be freed using nghttp2_nv_array_del().
+ *
+ * This function returns 0 if it succeeds or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory.
+ */
+int nghttp2_nv_array_copy(nghttp2_nv **nva_ptr, const nghttp2_nv *nva,
+                          size_t nvlen, nghttp2_mem *mem);
+
+/*
+ * Returns nonzero if the name/value pair |a| equals to |b|. The name
+ * is compared in case-sensitive, because we ensure that this function
+ * is called after the name is lower-cased.
+ */
+int nghttp2_nv_equal(const nghttp2_nv *a, const nghttp2_nv *b);
+
+/*
+ * Frees |nva|.
+ */
+void nghttp2_nv_array_del(nghttp2_nv *nva, nghttp2_mem *mem);
+
+/*
+ * Checks that the |iv|, which includes |niv| entries, does not have
+ * invalid values.
+ *
+ * This function returns nonzero if it succeeds, or 0.
+ */
+int nghttp2_iv_check(const nghttp2_settings_entry *iv, size_t niv);
+
+/*
+ * Sets Pad Length field and flags and adjusts frame header position
+ * of each buffers in |bufs|.  The number of padding is given in the
+ * |padlen| including Pad Length field.  The |hd| is the frame header
+ * for the serialized data.  This function fills zeros padding region
+ * unless framehd_only is nonzero.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory.
+ * NGHTTP2_ERR_FRAME_SIZE_ERROR
+ *     The length of the resulting frame is too large.
+ */
+int nghttp2_frame_add_pad(nghttp2_bufs *bufs, nghttp2_frame_hd *hd,
+                          size_t padlen, int framehd_only);
+
+#endif /* NGHTTP2_FRAME_H */
diff --git a/tools/sdk/include/nghttp/nghttp2_hd.h b/tools/sdk/include/nghttp/nghttp2_hd.h
new file mode 100644
index 00000000..1da9eb58
--- /dev/null
+++ b/tools/sdk/include/nghttp/nghttp2_hd.h
@@ -0,0 +1,430 @@
+/*
+ * nghttp2 - HTTP/2 C Library
+ *
+ * Copyright (c) 2013 Tatsuhiro Tsujikawa
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NGHTTP2_HD_H
+#define NGHTTP2_HD_H
+
+#ifdef HAVE_CONFIG_H
+#include 
+#endif /* HAVE_CONFIG_H */
+
+#include 
+
+#include "nghttp2_hd_huffman.h"
+#include "nghttp2_buf.h"
+#include "nghttp2_mem.h"
+#include "nghttp2_rcbuf.h"
+
+#define NGHTTP2_HD_DEFAULT_MAX_BUFFER_SIZE NGHTTP2_DEFAULT_HEADER_TABLE_SIZE
+#define NGHTTP2_HD_ENTRY_OVERHEAD 32
+
+/* The maximum length of one name/value pair.  This is the sum of the
+   length of name and value.  This is not specified by the spec. We
+   just chose the arbitrary size */
+#define NGHTTP2_HD_MAX_NV 65536
+
+/* Default size of maximum table buffer size for encoder. Even if
+   remote decoder notifies larger buffer size for its decoding,
+   encoder only uses the memory up to this value. */
+#define NGHTTP2_HD_DEFAULT_MAX_DEFLATE_BUFFER_SIZE (1 << 12)
+
+/* Exported for unit test */
+#define NGHTTP2_STATIC_TABLE_LENGTH 61
+
+/* Generated by genlibtokenlookup.py */
+typedef enum {
+  NGHTTP2_TOKEN__AUTHORITY = 0,
+  NGHTTP2_TOKEN__METHOD = 1,
+  NGHTTP2_TOKEN__PATH = 3,
+  NGHTTP2_TOKEN__SCHEME = 5,
+  NGHTTP2_TOKEN__STATUS = 7,
+  NGHTTP2_TOKEN_ACCEPT_CHARSET = 14,
+  NGHTTP2_TOKEN_ACCEPT_ENCODING = 15,
+  NGHTTP2_TOKEN_ACCEPT_LANGUAGE = 16,
+  NGHTTP2_TOKEN_ACCEPT_RANGES = 17,
+  NGHTTP2_TOKEN_ACCEPT = 18,
+  NGHTTP2_TOKEN_ACCESS_CONTROL_ALLOW_ORIGIN = 19,
+  NGHTTP2_TOKEN_AGE = 20,
+  NGHTTP2_TOKEN_ALLOW = 21,
+  NGHTTP2_TOKEN_AUTHORIZATION = 22,
+  NGHTTP2_TOKEN_CACHE_CONTROL = 23,
+  NGHTTP2_TOKEN_CONTENT_DISPOSITION = 24,
+  NGHTTP2_TOKEN_CONTENT_ENCODING = 25,
+  NGHTTP2_TOKEN_CONTENT_LANGUAGE = 26,
+  NGHTTP2_TOKEN_CONTENT_LENGTH = 27,
+  NGHTTP2_TOKEN_CONTENT_LOCATION = 28,
+  NGHTTP2_TOKEN_CONTENT_RANGE = 29,
+  NGHTTP2_TOKEN_CONTENT_TYPE = 30,
+  NGHTTP2_TOKEN_COOKIE = 31,
+  NGHTTP2_TOKEN_DATE = 32,
+  NGHTTP2_TOKEN_ETAG = 33,
+  NGHTTP2_TOKEN_EXPECT = 34,
+  NGHTTP2_TOKEN_EXPIRES = 35,
+  NGHTTP2_TOKEN_FROM = 36,
+  NGHTTP2_TOKEN_HOST = 37,
+  NGHTTP2_TOKEN_IF_MATCH = 38,
+  NGHTTP2_TOKEN_IF_MODIFIED_SINCE = 39,
+  NGHTTP2_TOKEN_IF_NONE_MATCH = 40,
+  NGHTTP2_TOKEN_IF_RANGE = 41,
+  NGHTTP2_TOKEN_IF_UNMODIFIED_SINCE = 42,
+  NGHTTP2_TOKEN_LAST_MODIFIED = 43,
+  NGHTTP2_TOKEN_LINK = 44,
+  NGHTTP2_TOKEN_LOCATION = 45,
+  NGHTTP2_TOKEN_MAX_FORWARDS = 46,
+  NGHTTP2_TOKEN_PROXY_AUTHENTICATE = 47,
+  NGHTTP2_TOKEN_PROXY_AUTHORIZATION = 48,
+  NGHTTP2_TOKEN_RANGE = 49,
+  NGHTTP2_TOKEN_REFERER = 50,
+  NGHTTP2_TOKEN_REFRESH = 51,
+  NGHTTP2_TOKEN_RETRY_AFTER = 52,
+  NGHTTP2_TOKEN_SERVER = 53,
+  NGHTTP2_TOKEN_SET_COOKIE = 54,
+  NGHTTP2_TOKEN_STRICT_TRANSPORT_SECURITY = 55,
+  NGHTTP2_TOKEN_TRANSFER_ENCODING = 56,
+  NGHTTP2_TOKEN_USER_AGENT = 57,
+  NGHTTP2_TOKEN_VARY = 58,
+  NGHTTP2_TOKEN_VIA = 59,
+  NGHTTP2_TOKEN_WWW_AUTHENTICATE = 60,
+  NGHTTP2_TOKEN_TE,
+  NGHTTP2_TOKEN_CONNECTION,
+  NGHTTP2_TOKEN_KEEP_ALIVE,
+  NGHTTP2_TOKEN_PROXY_CONNECTION,
+  NGHTTP2_TOKEN_UPGRADE,
+} nghttp2_token;
+
+struct nghttp2_hd_entry;
+typedef struct nghttp2_hd_entry nghttp2_hd_entry;
+
+typedef struct {
+  /* The buffer containing header field name.  NULL-termination is
+     guaranteed. */
+  nghttp2_rcbuf *name;
+  /* The buffer containing header field value.  NULL-termination is
+     guaranteed. */
+  nghttp2_rcbuf *value;
+  /* nghttp2_token value for name.  It could be -1 if we have no token
+     for that header field name. */
+  int32_t token;
+  /* Bitwise OR of one or more of nghttp2_nv_flag. */
+  uint8_t flags;
+} nghttp2_hd_nv;
+
+struct nghttp2_hd_entry {
+  /* The header field name/value pair */
+  nghttp2_hd_nv nv;
+  /* This is solely for nghttp2_hd_{deflate,inflate}_get_table_entry
+     APIs to keep backward compatibility. */
+  nghttp2_nv cnv;
+  /* The next entry which shares same bucket in hash table. */
+  nghttp2_hd_entry *next;
+  /* The sequence number.  We will increment it by one whenever we
+     store nghttp2_hd_entry to dynamic header table. */
+  uint32_t seq;
+  /* The hash value for header name (nv.name). */
+  uint32_t hash;
+};
+
+/* The entry used for static header table. */
+typedef struct {
+  nghttp2_rcbuf name;
+  nghttp2_rcbuf value;
+  nghttp2_nv cnv;
+  int32_t token;
+  uint32_t hash;
+} nghttp2_hd_static_entry;
+
+typedef struct {
+  nghttp2_hd_entry **buffer;
+  size_t mask;
+  size_t first;
+  size_t len;
+} nghttp2_hd_ringbuf;
+
+typedef enum {
+  NGHTTP2_HD_OPCODE_NONE,
+  NGHTTP2_HD_OPCODE_INDEXED,
+  NGHTTP2_HD_OPCODE_NEWNAME,
+  NGHTTP2_HD_OPCODE_INDNAME
+} nghttp2_hd_opcode;
+
+typedef enum {
+  NGHTTP2_HD_STATE_EXPECT_TABLE_SIZE,
+  NGHTTP2_HD_STATE_INFLATE_START,
+  NGHTTP2_HD_STATE_OPCODE,
+  NGHTTP2_HD_STATE_READ_TABLE_SIZE,
+  NGHTTP2_HD_STATE_READ_INDEX,
+  NGHTTP2_HD_STATE_NEWNAME_CHECK_NAMELEN,
+  NGHTTP2_HD_STATE_NEWNAME_READ_NAMELEN,
+  NGHTTP2_HD_STATE_NEWNAME_READ_NAMEHUFF,
+  NGHTTP2_HD_STATE_NEWNAME_READ_NAME,
+  NGHTTP2_HD_STATE_CHECK_VALUELEN,
+  NGHTTP2_HD_STATE_READ_VALUELEN,
+  NGHTTP2_HD_STATE_READ_VALUEHUFF,
+  NGHTTP2_HD_STATE_READ_VALUE
+} nghttp2_hd_inflate_state;
+
+typedef enum {
+  NGHTTP2_HD_WITH_INDEXING,
+  NGHTTP2_HD_WITHOUT_INDEXING,
+  NGHTTP2_HD_NEVER_INDEXING
+} nghttp2_hd_indexing_mode;
+
+typedef struct {
+  /* dynamic header table */
+  nghttp2_hd_ringbuf hd_table;
+  /* Memory allocator */
+  nghttp2_mem *mem;
+  /* Abstract buffer size of hd_table as described in the spec. This
+     is the sum of length of name/value in hd_table +
+     NGHTTP2_HD_ENTRY_OVERHEAD bytes overhead per each entry. */
+  size_t hd_table_bufsize;
+  /* The effective header table size. */
+  size_t hd_table_bufsize_max;
+  /* Next sequence number for nghttp2_hd_entry */
+  uint32_t next_seq;
+  /* If inflate/deflate error occurred, this value is set to 1 and
+     further invocation of inflate/deflate will fail with
+     NGHTTP2_ERR_HEADER_COMP. */
+  uint8_t bad;
+} nghttp2_hd_context;
+
+#define HD_MAP_SIZE 128
+
+typedef struct { nghttp2_hd_entry *table[HD_MAP_SIZE]; } nghttp2_hd_map;
+
+struct nghttp2_hd_deflater {
+  nghttp2_hd_context ctx;
+  nghttp2_hd_map map;
+  /* The upper limit of the header table size the deflater accepts. */
+  size_t deflate_hd_table_bufsize_max;
+  /* Minimum header table size notified in the next context update */
+  size_t min_hd_table_bufsize_max;
+  /* If nonzero, send header table size using encoding context update
+     in the next deflate process */
+  uint8_t notify_table_size_change;
+};
+
+struct nghttp2_hd_inflater {
+  nghttp2_hd_context ctx;
+  /* Stores current state of huffman decoding */
+  nghttp2_hd_huff_decode_context huff_decode_ctx;
+  /* header buffer */
+  nghttp2_buf namebuf, valuebuf;
+  nghttp2_rcbuf *namercbuf, *valuercbuf;
+  /* Pointer to the name/value pair which are used in the current
+     header emission. */
+  nghttp2_rcbuf *nv_name_keep, *nv_value_keep;
+  /* The number of bytes to read */
+  size_t left;
+  /* The index in indexed repr or indexed name */
+  size_t index;
+  /* The maximum header table size the inflater supports. This is the
+     same value transmitted in SETTINGS_HEADER_TABLE_SIZE */
+  size_t settings_hd_table_bufsize_max;
+  /* Minimum header table size set by nghttp2_hd_inflate_change_table_size */
+  size_t min_hd_table_bufsize_max;
+  /* The number of next shift to decode integer */
+  size_t shift;
+  nghttp2_hd_opcode opcode;
+  nghttp2_hd_inflate_state state;
+  /* nonzero if string is huffman encoded */
+  uint8_t huffman_encoded;
+  /* nonzero if deflater requires that current entry is indexed */
+  uint8_t index_required;
+  /* nonzero if deflater requires that current entry must not be
+     indexed */
+  uint8_t no_index;
+};
+
+/*
+ * Initializes the |ent| members.  The reference counts of nv->name
+ * and nv->value are increased by one for each.
+ */
+void nghttp2_hd_entry_init(nghttp2_hd_entry *ent, nghttp2_hd_nv *nv);
+
+/*
+ * This function decreases the reference counts of nv->name and
+ * nv->value.
+ */
+void nghttp2_hd_entry_free(nghttp2_hd_entry *ent);
+
+/*
+ * Initializes |deflater| for deflating name/values pairs.
+ *
+ * The encoder only uses up to
+ * NGHTTP2_HD_DEFAULT_MAX_DEFLATE_BUFFER_SIZE bytes for header table
+ * even if the larger value is specified later in
+ * nghttp2_hd_change_table_size().
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory.
+ */
+int nghttp2_hd_deflate_init(nghttp2_hd_deflater *deflater, nghttp2_mem *mem);
+
+/*
+ * Initializes |deflater| for deflating name/values pairs.
+ *
+ * The encoder only uses up to |deflate_hd_table_bufsize_max| bytes
+ * for header table even if the larger value is specified later in
+ * nghttp2_hd_change_table_size().
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory.
+ */
+int nghttp2_hd_deflate_init2(nghttp2_hd_deflater *deflater,
+                             size_t deflate_hd_table_bufsize_max,
+                             nghttp2_mem *mem);
+
+/*
+ * Deallocates any resources allocated for |deflater|.
+ */
+void nghttp2_hd_deflate_free(nghttp2_hd_deflater *deflater);
+
+/*
+ * Deflates the |nva|, which has the |nvlen| name/value pairs, into
+ * the |bufs|.
+ *
+ * This function expands |bufs| as necessary to store the result. If
+ * buffers is full and the process still requires more space, this
+ * funtion fails and returns NGHTTP2_ERR_HEADER_COMP.
+ *
+ * After this function returns, it is safe to delete the |nva|.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory.
+ * NGHTTP2_ERR_HEADER_COMP
+ *     Deflation process has failed.
+ * NGHTTP2_ERR_BUFFER_ERROR
+ *     Out of buffer space.
+ */
+int nghttp2_hd_deflate_hd_bufs(nghttp2_hd_deflater *deflater,
+                               nghttp2_bufs *bufs, const nghttp2_nv *nva,
+                               size_t nvlen);
+
+/*
+ * Initializes |inflater| for inflating name/values pairs.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * :enum:`NGHTTP2_ERR_NOMEM`
+ *     Out of memory.
+ */
+int nghttp2_hd_inflate_init(nghttp2_hd_inflater *inflater, nghttp2_mem *mem);
+
+/*
+ * Deallocates any resources allocated for |inflater|.
+ */
+void nghttp2_hd_inflate_free(nghttp2_hd_inflater *inflater);
+
+/*
+ * Similar to nghttp2_hd_inflate_hd(), but this takes nghttp2_hd_nv
+ * instead of nghttp2_nv as output parameter |nv_out|.  Other than
+ * that return values and semantics are the same as
+ * nghttp2_hd_inflate_hd().
+ */
+ssize_t nghttp2_hd_inflate_hd_nv(nghttp2_hd_inflater *inflater,
+                                 nghttp2_hd_nv *nv_out, int *inflate_flags,
+                                 const uint8_t *in, size_t inlen, int in_final);
+
+/* For unittesting purpose */
+int nghttp2_hd_emit_indname_block(nghttp2_bufs *bufs, size_t index,
+                                  nghttp2_nv *nv, int indexing_mode);
+
+/* For unittesting purpose */
+int nghttp2_hd_emit_newname_block(nghttp2_bufs *bufs, nghttp2_nv *nv,
+                                  int indexing_mode);
+
+/* For unittesting purpose */
+int nghttp2_hd_emit_table_size(nghttp2_bufs *bufs, size_t table_size);
+
+/* For unittesting purpose */
+nghttp2_hd_nv nghttp2_hd_table_get(nghttp2_hd_context *context, size_t index);
+
+/* For unittesting purpose */
+ssize_t nghttp2_hd_decode_length(uint32_t *res, size_t *shift_ptr, int *final,
+                                 uint32_t initial, size_t shift, uint8_t *in,
+                                 uint8_t *last, size_t prefix);
+
+/* Huffman encoding/decoding functions */
+
+/*
+ * Counts the required bytes to encode |src| with length |len|.
+ *
+ * This function returns the number of required bytes to encode given
+ * data, including padding of prefix of terminal symbol code. This
+ * function always succeeds.
+ */
+size_t nghttp2_hd_huff_encode_count(const uint8_t *src, size_t len);
+
+/*
+ * Encodes the given data |src| with length |srclen| to the |bufs|.
+ * This function expands extra buffers in |bufs| if necessary.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory.
+ * NGHTTP2_ERR_BUFFER_ERROR
+ *     Out of buffer space.
+ */
+int nghttp2_hd_huff_encode(nghttp2_bufs *bufs, const uint8_t *src,
+                           size_t srclen);
+
+void nghttp2_hd_huff_decode_context_init(nghttp2_hd_huff_decode_context *ctx);
+
+/*
+ * Decodes the given data |src| with length |srclen|.  The |ctx| must
+ * be initialized by nghttp2_hd_huff_decode_context_init(). The result
+ * will be written to |buf|.  This function assumes that |buf| has the
+ * enough room to store the decoded byte string.
+ *
+ * The caller must set the |final| to nonzero if the given input is
+ * the final block.
+ *
+ * This function returns the number of read bytes from the |in|.
+ *
+ * If this function fails, it returns one of the following negative
+ * return codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory.
+ * NGHTTP2_ERR_HEADER_COMP
+ *     Decoding process has failed.
+ */
+ssize_t nghttp2_hd_huff_decode(nghttp2_hd_huff_decode_context *ctx,
+                               nghttp2_buf *buf, const uint8_t *src,
+                               size_t srclen, int final);
+
+#endif /* NGHTTP2_HD_H */
diff --git a/tools/sdk/include/nghttp/nghttp2_hd_huffman.h b/tools/sdk/include/nghttp/nghttp2_hd_huffman.h
new file mode 100644
index 00000000..83323400
--- /dev/null
+++ b/tools/sdk/include/nghttp/nghttp2_hd_huffman.h
@@ -0,0 +1,77 @@
+/*
+ * nghttp2 - HTTP/2 C Library
+ *
+ * Copyright (c) 2013 Tatsuhiro Tsujikawa
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NGHTTP2_HD_HUFFMAN_H
+#define NGHTTP2_HD_HUFFMAN_H
+
+#ifdef HAVE_CONFIG_H
+#include 
+#endif /* HAVE_CONFIG_H */
+
+#include 
+
+typedef enum {
+  /* FSA accepts this state as the end of huffman encoding
+     sequence. */
+  NGHTTP2_HUFF_ACCEPTED = 1,
+  /* This state emits symbol */
+  NGHTTP2_HUFF_SYM = (1 << 1),
+  /* If state machine reaches this state, decoding fails. */
+  NGHTTP2_HUFF_FAIL = (1 << 2)
+} nghttp2_huff_decode_flag;
+
+typedef struct {
+  /* huffman decoding state, which is actually the node ID of internal
+     huffman tree.  We have 257 leaf nodes, but they are identical to
+     root node other than emitting a symbol, so we have 256 internal
+     nodes [1..255], inclusive. */
+  uint8_t state;
+  /* bitwise OR of zero or more of the nghttp2_huff_decode_flag */
+  uint8_t flags;
+  /* symbol if NGHTTP2_HUFF_SYM flag set */
+  uint8_t sym;
+} nghttp2_huff_decode;
+
+typedef nghttp2_huff_decode huff_decode_table_type[16];
+
+typedef struct {
+  /* Current huffman decoding state. We stripped leaf nodes, so the
+     value range is [0..255], inclusive. */
+  uint8_t state;
+  /* nonzero if we can say that the decoding process succeeds at this
+     state */
+  uint8_t accept;
+} nghttp2_hd_huff_decode_context;
+
+typedef struct {
+  /* The number of bits in this code */
+  uint32_t nbits;
+  /* Huffman code aligned to LSB */
+  uint32_t code;
+} nghttp2_huff_sym;
+
+extern const nghttp2_huff_sym huff_sym_table[];
+extern const nghttp2_huff_decode huff_decode_table[][16];
+
+#endif /* NGHTTP2_HD_HUFFMAN_H */
diff --git a/tools/sdk/include/nghttp/nghttp2_helper.h b/tools/sdk/include/nghttp/nghttp2_helper.h
new file mode 100644
index 00000000..4a32564f
--- /dev/null
+++ b/tools/sdk/include/nghttp/nghttp2_helper.h
@@ -0,0 +1,122 @@
+/*
+ * nghttp2 - HTTP/2 C Library
+ *
+ * Copyright (c) 2012 Tatsuhiro Tsujikawa
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NGHTTP2_HELPER_H
+#define NGHTTP2_HELPER_H
+
+#ifdef HAVE_CONFIG_H
+#include 
+#endif /* HAVE_CONFIG_H */
+
+#include 
+#include 
+
+#include 
+#include "nghttp2_mem.h"
+
+#define nghttp2_min(A, B) ((A) < (B) ? (A) : (B))
+#define nghttp2_max(A, B) ((A) > (B) ? (A) : (B))
+
+#define lstreq(A, B, N) ((sizeof((A)) - 1) == (N) && memcmp((A), (B), (N)) == 0)
+
+#define nghttp2_struct_of(ptr, type, member)                                   \
+  ((type *)(void *)((char *)(ptr)-offsetof(type, member)))
+
+/*
+ * Copies 2 byte unsigned integer |n| in host byte order to |buf| in
+ * network byte order.
+ */
+void nghttp2_put_uint16be(uint8_t *buf, uint16_t n);
+
+/*
+ * Copies 4 byte unsigned integer |n| in host byte order to |buf| in
+ * network byte order.
+ */
+void nghttp2_put_uint32be(uint8_t *buf, uint32_t n);
+
+/*
+ * Retrieves 2 byte unsigned integer stored in |data| in network byte
+ * order and returns it in host byte order.
+ */
+uint16_t nghttp2_get_uint16(const uint8_t *data);
+
+/*
+ * Retrieves 4 byte unsigned integer stored in |data| in network byte
+ * order and returns it in host byte order.
+ */
+uint32_t nghttp2_get_uint32(const uint8_t *data);
+
+void nghttp2_downcase(uint8_t *s, size_t len);
+
+/*
+ * Adjusts |*local_window_size_ptr|, |*recv_window_size_ptr|,
+ * |*recv_reduction_ptr| with |*delta_ptr| which is the
+ * WINDOW_UPDATE's window_size_increment sent from local side. If
+ * |delta| is strictly larger than |*recv_window_size_ptr|,
+ * |*local_window_size_ptr| is increased by delta -
+ * *recv_window_size_ptr. If |delta| is negative,
+ * |*local_window_size_ptr| is decreased by delta.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_FLOW_CONTROL
+ *     local_window_size overflow or gets negative.
+ */
+int nghttp2_adjust_local_window_size(int32_t *local_window_size_ptr,
+                                     int32_t *recv_window_size_ptr,
+                                     int32_t *recv_reduction_ptr,
+                                     int32_t *delta_ptr);
+
+/*
+ * This function works like nghttp2_adjust_local_window_size().  The
+ * difference is that this function assumes *delta_ptr >= 0, and
+ * *recv_window_size_ptr is not decreased by *delta_ptr.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_FLOW_CONTROL
+ *     local_window_size overflow or gets negative.
+ */
+int nghttp2_increase_local_window_size(int32_t *local_window_size_ptr,
+                                       int32_t *recv_window_size_ptr,
+                                       int32_t *recv_reduction_ptr,
+                                       int32_t *delta_ptr);
+
+/*
+ * Returns non-zero if the function decided that WINDOW_UPDATE should
+ * be sent.
+ */
+int nghttp2_should_send_window_update(int32_t local_window_size,
+                                      int32_t recv_window_size);
+
+/*
+ * Copies the buffer |src| of length |len| to the destination pointed
+ * by the |dest|, assuming that the |dest| is at lest |len| bytes long
+ * . Returns dest + len.
+ */
+uint8_t *nghttp2_cpymem(uint8_t *dest, const void *src, size_t len);
+
+#endif /* NGHTTP2_HELPER_H */
diff --git a/tools/sdk/include/nghttp/nghttp2_http.h b/tools/sdk/include/nghttp/nghttp2_http.h
new file mode 100644
index 00000000..ac684c4d
--- /dev/null
+++ b/tools/sdk/include/nghttp/nghttp2_http.h
@@ -0,0 +1,97 @@
+/*
+ * nghttp2 - HTTP/2 C Library
+ *
+ * Copyright (c) 2015 Tatsuhiro Tsujikawa
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NGHTTP2_HTTP_H
+#define NGHTTP2_HTTP_H
+
+#ifdef HAVE_CONFIG_H
+#include 
+#endif /* HAVE_CONFIG_H */
+
+#include 
+#include "nghttp2_session.h"
+#include "nghttp2_stream.h"
+
+/*
+ * This function is called when HTTP header field |nv| in |frame| is
+ * received for |stream|.  This function will validate |nv| against
+ * the current state of stream.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_HTTP_HEADER
+ *     Invalid HTTP header field was received.
+ * NGHTTP2_ERR_IGN_HTTP_HEADER
+ *     Invalid HTTP header field was received but it can be treated as
+ *     if it was not received because of compatibility reasons.
+ */
+int nghttp2_http_on_header(nghttp2_session *session, nghttp2_stream *stream,
+                           nghttp2_frame *frame, nghttp2_hd_nv *nv,
+                           int trailer);
+
+/*
+ * This function is called when request header is received.  This
+ * function performs validation and returns 0 if it succeeds, or -1.
+ */
+int nghttp2_http_on_request_headers(nghttp2_stream *stream,
+                                    nghttp2_frame *frame);
+
+/*
+ * This function is called when response header is received.  This
+ * function performs validation and returns 0 if it succeeds, or -1.
+ */
+int nghttp2_http_on_response_headers(nghttp2_stream *stream);
+
+/*
+ * This function is called trailer header (for both request and
+ * response) is received.  This function performs validation and
+ * returns 0 if it succeeds, or -1.
+ */
+int nghttp2_http_on_trailer_headers(nghttp2_stream *stream,
+                                    nghttp2_frame *frame);
+
+/*
+ * This function is called when END_STREAM flag is seen in incoming
+ * frame.  This function performs validation and returns 0 if it
+ * succeeds, or -1.
+ */
+int nghttp2_http_on_remote_end_stream(nghttp2_stream *stream);
+
+/*
+ * This function is called when chunk of data is received.  This
+ * function performs validation and returns 0 if it succeeds, or -1.
+ */
+int nghttp2_http_on_data_chunk(nghttp2_stream *stream, size_t n);
+
+/*
+ * This function inspects header field in |frame| and records its
+ * method in stream->http_flags.  If frame->hd.type is neither
+ * NGHTTP2_HEADERS nor NGHTTP2_PUSH_PROMISE, this function does
+ * nothing.
+ */
+void nghttp2_http_record_request_method(nghttp2_stream *stream,
+                                        nghttp2_frame *frame);
+
+#endif /* NGHTTP2_HTTP_H */
diff --git a/tools/sdk/include/nghttp/nghttp2_int.h b/tools/sdk/include/nghttp/nghttp2_int.h
new file mode 100644
index 00000000..c26c8e99
--- /dev/null
+++ b/tools/sdk/include/nghttp/nghttp2_int.h
@@ -0,0 +1,58 @@
+/*
+ * nghttp2 - HTTP/2 C Library
+ *
+ * Copyright (c) 2012 Tatsuhiro Tsujikawa
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NGHTTP2_INT_H
+#define NGHTTP2_INT_H
+
+#ifdef HAVE_CONFIG_H
+#include 
+#endif /* HAVE_CONFIG_H */
+
+/* Macros, types and constants for internal use */
+
+#ifdef DEBUGBUILD
+#define DEBUGF(x) x
+#else
+#define DEBUGF(x)                                                              \
+  do {                                                                         \
+  } while (0)
+#endif
+
+/* "less" function, return nonzero if |lhs| is less than |rhs|. */
+typedef int (*nghttp2_less)(const void *lhs, const void *rhs);
+
+/* Internal error code. They must be in the range [-499, -100],
+   inclusive. */
+typedef enum {
+  NGHTTP2_ERR_CREDENTIAL_PENDING = -101,
+  NGHTTP2_ERR_IGN_HEADER_BLOCK = -103,
+  NGHTTP2_ERR_IGN_PAYLOAD = -104,
+  /*
+   * Invalid HTTP header field was received but it can be treated as
+   * if it was not received because of compatibility reasons.
+   */
+  NGHTTP2_ERR_IGN_HTTP_HEADER = -105
+} nghttp2_internal_error;
+
+#endif /* NGHTTP2_INT_H */
diff --git a/tools/sdk/include/nghttp/nghttp2_map.h b/tools/sdk/include/nghttp/nghttp2_map.h
new file mode 100644
index 00000000..21262488
--- /dev/null
+++ b/tools/sdk/include/nghttp/nghttp2_map.h
@@ -0,0 +1,144 @@
+/*
+ * nghttp2 - HTTP/2 C Library
+ *
+ * Copyright (c) 2012 Tatsuhiro Tsujikawa
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NGHTTP2_MAP_H
+#define NGHTTP2_MAP_H
+
+#ifdef HAVE_CONFIG_H
+#include 
+#endif /* HAVE_CONFIG_H */
+
+#include 
+#include "nghttp2_int.h"
+#include "nghttp2_mem.h"
+
+/* Implementation of unordered map */
+
+typedef int32_t key_type;
+
+typedef struct nghttp2_map_entry {
+  struct nghttp2_map_entry *next;
+  key_type key;
+#if SIZEOF_INT_P == 4
+  /* we requires 8 bytes aligment */
+  int64_t pad;
+#endif
+} nghttp2_map_entry;
+
+typedef struct {
+  nghttp2_map_entry **table;
+  nghttp2_mem *mem;
+  size_t size;
+  uint32_t tablelen;
+} nghttp2_map;
+
+/*
+ * Initializes the map |map|.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *   Out of memory
+ */
+int nghttp2_map_init(nghttp2_map *map, nghttp2_mem *mem);
+
+/*
+ * Deallocates any resources allocated for |map|. The stored entries
+ * are not freed by this function. Use nghttp2_map_each_free() to free
+ * each entries.
+ */
+void nghttp2_map_free(nghttp2_map *map);
+
+/*
+ * Deallocates each entries using |func| function and any resources
+ * allocated for |map|. The |func| function is responsible for freeing
+ * given the |entry| object. The |ptr| will be passed to the |func| as
+ * send argument. The return value of the |func| will be ignored.
+ */
+void nghttp2_map_each_free(nghttp2_map *map,
+                           int (*func)(nghttp2_map_entry *entry, void *ptr),
+                           void *ptr);
+
+/*
+ * Initializes the |entry| with the |key|. All entries to be inserted
+ * to the map must be initialized with this function.
+ */
+void nghttp2_map_entry_init(nghttp2_map_entry *entry, key_type key);
+
+/*
+ * Inserts the new |entry| with the key |entry->key| to the map |map|.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_INVALID_ARGUMENT
+ *     The item associated by |key| already exists.
+ * NGHTTP2_ERR_NOMEM
+ *   Out of memory
+ */
+int nghttp2_map_insert(nghttp2_map *map, nghttp2_map_entry *entry);
+
+/*
+ * Returns the entry associated by the key |key|.  If there is no such
+ * entry, this function returns NULL.
+ */
+nghttp2_map_entry *nghttp2_map_find(nghttp2_map *map, key_type key);
+
+/*
+ * Removes the entry associated by the key |key| from the |map|.  The
+ * removed entry is not freed by this function.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_INVALID_ARGUMENT
+ *     The entry associated by |key| does not exist.
+ */
+int nghttp2_map_remove(nghttp2_map *map, key_type key);
+
+/*
+ * Returns the number of items stored in the map |map|.
+ */
+size_t nghttp2_map_size(nghttp2_map *map);
+
+/*
+ * Applies the function |func| to each entry in the |map| with the
+ * optional user supplied pointer |ptr|.
+ *
+ * If the |func| returns 0, this function calls the |func| with the
+ * next entry. If the |func| returns nonzero, it will not call the
+ * |func| for further entries and return the return value of the
+ * |func| immediately.  Thus, this function returns 0 if all the
+ * invocations of the |func| return 0, or nonzero value which the last
+ * invocation of |func| returns.
+ *
+ * Don't use this function to free each entry. Use
+ * nghttp2_map_each_free() instead.
+ */
+int nghttp2_map_each(nghttp2_map *map,
+                     int (*func)(nghttp2_map_entry *entry, void *ptr),
+                     void *ptr);
+
+#endif /* NGHTTP2_MAP_H */
diff --git a/tools/sdk/include/nghttp/nghttp2_mem.h b/tools/sdk/include/nghttp/nghttp2_mem.h
new file mode 100644
index 00000000..2d1bd6a0
--- /dev/null
+++ b/tools/sdk/include/nghttp/nghttp2_mem.h
@@ -0,0 +1,45 @@
+/*
+ * nghttp2 - HTTP/2 C Library
+ *
+ * Copyright (c) 2014 Tatsuhiro Tsujikawa
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NGHTTP2_MEM_H
+#define NGHTTP2_MEM_H
+
+#ifdef HAVE_CONFIG_H
+#include 
+#endif /* HAVE_CONFIG_H */
+
+#include 
+
+/* The default, system standard memory allocator */
+nghttp2_mem *nghttp2_mem_default(void);
+
+/* Convenient wrapper functions to call allocator function in
+   |mem|. */
+void *nghttp2_mem_malloc(nghttp2_mem *mem, size_t size);
+void nghttp2_mem_free(nghttp2_mem *mem, void *ptr);
+void nghttp2_mem_free2(nghttp2_free free_func, void *ptr, void *mem_user_data);
+void *nghttp2_mem_calloc(nghttp2_mem *mem, size_t nmemb, size_t size);
+void *nghttp2_mem_realloc(nghttp2_mem *mem, void *ptr, size_t size);
+
+#endif /* NGHTTP2_MEM_H */
diff --git a/tools/sdk/include/nghttp/nghttp2_net.h b/tools/sdk/include/nghttp/nghttp2_net.h
new file mode 100644
index 00000000..587f4189
--- /dev/null
+++ b/tools/sdk/include/nghttp/nghttp2_net.h
@@ -0,0 +1,91 @@
+/*
+ * nghttp2 - HTTP/2 C Library
+ *
+ * Copyright (c) 2012 Tatsuhiro Tsujikawa
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NGHTTP2_NET_H
+#define NGHTTP2_NET_H
+
+#ifdef HAVE_CONFIG_H
+#include 
+#endif /* HAVE_CONFIG_H */
+
+#ifdef HAVE_ARPA_INET_H
+#include 
+#endif /* HAVE_ARPA_INET_H */
+
+#ifdef HAVE_NETINET_IN_H
+#include 
+#endif /* HAVE_NETINET_IN_H */
+
+#include 
+
+#if defined(WIN32)
+/* Windows requires ws2_32 library for ntonl family functions.  We
+   define inline functions for those function so that we don't have
+   dependeny on that lib. */
+
+#ifdef _MSC_VER
+#define STIN static __inline
+#else
+#define STIN static inline
+#endif
+
+STIN uint32_t htonl(uint32_t hostlong) {
+  uint32_t res;
+  unsigned char *p = (unsigned char *)&res;
+  *p++ = hostlong >> 24;
+  *p++ = (hostlong >> 16) & 0xffu;
+  *p++ = (hostlong >> 8) & 0xffu;
+  *p = hostlong & 0xffu;
+  return res;
+}
+
+STIN uint16_t htons(uint16_t hostshort) {
+  uint16_t res;
+  unsigned char *p = (unsigned char *)&res;
+  *p++ = hostshort >> 8;
+  *p = hostshort & 0xffu;
+  return res;
+}
+
+STIN uint32_t ntohl(uint32_t netlong) {
+  uint32_t res;
+  unsigned char *p = (unsigned char *)&netlong;
+  res = *p++ << 24;
+  res += *p++ << 16;
+  res += *p++ << 8;
+  res += *p;
+  return res;
+}
+
+STIN uint16_t ntohs(uint16_t netshort) {
+  uint16_t res;
+  unsigned char *p = (unsigned char *)&netshort;
+  res = *p++ << 8;
+  res += *p;
+  return res;
+}
+
+#endif /* WIN32 */
+
+#endif /* NGHTTP2_NET_H */
diff --git a/tools/sdk/include/nghttp/nghttp2_npn.h b/tools/sdk/include/nghttp/nghttp2_npn.h
new file mode 100644
index 00000000..a481bde3
--- /dev/null
+++ b/tools/sdk/include/nghttp/nghttp2_npn.h
@@ -0,0 +1,34 @@
+/*
+ * nghttp2 - HTTP/2 C Library
+ *
+ * Copyright (c) 2012 Tatsuhiro Tsujikawa
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NGHTTP2_NPN_H
+#define NGHTTP2_NPN_H
+
+#ifdef HAVE_CONFIG_H
+#include 
+#endif /* HAVE_CONFIG_H */
+
+#include 
+
+#endif /* NGHTTP2_NPN_H */
diff --git a/tools/sdk/include/nghttp/nghttp2_option.h b/tools/sdk/include/nghttp/nghttp2_option.h
new file mode 100644
index 00000000..fb79b920
--- /dev/null
+++ b/tools/sdk/include/nghttp/nghttp2_option.h
@@ -0,0 +1,116 @@
+/*
+ * nghttp2 - HTTP/2 C Library
+ *
+ * Copyright (c) 2014 Tatsuhiro Tsujikawa
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NGHTTP2_OPTION_H
+#define NGHTTP2_OPTION_H
+
+#ifdef HAVE_CONFIG_H
+#include 
+#endif /* HAVE_CONFIG_H */
+
+#include 
+
+/**
+ * Configuration options
+ */
+typedef enum {
+  /**
+   * This option prevents the library from sending WINDOW_UPDATE for a
+   * connection automatically.  If this option is set to nonzero, the
+   * library won't send WINDOW_UPDATE for DATA until application calls
+   * nghttp2_session_consume() to indicate the amount of consumed
+   * DATA.  By default, this option is set to zero.
+   */
+  NGHTTP2_OPT_NO_AUTO_WINDOW_UPDATE = 1,
+  /**
+   * This option sets the SETTINGS_MAX_CONCURRENT_STREAMS value of
+   * remote endpoint as if it is received in SETTINGS frame. Without
+   * specifying this option, before the local endpoint receives
+   * SETTINGS_MAX_CONCURRENT_STREAMS in SETTINGS frame from remote
+   * endpoint, SETTINGS_MAX_CONCURRENT_STREAMS is unlimited. This may
+   * cause problem if local endpoint submits lots of requests
+   * initially and sending them at once to the remote peer may lead to
+   * the rejection of some requests. Specifying this option to the
+   * sensible value, say 100, may avoid this kind of issue. This value
+   * will be overwritten if the local endpoint receives
+   * SETTINGS_MAX_CONCURRENT_STREAMS from the remote endpoint.
+   */
+  NGHTTP2_OPT_PEER_MAX_CONCURRENT_STREAMS = 1 << 1,
+  NGHTTP2_OPT_NO_RECV_CLIENT_MAGIC = 1 << 2,
+  NGHTTP2_OPT_NO_HTTP_MESSAGING = 1 << 3,
+  NGHTTP2_OPT_MAX_RESERVED_REMOTE_STREAMS = 1 << 4,
+  NGHTTP2_OPT_USER_RECV_EXT_TYPES = 1 << 5,
+  NGHTTP2_OPT_NO_AUTO_PING_ACK = 1 << 6,
+  NGHTTP2_OPT_BUILTIN_RECV_EXT_TYPES = 1 << 7,
+  NGHTTP2_OPT_MAX_SEND_HEADER_BLOCK_LENGTH = 1 << 8,
+} nghttp2_option_flag;
+
+/**
+ * Struct to store option values for nghttp2_session.
+ */
+struct nghttp2_option {
+  /**
+   * NGHTTP2_OPT_MAX_SEND_HEADER_BLOCK_LENGTH
+   */
+  size_t max_send_header_block_length;
+  /**
+   * Bitwise OR of nghttp2_option_flag to determine that which fields
+   * are specified.
+   */
+  uint32_t opt_set_mask;
+  /**
+   * NGHTTP2_OPT_PEER_MAX_CONCURRENT_STREAMS
+   */
+  uint32_t peer_max_concurrent_streams;
+  /**
+   * NGHTTP2_OPT_MAX_RESERVED_REMOTE_STREAMS
+   */
+  uint32_t max_reserved_remote_streams;
+  /**
+   * NGHTTP2_OPT_BUILTIN_RECV_EXT_TYPES
+   */
+  uint32_t builtin_recv_ext_types;
+  /**
+   * NGHTTP2_OPT_NO_AUTO_WINDOW_UPDATE
+   */
+  int no_auto_window_update;
+  /**
+   * NGHTTP2_OPT_NO_RECV_CLIENT_MAGIC
+   */
+  int no_recv_client_magic;
+  /**
+   * NGHTTP2_OPT_NO_HTTP_MESSAGING
+   */
+  int no_http_messaging;
+  /**
+   * NGHTTP2_OPT_NO_AUTO_PING_ACK
+   */
+  int no_auto_ping_ack;
+  /**
+   * NGHTTP2_OPT_USER_RECV_EXT_TYPES
+   */
+  uint8_t user_recv_ext_types[32];
+};
+
+#endif /* NGHTTP2_OPTION_H */
diff --git a/tools/sdk/include/nghttp/nghttp2_outbound_item.h b/tools/sdk/include/nghttp/nghttp2_outbound_item.h
new file mode 100644
index 00000000..8bda776b
--- /dev/null
+++ b/tools/sdk/include/nghttp/nghttp2_outbound_item.h
@@ -0,0 +1,166 @@
+/*
+ * nghttp2 - HTTP/2 C Library
+ *
+ * Copyright (c) 2012 Tatsuhiro Tsujikawa
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NGHTTP2_OUTBOUND_ITEM_H
+#define NGHTTP2_OUTBOUND_ITEM_H
+
+#ifdef HAVE_CONFIG_H
+#include 
+#endif /* HAVE_CONFIG_H */
+
+#include 
+#include "nghttp2_frame.h"
+#include "nghttp2_mem.h"
+
+/* struct used for HEADERS and PUSH_PROMISE frame */
+typedef struct {
+  nghttp2_data_provider data_prd;
+  void *stream_user_data;
+  /* error code when request HEADERS is canceled by RST_STREAM while
+     it is in queue. */
+  uint32_t error_code;
+  /* nonzero if request HEADERS is canceled.  The error code is stored
+     in |error_code|. */
+  uint8_t canceled;
+} nghttp2_headers_aux_data;
+
+/* struct used for DATA frame */
+typedef struct {
+  /**
+   * The data to be sent for this DATA frame.
+   */
+  nghttp2_data_provider data_prd;
+  /**
+   * The flags of DATA frame.  We use separate flags here and
+   * nghttp2_data frame.  The latter contains flags actually sent to
+   * peer.  This |flags| may contain NGHTTP2_FLAG_END_STREAM and only
+   * when |eof| becomes nonzero, flags in nghttp2_data has
+   * NGHTTP2_FLAG_END_STREAM set.
+   */
+  uint8_t flags;
+  /**
+   * The flag to indicate whether EOF was reached or not. Initially
+   * |eof| is 0. It becomes 1 after all data were read.
+   */
+  uint8_t eof;
+  /**
+   * The flag to indicate that NGHTTP2_DATA_FLAG_NO_COPY is used.
+   */
+  uint8_t no_copy;
+} nghttp2_data_aux_data;
+
+typedef enum {
+  NGHTTP2_GOAWAY_AUX_NONE = 0x0,
+  /* indicates that session should be terminated after the
+     transmission of this frame. */
+  NGHTTP2_GOAWAY_AUX_TERM_ON_SEND = 0x1,
+  /* indicates that this GOAWAY is just a notification for graceful
+     shutdown.  No nghttp2_session.goaway_flags should be updated on
+     the reaction to this frame. */
+  NGHTTP2_GOAWAY_AUX_SHUTDOWN_NOTICE = 0x2
+} nghttp2_goaway_aux_flag;
+
+/* struct used for GOAWAY frame */
+typedef struct {
+  /* bitwise-OR of one or more of nghttp2_goaway_aux_flag. */
+  uint8_t flags;
+} nghttp2_goaway_aux_data;
+
+/* struct used for extension frame */
+typedef struct {
+  /* nonzero if this extension frame is serialized by library
+     function, instead of user-defined callbacks. */
+  uint8_t builtin;
+} nghttp2_ext_aux_data;
+
+/* Additional data which cannot be stored in nghttp2_frame struct */
+typedef union {
+  nghttp2_data_aux_data data;
+  nghttp2_headers_aux_data headers;
+  nghttp2_goaway_aux_data goaway;
+  nghttp2_ext_aux_data ext;
+} nghttp2_aux_data;
+
+struct nghttp2_outbound_item;
+typedef struct nghttp2_outbound_item nghttp2_outbound_item;
+
+struct nghttp2_outbound_item {
+  nghttp2_frame frame;
+  /* Storage for extension frame payload.  frame->ext.payload points
+     to this structure to avoid frequent memory allocation. */
+  nghttp2_ext_frame_payload ext_frame_payload;
+  nghttp2_aux_data aux_data;
+  /* The priority used in priority comparion.  Smaller is served
+     ealier.  For PING, SETTINGS and non-DATA frames (excluding
+     response HEADERS frame) have dedicated cycle value defined above.
+     For DATA frame, cycle is computed by taking into account of
+     effective weight and frame payload length previously sent, so
+     that the amount of transmission is distributed across streams
+     proportional to effective weight (inside a tree). */
+  uint64_t cycle;
+  nghttp2_outbound_item *qnext;
+  /* nonzero if this object is queued, except for DATA or HEADERS
+     which are attached to stream as item. */
+  uint8_t queued;
+};
+
+/*
+ * Initializes |item|.  No memory allocation is done in this function.
+ * Don't call nghttp2_outbound_item_free() until frame member is
+ * initialized.
+ */
+void nghttp2_outbound_item_init(nghttp2_outbound_item *item);
+
+/*
+ * Deallocates resource for |item|. If |item| is NULL, this function
+ * does nothing.
+ */
+void nghttp2_outbound_item_free(nghttp2_outbound_item *item, nghttp2_mem *mem);
+
+/*
+ * queue for nghttp2_outbound_item.
+ */
+typedef struct {
+  nghttp2_outbound_item *head, *tail;
+  /* number of items in this queue. */
+  size_t n;
+} nghttp2_outbound_queue;
+
+void nghttp2_outbound_queue_init(nghttp2_outbound_queue *q);
+
+/* Pushes |item| into |q| */
+void nghttp2_outbound_queue_push(nghttp2_outbound_queue *q,
+                                 nghttp2_outbound_item *item);
+
+/* Pops |item| at the top from |q|.  If |q| is empty, nothing
+   happens. */
+void nghttp2_outbound_queue_pop(nghttp2_outbound_queue *q);
+
+/* Returns the top item. */
+#define nghttp2_outbound_queue_top(Q) ((Q)->head)
+
+/* Returns the size of the queue */
+#define nghttp2_outbound_queue_size(Q) ((Q)->n)
+
+#endif /* NGHTTP2_OUTBOUND_ITEM_H */
diff --git a/tools/sdk/include/nghttp/nghttp2_pq.h b/tools/sdk/include/nghttp/nghttp2_pq.h
new file mode 100644
index 00000000..6b0ecfb4
--- /dev/null
+++ b/tools/sdk/include/nghttp/nghttp2_pq.h
@@ -0,0 +1,128 @@
+/*
+ * nghttp2 - HTTP/2 C Library
+ *
+ * Copyright (c) 2012 Tatsuhiro Tsujikawa
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NGHTTP2_PQ_H
+#define NGHTTP2_PQ_H
+
+#ifdef HAVE_CONFIG_H
+#include 
+#endif /* HAVE_CONFIG_H */
+
+#include 
+#include "nghttp2_int.h"
+#include "nghttp2_mem.h"
+
+/* Implementation of priority queue */
+
+typedef struct { size_t index; } nghttp2_pq_entry;
+
+typedef struct {
+  /* The pointer to the pointer to the item stored */
+  nghttp2_pq_entry **q;
+  /* Memory allocator */
+  nghttp2_mem *mem;
+  /* The number of items sotred */
+  size_t length;
+  /* The maximum number of items this pq can store. This is
+     automatically extended when length is reached to this value. */
+  size_t capacity;
+  /* The less function between items */
+  nghttp2_less less;
+} nghttp2_pq;
+
+/*
+ * Initializes priority queue |pq| with compare function |cmp|.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory.
+ */
+int nghttp2_pq_init(nghttp2_pq *pq, nghttp2_less less, nghttp2_mem *mem);
+
+/*
+ * Deallocates any resources allocated for |pq|.  The stored items are
+ * not freed by this function.
+ */
+void nghttp2_pq_free(nghttp2_pq *pq);
+
+/*
+ * Adds |item| to the priority queue |pq|.
+ *
+ * This function returns 0 if it succeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory.
+ */
+int nghttp2_pq_push(nghttp2_pq *pq, nghttp2_pq_entry *item);
+
+/*
+ * Returns item at the top of the queue |pq|. If the queue is empty,
+ * this function returns NULL.
+ */
+nghttp2_pq_entry *nghttp2_pq_top(nghttp2_pq *pq);
+
+/*
+ * Pops item at the top of the queue |pq|. The popped item is not
+ * freed by this function.
+ */
+void nghttp2_pq_pop(nghttp2_pq *pq);
+
+/*
+ * Returns nonzero if the queue |pq| is empty.
+ */
+int nghttp2_pq_empty(nghttp2_pq *pq);
+
+/*
+ * Returns the number of items in the queue |pq|.
+ */
+size_t nghttp2_pq_size(nghttp2_pq *pq);
+
+typedef int (*nghttp2_pq_item_cb)(nghttp2_pq_entry *item, void *arg);
+
+/*
+ * Updates each item in |pq| using function |fun| and re-construct
+ * priority queue. The |fun| must return non-zero if it modifies the
+ * item in a way that it affects ordering in the priority queue. The
+ * |arg| is passed to the 2nd parameter of |fun|.
+ */
+void nghttp2_pq_update(nghttp2_pq *pq, nghttp2_pq_item_cb fun, void *arg);
+
+/*
+ * Applys |fun| to each item in |pq|.  The |arg| is passed as arg
+ * parameter to callback function.  This function must not change the
+ * ordering key.  If the return value from callback is nonzero, this
+ * function returns 1 immediately without iterating remaining items.
+ * Otherwise this function returns 0.
+ */
+int nghttp2_pq_each(nghttp2_pq *pq, nghttp2_pq_item_cb fun, void *arg);
+
+/*
+ * Removes |item| from priority queue.
+ */
+void nghttp2_pq_remove(nghttp2_pq *pq, nghttp2_pq_entry *item);
+
+#endif /* NGHTTP2_PQ_H */
diff --git a/tools/sdk/include/nghttp/nghttp2_priority_spec.h b/tools/sdk/include/nghttp/nghttp2_priority_spec.h
new file mode 100644
index 00000000..98fac210
--- /dev/null
+++ b/tools/sdk/include/nghttp/nghttp2_priority_spec.h
@@ -0,0 +1,42 @@
+/*
+ * nghttp2 - HTTP/2 C Library
+ *
+ * Copyright (c) 2014 Tatsuhiro Tsujikawa
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NGHTTP2_PRIORITY_SPEC_H
+#define NGHTTP2_PRIORITY_SPEC_H
+
+#ifdef HAVE_CONFIG_H
+#include 
+#endif /* HAVE_CONFIG_H */
+
+#include 
+
+/*
+ * This function normalizes pri_spec->weight if it is out of range.
+ * If pri_spec->weight is less than NGHTTP2_MIN_WEIGHT, it is set to
+ * NGHTTP2_MIN_WEIGHT.  If pri_spec->weight is larger than
+ * NGHTTP2_MAX_WEIGHT, it is set to NGHTTP2_MAX_WEIGHT.
+ */
+void nghttp2_priority_spec_normalize_weight(nghttp2_priority_spec *pri_spec);
+
+#endif /* NGHTTP2_PRIORITY_SPEC_H */
diff --git a/tools/sdk/include/nghttp/nghttp2_queue.h b/tools/sdk/include/nghttp/nghttp2_queue.h
new file mode 100644
index 00000000..d872b07b
--- /dev/null
+++ b/tools/sdk/include/nghttp/nghttp2_queue.h
@@ -0,0 +1,49 @@
+/*
+ * nghttp2 - HTTP/2 C Library
+ *
+ * Copyright (c) 2012 Tatsuhiro Tsujikawa
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NGHTTP2_QUEUE_H
+#define NGHTTP2_QUEUE_H
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif /* HAVE_CONFIG_H */
+
+#include 
+
+typedef struct nghttp2_queue_cell {
+  void *data;
+  struct nghttp2_queue_cell *next;
+} nghttp2_queue_cell;
+
+typedef struct { nghttp2_queue_cell *front, *back; } nghttp2_queue;
+
+void nghttp2_queue_init(nghttp2_queue *queue);
+void nghttp2_queue_free(nghttp2_queue *queue);
+int nghttp2_queue_push(nghttp2_queue *queue, void *data);
+void nghttp2_queue_pop(nghttp2_queue *queue);
+void *nghttp2_queue_front(nghttp2_queue *queue);
+void *nghttp2_queue_back(nghttp2_queue *queue);
+int nghttp2_queue_empty(nghttp2_queue *queue);
+
+#endif /* NGHTTP2_QUEUE_H */
diff --git a/tools/sdk/include/nghttp/nghttp2_rcbuf.h b/tools/sdk/include/nghttp/nghttp2_rcbuf.h
new file mode 100644
index 00000000..29d1543e
--- /dev/null
+++ b/tools/sdk/include/nghttp/nghttp2_rcbuf.h
@@ -0,0 +1,80 @@
+/*
+ * nghttp2 - HTTP/2 C Library
+ *
+ * Copyright (c) 2016 Tatsuhiro Tsujikawa
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NGHTTP2_RCBUF_H
+#define NGHTTP2_RCBUF_H
+
+#ifdef HAVE_CONFIG_H
+#include 
+#endif /* HAVE_CONFIG_H */
+
+#include 
+
+struct nghttp2_rcbuf {
+  /* custom memory allocator belongs to the mem parameter when
+     creating this object. */
+  void *mem_user_data;
+  nghttp2_free free;
+  /* The pointer to the underlying buffer */
+  uint8_t *base;
+  /* Size of buffer pointed by |base|. */
+  size_t len;
+  /* Reference count */
+  int32_t ref;
+};
+
+/*
+ * Allocates nghttp2_rcbuf object with |size| as initial buffer size.
+ * When the function succeeds, the reference count becomes 1.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM:
+ *     Out of memory.
+ */
+int nghttp2_rcbuf_new(nghttp2_rcbuf **rcbuf_ptr, size_t size, nghttp2_mem *mem);
+
+/*
+ * Like nghttp2_rcbuf_new(), but initializes the buffer with |src| of
+ * length |srclen|.  This function allocates additional byte at the
+ * end and puts '\0' into it, so that the resulting buffer could be
+ * used as NULL-terminated string.  Still (*rcbuf_ptr)->len equals to
+ * |srclen|.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM:
+ *     Out of memory.
+ */
+int nghttp2_rcbuf_new2(nghttp2_rcbuf **rcbuf_ptr, const uint8_t *src,
+                       size_t srclen, nghttp2_mem *mem);
+
+/*
+ * Frees |rcbuf| itself, regardless of its reference cout.
+ */
+void nghttp2_rcbuf_del(nghttp2_rcbuf *rcbuf);
+
+#endif /* NGHTTP2_RCBUF_H */
diff --git a/tools/sdk/include/nghttp/nghttp2_session.h b/tools/sdk/include/nghttp/nghttp2_session.h
new file mode 100644
index 00000000..53470028
--- /dev/null
+++ b/tools/sdk/include/nghttp/nghttp2_session.h
@@ -0,0 +1,878 @@
+/*
+ * nghttp2 - HTTP/2 C Library
+ *
+ * Copyright (c) 2012 Tatsuhiro Tsujikawa
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NGHTTP2_SESSION_H
+#define NGHTTP2_SESSION_H
+
+#ifdef HAVE_CONFIG_H
+#include 
+#endif /* HAVE_CONFIG_H */
+
+#include 
+#include "nghttp2_map.h"
+#include "nghttp2_frame.h"
+#include "nghttp2_hd.h"
+#include "nghttp2_stream.h"
+#include "nghttp2_outbound_item.h"
+#include "nghttp2_int.h"
+#include "nghttp2_buf.h"
+#include "nghttp2_callbacks.h"
+#include "nghttp2_mem.h"
+
+/* The global variable for tests where we want to disable strict
+   preface handling. */
+extern int nghttp2_enable_strict_preface;
+
+/*
+ * Option flags.
+ */
+typedef enum {
+  NGHTTP2_OPTMASK_NO_AUTO_WINDOW_UPDATE = 1 << 0,
+  NGHTTP2_OPTMASK_NO_RECV_CLIENT_MAGIC = 1 << 1,
+  NGHTTP2_OPTMASK_NO_HTTP_MESSAGING = 1 << 2,
+  NGHTTP2_OPTMASK_NO_AUTO_PING_ACK = 1 << 3
+} nghttp2_optmask;
+
+/*
+ * bitmask for built-in type to enable the default handling for that
+ * type of the frame.
+ */
+typedef enum {
+  NGHTTP2_TYPEMASK_NONE = 0,
+  NGHTTP2_TYPEMASK_ALTSVC = 1 << 0
+} nghttp2_typemask;
+
+typedef enum {
+  NGHTTP2_OB_POP_ITEM,
+  NGHTTP2_OB_SEND_DATA,
+  NGHTTP2_OB_SEND_NO_COPY,
+  NGHTTP2_OB_SEND_CLIENT_MAGIC
+} nghttp2_outbound_state;
+
+typedef struct {
+  nghttp2_outbound_item *item;
+  nghttp2_bufs framebufs;
+  nghttp2_outbound_state state;
+} nghttp2_active_outbound_item;
+
+/* Buffer length for inbound raw byte stream used in
+   nghttp2_session_recv(). */
+#define NGHTTP2_INBOUND_BUFFER_LENGTH 3072//16384--LiuHan/08.12
+
+/* The default maximum number of incoming reserved streams */
+#define NGHTTP2_MAX_INCOMING_RESERVED_STREAMS 200
+
+/* Even if we have less SETTINGS_MAX_CONCURRENT_STREAMS than this
+   number, we keep NGHTTP2_MIN_IDLE_STREAMS streams in idle state */
+#define NGHTTP2_MIN_IDLE_STREAMS 16
+
+/* The maximum number of items in outbound queue, which is considered
+   as flooding caused by peer.  All frames are not considered here.
+   We only consider PING + ACK and SETTINGS + ACK.  This is because
+   they both are response to the frame initiated by peer and peer can
+   send as many of them as they want.  If peer does not read network,
+   response frames are stacked up, which leads to memory exhaustion.
+   The value selected here is arbitrary, but safe value and if we have
+   these frames in this number, it is considered suspicious. */
+#define NGHTTP2_MAX_OBQ_FLOOD_ITEM 10000
+
+/* The default value of maximum number of concurrent streams. */
+#define NGHTTP2_DEFAULT_MAX_CONCURRENT_STREAMS 0xffffffffu
+
+/* Internal state when receiving incoming frame */
+typedef enum {
+  /* Receiving frame header */
+  NGHTTP2_IB_READ_CLIENT_MAGIC,
+  NGHTTP2_IB_READ_FIRST_SETTINGS,
+  NGHTTP2_IB_READ_HEAD,
+  NGHTTP2_IB_READ_NBYTE,
+  NGHTTP2_IB_READ_HEADER_BLOCK,
+  NGHTTP2_IB_IGN_HEADER_BLOCK,
+  NGHTTP2_IB_IGN_PAYLOAD,
+  NGHTTP2_IB_FRAME_SIZE_ERROR,
+  NGHTTP2_IB_READ_SETTINGS,
+  NGHTTP2_IB_READ_GOAWAY_DEBUG,
+  NGHTTP2_IB_EXPECT_CONTINUATION,
+  NGHTTP2_IB_IGN_CONTINUATION,
+  NGHTTP2_IB_READ_PAD_DATA,
+  NGHTTP2_IB_READ_DATA,
+  NGHTTP2_IB_IGN_DATA,
+  NGHTTP2_IB_IGN_ALL,
+  NGHTTP2_IB_READ_ALTSVC_PAYLOAD,
+  NGHTTP2_IB_READ_EXTENSION_PAYLOAD
+} nghttp2_inbound_state;
+
+typedef struct {
+  nghttp2_frame frame;
+  /* Storage for extension frame payload.  frame->ext.payload points
+     to this structure to avoid frequent memory allocation. */
+  nghttp2_ext_frame_payload ext_frame_payload;
+  /* The received SETTINGS entry.  For the standard settings entries,
+     we only keep the last seen value.  For
+     SETTINGS_HEADER_TABLE_SIZE, we also keep minimum value in the
+     last index. */
+  nghttp2_settings_entry *iv;
+  /* buffer pointers to small buffer, raw_sbuf */
+  nghttp2_buf sbuf;
+  /* buffer pointers to large buffer, raw_lbuf */
+  nghttp2_buf lbuf;
+  /* Large buffer, malloced on demand */
+  uint8_t *raw_lbuf;
+  /* The number of entry filled in |iv| */
+  size_t niv;
+  /* The number of entries |iv| can store. */
+  size_t max_niv;
+  /* How many bytes we still need to receive for current frame */
+  size_t payloadleft;
+  /* padding length for the current frame */
+  size_t padlen;
+  nghttp2_inbound_state state;
+  /* Small buffer.  Currently the largest contiguous chunk to buffer
+     is frame header.  We buffer part of payload, but they are smaller
+     than frame header. */
+  uint8_t raw_sbuf[NGHTTP2_FRAME_HDLEN];
+} nghttp2_inbound_frame;
+
+typedef struct {
+  uint32_t header_table_size;
+  uint32_t enable_push;
+  uint32_t max_concurrent_streams;
+  uint32_t initial_window_size;
+  uint32_t max_frame_size;
+  uint32_t max_header_list_size;
+} nghttp2_settings_storage;
+
+typedef enum {
+  NGHTTP2_GOAWAY_NONE = 0,
+  /* Flag means that connection should be terminated after sending GOAWAY. */
+  NGHTTP2_GOAWAY_TERM_ON_SEND = 0x1,
+  /* Flag means GOAWAY to terminate session has been sent */
+  NGHTTP2_GOAWAY_TERM_SENT = 0x2,
+  /* Flag means GOAWAY was sent */
+  NGHTTP2_GOAWAY_SENT = 0x4,
+  /* Flag means GOAWAY was received */
+  NGHTTP2_GOAWAY_RECV = 0x8
+} nghttp2_goaway_flag;
+
+/* nghttp2_inflight_settings stores the SETTINGS entries which local
+   endpoint has sent to the remote endpoint, and has not received ACK
+   yet. */
+struct nghttp2_inflight_settings {
+  struct nghttp2_inflight_settings *next;
+  nghttp2_settings_entry *iv;
+  size_t niv;
+};
+
+typedef struct nghttp2_inflight_settings nghttp2_inflight_settings;
+
+struct nghttp2_session {
+  nghttp2_map /*  */ streams;
+  /* root of dependency tree*/
+  nghttp2_stream root;
+  /* Queue for outbound urgent frames (PING and SETTINGS) */
+  nghttp2_outbound_queue ob_urgent;
+  /* Queue for non-DATA frames */
+  nghttp2_outbound_queue ob_reg;
+  /* Queue for outbound stream-creating HEADERS (request or push
+     response) frame, which are subject to
+     SETTINGS_MAX_CONCURRENT_STREAMS limit. */
+  nghttp2_outbound_queue ob_syn;
+  nghttp2_active_outbound_item aob;
+  nghttp2_inbound_frame iframe;
+  nghttp2_hd_deflater hd_deflater;
+  nghttp2_hd_inflater hd_inflater;
+  nghttp2_session_callbacks callbacks;
+  /* Memory allocator */
+  nghttp2_mem mem;
+  /* Base value when we schedule next DATA frame write.  This is
+     updated when one frame was written. */
+  uint64_t last_cycle;
+  void *user_data;
+  /* Points to the latest incoming closed stream.  NULL if there is no
+     closed stream.  Only used when session is initialized as
+     server. */
+  nghttp2_stream *closed_stream_head;
+  /* Points to the oldest incoming closed stream.  NULL if there is no
+     closed stream.  Only used when session is initialized as
+     server. */
+  nghttp2_stream *closed_stream_tail;
+  /* Points to the latest idle stream.  NULL if there is no idle
+     stream.  Only used when session is initialized as server .*/
+  nghttp2_stream *idle_stream_head;
+  /* Points to the oldest idle stream.  NULL if there is no idle
+     stream.  Only used when session is initialized as erver. */
+  nghttp2_stream *idle_stream_tail;
+  /* Queue of In-flight SETTINGS values.  SETTINGS bearing ACK is not
+     considered as in-flight. */
+  nghttp2_inflight_settings *inflight_settings_head;
+  /* The number of outgoing streams. This will be capped by
+     remote_settings.max_concurrent_streams. */
+  size_t num_outgoing_streams;
+  /* The number of incoming streams. This will be capped by
+     local_settings.max_concurrent_streams. */
+  size_t num_incoming_streams;
+  /* The number of incoming reserved streams.  This is the number of
+     streams in reserved (remote) state.  RFC 7540 does not limit this
+     number.  nghttp2 offers
+     nghttp2_option_set_max_reserved_remote_streams() to achieve this.
+     If it is used, num_incoming_streams is capped by
+     max_incoming_reserved_streams.  Client application should
+     consider to set this because without that server can send
+     arbitrary number of PUSH_PROMISE, and exhaust client's memory. */
+  size_t num_incoming_reserved_streams;
+  /* The maximum number of incoming reserved streams (reserved
+     (remote) state).  RST_STREAM will be sent for the pushed stream
+     which exceeds this limit. */
+  size_t max_incoming_reserved_streams;
+  /* The number of closed streams still kept in |streams| hash.  The
+     closed streams can be accessed through single linked list
+     |closed_stream_head|.  The current implementation only keeps
+     incoming streams and session is initialized as server. */
+  size_t num_closed_streams;
+  /* The number of idle streams kept in |streams| hash.  The idle
+     streams can be accessed through doubly linked list
+     |idle_stream_head|.  The current implementation only keeps idle
+     streams if session is initialized as server. */
+  size_t num_idle_streams;
+  /* The number of bytes allocated for nvbuf */
+  size_t nvbuflen;
+  /* Counter for detecting flooding in outbound queue */
+  size_t obq_flood_counter_;
+  /* The maximum length of header block to send.  Calculated by the
+     same way as nghttp2_hd_deflate_bound() does. */
+  size_t max_send_header_block_length;
+  /* Next Stream ID. Made unsigned int to detect >= (1 << 31). */
+  uint32_t next_stream_id;
+  /* The last stream ID this session initiated.  For client session,
+     this is the last stream ID it has sent.  For server session, it
+     is the last promised stream ID sent in PUSH_PROMISE. */
+  int32_t last_sent_stream_id;
+  /* The largest stream ID received so far */
+  int32_t last_recv_stream_id;
+  /* The largest stream ID which has been processed in some way. This
+     value will be used as last-stream-id when sending GOAWAY
+     frame. */
+  int32_t last_proc_stream_id;
+  /* Counter of unique ID of PING. Wraps when it exceeds
+     NGHTTP2_MAX_UNIQUE_ID */
+  uint32_t next_unique_id;
+  /* This is the last-stream-ID we have sent in GOAWAY */
+  int32_t local_last_stream_id;
+  /* This is the value in GOAWAY frame received from remote endpoint. */
+  int32_t remote_last_stream_id;
+  /* Current sender window size. This value is computed against the
+     current initial window size of remote endpoint. */
+  int32_t remote_window_size;
+  /* Keep track of the number of bytes received without
+     WINDOW_UPDATE. This could be negative after submitting negative
+     value to WINDOW_UPDATE. */
+  int32_t recv_window_size;
+  /* The number of bytes consumed by the application and now is
+     subject to WINDOW_UPDATE.  This is only used when auto
+     WINDOW_UPDATE is turned off. */
+  int32_t consumed_size;
+  /* The amount of recv_window_size cut using submitting negative
+     value to WINDOW_UPDATE */
+  int32_t recv_reduction;
+  /* window size for local flow control. It is initially set to
+     NGHTTP2_INITIAL_CONNECTION_WINDOW_SIZE and could be
+     increased/decreased by submitting WINDOW_UPDATE. See
+     nghttp2_submit_window_update(). */
+  int32_t local_window_size;
+  /* Settings value received from the remote endpoint. We just use ID
+     as index. The index = 0 is unused. */
+  nghttp2_settings_storage remote_settings;
+  /* Settings value of the local endpoint. */
+  nghttp2_settings_storage local_settings;
+  /* Option flags. This is bitwise-OR of 0 or more of nghttp2_optmask. */
+  uint32_t opt_flags;
+  /* Unacked local SETTINGS_MAX_CONCURRENT_STREAMS value. We use this
+     to refuse the incoming stream if it exceeds this value. */
+  uint32_t pending_local_max_concurrent_stream;
+  /* The bitwose OR of zero or more of nghttp2_typemask to indicate
+     that the default handling of extension frame is enabled. */
+  uint32_t builtin_recv_ext_types;
+  /* Unacked local ENABLE_PUSH value.  We use this to refuse
+     PUSH_PROMISE before SETTINGS ACK is received. */
+  uint8_t pending_enable_push;
+  /* Nonzero if the session is server side. */
+  uint8_t server;
+  /* Flags indicating GOAWAY is sent and/or recieved. The flags are
+     composed by bitwise OR-ing nghttp2_goaway_flag. */
+  uint8_t goaway_flags;
+  /* This flag is used to reduce excessive queuing of WINDOW_UPDATE to
+     this session.  The nonzero does not necessarily mean
+     WINDOW_UPDATE is not queued. */
+  uint8_t window_update_queued;
+  /* Bitfield of extension frame types that application is willing to
+     receive.  To designate the bit of given frame type i, use
+     user_recv_ext_types[i / 8] & (1 << (i & 0x7)).  First 10 frame
+     types are standard frame types and not used in this bitfield.  If
+     bit is set, it indicates that incoming frame with that type is
+     passed to user defined callbacks, otherwise they are ignored. */
+  uint8_t user_recv_ext_types[32];
+};
+
+/* Struct used when updating initial window size of each active
+   stream. */
+typedef struct {
+  nghttp2_session *session;
+  int32_t new_window_size, old_window_size;
+} nghttp2_update_window_size_arg;
+
+typedef struct {
+  nghttp2_session *session;
+  /* linked list of streams to close */
+  nghttp2_stream *head;
+  int32_t last_stream_id;
+  /* nonzero if GOAWAY is sent to peer, which means we are going to
+     close incoming streams.  zero if GOAWAY is received from peer and
+     we are going to close outgoing streams. */
+  int incoming;
+} nghttp2_close_stream_on_goaway_arg;
+
+/* TODO stream timeout etc */
+
+/*
+ * Returns nonzero value if |stream_id| is initiated by local
+ * endpoint.
+ */
+int nghttp2_session_is_my_stream_id(nghttp2_session *session,
+                                    int32_t stream_id);
+
+/*
+ * Adds |item| to the outbound queue in |session|.  When this function
+ * succeeds, it takes ownership of |item|. So caller must not free it
+ * on success.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory.
+ * NGHTTP2_ERR_STREAM_CLOSED
+ *     Stream already closed (DATA and PUSH_PROMISE frame only)
+ */
+int nghttp2_session_add_item(nghttp2_session *session,
+                             nghttp2_outbound_item *item);
+
+/*
+ * Adds RST_STREAM frame for the stream |stream_id| with the error
+ * code |error_code|. This is a convenient function built on top of
+ * nghttp2_session_add_frame() to add RST_STREAM easily.
+ *
+ * This function simply returns 0 without adding RST_STREAM frame if
+ * given stream is in NGHTTP2_STREAM_CLOSING state, because multiple
+ * RST_STREAM for a stream is redundant.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory.
+ */
+int nghttp2_session_add_rst_stream(nghttp2_session *session, int32_t stream_id,
+                                   uint32_t error_code);
+
+/*
+ * Adds PING frame. This is a convenient functin built on top of
+ * nghttp2_session_add_frame() to add PING easily.
+ *
+ * If the |opaque_data| is not NULL, it must point to 8 bytes memory
+ * region of data. The data pointed by |opaque_data| is copied. It can
+ * be NULL. In this case, 8 bytes NULL is used.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory.
+ * NGHTTP2_ERR_FLOODED
+ *     There are too many items in outbound queue; this only happens
+ *     if NGHTTP2_FLAG_ACK is set in |flags|
+ */
+int nghttp2_session_add_ping(nghttp2_session *session, uint8_t flags,
+                             const uint8_t *opaque_data);
+
+/*
+ * Adds GOAWAY frame with the last-stream-ID |last_stream_id| and the
+ * error code |error_code|. This is a convenient function built on top
+ * of nghttp2_session_add_frame() to add GOAWAY easily.  The
+ * |aux_flags| are bitwise-OR of one or more of
+ * nghttp2_goaway_aux_flag.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory.
+ * NGHTTP2_ERR_INVALID_ARGUMENT
+ *     The |opaque_data_len| is too large.
+ */
+int nghttp2_session_add_goaway(nghttp2_session *session, int32_t last_stream_id,
+                               uint32_t error_code, const uint8_t *opaque_data,
+                               size_t opaque_data_len, uint8_t aux_flags);
+
+/*
+ * Adds WINDOW_UPDATE frame with stream ID |stream_id| and
+ * window-size-increment |window_size_increment|. This is a convenient
+ * function built on top of nghttp2_session_add_frame() to add
+ * WINDOW_UPDATE easily.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory.
+ */
+int nghttp2_session_add_window_update(nghttp2_session *session, uint8_t flags,
+                                      int32_t stream_id,
+                                      int32_t window_size_increment);
+
+/*
+ * Adds SETTINGS frame.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory.
+ * NGHTTP2_ERR_FLOODED
+ *     There are too many items in outbound queue; this only happens
+ *     if NGHTTP2_FLAG_ACK is set in |flags|
+ */
+int nghttp2_session_add_settings(nghttp2_session *session, uint8_t flags,
+                                 const nghttp2_settings_entry *iv, size_t niv);
+
+/*
+ * Creates new stream in |session| with stream ID |stream_id|,
+ * priority |pri_spec| and flags |flags|.  The |flags| is bitwise OR
+ * of nghttp2_stream_flag.  Since this function is called when initial
+ * HEADERS is sent or received, these flags are taken from it.  The
+ * state of stream is set to |initial_state|. The |stream_user_data|
+ * is a pointer to the arbitrary user supplied data to be associated
+ * to this stream.
+ *
+ * If |initial_state| is NGHTTP2_STREAM_RESERVED, this function sets
+ * NGHTTP2_STREAM_FLAG_PUSH flag set.
+ *
+ * This function returns a pointer to created new stream object, or
+ * NULL.
+ *
+ * This function adjusts neither the number of closed streams or idle
+ * streams.  The caller should manually call
+ * nghttp2_session_adjust_closed_stream() or
+ * nghttp2_session_adjust_idle_stream() respectively.
+ */
+nghttp2_stream *nghttp2_session_open_stream(nghttp2_session *session,
+                                            int32_t stream_id, uint8_t flags,
+                                            nghttp2_priority_spec *pri_spec,
+                                            nghttp2_stream_state initial_state,
+                                            void *stream_user_data);
+
+/*
+ * Closes stream whose stream ID is |stream_id|. The reason of closure
+ * is indicated by the |error_code|. When closing the stream,
+ * on_stream_close_callback will be called.
+ *
+ * If the session is initialized as server and |stream| is incoming
+ * stream, stream is just marked closed and this function calls
+ * nghttp2_session_keep_closed_stream() with |stream|.  Otherwise,
+ * |stream| will be deleted from memory.
+ *
+ * This function returns 0 if it succeeds, or one the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory
+ * NGHTTP2_ERR_INVALID_ARGUMENT
+ *     The specified stream does not exist.
+ * NGHTTP2_ERR_CALLBACK_FAILURE
+ *     The callback function failed.
+ */
+int nghttp2_session_close_stream(nghttp2_session *session, int32_t stream_id,
+                                 uint32_t error_code);
+
+/*
+ * Deletes |stream| from memory.  After this function returns, stream
+ * cannot be accessed.
+ *
+ * This function returns 0 if it succeeds, or one the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory
+ */
+int nghttp2_session_destroy_stream(nghttp2_session *session,
+                                   nghttp2_stream *stream);
+
+/*
+ * Tries to keep incoming closed stream |stream|.  Due to the
+ * limitation of maximum number of streams in memory, |stream| is not
+ * closed and just deleted from memory (see
+ * nghttp2_session_destroy_stream).
+ */
+void nghttp2_session_keep_closed_stream(nghttp2_session *session,
+                                        nghttp2_stream *stream);
+
+/*
+ * Appends |stream| to linked list |session->idle_stream_head|.  We
+ * apply fixed limit for list size.  To fit into that limit, one or
+ * more oldest streams are removed from list as necessary.
+ */
+void nghttp2_session_keep_idle_stream(nghttp2_session *session,
+                                      nghttp2_stream *stream);
+
+/*
+ * Detaches |stream| from idle streams linked list.
+ */
+void nghttp2_session_detach_idle_stream(nghttp2_session *session,
+                                        nghttp2_stream *stream);
+
+/*
+ * Deletes closed stream to ensure that number of incoming streams
+ * including active and closed is in the maximum number of allowed
+ * stream.
+ *
+ * This function returns 0 if it succeeds, or one the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory
+ */
+int nghttp2_session_adjust_closed_stream(nghttp2_session *session);
+
+/*
+ * Deletes idle stream to ensure that number of idle streams is in
+ * certain limit.
+ *
+ * This function returns 0 if it succeeds, or one the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory
+ */
+int nghttp2_session_adjust_idle_stream(nghttp2_session *session);
+
+/*
+ * If further receptions and transmissions over the stream |stream_id|
+ * are disallowed, close the stream with error code NGHTTP2_NO_ERROR.
+ *
+ * This function returns 0 if it
+ * succeeds, or one of the following negative error codes:
+ *
+ * NGHTTP2_ERR_INVALID_ARGUMENT
+ *     The specified stream does not exist.
+ */
+int nghttp2_session_close_stream_if_shut_rdwr(nghttp2_session *session,
+                                              nghttp2_stream *stream);
+
+int nghttp2_session_on_request_headers_received(nghttp2_session *session,
+                                                nghttp2_frame *frame);
+
+int nghttp2_session_on_response_headers_received(nghttp2_session *session,
+                                                 nghttp2_frame *frame,
+                                                 nghttp2_stream *stream);
+
+int nghttp2_session_on_push_response_headers_received(nghttp2_session *session,
+                                                      nghttp2_frame *frame,
+                                                      nghttp2_stream *stream);
+
+/*
+ * Called when HEADERS is received, assuming |frame| is properly
+ * initialized.  This function does first validate received frame and
+ * then open stream and call callback functions.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory.
+ * NGHTTP2_ERR_IGN_HEADER_BLOCK
+ *     Frame was rejected and header block must be decoded but
+ *     result must be ignored.
+ * NGHTTP2_ERR_CALLBACK_FAILURE
+ *     The read_callback failed
+ */
+int nghttp2_session_on_headers_received(nghttp2_session *session,
+                                        nghttp2_frame *frame,
+                                        nghttp2_stream *stream);
+
+/*
+ * Called when PRIORITY is received, assuming |frame| is properly
+ * initialized.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory.
+ * NGHTTP2_ERR_CALLBACK_FAILURE
+ *     The read_callback failed
+ */
+int nghttp2_session_on_priority_received(nghttp2_session *session,
+                                         nghttp2_frame *frame);
+
+/*
+ * Called when RST_STREAM is received, assuming |frame| is properly
+ * initialized.
+ *
+ * This function returns 0 if it succeeds, or one the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory
+ * NGHTTP2_ERR_CALLBACK_FAILURE
+ *     The read_callback failed
+ */
+int nghttp2_session_on_rst_stream_received(nghttp2_session *session,
+                                           nghttp2_frame *frame);
+
+/*
+ * Called when SETTINGS is received, assuming |frame| is properly
+ * initialized. If |noack| is non-zero, SETTINGS with ACK will not be
+ * submitted. If |frame| has NGHTTP2_FLAG_ACK flag set, no SETTINGS
+ * with ACK will not be submitted regardless of |noack|.
+ *
+ * This function returns 0 if it succeeds, or one the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory
+ * NGHTTP2_ERR_CALLBACK_FAILURE
+ *     The read_callback failed
+ * NGHTTP2_ERR_FLOODED
+ *     There are too many items in outbound queue, and this is most
+ *     likely caused by misbehaviour of peer.
+ */
+int nghttp2_session_on_settings_received(nghttp2_session *session,
+                                         nghttp2_frame *frame, int noack);
+
+/*
+ * Called when PUSH_PROMISE is received, assuming |frame| is properly
+ * initialized.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory.
+ * NGHTTP2_ERR_IGN_HEADER_BLOCK
+ *     Frame was rejected and header block must be decoded but
+ *     result must be ignored.
+ * NGHTTP2_ERR_CALLBACK_FAILURE
+ *     The read_callback failed
+ */
+int nghttp2_session_on_push_promise_received(nghttp2_session *session,
+                                             nghttp2_frame *frame);
+
+/*
+ * Called when PING is received, assuming |frame| is properly
+ * initialized.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory.
+ * NGHTTP2_ERR_CALLBACK_FAILURE
+ *   The callback function failed.
+ * NGHTTP2_ERR_FLOODED
+ *     There are too many items in outbound queue, and this is most
+ *     likely caused by misbehaviour of peer.
+ */
+int nghttp2_session_on_ping_received(nghttp2_session *session,
+                                     nghttp2_frame *frame);
+
+/*
+ * Called when GOAWAY is received, assuming |frame| is properly
+ * initialized.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory.
+ * NGHTTP2_ERR_CALLBACK_FAILURE
+ *   The callback function failed.
+ */
+int nghttp2_session_on_goaway_received(nghttp2_session *session,
+                                       nghttp2_frame *frame);
+
+/*
+ * Called when WINDOW_UPDATE is recieved, assuming |frame| is properly
+ * initialized.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory.
+ * NGHTTP2_ERR_CALLBACK_FAILURE
+ *   The callback function failed.
+ */
+int nghttp2_session_on_window_update_received(nghttp2_session *session,
+                                              nghttp2_frame *frame);
+
+/*
+ * Called when ALTSVC is recieved, assuming |frame| is properly
+ * initialized.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_CALLBACK_FAILURE
+ *   The callback function failed.
+ */
+int nghttp2_session_on_altsvc_received(nghttp2_session *session,
+                                       nghttp2_frame *frame);
+
+/*
+ * Called when DATA is received, assuming |frame| is properly
+ * initialized.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory.
+ * NGHTTP2_ERR_CALLBACK_FAILURE
+ *   The callback function failed.
+ */
+int nghttp2_session_on_data_received(nghttp2_session *session,
+                                     nghttp2_frame *frame);
+
+/*
+ * Returns nghttp2_stream* object whose stream ID is |stream_id|.  It
+ * could be NULL if such stream does not exist.  This function returns
+ * NULL if stream is marked as closed.
+ */
+nghttp2_stream *nghttp2_session_get_stream(nghttp2_session *session,
+                                           int32_t stream_id);
+
+/*
+ * This function behaves like nghttp2_session_get_stream(), but it
+ * returns stream object even if it is marked as closed or in
+ * NGHTTP2_STREAM_IDLE state.
+ */
+nghttp2_stream *nghttp2_session_get_stream_raw(nghttp2_session *session,
+                                               int32_t stream_id);
+
+/*
+ * Packs DATA frame |frame| in wire frame format and stores it in
+ * |bufs|.  Payload will be read using |aux_data->data_prd|.  The
+ * length of payload is at most |datamax| bytes.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_DEFERRED
+ *     The DATA frame is postponed.
+ * NGHTTP2_ERR_TEMPORAL_CALLBACK_FAILURE
+ *     The read_callback failed (stream error).
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory.
+ * NGHTTP2_ERR_CALLBACK_FAILURE
+ *     The read_callback failed (session error).
+ */
+int nghttp2_session_pack_data(nghttp2_session *session, nghttp2_bufs *bufs,
+                              size_t datamax, nghttp2_frame *frame,
+                              nghttp2_data_aux_data *aux_data,
+                              nghttp2_stream *stream);
+
+/*
+ * Pops and returns next item to send.  If there is no such item,
+ * returns NULL.  This function takes into account max concurrent
+ * streams.  That means if session->ob_syn has item and max concurrent
+ * streams is reached, the even if other queues contain items, then
+ * this function returns NULL.
+ */
+nghttp2_outbound_item *
+nghttp2_session_pop_next_ob_item(nghttp2_session *session);
+
+/*
+ * Returns next item to send.  If there is no such item, this function
+ * returns NULL.  This function takes into account max concurrent
+ * streams.  That means if session->ob_syn has item and max concurrent
+ * streams is reached, the even if other queues contain items, then
+ * this function returns NULL.
+ */
+nghttp2_outbound_item *
+nghttp2_session_get_next_ob_item(nghttp2_session *session);
+
+/*
+ * Updates local settings with the |iv|. The number of elements in the
+ * array pointed by the |iv| is given by the |niv|.  This function
+ * assumes that the all settings_id member in |iv| are in range 1 to
+ * NGHTTP2_SETTINGS_MAX, inclusive.
+ *
+ * While updating individual stream's local window size, if the window
+ * size becomes strictly larger than NGHTTP2_MAX_WINDOW_SIZE,
+ * RST_STREAM is issued against such a stream.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory
+ */
+int nghttp2_session_update_local_settings(nghttp2_session *session,
+                                          nghttp2_settings_entry *iv,
+                                          size_t niv);
+
+/*
+ * Re-prioritize |stream|. The new priority specification is
+ * |pri_spec|.  Caller must ensure that stream->hd.stream_id !=
+ * pri_spec->stream_id.
+ *
+ * This function does not adjust the number of idle streams.  The
+ * caller should call nghttp2_session_adjust_idle_stream() later.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory
+ */
+int nghttp2_session_reprioritize_stream(nghttp2_session *session,
+                                        nghttp2_stream *stream,
+                                        const nghttp2_priority_spec *pri_spec);
+
+/*
+ * Terminates current |session| with the |error_code|.  The |reason|
+ * is NULL-terminated debug string.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory.
+ * NGHTTP2_ERR_INVALID_ARGUMENT
+ *     The |reason| is too long.
+ */
+int nghttp2_session_terminate_session_with_reason(nghttp2_session *session,
+                                                  uint32_t error_code,
+                                                  const char *reason);
+
+#endif /* NGHTTP2_SESSION_H */
diff --git a/tools/sdk/include/nghttp/nghttp2_stream.h b/tools/sdk/include/nghttp/nghttp2_stream.h
new file mode 100644
index 00000000..da0e5d53
--- /dev/null
+++ b/tools/sdk/include/nghttp/nghttp2_stream.h
@@ -0,0 +1,436 @@
+/*
+ * nghttp2 - HTTP/2 C Library
+ *
+ * Copyright (c) 2012 Tatsuhiro Tsujikawa
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NGHTTP2_STREAM_H
+#define NGHTTP2_STREAM_H
+
+#ifdef HAVE_CONFIG_H
+#include 
+#endif /* HAVE_CONFIG_H */
+
+#include 
+#include "nghttp2_outbound_item.h"
+#include "nghttp2_map.h"
+#include "nghttp2_pq.h"
+#include "nghttp2_int.h"
+
+/*
+ * If local peer is stream initiator:
+ * NGHTTP2_STREAM_OPENING : upon sending request HEADERS
+ * NGHTTP2_STREAM_OPENED : upon receiving response HEADERS
+ * NGHTTP2_STREAM_CLOSING : upon queuing RST_STREAM
+ *
+ * If remote peer is stream initiator:
+ * NGHTTP2_STREAM_OPENING : upon receiving request HEADERS
+ * NGHTTP2_STREAM_OPENED : upon sending response HEADERS
+ * NGHTTP2_STREAM_CLOSING : upon queuing RST_STREAM
+ */
+typedef enum {
+  /* Initial state */
+  NGHTTP2_STREAM_INITIAL,
+  /* For stream initiator: request HEADERS has been sent, but response
+     HEADERS has not been received yet.  For receiver: request HEADERS
+     has been received, but it does not send response HEADERS yet. */
+  NGHTTP2_STREAM_OPENING,
+  /* For stream initiator: response HEADERS is received. For receiver:
+     response HEADERS is sent. */
+  NGHTTP2_STREAM_OPENED,
+  /* RST_STREAM is received, but somehow we need to keep stream in
+     memory. */
+  NGHTTP2_STREAM_CLOSING,
+  /* PUSH_PROMISE is received or sent */
+  NGHTTP2_STREAM_RESERVED,
+  /* Stream is created in this state if it is used as anchor in
+     dependency tree. */
+  NGHTTP2_STREAM_IDLE
+} nghttp2_stream_state;
+
+typedef enum {
+  NGHTTP2_SHUT_NONE = 0,
+  /* Indicates further receptions will be disallowed. */
+  NGHTTP2_SHUT_RD = 0x01,
+  /* Indicates further transmissions will be disallowed. */
+  NGHTTP2_SHUT_WR = 0x02,
+  /* Indicates both further receptions and transmissions will be
+     disallowed. */
+  NGHTTP2_SHUT_RDWR = NGHTTP2_SHUT_RD | NGHTTP2_SHUT_WR
+} nghttp2_shut_flag;
+
+typedef enum {
+  NGHTTP2_STREAM_FLAG_NONE = 0,
+  /* Indicates that this stream is pushed stream and not opened
+     yet. */
+  NGHTTP2_STREAM_FLAG_PUSH = 0x01,
+  /* Indicates that this stream was closed */
+  NGHTTP2_STREAM_FLAG_CLOSED = 0x02,
+  /* Indicates the item is deferred due to flow control. */
+  NGHTTP2_STREAM_FLAG_DEFERRED_FLOW_CONTROL = 0x04,
+  /* Indicates the item is deferred by user callback */
+  NGHTTP2_STREAM_FLAG_DEFERRED_USER = 0x08,
+  /* bitwise OR of NGHTTP2_STREAM_FLAG_DEFERRED_FLOW_CONTROL and
+     NGHTTP2_STREAM_FLAG_DEFERRED_USER. */
+  NGHTTP2_STREAM_FLAG_DEFERRED_ALL = 0x0c
+
+} nghttp2_stream_flag;
+
+/* HTTP related flags to enforce HTTP semantics */
+typedef enum {
+  NGHTTP2_HTTP_FLAG_NONE = 0,
+  /* header field seen so far */
+  NGHTTP2_HTTP_FLAG__AUTHORITY = 1,
+  NGHTTP2_HTTP_FLAG__PATH = 1 << 1,
+  NGHTTP2_HTTP_FLAG__METHOD = 1 << 2,
+  NGHTTP2_HTTP_FLAG__SCHEME = 1 << 3,
+  /* host is not pseudo header, but we require either host or
+     :authority */
+  NGHTTP2_HTTP_FLAG_HOST = 1 << 4,
+  NGHTTP2_HTTP_FLAG__STATUS = 1 << 5,
+  /* required header fields for HTTP request except for CONNECT
+     method. */
+  NGHTTP2_HTTP_FLAG_REQ_HEADERS = NGHTTP2_HTTP_FLAG__METHOD |
+                                  NGHTTP2_HTTP_FLAG__PATH |
+                                  NGHTTP2_HTTP_FLAG__SCHEME,
+  NGHTTP2_HTTP_FLAG_PSEUDO_HEADER_DISALLOWED = 1 << 6,
+  /* HTTP method flags */
+  NGHTTP2_HTTP_FLAG_METH_CONNECT = 1 << 7,
+  NGHTTP2_HTTP_FLAG_METH_HEAD = 1 << 8,
+  NGHTTP2_HTTP_FLAG_METH_OPTIONS = 1 << 9,
+  NGHTTP2_HTTP_FLAG_METH_UPGRADE_WORKAROUND = 1 << 10,
+  NGHTTP2_HTTP_FLAG_METH_ALL = NGHTTP2_HTTP_FLAG_METH_CONNECT |
+                               NGHTTP2_HTTP_FLAG_METH_HEAD |
+                               NGHTTP2_HTTP_FLAG_METH_OPTIONS |
+                               NGHTTP2_HTTP_FLAG_METH_UPGRADE_WORKAROUND,
+  /* :path category */
+  /* path starts with "/" */
+  NGHTTP2_HTTP_FLAG_PATH_REGULAR = 1 << 11,
+  /* path "*" */
+  NGHTTP2_HTTP_FLAG_PATH_ASTERISK = 1 << 12,
+  /* scheme */
+  /* "http" or "https" scheme */
+  NGHTTP2_HTTP_FLAG_SCHEME_HTTP = 1 << 13,
+  /* set if final response is expected */
+  NGHTTP2_HTTP_FLAG_EXPECT_FINAL_RESPONSE = 1 << 14
+} nghttp2_http_flag;
+
+struct nghttp2_stream {
+  /* Intrusive Map */
+  nghttp2_map_entry map_entry;
+  /* Entry for dep_prev->obq */
+  nghttp2_pq_entry pq_entry;
+  /* Priority Queue storing direct descendant (nghttp2_stream).  Only
+     streams which itself has some data to send, or has a descendant
+     which has some data to sent. */
+  nghttp2_pq obq;
+  /* Content-Length of request/response body.  -1 if unknown. */
+  int64_t content_length;
+  /* Received body so far */
+  int64_t recv_content_length;
+  /* Base last_cycle for direct descendent streams. */
+  uint32_t descendant_last_cycle;
+  /* Next scheduled time to sent item */
+  uint32_t cycle;
+  /* Next seq used for direct descendant streams */
+  uint64_t descendant_next_seq;
+  /* Secondary key for prioritization to break a tie for cycle.  This
+     value is monotonically increased for single parent stream. */
+  uint64_t seq;
+  /* pointers to form dependency tree.  If multiple streams depend on
+     a stream, only one stream (left most) has non-NULL dep_prev which
+     points to the stream it depends on. The remaining streams are
+     linked using sib_prev and sib_next.  The stream which has
+     non-NULL dep_prev always NULL sib_prev.  The right most stream
+     has NULL sib_next.  If this stream is a root of dependency tree,
+     dep_prev and sib_prev are NULL. */
+  nghttp2_stream *dep_prev, *dep_next;
+  nghttp2_stream *sib_prev, *sib_next;
+  /* When stream is kept after closure, it may be kept in doubly
+     linked list pointed by nghttp2_session closed_stream_head.
+     closed_next points to the next stream object if it is the element
+     of the list. */
+  nghttp2_stream *closed_prev, *closed_next;
+  /* The arbitrary data provided by user for this stream. */
+  void *stream_user_data;
+  /* Item to send */
+  nghttp2_outbound_item *item;
+  /* Last written length of frame payload */
+  size_t last_writelen;
+  /* stream ID */
+  int32_t stream_id;
+  /* Current remote window size. This value is computed against the
+     current initial window size of remote endpoint. */
+  int32_t remote_window_size;
+  /* Keep track of the number of bytes received without
+     WINDOW_UPDATE. This could be negative after submitting negative
+     value to WINDOW_UPDATE */
+  int32_t recv_window_size;
+  /* The number of bytes consumed by the application and now is
+     subject to WINDOW_UPDATE.  This is only used when auto
+     WINDOW_UPDATE is turned off. */
+  int32_t consumed_size;
+  /* The amount of recv_window_size cut using submitting negative
+     value to WINDOW_UPDATE */
+  int32_t recv_reduction;
+  /* window size for local flow control. It is initially set to
+     NGHTTP2_INITIAL_WINDOW_SIZE and could be increased/decreased by
+     submitting WINDOW_UPDATE. See nghttp2_submit_window_update(). */
+  int32_t local_window_size;
+  /* weight of this stream */
+  int32_t weight;
+  /* This is unpaid penalty (offset) when calculating cycle. */
+  uint32_t pending_penalty;
+  /* sum of weight of direct descendants */
+  int32_t sum_dep_weight;
+  nghttp2_stream_state state;
+  /* status code from remote server */
+  int16_t status_code;
+  /* Bitwise OR of zero or more nghttp2_http_flag values */
+  uint16_t http_flags;
+  /* This is bitwise-OR of 0 or more of nghttp2_stream_flag. */
+  uint8_t flags;
+  /* Bitwise OR of zero or more nghttp2_shut_flag values */
+  uint8_t shut_flags;
+  /* Nonzero if this stream has been queued to stream pointed by
+     dep_prev.  We maintain the invariant that if a stream is queued,
+     then its ancestors, except for root, are also queued.  This
+     invariant may break in fatal error condition. */
+  uint8_t queued;
+  /* This flag is used to reduce excessive queuing of WINDOW_UPDATE to
+     this stream.  The nonzero does not necessarily mean WINDOW_UPDATE
+     is not queued. */
+  uint8_t window_update_queued;
+};
+
+void nghttp2_stream_init(nghttp2_stream *stream, int32_t stream_id,
+                         uint8_t flags, nghttp2_stream_state initial_state,
+                         int32_t weight, int32_t remote_initial_window_size,
+                         int32_t local_initial_window_size,
+                         void *stream_user_data, nghttp2_mem *mem);
+
+void nghttp2_stream_free(nghttp2_stream *stream);
+
+/*
+ * Disallow either further receptions or transmissions, or both.
+ * |flag| is bitwise OR of one or more of nghttp2_shut_flag.
+ */
+void nghttp2_stream_shutdown(nghttp2_stream *stream, nghttp2_shut_flag flag);
+
+/*
+ * Defer |stream->item|.  We won't call this function in the situation
+ * where |stream->item| == NULL.  The |flags| is bitwise OR of zero or
+ * more of NGHTTP2_STREAM_FLAG_DEFERRED_USER and
+ * NGHTTP2_STREAM_FLAG_DEFERRED_FLOW_CONTROL.  The |flags| indicates
+ * the reason of this action.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory
+ */
+int nghttp2_stream_defer_item(nghttp2_stream *stream, uint8_t flags);
+
+/*
+ * Put back deferred data in this stream to active state.  The |flags|
+ * are one or more of bitwise OR of the following values:
+ * NGHTTP2_STREAM_FLAG_DEFERRED_USER and
+ * NGHTTP2_STREAM_FLAG_DEFERRED_FLOW_CONTROL and given masks are
+ * cleared if they are set.  So even if this function is called, if
+ * one of flag is still set, data does not become active.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory
+ */
+int nghttp2_stream_resume_deferred_item(nghttp2_stream *stream, uint8_t flags);
+
+/*
+ * Returns nonzero if item is deferred by whatever reason.
+ */
+int nghttp2_stream_check_deferred_item(nghttp2_stream *stream);
+
+/*
+ * Returns nonzero if item is deferred by flow control.
+ */
+int nghttp2_stream_check_deferred_by_flow_control(nghttp2_stream *stream);
+
+/*
+ * Updates the remote window size with the new value
+ * |new_initial_window_size|. The |old_initial_window_size| is used to
+ * calculate the current window size.
+ *
+ * This function returns 0 if it succeeds or -1. The failure is due to
+ * overflow.
+ */
+int nghttp2_stream_update_remote_initial_window_size(
+    nghttp2_stream *stream, int32_t new_initial_window_size,
+    int32_t old_initial_window_size);
+
+/*
+ * Updates the local window size with the new value
+ * |new_initial_window_size|. The |old_initial_window_size| is used to
+ * calculate the current window size.
+ *
+ * This function returns 0 if it succeeds or -1. The failure is due to
+ * overflow.
+ */
+int nghttp2_stream_update_local_initial_window_size(
+    nghttp2_stream *stream, int32_t new_initial_window_size,
+    int32_t old_initial_window_size);
+
+/*
+ * Call this function if promised stream |stream| is replied with
+ * HEADERS.  This function makes the state of the |stream| to
+ * NGHTTP2_STREAM_OPENED.
+ */
+void nghttp2_stream_promise_fulfilled(nghttp2_stream *stream);
+
+/*
+ * Returns nonzero if |target| is an ancestor of |stream|.
+ */
+int nghttp2_stream_dep_find_ancestor(nghttp2_stream *stream,
+                                     nghttp2_stream *target);
+
+/*
+ * Computes distributed weight of a stream of the |weight| under the
+ * |stream| if |stream| is removed from a dependency tree.
+ */
+int32_t nghttp2_stream_dep_distributed_weight(nghttp2_stream *stream,
+                                              int32_t weight);
+
+/*
+ * Makes the |stream| depend on the |dep_stream|.  This dependency is
+ * exclusive.  All existing direct descendants of |dep_stream| become
+ * the descendants of the |stream|.  This function assumes
+ * |stream->item| is NULL.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory
+ */
+int nghttp2_stream_dep_insert(nghttp2_stream *dep_stream,
+                              nghttp2_stream *stream);
+
+/*
+ * Makes the |stream| depend on the |dep_stream|.  This dependency is
+ * not exclusive.  This function assumes |stream->item| is NULL.
+ */
+void nghttp2_stream_dep_add(nghttp2_stream *dep_stream, nghttp2_stream *stream);
+
+/*
+ * Removes the |stream| from the current dependency tree.  This
+ * function assumes |stream->item| is NULL.
+ */
+int nghttp2_stream_dep_remove(nghttp2_stream *stream);
+
+/*
+ * Attaches |item| to |stream|.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory
+ */
+int nghttp2_stream_attach_item(nghttp2_stream *stream,
+                               nghttp2_outbound_item *item);
+
+/*
+ * Detaches |stream->item|.  This function does not free
+ * |stream->item|.  The caller must free it.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory
+ */
+int nghttp2_stream_detach_item(nghttp2_stream *stream);
+
+/*
+ * Makes the |stream| depend on the |dep_stream|.  This dependency is
+ * exclusive.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory
+ */
+int nghttp2_stream_dep_insert_subtree(nghttp2_stream *dep_stream,
+                                      nghttp2_stream *stream);
+
+/*
+ * Makes the |stream| depend on the |dep_stream|.  This dependency is
+ * not exclusive.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory
+ */
+int nghttp2_stream_dep_add_subtree(nghttp2_stream *dep_stream,
+                                   nghttp2_stream *stream);
+
+/*
+ * Removes subtree whose root stream is |stream|.  The
+ * effective_weight of streams in removed subtree is not updated.
+ *
+ * This function returns 0 if it succeeds, or one of the following
+ * negative error codes:
+ *
+ * NGHTTP2_ERR_NOMEM
+ *     Out of memory
+ */
+void nghttp2_stream_dep_remove_subtree(nghttp2_stream *stream);
+
+/*
+ * Returns nonzero if |stream| is in any dependency tree.
+ */
+int nghttp2_stream_in_dep_tree(nghttp2_stream *stream);
+
+/*
+ * Schedules transmission of |stream|'s item, assuming stream->item is
+ * attached, and stream->last_writelen was updated.
+ */
+void nghttp2_stream_reschedule(nghttp2_stream *stream);
+
+/*
+ * Changes |stream|'s weight to |weight|.  If |stream| is queued, it
+ * will be rescheduled based on new weight.
+ */
+void nghttp2_stream_change_weight(nghttp2_stream *stream, int32_t weight);
+
+/*
+ * Returns a stream which has highest priority, updating
+ * descendant_last_cycle of selected stream's ancestors.
+ */
+nghttp2_outbound_item *
+nghttp2_stream_next_outbound_item(nghttp2_stream *stream);
+
+#endif /* NGHTTP2_STREAM */
diff --git a/tools/sdk/include/nghttp/nghttp2_submit.h b/tools/sdk/include/nghttp/nghttp2_submit.h
new file mode 100644
index 00000000..545388cf
--- /dev/null
+++ b/tools/sdk/include/nghttp/nghttp2_submit.h
@@ -0,0 +1,34 @@
+/*
+ * nghttp2 - HTTP/2 C Library
+ *
+ * Copyright (c) 2012 Tatsuhiro Tsujikawa
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NGHTTP2_SUBMIT_H
+#define NGHTTP2_SUBMIT_H
+
+#ifdef HAVE_CONFIG_H
+#include 
+#endif /* HAVE_CONFIG_H */
+
+#include 
+
+#endif /* NGHTTP2_SUBMIT_H */
diff --git a/tools/sdk/include/nvs_flash/nvs.h b/tools/sdk/include/nvs_flash/nvs.h
new file mode 100644
index 00000000..912ea221
--- /dev/null
+++ b/tools/sdk/include/nvs_flash/nvs.h
@@ -0,0 +1,251 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef ESP_NVS_H
+#define ESP_NVS_H
+
+#include 
+#include 
+#include 
+#include "esp_err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Opaque pointer type representing non-volatile storage handle
+ */
+typedef uint32_t nvs_handle;
+
+#define ESP_ERR_NVS_BASE                0x1100
+#define ESP_ERR_NVS_NOT_INITIALIZED     (ESP_ERR_NVS_BASE + 0x01)
+#define ESP_ERR_NVS_NOT_FOUND           (ESP_ERR_NVS_BASE + 0x02)
+#define ESP_ERR_NVS_TYPE_MISMATCH       (ESP_ERR_NVS_BASE + 0x03)
+#define ESP_ERR_NVS_READ_ONLY           (ESP_ERR_NVS_BASE + 0x04)
+#define ESP_ERR_NVS_NOT_ENOUGH_SPACE    (ESP_ERR_NVS_BASE + 0x05)
+#define ESP_ERR_NVS_INVALID_NAME        (ESP_ERR_NVS_BASE + 0x06)
+#define ESP_ERR_NVS_INVALID_HANDLE      (ESP_ERR_NVS_BASE + 0x07)
+#define ESP_ERR_NVS_REMOVE_FAILED       (ESP_ERR_NVS_BASE + 0x08)
+#define ESP_ERR_NVS_KEY_TOO_LONG        (ESP_ERR_NVS_BASE + 0x09)
+#define ESP_ERR_NVS_PAGE_FULL           (ESP_ERR_NVS_BASE + 0x0a)
+#define ESP_ERR_NVS_INVALID_STATE       (ESP_ERR_NVS_BASE + 0x0b)
+#define ESP_ERR_NVS_INVALID_LENGTH      (ESP_ERR_NVS_BASE + 0x0c)
+
+typedef enum {
+	NVS_READONLY,
+	NVS_READWRITE
+} nvs_open_mode;
+
+/**
+ * @brief      Open non-volatile storage with a given namespace
+ *
+ * Multiple internal ESP-IDF and third party application modules can store
+ * their key-value pairs in the NVS module. In order to reduce possible
+ * conflicts on key names, each module can use its own namespace.
+ *
+ * @param[in]  name        Namespace name. Maximal length is determined by the
+ *                         underlying implementation, but is guaranteed to be
+ *                         at least 16 characters. Shouldn't be empty.
+ * @param[in]  open_mode   NVS_READWRITE or NVS_READONLY. If NVS_READONLY, will 
+ *						   open a handle for reading only. All write requests will 
+ *						   be rejected for this handle.
+ * @param[out] out_handle  If successful (return code is zero), handle will be
+ *                         returned in this argument.
+ *
+ * @return     - ESP_OK if storage handle was opened successfully
+ *             - ESP_ERR_NVS_NOT_INITIALIZED if the storage driver is not initialized
+ *             - ESP_ERR_NVS_NOT_FOUND id namespace doesn't exist yet and
+ *               mode is NVS_READONLY
+ *             - ESP_ERR_NVS_INVALID_NAME if namespace name doesn't satisfy constraints
+ *             - other error codes from the underlying storage driver
+ */
+esp_err_t nvs_open(const char* name, nvs_open_mode open_mode, nvs_handle *out_handle);
+
+/**
+ * @brief      nvs_set_X - set value for given key
+ *
+ * This family of functions set value for the key, given its name. Note that
+ * actual storage will not be updated until nvs_commit function is called.
+ *
+ * @param[in]  handle  Handle obtained from nvs_open function.
+ *                     Handles that were opened read only cannot be used.
+ * @param[in]  key     Key name. Maximal length is determined by the underlying
+ *                     implementation, but is guaranteed to be at least
+ *                     16 characters. Shouldn't be empty.
+ * @param[in]  value   The value to set.
+ * @param[in]  length  For nvs_set_blob: length of binary value to set, in bytes.
+ *
+ * @return     - ESP_OK if value was set successfully
+ *             - ESP_ERR_NVS_INVALID_HANDLE if handle has been closed or is NULL
+ *             - ESP_ERR_NVS_READ_ONLY if storage handle was opened as read only
+ *             - ESP_ERR_NVS_INVALID_NAME if key name doesn't satisfy constraints
+ *             - ESP_ERR_NVS_NOT_ENOUGH_SPACE if there is not enough space in the
+ *               underlying storage to save the value
+ *             - ESP_ERR_NVS_REMOVE_FAILED if the value wasn't updated because flash
+ *               write operation has failed. The value was written however, and
+ *               update will be finished after re-initialization of nvs, provided that
+ *               flash operation doesn't fail again.
+ */
+esp_err_t nvs_set_i8  (nvs_handle handle, const char* key, int8_t value);
+esp_err_t nvs_set_u8  (nvs_handle handle, const char* key, uint8_t value);
+esp_err_t nvs_set_i16 (nvs_handle handle, const char* key, int16_t value);
+esp_err_t nvs_set_u16 (nvs_handle handle, const char* key, uint16_t value);
+esp_err_t nvs_set_i32 (nvs_handle handle, const char* key, int32_t value);
+esp_err_t nvs_set_u32 (nvs_handle handle, const char* key, uint32_t value);
+esp_err_t nvs_set_i64 (nvs_handle handle, const char* key, int64_t value);
+esp_err_t nvs_set_u64 (nvs_handle handle, const char* key, uint64_t value);
+esp_err_t nvs_set_str (nvs_handle handle, const char* key, const char* value);
+esp_err_t nvs_set_blob(nvs_handle handle, const char* key, const void* value, size_t length);
+
+/**
+ * @brief      nvs_get_X - get value for given key
+ *
+ * These functions retrieve value for the key, given its name. If key does not
+ * exist, or the requested variable type doesn't match the type which was used
+ * when setting a value, an error is returned.
+ *
+ * In case of any error, out_value is not modified.
+ *
+ * All functions expect out_value to be a pointer to an already allocated variable
+ * of the given type.
+ * Additionally, nvs_get_str and nvs_get_blob support WinAPI-style length queries.
+ * To get the size necessary to store the value, call nvs_get_str or nvs_get_blob
+ * with zero out_value and non-zero pointer to length. Variable pointed to
+ * by length argument will be set to the required length. For nvs_get_str,
+ * this length includes the zero terminator. When calling nvs_get_str and
+ * nvs_get_blob with non-zero out_value, length has to be non-zero and has to
+ * point to the length available in out_value.
+ * It is suggested that nvs_get/set_str is used for zero-terminated C strings, and
+ * nvs_get/set_blob used for arbitrary data structures.
+ *
+ * Example of using nvs_get_i32:
+ * int32_t max_buffer_size = 4096; // default value
+ * esp_err_t err = nvs_get_i32(my_handle, "max_buffer_size", &max_buffer_size);
+ * assert(err == ESP_OK || err == ESP_ERR_NVS_NOT_FOUND);
+ * // if ESP_ERR_NVS_NOT_FOUND was returned, max_buffer_size will still
+ * // have its default value.
+ *
+ * Example (without error checking) of using nvs_get_str to get a string into dynamic array:
+ * size_t required_size;
+ * nvs_get_str(my_handle, "server_name", NULL, &required_size);
+ * char* server_name = malloc(required_size);
+ * nvs_get_str(my_handle, "server_name", server_name, &required_size);
+ *
+ * Example (without error checking) of using nvs_get_blob to get a binary data
+ * into a static array:
+ * uint8_t mac_addr[6];
+ * size_t size = sizeof(mac_addr);
+ * nvs_get_blob(my_handle, "dst_mac_addr", mac_addr, &size);
+ *
+ * @param[in]     handle     Handle obtained from nvs_open function.
+ * @param[in]     key        Key name. Maximal length is determined by the underlying
+ *                           implementation, but is guaranteed to be at least
+ *                           16 characters. Shouldn't be empty.
+ * @param         out_value  Pointer to the output value.
+ *                           May be NULL for nvs_get_str and nvs_get_blob, in this
+ *                           case required length will be returned in length argument.
+ * @param[inout]  length     For nvs_get_str and nvs_get_blob, non-zero pointer
+ *                           to the variable holding the length of out_value.
+ *                           In case out_value a zero, will be set to the length
+ *                           required to hold the value. In case out_value is not
+ *                           zero, will be set to the actual length of the value
+ *                           written. For nvs_get_str this includes zero terminator.
+ *
+ * @return     - ESP_OK if the value was retrieved successfully
+ *             - ESP_ERR_NVS_NOT_FOUND if the requested key doesn't exist
+ *             - ESP_ERR_NVS_INVALID_HANDLE if handle has been closed or is NULL
+ *             - ESP_ERR_NVS_INVALID_NAME if key name doesn't satisfy constraints
+ *             - ESP_ERR_NVS_INVALID_LENGTH if length is not sufficient to store data
+ */
+esp_err_t nvs_get_i8  (nvs_handle handle, const char* key, int8_t* out_value);
+esp_err_t nvs_get_u8  (nvs_handle handle, const char* key, uint8_t* out_value);
+esp_err_t nvs_get_i16 (nvs_handle handle, const char* key, int16_t* out_value);
+esp_err_t nvs_get_u16 (nvs_handle handle, const char* key, uint16_t* out_value);
+esp_err_t nvs_get_i32 (nvs_handle handle, const char* key, int32_t* out_value);
+esp_err_t nvs_get_u32 (nvs_handle handle, const char* key, uint32_t* out_value);
+esp_err_t nvs_get_i64 (nvs_handle handle, const char* key, int64_t* out_value);
+esp_err_t nvs_get_u64 (nvs_handle handle, const char* key, uint64_t* out_value);
+esp_err_t nvs_get_str (nvs_handle handle, const char* key, char* out_value, size_t* length);
+esp_err_t nvs_get_blob(nvs_handle handle, const char* key, void* out_value, size_t* length);
+
+/**
+ * @brief      Erase key-value pair with given key name.
+ *
+ * Note that actual storage may not be updated until nvs_commit function is called.
+ *
+ * @param[in]  handle  Storage handle obtained with nvs_open.
+ *                     Handles that were opened read only cannot be used.
+ *
+ * @param[in]  key     Key name. Maximal length is determined by the underlying
+ *                     implementation, but is guaranteed to be at least
+ *                     16 characters. Shouldn't be empty.
+ *
+ * @return      - ESP_OK if erase operation was successful
+ *              - ESP_ERR_NVS_INVALID_HANDLE if handle has been closed or is NULL
+ *              - ESP_ERR_NVS_READ_ONLY if handle was opened as read only
+ *              - ESP_ERR_NVS_NOT_FOUND if the requested key doesn't exist
+ *              - other error codes from the underlying storage driver
+ */
+esp_err_t nvs_erase_key(nvs_handle handle, const char* key);
+
+/**
+ * @brief      Erase all key-value pairs in a namespace
+ *
+ * Note that actual storage may not be updated until nvs_commit function is called.
+ *
+ * @param[in]  handle  Storage handle obtained with nvs_open.
+ *                     Handles that were opened read only cannot be used.
+ *
+ * @return      - ESP_OK if erase operation was successful
+ *              - ESP_ERR_NVS_INVALID_HANDLE if handle has been closed or is NULL
+ *              - ESP_ERR_NVS_READ_ONLY if handle was opened as read only
+ *              - other error codes from the underlying storage driver
+ */
+esp_err_t nvs_erase_all(nvs_handle handle);
+
+/**
+ * @brief      Write any pending changes to non-volatile storage
+ *
+ * After setting any values, nvs_commit() must be called to ensure changes are written
+ * to non-volatile storage. Individual implementations may write to storage at other times,
+ * but this is not guaranteed.
+ *
+ * @param[in]  handle  Storage handle obtained with nvs_open.
+ *                     Handles that were opened read only cannot be used.
+ *
+ * @return     - ESP_OK if the changes have been written successfully
+ *             - ESP_ERR_NVS_INVALID_HANDLE if handle has been closed or is NULL
+ *             - other error codes from the underlying storage driver
+ */
+esp_err_t nvs_commit(nvs_handle handle);
+
+/**
+ * @brief      Close the storage handle and free any allocated resources
+ *
+ * This function should be called for each handle opened with nvs_open once
+ * the handle is not in use any more. Closing the handle may not automatically
+ * write the changes to nonvolatile storage. This has to be done explicitly using
+ * nvs_commit function.
+ * Once this function is called on a handle, the handle should no longer be used.
+ *
+ * @param[in]  handle  Storage handle to close
+ */
+void nvs_close(nvs_handle handle);
+
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+
+#endif //ESP_NVS_H
diff --git a/tools/sdk/include/nvs_flash/nvs_flash.h b/tools/sdk/include/nvs_flash/nvs_flash.h
new file mode 100644
index 00000000..ce98f394
--- /dev/null
+++ b/tools/sdk/include/nvs_flash/nvs_flash.h
@@ -0,0 +1,46 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef nvs_flash_h
+#define nvs_flash_h
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Initialise NVS flash storage with default flash sector layout
+
+    Temporarily, this region is hardcoded as a 12KB (0x3000 byte)
+    region starting at 24KB (0x6000 byte) offset in flash.
+*/
+esp_err_t nvs_flash_init(void);
+
+/** Initialise NVS flash storage with custom flash sector layout
+
+    @param baseSector Flash sector (units of 4096 bytes) offset to start NVS.
+    @param sectorCount Length (in flash sectors) of NVS region.
+
+    @return ESP_OK if flash was successfully initialised.
+
+    @note Use this parameter if you're not using the options in menuconfig for
+          configuring flash layout & partition table.
+*/
+esp_err_t nvs_flash_init_custom(uint32_t baseSector, uint32_t sectorCount);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* nvs_flash_h */
diff --git a/tools/sdk/include/spi_flash/esp_spi_flash.h b/tools/sdk/include/spi_flash/esp_spi_flash.h
new file mode 100644
index 00000000..6d635880
--- /dev/null
+++ b/tools/sdk/include/spi_flash/esp_spi_flash.h
@@ -0,0 +1,116 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef ESP_SPI_FLASH_H
+#define ESP_SPI_FLASH_H
+
+#include 
+#include "esp_err.h"
+#include "sdkconfig.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ESP_ERR_FLASH_BASE       0x10010
+#define ESP_ERR_FLASH_OP_FAIL    (ESP_ERR_FLASH_BASE + 1)
+#define ESP_ERR_FLASH_OP_TIMEOUT (ESP_ERR_FLASH_BASE + 2)
+
+#define SPI_FLASH_SEC_SIZE  4096    /**< SPI Flash sector size */
+
+/**
+ * @brief  Initialize SPI flash access driver
+ *
+ *  This function must be called exactly once, before any other 
+ *  spi_flash_* functions are called.
+ *
+ */
+void spi_flash_init();
+
+/**
+ * @brief  Erase the Flash sector.
+ *
+ * @param  uint16 sec : Sector number, the count starts at sector 0, 4KB per sector.
+ *
+ * @return esp_err_t
+ */
+esp_err_t spi_flash_erase_sector(uint16_t sec);
+
+/**
+ * @brief  Write data to Flash.
+ *
+ * @param  uint32 des_addr  : destination address in Flash.
+ * @param  uint32 *src_addr : source address of the data.
+ * @param  uint32 size      : length of data
+ *
+ * @return esp_err_t
+ */
+esp_err_t spi_flash_write(uint32_t des_addr, const uint32_t *src_addr, uint32_t size);
+
+/**
+ * @brief  Read data from Flash.
+ *
+ * @param  uint32 src_addr  : source address of the data in Flash.
+ * @param  uint32 *des_addr : destination address.
+ * @param  uint32 size      : length of data
+ *
+ * @return esp_err_t
+ */
+esp_err_t spi_flash_read(uint32_t src_addr, uint32_t *des_addr, uint32_t size);
+
+
+#if CONFIG_SPI_FLASH_ENABLE_COUNTERS
+
+/**
+ * Structure holding statistics for one type of operation
+ */
+typedef struct {
+    uint32_t count;     // number of times operation was executed
+    uint32_t time;      // total time taken, in microseconds
+    uint32_t bytes;     // total number of bytes, for read and write operations
+} spi_flash_counter_t;
+
+typedef struct {
+    spi_flash_counter_t read;
+    spi_flash_counter_t write;
+    spi_flash_counter_t erase;
+} spi_flash_counters_t;
+
+/**
+ * @brief  Reset SPI flash operation counters
+ */
+void spi_flash_reset_counters();
+
+/**
+ * @brief  Print SPI flash operation counters
+ */
+void spi_flash_dump_counters();
+
+/**
+ * @brief  Return current SPI flash operation counters
+ *
+ * @return  pointer to the spi_flash_counters_t structure holding values
+ *          of the operation counters
+ */
+const spi_flash_counters_t* spi_flash_get_counters();
+
+#endif //CONFIG_SPI_FLASH_ENABLE_COUNTERS
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* ESP_SPI_FLASH_H */
+
diff --git a/tools/sdk/include/tcpip_adapter/tcpip_adapter.h b/tools/sdk/include/tcpip_adapter/tcpip_adapter.h
new file mode 100644
index 00000000..5b0fc4c6
--- /dev/null
+++ b/tools/sdk/include/tcpip_adapter/tcpip_adapter.h
@@ -0,0 +1,388 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _TCPIP_ADAPTER_H_
+#define _TCPIP_ADAPTER_H_
+
+/**
+ * @brief TCPIP adapter library
+ *
+ * The aim of this adapter is to provide an abstract layer upon TCPIP stack.
+ * With this layer, switch to other TCPIP stack is possible and easy in esp-idf.
+ *
+ * If users want to use other TCPIP stack, all those functions should be implemented
+ * by using the specific APIs of that stack. The macros in CONFIG_TCPIP_LWIP should be
+ * re-defined.
+ *
+ * tcpip_adapter_init should be called in the start of app_main for only once.
+ *
+ * Currently most adapter APIs are called in event_default_handlers.c.
+ *
+ * We recommend users only use set/get IP APIs, DHCP server/client APIs,
+ * get free station list APIs in application side. Other APIs are used in esp-idf internal,
+ * otherwise the state maybe wrong.
+ *
+ * TODO: ipv6 support will be added, use menuconfig to disable CONFIG_TCPIP_LWIP
+ */
+
+#include 
+#include "rom/queue.h"
+#include "esp_wifi_types.h"
+
+#define CONFIG_TCPIP_LWIP 1
+#define CONFIG_DHCP_STA_LIST 1
+
+#if CONFIG_TCPIP_LWIP
+#include "lwip/ip_addr.h"
+#include "apps/dhcpserver.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define IP2STR(ipaddr) ip4_addr1_16(ipaddr), \
+    ip4_addr2_16(ipaddr), \
+    ip4_addr3_16(ipaddr), \
+    ip4_addr4_16(ipaddr)
+
+#define IPSTR "%d.%d.%d.%d"
+
+typedef struct {
+    ip4_addr_t ip;
+    ip4_addr_t netmask;
+    ip4_addr_t gw;
+} tcpip_adapter_ip_info_t;
+
+typedef dhcps_lease_t tcpip_adapter_dhcps_lease_t;
+
+#if CONFIG_DHCP_STA_LIST 
+struct station_list {
+    STAILQ_ENTRY(station_list) next;
+    uint8_t mac[6];
+    ip4_addr_t ip;
+};
+#endif
+
+#endif
+
+#define ESP_ERR_TCPIP_ADAPTER_BASE      0x5000      // TODO: move base address to esp_err.h
+
+#define ESP_ERR_TCPIP_ADAPTER_INVALID_PARAMS        ESP_ERR_TCPIP_ADAPTER_BASE + 0x00
+#define ESP_ERR_TCPIP_ADAPTER_IF_NOT_READY          ESP_ERR_TCPIP_ADAPTER_BASE + 0x01
+#define ESP_ERR_TCPIP_ADAPTER_DHCPC_START_FAILED    ESP_ERR_TCPIP_ADAPTER_BASE + 0x02
+#define ESP_ERR_TCPIP_ADAPTER_DHCP_ALREADY_STARTED  ESP_ERR_TCPIP_ADAPTER_BASE + 0x03
+#define ESP_ERR_TCPIP_ADAPTER_DHCP_ALREADY_STOPPED  ESP_ERR_TCPIP_ADAPTER_BASE + 0x04
+#define ESP_ERR_TCPIP_ADAPTER_NO_MEM                ESP_ERR_TCPIP_ADAPTER_BASE + 0x05
+#define ESP_ERR_TCPIP_ADAPTER_DHCP_NOT_STOPPED      ESP_ERR_TCPIP_ADAPTER_BASE + 0x06
+
+/* TODO: add Ethernet interface */
+typedef enum {
+    TCPIP_ADAPTER_IF_STA = 0,     /**< ESP32 station interface */
+    TCPIP_ADAPTER_IF_AP,          /**< ESP32 soft-AP interface */
+    TCPIP_ADAPTER_IF_MAX
+} tcpip_adapter_if_t;
+
+/* status of DHCP client or DHCP server */
+typedef enum {
+    TCPIP_ADAPTER_DHCP_INIT = 0,    /**< DHCP client/server in initial state */
+    TCPIP_ADAPTER_DHCP_STARTED,     /**< DHCP client/server already been started */
+    TCPIP_ADAPTER_DHCP_STOPPED,     /**< DHCP client/server already been stopped */
+    TCPIP_ADAPTER_DHCP_STATUS_MAX
+} tcpip_adapter_dhcp_status_t;
+
+/* set the option mode for DHCP client or DHCP server */
+typedef enum{
+    TCPIP_ADAPTER_OP_START = 0,
+    TCPIP_ADAPTER_OP_SET,           /**< set option mode */
+    TCPIP_ADAPTER_OP_GET,           /**< get option mode */
+    TCPIP_ADAPTER_OP_MAX
+} tcpip_adapter_option_mode_t;
+
+typedef enum{
+    TCPIP_ADAPTER_ROUTER_SOLICITATION_ADDRESS   = 32,   /**< solicitation router address */
+    TCPIP_ADAPTER_REQUESTED_IP_ADDRESS          = 50,   /**< request IP address pool */
+    TCPIP_ADAPTER_IP_ADDRESS_LEASE_TIME         = 51,   /**< request IP address lease time */
+    TCPIP_ADAPTER_IP_REQUEST_RETRY_TIME         = 52,   /**< request IP address retry counter */
+} tcpip_adapter_option_id_t;
+
+/**
+ * @brief  Initialize tcpip adpater
+ *
+ * This will initialize TCPIP stack inside.
+ */
+void tcpip_adapter_init(void);
+
+/**
+ * @brief  Start an interface with specific MAC and IP
+ *
+ * softAP or station interface will be initialized, connect WiFi stack with TCPIP stack.
+ *
+ * For softAP interface, DHCP server will be started automatically.
+ *
+ * @param[in]  tcpip_if: the interface which we will start
+ * @param[in]  mac: set MAC address of this interface
+ * @param[in]  ip_info: set IP address of this interface
+ *
+ * @return ESP_OK
+ *         ESP_ERR_TCPIP_ADAPTER_INVALID_PARAMS
+ *         ESP_ERR_NO_MEM
+ */
+esp_err_t tcpip_adapter_start(tcpip_adapter_if_t tcpip_if, uint8_t *mac, tcpip_adapter_ip_info_t *ip_info);
+
+/**
+ * @brief  Stop an interface
+ *
+ * The interface will be cleanup in this API, if DHCP server/client are started, will be stopped.
+ *
+ * @param[in]  tcpip_if: the interface which will be started
+ *
+ * @return ESP_OK
+ *         ESP_ERR_TCPIP_ADAPTER_INVALID_PARAMS
+ *         ESP_ERR_TCPIP_ADAPTER_IF_NOT_READY
+ */
+esp_err_t tcpip_adapter_stop(tcpip_adapter_if_t tcpip_if);
+
+/**
+ * @brief  Bring up an interface
+ *
+ * Only station interface need to be brought up, since station interface will be shut down when disconnect.
+ *
+ * @param[in]  tcpip_if: the interface which will be up
+ *
+ * @return ESP_OK
+ *         ESP_ERR_TCPIP_ADAPTER_IF_NOT_READY
+ */
+esp_err_t tcpip_adapter_up(tcpip_adapter_if_t tcpip_if);
+
+/**
+ * @brief  Shut down an interface
+ *
+ * Only station interface need to be shut down, since station interface will be brought up when connect.
+ *
+ * @param[in]  tcpip_if: the interface which will be down
+ *
+ * @return ESP_OK
+ *         ESP_ERR_TCPIP_ADAPTER_IF_NOT_READY
+ */
+esp_err_t tcpip_adapter_down(tcpip_adapter_if_t tcpip_if);
+
+/**
+ * @brief  Get interface's IP information
+ *
+ * There has an IP information copy in adapter library, if interface is up, get IP information from
+ * interface, otherwise get from copy.
+ *
+ * @param[in]   tcpip_if: the interface which we want to get IP information
+ * @param[out]  ip_info: If successful, IP information will be returned in this argument.
+ *
+ * @return ESP_OK
+ *         ESP_ERR_TCPIP_ADAPTER_INVALID_PARAMS
+ */
+esp_err_t tcpip_adapter_get_ip_info(tcpip_adapter_if_t tcpip_if, tcpip_adapter_ip_info_t *ip_info);
+
+/**
+ * @brief  Set interface's IP information
+ *
+ * There has an IP information copy in adapter library, if interface is up, also set interface's IP.
+ * DHCP client/server should be stopped before set new IP information.
+ *
+ * This function is mainly used for setting static IP.
+ *
+ * @param[in]  tcpip_if: the interface which we want to set IP information
+ * @param[in]  ip_info: If successful, IP information will be returned in this argument.
+ *
+ * @return ESP_OK
+ *         ESP_ERR_TCPIP_ADAPTER_INVALID_PARAMS
+ */
+esp_err_t tcpip_adapter_set_ip_info(tcpip_adapter_if_t tcpip_if, tcpip_adapter_ip_info_t *ip_info);
+
+#if 0
+esp_err_t tcpip_adapter_get_mac(tcpip_adapter_if_t tcpip_if, uint8_t *mac);
+
+esp_err_t tcpip_adapter_set_mac(tcpip_adapter_if_t tcpip_if, uint8_t *mac);
+#endif
+
+/**
+ * @brief  Get DHCP server's status
+ *
+ * @param[in]   tcpip_if: the interface which we will get status of DHCP server
+ * @param[out]  status: If successful, the status of DHCP server will be return in this argument.
+ *
+ * @return ESP_OK
+ */
+esp_err_t tcpip_adapter_dhcps_get_status(tcpip_adapter_if_t tcpip_if, tcpip_adapter_dhcp_status_t *status);
+
+/**
+ * @brief  Set or Get DHCP server's option
+ *
+ * @param[in]  opt_op: option operate type, 1 for SET, 2 for GET.
+ * @param[in]  opt_id: option index, 32 for ROUTER, 50 for IP POLL, 51 for LEASE TIME, 52 for REQUEST TIME
+ * @param[in]  opt_val: option parameter
+ * @param[in]  opt_len: option length
+ *
+ * @return ESP_OK
+ *         ESP_ERR_TCPIP_ADAPTER_INVALID_PARAMS
+ *         ESP_ERR_TCPIP_ADAPTER_DHCP_ALREADY_STOPPED
+ *         ESP_ERR_TCPIP_ADAPTER_DHCP_ALREADY_STARTED
+ */
+esp_err_t tcpip_adapter_dhcps_option(tcpip_adapter_option_mode_t opt_op, tcpip_adapter_option_id_t opt_id, void *opt_val, uint32_t opt_len);
+
+/**
+ * @brief  Start DHCP server
+ *
+ * @note   Currently DHCP server is bind to softAP interface.
+ *
+ * @param[in]  tcpip_if: the interface which we will start DHCP server
+ *
+ * @return ESP_OK
+ *         ESP_ERR_TCPIP_ADAPTER_INVALID_PARAMS
+ *         ESP_ERR_TCPIP_ADAPTER_DHCP_ALREADY_STARTED
+ */
+esp_err_t tcpip_adapter_dhcps_start(tcpip_adapter_if_t tcpip_if);
+
+/**
+ * @brief  Stop DHCP server
+ *
+ * @note   Currently DHCP server is bind to softAP interface.
+ *
+ * @param[in]  tcpip_if: the interface which we will stop DHCP server
+ *
+ * @return ESP_OK
+ *         ESP_ERR_TCPIP_ADAPTER_INVALID_PARAMS
+ *         ESP_ERR_TCPIP_ADAPTER_DHCP_ALREADY_STOPED
+ *         ESP_ERR_TCPIP_ADAPTER_IF_NOT_READY
+ */
+esp_err_t tcpip_adapter_dhcps_stop(tcpip_adapter_if_t tcpip_if);
+
+/**
+ * @brief  Get DHCP client status
+ *
+ * @param[in]  tcpip_if: the interface which we will get status of DHCP client
+ * @param[out]  status: If successful, the status of DHCP client will be return in this argument.
+ *
+ * @return ESP_OK
+ */
+esp_err_t tcpip_adapter_dhcpc_get_status(tcpip_adapter_if_t tcpip_if, tcpip_adapter_dhcp_status_t *status);
+
+/**
+ * @brief  Set or Get DHCP client's option
+ *
+ * @note   This function is not implement now.
+ *
+ * @param[in]  opt_op: option operate type, 1 for SET, 2 for GET.
+ * @param[in]  opt_id: option index, 32 for ROUTER, 50 for IP POLL, 51 for LEASE TIME, 52 for REQUEST TIME
+ * @param[in]  opt_val: option parameter
+ * @param[in]  opt_len: option length
+ *
+ * @return ESP_OK
+ */
+esp_err_t tcpip_adapter_dhcpc_option(tcpip_adapter_option_mode_t opt_op, tcpip_adapter_option_id_t opt_id, void *opt_val, uint32_t opt_len);
+
+/**
+ * @brief  Start DHCP client
+ *
+ * @note   Currently DHCP client is bind to station interface.
+ *
+ * @param[in]  tcpip_if: the interface which we will start DHCP client
+ *
+ * @return ESP_OK
+ *         ESP_ERR_TCPIP_ADAPTER_INVALID_PARAMS
+ *         ESP_ERR_TCPIP_ADAPTER_DHCP_ALREADY_STARTED
+ *         ESP_ERR_TCPIP_ADAPTER_DHCPC_START_FAILED
+ */
+esp_err_t tcpip_adapter_dhcpc_start(tcpip_adapter_if_t tcpip_if);
+
+/**
+ * @brief  Stop DHCP client
+ *
+ * @note   Currently DHCP client is bind to station interface.
+ *
+ * @param[in]  tcpip_if: the interface which we will stop DHCP client
+ *
+ * @return ESP_OK
+ *         ESP_ERR_TCPIP_ADAPTER_INVALID_PARAMS
+ *         ESP_ERR_TCPIP_ADAPTER_DHCP_ALREADY_STOPED
+ *         ESP_ERR_TCPIP_ADAPTER_IF_NOT_READY
+ */
+esp_err_t tcpip_adapter_dhcpc_stop(tcpip_adapter_if_t tcpip_if);
+
+/**
+ * @brief  Get data from station interface
+ *
+ * This function should be installed by esp_wifi_reg_rxcb, so WiFi packets will be forward to TCPIP stack.
+ *
+ * @param[in]  void *buffer: the received data point
+ * @param[in]  uint16_t len: the received data length
+ * @param[in]  void *eb: parameter
+ *
+ * @return ESP_OK
+ */
+esp_err_t tcpip_adapter_sta_input(void *buffer, uint16_t len, void *eb);
+
+/**
+ * @brief  Get data from softAP interface
+ *
+ * This function should be installed by esp_wifi_reg_rxcb, so WiFi packets will be forward to TCPIP stack.
+ *
+ * @param[in]  void *buffer: the received data point
+ * @param[in]  uint16_t len: the received data length
+ * @param[in]  void *eb: parameter
+ *
+ * @return ESP_OK
+ */
+esp_err_t tcpip_adapter_ap_input(void *buffer, uint16_t len, void *eb);
+
+/**
+ * @brief  Get WiFi interface index
+ *
+ * Get WiFi interface from TCPIP interface struct pointer.
+ *
+ * @param[in]  void *dev: adapter interface
+ *
+ * @return WIFI_IF_STA
+ *         WIFI_IF_AP
+ *         WIFI_IF_MAX
+ */
+wifi_interface_t tcpip_adapter_get_wifi_if(void *dev);
+
+/**
+ * @brief  Get the station information list
+ *
+ * @note   This function should be called in AP mode and dhcp server started, and the list should
+ *         be by using tcpip_adapter_free_sta_list.
+ *
+ * @param[in]   sta_info: station information
+ * @param[out]  sta_list: station information list
+ *
+ * @return ESP_OK
+ *         ESP_ERR_TCPIP_ADAPTER_NO_MEM
+ *         ESP_ERR_TCPIP_ADAPTER_INVALID_PARAMS
+ */
+esp_err_t tcpip_adapter_get_sta_list(struct station_info *sta_info, struct station_list **sta_list);
+
+/**
+ * @brief Free the station information list's memory
+ *
+ * @param  sta_list: station information list
+ *
+ * @return ESP_OK
+ */
+esp_err_t tcpip_adapter_free_sta_list(struct station_list *sta_list);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*  _TCPIP_ADAPTER_H_ */
+
diff --git a/tools/sdk/ld/esp32.common.ld b/tools/sdk/ld/esp32.common.ld
new file mode 100644
index 00000000..a3c63678
--- /dev/null
+++ b/tools/sdk/ld/esp32.common.ld
@@ -0,0 +1,168 @@
+/*  Default entry point:  */
+ENTRY(call_start_cpu0);
+
+SECTIONS
+{
+  /* Send .iram0 code to iram */
+  .iram0.vectors : 
+  {
+    /* Vectors go to IRAM */
+    _init_start = ABSOLUTE(.);
+    /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */
+    . = 0x0;
+    KEEP(*(.WindowVectors.text));
+    . = 0x180;
+    KEEP(*(.Level2InterruptVector.text));
+    . = 0x1c0;
+    KEEP(*(.Level3InterruptVector.text));
+    . = 0x200;
+    KEEP(*(.Level4InterruptVector.text));
+    . = 0x240;
+    KEEP(*(.Level5InterruptVector.text));
+    . = 0x280;
+    KEEP(*(.DebugExceptionVector.text));
+    . = 0x2c0;
+    KEEP(*(.NMIExceptionVector.text));
+    . = 0x300;
+    KEEP(*(.KernelExceptionVector.text));
+    . = 0x340;
+    KEEP(*(.UserExceptionVector.text));
+    . = 0x3C0;
+    KEEP(*(.DoubleExceptionVector.text));
+    . = 0x400;
+    *(.*Vector.literal)
+
+    *(.UserEnter.literal);
+    *(.UserEnter.text);
+    . = ALIGN (16);
+    *(.entry.text)
+    *(.init.literal)
+    *(.init)
+    _init_end = ABSOLUTE(.);
+  } > iram0_0_seg
+
+  .iram0.text :
+  {
+    /* Code marked as runnning out of IRAM */
+    _iram_text_start = ABSOLUTE(.);
+    *(.iram1 .iram1.*)
+    *libfreertos.a:(.literal .text .literal.* .text.*)
+    *libphy.a:(.literal .text .literal.* .text.*)
+    *librtc.a:(.literal .text .literal.* .text.*)
+    *libpp.a:(.literal .text .literal.* .text.*)
+    *libhal.a:(.literal .text .literal.* .text.*)
+    _iram_text_end = ABSOLUTE(.);
+  } > iram0_0_seg
+
+  /* Shared RAM */
+  .dram0.bss (NOLOAD) :
+  {
+    . = ALIGN (8);
+    _bss_start = ABSOLUTE(.);
+    *(.dynsbss)
+    *(.sbss)
+    *(.sbss.*)
+    *(.gnu.linkonce.sb.*)
+    *(.scommon)
+    *(.sbss2)
+    *(.sbss2.*)
+    *(.gnu.linkonce.sb2.*)
+    *(.dynbss)
+    KEEP(*(.bss))
+    *(.bss.*)
+    *(.share.mem)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN (8);
+    _bss_end = ABSOLUTE(.);
+  } >dram0_0_seg
+
+  .dram0.data :
+  {
+    _data_start = ABSOLUTE(.);
+    KEEP(*(.data))
+    KEEP(*(.data.*))
+    KEEP(*(.gnu.linkonce.d.*))
+    KEEP(*(.data1))
+    KEEP(*(.sdata))
+    KEEP(*(.sdata.*))
+    KEEP(*(.gnu.linkonce.s.*))
+    KEEP(*(.sdata2))
+    KEEP(*(.sdata2.*))
+    KEEP(*(.gnu.linkonce.s2.*))
+    KEEP(*(.jcr))
+    *(.dram1 .dram1.*)
+    _data_end = ABSOLUTE(.);
+    . = ALIGN(4);
+    _heap_start = ABSOLUTE(.);
+  } >dram0_0_seg
+
+  .flash.rodata :
+  {
+    _rodata_start = ABSOLUTE(.);
+    *(.rodata)
+    *(.rodata.*)
+    *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
+    *(.gnu.linkonce.r.*)
+    *(.rodata1)
+    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
+    *(.xt_except_table)
+    *(.gcc_except_table)
+    *(.gnu.linkonce.e.*)
+    *(.gnu.version_r)
+    *(.eh_frame)
+    . = (. + 3) & ~ 3;
+    /*  C++ constructor and destructor tables, properly ordered:  */
+    __init_array_start = ABSOLUTE(.);
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    __init_array_end = ABSOLUTE(.);
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    /*  C++ exception handlers table:  */
+    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
+    *(.xt_except_desc)
+    *(.gnu.linkonce.h.*)
+    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
+    *(.xt_except_desc_end)
+    *(.dynamic)
+    *(.gnu.version_d)
+    _rodata_end = ABSOLUTE(.);
+    /* Literals are also RO data. */
+    _lit4_start = ABSOLUTE(.);
+    *(*.lit4)
+    *(.lit4.*)
+    *(.gnu.linkonce.lit4.*)
+    _lit4_end = ABSOLUTE(.);
+    . = ALIGN(4);
+  } >drom0_0_seg
+
+  .flash.text :
+  {
+    _stext = .;
+    _text_start = ABSOLUTE(.);
+    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+    *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
+    *(.fini.literal)
+    *(.fini)
+    *(.gnu.version)
+    _text_end = ABSOLUTE(.);
+    _etext = .;
+  } >iram0_2_seg
+
+  .rtc.text :
+  {
+    . = ALIGN(4);
+    *(.rtc.literal .rtc.text)
+  } >rtc_iram_seg
+
+  .rtc.data :
+  {
+    *(.rtc.data)
+    *(.rtc.rodata)
+  } > rtc_slow_seg
+}
diff --git a/tools/sdk/ld/esp32.ld b/tools/sdk/ld/esp32.ld
new file mode 100644
index 00000000..d6b0ac42
--- /dev/null
+++ b/tools/sdk/ld/esp32.ld
@@ -0,0 +1,55 @@
+/* ESP32 Linker Script Memory Layout
+
+   This file describes the memory layout (memory blocks) as virtual
+   memory addresses.
+
+   esp32.common.ld contains output sections to link compiler output
+   into these memory blocks.
+
+   ***
+
+   This linker script is passed through the C preprocessor to include
+   configuration options.
+
+   Please use preprocessor features sparingly! Restrict
+   to simple macros with numeric values, and/or #if/#endif blocks.
+*/
+#include "sdkconfig.h"
+
+MEMORY
+{
+  /* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
+  of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
+  are connected to the data port of the CPU and eg allow bytewise access. */
+
+  /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
+  iram0_0_seg (RX) :                 org = 0x40080000, len = 0x20000
+
+  /* Even though the segment name is iram, it is actually mapped to flash */
+  iram0_2_seg (RX) :                 org = 0x400D0018, len = 0x330000
+
+  /* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
+
+     Enabling Bluetooth & Trace Memory features in menuconfig will decrease
+     the amount of RAM available.
+  */
+  dram0_0_seg (RW) :                 org = 0x3FFB0000 + CONFIG_BT_RESERVE_DRAM,
+                                     len = 0x50000 - CONFIG_TRACEMEM_RESERVE_DRAM - CONFIG_BT_RESERVE_DRAM
+
+  /* Flash mapped constant data */
+  drom0_0_seg (R) :                  org = 0x3F400010, len = 0x800000
+
+  /* RTC fast memory (executable). Persists over deep sleep.
+   */
+  rtc_iram_seg(RWX) :                org = 0x400C0000, len = 0x2000
+
+  /* RTC slow memory (data accessible). Persists over deep sleep.
+
+     Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.
+  */
+  rtc_slow_seg(RW)  :                org = 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM,
+                                     len = 0x1000 - CONFIG_ULP_COPROC_RESERVE_MEM
+}
+
+/* Heap ends at top of dram0_0_seg */
+_heap_end = 0x40000000 - CONFIG_TRACEMEM_RESERVE_DRAM;
diff --git a/tools/sdk/ld/esp32.peripherals.ld b/tools/sdk/ld/esp32.peripherals.ld
new file mode 100644
index 00000000..aaadedce
--- /dev/null
+++ b/tools/sdk/ld/esp32.peripherals.ld
@@ -0,0 +1,20 @@
+PROVIDE ( UART0 = 0x3ff40000 );
+PROVIDE ( SPI1 = 0x3ff42000 );
+PROVIDE ( SPI0 = 0x3ff43000 );
+PROVIDE ( GPIO = 0x3ff44000 );
+PROVIDE ( SIGMADELTA = 0x3ff44f00 );
+PROVIDE ( UHCI1 = 0x3ff4C000 );
+PROVIDE ( I2S0 = 0x3ff4F000 );
+PROVIDE ( UART1 = 0x3ff50000 );
+PROVIDE ( I2C0 = 0x3ff53000 );
+PROVIDE ( UHCI0 = 0x3ff54000 );
+PROVIDE ( RMT = 0x3ff56000 );
+PROVIDE ( PCNT = 0x3ff57000 );
+PROVIDE ( LEDC = 0x3ff59000 );
+PROVIDE ( TIMERG0 = 0x3ff5F000 );
+PROVIDE ( TIMERG1 = 0x3ff60000 );
+PROVIDE ( SPI2 = 0x3ff64000 );
+PROVIDE ( SPI3 = 0x3ff65000 );
+PROVIDE ( I2C1 = 0x3ff67000 );
+PROVIDE ( I2S1 = 0x3ff6D000 );
+PROVIDE ( UART2 = 0x3ff6E000 );
diff --git a/tools/sdk/ld/esp32.rom.ld b/tools/sdk/ld/esp32.rom.ld
new file mode 100644
index 00000000..cc14d325
--- /dev/null
+++ b/tools/sdk/ld/esp32.rom.ld
@@ -0,0 +1,1841 @@
+/*
+ESP32 ROM address table
+Generated for ROM with MD5sum:
+ab8282ae908fe9e7a63fb2a4ac2df013  ../../rom_image/prorom.elf
+*/
+PROVIDE ( abort = 0x4000bba4 );
+PROVIDE ( abs = 0x40056340 );
+PROVIDE ( __absvdi2 = 0x4006387c );
+PROVIDE ( __absvsi2 = 0x40063868 );
+PROVIDE ( Add2SelfBigHex256 = 0x40015b7c );
+PROVIDE ( AddBigHex256 = 0x40015b28 );
+PROVIDE ( AddBigHexModP256 = 0x40015c98 );
+PROVIDE ( __adddf3 = 0x40002590 );
+PROVIDE ( AddP256 = 0x40015c74 );
+PROVIDE ( AddPdiv2_256 = 0x40015ce0 );
+PROVIDE ( __addsf3 = 0x400020e8 );
+PROVIDE ( __addvdi3 = 0x40002cbc );
+PROVIDE ( __addvsi3 = 0x40002c98 );
+PROVIDE ( aes_128_cbc_decrypt = 0x4005cc7c );
+PROVIDE ( aes_128_cbc_encrypt = 0x4005cc18 );
+PROVIDE ( aes_unwrap = 0x4005ccf0 );
+PROVIDE ( app_gpio_arg = 0x3ffe003c );
+PROVIDE ( app_gpio_handler = 0x3ffe0040 );
+PROVIDE ( __ascii_wctomb = 0x40058ef0 );
+PROVIDE ( asctime = 0x40059588 );
+PROVIDE ( asctime_r = 0x40000ec8 );
+PROVIDE ( __ashldi3 = 0x4000c818 );
+PROVIDE ( __ashrdi3 = 0x4000c830 );
+PROVIDE ( asiprintf = 0x40056d9c );
+PROVIDE ( _asiprintf_r = 0x40056d4c );
+PROVIDE ( asniprintf = 0x40056cd8 );
+PROVIDE ( _asniprintf_r = 0x40056c64 );
+PROVIDE ( asnprintf = 0x40056cd8 );
+PROVIDE ( _asnprintf_r = 0x40056c64 );
+PROVIDE ( asprintf = 0x40056d9c );
+PROVIDE ( _asprintf_r = 0x40056d4c );
+PROVIDE ( atoi = 0x400566c4 );
+PROVIDE ( _atoi_r = 0x400566d4 );
+PROVIDE ( atol = 0x400566ec );
+PROVIDE ( _atol_r = 0x400566fc );
+PROVIDE ( base64_decode = 0x4005ced8 );
+PROVIDE ( base64_encode = 0x4005cdbc );
+PROVIDE ( BasePoint_x_256 = 0x3ff97488 );
+PROVIDE ( BasePoint_y_256 = 0x3ff97468 );
+PROVIDE ( bigHexInversion256 = 0x400168f0 );
+PROVIDE ( bigHexP256 = 0x3ff973bc );
+PROVIDE ( __bswapdi2 = 0x400649c4 );
+PROVIDE ( __bswapsi2 = 0x4006499c );
+PROVIDE ( btdm_r_ble_bt_handler_tab_p_get = 0x40019b0c );
+PROVIDE ( btdm_r_btdm_option_data_p_get = 0x40010004 );
+PROVIDE ( btdm_r_btdm_rom_version_get = 0x40010078 );
+PROVIDE ( btdm_r_data_init = 0x4001002c );
+PROVIDE ( btdm_r_import_rf_phy_func_p_get = 0x40054298 );
+PROVIDE ( btdm_r_ip_func_p_get = 0x40019af0 );
+PROVIDE ( btdm_r_ip_func_p_set = 0x40019afc );
+PROVIDE ( btdm_r_modules_func_p_get = 0x4005427c );
+PROVIDE ( btdm_r_modules_func_p_set = 0x40054270 );
+PROVIDE ( btdm_r_plf_func_p_set = 0x40054288 );
+PROVIDE ( bt_util_buf_env = 0x3ffb8bd4 );
+PROVIDE ( bzero = 0x4000c1f4 );
+PROVIDE ( cache_flash_mmu_set = 0x400095e0 );
+PROVIDE ( Cache_Flush = 0x40009a14 );
+PROVIDE ( Cache_Read_Disable = 0x40009ab8 );
+PROVIDE ( Cache_Read_Enable = 0x40009a84 );
+PROVIDE ( Cache_Read_Init = 0x40009950 );
+PROVIDE ( cache_sram_mmu_set = 0x400097f4 );
+/* This is static function, but can be used, not generated by script*/
+PROVIDE ( calc_rtc_memory_crc = 0x40008170 );
+PROVIDE ( calloc = 0x4000bee4 );
+PROVIDE ( _calloc_r = 0x4000bbf8 );
+PROVIDE ( check_pos = 0x400068b8 );
+PROVIDE ( _cleanup = 0x40001df8 );
+PROVIDE ( _cleanup_r = 0x40001d48 );
+PROVIDE ( __clear_cache = 0x40063860 );
+PROVIDE ( close = 0x40001778 );
+PROVIDE ( _close_r = 0x4000bd3c );
+PROVIDE ( __clrsbdi2 = 0x40064a38 );
+PROVIDE ( __clrsbsi2 = 0x40064a20 );
+PROVIDE ( __clzdi2 = 0x4000ca50 );
+PROVIDE ( __clzsi2 = 0x4000c7e8 );
+PROVIDE ( __cmpdi2 = 0x40063820 );
+PROVIDE ( co_default_bdaddr = 0x3ffae704 );
+PROVIDE ( co_null_bdaddr = 0x3ffb80e0 );
+PROVIDE ( co_sca2ppm = 0x3ff971e8 );
+PROVIDE ( crc16_be = 0x4005d09c );
+PROVIDE ( crc16_le = 0x4005d05c );
+PROVIDE ( crc32_be = 0x4005d024 );
+PROVIDE ( crc32_le = 0x4005cfec );
+PROVIDE ( crc8_be = 0x4005d114 );
+PROVIDE ( crc8_le = 0x4005d0e0 );
+PROVIDE ( creat = 0x40000e8c );
+PROVIDE ( ctime = 0x400595b0 );
+PROVIDE ( ctime_r = 0x400595c4 );
+PROVIDE ( _ctype_ = 0x3ff96354 );
+PROVIDE ( __ctype_ptr__ = 0x3ff96350 );
+PROVIDE ( __ctzdi2 = 0x4000ca64 );
+PROVIDE ( __ctzsi2 = 0x4000c7f0 );
+PROVIDE ( _data_end = 0x4000d5c8 );
+PROVIDE ( _data_end_btdm_rom = 0x4000d4f8 );
+PROVIDE ( _data_start = 0x4000d4f8 );
+PROVIDE ( _data_start_btdm_rom = 0x4000d4f4 );
+PROVIDE ( _data_start_btdm = 0x3ffae6e0);
+PROVIDE ( _data_end_btdm = 0x3ffaff10);
+PROVIDE ( _bss_start_btdm = 0x3ffb8000);
+PROVIDE ( _bss_end_btdm = 0x3ffbff70);
+PROVIDE ( _daylight = 0x3ffae0a4 );
+PROVIDE ( dbg_default_handler = 0x3ff97218 );
+PROVIDE ( dbg_state = 0x3ffb8d5d );
+PROVIDE ( DebugE256PublicKey_x = 0x3ff97428 );
+PROVIDE ( DebugE256PublicKey_y = 0x3ff97408 );
+PROVIDE ( DebugE256SecretKey = 0x3ff973e8 );
+PROVIDE ( _DebugExceptionVector = 0x40000280 );
+PROVIDE ( debug_timer = 0x3ffe042c );
+PROVIDE ( debug_timerfn = 0x3ffe0430 );
+PROVIDE ( dh_group14_generator = 0x3ff9ac60 );
+PROVIDE ( dh_group14_prime = 0x3ff9ab60 );
+PROVIDE ( dh_group15_generator = 0x3ff9ab5f );
+PROVIDE ( dh_group15_prime = 0x3ff9a9df );
+PROVIDE ( dh_group16_generator = 0x3ff9a9de );
+PROVIDE ( dh_group16_prime = 0x3ff9a7de );
+PROVIDE ( dh_group17_generator = 0x3ff9a7dd );
+PROVIDE ( dh_group17_prime = 0x3ff9a4dd );
+PROVIDE ( dh_group18_generator = 0x3ff9a4dc );
+PROVIDE ( dh_group18_prime = 0x3ff9a0dc );
+PROVIDE ( dh_group1_generator = 0x3ff9ae03 );
+PROVIDE ( dh_group1_prime = 0x3ff9ada3 );
+PROVIDE ( dh_group2_generator = 0x3ff9ada2 );
+PROVIDE ( dh_group2_prime = 0x3ff9ad22 );
+PROVIDE ( dh_group5_generator = 0x3ff9ad21 );
+PROVIDE ( dh_group5_prime = 0x3ff9ac61 );
+PROVIDE ( div = 0x40056348 );
+PROVIDE ( __divdc3 = 0x40064460 );
+PROVIDE ( __divdf3 = 0x40002954 );
+PROVIDE ( __divdi3 = 0x4000ca84 );
+PROVIDE ( __divsc3 = 0x40064200 );
+PROVIDE ( __divsf3 = 0x4000234c );
+PROVIDE ( __divsi3 = 0x4000c7b8 );
+PROVIDE ( _DoubleExceptionVector = 0x400003c0 );
+PROVIDE ( dummy_len_plus = 0x3ffae290 );
+PROVIDE ( __dummy_lock = 0x4000c728 );
+PROVIDE ( __dummy_lock_try = 0x4000c730 );
+PROVIDE ( ecc_env = 0x3ffb8d60 );
+PROVIDE ( ecc_Jacobian_InfinityPoint256 = 0x3ff972e8 );
+PROVIDE ( em_buf_env = 0x3ffb8d74 );
+PROVIDE ( environ = 0x3ffae0b4 );
+PROVIDE ( __env_lock = 0x40001fd4 );
+PROVIDE ( __env_unlock = 0x40001fe0 );
+PROVIDE ( __eqdf2 = 0x400636a8 );
+PROVIDE ( __eqsf2 = 0x40063374 );
+PROVIDE ( esp_crc8 = 0x4005d144 );
+PROVIDE ( _etext = 0x4000d66c );
+PROVIDE ( ets_aes_crypt = 0x4005c9b8 );
+PROVIDE ( ets_aes_disable = 0x4005c8f8 );
+PROVIDE ( ets_aes_enable = 0x4005c8cc );
+PROVIDE ( ets_aes_set_endian = 0x4005c928 );
+PROVIDE ( ets_aes_setkey_dec = 0x4005c994 );
+PROVIDE ( ets_aes_setkey_enc = 0x4005c97c );
+PROVIDE ( ets_bigint_disable = 0x4005c4e0 );
+PROVIDE ( ets_bigint_enable = 0x4005c498 );
+PROVIDE ( ets_bigint_mod_mult_getz = 0x4005c818 );
+PROVIDE ( ets_bigint_mod_mult_prepare = 0x4005c7b4 );
+PROVIDE ( ets_bigint_mod_power_getz = 0x4005c614 );
+PROVIDE ( ets_bigint_mod_power_prepare = 0x4005c54c );
+PROVIDE ( ets_bigint_montgomery_mult_getz = 0x4005c7a4 );
+PROVIDE ( ets_bigint_montgomery_mult_prepare = 0x4005c6fc );
+PROVIDE ( ets_bigint_mult_getz = 0x4005c6e8 );
+PROVIDE ( ets_bigint_mult_prepare = 0x4005c630 );
+PROVIDE ( ets_bigint_wait_finish = 0x4005c520 );
+PROVIDE ( ets_delay_us = 0x40008534 );
+PROVIDE ( ets_efuse_get_8M_clock = 0x40008710 );
+PROVIDE ( ets_efuse_get_spiconfig = 0x40008658 );
+PROVIDE ( ets_efuse_program_op = 0x40008628 );
+PROVIDE ( ets_efuse_read_op = 0x40008600 );
+PROVIDE ( ets_get_cpu_frequency = 0x4000855c );
+PROVIDE ( ets_get_detected_xtal_freq = 0x40008588 );
+PROVIDE ( ets_get_xtal_scale = 0x4000856c );
+PROVIDE ( ets_install_putc1 = 0x40007d18 );
+PROVIDE ( ets_install_putc2 = 0x40007d38 );
+PROVIDE ( ets_install_uart_printf = 0x40007d28 );
+PROVIDE ( ets_intr_count = 0x3ffe03fc );
+PROVIDE ( ets_intr_lock = 0x400067b0 );
+PROVIDE ( ets_intr_unlock = 0x400067c4 );
+PROVIDE ( ets_isr_attach = 0x400067ec );
+PROVIDE ( ets_isr_mask = 0x400067fc );
+PROVIDE ( ets_isr_unmask = 0x40006808 );
+PROVIDE ( ets_post = 0x4000673c );
+PROVIDE ( ets_printf = 0x40007d54 );
+PROVIDE ( ets_readySet_ = 0x3ffe01f0 );
+PROVIDE ( ets_run = 0x400066bc );
+PROVIDE ( ets_secure_boot_check = 0x4005cb40 );
+PROVIDE ( ets_secure_boot_check_finish = 0x4005cc04 );
+PROVIDE ( ets_secure_boot_check_start = 0x4005cbcc );
+PROVIDE ( ets_secure_boot_finish = 0x4005ca84 );
+PROVIDE ( ets_secure_boot_hash = 0x4005cad4 );
+PROVIDE ( ets_secure_boot_obtain = 0x4005cb14 );
+PROVIDE ( ets_secure_boot_rd_abstract = 0x4005cba8 );
+PROVIDE ( ets_secure_boot_rd_iv = 0x4005cb84 );
+PROVIDE ( ets_secure_boot_start = 0x4005ca34 );
+PROVIDE ( ets_set_appcpu_boot_addr = 0x4000689c );
+PROVIDE ( ets_set_idle_cb = 0x40006674 );
+PROVIDE ( ets_set_startup_callback = 0x4000688c );
+PROVIDE ( ets_set_user_start = 0x4000687c );
+PROVIDE ( ets_sha_disable = 0x4005c0a8 );
+PROVIDE ( ets_sha_enable = 0x4005c07c );
+PROVIDE ( ets_sha_finish = 0x4005c104 );
+PROVIDE ( ets_sha_init = 0x4005c0d4 );
+PROVIDE ( ets_sha_update = 0x4005c2a0 );
+PROVIDE ( ets_startup_callback = 0x3ffe0404 );
+PROVIDE ( ets_task = 0x40006688 );
+PROVIDE ( ets_timer_arm = 0x40008368 );
+PROVIDE ( ets_timer_arm_us = 0x400083ac );
+PROVIDE ( ets_timer_disarm = 0x400083ec );
+PROVIDE ( ets_timer_done = 0x40008428 );
+PROVIDE ( ets_timer_handler_isr = 0x40008454 );
+PROVIDE ( ets_timer_init = 0x400084e8 );
+PROVIDE ( ets_timer_setfn = 0x40008350 );
+PROVIDE ( ets_unpack_flash_code = 0x40007018 );
+PROVIDE ( ets_unpack_flash_code_legacy = 0x4000694c );
+PROVIDE ( ets_update_cpu_frequency = 0x40008550 );
+PROVIDE ( ets_waiti0 = 0x400067d8 );
+PROVIDE ( exc_cause_table = 0x3ff991d0 );
+PROVIDE ( _exit_r = 0x4000bd28 );
+PROVIDE ( __extendsfdf2 = 0x40002c34 );
+PROVIDE ( fclose = 0x400020ac );
+PROVIDE ( _fclose_r = 0x40001fec );
+PROVIDE ( fflush = 0x40059394 );
+PROVIDE ( _fflush_r = 0x40059320 );
+PROVIDE ( __ffsdi2 = 0x4000ca2c );
+PROVIDE ( __ffssi2 = 0x4000c804 );
+PROVIDE ( FilePacketSendDeflatedReqMsgProc = 0x40008b24 );
+PROVIDE ( FilePacketSendReqMsgProc = 0x40008860 );
+PROVIDE ( _findenv_r = 0x40001f44 );
+PROVIDE ( fiprintf = 0x40056efc );
+PROVIDE ( _fiprintf_r = 0x40056ed8 );
+PROVIDE ( fiscanf = 0x40058884 );
+PROVIDE ( _fiscanf_r = 0x400588b4 );
+PROVIDE ( __fixdfdi = 0x40002ac4 );
+PROVIDE ( __fixdfsi = 0x40002a78 );
+PROVIDE ( __fixsfdi = 0x4000244c );
+PROVIDE ( __fixsfsi = 0x4000240c );
+PROVIDE ( __fixunsdfsi = 0x40002b30 );
+PROVIDE ( __fixunssfdi = 0x40002504 );
+PROVIDE ( __fixunssfsi = 0x400024ac );
+PROVIDE ( FlashDwnLdDeflatedStartMsgProc = 0x40008ad8 );
+PROVIDE ( FlashDwnLdParamCfgMsgProc = 0x4000891c );
+PROVIDE ( FlashDwnLdStartMsgProc = 0x40008820 );
+PROVIDE ( FlashDwnLdStopDeflatedReqMsgProc = 0x40008c18 );
+PROVIDE ( FlashDwnLdStopReqMsgProc = 0x400088ec );
+PROVIDE ( __floatdidf = 0x4000c988 );
+PROVIDE ( __floatdisf = 0x4000c8c0 );
+PROVIDE ( __floatsidf = 0x4000c944 );
+PROVIDE ( __floatsisf = 0x4000c870 );
+PROVIDE ( __floatundidf = 0x4000c978 );
+PROVIDE ( __floatundisf = 0x4000c8b0 );
+PROVIDE ( __floatunsidf = 0x4000c938 );
+PROVIDE ( __floatunsisf = 0x4000c864 );
+PROVIDE ( __fp_lock_all = 0x40001f1c );
+PROVIDE ( fprintf = 0x40056efc );
+PROVIDE ( _fprintf_r = 0x40056ed8 );
+PROVIDE ( __fp_unlock_all = 0x40001f30 );
+PROVIDE ( fputwc = 0x40058ea8 );
+PROVIDE ( __fputwc = 0x40058da0 );
+PROVIDE ( _fputwc_r = 0x40058e4c );
+PROVIDE ( free = 0x4000beb8 );
+PROVIDE ( _free_r = 0x4000bbcc );
+PROVIDE ( fscanf = 0x40058884 );
+PROVIDE ( _fscanf_r = 0x400588b4 );
+PROVIDE ( _fstat_r = 0x4000bccc );
+PROVIDE ( _fwalk = 0x4000c738 );
+PROVIDE ( _fwalk_reent = 0x4000c770 );
+PROVIDE ( __gcc_bcmp = 0x40064a70 );
+PROVIDE ( __gedf2 = 0x40063768 );
+PROVIDE ( _GeneralException = 0x40000e14 );
+PROVIDE ( __gesf2 = 0x4006340c );
+PROVIDE ( __get_current_time_locale = 0x40001834 );
+PROVIDE ( _getenv_r = 0x40001fbc );
+PROVIDE ( _getpid_r = 0x4000bcfc );
+PROVIDE ( __getreent = 0x4000be8c );
+PROVIDE ( _gettimeofday_r = 0x4000bc58 );
+PROVIDE ( __gettzinfo = 0x40001fcc );
+PROVIDE ( GetUartDevice = 0x40009598 );
+PROVIDE ( GF_Jacobian_Point_Addition256 = 0x400163a4 );
+PROVIDE ( GF_Jacobian_Point_Double256 = 0x40016260 );
+PROVIDE ( GF_Point_Jacobian_To_Affine256 = 0x40016b0c );
+PROVIDE ( _global_impure_ptr = 0x3ffae0b0 );
+PROVIDE ( gmtime = 0x40059848 );
+PROVIDE ( gmtime_r = 0x40059868 );
+PROVIDE ( g_phyFuns_instance = 0x3ffae0c4 );
+PROVIDE ( gpio_init = 0x40009c20 );
+PROVIDE ( gpio_input_get = 0x40009b88 );
+PROVIDE ( gpio_input_get_high = 0x40009b9c );
+PROVIDE ( gpio_intr_ack = 0x40009dd4 );
+PROVIDE ( gpio_intr_ack_high = 0x40009e1c );
+PROVIDE ( gpio_intr_handler_register = 0x40009e6c );
+PROVIDE ( gpio_intr_pending = 0x40009cec );
+PROVIDE ( gpio_intr_pending_high = 0x40009cf8 );
+PROVIDE ( gpio_matrix_in = 0x40009edc );
+PROVIDE ( gpio_matrix_out = 0x40009f0c );
+PROVIDE ( gpio_output_set = 0x40009b24 );
+PROVIDE ( gpio_output_set_high = 0x40009b5c );
+PROVIDE ( gpio_pad_hold = 0x4000a734 );
+PROVIDE ( gpio_pad_pulldown = 0x4000a348 );
+PROVIDE ( gpio_pad_pullup = 0x4000a22c );
+PROVIDE ( gpio_pad_select_gpio = 0x40009fdc );
+PROVIDE ( gpio_pad_set_drv = 0x4000a11c );
+PROVIDE ( gpio_pad_unhold = 0x4000a484 );
+PROVIDE ( gpio_pending_mask = 0x3ffe0038 );
+PROVIDE ( gpio_pending_mask_high = 0x3ffe0044 );
+PROVIDE ( gpio_pin_intr_state_set = 0x40009d04 );
+PROVIDE ( gpio_pin_wakeup_disable = 0x40009eb0 );
+PROVIDE ( gpio_pin_wakeup_enable = 0x40009e7c );
+PROVIDE ( gpio_register_get = 0x40009cbc );
+PROVIDE ( gpio_register_set = 0x40009bbc );
+PROVIDE ( __gtdf2 = 0x400636dc );
+PROVIDE ( __gtsf2 = 0x400633a0 );
+PROVIDE ( gTxMsg = 0x3ffe0050 );
+PROVIDE ( hci_cmd_desc_root_tab = 0x3ff976d4 );
+PROVIDE ( hci_cmd_desc_tab_ctrl_bb = 0x3ff97b70 );
+PROVIDE ( hci_cmd_desc_tab_info_par = 0x3ff97b1c );
+PROVIDE ( hci_cmd_desc_tab_le = 0x3ff97870 );
+PROVIDE ( hci_cmd_desc_tab_lk_ctrl = 0x3ff97fc0 );
+PROVIDE ( hci_cmd_desc_tab_lk_pol = 0x3ff97f3c );
+PROVIDE ( hci_cmd_desc_tab_stat_par = 0x3ff97ac8 );
+PROVIDE ( hci_cmd_desc_tab_testing = 0x3ff97a98 );
+PROVIDE ( hci_cmd_desc_tab_vs = 0x3ff97714 );
+PROVIDE ( hci_command_handler = 0x4004c928 );
+PROVIDE ( hci_env = 0x3ffb9350 );
+PROVIDE ( hci_evt_dbg_desc_tab = 0x3ff9750c );
+PROVIDE ( hci_evt_desc_tab = 0x3ff9751c );
+PROVIDE ( hci_evt_le_desc_tab = 0x3ff974b4 );
+PROVIDE ( hci_fc_env = 0x3ffb9340 );
+PROVIDE ( hmac_md5 = 0x4005d264 );
+PROVIDE ( hmac_md5_vector = 0x4005d17c );
+PROVIDE ( hmac_sha1 = 0x40060acc );
+PROVIDE ( hmac_sha1_vector = 0x400609e4 );
+PROVIDE ( hmac_sha256 = 0x40060d58 );
+PROVIDE ( hmac_sha256_vector = 0x40060c84 );
+PROVIDE ( intr_matrix_set = 0x4000681c );
+PROVIDE ( iprintf = 0x40056978 );
+PROVIDE ( _iprintf_r = 0x40056944 );
+PROVIDE ( isalnum = 0x40000f04 );
+PROVIDE ( isalpha = 0x40000f18 );
+PROVIDE ( isascii = 0x4000c20c );
+PROVIDE ( _isatty_r = 0x40000ea0 );
+PROVIDE ( isblank = 0x40000f2c );
+PROVIDE ( iscanf = 0x40058760 );
+PROVIDE ( _iscanf_r = 0x4005879c );
+PROVIDE ( iscntrl = 0x40000f50 );
+PROVIDE ( isdigit = 0x40000f64 );
+PROVIDE ( isgraph = 0x40000f94 );
+PROVIDE ( islower = 0x40000f78 );
+PROVIDE ( isprint = 0x40000fa8 );
+PROVIDE ( ispunct = 0x40000fc0 );
+PROVIDE ( isspace = 0x40000fd4 );
+PROVIDE ( isupper = 0x40000fe8 );
+PROVIDE ( itoa = 0x400566b4 );
+PROVIDE ( __itoa = 0x40056678 );
+PROVIDE ( jd_decomp = 0x400613e8 );
+PROVIDE ( jd_prepare = 0x40060fa8 );
+PROVIDE ( ke_env = 0x3ffb93cc );
+PROVIDE ( _KernelExceptionVector = 0x40000300 );
+PROVIDE ( _kill_r = 0x4000bd10 );
+PROVIDE ( labs = 0x40056370 );
+PROVIDE ( lb_default_handler = 0x3ff982b8 );
+PROVIDE ( lb_default_state_tab_p_get = 0x4001c198 );
+PROVIDE ( lb_env = 0x3ffb9424 );
+PROVIDE ( lb_hci_cmd_handler_tab_p_get = 0x4001c18c );
+PROVIDE ( lb_state = 0x3ffb94e8 );
+PROVIDE ( lc_default_handler = 0x3ff98648 );
+PROVIDE ( lc_default_state_tab_p_get = 0x4002f494 );
+PROVIDE ( lc_env = 0x3ffb94ec );
+PROVIDE ( lc_hci_cmd_handler_tab_p_get = 0x4002f488 );
+PROVIDE ( lc_state = 0x3ffb9508 );
+PROVIDE ( ld_acl_br_sizes = 0x3ff98a2a );
+PROVIDE ( ld_acl_br_types = 0x3ff98a36 );
+PROVIDE ( ld_acl_edr_sizes = 0x3ff98a14 );
+PROVIDE ( ld_acl_edr_types = 0x3ff98a22 );
+PROVIDE ( ld_env = 0x3ffb9510 );
+PROVIDE ( ldiv = 0x40056378 );
+PROVIDE ( ld_pcm_settings_dft = 0x3ff98a0c );
+PROVIDE ( ld_sched_params = 0x3ffb96c0 );
+PROVIDE ( ld_sync_train_channels = 0x3ff98a3c );
+PROVIDE ( __ledf2 = 0x40063704 );
+PROVIDE ( __lesf2 = 0x400633c0 );
+PROVIDE ( _Level2FromVector = 0x40000954 );
+PROVIDE ( _Level2Vector = 0x40000180 );
+PROVIDE ( _Level3FromVector = 0x40000a28 );
+PROVIDE ( _Level3Vector = 0x400001c0 );
+PROVIDE ( _Level4FromVector = 0x40000af8 );
+PROVIDE ( _Level4Vector = 0x40000200 );
+PROVIDE ( _Level5FromVector = 0x40000c68 );
+PROVIDE ( _Level5Vector = 0x40000240 );
+PROVIDE ( _LevelOneInterrupt = 0x40000835 );
+PROVIDE ( _link_r = 0x4000bc9c );
+PROVIDE ( llc_default_handler = 0x3ff98b3c );
+PROVIDE ( llc_default_state_tab_p_get = 0x40046058 );
+PROVIDE ( llc_env = 0x3ffb96d0 );
+PROVIDE ( llc_hci_acl_data_tx_handler = 0x40042398 );
+PROVIDE ( llc_hci_cmd_handler_tab_p_get = 0x40042358 );
+PROVIDE ( llc_hci_command_handler = 0x40042360 );
+PROVIDE ( llcp_pdu_handler_tab_p_get = 0x40043f64 );
+PROVIDE ( llc_state = 0x3ffb96f8 );
+PROVIDE ( lldesc_build_chain = 0x4000a850 );
+PROVIDE ( lldesc_num2link = 0x4000a948 );
+PROVIDE ( lldesc_set_owner = 0x4000a974 );
+PROVIDE ( lld_evt_env = 0x3ffb9704 );
+PROVIDE ( lld_pdu_adv_pk_desc_tab = 0x3ff98c70 );
+PROVIDE ( lld_pdu_llcp_pk_desc_tab = 0x3ff98b68 );
+PROVIDE ( LLM_AA_CT1 = 0x3ff98d8a );
+PROVIDE ( LLM_AA_CT2 = 0x3ff98d88 );
+PROVIDE ( llm_default_handler = 0x3ff98d80 );
+PROVIDE ( llm_default_state_tab_p_get = 0x4004e718 );
+PROVIDE ( llm_hci_cmd_handler_tab_p_get = 0x4004c920 );
+PROVIDE ( llm_le_env = 0x3ffb976c );
+PROVIDE ( llm_local_cmds = 0x3ff98d38 );
+PROVIDE ( llm_local_data_len_values = 0x3ff98d1c );
+PROVIDE ( llm_local_le_feats = 0x3ff98d30 );
+PROVIDE ( llm_local_le_states = 0x3ff98d28 );
+PROVIDE ( llm_state = 0x3ffb985c );
+PROVIDE ( lm_default_handler = 0x3ff990e0 );
+PROVIDE ( lm_default_state_tab_p_get = 0x40054268 );
+PROVIDE ( lm_env = 0x3ffb9860 );
+PROVIDE ( lm_hci_cmd_handler_tab_p_get = 0x4005425c );
+PROVIDE ( lm_local_supp_feats = 0x3ff990ee );
+PROVIDE ( lm_n_page_tab = 0x3ff990e8 );
+PROVIDE ( lmp_desc_tab = 0x3ff96e6c );
+PROVIDE ( lmp_ext_desc_tab = 0x3ff96d9c );
+PROVIDE ( lm_state = 0x3ffb9a1c );
+PROVIDE ( __locale_charset = 0x40059540 );
+PROVIDE ( __locale_cjk_lang = 0x40059558 );
+PROVIDE ( localeconv = 0x4005957c );
+PROVIDE ( _localeconv_r = 0x40059560 );
+PROVIDE ( __locale_mb_cur_max = 0x40059548 );
+PROVIDE ( __locale_msgcharset = 0x40059550 );
+PROVIDE ( localtime = 0x400595dc );
+PROVIDE ( localtime_r = 0x400595fc );
+PROVIDE ( _lock_acquire = 0x4000be14 );
+PROVIDE ( _lock_acquire_recursive = 0x4000be28 );
+PROVIDE ( _lock_close = 0x4000bdec );
+PROVIDE ( _lock_close_recursive = 0x4000be00 );
+PROVIDE ( _lock_init = 0x4000bdc4 );
+PROVIDE ( _lock_init_recursive = 0x4000bdd8 );
+PROVIDE ( _lock_release = 0x4000be64 );
+PROVIDE ( _lock_release_recursive = 0x4000be78 );
+PROVIDE ( _lock_try_acquire = 0x4000be3c );
+PROVIDE ( _lock_try_acquire_recursive = 0x4000be50 );
+PROVIDE ( longjmp = 0x400562cc );
+PROVIDE ( _lseek_r = 0x4000bd8c );
+PROVIDE ( __lshrdi3 = 0x4000c84c );
+PROVIDE ( __ltdf2 = 0x40063790 );
+PROVIDE ( __ltsf2 = 0x4006342c );
+PROVIDE ( malloc = 0x4000bea0 );
+PROVIDE ( _malloc_r = 0x4000bbb4 );
+PROVIDE ( maxSecretKey_256 = 0x3ff97448 );
+PROVIDE ( __mb_cur_max = 0x3ff96530 );
+PROVIDE ( MD5Final = 0x4005db1c );
+PROVIDE ( MD5Init = 0x4005da7c );
+PROVIDE ( MD5Update = 0x4005da9c );
+PROVIDE ( md5_vector = 0x4005db80 );
+PROVIDE ( memccpy = 0x4000c220 );
+PROVIDE ( memchr = 0x4000c244 );
+PROVIDE ( memcmp = 0x4000c260 );
+PROVIDE ( memcpy = 0x4000c2c8 );
+PROVIDE ( MemDwnLdStartMsgProc = 0x40008948 );
+PROVIDE ( MemDwnLdStopReqMsgProc = 0x400089dc );
+PROVIDE ( memmove = 0x4000c3c0 );
+PROVIDE ( MemPacketSendReqMsgProc = 0x40008978 );
+PROVIDE ( memrchr = 0x4000c400 );
+PROVIDE ( memset = 0x4000c44c );
+PROVIDE ( mktime = 0x4005a5e8 );
+PROVIDE ( mmu_init = 0x400095a4 );
+PROVIDE ( __moddi3 = 0x4000cd4c );
+PROVIDE ( __modsi3 = 0x4000c7c0 );
+PROVIDE ( __month_lengths = 0x3ff9609c );
+PROVIDE ( __muldc3 = 0x40063bf4 );
+PROVIDE ( __muldf3 = 0x4006358c );
+PROVIDE ( __muldi3 = 0x4000c9fc );
+PROVIDE ( __mulsc3 = 0x40063934 );
+PROVIDE ( __mulsf3 = 0x400632c8 );
+PROVIDE ( __mulsi3 = 0x4000c7b0 );
+PROVIDE ( MultiplyBigHexByUint32_256 = 0x40016214 );
+PROVIDE ( MultiplyBigHexModP256 = 0x400160b8 );
+PROVIDE ( MultiplyByU32ModP256 = 0x40015fdc );
+PROVIDE ( multofup = 0x4000ab8c );
+PROVIDE ( __mulvdi3 = 0x40002d78 );
+PROVIDE ( __mulvsi3 = 0x40002d60 );
+PROVIDE ( mz_adler32 = 0x4005edbc );
+PROVIDE ( mz_crc32 = 0x4005ee88 );
+PROVIDE ( mz_free = 0x4005eed4 );
+PROVIDE ( __nedf2 = 0x400636a8 );
+PROVIDE ( __negdf2 = 0x400634a0 );
+PROVIDE ( __negdi2 = 0x4000ca14 );
+PROVIDE ( __negsf2 = 0x400020c0 );
+PROVIDE ( __negvdi2 = 0x40002e98 );
+PROVIDE ( __negvsi2 = 0x40002e78 );
+PROVIDE ( __nesf2 = 0x40063374 );
+PROVIDE ( _NMIExceptionVector = 0x400002c0 );
+PROVIDE ( notEqual256 = 0x40015b04 );
+PROVIDE ( __nsau_data = 0x3ff96544 );
+PROVIDE ( one_bits = 0x3ff971f8 );
+PROVIDE ( open = 0x4000178c );
+PROVIDE ( _open_r = 0x4000bd54 );
+PROVIDE ( __paritysi2 = 0x40002f3c );
+PROVIDE ( pbkdf2_sha1 = 0x40060ba4 );
+PROVIDE ( phy_get_romfuncs = 0x40004100 );
+PROVIDE ( __popcountdi2 = 0x40002ef8 );
+PROVIDE ( __popcountsi2 = 0x40002ed0 );
+PROVIDE ( __popcount_tab = 0x3ff96544 );
+PROVIDE ( __powidf2 = 0x400638d4 );
+PROVIDE ( __powisf2 = 0x4006389c );
+PROVIDE ( _Pri_4_HandlerAddress = 0x3ffe0648 );
+PROVIDE ( _Pri_5_HandlerAddress = 0x3ffe064c );
+PROVIDE ( printf = 0x40056978 );
+PROVIDE ( _printf_common = 0x40057338 );
+PROVIDE ( _printf_float = 0x4000befc );
+PROVIDE ( _printf_i = 0x40057404 );
+PROVIDE ( _printf_r = 0x40056944 );
+PROVIDE ( qsort = 0x40056424 );
+PROVIDE ( _raise_r = 0x4000bc70 );
+PROVIDE ( rand = 0x40001058 );
+PROVIDE ( rand_r = 0x400010d4 );
+PROVIDE ( r_btdm_option_data = 0x3ffae6e0 );
+PROVIDE ( r_bt_util_buf_acl_rx_alloc = 0x40010218 );
+PROVIDE ( r_bt_util_buf_acl_rx_free = 0x40010234 );
+PROVIDE ( r_bt_util_buf_acl_tx_alloc = 0x40010268 );
+PROVIDE ( r_bt_util_buf_acl_tx_free = 0x40010280 );
+PROVIDE ( r_bt_util_buf_init = 0x400100e4 );
+PROVIDE ( r_bt_util_buf_lmp_tx_alloc = 0x400101d0 );
+PROVIDE ( r_bt_util_buf_lmp_tx_free = 0x400101ec );
+PROVIDE ( r_bt_util_buf_sync_clear = 0x400103c8 );
+PROVIDE ( r_bt_util_buf_sync_init = 0x400102c4 );
+PROVIDE ( r_bt_util_buf_sync_rx_alloc = 0x40010468 );
+PROVIDE ( r_bt_util_buf_sync_rx_free = 0x4001049c );
+PROVIDE ( r_bt_util_buf_sync_tx_alloc = 0x400103ec );
+PROVIDE ( r_bt_util_buf_sync_tx_free = 0x40010428 );
+PROVIDE ( rc4_skip = 0x40060928 );
+PROVIDE ( r_co_bdaddr_compare = 0x40014324 );
+PROVIDE ( r_co_bytes_to_string = 0x400142e4 );
+PROVIDE ( r_co_list_check_size_available = 0x400142c4 );
+PROVIDE ( r_co_list_extract = 0x4001404c );
+PROVIDE ( r_co_list_extract_after = 0x40014118 );
+PROVIDE ( r_co_list_find = 0x4001419c );
+PROVIDE ( r_co_list_init = 0x40013f14 );
+PROVIDE ( r_co_list_insert_after = 0x40014254 );
+PROVIDE ( r_co_list_insert_before = 0x40014200 );
+PROVIDE ( r_co_list_merge = 0x400141bc );
+PROVIDE ( r_co_list_pool_init = 0x40013f30 );
+PROVIDE ( r_co_list_pop_front = 0x40014028 );
+PROVIDE ( r_co_list_push_back = 0x40013fb8 );
+PROVIDE ( r_co_list_push_front = 0x40013ff4 );
+PROVIDE ( r_co_list_size = 0x400142ac );
+PROVIDE ( r_co_nb_good_channels = 0x40014360 );
+PROVIDE ( r_co_slot_to_duration = 0x40014348 );
+PROVIDE ( RcvMsg = 0x4000954c );
+PROVIDE ( r_dbg_init = 0x40014394 );
+PROVIDE ( r_dbg_platform_reset_complete = 0x400143d0 );
+PROVIDE ( r_dbg_swdiag_init = 0x40014470 );
+PROVIDE ( r_dbg_swdiag_read = 0x400144a4 );
+PROVIDE ( r_dbg_swdiag_write = 0x400144d0 );
+PROVIDE ( r_E1 = 0x400108e8 );
+PROVIDE ( r_E21 = 0x40010968 );
+PROVIDE ( r_E22 = 0x400109b4 );
+PROVIDE ( r_E3 = 0x40010a58 );
+PROVIDE ( r_ea_alarm_clear = 0x40015ab4 );
+PROVIDE ( r_ea_alarm_set = 0x40015a10 );
+PROVIDE ( read = 0x400017dc );
+PROVIDE ( _read_r = 0x4000bda8 );
+PROVIDE ( r_ea_elt_cancel = 0x400150d0 );
+PROVIDE ( r_ea_elt_create = 0x40015264 );
+PROVIDE ( r_ea_elt_insert = 0x400152a8 );
+PROVIDE ( r_ea_elt_remove = 0x400154f0 );
+PROVIDE ( r_ea_finetimer_isr = 0x400155d4 );
+PROVIDE ( r_ea_init = 0x40015228 );
+PROVIDE ( r_ea_interval_create = 0x4001555c );
+PROVIDE ( r_ea_interval_delete = 0x400155a8 );
+PROVIDE ( r_ea_interval_duration_req = 0x4001597c );
+PROVIDE ( r_ea_interval_insert = 0x4001557c );
+PROVIDE ( r_ea_interval_remove = 0x40015590 );
+PROVIDE ( realloc = 0x4000becc );
+PROVIDE ( _realloc_r = 0x4000bbe0 );
+PROVIDE ( r_ea_offset_req = 0x40015748 );
+PROVIDE ( r_ea_sleep_check = 0x40015928 );
+PROVIDE ( r_ea_sw_isr = 0x40015724 );
+PROVIDE ( r_ea_time_get_halfslot_rounded = 0x40015894 );
+PROVIDE ( r_ea_time_get_slot_rounded = 0x400158d4 );
+PROVIDE ( r_ecc_abort_key256_generation = 0x40017070 );
+PROVIDE ( r_ecc_generate_key256 = 0x40016e00 );
+PROVIDE ( r_ecc_gen_new_public_key = 0x400170c0 );
+PROVIDE ( r_ecc_gen_new_secret_key = 0x400170e4 );
+PROVIDE ( r_ecc_get_debug_Keys = 0x40017224 );
+PROVIDE ( r_ecc_init = 0x40016dbc );
+PROVIDE ( RecvBuff = 0x3ffe009c );
+PROVIDE ( recv_packet = 0x40009424 );
+PROVIDE ( r_em_buf_init = 0x4001729c );
+PROVIDE ( r_em_buf_rx_buff_addr_get = 0x400173e8 );
+PROVIDE ( r_em_buf_rx_free = 0x400173c4 );
+PROVIDE ( r_em_buf_tx_buff_addr_get = 0x40017404 );
+PROVIDE ( r_em_buf_tx_free = 0x4001741c );
+PROVIDE ( _rename_r = 0x4000bc28 );
+PROVIDE ( _ResetHandler = 0x40000450 );
+PROVIDE ( _ResetVector = 0x40000400 );
+PROVIDE ( r_F1_256 = 0x400133e4 );
+PROVIDE ( r_F2_256 = 0x40013568 );
+PROVIDE ( r_F3_256 = 0x40013664 );
+PROVIDE ( RFPLL_ICP_TABLE = 0x3ffb8b7c );
+PROVIDE ( r_G_256 = 0x40013470 );
+PROVIDE ( r_H3 = 0x40013760 );
+PROVIDE ( r_H4 = 0x40013830 );
+PROVIDE ( r_h4tl_init = 0x40017878 );
+PROVIDE ( r_h4tl_start = 0x40017924 );
+PROVIDE ( r_h4tl_stop = 0x40017934 );
+PROVIDE ( r_h4tl_write = 0x400178d0 );
+PROVIDE ( r_H5 = 0x400138dc );
+PROVIDE ( r_hashConcat = 0x40013a38 );
+PROVIDE ( r_hci_acl_tx_data_alloc = 0x4001951c );
+PROVIDE ( r_hci_acl_tx_data_received = 0x40019654 );
+PROVIDE ( r_hci_bt_acl_bdaddr_register = 0x40018900 );
+PROVIDE ( r_hci_bt_acl_bdaddr_unregister = 0x400189ac );
+PROVIDE ( r_hci_bt_acl_conhdl_register = 0x4001895c );
+PROVIDE ( r_hci_cmd_get_max_param_size = 0x400192d0 );
+PROVIDE ( r_hci_cmd_received = 0x400192f8 );
+PROVIDE ( r_hci_evt_filter_add = 0x40018a64 );
+PROVIDE ( r_hci_evt_mask_set = 0x400189e4 );
+PROVIDE ( r_hci_fc_acl_buf_size_set = 0x40017988 );
+PROVIDE ( r_hci_fc_acl_en = 0x400179d8 );
+PROVIDE ( r_hci_fc_acl_packet_sent = 0x40017a3c );
+PROVIDE ( r_hci_fc_check_host_available_nb_acl_packets = 0x40017aa4 );
+PROVIDE ( r_hci_fc_check_host_available_nb_sync_packets = 0x40017ac8 );
+PROVIDE ( r_hci_fc_host_nb_acl_pkts_complete = 0x40017a6c );
+PROVIDE ( r_hci_fc_host_nb_sync_pkts_complete = 0x40017a88 );
+PROVIDE ( r_hci_fc_init = 0x40017974 );
+PROVIDE ( r_hci_fc_sync_buf_size_set = 0x400179b0 );
+PROVIDE ( r_hci_fc_sync_en = 0x40017a30 );
+PROVIDE ( r_hci_fc_sync_packet_sent = 0x40017a54 );
+PROVIDE ( r_hci_init = 0x40018538 );
+PROVIDE ( r_hci_look_for_cmd_desc = 0x40018454 );
+PROVIDE ( r_hci_look_for_dbg_evt_desc = 0x400184c4 );
+PROVIDE ( r_hci_look_for_evt_desc = 0x400184a0 );
+PROVIDE ( r_hci_look_for_le_evt_desc = 0x400184e0 );
+PROVIDE ( r_hci_reset = 0x4001856c );
+PROVIDE ( r_hci_send_2_host = 0x400185bc );
+PROVIDE ( r_hci_sync_tx_data_alloc = 0x40019754 );
+PROVIDE ( r_hci_sync_tx_data_received = 0x400197c0 );
+PROVIDE ( r_hci_tl_init = 0x40019290 );
+PROVIDE ( r_hci_tl_send = 0x40019228 );
+PROVIDE ( r_hci_util_pack = 0x40019874 );
+PROVIDE ( r_hci_util_unpack = 0x40019998 );
+PROVIDE ( r_hci_voice_settings_get = 0x40018bdc );
+PROVIDE ( r_hci_voice_settings_set = 0x40018be8 );
+PROVIDE ( r_HMAC = 0x40013968 );
+PROVIDE ( r_import_rf_phy_func = 0x3ffb8354 );
+PROVIDE ( r_import_rf_phy_func_p = 0x3ffafd64 );
+PROVIDE ( r_ip_funcs = 0x3ffae710 );
+PROVIDE ( r_ip_funcs_p = 0x3ffae70c );
+PROVIDE ( r_ke_check_malloc = 0x40019de0 );
+PROVIDE ( r_ke_event_callback_set = 0x40019ba8 );
+PROVIDE ( r_ke_event_clear = 0x40019c2c );
+PROVIDE ( r_ke_event_flush = 0x40019ccc );
+PROVIDE ( r_ke_event_get = 0x40019c78 );
+PROVIDE ( r_ke_event_get_all = 0x40019cc0 );
+PROVIDE ( r_ke_event_init = 0x40019b90 );
+PROVIDE ( r_ke_event_schedule = 0x40019cdc );
+PROVIDE ( r_ke_event_set = 0x40019be0 );
+PROVIDE ( r_ke_flush = 0x4001a374 );
+PROVIDE ( r_ke_free = 0x4001a014 );
+PROVIDE ( r_ke_get_max_mem_usage = 0x4001a1c8 );
+PROVIDE ( r_ke_get_mem_usage = 0x4001a1a0 );
+PROVIDE ( r_ke_init = 0x4001a318 );
+PROVIDE ( r_ke_is_free = 0x4001a184 );
+PROVIDE ( r_ke_malloc = 0x40019eb4 );
+PROVIDE ( r_ke_mem_init = 0x40019d3c );
+PROVIDE ( r_ke_mem_is_empty = 0x40019d8c );
+PROVIDE ( r_ke_msg_alloc = 0x4001a1e0 );
+PROVIDE ( r_ke_msg_dest_id_get = 0x4001a2e0 );
+PROVIDE ( r_ke_msg_discard = 0x4001a850 );
+PROVIDE ( r_ke_msg_forward = 0x4001a290 );
+PROVIDE ( r_ke_msg_forward_new_id = 0x4001a2ac );
+PROVIDE ( r_ke_msg_free = 0x4001a2cc );
+PROVIDE ( r_ke_msg_in_queue = 0x4001a2f8 );
+PROVIDE ( r_ke_msg_save = 0x4001a858 );
+PROVIDE ( r_ke_msg_send = 0x4001a234 );
+PROVIDE ( r_ke_msg_send_basic = 0x4001a26c );
+PROVIDE ( r_ke_msg_src_id_get = 0x4001a2ec );
+PROVIDE ( r_ke_queue_extract = 0x40055fd0 );
+PROVIDE ( r_ke_queue_insert = 0x40056020 );
+PROVIDE ( r_ke_sleep_check = 0x4001a3d8 );
+PROVIDE ( r_ke_state_get = 0x4001a7d8 );
+PROVIDE ( r_ke_state_set = 0x4001a6fc );
+PROVIDE ( r_ke_stats_get = 0x4001a3f0 );
+PROVIDE ( r_ke_task_check = 0x4001a8a4 );
+PROVIDE ( r_ke_task_create = 0x4001a674 );
+PROVIDE ( r_ke_task_delete = 0x4001a6c0 );
+PROVIDE ( r_ke_task_init = 0x4001a650 );
+PROVIDE ( r_ke_task_msg_flush = 0x4001a860 );
+PROVIDE ( r_ke_timer_active = 0x4001ac08 );
+PROVIDE ( r_ke_timer_adjust_all = 0x4001ac30 );
+PROVIDE ( r_ke_timer_clear = 0x4001ab90 );
+PROVIDE ( r_ke_timer_init = 0x4001aa9c );
+PROVIDE ( r_ke_timer_set = 0x4001aac0 );
+PROVIDE ( r_ke_timer_sleep_check = 0x4001ac50 );
+PROVIDE ( r_KPrimC = 0x40010ad4 );
+PROVIDE ( r_lb_clk_adj_activate = 0x4001ae70 );
+PROVIDE ( r_lb_clk_adj_id_get = 0x4001af14 );
+PROVIDE ( r_lb_clk_adj_period_update = 0x4001af20 );
+PROVIDE ( r_lb_init = 0x4001acd4 );
+PROVIDE ( r_lb_mst_key = 0x4001afc0 );
+PROVIDE ( r_lb_mst_key_cmp = 0x4001af74 );
+PROVIDE ( r_lb_mst_key_restart_enc = 0x4001b0d4 );
+PROVIDE ( r_lb_mst_start_act_bcst_enc = 0x4001b198 );
+PROVIDE ( r_lb_mst_stop_act_bcst_enc = 0x4001b24c );
+PROVIDE ( r_lb_reset = 0x4001ad38 );
+PROVIDE ( r_lb_send_lmp = 0x4001adbc );
+PROVIDE ( r_lb_send_pdu_clk_adj = 0x4001af3c );
+PROVIDE ( r_lb_util_get_csb_mode = 0x4001ada4 );
+PROVIDE ( r_lb_util_get_nb_broadcast = 0x4001ad80 );
+PROVIDE ( r_lb_util_get_res_lt_addr = 0x4001ad98 );
+PROVIDE ( r_lb_util_set_nb_broadcast = 0x4001ad8c );
+PROVIDE ( r_lc_afh_set = 0x4001cc74 );
+PROVIDE ( r_lc_afh_start = 0x4001d240 );
+PROVIDE ( r_lc_auth_cmp = 0x4001cd54 );
+PROVIDE ( r_lc_calc_link_key = 0x4001ce7c );
+PROVIDE ( r_lc_chg_pkt_type_cmp = 0x4001d038 );
+PROVIDE ( r_lc_chg_pkt_type_cont = 0x4001cfbc );
+PROVIDE ( r_lc_chg_pkt_type_retry = 0x4001d0ac );
+PROVIDE ( r_lc_chk_to = 0x4001d2a8 );
+PROVIDE ( r_lc_cmd_stat_send = 0x4001c914 );
+PROVIDE ( r_lc_comb_key_svr = 0x4001d30c );
+PROVIDE ( r_lc_con_cmp = 0x4001d44c );
+PROVIDE ( r_lc_con_cmp_evt_send = 0x4001d4fc );
+PROVIDE ( r_lc_conn_seq_done = 0x40021334 );
+PROVIDE ( r_lc_detach = 0x4002037c );
+PROVIDE ( r_lc_dhkey = 0x4001d564 );
+PROVIDE ( r_lc_enc_cmp = 0x4001d8bc );
+PROVIDE ( r_lc_enc_key_refresh = 0x4001d720 );
+PROVIDE ( r_lc_end_chk_colli = 0x4001d858 );
+PROVIDE ( r_lc_end_of_sniff_nego = 0x4001d9a4 );
+PROVIDE ( r_lc_enter_sniff_mode = 0x4001ddb8 );
+PROVIDE ( r_lc_epr_change_lk = 0x4001db38 );
+PROVIDE ( r_lc_epr_cmp = 0x4001da88 );
+PROVIDE ( r_lc_epr_resp = 0x4001e0b4 );
+PROVIDE ( r_lc_epr_rsw_cmp = 0x4001dd40 );
+PROVIDE ( r_lc_ext_feat = 0x40020d6c );
+PROVIDE ( r_lc_feat = 0x40020984 );
+PROVIDE ( r_lc_hl_connect = 0x400209e8 );
+PROVIDE ( r_lc_init = 0x4001c948 );
+PROVIDE ( r_lc_init_calc_f3 = 0x4001deb0 );
+PROVIDE ( r_lc_initiator_epr = 0x4001e064 );
+PROVIDE ( r_lc_init_passkey_loop = 0x4001dfc0 );
+PROVIDE ( r_lc_init_start_mutual_auth = 0x4001df60 );
+PROVIDE ( r_lc_key_exch_end = 0x4001e140 );
+PROVIDE ( r_lc_legacy_pair = 0x4001e1c0 );
+PROVIDE ( r_lc_local_switch = 0x4001e22c );
+PROVIDE ( r_lc_local_trans_mode = 0x4001e2e4 );
+PROVIDE ( r_lc_local_untrans_mode = 0x4001e3a0 );
+PROVIDE ( r_lc_loc_auth = 0x40020ecc );
+PROVIDE ( r_lc_locepr_lkref = 0x4001d648 );
+PROVIDE ( r_lc_locepr_rsw = 0x4001d5d0 );
+PROVIDE ( r_lc_loc_sniff = 0x40020a6c );
+PROVIDE ( r_lc_max_slot_mgt = 0x4001e410 );
+PROVIDE ( r_lc_mst_key = 0x4001e7c0 );
+PROVIDE ( r_lc_mst_qos_done = 0x4001ea80 );
+PROVIDE ( r_lc_mst_send_mst_key = 0x4001e8f4 );
+PROVIDE ( r_lc_mutual_auth_end = 0x4001e670 );
+PROVIDE ( r_lc_mutual_auth_end2 = 0x4001e4f4 );
+PROVIDE ( r_lc_packet_type = 0x40021038 );
+PROVIDE ( r_lc_pair = 0x40020ddc );
+PROVIDE ( r_lc_pairing_cont = 0x4001eafc );
+PROVIDE ( r_lc_passkey_comm = 0x4001ed20 );
+PROVIDE ( r_lc_prepare_all_links_for_clk_adj = 0x40021430 );
+PROVIDE ( r_lc_proc_rcv_dhkey = 0x4001edec );
+PROVIDE ( r_lc_ptt = 0x4001ee2c );
+PROVIDE ( r_lc_ptt_cmp = 0x4001eeec );
+PROVIDE ( r_lc_qos_setup = 0x4001ef50 );
+PROVIDE ( r_lc_rd_rem_name = 0x4001efd0 );
+PROVIDE ( r_lc_release = 0x4001f8a8 );
+PROVIDE ( r_lc_rem_enc = 0x4001f124 );
+PROVIDE ( r_lc_rem_name_cont = 0x4001f290 );
+PROVIDE ( r_lc_rem_nego_trans_mode = 0x4001f1b4 );
+PROVIDE ( r_lc_rem_sniff = 0x40020ca4 );
+PROVIDE ( r_lc_rem_sniff_sub_rate = 0x40020b10 );
+PROVIDE ( r_lc_rem_switch = 0x4001f070 );
+PROVIDE ( r_lc_rem_trans_mode = 0x4001f314 );
+PROVIDE ( r_lc_rem_unsniff = 0x400207a0 );
+PROVIDE ( r_lc_rem_untrans_mode = 0x4001f36c );
+PROVIDE ( r_lc_reset = 0x4001c99c );
+PROVIDE ( r_lc_resp_auth = 0x4001f518 );
+PROVIDE ( r_lc_resp_calc_f3 = 0x4001f710 );
+PROVIDE ( r_lc_resp_num_comp = 0x40020074 );
+PROVIDE ( r_lc_resp_oob_nonce = 0x4001f694 );
+PROVIDE ( r_lc_resp_oob_wait_nonce = 0x4001f66c );
+PROVIDE ( r_lc_resp_pair = 0x400208a4 );
+PROVIDE ( r_lc_resp_sec_auth = 0x4001f4a0 );
+PROVIDE ( r_lc_resp_wait_dhkey_cont = 0x4001f86c );
+PROVIDE ( r_lc_restart_enc = 0x4001f8ec );
+PROVIDE ( r_lc_restart_enc_cont = 0x4001f940 );
+PROVIDE ( r_lc_restore_afh_reporting = 0x4001f028 );
+PROVIDE ( r_lc_restore_to = 0x4001f9e0 );
+PROVIDE ( r_lc_ret_sniff_max_slot_chg = 0x4001fa30 );
+PROVIDE ( r_lc_rsw_clean_up = 0x4001dc70 );
+PROVIDE ( r_lc_rsw_done = 0x4001db94 );
+PROVIDE ( r_lc_sco_baseband_ack = 0x40022b00 );
+PROVIDE ( r_lc_sco_detach = 0x40021e40 );
+PROVIDE ( r_lc_sco_host_accept = 0x40022118 );
+PROVIDE ( r_lc_sco_host_reject = 0x400222b8 );
+PROVIDE ( r_lc_sco_host_request = 0x40021f4c );
+PROVIDE ( r_lc_sco_host_request_disc = 0x4002235c );
+PROVIDE ( r_lc_sco_init = 0x40021dc8 );
+PROVIDE ( r_lc_sco_peer_accept = 0x40022780 );
+PROVIDE ( r_lc_sco_peer_accept_disc = 0x40022a08 );
+PROVIDE ( r_lc_sco_peer_reject = 0x40022824 );
+PROVIDE ( r_lc_sco_peer_reject_disc = 0x40022a8c );
+PROVIDE ( r_lc_sco_peer_request = 0x4002240c );
+PROVIDE ( r_lc_sco_peer_request_disc = 0x400228ec );
+PROVIDE ( r_lc_sco_release = 0x40021eec );
+PROVIDE ( r_lc_sco_reset = 0x40021dfc );
+PROVIDE ( r_lc_sco_timeout = 0x40022bd4 );
+PROVIDE ( r_lc_sec_auth_compute_sres = 0x4001f3ec );
+PROVIDE ( r_lc_semi_key_cmp = 0x40020294 );
+PROVIDE ( r_lc_send_enc_chg_evt = 0x4002134c );
+PROVIDE ( r_lc_send_enc_mode = 0x40020220 );
+PROVIDE ( r_lc_send_lmp = 0x4001c1a8 );
+PROVIDE ( r_lc_send_pdu_acc = 0x4001c21c );
+PROVIDE ( r_lc_send_pdu_acc_ext4 = 0x4001c240 );
+PROVIDE ( r_lc_send_pdu_au_rand = 0x4001c308 );
+PROVIDE ( r_lc_send_pdu_auto_rate = 0x4001c5d0 );
+PROVIDE ( r_lc_send_pdu_clk_adj_ack = 0x4001c46c );
+PROVIDE ( r_lc_send_pdu_clk_adj_req = 0x4001c494 );
+PROVIDE ( r_lc_send_pdu_comb_key = 0x4001c368 );
+PROVIDE ( r_lc_send_pdu_dhkey_chk = 0x4001c8e8 );
+PROVIDE ( r_lc_send_pdu_encaps_head = 0x4001c440 );
+PROVIDE ( r_lc_send_pdu_encaps_payl = 0x4001c410 );
+PROVIDE ( r_lc_send_pdu_enc_key_sz_req = 0x4001c670 );
+PROVIDE ( r_lc_send_pdu_esco_lk_rem_req = 0x4001c5a8 );
+PROVIDE ( r_lc_send_pdu_feats_ext_req = 0x4001c6ec );
+PROVIDE ( r_lc_send_pdu_feats_res = 0x4001c694 );
+PROVIDE ( r_lc_send_pdu_in_rand = 0x4001c338 );
+PROVIDE ( r_lc_send_pdu_io_cap_res = 0x4001c72c );
+PROVIDE ( r_lc_send_pdu_lsto = 0x4001c64c );
+PROVIDE ( r_lc_send_pdu_max_slot = 0x4001c3c8 );
+PROVIDE ( r_lc_send_pdu_max_slot_req = 0x4001c3ec );
+PROVIDE ( r_lc_send_pdu_not_acc = 0x4001c26c );
+PROVIDE ( r_lc_send_pdu_not_acc_ext4 = 0x4001c294 );
+PROVIDE ( r_lc_send_pdu_num_comp_fail = 0x4001c770 );
+PROVIDE ( r_lc_send_pdu_pause_enc_aes_req = 0x4001c794 );
+PROVIDE ( r_lc_send_pdu_paus_enc_req = 0x4001c7c0 );
+PROVIDE ( r_lc_send_pdu_ptt_req = 0x4001c4c0 );
+PROVIDE ( r_lc_send_pdu_qos_req = 0x4001c82c );
+PROVIDE ( r_lc_send_pdu_resu_enc_req = 0x4001c7e4 );
+PROVIDE ( r_lc_send_pdu_sco_lk_rem_req = 0x4001c580 );
+PROVIDE ( r_lc_send_pdu_set_afh = 0x4001c2c8 );
+PROVIDE ( r_lc_send_pdu_setup_cmp = 0x4001c808 );
+PROVIDE ( r_lc_send_pdu_slot_off = 0x4001c854 );
+PROVIDE ( r_lc_send_pdu_sniff_req = 0x4001c5f0 );
+PROVIDE ( r_lc_send_pdu_sp_cfm = 0x4001c518 );
+PROVIDE ( r_lc_send_pdu_sp_nb = 0x4001c4e8 );
+PROVIDE ( r_lc_send_pdu_sres = 0x4001c548 );
+PROVIDE ( r_lc_send_pdu_tim_acc = 0x4001c6cc );
+PROVIDE ( r_lc_send_pdu_unit_key = 0x4001c398 );
+PROVIDE ( r_lc_send_pdu_unsniff_req = 0x4001c894 );
+PROVIDE ( r_lc_send_pdu_vers_req = 0x4001c8b4 );
+PROVIDE ( r_lc_skip_hl_oob_req = 0x400201bc );
+PROVIDE ( r_lc_sniff_init = 0x40022cac );
+PROVIDE ( r_lc_sniff_max_slot_chg = 0x40020590 );
+PROVIDE ( r_lc_sniff_reset = 0x40022cc8 );
+PROVIDE ( r_lc_sniff_slot_unchange = 0x40021100 );
+PROVIDE ( r_lc_sniff_sub_mode = 0x400204fc );
+PROVIDE ( r_lc_sp_end = 0x400213a8 );
+PROVIDE ( r_lc_sp_fail = 0x40020470 );
+PROVIDE ( r_lc_sp_oob_tid_fail = 0x400204cc );
+PROVIDE ( r_lc_ssr_nego = 0x4002125c );
+PROVIDE ( r_lc_start = 0x4001ca28 );
+PROVIDE ( r_lc_start_enc = 0x4001fb28 );
+PROVIDE ( r_lc_start_enc_key_size = 0x4001fd9c );
+PROVIDE ( r_lc_start_key_exch = 0x4001fe10 );
+PROVIDE ( r_lc_start_lmp_to = 0x4001fae8 );
+PROVIDE ( r_lc_start_oob = 0x4001fffc );
+PROVIDE ( r_lc_start_passkey = 0x4001feac );
+PROVIDE ( r_lc_start_passkey_loop = 0x4001ff88 );
+PROVIDE ( r_lc_stop_afh_report = 0x40020184 );
+PROVIDE ( r_lc_stop_enc = 0x40020110 );
+PROVIDE ( r_lc_switch_cmp = 0x40020448 );
+PROVIDE ( r_lc_unit_key_svr = 0x400206d8 );
+PROVIDE ( r_lc_unsniff = 0x40020c50 );
+PROVIDE ( r_lc_unsniff_cmp = 0x40020810 );
+PROVIDE ( r_lc_unsniff_cont = 0x40020750 );
+PROVIDE ( r_lc_upd_to = 0x4002065c );
+PROVIDE ( r_lc_util_convert_pref_rate_to_packet_type = 0x4002f9b0 );
+PROVIDE ( r_lc_util_get_max_packet_size = 0x4002f4ac );
+PROVIDE ( r_lc_util_get_offset_clke = 0x4002f538 );
+PROVIDE ( r_lc_util_get_offset_clkn = 0x4002f51c );
+PROVIDE ( r_lc_util_set_loc_trans_coll = 0x4002f500 );
+PROVIDE ( r_lc_version = 0x40020a30 );
+PROVIDE ( r_ld_acl_active_hop_types_get = 0x40036e10 );
+PROVIDE ( r_ld_acl_afh_confirm = 0x40036d40 );
+PROVIDE ( r_ld_acl_afh_prepare = 0x40036c84 );
+PROVIDE ( r_ld_acl_afh_set = 0x40036b60 );
+PROVIDE ( r_ld_acl_allowed_tx_packet_types_set = 0x40036810 );
+PROVIDE ( r_ld_acl_bcst_rx_dec = 0x40036394 );
+PROVIDE ( r_ld_acl_bit_off_get = 0x40036b18 );
+PROVIDE ( r_ld_acl_clk_adj_set = 0x40036a00 );
+PROVIDE ( r_ld_acl_clk_off_get = 0x40036b00 );
+PROVIDE ( r_ld_acl_clk_set = 0x40036950 );
+PROVIDE ( r_ld_acl_clock_offset_get = 0x400364c0 );
+PROVIDE ( r_ld_acl_current_tx_power_get = 0x400368f0 );
+PROVIDE ( r_ld_acl_data_flush = 0x400357bc );
+PROVIDE ( r_ld_acl_data_tx = 0x4003544c );
+PROVIDE ( r_ld_acl_edr_set = 0x4003678c );
+PROVIDE ( r_ld_acl_enc_key_load = 0x40036404 );
+PROVIDE ( r_ld_acl_flow_off = 0x40035400 );
+PROVIDE ( r_ld_acl_flow_on = 0x4003541c );
+PROVIDE ( r_ld_acl_flush_timeout_get = 0x40035f9c );
+PROVIDE ( r_ld_acl_flush_timeout_set = 0x40035fe0 );
+PROVIDE ( r_ld_acl_init = 0x40034d08 );
+PROVIDE ( r_ld_acl_lmp_flush = 0x40035d80 );
+PROVIDE ( r_ld_acl_lmp_tx = 0x40035b34 );
+PROVIDE ( r_ld_acl_lsto_get = 0x400366b4 );
+PROVIDE ( r_ld_acl_lsto_set = 0x400366f8 );
+PROVIDE ( r_ld_acl_reset = 0x40034d24 );
+PROVIDE ( r_ld_acl_role_get = 0x40036b30 );
+PROVIDE ( r_ld_acl_rssi_delta_get = 0x40037028 );
+PROVIDE ( r_ld_acl_rsw_req = 0x40035e74 );
+PROVIDE ( r_ld_acl_rx_enc = 0x40036344 );
+PROVIDE ( r_ld_acl_rx_max_slot_get = 0x40036e58 );
+PROVIDE ( r_ld_acl_rx_max_slot_set = 0x40036ea0 );
+PROVIDE ( r_ld_acl_slot_offset_get = 0x4003653c );
+PROVIDE ( r_ld_acl_slot_offset_set = 0x40036658 );
+PROVIDE ( r_ld_acl_sniff = 0x4003617c );
+PROVIDE ( r_ld_acl_sniff_trans = 0x400360a8 );
+PROVIDE ( r_ld_acl_ssr_set = 0x40036274 );
+PROVIDE ( r_ld_acl_start = 0x40034ddc );
+PROVIDE ( r_ld_acl_stop = 0x4003532c );
+PROVIDE ( r_ld_acl_test_mode_set = 0x40036f24 );
+PROVIDE ( r_ld_acl_timing_accuracy_set = 0x4003673c );
+PROVIDE ( r_ld_acl_t_poll_get = 0x40036024 );
+PROVIDE ( r_ld_acl_t_poll_set = 0x40036068 );
+PROVIDE ( r_ld_acl_tx_enc = 0x400362f8 );
+PROVIDE ( r_ld_acl_unsniff = 0x400361e0 );
+PROVIDE ( r_ld_active_check = 0x4003cac4 );
+PROVIDE ( r_ld_afh_ch_assess_data_get = 0x4003caec );
+PROVIDE ( r_ld_bcst_acl_data_tx = 0x40038d3c );
+PROVIDE ( r_ld_bcst_acl_init = 0x40038bd0 );
+PROVIDE ( r_ld_bcst_acl_reset = 0x40038bdc );
+PROVIDE ( r_ld_bcst_acl_start = 0x4003882c );
+PROVIDE ( r_ld_bcst_afh_update = 0x40038f3c );
+PROVIDE ( r_ld_bcst_enc_key_load = 0x4003906c );
+PROVIDE ( r_ld_bcst_lmp_tx = 0x40038bf8 );
+PROVIDE ( r_ld_bcst_tx_enc = 0x40038ff8 );
+PROVIDE ( r_ld_bd_addr_get = 0x4003ca20 );
+PROVIDE ( r_ld_channel_assess = 0x4003c184 );
+PROVIDE ( r_ld_class_of_dev_get = 0x4003ca34 );
+PROVIDE ( r_ld_class_of_dev_set = 0x4003ca50 );
+PROVIDE ( r_ld_csb_rx_afh_update = 0x40039af4 );
+PROVIDE ( r_ld_csb_rx_init = 0x40039690 );
+PROVIDE ( r_ld_csb_rx_reset = 0x4003969c );
+PROVIDE ( r_ld_csb_rx_start = 0x4003972c );
+PROVIDE ( r_ld_csb_rx_stop = 0x40039bb8 );
+PROVIDE ( r_ld_csb_tx_afh_update = 0x4003a5fc );
+PROVIDE ( r_ld_csb_tx_clr_data = 0x4003a71c );
+PROVIDE ( r_ld_csb_tx_dis = 0x4003a5e8 );
+PROVIDE ( r_ld_csb_tx_en = 0x4003a1c0 );
+PROVIDE ( r_ld_csb_tx_init = 0x4003a0e8 );
+PROVIDE ( r_ld_csb_tx_reset = 0x4003a0f8 );
+PROVIDE ( r_ld_csb_tx_set_data = 0x4003a6c0 );
+PROVIDE ( r_ld_fm_clk_isr = 0x4003a7a8 );
+PROVIDE ( r_ld_fm_frame_isr = 0x4003a82c );
+PROVIDE ( r_ld_fm_init = 0x4003a760 );
+PROVIDE ( r_ld_fm_prog_check = 0x4003ab28 );
+PROVIDE ( r_ld_fm_prog_disable = 0x4003a984 );
+PROVIDE ( r_ld_fm_prog_enable = 0x4003a944 );
+PROVIDE ( r_ld_fm_prog_push = 0x4003a9d4 );
+PROVIDE ( r_ld_fm_reset = 0x4003a794 );
+PROVIDE ( r_ld_fm_rx_isr = 0x4003a7f4 );
+PROVIDE ( r_ld_fm_sket_isr = 0x4003a8a4 );
+PROVIDE ( r_ld_init = 0x4003c294 );
+PROVIDE ( r_ld_inq_init = 0x4003b15c );
+PROVIDE ( r_ld_inq_reset = 0x4003b168 );
+PROVIDE ( r_ld_inq_start = 0x4003b1f0 );
+PROVIDE ( r_ld_inq_stop = 0x4003b4f0 );
+PROVIDE ( r_ld_iscan_eir_get = 0x4003c118 );
+PROVIDE ( r_ld_iscan_eir_set = 0x4003bfa0 );
+PROVIDE ( r_ld_iscan_init = 0x4003b9f0 );
+PROVIDE ( r_ld_iscan_reset = 0x4003ba14 );
+PROVIDE ( r_ld_iscan_restart = 0x4003ba44 );
+PROVIDE ( r_ld_iscan_start = 0x4003bb28 );
+PROVIDE ( r_ld_iscan_stop = 0x4003bf1c );
+PROVIDE ( r_ld_iscan_tx_pwr_get = 0x4003c138 );
+PROVIDE ( r_ld_page_init = 0x4003d808 );
+PROVIDE ( r_ld_page_reset = 0x4003d814 );
+PROVIDE ( r_ld_page_start = 0x4003d848 );
+PROVIDE ( r_ld_page_stop = 0x4003da54 );
+PROVIDE ( r_ld_pca_coarse_clock_adjust = 0x4003e324 );
+PROVIDE ( r_ld_pca_init = 0x4003deb4 );
+PROVIDE ( r_ld_pca_initiate_clock_dragging = 0x4003e4ac );
+PROVIDE ( r_ld_pca_local_config = 0x4003df6c );
+PROVIDE ( r_ld_pca_mws_frame_sync = 0x4003e104 );
+PROVIDE ( r_ld_pca_mws_moment_offset_gt = 0x4003e278 );
+PROVIDE ( r_ld_pca_mws_moment_offset_lt = 0x4003e280 );
+PROVIDE ( r_ld_pca_reporting_enable = 0x4003e018 );
+PROVIDE ( r_ld_pca_reset = 0x4003df0c );
+PROVIDE ( r_ld_pca_update_target_offset = 0x4003e050 );
+PROVIDE ( r_ld_pscan_evt_handler = 0x4003f238 );
+PROVIDE ( r_ld_pscan_init = 0x4003f474 );
+PROVIDE ( r_ld_pscan_reset = 0x4003f498 );
+PROVIDE ( r_ld_pscan_restart = 0x4003f4b8 );
+PROVIDE ( r_ld_pscan_start = 0x4003f514 );
+PROVIDE ( r_ld_pscan_stop = 0x4003f618 );
+PROVIDE ( r_ld_read_clock = 0x4003c9e4 );
+PROVIDE ( r_ld_reset = 0x4003c714 );
+PROVIDE ( r_ld_sched_acl_add = 0x4003f978 );
+PROVIDE ( r_ld_sched_acl_remove = 0x4003f99c );
+PROVIDE ( r_ld_sched_compute = 0x4003f6f8 );
+PROVIDE ( r_ld_sched_init = 0x4003f7ac );
+PROVIDE ( r_ld_sched_inq_add = 0x4003f8a8 );
+PROVIDE ( r_ld_sched_inq_remove = 0x4003f8d0 );
+PROVIDE ( r_ld_sched_iscan_add = 0x4003f7e8 );
+PROVIDE ( r_ld_sched_iscan_remove = 0x4003f808 );
+PROVIDE ( r_ld_sched_page_add = 0x4003f910 );
+PROVIDE ( r_ld_sched_page_remove = 0x4003f938 );
+PROVIDE ( r_ld_sched_pscan_add = 0x4003f828 );
+PROVIDE ( r_ld_sched_pscan_remove = 0x4003f848 );
+PROVIDE ( r_ld_sched_reset = 0x4003f7d4 );
+PROVIDE ( r_ld_sched_sco_add = 0x4003fa4c );
+PROVIDE ( r_ld_sched_sco_remove = 0x4003fa9c );
+PROVIDE ( r_ld_sched_sniff_add = 0x4003f9c4 );
+PROVIDE ( r_ld_sched_sniff_remove = 0x4003fa0c );
+PROVIDE ( r_ld_sched_sscan_add = 0x4003f868 );
+PROVIDE ( r_ld_sched_sscan_remove = 0x4003f888 );
+PROVIDE ( r_ld_sco_audio_isr = 0x40037cc8 );
+PROVIDE ( r_ld_sco_data_tx = 0x40037ee8 );
+PROVIDE ( r_ld_sco_start = 0x40037110 );
+PROVIDE ( r_ld_sco_stop = 0x40037c40 );
+PROVIDE ( r_ld_sco_update = 0x40037a74 );
+PROVIDE ( r_ld_sscan_activated = 0x4004031c );
+PROVIDE ( r_ld_sscan_init = 0x400402f0 );
+PROVIDE ( r_ld_sscan_reset = 0x400402fc );
+PROVIDE ( r_ld_sscan_start = 0x40040384 );
+PROVIDE ( r_ld_strain_init = 0x400409f4 );
+PROVIDE ( r_ld_strain_reset = 0x40040a00 );
+PROVIDE ( r_ld_strain_start = 0x40040a8c );
+PROVIDE ( r_ld_strain_stop = 0x40040df0 );
+PROVIDE ( r_ld_timing_accuracy_get = 0x4003caac );
+PROVIDE ( r_ld_util_active_master_afh_map_get = 0x4004131c );
+PROVIDE ( r_ld_util_active_master_afh_map_set = 0x40041308 );
+PROVIDE ( r_ld_util_bch_create = 0x40040fcc );
+PROVIDE ( r_ld_util_fhs_pk = 0x400411c8 );
+PROVIDE ( r_ld_util_fhs_unpk = 0x40040e54 );
+PROVIDE ( r_ld_util_stp_pk = 0x400413f4 );
+PROVIDE ( r_ld_util_stp_unpk = 0x40041324 );
+PROVIDE ( r_ld_version_get = 0x4003ca6c );
+PROVIDE ( r_ld_wlcoex_set = 0x4003caf8 );
+PROVIDE ( r_llc_ch_assess_get_current_ch_map = 0x40041574 );
+PROVIDE ( r_llc_ch_assess_get_local_ch_map = 0x4004150c );
+PROVIDE ( r_llc_ch_assess_local = 0x40041494 );
+PROVIDE ( r_llc_ch_assess_merge_ch = 0x40041588 );
+PROVIDE ( r_llc_ch_assess_reass_ch = 0x400415c0 );
+PROVIDE ( r_llc_common_cmd_complete_send = 0x40044eac );
+PROVIDE ( r_llc_common_cmd_status_send = 0x40044ee0 );
+PROVIDE ( r_llc_common_enc_change_evt_send = 0x40044f6c );
+PROVIDE ( r_llc_common_enc_key_ref_comp_evt_send = 0x40044f38 );
+PROVIDE ( r_llc_common_flush_occurred_send = 0x40044f0c );
+PROVIDE ( r_llc_common_nb_of_pkt_comp_evt_send = 0x40045000 );
+PROVIDE ( r_llc_con_update_complete_send = 0x40044d68 );
+PROVIDE ( r_llc_con_update_finished = 0x4004518c );
+PROVIDE ( r_llc_con_update_ind = 0x40045038 );
+PROVIDE ( r_llc_discon_event_complete_send = 0x40044a30 );
+PROVIDE ( r_llc_end_evt_defer = 0x40046330 );
+PROVIDE ( r_llc_feats_rd_event_send = 0x40044e0c );
+PROVIDE ( r_llc_init = 0x40044778 );
+PROVIDE ( r_llc_le_con_cmp_evt_send = 0x40044a78 );
+PROVIDE ( r_llc_llcp_ch_map_update_pdu_send = 0x40043f94 );
+PROVIDE ( r_llc_llcp_con_param_req_pdu_send = 0x400442fc );
+PROVIDE ( r_llc_llcp_con_param_rsp_pdu_send = 0x40044358 );
+PROVIDE ( r_llc_llcp_con_update_pdu_send = 0x400442c4 );
+PROVIDE ( r_llc_llcp_enc_req_pdu_send = 0x40044064 );
+PROVIDE ( r_llc_llcp_enc_rsp_pdu_send = 0x40044160 );
+PROVIDE ( r_llc_llcp_feats_req_pdu_send = 0x400443b4 );
+PROVIDE ( r_llc_llcp_feats_rsp_pdu_send = 0x400443f0 );
+PROVIDE ( r_llc_llcp_get_autorize = 0x4004475c );
+PROVIDE ( r_llc_llcp_length_req_pdu_send = 0x40044574 );
+PROVIDE ( r_llc_llcp_length_rsp_pdu_send = 0x400445ac );
+PROVIDE ( r_llc_llcp_pause_enc_req_pdu_send = 0x40043fd8 );
+PROVIDE ( r_llc_llcp_pause_enc_rsp_pdu_send = 0x40044010 );
+PROVIDE ( r_llc_llcp_ping_req_pdu_send = 0x4004454c );
+PROVIDE ( r_llc_llcp_ping_rsp_pdu_send = 0x40044560 );
+PROVIDE ( r_llc_llcp_recv_handler = 0x40044678 );
+PROVIDE ( r_llc_llcp_reject_ind_pdu_send = 0x4004425c );
+PROVIDE ( r_llc_llcp_start_enc_req_pdu_send = 0x4004441c );
+PROVIDE ( r_llc_llcp_start_enc_rsp_pdu_send = 0x400441f8 );
+PROVIDE ( r_llc_llcp_terminate_ind_pdu_send = 0x400444b0 );
+PROVIDE ( r_llc_llcp_tester_send = 0x400445e4 );
+PROVIDE ( r_llc_llcp_unknown_rsp_send_pdu = 0x40044534 );
+PROVIDE ( r_llc_llcp_version_ind_pdu_send = 0x40043f6c );
+PROVIDE ( r_llc_lsto_con_update = 0x40045098 );
+PROVIDE ( r_llc_ltk_req_send = 0x40044dc0 );
+PROVIDE ( r_llc_map_update_finished = 0x40045260 );
+PROVIDE ( r_llc_map_update_ind = 0x400450f0 );
+PROVIDE ( r_llc_pdu_acl_tx_ack_defer = 0x400464dc );
+PROVIDE ( r_llc_pdu_defer = 0x40046528 );
+PROVIDE ( r_llc_pdu_llcp_tx_ack_defer = 0x400463ac );
+PROVIDE ( r_llc_reset = 0x400447b8 );
+PROVIDE ( r_llc_start = 0x400447f4 );
+PROVIDE ( r_llc_stop = 0x400449ac );
+PROVIDE ( r_llc_util_bw_mgt = 0x4004629c );
+PROVIDE ( r_llc_util_clear_operation_ptr = 0x40046234 );
+PROVIDE ( r_llc_util_dicon_procedure = 0x40046130 );
+PROVIDE ( r_llc_util_get_free_conhdl = 0x400460c8 );
+PROVIDE ( r_llc_util_get_nb_active_link = 0x40046100 );
+PROVIDE ( r_llc_util_set_auth_payl_to_margin = 0x400461f4 );
+PROVIDE ( r_llc_util_set_llcp_discard_enable = 0x400461c8 );
+PROVIDE ( r_llc_util_update_channel_map = 0x400461ac );
+PROVIDE ( r_llc_version_rd_event_send = 0x40044e60 );
+PROVIDE ( r_lld_adv_start = 0x40048b38 );
+PROVIDE ( r_lld_adv_stop = 0x40048ea0 );
+PROVIDE ( r_lld_ch_map_ind = 0x4004a2f4 );
+PROVIDE ( r_lld_con_param_req = 0x40049f0c );
+PROVIDE ( r_lld_con_param_rsp = 0x40049e00 );
+PROVIDE ( r_lld_con_start = 0x400491f8 );
+PROVIDE ( r_lld_con_stop = 0x40049fdc );
+PROVIDE ( r_lld_con_update_after_param_req = 0x40049bcc );
+PROVIDE ( r_lld_con_update_ind = 0x4004a30c );
+PROVIDE ( r_lld_con_update_req = 0x40049b60 );
+PROVIDE ( r_lld_core_reset = 0x40048a9c );
+PROVIDE ( r_lld_crypt_isr = 0x4004a324 );
+PROVIDE ( r_lld_evt_adv_create = 0x400481f4 );
+PROVIDE ( r_lld_evt_canceled = 0x400485c8 );
+PROVIDE ( r_lld_evt_channel_next = 0x40046aac );
+PROVIDE ( r_lld_evt_deffered_elt_handler = 0x400482bc );
+PROVIDE ( r_lld_evt_delete_elt_handler = 0x40046974 );
+PROVIDE ( r_lld_evt_delete_elt_push = 0x40046a3c );
+PROVIDE ( r_lld_evt_drift_compute = 0x40047670 );
+PROVIDE ( r_lld_evt_elt_delete = 0x40047538 );
+PROVIDE ( r_lld_evt_elt_insert = 0x400474c8 );
+PROVIDE ( r_lld_evt_end = 0x400483e8 );
+PROVIDE ( r_lld_evt_end_isr = 0x4004862c );
+PROVIDE ( r_lld_evt_init = 0x40046b3c );
+PROVIDE ( r_lld_evt_init_evt = 0x40046cd0 );
+PROVIDE ( r_lld_evt_move_to_master = 0x40047ba0 );
+PROVIDE ( r_lld_evt_move_to_slave = 0x40047e18 );
+PROVIDE ( r_lld_evt_prevent_stop = 0x40047adc );
+PROVIDE ( r_lld_evt_restart = 0x40046d50 );
+PROVIDE ( r_lld_evt_rx = 0x40048578 );
+PROVIDE ( r_lld_evt_rx_isr = 0x40048678 );
+PROVIDE ( r_lld_evt_scan_create = 0x40047ae8 );
+PROVIDE ( r_lld_evt_schedule = 0x40047908 );
+PROVIDE ( r_lld_evt_schedule_next = 0x400477dc );
+PROVIDE ( r_lld_evt_schedule_next_instant = 0x400476a8 );
+PROVIDE ( r_lld_evt_slave_update = 0x40048138 );
+PROVIDE ( r_lld_evt_update_create = 0x40047cd8 );
+PROVIDE ( r_lld_get_mode = 0x40049ff8 );
+PROVIDE ( r_lld_init = 0x4004873c );
+PROVIDE ( r_lld_move_to_master = 0x400499e0 );
+PROVIDE ( r_lld_move_to_slave = 0x4004a024 );
+PROVIDE ( r_lld_pdu_adv_pack = 0x4004b488 );
+PROVIDE ( r_lld_pdu_check = 0x4004ac34 );
+PROVIDE ( r_lld_pdu_data_send = 0x4004b018 );
+PROVIDE ( r_lld_pdu_data_tx_push = 0x4004aecc );
+PROVIDE ( r_lld_pdu_rx_handler = 0x4004b4d4 );
+PROVIDE ( r_lld_pdu_send_packet = 0x4004b774 );
+PROVIDE ( r_lld_pdu_tx_flush = 0x4004b414 );
+PROVIDE ( r_lld_pdu_tx_loop = 0x4004ae40 );
+PROVIDE ( r_lld_pdu_tx_prog = 0x4004b120 );
+PROVIDE ( r_lld_pdu_tx_push = 0x4004b080 );
+PROVIDE ( r_lld_ral_renew_req = 0x4004a73c );
+PROVIDE ( r_lld_scan_start = 0x40048ee0 );
+PROVIDE ( r_lld_scan_stop = 0x40049190 );
+PROVIDE ( r_lld_test_mode_rx = 0x4004a540 );
+PROVIDE ( r_lld_test_mode_tx = 0x4004a350 );
+PROVIDE ( r_lld_test_stop = 0x4004a710 );
+PROVIDE ( r_lld_util_anchor_point_move = 0x4004bacc );
+PROVIDE ( r_lld_util_compute_ce_max = 0x4004bc0c );
+PROVIDE ( r_lld_util_connection_param_set = 0x4004ba40 );
+PROVIDE ( r_lld_util_dle_set_cs_fields = 0x4004ba90 );
+PROVIDE ( r_lld_util_eff_tx_time_set = 0x4004bd88 );
+PROVIDE ( r_lld_util_elt_programmed = 0x4004bce0 );
+PROVIDE ( r_lld_util_flush_list = 0x4004bbd8 );
+PROVIDE ( r_lld_util_freq2chnl = 0x4004b9e4 );
+PROVIDE ( r_lld_util_get_bd_address = 0x4004b8ac );
+PROVIDE ( r_lld_util_get_local_offset = 0x4004ba10 );
+PROVIDE ( r_lld_util_get_peer_offset = 0x4004ba24 );
+PROVIDE ( r_lld_util_get_tx_pkt_cnt = 0x4004bd80 );
+PROVIDE ( r_lld_util_instant_get = 0x4004b890 );
+PROVIDE ( r_lld_util_instant_ongoing = 0x4004bbfc );
+PROVIDE ( r_lld_util_priority_set = 0x4004bd10 );
+PROVIDE ( r_lld_util_priority_update = 0x4004bd78 );
+PROVIDE ( r_lld_util_ral_force_rpa_renew = 0x4004b980 );
+PROVIDE ( r_lld_util_set_bd_address = 0x4004b8f8 );
+PROVIDE ( r_lld_wlcoex_set = 0x4004bd98 );
+PROVIDE ( r_llm_ble_ready = 0x4004cc34 );
+PROVIDE ( r_llm_common_cmd_complete_send = 0x4004d288 );
+PROVIDE ( r_llm_common_cmd_status_send = 0x4004d2b4 );
+PROVIDE ( r_llm_con_req_ind = 0x4004cc54 );
+PROVIDE ( r_llm_con_req_tx_cfm = 0x4004d158 );
+PROVIDE ( r_llm_create_con = 0x4004de78 );
+PROVIDE ( r_llm_encryption_done = 0x4004dff8 );
+PROVIDE ( r_llm_encryption_start = 0x4004e128 );
+PROVIDE ( r_llm_end_evt_defer = 0x4004eb6c );
+PROVIDE ( r_llm_init = 0x4004c9f8 );
+PROVIDE ( r_llm_le_adv_report_ind = 0x4004cdf4 );
+PROVIDE ( r_llm_pdu_defer = 0x4004ec48 );
+PROVIDE ( r_llm_ral_clear = 0x4004e1fc );
+PROVIDE ( r_llm_ral_dev_add = 0x4004e23c );
+PROVIDE ( r_llm_ral_dev_rm = 0x4004e3bc );
+PROVIDE ( r_llm_ral_get_rpa = 0x4004e400 );
+PROVIDE ( r_llm_ral_set_timeout = 0x4004e4a0 );
+PROVIDE ( r_llm_ral_update = 0x4004e4f8 );
+PROVIDE ( r_llm_set_adv_data = 0x4004d960 );
+PROVIDE ( r_llm_set_adv_en = 0x4004d7ec );
+PROVIDE ( r_llm_set_adv_param = 0x4004d5f4 );
+PROVIDE ( r_llm_set_scan_en = 0x4004db64 );
+PROVIDE ( r_llm_set_scan_param = 0x4004dac8 );
+PROVIDE ( r_llm_set_scan_rsp_data = 0x4004da14 );
+PROVIDE ( r_llm_test_mode_start_rx = 0x4004d534 );
+PROVIDE ( r_llm_test_mode_start_tx = 0x4004d2fc );
+PROVIDE ( r_llm_util_adv_data_update = 0x4004e8fc );
+PROVIDE ( r_llm_util_apply_bd_addr = 0x4004e868 );
+PROVIDE ( r_llm_util_bd_addr_in_ral = 0x4004eb08 );
+PROVIDE ( r_llm_util_bd_addr_in_wl = 0x4004e788 );
+PROVIDE ( r_llm_util_bd_addr_wl_position = 0x4004e720 );
+PROVIDE ( r_llm_util_bl_add = 0x4004e9ac );
+PROVIDE ( r_llm_util_bl_check = 0x4004e930 );
+PROVIDE ( r_llm_util_bl_rem = 0x4004ea70 );
+PROVIDE ( r_llm_util_check_address_validity = 0x4004e7e4 );
+PROVIDE ( r_llm_util_check_evt_mask = 0x4004e8b0 );
+PROVIDE ( r_llm_util_check_map_validity = 0x4004e800 );
+PROVIDE ( r_llm_util_get_channel_map = 0x4004e8d4 );
+PROVIDE ( r_llm_util_get_supp_features = 0x4004e8e8 );
+PROVIDE ( r_llm_util_set_public_addr = 0x4004e89c );
+PROVIDE ( r_llm_wl_clr = 0x4004dc54 );
+PROVIDE ( r_llm_wl_dev_add = 0x4004dcc0 );
+PROVIDE ( r_llm_wl_dev_add_hdl = 0x4004dd38 );
+PROVIDE ( r_llm_wl_dev_rem = 0x4004dcfc );
+PROVIDE ( r_llm_wl_dev_rem_hdl = 0x4004dde0 );
+PROVIDE ( r_lm_acl_disc = 0x4004f148 );
+PROVIDE ( r_LM_AddSniff = 0x40022d20 );
+PROVIDE ( r_lm_add_sync = 0x40051358 );
+PROVIDE ( r_lm_afh_activate_timer = 0x4004f444 );
+PROVIDE ( r_lm_afh_ch_ass_en_get = 0x4004f3f8 );
+PROVIDE ( r_lm_afh_host_ch_class_get = 0x4004f410 );
+PROVIDE ( r_lm_afh_master_ch_map_get = 0x4004f43c );
+PROVIDE ( r_lm_afh_peer_ch_class_set = 0x4004f418 );
+PROVIDE ( r_lm_check_active_sync = 0x40051334 );
+PROVIDE ( r_LM_CheckEdrFeatureRequest = 0x4002f90c );
+PROVIDE ( r_LM_CheckSwitchInstant = 0x4002f8c0 );
+PROVIDE ( r_lm_check_sync_hl_rsp = 0x4005169c );
+PROVIDE ( r_lm_clk_adj_ack_pending_clear = 0x4004f514 );
+PROVIDE ( r_lm_clk_adj_instant_pending_set = 0x4004f4d8 );
+PROVIDE ( r_LM_ComputePacketType = 0x4002f554 );
+PROVIDE ( r_LM_ComputeSniffSubRate = 0x400233ac );
+PROVIDE ( r_lm_debug_key_compare_192 = 0x4004f3a8 );
+PROVIDE ( r_lm_debug_key_compare_256 = 0x4004f3d0 );
+PROVIDE ( r_lm_dhkey_calc_init = 0x40013234 );
+PROVIDE ( r_lm_dhkey_compare = 0x400132d8 );
+PROVIDE ( r_lm_dut_mode_en_get = 0x4004f3ec );
+PROVIDE ( r_LM_ExtractMaxEncKeySize = 0x4001aca4 );
+PROVIDE ( r_lm_f1 = 0x40012bb8 );
+PROVIDE ( r_lm_f2 = 0x40012cfc );
+PROVIDE ( r_lm_f3 = 0x40013050 );
+PROVIDE ( r_lm_g = 0x40012f90 );
+PROVIDE ( r_LM_GetAFHSwitchInstant = 0x4002f86c );
+PROVIDE ( r_lm_get_auth_en = 0x4004f1ac );
+PROVIDE ( r_lm_get_common_pkt_types = 0x4002fa1c );
+PROVIDE ( r_LM_GetConnectionAcceptTimeout = 0x4004f1f4 );
+PROVIDE ( r_LM_GetFeature = 0x4002f924 );
+PROVIDE ( r_LM_GetLinkTimeout = 0x400233ec );
+PROVIDE ( r_LM_GetLocalNameSeg = 0x4004f200 );
+PROVIDE ( r_lm_get_loopback_mode = 0x4004f248 );
+PROVIDE ( r_LM_GetMasterEncKeySize = 0x4001b29c );
+PROVIDE ( r_LM_GetMasterEncRand = 0x4001b288 );
+PROVIDE ( r_LM_GetMasterKey = 0x4001b260 );
+PROVIDE ( r_LM_GetMasterKeyRand = 0x4001b274 );
+PROVIDE ( r_lm_get_min_sync_intv = 0x400517a8 );
+PROVIDE ( r_lm_get_nb_acl = 0x4004ef9c );
+PROVIDE ( r_lm_get_nb_sync_link = 0x4005179c );
+PROVIDE ( r_lm_get_nonce = 0x400131c4 );
+PROVIDE ( r_lm_get_oob_local_commit = 0x4004f374 );
+PROVIDE ( r_lm_get_oob_local_data_192 = 0x4004f2d4 );
+PROVIDE ( r_lm_get_oob_local_data_256 = 0x4004f318 );
+PROVIDE ( r_LM_GetPINType = 0x4004f1e8 );
+PROVIDE ( r_lm_get_priv_key_192 = 0x4004f278 );
+PROVIDE ( r_lm_get_priv_key_256 = 0x4004f2b8 );
+PROVIDE ( r_lm_get_pub_key_192 = 0x4004f258 );
+PROVIDE ( r_lm_get_pub_key_256 = 0x4004f298 );
+PROVIDE ( r_LM_GetQoSParam = 0x4002f6e0 );
+PROVIDE ( r_lm_get_sec_con_host_supp = 0x4004f1d4 );
+PROVIDE ( r_LM_GetSniffSubratingParam = 0x4002325c );
+PROVIDE ( r_lm_get_sp_en = 0x4004f1c0 );
+PROVIDE ( r_LM_GetSwitchInstant = 0x4002f7f8 );
+PROVIDE ( r_lm_get_synchdl = 0x4005175c );
+PROVIDE ( r_lm_get_sync_param = 0x400503b4 );
+PROVIDE ( r_lm_init = 0x4004ed34 );
+PROVIDE ( r_lm_init_sync = 0x400512d8 );
+PROVIDE ( r_lm_is_acl_con = 0x4004f47c );
+PROVIDE ( r_lm_is_acl_con_role = 0x4004f49c );
+PROVIDE ( r_lm_is_clk_adj_ack_pending = 0x4004f4e8 );
+PROVIDE ( r_lm_is_clk_adj_instant_pending = 0x4004f4c8 );
+PROVIDE ( r_lm_local_ext_fr_configured = 0x4004f540 );
+PROVIDE ( r_lm_look_for_stored_link_key = 0x4002f948 );
+PROVIDE ( r_lm_look_for_sync = 0x40051774 );
+PROVIDE ( r_lm_lt_addr_alloc = 0x4004ef1c );
+PROVIDE ( r_lm_lt_addr_free = 0x4004ef74 );
+PROVIDE ( r_lm_lt_addr_reserve = 0x4004ef48 );
+PROVIDE ( r_LM_MakeCof = 0x4002f84c );
+PROVIDE ( r_LM_MakeRandVec = 0x400112d8 );
+PROVIDE ( r_lm_master_clk_adj_req_handler = 0x40054180 );
+PROVIDE ( r_LM_MaxSlot = 0x4002f694 );
+PROVIDE ( r_lm_modif_sync = 0x40051578 );
+PROVIDE ( r_lm_n_is_zero = 0x40012170 );
+PROVIDE ( r_lm_num_clk_adj_ack_pending_set = 0x4004f500 );
+PROVIDE ( r_lm_oob_f1 = 0x40012e54 );
+PROVIDE ( r_lm_pca_sscan_link_get = 0x4004f560 );
+PROVIDE ( r_lm_pca_sscan_link_set = 0x4004f550 );
+PROVIDE ( r_lmp_pack = 0x4001135c );
+PROVIDE ( r_lmp_unpack = 0x4001149c );
+PROVIDE ( r_lm_read_features = 0x4004f0d8 );
+PROVIDE ( r_LM_RemoveSniff = 0x40023124 );
+PROVIDE ( r_LM_RemoveSniffSubrating = 0x400233c4 );
+PROVIDE ( r_lm_remove_sync = 0x400517c8 );
+PROVIDE ( r_lm_reset_sync = 0x40051304 );
+PROVIDE ( r_lm_role_switch_finished = 0x4004f028 );
+PROVIDE ( r_lm_role_switch_start = 0x4004efe0 );
+PROVIDE ( r_lm_sco_nego_end = 0x40051828 );
+PROVIDE ( r_LM_SniffSubrateNegoRequired = 0x40023334 );
+PROVIDE ( r_LM_SniffSubratingHlReq = 0x40023154 );
+PROVIDE ( r_LM_SniffSubratingPeerReq = 0x400231dc );
+PROVIDE ( r_lm_sp_debug_mode_get = 0x4004f398 );
+PROVIDE ( r_lm_sp_n192_convert_wnaf = 0x400123c0 );
+PROVIDE ( r_lm_sp_n_one = 0x400123a4 );
+PROVIDE ( r_lm_sp_p192_add = 0x40012828 );
+PROVIDE ( r_lm_sp_p192_dbl = 0x4001268c );
+PROVIDE ( r_lm_sp_p192_invert = 0x40012b6c );
+PROVIDE ( r_lm_sp_p192_point_jacobian_to_affine = 0x40012468 );
+PROVIDE ( r_lm_sp_p192_points_jacobian_to_affine = 0x400124e4 );
+PROVIDE ( r_lm_sp_p192_point_to_inf = 0x40012458 );
+PROVIDE ( r_lm_sp_pre_compute_points = 0x40012640 );
+PROVIDE ( r_lm_sp_sha256_calculate = 0x400121a0 );
+PROVIDE ( r_LM_SuppressAclPacket = 0x4002f658 );
+PROVIDE ( r_lm_sync_flow_ctrl_en_get = 0x4004f404 );
+PROVIDE ( r_LM_UpdateAclEdrPacketType = 0x4002f5d8 );
+PROVIDE ( r_LM_UpdateAclPacketType = 0x4002f584 );
+PROVIDE ( r_modules_funcs = 0x3ffafd6c );
+PROVIDE ( r_modules_funcs_p = 0x3ffafd68 );
+PROVIDE ( r_nvds_del = 0x400544c4 );
+PROVIDE ( r_nvds_get = 0x40054488 );
+PROVIDE ( r_nvds_init = 0x40054410 );
+PROVIDE ( r_nvds_lock = 0x400544fc );
+PROVIDE ( r_nvds_put = 0x40054534 );
+PROVIDE ( rom_abs_temp = 0x400054f0 );
+PROVIDE ( rom_bb_bss_bw_40_en = 0x4000401c );
+PROVIDE ( rom_bb_bss_cbw40_dig = 0x40003bac );
+PROVIDE ( rom_bb_rx_ht20_cen_bcov_en = 0x40003734 );
+PROVIDE ( rom_bb_tx_ht20_cen = 0x40003760 );
+PROVIDE ( rom_bb_wdg_test_en = 0x40003b70 );
+PROVIDE ( rom_cbw2040_cfg = 0x400040b0 );
+PROVIDE ( rom_check_noise_floor = 0x40003c78 );
+PROVIDE ( rom_chip_i2c_readReg = 0x40004110 );
+PROVIDE ( rom_chip_i2c_writeReg = 0x40004168 );
+PROVIDE ( rom_chip_v7_bt_init = 0x40004d8c );
+PROVIDE ( rom_chip_v7_rx_init = 0x40004cec );
+PROVIDE ( rom_chip_v7_rx_rifs_en = 0x40003d90 );
+PROVIDE ( rom_chip_v7_tx_init = 0x40004d18 );
+PROVIDE ( rom_clk_force_on_vit = 0x40003710 );
+PROVIDE ( rom_correct_rf_ana_gain = 0x400062a8 );
+PROVIDE ( rom_dc_iq_est = 0x400055c8 );
+PROVIDE ( rom_disable_agc = 0x40002fa4 );
+PROVIDE ( rom_enable_agc = 0x40002fcc );
+PROVIDE ( rom_en_pwdet = 0x4000506c );
+PROVIDE ( rom_gen_rx_gain_table = 0x40003e3c );
+PROVIDE ( rom_get_data_sat = 0x4000312c );
+PROVIDE ( rom_get_fm_sar_dout = 0x40005204 );
+PROVIDE ( rom_get_power_db = 0x40005fc8 );
+PROVIDE ( rom_get_pwctrl_correct = 0x400065d4 );
+PROVIDE ( rom_get_rfcal_rxiq_data = 0x40005bbc );
+PROVIDE ( rom_get_rf_gain_qdb = 0x40006290 );
+PROVIDE ( rom_get_sar_dout = 0x40006564 );
+PROVIDE ( rom_i2c_readReg = 0x40004148 );
+PROVIDE ( rom_i2c_readReg_Mask = 0x400041c0 );
+PROVIDE ( rom_i2c_writeReg = 0x400041a4 );
+PROVIDE ( rom_i2c_writeReg_Mask = 0x400041fc );
+PROVIDE ( rom_index_to_txbbgain = 0x40004df8 );
+PROVIDE ( rom_iq_est_disable = 0x40005590 );
+PROVIDE ( rom_iq_est_enable = 0x40005514 );
+PROVIDE ( rom_linear_to_db = 0x40005f64 );
+PROVIDE ( rom_loopback_mode_en = 0x400030f8 );
+PROVIDE ( rom_main = 0x400076c4 );
+PROVIDE ( rom_meas_tone_pwr_db = 0x40006004 );
+PROVIDE ( rom_mhz2ieee = 0x4000404c );
+PROVIDE ( rom_noise_floor_auto_set = 0x40003bdc );
+PROVIDE ( rom_pbus_debugmode = 0x40004458 );
+PROVIDE ( rom_pbus_force_mode = 0x40004270 );
+PROVIDE ( rom_pbus_force_test = 0x400043c0 );
+PROVIDE ( rom_pbus_rd = 0x40004414 );
+PROVIDE ( rom_pbus_rd_addr = 0x40004334 );
+PROVIDE ( rom_pbus_rd_shift = 0x40004374 );
+PROVIDE ( rom_pbus_rx_dco_cal = 0x40005620 );
+PROVIDE ( rom_pbus_set_dco = 0x40004638 );
+PROVIDE ( rom_pbus_set_rxgain = 0x40004480 );
+PROVIDE ( rom_pbus_workmode = 0x4000446c );
+PROVIDE ( rom_pbus_xpd_rx_off = 0x40004508 );
+PROVIDE ( rom_pbus_xpd_rx_on = 0x4000453c );
+PROVIDE ( rom_pbus_xpd_tx_off = 0x40004590 );
+PROVIDE ( rom_pbus_xpd_tx_on = 0x400045e0 );
+PROVIDE ( rom_phy_disable_agc = 0x40002f6c );
+PROVIDE ( rom_phy_disable_cca = 0x40003000 );
+PROVIDE ( rom_phy_enable_agc = 0x40002f88 );
+PROVIDE ( rom_phy_enable_cca = 0x4000302c );
+PROVIDE ( rom_phy_freq_correct = 0x40004b44 );
+PROVIDE ( rom_phyFuns = 0x3ffae0c0 );
+PROVIDE ( rom_phy_get_noisefloor = 0x40003c2c );
+PROVIDE ( rom_phy_get_vdd33 = 0x4000642c );
+PROVIDE ( rom_pow_usr = 0x40003044 );
+PROVIDE ( rom_read_sar_dout = 0x400051c0 );
+PROVIDE ( rom_restart_cal = 0x400046e0 );
+PROVIDE ( rom_rfcal_pwrctrl = 0x40006058 );
+PROVIDE ( rom_rfcal_rxiq = 0x40005b4c );
+PROVIDE ( rom_rfcal_txcap = 0x40005dec );
+PROVIDE ( rom_rfpll_reset = 0x40004680 );
+PROVIDE ( rom_rfpll_set_freq = 0x400047f8 );
+PROVIDE ( rom_rtc_mem_backup = 0x40003db4 );
+PROVIDE ( rom_rtc_mem_recovery = 0x40003df4 );
+PROVIDE ( rom_rx_gain_force = 0x4000351c );
+PROVIDE ( rom_rxiq_cover_mg_mp = 0x40005a68 );
+PROVIDE ( rom_rxiq_get_mis = 0x400058e4 );
+PROVIDE ( rom_rxiq_set_reg = 0x40005a00 );
+PROVIDE ( rom_set_cal_rxdc = 0x400030b8 );
+PROVIDE ( rom_set_chan_cal_interp = 0x40005ce0 );
+PROVIDE ( rom_set_channel_freq = 0x40004880 );
+PROVIDE ( rom_set_loopback_gain = 0x40003060 );
+PROVIDE ( rom_set_noise_floor = 0x40003d48 );
+PROVIDE ( rom_set_pbus_mem = 0x400031a4 );
+PROVIDE ( rom_set_rf_freq_offset = 0x40004ca8 );
+PROVIDE ( rom_set_rxclk_en = 0x40003594 );
+PROVIDE ( rom_set_txcap_reg = 0x40005d50 );
+PROVIDE ( rom_set_txclk_en = 0x40003564 );
+PROVIDE ( rom_spur_coef_cfg = 0x40003ac8 );
+PROVIDE ( rom_spur_reg_write_one_tone = 0x400037f0 );
+PROVIDE ( rom_start_tx_tone = 0x400036b4 );
+PROVIDE ( rom_start_tx_tone_step = 0x400035d0 );
+PROVIDE ( rom_stop_tx_tone = 0x40003f98 );
+PROVIDE ( _rom_store = 0x4000d66c );
+PROVIDE ( _rom_store_table = 0x4000d4f8 );
+PROVIDE ( rom_target_power_add_backoff = 0x40006268 );
+PROVIDE ( rom_tx_atten_set_interp = 0x400061cc );
+PROVIDE ( rom_txbbgain_to_index = 0x40004dc0 );
+PROVIDE ( rom_txcal_work_mode = 0x4000510c );
+PROVIDE ( rom_txdc_cal_init = 0x40004e10 );
+PROVIDE ( rom_txdc_cal_v70 = 0x40004ea4 );
+PROVIDE ( rom_txiq_cover = 0x4000538c );
+PROVIDE ( rom_txiq_get_mis_pwr = 0x400052dc );
+PROVIDE ( rom_txiq_set_reg = 0x40005154 );
+PROVIDE ( rom_tx_pwctrl_bg_init = 0x4000662c );
+PROVIDE ( rom_txtone_linear_pwr = 0x40005290 );
+PROVIDE ( rom_wait_rfpll_cal_end = 0x400047a8 );
+PROVIDE ( rom_write_gain_mem = 0x4000348c );
+PROVIDE ( rom_write_rfpll_sdm = 0x40004740 );
+PROVIDE ( roundup2 = 0x4000ab7c );
+PROVIDE ( r_plf_funcs_p = 0x3ffb8360 );
+PROVIDE ( r_rf_rw_bt_init = 0x40054868 );
+PROVIDE ( r_rf_rw_init = 0x40054b0c );
+PROVIDE ( r_rf_rw_le_init = 0x400549d0 );
+PROVIDE ( r_rwble_activity_ongoing_check = 0x40054d8c );
+PROVIDE ( r_rwble_init = 0x40054bf4 );
+PROVIDE ( r_rwble_isr = 0x40054e08 );
+PROVIDE ( r_rwble_reset = 0x40054ce8 );
+PROVIDE ( r_rwble_sleep_check = 0x40054d78 );
+PROVIDE ( r_rwble_version = 0x40054dac );
+PROVIDE ( r_rwbt_init = 0x40055160 );
+PROVIDE ( r_rwbt_isr = 0x40055248 );
+PROVIDE ( r_rwbt_reset = 0x400551bc );
+PROVIDE ( r_rwbt_sleep_check = 0x4005577c );
+PROVIDE ( r_rwbt_sleep_enter = 0x400557a4 );
+PROVIDE ( r_rwbt_sleep_wakeup = 0x400557fc );
+PROVIDE ( r_rwbt_sleep_wakeup_end = 0x400558cc );
+PROVIDE ( r_rwbt_version = 0x4005520c );
+PROVIDE ( r_rwip_assert_err = 0x40055f88 );
+PROVIDE ( r_rwip_check_wakeup_boundary = 0x400558fc );
+PROVIDE ( r_rwip_ext_wakeup_enable = 0x40055f3c );
+PROVIDE ( r_rwip_init = 0x4005595c );
+PROVIDE ( r_rwip_pca_clock_dragging_only = 0x40055f48 );
+PROVIDE ( r_rwip_prevent_sleep_clear = 0x40055ec8 );
+PROVIDE ( r_rwip_prevent_sleep_set = 0x40055e64 );
+PROVIDE ( r_rwip_reset = 0x40055ab8 );
+PROVIDE ( r_rwip_schedule = 0x40055b38 );
+PROVIDE ( r_rwip_sleep = 0x40055b5c );
+PROVIDE ( r_rwip_sleep_enable = 0x40055f30 );
+PROVIDE ( r_rwip_version = 0x40055b20 );
+PROVIDE ( r_rwip_wakeup = 0x40055dc4 );
+PROVIDE ( r_rwip_wakeup_delay_set = 0x40055e4c );
+PROVIDE ( r_rwip_wakeup_end = 0x40055e18 );
+PROVIDE ( r_rwip_wlcoex_set = 0x40055f60 );
+PROVIDE ( r_SHA_256 = 0x40013a90 );
+PROVIDE ( rtc_boot_control = 0x4000821c );
+PROVIDE ( rtc_get_reset_reason = 0x400081d4 );
+PROVIDE ( rtc_get_wakeup_cause = 0x400081f4 );
+PROVIDE ( rtc_select_apb_bridge = 0x40008288 );
+PROVIDE ( rwip_coex_cfg = 0x3ff9914c );
+PROVIDE ( rwip_priority = 0x3ff99159 );
+PROVIDE ( rwip_rf = 0x3ffbdb28 );
+PROVIDE ( rwip_rf_p_get = 0x400558f4 );
+PROVIDE ( r_XorKey = 0x400112c0 );
+PROVIDE ( sbrk = 0x400017f4 );
+PROVIDE ( _sbrk_r = 0x4000bce4 );
+PROVIDE ( scanf = 0x40058760 );
+PROVIDE ( _scanf_chars = 0x40058384 );
+PROVIDE ( _scanf_float = 0x4000bf18 );
+PROVIDE ( _scanf_i = 0x4005845c );
+PROVIDE ( _scanf_r = 0x4005879c );
+PROVIDE ( __sccl = 0x4000c498 );
+PROVIDE ( __sclose = 0x400011b8 );
+PROVIDE ( SelectSpiFunction = 0x40061f84 );
+PROVIDE ( SelectSpiQIO = 0x40061ddc );
+PROVIDE ( SendMsg = 0x40009384 );
+PROVIDE ( send_packet = 0x40009340 );
+PROVIDE ( __seofread = 0x40001148 );
+PROVIDE ( setjmp = 0x40056268 );
+PROVIDE ( setlocale = 0x40059568 );
+PROVIDE ( _setlocale_r = 0x4005950c );
+PROVIDE ( set_rtc_memory_crc = 0x40008208 );
+PROVIDE ( SetSpiDrvs = 0x40061e78 );
+PROVIDE ( __sf_fake_stderr = 0x3ff96458 );
+PROVIDE ( __sf_fake_stdin = 0x3ff96498 );
+PROVIDE ( __sf_fake_stdout = 0x3ff96478 );
+PROVIDE ( __sflush_r = 0x400591e0 );
+PROVIDE ( __sfmoreglue = 0x40001dc8 );
+PROVIDE ( __sfp = 0x40001e90 );
+PROVIDE ( __sfp_lock_acquire = 0x40001e08 );
+PROVIDE ( __sfp_lock_release = 0x40001e14 );
+PROVIDE ( __sfputs_r = 0x40057790 );
+PROVIDE ( __sfvwrite_r = 0x4005893c );
+PROVIDE ( sha1_prf = 0x40060ae8 );
+PROVIDE ( sha1_vector = 0x40060b64 );
+PROVIDE ( sha256_prf = 0x40060d70 );
+PROVIDE ( sha256_vector = 0x40060e08 );
+PROVIDE ( sha_blk_bits = 0x3ff99290 );
+PROVIDE ( sha_blk_bits_bytes = 0x3ff99288 );
+PROVIDE ( sha_blk_hash_bytes = 0x3ff9928c );
+PROVIDE ( sig_matrix = 0x3ffae293 );
+PROVIDE ( __sinit = 0x40001e38 );
+PROVIDE ( __sinit_lock_acquire = 0x40001e20 );
+PROVIDE ( __sinit_lock_release = 0x40001e2c );
+PROVIDE ( sip_after_tx_complete = 0x4000b358 );
+PROVIDE ( sip_alloc_to_host_evt = 0x4000ab9c );
+PROVIDE ( sip_get_ptr = 0x4000b34c );
+PROVIDE ( sip_get_state = 0x4000ae2c );
+PROVIDE ( sip_init_attach = 0x4000ae58 );
+PROVIDE ( sip_install_rx_ctrl_cb = 0x4000ae10 );
+PROVIDE ( sip_install_rx_data_cb = 0x4000ae20 );
+PROVIDE ( sip_is_active = 0x4000b3c0 );
+PROVIDE ( sip_post_init = 0x4000aed8 );
+PROVIDE ( sip_reclaim_from_host_cmd = 0x4000adbc );
+PROVIDE ( sip_reclaim_tx_data_pkt = 0x4000ad5c );
+PROVIDE ( siprintf = 0x40056c08 );
+PROVIDE ( _siprintf_r = 0x40056bbc );
+PROVIDE ( sip_send = 0x4000af54 );
+PROVIDE ( sip_to_host_chain_append = 0x4000aef8 );
+PROVIDE ( sip_to_host_evt_send_done = 0x4000ac04 );
+PROVIDE ( siscanf = 0x400587d0 );
+PROVIDE ( _siscanf_r = 0x40058830 );
+PROVIDE ( slc_add_credits = 0x4000baf4 );
+PROVIDE ( slc_enable = 0x4000b64c );
+PROVIDE ( slc_from_host_chain_fetch = 0x4000b7e8 );
+PROVIDE ( slc_from_host_chain_recycle = 0x4000bb10 );
+PROVIDE ( slc_has_pkt_to_host = 0x4000b5fc );
+PROVIDE ( slc_init_attach = 0x4000b918 );
+PROVIDE ( slc_init_credit = 0x4000badc );
+PROVIDE ( slc_reattach = 0x4000b62c );
+PROVIDE ( slc_send_to_host_chain = 0x4000b6a0 );
+PROVIDE ( slc_set_host_io_max_window = 0x4000b89c );
+PROVIDE ( slc_to_host_chain_recycle = 0x4000b758 );
+PROVIDE ( __smakebuf_r = 0x40059108 );
+PROVIDE ( sniprintf = 0x40056b4c );
+PROVIDE ( _sniprintf_r = 0x40056ae4 );
+PROVIDE ( snprintf = 0x40056b4c );
+PROVIDE ( _snprintf_r = 0x40056ae4 );
+PROVIDE ( software_reset = 0x4000824c );
+PROVIDE ( software_reset_cpu = 0x40008264 );
+PROVIDE ( specialModP256 = 0x4001600c );
+PROVIDE ( spi_cache_sram_init = 0x400626e4 );
+PROVIDE ( SPIClkConfig = 0x40062bc8 );
+PROVIDE ( SPI_Common_Command = 0x4006246c );
+PROVIDE ( spi_dummy_len_fix = 0x40061d90 );
+PROVIDE ( SPI_Encrypt_Write = 0x40062e78 );
+PROVIDE ( SPIEraseArea = 0x400631ac );
+PROVIDE ( SPIEraseBlock = 0x40062c4c );
+PROVIDE ( SPIEraseChip = 0x40062c14 );
+PROVIDE ( SPIEraseSector = 0x40062ccc );
+PROVIDE ( spi_flash_attach = 0x40062a6c );
+PROVIDE ( SPILock = 0x400628f0 );
+PROVIDE ( SPIMasterReadModeCnfig = 0x40062b64 );
+PROVIDE ( spi_modes = 0x3ff99270 );
+PROVIDE ( SPIParamCfg = 0x40063238 );
+PROVIDE ( SPI_Prepare_Encrypt_Data = 0x40062e1c );
+PROVIDE ( SPIRead = 0x40062ed8 );
+PROVIDE ( SPIReadModeCnfig = 0x40062944 );
+/* This is static function, but can be used, not generated by script*/
+PROVIDE ( SPI_read_status = 0x4006226c );
+/* This is static function, but can be used, not generated by script*/
+PROVIDE ( SPI_read_status_high = 0x40062448 );
+PROVIDE ( SPIUnlock = 0x400628b0 );
+PROVIDE ( SPI_user_command_read = 0x400621b0 );
+PROVIDE ( spi_w25q16 = 0x3ffae270 );
+PROVIDE ( SPIWrite = 0x40062d50 );
+/* This is static function, but can be used, not generated by script*/
+PROVIDE ( SPI_write_enable = 0x40062320 );
+PROVIDE ( SPI_Write_Encrypt_Disable = 0x40062e60 );
+PROVIDE ( SPI_Write_Encrypt_Enable = 0x40062df4 );
+/* This is static function, but can be used, not generated by script*/
+PROVIDE ( SPI_write_status = 0x400622f0 );
+PROVIDE ( sprintf = 0x40056c08 );
+PROVIDE ( _sprintf_r = 0x40056bbc );
+PROVIDE ( __sprint_r = 0x400577e4 );
+PROVIDE ( srand = 0x40001004 );
+PROVIDE ( __sread = 0x40001118 );
+PROVIDE ( __srefill_r = 0x400593d4 );
+PROVIDE ( sscanf = 0x400587d0 );
+PROVIDE ( _sscanf_r = 0x40058830 );
+PROVIDE ( __sseek = 0x40001184 );
+PROVIDE ( __ssprint_r = 0x40056ff8 );
+PROVIDE ( __ssputs_r = 0x40056f2c );
+PROVIDE ( __ssrefill_r = 0x40057fec );
+PROVIDE ( __ssvfiscanf_r = 0x4005802c );
+PROVIDE ( __ssvfscanf_r = 0x4005802c );
+PROVIDE ( __stack = 0x3ffe3f20 );
+PROVIDE ( __stack_app = 0x3ffe7e30 );
+PROVIDE ( _stack_sentry = 0x3ffe1320 );
+PROVIDE ( _stack_sentry_app = 0x3ffe5230 );
+PROVIDE ( _start = 0x40000704 );
+PROVIDE ( start_tb_console = 0x4005a980 );
+PROVIDE ( _stat_r = 0x4000bcb4 );
+PROVIDE ( _stext = 0x40000560 );
+PROVIDE ( strcasecmp = 0x400011cc );
+PROVIDE ( strcasestr = 0x40001210 );
+PROVIDE ( strcat = 0x4000c518 );
+PROVIDE ( strchr = 0x4000c53c );
+PROVIDE ( strcmp = 0x40001274 );
+PROVIDE ( strcoll = 0x40001398 );
+PROVIDE ( strcpy = 0x400013ac );
+PROVIDE ( strcspn = 0x4000c558 );
+PROVIDE ( strdup = 0x4000143c );
+PROVIDE ( _strdup_r = 0x40001450 );
+PROVIDE ( strftime = 0x40059ab4 );
+PROVIDE ( strlcat = 0x40001470 );
+PROVIDE ( strlcpy = 0x4000c584 );
+PROVIDE ( strlen = 0x400014c0 );
+PROVIDE ( strlwr = 0x40001524 );
+PROVIDE ( strncasecmp = 0x40001550 );
+PROVIDE ( strncat = 0x4000c5c4 );
+PROVIDE ( strncmp = 0x4000c5f4 );
+PROVIDE ( strncpy = 0x400015d4 );
+PROVIDE ( strndup = 0x400016b0 );
+PROVIDE ( _strndup_r = 0x400016c4 );
+PROVIDE ( strnlen = 0x4000c628 );
+PROVIDE ( strrchr = 0x40001708 );
+PROVIDE ( strsep = 0x40001734 );
+PROVIDE ( strspn = 0x4000c648 );
+PROVIDE ( strstr = 0x4000c674 );
+PROVIDE ( __strtok_r = 0x4000c6a8 );
+PROVIDE ( strtok_r = 0x4000c70c );
+PROVIDE ( strtol = 0x4005681c );
+PROVIDE ( _strtol_r = 0x40056714 );
+PROVIDE ( strtoul = 0x4005692c );
+PROVIDE ( _strtoul_r = 0x40056834 );
+PROVIDE ( strupr = 0x4000174c );
+PROVIDE ( __subdf3 = 0x400026e4 );
+PROVIDE ( __submore = 0x40058f3c );
+PROVIDE ( __subsf3 = 0x400021d0 );
+PROVIDE ( SubtractBigHex256 = 0x40015bcc );
+PROVIDE ( SubtractBigHexMod256 = 0x40015e8c );
+PROVIDE ( SubtractBigHexUint32_256 = 0x40015f8c );
+PROVIDE ( SubtractFromSelfBigHex256 = 0x40015c20 );
+PROVIDE ( SubtractFromSelfBigHexSign256 = 0x40015dc8 );
+PROVIDE ( __subvdi3 = 0x40002d20 );
+PROVIDE ( __subvsi3 = 0x40002cf8 );
+PROVIDE ( _sungetc_r = 0x40057f6c );
+PROVIDE ( _svfiprintf_r = 0x40057100 );
+PROVIDE ( __svfiscanf_r = 0x40057b08 );
+PROVIDE ( _svfprintf_r = 0x40057100 );
+PROVIDE ( __svfscanf = 0x40057f04 );
+PROVIDE ( __svfscanf_r = 0x40057b08 );
+PROVIDE ( __swbuf = 0x40058cb4 );
+PROVIDE ( __swbuf_r = 0x40058bec );
+PROVIDE ( __swrite = 0x40001150 );
+PROVIDE ( __swsetup_r = 0x40058cc8 );
+PROVIDE ( sw_to_hw = 0x3ffb8d40 );
+PROVIDE ( _SyscallException = 0x400007cf );
+PROVIDE ( syscall_table_ptr_app = 0x3ffae020 );
+PROVIDE ( syscall_table_ptr_pro = 0x3ffae024 );
+PROVIDE ( _system_r = 0x4000bc10 );
+PROVIDE ( tdefl_compress = 0x400600bc );
+PROVIDE ( tdefl_compress_buffer = 0x400607f4 );
+PROVIDE ( tdefl_compress_mem_to_mem = 0x40060900 );
+PROVIDE ( tdefl_compress_mem_to_output = 0x400608e0 );
+PROVIDE ( tdefl_get_adler32 = 0x400608d8 );
+PROVIDE ( tdefl_get_prev_return_status = 0x400608d0 );
+PROVIDE ( tdefl_init = 0x40060810 );
+PROVIDE ( tdefl_write_image_to_png_file_in_memory = 0x4006091c );
+PROVIDE ( tdefl_write_image_to_png_file_in_memory_ex = 0x40060910 );
+PROVIDE ( time = 0x40001844 );
+PROVIDE ( __time_load_locale = 0x4000183c );
+PROVIDE ( times = 0x40001808 );
+PROVIDE ( _times_r = 0x4000bc40 );
+PROVIDE ( _timezone = 0x3ffae0a0 );
+PROVIDE ( tinfl_decompress = 0x4005ef30 );
+PROVIDE ( tinfl_decompress_mem_to_callback = 0x40060090 );
+PROVIDE ( tinfl_decompress_mem_to_mem = 0x40060050 );
+PROVIDE ( toascii = 0x4000c720 );
+PROVIDE ( tolower = 0x40001868 );
+PROVIDE ( toupper = 0x40001884 );
+PROVIDE ( __truncdfsf2 = 0x40002b90 );
+PROVIDE ( __tzcalc_limits = 0x400018a0 );
+PROVIDE ( __tz_lock = 0x40001a04 );
+PROVIDE ( _tzname = 0x3ffae030 );
+PROVIDE ( tzset = 0x40001a1c );
+PROVIDE ( _tzset_r = 0x40001a28 );
+PROVIDE ( __tz_unlock = 0x40001a10 );
+PROVIDE ( uartAttach = 0x40008fd0 );
+PROVIDE ( uart_baudrate_detect = 0x40009034 );
+PROVIDE ( uart_buff_switch = 0x400093c0 );
+PROVIDE ( UartConnCheck = 0x40008738 );
+PROVIDE ( UartConnectProc = 0x40008a04 );
+PROVIDE ( UartDev = 0x3ffe019c );
+PROVIDE ( uart_div_modify = 0x400090cc );
+PROVIDE ( UartDwnLdProc = 0x40008ce8 );
+PROVIDE ( UartGetCmdLn = 0x40009564 );
+PROVIDE ( Uart_Init = 0x40009120 );
+PROVIDE ( UartRegReadProc = 0x40008a58 );
+PROVIDE ( UartRegWriteProc = 0x40008a14 );
+PROVIDE ( uart_rx_intr_handler = 0x40008f4c );
+PROVIDE ( uart_rx_one_char = 0x400092d0 );
+PROVIDE ( uart_rx_one_char_block = 0x400092a4 );
+PROVIDE ( uart_rx_readbuff = 0x40009394 );
+PROVIDE ( UartRxString = 0x400092fc );
+PROVIDE ( UartSetBaudProc = 0x40008aac );
+PROVIDE ( UartSpiAttachProc = 0x40008a6c );
+PROVIDE ( UartSpiReadProc = 0x40008a80 );
+PROVIDE ( uart_tx_flush = 0x40009258 );
+PROVIDE ( uart_tx_one_char = 0x40009200 );
+PROVIDE ( uart_tx_one_char2 = 0x4000922c );
+PROVIDE ( uart_tx_switch = 0x40009028 );
+PROVIDE ( uart_tx_wait_idle = 0x40009278 );
+PROVIDE ( __ucmpdi2 = 0x40063840 );
+PROVIDE ( __udivdi3 = 0x4000cff8 );
+PROVIDE ( __udivmoddi4 = 0x40064ab0 );
+PROVIDE ( __udivsi3 = 0x4000c7c8 );
+PROVIDE ( __udiv_w_sdiv = 0x40064aa8 );
+PROVIDE ( __umoddi3 = 0x4000d280 );
+PROVIDE ( __umodsi3 = 0x4000c7d0 );
+PROVIDE ( __umulsidi3 = 0x4000c7d8 );
+PROVIDE ( ungetc = 0x400590f4 );
+PROVIDE ( _ungetc_r = 0x40058fa0 );
+PROVIDE ( _unlink_r = 0x4000bc84 );
+PROVIDE ( __unorddf2 = 0x400637f4 );
+PROVIDE ( __unordsf2 = 0x40063478 );
+PROVIDE ( user_code_start = 0x3ffe0400 );
+PROVIDE ( _UserExceptionVector = 0x40000340 );
+PROVIDE ( utoa = 0x40056258 );
+PROVIDE ( __utoa = 0x400561f0 );
+PROVIDE ( vasiprintf = 0x40056eb8 );
+PROVIDE ( _vasiprintf_r = 0x40056e80 );
+PROVIDE ( vasniprintf = 0x40056e58 );
+PROVIDE ( _vasniprintf_r = 0x40056df8 );
+PROVIDE ( vasnprintf = 0x40056e58 );
+PROVIDE ( _vasnprintf_r = 0x40056df8 );
+PROVIDE ( vasprintf = 0x40056eb8 );
+PROVIDE ( _vasprintf_r = 0x40056e80 );
+PROVIDE ( VerifyFlashMd5Proc = 0x40008c44 );
+PROVIDE ( veryBigHexP256 = 0x3ff9736c );
+PROVIDE ( vfiprintf = 0x40057ae8 );
+PROVIDE ( _vfiprintf_r = 0x40057850 );
+PROVIDE ( vfiscanf = 0x40057eb8 );
+PROVIDE ( _vfiscanf_r = 0x40057f24 );
+PROVIDE ( vfprintf = 0x40057ae8 );
+PROVIDE ( _vfprintf_r = 0x40057850 );
+PROVIDE ( vfscanf = 0x40057eb8 );
+PROVIDE ( _vfscanf_r = 0x40057f24 );
+PROVIDE ( viprintf = 0x400569b4 );
+PROVIDE ( _viprintf_r = 0x400569e4 );
+PROVIDE ( viscanf = 0x40058698 );
+PROVIDE ( _viscanf_r = 0x400586c8 );
+PROVIDE ( vprintf = 0x400569b4 );
+PROVIDE ( _vprintf_r = 0x400569e4 );
+PROVIDE ( vscanf = 0x40058698 );
+PROVIDE ( _vscanf_r = 0x400586c8 );
+PROVIDE ( vsiprintf = 0x40056ac4 );
+PROVIDE ( _vsiprintf_r = 0x40056a90 );
+PROVIDE ( vsiscanf = 0x40058740 );
+PROVIDE ( _vsiscanf_r = 0x400586f8 );
+PROVIDE ( vsniprintf = 0x40056a68 );
+PROVIDE ( _vsniprintf_r = 0x40056a14 );
+PROVIDE ( vsnprintf = 0x40056a68 );
+PROVIDE ( _vsnprintf_r = 0x40056a14 );
+PROVIDE ( vsprintf = 0x40056ac4 );
+PROVIDE ( _vsprintf_r = 0x40056a90 );
+PROVIDE ( vsscanf = 0x40058740 );
+PROVIDE ( _vsscanf_r = 0x400586f8 );
+PROVIDE ( wcrtomb = 0x40058920 );
+PROVIDE ( _wcrtomb_r = 0x400588d8 );
+PROVIDE ( __wctomb = 0x3ff96540 );
+PROVIDE ( _wctomb_r = 0x40058f14 );
+PROVIDE ( _WindowOverflow12 = 0x40000100 );
+PROVIDE ( _WindowOverflow4 = 0x40000000 );
+PROVIDE ( _WindowOverflow8 = 0x40000080 );
+PROVIDE ( _WindowUnderflow12 = 0x40000140 );
+PROVIDE ( _WindowUnderflow4 = 0x40000040 );
+PROVIDE ( _WindowUnderflow8 = 0x400000c0 );
+PROVIDE ( write = 0x4000181c );
+PROVIDE ( _write_r = 0x4000bd70 );
+PROVIDE ( xthal_bcopy = 0x4000c098 );
+PROVIDE ( xthal_copy123 = 0x4000c124 );
+PROVIDE ( xthal_get_ccompare = 0x4000c078 );
+PROVIDE ( xthal_get_ccount = 0x4000c050 );
+PROVIDE ( xthal_get_interrupt = 0x4000c1e4 );
+PROVIDE ( xthal_get_intread = 0x4000c1e4 );
+PROVIDE ( Xthal_intlevel = 0x3ff9c2b4 );
+PROVIDE ( xthal_memcpy = 0x4000c0bc );
+PROVIDE ( xthal_set_ccompare = 0x4000c058 );
+PROVIDE ( xthal_set_intclear = 0x4000c1ec );
+PROVIDE ( _xtos_alloca_handler = 0x40000010 );
+PROVIDE ( _xtos_cause3_handler = 0x40000dd8 );
+PROVIDE ( _xtos_c_handler_table = 0x3ffe0548 );
+PROVIDE ( _xtos_c_wrapper_handler = 0x40000de8 );
+PROVIDE ( _xtos_enabled = 0x3ffe0650 );
+PROVIDE ( _xtos_exc_handler_table = 0x3ffe0448 );
+PROVIDE ( _xtos_interrupt_mask_table = 0x3ffe0758 );
+PROVIDE ( _xtos_interrupt_table = 0x3ffe0658 );
+PROVIDE ( _xtos_ints_off = 0x4000bfac );
+PROVIDE ( _xtos_ints_on = 0x4000bf88 );
+PROVIDE ( _xtos_intstruct = 0x3ffe0650 );
+PROVIDE ( _xtos_l1int_handler = 0x40000814 );
+PROVIDE ( _xtos_p_none = 0x4000bfd4 );
+PROVIDE ( _xtos_restore_intlevel = 0x40000928 );
+PROVIDE ( _xtos_return_from_exc = 0x4000c034 );
+PROVIDE ( _xtos_set_exception_handler = 0x4000074c );
+PROVIDE ( _xtos_set_interrupt_handler = 0x4000bf78 );
+PROVIDE ( _xtos_set_interrupt_handler_arg = 0x4000bf34 );
+PROVIDE ( _xtos_set_intlevel = 0x4000bfdc );
+PROVIDE ( _xtos_set_min_intlevel = 0x4000bff8 );
+PROVIDE ( _xtos_set_vpri = 0x40000934 );
+PROVIDE ( _xtos_syscall_handler = 0x40000790 );
+PROVIDE ( _xtos_unhandled_exception = 0x4000c024 );
+PROVIDE ( _xtos_unhandled_interrupt = 0x4000c01c );
+PROVIDE ( _xtos_vpri_enabled = 0x3ffe0654 );
diff --git a/tools/sdk/ld/esp32_out.ld b/tools/sdk/ld/esp32_out.ld
new file mode 100644
index 00000000..5e7cd392
--- /dev/null
+++ b/tools/sdk/ld/esp32_out.ld
@@ -0,0 +1,52 @@
+/* ESP32 Linker Script Memory Layout
+
+   This file describes the memory layout (memory blocks) as virtual
+   memory addresses.
+
+   esp32.common.ld contains output sections to link compiler output
+   into these memory blocks.
+
+   ***
+
+   This linker script is passed through the C preprocessor to include
+   configuration options.
+
+   Please use preprocessor features sparingly! Restrict
+   to simple macros with numeric values, and/or #if/#endif blocks.
+*/
+/*
+ *
+ * Automatically generated file; DO NOT EDIT.
+ * Espressif IoT Development Framework Configuration
+ *
+ */
+MEMORY
+{
+  /* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
+  of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
+  are connected to the data port of the CPU and eg allow bytewise access. */
+  /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
+  iram0_0_seg (RX) : org = 0x40080000, len = 0x20000
+  /* Even though the segment name is iram, it is actually mapped to flash */
+  iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000
+  /* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
+
+     Enabling Bluetooth & Trace Memory features in menuconfig will decrease
+     the amount of RAM available.
+  */
+  dram0_0_seg (RW) : org = 0x3FFB0000 + 0x0,
+                                     len = 0x50000 - 0x0 - 0x0
+  /* Flash mapped constant data */
+  drom0_0_seg (R) : org = 0x3F400010, len = 0x800000
+  /* RTC fast memory (executable). Persists over deep sleep.
+   */
+  rtc_iram_seg(RWX) : org = 0x400C0000, len = 0x2000
+  /* RTC slow memory (data accessible). Persists over deep sleep.
+
+     Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.
+  */
+  rtc_slow_seg(RW) : org = 0x50000000 + 0,
+                                     len = 0x1000 - 0
+}
+/* Heap ends at top of dram0_0_seg */
+_heap_end = 0x40000000 - 0x0;
diff --git a/tools/sdk/lib/libbt.a b/tools/sdk/lib/libbt.a
new file mode 100644
index 00000000..40e814d0
Binary files /dev/null and b/tools/sdk/lib/libbt.a differ
diff --git a/tools/sdk/lib/libbtdm_app.a b/tools/sdk/lib/libbtdm_app.a
new file mode 100644
index 00000000..b8ec4f98
Binary files /dev/null and b/tools/sdk/lib/libbtdm_app.a differ
diff --git a/tools/sdk/lib/libc.a b/tools/sdk/lib/libc.a
new file mode 100644
index 00000000..263a4d88
Binary files /dev/null and b/tools/sdk/lib/libc.a differ
diff --git a/tools/sdk/lib/libcore.a b/tools/sdk/lib/libcore.a
new file mode 100644
index 00000000..18ad4b16
Binary files /dev/null and b/tools/sdk/lib/libcore.a differ
diff --git a/tools/sdk/lib/libcrypto.a b/tools/sdk/lib/libcrypto.a
new file mode 100644
index 00000000..b146ef7a
Binary files /dev/null and b/tools/sdk/lib/libcrypto.a differ
diff --git a/tools/sdk/lib/libdriver.a b/tools/sdk/lib/libdriver.a
new file mode 100644
index 00000000..0095d980
Binary files /dev/null and b/tools/sdk/lib/libdriver.a differ
diff --git a/tools/sdk/lib/libesp32.a b/tools/sdk/lib/libesp32.a
new file mode 100644
index 00000000..cdb6d872
Binary files /dev/null and b/tools/sdk/lib/libesp32.a differ
diff --git a/tools/sdk/lib/libexpat.a b/tools/sdk/lib/libexpat.a
new file mode 100644
index 00000000..ec263d94
Binary files /dev/null and b/tools/sdk/lib/libexpat.a differ
diff --git a/tools/sdk/lib/libfreertos.a b/tools/sdk/lib/libfreertos.a
new file mode 100644
index 00000000..4c16cea6
Binary files /dev/null and b/tools/sdk/lib/libfreertos.a differ
diff --git a/tools/sdk/lib/libg.a b/tools/sdk/lib/libg.a
new file mode 100644
index 00000000..f583174f
Binary files /dev/null and b/tools/sdk/lib/libg.a differ
diff --git a/tools/sdk/lib/libhal.a b/tools/sdk/lib/libhal.a
new file mode 100644
index 00000000..382f4e0a
Binary files /dev/null and b/tools/sdk/lib/libhal.a differ
diff --git a/tools/sdk/lib/libjson.a b/tools/sdk/lib/libjson.a
new file mode 100644
index 00000000..467cbf46
Binary files /dev/null and b/tools/sdk/lib/libjson.a differ
diff --git a/tools/sdk/lib/liblog.a b/tools/sdk/lib/liblog.a
new file mode 100644
index 00000000..0ac53728
Binary files /dev/null and b/tools/sdk/lib/liblog.a differ
diff --git a/tools/sdk/lib/liblwip.a b/tools/sdk/lib/liblwip.a
new file mode 100644
index 00000000..66390e1c
Binary files /dev/null and b/tools/sdk/lib/liblwip.a differ
diff --git a/tools/sdk/lib/libm.a b/tools/sdk/lib/libm.a
new file mode 100644
index 00000000..f3fe6dab
Binary files /dev/null and b/tools/sdk/lib/libm.a differ
diff --git a/tools/sdk/lib/libmbedtls.a b/tools/sdk/lib/libmbedtls.a
new file mode 100644
index 00000000..97595041
Binary files /dev/null and b/tools/sdk/lib/libmbedtls.a differ
diff --git a/tools/sdk/lib/libnet80211.a b/tools/sdk/lib/libnet80211.a
new file mode 100644
index 00000000..fb04fbe1
Binary files /dev/null and b/tools/sdk/lib/libnet80211.a differ
diff --git a/tools/sdk/lib/libnghttp.a b/tools/sdk/lib/libnghttp.a
new file mode 100644
index 00000000..944b4129
Binary files /dev/null and b/tools/sdk/lib/libnghttp.a differ
diff --git a/tools/sdk/lib/libnvs_flash.a b/tools/sdk/lib/libnvs_flash.a
new file mode 100644
index 00000000..32f923c8
Binary files /dev/null and b/tools/sdk/lib/libnvs_flash.a differ
diff --git a/tools/sdk/lib/libphy.a b/tools/sdk/lib/libphy.a
new file mode 100755
index 00000000..70b64cf2
Binary files /dev/null and b/tools/sdk/lib/libphy.a differ
diff --git a/tools/sdk/lib/libpp.a b/tools/sdk/lib/libpp.a
new file mode 100644
index 00000000..45bd8383
Binary files /dev/null and b/tools/sdk/lib/libpp.a differ
diff --git a/tools/sdk/lib/librtc.a b/tools/sdk/lib/librtc.a
new file mode 100644
index 00000000..39a9bb98
Binary files /dev/null and b/tools/sdk/lib/librtc.a differ
diff --git a/tools/sdk/lib/libsmartconfig.a b/tools/sdk/lib/libsmartconfig.a
new file mode 100644
index 00000000..81bc725b
Binary files /dev/null and b/tools/sdk/lib/libsmartconfig.a differ
diff --git a/tools/sdk/lib/libspi_flash.a b/tools/sdk/lib/libspi_flash.a
new file mode 100644
index 00000000..de3e2582
Binary files /dev/null and b/tools/sdk/lib/libspi_flash.a differ
diff --git a/tools/sdk/lib/libtcpip_adapter.a b/tools/sdk/lib/libtcpip_adapter.a
new file mode 100644
index 00000000..a2bcc0d1
Binary files /dev/null and b/tools/sdk/lib/libtcpip_adapter.a differ
diff --git a/tools/sdk/lib/libwpa.a b/tools/sdk/lib/libwpa.a
new file mode 100644
index 00000000..2349056a
Binary files /dev/null and b/tools/sdk/lib/libwpa.a differ
diff --git a/variants/esp32/pins_arduino.h b/variants/esp32/pins_arduino.h
new file mode 100644
index 00000000..d734b1b3
--- /dev/null
+++ b/variants/esp32/pins_arduino.h
@@ -0,0 +1,33 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+
+#define digitalPinToPort(pin)       (0)
+#define digitalPinToBitMask(pin)    (1UL << (pin))
+#define digitalPinToTimer(pin)      (0)
+#define portOutputRegister(port)
+#define portInputRegister(port)
+#define portModeRegister(port)
+
+#define NOT_A_PIN -1
+#define NOT_A_PORT -1
+#define NOT_AN_INTERRUPT -1
+#define NOT_ON_TIMER 0
+
+#define EXTERNAL_NUM_INTERRUPTS 16
+#define NUM_DIGITAL_PINS        40
+#define NUM_ANALOG_INPUTS       18
+
+#define analogInputToDigitalPin(p)
+#define digitalPinToInterrupt(p)
+#define digitalPinHasPWM(p)
+
+static const uint8_t SDA = 21;
+static const uint8_t SCL = 22;
+
+static const uint8_t SS    = 2;
+static const uint8_t MOSI  = 23;
+static const uint8_t MISO  = 19;
+static const uint8_t SCK   = 18;
+
+#endif /* Pins_Arduino_h */
\ No newline at end of file