From 7d2632c024c721e9416cace840e013863804a122 Mon Sep 17 00:00:00 2001
From: chuck todd <stickbreaker@users.noreply.github.com>
Date: Mon, 11 Nov 2019 07:37:35 -0700
Subject: [PATCH] Implement Tx only Flush (#3433)

* add option to Flush() to only clear txQueue

Add the option to cause Flush() to just wait for tx data to clear the tx fifo and uart, leave the rx queue and rx fifo as is.

* support tx only flush()

* support tx only Flush()

* support txOnly for Flush()

* compatibility to Stream()

* compatibility for Stream()

* default value error

* default value error

* Update esp32-hal-uart.h

* Update esp32-hal-uart.c

* Update HardwareSerial.cpp

* sp

* correctly implement flushTxOnly()
---
 cores/esp32/HardwareSerial.cpp |  7 ++++++-
 cores/esp32/HardwareSerial.h   |  1 +
 cores/esp32/esp32-hal-uart.c   | 23 +++++++++++++++--------
 cores/esp32/esp32-hal-uart.h   |  1 +
 4 files changed, 23 insertions(+), 9 deletions(-)

diff --git a/cores/esp32/HardwareSerial.cpp b/cores/esp32/HardwareSerial.cpp
index 545c9b05..860c2c0f 100644
--- a/cores/esp32/HardwareSerial.cpp
+++ b/cores/esp32/HardwareSerial.cpp
@@ -131,11 +131,16 @@ int HardwareSerial::read(void)
     return -1;
 }
 
-void HardwareSerial::flush()
+void HardwareSerial::flush(void)
 {
     uartFlush(_uart);
 }
 
+void HardwareSerial::flush(bool txOnly)
+{
+    uartFlushTxOnly(_uart, txOnly);
+}
+
 size_t HardwareSerial::write(uint8_t c)
 {
     uartWrite(_uart, c);
diff --git a/cores/esp32/HardwareSerial.h b/cores/esp32/HardwareSerial.h
index 5f886650..7d9f26d2 100644
--- a/cores/esp32/HardwareSerial.h
+++ b/cores/esp32/HardwareSerial.h
@@ -63,6 +63,7 @@ public:
     int peek(void);
     int read(void);
     void flush(void);
+    void flush( bool txOnly);
     size_t write(uint8_t);
     size_t write(const uint8_t *buffer, size_t size);
 
diff --git a/cores/esp32/esp32-hal-uart.c b/cores/esp32/esp32-hal-uart.c
index 2dee63dc..8bb4b185 100644
--- a/cores/esp32/esp32-hal-uart.c
+++ b/cores/esp32/esp32-hal-uart.c
@@ -327,6 +327,11 @@ void uartWriteBuf(uart_t* uart, const uint8_t * data, size_t len)
 }
 
 void uartFlush(uart_t* uart)
+{
+    uartFlushTxOnly(uart,false);
+}
+
+void uartFlushTxOnly(uart_t* uart, bool txOnly)
 {
     if(uart == NULL) {
         return;
@@ -334,17 +339,19 @@ void uartFlush(uart_t* uart)
 
     UART_MUTEX_LOCK();
     while(uart->dev->status.txfifo_cnt || uart->dev->status.st_utx_out);
+    
+    if( !txOnly ){
+        //Due to hardware issue, we can not use fifo_rst to reset uart fifo.
+        //See description about UART_TXFIFO_RST and UART_RXFIFO_RST in <<esp32_technical_reference_manual>> v2.6 or later.
 
-    //Due to hardware issue, we can not use fifo_rst to reset uart fifo.
-    //See description about UART_TXFIFO_RST and UART_RXFIFO_RST in <<esp32_technical_reference_manual>> v2.6 or later.
+        // we read the data out and make `fifo_len == 0 && rd_addr == wr_addr`.
+        while(uart->dev->status.rxfifo_cnt != 0 || (uart->dev->mem_rx_status.wr_addr != uart->dev->mem_rx_status.rd_addr)) {
+            READ_PERI_REG(UART_FIFO_REG(uart->num));
+        }
 
-    // we read the data out and make `fifo_len == 0 && rd_addr == wr_addr`.
-    while(uart->dev->status.rxfifo_cnt != 0 || (uart->dev->mem_rx_status.wr_addr != uart->dev->mem_rx_status.rd_addr)) {
-        READ_PERI_REG(UART_FIFO_REG(uart->num));
+        xQueueReset(uart->queue);
     }
-
-    xQueueReset(uart->queue);
-
+    
     UART_MUTEX_UNLOCK();
 }
 
diff --git a/cores/esp32/esp32-hal-uart.h b/cores/esp32/esp32-hal-uart.h
index 821ca9c6..e44d25bb 100644
--- a/cores/esp32/esp32-hal-uart.h
+++ b/cores/esp32/esp32-hal-uart.h
@@ -63,6 +63,7 @@ void uartWrite(uart_t* uart, uint8_t c);
 void uartWriteBuf(uart_t* uart, const uint8_t * data, size_t len);
 
 void uartFlush(uart_t* uart);
+void uartFlushTxOnly(uart_t* uart, bool txOnly );
 
 void uartSetBaudRate(uart_t* uart, uint32_t baud_rate);
 uint32_t uartGetBaudRate(uart_t* uart);