Update IDF to afe4c76 and BLE lib (#2130)

* Update BLE

* Update IDF to afe4c76

* Update CMakeLists.txt

* Update BLE to fix compilation issues

* Update BLE

CMakeLists.txt

@@ -150,6 +150,8 @@ set(BLE_SRCS
   libraries/BLE/src/BLEDescriptor.cpp
   libraries/BLE/src/BLEDescriptorMap.cpp
   libraries/BLE/src/BLEDevice.cpp
+  libraries/BLE/src/BLEEddystoneTLM.cpp
+  libraries/BLE/src/BLEEddystoneURL.cpp
   libraries/BLE/src/BLEExceptions.cpp
   libraries/BLE/src/BLEHIDDevice.cpp
   libraries/BLE/src/BLERemoteCharacteristic.cpp

libraries/BLE

@@ -1 +1 @@
-Subproject commit 7951347ed68313d75c367e1f2cce763cb56d1eb2
+Subproject commit 11a0aa645326aed0cb681e86060fe28d4623bc68

tools/gen_esp32part.py

@@ -29,6 +29,7 @@ import struct
 import sys
 import hashlib
 import binascii
+import errno
 
 MAX_PARTITION_LENGTH = 0xC00   # 3K for partition data (96 entries) leaves 1K in a 4K sector for signature
 MD5_PARTITION_BEGIN = b"\xEB\xEB" + b"\xFF" * 14 # The first 2 bytes are like magic numbers for MD5 sum
@@ -480,6 +481,16 @@ def main():
             raise InputError("Partitions defined in '%s' occupy %.1fMB of flash (%d bytes) which does not fit in configured flash size %dMB. Change the flash size in menuconfig under the 'Serial Flasher Config' menu." %
                              (args.input.name, table_size / 1024.0 / 1024.0, table_size, size_mb))
 
+    # Make sure that the output directory is created
+    output_dir = os.path.abspath(os.path.dirname(args.output))
+
+    if not os.path.exists(output_dir):
+        try:
+            os.makedirs(output_dir)
+        except OSError as exc: 
+            if exc.errno != errno.EEXIST:
+                raise
+
     if input_is_binary:
         output = table.to_csv()
         with sys.stdout if args.output == '-' else open(args.output, 'w') as f:

tools/sdk/include/config/sdkconfig.h

@@ -120,6 +120,7 @@
 #define CONFIG_SCAN_DUPLICATE_BY_DEVICE_ADDR 1
 #define CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER 1
 #define CONFIG_MB_SERIAL_TASK_STACK_SIZE 2048
+#define CONFIG_MBEDTLS_PSK_MODES 1
 #define CONFIG_GATTS_SEND_SERVICE_CHANGE_AUTO 1
 #define CONFIG_LWIP_DHCPS_LEASE_UNIT 60
 #define CONFIG_SPIFFS_USE_MAGIC 1
@@ -164,9 +165,11 @@
 #define CONFIG_BTDM_LPCLK_SEL_MAIN_XTAL 1
 #define CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED 1
 #define CONFIG_LIBSODIUM_USE_MBEDTLS_SHA 1
+#define CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_PSK 1
 #define CONFIG_SW_COEXIST_PREFERENCE_WIFI 1
 #define CONFIG_DMA_RX_BUF_NUM 10
 #define CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED 1
+#define CONFIG_MBEDTLS_KEY_EXCHANGE_PSK 1
 #define CONFIG_TCP_SYNMAXRTX 6
 #define CONFIG_MB_UART_RTS 32
 #define CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA 1
@@ -199,6 +202,7 @@
 #define CONFIG_SW_COEXIST_PREFERENCE_VALUE 0
 #define CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA 1
 #define CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER 1
+#define CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_PSK 1
 #define CONFIG_PPP_SUPPORT 1
 #define CONFIG_SPIRAM_SPEED_40M 1
 #define CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE 2048
@@ -278,6 +282,7 @@
 #define CONFIG_MBEDTLS_HAVE_TIME 1
 #define CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY 1
 #define CONFIG_TCP_QUEUE_OOSEQ 1
+#define CONFIG_FATFS_ALLOC_PREFER_EXTRAM 1
 #define CONFIG_GATTS_ENABLE 1
 #define CONFIG_CXX_EXCEPTIONS_EMG_POOL_SIZE 0
 #define CONFIG_ADC_CAL_EFUSE_VREF_ENABLE 1
@@ -287,6 +292,7 @@
 #define CONFIG_SUPPORT_TERMIOS 1
 #define CONFIG_CLASSIC_BT_ENABLED 1
 #define CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK 1
+#define CONFIG_MBEDTLS_KEY_EXCHANGE_RSA_PSK 1
 #define CONFIG_OPENSSL_ASSERT_DO_NOTHING 1
 #define CONFIG_IDF_TARGET "esp32"
 #define CONFIG_WL_SECTOR_SIZE_4096 1

tools/sdk/include/driver/driver/i2s.h

@@ -139,6 +139,7 @@ typedef struct {
     int                     dma_buf_count;          /*!< I2S DMA Buffer Count */
     int                     dma_buf_len;            /*!< I2S DMA Buffer Length */
     bool                    use_apll;              /*!< I2S using APLL as main I2S clock, enable it to get accurate clock */
+    bool                    tx_desc_auto_clear;     /*!< I2S auto clear tx descriptor if there is underflow condition (helps in avoiding noise in case of data unavailability) */
     int                     fixed_mclk;             /*!< I2S using fixed MCLK output. If use_apll = true and fixed_mclk > 0, then the clock output for i2s is fixed and equal to the fixed_mclk value.*/
 } i2s_config_t;
 

tools/sdk/include/driver/driver/rmt.h

@@ -80,6 +80,19 @@ typedef enum {
     RMT_CARRIER_LEVEL_MAX
 } rmt_carrier_level_t;
 
+typedef enum {
+    RMT_CHANNEL_UNINIT = 0, /*!< RMT channel uninitialized */
+    RMT_CHANNEL_IDLE = 1,   /*!< RMT channel status idle */
+    RMT_CHANNEL_BUSY = 2,   /*!< RMT channel status busy */
+} rmt_channel_status_t;
+
+/**
+ * @brief Data struct of RMT channel status
+ */
+typedef struct {
+  rmt_channel_status_t status[RMT_CHANNEL_MAX]; /*!< Store the current status of each channel */
+} rmt_channel_status_result_t;
+
 /**
  * @brief Data struct of RMT TX configure parameters
  */
@@ -496,6 +509,7 @@ esp_err_t rmt_set_idle_level(rmt_channel_t channel, bool idle_out_en, rmt_idle_l
  * @param channel RMT channel (0-7)
  *
  * @param status Pointer to accept channel status.
+ *        Please refer to RMT_CHnSTATUS_REG(n=0~7) in `rmt_reg.h` for more details of each field.
  *
  * @return
  *     - ESP_ERR_INVALID_ARG Parameter error
@@ -679,6 +693,19 @@ esp_err_t rmt_driver_install(rmt_channel_t channel, size_t rx_buf_size, int intr
  */
 esp_err_t rmt_driver_uninstall(rmt_channel_t channel);
 
+/**
+ * @brief Get the current status of eight channels.
+ *
+ * @note Do not call this function if it is possible that `rmt_driver_uninstall` will be called at the same time.
+ *
+ * @param[out] channel_status store the current status of each channel
+ *
+ * @return
+ *     - ESP_ERR_INVALID_ARG Parameter is NULL
+ *     - ESP_OK Success
+ */
+esp_err_t rmt_get_channel_status(rmt_channel_status_result_t *channel_status);
+
 /**
  * @brief RMT send waveform from rmt_item array.
  *

tools/sdk/include/driver/driver/uart.h

@@ -801,7 +801,7 @@ esp_err_t uart_get_collision_flag(uart_port_t uart_num, bool* collision_flag);
  * light sleep. This function allows setting the threshold value.
  *
  * Stop bit and parity bits (if enabled) also contribute to the number of edges.
- * For example, letter 'a' with ASCII code 97 is encoded as 010001101 on the wire
+ * For example, letter 'a' with ASCII code 97 is encoded as 0100001101 on the wire
  * (with 8n1 configuration), start and stop bits included. This sequence has 3
  * positive edges (transitions from 0 to 1). Therefore, to wake up the system
  * when 'a' is sent, set wakeup_threshold=3.
@@ -813,7 +813,10 @@ esp_err_t uart_get_collision_flag(uart_port_t uart_num, bool* collision_flag);
  * correct baud rate all the time, select REF_TICK as UART clock source,
  * by setting use_ref_tick field in uart_config_t to true.
  *
- * @note in ESP32, UART2 does not support light sleep wakeup feature.
+ * @note in ESP32, the wakeup signal can only be input via IO_MUX (i.e.
+ *       GPIO3 should be configured as function_1 to wake up UART0,
+ *       GPIO9 should be configured as function_5 to wake up UART1), UART2
+ *       does not support light sleep wakeup feature.
  *
  * @param uart_num  UART number
  * @param wakeup_threshold  number of RX edges for light sleep wakeup, value is 3 .. 0x3ff.

tools/sdk/include/esp32/esp_mesh.h

@@ -187,6 +187,11 @@ typedef enum {
                                              this event, and add the corresponding scan done handler in this event. */
     MESH_EVENT_NETWORK_STATE,           /**< network state, such as whether current mesh network has a root. */
     MESH_EVENT_STOP_RECONNECTION,       /**< the root stops reconnecting to the router and non-root devices stop reconnecting to their parents. */
+    MESH_EVENT_FIND_NETWORK,            /**< when the channel field in mesh configuration is set to zero, mesh stack will perform a
+                                             full channel scan to find a mesh network that can join, and return the channel value
+                                             after finding it. */
+    MESH_EVENT_ROUTER_SWITCH,           /**< if users specify BSSID of the router in mesh configuration, when the root connects to another
+                                             router with the same SSID, this event will be posted and the new router information is attached. */
     MESH_EVENT_MAX,
 } mesh_event_id_t;
 
@@ -310,6 +315,14 @@ typedef struct {
     mesh_addr_t rc_addr;    /**< root address specified by users via API esp_mesh_waive_root() */
 } mesh_event_vote_started_t;
 
+/**
+ * @brief find a mesh network that this device can join
+ */
+typedef struct {
+    uint8_t channel;            /**< channel number of the new found network */
+    uint8_t router_bssid[6];    /**< router BSSID */
+} mesh_event_find_network_t;
+
 /**
  * @brief IP settings from LwIP stack
  */
@@ -381,6 +394,11 @@ typedef struct {
     bool is_rootless;     /**< whether current mesh network has a root */
 } mesh_event_network_state_t;
 
+/**
+ * @brief New router information
+ */
+typedef system_event_sta_connected_t mesh_event_router_switch_t;
+
 /**
  * @brief Mesh event information
  */
@@ -405,6 +423,8 @@ typedef union {
     mesh_event_root_fixed_t root_fixed;                    /**< fixed root */
     mesh_event_scan_done_t scan_done;                      /**< scan done */
     mesh_event_network_state_t network_state;              /**< network state, such as whether current mesh network has a root. */
+    mesh_event_find_network_t find_network;                /**< network found that can join */
+    mesh_event_router_switch_t router_switch;              /**< new router information */
 } mesh_event_info_t;
 
 /**
@@ -445,10 +465,16 @@ typedef struct {
  * @brief Router configuration
  */
 typedef struct {
-    uint8_t ssid[32];        /**< SSID */
+    uint8_t ssid[32];             /**< SSID */
-    uint8_t ssid_len;        /**< length of SSID */
+    uint8_t ssid_len;             /**< length of SSID */
-    uint8_t bssid[6];        /**< BSSID, if router is hidden, this value is mandatory */
+    uint8_t bssid[6];             /**< BSSID, if this value is specified, users should also specify "allow_router_switch". */
-    uint8_t password[64];    /**< password */
+    uint8_t password[64];         /**< password */
+    bool allow_router_switch;     /**< if the BSSID is specified and this value is also set, when the router of this specified BSSID
+                                       fails to be found after "fail" (mesh_attempts_t) times, the whole network is allowed to switch
+                                       to another router with the same SSID. The new router might also be on a different channel.
+                                       The default value is false.
+                                       There is a risk that if the password is different between the new switched router and the previous
+                                       one, the mesh network could be established but the root will never connect to the new switched router. */
 } mesh_router_t;
 
 /**
@@ -464,6 +490,8 @@ typedef struct {
  */
 typedef struct {
     uint8_t channel;                            /**< channel, the mesh network on */
+    bool allow_channel_switch;                  /**< if this value is set, when "fail" (mesh_attempts_t) times is reached, device will change to
+                                                     a full channel scan for a network that could join. The default value is false. */
     mesh_event_cb_t event_cb;                   /**< mesh event callback */
     mesh_addr_t mesh_id;                        /**< mesh network identification */
     mesh_router_t router;                       /**< router configuration */
@@ -1412,6 +1440,23 @@ esp_err_t esp_mesh_disconnect(void);
  */
 esp_err_t esp_mesh_connect(void);
 
+/**
+ * @brief      Cause the root device to add Channel Switch Announcement Element (CSA IE) to beacon
+ *             - Set the new channel
+ *             - Set how many beacons with CSA IE will be sent before changing a new channel
+ *             - Enable the channel switch function
+ *
+ * @attention  This API is only called by the root.
+ *
+ * @param[in]  new_bssid  the new router BSSID if the router changes
+ * @param[in]  csa_newchan  the new channel number to which the whole network is moving
+ * @param[in]  csa_count  channel switch period(beacon count), unit is based on beacon interval of its softAP, the default value is 15.
+ *
+ * @return
+ *    - ESP_OK
+ */
+esp_err_t esp_mesh_switch_channel(const uint8_t *new_bssid, int csa_newchan, int csa_count);
+
 #ifdef __cplusplus
 }
 #endif

tools/sdk/include/fatfs/ffconf.h

@@ -301,4 +301,11 @@
 #include "freertos/FreeRTOS.h"
 #include "freertos/semphr.h"
 
+/* Some memory allocation functions are declared here in addition to ff.h, so that
+   they can be used also by external code when LFN feature is disabled.
+ */
+void* ff_memalloc (UINT msize);
+void* ff_memcalloc (UINT num, UINT size);
+
+
 /*--- End of configuration options ---*/

tools/sdk/include/idf_test/idf_performance.h

@@ -12,8 +12,8 @@
 #define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA                        15
 /* Due to code size & linker layout differences interacting with cache, VFS
    microbenchmark currently runs slower with PSRAM enabled. */
-#define IDF_PERFORMANCE_MAX_VFS_OPEN_WRITE_CLOSE_TIME                           50000
+#define IDF_PERFORMANCE_MAX_VFS_OPEN_WRITE_CLOSE_TIME                           20000
-#define IDF_PERFORMANCE_MAX_VFS_OPEN_WRITE_CLOSE_TIME_PSRAM                     40000
+#define IDF_PERFORMANCE_MAX_VFS_OPEN_WRITE_CLOSE_TIME_PSRAM                     25000
 // throughput performance by iperf
 #define IDF_PERFORMANCE_MIN_TCP_RX_THROUGHPUT                                   50
 #define IDF_PERFORMANCE_MIN_TCP_TX_THROUGHPUT                                   40

tools/sdk/include/soc/soc/rmt_reg.h

@@ -995,6 +995,60 @@
 #define RMT_STATUS_CH0_M  ((RMT_STATUS_CH0_V)<<(RMT_STATUS_CH0_S))
 #define RMT_STATUS_CH0_V  0xFFFFFFFF
 #define RMT_STATUS_CH0_S  0
+/* RMT_APB_MEM_RD_ERR_CH0 : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: The apb read memory status bit for channel0 turns to
+ high level when the apb read address exceeds the configuration range.*/
+#define RMT_APB_MEM_RD_ERR_CH0 (BIT(31))
+#define RMT_APB_MEM_RD_ERR_CH0_M  ((RMT_APB_MEM_RD_ERR_CH0_V)<<(RMT_APB_MEM_RD_ERR_CH0_S))
+#define RMT_APB_MEM_RD_ERR_CH0_V  0x1
+#define RMT_APB_MEM_RD_ERR_CH0_S  31
+/* RMT_APB_MEM_WR_ERR_CH0 : RO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: The apb write memory status bit for channel0 turns to
+ high level when the apb write address exceeds the configuration range.*/
+#define RMT_APB_MEM_WR_ERR_CH0 (BIT(30))
+#define RMT_APB_MEM_WR_ERR_CH0_M  ((RMT_APB_MEM_WR_ERR_CH0_V)<<(RMT_APB_MEM_WR_ERR_CH0_S))
+#define RMT_APB_MEM_WR_ERR_CH0_V  0x1
+#define RMT_APB_MEM_WR_ERR_CH0_S  30
+/* RMT_MEM_EMPTY_CH0 : RO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: The memory empty status bit for channel0. in acyclic mode,
+ this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.*/
+#define RMT_MEM_EMPTY_CH0 (BIT(29))
+#define RMT_MEM_EMPTY_CH0_M  ((RMT_MEM_EMPTY_CH0_V)<<(RMT_MEM_EMPTY_CH0_S))
+#define RMT_MEM_EMPTY_CH0_V  0x1
+#define RMT_MEM_EMPTY_CH0_S  29
+/* RMT_MEM_FULL_CH0 : RO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: The memory full status bit for channel0 turns to high level
+ when mem_waddr_ex is greater than or equal to the configuration range.*/
+#define RMT_MEM_FULL_CH0 (BIT(28))
+#define RMT_MEM_FULL_CH0_M  ((RMT_MEM_FULL_CH0_V)<<(RMT_MEM_FULL_CH0_S))
+#define RMT_MEM_FULL_CH0_V  0x1
+#define RMT_MEM_FULL_CH0_S  28
+/* RMT_MEM_OWNER_ERR_CH0 : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: When channel0 is configured for receive mode, this bit will turn to high level
+ if rmt_mem_owner register is not set to 1.*/
+#define RMT_MEM_OWNER_ERR_CH0 (BIT(27))
+#define RMT_MEM_OWNER_ERR_CH0_M  ((RMT_MEM_OWNER_ERR_CH0_V)<<(RMT_MEM_OWNER_ERR_CH0_S))
+#define RMT_MEM_OWNER_ERR_CH0_V  0x1
+#define RMT_MEM_OWNER_ERR_CH0_S  27
+/* RMT_STATE_CH0 : RO ;bitpos:[26:24] ;default: 3'h0 ; */
+/*description: The channel0 state machine status register.
+3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.*/
+#define RMT_STATE_CH0 0x07000000
+#define RMT_STATE_CH0_M  ((RMT_STATE_CH0_V)<<(RMT_STATE_CH0_S))
+#define RMT_STATE_CH0_V  0x7
+#define RMT_STATE_CH0_S  24
+/* RMT_MEM_RADDR_EX_CH0 : RO ;bitpos:[21:12] ;default: 10'h0 ; */
+/*description: The current memory write address of channel0.*/
+#define RMT_MEM_RADDR_EX_CH0 0x003ff000
+#define RMT_MEM_RADDR_EX_CH0_M  ((RMT_MEM_RADDR_EX_CH0_V)<<(RMT_MEM_RADDR_EX_CH0_S))
+#define RMT_MEM_RADDR_EX_CH0_V  0x3ff
+#define RMT_MEM_RADDR_EX_CH0_S  12
+/* RMT_MEM_WADDR_EX_CH0 : RO ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: The current memory read address of channel0.*/
+#define RMT_MEM_WADDR_EX_CH0 0x000003ff
+#define RMT_MEM_WADDR_EX_CH0_M  ((RMT_MEM_WADDR_EX_CH0_V)<<(RMT_MEM_WADDR_EX_CH0_S))
+#define RMT_MEM_WADDR_EX_CH0_V  0x3ff
+#define RMT_MEM_WADDR_EX_CH0_S  0
 
 #define RMT_CH1STATUS_REG          (DR_REG_RMT_BASE + 0x0064)
 /* RMT_STATUS_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
@@ -1003,6 +1057,60 @@
 #define RMT_STATUS_CH1_M  ((RMT_STATUS_CH1_V)<<(RMT_STATUS_CH1_S))
 #define RMT_STATUS_CH1_V  0xFFFFFFFF
 #define RMT_STATUS_CH1_S  0
+/* RMT_APB_MEM_RD_ERR_CH1 : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: The apb read memory status bit for channel1 turns to
+ high level when the apb read address exceeds the configuration range.*/
+#define RMT_APB_MEM_RD_ERR_CH1 (BIT(31))
+#define RMT_APB_MEM_RD_ERR_CH1_M  ((RMT_APB_MEM_RD_ERR_CH1_V)<<(RMT_APB_MEM_RD_ERR_CH1_S))
+#define RMT_APB_MEM_RD_ERR_CH1_V  0x1
+#define RMT_APB_MEM_RD_ERR_CH1_S  31
+/* RMT_APB_MEM_WR_ERR_CH1 : RO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: The apb write memory status bit for channel1 turns to
+ high level when the apb write address exceeds the configuration range.*/
+#define RMT_APB_MEM_WR_ERR_CH1 (BIT(30))
+#define RMT_APB_MEM_WR_ERR_CH1_M  ((RMT_APB_MEM_WR_ERR_CH1_V)<<(RMT_APB_MEM_WR_ERR_CH1_S))
+#define RMT_APB_MEM_WR_ERR_CH1_V  0x1
+#define RMT_APB_MEM_WR_ERR_CH1_S  30
+/* RMT_MEM_EMPTY_CH1 : RO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: The memory empty status bit for channel1. in acyclic mode,
+ this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.*/
+#define RMT_MEM_EMPTY_CH1 (BIT(29))
+#define RMT_MEM_EMPTY_CH1_M  ((RMT_MEM_EMPTY_CH1_V)<<(RMT_MEM_EMPTY_CH1_S))
+#define RMT_MEM_EMPTY_CH1_V  0x1
+#define RMT_MEM_EMPTY_CH1_S  29
+/* RMT_MEM_FULL_CH1 : RO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: The memory full status bit for channel1 turns to high level
+ when mem_waddr_ex is greater than or equal to the configuration range.*/
+#define RMT_MEM_FULL_CH1 (BIT(28))
+#define RMT_MEM_FULL_CH1_M  ((RMT_MEM_FULL_CH1_V)<<(RMT_MEM_FULL_CH1_S))
+#define RMT_MEM_FULL_CH1_V  0x1
+#define RMT_MEM_FULL_CH1_S  28
+/* RMT_MEM_OWNER_ERR_CH1 : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: When channel1 is configured for receive mode, this bit will turn to high level
+ if rmt_mem_owner register is not set to 1.*/
+#define RMT_MEM_OWNER_ERR_CH1 (BIT(27))
+#define RMT_MEM_OWNER_ERR_CH1_M  ((RMT_MEM_OWNER_ERR_CH1_V)<<(RMT_MEM_OWNER_ERR_CH1_S))
+#define RMT_MEM_OWNER_ERR_CH1_V  0x1
+#define RMT_MEM_OWNER_ERR_CH1_S  27
+/* RMT_STATE_CH1 : RO ;bitpos:[26:24] ;default: 3'h0 ; */
+/*description: The channel1 state machine status register.
+3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.*/
+#define RMT_STATE_CH1 0x07000000
+#define RMT_STATE_CH1_M  ((RMT_STATE_CH1_V)<<(RMT_STATE_CH1_S))
+#define RMT_STATE_CH1_V  0x7
+#define RMT_STATE_CH1_S  24
+/* RMT_MEM_RADDR_EX_CH1 : RO ;bitpos:[21:12] ;default: 10'h0 ; */
+/*description: The current memory write address of channel1.*/
+#define RMT_MEM_RADDR_EX_CH1 0x003ff000
+#define RMT_MEM_RADDR_EX_CH1_M  ((RMT_MEM_RADDR_EX_CH1_V)<<(RMT_MEM_RADDR_EX_CH1_S))
+#define RMT_MEM_RADDR_EX_CH1_V  0x3ff
+#define RMT_MEM_RADDR_EX_CH1_S  12
+/* RMT_MEM_WADDR_EX_CH1 : RO ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: The current memory read address of channel1.*/
+#define RMT_MEM_WADDR_EX_CH1 0x000003ff
+#define RMT_MEM_WADDR_EX_CH1_M  ((RMT_MEM_WADDR_EX_CH1_V)<<(RMT_MEM_WADDR_EX_CH1_S))
+#define RMT_MEM_WADDR_EX_CH1_V  0x3ff
+#define RMT_MEM_WADDR_EX_CH1_S  0
 
 #define RMT_CH2STATUS_REG          (DR_REG_RMT_BASE + 0x0068)
 /* RMT_STATUS_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
@@ -1011,6 +1119,60 @@
 #define RMT_STATUS_CH2_M  ((RMT_STATUS_CH2_V)<<(RMT_STATUS_CH2_S))
 #define RMT_STATUS_CH2_V  0xFFFFFFFF
 #define RMT_STATUS_CH2_S  0
+/* RMT_APB_MEM_RD_ERR_CH2 : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: The apb read memory status bit for channel2 turns to
+ high level when the apb read address exceeds the configuration range.*/
+#define RMT_APB_MEM_RD_ERR_CH2 (BIT(31))
+#define RMT_APB_MEM_RD_ERR_CH2_M  ((RMT_APB_MEM_RD_ERR_CH2_V)<<(RMT_APB_MEM_RD_ERR_CH2_S))
+#define RMT_APB_MEM_RD_ERR_CH2_V  0x1
+#define RMT_APB_MEM_RD_ERR_CH2_S  31
+/* RMT_APB_MEM_WR_ERR_CH2 : RO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: The apb write memory status bit for channel2 turns to
+ high level when the apb write address exceeds the configuration range.*/
+#define RMT_APB_MEM_WR_ERR_CH2 (BIT(30))
+#define RMT_APB_MEM_WR_ERR_CH2_M  ((RMT_APB_MEM_WR_ERR_CH2_V)<<(RMT_APB_MEM_WR_ERR_CH2_S))
+#define RMT_APB_MEM_WR_ERR_CH2_V  0x1
+#define RMT_APB_MEM_WR_ERR_CH2_S  30
+/* RMT_MEM_EMPTY_CH2 : RO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: The memory empty status bit for channel2. in acyclic mode,
+ this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.*/
+#define RMT_MEM_EMPTY_CH2 (BIT(29))
+#define RMT_MEM_EMPTY_CH2_M  ((RMT_MEM_EMPTY_CH2_V)<<(RMT_MEM_EMPTY_CH2_S))
+#define RMT_MEM_EMPTY_CH2_V  0x1
+#define RMT_MEM_EMPTY_CH2_S  29
+/* RMT_MEM_FULL_CH2 : RO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: The memory full status bit for channel2 turns to high level
+ when mem_waddr_ex is greater than or equal to the configuration range.*/
+#define RMT_MEM_FULL_CH2 (BIT(28))
+#define RMT_MEM_FULL_CH2_M  ((RMT_MEM_FULL_CH2_V)<<(RMT_MEM_FULL_CH2_S))
+#define RMT_MEM_FULL_CH2_V  0x1
+#define RMT_MEM_FULL_CH2_S  28
+/* RMT_MEM_OWNER_ERR_CH2 : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: When channel2 is configured for receive mode, this bit will turn to high level
+ if rmt_mem_owner register is not set to 1.*/
+#define RMT_MEM_OWNER_ERR_CH2 (BIT(27))
+#define RMT_MEM_OWNER_ERR_CH2_M  ((RMT_MEM_OWNER_ERR_CH2_V)<<(RMT_MEM_OWNER_ERR_CH2_S))
+#define RMT_MEM_OWNER_ERR_CH2_V  0x1
+#define RMT_MEM_OWNER_ERR_CH2_S  27
+/* RMT_STATE_CH2 : RO ;bitpos:[26:24] ;default: 3'h0 ; */
+/*description: The channel2 state machine status register.
+3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.*/
+#define RMT_STATE_CH2 0x07000000
+#define RMT_STATE_CH2_M  ((RMT_STATE_CH2_V)<<(RMT_STATE_CH2_S))
+#define RMT_STATE_CH2_V  0x7
+#define RMT_STATE_CH2_S  24
+/* RMT_MEM_RADDR_EX_CH2 : RO ;bitpos:[21:12] ;default: 10'h0 ; */
+/*description: The current memory write address of channel2.*/
+#define RMT_MEM_RADDR_EX_CH2 0x003ff000
+#define RMT_MEM_RADDR_EX_CH2_M  ((RMT_MEM_RADDR_EX_CH2_V)<<(RMT_MEM_RADDR_EX_CH2_S))
+#define RMT_MEM_RADDR_EX_CH2_V  0x3ff
+#define RMT_MEM_RADDR_EX_CH2_S  12
+/* RMT_MEM_WADDR_EX_CH2 : RO ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: The current memory read address of channel2.*/
+#define RMT_MEM_WADDR_EX_CH2 0x000003ff
+#define RMT_MEM_WADDR_EX_CH2_M  ((RMT_MEM_WADDR_EX_CH2_V)<<(RMT_MEM_WADDR_EX_CH2_S))
+#define RMT_MEM_WADDR_EX_CH2_V  0x3ff
+#define RMT_MEM_WADDR_EX_CH2_S  0
 
 #define RMT_CH3STATUS_REG          (DR_REG_RMT_BASE + 0x006c)
 /* RMT_STATUS_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
@@ -1019,6 +1181,60 @@
 #define RMT_STATUS_CH3_M  ((RMT_STATUS_CH3_V)<<(RMT_STATUS_CH3_S))
 #define RMT_STATUS_CH3_V  0xFFFFFFFF
 #define RMT_STATUS_CH3_S  0
+/* RMT_APB_MEM_RD_ERR_CH3 : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: The apb read memory status bit for channel3 turns to
+ high level when the apb read address exceeds the configuration range.*/
+#define RMT_APB_MEM_RD_ERR_CH3 (BIT(31))
+#define RMT_APB_MEM_RD_ERR_CH3_M  ((RMT_APB_MEM_RD_ERR_CH3_V)<<(RMT_APB_MEM_RD_ERR_CH3_S))
+#define RMT_APB_MEM_RD_ERR_CH3_V  0x1
+#define RMT_APB_MEM_RD_ERR_CH3_S  31
+/* RMT_APB_MEM_WR_ERR_CH3 : RO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: The apb write memory status bit for channel3 turns to
+ high level when the apb write address exceeds the configuration range.*/
+#define RMT_APB_MEM_WR_ERR_CH3 (BIT(30))
+#define RMT_APB_MEM_WR_ERR_CH3_M  ((RMT_APB_MEM_WR_ERR_CH3_V)<<(RMT_APB_MEM_WR_ERR_CH3_S))
+#define RMT_APB_MEM_WR_ERR_CH3_V  0x1
+#define RMT_APB_MEM_WR_ERR_CH3_S  30
+/* RMT_MEM_EMPTY_CH3 : RO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: The memory empty status bit for channel3. in acyclic mode,
+ this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.*/
+#define RMT_MEM_EMPTY_CH3 (BIT(29))
+#define RMT_MEM_EMPTY_CH3_M  ((RMT_MEM_EMPTY_CH3_V)<<(RMT_MEM_EMPTY_CH3_S))
+#define RMT_MEM_EMPTY_CH3_V  0x1
+#define RMT_MEM_EMPTY_CH3_S  29
+/* RMT_MEM_FULL_CH3 : RO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: The memory full status bit for channel3 turns to high level
+ when mem_waddr_ex is greater than or equal to the configuration range.*/
+#define RMT_MEM_FULL_CH3 (BIT(28))
+#define RMT_MEM_FULL_CH3_M  ((RMT_MEM_FULL_CH3_V)<<(RMT_MEM_FULL_CH3_S))
+#define RMT_MEM_FULL_CH3_V  0x1
+#define RMT_MEM_FULL_CH3_S  28
+/* RMT_MEM_OWNER_ERR_CH3 : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: When channel3 is configured for receive mode, this bit will turn to high level
+ if rmt_mem_owner register is not set to 1.*/
+#define RMT_MEM_OWNER_ERR_CH3 (BIT(27))
+#define RMT_MEM_OWNER_ERR_CH3_M  ((RMT_MEM_OWNER_ERR_CH3_V)<<(RMT_MEM_OWNER_ERR_CH3_S))
+#define RMT_MEM_OWNER_ERR_CH3_V  0x1
+#define RMT_MEM_OWNER_ERR_CH3_S  27
+/* RMT_STATE_CH3 : RO ;bitpos:[26:24] ;default: 3'h0 ; */
+/*description: The channel3 state machine status register.
+3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.*/
+#define RMT_STATE_CH3 0x07000000
+#define RMT_STATE_CH3_M  ((RMT_STATE_CH3_V)<<(RMT_STATE_CH3_S))
+#define RMT_STATE_CH3_V  0x7
+#define RMT_STATE_CH3_S  24
+/* RMT_MEM_RADDR_EX_CH3 : RO ;bitpos:[21:12] ;default: 10'h0 ; */
+/*description: The current memory write address of channel3.*/
+#define RMT_MEM_RADDR_EX_CH3 0x003ff000
+#define RMT_MEM_RADDR_EX_CH3_M  ((RMT_MEM_RADDR_EX_CH3_V)<<(RMT_MEM_RADDR_EX_CH3_S))
+#define RMT_MEM_RADDR_EX_CH3_V  0x3ff
+#define RMT_MEM_RADDR_EX_CH3_S  12
+/* RMT_MEM_WADDR_EX_CH3 : RO ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: The current memory read address of channel3.*/
+#define RMT_MEM_WADDR_EX_CH3 0x000003ff
+#define RMT_MEM_WADDR_EX_CH3_M  ((RMT_MEM_WADDR_EX_CH3_V)<<(RMT_MEM_WADDR_EX_CH3_S))
+#define RMT_MEM_WADDR_EX_CH3_V  0x3ff
+#define RMT_MEM_WADDR_EX_CH3_S  0
 
 #define RMT_CH4STATUS_REG          (DR_REG_RMT_BASE + 0x0070)
 /* RMT_STATUS_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
@@ -1027,6 +1243,60 @@
 #define RMT_STATUS_CH4_M  ((RMT_STATUS_CH4_V)<<(RMT_STATUS_CH4_S))
 #define RMT_STATUS_CH4_V  0xFFFFFFFF
 #define RMT_STATUS_CH4_S  0
+/* RMT_APB_MEM_RD_ERR_CH4 : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: The apb read memory status bit for channel4 turns to
+ high level when the apb read address exceeds the configuration range.*/
+#define RMT_APB_MEM_RD_ERR_CH4 (BIT(31))
+#define RMT_APB_MEM_RD_ERR_CH4_M  ((RMT_APB_MEM_RD_ERR_CH4_V)<<(RMT_APB_MEM_RD_ERR_CH4_S))
+#define RMT_APB_MEM_RD_ERR_CH4_V  0x1
+#define RMT_APB_MEM_RD_ERR_CH4_S  31
+/* RMT_APB_MEM_WR_ERR_CH4 : RO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: The apb write memory status bit for channel4 turns to
+ high level when the apb write address exceeds the configuration range.*/
+#define RMT_APB_MEM_WR_ERR_CH4 (BIT(30))
+#define RMT_APB_MEM_WR_ERR_CH4_M  ((RMT_APB_MEM_WR_ERR_CH4_V)<<(RMT_APB_MEM_WR_ERR_CH4_S))
+#define RMT_APB_MEM_WR_ERR_CH4_V  0x1
+#define RMT_APB_MEM_WR_ERR_CH4_S  30
+/* RMT_MEM_EMPTY_CH4 : RO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: The memory empty status bit for channel4. in acyclic mode,
+ this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.*/
+#define RMT_MEM_EMPTY_CH4 (BIT(29))
+#define RMT_MEM_EMPTY_CH4_M  ((RMT_MEM_EMPTY_CH4_V)<<(RMT_MEM_EMPTY_CH4_S))
+#define RMT_MEM_EMPTY_CH4_V  0x1
+#define RMT_MEM_EMPTY_CH4_S  29
+/* RMT_MEM_FULL_CH4 : RO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: The memory full status bit for channel4 turns to high level
+ when mem_waddr_ex is greater than or equal to the configuration range.*/
+#define RMT_MEM_FULL_CH4 (BIT(28))
+#define RMT_MEM_FULL_CH4_M  ((RMT_MEM_FULL_CH4_V)<<(RMT_MEM_FULL_CH4_S))
+#define RMT_MEM_FULL_CH4_V  0x1
+#define RMT_MEM_FULL_CH4_S  28
+/* RMT_MEM_OWNER_ERR_CH4 : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: When channel4 is configured for receive mode, this bit will turn to high level
+ if rmt_mem_owner register is not set to 1.*/
+#define RMT_MEM_OWNER_ERR_CH4 (BIT(27))
+#define RMT_MEM_OWNER_ERR_CH4_M  ((RMT_MEM_OWNER_ERR_CH4_V)<<(RMT_MEM_OWNER_ERR_CH4_S))
+#define RMT_MEM_OWNER_ERR_CH4_V  0x1
+#define RMT_MEM_OWNER_ERR_CH4_S  27
+/* RMT_STATE_CH4 : RO ;bitpos:[26:24] ;default: 3'h0 ; */
+/*description: The channel4 state machine status register.
+3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.*/
+#define RMT_STATE_CH4 0x07000000
+#define RMT_STATE_CH4_M  ((RMT_STATE_CH4_V)<<(RMT_STATE_CH4_S))
+#define RMT_STATE_CH4_V  0x7
+#define RMT_STATE_CH4_S  24
+/* RMT_MEM_RADDR_EX_CH4 : RO ;bitpos:[21:12] ;default: 10'h0 ; */
+/*description: The current memory write address of channel4.*/
+#define RMT_MEM_RADDR_EX_CH4 0x003ff000
+#define RMT_MEM_RADDR_EX_CH4_M  ((RMT_MEM_RADDR_EX_CH4_V)<<(RMT_MEM_RADDR_EX_CH4_S))
+#define RMT_MEM_RADDR_EX_CH4_V  0x3ff
+#define RMT_MEM_RADDR_EX_CH4_S  12
+/* RMT_MEM_WADDR_EX_CH4 : RO ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: The current memory read address of channel4.*/
+#define RMT_MEM_WADDR_EX_CH4 0x000003ff
+#define RMT_MEM_WADDR_EX_CH4_M  ((RMT_MEM_WADDR_EX_CH4_V)<<(RMT_MEM_WADDR_EX_CH4_S))
+#define RMT_MEM_WADDR_EX_CH4_V  0x3ff
+#define RMT_MEM_WADDR_EX_CH4_S  0
 
 #define RMT_CH5STATUS_REG          (DR_REG_RMT_BASE + 0x0074)
 /* RMT_STATUS_CH5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
@@ -1035,6 +1305,60 @@
 #define RMT_STATUS_CH5_M  ((RMT_STATUS_CH5_V)<<(RMT_STATUS_CH5_S))
 #define RMT_STATUS_CH5_V  0xFFFFFFFF
 #define RMT_STATUS_CH5_S  0
+/* RMT_APB_MEM_RD_ERR_CH5 : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: The apb read memory status bit for channel5 turns to
+ high level when the apb read address exceeds the configuration range.*/
+#define RMT_APB_MEM_RD_ERR_CH5 (BIT(31))
+#define RMT_APB_MEM_RD_ERR_CH5_M  ((RMT_APB_MEM_RD_ERR_CH5_V)<<(RMT_APB_MEM_RD_ERR_CH5_S))
+#define RMT_APB_MEM_RD_ERR_CH5_V  0x1
+#define RMT_APB_MEM_RD_ERR_CH5_S  31
+/* RMT_APB_MEM_WR_ERR_CH5 : RO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: The apb write memory status bit for channel5 turns to
+ high level when the apb write address exceeds the configuration range.*/
+#define RMT_APB_MEM_WR_ERR_CH5 (BIT(30))
+#define RMT_APB_MEM_WR_ERR_CH5_M  ((RMT_APB_MEM_WR_ERR_CH5_V)<<(RMT_APB_MEM_WR_ERR_CH5_S))
+#define RMT_APB_MEM_WR_ERR_CH5_V  0x1
+#define RMT_APB_MEM_WR_ERR_CH5_S  30
+/* RMT_MEM_EMPTY_CH5 : RO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: The memory empty status bit for channel5. in acyclic mode,
+ this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.*/
+#define RMT_MEM_EMPTY_CH5 (BIT(29))
+#define RMT_MEM_EMPTY_CH5_M  ((RMT_MEM_EMPTY_CH5_V)<<(RMT_MEM_EMPTY_CH5_S))
+#define RMT_MEM_EMPTY_CH5_V  0x1
+#define RMT_MEM_EMPTY_CH5_S  29
+/* RMT_MEM_FULL_CH5 : RO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: The memory full status bit for channel5 turns to high level
+ when mem_waddr_ex is greater than or equal to the configuration range.*/
+#define RMT_MEM_FULL_CH5 (BIT(28))
+#define RMT_MEM_FULL_CH5_M  ((RMT_MEM_FULL_CH5_V)<<(RMT_MEM_FULL_CH5_S))
+#define RMT_MEM_FULL_CH5_V  0x1
+#define RMT_MEM_FULL_CH5_S  28
+/* RMT_MEM_OWNER_ERR_CH5 : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: When channel5 is configured for receive mode, this bit will turn to high level
+ if rmt_mem_owner register is not set to 1.*/
+#define RMT_MEM_OWNER_ERR_CH5 (BIT(27))
+#define RMT_MEM_OWNER_ERR_CH5_M  ((RMT_MEM_OWNER_ERR_CH5_V)<<(RMT_MEM_OWNER_ERR_CH5_S))
+#define RMT_MEM_OWNER_ERR_CH5_V  0x1
+#define RMT_MEM_OWNER_ERR_CH5_S  27
+/* RMT_STATE_CH5 : RO ;bitpos:[26:24] ;default: 3'h0 ; */
+/*description: The channel5 state machine status register.
+3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.*/
+#define RMT_STATE_CH5 0x07000000
+#define RMT_STATE_CH5_M  ((RMT_STATE_CH5_V)<<(RMT_STATE_CH5_S))
+#define RMT_STATE_CH5_V  0x7
+#define RMT_STATE_CH5_S  24
+/* RMT_MEM_RADDR_EX_CH5 : RO ;bitpos:[21:12] ;default: 10'h0 ; */
+/*description: The current memory write address of channel5.*/
+#define RMT_MEM_RADDR_EX_CH5 0x003ff000
+#define RMT_MEM_RADDR_EX_CH5_M  ((RMT_MEM_RADDR_EX_CH5_V)<<(RMT_MEM_RADDR_EX_CH5_S))
+#define RMT_MEM_RADDR_EX_CH5_V  0x3ff
+#define RMT_MEM_RADDR_EX_CH5_S  12
+/* RMT_MEM_WADDR_EX_CH5 : RO ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: The current memory read address of channel5.*/
+#define RMT_MEM_WADDR_EX_CH5 0x000003ff
+#define RMT_MEM_WADDR_EX_CH5_M  ((RMT_MEM_WADDR_EX_CH5_V)<<(RMT_MEM_WADDR_EX_CH5_S))
+#define RMT_MEM_WADDR_EX_CH5_V  0x3ff
+#define RMT_MEM_WADDR_EX_CH5_S  0
 
 #define RMT_CH6STATUS_REG          (DR_REG_RMT_BASE + 0x0078)
 /* RMT_STATUS_CH6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
@@ -1043,6 +1367,60 @@
 #define RMT_STATUS_CH6_M  ((RMT_STATUS_CH6_V)<<(RMT_STATUS_CH6_S))
 #define RMT_STATUS_CH6_V  0xFFFFFFFF
 #define RMT_STATUS_CH6_S  0
+/* RMT_APB_MEM_RD_ERR_CH6 : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: The apb read memory status bit for channel6 turns to
+ high level when the apb read address exceeds the configuration range.*/
+#define RMT_APB_MEM_RD_ERR_CH6 (BIT(31))
+#define RMT_APB_MEM_RD_ERR_CH6_M  ((RMT_APB_MEM_RD_ERR_CH6_V)<<(RMT_APB_MEM_RD_ERR_CH6_S))
+#define RMT_APB_MEM_RD_ERR_CH6_V  0x1
+#define RMT_APB_MEM_RD_ERR_CH6_S  31
+/* RMT_APB_MEM_WR_ERR_CH6 : RO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: The apb write memory status bit for channel6 turns to
+ high level when the apb write address exceeds the configuration range.*/
+#define RMT_APB_MEM_WR_ERR_CH6 (BIT(30))
+#define RMT_APB_MEM_WR_ERR_CH6_M  ((RMT_APB_MEM_WR_ERR_CH6_V)<<(RMT_APB_MEM_WR_ERR_CH6_S))
+#define RMT_APB_MEM_WR_ERR_CH6_V  0x1
+#define RMT_APB_MEM_WR_ERR_CH6_S  30
+/* RMT_MEM_EMPTY_CH6 : RO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: The memory empty status bit for channel6. in acyclic mode,
+ this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.*/
+#define RMT_MEM_EMPTY_CH6 (BIT(29))
+#define RMT_MEM_EMPTY_CH6_M  ((RMT_MEM_EMPTY_CH6_V)<<(RMT_MEM_EMPTY_CH6_S))
+#define RMT_MEM_EMPTY_CH6_V  0x1
+#define RMT_MEM_EMPTY_CH6_S  29
+/* RMT_MEM_FULL_CH6 : RO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: The memory full status bit for channel6 turns to high level
+ when mem_waddr_ex is greater than or equal to the configuration range.*/
+#define RMT_MEM_FULL_CH6 (BIT(28))
+#define RMT_MEM_FULL_CH6_M  ((RMT_MEM_FULL_CH6_V)<<(RMT_MEM_FULL_CH6_S))
+#define RMT_MEM_FULL_CH6_V  0x1
+#define RMT_MEM_FULL_CH6_S  28
+/* RMT_MEM_OWNER_ERR_CH6 : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: When channel6 is configured for receive mode, this bit will turn to high level
+ if rmt_mem_owner register is not set to 1.*/
+#define RMT_MEM_OWNER_ERR_CH6 (BIT(27))
+#define RMT_MEM_OWNER_ERR_CH6_M  ((RMT_MEM_OWNER_ERR_CH6_V)<<(RMT_MEM_OWNER_ERR_CH6_S))
+#define RMT_MEM_OWNER_ERR_CH6_V  0x1
+#define RMT_MEM_OWNER_ERR_CH6_S  27
+/* RMT_STATE_CH6 : RO ;bitpos:[26:24] ;default: 3'h0 ; */
+/*description: The channel6 state machine status register.
+3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.*/
+#define RMT_STATE_CH6 0x07000000
+#define RMT_STATE_CH6_M  ((RMT_STATE_CH6_V)<<(RMT_STATE_CH6_S))
+#define RMT_STATE_CH6_V  0x7
+#define RMT_STATE_CH6_S  24
+/* RMT_MEM_RADDR_EX_CH6 : RO ;bitpos:[21:12] ;default: 10'h0 ; */
+/*description: The current memory write address of channel6.*/
+#define RMT_MEM_RADDR_EX_CH6 0x003ff000
+#define RMT_MEM_RADDR_EX_CH6_M  ((RMT_MEM_RADDR_EX_CH6_V)<<(RMT_MEM_RADDR_EX_CH6_S))
+#define RMT_MEM_RADDR_EX_CH6_V  0x3ff
+#define RMT_MEM_RADDR_EX_CH6_S  12
+/* RMT_MEM_WADDR_EX_CH6 : RO ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: The current memory read address of channel6.*/
+#define RMT_MEM_WADDR_EX_CH6 0x000003ff
+#define RMT_MEM_WADDR_EX_CH6_M  ((RMT_MEM_WADDR_EX_CH6_V)<<(RMT_MEM_WADDR_EX_CH6_S))
+#define RMT_MEM_WADDR_EX_CH6_V  0x3ff
+#define RMT_MEM_WADDR_EX_CH6_S  0
 
 #define RMT_CH7STATUS_REG          (DR_REG_RMT_BASE + 0x007c)
 /* RMT_STATUS_CH7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
@@ -1051,6 +1429,60 @@
 #define RMT_STATUS_CH7_M  ((RMT_STATUS_CH7_V)<<(RMT_STATUS_CH7_S))
 #define RMT_STATUS_CH7_V  0xFFFFFFFF
 #define RMT_STATUS_CH7_S  0
+/* RMT_APB_MEM_RD_ERR_CH7 : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: The apb read memory status bit for channel7 turns to
+ high level when the apb read address exceeds the configuration range.*/
+#define RMT_APB_MEM_RD_ERR_CH7 (BIT(31))
+#define RMT_APB_MEM_RD_ERR_CH7_M  ((RMT_APB_MEM_RD_ERR_CH7_V)<<(RMT_APB_MEM_RD_ERR_CH7_S))
+#define RMT_APB_MEM_RD_ERR_CH7_V  0x1
+#define RMT_APB_MEM_RD_ERR_CH7_S  31
+/* RMT_APB_MEM_WR_ERR_CH7 : RO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: The apb write memory status bit for channel7 turns to
+ high level when the apb write address exceeds the configuration range.*/
+#define RMT_APB_MEM_WR_ERR_CH7 (BIT(30))
+#define RMT_APB_MEM_WR_ERR_CH7_M  ((RMT_APB_MEM_WR_ERR_CH7_V)<<(RMT_APB_MEM_WR_ERR_CH7_S))
+#define RMT_APB_MEM_WR_ERR_CH7_V  0x1
+#define RMT_APB_MEM_WR_ERR_CH7_S  30
+/* RMT_MEM_EMPTY_CH7 : RO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: The memory empty status bit for channel7. in acyclic mode,
+ this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.*/
+#define RMT_MEM_EMPTY_CH7 (BIT(29))
+#define RMT_MEM_EMPTY_CH7_M  ((RMT_MEM_EMPTY_CH7_V)<<(RMT_MEM_EMPTY_CH7_S))
+#define RMT_MEM_EMPTY_CH7_V  0x1
+#define RMT_MEM_EMPTY_CH7_S  29
+/* RMT_MEM_FULL_CH7 : RO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: The memory full status bit for channel7 turns to high level
+ when mem_waddr_ex is greater than or equal to the configuration range.*/
+#define RMT_MEM_FULL_CH7 (BIT(28))
+#define RMT_MEM_FULL_CH7_M  ((RMT_MEM_FULL_CH7_V)<<(RMT_MEM_FULL_CH7_S))
+#define RMT_MEM_FULL_CH7_V  0x1
+#define RMT_MEM_FULL_CH7_S  28
+/* RMT_MEM_OWNER_ERR_CH7 : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: When channel7 is configured for receive mode, this bit will turn to high level
+ if rmt_mem_owner register is not set to 1.*/
+#define RMT_MEM_OWNER_ERR_CH7 (BIT(27))
+#define RMT_MEM_OWNER_ERR_CH7_M  ((RMT_MEM_OWNER_ERR_CH7_V)<<(RMT_MEM_OWNER_ERR_CH7_S))
+#define RMT_MEM_OWNER_ERR_CH7_V  0x1
+#define RMT_MEM_OWNER_ERR_CH7_S  27
+/* RMT_STATE_CH7 : RO ;bitpos:[26:24] ;default: 3'h0 ; */
+/*description: The channel7 state machine status register.
+3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.*/
+#define RMT_STATE_CH7 0x07000000
+#define RMT_STATE_CH7_M  ((RMT_STATE_CH7_V)<<(RMT_STATE_CH7_S))
+#define RMT_STATE_CH7_V  0x7
+#define RMT_STATE_CH7_S  24
+/* RMT_MEM_RADDR_EX_CH7 : RO ;bitpos:[21:12] ;default: 10'h0 ; */
+/*description: The current memory write address of channel7.*/
+#define RMT_MEM_RADDR_EX_CH7 0x003ff000
+#define RMT_MEM_RADDR_EX_CH7_M  ((RMT_MEM_RADDR_EX_CH7_V)<<(RMT_MEM_RADDR_EX_CH7_S))
+#define RMT_MEM_RADDR_EX_CH7_V  0x3ff
+#define RMT_MEM_RADDR_EX_CH7_S  12
+/* RMT_MEM_WADDR_EX_CH7 : RO ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: The current memory read address of channel7.*/
+#define RMT_MEM_WADDR_EX_CH7 0x000003ff
+#define RMT_MEM_WADDR_EX_CH7_M  ((RMT_MEM_WADDR_EX_CH7_V)<<(RMT_MEM_WADDR_EX_CH7_S))
+#define RMT_MEM_WADDR_EX_CH7_V  0x3ff
+#define RMT_MEM_WADDR_EX_CH7_S  0
 
 #define RMT_CH0ADDR_REG          (DR_REG_RMT_BASE + 0x0080)
 /* RMT_APB_MEM_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
@@ -1118,8 +1550,8 @@
 
 #define RMT_INT_RAW_REG          (DR_REG_RMT_BASE + 0x00a0)
 /* RMT_CH7_TX_THR_EVENT_INT_RAW : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for channel 7 turns to high level when
+/*description: The interrupt raw bit for channel7 turns to high level when
- transmitter in channle7  have send datas more than  reg_rmt_tx_lim_ch7  after detecting this interrupt  software can updata the old datas with new datas.*/
+ transmitter in channle 7  have send datas more than  reg_rmt_tx_lim_ch7  after detecting this interrupt  software can updata the old datas with new datas.*/
 #define RMT_CH7_TX_THR_EVENT_INT_RAW  (BIT(31))
 #define RMT_CH7_TX_THR_EVENT_INT_RAW_M  (BIT(31))
 #define RMT_CH7_TX_THR_EVENT_INT_RAW_V  0x1

tools/sdk/sdkconfig

@@ -446,6 +446,7 @@ CONFIG_FATFS_API_ENCODING_UTF_8=
 CONFIG_FATFS_FS_LOCK=0
 CONFIG_FATFS_TIMEOUT_MS=10000
 CONFIG_FATFS_PER_FILE_CACHE=y
+CONFIG_FATFS_ALLOC_PREFER_EXTRAM=y
 
 #
 # Modbus configuration
@@ -626,7 +627,11 @@ CONFIG_MBEDTLS_TLS_ENABLED=y
 #
 # TLS Key Exchange Methods
 #
-CONFIG_MBEDTLS_PSK_MODES=
+CONFIG_MBEDTLS_PSK_MODES=y
+CONFIG_MBEDTLS_KEY_EXCHANGE_PSK=y
+CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_PSK=y
+CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_PSK=y
+CONFIG_MBEDTLS_KEY_EXCHANGE_RSA_PSK=y
 CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y
 CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_RSA=y
 CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y