334 lines
13 KiB
C
334 lines
13 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "esp32-hal.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/semphr.h"
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#include "esp32-hal-matrix.h"
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#include "soc/ledc_reg.h"
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#include "soc/ledc_struct.h"
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#include "driver/periph_ctrl.h"
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#include "esp_system.h"
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#ifdef ESP_IDF_VERSION_MAJOR // IDF 4+
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#if CONFIG_IDF_TARGET_ESP32 // ESP32/PICO-D4
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#include "soc/dport_reg.h"
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#include "esp32/rom/ets_sys.h"
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#define LAST_CHAN (15)
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "soc/dport_reg.h"
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#include "esp32s2/rom/ets_sys.h"
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#define LAST_CHAN (7)
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#define LEDC_DIV_NUM_HSTIMER0_V LEDC_CLK_DIV_LSTIMER0_V
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#elif CONFIG_IDF_TARGET_ESP32C3
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#include "esp32c3/rom/ets_sys.h"
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#define LAST_CHAN (7)
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#define LEDC_DIV_NUM_HSTIMER0_V LEDC_CLK_DIV_LSTIMER0_V
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#else
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#error Target CONFIG_IDF_TARGET is not supported
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#endif
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#else // ESP32 Before IDF 4.0
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#include "rom/ets_sys.h"
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#endif
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#if CONFIG_DISABLE_HAL_LOCKS
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#define LEDC_MUTEX_LOCK()
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#define LEDC_MUTEX_UNLOCK()
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#else
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#define LEDC_MUTEX_LOCK() do {} while (xSemaphoreTake(_ledc_sys_lock, portMAX_DELAY) != pdPASS)
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#define LEDC_MUTEX_UNLOCK() xSemaphoreGive(_ledc_sys_lock)
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xSemaphoreHandle _ledc_sys_lock = NULL;
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#endif
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/*
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* LEDC Chan to Group/Channel/Timer Mapping
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** ledc: 0 => Group: 0, Channel: 0, Timer: 0
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** ledc: 1 => Group: 0, Channel: 1, Timer: 0
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** ledc: 2 => Group: 0, Channel: 2, Timer: 1
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** ledc: 3 => Group: 0, Channel: 3, Timer: 1
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** ledc: 4 => Group: 0, Channel: 4, Timer: 2
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** ledc: 5 => Group: 0, Channel: 5, Timer: 2
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** ledc: 6 => Group: 0, Channel: 6, Timer: 3
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** ledc: 7 => Group: 0, Channel: 7, Timer: 3
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** ledc: 8 => Group: 1, Channel: 0, Timer: 0
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** ledc: 9 => Group: 1, Channel: 1, Timer: 0
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** ledc: 10 => Group: 1, Channel: 2, Timer: 1
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** ledc: 11 => Group: 1, Channel: 3, Timer: 1
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** ledc: 12 => Group: 1, Channel: 4, Timer: 2
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** ledc: 13 => Group: 1, Channel: 5, Timer: 2
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** ledc: 14 => Group: 1, Channel: 6, Timer: 3
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** ledc: 15 => Group: 1, Channel: 7, Timer: 3
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*/
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#define LEDC_CHAN(g,c) LEDC.channel_group[(g)].channel[(c)]
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#define LEDC_TIMER(g,t) LEDC.timer_group[(g)].timer[(t)]
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static void _on_apb_change(void * arg, apb_change_ev_t ev_type, uint32_t old_apb, uint32_t new_apb){
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if(ev_type == APB_AFTER_CHANGE && old_apb != new_apb){
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uint16_t iarg = *(uint16_t*)arg;
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uint8_t chan = 0;
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old_apb /= 1000000;
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new_apb /= 1000000;
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while(iarg){ // run though all active channels, adjusting timing configurations
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if(iarg & 1) {// this channel is active
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uint8_t group=(chan/8), timer=((chan/2)%4);
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if(LEDC_TIMER(group, timer).conf.tick_sel){
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LEDC_MUTEX_LOCK();
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uint32_t old_div = LEDC_TIMER(group, timer).conf.clock_divider;
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uint32_t div_num = (new_apb * old_div) / old_apb;
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if(div_num > LEDC_DIV_NUM_HSTIMER0_V){
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div_num = ((REF_CLK_FREQ /1000000) * old_div) / old_apb;
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if(div_num > LEDC_DIV_NUM_HSTIMER0_V) {
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div_num = LEDC_DIV_NUM_HSTIMER0_V;//lowest clock possible
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}
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LEDC_TIMER(group, timer).conf.tick_sel = 0;
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} else if(div_num < 256) {
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div_num = 256;//highest clock possible
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}
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LEDC_TIMER(group, timer).conf.clock_divider = div_num;
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LEDC_MUTEX_UNLOCK();
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}
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else {
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log_d("using REF_CLK chan=%d",chan);
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}
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}
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iarg = iarg >> 1;
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chan++;
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}
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}
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}
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//uint32_t frequency = (80MHz or 1MHz)/((div_num / 256.0)*(1 << bit_num));
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static void _ledcSetupTimer(uint8_t chan, uint32_t div_num, uint8_t bit_num, bool apb_clk)
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{
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uint8_t group=(chan/8), timer=((chan/2)%4);
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static bool tHasStarted = false;
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static uint16_t _activeChannels = 0;
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#if CONFIG_IDF_TARGET_ESP32S2
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// ESP32-S2 TRM v1.0 on Page 789 -> BIT LEDC_TICK_SEL_TIMERx is 0 for LEDC_PWM_CLK and 1 for REF_TICK
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apb_clk = 0;
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#endif
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if(!tHasStarted) {
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tHasStarted = true;
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periph_module_enable(PERIPH_LEDC_MODULE);
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LEDC.conf.apb_clk_sel = 1;//LS use apb clock
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addApbChangeCallback((void*)&_activeChannels, _on_apb_change);
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#if !CONFIG_DISABLE_HAL_LOCKS
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_ledc_sys_lock = xSemaphoreCreateMutex();
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#endif
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}
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LEDC_MUTEX_LOCK();
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LEDC_TIMER(group, timer).conf.clock_divider = div_num;//18 bit (10.8) This register is used to configure parameter for divider in timer the least significant eight bits represent the decimal part.
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LEDC_TIMER(group, timer).conf.duty_resolution = bit_num;//5 bit This register controls the range of the counter in timer. the counter range is [0 2**bit_num] the max bit width for counter is 20.
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LEDC_TIMER(group, timer).conf.tick_sel = apb_clk;//apb clock
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#if CONFIG_IDF_TARGET_ESP32
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if(group) {
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#endif
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LEDC_TIMER(group, timer).conf.low_speed_update = 1;//This bit is only useful for low speed timer channels, reserved for high speed timers
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#if CONFIG_IDF_TARGET_ESP32
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}
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#endif
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LEDC_TIMER(group, timer).conf.pause = 0;
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LEDC_TIMER(group, timer).conf.rst = 1;//This bit is used to reset timer the counter will be 0 after reset.
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LEDC_TIMER(group, timer).conf.rst = 0;
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LEDC_MUTEX_UNLOCK();
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_activeChannels |= (1 << chan); // mark as active for APB callback
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}
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//max div_num 0x3FFFF (262143)
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//max bit_num 0x1F (31)
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static double _ledcSetupTimerFreq(uint8_t chan, double freq, uint8_t bit_num)
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{
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uint64_t clk_freq = getApbFrequency();
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clk_freq <<= 8;//div_num is 8 bit decimal
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