124 lines
4.4 KiB
C
124 lines
4.4 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_SYSCON_STRUCT_H_
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#define _SOC_SYSCON_STRUCT_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef volatile struct {
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union {
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struct {
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uint32_t pre_div: 10;
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uint32_t clk_320m_en: 1;
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uint32_t clk_en: 1;
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uint32_t rst_tick: 1;
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uint32_t quick_clk_chng: 1;
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uint32_t reserved14: 18;
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};
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uint32_t val;
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}clk_conf;
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union {
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struct {
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uint32_t xtal_tick: 8;
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uint32_t reserved8: 24;
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};
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uint32_t val;
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}xtal_tick_conf;
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union {
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struct {
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uint32_t pll_tick: 8;
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uint32_t reserved8: 24;
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};
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uint32_t val;
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}pll_tick_conf;
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union {
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struct {
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uint32_t ck8m_tick: 8;
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uint32_t reserved8: 24;
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};
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uint32_t val;
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}ck8m_tick_conf;
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union {
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struct {
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uint32_t start_force: 1;
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uint32_t start: 1;
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uint32_t sar2_mux: 1; /*1: SAR ADC2 is controlled by DIG ADC2 CTRL 0: SAR ADC2 is controlled by PWDET CTRL*/
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uint32_t work_mode: 2; /*0: single mode 1: double mode 2: alternate mode*/
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uint32_t sar_sel: 1; /*0: SAR1 1: SAR2 only work for single SAR mode*/
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uint32_t sar_clk_gated: 1;
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uint32_t sar_clk_div: 8; /*SAR clock divider*/
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uint32_t sar1_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/
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uint32_t sar2_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/
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uint32_t sar1_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC1 CTRL*/
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uint32_t sar2_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC2 CTRL*/
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uint32_t data_sar_sel: 1; /*1: sar_sel will be coded by the MSB of the 16-bit output data in this case the resolution should not be larger than 11 bits.*/
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uint32_t data_to_i2s: 1; /*1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix*/
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uint32_t reserved27: 5;
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};
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uint32_t val;
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}saradc_ctrl;
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union {
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struct {
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uint32_t meas_num_limit: 1;
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uint32_t max_meas_num: 8; /*max conversion number*/
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uint32_t sar1_inv: 1; /*1: data to DIG ADC1 CTRL is inverted otherwise not*/
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uint32_t sar2_inv: 1; /*1: data to DIG ADC2 CTRL is inverted otherwise not*/
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uint32_t reserved11: 21;
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};
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uint32_t val;
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}saradc_ctrl2;
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union {
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struct {
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uint32_t rstb_wait: 8;
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uint32_t standby_wait: 8;
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uint32_t start_wait: 8;
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uint32_t sample_cycle: 8; /*sample cycles*/
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};
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uint32_t val;
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}saradc_fsm;
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uint32_t saradc_sar1_patt_tab[4]; /*item 0 ~ 3 for ADC1 pattern table*/
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uint32_t saradc_sar2_patt_tab[4]; /*item 0 ~ 3 for ADC2 pattern table*/
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union {
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struct {
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uint32_t apll_tick: 8;
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uint32_t reserved8: 24;
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};
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uint32_t val;
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}apll_tick_conf;
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uint32_t reserved_40;
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uint32_t reserved_44;
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uint32_t reserved_48;
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uint32_t reserved_4c;
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uint32_t reserved_50;
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uint32_t reserved_54;
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uint32_t reserved_58;
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uint32_t reserved_5c;
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uint32_t reserved_60;
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uint32_t reserved_64;
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uint32_t reserved_68;
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uint32_t reserved_6c;
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uint32_t reserved_70;
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uint32_t reserved_74;
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uint32_t reserved_78;
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uint32_t date; /**/
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} syscon_dev_t;
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#ifdef __cplusplus
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}
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#endif
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extern syscon_dev_t SYSCON;
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#endif /* _SOC_SYSCON_STRUCT_H_ */
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