755 lines
20 KiB
C
755 lines
20 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "esp32-hal-uart.h"
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#include "esp32-hal.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/queue.h"
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#include "freertos/semphr.h"
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#include "esp_attr.h"
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#include "soc/uart_reg.h"
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#include "soc/uart_struct.h"
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#include "soc/io_mux_reg.h"
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#include "soc/gpio_sig_map.h"
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#include "soc/rtc.h"
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#include "hal/uart_ll.h"
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#include "esp_intr_alloc.h"
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#include "esp_system.h"
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#ifdef ESP_IDF_VERSION_MAJOR // IDF 4+
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#if CONFIG_IDF_TARGET_ESP32 // ESP32/PICO-D4
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#include "soc/dport_reg.h"
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#include "esp32/rom/ets_sys.h"
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#include "esp32/rom/uart.h"
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "soc/dport_reg.h"
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#include "esp32s2/rom/ets_sys.h"
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#include "esp32s2/rom/uart.h"
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#include "soc/periph_defs.h"
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#elif CONFIG_IDF_TARGET_ESP32C3
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#include "esp32c3/rom/ets_sys.h"
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#include "esp32c3/rom/uart.h"
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#include "soc/periph_defs.h"
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#else
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#error Target CONFIG_IDF_TARGET is not supported
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#endif
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#else // ESP32 Before IDF 4.0
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#include "rom/ets_sys.h"
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#include "rom/uart.h"
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#include "esp_intr.h"
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#endif
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#if CONFIG_IDF_TARGET_ESP32
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#define UART_PORTS_NUM 3
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#define UART_REG_BASE(u) ((u==0)?DR_REG_UART_BASE:( (u==1)?DR_REG_UART1_BASE:( (u==2)?DR_REG_UART2_BASE:0)))
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#define UART_RXD_IDX(u) ((u==0)?U0RXD_IN_IDX:( (u==1)?U1RXD_IN_IDX:( (u==2)?U2RXD_IN_IDX:0)))
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#define UART_TXD_IDX(u) ((u==0)?U0TXD_OUT_IDX:( (u==1)?U1TXD_OUT_IDX:( (u==2)?U2TXD_OUT_IDX:0)))
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#define UART_INTR_SOURCE(u) ((u==0)?ETS_UART0_INTR_SOURCE:( (u==1)?ETS_UART1_INTR_SOURCE:((u==2)?ETS_UART2_INTR_SOURCE:0)))
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#elif CONFIG_IDF_TARGET_ESP32S2
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#define UART_PORTS_NUM 2
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#define UART_REG_BASE(u) ((u==0)?DR_REG_UART_BASE:( (u==1)?DR_REG_UART1_BASE:0))
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#define UART_RXD_IDX(u) ((u==0)?U0RXD_IN_IDX:( (u==1)?U1RXD_IN_IDX:0))
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#define UART_TXD_IDX(u) ((u==0)?U0TXD_OUT_IDX:( (u==1)?U1TXD_OUT_IDX:0))
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#define UART_INTR_SOURCE(u) ((u==0)?ETS_UART0_INTR_SOURCE:( (u==1)?ETS_UART1_INTR_SOURCE:0))
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#else
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#define UART_PORTS_NUM 2
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#define UART_REG_BASE(u) ((u==0)?DR_REG_UART_BASE:( (u==1)?DR_REG_UART1_BASE:0))
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#define UART_RXD_IDX(u) ((u==0)?U0RXD_IN_IDX:( (u==1)?U1RXD_IN_IDX:0))
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#define UART_TXD_IDX(u) ((u==0)?U0TXD_OUT_IDX:( (u==1)?U1TXD_OUT_IDX:0))
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#define UART_INTR_SOURCE(u) ((u==0)?ETS_UART0_INTR_SOURCE:( (u==1)?ETS_UART1_INTR_SOURCE:0))
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#endif
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static int s_uart_debug_nr = 0;
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struct uart_struct_t {
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uart_dev_t * dev;
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#if !CONFIG_DISABLE_HAL_LOCKS
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xSemaphoreHandle lock;
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#endif
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uint8_t num;
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xQueueHandle queue;
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intr_handle_t intr_handle;
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};
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#if CONFIG_DISABLE_HAL_LOCKS
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#define UART_MUTEX_LOCK()
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#define UART_MUTEX_UNLOCK()
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static uart_t _uart_bus_array[] = {
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{&UART0, 0, NULL, NULL},
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{&UART1, 1, NULL, NULL},
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#if CONFIG_IDF_TARGET_ESP32
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{&UART2, 2, NULL, NULL}
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#endif
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};
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#else
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#define UART_MUTEX_LOCK() do {} while (xSemaphoreTake(uart->lock, portMAX_DELAY) != pdPASS)
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#define UART_MUTEX_UNLOCK() xSemaphoreGive(uart->lock)
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static uart_t _uart_bus_array[] = {
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{&UART0, NULL, 0, NULL, NULL},
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{&UART1, NULL, 1, NULL, NULL},
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#if CONFIG_IDF_TARGET_ESP32
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{&UART2, NULL, 2, NULL, NULL}
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#endif
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};
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#endif
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static void uart_on_apb_change(void * arg, apb_change_ev_t ev_type, uint32_t old_apb, uint32_t new_apb);
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static void ARDUINO_ISR_ATTR _uart_isr(void *arg)
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{
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uint8_t i, c;
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BaseType_t xHigherPriorityTaskWoken;
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uart_t* uart;
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for(i=0;i<UART_PORTS_NUM;i++){
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uart = &_uart_bus_array[i];
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if(uart->intr_handle == NULL){
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continue;
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}
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uart->dev->int_clr.rxfifo_full = 1;
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uart->dev->int_clr.frm_err = 1;
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uart->dev->int_clr.rxfifo_tout = 1;
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#if CONFIG_IDF_TARGET_ESP32
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while(uart->dev->status.rxfifo_cnt || (uart->dev->mem_rx_status.wr_addr != uart->dev->mem_rx_status.rd_addr)) {
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c = uart->dev->fifo.rw_byte;
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#else
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uint32_t fifo_reg = UART_FIFO_AHB_REG(i);
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while(uart->dev->status.rxfifo_cnt) {
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c = ESP_REG(fifo_reg);
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#endif
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if(uart->queue != NULL) {
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xQueueSendFromISR(uart->queue, &c, &xHigherPriorityTaskWoken);
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}
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}
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}
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if (xHigherPriorityTaskWoken) {
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portYIELD_FROM_ISR();
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}
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}
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static void uartEnableInterrupt(uart_t* uart, uint8_t rxfifo_full_thrhd)
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{
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UART_MUTEX_LOCK();
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uart->dev->conf1.rxfifo_full_thrhd = rxfifo_full_thrhd;
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#if CONFIG_IDF_TARGET_ESP32
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uart->dev->conf1.rx_tout_thrhd = 2;
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#else
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uart->dev->mem_conf.rx_tout_thrhd = 2;
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#endif
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uart->dev->conf1.rx_tout_en = 1;
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uart->dev->int_ena.rxfifo_full = 1;
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uart->dev->int_ena.frm_err = 1;
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uart->dev->int_ena.rxfifo_tout = 1;
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uart->dev->int_clr.val = 0xffffffff;
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esp_intr_alloc(UART_INTR_SOURCE(uart->num), (int)ARDUINO_ISR_FLAG, _uart_isr, NULL, &uart->intr_handle);
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UART_MUTEX_UNLOCK();
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}
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static void uartDisableInterrupt(uart_t* uart)
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{
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UART_MUTEX_LOCK();
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#if CONFIG_IDF_TARGET_ESP32
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uart->dev->conf1.val = 0;
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#endif
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uart->dev->int_ena.val = 0;
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uart->dev->int_clr.val = 0xffffffff;
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esp_intr_free(uart->intr_handle);
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uart->intr_handle = NULL;
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UART_MUTEX_UNLOCK();
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}
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static void uartDetachRx(uart_t* uart, uint8_t rxPin)
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{
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if(uart == NULL) {
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return;
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}
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pinMatrixInDetach(UART_RXD_IDX(uart->num), false, false);
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uartDisableInterrupt(uart);
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}
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static void uartDetachTx(uart_t* uart, uint8_t txPin)
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{
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if(uart == NULL) {
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return;
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}
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pinMatrixOutDetach(txPin, false, false);
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}
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static void uartAttachRx(uart_t* uart, uint8_t rxPin, bool inverted, uint8_t rxfifo_full_thrhd)
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{
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if(uart == NULL || rxPin >= GPIO_PIN_COUNT) {
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return;
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}
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pinMode(rxPin, INPUT);
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uartEnableInterrupt(uart, rxfifo_full_thrhd);
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pinMatrixInAttach(rxPin, UART_RXD_IDX(uart->num), inverted);
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}
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static void uartAttachTx(uart_t* uart, uint8_t txPin, bool inverted)
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{
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if(uart == NULL || txPin >= GPIO_PIN_COUNT) {
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return;
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}
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pinMode(txPin, OUTPUT);
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pinMatrixOutAttach(txPin, UART_TXD_IDX(uart->num), inverted, false);
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}
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uart_t* uartBegin(uint8_t uart_nr, uint32_t baudrate, uint32_t config, int8_t rxPin, int8_t txPin, uint16_t queueLen, bool inverted, uint8_t rxfifo_full_thrhd)
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{
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if(uart_nr >= UART_PORTS_NUM) {
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return NULL;
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}
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if(rxPin == -1 && txPin == -1) {
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return NULL;
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}
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uart_t* uart = &_uart_bus_array[uart_nr];
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#if !CONFIG_DISABLE_HAL_LOCKS
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if(uart->lock == NULL) {
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uart->lock = xSemaphoreCreateMutex();
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if(uart->lock == NULL) {
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return NULL;
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}
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}
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#endif
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if(queueLen && uart->queue == NULL) {
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uart->queue = xQueueCreate(queueLen, sizeof(uint8_t)); //initialize the queue
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if(uart->queue == NULL) {
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return NULL;
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}
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}
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#if CONFIG_IDF_TARGET_ESP32C3
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#else
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if(uart_nr == 1){
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UART1_CLK_EN);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART1_RST);
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#if CONFIG_IDF_TARGET_ESP32
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} else if(uart_nr == 2){
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UART2_CLK_EN);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART2_RST);
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#endif
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} else {
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UART_CLK_EN);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART_RST);
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}
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#endif
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uartFlush(uart);
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uartSetBaudRate(uart, baudrate);
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UART_MUTEX_LOCK();
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uart->dev->conf0.val = config;
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#define TWO_STOP_BITS_CONF 0x3
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#define ONE_STOP_BITS_CONF 0x1
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if ( uart->dev->conf0.stop_bit_num == TWO_STOP_BITS_CONF) {
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uart->dev->conf0.stop_bit_num = ONE_STOP_BITS_CONF;
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uart->dev->rs485_conf.dl1_en = 1;
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}
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// tx_idle_num : idle interval after tx FIFO is empty(unit: the time it takes to send one bit under current baudrate)
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// Setting it to 0 prevents line idle time/delays when sending messages with small intervals
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uart->dev->idle_conf.tx_idle_num = 0; //
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UART_MUTEX_UNLOCK();
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if(rxPin != -1) {
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uartAttachRx(uart, rxPin, inverted, rxfifo_full_thrhd);
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}
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if(txPin != -1) {
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uartAttachTx(uart, txPin, inverted);
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}
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addApbChangeCallback(uart, uart_on_apb_change);
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return uart;
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}
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void uartEnd(uart_t* uart, uint8_t txPin, uint8_t rxPin)
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{
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if(uart == NULL) {
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return;
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}
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removeApbChangeCallback(uart, uart_on_apb_change);
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UART_MUTEX_LOCK();
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if(uart->queue != NULL) {
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vQueueDelete(uart->queue);
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uart->queue = NULL;
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}
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uart->dev->conf0.val = 0;
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UART_MUTEX_UNLOCK();
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uartDetachRx(uart, rxPin);
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uartDetachTx(uart, txPin);
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}
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size_t uartResizeRxBuffer(uart_t * uart, size_t new_size) {
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if(uart == NULL) {
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return 0;
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}
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UART_MUTEX_LOCK();
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if(uart->queue != NULL) {
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vQueueDelete(uart->queue);
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uart->queue = xQueueCreate(new_size, sizeof(uint8_t));
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if(uart->queue == NULL) {
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UART_MUTEX_UNLOCK();
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return 0;
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}
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}
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UART_MUTEX_UNLOCK();
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return new_size;
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}
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void uartSetRxInvert(uart_t* uart, bool invert)
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{
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if (uart == NULL)
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return;
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if (invert)
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uart->dev->conf0.rxd_inv = 1;
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else
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uart->dev->conf0.rxd_inv = 0;
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}
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uint32_t uartAvailable(uart_t* uart)
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{
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if(uart == NULL || uart->queue == NULL) {
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return 0;
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}
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#ifdef UART_READ_RX_FIFO
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return (uxQueueMessagesWaiting(uart->queue) + uart->dev->status.rxfifo_cnt) ;
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#else
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return uxQueueMessagesWaiting(uart->queue);
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#endif
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}
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uint32_t uartAvailableForWrite(uart_t* uart)
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{
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if(uart == NULL) {
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return 0;
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}
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return 0x7f - uart->dev->status.txfifo_cnt;
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}
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#ifdef UART_READ_RX_FIFO
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void uartRxFifoToQueue(uart_t* uart)
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{
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uint8_t c;
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UART_MUTEX_LOCK();
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//disable interrupts
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uart->dev->int_ena.val = 0;
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uart->dev->int_clr.val = 0xffffffff;
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#if CONFIG_IDF_TARGET_ESP32
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while (uart->dev->status.rxfifo_cnt || (uart->dev->mem_rx_status.wr_addr != uart->dev->mem_rx_status.rd_addr)) {
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c = uart->dev->fifo.rw_byte;
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#else
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uint32_t fifo_reg = UART_FIFO_AHB_REG(uart->num);
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while (uart->dev->status.rxfifo_cnt) {
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c = ESP_REG(fifo_reg);
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#endif
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xQueueSend(uart->queue, &c, 0);
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}
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//enable interrupts
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uart->dev->int_ena.rxfifo_full = 1;
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uart->dev->int_ena.frm_err = 1;
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uart->dev->int_ena.rxfifo_tout = 1;
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uart->dev->int_clr.val = 0xffffffff;
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UART_MUTEX_UNLOCK();
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}
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#endif
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uint8_t uartRead(uart_t* uart)
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{
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if(uart == NULL || uart->queue == NULL) {
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return 0;
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}
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uint8_t c;
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#ifdef UART_READ_RX_FIFO
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if ((uxQueueMessagesWaiting(uart->queue) == 0) && (uart->dev->status.rxfifo_cnt > 0))
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{
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uartRxFifoToQueue(uart);
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}
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#endif
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if(xQueueReceive(uart->queue, &c, 0)) {
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return c;
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}
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return 0;
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}
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uint8_t uartPeek(uart_t* uart)
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{
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if(uart == NULL || uart->queue == NULL) {
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return 0;
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}
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uint8_t c;
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#ifdef UART_READ_RX_FIFO
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if ((uxQueueMessagesWaiting(uart->queue) == 0) && (uart->dev->status.rxfifo_cnt > 0))
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{
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uartRxFifoToQueue(uart);
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}
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#endif
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if(xQueuePeek(uart->queue, &c, 0)) {
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return c;
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}
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return 0;
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}
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void uartWrite(uart_t* uart, uint8_t c)
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{
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if(uart == NULL) {
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return;
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}
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UART_MUTEX_LOCK();
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while(uart->dev->status.txfifo_cnt >= 0x7E);
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#if CONFIG_IDF_TARGET_ESP32
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uart->dev->fifo.rw_byte = c;
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#else
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ESP_REG(UART_FIFO_AHB_REG(uart->num)) = c;
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#endif
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UART_MUTEX_UNLOCK();
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}
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void uartWriteBuf(uart_t* uart, const uint8_t * data, size_t len)
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{
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if(uart == NULL) {
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return;
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}
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UART_MUTEX_LOCK();
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#ifndef CONFIG_IDF_TARGET_ESP32
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uint32_t fifo_reg = UART_FIFO_AHB_REG(uart->num);
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#endif
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while(len) {
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while(uart->dev->status.txfifo_cnt >= 0x7E);
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#if CONFIG_IDF_TARGET_ESP32
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uart->dev->fifo.rw_byte = *data++;
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#else
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ESP_REG(fifo_reg) = *data++;
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#endif
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len--;
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}
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UART_MUTEX_UNLOCK();
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}
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void uartFlush(uart_t* uart)
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{
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uartFlushTxOnly(uart,true);
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}
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void uartFlushTxOnly(uart_t* uart, bool txOnly)
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{
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if(uart == NULL) {
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return;
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}
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UART_MUTEX_LOCK();
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#if CONFIG_IDF_TARGET_ESP32
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while(uart->dev->status.txfifo_cnt || uart->dev->status.st_utx_out);
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if( !txOnly ){
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//Due to hardware issue, we can not use fifo_rst to reset uart fifo.
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//See description about UART_TXFIFO_RST and UART_RXFIFO_RST in <<esp32_technical_reference_manual>> v2.6 or later.
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// we read the data out and make `fifo_len == 0 && rd_addr == wr_addr`.
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while(uart->dev->status.rxfifo_cnt != 0 || (uart->dev->mem_rx_status.wr_addr != uart->dev->mem_rx_status.rd_addr)) {
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READ_PERI_REG(UART_FIFO_REG(uart->num));
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}
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xQueueReset(uart->queue);
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}
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#else
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while(uart->dev->status.txfifo_cnt);
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uart->dev->conf0.txfifo_rst = 1;
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uart->dev->conf0.txfifo_rst = 0;
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#endif
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UART_MUTEX_UNLOCK();
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}
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void uartSetBaudRate(uart_t* uart, uint32_t baud_rate)
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{
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if(uart == NULL) {
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return;
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}
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UART_MUTEX_LOCK();
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uart_ll_set_baudrate(uart->dev, baud_rate);
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UART_MUTEX_UNLOCK();
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}
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static void uart_on_apb_change(void * arg, apb_change_ev_t ev_type, uint32_t old_apb, uint32_t new_apb)
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{
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uart_t* uart = (uart_t*)arg;
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if(ev_type == APB_BEFORE_CHANGE){
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UART_MUTEX_LOCK();
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//disabple interrupt
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uart->dev->int_ena.val = 0;
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uart->dev->int_clr.val = 0xffffffff;
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// read RX fifo
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uint8_t c;
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// BaseType_t xHigherPriorityTaskWoken;
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#if CONFIG_IDF_TARGET_ESP32
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while(uart->dev->status.rxfifo_cnt != 0 || (uart->dev->mem_rx_status.wr_addr != uart->dev->mem_rx_status.rd_addr)) {
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c = uart->dev->fifo.rw_byte;
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#else
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uint32_t fifo_reg = UART_FIFO_AHB_REG(uart->num);
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while(uart->dev->status.rxfifo_cnt != 0) {
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c = ESP_REG(fifo_reg);
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#endif
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if(uart->queue != NULL ) {
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xQueueSend(uart->queue, &c, 1); //&xHigherPriorityTaskWoken);
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}
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}
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UART_MUTEX_UNLOCK();
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// wait TX empty
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#if CONFIG_IDF_TARGET_ESP32
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while(uart->dev->status.txfifo_cnt || uart->dev->status.st_utx_out);
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#else
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while(uart->dev->status.txfifo_cnt);
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#endif
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} else {
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//todo:
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// set baudrate
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UART_MUTEX_LOCK();
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uint32_t clk_div = (uart->dev->clk_div.div_int << 4) | (uart->dev->clk_div.div_frag & 0x0F);
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uint32_t baud_rate = ((old_apb<<4)/clk_div);
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clk_div = ((new_apb<<4)/baud_rate);
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uart->dev->clk_div.div_int = clk_div>>4 ;
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uart->dev->clk_div.div_frag = clk_div & 0xf;
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//enable interrupts
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uart->dev->int_ena.rxfifo_full = 1;
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uart->dev->int_ena.frm_err = 1;
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uart->dev->int_ena.rxfifo_tout = 1;
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uart->dev->int_clr.val = 0xffffffff;
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UART_MUTEX_UNLOCK();
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}
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}
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uint32_t uartGetBaudRate(uart_t* uart)
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{
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if(uart == NULL) {
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return 0;
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}
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uint32_t clk_div = (uart->dev->clk_div.div_int << 4) | (uart->dev->clk_div.div_frag & 0x0F);
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if(!clk_div) {
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return 0;
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}
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return ((getApbFrequency()<<4)/clk_div);
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}
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static void ARDUINO_ISR_ATTR uart0_write_char(char c)
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{
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#if CONFIG_IDF_TARGET_ESP32
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while(((ESP_REG(0x01C+DR_REG_UART_BASE) >> UART_TXFIFO_CNT_S) & 0x7F) >= 0x7E);
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ESP_REG(DR_REG_UART_BASE) = c;
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#else
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while(UART0.status.txfifo_cnt == 0x7F);
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WRITE_PERI_REG(UART_FIFO_AHB_REG(0), c);
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#endif
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}
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static void ARDUINO_ISR_ATTR uart1_write_char(char c)
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{
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#if CONFIG_IDF_TARGET_ESP32
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while(((ESP_REG(0x01C+DR_REG_UART1_BASE) >> UART_TXFIFO_CNT_S) & 0x7F) >= 0x7E);
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ESP_REG(DR_REG_UART1_BASE) = c;
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#else
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while(UART1.status.txfifo_cnt == 0x7F);
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WRITE_PERI_REG(UART_FIFO_AHB_REG(1), c);
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#endif
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}
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#if CONFIG_IDF_TARGET_ESP32
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static void ARDUINO_ISR_ATTR uart2_write_char(char c)
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{
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while(((ESP_REG(0x01C+DR_REG_UART2_BASE) >> UART_TXFIFO_CNT_S) & 0x7F) >= 0x7E);
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ESP_REG(DR_REG_UART2_BASE) = c;
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}
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#endif
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void uart_install_putc()
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{
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switch(s_uart_debug_nr) {
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case 0:
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ets_install_putc1((void (*)(char)) &uart0_write_char);
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break;
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case 1:
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ets_install_putc1((void (*)(char)) &uart1_write_char);
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break;
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#if CONFIG_IDF_TARGET_ESP32
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case 2:
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ets_install_putc1((void (*)(char)) &uart2_write_char);
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break;
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#endif
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default:
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ets_install_putc1(NULL);
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break;
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}
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}
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void uartSetDebug(uart_t* uart)
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{
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if(uart == NULL || uart->num >= UART_PORTS_NUM) {
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s_uart_debug_nr = -1;
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//ets_install_putc1(NULL);
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//return;
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} else
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if(s_uart_debug_nr == uart->num) {
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return;
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} else
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s_uart_debug_nr = uart->num;
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uart_install_putc();
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}
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int uartGetDebug()
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{
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return s_uart_debug_nr;
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}
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int log_printf(const char *format, ...)
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{
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static char loc_buf[64];
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char * temp = loc_buf;
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int len;
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va_list arg;
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va_list copy;
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va_start(arg, format);
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va_copy(copy, arg);
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len = vsnprintf(NULL, 0, format, arg);
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va_end(copy);
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if(len >= sizeof(loc_buf)){
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temp = (char*)malloc(len+1);
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if(temp == NULL) {
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return 0;
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}
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}
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vsnprintf(temp, len+1, format, arg);
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#if !CONFIG_DISABLE_HAL_LOCKS
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if(s_uart_debug_nr != -1 && _uart_bus_array[s_uart_debug_nr].lock){
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xSemaphoreTake(_uart_bus_array[s_uart_debug_nr].lock, portMAX_DELAY);
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ets_printf("%s", temp);
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xSemaphoreGive(_uart_bus_array[s_uart_debug_nr].lock);
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} else {
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ets_printf("%s", temp);
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}
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#else
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ets_printf("%s", temp);
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#endif
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va_end(arg);
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if(len >= sizeof(loc_buf)){
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|
free(temp);
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}
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|
return len;
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|
}
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|
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/*
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* if enough pulses are detected return the minimum high pulse duration + minimum low pulse duration divided by two.
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* This equals one bit period. If flag is true the function return inmediately, otherwise it waits for enough pulses.
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*/
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unsigned long uartBaudrateDetect(uart_t *uart, bool flg)
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{
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while(uart->dev->rxd_cnt.edge_cnt < 30) { // UART_PULSE_NUM(uart_num)
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if(flg) return 0;
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ets_delay_us(1000);
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}
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UART_MUTEX_LOCK();
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unsigned long ret = ((uart->dev->lowpulse.min_cnt + uart->dev->highpulse.min_cnt) >> 1) + 12;
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UART_MUTEX_UNLOCK();
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return ret;
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}
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|
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/*
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* To start detection of baud rate with the uart the auto_baud.en bit needs to be cleared and set. The bit period is
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* detected calling uartBadrateDetect(). The raw baudrate is computed using the UART_CLK_FREQ. The raw baudrate is
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* rounded to the closed real baudrate.
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*/
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void uartStartDetectBaudrate(uart_t *uart) {
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if(!uart) return;
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#ifndef CONFIG_IDF_TARGET_ESP32C3
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uart->dev->auto_baud.glitch_filt = 0x08;
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uart->dev->auto_baud.en = 0;
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uart->dev->auto_baud.en = 1;
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#endif
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}
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unsigned long
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uartDetectBaudrate(uart_t *uart)
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{
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#ifndef CONFIG_IDF_TARGET_ESP32C3
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static bool uartStateDetectingBaudrate = false;
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if(!uartStateDetectingBaudrate) {
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uart->dev->auto_baud.glitch_filt = 0x08;
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uart->dev->auto_baud.en = 0;
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uart->dev->auto_baud.en = 1;
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uartStateDetectingBaudrate = true;
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}
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unsigned long divisor = uartBaudrateDetect(uart, true);
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if (!divisor) {
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return 0;
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|
}
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uart->dev->auto_baud.en = 0;
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uartStateDetectingBaudrate = false; // Initialize for the next round
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|
unsigned long baudrate = getApbFrequency() / divisor;
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|
static const unsigned long default_rates[] = {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 74880, 115200, 230400, 256000, 460800, 921600, 1843200, 3686400};
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|
|
size_t i;
|
|
for (i = 1; i < sizeof(default_rates) / sizeof(default_rates[0]) - 1; i++) // find the nearest real baudrate
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|
{
|
|
if (baudrate <= default_rates[i])
|
|
{
|
|
if (baudrate - default_rates[i - 1] < default_rates[i] - baudrate) {
|
|
i--;
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
return default_rates[i];
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#else
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|
return 0;
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|
#endif
|
|
}
|
|
|
|
/*
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|
* Returns the status of the RX state machine, if the value is non-zero the state machine is active.
|
|
*/
|
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bool uartRxActive(uart_t* uart) {
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#if CONFIG_IDF_TARGET_ESP32
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|
return uart->dev->status.st_urx_out != 0;
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#else
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|
return 0;
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|
#endif
|
|
}
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