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Adjusted trace constraints and corrected to comply

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This commit is contained in:
Jacob Eva 2023-04-18 17:28:20 +01:00
parent 1e70068cf4
commit 4f7d1fc43f
3 changed files with 765 additions and 578 deletions
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1332
Electrical/Roamer.kicad_pcb
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6
Electrical/Roamer.kicad_prl
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@ -1,7 +1,7 @@
{
"board": {
"active_layer": 37,
"active_layer_preset": "",
"active_layer": 0,
"active_layer_preset": "All Layers",
"auto_track_width": true,
"hidden_netclasses": [],
"hidden_nets": [],
@ -65,7 +65,7 @@
39,
40
],
"visible_layers": "fffffdf_ffffffff",
"visible_layers": "fffffff_ffffffff",
"zone_display_mode": 0
},
"meta": {

5
Electrical/Roamer.kicad_pro
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@ -56,6 +56,7 @@
}
],
"drc_exclusions": [
"silk_overlap|143832000|184229500|1a2ea27d-5680-4bd0-8baf-a3d7e46f4b3b|6fed890f-e9fc-4175-b2e8-fb6a112a419c",
"silk_overlap|146802000|184189500|1a2ea27d-5680-4bd0-8baf-a3d7e46f4b3b|6fed890f-e9fc-4175-b2e8-fb6a112a419c"
],
"meta": {
@ -114,7 +115,7 @@
},
"rules": {
"max_error": 0.005,
"min_clearance": 0.0,
"min_clearance": 0.09999999999999999,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.024999999999999998,
"min_hole_clearance": 0.25,
@ -123,7 +124,7 @@
"min_microvia_drill": 0.09999999999999999,
"min_resolved_spokes": 2,
"min_silk_clearance": 0.0,
"min_text_height": 0.7999999999999999,
"min_text_height": 0.5,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.15239999999999998,