Commit Graph

62 Commits

Author SHA1 Message Date
Zeos-ctrl
3abf4ab609 added basic lid shape 2023-04-16 12:47:17 +01:00
jacob.eva
115f7ba6cb
Updated dimensions 2023-04-15 12:13:58 +01:00
2f13a5a4e0 Added PWR and WWAN labels to diodes 2023-04-13 16:59:58 +01:00
1b475ef967 Added company logo, name and license 2023-04-13 16:52:16 +01:00
c40cb92a58 Added resistance note to DC to DC IC 2023-04-13 15:58:31 +01:00
43cb03715e Corrected card area length 2023-04-13 15:56:10 +01:00
cc3dac4df9 Finished main design (one commit fight me) 2023-04-13 15:49:30 +01:00
jacob.eva
dab6156b19
Updated PCB to Framework's specs 2023-04-11 18:33:14 +01:00
jacob.eva
9664257e68
Reformatted schematic 2023-04-11 18:32:35 +01:00
jacob.eva
34f224a20e
Exported card as STL 2023-04-06 17:05:21 +01:00
jacob.eva
d1c4e4406d
Added SIM slot footprint 2023-04-06 17:02:56 +01:00
jacob.eva
8893f9c87e
Added to git 2023-04-05 19:24:53 +01:00