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1998dbf42e
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Moved trace to comply with DRC
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2023-07-19 21:45:15 +01:00 |
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c06af93822
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Changed molex model path
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2023-07-11 17:53:46 +01:00 |
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01828790ec
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Moved J1, J2, deleted UART test points
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2023-07-11 18:38:50 +01:00 |
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c575aac69a
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Corrected typo on pin 22
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2023-07-08 12:57:43 +01:00 |
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64914e2aaa
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Added JLCPCB order silkscreen
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2023-07-08 12:47:33 +01:00 |
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a4681854a6
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Finishing touches
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2023-06-27 15:21:49 +01:00 |
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167737a61d
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Completed the whole crapping thing
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2023-06-10 11:27:50 +01:00 |
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d20e97775d
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Updated crapping everything
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2023-06-05 23:18:52 +01:00 |
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7c3f04e593
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Updated schematic
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2023-05-28 10:28:52 +01:00 |
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ce1d215d2a
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Reverted trace width and moved H5 silkscreen
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2023-04-22 18:49:36 +01:00 |
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23da2edd95
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Adjusted trace spacing
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2023-04-22 18:34:26 +01:00 |
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42ba2a3662
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Updated PCB to reflect schematic
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2023-04-20 13:24:24 +01:00 |
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4f7d1fc43f
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Adjusted trace constraints and corrected to comply
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2023-04-18 17:28:20 +01:00 |
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cc3dac4df9
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Finished main design (one commit fight me)
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2023-04-13 15:49:30 +01:00 |
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jacob.eva
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dab6156b19
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Updated PCB to Framework's specs
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2023-04-11 18:33:14 +01:00 |
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jacob.eva
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8893f9c87e
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Added to git
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2023-04-05 19:24:53 +01:00 |
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