2018-04-05 18:10:42 +02:00
|
|
|
// Copyright (c) Sandeep Mistry. All rights reserved.
|
2020-05-21 12:41:39 +02:00
|
|
|
// Licensed under the MIT license.
|
|
|
|
|
2023-01-14 00:11:02 +01:00
|
|
|
// Modifications and additions copyright 2023 by Mark Qvist
|
2020-05-21 12:41:39 +02:00
|
|
|
// Obviously still under the MIT license.
|
2018-04-05 18:10:42 +02:00
|
|
|
|
2024-02-09 21:46:39 +01:00
|
|
|
#ifndef SX128X_H
|
|
|
|
#define SX128X_H
|
2018-04-05 18:10:42 +02:00
|
|
|
|
|
|
|
#include <Arduino.h>
|
|
|
|
#include <SPI.h>
|
2024-05-21 18:15:21 +02:00
|
|
|
#include "Interfaces.h"
|
2018-04-05 18:10:42 +02:00
|
|
|
|
|
|
|
#define LORA_DEFAULT_SS_PIN 10
|
|
|
|
#define LORA_DEFAULT_RESET_PIN 9
|
|
|
|
#define LORA_DEFAULT_DIO0_PIN 2
|
2024-01-19 11:08:55 +01:00
|
|
|
#define LORA_DEFAULT_RXEN_PIN -1
|
2024-02-09 21:46:39 +01:00
|
|
|
#define LORA_DEFAULT_TXEN_PIN -1
|
2024-05-21 18:15:21 +02:00
|
|
|
#define LORA_DEFAULT_BUSY_PIN 11
|
2018-04-05 18:10:42 +02:00
|
|
|
|
|
|
|
#define PA_OUTPUT_RFO_PIN 0
|
|
|
|
#define PA_OUTPUT_PA_BOOST_PIN 1
|
|
|
|
|
2019-11-07 15:26:21 +01:00
|
|
|
#define RSSI_OFFSET 157
|
|
|
|
|
2024-02-09 21:46:39 +01:00
|
|
|
class sx128x : public Stream {
|
2018-04-05 18:10:42 +02:00
|
|
|
public:
|
2024-02-09 21:46:39 +01:00
|
|
|
sx128x();
|
2018-04-05 18:10:42 +02:00
|
|
|
|
2024-02-09 21:46:39 +01:00
|
|
|
int begin(unsigned long frequency);
|
2018-04-05 18:10:42 +02:00
|
|
|
void end();
|
|
|
|
|
|
|
|
int beginPacket(int implicitHeader = false);
|
|
|
|
int endPacket();
|
|
|
|
|
|
|
|
int parsePacket(int size = 0);
|
|
|
|
int packetRssi();
|
2022-10-29 00:52:51 +02:00
|
|
|
int currentRssi();
|
2018-06-27 14:08:16 +02:00
|
|
|
uint8_t packetRssiRaw();
|
2022-10-29 00:52:51 +02:00
|
|
|
uint8_t currentRssiRaw();
|
2020-05-21 12:41:39 +02:00
|
|
|
uint8_t packetSnrRaw();
|
2018-04-05 18:10:42 +02:00
|
|
|
float packetSnr();
|
|
|
|
long packetFrequencyError();
|
|
|
|
|
|
|
|
// from Print
|
|
|
|
virtual size_t write(uint8_t byte);
|
|
|
|
virtual size_t write(const uint8_t *buffer, size_t size);
|
|
|
|
|
|
|
|
// from Stream
|
|
|
|
virtual int available();
|
|
|
|
virtual int read();
|
|
|
|
virtual int peek();
|
|
|
|
virtual void flush();
|
|
|
|
|
|
|
|
void onReceive(void(*callback)(int));
|
|
|
|
|
|
|
|
void receive(int size = 0);
|
|
|
|
void idle();
|
|
|
|
void sleep();
|
|
|
|
|
2023-01-07 16:35:07 +01:00
|
|
|
bool preInit();
|
|
|
|
uint8_t getTxPower();
|
2018-04-05 18:10:42 +02:00
|
|
|
void setTxPower(int level, int outputPin = PA_OUTPUT_PA_BOOST_PIN);
|
2018-06-20 16:32:30 +02:00
|
|
|
uint32_t getFrequency();
|
2024-02-09 21:46:39 +01:00
|
|
|
void setFrequency(unsigned long frequency);
|
2018-04-05 18:10:42 +02:00
|
|
|
void setSpreadingFactor(int sf);
|
|
|
|
long getSignalBandwidth();
|
|
|
|
void setSignalBandwidth(long sbw);
|
|
|
|
void setCodingRate4(int denominator);
|
|
|
|
void setPreambleLength(long length);
|
|
|
|
void setSyncWord(int sw);
|
2018-04-26 15:52:43 +02:00
|
|
|
uint8_t modemStatus();
|
2018-04-05 18:10:42 +02:00
|
|
|
void enableCrc();
|
|
|
|
void disableCrc();
|
2023-06-07 20:49:26 +02:00
|
|
|
void enableTCXO();
|
|
|
|
void disableTCXO();
|
2018-04-05 18:10:42 +02:00
|
|
|
|
2024-02-09 21:46:39 +01:00
|
|
|
void txAntEnable();
|
|
|
|
void rxAntEnable();
|
|
|
|
void loraMode();
|
|
|
|
void waitOnBusy();
|
|
|
|
void executeOpcode(uint8_t opcode, uint8_t *buffer, uint8_t size);
|
|
|
|
void executeOpcodeRead(uint8_t opcode, uint8_t *buffer, uint8_t size);
|
|
|
|
void writeBuffer(const uint8_t* buffer, size_t size);
|
|
|
|
void readBuffer(uint8_t* buffer, size_t size);
|
|
|
|
void setPacketParams(uint32_t preamble, uint8_t headermode, uint8_t length, uint8_t crc);
|
|
|
|
void setModulationParams(uint8_t sf, uint8_t bw, uint8_t cr);
|
2024-01-19 11:08:55 +01:00
|
|
|
|
2018-04-05 18:10:42 +02:00
|
|
|
// deprecated
|
|
|
|
void crc() { enableCrc(); }
|
|
|
|
void noCrc() { disableCrc(); }
|
|
|
|
|
|
|
|
byte random();
|
|
|
|
|
2024-02-09 21:46:39 +01:00
|
|
|
void setPins(int ss = LORA_DEFAULT_SS_PIN, int reset = LORA_DEFAULT_RESET_PIN, int dio0 = LORA_DEFAULT_DIO0_PIN, int busy = LORA_DEFAULT_BUSY_PIN, int rxen = LORA_DEFAULT_RXEN_PIN, int txen = LORA_DEFAULT_TXEN_PIN);
|
2018-04-05 18:10:42 +02:00
|
|
|
void setSPIFrequency(uint32_t frequency);
|
|
|
|
|
|
|
|
void dumpRegisters(Stream& out);
|
|
|
|
|
|
|
|
private:
|
|
|
|
void explicitHeaderMode();
|
|
|
|
void implicitHeaderMode();
|
|
|
|
|
|
|
|
void handleDio0Rise();
|
|
|
|
|
2024-02-09 21:46:39 +01:00
|
|
|
uint8_t readRegister(uint16_t address);
|
|
|
|
void writeRegister(uint16_t address, uint8_t value);
|
|
|
|
uint8_t singleTransfer(uint8_t opcode, uint16_t address, uint8_t value);
|
2018-04-05 18:10:42 +02:00
|
|
|
|
|
|
|
static void onDio0Rise();
|
|
|
|
|
2019-10-14 23:16:30 +02:00
|
|
|
void handleLowDataRate();
|
2023-04-22 07:56:46 +02:00
|
|
|
void optimizeModemSensitivity();
|
2019-10-14 23:16:30 +02:00
|
|
|
|
2018-04-05 18:10:42 +02:00
|
|
|
private:
|
|
|
|
SPISettings _spiSettings;
|
|
|
|
int _ss;
|
|
|
|
int _reset;
|
|
|
|
int _dio0;
|
2024-01-19 11:08:55 +01:00
|
|
|
int _rxen;
|
2024-02-09 21:46:39 +01:00
|
|
|
int _txen;
|
2024-01-19 11:08:55 +01:00
|
|
|
int _busy;
|
2024-02-09 21:46:39 +01:00
|
|
|
int _modem;
|
|
|
|
unsigned long _frequency;
|
2024-01-19 11:08:55 +01:00
|
|
|
int _txp;
|
|
|
|
uint8_t _sf;
|
|
|
|
uint8_t _bw;
|
|
|
|
uint8_t _cr;
|
2018-04-05 18:10:42 +02:00
|
|
|
int _packetIndex;
|
2024-02-09 21:46:39 +01:00
|
|
|
uint32_t _preambleLength;
|
2018-04-05 18:10:42 +02:00
|
|
|
int _implicitHeaderMode;
|
2024-01-19 11:08:55 +01:00
|
|
|
int _payloadLength;
|
|
|
|
int _crcMode;
|
2024-02-09 21:46:39 +01:00
|
|
|
int _fifo_tx_addr_ptr;
|
|
|
|
int _fifo_rx_addr_ptr;
|
|
|
|
uint8_t _packet[256];
|
|
|
|
bool _preinit_done;
|
|
|
|
int _rxPacketLength;
|
2018-04-05 18:10:42 +02:00
|
|
|
void (*_onReceive)(int);
|
|
|
|
};
|
|
|
|
|
2024-02-09 21:46:39 +01:00
|
|
|
extern sx128x sx128x_modem;
|
2018-04-05 18:10:42 +02:00
|
|
|
|
2024-01-19 11:08:55 +01:00
|
|
|
#endif
|