890 lines
18 KiB
C++
890 lines
18 KiB
C++
// Copyright (c) Sandeep Mistry. All rights reserved.
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// Licensed under the MIT license.
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// Modifications and additions copyright 2023 by Mark Qvist
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// Obviously still under the MIT license.
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#include "sx128x.h"
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#include "Boards.h"
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#define MCU_1284P 0x91
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#define MCU_2560 0x92
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#define MCU_ESP32 0x81
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#define MCU_NRF52 0x71
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#if defined(__AVR_ATmega1284P__)
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#define PLATFORM PLATFORM_AVR
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#define MCU_VARIANT MCU_1284P
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#elif defined(__AVR_ATmega2560__)
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#define PLATFORM PLATFORM_AVR
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#define MCU_VARIANT MCU_2560
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#elif defined(ESP32)
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#define PLATFORM PLATFORM_ESP32
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#define MCU_VARIANT MCU_ESP32
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#elif defined(NRF52840_XXAA)
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#define PLATFORM PLATFORM_NRF52
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#define MCU_VARIANT MCU_NRF52
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#endif
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#ifndef MCU_VARIANT
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#error No MCU variant defined, cannot compile
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#endif
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#if MCU_VARIANT == MCU_ESP32
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#if MCU_VARIANT == MCU_ESP32 and !defined(CONFIG_IDF_TARGET_ESP32S3)
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#include "soc/rtc_wdt.h"
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#endif
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#define ISR_VECT IRAM_ATTR
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#else
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#define ISR_VECT
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#endif
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#define OP_RF_FREQ_8X 0x86
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#define OP_SLEEP_8X 0x84
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#define OP_STANDBY_8X 0x80
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#define OP_TX_8X 0x83
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#define OP_RX_8X 0x82
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#define OP_SET_IRQ_FLAGS_8X 0x8D // also provides info such as
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// preamble detection, etc for
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// knowing when it's safe to switch
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// antenna modes
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#define OP_CLEAR_IRQ_STATUS_8X 0x97
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#define OP_GET_IRQ_STATUS_8X 0x15
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#define OP_RX_BUFFER_STATUS_8X 0x17
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#define OP_PACKET_STATUS_8X 0x1D // get snr & rssi of last packet
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#define OP_CURRENT_RSSI_8X 0x1F
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#define OP_MODULATION_PARAMS_8X 0x8B // bw, sf, cr, etc.
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#define OP_PACKET_PARAMS_8X 0x8C // crc, preamble, payload length, etc.
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#define OP_STATUS_8X 0xC0
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#define OP_TX_PARAMS_8X 0x8E // set dbm, etc
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#define OP_PACKET_TYPE_8X 0x8A
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#define OP_BUFFER_BASE_ADDR_8X 0x8F
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#define OP_READ_REGISTER_8X 0x19
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#define OP_WRITE_REGISTER_8X 0x18
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#define IRQ_TX_DONE_MASK_8X 0x01
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#define IRQ_RX_DONE_MASK_8X 0x02
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#define IRQ_HEADER_DET_MASK_8X 0x10
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#define IRQ_HEADER_ERROR_MASK_8X 0x20
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#define IRQ_PAYLOAD_CRC_ERROR_MASK_8X 0x40
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#define MODE_LONG_RANGE_MODE_8X 0x01
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#define OP_FIFO_WRITE_8X 0x1A
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#define OP_FIFO_READ_8X 0x1B
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#define IRQ_PREAMBLE_DET_MASK_8X 0x80
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#define REG_PACKET_SIZE 0x901
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#define REG_FIRM_VER_MSB 0x154
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#define REG_FIRM_VER_LSB 0x153
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#define XTAL_FREQ_8X (double)52000000
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#define FREQ_DIV_8X (double)pow(2.0, 18.0)
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#define FREQ_STEP_8X (double)(XTAL_FREQ_8X / FREQ_DIV_8X)
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#if defined(NRF52840_XXAA)
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extern SPIClass spiModem;
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#define SPI spiModem
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#endif
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extern SPIClass SPI;
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#define MAX_PKT_LENGTH 255
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sx128x::sx128x() :
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_spiSettings(8E6, MSBFIRST, SPI_MODE0),
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_ss(LORA_DEFAULT_SS_PIN), _reset(LORA_DEFAULT_RESET_PIN), _dio0(LORA_DEFAULT_DIO0_PIN), _rxen(LORA_DEFAULT_RXEN_PIN), _busy(LORA_DEFAULT_BUSY_PIN),
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_frequency(0),
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_txp(0),
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_sf(0x50),
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_bw(0x34),
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_cr(0x01),
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_packetIndex(0),
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_preambleLength(18),
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_implicitHeaderMode(0),
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_payloadLength(255),
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_crcMode(0),
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_fifo_tx_addr_ptr(0),
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_fifo_rx_addr_ptr(0),
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_packet({0}),
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_rxPacketLength(0),
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_preinit_done(false),
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_onReceive(NULL)
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{
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// overide Stream timeout value
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setTimeout(0);
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}
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bool sx128x::preInit() {
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// setup pins
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pinMode(_ss, OUTPUT);
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// set SS high
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digitalWrite(_ss, HIGH);
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SPI.begin();
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// check version (retry for up to 2 seconds)
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long start = millis();
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uint8_t version_msb;
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uint8_t version_lsb;
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while (((millis() - start) < 2000) && (millis() >= start)) {
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version_msb = readRegister(REG_FIRM_VER_MSB);
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version_lsb = readRegister(REG_FIRM_VER_LSB);
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if ((version_msb == 0xB7 && version_lsb == 0xA9) || (version_msb == 0xB5 && version_lsb == 0xA9)) {
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break;
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}
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delay(100);
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}
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if ((version_msb != 0xB7 || version_lsb != 0xA9) && (version_msb != 0xB5 || version_lsb != 0xA9)) {
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return false;
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}
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_preinit_done = true;
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return true;
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}
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uint8_t ISR_VECT sx128x::readRegister(uint16_t address)
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{
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return singleTransfer(OP_READ_REGISTER_8X, address, 0x00);
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}
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void sx128x::writeRegister(uint16_t address, uint8_t value)
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{
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singleTransfer(OP_WRITE_REGISTER_8X, address, value);
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}
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uint8_t ISR_VECT sx128x::singleTransfer(uint8_t opcode, uint16_t address, uint8_t value)
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{
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waitOnBusy();
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uint8_t response;
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digitalWrite(_ss, LOW);
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SPI.beginTransaction(_spiSettings);
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SPI.transfer(opcode);
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SPI.transfer((address & 0xFF00) >> 8);
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SPI.transfer(address & 0x00FF);
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if (opcode == OP_READ_REGISTER_8X) {
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SPI.transfer(0x00);
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}
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response = SPI.transfer(value);
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SPI.endTransaction();
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digitalWrite(_ss, HIGH);
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return response;
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}
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void sx128x::rxAntEnable()
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{
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if (_txen != -1) {
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digitalWrite(_txen, LOW);
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}
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if (_rxen != -1) {
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digitalWrite(_rxen, HIGH);
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}
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}
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void sx128x::txAntEnable()
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{
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if (_txen != -1) {
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digitalWrite(_txen, HIGH);
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}
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if (_rxen != -1) {
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digitalWrite(_rxen, LOW);
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}
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}
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void sx128x::loraMode() {
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// enable lora mode on the SX1262 chip
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uint8_t mode = MODE_LONG_RANGE_MODE_8X;
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executeOpcode(OP_PACKET_TYPE_8X, &mode, 1);
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}
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void sx128x::waitOnBusy() {
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unsigned long time = millis();
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if (_busy != -1) {
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while (digitalRead(_busy) == HIGH)
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{
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if (millis() >= (time + 100)) {
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break;
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}
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// do nothing
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}
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}
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}
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void sx128x::executeOpcode(uint8_t opcode, uint8_t *buffer, uint8_t size)
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{
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waitOnBusy();
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digitalWrite(_ss, LOW);
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SPI.beginTransaction(_spiSettings);
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SPI.transfer(opcode);
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for (int i = 0; i < size; i++)
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{
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SPI.transfer(buffer[i]);
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}
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SPI.endTransaction();
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digitalWrite(_ss, HIGH);
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}
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void sx128x::executeOpcodeRead(uint8_t opcode, uint8_t *buffer, uint8_t size)
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{
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waitOnBusy();
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digitalWrite(_ss, LOW);
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SPI.beginTransaction(_spiSettings);
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SPI.transfer(opcode);
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SPI.transfer(0x00);
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for (int i = 0; i < size; i++)
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{
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buffer[i] = SPI.transfer(0x00);
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}
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SPI.endTransaction();
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digitalWrite(_ss, HIGH);
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}
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void sx128x::writeBuffer(const uint8_t* buffer, size_t size)
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{
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waitOnBusy();
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digitalWrite(_ss, LOW);
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SPI.beginTransaction(_spiSettings);
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SPI.transfer(OP_FIFO_WRITE_8X);
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SPI.transfer(_fifo_tx_addr_ptr);
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for (int i = 0; i < size; i++)
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{
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SPI.transfer(buffer[i]);
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_fifo_tx_addr_ptr++;
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}
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SPI.endTransaction();
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digitalWrite(_ss, HIGH);
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}
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void sx128x::readBuffer(uint8_t* buffer, size_t size)
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{
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waitOnBusy();
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digitalWrite(_ss, LOW);
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SPI.beginTransaction(_spiSettings);
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SPI.transfer(OP_FIFO_READ_8X);
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SPI.transfer(_fifo_rx_addr_ptr);
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SPI.transfer(0x00);
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for (int i = 0; i < size; i++)
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{
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buffer[i] = SPI.transfer(0x00);
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}
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SPI.endTransaction();
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digitalWrite(_ss, HIGH);
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}
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void sx128x::setModulationParams(uint8_t sf, uint8_t bw, uint8_t cr) {
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// because there is no access to these registers on the sx1280, we have
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// to set all these parameters at once or not at all.
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uint8_t buf[3];
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buf[0] = sf;
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buf[1] = bw;
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buf[2] = cr;
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executeOpcode(OP_MODULATION_PARAMS_8X, buf, 3);
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if (sf <= 6) {
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writeRegister(0x925, 0x1E);
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} else if (sf <= 8) {
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writeRegister(0x925, 0x37);
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} else if (sf >= 9) {
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writeRegister(0x925, 0x32);
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}
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writeRegister(0x093C, 0x1);
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}
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void sx128x::setPacketParams(uint32_t preamble, uint8_t headermode, uint8_t length, uint8_t crc) {
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// because there is no access to these registers on the sx1280, we have
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// to set all these parameters at once or not at all.
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uint8_t buf[7];
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// calculate exponent and mantissa values for modem
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uint8_t e = 1;
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uint8_t m = 1;
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uint32_t preamblelen;
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for (e <= 15; e++;) {
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for (m <= 15; m++;) {
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preamblelen = m * (uint32_t(1) << e);
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if (preamblelen >= preamble) break;
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}
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if (preamblelen >= preamble) break;
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}
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buf[0] = (e << 4) | m;
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buf[1] = headermode;
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buf[2] = length;
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buf[3] = crc;
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// standard IQ setting (no inversion)
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buf[4] = 0x40;
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// unused params
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buf[5] = 0x00;
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buf[6] = 0x00;
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executeOpcode(OP_PACKET_PARAMS_8X, buf, 7);
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}
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int sx128x::begin(unsigned long frequency)
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{
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if (_reset != -1) {
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pinMode(_reset, OUTPUT);
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// perform reset
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digitalWrite(_reset, LOW);
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delay(10);
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digitalWrite(_reset, HIGH);
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delay(10);
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}
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if (_rxen != -1) {
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pinMode(_rxen, OUTPUT);
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}
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if (_txen != -1) {
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pinMode(_txen, OUTPUT);
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}
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if (_busy != -1) {
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pinMode(_busy, INPUT);
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}
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if (!_preinit_done) {
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if (!preInit()) {
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return false;
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}
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}
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idle();
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loraMode();
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rxAntEnable();
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setFrequency(frequency);
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// set LNA boost
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// todo: implement this
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//writeRegister(REG_LNA, 0x96);
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setModulationParams(_sf, _bw, _cr);
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setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode);
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// set output power to 2 dBm
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setTxPower(2);
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// set base addresses
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uint8_t basebuf[2] = {0};
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executeOpcode(OP_BUFFER_BASE_ADDR_8X, basebuf, 2);
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return 1;
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}
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void sx128x::end()
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{
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// put in sleep mode
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sleep();
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// stop SPI
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SPI.end();
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_preinit_done = false;
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}
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int sx128x::beginPacket(int implicitHeader)
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{
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// put in standby mode
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idle();
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if (implicitHeader) {
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implicitHeaderMode();
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} else {
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explicitHeaderMode();
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}
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_payloadLength = 0;
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_fifo_tx_addr_ptr = 0;
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setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode);
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return 1;
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}
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int sx128x::endPacket()
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{
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setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode);
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txAntEnable();
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// put in single TX mode
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uint8_t timeout[3] = {0};
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executeOpcode(OP_TX_8X, timeout, 3);
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uint8_t buf[2];
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buf[0] = 0x00;
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buf[1] = 0x00;
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executeOpcodeRead(OP_GET_IRQ_STATUS_8X, buf, 2);
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// wait for TX done
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while ((buf[1] & IRQ_TX_DONE_MASK_8X) == 0) {
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buf[0] = 0x00;
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buf[1] = 0x00;
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executeOpcodeRead(OP_GET_IRQ_STATUS_8X, buf, 2);
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yield();
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}
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// clear IRQ's
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uint8_t mask[2];
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mask[0] = 0x00;
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mask[1] = IRQ_TX_DONE_MASK_8X;
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executeOpcode(OP_CLEAR_IRQ_STATUS_8X, mask, 2);
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return 1;
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}
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uint8_t sx128x::modemStatus() {
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// imitate the register status from the sx1276 / 78
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uint8_t buf[2] = {0};
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executeOpcodeRead(OP_GET_IRQ_STATUS_8X, buf, 2);
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uint8_t clearbuf[2] = {0};
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uint8_t byte = 0x00;
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if ((buf[0] & IRQ_PREAMBLE_DET_MASK_8X) != 0) {
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byte = byte | 0x01 | 0x04;
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// clear register after reading
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clearbuf[0] = 0xFF;
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}
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if ((buf[1] & IRQ_HEADER_DET_MASK_8X) != 0) {
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byte = byte | 0x02 | 0x04;
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// clear register after reading
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clearbuf[1] = 0xFF;
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}
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executeOpcode(OP_CLEAR_IRQ_STATUS_8X, clearbuf, 2);
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return byte;
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}
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uint8_t sx128x::currentRssiRaw() {
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uint8_t byte = 0;
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executeOpcodeRead(OP_CURRENT_RSSI_8X, &byte, 1);
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return byte;
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}
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int ISR_VECT sx128x::currentRssi() {
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uint8_t byte = 0;
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executeOpcodeRead(OP_CURRENT_RSSI_8X, &byte, 1);
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int rssi = -byte / 2;
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return rssi;
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}
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uint8_t sx128x::packetRssiRaw() {
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uint8_t buf[5] = {0};
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executeOpcodeRead(OP_PACKET_STATUS_8X, buf, 5);
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return buf[0];
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}
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int ISR_VECT sx128x::packetRssi() {
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// may need more calculations here
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uint8_t buf[5] = {0};
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executeOpcodeRead(OP_PACKET_STATUS_8X, buf, 5);
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int pkt_rssi = -buf[0] / 2;
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return pkt_rssi;
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}
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uint8_t ISR_VECT sx128x::packetSnrRaw() {
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uint8_t buf[5] = {0};
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executeOpcodeRead(OP_PACKET_STATUS_8X, buf, 5);
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return buf[1];
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}
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float ISR_VECT sx128x::packetSnr() {
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uint8_t buf[5] = {0};
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executeOpcodeRead(OP_PACKET_STATUS_8X, buf, 3);
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return float(buf[1]) * 0.25;
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}
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long sx128x::packetFrequencyError()
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{
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int32_t freqError = 0;
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// todo: implement this, page 120 of sx1280 datasheet
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const float fError = 0.0;
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return static_cast<long>(fError);
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|
}
|
|
|
|
size_t sx128x::write(uint8_t byte)
|
|
{
|
|
return write(&byte, sizeof(byte));
|
|
}
|
|
|
|
size_t sx128x::write(const uint8_t *buffer, size_t size)
|
|
{
|
|
if ((_payloadLength + size) > MAX_PKT_LENGTH) {
|
|
size = MAX_PKT_LENGTH - _payloadLength;
|
|
}
|
|
|
|
// write data
|
|
writeBuffer(buffer, size);
|
|
_payloadLength = _payloadLength + size;
|
|
return size;
|
|
}
|
|
|
|
int ISR_VECT sx128x::available()
|
|
{
|
|
return _rxPacketLength - _packetIndex;
|
|
}
|
|
|
|
int ISR_VECT sx128x::read()
|
|
{
|
|
if (!available()) {
|
|
return -1;
|
|
}
|
|
|
|
uint8_t byte = _packet[_packetIndex];
|
|
_packetIndex++;
|
|
return byte;
|
|
}
|
|
|
|
int sx128x::peek()
|
|
{
|
|
if (!available()) {
|
|
return -1;
|
|
}
|
|
|
|
uint8_t b = _packet[_packetIndex];
|
|
return b;
|
|
}
|
|
|
|
void sx128x::flush()
|
|
{
|
|
}
|
|
|
|
void sx128x::onReceive(void(*callback)(int))
|
|
{
|
|
_onReceive = callback;
|
|
|
|
if (callback) {
|
|
pinMode(_dio0, INPUT);
|
|
|
|
// set preamble and header detection irqs, plus dio0 mask
|
|
uint8_t buf[8];
|
|
|
|
// set irq masks, enable all
|
|
buf[0] = 0xFF;
|
|
buf[1] = 0xFF;
|
|
|
|
// set dio0 masks
|
|
buf[2] = 0x00;
|
|
buf[3] = IRQ_RX_DONE_MASK_8X;
|
|
|
|
// set dio1 masks
|
|
buf[4] = 0x00;
|
|
buf[5] = 0x00;
|
|
|
|
// set dio2 masks
|
|
buf[6] = 0x00;
|
|
buf[7] = 0x00;
|
|
|
|
executeOpcode(OP_SET_IRQ_FLAGS_8X, buf, 8);
|
|
//#ifdef SPI_HAS_NOTUSINGINTERRUPT
|
|
// SPI.usingInterrupt(digitalPinToInterrupt(_dio0));
|
|
//#endif
|
|
attachInterrupt(digitalPinToInterrupt(_dio0), sx128x::onDio0Rise, RISING);
|
|
} else {
|
|
detachInterrupt(digitalPinToInterrupt(_dio0));
|
|
//#ifdef SPI_HAS_NOTUSINGINTERRUPT
|
|
// SPI.notUsingInterrupt(digitalPinToInterrupt(_dio0));
|
|
//#endif
|
|
}
|
|
}
|
|
|
|
void sx128x::receive(int size)
|
|
{
|
|
if (size > 0) {
|
|
implicitHeaderMode();
|
|
|
|
// tell radio payload length
|
|
_rxPacketLength = size;
|
|
//_payloadLength = size;
|
|
//setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode);
|
|
} else {
|
|
explicitHeaderMode();
|
|
}
|
|
|
|
rxAntEnable();
|
|
|
|
uint8_t mode[3] = {0xFF, 0xFF, 0xFF}; // continuous mode
|
|
executeOpcode(OP_RX_8X, mode, 3);
|
|
}
|
|
|
|
void sx128x::idle()
|
|
{
|
|
#if HAS_TCXO
|
|
// STDBY_XOSC
|
|
uint8_t byte = 0x01;
|
|
#else
|
|
// STDBY_RC
|
|
uint8_t byte = 0x00;
|
|
#endif
|
|
executeOpcode(OP_STANDBY_8X, &byte, 1);
|
|
}
|
|
|
|
void sx128x::sleep()
|
|
{
|
|
uint8_t byte = 0x00;
|
|
executeOpcode(OP_SLEEP_8X, &byte, 1);
|
|
}
|
|
|
|
void sx128x::enableTCXO() {
|
|
// todo: need to check how to implement on sx1280
|
|
}
|
|
|
|
void sx128x::disableTCXO() {
|
|
// todo: need to check how to implement on sx1280
|
|
}
|
|
|
|
void sx128x::setTxPower(int level, int outputPin) {
|
|
if (level > 13) {
|
|
level = 13;
|
|
} else if (level < -18) {
|
|
level = -18;
|
|
}
|
|
|
|
_txp = level;
|
|
|
|
level = level + 18;
|
|
|
|
uint8_t tx_buf[2];
|
|
|
|
tx_buf[0] = level;
|
|
tx_buf[1] = 0xE0; // ramping time - 20 microseconds
|
|
|
|
executeOpcode(OP_TX_PARAMS_8X, tx_buf, 2);
|
|
}
|
|
|
|
uint8_t sx128x::getTxPower() {
|
|
return _txp;
|
|
}
|
|
|
|
void sx128x::setFrequency(unsigned long frequency) {
|
|
_frequency = frequency;
|
|
|
|
uint8_t buf[3];
|
|
|
|
uint32_t freq = (uint32_t)((double)frequency / (double)FREQ_STEP_8X);
|
|
|
|
buf[0] = ((freq >> 16) & 0xFF);
|
|
buf[1] = ((freq >> 8) & 0xFF);
|
|
buf[2] = (freq & 0xFF);
|
|
|
|
executeOpcode(OP_RF_FREQ_8X, buf, 3);
|
|
}
|
|
|
|
uint32_t sx128x::getFrequency() {
|
|
// we can't read the frequency on the sx1280
|
|
uint32_t frequency = _frequency;
|
|
|
|
return frequency;
|
|
}
|
|
|
|
void sx128x::setSpreadingFactor(int sf)
|
|
{
|
|
if (sf < 5) {
|
|
sf = 5;
|
|
} else if (sf > 12) {
|
|
sf = 12;
|
|
}
|
|
|
|
_sf = sf << 4;
|
|
|
|
setModulationParams(sf << 4, _bw, _cr);
|
|
handleLowDataRate();
|
|
}
|
|
|
|
long sx128x::getSignalBandwidth()
|
|
{
|
|
int bw = _bw;
|
|
switch (bw) {
|
|
case 0x34: return 203.125E3;
|
|
case 0x26: return 406.25E3;
|
|
case 0x18: return 812.5E3;
|
|
case 0x0A: return 1625E3;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void sx128x::handleLowDataRate(){
|
|
// todo: do i need this??
|
|
}
|
|
|
|
void sx128x::optimizeModemSensitivity(){
|
|
// todo: check if there's anything the sx1280 can do here
|
|
}
|
|
|
|
void sx128x::setSignalBandwidth(long sbw)
|
|
{
|
|
if (sbw <= 203.125E3) {
|
|
_bw = 0x34;
|
|
} else if (sbw <= 406.25E3) {
|
|
_bw = 0x26;
|
|
} else if (sbw <= 812.5E3) {
|
|
_bw = 0x18;
|
|
} else {
|
|
_bw = 0x0A;
|
|
}
|
|
|
|
setModulationParams(_sf, _bw, _cr);
|
|
|
|
handleLowDataRate();
|
|
optimizeModemSensitivity();
|
|
}
|
|
|
|
void sx128x::setCodingRate4(int denominator)
|
|
{
|
|
if (denominator < 5) {
|
|
denominator = 5;
|
|
} else if (denominator > 8) {
|
|
denominator = 8;
|
|
}
|
|
|
|
_cr = denominator - 4;
|
|
|
|
// todo: add support for new interleaving scheme, see page 117 of sx1280
|
|
// datasheet
|
|
|
|
// update cr values for sx1280's use
|
|
|
|
setModulationParams(_sf, _bw, _cr);
|
|
}
|
|
|
|
void sx128x::setPreambleLength(long length)
|
|
{
|
|
_preambleLength = length;
|
|
setPacketParams(length, _implicitHeaderMode, _payloadLength, _crcMode);
|
|
}
|
|
|
|
void sx128x::setSyncWord(int sw)
|
|
{
|
|
// not implemented
|
|
}
|
|
|
|
void sx128x::enableCrc()
|
|
{
|
|
_crcMode = 0x20;
|
|
setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode);
|
|
}
|
|
|
|
void sx128x::disableCrc()
|
|
{
|
|
_crcMode = 0;
|
|
setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode);
|
|
}
|
|
|
|
byte sx128x::random()
|
|
{
|
|
// todo: implement
|
|
}
|
|
|
|
void sx128x::setPins(int ss, int reset, int dio0, int busy, int rxen, int txen)
|
|
{
|
|
_ss = ss;
|
|
_reset = reset;
|
|
_dio0 = dio0;
|
|
_busy = busy;
|
|
_rxen = rxen;
|
|
_txen = txen;
|
|
}
|
|
|
|
void sx128x::setSPIFrequency(uint32_t frequency)
|
|
{
|
|
_spiSettings = SPISettings(frequency, MSBFIRST, SPI_MODE0);
|
|
}
|
|
|
|
void sx128x::dumpRegisters(Stream& out)
|
|
{
|
|
for (int i = 0; i < 128; i++) {
|
|
out.print("0x");
|
|
out.print(i, HEX);
|
|
out.print(": 0x");
|
|
out.println(readRegister(i), HEX);
|
|
}
|
|
}
|
|
|
|
void sx128x::explicitHeaderMode()
|
|
{
|
|
_implicitHeaderMode = 0;
|
|
|
|
setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode);
|
|
}
|
|
|
|
void sx128x::implicitHeaderMode()
|
|
{
|
|
_implicitHeaderMode = 0x80;
|
|
setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode);
|
|
}
|
|
|
|
|
|
void ISR_VECT sx128x::handleDio0Rise()
|
|
{
|
|
uint8_t buf[2];
|
|
|
|
buf[0] = 0x00;
|
|
buf[1] = 0x00;
|
|
|
|
executeOpcodeRead(OP_GET_IRQ_STATUS_8X, buf, 2);
|
|
|
|
executeOpcode(OP_CLEAR_IRQ_STATUS_8X, buf, 2);
|
|
|
|
if ((buf[1] & IRQ_PAYLOAD_CRC_ERROR_MASK_8X) == 0) {
|
|
// received a packet
|
|
_packetIndex = 0;
|
|
|
|
uint8_t rxbuf[2] = {0};
|
|
executeOpcodeRead(OP_RX_BUFFER_STATUS_8X, rxbuf, 2);
|
|
_rxPacketLength = rxbuf[0];
|
|
_fifo_rx_addr_ptr = rxbuf[1];
|
|
readBuffer(_packet, _rxPacketLength);
|
|
|
|
if (_onReceive) {
|
|
_onReceive(_rxPacketLength);
|
|
}
|
|
|
|
}
|
|
}
|
|
|
|
void ISR_VECT sx128x::onDio0Rise()
|
|
{
|
|
sx128x_modem.handleDio0Rise();
|
|
}
|
|
|
|
sx128x sx128x_modem;
|