2021-03-11 12:11:53 +02:00
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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2016-10-06 14:21:30 +03:00
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "esp32-hal-i2c.h"
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2016-10-11 15:11:51 +03:00
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#include "esp32-hal.h"
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2016-10-06 14:21:30 +03:00
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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2016-10-11 14:20:02 +03:00
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#include "freertos/semphr.h"
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2018-06-27 09:01:06 +02:00
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#include "freertos/event_groups.h"
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2017-09-29 09:17:13 -04:00
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#include "driver/periph_ctrl.h"
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2016-10-06 14:21:30 +03:00
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#include "soc/i2c_reg.h"
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2016-10-11 15:11:51 +03:00
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#include "soc/i2c_struct.h"
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2018-06-27 09:01:06 +02:00
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#include "esp_attr.h"
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2019-01-09 10:07:54 +01:00
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#include "esp32-hal-cpu.h" // cpu clock change support 31DEC2018
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2021-04-05 14:23:58 +03:00
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#include "esp_system.h"
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#ifdef ESP_IDF_VERSION_MAJOR // IDF 4+
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#if CONFIG_IDF_TARGET_ESP32 // ESP32/PICO-D4
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2021-04-14 18:10:05 +03:00
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#include "soc/dport_reg.h"
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2021-04-05 14:23:58 +03:00
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#include "esp32/rom/ets_sys.h"
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#elif CONFIG_IDF_TARGET_ESP32S2
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2021-04-14 18:10:05 +03:00
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#include "soc/dport_reg.h"
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2021-04-05 14:23:58 +03:00
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#include "esp32s2/rom/ets_sys.h"
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2021-04-14 18:10:05 +03:00
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#elif CONFIG_IDF_TARGET_ESP32C3
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#include "esp32c3/rom/ets_sys.h"
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2021-04-05 14:23:58 +03:00
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#else
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#error Target CONFIG_IDF_TARGET is not supported
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#endif
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#else // ESP32 Before IDF 4.0
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#include "rom/ets_sys.h"
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#endif
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#if CONFIG_IDF_TARGET_ESP32
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2016-10-11 15:11:51 +03:00
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//#define I2C_DEV(i) (volatile i2c_dev_t *)((i)?DR_REG_I2C1_EXT_BASE:DR_REG_I2C_EXT_BASE)
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//#define I2C_DEV(i) ((i2c_dev_t *)(REG_I2C_BASE(i)))
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2016-10-06 14:21:30 +03:00
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#define I2C_SCL_IDX(p) ((p==0)?I2CEXT0_SCL_OUT_IDX:((p==1)?I2CEXT1_SCL_OUT_IDX:0))
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#define I2C_SDA_IDX(p) ((p==0)?I2CEXT0_SDA_OUT_IDX:((p==1)?I2CEXT1_SDA_OUT_IDX:0))
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2017-03-26 00:27:27 +02:00
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#define DR_REG_I2C_EXT_BASE_FIXED 0x60013000
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#define DR_REG_I2C1_EXT_BASE_FIXED 0x60027000
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2016-10-11 14:20:02 +03:00
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2018-07-24 11:43:45 -06:00
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/* Stickbreaker ISR mode debug support
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ENABLE_I2C_DEBUG_BUFFER
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Wire ReSTART fix, with others (#1717)
* ReSTART fix, Sequencing fix
pr #1665 introduce a problem with ReSTART, when solving this problem I found an interaction between the TxFifo refill, RxFifo empty and CMD[] fill. during certain sequences a dataqueue command would be skipped, this skipping resulted in a mismatch between the contents of the TxFifo and the i2c command sequence. The problem manifested as an ACK error.
In addition to this required bug fix I propose:
* `Wire.begin()` be changed from a `void` to a `bool` this will allow the reset functionality of `Wire.begin()` to be reported. Currently `Wire.begin()` attempts to reset the i2c Peripheral, but cannot report success/failure.
* `Wire.busy()` be added. this `bool` function returns the hardware status of the bus. This status can be use in multi-master environments for application level interleaving of commands, also in single master environment, it can be used to detect a 'hung' bus. With the functional change to `Wire.begin()` this allows app level recover of a hung bus.
* `Wire.lastError()` value updated for all errors, previously when interleaving `Wire.endTransmission(false)` and `Wire.readTransmission(false)`, the 128 byte `Wire.write()` buffer was exhausted without generating and error(very exotic). I discovered this error when I created a sequence of directed reads to a EEPROM. Each directed read used 2 bytes of the 128 byte `write()` buffer, so after 64 consecutive ReSTART writes with ReSTART reads, `Wire()` had no room to record the directed address bytes. It generated just a NAK check without setting the EEPROMs internal register address. The succeeding ReSTART read succeeded at incorrect address.
* Changes to the HAL layer:
** added `i2cGetStatus()` which returns the i2c peripheral status word, used to detect bus_busy currently
** added `i2cDebug()` programmatic control of debug buffer output
** changed `i2cAddQueue()` to allow data_only queue element this will allow a i2c transaction to use multiple data pointers.
** removed direct access to DumpInts(), DumpI2c() from app, use i2cDebug() to set trigger points
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* Update esp32-hal-i2c.c
* Update Wire.cpp
* ReSTART, Sequencing
pr #1665 introduce a problem with ReSTART, when solving this problem I found an interaction between the TxFifo refill, RxFifo empty and CMD[] fill. during certain sequences a dataqueue command would be skipped, this skipping resulted in a mismatch between the contents of the TxFifo and the i2c command sequence. The problem manifested as an ACK error.
In addition to this required bug fix I propose:
* `Wire.begin()` be changed from a `void` to a `bool` this will allow the reset functionality of `Wire.begin()` to be reported. Currently `Wire.begin()` attempts to reset the i2c Peripheral, but cannot report success/failure.
* `Wire.busy()` be added. this `bool` function returns the hardware status of the bus. This status can be use in multi-master environments for application level interleaving of commands, also in single master environment, it can be used to detect a 'hung' bus. With the functional change to `Wire.begin()` this allows app level recover of a hung bus.
* `Wire.lastError()` value updated for all errors, previously when interleaving `Wire.endTransmission(false)` and `Wire.readTransmission(false)`, the 128 byte `Wire.write()` buffer was exhausted without generating and error(very exotic). I discovered this error when I created a sequence of directed reads to a EEPROM. Each directed read used 2 bytes of the 128 byte `write()` buffer, so after 64 consecutive ReSTART writes with ReSTART reads, `Wire()` had no room to record the directed address bytes. It generated just a NAK check without setting the EEPROMs internal register address. The succeeding ReSTART read succeeded at incorrect address.
* Changes to the HAL layer:
** added `i2cGetStatus()` which returns the i2c peripheral status word, used to detect bus_busy currently
** added `i2cDebug()` programmatic control of debug buffer output
** changed `i2cAddQueue()` to allow data_only queue element this will allow a i2c transaction to use multiple data pointers.
** removed direct access to DumpInts(), DumpI2c() from app, use i2cDebug() to set trigger points
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* Forgot DebugFlags Return
@andriyadi found this, total brain fade on my part.
2018-08-14 03:51:15 -06:00
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Enable debug interrupt history buffer, fifoTx history buffer.
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Setting this define will result in 2570 bytes of RAM being used whenever CORE_DEBUG_LEVEL
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is higher than WARNING. Unless you are debugging a problem in the I2C subsystem,
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I would recommend you leave it commented out.
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2018-07-24 11:43:45 -06:00
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*/
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//#define ENABLE_I2C_DEBUG_BUFFER
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#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO) && (defined ENABLE_I2C_DEBUG_BUFFER)
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#define INTBUFFMAX 64
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Wire ReSTART fix, with others (#1717)
* ReSTART fix, Sequencing fix
pr #1665 introduce a problem with ReSTART, when solving this problem I found an interaction between the TxFifo refill, RxFifo empty and CMD[] fill. during certain sequences a dataqueue command would be skipped, this skipping resulted in a mismatch between the contents of the TxFifo and the i2c command sequence. The problem manifested as an ACK error.
In addition to this required bug fix I propose:
* `Wire.begin()` be changed from a `void` to a `bool` this will allow the reset functionality of `Wire.begin()` to be reported. Currently `Wire.begin()` attempts to reset the i2c Peripheral, but cannot report success/failure.
* `Wire.busy()` be added. this `bool` function returns the hardware status of the bus. This status can be use in multi-master environments for application level interleaving of commands, also in single master environment, it can be used to detect a 'hung' bus. With the functional change to `Wire.begin()` this allows app level recover of a hung bus.
* `Wire.lastError()` value updated for all errors, previously when interleaving `Wire.endTransmission(false)` and `Wire.readTransmission(false)`, the 128 byte `Wire.write()` buffer was exhausted without generating and error(very exotic). I discovered this error when I created a sequence of directed reads to a EEPROM. Each directed read used 2 bytes of the 128 byte `write()` buffer, so after 64 consecutive ReSTART writes with ReSTART reads, `Wire()` had no room to record the directed address bytes. It generated just a NAK check without setting the EEPROMs internal register address. The succeeding ReSTART read succeeded at incorrect address.
* Changes to the HAL layer:
** added `i2cGetStatus()` which returns the i2c peripheral status word, used to detect bus_busy currently
** added `i2cDebug()` programmatic control of debug buffer output
** changed `i2cAddQueue()` to allow data_only queue element this will allow a i2c transaction to use multiple data pointers.
** removed direct access to DumpInts(), DumpI2c() from app, use i2cDebug() to set trigger points
*
* Update esp32-hal-i2c.c
* Update Wire.cpp
* ReSTART, Sequencing
pr #1665 introduce a problem with ReSTART, when solving this problem I found an interaction between the TxFifo refill, RxFifo empty and CMD[] fill. during certain sequences a dataqueue command would be skipped, this skipping resulted in a mismatch between the contents of the TxFifo and the i2c command sequence. The problem manifested as an ACK error.
In addition to this required bug fix I propose:
* `Wire.begin()` be changed from a `void` to a `bool` this will allow the reset functionality of `Wire.begin()` to be reported. Currently `Wire.begin()` attempts to reset the i2c Peripheral, but cannot report success/failure.
* `Wire.busy()` be added. this `bool` function returns the hardware status of the bus. This status can be use in multi-master environments for application level interleaving of commands, also in single master environment, it can be used to detect a 'hung' bus. With the functional change to `Wire.begin()` this allows app level recover of a hung bus.
* `Wire.lastError()` value updated for all errors, previously when interleaving `Wire.endTransmission(false)` and `Wire.readTransmission(false)`, the 128 byte `Wire.write()` buffer was exhausted without generating and error(very exotic). I discovered this error when I created a sequence of directed reads to a EEPROM. Each directed read used 2 bytes of the 128 byte `write()` buffer, so after 64 consecutive ReSTART writes with ReSTART reads, `Wire()` had no room to record the directed address bytes. It generated just a NAK check without setting the EEPROMs internal register address. The succeeding ReSTART read succeeded at incorrect address.
* Changes to the HAL layer:
** added `i2cGetStatus()` which returns the i2c peripheral status word, used to detect bus_busy currently
** added `i2cDebug()` programmatic control of debug buffer output
** changed `i2cAddQueue()` to allow data_only queue element this will allow a i2c transaction to use multiple data pointers.
** removed direct access to DumpInts(), DumpI2c() from app, use i2cDebug() to set trigger points
*
* Forgot DebugFlags Return
@andriyadi found this, total brain fade on my part.
2018-08-14 03:51:15 -06:00
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#define FIFOMAX 512
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2018-07-24 11:43:45 -06:00
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static uint32_t intBuff[INTBUFFMAX][3][2];
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static uint32_t intPos[2]= {0,0};
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Wire ReSTART fix, with others (#1717)
* ReSTART fix, Sequencing fix
pr #1665 introduce a problem with ReSTART, when solving this problem I found an interaction between the TxFifo refill, RxFifo empty and CMD[] fill. during certain sequences a dataqueue command would be skipped, this skipping resulted in a mismatch between the contents of the TxFifo and the i2c command sequence. The problem manifested as an ACK error.
In addition to this required bug fix I propose:
* `Wire.begin()` be changed from a `void` to a `bool` this will allow the reset functionality of `Wire.begin()` to be reported. Currently `Wire.begin()` attempts to reset the i2c Peripheral, but cannot report success/failure.
* `Wire.busy()` be added. this `bool` function returns the hardware status of the bus. This status can be use in multi-master environments for application level interleaving of commands, also in single master environment, it can be used to detect a 'hung' bus. With the functional change to `Wire.begin()` this allows app level recover of a hung bus.
* `Wire.lastError()` value updated for all errors, previously when interleaving `Wire.endTransmission(false)` and `Wire.readTransmission(false)`, the 128 byte `Wire.write()` buffer was exhausted without generating and error(very exotic). I discovered this error when I created a sequence of directed reads to a EEPROM. Each directed read used 2 bytes of the 128 byte `write()` buffer, so after 64 consecutive ReSTART writes with ReSTART reads, `Wire()` had no room to record the directed address bytes. It generated just a NAK check without setting the EEPROMs internal register address. The succeeding ReSTART read succeeded at incorrect address.
* Changes to the HAL layer:
** added `i2cGetStatus()` which returns the i2c peripheral status word, used to detect bus_busy currently
** added `i2cDebug()` programmatic control of debug buffer output
** changed `i2cAddQueue()` to allow data_only queue element this will allow a i2c transaction to use multiple data pointers.
** removed direct access to DumpInts(), DumpI2c() from app, use i2cDebug() to set trigger points
*
* Update esp32-hal-i2c.c
* Update Wire.cpp
* ReSTART, Sequencing
pr #1665 introduce a problem with ReSTART, when solving this problem I found an interaction between the TxFifo refill, RxFifo empty and CMD[] fill. during certain sequences a dataqueue command would be skipped, this skipping resulted in a mismatch between the contents of the TxFifo and the i2c command sequence. The problem manifested as an ACK error.
In addition to this required bug fix I propose:
* `Wire.begin()` be changed from a `void` to a `bool` this will allow the reset functionality of `Wire.begin()` to be reported. Currently `Wire.begin()` attempts to reset the i2c Peripheral, but cannot report success/failure.
* `Wire.busy()` be added. this `bool` function returns the hardware status of the bus. This status can be use in multi-master environments for application level interleaving of commands, also in single master environment, it can be used to detect a 'hung' bus. With the functional change to `Wire.begin()` this allows app level recover of a hung bus.
* `Wire.lastError()` value updated for all errors, previously when interleaving `Wire.endTransmission(false)` and `Wire.readTransmission(false)`, the 128 byte `Wire.write()` buffer was exhausted without generating and error(very exotic). I discovered this error when I created a sequence of directed reads to a EEPROM. Each directed read used 2 bytes of the 128 byte `write()` buffer, so after 64 consecutive ReSTART writes with ReSTART reads, `Wire()` had no room to record the directed address bytes. It generated just a NAK check without setting the EEPROMs internal register address. The succeeding ReSTART read succeeded at incorrect address.
* Changes to the HAL layer:
** added `i2cGetStatus()` which returns the i2c peripheral status word, used to detect bus_busy currently
** added `i2cDebug()` programmatic control of debug buffer output
** changed `i2cAddQueue()` to allow data_only queue element this will allow a i2c transaction to use multiple data pointers.
** removed direct access to DumpInts(), DumpI2c() from app, use i2cDebug() to set trigger points
*
* Forgot DebugFlags Return
@andriyadi found this, total brain fade on my part.
2018-08-14 03:51:15 -06:00
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static uint16_t fifoBuffer[FIFOMAX];
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static uint16_t fifoPos = 0;
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2018-07-24 11:43:45 -06:00
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#endif
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2018-06-27 09:01:06 +02:00
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// start from tools/sdk/include/soc/soc/i2c_struct.h
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typedef union {
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struct {
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uint32_t byte_num: 8; /*Byte_num represent the number of data need to be send or data need to be received.*/
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uint32_t ack_en: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/
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uint32_t ack_exp: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/
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uint32_t ack_val: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/
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uint32_t op_code: 3; /*op_code is the command 0：RSTART 1：WRITE 2：READ 3：STOP . 4:END.*/
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uint32_t reserved14: 17;
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uint32_t done: 1; /*When command0 is done in I2C Master mode this bit changes to high level.*/
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};
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uint32_t val;
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} I2C_COMMAND_t;
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typedef union {
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struct {
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uint32_t rx_fifo_full_thrhd: 5;
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uint32_t tx_fifo_empty_thrhd:5; //Config tx_fifo empty threhd value when using apb fifo access * /
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uint32_t nonfifo_en: 1; //Set this bit to enble apb nonfifo access. * /
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uint32_t fifo_addr_cfg_en: 1; //When this bit is set to 1 then the byte after address represent the offset address of I2C Slave's ram. * /
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uint32_t rx_fifo_rst: 1; //Set this bit to reset rx fifo when using apb fifo access. * /
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// chuck while this bit is 1, the RX fifo is held in REST, Toggle it * /
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uint32_t tx_fifo_rst: 1; //Set this bit to reset tx fifo when using apb fifo access. * /
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// chuck while this bit is 1, the TX fifo is held in REST, Toggle it * /
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