arduino-esp32/tools/sdk/esp32/ld/memory.ld

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IDF master d93887f9f (#5336) * Update toolchain * Update package_esp32_index.template.json * add optional component dependencies after Kconfig options are known (#5404) Until this commit, Kconfig options (e.g. CONFIG_TINYUSB_ENABLED) were used in conditions preceding idf_component_register to determine which components need to be added to `arduino` component requirements. However the Kconfig options aren't known at the early expansion stage, when the component CMakeLists.txt files are expanded the first time and requirements are evaluated. So all the conditions evaluated as if the options were not set. This commit changes the logic to only add these components as dependencies when the Kconfig options are known. Dependencies become "weak", which means that if one of the components isn't included into the build for some reason, it is not added as a dependency. This may happen, for example, if the component is not present in the `components` directory or is excluded by setting `COMPONENTS` variable in the project CMakeLists.txt file. This also ensures that if the component is not present, it will not be added as a dependency, and this will allow the build to proceed. Follow-up to https://github.com/espressif/arduino-esp32/pull/5391. Closes https://github.com/espressif/arduino-esp32/issues/5319. * IDF master d93887f9f * PlatformIO updates for CI (#5387) * Update PlatformIO CI build script - Switch to the latest toolchains 8.4.0 for ESP32, ESP32S2, ESP32C3 - Use PlatformIO from master branch for better robustness * Update package.json for PlatformIO Co-authored-by: Ivan Grokhotkov <ivan@espressif.com> Co-authored-by: Valerii Koval <valeros@users.noreply.github.com>
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/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
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/* ESP32 Linker Script Memory Layout
This file describes the memory layout (memory blocks) as virtual
memory addresses.
esp32.project.ld contains output sections to link compiler output
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into these memory blocks.
***
This linker script is passed through the C preprocessor to include
configuration options.
Please use preprocessor features sparingly! Restrict
to simple macros with numeric values, and/or #if/#endif blocks.
*/
/*
* Automatically generated file. DO NOT EDIT.
* Espressif IoT Development Framework (ESP-IDF) Configuration Header
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*/
/* List of deprecated options */
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/* If BT is not built at all */
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MEMORY
{
/* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
are connected to the data port of the CPU and eg allow bytewise access. */
/* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
iram0_0_seg (RX) : org = 0x40080000, len = 0x20000
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/* Even though the segment name is iram, it is actually mapped to flash
*/
iram0_2_seg (RX) : org = 0x400D0020, len = 0x330000-0x20
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/*
(0x20 offset above is a convenience for the app binary image generation.
Flash cache has 64KB pages. The .bin file which is flashed to the chip
has a 0x18 byte file header, and each segment has a 0x08 byte segment
header. Setting this offset makes it simple to meet the flash cache MMU's
constraint that (paddr % 64KB == vaddr % 64KB).)
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*/
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/* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
Enabling Bluetooth & Trace Memory features in menuconfig will decrease
the amount of RAM available.
Note: Length of this section *should* be 0x50000, and this extra DRAM is available
in heap at runtime. However due to static ROM memory usage at this 176KB mark, the
additional static memory temporarily cannot be used.
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*/
dram0_0_seg (RW) : org = 0x3FFB0000 + 0xdb5c,
len = 0x2c200 - 0xdb5c
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/* Flash mapped constant data */
drom0_0_seg (R) : org = 0x3F400020, len = 0x400000-0x20
/* (See iram0_2_seg for meaning of 0x20 offset in the above.) */
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/* RTC fast memory (executable). Persists over deep sleep.
*/
rtc_iram_seg(RWX) : org = 0x400C0000, len = 0x2000
/* RTC fast memory (same block as above), viewed from data bus */
rtc_data_seg(RW) : org = 0x3ff80000, len = 0x2000 - 0
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/* RTC slow memory (data accessible). Persists over deep sleep.
Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.
*/
rtc_slow_seg(RW) : org = 0x50000000 + 512,
len = 0x2000 - 512
/* external memory ,including data and text */
extern_ram_seg(RWX) : org = 0x3F800000,
len = 0x400000
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}
_static_data_end = _bss_end;
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/* Heap ends at top of dram0_0_seg */
_heap_end = 0x40000000 - 0x0;
_data_seg_org = ORIGIN(rtc_data_seg);
/* The lines below define location alias for .rtc.data section based on Kconfig option.
When the option is not defined then use slow memory segment
else the data will be placed in fast memory segment */
REGION_ALIAS("rtc_data_location", rtc_slow_seg );
REGION_ALIAS("default_code_seg", iram0_2_seg);
REGION_ALIAS("default_rodata_seg", drom0_0_seg);
/**
* If rodata default segment is placed in `drom0_0_seg`, then flash's first rodata section must
* also be first in the segment.
*/
ASSERT(_rodata_start == ORIGIN(default_rodata_seg),
".flash.appdesc section must be placed at the beginning of the rodata segment.")