2016-10-06 13:21:30 +02:00
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "esp32-hal-i2c.h"
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2016-10-11 14:11:51 +02:00
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#include "esp32-hal.h"
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2016-10-06 13:21:30 +02:00
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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2016-10-11 13:20:02 +02:00
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#include "freertos/semphr.h"
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2016-10-06 13:21:30 +02:00
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#include "rom/ets_sys.h"
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2017-09-29 15:17:13 +02:00
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#include "driver/periph_ctrl.h"
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2016-10-06 13:21:30 +02:00
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#include "soc/i2c_reg.h"
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2016-10-11 14:11:51 +02:00
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#include "soc/i2c_struct.h"
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2016-10-06 13:21:30 +02:00
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#include "soc/dport_reg.h"
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2016-10-11 14:11:51 +02:00
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//#define I2C_DEV(i) (volatile i2c_dev_t *)((i)?DR_REG_I2C1_EXT_BASE:DR_REG_I2C_EXT_BASE)
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//#define I2C_DEV(i) ((i2c_dev_t *)(REG_I2C_BASE(i)))
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2016-10-06 13:21:30 +02:00
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#define I2C_SCL_IDX(p) ((p==0)?I2CEXT0_SCL_OUT_IDX:((p==1)?I2CEXT1_SCL_OUT_IDX:0))
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#define I2C_SDA_IDX(p) ((p==0)?I2CEXT0_SDA_OUT_IDX:((p==1)?I2CEXT1_SDA_OUT_IDX:0))
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2017-03-25 23:27:27 +01:00
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#define DR_REG_I2C_EXT_BASE_FIXED 0x60013000
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#define DR_REG_I2C1_EXT_BASE_FIXED 0x60027000
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2016-10-11 13:20:02 +02:00
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2017-10-21 14:26:46 +02:00
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#define COMMAND_BUFFER_LENGTH 16
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2016-10-11 13:20:02 +02:00
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struct i2c_struct_t {
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i2c_dev_t * dev;
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2016-11-18 14:07:25 +01:00
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#if !CONFIG_DISABLE_HAL_LOCKS
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2016-10-11 13:20:02 +02:00
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xSemaphoreHandle lock;
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2016-11-18 14:07:25 +01:00
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#endif
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2016-10-11 13:20:02 +02:00
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uint8_t num;
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};
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enum {
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I2C_CMD_RSTART,
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I2C_CMD_WRITE,
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I2C_CMD_READ,
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I2C_CMD_STOP,
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I2C_CMD_END
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};
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2016-11-18 14:07:25 +01:00
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#if CONFIG_DISABLE_HAL_LOCKS
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#define I2C_MUTEX_LOCK()
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#define I2C_MUTEX_UNLOCK()
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static i2c_t _i2c_bus_array[2] = {
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2017-03-25 23:27:27 +01:00
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{(volatile i2c_dev_t *)(DR_REG_I2C_EXT_BASE_FIXED), 0},
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{(volatile i2c_dev_t *)(DR_REG_I2C1_EXT_BASE_FIXED), 1}
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2016-11-18 14:07:25 +01:00
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};
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#else
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2016-10-11 13:20:02 +02:00
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#define I2C_MUTEX_LOCK() do {} while (xSemaphoreTake(i2c->lock, portMAX_DELAY) != pdPASS)
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#define I2C_MUTEX_UNLOCK() xSemaphoreGive(i2c->lock)
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static i2c_t _i2c_bus_array[2] = {
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2017-03-25 23:27:27 +01:00
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{(volatile i2c_dev_t *)(DR_REG_I2C_EXT_BASE_FIXED), NULL, 0},
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{(volatile i2c_dev_t *)(DR_REG_I2C1_EXT_BASE_FIXED), NULL, 1}
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2016-10-11 13:20:02 +02:00
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};
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2016-11-18 14:07:25 +01:00
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#endif
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2016-10-11 13:20:02 +02:00
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2016-10-11 14:11:51 +02:00
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i2c_err_t i2cAttachSCL(i2c_t * i2c, int8_t scl)
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2016-10-06 13:21:30 +02:00
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{
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2016-10-11 13:20:02 +02:00
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if(i2c == NULL){
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2016-10-11 14:11:51 +02:00
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return I2C_ERROR_DEV;
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2016-10-11 13:20:02 +02:00
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}
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2016-12-14 12:11:10 +01:00
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pinMode(scl, OUTPUT_OPEN_DRAIN | PULLUP);
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2016-10-06 13:21:30 +02:00
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pinMatrixOutAttach(scl, I2C_SCL_IDX(i2c->num), false, false);
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pinMatrixInAttach(scl, I2C_SCL_IDX(i2c->num), false);
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2016-10-11 14:11:51 +02:00
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return I2C_ERROR_OK;
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2016-10-06 13:21:30 +02:00
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}
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2016-10-11 14:11:51 +02:00
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i2c_err_t i2cDetachSCL(i2c_t * i2c, int8_t scl)
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2016-10-06 13:21:30 +02:00
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{
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2016-10-11 13:20:02 +02:00
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if(i2c == NULL){
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2016-10-11 14:11:51 +02:00
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return I2C_ERROR_DEV;
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2016-10-11 13:20:02 +02:00
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}
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2016-10-06 13:21:30 +02:00
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pinMatrixOutDetach(scl, false, false);
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pinMatrixInDetach(I2C_SCL_IDX(i2c->num), false, false);
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pinMode(scl, INPUT);
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2016-10-11 14:11:51 +02:00
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return I2C_ERROR_OK;
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2016-10-06 13:21:30 +02:00
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}
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2016-10-11 14:11:51 +02:00
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i2c_err_t i2cAttachSDA(i2c_t * i2c, int8_t sda)
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2016-10-06 13:21:30 +02:00
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{
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2016-10-11 13:20:02 +02:00
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if(i2c == NULL){
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2016-10-11 14:11:51 +02:00
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return I2C_ERROR_DEV;
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2016-10-11 13:20:02 +02:00
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}
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2016-12-14 12:11:10 +01:00
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pinMode(sda, OUTPUT_OPEN_DRAIN | PULLUP);
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2016-10-06 13:21:30 +02:00
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pinMatrixOutAttach(sda, I2C_SDA_IDX(i2c->num), false, false);
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pinMatrixInAttach(sda, I2C_SDA_IDX(i2c->num), false);
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2016-10-11 14:11:51 +02:00
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return I2C_ERROR_OK;
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2016-10-06 13:21:30 +02:00
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}
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2016-10-11 14:11:51 +02:00
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i2c_err_t i2cDetachSDA(i2c_t * i2c, int8_t sda)
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2016-10-06 13:21:30 +02:00
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{
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2016-10-11 13:20:02 +02:00
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if(i2c == NULL){
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2016-10-11 14:11:51 +02:00
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return I2C_ERROR_DEV;
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2016-10-11 13:20:02 +02:00
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}
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2016-10-06 13:21:30 +02:00
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pinMatrixOutDetach(sda, false, false);
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pinMatrixInDetach(I2C_SDA_IDX(i2c->num), false, false);
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pinMode(sda, INPUT);
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2016-10-11 14:11:51 +02:00
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return I2C_ERROR_OK;
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2016-10-06 13:21:30 +02:00
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}
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/*
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* index - command index (0 to 15)
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* op_code - is the command
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2016-10-08 16:32:11 +02:00
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* byte_num - This register is to store the amounts of data that is read and written. byte_num in RSTART, STOP, END is null.
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2016-10-06 13:21:30 +02:00
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* ack_val - Each data byte is terminated by an ACK bit used to set the bit level.
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* ack_exp - This bit is to set an expected ACK value for the transmitter.
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* ack_check - This bit is to decide whether the transmitter checks ACK bit. 1 means yes and 0 means no.
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* */
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void i2cSetCmd(i2c_t * i2c, uint8_t index, uint8_t op_code, uint8_t byte_num, bool ack_val, bool ack_exp, bool ack_check)
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{
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i2c->dev->command[index].val = 0;
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i2c->dev->command[index].ack_en = ack_check;
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i2c->dev->command[index].ack_exp = ack_exp;
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i2c->dev->command[index].ack_val = ack_val;
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i2c->dev->command[index].byte_num = byte_num;
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i2c->dev->command[index].op_code = op_code;
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}
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2017-10-21 14:26:46 +02:00
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void i2cResetCmd(i2c_t * i2c) {
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uint8_t i;
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2016-11-16 23:46:56 +01:00
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for(i=0;i<16;i++){
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i2c->dev->command[i].val = 0;
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}
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}
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2017-10-21 14:26:46 +02:00
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void i2cResetFiFo(i2c_t * i2c) {
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2016-10-11 13:20:02 +02:00
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i2c->dev->fifo_conf.tx_fifo_rst = 1;
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i2c->dev->fifo_conf.tx_fifo_rst = 0;
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i2c->dev->fifo_conf.rx_fifo_rst = 1;
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i2c->dev->fifo_conf.rx_fifo_rst = 0;
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}
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2017-10-21 14:26:46 +02:00
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i2c_err_t i2cWrite(i2c_t * i2c, uint16_t address, bool addr_10bit, uint8_t * data, uint16_t len, bool sendStop)
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2016-10-06 13:21:30 +02:00
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{
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2016-10-08 16:32:11 +02:00
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int i;
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2017-10-21 14:26:46 +02:00
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uint16_t index = 0;
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uint16_t dataLen = len + (addr_10bit?2:1);
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2016-10-06 13:21:30 +02:00
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address = (address << 1);
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2016-10-11 13:20:02 +02:00
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if(i2c == NULL){
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2016-10-11 14:11:51 +02:00
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return I2C_ERROR_DEV;
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2016-10-11 13:20:02 +02:00
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}
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I2C_MUTEX_LOCK();
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2017-09-29 15:17:13 +02:00
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if (i2c->dev->status_reg.bus_busy == 1)
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{
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2017-09-29 15:24:06 +02:00
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log_e( "Busy Timeout! Addr: %x", address >> 1 );
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2017-09-29 15:17:13 +02:00
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I2C_MUTEX_UNLOCK();
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return I2C_ERROR_BUSY;
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}
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2016-10-06 13:21:30 +02:00
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while(dataLen) {
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uint8_t willSend = (dataLen > 32)?32:dataLen;
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uint8_t dataSend = willSend;
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2016-10-08 16:32:11 +02:00
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2016-10-10 13:54:36 +02:00
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i2cResetFiFo(i2c);
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2016-11-16 23:46:56 +01:00
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i2cResetCmd(i2c);
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2016-12-14 01:41:22 +01:00
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//Clear Interrupts
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i2c->dev->int_clr.val = 0xFFFFFFFF;
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2016-10-10 13:54:36 +02:00
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2016-10-08 16:32:11 +02:00
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//CMD START
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i2cSetCmd(i2c, 0, I2C_CMD_RSTART, 0, false, false, false);
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//CMD WRITE(ADDRESS + DATA)
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2016-10-06 13:21:30 +02:00
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if(!index) {
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2017-10-21 21:14:14 +02:00
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if(addr_10bit){// address is leftshifted with Read/Write bit set
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i2c->dev->fifo_data.data = (((address >> 8) & 0x6) | 0xF0); // send a9:a8 plus 1111 0xxW mask
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i2c->dev->fifo_data.data = ((address >> 1) & 0xFF); // send a7:a0, remove W bit (7bit address style)
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dataSend -= 2;
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}
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else { // 7bit address
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i2c->dev->fifo_data.data = address & 0xFF;
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2016-10-06 13:21:30 +02:00
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dataSend--;
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}
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}
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2016-10-08 16:32:11 +02:00
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i = 0;
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2016-10-06 13:21:30 +02:00
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while(i<dataSend) {
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i++;
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2016-12-14 01:41:22 +01:00
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i2c->dev->fifo_data.val = data[index++];
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while(i2c->dev->status_reg.tx_fifo_cnt < i);
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2016-10-06 13:21:30 +02:00
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}
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2016-10-08 16:32:11 +02:00
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i2cSetCmd(i2c, 1, I2C_CMD_WRITE, willSend, false, false, true);
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2016-10-06 13:21:30 +02:00
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dataLen -= willSend;
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2016-10-08 16:32:11 +02:00
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//CMD STOP or CMD END if there is more data
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2016-12-14 01:41:22 +01:00
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if(dataLen || !sendStop) {
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2016-10-06 13:21:30 +02:00
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i2cSetCmd(i2c, 2, I2C_CMD_END, 0, false, false, false);
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} else if(sendStop) {
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2016-10-08 16:32:11 +02:00
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i2cSetCmd(i2c, 2, I2C_CMD_STOP, 0, false, false, false);
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2016-10-06 13:21:30 +02:00
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}
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2016-10-08 16:32:11 +02:00
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//START Transmission
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2016-10-06 13:21:30 +02:00
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i2c->dev->ctr.trans_start = 1;
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2016-10-08 16:32:11 +02:00
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//WAIT Transmission
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2016-12-14 01:41:22 +01:00
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uint32_t startAt = millis();
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2016-10-08 16:32:11 +02:00
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while(1) {
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2016-12-14 01:41:22 +01:00
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//have been looping for too long
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if((millis() - startAt)>50){
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2017-09-29 15:24:06 +02:00
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log_e("Timeout! Addr: %x", address >> 1);
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2016-12-14 01:41:22 +01:00
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I2C_MUTEX_UNLOCK();
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return I2C_ERROR_BUS;
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}
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2016-10-10 13:54:36 +02:00
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//Bus failed (maybe check for this while waiting?
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if(i2c->dev->int_raw.arbitration_lost) {
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2017-09-29 15:24:06 +02:00
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log_e("Bus Fail! Addr: %x", address >> 1);
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2016-10-11 13:20:02 +02:00
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I2C_MUTEX_UNLOCK();
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2016-10-11 14:11:51 +02:00
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return I2C_ERROR_BUS;
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2016-10-10 13:54:36 +02:00
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}
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//Bus timeout
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if(i2c->dev->int_raw.time_out) {
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2017-09-29 15:24:06 +02:00
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log_e("Bus Timeout! Addr: %x", address >> 1);
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2016-10-11 13:20:02 +02:00
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I2C_MUTEX_UNLOCK();
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2016-10-11 14:11:51 +02:00
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return I2C_ERROR_TIMEOUT;
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2016-10-10 13:54:36 +02:00
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}
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//Transmission did not finish and ACK_ERR is set
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if(i2c->dev->int_raw.ack_err) {
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2017-09-29 15:24:06 +02:00
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log_w("Ack Error! Addr: %x", address >> 1);
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2017-10-21 08:40:53 +02:00
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while((i2c->dev->status_reg.bus_busy) && ((millis() - startAt)<50));
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2016-10-11 13:20:02 +02:00
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I2C_MUTEX_UNLOCK();
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2016-10-11 14:11:51 +02:00
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return I2C_ERROR_ACK;
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2016-10-10 13:54:36 +02:00
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}
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2016-12-14 01:41:22 +01:00
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if((sendStop && i2c->dev->command[2].done) || !i2c->dev->status_reg.bus_busy){
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2016-10-08 16:32:11 +02:00
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break;
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}
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2016-10-06 13:21:30 +02:00
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}
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2016-10-08 16:32:11 +02:00
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2016-10-06 13:21:30 +02:00
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}
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2016-10-11 13:20:02 +02:00
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I2C_MUTEX_UNLOCK();
|
2016-10-11 14:11:51 +02:00
|
|
|
return I2C_ERROR_OK;
|
2016-10-06 13:21:30 +02:00
|
|
|
}
|
|
|
|
|
2017-10-21 14:26:46 +02:00
|
|
|
uint8_t inc( uint8_t* index )
|
|
|
|
{
|
|
|
|
uint8_t i = index[ 0 ];
|
|
|
|
if (++index[ 0 ] == COMMAND_BUFFER_LENGTH)
|
|
|
|
{
|
|
|
|
index[ 0 ] = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
return i;
|
|
|
|
}
|
|
|
|
|
|
|
|
i2c_err_t i2cRead(i2c_t * i2c, uint16_t address, bool addr_10bit, uint8_t * data, uint16_t len, bool sendStop)
|
2016-10-06 13:21:30 +02:00
|
|
|
{
|
|
|
|
address = (address << 1) | 1;
|
|
|
|
uint8_t addrLen = (addr_10bit?2:1);
|
2017-10-21 14:26:46 +02:00
|
|
|
uint8_t amountRead[16];
|
|
|
|
uint16_t index = 0;
|
|
|
|
uint8_t cmdIdx = 0, currentCmdIdx = 0, nextCmdCount;
|
|
|
|
bool stopped = false, isEndNear = false;
|
2016-10-06 13:21:30 +02:00
|
|
|
uint8_t willRead;
|
|
|
|
|
2016-10-11 13:20:02 +02:00
|
|
|
if(i2c == NULL){
|
2016-10-11 14:11:51 +02:00
|
|
|
return I2C_ERROR_DEV;
|
2016-10-11 13:20:02 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
I2C_MUTEX_LOCK();
|
|
|
|
|
2017-09-29 15:17:13 +02:00
|
|
|
if (i2c->dev->status_reg.bus_busy == 1)
|
|
|
|
{
|
2017-09-29 15:24:06 +02:00
|
|
|
log_w( "Busy Timeout! Addr: %x", address >> 1 );
|
2017-09-29 15:17:13 +02:00
|
|
|
I2C_MUTEX_UNLOCK();
|
|
|
|
return I2C_ERROR_BUSY;
|
|
|
|
}
|
|
|
|
|
2016-10-10 13:54:36 +02:00
|
|
|
i2cResetFiFo(i2c);
|
2016-11-16 23:46:56 +01:00
|
|
|
i2cResetCmd(i2c);
|
2016-10-10 13:54:36 +02:00
|
|
|
|
2016-10-08 16:32:11 +02:00
|
|
|
//CMD START
|
2017-10-21 14:26:46 +02:00
|
|
|
i2cSetCmd(i2c, cmdIdx++, I2C_CMD_RSTART, 0, false, false, false);
|
2016-10-08 16:32:11 +02:00
|
|
|
|
|
|
|
//CMD WRITE ADDRESS
|
2017-10-23 20:40:33 +02:00
|
|
|
if (addr_10bit) { // address is left-shifted with Read/Write bit set
|
2017-10-21 21:14:14 +02:00
|
|
|
i2c->dev->fifo_data.data = (((address >> 8) & 0x6) | 0xF1); // send a9:a8 plus 1111 0xxR mask
|
|
|
|
i2c->dev->fifo_data.data = ((address >> 1) & 0xFF); // send a7:a0, remove R bit (7bit address style)
|
|
|
|
}
|
|
|
|
else { // 7bit address
|
|
|
|
i2c->dev->fifo_data.data = address & 0xFF;
|
2016-10-06 13:21:30 +02:00
|
|
|
}
|
2017-10-21 14:26:46 +02:00
|
|
|
i2cSetCmd(i2c, cmdIdx++, I2C_CMD_WRITE, addrLen, false, false, true);
|
|
|
|
nextCmdCount = cmdIdx;
|
2017-10-21 21:14:14 +02:00
|
|
|
|
2017-10-21 14:26:46 +02:00
|
|
|
//Clear Interrupts
|
|
|
|
i2c->dev->int_clr.val = 0x00001FFF;
|
2016-10-08 16:32:11 +02:00
|
|
|
|
2017-10-21 14:26:46 +02:00
|
|
|
//START Transmission
|
|
|
|
i2c->dev->ctr.trans_start = 1;
|
|
|
|
while (!stopped) {
|
2016-10-08 16:32:11 +02:00
|
|
|
//WAIT Transmission
|
2016-12-14 01:41:22 +01:00
|
|
|
uint32_t startAt = millis();
|
2016-10-08 16:32:11 +02:00
|
|
|
while(1) {
|
2016-12-14 01:41:22 +01:00
|
|
|
//have been looping for too long
|
2017-10-21 14:26:46 +02:00
|
|
|
if((millis() - startAt)>50) {
|
|
|
|
log_e("Timeout! Addr: %x, index %d", (address >> 1), index);
|
2016-12-14 01:41:22 +01:00
|
|
|
I2C_MUTEX_UNLOCK();
|
|
|
|
return I2C_ERROR_BUS;
|
|
|
|
}
|
|
|
|
|
2016-10-10 13:54:36 +02:00
|
|
|
//Bus failed (maybe check for this while waiting?
|
|
|
|
if(i2c->dev->int_raw.arbitration_lost) {
|
2017-10-21 14:26:46 +02:00
|
|
|
log_e("Bus Fail! Addr: %x", (address >> 1));
|
2016-10-11 13:20:02 +02:00
|
|
|
I2C_MUTEX_UNLOCK();
|
2016-10-11 14:11:51 +02:00
|
|
|
return I2C_ERROR_BUS;
|
2016-10-10 13:54:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
//Bus timeout
|
|
|
|
if(i2c->dev->int_raw.time_out) {
|
2017-10-21 14:26:46 +02:00
|
|
|
log_e("Bus Timeout! Addr: %x, index %d", (address >> 1), index );
|
2016-10-11 13:20:02 +02:00
|
|
|
I2C_MUTEX_UNLOCK();
|
2016-10-11 14:11:51 +02:00
|
|
|
return I2C_ERROR_TIMEOUT;
|
2016-10-10 13:54:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
//Transmission did not finish and ACK_ERR is set
|
|
|
|
if(i2c->dev->int_raw.ack_err) {
|
2017-09-29 15:24:06 +02:00
|
|
|
log_w("Ack Error! Addr: %x", address >> 1);
|
2017-10-21 14:26:46 +02:00
|
|
|
while((i2c->dev->status_reg.bus_busy) && ((millis() - startAt)<50));
|
2016-10-11 13:20:02 +02:00
|
|
|
I2C_MUTEX_UNLOCK();
|
2016-10-11 14:11:51 +02:00
|
|
|
return I2C_ERROR_ACK;
|
2016-10-10 13:54:36 +02:00
|
|
|
}
|
2016-12-14 01:41:22 +01:00
|
|
|
|
2017-10-21 14:26:46 +02:00
|
|
|
// Save bytes from the buffer as they arrive instead of doing them at the end of the loop since there is no
|
|
|
|
// pause from an END operation in this approach.
|
|
|
|
if((!isEndNear) && (nextCmdCount < 2)) {
|
2017-10-24 00:21:00 +02:00
|
|
|
willRead = ((len>32)?32:len);
|
|
|
|
if (willRead > 0) {
|
2017-10-21 14:26:46 +02:00
|
|
|
if (willRead > 1) {
|
|
|
|
i2cSetCmd(i2c, cmdIdx, I2C_CMD_READ, (amountRead[ inc( &cmdIdx ) ] = willRead -1), false, false, false);
|
|
|
|
nextCmdCount++;
|
|
|
|
}
|
|
|
|
i2cSetCmd(i2c, cmdIdx, I2C_CMD_READ, (amountRead[ inc( &cmdIdx ) ] = 1), (len<=32), false, false);
|
|
|
|
nextCmdCount++;
|
|
|
|
len -= willRead;
|
|
|
|
} else {
|
|
|
|
i2cSetCmd(i2c, inc( &cmdIdx ), I2C_CMD_STOP, 0, false, false, false);
|
|
|
|
isEndNear = true;
|
|
|
|
nextCmdCount++;
|
|
|
|
}
|
2016-10-08 16:32:11 +02:00
|
|
|
}
|
|
|
|
|
2017-10-21 14:26:46 +02:00
|
|
|
if(i2c->dev->command[currentCmdIdx].done) {
|
|
|
|
nextCmdCount--;
|
|
|
|
if (i2c->dev->command[currentCmdIdx].op_code == I2C_CMD_READ) {
|
|
|
|
while(amountRead[currentCmdIdx]>0) {
|
|
|
|
data[index++] = i2c->dev->fifo_data.val & 0xFF;
|
|
|
|
amountRead[currentCmdIdx]--;
|
|
|
|
}
|
|
|
|
i2cResetFiFo(i2c);
|
|
|
|
} else if (i2c->dev->command[currentCmdIdx].op_code == I2C_CMD_STOP) {
|
|
|
|
stopped = true;
|
|
|
|
}
|
|
|
|
inc( ¤tCmdIdx );
|
|
|
|
break;
|
|
|
|
}
|
2016-10-06 13:21:30 +02:00
|
|
|
}
|
|
|
|
}
|
2016-10-11 13:20:02 +02:00
|
|
|
I2C_MUTEX_UNLOCK();
|
2017-10-21 14:26:46 +02:00
|
|
|
|
2016-10-11 14:11:51 +02:00
|
|
|
return I2C_ERROR_OK;
|
2016-10-06 13:21:30 +02:00
|
|
|
}
|
|
|
|
|
2016-10-11 14:11:51 +02:00
|
|
|
i2c_err_t i2cSetFrequency(i2c_t * i2c, uint32_t clk_speed)
|
2016-10-06 13:21:30 +02:00
|
|
|
{
|
2016-10-11 13:20:02 +02:00
|
|
|
if(i2c == NULL){
|
2016-10-11 14:11:51 +02:00
|
|
|
return I2C_ERROR_DEV;
|
2016-10-11 13:20:02 +02:00
|
|
|
}
|
|
|
|
|
2016-12-14 01:41:22 +01:00
|
|
|
uint32_t period = (APB_CLK_FREQ/clk_speed) / 2;
|
|
|
|
uint32_t halfPeriod = period/2;
|
|
|
|
uint32_t quarterPeriod = period/4;
|
|
|
|
|
2016-10-11 13:20:02 +02:00
|
|
|
I2C_MUTEX_LOCK();
|
2016-12-14 01:41:22 +01:00
|
|
|
//the clock num during SCL is low level
|
2017-01-05 12:54:40 +01:00
|
|
|
i2c->dev->scl_low_period.period = period;
|
2016-12-14 01:41:22 +01:00
|
|
|
//the clock num during SCL is high level
|
2016-10-06 13:21:30 +02:00
|
|
|
i2c->dev->scl_high_period.period = period;
|
|
|
|
|
2016-12-14 01:41:22 +01:00
|
|
|
//the clock num between the negedge of SDA and negedge of SCL for start mark
|
|
|
|
i2c->dev->scl_start_hold.time = halfPeriod;
|
|
|
|
//the clock num between the posedge of SCL and the negedge of SDA for restart mark
|
|
|
|
i2c->dev->scl_rstart_setup.time = halfPeriod;
|
2016-10-06 13:21:30 +02:00
|
|
|
|
2016-12-14 01:41:22 +01:00
|
|
|
//the clock num after the STOP bit's posedge
|
|
|
|
i2c->dev->scl_stop_hold.time = halfPeriod;
|
|
|
|
//the clock num between the posedge of SCL and the posedge of SDA
|
|
|
|
i2c->dev->scl_stop_setup.time = halfPeriod;
|
2016-10-06 13:21:30 +02:00
|
|
|
|
2016-12-14 01:41:22 +01:00
|
|
|
//the clock num I2C used to hold the data after the negedge of SCL.
|
|
|
|
i2c->dev->sda_hold.time = quarterPeriod;
|
|
|
|
//the clock num I2C used to sample data on SDA after the posedge of SCL
|
|
|
|
i2c->dev->sda_sample.time = quarterPeriod;
|
2016-10-11 13:20:02 +02:00
|
|
|
I2C_MUTEX_UNLOCK();
|
2016-10-11 14:11:51 +02:00
|
|
|
return I2C_ERROR_OK;
|
2016-10-06 13:21:30 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t i2cGetFrequency(i2c_t * i2c)
|
|
|
|
{
|
2016-10-11 13:20:02 +02:00
|
|
|
if(i2c == NULL){
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-01-05 12:54:40 +01:00
|
|
|
return APB_CLK_FREQ/(i2c->dev->scl_low_period.period+i2c->dev->scl_high_period.period);
|
2016-10-06 13:21:30 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* mode - 0 = Slave, 1 = Master
|
|
|
|
* slave_addr - I2C Address
|
|
|
|
* addr_10bit_en - enable slave 10bit address mode.
|
|
|
|
* */
|
|
|
|
|
|
|
|
i2c_t * i2cInit(uint8_t i2c_num, uint16_t slave_addr, bool addr_10bit_en)
|
|
|
|
{
|
2016-10-11 13:20:02 +02:00
|
|
|
if(i2c_num > 1){
|
2016-10-06 13:21:30 +02:00
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2016-10-11 13:20:02 +02:00
|
|
|
i2c_t * i2c = &_i2c_bus_array[i2c_num];
|
|
|
|
|
2016-11-18 14:07:25 +01:00
|
|
|
#if !CONFIG_DISABLE_HAL_LOCKS
|
2016-10-11 13:20:02 +02:00
|
|
|
if(i2c->lock == NULL){
|
|
|
|
i2c->lock = xSemaphoreCreateMutex();
|
|
|
|
if(i2c->lock == NULL) {
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
}
|
2016-11-18 14:07:25 +01:00
|
|
|
#endif
|
2016-10-06 13:21:30 +02:00
|
|
|
|
2016-10-11 13:20:02 +02:00
|
|
|
if(i2c_num == 0) {
|
2018-04-06 18:13:59 +02:00
|
|
|
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,DPORT_I2C_EXT0_RST); // I2C0 peripheral into Reset mode
|
2017-05-15 19:53:09 +02:00
|
|
|
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG,DPORT_I2C_EXT0_CLK_EN);
|
2018-04-06 18:13:59 +02:00
|
|
|
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,DPORT_I2C_EXT0_RST); // Release Reset Mode
|
2016-10-11 13:20:02 +02:00
|
|
|
} else {
|
2018-04-06 18:13:59 +02:00
|
|
|
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,DPORT_I2C_EXT1_RST); // I2C1 peripheral into Reset Mode
|
2017-05-15 19:53:09 +02:00
|
|
|
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG,DPORT_I2C_EXT1_CLK_EN);
|
2018-04-06 18:13:59 +02:00
|
|
|
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,DPORT_I2C_EXT1_RST); // Release Reset Mode
|
2016-10-06 13:21:30 +02:00
|
|
|
}
|
2017-10-21 14:26:46 +02:00
|
|
|
|
2016-10-14 02:24:20 +02:00
|
|
|
I2C_MUTEX_LOCK();
|
2016-10-08 16:32:11 +02:00
|
|
|
i2c->dev->ctr.val = 0;
|
2016-10-06 13:21:30 +02:00
|
|
|
i2c->dev->ctr.ms_mode = (slave_addr == 0);
|
|
|
|
i2c->dev->ctr.sda_force_out = 1 ;
|
|
|
|
i2c->dev->ctr.scl_force_out = 1 ;
|
2016-10-08 16:32:11 +02:00
|
|
|
i2c->dev->ctr.clk_en = 1;
|
2016-10-06 13:21:30 +02:00
|
|
|
|
2016-12-14 01:41:22 +01:00
|
|
|
//the max clock number of receiving a data
|
2017-10-21 14:26:46 +02:00
|
|
|
i2c->dev->timeout.tout = 1048575;//clocks max=1048575
|
2016-12-14 01:41:22 +01:00
|
|
|
//disable apb nonfifo access
|
2016-10-06 13:21:30 +02:00
|
|
|
i2c->dev->fifo_conf.nonfifo_en = 0;
|
|
|
|
|
2016-10-08 16:32:11 +02:00
|
|
|
i2c->dev->slave_addr.val = 0;
|
2016-10-06 13:21:30 +02:00
|
|
|
if (slave_addr) {
|
|
|
|
i2c->dev->slave_addr.addr = slave_addr;
|
|
|
|
i2c->dev->slave_addr.en_10bit = addr_10bit_en;
|
|
|
|
}
|
2016-10-14 02:24:20 +02:00
|
|
|
I2C_MUTEX_UNLOCK();
|
2016-10-06 13:21:30 +02:00
|
|
|
|
|
|
|
return i2c;
|
|
|
|
}
|
|
|
|
|
2016-12-14 01:41:22 +01:00
|
|
|
void i2cInitFix(i2c_t * i2c){
|
|
|
|
if(i2c == NULL){
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
I2C_MUTEX_LOCK();
|
|
|
|
i2cResetFiFo(i2c);
|
|
|
|
i2cResetCmd(i2c);
|
|
|
|
i2c->dev->int_clr.val = 0xFFFFFFFF;
|
|
|
|
i2cSetCmd(i2c, 0, I2C_CMD_RSTART, 0, false, false, false);
|
|
|
|
i2c->dev->fifo_data.data = 0;
|
|
|
|
i2cSetCmd(i2c, 1, I2C_CMD_WRITE, 1, false, false, false);
|
|
|
|
i2cSetCmd(i2c, 2, I2C_CMD_STOP, 0, false, false, false);
|
2017-09-29 15:17:13 +02:00
|
|
|
if (i2c->dev->status_reg.bus_busy) // If this condition is true, the while loop will timeout as done will not be set
|
|
|
|
{
|
2017-09-29 15:24:06 +02:00
|
|
|
log_e("Busy at initialization!");
|
2017-09-29 15:17:13 +02:00
|
|
|
}
|
2016-12-14 01:41:22 +01:00
|
|
|
i2c->dev->ctr.trans_start = 1;
|
2017-09-29 15:17:13 +02:00
|
|
|
uint16_t count = 50000;
|
|
|
|
while ((!i2c->dev->command[2].done) && (--count > 0));
|
2016-12-14 01:41:22 +01:00
|
|
|
I2C_MUTEX_UNLOCK();
|
|
|
|
}
|
2017-09-29 15:17:13 +02:00
|
|
|
|
|
|
|
void i2cReset(i2c_t* i2c){
|
|
|
|
if(i2c == NULL){
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
I2C_MUTEX_LOCK();
|
|
|
|
periph_module_t moduleId = (i2c == &_i2c_bus_array[0])?PERIPH_I2C0_MODULE:PERIPH_I2C1_MODULE;
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periph_module_disable( moduleId );
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delay( 20 ); // Seems long but delay was chosen to ensure system teardown and setup without core generation
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periph_module_enable( moduleId );
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I2C_MUTEX_UNLOCK();
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}
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