2023-01-14 00:11:02 +01:00
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// Copyright (C) 2023, Mark Qvist
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <https://www.gnu.org/licenses/>.
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2018-06-20 08:45:49 +02:00
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#ifndef ROM_H
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#define ROM_H
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#define CHECKSUMMED_SIZE 0x0B
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2022-01-22 21:43:52 +01:00
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#define PRODUCT_RNODE 0x03
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#define PRODUCT_HMBRW 0xF0
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#define PRODUCT_TBEAM 0xE0
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2023-05-03 15:57:02 +02:00
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#define PRODUCT_T32_10 0xB2
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2022-01-22 21:43:52 +01:00
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#define PRODUCT_T32_20 0xB0
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#define PRODUCT_T32_21 0xB1
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2022-06-16 19:12:28 +02:00
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#define PRODUCT_H32_V2 0xC0
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2024-04-11 07:38:06 +02:00
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#define PRODUCT_H32_V3 0xC1
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2024-05-13 23:25:24 +02:00
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#define PRODUCT_RAK4631 0x10
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2024-07-12 14:54:50 +02:00
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#define PRODUCT_FREENODE 0x20
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2024-05-13 23:25:24 +02:00
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#define MODEL_11 0x11
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#define MODEL_12 0x12
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2024-07-09 11:37:50 +02:00
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#define MODEL_13 0x13 // RAK4631 with WisBlock SX1280 module (LIBSYS002)
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2024-07-12 14:54:50 +02:00
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#define MODEL_21 0x21 // European band, 868MHz
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2024-02-10 17:13:52 +01:00
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#define MODEL_A1 0xA1
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2024-07-09 11:37:50 +02:00
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#define MODEL_A5 0xA5 // T3S3 SX1280 PA
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2024-02-10 17:13:52 +01:00
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#define MODEL_A6 0xA6
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2018-06-20 08:45:49 +02:00
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#define MODEL_A4 0xA4
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#define MODEL_A9 0xA9
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2022-06-16 19:12:28 +02:00
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#define MODEL_A3 0xA3
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#define MODEL_A8 0xA8
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#define MODEL_A2 0xA2
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#define MODEL_A7 0xA7
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2022-01-22 21:43:52 +01:00
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#define MODEL_B3 0xB3
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#define MODEL_B8 0xB8
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#define MODEL_B4 0xB4
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#define MODEL_B9 0xB9
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2023-05-03 16:39:22 +02:00
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#define MODEL_BA 0xBA
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#define MODEL_BB 0xBB
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2022-06-16 19:12:28 +02:00
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#define MODEL_C4 0xC4
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#define MODEL_C9 0xC9
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2024-04-11 07:38:06 +02:00
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#define MODEL_C5 0xC5
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#define MODEL_CA 0xCA
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2022-01-09 23:40:30 +01:00
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#define MODEL_E4 0xE4
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#define MODEL_E9 0xE9
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2024-02-13 17:26:25 +01:00
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#define MODEL_E3 0xE3
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#define MODEL_E8 0xE8
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2022-06-29 14:28:01 +02:00
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#define MODEL_FE 0xFE
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2022-01-09 23:40:30 +01:00
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#define MODEL_FF 0xFF
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2018-06-20 08:45:49 +02:00
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#define ADDR_PRODUCT 0x00
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#define ADDR_MODEL 0x01
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#define ADDR_HW_REV 0x02
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#define ADDR_SERIAL 0x03
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2024-02-10 17:13:52 +01:00
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#define ADDR_MADE 0x07
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2018-06-20 08:45:49 +02:00
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#define ADDR_CHKSUM 0x0B
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#define ADDR_SIGNATURE 0x1B
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#define ADDR_INFO_LOCK 0x9B
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#define ADDR_CONF_SF 0x9C
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#define ADDR_CONF_CR 0x9D
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#define ADDR_CONF_TXP 0x9E
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#define ADDR_CONF_BW 0x9F
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#define ADDR_CONF_FREQ 0xA3
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#define ADDR_CONF_OK 0xA7
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2022-10-30 14:52:22 +01:00
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#define ADDR_CONF_BT 0xB0
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2023-05-03 14:05:49 +02:00
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#define ADDR_CONF_DSET 0xB1
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#define ADDR_CONF_DINT 0xB2
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2023-09-19 18:32:29 +02:00
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#define ADDR_CONF_DADR 0xB3
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2018-06-20 08:45:49 +02:00
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#define INFO_LOCK_BYTE 0x73
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#define CONF_OK_BYTE 0x73
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2022-10-30 14:52:22 +01:00
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#define BT_ENABLE_BYTE 0x73
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2018-06-20 08:45:49 +02:00
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#define EEPROM_RESERVED 200
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2024-02-11 18:27:47 +01:00
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2024-01-19 11:08:55 +01:00
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#endif
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